1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: RISCV.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands,
18 const SmallBitVector &OptionalOperandsMask,
19 ArrayRef<unsigned> DefaultsOffset);
20 void convertToMapAndConstraints(unsigned Kind,
21 const OperandVector &Operands) override;
22 unsigned MatchInstructionImpl(const OperandVector &Operands,
23 MCInst &Inst,
24 SmallVectorImpl<NearMissInfo> *NearMisses,
25 bool matchingInlineAsm,
26 unsigned VariantID = 0);
27 ParseStatus MatchOperandParserImpl(
28 OperandVector &Operands,
29 StringRef Mnemonic,
30 bool ParseForAllFeatures = false);
31 ParseStatus tryCustomParseOperand(
32 OperandVector &Operands,
33 unsigned MCK);
34
35#endif // GET_ASSEMBLER_HEADER
36
37
38#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
39#undef GET_OPERAND_DIAGNOSTIC_TYPES
40
41 Match_GPRC,
42 Match_InvalidBareSImm11Lsb0,
43 Match_InvalidBareSImm12Lsb0,
44 Match_InvalidBareSImm13Lsb0,
45 Match_InvalidBareSImm21Lsb0,
46 Match_InvalidBareSImm32,
47 Match_InvalidBareSImm32Lsb0,
48 Match_InvalidBareSImm9Lsb0,
49 Match_InvalidBareSymbol,
50 Match_InvalidBareSymbolQC_E_LI,
51 Match_InvalidCLUIImm,
52 Match_InvalidCSRSystemRegister,
53 Match_InvalidCallSymbol,
54 Match_InvalidGPRPairCRV32,
55 Match_InvalidGPRPairNoX0RV32,
56 Match_InvalidImm5Zibi,
57 Match_InvalidImmFour,
58 Match_InvalidImmThree,
59 Match_InvalidImmXLenLI,
60 Match_InvalidImmXLenLI_Restricted,
61 Match_InvalidImmZero,
62 Match_InvalidLoadFPImm,
63 Match_InvalidPseudoJumpSymbol,
64 Match_InvalidQCAccessSymbol,
65 Match_InvalidRTZArg,
66 Match_InvalidRegClassGPR,
67 Match_InvalidRegClassGPRNoX0,
68 Match_InvalidRegClassGPRNoX0X2,
69 Match_InvalidRegClassGPRNoX2,
70 Match_InvalidRegClassGPRX0,
71 Match_InvalidRegClassGPRX1,
72 Match_InvalidRegClassGPRX1X5,
73 Match_InvalidRegClassGPRX31,
74 Match_InvalidRegClassGPRX5,
75 Match_InvalidRegClassSP,
76 Match_InvalidRegClassSR07,
77 Match_InvalidRegList,
78 Match_InvalidRegListS0,
79 Match_InvalidRnumArg,
80 Match_InvalidSImm10,
81 Match_InvalidSImm10Lsb0000NonZero,
82 Match_InvalidSImm10PLI_H,
83 Match_InvalidSImm10PLI_W,
84 Match_InvalidSImm10PLUI,
85 Match_InvalidSImm11,
86 Match_InvalidSImm12,
87 Match_InvalidSImm12LO,
88 Match_InvalidSImm12Lsb00000,
89 Match_InvalidSImm16,
90 Match_InvalidSImm16NonZero,
91 Match_InvalidSImm18,
92 Match_InvalidSImm18Lsb0,
93 Match_InvalidSImm19Lsb00,
94 Match_InvalidSImm20LI,
95 Match_InvalidSImm20Lsb000,
96 Match_InvalidSImm26,
97 Match_InvalidSImm5,
98 Match_InvalidSImm5NonZero,
99 Match_InvalidSImm5Plus1,
100 Match_InvalidSImm6,
101 Match_InvalidSImm6NonZero,
102 Match_InvalidSImm8PLI_B,
103 Match_InvalidSMTI8,
104 Match_InvalidSMTType,
105 Match_InvalidStackAdj,
106 Match_InvalidTLSDESCCallSymbol,
107 Match_InvalidTPRelAddSymbol,
108 Match_InvalidTileLambda,
109 Match_InvalidUImm1,
110 Match_InvalidUImm10,
111 Match_InvalidUImm10Lsb00NonZero,
112 Match_InvalidUImm11,
113 Match_InvalidUImm14Lsb00,
114 Match_InvalidUImm16,
115 Match_InvalidUImm16NonZero,
116 Match_InvalidUImm2,
117 Match_InvalidUImm20,
118 Match_InvalidUImm20AUIPC,
119 Match_InvalidUImm20LUI,
120 Match_InvalidUImm2Lsb0,
121 Match_InvalidUImm3,
122 Match_InvalidUImm32,
123 Match_InvalidUImm4,
124 Match_InvalidUImm48,
125 Match_InvalidUImm4Plus1,
126 Match_InvalidUImm5,
127 Match_InvalidUImm5GE6Plus1,
128 Match_InvalidUImm5GT3,
129 Match_InvalidUImm5Lsb0,
130 Match_InvalidUImm5NonZero,
131 Match_InvalidUImm5Plus1,
132 Match_InvalidUImm5Slist,
133 Match_InvalidUImm6,
134 Match_InvalidUImm64,
135 Match_InvalidUImm6Lsb0,
136 Match_InvalidUImm6Plus1,
137 Match_InvalidUImm7,
138 Match_InvalidUImm7EqXLen,
139 Match_InvalidUImm7Lsb00,
140 Match_InvalidUImm7Lsb000,
141 Match_InvalidUImm8,
142 Match_InvalidUImm8GE32,
143 Match_InvalidUImm8Lsb00,
144 Match_InvalidUImm8Lsb000,
145 Match_InvalidUImm9,
146 Match_InvalidUImm9Lsb000,
147 Match_InvalidUImmLog2XLen,
148 Match_InvalidUImmLog2XLenNonZero,
149 Match_InvalidVMaskCarryInRegister,
150 Match_InvalidVMaskRegister,
151 Match_InvalidVScaleRegister,
152 Match_InvalidVTypeI,
153 Match_InvalidYBNDSWImm,
154 END_OPERAND_DIAGNOSTIC_TYPES
155#endif // GET_OPERAND_DIAGNOSTIC_TYPES
156
157
158#ifdef GET_REGISTER_MATCHER
159#undef GET_REGISTER_MATCHER
160
161// Bits for subtarget features that participate in instruction matching.
162enum SubtargetFeatureBits : uint8_t {
163 Feature_HasStdExtZibiBit = 46,
164 Feature_HasStdExtZicbomBit = 47,
165 Feature_HasStdExtZicbopBit = 48,
166 Feature_HasStdExtZicbozBit = 49,
167 Feature_HasStdExtZicsrBit = 52,
168 Feature_HasStdExtZicondBit = 51,
169 Feature_HasStdExtZifenceiBit = 53,
170 Feature_HasStdExtZihintpauseBit = 55,
171 Feature_HasStdExtZihintntlBit = 54,
172 Feature_HasStdExtZimopBit = 57,
173 Feature_HasStdExtZicfissBit = 50,
174 Feature_HasStdExtZilsdBit = 56,
175 Feature_HasStdExtZmmulBit = 65,
176 Feature_HasStdExtMBit = 7,
177 Feature_HasStdExtZaamoBit = 14,
178 Feature_HasStdExtZalrscBit = 18,
179 Feature_HasStdExtABit = 2,
180 Feature_HasStdExtZtsoBit = 66,
181 Feature_HasStdExtZabhaBit = 15,
182 Feature_HasStdExtZacasBit = 16,
183 Feature_HasStdExtZalasrBit = 17,
184 Feature_HasStdExtZawrsBit = 19,
185 Feature_HasStdExtFBit = 4,
186 Feature_HasStdExtDBit = 3,
187 Feature_HasStdExtQBit = 9,
188 Feature_HasStdExtZfhminBit = 42,
189 Feature_HasStdExtZfhBit = 40,
190 Feature_HasStdExtZfbfminBit = 39,
191 Feature_HasHalfFPLoadStoreMoveBit = 1,
192 Feature_HasStdExtZfaBit = 38,
193 Feature_HasStdExtZfinxBit = 43,
194 Feature_HasStdExtFOrZfinxBit = 5,
195 Feature_HasStdExtZdinxBit = 37,
196 Feature_HasStdExtZhinxminBit = 45,
197 Feature_HasStdExtZhinxBit = 44,
198 Feature_HasStdExtZcaBit = 29,
199 Feature_HasStdExtZcbBit = 30,
200 Feature_HasStdExtZcfBit = 32,
201 Feature_HasStdExtZcdBit = 31,
202 Feature_HasStdExtZclsdBit = 33,
203 Feature_HasStdExtZcmpBit = 35,
204 Feature_HasStdExtZcmtBit = 36,
205 Feature_HasStdExtZcmopBit = 34,
206 Feature_HasStdExtZbaBit = 20,
207 Feature_HasStdExtZbbBit = 21,
208 Feature_NoStdExtZbbBit = 170,
209 Feature_HasStdExtZbsBit = 28,
210 Feature_HasStdExtZbkbBit = 24,
211 Feature_NoStdExtZbkbBit = 171,
212 Feature_HasStdExtZbkxBit = 27,
213 Feature_HasStdExtZbbOrZbkbBit = 22,
214 Feature_HasStdExtZbkcBit = 26,
215 Feature_HasStdExtZbcBit = 23,
216 Feature_HasStdExtZkndBit = 58,
217 Feature_HasStdExtZkneBit = 60,
218 Feature_HasStdExtZkndOrZkneBit = 59,
219 Feature_HasStdExtZknhBit = 61,
220 Feature_HasStdExtZksedBit = 63,
221 Feature_HasStdExtZkshBit = 64,
222 Feature_HasStdExtZkrBit = 62,
223 Feature_HasStdExtZvabdBit = 67,
224 Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit = 90,
225 Feature_HasStdExtZvfwdota16bfBit = 80,
226 Feature_HasStdExtZvfqwdota8fBit = 78,
227 Feature_HasStdExtZvfbfminBit = 73,
228 Feature_HasStdExtZvfbfwmaBit = 75,
229 Feature_HasStdExtZfhOrZvfhBit = 41,
230 Feature_HasStdExtZvfofp8minBit = 76,
231 Feature_HasStdExtZvfbfminOrZvfofp8minBit = 74,
232 Feature_HasStdExtZvkbBit = 81,
233 Feature_HasStdExtZvbbBit = 68,
234 Feature_HasStdExtZvbcBit = 69,
235 Feature_HasStdExtZvbcOrZvbc32eBit = 70,
236 Feature_HasStdExtZvkgBit = 82,
237 Feature_HasStdExtZvkgsBit = 83,
238 Feature_HasStdExtZvknedBit = 84,
239 Feature_HasStdExtZvknhaBit = 85,
240 Feature_HasStdExtZvknhbBit = 86,
241 Feature_HasStdExtZvksedBit = 87,
242 Feature_HasStdExtZvkshBit = 88,
243 Feature_HasStdExtZvdot4a8iBit = 71,
244 Feature_HasStdExtZvzipBit = 95,
245 Feature_HasStdExtZvvmmBit = 92,
246 Feature_HasStdExtZvvfmmBit = 91,
247 Feature_HasStdExtZvvmtlsBit = 93,
248 Feature_HasStdExtZvvmttlsBit = 94,
249 Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit = 89,
250 Feature_HasStdExtZvfwbdota16bfBit = 79,
251 Feature_HasStdExtZvfqwbdota8fBit = 77,
252 Feature_HasStdExtZvfbdota32fBit = 72,
253 Feature_HasVInstructionsBit = 96,
254 Feature_HasVInstructionsI64Bit = 99,
255 Feature_HasVInstructionsAnyFBit = 97,
256 Feature_HasVInstructionsF16MinimalBit = 98,
257 Feature_HasStdExtHBit = 6,
258 Feature_HasStdExtSmrnmiBit = 11,
259 Feature_HasStdExtSvinvalBit = 12,
260 Feature_HasStdExtSmctrOrSsctrBit = 10,
261 Feature_HasStdExtPBit = 8,
262 Feature_HasStdExtZbkbOrPBit = 25,
263 Feature_HasStdExtYBit = 13,
264 Feature_HasVendorXVentanaCondOpsBit = 145,
265 Feature_HasVendorXTHeadBaBit = 134,
266 Feature_HasVendorXTHeadBbBit = 135,
267 Feature_HasVendorXTHeadBsBit = 136,
268 Feature_HasVendorXTHeadCondMovBit = 138,
269 Feature_HasVendorXTHeadCmoBit = 137,
270 Feature_HasVendorXTHeadFMemIdxBit = 139,
271 Feature_HasVendorXTHeadMacBit = 140,
272 Feature_HasVendorXTHeadMemIdxBit = 141,
273 Feature_HasVendorXTHeadMemPairBit = 142,
274 Feature_HasVendorXTHeadSyncBit = 143,
275 Feature_HasVendorXTHeadVdotBit = 144,
276 Feature_HasVendorXSfvcpBit = 125,
277 Feature_HasVendorXSfmmbaseBit = 124,
278 Feature_HasVendorXSfmm32a8fBit = 121,
279 Feature_HasVendorXSfmm32a8iBit = 122,
280 Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit = 123,
281 Feature_HasVendorXSfvqmaccdodBit = 130,
282 Feature_HasVendorXSfvqmaccqoqBit = 131,
283 Feature_HasVendorXSfvfwmaccqqqBit = 129,
284 Feature_HasVendorXSfvfnrclipxfqfBit = 128,
285 Feature_HasVendorXSfvfexpAnyBit = 126,
286 Feature_HasVendorXSfvfexpaBit = 127,
287 Feature_HasVendorXSiFivecdiscarddloneBit = 132,
288 Feature_HasVendorXSiFivecflushdloneBit = 133,
289 Feature_HasVendorXSfceaseBit = 120,
290 Feature_HasVendorXCVelwBit = 110,
291 Feature_HasVendorXCVbitmanipBit = 109,
292 Feature_HasVendorXCVmacBit = 111,
293 Feature_HasVendorXCVmemBit = 112,
294 Feature_HasVendorXCValuBit = 107,
295 Feature_HasVendorXCVsimdBit = 113,
296 Feature_HasVendorXCVbiBit = 108,
297 Feature_HasVendorXMIPSCMovBit = 115,
298 Feature_HasVendorXMIPSLSPBit = 117,
299 Feature_HasVendorXMIPSCBOPBit = 114,
300 Feature_HasVendorXMIPSEXECTLBit = 116,
301 Feature_HasVendorXwchcBit = 166,
302 Feature_HasVendorXqccmpBit = 146,
303 Feature_HasVendorXqccmtBit = 147,
304 Feature_HasVendorXqciaBit = 148,
305 Feature_HasVendorXqciacBit = 149,
306 Feature_HasVendorXqcibiBit = 150,
307 Feature_HasVendorXqcibmBit = 151,
308 Feature_HasVendorXqcicliBit = 152,
309 Feature_HasVendorXqcicmBit = 153,
310 Feature_HasVendorXqcicsBit = 154,
311 Feature_HasVendorXqcicsrBit = 155,
312 Feature_HasVendorXqciintBit = 156,
313 Feature_HasVendorXqciioBit = 157,
314 Feature_HasVendorXqcilbBit = 158,
315 Feature_HasVendorXqciliBit = 159,
316 Feature_HasVendorXqciliaBit = 160,
317 Feature_HasVendorXqciloBit = 161,
318 Feature_HasVendorXqcilsmBit = 162,
319 Feature_HasVendorXqcisimBit = 163,
320 Feature_HasVendorXqcislsBit = 164,
321 Feature_HasVendorXqcisyncBit = 165,
322 Feature_HasVendorXAndesPerfBit = 101,
323 Feature_HasVendorXAndesBFHCvtBit = 100,
324 Feature_HasVendorXAndesVBFHCvtBit = 102,
325 Feature_HasVendorXAndesVSIntHBit = 105,
326 Feature_HasVendorXAndesVSIntLoadBit = 106,
327 Feature_HasVendorXAndesVPackFPHBit = 104,
328 Feature_HasVendorXAndesVDotBit = 103,
329 Feature_HasVendorXSMTVDotBit = 118,
330 Feature_HasVendorXSMTVDotIIBit = 119,
331 Feature_HasXAIFETBit = 167,
332 Feature_HasCheriotBit = 0,
333 Feature_IsRV64Bit = 169,
334 Feature_IsRV32Bit = 168,
335};
336
337static MCRegister MatchRegisterName(StringRef Name) {
338 switch (Name.size()) {
339 default: break;
340 case 1: // 1 string to match.
341 if (Name[0] != '0')
342 break;
343 return RISCV::DUMMY_REG_PAIR_WITH_X0; // "0"
344 case 2: // 212 strings to match.
345 switch (Name[0]) {
346 default: break;
347 case 'f': // 50 strings to match.
348 switch (Name[1]) {
349 default: break;
350 case '0': // 5 strings to match.
351 return RISCV::F0_D; // "f0"
352 case '1': // 5 strings to match.
353 return RISCV::F1_D; // "f1"
354 case '2': // 5 strings to match.
355 return RISCV::F2_D; // "f2"
356 case '3': // 5 strings to match.
357 return RISCV::F3_D; // "f3"
358 case '4': // 5 strings to match.
359 return RISCV::F4_D; // "f4"
360 case '5': // 5 strings to match.
361 return RISCV::F5_D; // "f5"
362 case '6': // 5 strings to match.
363 return RISCV::F6_D; // "f6"
364 case '7': // 5 strings to match.
365 return RISCV::F7_D; // "f7"
366 case '8': // 5 strings to match.
367 return RISCV::F8_D; // "f8"
368 case '9': // 5 strings to match.
369 return RISCV::F9_D; // "f9"
370 }
371 break;
372 case 'm': // 8 strings to match.
373 switch (Name[1]) {
374 default: break;
375 case '0': // 1 string to match.
376 return RISCV::M0; // "m0"
377 case '1': // 1 string to match.
378 return RISCV::M1; // "m1"
379 case '2': // 1 string to match.
380 return RISCV::M2; // "m2"
381 case '3': // 1 string to match.
382 return RISCV::M3; // "m3"
383 case '4': // 1 string to match.
384 return RISCV::M4; // "m4"
385 case '5': // 1 string to match.
386 return RISCV::M5; // "m5"
387 case '6': // 1 string to match.
388 return RISCV::M6; // "m6"
389 case '7': // 1 string to match.
390 return RISCV::M7; // "m7"
391 }
392 break;
393 case 'v': // 109 strings to match.
394 switch (Name[1]) {
395 default: break;
396 case '0': // 15 strings to match.
397 return RISCV::V0; // "v0"
398 case '1': // 8 strings to match.
399 return RISCV::V1; // "v1"
400 case '2': // 12 strings to match.
401 return RISCV::V2; // "v2"
402 case '3': // 8 strings to match.
403 return RISCV::V3; // "v3"
404 case '4': // 14 strings to match.
405 return RISCV::V4; // "v4"
406 case '5': // 8 strings to match.
407 return RISCV::V5; // "v5"
408 case '6': // 12 strings to match.
409 return RISCV::V6; // "v6"
410 case '7': // 8 strings to match.
411 return RISCV::V7; // "v7"
412 case '8': // 15 strings to match.
413 return RISCV::V8; // "v8"
414 case '9': // 8 strings to match.
415 return RISCV::V9; // "v9"
416 case 'l': // 1 string to match.
417 return RISCV::VL; // "vl"
418 }
419 break;
420 case 'x': // 45 strings to match.
421 switch (Name[1]) {
422 default: break;
423 case '0': // 5 strings to match.
424 return RISCV::X0; // "x0"
425 case '1': // 4 strings to match.
426 return RISCV::X1; // "x1"
427 case '2': // 5 strings to match.
428 return RISCV::X2; // "x2"
429 case '3': // 4 strings to match.
430 return RISCV::X3; // "x3"
431 case '4': // 5 strings to match.
432 return RISCV::X4; // "x4"
433 case '5': // 4 strings to match.
434 return RISCV::X5; // "x5"
435 case '6': // 5 strings to match.
436 return RISCV::X6; // "x6"
437 case '7': // 4 strings to match.
438 return RISCV::X7; // "x7"
439 case '8': // 5 strings to match.
440 return RISCV::X8; // "x8"
441 case '9': // 4 strings to match.
442 return RISCV::X9; // "x9"
443 }
444 break;
445 }
446 break;
447 case 3: // 418 strings to match.
448 switch (Name[0]) {
449 default: break;
450 case 'f': // 111 strings to match.
451 switch (Name[1]) {
452 default: break;
453 case '1': // 50 strings to match.
454 switch (Name[2]) {
455 default: break;
456 case '0': // 5 strings to match.
457 return RISCV::F10_D; // "f10"
458 case '1': // 5 strings to match.
459 return RISCV::F11_D; // "f11"
460 case '2': // 5 strings to match.
461 return RISCV::F12_D; // "f12"
462 case '3': // 5 strings to match.
463 return RISCV::F13_D; // "f13"
464 case '4': // 5 strings to match.
465 return RISCV::F14_D; // "f14"
466 case '5': // 5 strings to match.
467 return RISCV::F15_D; // "f15"
468 case '6': // 5 strings to match.
469 return RISCV::F16_D; // "f16"
470 case '7': // 5 strings to match.
471 return RISCV::F17_D; // "f17"
472 case '8': // 5 strings to match.
473 return RISCV::F18_D; // "f18"
474 case '9': // 5 strings to match.
475 return RISCV::F19_D; // "f19"
476 }
477 break;
478 case '2': // 50 strings to match.
479 switch (Name[2]) {
480 default: break;
481 case '0': // 5 strings to match.
482 return RISCV::F20_D; // "f20"
483 case '1': // 5 strings to match.
484 return RISCV::F21_D; // "f21"
485 case '2': // 5 strings to match.
486 return RISCV::F22_D; // "f22"
487 case '3': // 5 strings to match.
488 return RISCV::F23_D; // "f23"
489 case '4': // 5 strings to match.
490 return RISCV::F24_D; // "f24"
491 case '5': // 5 strings to match.
492 return RISCV::F25_D; // "f25"
493 case '6': // 5 strings to match.
494 return RISCV::F26_D; // "f26"
495 case '7': // 5 strings to match.
496 return RISCV::F27_D; // "f27"
497 case '8': // 5 strings to match.
498 return RISCV::F28_D; // "f28"
499 case '9': // 5 strings to match.
500 return RISCV::F29_D; // "f29"
501 }
502 break;
503 case '3': // 10 strings to match.
504 switch (Name[2]) {
505 default: break;
506 case '0': // 5 strings to match.
507 return RISCV::F30_D; // "f30"
508 case '1': // 5 strings to match.
509 return RISCV::F31_D; // "f31"
510 }
511 break;
512 case 'r': // 1 string to match.
513 if (Name[2] != 'm')
514 break;
515 return RISCV::FRM; // "frm"
516 }
517 break;
518 case 'm': // 10 strings to match.
519 if (Name[1] != 't')
520 break;
521 switch (Name[2]) {
522 default: break;
523 case '0': // 1 string to match.
524 return RISCV::T0; // "mt0"
525 case '1': // 1 string to match.
526 return RISCV::T1; // "mt1"
527 case '2': // 1 string to match.
528 return RISCV::T2; // "mt2"
529 case '3': // 1 string to match.
530 return RISCV::T3; // "mt3"
531 case '4': // 1 string to match.
532 return RISCV::T4; // "mt4"
533 case '5': // 1 string to match.
534 return RISCV::T5; // "mt5"
535 case '6': // 1 string to match.
536 return RISCV::T6; // "mt6"
537 case '7': // 1 string to match.
538 return RISCV::T7; // "mt7"
539 case '8': // 1 string to match.
540 return RISCV::T8; // "mt8"
541 case '9': // 1 string to match.
542 return RISCV::T9; // "mt9"
543 }
544 break;
545 case 's': // 1 string to match.
546 if (memcmp(Name.data()+1, "sp", 2) != 0)
547 break;
548 return RISCV::SSP; // "ssp"
549 case 'v': // 197 strings to match.
550 switch (Name[1]) {
551 default: break;
552 case '1': // 105 strings to match.
553 switch (Name[2]) {
554 default: break;
555 case '0': // 12 strings to match.
556 return RISCV::V10; // "v10"
557 case '1': // 8 strings to match.
558 return RISCV::V11; // "v11"
559 case '2': // 14 strings to match.
560 return RISCV::V12; // "v12"
561 case '3': // 8 strings to match.
562 return RISCV::V13; // "v13"
563 case '4': // 12 strings to match.
564 return RISCV::V14; // "v14"
565 case '5': // 8 strings to match.
566 return RISCV::V15; // "v15"
567 case '6': // 15 strings to match.
568 return RISCV::V16; // "v16"
569 case '7': // 8 strings to match.
570 return RISCV::V17; // "v17"
571 case '8': // 12 strings to match.
572 return RISCV::V18; // "v18"
573 case '9': // 8 strings to match.
574 return RISCV::V19; // "v19"
575 }
576 break;
577 case '2': // 88 strings to match.
578 switch (Name[2]) {
579 default: break;
580 case '0': // 14 strings to match.
581 return RISCV::V20; // "v20"
582 case '1': // 8 strings to match.
583 return RISCV::V21; // "v21"
584 case '2': // 12 strings to match.
585 return RISCV::V22; // "v22"
586 case '3': // 8 strings to match.
587 return RISCV::V23; // "v23"
588 case '4': // 15 strings to match.
589 return RISCV::V24; // "v24"
590 case '5': // 7 strings to match.
591 return RISCV::V25; // "v25"
592 case '6': // 9 strings to match.
593 return RISCV::V26; // "v26"
594 case '7': // 5 strings to match.
595 return RISCV::V27; // "v27"
596 case '8': // 7 strings to match.
597 return RISCV::V28; // "v28"
598 case '9': // 3 strings to match.
599 return RISCV::V29; // "v29"
600 }
601 break;
602 case '3': // 4 strings to match.
603 switch (Name[2]) {
604 default: break;
605 case '0': // 3 strings to match.
606 return RISCV::V30; // "v30"
607 case '1': // 1 string to match.
608 return RISCV::V31; // "v31"
609 }
610 break;
611 }
612 break;
613 case 'x': // 99 strings to match.
614 switch (Name[1]) {
615 default: break;
616 case '1': // 45 strings to match.
617 switch (Name[2]) {
618 default: break;
619 case '0': // 5 strings to match.
620 return RISCV::X10; // "x10"
621 case '1': // 4 strings to match.
622 return RISCV::X11; // "x11"
623 case '2': // 5 strings to match.
624 return RISCV::X12; // "x12"
625 case '3': // 4 strings to match.
626 return RISCV::X13; // "x13"
627 case '4': // 5 strings to match.
628 return RISCV::X14; // "x14"
629 case '5': // 4 strings to match.
630 return RISCV::X15; // "x15"
631 case '6': // 5 strings to match.
632 return RISCV::X16; // "x16"
633 case '7': // 4 strings to match.
634 return RISCV::X17; // "x17"
635 case '8': // 5 strings to match.
636 return RISCV::X18; // "x18"
637 case '9': // 4 strings to match.
638 return RISCV::X19; // "x19"
639 }
640 break;
641 case '2': // 45 strings to match.
642 switch (Name[2]) {
643 default: break;
644 case '0': // 5 strings to match.
645 return RISCV::X20; // "x20"
646 case '1': // 4 strings to match.
647 return RISCV::X21; // "x21"
648 case '2': // 5 strings to match.
649 return RISCV::X22; // "x22"
650 case '3': // 4 strings to match.
651 return RISCV::X23; // "x23"
652 case '4': // 5 strings to match.
653 return RISCV::X24; // "x24"
654 case '5': // 4 strings to match.
655 return RISCV::X25; // "x25"
656 case '6': // 5 strings to match.
657 return RISCV::X26; // "x26"
658 case '7': // 4 strings to match.
659 return RISCV::X27; // "x27"
660 case '8': // 5 strings to match.
661 return RISCV::X28; // "x28"
662 case '9': // 4 strings to match.
663 return RISCV::X29; // "x29"
664 }
665 break;
666 case '3': // 9 strings to match.
667 switch (Name[2]) {
668 default: break;
669 case '0': // 5 strings to match.
670 return RISCV::X30; // "x30"
671 case '1': // 4 strings to match.
672 return RISCV::X31; // "x31"
673 }
674 break;
675 }
676 break;
677 }
678 break;
679 case 4: // 8 strings to match.
680 switch (Name[0]) {
681 default: break;
682 case 'f': // 1 string to match.
683 if (memcmp(Name.data()+1, "csr", 3) != 0)
684 break;
685 return RISCV::FCSR; // "fcsr"
686 case 'm': // 6 strings to match.
687 if (memcmp(Name.data()+1, "t1", 2) != 0)
688 break;
689 switch (Name[3]) {
690 default: break;
691 case '0': // 1 string to match.
692 return RISCV::T10; // "mt10"
693 case '1': // 1 string to match.
694 return RISCV::T11; // "mt11"
695 case '2': // 1 string to match.
696 return RISCV::T12; // "mt12"
697 case '3': // 1 string to match.
698 return RISCV::T13; // "mt13"
699 case '4': // 1 string to match.
700 return RISCV::T14; // "mt14"
701 case '5': // 1 string to match.
702 return RISCV::T15; // "mt15"
703 }
704 break;
705 case 'v': // 1 string to match.
706 if (memcmp(Name.data()+1, "xrm", 3) != 0)
707 break;
708 return RISCV::VXRM; // "vxrm"
709 }
710 break;
711 case 5: // 3 strings to match.
712 if (Name[0] != 'v')
713 break;
714 switch (Name[1]) {
715 default: break;
716 case 'l': // 1 string to match.
717 if (memcmp(Name.data()+2, "enb", 3) != 0)
718 break;
719 return RISCV::VLENB; // "vlenb"
720 case 't': // 1 string to match.
721 if (memcmp(Name.data()+2, "ype", 3) != 0)
722 break;
723 return RISCV::VTYPE; // "vtype"
724 case 'x': // 1 string to match.
725 if (memcmp(Name.data()+2, "sat", 3) != 0)
726 break;
727 return RISCV::VXSAT; // "vxsat"
728 }
729 break;
730 case 6: // 1 string to match.
731 if (memcmp(Name.data()+0, "fflags", 6) != 0)
732 break;
733 return RISCV::FFLAGS; // "fflags"
734 case 13: // 1 string to match.
735 if (memcmp(Name.data()+0, "sf.vcix_state", 13) != 0)
736 break;
737 return RISCV::SF_VCIX_STATE; // "sf.vcix_state"
738 }
739 return RISCV::NoRegister;
740}
741
742static MCRegister MatchRegisterAltName(StringRef Name) {
743 switch (Name.size()) {
744 default: break;
745 case 2: // 143 strings to match.
746 switch (Name[0]) {
747 default: break;
748 case 'a': // 36 strings to match.
749 switch (Name[1]) {
750 default: break;
751 case '0': // 5 strings to match.
752 return RISCV::X10; // "a0"
753 case '1': // 4 strings to match.
754 return RISCV::X11; // "a1"
755 case '2': // 5 strings to match.
756 return RISCV::X12; // "a2"
757 case '3': // 4 strings to match.
758 return RISCV::X13; // "a3"
759 case '4': // 5 strings to match.
760 return RISCV::X14; // "a4"
761 case '5': // 4 strings to match.
762 return RISCV::X15; // "a5"
763 case '6': // 5 strings to match.
764 return RISCV::X16; // "a6"
765 case '7': // 4 strings to match.
766 return RISCV::X17; // "a7"
767 }
768 break;
769 case 'f': // 5 strings to match.
770 if (Name[1] != 'p')
771 break;
772 return RISCV::X8; // "fp"
773 case 'g': // 4 strings to match.
774 if (Name[1] != 'p')
775 break;
776 return RISCV::X3; // "gp"
777 case 'm': // 8 strings to match.
778 switch (Name[1]) {
779 default: break;
780 case '0': // 1 string to match.
781 return RISCV::M0; // "m0"
782 case '1': // 1 string to match.
783 return RISCV::M1; // "m1"
784 case '2': // 1 string to match.
785 return RISCV::M2; // "m2"
786 case '3': // 1 string to match.
787 return RISCV::M3; // "m3"
788 case '4': // 1 string to match.
789 return RISCV::M4; // "m4"
790 case '5': // 1 string to match.
791 return RISCV::M5; // "m5"
792 case '6': // 1 string to match.
793 return RISCV::M6; // "m6"
794 case '7': // 1 string to match.
795 return RISCV::M7; // "m7"
796 }
797 break;
798 case 'r': // 4 strings to match.
799 if (Name[1] != 'a')
800 break;
801 return RISCV::X1; // "ra"
802 case 's': // 50 strings to match.
803 switch (Name[1]) {
804 default: break;
805 case '0': // 5 strings to match.
806 return RISCV::X8; // "s0"
807 case '1': // 4 strings to match.
808 return RISCV::X9; // "s1"
809 case '2': // 5 strings to match.
810 return RISCV::X18; // "s2"
811 case '3': // 4 strings to match.
812 return RISCV::X19; // "s3"
813 case '4': // 5 strings to match.
814 return RISCV::X20; // "s4"
815 case '5': // 4 strings to match.
816 return RISCV::X21; // "s5"
817 case '6': // 5 strings to match.
818 return RISCV::X22; // "s6"
819 case '7': // 4 strings to match.
820 return RISCV::X23; // "s7"
821 case '8': // 5 strings to match.
822 return RISCV::X24; // "s8"
823 case '9': // 4 strings to match.
824 return RISCV::X25; // "s9"
825 case 'p': // 5 strings to match.
826 return RISCV::X2; // "sp"
827 }
828 break;
829 case 't': // 36 strings to match.
830 switch (Name[1]) {
831 default: break;
832 case '0': // 4 strings to match.
833 return RISCV::X5; // "t0"
834 case '1': // 5 strings to match.
835 return RISCV::X6; // "t1"
836 case '2': // 4 strings to match.
837 return RISCV::X7; // "t2"
838 case '3': // 5 strings to match.
839 return RISCV::X28; // "t3"
840 case '4': // 4 strings to match.
841 return RISCV::X29; // "t4"
842 case '5': // 5 strings to match.
843 return RISCV::X30; // "t5"
844 case '6': // 4 strings to match.
845 return RISCV::X31; // "t6"
846 case 'p': // 5 strings to match.
847 return RISCV::X4; // "tp"
848 }
849 break;
850 }
851 break;
852 case 3: // 149 strings to match.
853 switch (Name[0]) {
854 default: break;
855 case 'f': // 140 strings to match.
856 switch (Name[1]) {
857 default: break;
858 case 'a': // 40 strings to match.
859 switch (Name[2]) {
860 default: break;
861 case '0': // 5 strings to match.
862 return RISCV::F10_D; // "fa0"
863 case '1': // 5 strings to match.
864 return RISCV::F11_D; // "fa1"
865 case '2': // 5 strings to match.
866 return RISCV::F12_D; // "fa2"
867 case '3': // 5 strings to match.
868 return RISCV::F13_D; // "fa3"
869 case '4': // 5 strings to match.
870 return RISCV::F14_D; // "fa4"
871 case '5': // 5 strings to match.
872 return RISCV::F15_D; // "fa5"
873 case '6': // 5 strings to match.
874 return RISCV::F16_D; // "fa6"
875 case '7': // 5 strings to match.
876 return RISCV::F17_D; // "fa7"
877 }
878 break;
879 case 's': // 50 strings to match.
880 switch (Name[2]) {
881 default: break;
882 case '0': // 5 strings to match.
883 return RISCV::F8_D; // "fs0"
884 case '1': // 5 strings to match.
885 return RISCV::F9_D; // "fs1"
886 case '2': // 5 strings to match.
887 return RISCV::F18_D; // "fs2"
888 case '3': // 5 strings to match.
889 return RISCV::F19_D; // "fs3"
890 case '4': // 5 strings to match.
891 return RISCV::F20_D; // "fs4"
892 case '5': // 5 strings to match.
893 return RISCV::F21_D; // "fs5"
894 case '6': // 5 strings to match.
895 return RISCV::F22_D; // "fs6"
896 case '7': // 5 strings to match.
897 return RISCV::F23_D; // "fs7"
898 case '8': // 5 strings to match.
899 return RISCV::F24_D; // "fs8"
900 case '9': // 5 strings to match.
901 return RISCV::F25_D; // "fs9"
902 }
903 break;
904 case 't': // 50 strings to match.
905 switch (Name[2]) {
906 default: break;
907 case '0': // 5 strings to match.
908 return RISCV::F0_D; // "ft0"
909 case '1': // 5 strings to match.
910 return RISCV::F1_D; // "ft1"
911 case '2': // 5 strings to match.
912 return RISCV::F2_D; // "ft2"
913 case '3': // 5 strings to match.
914 return RISCV::F3_D; // "ft3"
915 case '4': // 5 strings to match.
916 return RISCV::F4_D; // "ft4"
917 case '5': // 5 strings to match.
918 return RISCV::F5_D; // "ft5"
919 case '6': // 5 strings to match.
920 return RISCV::F6_D; // "ft6"
921 case '7': // 5 strings to match.
922 return RISCV::F7_D; // "ft7"
923 case '8': // 5 strings to match.
924 return RISCV::F28_D; // "ft8"
925 case '9': // 5 strings to match.
926 return RISCV::F29_D; // "ft9"
927 }
928 break;
929 }
930 break;
931 case 's': // 9 strings to match.
932 if (Name[1] != '1')
933 break;
934 switch (Name[2]) {
935 default: break;
936 case '0': // 5 strings to match.
937 return RISCV::X26; // "s10"
938 case '1': // 4 strings to match.
939 return RISCV::X27; // "s11"
940 }
941 break;
942 }
943 break;
944 case 4: // 26 strings to match.
945 switch (Name[0]) {
946 default: break;
947 case 'f': // 20 strings to match.
948 switch (Name[1]) {
949 default: break;
950 case 's': // 10 strings to match.
951 if (Name[2] != '1')
952 break;
953 switch (Name[3]) {
954 default: break;
955 case '0': // 5 strings to match.
956 return RISCV::F26_D; // "fs10"
957 case '1': // 5 strings to match.
958 return RISCV::F27_D; // "fs11"
959 }
960 break;
961 case 't': // 10 strings to match.
962 if (Name[2] != '1')
963 break;
964 switch (Name[3]) {
965 default: break;
966 case '0': // 5 strings to match.
967 return RISCV::F30_D; // "ft10"
968 case '1': // 5 strings to match.
969 return RISCV::F31_D; // "ft11"
970 }
971 break;
972 }
973 break;
974 case 'n': // 1 string to match.
975 if (memcmp(Name.data()+1, "ull", 3) != 0)
976 break;
977 return RISCV::X0_Y; // "null"
978 case 'z': // 5 strings to match.
979 if (memcmp(Name.data()+1, "ero", 3) != 0)
980 break;
981 return RISCV::X0; // "zero"
982 }
983 break;
984 }
985 return RISCV::NoRegister;
986}
987
988#endif // GET_REGISTER_MATCHER
989
990
991#ifdef GET_SUBTARGET_FEATURE_NAME
992#undef GET_SUBTARGET_FEATURE_NAME
993
994// User-level names for subtarget features that participate in
995// instruction matching.
996static const char *getSubtargetFeatureName(uint64_t Val) {
997 switch(Val) {
998 case Feature_HasStdExtZibiBit: return "'Zibi' (Branch with Immediate)";
999 case Feature_HasStdExtZicbomBit: return "'Zicbom' (Cache-Block Management Instructions)";
1000 case Feature_HasStdExtZicbopBit: return "'Zicbop' (Cache-Block Prefetch Instructions)";
1001 case Feature_HasStdExtZicbozBit: return "'Zicboz' (Cache-Block Zero Instructions)";
1002 case Feature_HasStdExtZicsrBit: return "'Zicsr' (CSRs)";
1003 case Feature_HasStdExtZicondBit: return "(Integer Conditional Operations)";
1004 case Feature_HasStdExtZifenceiBit: return "'Zifencei' (fence.i)";
1005 case Feature_HasStdExtZihintpauseBit: return "'Zihintpause' (Pause Hint)";
1006 case Feature_HasStdExtZihintntlBit: return "'Zihintntl' (Non-Temporal Locality Hints)";
1007 case Feature_HasStdExtZimopBit: return "'Zimop' (May-Be-Operations)";
1008 case Feature_HasStdExtZicfissBit: return "'Zicfiss' (Shadow stack)";
1009 case Feature_HasStdExtZilsdBit: return "'Zilsd' (Load/Store pair instructions)";
1010 case Feature_HasStdExtZmmulBit: return "'Zmmul' (Integer Multiplication)";
1011 case Feature_HasStdExtMBit: return "'M' (Integer Multiplication and Division)";
1012 case Feature_HasStdExtZaamoBit: return "'Zaamo' (Atomic Memory Operations)";
1013 case Feature_HasStdExtZalrscBit: return "'Zalrsc' (Load-Reserved/Store-Conditional)";
1014 case Feature_HasStdExtABit: return "'A' (Atomic Instructions)";
1015 case Feature_HasStdExtZtsoBit: return "'Ztso' (Memory Model - Total Store Order)";
1016 case Feature_HasStdExtZabhaBit: return "'Zabha' (Byte and Halfword Atomic Memory Operations)";
1017 case Feature_HasStdExtZacasBit: return "'Zacas' (Atomic Compare-And-Swap Instructions)";
1018 case Feature_HasStdExtZalasrBit: return "'Zalasr' (Load-Acquire and Store-Release Instructions)";
1019 case Feature_HasStdExtZawrsBit: return "'Zawrs' (Wait on Reservation Set)";
1020 case Feature_HasStdExtFBit: return "'F' (Single-Precision Floating-Point)";
1021 case Feature_HasStdExtDBit: return "'D' (Double-Precision Floating-Point)";
1022 case Feature_HasStdExtQBit: return "'Q' (Quad-Precision Floating-Point)";
1023 case Feature_HasStdExtZfhminBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)";
1024 case Feature_HasStdExtZfhBit: return "'Zfh' (Half-Precision Floating-Point)";
1025 case Feature_HasStdExtZfbfminBit: return "'Zfbfmin' (Scalar BF16 Converts)";
1026 case Feature_HasHalfFPLoadStoreMoveBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts)";
1027 case Feature_HasStdExtZfaBit: return "'Zfa' (Additional Floating-Point)";
1028 case Feature_HasStdExtZfinxBit: return "'Zfinx' (Float in Integer)";
1029 case Feature_HasStdExtFOrZfinxBit: return "'F' (Single-Precision Floating-Point) or 'Zfinx' (Float in Integer)";
1030 case Feature_HasStdExtZdinxBit: return "'Zdinx' (Double in Integer)";
1031 case Feature_HasStdExtZhinxminBit: return "'Zhinx' (Half Float in Integer) or 'Zhinxmin' (Half Float in Integer Minimal)";
1032 case Feature_HasStdExtZhinxBit: return "'Zhinx' (Half Float in Integer)";
1033 case Feature_HasStdExtZcaBit: return "'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores)";
1034 case Feature_HasStdExtZcbBit: return "'Zcb' (Compressed basic bit manipulation instructions)";
1035 case Feature_HasStdExtZcfBit: return "'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions)";
1036 case Feature_HasStdExtZcdBit: return "'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions)";
1037 case Feature_HasStdExtZclsdBit: return "'Zclsd' (Compressed Load/Store pair instructions)";
1038 case Feature_HasStdExtZcmpBit: return "'Zcmp' (sequenced instructions for code-size reduction)";
1039 case Feature_HasStdExtZcmtBit: return "'Zcmt' (table jump instructions for code-size reduction)";
1040 case Feature_HasStdExtZcmopBit: return "'Zcmop' (Compressed May-Be-Operations)";
1041 case Feature_HasStdExtZbaBit: return "'Zba' (Address Generation Instructions)";
1042 case Feature_HasStdExtZbbBit: return "'Zbb' (Basic Bit-Manipulation)";
1043 case Feature_NoStdExtZbbBit: return "";
1044 case Feature_HasStdExtZbsBit: return "'Zbs' (Single-Bit Instructions)";
1045 case Feature_HasStdExtZbkbBit: return "'Zbkb' (Bitmanip instructions for Cryptography)";
1046 case Feature_NoStdExtZbkbBit: return "";
1047 case Feature_HasStdExtZbkxBit: return "'Zbkx' (Crossbar permutation instructions)";
1048 case Feature_HasStdExtZbbOrZbkbBit: return "'Zbb' (Basic Bit-Manipulation) or 'Zbkb' (Bitmanip instructions for Cryptography)";
1049 case Feature_HasStdExtZbkcBit: return "'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography)";
1050 case Feature_HasStdExtZbcBit: return "'Zbc' (Carry-Less Multiplication)";
1051 case Feature_HasStdExtZkndBit: return "'Zknd' (NIST Suite: AES Decryption)";
1052 case Feature_HasStdExtZkneBit: return "'Zkne' (NIST Suite: AES Encryption)";
1053 case Feature_HasStdExtZkndOrZkneBit: return "'Zknd' (NIST Suite: AES Decryption) or 'Zkne' (NIST Suite: AES Encryption)";
1054 case Feature_HasStdExtZknhBit: return "'Zknh' (NIST Suite: Hash Function Instructions)";
1055 case Feature_HasStdExtZksedBit: return "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)";
1056 case Feature_HasStdExtZkshBit: return "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)";
1057 case Feature_HasStdExtZkrBit: return "'Zkr' (Entropy Source Extension)";
1058 case Feature_HasStdExtZvabdBit: return "'Zvabd' (Vector Absolute Difference)";
1059 case Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit: return "'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Product)";
1060 case Feature_HasStdExtZvfwdota16bfBit: return "'Zvfwdota16bf' (BF16 Dot-Product)";
1061 case Feature_HasStdExtZvfqwdota8fBit: return "'Zvfqwdota8f' (OCP FP8 Dot-Product)";
1062 case Feature_HasStdExtZvfbfminBit: return "'Zvfbfmin' (Vector BF16 Converts)";
1063 case Feature_HasStdExtZvfbfwmaBit: return "'Zvfbfwma' (Vector BF16 widening mul-add)";
1064 case Feature_HasStdExtZfhOrZvfhBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zvfh' (Vector Half-Precision Floating-Point)";
1065 case Feature_HasStdExtZvfofp8minBit: return "'Zvfofp8min' (Vector OFP8 Converts)";
1066 case Feature_HasStdExtZvfbfminOrZvfofp8minBit: return "'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts)";
1067 case Feature_HasStdExtZvkbBit: return "'Zvkb' (Vector Bit-manipulation used in Cryptography)";
1068 case Feature_HasStdExtZvbbBit: return "'Zvbb' (Vector basic bit-manipulation instructions)";
1069 case Feature_HasStdExtZvbcBit: return "'Zvbc' (Vector Carryless Multiplication)";
1070 case Feature_HasStdExtZvbcOrZvbc32eBit: return "'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)";
1071 case Feature_HasStdExtZvkgBit: return "'Zvkg' (Vector GCM instructions for Cryptography)";
1072 case Feature_HasStdExtZvkgsBit: return "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)";
1073 case Feature_HasStdExtZvknedBit: return "'Zvkned' (Vector AES Encryption & Decryption (Single Round))";
1074 case Feature_HasStdExtZvknhaBit: return "'Zvknha' (Vector SHA-2 (SHA-256 only))";
1075 case Feature_HasStdExtZvknhbBit: return "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))";
1076 case Feature_HasStdExtZvksedBit: return "'Zvksed' (SM4 Block Cipher Instructions)";
1077 case Feature_HasStdExtZvkshBit: return "'Zvksh' (SM3 Hash Function Instructions)";
1078 case Feature_HasStdExtZvdot4a8iBit: return "'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers)";
1079 case Feature_HasStdExtZvzipBit: return "'Zvzip' (Vector Reordering Structured Data)";
1080 case Feature_HasStdExtZvvmmBit: return "'Zvvmm' (Integer Matrix Multiply-Accumulate)";
1081 case Feature_HasStdExtZvvfmmBit: return "'Zvvfmm' (Floating-Point Matrix Multiply-Accumulate)";
1082 case Feature_HasStdExtZvvmtlsBit: return "'Zvvmtls' (Matrix Tile Load/Store)";
1083 case Feature_HasStdExtZvvmttlsBit: return "'Zvvmttls' (Transposing Matrix Tile Load/Store)";
1084 case Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit: return "'Zvqwbdota8i' or 'Zvqwbdota16i' (8-bit or 16-bit integer batched dot-product extension)";
1085 case Feature_HasStdExtZvfwbdota16bfBit: return "'Zvfwbdota16bf' (BF16 batched dot-product extension)";
1086 case Feature_HasStdExtZvfqwbdota8fBit: return "'Zvfqwbdota8f' (OCP FP8 batched dot-product extension)";
1087 case Feature_HasStdExtZvfbdota32fBit: return "'Zvfbdota32f' (FP32 batched dot-product extension)";
1088 case Feature_HasVInstructionsBit: return "'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors)";
1089 case Feature_HasVInstructionsI64Bit: return "'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors)";
1090 case Feature_HasVInstructionsAnyFBit: return "'V' (Vector Extension for Application Processors), 'Zve32f' (Vector Extensions for Embedded Processors)";
1091 case Feature_HasVInstructionsF16MinimalBit: return "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or 'Zvfh' (Vector Half-Precision Floating-Point)";
1092 case Feature_HasStdExtHBit: return "'H' (Hypervisor)";
1093 case Feature_HasStdExtSmrnmiBit: return "'Smrnmi' (Resumable Non-Maskable Interrupts)";
1094 case Feature_HasStdExtSvinvalBit: return "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)";
1095 case Feature_HasStdExtSmctrOrSsctrBit: return "'Smctr' (Control Transfer Records Machine Level) or 'Ssctr' (Control Transfer Records Supervisor Level)";
1096 case Feature_HasStdExtPBit: return "'Base P' (Packed SIMD)";
1097 case Feature_HasStdExtZbkbOrPBit: return "'Zbkb' (Bitmanip instructions for Cryptography) or 'Base P' (Packed-SIMD)";
1098 case Feature_HasStdExtYBit: return "'Base Y' (CHERI)";
1099 case Feature_HasVendorXVentanaCondOpsBit: return "'XVentanaCondOps' (Ventana Conditional Ops)";
1100 case Feature_HasVendorXTHeadBaBit: return "'XTHeadBa' (T-Head address calculation instructions)";
1101 case Feature_HasVendorXTHeadBbBit: return "'XTHeadBb' (T-Head basic bit-manipulation instructions)";
1102 case Feature_HasVendorXTHeadBsBit: return "'XTHeadBs' (T-Head single-bit instructions)";
1103 case Feature_HasVendorXTHeadCondMovBit: return "'XTHeadCondMov' (T-Head conditional move instructions)";
1104 case Feature_HasVendorXTHeadCmoBit: return "'XTHeadCmo' (T-Head cache management instructions)";
1105 case Feature_HasVendorXTHeadFMemIdxBit: return "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)";
1106 case Feature_HasVendorXTHeadMacBit: return "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)";
1107 case Feature_HasVendorXTHeadMemIdxBit: return "'XTHeadMemIdx' (T-Head Indexed Memory Operations)";
1108 case Feature_HasVendorXTHeadMemPairBit: return "'XTHeadMemPair' (T-Head two-GPR Memory Operations)";
1109 case Feature_HasVendorXTHeadSyncBit: return "'XTHeadSync' (T-Head multicore synchronization instructions)";
1110 case Feature_HasVendorXTHeadVdotBit: return "'XTHeadVdot' (T-Head Vector Extensions for Dot)";
1111 case Feature_HasVendorXSfvcpBit: return "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)";
1112 case Feature_HasVendorXSfmmbaseBit: return "'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)";
1113 case Feature_HasVendorXSfmm32a8fBit: return "'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)";
1114 case Feature_HasVendorXSfmm32a8iBit: return "'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)";
1115 case Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit: return "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF)), or 'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b), or 'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)";
1116 case Feature_HasVendorXSfvqmaccdodBit: return "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))";
1117 case Feature_HasVendorXSfvqmaccqoqBit: return "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))";
1118 case Feature_HasVendorXSfvfwmaccqqqBit: return "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))";
1119 case Feature_HasVendorXSfvfnrclipxfqfBit: return "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)";
1120 case Feature_HasVendorXSfvfexpAnyBit: return "'Xsfvfbfexp16e', 'Xsfvfexp16e', or 'Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction)";
1121 case Feature_HasVendorXSfvfexpaBit: return "'Xsfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)";
1122 case Feature_HasVendorXSiFivecdiscarddloneBit: return "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)";
1123 case Feature_HasVendorXSiFivecflushdloneBit: return "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)";
1124 case Feature_HasVendorXSfceaseBit: return "'XSfcease' (SiFive sf.cease Instruction)";
1125 case Feature_HasVendorXCVelwBit: return "'XCVelw' (CORE-V Event Load Word)";
1126 case Feature_HasVendorXCVbitmanipBit: return "'XCVbitmanip' (CORE-V Bit Manipulation)";
1127 case Feature_HasVendorXCVmacBit: return "'XCVmac' (CORE-V Multiply-Accumulate)";
1128 case Feature_HasVendorXCVmemBit: return "'XCVmem' (CORE-V Post-incrementing Load & Store)";
1129 case Feature_HasVendorXCValuBit: return "'XCValu' (CORE-V ALU Operations)";
1130 case Feature_HasVendorXCVsimdBit: return "'XCVsimd' (CORE-V SIMD ALU)";
1131 case Feature_HasVendorXCVbiBit: return "'XCVbi' (CORE-V Immediate Branching)";
1132 case Feature_HasVendorXMIPSCMovBit: return "'Xmipscmov' ('mips.ccmov' instruction)";
1133 case Feature_HasVendorXMIPSLSPBit: return "'Xmipslsp' (load and store pair instructions)";
1134 case Feature_HasVendorXMIPSCBOPBit: return "'Xmipscbop' (MIPS hardware prefetch)";
1135 case Feature_HasVendorXMIPSEXECTLBit: return "'Xmipsexectl' (MIPS execution control)";
1136 case Feature_HasVendorXwchcBit: return "'Xwchc' (WCH/QingKe additional compressed opcodes)";
1137 case Feature_HasVendorXqccmpBit: return "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)";
1138 case Feature_HasVendorXqccmtBit: return "'Xqccmt' (Qualcomm 16-bit Table Jump)";
1139 case Feature_HasVendorXqciaBit: return "'Xqcia' (Qualcomm uC Arithmetic Extension)";
1140 case Feature_HasVendorXqciacBit: return "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)";
1141 case Feature_HasVendorXqcibiBit: return "'Xqcibi' (Qualcomm uC Branch Immediate Extension)";
1142 case Feature_HasVendorXqcibmBit: return "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)";
1143 case Feature_HasVendorXqcicliBit: return "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)";
1144 case Feature_HasVendorXqcicmBit: return "'Xqcicm' (Qualcomm uC Conditional Move Extension)";
1145 case Feature_HasVendorXqcicsBit: return "'Xqcics' (Qualcomm uC Conditional Select Extension)";
1146 case Feature_HasVendorXqcicsrBit: return "'Xqcicsr' (Qualcomm uC CSR Extension)";
1147 case Feature_HasVendorXqciintBit: return "'Xqciint' (Qualcomm uC Interrupts Extension)";
1148 case Feature_HasVendorXqciioBit: return "'Xqciio' (Qualcomm uC External Input Output Extension)";
1149 case Feature_HasVendorXqcilbBit: return "'Xqcilb' (Qualcomm uC Long Branch Extension)";
1150 case Feature_HasVendorXqciliBit: return "'Xqcili' (Qualcomm uC Load Large Immediate Extension)";
1151 case Feature_HasVendorXqciliaBit: return "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)";
1152 case Feature_HasVendorXqciloBit: return "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)";
1153 case Feature_HasVendorXqcilsmBit: return "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)";
1154 case Feature_HasVendorXqcisimBit: return "'Xqcisim' (Qualcomm uC Simulation Hint Extension)";
1155 case Feature_HasVendorXqcislsBit: return "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)";
1156 case Feature_HasVendorXqcisyncBit: return "'Xqcisync' (Qualcomm uC Sync Delay Extension)";
1157 case Feature_HasVendorXAndesPerfBit: return "'XAndesPerf' (Andes Performance Extension)";
1158 case Feature_HasVendorXAndesBFHCvtBit: return "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)";
1159 case Feature_HasVendorXAndesVBFHCvtBit: return "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)";
1160 case Feature_HasVendorXAndesVSIntHBit: return "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)";
1161 case Feature_HasVendorXAndesVSIntLoadBit: return "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)";
1162 case Feature_HasVendorXAndesVPackFPHBit: return "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)";
1163 case Feature_HasVendorXAndesVDotBit: return "'XAndesVDot' (Andes Vector Dot Product Extension)";
1164 case Feature_HasVendorXSMTVDotBit: return "'XSMTVDot' (SpacemiT Vector Dot Product Extension)";
1165 case Feature_HasVendorXSMTVDotIIBit: return "'XSMTVDotII' (SpacemiT Vector Extension for Matrix 2.0)";
1166 case Feature_HasXAIFETBit: return "'XAIFET' (AI Foundry ET Extension)";
1167 case Feature_HasCheriotBit: return "'XCheriot' (CHERIoT Extension)";
1168 case Feature_IsRV64Bit: return "RV64I Base Instruction Set";
1169 case Feature_IsRV32Bit: return "RV32I Base Instruction Set";
1170 default: return "(unknown)";
1171 }
1172}
1173
1174#endif // GET_SUBTARGET_FEATURE_NAME
1175
1176
1177#ifdef GET_MATCHER_IMPLEMENTATION
1178#undef GET_MATCHER_IMPLEMENTATION
1179
1180static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
1181 switch (Mnemonic.size()) {
1182 default: break;
1183 case 4: // 4 strings to match.
1184 switch (Mnemonic[0]) {
1185 default: break;
1186 case 'f': // 2 strings to match.
1187 switch (Mnemonic[1]) {
1188 default: break;
1189 case 'r': // 1 string to match.
1190 if (memcmp(Mnemonic.data()+2, "sr", 2) != 0)
1191 break;
1192 if (Features.test(Feature_HasStdExtFOrZfinxBit)) // "frsr"
1193 Mnemonic = "frcsr";
1194 return;
1195 case 's': // 1 string to match.
1196 if (memcmp(Mnemonic.data()+2, "sr", 2) != 0)
1197 break;
1198 if (Features.test(Feature_HasStdExtFOrZfinxBit)) // "fssr"
1199 Mnemonic = "fscsr";
1200 return;
1201 }
1202 break;
1203 case 'm': // 1 string to match.
1204 if (memcmp(Mnemonic.data()+1, "ove", 3) != 0)
1205 break;
1206 Mnemonic = "mv"; // "move"
1207 return;
1208 case 'y': // 1 string to match.
1209 if (memcmp(Mnemonic.data()+1, "hiw", 3) != 0)
1210 break;
1211 if (Features.test(Feature_HasStdExtYBit)) // "yhiw"
1212 Mnemonic = "packy";
1213 return;
1214 }
1215 break;
1216 case 5: // 1 string to match.
1217 if (memcmp(Mnemonic.data()+0, "scall", 5) != 0)
1218 break;
1219 Mnemonic = "ecall"; // "scall"
1220 return;
1221 case 6: // 3 strings to match.
1222 switch (Mnemonic[0]) {
1223 default: break;
1224 case 's': // 1 string to match.
1225 if (memcmp(Mnemonic.data()+1, "break", 5) != 0)
1226 break;
1227 Mnemonic = "ebreak"; // "sbreak"
1228 return;
1229 case 'v': // 2 strings to match.
1230 switch (Mnemonic[1]) {
1231 default: break;
1232 case 'l': // 1 string to match.
1233 if (memcmp(Mnemonic.data()+2, "e1.v", 4) != 0)
1234 break;
1235 if (Features.test(Feature_HasVInstructionsBit)) // "vle1.v"
1236 Mnemonic = "vlm.v";
1237 return;
1238 case 's': // 1 string to match.
1239 if (memcmp(Mnemonic.data()+2, "e1.v", 4) != 0)
1240 break;
1241 if (Features.test(Feature_HasVInstructionsBit)) // "vse1.v"
1242 Mnemonic = "vsm.v";
1243 return;
1244 }
1245 break;
1246 }
1247 break;
1248 case 7: // 4 strings to match.
1249 switch (Mnemonic[0]) {
1250 default: break;
1251 case 'c': // 1 string to match.
1252 if (memcmp(Mnemonic.data()+1, "v.slet", 6) != 0)
1253 break;
1254 if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit)) // "cv.slet"
1255 Mnemonic = "cv.sle";
1256 return;
1257 case 'f': // 2 strings to match.
1258 if (memcmp(Mnemonic.data()+1, "mv.", 3) != 0)
1259 break;
1260 switch (Mnemonic[4]) {
1261 default: break;
1262 case 's': // 1 string to match.
1263 if (memcmp(Mnemonic.data()+5, ".x", 2) != 0)
1264 break;
1265 if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x"
1266 Mnemonic = "fmv.w.x";
1267 return;
1268 case 'x': // 1 string to match.
1269 if (memcmp(Mnemonic.data()+5, ".s", 2) != 0)
1270 break;
1271 if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s"
1272 Mnemonic = "fmv.x.w";
1273 return;
1274 }
1275 break;
1276 case 'v': // 1 string to match.
1277 if (memcmp(Mnemonic.data()+1, "popc.m", 6) != 0)
1278 break;
1279 if (Features.test(Feature_HasVInstructionsBit)) // "vpopc.m"
1280 Mnemonic = "vcpop.m";
1281 return;
1282 }
1283 break;
1284 case 8: // 1 string to match.
1285 if (memcmp(Mnemonic.data()+0, "cv.sletu", 8) != 0)
1286 break;
1287 if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit)) // "cv.sletu"
1288 Mnemonic = "cv.sleu";
1289 return;
1290 case 10: // 1 string to match.
1291 if (memcmp(Mnemonic.data()+0, "vmornot.mm", 10) != 0)
1292 break;
1293 if (Features.test(Feature_HasVInstructionsBit)) // "vmornot.mm"
1294 Mnemonic = "vmorn.mm";
1295 return;
1296 case 11: // 2 strings to match.
1297 if (Mnemonic[0] != 'v')
1298 break;
1299 switch (Mnemonic[1]) {
1300 default: break;
1301 case 'f': // 1 string to match.
1302 if (memcmp(Mnemonic.data()+2, "redsum.vs", 9) != 0)
1303 break;
1304 if (Features.test(Feature_HasVInstructionsAnyFBit)) // "vfredsum.vs"
1305 Mnemonic = "vfredusum.vs";
1306 return;
1307 case 'm': // 1 string to match.
1308 if (memcmp(Mnemonic.data()+2, "andnot.mm", 9) != 0)
1309 break;
1310 if (Features.test(Feature_HasVInstructionsBit)) // "vmandnot.mm"
1311 Mnemonic = "vmandn.mm";
1312 return;
1313 }
1314 break;
1315 case 12: // 1 string to match.
1316 if (memcmp(Mnemonic.data()+0, "vfwredsum.vs", 12) != 0)
1317 break;
1318 if (Features.test(Feature_HasVInstructionsAnyFBit)) // "vfwredsum.vs"
1319 Mnemonic = "vfwredusum.vs";
1320 return;
1321 }
1322}
1323
1324enum {
1325 Tie0_1_1,
1326 Tie0_2_2,
1327 Tie0_3_3,
1328 Tie1_3_3,
1329};
1330
1331static const uint8_t TiedAsmOperandTable[][3] = {
1332 /* Tie0_1_1 */ { 0, 1, 1 },
1333 /* Tie0_2_2 */ { 0, 2, 2 },
1334 /* Tie0_3_3 */ { 0, 3, 3 },
1335 /* Tie1_3_3 */ { 1, 3, 3 },
1336};
1337
1338namespace {
1339enum OperatorConversionKind {
1340 CVT_Done,
1341 CVT_Reg,
1342 CVT_Tied,
1343 CVT_95_addImmOperands,
1344 CVT_95_addRegOperands,
1345 CVT_imm_95_0,
1346 CVT_95_Reg,
1347 CVT_95_addFRMArgOperands_95_defaultFRMArgOp,
1348 CVT_regX0,
1349 CVT_regX1,
1350 CVT_regX5,
1351 CVT_regX2,
1352 CVT_regX3,
1353 CVT_regX4,
1354 CVT_95_addRegListOperands,
1355 CVT_95_addStackAdjOperands,
1356 CVT_95_addCSRSystemRegisterOperands,
1357 CVT_95_addRegRegOperands,
1358 CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp,
1359 CVT_95_addFRMArgOperands,
1360 CVT_imm_95_15,
1361 CVT_95_addFenceArgOperands,
1362 CVT_95_addFPImmOperands,
1363 CVT_imm_95_3,
1364 CVT_imm_95_1,
1365 CVT_imm_95_2,
1366 CVT_regX0_Pair,
1367 CVT_95_addRegOperands_95_defaultMaskRegOp,
1368 CVT_imm_95__MINUS_1,
1369 CVT_95_addSExtImmOperands_LT_8_GT_,
1370 CVT_95_addSExtImmOperands_LT_10_GT_,
1371 CVT_imm_95_8,
1372 CVT_imm_95_16,
1373 CVT_imm_95_1536,
1374 CVT_imm_95__MINUS_1280,
1375 CVT_imm_95__MINUS_2048,
1376 CVT_imm_95_1792,
1377 CVT_imm_95__MINUS_1792,
1378 CVT_imm_95__MINUS_1536,
1379 CVT_imm_95__MINUS_1024,
1380 CVT_imm_95_3072,
1381 CVT_imm_95_3200,
1382 CVT_imm_95_3074,
1383 CVT_imm_95_3202,
1384 CVT_imm_95_3073,
1385 CVT_imm_95_3201,
1386 CVT_95_addVTypeIOperands,
1387 CVT_95_addSMTVTypeOperand_95_defaultSMTVType,
1388 CVT_reg0,
1389 CVT_imm_95_64,
1390 CVT_imm_95_32,
1391 CVT_imm_95_255,
1392 CVT_NUM_CONVERTERS
1393};
1394
1395enum InstructionConversionKind {
1396 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4,
1397 Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4,
1398 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3,
1399 Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3,
1400 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3,
1401 Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2,
1402 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0,
1403 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3,
1404 Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3,
1405 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0,
1406 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3,
1407 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3,
1408 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4,
1409 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0,
1410 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm12LO1_3,
1411 Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2,
1412 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4,
1413 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5,
1414 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5,
1415 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_5__imm_95_0,
1416 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__SImm261_4,
1417 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4,
1418 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_5__imm_95_0,
1419 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__SImm261_4,
1420 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5,
1421 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6,
1422 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0,
1423 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm12LO1_3,
1424 Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2,
1425 Convert__Reg1_0__Reg1_1__Reg1_2,
1426 Convert__Reg1_0__Reg1_1,
1427 Convert__Reg1_0__Reg1_1__SImm12LO1_2,
1428 Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3,
1429 Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2,
1430 Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3,
1431 Convert__Reg1_0__Reg1_1__RnumArg1_2,
1432 Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2,
1433 Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3,
1434 Convert__Reg1_0__Reg1_1__SImm101_2,
1435 Convert__Reg1_0__SImm12LO1_1__Reg1_3,
1436 Convert__Reg1_0__UImm20LUI1_1,
1437 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
1438 Convert__Reg1_0__Reg1_1__FRMArg1_2,
1439 Convert__Reg1_0__Reg1_2,
1440 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4,
1441 Convert__Reg1_0__Reg1_1__UImm31_2,
1442 Convert__Reg1_0__Reg1_1__UImm51_2,
1443 Convert__Reg1_0__Reg1_1__UImm81_2,
1444 Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3,
1445 Convert__Reg1_0,
1446 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1,
1447 Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2,
1448 Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2,
1449 Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2,
1450 Convert__Reg1_0__UImm20AUIPC1_1,
1451 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2,
1452 Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2,
1453 Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2,
1454 Convert__Reg1_0__regX0__BareSImm13Lsb01_1,
1455 Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2,
1456 Convert__regX0__Reg1_0__BareSImm13Lsb01_1,
1457 Convert__Reg1_0__Tie0_1_1__Reg1_1,
1458 Convert__Reg1_0__Tie0_1_1__SImm61_1,
1459 Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1,
1460 Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2,
1461 Convert__Reg1_0__BareSImm9Lsb01_1,
1462 Convert_NoOperands,
1463 Convert__Reg1_0__Reg1_2__imm_95_0,
1464 Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1,
1465 Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1,
1466 Convert__Reg1_0__Reg1_3__UImm7Lsb001_1,
1467 Convert__Reg1_0__Reg1_3__UImm8Lsb001_1,
1468 Convert__BareSImm12Lsb01_0,
1469 Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4,
1470 Convert__Reg1_0__Reg1_3__UImm21_1,
1471 Convert__Reg1_0__Reg1_3__UImm21_1__QCAccessSymbol1_5,
1472 Convert__GPRPairCRV321_0__Reg1_2__imm_95_0,
1473 Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1,
1474 Convert__GPRPairNoX0RV321_0__Reg1_2__imm_95_0,
1475 Convert__GPRPairNoX0RV321_0__Reg1_3__UImm9Lsb0001_1,
1476 Convert__Reg1_0__Reg1_3__UImm2Lsb01_1,
1477 Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5,
1478 Convert__Reg1_0__SImm61_1,
1479 Convert__Reg1_0__CLUIImm1_1,
1480 Convert__Reg1_0__Reg1_3__UImm7Lsb001_1__QCAccessSymbol1_5,
1481 Convert__regX1,
1482 Convert__regX5,
1483 Convert__SImm6NonZero1_0,
1484 Convert__Reg1_0__Tie0_1_1,
1485 Convert__regX0__Tie0_1_1__regX5,
1486 Convert__regX0__Tie0_1_1__regX2,
1487 Convert__regX0__Tie0_1_1__regX3,
1488 Convert__regX0__Tie0_1_1__regX4,
1489 Convert__GPRPairRV321_0__Reg1_2__imm_95_0,
1490 Convert__GPRPairRV321_0__Reg1_3__UImm9Lsb0001_1,
1491 Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1,
1492 Convert__Reg1_0__Tie0_1_1__imm_95_0,
1493 Convert__CallSymbol1_0,
1494 Convert__Reg1_0__CallSymbol1_1,
1495 Convert__ZeroOffsetMemOpOperand1_0,
1496 Convert__UImm8GE321_0,
1497 Convert__UImm51_0,
1498 Convert__RegList1_0__StackAdj1_1,
1499 Convert__RegList1_0__NegStackAdj1_1,
1500 Convert__regX0__CSRSystemRegister1_0__Reg1_1,
1501 Convert__regX0__CSRSystemRegister1_0__UImm51_1,
1502 Convert__Reg1_0__CSRSystemRegister1_1__regX0,
1503 Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2,
1504 Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2,
1505 Convert__Reg1_0__Reg1_1__SImm61_2,
1506 Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3,
1507 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
1508 Convert__Reg1_0__Reg1_1__UImm61_2,
1509 Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3,
1510 Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2,
1511 Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3,
1512 Convert__Reg1_0__BareSymbol1_1,
1513 Convert__Reg1_0__Reg1_3__SImm12LO1_1,
1514 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3,
1515 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2,
1516 Convert__Reg1_0__RegReg2_1,
1517 Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4,
1518 Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4,
1519 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3,
1520 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
1521 Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4,
1522 Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4,
1523 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2,
1524 Convert__Reg1_0__Reg1_1__UImm41_2,
1525 Convert__Reg1_0__Reg1_1__Reg1_1,
1526 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1,
1527 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1,
1528 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1,
1529 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1,
1530 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3,
1531 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3,
1532 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3,
1533 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3,
1534 Convert__Reg1_0__GPRF64AsFPR1_1,
1535 Convert__Reg1_0__GPRPairAsFPR1_1,
1536 Convert__Reg1_0__GPRAsFPR161_1,
1537 Convert__Reg1_0__GPRAsFPR321_1,
1538 Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2,
1539 Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1540 Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1541 Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2,
1542 Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
1543 Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
1544 Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2,
1545 Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2,
1546 Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2,
1547 Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2,
1548 Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2,
1549 Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2,
1550 Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2,
1551 Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2,
1552 Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2,
1553 Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2,
1554 Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2,
1555 Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1556 Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2,
1557 Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2,
1558 Convert__Reg1_0__Reg1_1__RTZArg1_2,
1559 Convert__imm_95_15__imm_95_15,
1560 Convert__FenceArg1_0__FenceArg1_1,
1561 Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
1562 Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
1563 Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2,
1564 Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2,
1565 Convert__Reg1_0__Reg1_2__Reg1_1,
1566 Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1,
1567 Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1,
1568 Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1,
1569 Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1,
1570 Convert__Reg1_2__Reg1_0__BareSymbol1_1,
1571 Convert__Reg1_0__LoadFPImm1_1,
1572 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4,
1573 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4,
1574 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4,
1575 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4,
1576 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
1577 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
1578 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2,
1579 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2,
1580 Convert__Reg1_0__imm_95_3__regX0,
1581 Convert__Reg1_0__imm_95_1__regX0,
1582 Convert__Reg1_0__imm_95_2__regX0,
1583 Convert__regX0__imm_95_3__Reg1_0,
1584 Convert__Reg1_0__imm_95_3__Reg1_1,
1585 Convert__regX0__imm_95_1__Reg1_0,
1586 Convert__Reg1_0__imm_95_1__Reg1_1,
1587 Convert__regX0__imm_95_1__UImm51_0,
1588 Convert__Reg1_0__imm_95_1__UImm51_1,
1589 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2,
1590 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2,
1591 Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2,
1592 Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2,
1593 Convert__regX0__imm_95_2__Reg1_0,
1594 Convert__Reg1_0__imm_95_2__Reg1_1,
1595 Convert__regX0__imm_95_2__UImm51_0,
1596 Convert__Reg1_0__imm_95_2__UImm51_1,
1597 Convert__regX0__regX0,
1598 Convert__Reg1_0__regX0,
1599 Convert__regX0__BareSImm21Lsb01_0,
1600 Convert__regX1__BareSImm21Lsb01_0,
1601 Convert__Reg1_0__BareSImm21Lsb01_1,
1602 Convert__regX1__Reg1_0__imm_95_0,
1603 Convert__Reg1_0__Reg1_1__imm_95_0,
1604 Convert__regX1__Reg1_0__SImm12LO1_1,
1605 Convert__regX1__Reg1_1__imm_95_0,
1606 Convert__regX1__Reg1_2__SImm12LO1_0,
1607 Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5,
1608 Convert__regX0__Reg1_0__imm_95_0,
1609 Convert__regX0__Reg1_0__SImm12LO1_1,
1610 Convert__regX0__Reg1_1__imm_95_0,
1611 Convert__regX0__Reg1_2__SImm12LO1_0,
1612 Convert__Reg1_1__PseudoJumpSymbol1_0,
1613 Convert__Reg1_0__ImmXLenLI_Restricted1_1,
1614 Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5,
1615 Convert__GPRPairRV321_0__BareSymbol1_1,
1616 Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1,
1617 Convert__Reg1_0__regX0__SImm12LO1_1,
1618 Convert__Reg1_0__ImmXLenLI1_1,
1619 Convert__regX0__UImm201_0,
1620 Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3,
1621 Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2,
1622 Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2,
1623 Convert__Reg1_3__UImm91_1__UImm51_0,
1624 Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2,
1625 Convert__Reg1_0__Reg1_1__regX0,
1626 Convert__Reg1_0__regX0__Reg1_1,
1627 Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1,
1628 Convert__Reg1_0__GPRPairRV321_1__Reg1_2,
1629 Convert__Reg1_0__GPRPairRV321_1__UImm61_2,
1630 Convert__Reg1_0__SImm181_1,
1631 Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2,
1632 Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2,
1633 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3,
1634 Convert__Reg1_0__SImm20Lsb0001_1,
1635 Convert__Reg1_0__SImm18Lsb01_1,
1636 Convert__Reg1_0__SImm19Lsb001_1,
1637 Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1638 Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3,
1639 Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2,
1640 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2,
1641 Convert__regX0__regX0__imm_95_0,
1642 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1,
1643 Convert__regX0__regX0__regX5,
1644 Convert__regX0__regX0__regX2,
1645 Convert__regX0__regX0__regX3,
1646 Convert__regX0__regX0__regX4,
1647 Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair,
1648 Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2,
1649 Convert__imm_95_1__imm_95_0,
1650 Convert__Reg1_0__SImm8PLI_B1_1,
1651 Convert__GPRPairRV321_0__SImm8PLI_B1_1,
1652 Convert__GPRPairRV321_0__SImm10PLI_H1_1,
1653 Convert__Reg1_0__SImm10PLI_H1_1,
1654 Convert__Reg1_0__SImm10PLI_W1_1,
1655 Convert__GPRPairRV321_0__SImm10PLUI1_1,
1656 Convert__Reg1_0__SImm10PLUI1_1,
1657 Convert__GPRPairRV321_0__Reg1_1__Reg1_2,
1658 Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1,
1659 Convert__GPRPairRV321_0__regX0_Pair__Reg1_1,
1660 Convert__Reg1_0__GPRPairRV321_1__UImm41_2,
1661 Convert__Reg1_0__GPRPairRV321_1__UImm51_2,
1662 Convert__Reg1_0__GPRPairRV321_1__imm_95_0,
1663 Convert__Reg1_0__GPRPairRV321_1__imm_95_8,
1664 Convert__Reg1_0__GPRPairRV321_1__imm_95_16,
1665 Convert__Reg1_2__SImm12Lsb000001_0,
1666 Convert__GPRPairRV321_0__GPRPairRV321_1,
1667 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2,
1668 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2,
1669 Convert__Reg1_0__Reg1_1__UImm4Plus11_2,
1670 Convert__Reg1_0__Reg1_1__UImm5Plus11_2,
1671 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2,
1672 Convert__GPRPairRV321_0__Reg1_1__regX0,
1673 Convert__GPRPairRV321_0__regX0__Reg1_1,
1674 Convert__GPRPairRV321_0__Reg1_1__UImm41_2,
1675 Convert__GPRPairRV321_0__Reg1_1__UImm51_2,
1676 Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2,
1677 Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2,
1678 Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1,
1679 Convert__regX0__Tie0_1_1__UImm5NonZero1_0,
1680 Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1,
1681 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2,
1682 Convert__regX0__Tie0_1_1__imm_95_0,
1683 Convert__UImm5Slist1_0,
1684 Convert__UImm101_0,
1685 Convert__RegListS01_0__NegStackAdj1_1,
1686 Convert__Reg1_0__UImm51_1__Reg1_2,
1687 Convert__Reg1_0__Tie0_1_1__BareSImm321_1,
1688 Convert__Reg1_0__Reg1_1__SImm261_2,
1689 Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2,
1690 Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2,
1691 Convert__BareSImm32Lsb01_0,
1692 Convert__Reg1_0__Reg1_3__SImm261_1,
1693 Convert__Reg1_0__BareSImm321_1,
1694 Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1,
1695 Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3,
1696 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3,
1697 Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3,
1698 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2,
1699 Convert__Reg1_0__Reg1_3__UImm14Lsb001_1,
1700 Convert__Reg1_0__SImm20LI1_1,
1701 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3,
1702 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3,
1703 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3,
1704 Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3,
1705 Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0,
1706 Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2,
1707 Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0,
1708 Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2,
1709 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2,
1710 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3,
1711 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3,
1712 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3,
1713 Convert__regX0__regX0__imm_95_1536,
1714 Convert__regX0__Reg1_0__imm_95__MINUS_1280,
1715 Convert__regX0__Reg1_0__imm_95__MINUS_2048,
1716 Convert__regX0__regX0__imm_95_1792,
1717 Convert__regX0__Reg1_0__imm_95__MINUS_1792,
1718 Convert__UImm81_0,
1719 Convert__regX0__Reg1_0__imm_95__MINUS_1536,
1720 Convert__regX0__Reg1_0__imm_95__MINUS_1024,
1721 Convert__regX0__regX0__UImm101_0,
1722 Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3,
1723 Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3,
1724 Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3,
1725 Convert__Reg1_0__Reg1_1__UImm111_2,
1726 Convert__Reg1_0__Reg1_3__UImm51_1,
1727 Convert__Reg1_0__Reg1_3__UImm41_1,
1728 Convert__Reg1_0__Reg1_3__UImm6Lsb01_1,
1729 Convert__Reg1_0__Reg1_3__UImm5Lsb01_1,
1730 Convert__Reg1_0__imm_95_3072__regX0,
1731 Convert__Reg1_0__imm_95_3200__regX0,
1732 Convert__Reg1_0__imm_95_3074__regX0,
1733 Convert__Reg1_0__imm_95_3202__regX0,
1734 Convert__Reg1_0__imm_95_3073__regX0,
1735 Convert__Reg1_0__imm_95_3201__regX0,
1736 Convert__regX0__regX1__imm_95_0,
1737 Convert__Reg1_0__Reg1_1__UImm6Plus11_2,
1738 Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1,
1739 Convert__Reg1_0__Reg1_1__imm_95_1,
1740 Convert__regX0,
1741 Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3,
1742 Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3,
1743 Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3,
1744 Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3,
1745 Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3,
1746 Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3,
1747 Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3,
1748 Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3,
1749 Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3,
1750 Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3,
1751 Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3,
1752 Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3,
1753 Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3,
1754 Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3,
1755 Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3,
1756 Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3,
1757 Convert__Reg1_0__Reg1_1__XSfmmVType1_2,
1758 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3,
1759 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5,
1760 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5,
1761 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3,
1762 Convert__Reg1_0__Reg1_1__UImm7EqXLen1_2,
1763 Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5,
1764 Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6,
1765 Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6,
1766 Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5,
1767 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1768 Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3,
1769 Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3,
1770 Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3,
1771 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3,
1772 Convert__Reg1_0__Reg1_1__Reg1_1__reg0,
1773 Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2,
1774 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4,
1775 Convert__Reg1_0__RVVMaskRegOpOperand1_1,
1776 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1777 Convert__Reg1_0__Reg1_1__SImm51_2,
1778 Convert__Reg1_0__Reg1_0__Reg1_0,
1779 Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3,
1780 Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1781 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3,
1782 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4,
1783 Convert__Reg1_0__SImm51_1,
1784 Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3,
1785 Convert__Reg1_0__Reg1_1__regX0__reg0,
1786 Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2,
1787 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0,
1788 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2,
1789 Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3,
1790 Convert__Reg1_0__UImm51_1__VTypeI101_2,
1791 Convert__Reg1_0__Reg1_1__VTypeI111_2,
1792 Convert__GPRPairRV321_0__Reg1_1__UImm61_2,
1793 Convert__Reg1_0__Reg1_1__YBNDSWImm1_2,
1794 Convert__Reg1_0__Reg1_1__imm_95_64,
1795 Convert__Reg1_0__Reg1_1__imm_95_32,
1796 Convert__Reg1_0__Reg1_1__imm_95_255,
1797 CVT_NUM_SIGNATURES
1798};
1799
1800} // end anonymous namespace
1801
1802static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][15] = {
1803 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4
1804 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1805 // Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4
1806 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_Done },
1807 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3
1808 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1809 // Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3
1810 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
1811 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3
1812 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
1813 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2
1814 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1815 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0
1816 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1817 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3
1818 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1819 // Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3
1820 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_Done },
1821 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0
1822 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1823 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3
1824 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1825 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3
1826 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1827 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4
1828 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1829 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0
1830 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1831 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm12LO1_3
1832 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1833 // Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2
1834 { CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
1835 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4
1836 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
1837 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5
1838 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1839 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5
1840 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1841 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_5__imm_95_0
1842 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
1843 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__SImm261_4
1844 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 7, CVT_95_addImmOperands, 5, CVT_Done },
1845 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4
1846 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1847 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_5__imm_95_0
1848 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
1849 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__SImm261_4
1850 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addRegOperands, 7, CVT_95_addImmOperands, 5, CVT_Done },
1851 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5
1852 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
1853 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6
1854 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_95_addRegOperands, 7, CVT_Done },
1855 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0
1856 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1857 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm12LO1_3
1858 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1859 // Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2
1860 { CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
1861 // Convert__Reg1_0__Reg1_1__Reg1_2
1862 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1863 // Convert__Reg1_0__Reg1_1
1864 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1865 // Convert__Reg1_0__Reg1_1__SImm12LO1_2
1866 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1867 // Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3
1868 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1869 // Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2
1870 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1871 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3
1872 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1873 // Convert__Reg1_0__Reg1_1__RnumArg1_2
1874 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1875 // Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2
1876 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands, 3, CVT_Done },
1877 // Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3
1878 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
1879 // Convert__Reg1_0__Reg1_1__SImm101_2
1880 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1881 // Convert__Reg1_0__SImm12LO1_1__Reg1_3
1882 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_Done },
1883 // Convert__Reg1_0__UImm20LUI1_1
1884 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1885 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
1886 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
1887 // Convert__Reg1_0__Reg1_1__FRMArg1_2
1888 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
1889 // Convert__Reg1_0__Reg1_2
1890 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
1891 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4
1892 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
1893 // Convert__Reg1_0__Reg1_1__UImm31_2
1894 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1895 // Convert__Reg1_0__Reg1_1__UImm51_2
1896 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1897 // Convert__Reg1_0__Reg1_1__UImm81_2
1898 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1899 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3
1900 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1901 // Convert__Reg1_0
1902 { CVT_95_Reg, 1, CVT_Done },
1903 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1
1904 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
1905 // Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2
1906 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addRegOperands, 3, CVT_Done },
1907 // Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2
1908 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1909 // Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2
1910 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1911 // Convert__Reg1_0__UImm20AUIPC1_1
1912 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1913 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2
1914 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1915 // Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2
1916 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1917 // Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2
1918 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1919 // Convert__Reg1_0__regX0__BareSImm13Lsb01_1
1920 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
1921 // Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2
1922 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },
1923 // Convert__regX0__Reg1_0__BareSImm13Lsb01_1
1924 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1925 // Convert__Reg1_0__Tie0_1_1__Reg1_1
1926 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
1927 // Convert__Reg1_0__Tie0_1_1__SImm61_1
1928 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1929 // Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1
1930 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1931 // Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2
1932 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1933 // Convert__Reg1_0__BareSImm9Lsb01_1
1934 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1935 // Convert_NoOperands
1936 { CVT_Done },
1937 // Convert__Reg1_0__Reg1_2__imm_95_0
1938 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1939 // Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1
1940 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1941 // Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1
1942 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1943 // Convert__Reg1_0__Reg1_3__UImm7Lsb001_1
1944 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1945 // Convert__Reg1_0__Reg1_3__UImm8Lsb001_1
1946 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1947 // Convert__BareSImm12Lsb01_0
1948 { CVT_95_addImmOperands, 1, CVT_Done },
1949 // Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4
1950 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 5, CVT_Done },
1951 // Convert__Reg1_0__Reg1_3__UImm21_1
1952 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1953 // Convert__Reg1_0__Reg1_3__UImm21_1__QCAccessSymbol1_5
1954 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
1955 // Convert__GPRPairCRV321_0__Reg1_2__imm_95_0
1956 { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1957 // Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1
1958 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1959 // Convert__GPRPairNoX0RV321_0__Reg1_2__imm_95_0
1960 { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1961 // Convert__GPRPairNoX0RV321_0__Reg1_3__UImm9Lsb0001_1
1962 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1963 // Convert__Reg1_0__Reg1_3__UImm2Lsb01_1
1964 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1965 // Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5
1966 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
1967 // Convert__Reg1_0__SImm61_1
1968 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1969 // Convert__Reg1_0__CLUIImm1_1
1970 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1971 // Convert__Reg1_0__Reg1_3__UImm7Lsb001_1__QCAccessSymbol1_5
1972 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
1973 // Convert__regX1
1974 { CVT_regX1, 0, CVT_Done },
1975 // Convert__regX5
1976 { CVT_regX5, 0, CVT_Done },
1977 // Convert__SImm6NonZero1_0
1978 { CVT_95_addImmOperands, 1, CVT_Done },
1979 // Convert__Reg1_0__Tie0_1_1
1980 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1981 // Convert__regX0__Tie0_1_1__regX5
1982 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX5, 0, CVT_Done },
1983 // Convert__regX0__Tie0_1_1__regX2
1984 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX2, 0, CVT_Done },
1985 // Convert__regX0__Tie0_1_1__regX3
1986 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX3, 0, CVT_Done },
1987 // Convert__regX0__Tie0_1_1__regX4
1988 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX4, 0, CVT_Done },
1989 // Convert__GPRPairRV321_0__Reg1_2__imm_95_0
1990 { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1991 // Convert__GPRPairRV321_0__Reg1_3__UImm9Lsb0001_1
1992 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1993 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1
1994 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1995 // Convert__Reg1_0__Tie0_1_1__imm_95_0
1996 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
1997 // Convert__CallSymbol1_0
1998 { CVT_95_addImmOperands, 1, CVT_Done },
1999 // Convert__Reg1_0__CallSymbol1_1
2000 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2001 // Convert__ZeroOffsetMemOpOperand1_0
2002 { CVT_95_addRegOperands, 1, CVT_Done },
2003 // Convert__UImm8GE321_0
2004 { CVT_95_addImmOperands, 1, CVT_Done },
2005 // Convert__UImm51_0
2006 { CVT_95_addImmOperands, 1, CVT_Done },
2007 // Convert__RegList1_0__StackAdj1_1
2008 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
2009 // Convert__RegList1_0__NegStackAdj1_1
2010 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
2011 // Convert__regX0__CSRSystemRegister1_0__Reg1_1
2012 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
2013 // Convert__regX0__CSRSystemRegister1_0__UImm51_1
2014 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2015 // Convert__Reg1_0__CSRSystemRegister1_1__regX0
2016 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_regX0, 0, CVT_Done },
2017 // Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2
2018 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_Reg, 3, CVT_Done },
2019 // Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2
2020 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2021 // Convert__Reg1_0__Reg1_1__SImm61_2
2022 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2023 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3
2024 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2025 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
2026 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2027 // Convert__Reg1_0__Reg1_1__UImm61_2
2028 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2029 // Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3
2030 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2031 // Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2
2032 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2033 // Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3
2034 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2035 // Convert__Reg1_0__BareSymbol1_1
2036 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2037 // Convert__Reg1_0__Reg1_3__SImm12LO1_1
2038 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2039 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3
2040 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2041 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2
2042 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2043 // Convert__Reg1_0__RegReg2_1
2044 { CVT_95_Reg, 1, CVT_95_addRegRegOperands, 2, CVT_Done },
2045 // Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4
2046 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_Reg, 5, CVT_Done },
2047 // Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4
2048 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_Done },
2049 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3
2050 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2051 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
2052 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
2053 // Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4
2054 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
2055 // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4
2056 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
2057 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2
2058 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2059 // Convert__Reg1_0__Reg1_1__UImm41_2
2060 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2061 // Convert__Reg1_0__Reg1_1__Reg1_1
2062 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_Done },
2063 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1
2064 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2065 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1
2066 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2067 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1
2068 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2069 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1
2070 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2071 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3
2072 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2073 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3
2074 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2075 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3
2076 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2077 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3
2078 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2079 // Convert__Reg1_0__GPRF64AsFPR1_1
2080 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2081 // Convert__Reg1_0__GPRPairAsFPR1_1
2082 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2083 // Convert__Reg1_0__GPRAsFPR161_1
2084 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2085 // Convert__Reg1_0__GPRAsFPR321_1
2086 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2087 // Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2
2088 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2089 // Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2
2090 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2091 // Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2
2092 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2093 // Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2
2094 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2095 // Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2
2096 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2097 // Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2
2098 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2099 // Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2
2100 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2101 // Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2
2102 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2103 // Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2
2104 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2105 // Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2
2106 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2107 // Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2
2108 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2109 // Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2
2110 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2111 // Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2
2112 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2113 // Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2
2114 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2115 // Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2
2116 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2117 // Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2
2118 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2119 // Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2
2120 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2121 // Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2
2122 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2123 // Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2
2124 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2125 // Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2
2126 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2127 // Convert__Reg1_0__Reg1_1__RTZArg1_2
2128 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
2129 // Convert__imm_95_15__imm_95_15
2130 { CVT_imm_95_15, 0, CVT_imm_95_15, 0, CVT_Done },
2131 // Convert__FenceArg1_0__FenceArg1_1
2132 { CVT_95_addFenceArgOperands, 1, CVT_95_addFenceArgOperands, 2, CVT_Done },
2133 // Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
2134 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2135 // Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2
2136 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2137 // Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2
2138 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2139 // Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2
2140 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2141 // Convert__Reg1_0__Reg1_2__Reg1_1
2142 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
2143 // Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1
2144 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2145 // Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1
2146 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2147 // Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1
2148 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2149 // Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1
2150 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2151 // Convert__Reg1_2__Reg1_0__BareSymbol1_1
2152 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2153 // Convert__Reg1_0__LoadFPImm1_1
2154 { CVT_95_Reg, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
2155 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4
2156 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2157 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4
2158 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2159 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4
2160 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2161 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4
2162 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2163 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
2164 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2165 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2
2166 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2167 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2
2168 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2169 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2
2170 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2171 // Convert__Reg1_0__imm_95_3__regX0
2172 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_regX0, 0, CVT_Done },
2173 // Convert__Reg1_0__imm_95_1__regX0
2174 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_regX0, 0, CVT_Done },
2175 // Convert__Reg1_0__imm_95_2__regX0
2176 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_regX0, 0, CVT_Done },
2177 // Convert__regX0__imm_95_3__Reg1_0
2178 { CVT_regX0, 0, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
2179 // Convert__Reg1_0__imm_95_3__Reg1_1
2180 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
2181 // Convert__regX0__imm_95_1__Reg1_0
2182 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
2183 // Convert__Reg1_0__imm_95_1__Reg1_1
2184 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
2185 // Convert__regX0__imm_95_1__UImm51_0
2186 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_addImmOperands, 1, CVT_Done },
2187 // Convert__Reg1_0__imm_95_1__UImm51_1
2188 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_addImmOperands, 2, CVT_Done },
2189 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2
2190 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2191 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2
2192 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2193 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2
2194 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2195 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2
2196 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2197 // Convert__regX0__imm_95_2__Reg1_0
2198 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
2199 // Convert__Reg1_0__imm_95_2__Reg1_1
2200 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
2201 // Convert__regX0__imm_95_2__UImm51_0
2202 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_addImmOperands, 1, CVT_Done },
2203 // Convert__Reg1_0__imm_95_2__UImm51_1
2204 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_addImmOperands, 2, CVT_Done },
2205 // Convert__regX0__regX0
2206 { CVT_regX0, 0, CVT_regX0, 0, CVT_Done },
2207 // Convert__Reg1_0__regX0
2208 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_Done },
2209 // Convert__regX0__BareSImm21Lsb01_0
2210 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2211 // Convert__regX1__BareSImm21Lsb01_0
2212 { CVT_regX1, 0, CVT_95_addImmOperands, 1, CVT_Done },
2213 // Convert__Reg1_0__BareSImm21Lsb01_1
2214 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2215 // Convert__regX1__Reg1_0__imm_95_0
2216 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2217 // Convert__Reg1_0__Reg1_1__imm_95_0
2218 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2219 // Convert__regX1__Reg1_0__SImm12LO1_1
2220 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2221 // Convert__regX1__Reg1_1__imm_95_0
2222 { CVT_regX1, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2223 // Convert__regX1__Reg1_2__SImm12LO1_0
2224 { CVT_regX1, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2225 // Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5
2226 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
2227 // Convert__regX0__Reg1_0__imm_95_0
2228 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2229 // Convert__regX0__Reg1_0__SImm12LO1_1
2230 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2231 // Convert__regX0__Reg1_1__imm_95_0
2232 { CVT_regX0, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2233 // Convert__regX0__Reg1_2__SImm12LO1_0
2234 { CVT_regX0, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2235 // Convert__Reg1_1__PseudoJumpSymbol1_0
2236 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
2237 // Convert__Reg1_0__ImmXLenLI_Restricted1_1
2238 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2239 // Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5
2240 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
2241 // Convert__GPRPairRV321_0__BareSymbol1_1
2242 { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2243 // Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1
2244 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2245 // Convert__Reg1_0__regX0__SImm12LO1_1
2246 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
2247 // Convert__Reg1_0__ImmXLenLI1_1
2248 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2249 // Convert__regX0__UImm201_0
2250 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2251 // Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3
2252 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Done },
2253 // Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2
2254 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_95_addImmOperands, 3, CVT_Done },
2255 // Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2
2256 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_95_addImmOperands, 3, CVT_Done },
2257 // Convert__Reg1_3__UImm91_1__UImm51_0
2258 { CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2259 // Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2
2260 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2261 // Convert__Reg1_0__Reg1_1__regX0
2262 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
2263 // Convert__Reg1_0__regX0__Reg1_1
2264 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
2265 // Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1
2266 { CVT_95_addRegOperands, 1, CVT_regX0_Pair, 0, CVT_95_addRegOperands, 2, CVT_Done },
2267 // Convert__Reg1_0__GPRPairRV321_1__Reg1_2
2268 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_Done },
2269 // Convert__Reg1_0__GPRPairRV321_1__UImm61_2
2270 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2271 // Convert__Reg1_0__SImm181_1
2272 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2273 // Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2
2274 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2275 // Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2
2276 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2277 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3
2278 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2279 // Convert__Reg1_0__SImm20Lsb0001_1
2280 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2281 // Convert__Reg1_0__SImm18Lsb01_1
2282 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2283 // Convert__Reg1_0__SImm19Lsb001_1
2284 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2285 // Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2286 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2287 // Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3
2288 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2289 // Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2
2290 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2291 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2
2292 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2293 // Convert__regX0__regX0__imm_95_0
2294 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done },
2295 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1
2296 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_Done },
2297 // Convert__regX0__regX0__regX5
2298 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX5, 0, CVT_Done },
2299 // Convert__regX0__regX0__regX2
2300 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX2, 0, CVT_Done },
2301 // Convert__regX0__regX0__regX3
2302 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX3, 0, CVT_Done },
2303 // Convert__regX0__regX0__regX4
2304 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX4, 0, CVT_Done },
2305 // Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair
2306 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_regX0_Pair, 0, CVT_Done },
2307 // Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2
2308 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_Done },
2309 // Convert__imm_95_1__imm_95_0
2310 { CVT_imm_95_1, 0, CVT_imm_95_0, 0, CVT_Done },
2311 // Convert__Reg1_0__SImm8PLI_B1_1
2312 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_8_GT_, 2, CVT_Done },
2313 // Convert__GPRPairRV321_0__SImm8PLI_B1_1
2314 { CVT_95_addRegOperands, 1, CVT_95_addSExtImmOperands_LT_8_GT_, 2, CVT_Done },
2315 // Convert__GPRPairRV321_0__SImm10PLI_H1_1
2316 { CVT_95_addRegOperands, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2317 // Convert__Reg1_0__SImm10PLI_H1_1
2318 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2319 // Convert__Reg1_0__SImm10PLI_W1_1
2320 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2321 // Convert__GPRPairRV321_0__SImm10PLUI1_1
2322 { CVT_95_addRegOperands, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2323 // Convert__Reg1_0__SImm10PLUI1_1
2324 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2325 // Convert__GPRPairRV321_0__Reg1_1__Reg1_2
2326 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2327 // Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1
2328 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2329 // Convert__GPRPairRV321_0__regX0_Pair__Reg1_1
2330 { CVT_95_addRegOperands, 1, CVT_regX0_Pair, 0, CVT_95_Reg, 2, CVT_Done },
2331 // Convert__Reg1_0__GPRPairRV321_1__UImm41_2
2332 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2333 // Convert__Reg1_0__GPRPairRV321_1__UImm51_2
2334 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2335 // Convert__Reg1_0__GPRPairRV321_1__imm_95_0
2336 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2337 // Convert__Reg1_0__GPRPairRV321_1__imm_95_8
2338 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_8, 0, CVT_Done },
2339 // Convert__Reg1_0__GPRPairRV321_1__imm_95_16
2340 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_16, 0, CVT_Done },
2341 // Convert__Reg1_2__SImm12Lsb000001_0
2342 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2343 // Convert__GPRPairRV321_0__GPRPairRV321_1
2344 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
2345 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2
2346 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2347 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2
2348 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2349 // Convert__Reg1_0__Reg1_1__UImm4Plus11_2
2350 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2351 // Convert__Reg1_0__Reg1_1__UImm5Plus11_2
2352 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2353 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2
2354 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2355 // Convert__GPRPairRV321_0__Reg1_1__regX0
2356 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
2357 // Convert__GPRPairRV321_0__regX0__Reg1_1
2358 { CVT_95_addRegOperands, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
2359 // Convert__GPRPairRV321_0__Reg1_1__UImm41_2
2360 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2361 // Convert__GPRPairRV321_0__Reg1_1__UImm51_2
2362 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2363 // Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2
2364 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2365 // Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2
2366 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2367 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1
2368 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2369 // Convert__regX0__Tie0_1_1__UImm5NonZero1_0
2370 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2371 // Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1
2372 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2373 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2
2374 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2375 // Convert__regX0__Tie0_1_1__imm_95_0
2376 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
2377 // Convert__UImm5Slist1_0
2378 { CVT_95_addImmOperands, 1, CVT_Done },
2379 // Convert__UImm101_0
2380 { CVT_95_addImmOperands, 1, CVT_Done },
2381 // Convert__RegListS01_0__NegStackAdj1_1
2382 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
2383 // Convert__Reg1_0__UImm51_1__Reg1_2
2384 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
2385 // Convert__Reg1_0__Tie0_1_1__BareSImm321_1
2386 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2387 // Convert__Reg1_0__Reg1_1__SImm261_2
2388 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2389 // Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2
2390 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2391 // Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2
2392 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2393 // Convert__BareSImm32Lsb01_0
2394 { CVT_95_addImmOperands, 1, CVT_Done },
2395 // Convert__Reg1_0__Reg1_3__SImm261_1
2396 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2397 // Convert__Reg1_0__BareSImm321_1
2398 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2399 // Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1
2400 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
2401 // Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3
2402 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2403 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3
2404 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2405 // Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3
2406 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2407 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2
2408 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2409 // Convert__Reg1_0__Reg1_3__UImm14Lsb001_1
2410 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2411 // Convert__Reg1_0__SImm20LI1_1
2412 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2413 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3
2414 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2415 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3
2416 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2417 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3
2418 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2419 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3
2420 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2421 // Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0
2422 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2423 // Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2
2424 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2425 // Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0
2426 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2427 // Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2
2428 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2429 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2
2430 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2431 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3
2432 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2433 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3
2434 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2435 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3
2436 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2437 // Convert__regX0__regX0__imm_95_1536
2438 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_1536, 0, CVT_Done },
2439 // Convert__regX0__Reg1_0__imm_95__MINUS_1280
2440 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1280, 0, CVT_Done },
2441 // Convert__regX0__Reg1_0__imm_95__MINUS_2048
2442 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_2048, 0, CVT_Done },
2443 // Convert__regX0__regX0__imm_95_1792
2444 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_1792, 0, CVT_Done },
2445 // Convert__regX0__Reg1_0__imm_95__MINUS_1792
2446 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1792, 0, CVT_Done },
2447 // Convert__UImm81_0
2448 { CVT_95_addImmOperands, 1, CVT_Done },
2449 // Convert__regX0__Reg1_0__imm_95__MINUS_1536
2450 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1536, 0, CVT_Done },
2451 // Convert__regX0__Reg1_0__imm_95__MINUS_1024
2452 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1024, 0, CVT_Done },
2453 // Convert__regX0__regX0__UImm101_0
2454 { CVT_regX0, 0, CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2455 // Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3
2456 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2457 // Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3
2458 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2459 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3
2460 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2461 // Convert__Reg1_0__Reg1_1__UImm111_2
2462 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2463 // Convert__Reg1_0__Reg1_3__UImm51_1
2464 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2465 // Convert__Reg1_0__Reg1_3__UImm41_1
2466 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2467 // Convert__Reg1_0__Reg1_3__UImm6Lsb01_1
2468 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2469 // Convert__Reg1_0__Reg1_3__UImm5Lsb01_1
2470 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2471 // Convert__Reg1_0__imm_95_3072__regX0
2472 { CVT_95_Reg, 1, CVT_imm_95_3072, 0, CVT_regX0, 0, CVT_Done },
2473 // Convert__Reg1_0__imm_95_3200__regX0
2474 { CVT_95_Reg, 1, CVT_imm_95_3200, 0, CVT_regX0, 0, CVT_Done },
2475 // Convert__Reg1_0__imm_95_3074__regX0
2476 { CVT_95_Reg, 1, CVT_imm_95_3074, 0, CVT_regX0, 0, CVT_Done },
2477 // Convert__Reg1_0__imm_95_3202__regX0
2478 { CVT_95_Reg, 1, CVT_imm_95_3202, 0, CVT_regX0, 0, CVT_Done },
2479 // Convert__Reg1_0__imm_95_3073__regX0
2480 { CVT_95_Reg, 1, CVT_imm_95_3073, 0, CVT_regX0, 0, CVT_Done },
2481 // Convert__Reg1_0__imm_95_3201__regX0
2482 { CVT_95_Reg, 1, CVT_imm_95_3201, 0, CVT_regX0, 0, CVT_Done },
2483 // Convert__regX0__regX1__imm_95_0
2484 { CVT_regX0, 0, CVT_regX1, 0, CVT_imm_95_0, 0, CVT_Done },
2485 // Convert__Reg1_0__Reg1_1__UImm6Plus11_2
2486 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2487 // Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1
2488 { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2489 // Convert__Reg1_0__Reg1_1__imm_95_1
2490 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
2491 // Convert__regX0
2492 { CVT_regX0, 0, CVT_Done },
2493 // Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3
2494 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2495 // Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3
2496 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2497 // Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3
2498 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2499 // Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3
2500 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2501 // Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3
2502 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2503 // Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3
2504 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2505 // Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3
2506 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2507 // Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3
2508 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
2509 // Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3
2510 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2511 // Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3
2512 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2513 // Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3
2514 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2515 // Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3
2516 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2517 // Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3
2518 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_Done },
2519 // Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3
2520 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2521 // Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3
2522 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2523 // Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3
2524 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2525 // Convert__Reg1_0__Reg1_1__XSfmmVType1_2
2526 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2527 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3
2528 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addSMTVTypeOperand_95_defaultSMTVType, 4, CVT_Done },
2529 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5
2530 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addSMTVTypeOperand_95_defaultSMTVType, 6, CVT_Done },
2531 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5
2532 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addSMTVTypeOperand_95_defaultSMTVType, 6, CVT_Done },
2533 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3
2534 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addSMTVTypeOperand_95_defaultSMTVType, 4, CVT_Done },
2535 // Convert__Reg1_0__Reg1_1__UImm7EqXLen1_2
2536 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2537 // Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5
2538 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2539 // Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6
2540 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
2541 // Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6
2542 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
2543 // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5
2544 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2545 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2546 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2547 // Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3
2548 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
2549 // Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3
2550 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 4, CVT_Done },
2551 // Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3
2552 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2553 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3
2554 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 4, CVT_Done },
2555 // Convert__Reg1_0__Reg1_1__Reg1_1__reg0
2556 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_reg0, 0, CVT_Done },
2557 // Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2
2558 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2559 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4
2560 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addRegOperands_95_defaultMaskRegOp, 5, CVT_Done },
2561 // Convert__Reg1_0__RVVMaskRegOpOperand1_1
2562 { CVT_95_Reg, 1, CVT_95_addRegOperands_95_defaultMaskRegOp, 2, CVT_Done },
2563 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3
2564 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2565 // Convert__Reg1_0__Reg1_1__SImm51_2
2566 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2567 // Convert__Reg1_0__Reg1_0__Reg1_0
2568 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_Done },
2569 // Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3
2570 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2571 // Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2572 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2573 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3
2574 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2575 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4
2576 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addRegOperands_95_defaultMaskRegOp, 5, CVT_Done },
2577 // Convert__Reg1_0__SImm51_1
2578 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2579 // Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3
2580 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2581 // Convert__Reg1_0__Reg1_1__regX0__reg0
2582 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_reg0, 0, CVT_Done },
2583 // Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2
2584 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2585 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0
2586 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_reg0, 0, CVT_Done },
2587 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2
2588 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2589 // Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3
2590 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2591 // Convert__Reg1_0__UImm51_1__VTypeI101_2
2592 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2593 // Convert__Reg1_0__Reg1_1__VTypeI111_2
2594 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2595 // Convert__GPRPairRV321_0__Reg1_1__UImm61_2
2596 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2597 // Convert__Reg1_0__Reg1_1__YBNDSWImm1_2
2598 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2599 // Convert__Reg1_0__Reg1_1__imm_95_64
2600 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_64, 0, CVT_Done },
2601 // Convert__Reg1_0__Reg1_1__imm_95_32
2602 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_32, 0, CVT_Done },
2603 // Convert__Reg1_0__Reg1_1__imm_95_255
2604 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_255, 0, CVT_Done },
2605};
2606
2607void RISCVAsmParser::
2608convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2609 const OperandVector &Operands,
2610 const SmallBitVector &OptionalOperandsMask,
2611 ArrayRef<unsigned> DefaultsOffset) {
2612 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2613 const uint8_t *Converter = ConversionTable[Kind];
2614 Inst.setOpcode(Opcode);
2615 for (const uint8_t *p = Converter; *p; p += 2) {
2616 unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
2617 switch (*p) {
2618 default: llvm_unreachable("invalid conversion entry!");
2619 case CVT_Reg:
2620 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2621 break;
2622 case CVT_Tied: {
2623 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
2624 std::begin(TiedAsmOperandTable)) &&
2625 "Tied operand not found");
2626 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
2627 if (TiedResOpnd != (uint8_t)-1)
2628 Inst.addOperand(Inst.getOperand(TiedResOpnd));
2629 break;
2630 }
2631 case CVT_95_addImmOperands:
2632 static_cast<RISCVOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2633 break;
2634 case CVT_95_addRegOperands:
2635 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2636 break;
2637 case CVT_imm_95_0:
2638 Inst.addOperand(MCOperand::createImm(0));
2639 break;
2640 case CVT_95_Reg:
2641 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2642 break;
2643 case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
2644 if (OptionalOperandsMask[*(p + 1)]) {
2645 defaultFRMArgOp()->addFRMArgOperands(Inst, 1);
2646 } else {
2647 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2648 }
2649 break;
2650 case CVT_regX0:
2651 Inst.addOperand(MCOperand::createReg(RISCV::X0));
2652 break;
2653 case CVT_regX1:
2654 Inst.addOperand(MCOperand::createReg(RISCV::X1));
2655 break;
2656 case CVT_regX5:
2657 Inst.addOperand(MCOperand::createReg(RISCV::X5));
2658 break;
2659 case CVT_regX2:
2660 Inst.addOperand(MCOperand::createReg(RISCV::X2));
2661 break;
2662 case CVT_regX3:
2663 Inst.addOperand(MCOperand::createReg(RISCV::X3));
2664 break;
2665 case CVT_regX4:
2666 Inst.addOperand(MCOperand::createReg(RISCV::X4));
2667 break;
2668 case CVT_95_addRegListOperands:
2669 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
2670 break;
2671 case CVT_95_addStackAdjOperands:
2672 static_cast<RISCVOperand &>(*Operands[OpIdx]).addStackAdjOperands(Inst, 1);
2673 break;
2674 case CVT_95_addCSRSystemRegisterOperands:
2675 static_cast<RISCVOperand &>(*Operands[OpIdx]).addCSRSystemRegisterOperands(Inst, 1);
2676 break;
2677 case CVT_95_addRegRegOperands:
2678 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegRegOperands(Inst, 2);
2679 break;
2680 case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
2681 if (OptionalOperandsMask[*(p + 1)]) {
2682 defaultFRMArgLegacyOp()->addFRMArgOperands(Inst, 1);
2683 } else {
2684 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2685 }
2686 break;
2687 case CVT_95_addFRMArgOperands:
2688 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2689 break;
2690 case CVT_imm_95_15:
2691 Inst.addOperand(MCOperand::createImm(15));
2692 break;
2693 case CVT_95_addFenceArgOperands:
2694 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFenceArgOperands(Inst, 1);
2695 break;
2696 case CVT_95_addFPImmOperands:
2697 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
2698 break;
2699 case CVT_imm_95_3:
2700 Inst.addOperand(MCOperand::createImm(3));
2701 break;
2702 case CVT_imm_95_1:
2703 Inst.addOperand(MCOperand::createImm(1));
2704 break;
2705 case CVT_imm_95_2:
2706 Inst.addOperand(MCOperand::createImm(2));
2707 break;
2708 case CVT_regX0_Pair:
2709 Inst.addOperand(MCOperand::createReg(RISCV::X0_Pair));
2710 break;
2711 case CVT_95_addRegOperands_95_defaultMaskRegOp:
2712 if (OptionalOperandsMask[*(p + 1)]) {
2713 defaultMaskRegOp()->addRegOperands(Inst, 1);
2714 } else {
2715 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2716 }
2717 break;
2718 case CVT_imm_95__MINUS_1:
2719 Inst.addOperand(MCOperand::createImm(-1));
2720 break;
2721 case CVT_95_addSExtImmOperands_LT_8_GT_:
2722 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSExtImmOperands<8>(Inst, 1);
2723 break;
2724 case CVT_95_addSExtImmOperands_LT_10_GT_:
2725 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSExtImmOperands<10>(Inst, 1);
2726 break;
2727 case CVT_imm_95_8:
2728 Inst.addOperand(MCOperand::createImm(8));
2729 break;
2730 case CVT_imm_95_16:
2731 Inst.addOperand(MCOperand::createImm(16));
2732 break;
2733 case CVT_imm_95_1536:
2734 Inst.addOperand(MCOperand::createImm(1536));
2735 break;
2736 case CVT_imm_95__MINUS_1280:
2737 Inst.addOperand(MCOperand::createImm(-1280));
2738 break;
2739 case CVT_imm_95__MINUS_2048:
2740 Inst.addOperand(MCOperand::createImm(-2048));
2741 break;
2742 case CVT_imm_95_1792:
2743 Inst.addOperand(MCOperand::createImm(1792));
2744 break;
2745 case CVT_imm_95__MINUS_1792:
2746 Inst.addOperand(MCOperand::createImm(-1792));
2747 break;
2748 case CVT_imm_95__MINUS_1536:
2749 Inst.addOperand(MCOperand::createImm(-1536));
2750 break;
2751 case CVT_imm_95__MINUS_1024:
2752 Inst.addOperand(MCOperand::createImm(-1024));
2753 break;
2754 case CVT_imm_95_3072:
2755 Inst.addOperand(MCOperand::createImm(3072));
2756 break;
2757 case CVT_imm_95_3200:
2758 Inst.addOperand(MCOperand::createImm(3200));
2759 break;
2760 case CVT_imm_95_3074:
2761 Inst.addOperand(MCOperand::createImm(3074));
2762 break;
2763 case CVT_imm_95_3202:
2764 Inst.addOperand(MCOperand::createImm(3202));
2765 break;
2766 case CVT_imm_95_3073:
2767 Inst.addOperand(MCOperand::createImm(3073));
2768 break;
2769 case CVT_imm_95_3201:
2770 Inst.addOperand(MCOperand::createImm(3201));
2771 break;
2772 case CVT_95_addVTypeIOperands:
2773 static_cast<RISCVOperand &>(*Operands[OpIdx]).addVTypeIOperands(Inst, 1);
2774 break;
2775 case CVT_95_addSMTVTypeOperand_95_defaultSMTVType:
2776 if (OptionalOperandsMask[*(p + 1)]) {
2777 defaultSMTVType()->addSMTVTypeOperand(Inst, 1);
2778 } else {
2779 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSMTVTypeOperand(Inst, 1);
2780 }
2781 break;
2782 case CVT_reg0:
2783 Inst.addOperand(MCOperand::createReg(0));
2784 break;
2785 case CVT_imm_95_64:
2786 Inst.addOperand(MCOperand::createImm(64));
2787 break;
2788 case CVT_imm_95_32:
2789 Inst.addOperand(MCOperand::createImm(32));
2790 break;
2791 case CVT_imm_95_255:
2792 Inst.addOperand(MCOperand::createImm(255));
2793 break;
2794 }
2795 }
2796}
2797
2798void RISCVAsmParser::
2799convertToMapAndConstraints(unsigned Kind,
2800 const OperandVector &Operands) {
2801 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2802 unsigned NumMCOperands = 0;
2803 const uint8_t *Converter = ConversionTable[Kind];
2804 for (const uint8_t *p = Converter; *p; p += 2) {
2805 switch (*p) {
2806 default: llvm_unreachable("invalid conversion entry!");
2807 case CVT_Reg:
2808 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2809 Operands[*(p + 1)]->setConstraint("r");
2810 ++NumMCOperands;
2811 break;
2812 case CVT_Tied:
2813 ++NumMCOperands;
2814 break;
2815 case CVT_95_addImmOperands:
2816 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2817 Operands[*(p + 1)]->setConstraint("m");
2818 NumMCOperands += 1;
2819 break;
2820 case CVT_95_addRegOperands:
2821 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2822 Operands[*(p + 1)]->setConstraint("m");
2823 NumMCOperands += 1;
2824 break;
2825 case CVT_imm_95_0:
2826 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2827 Operands[*(p + 1)]->setConstraint("");
2828 ++NumMCOperands;
2829 break;
2830 case CVT_95_Reg:
2831 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2832 Operands[*(p + 1)]->setConstraint("r");
2833 NumMCOperands += 1;
2834 break;
2835 case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
2836 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2837 Operands[*(p + 1)]->setConstraint("m");
2838 NumMCOperands += 1;
2839 break;
2840 case CVT_regX0:
2841 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2842 Operands[*(p + 1)]->setConstraint("m");
2843 ++NumMCOperands;
2844 break;
2845 case CVT_regX1:
2846 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2847 Operands[*(p + 1)]->setConstraint("m");
2848 ++NumMCOperands;
2849 break;
2850 case CVT_regX5:
2851 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2852 Operands[*(p + 1)]->setConstraint("m");
2853 ++NumMCOperands;
2854 break;
2855 case CVT_regX2:
2856 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2857 Operands[*(p + 1)]->setConstraint("m");
2858 ++NumMCOperands;
2859 break;
2860 case CVT_regX3:
2861 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2862 Operands[*(p + 1)]->setConstraint("m");
2863 ++NumMCOperands;
2864 break;
2865 case CVT_regX4:
2866 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2867 Operands[*(p + 1)]->setConstraint("m");
2868 ++NumMCOperands;
2869 break;
2870 case CVT_95_addRegListOperands:
2871 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2872 Operands[*(p + 1)]->setConstraint("m");
2873 NumMCOperands += 1;
2874 break;
2875 case CVT_95_addStackAdjOperands:
2876 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2877 Operands[*(p + 1)]->setConstraint("m");
2878 NumMCOperands += 1;
2879 break;
2880 case CVT_95_addCSRSystemRegisterOperands:
2881 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2882 Operands[*(p + 1)]->setConstraint("m");
2883 NumMCOperands += 1;
2884 break;
2885 case CVT_95_addRegRegOperands:
2886 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2887 Operands[*(p + 1)]->setConstraint("m");
2888 NumMCOperands += 2;
2889 break;
2890 case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
2891 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2892 Operands[*(p + 1)]->setConstraint("m");
2893 NumMCOperands += 1;
2894 break;
2895 case CVT_95_addFRMArgOperands:
2896 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2897 Operands[*(p + 1)]->setConstraint("m");
2898 NumMCOperands += 1;
2899 break;
2900 case CVT_imm_95_15:
2901 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2902 Operands[*(p + 1)]->setConstraint("");
2903 ++NumMCOperands;
2904 break;
2905 case CVT_95_addFenceArgOperands:
2906 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2907 Operands[*(p + 1)]->setConstraint("m");
2908 NumMCOperands += 1;
2909 break;
2910 case CVT_95_addFPImmOperands:
2911 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2912 Operands[*(p + 1)]->setConstraint("m");
2913 NumMCOperands += 1;
2914 break;
2915 case CVT_imm_95_3:
2916 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2917 Operands[*(p + 1)]->setConstraint("");
2918 ++NumMCOperands;
2919 break;
2920 case CVT_imm_95_1:
2921 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2922 Operands[*(p + 1)]->setConstraint("");
2923 ++NumMCOperands;
2924 break;
2925 case CVT_imm_95_2:
2926 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2927 Operands[*(p + 1)]->setConstraint("");
2928 ++NumMCOperands;
2929 break;
2930 case CVT_regX0_Pair:
2931 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2932 Operands[*(p + 1)]->setConstraint("m");
2933 ++NumMCOperands;
2934 break;
2935 case CVT_95_addRegOperands_95_defaultMaskRegOp:
2936 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2937 Operands[*(p + 1)]->setConstraint("m");
2938 NumMCOperands += 1;
2939 break;
2940 case CVT_imm_95__MINUS_1:
2941 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2942 Operands[*(p + 1)]->setConstraint("");
2943 ++NumMCOperands;
2944 break;
2945 case CVT_95_addSExtImmOperands_LT_8_GT_:
2946 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2947 Operands[*(p + 1)]->setConstraint("m");
2948 NumMCOperands += 1;
2949 break;
2950 case CVT_95_addSExtImmOperands_LT_10_GT_:
2951 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2952 Operands[*(p + 1)]->setConstraint("m");
2953 NumMCOperands += 1;
2954 break;
2955 case CVT_imm_95_8:
2956 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2957 Operands[*(p + 1)]->setConstraint("");
2958 ++NumMCOperands;
2959 break;
2960 case CVT_imm_95_16:
2961 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2962 Operands[*(p + 1)]->setConstraint("");
2963 ++NumMCOperands;
2964 break;
2965 case CVT_imm_95_1536:
2966 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2967 Operands[*(p + 1)]->setConstraint("");
2968 ++NumMCOperands;
2969 break;
2970 case CVT_imm_95__MINUS_1280:
2971 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2972 Operands[*(p + 1)]->setConstraint("");
2973 ++NumMCOperands;
2974 break;
2975 case CVT_imm_95__MINUS_2048:
2976 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2977 Operands[*(p + 1)]->setConstraint("");
2978 ++NumMCOperands;
2979 break;
2980 case CVT_imm_95_1792:
2981 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2982 Operands[*(p + 1)]->setConstraint("");
2983 ++NumMCOperands;
2984 break;
2985 case CVT_imm_95__MINUS_1792:
2986 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2987 Operands[*(p + 1)]->setConstraint("");
2988 ++NumMCOperands;
2989 break;
2990 case CVT_imm_95__MINUS_1536:
2991 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2992 Operands[*(p + 1)]->setConstraint("");
2993 ++NumMCOperands;
2994 break;
2995 case CVT_imm_95__MINUS_1024:
2996 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2997 Operands[*(p + 1)]->setConstraint("");
2998 ++NumMCOperands;
2999 break;
3000 case CVT_imm_95_3072:
3001 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3002 Operands[*(p + 1)]->setConstraint("");
3003 ++NumMCOperands;
3004 break;
3005 case CVT_imm_95_3200:
3006 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3007 Operands[*(p + 1)]->setConstraint("");
3008 ++NumMCOperands;
3009 break;
3010 case CVT_imm_95_3074:
3011 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3012 Operands[*(p + 1)]->setConstraint("");
3013 ++NumMCOperands;
3014 break;
3015 case CVT_imm_95_3202:
3016 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3017 Operands[*(p + 1)]->setConstraint("");
3018 ++NumMCOperands;
3019 break;
3020 case CVT_imm_95_3073:
3021 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3022 Operands[*(p + 1)]->setConstraint("");
3023 ++NumMCOperands;
3024 break;
3025 case CVT_imm_95_3201:
3026 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3027 Operands[*(p + 1)]->setConstraint("");
3028 ++NumMCOperands;
3029 break;
3030 case CVT_95_addVTypeIOperands:
3031 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3032 Operands[*(p + 1)]->setConstraint("m");
3033 NumMCOperands += 1;
3034 break;
3035 case CVT_95_addSMTVTypeOperand_95_defaultSMTVType:
3036 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3037 Operands[*(p + 1)]->setConstraint("m");
3038 NumMCOperands += 1;
3039 break;
3040 case CVT_reg0:
3041 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3042 Operands[*(p + 1)]->setConstraint("m");
3043 ++NumMCOperands;
3044 break;
3045 case CVT_imm_95_64:
3046 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3047 Operands[*(p + 1)]->setConstraint("");
3048 ++NumMCOperands;
3049 break;
3050 case CVT_imm_95_32:
3051 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3052 Operands[*(p + 1)]->setConstraint("");
3053 ++NumMCOperands;
3054 break;
3055 case CVT_imm_95_255:
3056 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3057 Operands[*(p + 1)]->setConstraint("");
3058 ++NumMCOperands;
3059 break;
3060 }
3061 }
3062}
3063
3064namespace {
3065
3066/// MatchClassKind - The kinds of classes which participate in
3067/// instruction matching.
3068enum MatchClassKind {
3069 InvalidMatchClass = 0,
3070 OptionalMatchClass = 1,
3071 MCK__40_, // '('
3072 MCK__41_, // ')'
3073 MCK_LAST_TOKEN = MCK__41_,
3074 MCK_Reg144, // derived register class
3075 MCK_Reg141, // derived register class
3076 MCK_Reg138, // derived register class
3077 MCK_Reg135, // derived register class
3078 MCK_Reg132, // derived register class
3079 MCK_Reg129, // derived register class
3080 MCK_Reg126, // derived register class
3081 MCK_Reg123, // derived register class
3082 MCK_Reg120, // derived register class
3083 MCK_Reg117, // derived register class
3084 MCK_Reg114, // derived register class
3085 MCK_Reg100, // derived register class
3086 MCK_Reg97, // derived register class
3087 MCK_Reg94, // derived register class
3088 MCK_Reg75, // derived register class
3089 MCK_Reg70, // derived register class
3090 MCK_Reg67, // derived register class
3091 MCK_Reg64, // derived register class
3092 MCK_Reg61, // derived register class
3093 MCK_Reg56, // derived register class
3094 MCK_Reg47, // derived register class
3095 MCK_Reg46, // derived register class
3096 MCK_Reg40, // derived register class
3097 MCK_Reg35, // derived register class
3098 MCK_GPRF16X0, // register class 'GPRF16X0'
3099 MCK_GPRF32X0, // register class 'GPRF32X0'
3100 MCK_GPRX0, // register class 'GPRX0'
3101 MCK_GPRX1, // register class 'GPRX1'
3102 MCK_GPRX5, // register class 'GPRX5'
3103 MCK_GPRX7, // register class 'GPRX7'
3104 MCK_MR0, // register class 'MR0'
3105 MCK_SP, // register class 'SP'
3106 MCK_VMV0, // register class 'VMV0'
3107 MCK_anonymous_14663, // register class 'anonymous_14663'
3108 MCK_Reg57, // derived register class
3109 MCK_Reg45, // derived register class
3110 MCK_Reg31, // derived register class
3111 MCK_GPRX1X5, // register class 'GPRX1X5'
3112 MCK_Reg80, // derived register class
3113 MCK_VCSR, // register class 'VCSR'
3114 MCK_VRM8NoV0, // register class 'VRM8NoV0'
3115 MCK_Reg79, // derived register class
3116 MCK_GPRPairC, // register class 'GPRPairC'
3117 MCK_TRM4, // register class 'TRM4'
3118 MCK_VRM8, // register class 'VRM8'
3119 MCK_Reg81, // derived register class
3120 MCK_Reg82, // derived register class
3121 MCK_Reg73, // derived register class
3122 MCK_Reg60, // derived register class
3123 MCK_Reg34, // derived register class
3124 MCK_VRN2M4NoV0, // register class 'VRN2M4NoV0'
3125 MCK_Reg74, // derived register class
3126 MCK_VRM4NoV0, // register class 'VRM4NoV0'
3127 MCK_VRN2M4, // register class 'VRN2M4'
3128 MCK_Reg109, // derived register class
3129 MCK_Reg90, // derived register class
3130 MCK_Reg59, // derived register class
3131 MCK_Reg58, // derived register class
3132 MCK_FPR16C, // register class 'FPR16C'
3133 MCK_FPR32C, // register class 'FPR32C'
3134 MCK_FPR64C, // register class 'FPR64C'
3135 MCK_GPRC, // register class 'GPRC'
3136 MCK_GPRF16C, // register class 'GPRF16C'
3137 MCK_GPRF32C, // register class 'GPRF32C'
3138 MCK_MR, // register class 'MR'
3139 MCK_SR07, // register class 'SR07'
3140 MCK_TRM2, // register class 'TRM2'
3141 MCK_VRM4, // register class 'VRM4'
3142 MCK_Reg77, // derived register class
3143 MCK_Reg78, // derived register class
3144 MCK_Reg71, // derived register class
3145 MCK_Reg54, // derived register class
3146 MCK_Reg28, // derived register class
3147 MCK_VRN4M2NoV0, // register class 'VRN4M2NoV0'
3148 MCK_Reg72, // derived register class
3149 MCK_Reg68, // derived register class
3150 MCK_Reg55, // derived register class
3151 MCK_Reg50, // derived register class
3152 MCK_Reg24, // derived register class
3153 MCK_GPRTCNonX7, // register class 'GPRTCNonX7'
3154 MCK_VRN3M2NoV0, // register class 'VRN3M2NoV0'
3155 MCK_VRN4M2, // register class 'VRN4M2'
3156 MCK_Reg69, // derived register class
3157 MCK_Reg65, // derived register class
3158 MCK_Reg51, // derived register class
3159 MCK_GPRTC, // register class 'GPRTC'
3160 MCK_VRN2M2NoV0, // register class 'VRN2M2NoV0'
3161 MCK_VRN3M2, // register class 'VRN3M2'
3162 MCK_Reg63, // derived register class
3163 MCK_GPRPairNoX0, // register class 'GPRPairNoX0'
3164 MCK_VRM2NoV0, // register class 'VRM2NoV0'
3165 MCK_VRN2M2, // register class 'VRN2M2'
3166 MCK_GPRPair, // register class 'GPRPair'
3167 MCK_TR, // register class 'TR'
3168 MCK_VRM2, // register class 'VRM2'
3169 MCK_Reg52, // derived register class
3170 MCK_Reg26, // derived register class
3171 MCK_VRN8M1NoV0, // register class 'VRN8M1NoV0'
3172 MCK_Reg53, // derived register class
3173 MCK_Reg48, // derived register class
3174 MCK_Reg22, // derived register class
3175 MCK_GPRJALRNonX7, // register class 'GPRJALRNonX7'
3176 MCK_VRN7M1NoV0, // register class 'VRN7M1NoV0'
3177 MCK_VRN8M1, // register class 'VRN8M1'
3178 MCK_Reg49, // derived register class
3179 MCK_GPRJALR, // register class 'GPRJALR'
3180 MCK_VRN6M1NoV0, // register class 'VRN6M1NoV0'
3181 MCK_VRN7M1, // register class 'VRN7M1'
3182 MCK_VRN5M1NoV0, // register class 'VRN5M1NoV0'
3183 MCK_VRN6M1, // register class 'VRN6M1'
3184 MCK_VRN4M1NoV0, // register class 'VRN4M1NoV0'
3185 MCK_VRN5M1, // register class 'VRN5M1'
3186 MCK_Reg43, // derived register class
3187 MCK_Reg17, // derived register class
3188 MCK_VRN3M1NoV0, // register class 'VRN3M1NoV0'
3189 MCK_VRN4M1, // register class 'VRN4M1'
3190 MCK_Reg44, // derived register class
3191 MCK_Reg41, // derived register class
3192 MCK_Reg38, // derived register class
3193 MCK_Reg15, // derived register class
3194 MCK_Reg12, // derived register class
3195 MCK_GPRNoX0X2, // register class 'GPRNoX0X2'
3196 MCK_VRN2M1NoV0, // register class 'VRN2M1NoV0'
3197 MCK_VRN3M1, // register class 'VRN3M1'
3198 MCK_Reg42, // derived register class
3199 MCK_Reg39, // derived register class
3200 MCK_Reg36, // derived register class
3201 MCK_GPRF16NoX0, // register class 'GPRF16NoX0'
3202 MCK_GPRF32NoX0, // register class 'GPRF32NoX0'
3203 MCK_GPRNoX0, // register class 'GPRNoX0'
3204 MCK_GPRNoX2, // register class 'GPRNoX2'
3205 MCK_GPRNoX31, // register class 'GPRNoX31'
3206 MCK_VRN2M1, // register class 'VRN2M1'
3207 MCK_VRNoV0, // register class 'VRNoV0,ZZZ_VMNoV0,ZZZ_VRMF2NoV0,ZZZ_VRMF4NoV0,ZZZ_VRMF8NoV0'
3208 MCK_FPR128, // register class 'FPR128'
3209 MCK_FPR16, // register class 'FPR16'
3210 MCK_FPR256, // register class 'FPR256'
3211 MCK_FPR32, // register class 'FPR32'
3212 MCK_FPR64, // register class 'FPR64'
3213 MCK_GPR, // register class 'GPR'
3214 MCK_GPRF16, // register class 'GPRF16'
3215 MCK_GPRF32, // register class 'GPRF32'
3216 MCK_VR, // register class 'VR,ZZZ_VM,ZZZ_VRMF2,ZZZ_VRMF4,ZZZ_VRMF8'
3217 MCK_YGPR, // register class 'YGPR'
3218 MCK_GPRAll, // register class 'GPRAll'
3219 MCK_LAST_REGISTER = MCK_GPRAll,
3220 MCK_AnyRegCOperand, // user defined class 'AnyRegCOperand'
3221 MCK_AnyRegOperand, // user defined class 'AnyRegOperand'
3222 MCK_BareSymbol, // user defined class 'BareSymbol'
3223 MCK_BareSymbolQC_E_LI, // user defined class 'BareSymbolQC_E_LI'
3224 MCK_CLUIImm, // user defined class 'CLUIImmAsmOperand'
3225 MCK_CSRSystemRegister, // user defined class 'CSRSystemRegister'
3226 MCK_RegReg, // user defined class 'CVrrAsmOperand'
3227 MCK_CallSymbol, // user defined class 'CallSymbol'
3228 MCK_FRMArg, // user defined class 'FRMArg'
3229 MCK_FRMArgLegacy, // user defined class 'FRMArgLegacy'
3230 MCK_FenceArg, // user defined class 'FenceArg'
3231 MCK_GPRAsFPR16, // user defined class 'GPRAsFPR16'
3232 MCK_GPRAsFPR32, // user defined class 'GPRAsFPR32'
3233 MCK_GPRF64AsFPR, // user defined class 'GPRF64AsFPR'
3234 MCK_GPRPairAsFPR, // user defined class 'GPRPairAsFPR'
3235 MCK_GPRPairCRV32, // user defined class 'GPRPairCRV32Operand'
3236 MCK_GPRPairNoX0RV32, // user defined class 'GPRPairNoX0RV32Operand'
3237 MCK_GPRPairRV32, // user defined class 'GPRPairRV32Operand'
3238 MCK_GPRPairRV64, // user defined class 'GPRPairRV64Operand'
3239 MCK_Imm, // user defined class 'ImmAsmOperand'
3240 MCK_ImmFour, // user defined class 'ImmFourAsmOperand'
3241 MCK_ImmThree, // user defined class 'ImmThreeAsmOperand'
3242 MCK_ImmZero, // user defined class 'ImmZeroAsmOperand'
3243 MCK_InsnCDirectiveOpcode, // user defined class 'InsnCDirectiveOpcode'
3244 MCK_InsnDirectiveOpcode, // user defined class 'InsnDirectiveOpcode'
3245 MCK_LoadFPImm, // user defined class 'LoadFPImmOperand'
3246 MCK_NegStackAdj, // user defined class 'NegStackAdjAsmOperand'
3247 MCK_PseudoJumpSymbol, // user defined class 'PseudoJumpSymbol'
3248 MCK_QCAccessSymbol, // user defined class 'QCAccessSymbol'
3249 MCK_RTZArg, // user defined class 'RTZArg'
3250 MCK_RegList, // user defined class 'RegListAsmOperand'
3251 MCK_RegListS0, // user defined class 'RegListS0AsmOperand'
3252 MCK_RnumArg, // user defined class 'RnumArg'
3253 MCK_SImm10PLI_H, // user defined class 'SImm10PLI_HAsmOperand'
3254 MCK_SImm10PLI_W, // user defined class 'SImm10PLI_WAsmOperand'
3255 MCK_SImm10PLUI, // user defined class 'SImm10PLUIAsmOperand'
3256 MCK_SImm8PLI_B, // user defined class 'SImm8PLI_BAsmOperand'
3257 MCK_SMTI8, // user defined class 'SMTI8'
3258 MCK_SMTVType, // user defined class 'SMTVType'
3259 MCK_BareSImm21Lsb0, // user defined class 'Simm21Lsb0JALAsmOperand'
3260 MCK_StackAdj, // user defined class 'StackAdjAsmOperand'
3261 MCK_TLSDESCCallSymbol, // user defined class 'TLSDESCCallSymbol'
3262 MCK_TPRelAddSymbol, // user defined class 'TPRelAddSymbol'
3263 MCK_TileLambda, // user defined class 'TileLambdaAsmOperand'
3264 MCK_UImmLog2XLen, // user defined class 'UImmLog2XLenAsmOperand'
3265 MCK_UImmLog2XLenNonZero, // user defined class 'UImmLog2XLenNonZeroAsmOperand'
3266 MCK_RVVMaskRegOpOperand, // user defined class 'VMaskAsmOperand'
3267 MCK_RVVMaskCarryInRegOpOperand, // user defined class 'VMaskCarryInAsmOperand'
3268 MCK_RVVScaleRegOpOperand, // user defined class 'VScaleAsmOperand'
3269 MCK_XSfmmVType, // user defined class 'XSfmmVTypeAsmOperand'
3270 MCK_YBNDSWImm, // user defined class 'YBNDSWImmOperand'
3271 MCK_ZeroOffsetMemOpOperand, // user defined class 'ZeroOffsetMemOpOperand'
3272 MCK_UImm1, // user defined class 'anonymous_15054'
3273 MCK_UImm2, // user defined class 'anonymous_15055'
3274 MCK_UImm3, // user defined class 'anonymous_15056'
3275 MCK_UImm4, // user defined class 'anonymous_15057'
3276 MCK_UImm5, // user defined class 'anonymous_15058'
3277 MCK_UImm6, // user defined class 'anonymous_15059'
3278 MCK_UImm7, // user defined class 'anonymous_15060'
3279 MCK_UImm8, // user defined class 'anonymous_15061'
3280 MCK_UImm16, // user defined class 'anonymous_15062'
3281 MCK_UImm32, // user defined class 'anonymous_15063'
3282 MCK_UImm48, // user defined class 'anonymous_15064'
3283 MCK_UImm64, // user defined class 'anonymous_15065'
3284 MCK_SImm12, // user defined class 'anonymous_15066'
3285 MCK_SImm12LO, // user defined class 'anonymous_15067'
3286 MCK_BareSImm13Lsb0, // user defined class 'anonymous_15068'
3287 MCK_UImm20, // user defined class 'anonymous_15069'
3288 MCK_UImm20LUI, // user defined class 'anonymous_15070'
3289 MCK_UImm20AUIPC, // user defined class 'anonymous_15071'
3290 MCK_ImmXLenLI, // user defined class 'anonymous_15072'
3291 MCK_ImmXLenLI_Restricted, // user defined class 'anonymous_15073'
3292 MCK_SImm12Lsb00000, // user defined class 'anonymous_16047'
3293 MCK_Imm5Zibi, // user defined class 'anonymous_16059'
3294 MCK_VTypeI10, // user defined class 'anonymous_16750'
3295 MCK_VTypeI11, // user defined class 'anonymous_16751'
3296 MCK_SImm5, // user defined class 'anonymous_16752'
3297 MCK_SImm5Plus1, // user defined class 'anonymous_16753'
3298 MCK_UImm4Plus1, // user defined class 'anonymous_61312'
3299 MCK_UImm5Plus1, // user defined class 'anonymous_61313'
3300 MCK_UImm6Plus1, // user defined class 'anonymous_61314'
3301 MCK_SImm6, // user defined class 'anonymous_61819'
3302 MCK_SImm6NonZero, // user defined class 'anonymous_61820'
3303 MCK_UImm7Lsb00, // user defined class 'anonymous_61821'
3304 MCK_UImm8Lsb00, // user defined class 'anonymous_61822'
3305 MCK_UImm8Lsb000, // user defined class 'anonymous_61823'
3306 MCK_BareSImm9Lsb0, // user defined class 'anonymous_61824'
3307 MCK_UImm9Lsb000, // user defined class 'anonymous_61825'
3308 MCK_UImm10Lsb00NonZero, // user defined class 'anonymous_61826'
3309 MCK_SImm10Lsb0000NonZero, // user defined class 'anonymous_61827'
3310 MCK_BareSImm12Lsb0, // user defined class 'anonymous_61828'
3311 MCK_UImm2Lsb0, // user defined class 'anonymous_61920'
3312 MCK_UImm8GE32, // user defined class 'anonymous_61921'
3313 MCK_UImm7EqXLen, // user defined class 'anonymous_61961'
3314 MCK_UImm5Lsb0, // user defined class 'anonymous_63834'
3315 MCK_UImm6Lsb0, // user defined class 'anonymous_63835'
3316 MCK_UImm5NonZero, // user defined class 'anonymous_63853'
3317 MCK_UImm5GT3, // user defined class 'anonymous_63854'
3318 MCK_UImm5GE6Plus1, // user defined class 'anonymous_63855'
3319 MCK_UImm5Slist, // user defined class 'anonymous_63856'
3320 MCK_UImm10, // user defined class 'anonymous_63857'
3321 MCK_UImm11, // user defined class 'anonymous_63858'
3322 MCK_UImm14Lsb00, // user defined class 'anonymous_63859'
3323 MCK_UImm16NonZero, // user defined class 'anonymous_63860'
3324 MCK_SImm5NonZero, // user defined class 'anonymous_63861'
3325 MCK_SImm11, // user defined class 'anonymous_63862'
3326 MCK_SImm16, // user defined class 'anonymous_63863'
3327 MCK_SImm16NonZero, // user defined class 'anonymous_63864'
3328 MCK_SImm20LI, // user defined class 'anonymous_63865'
3329 MCK_SImm26, // user defined class 'anonymous_63866'
3330 MCK_BareSImm32, // user defined class 'anonymous_63867'
3331 MCK_BareSImm32Lsb0, // user defined class 'anonymous_63868'
3332 MCK_UImm7Lsb000, // user defined class 'anonymous_64128'
3333 MCK_UImm9, // user defined class 'anonymous_64129'
3334 MCK_BareSImm11Lsb0, // user defined class 'anonymous_64140'
3335 MCK_SImm18, // user defined class 'anonymous_64141'
3336 MCK_SImm18Lsb0, // user defined class 'anonymous_64142'
3337 MCK_SImm19Lsb00, // user defined class 'anonymous_64143'
3338 MCK_SImm20Lsb000, // user defined class 'anonymous_64144'
3339 MCK_SImm10, // user defined class 'anonymous_64417'
3340 NumMatchClassKinds
3341};
3342
3343} // end anonymous namespace
3344
3345static const char *getMatchKindDiag(RISCVAsmParser::RISCVMatchResultTy MatchResult) {
3346 switch (MatchResult) {
3347 case RISCVAsmParser::Match_InvalidRegClassGPRX0:
3348 return "register must be zero (x0)";
3349 case RISCVAsmParser::Match_InvalidRegClassGPRX1:
3350 return "register must be ra (x1)";
3351 case RISCVAsmParser::Match_InvalidRegClassGPRX5:
3352 return "register must be t0 (x5)";
3353 case RISCVAsmParser::Match_InvalidRegClassSP:
3354 return "register must be sp (x2)";
3355 case RISCVAsmParser::Match_InvalidRegClassGPRX1X5:
3356 return "register must be ra or t0 (x1 or x5)";
3357 case RISCVAsmParser::Match_GPRC:
3358 return "register must be a GPR from x8 to x15";
3359 case RISCVAsmParser::Match_InvalidRegClassSR07:
3360 return "register must be GPR from s0 to s7 (x8, x9 or x18-x23)";
3361 case RISCVAsmParser::Match_InvalidRegClassGPRNoX0X2:
3362 return "register must be a GPR excluding zero (x0) and sp (x2)";
3363 case RISCVAsmParser::Match_InvalidRegClassGPRNoX0:
3364 return "register must be a GPR excluding zero (x0)";
3365 case RISCVAsmParser::Match_InvalidRegClassGPRNoX2:
3366 return "register must be a GPR excluding sp (x2)";
3367 case RISCVAsmParser::Match_InvalidRegClassGPRX31:
3368 return "register must be a GPR excluding t6 (x31)";
3369 case RISCVAsmParser::Match_InvalidRegClassGPR:
3370 return "register must be a GPR";
3371 case RISCVAsmParser::Match_InvalidBareSymbol:
3372 return "operand must be a bare symbol name";
3373 case RISCVAsmParser::Match_InvalidCallSymbol:
3374 return "operand must be a bare symbol name";
3375 case RISCVAsmParser::Match_InvalidGPRPairCRV32:
3376 return "register pair must start with x8, x10, x12, or x14";
3377 case RISCVAsmParser::Match_InvalidGPRPairNoX0RV32:
3378 return "register pair must start with an even GPR other than x0";
3379 case RISCVAsmParser::Match_InvalidImmFour:
3380 return "operand must be constant 4";
3381 case RISCVAsmParser::Match_InvalidImmThree:
3382 return "operand must be constant 3";
3383 case RISCVAsmParser::Match_InvalidImmZero:
3384 return "immediate must be zero";
3385 case RISCVAsmParser::Match_InvalidLoadFPImm:
3386 return "operand must be a valid floating-point constant";
3387 case RISCVAsmParser::Match_InvalidPseudoJumpSymbol:
3388 return "operand must be a valid jump target";
3389 case RISCVAsmParser::Match_InvalidQCAccessSymbol:
3390 return "operand must be a symbol with a %qc.access specifier";
3391 case RISCVAsmParser::Match_InvalidRTZArg:
3392 return "operand must be 'rtz' floating-point rounding mode";
3393 case RISCVAsmParser::Match_InvalidRegList:
3394 return "operand must be {ra [, s0[-sN]]} or {x1 [, x8[-x9][, x18[-xN]]]}";
3395 case RISCVAsmParser::Match_InvalidRegListS0:
3396 return "operand must be {ra, s0[-sN]} or {x1, x8[-x9][, x18[-xN]]}";
3397 case RISCVAsmParser::Match_InvalidSMTI8:
3398 return "smt.vmadot with slide only supports i8 type";
3399 case RISCVAsmParser::Match_InvalidSMTType:
3400 return "This Inst only supports i4 and i8, i8 is the default type";
3401 case RISCVAsmParser::Match_InvalidTLSDESCCallSymbol:
3402 return "operand must be a symbol with %tlsdesc_call specifier";
3403 case RISCVAsmParser::Match_InvalidTPRelAddSymbol:
3404 return "operand must be a symbol with %tprel_add specifier";
3405 case RISCVAsmParser::Match_InvalidTileLambda:
3406 return "operand must be L1, L2, L4, L8, L16, L32, or L64";
3407 case RISCVAsmParser::Match_InvalidVMaskRegister:
3408 return "operand must be v0.t";
3409 case RISCVAsmParser::Match_InvalidVMaskCarryInRegister:
3410 return "operand must be v0";
3411 case RISCVAsmParser::Match_InvalidVScaleRegister:
3412 return "operand must be v0.scale";
3413 default:
3414 return nullptr;
3415 }
3416}
3417
3418static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
3419 switch (RegisterClass) {
3420 case MCK_GPRX0:
3421 return RISCVAsmParser::Match_InvalidRegClassGPRX0;
3422 case MCK_GPRX1:
3423 return RISCVAsmParser::Match_InvalidRegClassGPRX1;
3424 case MCK_GPRX5:
3425 return RISCVAsmParser::Match_InvalidRegClassGPRX5;
3426 case MCK_SP:
3427 return RISCVAsmParser::Match_InvalidRegClassSP;
3428 case MCK_GPRX1X5:
3429 return RISCVAsmParser::Match_InvalidRegClassGPRX1X5;
3430 case MCK_GPRC:
3431 return RISCVAsmParser::Match_GPRC;
3432 case MCK_SR07:
3433 return RISCVAsmParser::Match_InvalidRegClassSR07;
3434 case MCK_GPRNoX0X2:
3435 return RISCVAsmParser::Match_InvalidRegClassGPRNoX0X2;
3436 case MCK_GPRNoX0:
3437 return RISCVAsmParser::Match_InvalidRegClassGPRNoX0;
3438 case MCK_GPRNoX2:
3439 return RISCVAsmParser::Match_InvalidRegClassGPRNoX2;
3440 case MCK_GPRNoX31:
3441 return RISCVAsmParser::Match_InvalidRegClassGPRX31;
3442 case MCK_GPR:
3443 return RISCVAsmParser::Match_InvalidRegClassGPR;
3444 default:
3445 return MCTargetAsmParser::Match_InvalidOperand;
3446 }
3447}
3448
3449static MatchClassKind matchTokenString(StringRef Name) {
3450 switch (Name.size()) {
3451 default: break;
3452 case 1: // 2 strings to match.
3453 switch (Name[0]) {
3454 default: break;
3455 case '(': // 1 string to match.
3456 return MCK__40_; // "("
3457 case ')': // 1 string to match.
3458 return MCK__41_; // ")"
3459 }
3460 break;
3461 }
3462 return InvalidMatchClass;
3463}
3464
3465/// isSubclass - Compute whether \p A is a subclass of \p B.
3466static bool isSubclass(MatchClassKind A, MatchClassKind B) {
3467 if (A == B)
3468 return true;
3469
3470 [[maybe_unused]] static constexpr struct {
3471 uint32_t Offset;
3472 uint16_t Start;
3473 uint16_t Length;
3474 } Table[] = {
3475 {0, 0, 0},
3476 {0, 0, 0},
3477 {0, 0, 0},
3478 {0, 0, 0},
3479 {0, 107, 1},
3480 {1, 111, 1},
3481 {2, 113, 1},
3482 {3, 115, 1},
3483 {4, 85, 1},
3484 {5, 119, 1},
3485 {6, 91, 1},
3486 {7, 127, 1},
3487 {8, 57, 1},
3488 {9, 95, 1},
3489 {10, 136, 1},
3490 {11, 48, 1},
3491 {12, 71, 1},
3492 {13, 98, 1},
3493 {14, 45, 52},
3494 {66, 51, 46},
3495 {112, 79, 18},
3496 {130, 87, 10},
3497 {140, 92, 5},
3498 {145, 81, 67},
3499 {212, 39, 109},
3500 {321, 121, 27},
3501 {348, 39, 109},
3502 {457, 122, 26},
3503 {483, 144, 1},
3504 {484, 145, 1},
3505 {485, 124, 25},
3506 {510, 41, 108},
3507 {618, 41, 108},
3508 {726, 82, 67},
3509 {793, 68, 1},
3510 {794, 123, 26},
3511 {820, 146, 1},
3512 {821, 0, 0},
3513 {821, 60, 88},
3514 {909, 116, 32},
3515 {941, 65, 84},
3516 {1025, 117, 32},
3517 {1057, 46, 51},
3518 {1108, 0, 0},
3519 {1108, 48, 1},
3520 {1109, 72, 25},
3521 {1134, 72, 25},
3522 {1159, 70, 28},
3523 {1187, 0, 0},
3524 {1187, 50, 47},
3525 {1234, 55, 42},
3526 {1276, 55, 42},
3527 {1318, 61, 87},
3528 {1405, 65, 84},
3529 {1489, 57, 1},
3530 {1490, 78, 19},
3531 {1509, 71, 1},
3532 {1510, 0, 0},
3533 {1510, 140, 1},
3534 {1511, 138, 1},
3535 {1512, 99, 49},
3536 {1561, 99, 49},
3537 {1610, 139, 1},
3538 {1611, 141, 1},
3539 {1612, 142, 1},
3540 {1613, 100, 49},
3541 {1662, 131, 14},
3542 {1676, 132, 14},
3543 {1690, 0, 0},
3544 {1690, 100, 49},
3545 {1739, 97, 1},
3546 {1740, 0, 0},
3547 {1740, 73, 24},
3548 {1764, 78, 19},
3549 {1783, 78, 19},
3550 {1802, 80, 68},
3551 {1870, 82, 67},
3552 {1937, 85, 1},
3553 {1938, 86, 11},
3554 {1949, 86, 11},
3555 {1960, 88, 60},
3556 {2020, 88, 60},
3557 {2080, 89, 60},
3558 {2140, 89, 60},
3559 {2200, 91, 1},
3560 {2201, 0, 0},
3561 {2201, 92, 5},
3562 {2206, 93, 4},
3563 {2210, 108, 40},
3564 {2250, 109, 40},
3565 {2290, 95, 1},
3566 {2291, 0, 0},
3567 {2291, 96, 1},
3568 {2292, 96, 1},
3569 {2293, 98, 1},
3570 {2294, 0, 0},
3571 {2294, 0, 0},
3572 {2294, 0, 0},
3573 {2294, 0, 0},
3574 {2294, 102, 46},
3575 {2340, 104, 45},
3576 {2385, 107, 1},
3577 {2386, 108, 40},
3578 {2426, 108, 40},
3579 {2466, 109, 40},
3580 {2506, 109, 40},
3581 {2546, 111, 1},
3582 {2547, 0, 0},
3583 {2547, 120, 28},
3584 {2575, 125, 24},
3585 {2599, 113, 1},
3586 {2600, 0, 0},
3587 {2600, 115, 1},
3588 {2601, 0, 0},
3589 {2601, 119, 1},
3590 {2602, 0, 0},
3591 {2602, 120, 28},
3592 {2630, 123, 26},
3593 {2656, 127, 1},
3594 {2657, 0, 0},
3595 {2657, 128, 20},
3596 {2677, 128, 20},
3597 {2697, 129, 19},
3598 {2716, 133, 16},
3599 {2732, 134, 15},
3600 {2747, 133, 16},
3601 {2763, 136, 1},
3602 {2764, 0, 0},
3603 {2764, 147, 1},
3604 {2765, 147, 1},
3605 {2766, 147, 1},
3606 {2767, 144, 1},
3607 {2768, 145, 1},
3608 {2769, 143, 6},
3609 {2775, 143, 6},
3610 {2781, 143, 6},
3611 {2787, 0, 0},
3612 {2787, 146, 1},
3613 {2788, 0, 0},
3614 {2788, 0, 0},
3615 {2788, 0, 0},
3616 {2788, 0, 0},
3617 {2788, 0, 0},
3618 {2788, 148, 1},
3619 {2789, 0, 0},
3620 {2789, 0, 0},
3621 {2789, 0, 0},
3622 {2789, 0, 0},
3623 {2789, 0, 0},
3624 {2789, 0, 0},
3625 {2789, 0, 0},
3626 {2789, 0, 0},
3627 {2789, 0, 0},
3628 {2789, 0, 0},
3629 {2789, 0, 0},
3630 {2789, 0, 0},
3631 {2789, 0, 0},
3632 {2789, 1, 1},
3633 {2790, 1, 1},
3634 {2791, 0, 0},
3635 {2791, 0, 0},
3636 {2791, 0, 0},
3637 {2791, 0, 0},
3638 {2791, 0, 0},
3639 {2791, 0, 0},
3640 {2791, 0, 0},
3641 {2791, 0, 0},
3642 {2791, 0, 0},
3643 {2791, 0, 0},
3644 {2791, 0, 0},
3645 {2791, 0, 0},
3646 {2791, 0, 0},
3647 {2791, 0, 0},
3648 {2791, 0, 0},
3649 {2791, 0, 0},
3650 {2791, 0, 0},
3651 {2791, 0, 0},
3652 {2791, 0, 0},
3653 {2791, 0, 0},
3654 {2791, 0, 0},
3655 {2791, 0, 0},
3656 {2791, 0, 0},
3657 {2791, 0, 0},
3658 {2791, 0, 0},
3659 {2791, 0, 0},
3660 {2791, 0, 0},
3661 {2791, 1, 1},
3662 {2792, 1, 1},
3663 {2793, 0, 0},
3664 {2793, 0, 0},
3665 {2793, 0, 0},
3666 {2793, 0, 0},
3667 {2793, 0, 0},
3668 {2793, 0, 0},
3669 {2793, 0, 0},
3670 {2793, 1, 1},
3671 {2794, 0, 0},
3672 {2794, 0, 0},
3673 {2794, 0, 0},
3674 {2794, 0, 0},
3675 {2794, 0, 0},
3676 {2794, 0, 0},
3677 {2794, 0, 0},
3678 {2794, 0, 0},
3679 {2794, 0, 0},
3680 {2794, 0, 0},
3681 {2794, 0, 0},
3682 {2794, 0, 0},
3683 {2794, 0, 0},
3684 {2794, 0, 0},
3685 {2794, 0, 0},
3686 {2794, 0, 0},
3687 {2794, 0, 0},
3688 {2794, 0, 0},
3689 {2794, 0, 0},
3690 {2794, 0, 0},
3691 {2794, 0, 0},
3692 {2794, 0, 0},
3693 {2794, 0, 0},
3694 {2794, 0, 0},
3695 {2794, 0, 0},
3696 {2794, 0, 0},
3697 {2794, 0, 0},
3698 {2794, 0, 0},
3699 {2794, 0, 0},
3700 {2794, 0, 0},
3701 {2794, 0, 0},
3702 {2794, 0, 0},
3703 {2794, 0, 0},
3704 {2794, 0, 0},
3705 {2794, 0, 0},
3706 {2794, 0, 0},
3707 {2794, 0, 0},
3708 {2794, 0, 0},
3709 {2794, 0, 0},
3710 {2794, 0, 0},
3711 {2794, 0, 0},
3712 {2794, 0, 0},
3713 {2794, 0, 0},
3714 {2794, 0, 0},
3715 {2794, 0, 0},
3716 {2794, 0, 0},
3717 {2794, 0, 0},
3718 {2794, 0, 0},
3719 {2794, 0, 0},
3720 {2794, 0, 0},
3721 {2794, 0, 0},
3722 {2794, 0, 0},
3723 {2794, 0, 0},
3724 {2794, 0, 0},
3725 {2794, 0, 0},
3726 {2794, 0, 0},
3727 {2794, 0, 0},
3728 {2794, 0, 0},
3729 {2794, 0, 0},
3730 {2794, 0, 0},
3731 {2794, 0, 0},
3732 {2794, 0, 0},
3733 {2794, 0, 0},
3734 {2794, 0, 0},
3735 {2794, 0, 0},
3736 {2794, 0, 0},
3737 {2794, 0, 0},
3738 {2794, 0, 0},
3739 {2794, 0, 0},
3740 {2794, 0, 0},
3741 {2794, 0, 0},
3742 {2794, 0, 0},
3743 {2794, 0, 0},
3744 };
3745
3746 static constexpr uint8_t Data[] = {
3747 0xFF,
3748 0xFF,
3749 0x00,
3750 0x00,
3751 0x00,
3752 0x8E,
3753 0x81,
3754 0x61,
3755 0x46,
3756 0x00,
3757 0x00,
3758 0x62,
3759 0x60,
3760 0x98,
3761 0x81,
3762 0x61,
3763 0x06,
3764 0x19,
3765 0x03,
3766 0x01,
3767 0x80,
3768 0x10,
3769 0x10,
3770 0x07,
3771 0x07,
3772 0x00,
3773 0x18,
3774 0x00,
3775 0x00,
3776 0x00,
3777 0x00,
3778 0x00,
3779 0x00,
3780 0x00,
3781 0x00,
3782 0x00,
3783 0xE2,
3784 0xE0,
3785 0x00,
3786 0x00,
3787 0x03,
3788 0x05,
3789 0x00,
3790 0x18,
3791 0x00,
3792 0x00,
3793 0x00,
3794 0x00,
3795 0x00,
3796 0x00,
3797 0x00,
3798 0x00,
3799 0x00,
3800 0xE2,
3801 0xE0,
3802 0x00,
3803 0x00,
3804 0x03,
3805 0x03,
3806 0x00,
3807 0x3C,
3808 0x80,
3809 0x01,
3810 0x61,
3811 0x00,
3812 0x00,
3813 0x00,
3814 0x00,
3815 0x00,
3816 0x00,
3817 0x00,
3818 0x00,
3819 0x00,
3820 0x04,
3821 0x07,
3822 0x1C,
3823 0x10,
3824 0x06,
3825 0x00,
3826 0x00,
3827 0x00,
3828 0x00,
3829 0x00,
3830 0x00,
3831 0x00,
3832 0x00,
3833 0x40,
3834 0x70,
3835 0xC0,
3836 0x01,
3837 0x61,
3838 0x20,
3839 0x00,
3840 0x10,
3841 0x02,
3842 0x82,
3843 0x03,
3844 0x0E,
3845 0x08,
3846 0x07,
3847 0x50,
3848 0x40,
3849 0x78,
3850 0x00,
3851 0x00,
3852 0x00,
3853 0x00,
3854 0x90,
3855 0x21,
3856 0x20,
3857 0x0E,
3858 0x0E,
3859 0x00,
3860 0x30,
3861 0x0E,
3862 0x0E,
3863 0x00,
3864 0x30,
3865 0x02,
3866 0x00,
3867 0x00,
3868 0x00,
3869 0x31,
3870 0x02,
3871 0x82,
3872 0x03,
3873 0x0E,
3874 0x08,
3875 0x83,
3876 0x03,
3877 0x0E,
3878 0x08,
3879 0x73,
3880 0x04,
3881 0x00,
3882 0x38,
3883 0x06,
3884 0x86,
3885 0xF9,
3886 0x18,
3887 0x18,
3888 0xE6,
3889 0x31,
3890 0x30,
3891 0xCC,
3892 0x00,
3893 0x00,
3894 0x00,
3895 0x1C,
3896 0x01,
3897 0x00,
3898 0x8E,
3899 0x81,
3900 0x61,
3901 0x06,
3902 0x00,
3903 0x10,
3904 0x02,
3905 0x82,
3906 0x19,
3907 0x00,
3908 0x80,
3909 0x18,
3910 0x18,
3911 0x66,
3912 0x00,
3913 0x10,
3914 0x06,
3915 0x02,
3916 0x90,
3917 0x21,
3918 0x20,
3919 0x0E,
3920 0x0E,
3921 0x00,
3922 0x30,
3923 0x00,
3924 0xC1,
3925 0x20,
3926 0x00,
3927 0x31,
3928 0x02,
3929 0x82,
3930 0x03,
3931 0x0E,
3932 0x08,
3933 0x07,
3934 0x04,
3935 0xF3,
3936 0x19,
3937 0x02,
3938 0xE2,
3939 0xE0,
3940 0x00,
3941 0x00,
3942 0x33,
3943 0x04,
3944 0xC4,
3945 0xC1,
3946 0x01,
3947 0x00,
3948 0x3E,
3949 0x46,
3950 0x40,
3951 0x70,
3952 0xC0,
3953 0x01,
3954 0x61,
3955 0x00,
3956 0x18,
3957 0x00,
3958 0xC6,
3959 0x08,
3960 0x08,
3961 0x0E,
3962 0x38,
3963 0x20,
3964 0x3C,
3965 0x06,
3966 0x86,
3967 0x19,
3968 0x10,
3969 0xCC,
3970 0x81,
3971 0x61,
3972 0x0E,
3973 0x04,
3974 0x20,
3975 0x43,
3976 0x40,
3977 0x1C,
3978 0x1C,
3979 0x00,
3980 0xE0,
3981 0x20,
3982 0x00,
3983 0x31,
3984 0x02,
3985 0x82,
3986 0x03,
3987 0x0E,
3988 0x08,
3989 0x07,
3990 0x73,
3991 0x98,
3992 0x01,
3993 0x40,
3994 0x10,
3995 0x00,
3996 0x01,
3997 0x03,
3998 0x00,
3999 0x18,
4000 0x00,
4001 0x08,
4002 0x01,
4003 0x71,
4004 0x70,
4005 0x00,
4006 0x80,
4007 0x01,
4008 0x80,
4009 0x10,
4010 0x10,
4011 0x1C,
4012 0x70,
4013 0x40,
4014 0x18,
4015 0x00,
4016 0x10,
4017 0x01,
4018 0x00,
4019 0x01,
4020 0x03,
4021 0x84,
4022 0x67,
4023 0x06,
4024 0x40,
4025 0xC0,
4026 0x00,
4027 0x00,
4028 0x06,
4029 0x00,
4030 0x04,
4031 0x0C,
4032 0x10,
4033 0xFE,
4034 0x10,
4035 0x10,
4036 0x07,
4037 0x07,
4038 0x00,
4039 0x38,
4040 0x02,
4041 0x82,
4042 0x03,
4043 0x0E,
4044 0x08,
4045 0x07,
4046 0x40,
4047 0xC0,
4048 0x00,
4049 0x00,
4050 0x06,
4051 0xC4,
4052 0xC1,
4053 0x01,
4054 0x00,
4055 0x06,
4056 0x04,
4057 0x07,
4058 0x1C,
4059 0x10,
4060 0x06,
4061 0x00,
4062 0x04,
4063 0x0C,
4064 0x10,
4065 0x0E,
4066 0x18,
4067 0x00,
4068 0xC0,
4069 0x80,
4070 0x01,
4071 0xC2,
4072 0x1F,
4073 0x1C,
4074 0x00,
4075 0xE0,
4076 0x01,
4077 0x07,
4078 0x84,
4079 0x07,
4080 0x00,
4081 0xB0,
4082 0x00,
4083 0x00,
4084 0x07,
4085 0x00,
4086 0x58,
4087 0x40,
4088 0x38,
4089 0x20,
4090 0x1C,
4091 0x20,
4092 0xFC,
4093 0xC3,
4094 0x30,
4095 0xFC,
4096 0x03,
4097 };
4098
4099 auto &Entry = Table[A];
4100 unsigned Idx = B - Entry.Start;
4101 if (Idx >= Entry.Length)
4102 return false;
4103 Idx += Entry.Offset;
4104 return (Data[Idx / 8] >> (Idx % 8)) & 1;
4105}
4106
4107static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
4108 RISCVOperand &Operand = (RISCVOperand &)GOp;
4109 if (Kind == InvalidMatchClass)
4110 return MCTargetAsmParser::Match_InvalidOperand;
4111
4112 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
4113 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
4114 MCTargetAsmParser::Match_Success :
4115 MCTargetAsmParser::Match_InvalidOperand;
4116
4117 switch (Kind) {
4118 default: break;
4119 case MCK_AnyRegCOperand: {
4120 DiagnosticPredicate DP(Operand.isAnyRegC());
4121 if (DP.isMatch())
4122 return MCTargetAsmParser::Match_Success;
4123 break;
4124 }
4125 case MCK_AnyRegOperand: {
4126 DiagnosticPredicate DP(Operand.isAnyReg());
4127 if (DP.isMatch())
4128 return MCTargetAsmParser::Match_Success;
4129 break;
4130 }
4131 case MCK_BareSymbol: {
4132 DiagnosticPredicate DP(Operand.isBareSymbol());
4133 if (DP.isMatch())
4134 return MCTargetAsmParser::Match_Success;
4135 if (DP.isNearMatch())
4136 return RISCVAsmParser::Match_InvalidBareSymbol;
4137 break;
4138 }
4139 case MCK_BareSymbolQC_E_LI: {
4140 DiagnosticPredicate DP(Operand.isBareSymbol());
4141 if (DP.isMatch())
4142 return MCTargetAsmParser::Match_Success;
4143 if (DP.isNearMatch())
4144 return RISCVAsmParser::Match_InvalidBareSymbolQC_E_LI;
4145 break;
4146 }
4147 case MCK_CLUIImm: {
4148 DiagnosticPredicate DP(Operand.isCLUIImm());
4149 if (DP.isMatch())
4150 return MCTargetAsmParser::Match_Success;
4151 if (DP.isNearMatch())
4152 return RISCVAsmParser::Match_InvalidCLUIImm;
4153 break;
4154 }
4155 case MCK_CSRSystemRegister: {
4156 DiagnosticPredicate DP(Operand.isCSRSystemRegister());
4157 if (DP.isMatch())
4158 return MCTargetAsmParser::Match_Success;
4159 if (DP.isNearMatch())
4160 return RISCVAsmParser::Match_InvalidCSRSystemRegister;
4161 break;
4162 }
4163 case MCK_RegReg: {
4164 DiagnosticPredicate DP(Operand.isRegReg());
4165 if (DP.isMatch())
4166 return MCTargetAsmParser::Match_Success;
4167 break;
4168 }
4169 case MCK_CallSymbol: {
4170 DiagnosticPredicate DP(Operand.isCallSymbol());
4171 if (DP.isMatch())
4172 return MCTargetAsmParser::Match_Success;
4173 if (DP.isNearMatch())
4174 return RISCVAsmParser::Match_InvalidCallSymbol;
4175 break;
4176 }
4177 case MCK_FRMArg: {
4178 DiagnosticPredicate DP(Operand.isFRMArg());
4179 if (DP.isMatch())
4180 return MCTargetAsmParser::Match_Success;
4181 break;
4182 }
4183 case MCK_FRMArgLegacy: {
4184 DiagnosticPredicate DP(Operand.isFRMArgLegacy());
4185 if (DP.isMatch())
4186 return MCTargetAsmParser::Match_Success;
4187 break;
4188 }
4189 case MCK_FenceArg: {
4190 DiagnosticPredicate DP(Operand.isFenceArg());
4191 if (DP.isMatch())
4192 return MCTargetAsmParser::Match_Success;
4193 break;
4194 }
4195 case MCK_GPRAsFPR16: {
4196 DiagnosticPredicate DP(Operand.isGPRAsFPR16());
4197 if (DP.isMatch())
4198 return MCTargetAsmParser::Match_Success;
4199 break;
4200 }
4201 case MCK_GPRAsFPR32: {
4202 DiagnosticPredicate DP(Operand.isGPRAsFPR32());
4203 if (DP.isMatch())
4204 return MCTargetAsmParser::Match_Success;
4205 break;
4206 }
4207 case MCK_GPRF64AsFPR: {
4208 DiagnosticPredicate DP(Operand.isGPRAsFPR());
4209 if (DP.isMatch())
4210 return MCTargetAsmParser::Match_Success;
4211 break;
4212 }
4213 case MCK_GPRPairAsFPR: {
4214 DiagnosticPredicate DP(Operand.isGPRPairAsFPR64());
4215 if (DP.isMatch())
4216 return MCTargetAsmParser::Match_Success;
4217 break;
4218 }
4219 case MCK_GPRPairCRV32: {
4220 DiagnosticPredicate DP(Operand.isGPRPairC());
4221 if (DP.isMatch())
4222 return MCTargetAsmParser::Match_Success;
4223 if (DP.isNearMatch())
4224 return RISCVAsmParser::Match_InvalidGPRPairCRV32;
4225 break;
4226 }
4227 case MCK_GPRPairNoX0RV32: {
4228 DiagnosticPredicate DP(Operand.isGPRPairNoX0());
4229 if (DP.isMatch())
4230 return MCTargetAsmParser::Match_Success;
4231 if (DP.isNearMatch())
4232 return RISCVAsmParser::Match_InvalidGPRPairNoX0RV32;
4233 break;
4234 }
4235 case MCK_GPRPairRV32: {
4236 DiagnosticPredicate DP(Operand.isGPRPair());
4237 if (DP.isMatch())
4238 return MCTargetAsmParser::Match_Success;
4239 break;
4240 }
4241 case MCK_GPRPairRV64: {
4242 DiagnosticPredicate DP(Operand.isGPRPair());
4243 if (DP.isMatch())
4244 return MCTargetAsmParser::Match_Success;
4245 break;
4246 }
4247 case MCK_Imm: {
4248 DiagnosticPredicate DP(Operand.isImm());
4249 if (DP.isMatch())
4250 return MCTargetAsmParser::Match_Success;
4251 break;
4252 }
4253 case MCK_ImmFour: {
4254 DiagnosticPredicate DP(Operand.isImmFour());
4255 if (DP.isMatch())
4256 return MCTargetAsmParser::Match_Success;
4257 if (DP.isNearMatch())
4258 return RISCVAsmParser::Match_InvalidImmFour;
4259 break;
4260 }
4261 case MCK_ImmThree: {
4262 DiagnosticPredicate DP(Operand.isImmThree());
4263 if (DP.isMatch())
4264 return MCTargetAsmParser::Match_Success;
4265 if (DP.isNearMatch())
4266 return RISCVAsmParser::Match_InvalidImmThree;
4267 break;
4268 }
4269 case MCK_ImmZero: {
4270 DiagnosticPredicate DP(Operand.isImmZero());
4271 if (DP.isMatch())
4272 return MCTargetAsmParser::Match_Success;
4273 if (DP.isNearMatch())
4274 return RISCVAsmParser::Match_InvalidImmZero;
4275 break;
4276 }
4277 case MCK_InsnCDirectiveOpcode: {
4278 DiagnosticPredicate DP(Operand.isImm());
4279 if (DP.isMatch())
4280 return MCTargetAsmParser::Match_Success;
4281 break;
4282 }
4283 case MCK_InsnDirectiveOpcode: {
4284 DiagnosticPredicate DP(Operand.isImm());
4285 if (DP.isMatch())
4286 return MCTargetAsmParser::Match_Success;
4287 break;
4288 }
4289 case MCK_LoadFPImm: {
4290 DiagnosticPredicate DP(Operand.isLoadFPImm());
4291 if (DP.isMatch())
4292 return MCTargetAsmParser::Match_Success;
4293 if (DP.isNearMatch())
4294 return RISCVAsmParser::Match_InvalidLoadFPImm;
4295 break;
4296 }
4297 case MCK_NegStackAdj: {
4298 DiagnosticPredicate DP(Operand.isStackAdj());
4299 if (DP.isMatch())
4300 return MCTargetAsmParser::Match_Success;
4301 if (DP.isNearMatch())
4302 return RISCVAsmParser::Match_InvalidStackAdj;
4303 break;
4304 }
4305 case MCK_PseudoJumpSymbol: {
4306 DiagnosticPredicate DP(Operand.isPseudoJumpSymbol());
4307 if (DP.isMatch())
4308 return MCTargetAsmParser::Match_Success;
4309 if (DP.isNearMatch())
4310 return RISCVAsmParser::Match_InvalidPseudoJumpSymbol;
4311 break;
4312 }
4313 case MCK_QCAccessSymbol: {
4314 DiagnosticPredicate DP(Operand.isQCAccessSymbol());
4315 if (DP.isMatch())
4316 return MCTargetAsmParser::Match_Success;
4317 if (DP.isNearMatch())
4318 return RISCVAsmParser::Match_InvalidQCAccessSymbol;
4319 break;
4320 }
4321 case MCK_RTZArg: {
4322 DiagnosticPredicate DP(Operand.isRTZArg());
4323 if (DP.isMatch())
4324 return MCTargetAsmParser::Match_Success;
4325 if (DP.isNearMatch())
4326 return RISCVAsmParser::Match_InvalidRTZArg;
4327 break;
4328 }
4329 case MCK_RegList: {
4330 DiagnosticPredicate DP(Operand.isRegList());
4331 if (DP.isMatch())
4332 return MCTargetAsmParser::Match_Success;
4333 if (DP.isNearMatch())
4334 return RISCVAsmParser::Match_InvalidRegList;
4335 break;
4336 }
4337 case MCK_RegListS0: {
4338 DiagnosticPredicate DP(Operand.isRegListS0());
4339 if (DP.isMatch())
4340 return MCTargetAsmParser::Match_Success;
4341 if (DP.isNearMatch())
4342 return RISCVAsmParser::Match_InvalidRegListS0;
4343 break;
4344 }
4345 case MCK_RnumArg: {
4346 DiagnosticPredicate DP(Operand.isRnumArg());
4347 if (DP.isMatch())
4348 return MCTargetAsmParser::Match_Success;
4349 if (DP.isNearMatch())
4350 return RISCVAsmParser::Match_InvalidRnumArg;
4351 break;
4352 }
4353 case MCK_SImm10PLI_H: {
4354 DiagnosticPredicate DP(Operand.isSImm10PLI_H());
4355 if (DP.isMatch())
4356 return MCTargetAsmParser::Match_Success;
4357 if (DP.isNearMatch())
4358 return RISCVAsmParser::Match_InvalidSImm10PLI_H;
4359 break;
4360 }
4361 case MCK_SImm10PLI_W: {
4362 DiagnosticPredicate DP(Operand.isSImm10PLI_W());
4363 if (DP.isMatch())
4364 return MCTargetAsmParser::Match_Success;
4365 if (DP.isNearMatch())
4366 return RISCVAsmParser::Match_InvalidSImm10PLI_W;
4367 break;
4368 }
4369 case MCK_SImm10PLUI: {
4370 DiagnosticPredicate DP(Operand.isSImm10PLUI());
4371 if (DP.isMatch())
4372 return MCTargetAsmParser::Match_Success;
4373 if (DP.isNearMatch())
4374 return RISCVAsmParser::Match_InvalidSImm10PLUI;
4375 break;
4376 }
4377 case MCK_SImm8PLI_B: {
4378 DiagnosticPredicate DP(Operand.isSImm8PLI_B());
4379 if (DP.isMatch())
4380 return MCTargetAsmParser::Match_Success;
4381 if (DP.isNearMatch())
4382 return RISCVAsmParser::Match_InvalidSImm8PLI_B;
4383 break;
4384 }
4385 case MCK_SMTI8: {
4386 DiagnosticPredicate DP(Operand.isSMTI8());
4387 if (DP.isMatch())
4388 return MCTargetAsmParser::Match_Success;
4389 if (DP.isNearMatch())
4390 return RISCVAsmParser::Match_InvalidSMTI8;
4391 break;
4392 }
4393 case MCK_SMTVType: {
4394 DiagnosticPredicate DP(Operand.isSMTVType());
4395 if (DP.isMatch())
4396 return MCTargetAsmParser::Match_Success;
4397 if (DP.isNearMatch())
4398 return RISCVAsmParser::Match_InvalidSMTType;
4399 break;
4400 }
4401 case MCK_BareSImm21Lsb0: {
4402 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<21>());
4403 if (DP.isMatch())
4404 return MCTargetAsmParser::Match_Success;
4405 if (DP.isNearMatch())
4406 return RISCVAsmParser::Match_InvalidBareSImm21Lsb0;
4407 break;
4408 }
4409 case MCK_StackAdj: {
4410 DiagnosticPredicate DP(Operand.isStackAdj());
4411 if (DP.isMatch())
4412 return MCTargetAsmParser::Match_Success;
4413 if (DP.isNearMatch())
4414 return RISCVAsmParser::Match_InvalidStackAdj;
4415 break;
4416 }
4417 case MCK_TLSDESCCallSymbol: {
4418 DiagnosticPredicate DP(Operand.isTLSDESCCallSymbol());
4419 if (DP.isMatch())
4420 return MCTargetAsmParser::Match_Success;
4421 if (DP.isNearMatch())
4422 return RISCVAsmParser::Match_InvalidTLSDESCCallSymbol;
4423 break;
4424 }
4425 case MCK_TPRelAddSymbol: {
4426 DiagnosticPredicate DP(Operand.isTPRelAddSymbol());
4427 if (DP.isMatch())
4428 return MCTargetAsmParser::Match_Success;
4429 if (DP.isNearMatch())
4430 return RISCVAsmParser::Match_InvalidTPRelAddSymbol;
4431 break;
4432 }
4433 case MCK_TileLambda: {
4434 DiagnosticPredicate DP(Operand.isTileLambda());
4435 if (DP.isMatch())
4436 return MCTargetAsmParser::Match_Success;
4437 if (DP.isNearMatch())
4438 return RISCVAsmParser::Match_InvalidTileLambda;
4439 break;
4440 }
4441 case MCK_UImmLog2XLen: {
4442 DiagnosticPredicate DP(Operand.isUImmLog2XLen());
4443 if (DP.isMatch())
4444 return MCTargetAsmParser::Match_Success;
4445 if (DP.isNearMatch())
4446 return RISCVAsmParser::Match_InvalidUImmLog2XLen;
4447 break;
4448 }
4449 case MCK_UImmLog2XLenNonZero: {
4450 DiagnosticPredicate DP(Operand.isUImmLog2XLenNonZero());
4451 if (DP.isMatch())
4452 return MCTargetAsmParser::Match_Success;
4453 if (DP.isNearMatch())
4454 return RISCVAsmParser::Match_InvalidUImmLog2XLenNonZero;
4455 break;
4456 }
4457 case MCK_RVVMaskRegOpOperand: {
4458 DiagnosticPredicate DP(Operand.isV0Reg());
4459 if (DP.isMatch())
4460 return MCTargetAsmParser::Match_Success;
4461 if (DP.isNearMatch())
4462 return RISCVAsmParser::Match_InvalidVMaskRegister;
4463 break;
4464 }
4465 case MCK_RVVMaskCarryInRegOpOperand: {
4466 DiagnosticPredicate DP(Operand.isV0Reg());
4467 if (DP.isMatch())
4468 return MCTargetAsmParser::Match_Success;
4469 if (DP.isNearMatch())
4470 return RISCVAsmParser::Match_InvalidVMaskCarryInRegister;
4471 break;
4472 }
4473 case MCK_RVVScaleRegOpOperand: {
4474 DiagnosticPredicate DP(Operand.isV0Reg());
4475 if (DP.isMatch())
4476 return MCTargetAsmParser::Match_Success;
4477 if (DP.isNearMatch())
4478 return RISCVAsmParser::Match_InvalidVScaleRegister;
4479 break;
4480 }
4481 case MCK_XSfmmVType: {
4482 DiagnosticPredicate DP(Operand.isXSfmmVType());
4483 if (DP.isMatch())
4484 return MCTargetAsmParser::Match_Success;
4485 break;
4486 }
4487 case MCK_YBNDSWImm: {
4488 DiagnosticPredicate DP(Operand.isYBNDSWImm());
4489 if (DP.isMatch())
4490 return MCTargetAsmParser::Match_Success;
4491 if (DP.isNearMatch())
4492 return RISCVAsmParser::Match_InvalidYBNDSWImm;
4493 break;
4494 }
4495 case MCK_ZeroOffsetMemOpOperand: {
4496 DiagnosticPredicate DP(Operand.isGPR());
4497 if (DP.isMatch())
4498 return MCTargetAsmParser::Match_Success;
4499 break;
4500 }
4501 case MCK_UImm1: {
4502 DiagnosticPredicate DP(Operand.isUImm1());
4503 if (DP.isMatch())
4504 return MCTargetAsmParser::Match_Success;
4505 if (DP.isNearMatch())
4506 return RISCVAsmParser::Match_InvalidUImm1;
4507 break;
4508 }
4509 case MCK_UImm2: {
4510 DiagnosticPredicate DP(Operand.isUImm2());
4511 if (DP.isMatch())
4512 return MCTargetAsmParser::Match_Success;
4513 if (DP.isNearMatch())
4514 return RISCVAsmParser::Match_InvalidUImm2;
4515 break;
4516 }
4517 case MCK_UImm3: {
4518 DiagnosticPredicate DP(Operand.isUImm3());
4519 if (DP.isMatch())
4520 return MCTargetAsmParser::Match_Success;
4521 if (DP.isNearMatch())
4522 return RISCVAsmParser::Match_InvalidUImm3;
4523 break;
4524 }
4525 case MCK_UImm4: {
4526 DiagnosticPredicate DP(Operand.isUImm4());
4527 if (DP.isMatch())
4528 return MCTargetAsmParser::Match_Success;
4529 if (DP.isNearMatch())
4530 return RISCVAsmParser::Match_InvalidUImm4;
4531 break;
4532 }
4533 case MCK_UImm5: {
4534 DiagnosticPredicate DP(Operand.isUImm5());
4535 if (DP.isMatch())
4536 return MCTargetAsmParser::Match_Success;
4537 if (DP.isNearMatch())
4538 return RISCVAsmParser::Match_InvalidUImm5;
4539 break;
4540 }
4541 case MCK_UImm6: {
4542 DiagnosticPredicate DP(Operand.isUImm6());
4543 if (DP.isMatch())
4544 return MCTargetAsmParser::Match_Success;
4545 if (DP.isNearMatch())
4546 return RISCVAsmParser::Match_InvalidUImm6;
4547 break;
4548 }
4549 case MCK_UImm7: {
4550 DiagnosticPredicate DP(Operand.isUImm7());
4551 if (DP.isMatch())
4552 return MCTargetAsmParser::Match_Success;
4553 if (DP.isNearMatch())
4554 return RISCVAsmParser::Match_InvalidUImm7;
4555 break;
4556 }
4557 case MCK_UImm8: {
4558 DiagnosticPredicate DP(Operand.isUImm8());
4559 if (DP.isMatch())
4560 return MCTargetAsmParser::Match_Success;
4561 if (DP.isNearMatch())
4562 return RISCVAsmParser::Match_InvalidUImm8;
4563 break;
4564 }
4565 case MCK_UImm16: {
4566 DiagnosticPredicate DP(Operand.isUImm16());
4567 if (DP.isMatch())
4568 return MCTargetAsmParser::Match_Success;
4569 if (DP.isNearMatch())
4570 return RISCVAsmParser::Match_InvalidUImm16;
4571 break;
4572 }
4573 case MCK_UImm32: {
4574 DiagnosticPredicate DP(Operand.isUImm32());
4575 if (DP.isMatch())
4576 return MCTargetAsmParser::Match_Success;
4577 if (DP.isNearMatch())
4578 return RISCVAsmParser::Match_InvalidUImm32;
4579 break;
4580 }
4581 case MCK_UImm48: {
4582 DiagnosticPredicate DP(Operand.isUImm48());
4583 if (DP.isMatch())
4584 return MCTargetAsmParser::Match_Success;
4585 if (DP.isNearMatch())
4586 return RISCVAsmParser::Match_InvalidUImm48;
4587 break;
4588 }
4589 case MCK_UImm64: {
4590 DiagnosticPredicate DP(Operand.isUImm64());
4591 if (DP.isMatch())
4592 return MCTargetAsmParser::Match_Success;
4593 if (DP.isNearMatch())
4594 return RISCVAsmParser::Match_InvalidUImm64;
4595 break;
4596 }
4597 case MCK_SImm12: {
4598 DiagnosticPredicate DP(Operand.isSImm12());
4599 if (DP.isMatch())
4600 return MCTargetAsmParser::Match_Success;
4601 if (DP.isNearMatch())
4602 return RISCVAsmParser::Match_InvalidSImm12;
4603 break;
4604 }
4605 case MCK_SImm12LO: {
4606 DiagnosticPredicate DP(Operand.isSImm12LO());
4607 if (DP.isMatch())
4608 return MCTargetAsmParser::Match_Success;
4609 if (DP.isNearMatch())
4610 return RISCVAsmParser::Match_InvalidSImm12LO;
4611 break;
4612 }
4613 case MCK_BareSImm13Lsb0: {
4614 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<13>());
4615 if (DP.isMatch())
4616 return MCTargetAsmParser::Match_Success;
4617 if (DP.isNearMatch())
4618 return RISCVAsmParser::Match_InvalidBareSImm13Lsb0;
4619 break;
4620 }
4621 case MCK_UImm20: {
4622 DiagnosticPredicate DP(Operand.isUImm20());
4623 if (DP.isMatch())
4624 return MCTargetAsmParser::Match_Success;
4625 if (DP.isNearMatch())
4626 return RISCVAsmParser::Match_InvalidUImm20;
4627 break;
4628 }
4629 case MCK_UImm20LUI: {
4630 DiagnosticPredicate DP(Operand.isUImm20LUI());
4631 if (DP.isMatch())
4632 return MCTargetAsmParser::Match_Success;
4633 if (DP.isNearMatch())
4634 return RISCVAsmParser::Match_InvalidUImm20LUI;
4635 break;
4636 }
4637 case MCK_UImm20AUIPC: {
4638 DiagnosticPredicate DP(Operand.isUImm20AUIPC());
4639 if (DP.isMatch())
4640 return MCTargetAsmParser::Match_Success;
4641 if (DP.isNearMatch())
4642 return RISCVAsmParser::Match_InvalidUImm20AUIPC;
4643 break;
4644 }
4645 case MCK_ImmXLenLI: {
4646 DiagnosticPredicate DP(Operand.isImmXLenLI());
4647 if (DP.isMatch())
4648 return MCTargetAsmParser::Match_Success;
4649 if (DP.isNearMatch())
4650 return RISCVAsmParser::Match_InvalidImmXLenLI;
4651 break;
4652 }
4653 case MCK_ImmXLenLI_Restricted: {
4654 DiagnosticPredicate DP(Operand.isImmXLenLI_Restricted());
4655 if (DP.isMatch())
4656 return MCTargetAsmParser::Match_Success;
4657 if (DP.isNearMatch())
4658 return RISCVAsmParser::Match_InvalidImmXLenLI_Restricted;
4659 break;
4660 }
4661 case MCK_SImm12Lsb00000: {
4662 DiagnosticPredicate DP(Operand.isSImm12Lsb00000());
4663 if (DP.isMatch())
4664 return MCTargetAsmParser::Match_Success;
4665 if (DP.isNearMatch())
4666 return RISCVAsmParser::Match_InvalidSImm12Lsb00000;
4667 break;
4668 }
4669 case MCK_Imm5Zibi: {
4670 DiagnosticPredicate DP(Operand.isImm5Zibi());
4671 if (DP.isMatch())
4672 return MCTargetAsmParser::Match_Success;
4673 if (DP.isNearMatch())
4674 return RISCVAsmParser::Match_InvalidImm5Zibi;
4675 break;
4676 }
4677 case MCK_VTypeI10: {
4678 DiagnosticPredicate DP(Operand.isVTypeI10());
4679 if (DP.isMatch())
4680 return MCTargetAsmParser::Match_Success;
4681 if (DP.isNearMatch())
4682 return RISCVAsmParser::Match_InvalidVTypeI;
4683 break;
4684 }
4685 case MCK_VTypeI11: {
4686 DiagnosticPredicate DP(Operand.isVTypeI11());
4687 if (DP.isMatch())
4688 return MCTargetAsmParser::Match_Success;
4689 if (DP.isNearMatch())
4690 return RISCVAsmParser::Match_InvalidVTypeI;
4691 break;
4692 }
4693 case MCK_SImm5: {
4694 DiagnosticPredicate DP(Operand.isSImm5());
4695 if (DP.isMatch())
4696 return MCTargetAsmParser::Match_Success;
4697 if (DP.isNearMatch())
4698 return RISCVAsmParser::Match_InvalidSImm5;
4699 break;
4700 }
4701 case MCK_SImm5Plus1: {
4702 DiagnosticPredicate DP(Operand.isSImm5Plus1());
4703 if (DP.isMatch())
4704 return MCTargetAsmParser::Match_Success;
4705 if (DP.isNearMatch())
4706 return RISCVAsmParser::Match_InvalidSImm5Plus1;
4707 break;
4708 }
4709 case MCK_UImm4Plus1: {
4710 DiagnosticPredicate DP(Operand.isUImm4Plus1());
4711 if (DP.isMatch())
4712 return MCTargetAsmParser::Match_Success;
4713 if (DP.isNearMatch())
4714 return RISCVAsmParser::Match_InvalidUImm4Plus1;
4715 break;
4716 }
4717 case MCK_UImm5Plus1: {
4718 DiagnosticPredicate DP(Operand.isUImm5Plus1());
4719 if (DP.isMatch())
4720 return MCTargetAsmParser::Match_Success;
4721 if (DP.isNearMatch())
4722 return RISCVAsmParser::Match_InvalidUImm5Plus1;
4723 break;
4724 }
4725 case MCK_UImm6Plus1: {
4726 DiagnosticPredicate DP(Operand.isUImm6Plus1());
4727 if (DP.isMatch())
4728 return MCTargetAsmParser::Match_Success;
4729 if (DP.isNearMatch())
4730 return RISCVAsmParser::Match_InvalidUImm6Plus1;
4731 break;
4732 }
4733 case MCK_SImm6: {
4734 DiagnosticPredicate DP(Operand.isSImm6());
4735 if (DP.isMatch())
4736 return MCTargetAsmParser::Match_Success;
4737 if (DP.isNearMatch())
4738 return RISCVAsmParser::Match_InvalidSImm6;
4739 break;
4740 }
4741 case MCK_SImm6NonZero: {
4742 DiagnosticPredicate DP(Operand.isSImm6NonZero());
4743 if (DP.isMatch())
4744 return MCTargetAsmParser::Match_Success;
4745 if (DP.isNearMatch())
4746 return RISCVAsmParser::Match_InvalidSImm6NonZero;
4747 break;
4748 }
4749 case MCK_UImm7Lsb00: {
4750 DiagnosticPredicate DP(Operand.isUImm7Lsb00());
4751 if (DP.isMatch())
4752 return MCTargetAsmParser::Match_Success;
4753 if (DP.isNearMatch())
4754 return RISCVAsmParser::Match_InvalidUImm7Lsb00;
4755 break;
4756 }
4757 case MCK_UImm8Lsb00: {
4758 DiagnosticPredicate DP(Operand.isUImm8Lsb00());
4759 if (DP.isMatch())
4760 return MCTargetAsmParser::Match_Success;
4761 if (DP.isNearMatch())
4762 return RISCVAsmParser::Match_InvalidUImm8Lsb00;
4763 break;
4764 }
4765 case MCK_UImm8Lsb000: {
4766 DiagnosticPredicate DP(Operand.isUImm8Lsb000());
4767 if (DP.isMatch())
4768 return MCTargetAsmParser::Match_Success;
4769 if (DP.isNearMatch())
4770 return RISCVAsmParser::Match_InvalidUImm8Lsb000;
4771 break;
4772 }
4773 case MCK_BareSImm9Lsb0: {
4774 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<9>());
4775 if (DP.isMatch())
4776 return MCTargetAsmParser::Match_Success;
4777 if (DP.isNearMatch())
4778 return RISCVAsmParser::Match_InvalidBareSImm9Lsb0;
4779 break;
4780 }
4781 case MCK_UImm9Lsb000: {
4782 DiagnosticPredicate DP(Operand.isUImm9Lsb000());
4783 if (DP.isMatch())
4784 return MCTargetAsmParser::Match_Success;
4785 if (DP.isNearMatch())
4786 return RISCVAsmParser::Match_InvalidUImm9Lsb000;
4787 break;
4788 }
4789 case MCK_UImm10Lsb00NonZero: {
4790 DiagnosticPredicate DP(Operand.isUImm10Lsb00NonZero());
4791 if (DP.isMatch())
4792 return MCTargetAsmParser::Match_Success;
4793 if (DP.isNearMatch())
4794 return RISCVAsmParser::Match_InvalidUImm10Lsb00NonZero;
4795 break;
4796 }
4797 case MCK_SImm10Lsb0000NonZero: {
4798 DiagnosticPredicate DP(Operand.isSImm10Lsb0000NonZero());
4799 if (DP.isMatch())
4800 return MCTargetAsmParser::Match_Success;
4801 if (DP.isNearMatch())
4802 return RISCVAsmParser::Match_InvalidSImm10Lsb0000NonZero;
4803 break;
4804 }
4805 case MCK_BareSImm12Lsb0: {
4806 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<12>());
4807 if (DP.isMatch())
4808 return MCTargetAsmParser::Match_Success;
4809 if (DP.isNearMatch())
4810 return RISCVAsmParser::Match_InvalidBareSImm12Lsb0;
4811 break;
4812 }
4813 case MCK_UImm2Lsb0: {
4814 DiagnosticPredicate DP(Operand.isUImm2Lsb0());
4815 if (DP.isMatch())
4816 return MCTargetAsmParser::Match_Success;
4817 if (DP.isNearMatch())
4818 return RISCVAsmParser::Match_InvalidUImm2Lsb0;
4819 break;
4820 }
4821 case MCK_UImm8GE32: {
4822 DiagnosticPredicate DP(Operand.isUImm8GE32());
4823 if (DP.isMatch())
4824 return MCTargetAsmParser::Match_Success;
4825 if (DP.isNearMatch())
4826 return RISCVAsmParser::Match_InvalidUImm8GE32;
4827 break;
4828 }
4829 case MCK_UImm7EqXLen: {
4830 DiagnosticPredicate DP(Operand.isUImm7EqXLen());
4831 if (DP.isMatch())
4832 return MCTargetAsmParser::Match_Success;
4833 if (DP.isNearMatch())
4834 return RISCVAsmParser::Match_InvalidUImm7EqXLen;
4835 break;
4836 }
4837 case MCK_UImm5Lsb0: {
4838 DiagnosticPredicate DP(Operand.isUImm5Lsb0());
4839 if (DP.isMatch())
4840 return MCTargetAsmParser::Match_Success;
4841 if (DP.isNearMatch())
4842 return RISCVAsmParser::Match_InvalidUImm5Lsb0;
4843 break;
4844 }
4845 case MCK_UImm6Lsb0: {
4846 DiagnosticPredicate DP(Operand.isUImm6Lsb0());
4847 if (DP.isMatch())
4848 return MCTargetAsmParser::Match_Success;
4849 if (DP.isNearMatch())
4850 return RISCVAsmParser::Match_InvalidUImm6Lsb0;
4851 break;
4852 }
4853 case MCK_UImm5NonZero: {
4854 DiagnosticPredicate DP(Operand.isUImm5NonZero());
4855 if (DP.isMatch())
4856 return MCTargetAsmParser::Match_Success;
4857 if (DP.isNearMatch())
4858 return RISCVAsmParser::Match_InvalidUImm5NonZero;
4859 break;
4860 }
4861 case MCK_UImm5GT3: {
4862 DiagnosticPredicate DP(Operand.isUImm5GT3());
4863 if (DP.isMatch())
4864 return MCTargetAsmParser::Match_Success;
4865 if (DP.isNearMatch())
4866 return RISCVAsmParser::Match_InvalidUImm5GT3;
4867 break;
4868 }
4869 case MCK_UImm5GE6Plus1: {
4870 DiagnosticPredicate DP(Operand.isUImm5GE6Plus1());
4871 if (DP.isMatch())
4872 return MCTargetAsmParser::Match_Success;
4873 if (DP.isNearMatch())
4874 return RISCVAsmParser::Match_InvalidUImm5GE6Plus1;
4875 break;
4876 }
4877 case MCK_UImm5Slist: {
4878 DiagnosticPredicate DP(Operand.isUImm5Slist());
4879 if (DP.isMatch())
4880 return MCTargetAsmParser::Match_Success;
4881 if (DP.isNearMatch())
4882 return RISCVAsmParser::Match_InvalidUImm5Slist;
4883 break;
4884 }
4885 case MCK_UImm10: {
4886 DiagnosticPredicate DP(Operand.isUImm10());
4887 if (DP.isMatch())
4888 return MCTargetAsmParser::Match_Success;
4889 if (DP.isNearMatch())
4890 return RISCVAsmParser::Match_InvalidUImm10;
4891 break;
4892 }
4893 case MCK_UImm11: {
4894 DiagnosticPredicate DP(Operand.isUImm11());
4895 if (DP.isMatch())
4896 return MCTargetAsmParser::Match_Success;
4897 if (DP.isNearMatch())
4898 return RISCVAsmParser::Match_InvalidUImm11;
4899 break;
4900 }
4901 case MCK_UImm14Lsb00: {
4902 DiagnosticPredicate DP(Operand.isUImm14Lsb00());
4903 if (DP.isMatch())
4904 return MCTargetAsmParser::Match_Success;
4905 if (DP.isNearMatch())
4906 return RISCVAsmParser::Match_InvalidUImm14Lsb00;
4907 break;
4908 }
4909 case MCK_UImm16NonZero: {
4910 DiagnosticPredicate DP(Operand.isUImm16NonZero());
4911 if (DP.isMatch())
4912 return MCTargetAsmParser::Match_Success;
4913 if (DP.isNearMatch())
4914 return RISCVAsmParser::Match_InvalidUImm16NonZero;
4915 break;
4916 }
4917 case MCK_SImm5NonZero: {
4918 DiagnosticPredicate DP(Operand.isSImm5NonZero());
4919 if (DP.isMatch())
4920 return MCTargetAsmParser::Match_Success;
4921 if (DP.isNearMatch())
4922 return RISCVAsmParser::Match_InvalidSImm5NonZero;
4923 break;
4924 }
4925 case MCK_SImm11: {
4926 DiagnosticPredicate DP(Operand.isSImm11());
4927 if (DP.isMatch())
4928 return MCTargetAsmParser::Match_Success;
4929 if (DP.isNearMatch())
4930 return RISCVAsmParser::Match_InvalidSImm11;
4931 break;
4932 }
4933 case MCK_SImm16: {
4934 DiagnosticPredicate DP(Operand.isSImm16());
4935 if (DP.isMatch())
4936 return MCTargetAsmParser::Match_Success;
4937 if (DP.isNearMatch())
4938 return RISCVAsmParser::Match_InvalidSImm16;
4939 break;
4940 }
4941 case MCK_SImm16NonZero: {
4942 DiagnosticPredicate DP(Operand.isSImm16NonZero());
4943 if (DP.isMatch())
4944 return MCTargetAsmParser::Match_Success;
4945 if (DP.isNearMatch())
4946 return RISCVAsmParser::Match_InvalidSImm16NonZero;
4947 break;
4948 }
4949 case MCK_SImm20LI: {
4950 DiagnosticPredicate DP(Operand.isSImm20LI());
4951 if (DP.isMatch())
4952 return MCTargetAsmParser::Match_Success;
4953 if (DP.isNearMatch())
4954 return RISCVAsmParser::Match_InvalidSImm20LI;
4955 break;
4956 }
4957 case MCK_SImm26: {
4958 DiagnosticPredicate DP(Operand.isSImm26());
4959 if (DP.isMatch())
4960 return MCTargetAsmParser::Match_Success;
4961 if (DP.isNearMatch())
4962 return RISCVAsmParser::Match_InvalidSImm26;
4963 break;
4964 }
4965 case MCK_BareSImm32: {
4966 DiagnosticPredicate DP(Operand.isBareSimmN<32>());
4967 if (DP.isMatch())
4968 return MCTargetAsmParser::Match_Success;
4969 if (DP.isNearMatch())
4970 return RISCVAsmParser::Match_InvalidBareSImm32;
4971 break;
4972 }
4973 case MCK_BareSImm32Lsb0: {
4974 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<32>());
4975 if (DP.isMatch())
4976 return MCTargetAsmParser::Match_Success;
4977 if (DP.isNearMatch())
4978 return RISCVAsmParser::Match_InvalidBareSImm32Lsb0;
4979 break;
4980 }
4981 case MCK_UImm7Lsb000: {
4982 DiagnosticPredicate DP(Operand.isUImm7Lsb000());
4983 if (DP.isMatch())
4984 return MCTargetAsmParser::Match_Success;
4985 if (DP.isNearMatch())
4986 return RISCVAsmParser::Match_InvalidUImm7Lsb000;
4987 break;
4988 }
4989 case MCK_UImm9: {
4990 DiagnosticPredicate DP(Operand.isUImm9());
4991 if (DP.isMatch())
4992 return MCTargetAsmParser::Match_Success;
4993 if (DP.isNearMatch())
4994 return RISCVAsmParser::Match_InvalidUImm9;
4995 break;
4996 }
4997 case MCK_BareSImm11Lsb0: {
4998 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<11>());
4999 if (DP.isMatch())
5000 return MCTargetAsmParser::Match_Success;
5001 if (DP.isNearMatch())
5002 return RISCVAsmParser::Match_InvalidBareSImm11Lsb0;
5003 break;
5004 }
5005 case MCK_SImm18: {
5006 DiagnosticPredicate DP(Operand.isSImm18());
5007 if (DP.isMatch())
5008 return MCTargetAsmParser::Match_Success;
5009 if (DP.isNearMatch())
5010 return RISCVAsmParser::Match_InvalidSImm18;
5011 break;
5012 }
5013 case MCK_SImm18Lsb0: {
5014 DiagnosticPredicate DP(Operand.isSImm18Lsb0());
5015 if (DP.isMatch())
5016 return MCTargetAsmParser::Match_Success;
5017 if (DP.isNearMatch())
5018 return RISCVAsmParser::Match_InvalidSImm18Lsb0;
5019 break;
5020 }
5021 case MCK_SImm19Lsb00: {
5022 DiagnosticPredicate DP(Operand.isSImm19Lsb00());
5023 if (DP.isMatch())
5024 return MCTargetAsmParser::Match_Success;
5025 if (DP.isNearMatch())
5026 return RISCVAsmParser::Match_InvalidSImm19Lsb00;
5027 break;
5028 }
5029 case MCK_SImm20Lsb000: {
5030 DiagnosticPredicate DP(Operand.isSImm20Lsb000());
5031 if (DP.isMatch())
5032 return MCTargetAsmParser::Match_Success;
5033 if (DP.isNearMatch())
5034 return RISCVAsmParser::Match_InvalidSImm20Lsb000;
5035 break;
5036 }
5037 case MCK_SImm10: {
5038 DiagnosticPredicate DP(Operand.isSImm10());
5039 if (DP.isMatch())
5040 return MCTargetAsmParser::Match_Success;
5041 if (DP.isNearMatch())
5042 return RISCVAsmParser::Match_InvalidSImm10;
5043 break;
5044 }
5045 } // end switch (Kind)
5046
5047 if (Operand.isReg()) {
5048 static constexpr uint16_t Table[RISCV::NUM_TARGET_REGS] = {
5049 InvalidMatchClass,
5050 InvalidMatchClass,
5051 InvalidMatchClass,
5052 InvalidMatchClass,
5053 MCK_anonymous_14663,
5054 InvalidMatchClass,
5055 MCK_VCSR,
5056 MCK_VCSR,
5057 MCK_VCSR,
5058 InvalidMatchClass,
5059 InvalidMatchClass,
5060 MCK_GPRAll,
5061 MCK_MR0,
5062 MCK_MR,
5063 MCK_MR,
5064 MCK_MR,
5065 MCK_MR,
5066 MCK_MR,
5067 MCK_MR,
5068 MCK_MR,
5069 MCK_TRM4,
5070 MCK_TR,
5071 MCK_TRM2,
5072 MCK_TR,
5073 MCK_TRM4,
5074 MCK_TR,
5075 MCK_TRM2,
5076 MCK_TR,
5077 MCK_TRM4,
5078 MCK_TR,
5079 MCK_TRM2,
5080 MCK_TR,
5081 MCK_TRM4,
5082 MCK_TR,
5083 MCK_TRM2,
5084 MCK_TR,
5085 MCK_VMV0,
5086 MCK_VRNoV0,
5087 MCK_VRNoV0,
5088 MCK_VRNoV0,
5089 MCK_VRNoV0,
5090 MCK_VRNoV0,
5091 MCK_VRNoV0,
5092 MCK_VRNoV0,
5093 MCK_VRNoV0,
5094 MCK_VRNoV0,
5095 MCK_VRNoV0,
5096 MCK_VRNoV0,
5097 MCK_VRNoV0,
5098 MCK_VRNoV0,
5099 MCK_VRNoV0,
5100 MCK_VRNoV0,
5101 MCK_VRNoV0,
5102 MCK_VRNoV0,
5103 MCK_VRNoV0,
5104 MCK_VRNoV0,
5105 MCK_VRNoV0,
5106 MCK_VRNoV0,
5107 MCK_VRNoV0,
5108 MCK_VRNoV0,
5109 MCK_VRNoV0,
5110 MCK_VRNoV0,
5111 MCK_VRNoV0,
5112 MCK_VRNoV0,
5113 MCK_VRNoV0,
5114 MCK_VRNoV0,
5115 MCK_VRNoV0,
5116 MCK_VRNoV0,
5117 MCK_GPRX0,
5118 MCK_GPRX1,
5119 MCK_SP,
5120 MCK_Reg17,
5121 MCK_Reg17,
5122 MCK_GPRX5,
5123 MCK_Reg28,
5124 MCK_GPRX7,
5125 MCK_Reg31,
5126 MCK_Reg31,
5127 MCK_Reg34,
5128 MCK_Reg34,
5129 MCK_Reg34,
5130 MCK_Reg34,
5131 MCK_Reg34,
5132 MCK_Reg34,
5133 MCK_Reg28,
5134 MCK_Reg28,
5135 MCK_SR07,
5136 MCK_SR07,
5137 MCK_SR07,
5138 MCK_SR07,
5139 MCK_SR07,
5140 MCK_SR07,
5141 MCK_Reg26,
5142 MCK_Reg26,
5143 MCK_Reg26,
5144 MCK_Reg26,
5145 MCK_Reg28,
5146 MCK_Reg28,
5147 MCK_Reg28,
5148 MCK_GPRTCNonX7,
5149 MCK_FPR64,
5150 MCK_FPR64,
5151 MCK_FPR64,
5152 MCK_FPR64,
5153 MCK_FPR64,
5154 MCK_FPR64,
5155 MCK_FPR64,
5156 MCK_FPR64,
5157 MCK_FPR64C,
5158 MCK_FPR64C,
5159 MCK_FPR64C,
5160 MCK_FPR64C,
5161 MCK_FPR64C,
5162 MCK_FPR64C,
5163 MCK_FPR64C,
5164 MCK_FPR64C,
5165 MCK_FPR64,
5166 MCK_FPR64,
5167 MCK_FPR64,
5168 MCK_FPR64,
5169 MCK_FPR64,
5170 MCK_FPR64,
5171 MCK_FPR64,
5172 MCK_FPR64,
5173 MCK_FPR64,
5174 MCK_FPR64,
5175 MCK_FPR64,
5176 MCK_FPR64,
5177 MCK_FPR64,
5178 MCK_FPR64,
5179 MCK_FPR64,
5180 MCK_FPR64,
5181 MCK_FPR32,
5182 MCK_FPR32,
5183 MCK_FPR32,
5184 MCK_FPR32,
5185 MCK_FPR32,
5186 MCK_FPR32,
5187 MCK_FPR32,
5188 MCK_FPR32,
5189 MCK_FPR32C,
5190 MCK_FPR32C,
5191 MCK_FPR32C,
5192 MCK_FPR32C,
5193 MCK_FPR32C,
5194 MCK_FPR32C,
5195 MCK_FPR32C,
5196 MCK_FPR32C,
5197 MCK_FPR32,
5198 MCK_FPR32,
5199 MCK_FPR32,
5200 MCK_FPR32,
5201 MCK_FPR32,
5202 MCK_FPR32,
5203 MCK_FPR32,
5204 MCK_FPR32,
5205 MCK_FPR32,
5206 MCK_FPR32,
5207 MCK_FPR32,
5208 MCK_FPR32,
5209 MCK_FPR32,
5210 MCK_FPR32,
5211 MCK_FPR32,
5212 MCK_FPR32,
5213 MCK_FPR16,
5214 MCK_FPR16,
5215 MCK_FPR16,
5216 MCK_FPR16,
5217 MCK_FPR16,
5218 MCK_FPR16,
5219 MCK_FPR16,
5220 MCK_FPR16,
5221 MCK_FPR16C,
5222 MCK_FPR16C,
5223 MCK_FPR16C,
5224 MCK_FPR16C,
5225 MCK_FPR16C,
5226 MCK_FPR16C,
5227 MCK_FPR16C,
5228 MCK_FPR16C,
5229 MCK_FPR16,
5230 MCK_FPR16,
5231 MCK_FPR16,
5232 MCK_FPR16,
5233 MCK_FPR16,
5234 MCK_FPR16,
5235 MCK_FPR16,
5236 MCK_FPR16,
5237 MCK_FPR16,
5238 MCK_FPR16,
5239 MCK_FPR16,
5240 MCK_FPR16,
5241 MCK_FPR16,
5242 MCK_FPR16,
5243 MCK_FPR16,
5244 MCK_FPR16,
5245 MCK_FPR128,
5246 MCK_FPR128,
5247 MCK_FPR128,
5248 MCK_FPR128,
5249 MCK_FPR128,
5250 MCK_FPR128,
5251 MCK_FPR128,
5252 MCK_FPR128,
5253 MCK_Reg90,
5254 MCK_Reg90,
5255 MCK_Reg90,
5256 MCK_Reg90,
5257 MCK_Reg90,
5258 MCK_Reg90,
5259 MCK_Reg90,
5260 MCK_Reg90,
5261 MCK_FPR128,
5262 MCK_FPR128,
5263 MCK_FPR128,
5264 MCK_FPR128,
5265 MCK_FPR128,
5266 MCK_FPR128,
5267 MCK_FPR128,
5268 MCK_FPR128,
5269 MCK_FPR128,
5270 MCK_FPR128,
5271 MCK_FPR128,
5272 MCK_FPR128,
5273 MCK_FPR128,
5274 MCK_FPR128,
5275 MCK_FPR128,
5276 MCK_FPR128,
5277 MCK_GPRF16X0,
5278 MCK_GPRF16NoX0,
5279 MCK_GPRF16NoX0,
5280 MCK_GPRF16NoX0,
5281 MCK_GPRF16NoX0,
5282 MCK_GPRF16NoX0,
5283 MCK_GPRF16NoX0,
5284 MCK_GPRF16NoX0,
5285 MCK_GPRF16C,
5286 MCK_GPRF16C,
5287 MCK_GPRF16C,
5288 MCK_GPRF16C,
5289 MCK_GPRF16C,
5290 MCK_GPRF16C,
5291 MCK_GPRF16C,
5292 MCK_GPRF16C,
5293 MCK_GPRF16NoX0,
5294 MCK_GPRF16NoX0,
5295 MCK_GPRF16NoX0,
5296 MCK_GPRF16NoX0,
5297 MCK_GPRF16NoX0,
5298 MCK_GPRF16NoX0,
5299 MCK_GPRF16NoX0,
5300 MCK_GPRF16NoX0,
5301 MCK_GPRF16NoX0,
5302 MCK_GPRF16NoX0,
5303 MCK_GPRF16NoX0,
5304 MCK_GPRF16NoX0,
5305 MCK_GPRF16NoX0,
5306 MCK_GPRF16NoX0,
5307 MCK_GPRF16NoX0,
5308 MCK_GPRF16NoX0,
5309 MCK_Reg61,
5310 MCK_GPRF32X0,
5311 MCK_GPRF32NoX0,
5312 MCK_GPRF32NoX0,
5313 MCK_GPRF32NoX0,
5314 MCK_GPRF32NoX0,
5315 MCK_GPRF32NoX0,
5316 MCK_GPRF32NoX0,
5317 MCK_GPRF32NoX0,
5318 MCK_GPRF32C,
5319 MCK_GPRF32C,
5320 MCK_GPRF32C,
5321 MCK_GPRF32C,
5322 MCK_GPRF32C,
5323 MCK_GPRF32C,
5324 MCK_GPRF32C,
5325 MCK_GPRF32C,
5326 MCK_GPRF32NoX0,
5327 MCK_GPRF32NoX0,
5328 MCK_GPRF32NoX0,
5329 MCK_GPRF32NoX0,
5330 MCK_GPRF32NoX0,
5331 MCK_GPRF32NoX0,
5332 MCK_GPRF32NoX0,
5333 MCK_GPRF32NoX0,
5334 MCK_GPRF32NoX0,
5335 MCK_GPRF32NoX0,
5336 MCK_GPRF32NoX0,
5337 MCK_GPRF32NoX0,
5338 MCK_GPRF32NoX0,
5339 MCK_GPRF32NoX0,
5340 MCK_GPRF32NoX0,
5341 MCK_GPRF32NoX0,
5342 MCK_Reg35,
5343 MCK_Reg40,
5344 MCK_Reg46,
5345 MCK_Reg43,
5346 MCK_Reg43,
5347 MCK_Reg47,
5348 MCK_Reg54,
5349 MCK_Reg56,
5350 MCK_Reg57,
5351 MCK_Reg57,
5352 MCK_Reg60,
5353 MCK_Reg60,
5354 MCK_Reg60,
5355 MCK_Reg60,
5356 MCK_Reg60,
5357 MCK_Reg60,
5358 MCK_Reg54,
5359 MCK_Reg54,
5360 MCK_Reg59,
5361 MCK_Reg59,
5362 MCK_Reg59,
5363 MCK_Reg59,
5364 MCK_Reg59,
5365 MCK_Reg59,
5366 MCK_Reg52,
5367 MCK_Reg52,
5368 MCK_Reg52,
5369 MCK_Reg52,
5370 MCK_Reg54,
5371 MCK_Reg54,
5372 MCK_Reg54,
5373 MCK_Reg55,
5374 MCK_FPR256,
5375 MCK_FPR256,
5376 MCK_FPR256,
5377 MCK_FPR256,
5378 MCK_FPR256,
5379 MCK_FPR256,
5380 MCK_FPR256,
5381 MCK_FPR256,
5382 MCK_Reg109,
5383 MCK_Reg109,
5384 MCK_Reg109,
5385 MCK_Reg109,
5386 MCK_Reg109,
5387 MCK_Reg109,
5388 MCK_Reg109,
5389 MCK_Reg109,
5390 MCK_FPR256,
5391 MCK_FPR256,
5392 MCK_FPR256,
5393 MCK_FPR256,
5394 MCK_FPR256,
5395 MCK_FPR256,
5396 MCK_FPR256,
5397 MCK_FPR256,
5398 MCK_FPR256,
5399 MCK_FPR256,
5400 MCK_FPR256,
5401 MCK_FPR256,
5402 MCK_FPR256,
5403 MCK_FPR256,
5404 MCK_FPR256,
5405 MCK_FPR256,
5406 MCK_Reg94,
5407 MCK_Reg97,
5408 MCK_Reg100,
5409 MCK_VRM2NoV0,
5410 MCK_VRM2NoV0,
5411 MCK_VRM4NoV0,
5412 MCK_VRM2NoV0,
5413 MCK_VRM2NoV0,
5414 MCK_VRM4NoV0,
5415 MCK_VRM8NoV0,
5416 MCK_VRM2NoV0,
5417 MCK_VRM2NoV0,
5418 MCK_VRM4NoV0,
5419 MCK_VRM2NoV0,
5420 MCK_VRM2NoV0,
5421 MCK_VRM4NoV0,
5422 MCK_VRM8NoV0,
5423 MCK_VRM2NoV0,
5424 MCK_VRM2NoV0,
5425 MCK_VRM4NoV0,
5426 MCK_VRM2NoV0,
5427 MCK_VRM2NoV0,
5428 MCK_VRM4NoV0,
5429 MCK_VRM8NoV0,
5430 MCK_VRM2NoV0,
5431 MCK_VRM2NoV0,
5432 MCK_VRM4NoV0,
5433 MCK_VRM2NoV0,
5434 MCK_Reg64,
5435 MCK_Reg67,
5436 MCK_Reg70,
5437 MCK_Reg75,
5438 MCK_Reg80,
5439 MCK_Reg80,
5440 MCK_Reg80,
5441 MCK_Reg81,
5442 MCK_Reg79,
5443 MCK_Reg79,
5444 MCK_Reg79,
5445 MCK_Reg77,
5446 MCK_Reg77,
5447 MCK_Reg81,
5448 MCK_Reg82,
5449 MCK_VRN2M1NoV0,
5450 MCK_VRN2M1NoV0,
5451 MCK_VRN2M1NoV0,
5452 MCK_VRN2M1NoV0,
5453 MCK_VRN2M1NoV0,
5454 MCK_VRN2M1NoV0,
5455 MCK_VRN2M1NoV0,
5456 MCK_VRN2M1NoV0,
5457 MCK_VRN2M1NoV0,
5458 MCK_VRN2M1NoV0,
5459 MCK_VRN2M1NoV0,
5460 MCK_VRN2M1NoV0,
5461 MCK_VRN2M1NoV0,
5462 MCK_VRN2M1NoV0,
5463 MCK_VRN2M1NoV0,
5464 MCK_VRN2M1NoV0,
5465 MCK_VRN2M1NoV0,
5466 MCK_VRN2M1NoV0,
5467 MCK_VRN2M1NoV0,
5468 MCK_VRN2M1NoV0,
5469 MCK_VRN2M1NoV0,
5470 MCK_VRN2M1NoV0,
5471 MCK_VRN2M1NoV0,
5472 MCK_VRN2M1NoV0,
5473 MCK_VRN2M1NoV0,
5474 MCK_VRN2M1NoV0,
5475 MCK_VRN2M1NoV0,
5476 MCK_VRN2M1NoV0,
5477 MCK_VRN2M1NoV0,
5478 MCK_VRN2M1NoV0,
5479 MCK_Reg114,
5480 MCK_VRN2M2NoV0,
5481 MCK_VRN2M2NoV0,
5482 MCK_VRN2M2NoV0,
5483 MCK_VRN2M2NoV0,
5484 MCK_VRN2M2NoV0,
5485 MCK_VRN2M2NoV0,
5486 MCK_VRN2M2NoV0,
5487 MCK_VRN2M2NoV0,
5488 MCK_VRN2M2NoV0,
5489 MCK_VRN2M2NoV0,
5490 MCK_VRN2M2NoV0,
5491 MCK_VRN2M2NoV0,
5492 MCK_VRN2M2NoV0,
5493 MCK_VRN2M2NoV0,
5494 MCK_Reg117,
5495 MCK_VRN2M4NoV0,
5496 MCK_VRN2M4NoV0,
5497 MCK_VRN2M4NoV0,
5498 MCK_VRN2M4NoV0,
5499 MCK_VRN2M4NoV0,
5500 MCK_VRN2M4NoV0,
5501 MCK_Reg120,
5502 MCK_VRN3M1NoV0,
5503 MCK_VRN3M1NoV0,
5504 MCK_VRN3M1NoV0,
5505 MCK_VRN3M1NoV0,
5506 MCK_VRN3M1NoV0,
5507 MCK_VRN3M1NoV0,
5508 MCK_VRN3M1NoV0,
5509 MCK_VRN3M1NoV0,
5510 MCK_VRN3M1NoV0,
5511 MCK_VRN3M1NoV0,
5512 MCK_VRN3M1NoV0,
5513 MCK_VRN3M1NoV0,
5514 MCK_VRN3M1NoV0,
5515 MCK_VRN3M1NoV0,
5516 MCK_VRN3M1NoV0,
5517 MCK_VRN3M1NoV0,
5518 MCK_VRN3M1NoV0,
5519 MCK_VRN3M1NoV0,
5520 MCK_VRN3M1NoV0,
5521 MCK_VRN3M1NoV0,
5522 MCK_VRN3M1NoV0,
5523 MCK_VRN3M1NoV0,
5524 MCK_VRN3M1NoV0,
5525 MCK_VRN3M1NoV0,
5526 MCK_VRN3M1NoV0,
5527 MCK_VRN3M1NoV0,
5528 MCK_VRN3M1NoV0,
5529 MCK_VRN3M1NoV0,
5530 MCK_VRN3M1NoV0,
5531 MCK_Reg123,
5532 MCK_VRN3M2NoV0,
5533 MCK_VRN3M2NoV0,
5534 MCK_VRN3M2NoV0,
5535 MCK_VRN3M2NoV0,
5536 MCK_VRN3M2NoV0,
5537 MCK_VRN3M2NoV0,
5538 MCK_VRN3M2NoV0,
5539 MCK_VRN3M2NoV0,
5540 MCK_VRN3M2NoV0,
5541 MCK_VRN3M2NoV0,
5542 MCK_VRN3M2NoV0,
5543 MCK_VRN3M2NoV0,
5544 MCK_VRN3M2NoV0,
5545 MCK_Reg126,
5546 MCK_VRN4M1NoV0,
5547 MCK_VRN4M1NoV0,
5548 MCK_VRN4M1NoV0,
5549 MCK_VRN4M1NoV0,
5550 MCK_VRN4M1NoV0,
5551 MCK_VRN4M1NoV0,
5552 MCK_VRN4M1NoV0,
5553 MCK_VRN4M1NoV0,
5554 MCK_VRN4M1NoV0,
5555 MCK_VRN4M1NoV0,
5556 MCK_VRN4M1NoV0,
5557 MCK_VRN4M1NoV0,
5558 MCK_VRN4M1NoV0,
5559 MCK_VRN4M1NoV0,
5560 MCK_VRN4M1NoV0,
5561 MCK_VRN4M1NoV0,
5562 MCK_VRN4M1NoV0,
5563 MCK_VRN4M1NoV0,
5564 MCK_VRN4M1NoV0,
5565 MCK_VRN4M1NoV0,
5566 MCK_VRN4M1NoV0,
5567 MCK_VRN4M1NoV0,
5568 MCK_VRN4M1NoV0,
5569 MCK_VRN4M1NoV0,
5570 MCK_VRN4M1NoV0,
5571 MCK_VRN4M1NoV0,
5572 MCK_VRN4M1NoV0,
5573 MCK_VRN4M1NoV0,
5574 MCK_Reg129,
5575 MCK_VRN4M2NoV0,
5576 MCK_VRN4M2NoV0,
5577 MCK_VRN4M2NoV0,
5578 MCK_VRN4M2NoV0,
5579 MCK_VRN4M2NoV0,
5580 MCK_VRN4M2NoV0,
5581 MCK_VRN4M2NoV0,
5582 MCK_VRN4M2NoV0,
5583 MCK_VRN4M2NoV0,
5584 MCK_VRN4M2NoV0,
5585 MCK_VRN4M2NoV0,
5586 MCK_VRN4M2NoV0,
5587 MCK_Reg132,
5588 MCK_VRN5M1NoV0,
5589 MCK_VRN5M1NoV0,
5590 MCK_VRN5M1NoV0,
5591 MCK_VRN5M1NoV0,
5592 MCK_VRN5M1NoV0,
5593 MCK_VRN5M1NoV0,
5594 MCK_VRN5M1NoV0,
5595 MCK_VRN5M1NoV0,
5596 MCK_VRN5M1NoV0,
5597 MCK_VRN5M1NoV0,
5598 MCK_VRN5M1NoV0,
5599 MCK_VRN5M1NoV0,
5600 MCK_VRN5M1NoV0,
5601 MCK_VRN5M1NoV0,
5602 MCK_VRN5M1NoV0,
5603 MCK_VRN5M1NoV0,
5604 MCK_VRN5M1NoV0,
5605 MCK_VRN5M1NoV0,
5606 MCK_VRN5M1NoV0,
5607 MCK_VRN5M1NoV0,
5608 MCK_VRN5M1NoV0,
5609 MCK_VRN5M1NoV0,
5610 MCK_VRN5M1NoV0,
5611 MCK_VRN5M1NoV0,
5612 MCK_VRN5M1NoV0,
5613 MCK_VRN5M1NoV0,
5614 MCK_VRN5M1NoV0,
5615 MCK_Reg135,
5616 MCK_VRN6M1NoV0,
5617 MCK_VRN6M1NoV0,
5618 MCK_VRN6M1NoV0,
5619 MCK_VRN6M1NoV0,
5620 MCK_VRN6M1NoV0,
5621 MCK_VRN6M1NoV0,
5622 MCK_VRN6M1NoV0,
5623 MCK_VRN6M1NoV0,
5624 MCK_VRN6M1NoV0,
5625 MCK_VRN6M1NoV0,
5626 MCK_VRN6M1NoV0,
5627 MCK_VRN6M1NoV0,
5628 MCK_VRN6M1NoV0,
5629 MCK_VRN6M1NoV0,
5630 MCK_VRN6M1NoV0,
5631 MCK_VRN6M1NoV0,
5632 MCK_VRN6M1NoV0,
5633 MCK_VRN6M1NoV0,
5634 MCK_VRN6M1NoV0,
5635 MCK_VRN6M1NoV0,
5636 MCK_VRN6M1NoV0,
5637 MCK_VRN6M1NoV0,
5638 MCK_VRN6M1NoV0,
5639 MCK_VRN6M1NoV0,
5640 MCK_VRN6M1NoV0,
5641 MCK_VRN6M1NoV0,
5642 MCK_Reg138,
5643 MCK_VRN7M1NoV0,
5644 MCK_VRN7M1NoV0,
5645 MCK_VRN7M1NoV0,
5646 MCK_VRN7M1NoV0,
5647 MCK_VRN7M1NoV0,
5648 MCK_VRN7M1NoV0,
5649 MCK_VRN7M1NoV0,
5650 MCK_VRN7M1NoV0,
5651 MCK_VRN7M1NoV0,
5652 MCK_VRN7M1NoV0,
5653 MCK_VRN7M1NoV0,
5654 MCK_VRN7M1NoV0,
5655 MCK_VRN7M1NoV0,
5656 MCK_VRN7M1NoV0,
5657 MCK_VRN7M1NoV0,
5658 MCK_VRN7M1NoV0,
5659 MCK_VRN7M1NoV0,
5660 MCK_VRN7M1NoV0,
5661 MCK_VRN7M1NoV0,
5662 MCK_VRN7M1NoV0,
5663 MCK_VRN7M1NoV0,
5664 MCK_VRN7M1NoV0,
5665 MCK_VRN7M1NoV0,
5666 MCK_VRN7M1NoV0,
5667 MCK_VRN7M1NoV0,
5668 MCK_Reg141,
5669 MCK_VRN8M1NoV0,
5670 MCK_VRN8M1NoV0,
5671 MCK_VRN8M1NoV0,
5672 MCK_VRN8M1NoV0,
5673 MCK_VRN8M1NoV0,
5674 MCK_VRN8M1NoV0,
5675 MCK_VRN8M1NoV0,
5676 MCK_VRN8M1NoV0,
5677 MCK_VRN8M1NoV0,
5678 MCK_VRN8M1NoV0,
5679 MCK_VRN8M1NoV0,
5680 MCK_VRN8M1NoV0,
5681 MCK_VRN8M1NoV0,
5682 MCK_VRN8M1NoV0,
5683 MCK_VRN8M1NoV0,
5684 MCK_VRN8M1NoV0,
5685 MCK_VRN8M1NoV0,
5686 MCK_VRN8M1NoV0,
5687 MCK_VRN8M1NoV0,
5688 MCK_VRN8M1NoV0,
5689 MCK_VRN8M1NoV0,
5690 MCK_VRN8M1NoV0,
5691 MCK_VRN8M1NoV0,
5692 MCK_VRN8M1NoV0,
5693 MCK_Reg144,
5694 };
5695
5696 MCRegister Reg = Operand.getReg();
5697 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
5698 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
5699 getDiagKindFromRegisterClass(Kind);
5700 }
5701
5702 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
5703 return getDiagKindFromRegisterClass(Kind);
5704
5705 return MCTargetAsmParser::Match_InvalidOperand;
5706}
5707
5708#ifndef NDEBUG
5709const char *getMatchClassName(MatchClassKind Kind) {
5710 switch (Kind) {
5711 case InvalidMatchClass: return "InvalidMatchClass";
5712 case OptionalMatchClass: return "OptionalMatchClass";
5713 case MCK__40_: return "MCK__40_";
5714 case MCK__41_: return "MCK__41_";
5715 case MCK_Reg144: return "MCK_Reg144";
5716 case MCK_Reg141: return "MCK_Reg141";
5717 case MCK_Reg138: return "MCK_Reg138";
5718 case MCK_Reg135: return "MCK_Reg135";
5719 case MCK_Reg132: return "MCK_Reg132";
5720 case MCK_Reg129: return "MCK_Reg129";
5721 case MCK_Reg126: return "MCK_Reg126";
5722 case MCK_Reg123: return "MCK_Reg123";
5723 case MCK_Reg120: return "MCK_Reg120";
5724 case MCK_Reg117: return "MCK_Reg117";
5725 case MCK_Reg114: return "MCK_Reg114";
5726 case MCK_Reg100: return "MCK_Reg100";
5727 case MCK_Reg97: return "MCK_Reg97";
5728 case MCK_Reg94: return "MCK_Reg94";
5729 case MCK_Reg75: return "MCK_Reg75";
5730 case MCK_Reg70: return "MCK_Reg70";
5731 case MCK_Reg67: return "MCK_Reg67";
5732 case MCK_Reg64: return "MCK_Reg64";
5733 case MCK_Reg61: return "MCK_Reg61";
5734 case MCK_Reg56: return "MCK_Reg56";
5735 case MCK_Reg47: return "MCK_Reg47";
5736 case MCK_Reg46: return "MCK_Reg46";
5737 case MCK_Reg40: return "MCK_Reg40";
5738 case MCK_Reg35: return "MCK_Reg35";
5739 case MCK_GPRF16X0: return "MCK_GPRF16X0";
5740 case MCK_GPRF32X0: return "MCK_GPRF32X0";
5741 case MCK_GPRX0: return "MCK_GPRX0";
5742 case MCK_GPRX1: return "MCK_GPRX1";
5743 case MCK_GPRX5: return "MCK_GPRX5";
5744 case MCK_GPRX7: return "MCK_GPRX7";
5745 case MCK_MR0: return "MCK_MR0";
5746 case MCK_SP: return "MCK_SP";
5747 case MCK_VMV0: return "MCK_VMV0";
5748 case MCK_anonymous_14663: return "MCK_anonymous_14663";
5749 case MCK_Reg57: return "MCK_Reg57";
5750 case MCK_Reg45: return "MCK_Reg45";
5751 case MCK_Reg31: return "MCK_Reg31";
5752 case MCK_GPRX1X5: return "MCK_GPRX1X5";
5753 case MCK_Reg80: return "MCK_Reg80";
5754 case MCK_VCSR: return "MCK_VCSR";
5755 case MCK_VRM8NoV0: return "MCK_VRM8NoV0";
5756 case MCK_Reg79: return "MCK_Reg79";
5757 case MCK_GPRPairC: return "MCK_GPRPairC";
5758 case MCK_TRM4: return "MCK_TRM4";
5759 case MCK_VRM8: return "MCK_VRM8";
5760 case MCK_Reg81: return "MCK_Reg81";
5761 case MCK_Reg82: return "MCK_Reg82";
5762 case MCK_Reg73: return "MCK_Reg73";
5763 case MCK_Reg60: return "MCK_Reg60";
5764 case MCK_Reg34: return "MCK_Reg34";
5765 case MCK_VRN2M4NoV0: return "MCK_VRN2M4NoV0";
5766 case MCK_Reg74: return "MCK_Reg74";
5767 case MCK_VRM4NoV0: return "MCK_VRM4NoV0";
5768 case MCK_VRN2M4: return "MCK_VRN2M4";
5769 case MCK_Reg109: return "MCK_Reg109";
5770 case MCK_Reg90: return "MCK_Reg90";
5771 case MCK_Reg59: return "MCK_Reg59";
5772 case MCK_Reg58: return "MCK_Reg58";
5773 case MCK_FPR16C: return "MCK_FPR16C";
5774 case MCK_FPR32C: return "MCK_FPR32C";
5775 case MCK_FPR64C: return "MCK_FPR64C";
5776 case MCK_GPRC: return "MCK_GPRC";
5777 case MCK_GPRF16C: return "MCK_GPRF16C";
5778 case MCK_GPRF32C: return "MCK_GPRF32C";
5779 case MCK_MR: return "MCK_MR";
5780 case MCK_SR07: return "MCK_SR07";
5781 case MCK_TRM2: return "MCK_TRM2";
5782 case MCK_VRM4: return "MCK_VRM4";
5783 case MCK_Reg77: return "MCK_Reg77";
5784 case MCK_Reg78: return "MCK_Reg78";
5785 case MCK_Reg71: return "MCK_Reg71";
5786 case MCK_Reg54: return "MCK_Reg54";
5787 case MCK_Reg28: return "MCK_Reg28";
5788 case MCK_VRN4M2NoV0: return "MCK_VRN4M2NoV0";
5789 case MCK_Reg72: return "MCK_Reg72";
5790 case MCK_Reg68: return "MCK_Reg68";
5791 case MCK_Reg55: return "MCK_Reg55";
5792 case MCK_Reg50: return "MCK_Reg50";
5793 case MCK_Reg24: return "MCK_Reg24";
5794 case MCK_GPRTCNonX7: return "MCK_GPRTCNonX7";
5795 case MCK_VRN3M2NoV0: return "MCK_VRN3M2NoV0";
5796 case MCK_VRN4M2: return "MCK_VRN4M2";
5797 case MCK_Reg69: return "MCK_Reg69";
5798 case MCK_Reg65: return "MCK_Reg65";
5799 case MCK_Reg51: return "MCK_Reg51";
5800 case MCK_GPRTC: return "MCK_GPRTC";
5801 case MCK_VRN2M2NoV0: return "MCK_VRN2M2NoV0";
5802 case MCK_VRN3M2: return "MCK_VRN3M2";
5803 case MCK_Reg63: return "MCK_Reg63";
5804 case MCK_GPRPairNoX0: return "MCK_GPRPairNoX0";
5805 case MCK_VRM2NoV0: return "MCK_VRM2NoV0";
5806 case MCK_VRN2M2: return "MCK_VRN2M2";
5807 case MCK_GPRPair: return "MCK_GPRPair";
5808 case MCK_TR: return "MCK_TR";
5809 case MCK_VRM2: return "MCK_VRM2";
5810 case MCK_Reg52: return "MCK_Reg52";
5811 case MCK_Reg26: return "MCK_Reg26";
5812 case MCK_VRN8M1NoV0: return "MCK_VRN8M1NoV0";
5813 case MCK_Reg53: return "MCK_Reg53";
5814 case MCK_Reg48: return "MCK_Reg48";
5815 case MCK_Reg22: return "MCK_Reg22";
5816 case MCK_GPRJALRNonX7: return "MCK_GPRJALRNonX7";
5817 case MCK_VRN7M1NoV0: return "MCK_VRN7M1NoV0";
5818 case MCK_VRN8M1: return "MCK_VRN8M1";
5819 case MCK_Reg49: return "MCK_Reg49";
5820 case MCK_GPRJALR: return "MCK_GPRJALR";
5821 case MCK_VRN6M1NoV0: return "MCK_VRN6M1NoV0";
5822 case MCK_VRN7M1: return "MCK_VRN7M1";
5823 case MCK_VRN5M1NoV0: return "MCK_VRN5M1NoV0";
5824 case MCK_VRN6M1: return "MCK_VRN6M1";
5825 case MCK_VRN4M1NoV0: return "MCK_VRN4M1NoV0";
5826 case MCK_VRN5M1: return "MCK_VRN5M1";
5827 case MCK_Reg43: return "MCK_Reg43";
5828 case MCK_Reg17: return "MCK_Reg17";
5829 case MCK_VRN3M1NoV0: return "MCK_VRN3M1NoV0";
5830 case MCK_VRN4M1: return "MCK_VRN4M1";
5831 case MCK_Reg44: return "MCK_Reg44";
5832 case MCK_Reg41: return "MCK_Reg41";
5833 case MCK_Reg38: return "MCK_Reg38";
5834 case MCK_Reg15: return "MCK_Reg15";
5835 case MCK_Reg12: return "MCK_Reg12";
5836 case MCK_GPRNoX0X2: return "MCK_GPRNoX0X2";
5837 case MCK_VRN2M1NoV0: return "MCK_VRN2M1NoV0";
5838 case MCK_VRN3M1: return "MCK_VRN3M1";
5839 case MCK_Reg42: return "MCK_Reg42";
5840 case MCK_Reg39: return "MCK_Reg39";
5841 case MCK_Reg36: return "MCK_Reg36";
5842 case MCK_GPRF16NoX0: return "MCK_GPRF16NoX0";
5843 case MCK_GPRF32NoX0: return "MCK_GPRF32NoX0";
5844 case MCK_GPRNoX0: return "MCK_GPRNoX0";
5845 case MCK_GPRNoX2: return "MCK_GPRNoX2";
5846 case MCK_GPRNoX31: return "MCK_GPRNoX31";
5847 case MCK_VRN2M1: return "MCK_VRN2M1";
5848 case MCK_VRNoV0: return "MCK_VRNoV0";
5849 case MCK_FPR128: return "MCK_FPR128";
5850 case MCK_FPR16: return "MCK_FPR16";
5851 case MCK_FPR256: return "MCK_FPR256";
5852 case MCK_FPR32: return "MCK_FPR32";
5853 case MCK_FPR64: return "MCK_FPR64";
5854 case MCK_GPR: return "MCK_GPR";
5855 case MCK_GPRF16: return "MCK_GPRF16";
5856 case MCK_GPRF32: return "MCK_GPRF32";
5857 case MCK_VR: return "MCK_VR";
5858 case MCK_YGPR: return "MCK_YGPR";
5859 case MCK_GPRAll: return "MCK_GPRAll";
5860 case MCK_AnyRegCOperand: return "MCK_AnyRegCOperand";
5861 case MCK_AnyRegOperand: return "MCK_AnyRegOperand";
5862 case MCK_BareSymbol: return "MCK_BareSymbol";
5863 case MCK_BareSymbolQC_E_LI: return "MCK_BareSymbolQC_E_LI";
5864 case MCK_CLUIImm: return "MCK_CLUIImm";
5865 case MCK_CSRSystemRegister: return "MCK_CSRSystemRegister";
5866 case MCK_RegReg: return "MCK_RegReg";
5867 case MCK_CallSymbol: return "MCK_CallSymbol";
5868 case MCK_FRMArg: return "MCK_FRMArg";
5869 case MCK_FRMArgLegacy: return "MCK_FRMArgLegacy";
5870 case MCK_FenceArg: return "MCK_FenceArg";
5871 case MCK_GPRAsFPR16: return "MCK_GPRAsFPR16";
5872 case MCK_GPRAsFPR32: return "MCK_GPRAsFPR32";
5873 case MCK_GPRF64AsFPR: return "MCK_GPRF64AsFPR";
5874 case MCK_GPRPairAsFPR: return "MCK_GPRPairAsFPR";
5875 case MCK_GPRPairCRV32: return "MCK_GPRPairCRV32";
5876 case MCK_GPRPairNoX0RV32: return "MCK_GPRPairNoX0RV32";
5877 case MCK_GPRPairRV32: return "MCK_GPRPairRV32";
5878 case MCK_GPRPairRV64: return "MCK_GPRPairRV64";
5879 case MCK_Imm: return "MCK_Imm";
5880 case MCK_ImmFour: return "MCK_ImmFour";
5881 case MCK_ImmThree: return "MCK_ImmThree";
5882 case MCK_ImmZero: return "MCK_ImmZero";
5883 case MCK_InsnCDirectiveOpcode: return "MCK_InsnCDirectiveOpcode";
5884 case MCK_InsnDirectiveOpcode: return "MCK_InsnDirectiveOpcode";
5885 case MCK_LoadFPImm: return "MCK_LoadFPImm";
5886 case MCK_NegStackAdj: return "MCK_NegStackAdj";
5887 case MCK_PseudoJumpSymbol: return "MCK_PseudoJumpSymbol";
5888 case MCK_QCAccessSymbol: return "MCK_QCAccessSymbol";
5889 case MCK_RTZArg: return "MCK_RTZArg";
5890 case MCK_RegList: return "MCK_RegList";
5891 case MCK_RegListS0: return "MCK_RegListS0";
5892 case MCK_RnumArg: return "MCK_RnumArg";
5893 case MCK_SImm10PLI_H: return "MCK_SImm10PLI_H";
5894 case MCK_SImm10PLI_W: return "MCK_SImm10PLI_W";
5895 case MCK_SImm10PLUI: return "MCK_SImm10PLUI";
5896 case MCK_SImm8PLI_B: return "MCK_SImm8PLI_B";
5897 case MCK_SMTI8: return "MCK_SMTI8";
5898 case MCK_SMTVType: return "MCK_SMTVType";
5899 case MCK_BareSImm21Lsb0: return "MCK_BareSImm21Lsb0";
5900 case MCK_StackAdj: return "MCK_StackAdj";
5901 case MCK_TLSDESCCallSymbol: return "MCK_TLSDESCCallSymbol";
5902 case MCK_TPRelAddSymbol: return "MCK_TPRelAddSymbol";
5903 case MCK_TileLambda: return "MCK_TileLambda";
5904 case MCK_UImmLog2XLen: return "MCK_UImmLog2XLen";
5905 case MCK_UImmLog2XLenNonZero: return "MCK_UImmLog2XLenNonZero";
5906 case MCK_RVVMaskRegOpOperand: return "MCK_RVVMaskRegOpOperand";
5907 case MCK_RVVMaskCarryInRegOpOperand: return "MCK_RVVMaskCarryInRegOpOperand";
5908 case MCK_RVVScaleRegOpOperand: return "MCK_RVVScaleRegOpOperand";
5909 case MCK_XSfmmVType: return "MCK_XSfmmVType";
5910 case MCK_YBNDSWImm: return "MCK_YBNDSWImm";
5911 case MCK_ZeroOffsetMemOpOperand: return "MCK_ZeroOffsetMemOpOperand";
5912 case MCK_UImm1: return "MCK_UImm1";
5913 case MCK_UImm2: return "MCK_UImm2";
5914 case MCK_UImm3: return "MCK_UImm3";
5915 case MCK_UImm4: return "MCK_UImm4";
5916 case MCK_UImm5: return "MCK_UImm5";
5917 case MCK_UImm6: return "MCK_UImm6";
5918 case MCK_UImm7: return "MCK_UImm7";
5919 case MCK_UImm8: return "MCK_UImm8";
5920 case MCK_UImm16: return "MCK_UImm16";
5921 case MCK_UImm32: return "MCK_UImm32";
5922 case MCK_UImm48: return "MCK_UImm48";
5923 case MCK_UImm64: return "MCK_UImm64";
5924 case MCK_SImm12: return "MCK_SImm12";
5925 case MCK_SImm12LO: return "MCK_SImm12LO";
5926 case MCK_BareSImm13Lsb0: return "MCK_BareSImm13Lsb0";
5927 case MCK_UImm20: return "MCK_UImm20";
5928 case MCK_UImm20LUI: return "MCK_UImm20LUI";
5929 case MCK_UImm20AUIPC: return "MCK_UImm20AUIPC";
5930 case MCK_ImmXLenLI: return "MCK_ImmXLenLI";
5931 case MCK_ImmXLenLI_Restricted: return "MCK_ImmXLenLI_Restricted";
5932 case MCK_SImm12Lsb00000: return "MCK_SImm12Lsb00000";
5933 case MCK_Imm5Zibi: return "MCK_Imm5Zibi";
5934 case MCK_VTypeI10: return "MCK_VTypeI10";
5935 case MCK_VTypeI11: return "MCK_VTypeI11";
5936 case MCK_SImm5: return "MCK_SImm5";
5937 case MCK_SImm5Plus1: return "MCK_SImm5Plus1";
5938 case MCK_UImm4Plus1: return "MCK_UImm4Plus1";
5939 case MCK_UImm5Plus1: return "MCK_UImm5Plus1";
5940 case MCK_UImm6Plus1: return "MCK_UImm6Plus1";
5941 case MCK_SImm6: return "MCK_SImm6";
5942 case MCK_SImm6NonZero: return "MCK_SImm6NonZero";
5943 case MCK_UImm7Lsb00: return "MCK_UImm7Lsb00";
5944 case MCK_UImm8Lsb00: return "MCK_UImm8Lsb00";
5945 case MCK_UImm8Lsb000: return "MCK_UImm8Lsb000";
5946 case MCK_BareSImm9Lsb0: return "MCK_BareSImm9Lsb0";
5947 case MCK_UImm9Lsb000: return "MCK_UImm9Lsb000";
5948 case MCK_UImm10Lsb00NonZero: return "MCK_UImm10Lsb00NonZero";
5949 case MCK_SImm10Lsb0000NonZero: return "MCK_SImm10Lsb0000NonZero";
5950 case MCK_BareSImm12Lsb0: return "MCK_BareSImm12Lsb0";
5951 case MCK_UImm2Lsb0: return "MCK_UImm2Lsb0";
5952 case MCK_UImm8GE32: return "MCK_UImm8GE32";
5953 case MCK_UImm7EqXLen: return "MCK_UImm7EqXLen";
5954 case MCK_UImm5Lsb0: return "MCK_UImm5Lsb0";
5955 case MCK_UImm6Lsb0: return "MCK_UImm6Lsb0";
5956 case MCK_UImm5NonZero: return "MCK_UImm5NonZero";
5957 case MCK_UImm5GT3: return "MCK_UImm5GT3";
5958 case MCK_UImm5GE6Plus1: return "MCK_UImm5GE6Plus1";
5959 case MCK_UImm5Slist: return "MCK_UImm5Slist";
5960 case MCK_UImm10: return "MCK_UImm10";
5961 case MCK_UImm11: return "MCK_UImm11";
5962 case MCK_UImm14Lsb00: return "MCK_UImm14Lsb00";
5963 case MCK_UImm16NonZero: return "MCK_UImm16NonZero";
5964 case MCK_SImm5NonZero: return "MCK_SImm5NonZero";
5965 case MCK_SImm11: return "MCK_SImm11";
5966 case MCK_SImm16: return "MCK_SImm16";
5967 case MCK_SImm16NonZero: return "MCK_SImm16NonZero";
5968 case MCK_SImm20LI: return "MCK_SImm20LI";
5969 case MCK_SImm26: return "MCK_SImm26";
5970 case MCK_BareSImm32: return "MCK_BareSImm32";
5971 case MCK_BareSImm32Lsb0: return "MCK_BareSImm32Lsb0";
5972 case MCK_UImm7Lsb000: return "MCK_UImm7Lsb000";
5973 case MCK_UImm9: return "MCK_UImm9";
5974 case MCK_BareSImm11Lsb0: return "MCK_BareSImm11Lsb0";
5975 case MCK_SImm18: return "MCK_SImm18";
5976 case MCK_SImm18Lsb0: return "MCK_SImm18Lsb0";
5977 case MCK_SImm19Lsb00: return "MCK_SImm19Lsb00";
5978 case MCK_SImm20Lsb000: return "MCK_SImm20Lsb000";
5979 case MCK_SImm10: return "MCK_SImm10";
5980 case NumMatchClassKinds: return "NumMatchClassKinds";
5981 }
5982 llvm_unreachable("unhandled MatchClassKind!");
5983}
5984
5985#endif // NDEBUG
5986FeatureBitset RISCVAsmParser::
5987ComputeAvailableFeatures(const FeatureBitset &FB) const {
5988 FeatureBitset Features;
5989 if (FB[RISCV::FeatureStdExtZibi])
5990 Features.set(Feature_HasStdExtZibiBit);
5991 if (FB[RISCV::FeatureStdExtZicbom])
5992 Features.set(Feature_HasStdExtZicbomBit);
5993 if (FB[RISCV::FeatureStdExtZicbop])
5994 Features.set(Feature_HasStdExtZicbopBit);
5995 if (FB[RISCV::FeatureStdExtZicboz])
5996 Features.set(Feature_HasStdExtZicbozBit);
5997 if (FB[RISCV::FeatureStdExtZicsr])
5998 Features.set(Feature_HasStdExtZicsrBit);
5999 if (FB[RISCV::FeatureStdExtZicond])
6000 Features.set(Feature_HasStdExtZicondBit);
6001 if (FB[RISCV::FeatureStdExtZifencei])
6002 Features.set(Feature_HasStdExtZifenceiBit);
6003 if (FB[RISCV::FeatureStdExtZihintpause])
6004 Features.set(Feature_HasStdExtZihintpauseBit);
6005 if (FB[RISCV::FeatureStdExtZihintntl])
6006 Features.set(Feature_HasStdExtZihintntlBit);
6007 if (FB[RISCV::FeatureStdExtZimop])
6008 Features.set(Feature_HasStdExtZimopBit);
6009 if (FB[RISCV::FeatureStdExtZicfiss])
6010 Features.set(Feature_HasStdExtZicfissBit);
6011 if (FB[RISCV::FeatureStdExtZilsd])
6012 Features.set(Feature_HasStdExtZilsdBit);
6013 if (FB[RISCV::FeatureStdExtZmmul])
6014 Features.set(Feature_HasStdExtZmmulBit);
6015 if (FB[RISCV::FeatureStdExtM])
6016 Features.set(Feature_HasStdExtMBit);
6017 if (FB[RISCV::FeatureStdExtZaamo])
6018 Features.set(Feature_HasStdExtZaamoBit);
6019 if (FB[RISCV::FeatureStdExtZalrsc])
6020 Features.set(Feature_HasStdExtZalrscBit);
6021 if (FB[RISCV::FeatureStdExtA])
6022 Features.set(Feature_HasStdExtABit);
6023 if (FB[RISCV::FeatureStdExtZtso])
6024 Features.set(Feature_HasStdExtZtsoBit);
6025 if (FB[RISCV::FeatureStdExtZabha])
6026 Features.set(Feature_HasStdExtZabhaBit);
6027 if (FB[RISCV::FeatureStdExtZacas])
6028 Features.set(Feature_HasStdExtZacasBit);
6029 if (FB[RISCV::FeatureStdExtZalasr])
6030 Features.set(Feature_HasStdExtZalasrBit);
6031 if (FB[RISCV::FeatureStdExtZawrs])
6032 Features.set(Feature_HasStdExtZawrsBit);
6033 if (FB[RISCV::FeatureStdExtF])
6034 Features.set(Feature_HasStdExtFBit);
6035 if (FB[RISCV::FeatureStdExtD])
6036 Features.set(Feature_HasStdExtDBit);
6037 if (FB[RISCV::FeatureStdExtQ])
6038 Features.set(Feature_HasStdExtQBit);
6039 if (FB[RISCV::FeatureStdExtZfhmin])
6040 Features.set(Feature_HasStdExtZfhminBit);
6041 if (FB[RISCV::FeatureStdExtZfh])
6042 Features.set(Feature_HasStdExtZfhBit);
6043 if (FB[RISCV::FeatureStdExtZfbfmin])
6044 Features.set(Feature_HasStdExtZfbfminBit);
6045 if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZfhmin] || FB[RISCV::FeatureStdExtZfbfmin])
6046 Features.set(Feature_HasHalfFPLoadStoreMoveBit);
6047 if (FB[RISCV::FeatureStdExtZfa])
6048 Features.set(Feature_HasStdExtZfaBit);
6049 if (FB[RISCV::FeatureStdExtZfinx])
6050 Features.set(Feature_HasStdExtZfinxBit);
6051 if (FB[RISCV::FeatureStdExtF] || FB[RISCV::FeatureStdExtZfinx])
6052 Features.set(Feature_HasStdExtFOrZfinxBit);
6053 if (FB[RISCV::FeatureStdExtZdinx])
6054 Features.set(Feature_HasStdExtZdinxBit);
6055 if (FB[RISCV::FeatureStdExtZhinxmin])
6056 Features.set(Feature_HasStdExtZhinxminBit);
6057 if (FB[RISCV::FeatureStdExtZhinx])
6058 Features.set(Feature_HasStdExtZhinxBit);
6059 if (FB[RISCV::FeatureStdExtZca])
6060 Features.set(Feature_HasStdExtZcaBit);
6061 if (FB[RISCV::FeatureStdExtZcb])
6062 Features.set(Feature_HasStdExtZcbBit);
6063 if (FB[RISCV::FeatureStdExtZcf])
6064 Features.set(Feature_HasStdExtZcfBit);
6065 if (FB[RISCV::FeatureStdExtZcd])
6066 Features.set(Feature_HasStdExtZcdBit);
6067 if (FB[RISCV::FeatureStdExtZclsd])
6068 Features.set(Feature_HasStdExtZclsdBit);
6069 if (FB[RISCV::FeatureStdExtZcmp])
6070 Features.set(Feature_HasStdExtZcmpBit);
6071 if (FB[RISCV::FeatureStdExtZcmt])
6072 Features.set(Feature_HasStdExtZcmtBit);
6073 if (FB[RISCV::FeatureStdExtZcmop])
6074 Features.set(Feature_HasStdExtZcmopBit);
6075 if (FB[RISCV::FeatureStdExtZba])
6076 Features.set(Feature_HasStdExtZbaBit);
6077 if (FB[RISCV::FeatureStdExtZbb])
6078 Features.set(Feature_HasStdExtZbbBit);
6079 if (!(FB[RISCV::FeatureStdExtZbb]))
6080 Features.set(Feature_NoStdExtZbbBit);
6081 if (FB[RISCV::FeatureStdExtZbs])
6082 Features.set(Feature_HasStdExtZbsBit);
6083 if (FB[RISCV::FeatureStdExtZbkb])
6084 Features.set(Feature_HasStdExtZbkbBit);
6085 if (!(FB[RISCV::FeatureStdExtZbkb]))
6086 Features.set(Feature_NoStdExtZbkbBit);
6087 if (FB[RISCV::FeatureStdExtZbkx])
6088 Features.set(Feature_HasStdExtZbkxBit);
6089 if (FB[RISCV::FeatureStdExtZbb] || FB[RISCV::FeatureStdExtZbkb])
6090 Features.set(Feature_HasStdExtZbbOrZbkbBit);
6091 if (FB[RISCV::FeatureStdExtZbkc])
6092 Features.set(Feature_HasStdExtZbkcBit);
6093 if (FB[RISCV::FeatureStdExtZbc])
6094 Features.set(Feature_HasStdExtZbcBit);
6095 if (FB[RISCV::FeatureStdExtZknd])
6096 Features.set(Feature_HasStdExtZkndBit);
6097 if (FB[RISCV::FeatureStdExtZkne])
6098 Features.set(Feature_HasStdExtZkneBit);
6099 if (FB[RISCV::FeatureStdExtZknd] || FB[RISCV::FeatureStdExtZkne])
6100 Features.set(Feature_HasStdExtZkndOrZkneBit);
6101 if (FB[RISCV::FeatureStdExtZknh])
6102 Features.set(Feature_HasStdExtZknhBit);
6103 if (FB[RISCV::FeatureStdExtZksed])
6104 Features.set(Feature_HasStdExtZksedBit);
6105 if (FB[RISCV::FeatureStdExtZksh])
6106 Features.set(Feature_HasStdExtZkshBit);
6107 if (FB[RISCV::FeatureStdExtZkr])
6108 Features.set(Feature_HasStdExtZkrBit);
6109 if (FB[RISCV::FeatureStdExtZvabd])
6110 Features.set(Feature_HasStdExtZvabdBit);
6111 if (FB[RISCV::FeatureStdExtZvqwdota8i] || FB[RISCV::FeatureStdExtZvqwdota16i])
6112 Features.set(Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit);
6113 if (FB[RISCV::FeatureStdExtZvfwdota16bf])
6114 Features.set(Feature_HasStdExtZvfwdota16bfBit);
6115 if (FB[RISCV::FeatureStdExtZvfqwdota8f])
6116 Features.set(Feature_HasStdExtZvfqwdota8fBit);
6117 if (FB[RISCV::FeatureStdExtZvfbfmin])
6118 Features.set(Feature_HasStdExtZvfbfminBit);
6119 if (FB[RISCV::FeatureStdExtZvfbfwma])
6120 Features.set(Feature_HasStdExtZvfbfwmaBit);
6121 if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZvfh])
6122 Features.set(Feature_HasStdExtZfhOrZvfhBit);
6123 if (FB[RISCV::FeatureStdExtZvfofp8min])
6124 Features.set(Feature_HasStdExtZvfofp8minBit);
6125 if (FB[RISCV::FeatureStdExtZvfbfmin] || FB[RISCV::FeatureStdExtZvfofp8min])
6126 Features.set(Feature_HasStdExtZvfbfminOrZvfofp8minBit);
6127 if (FB[RISCV::FeatureStdExtZvkb])
6128 Features.set(Feature_HasStdExtZvkbBit);
6129 if (FB[RISCV::FeatureStdExtZvbb])
6130 Features.set(Feature_HasStdExtZvbbBit);
6131 if (FB[RISCV::FeatureStdExtZvbc])
6132 Features.set(Feature_HasStdExtZvbcBit);
6133 if (FB[RISCV::FeatureStdExtZvbc] || FB[RISCV::FeatureStdExtZvbc32e])
6134 Features.set(Feature_HasStdExtZvbcOrZvbc32eBit);
6135 if (FB[RISCV::FeatureStdExtZvkg])
6136 Features.set(Feature_HasStdExtZvkgBit);
6137 if (FB[RISCV::FeatureStdExtZvkgs])
6138 Features.set(Feature_HasStdExtZvkgsBit);
6139 if (FB[RISCV::FeatureStdExtZvkned])
6140 Features.set(Feature_HasStdExtZvknedBit);
6141 if (FB[RISCV::FeatureStdExtZvknha])
6142 Features.set(Feature_HasStdExtZvknhaBit);
6143 if (FB[RISCV::FeatureStdExtZvknhb])
6144 Features.set(Feature_HasStdExtZvknhbBit);
6145 if (FB[RISCV::FeatureStdExtZvksed])
6146 Features.set(Feature_HasStdExtZvksedBit);
6147 if (FB[RISCV::FeatureStdExtZvksh])
6148 Features.set(Feature_HasStdExtZvkshBit);
6149 if (FB[RISCV::FeatureStdExtZvdot4a8i])
6150 Features.set(Feature_HasStdExtZvdot4a8iBit);
6151 if (FB[RISCV::FeatureStdExtZvzip])
6152 Features.set(Feature_HasStdExtZvzipBit);
6153 if (FB[RISCV::FeatureStdExtZvvmm])
6154 Features.set(Feature_HasStdExtZvvmmBit);
6155 if (FB[RISCV::FeatureStdExtZvvfmm])
6156 Features.set(Feature_HasStdExtZvvfmmBit);
6157 if (FB[RISCV::FeatureStdExtZvvmtls])
6158 Features.set(Feature_HasStdExtZvvmtlsBit);
6159 if (FB[RISCV::FeatureStdExtZvvmttls])
6160 Features.set(Feature_HasStdExtZvvmttlsBit);
6161 if (FB[RISCV::FeatureStdExtZvqwbdota8i] || FB[RISCV::FeatureStdExtZvqwbdota16i])
6162 Features.set(Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit);
6163 if (FB[RISCV::FeatureStdExtZvfwbdota16bf])
6164 Features.set(Feature_HasStdExtZvfwbdota16bfBit);
6165 if (FB[RISCV::FeatureStdExtZvfqwbdota8f])
6166 Features.set(Feature_HasStdExtZvfqwbdota8fBit);
6167 if (FB[RISCV::FeatureStdExtZvfbdota32f])
6168 Features.set(Feature_HasStdExtZvfbdota32fBit);
6169 if (FB[RISCV::FeatureStdExtZve32x])
6170 Features.set(Feature_HasVInstructionsBit);
6171 if (FB[RISCV::FeatureStdExtZve64x])
6172 Features.set(Feature_HasVInstructionsI64Bit);
6173 if (FB[RISCV::FeatureStdExtZve32f])
6174 Features.set(Feature_HasVInstructionsAnyFBit);
6175 if (FB[RISCV::FeatureStdExtZvfhmin] || FB[RISCV::FeatureStdExtZvfh])
6176 Features.set(Feature_HasVInstructionsF16MinimalBit);
6177 if (FB[RISCV::FeatureStdExtH])
6178 Features.set(Feature_HasStdExtHBit);
6179 if (FB[RISCV::FeatureStdExtSmrnmi])
6180 Features.set(Feature_HasStdExtSmrnmiBit);
6181 if (FB[RISCV::FeatureStdExtSvinval])
6182 Features.set(Feature_HasStdExtSvinvalBit);
6183 if (FB[RISCV::FeatureStdExtSmctr] || FB[RISCV::FeatureStdExtSsctr])
6184 Features.set(Feature_HasStdExtSmctrOrSsctrBit);
6185 if (FB[RISCV::FeatureStdExtP])
6186 Features.set(Feature_HasStdExtPBit);
6187 if (FB[RISCV::FeatureStdExtZbkb] || FB[RISCV::FeatureStdExtP])
6188 Features.set(Feature_HasStdExtZbkbOrPBit);
6189 if (FB[RISCV::FeatureStdExtY])
6190 Features.set(Feature_HasStdExtYBit);
6191 if (FB[RISCV::FeatureVendorXVentanaCondOps])
6192 Features.set(Feature_HasVendorXVentanaCondOpsBit);
6193 if (FB[RISCV::FeatureVendorXTHeadBa])
6194 Features.set(Feature_HasVendorXTHeadBaBit);
6195 if (FB[RISCV::FeatureVendorXTHeadBb])
6196 Features.set(Feature_HasVendorXTHeadBbBit);
6197 if (FB[RISCV::FeatureVendorXTHeadBs])
6198 Features.set(Feature_HasVendorXTHeadBsBit);
6199 if (FB[RISCV::FeatureVendorXTHeadCondMov])
6200 Features.set(Feature_HasVendorXTHeadCondMovBit);
6201 if (FB[RISCV::FeatureVendorXTHeadCmo])
6202 Features.set(Feature_HasVendorXTHeadCmoBit);
6203 if (FB[RISCV::FeatureVendorXTHeadFMemIdx])
6204 Features.set(Feature_HasVendorXTHeadFMemIdxBit);
6205 if (FB[RISCV::FeatureVendorXTHeadMac])
6206 Features.set(Feature_HasVendorXTHeadMacBit);
6207 if (FB[RISCV::FeatureVendorXTHeadMemIdx])
6208 Features.set(Feature_HasVendorXTHeadMemIdxBit);
6209 if (FB[RISCV::FeatureVendorXTHeadMemPair])
6210 Features.set(Feature_HasVendorXTHeadMemPairBit);
6211 if (FB[RISCV::FeatureVendorXTHeadSync])
6212 Features.set(Feature_HasVendorXTHeadSyncBit);
6213 if (FB[RISCV::FeatureVendorXTHeadVdot])
6214 Features.set(Feature_HasVendorXTHeadVdotBit);
6215 if (FB[RISCV::FeatureVendorXSfvcp])
6216 Features.set(Feature_HasVendorXSfvcpBit);
6217 if (FB[RISCV::FeatureVendorXSfmmbase])
6218 Features.set(Feature_HasVendorXSfmmbaseBit);
6219 if (FB[RISCV::FeatureVendorXSfmm32a8f])
6220 Features.set(Feature_HasVendorXSfmm32a8fBit);
6221 if (FB[RISCV::FeatureVendorXSfmm32a8i])
6222 Features.set(Feature_HasVendorXSfmm32a8iBit);
6223 if (FB[RISCV::FeatureVendorXSfmm32a16f] || FB[RISCV::FeatureVendorXSfmm32a32f] || FB[RISCV::FeatureVendorXSfmm64a64f])
6224 Features.set(Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit);
6225 if (FB[RISCV::FeatureVendorXSfvqmaccdod])
6226 Features.set(Feature_HasVendorXSfvqmaccdodBit);
6227 if (FB[RISCV::FeatureVendorXSfvqmaccqoq])
6228 Features.set(Feature_HasVendorXSfvqmaccqoqBit);
6229 if (FB[RISCV::FeatureVendorXSfvfwmaccqqq])
6230 Features.set(Feature_HasVendorXSfvfwmaccqqqBit);
6231 if (FB[RISCV::FeatureVendorXSfvfnrclipxfqf])
6232 Features.set(Feature_HasVendorXSfvfnrclipxfqfBit);
6233 if (FB[RISCV::FeatureVendorXSfvfbfexp16e] || FB[RISCV::FeatureVendorXSfvfexp16e] || FB[RISCV::FeatureVendorXSfvfexp32e])
6234 Features.set(Feature_HasVendorXSfvfexpAnyBit);
6235 if (FB[RISCV::FeatureVendorXSfvfexpa])
6236 Features.set(Feature_HasVendorXSfvfexpaBit);
6237 if (FB[RISCV::FeatureVendorXSiFivecdiscarddlone])
6238 Features.set(Feature_HasVendorXSiFivecdiscarddloneBit);
6239 if (FB[RISCV::FeatureVendorXSiFivecflushdlone])
6240 Features.set(Feature_HasVendorXSiFivecflushdloneBit);
6241 if (FB[RISCV::FeatureVendorXSfcease])
6242 Features.set(Feature_HasVendorXSfceaseBit);
6243 if (FB[RISCV::FeatureVendorXCVelw])
6244 Features.set(Feature_HasVendorXCVelwBit);
6245 if (FB[RISCV::FeatureVendorXCVbitmanip])
6246 Features.set(Feature_HasVendorXCVbitmanipBit);
6247 if (FB[RISCV::FeatureVendorXCVmac])
6248 Features.set(Feature_HasVendorXCVmacBit);
6249 if (FB[RISCV::FeatureVendorXCVmem])
6250 Features.set(Feature_HasVendorXCVmemBit);
6251 if (FB[RISCV::FeatureVendorXCValu])
6252 Features.set(Feature_HasVendorXCValuBit);
6253 if (FB[RISCV::FeatureVendorXCVsimd])
6254 Features.set(Feature_HasVendorXCVsimdBit);
6255 if (FB[RISCV::FeatureVendorXCVbi])
6256 Features.set(Feature_HasVendorXCVbiBit);
6257 if (FB[RISCV::FeatureVendorXMIPSCMov])
6258 Features.set(Feature_HasVendorXMIPSCMovBit);
6259 if (FB[RISCV::FeatureVendorXMIPSLSP])
6260 Features.set(Feature_HasVendorXMIPSLSPBit);
6261 if (FB[RISCV::FeatureVendorXMIPSCBOP])
6262 Features.set(Feature_HasVendorXMIPSCBOPBit);
6263 if (FB[RISCV::FeatureVendorXMIPSEXECTL])
6264 Features.set(Feature_HasVendorXMIPSEXECTLBit);
6265 if (FB[RISCV::FeatureVendorXwchc])
6266 Features.set(Feature_HasVendorXwchcBit);
6267 if (FB[RISCV::FeatureVendorXqccmp])
6268 Features.set(Feature_HasVendorXqccmpBit);
6269 if (FB[RISCV::FeatureVendorXqccmt])
6270 Features.set(Feature_HasVendorXqccmtBit);
6271 if (FB[RISCV::FeatureVendorXqcia])
6272 Features.set(Feature_HasVendorXqciaBit);
6273 if (FB[RISCV::FeatureVendorXqciac])
6274 Features.set(Feature_HasVendorXqciacBit);
6275 if (FB[RISCV::FeatureVendorXqcibi])
6276 Features.set(Feature_HasVendorXqcibiBit);
6277 if (FB[RISCV::FeatureVendorXqcibm])
6278 Features.set(Feature_HasVendorXqcibmBit);
6279 if (FB[RISCV::FeatureVendorXqcicli])
6280 Features.set(Feature_HasVendorXqcicliBit);
6281 if (FB[RISCV::FeatureVendorXqcicm])
6282 Features.set(Feature_HasVendorXqcicmBit);
6283 if (FB[RISCV::FeatureVendorXqcics])
6284 Features.set(Feature_HasVendorXqcicsBit);
6285 if (FB[RISCV::FeatureVendorXqcicsr])
6286 Features.set(Feature_HasVendorXqcicsrBit);
6287 if (FB[RISCV::FeatureVendorXqciint])
6288 Features.set(Feature_HasVendorXqciintBit);
6289 if (FB[RISCV::FeatureVendorXqciio])
6290 Features.set(Feature_HasVendorXqciioBit);
6291 if (FB[RISCV::FeatureVendorXqcilb])
6292 Features.set(Feature_HasVendorXqcilbBit);
6293 if (FB[RISCV::FeatureVendorXqcili])
6294 Features.set(Feature_HasVendorXqciliBit);
6295 if (FB[RISCV::FeatureVendorXqcilia])
6296 Features.set(Feature_HasVendorXqciliaBit);
6297 if (FB[RISCV::FeatureVendorXqcilo])
6298 Features.set(Feature_HasVendorXqciloBit);
6299 if (FB[RISCV::FeatureVendorXqcilsm])
6300 Features.set(Feature_HasVendorXqcilsmBit);
6301 if (FB[RISCV::FeatureVendorXqcisim])
6302 Features.set(Feature_HasVendorXqcisimBit);
6303 if (FB[RISCV::FeatureVendorXqcisls])
6304 Features.set(Feature_HasVendorXqcislsBit);
6305 if (FB[RISCV::FeatureVendorXqcisync])
6306 Features.set(Feature_HasVendorXqcisyncBit);
6307 if (FB[RISCV::FeatureVendorXAndesPerf])
6308 Features.set(Feature_HasVendorXAndesPerfBit);
6309 if (FB[RISCV::FeatureVendorXAndesBFHCvt])
6310 Features.set(Feature_HasVendorXAndesBFHCvtBit);
6311 if (FB[RISCV::FeatureVendorXAndesVBFHCvt])
6312 Features.set(Feature_HasVendorXAndesVBFHCvtBit);
6313 if (FB[RISCV::FeatureVendorXAndesVSIntH])
6314 Features.set(Feature_HasVendorXAndesVSIntHBit);
6315 if (FB[RISCV::FeatureVendorXAndesVSIntLoad])
6316 Features.set(Feature_HasVendorXAndesVSIntLoadBit);
6317 if (FB[RISCV::FeatureVendorXAndesVPackFPH])
6318 Features.set(Feature_HasVendorXAndesVPackFPHBit);
6319 if (FB[RISCV::FeatureVendorXAndesVDot])
6320 Features.set(Feature_HasVendorXAndesVDotBit);
6321 if (FB[RISCV::FeatureVendorXSMTVDot])
6322 Features.set(Feature_HasVendorXSMTVDotBit);
6323 if (FB[RISCV::FeatureVendorXSMTVDotII])
6324 Features.set(Feature_HasVendorXSMTVDotIIBit);
6325 if (FB[RISCV::FeatureVendorXAIFET])
6326 Features.set(Feature_HasXAIFETBit);
6327 if (FB[RISCV::FeatureVendorXCheriot])
6328 Features.set(Feature_HasCheriotBit);
6329 if (FB[RISCV::Feature64Bit])
6330 Features.set(Feature_IsRV64Bit);
6331 if (!(FB[RISCV::Feature64Bit]))
6332 Features.set(Feature_IsRV32Bit);
6333 return Features;
6334}
6335
6336static const char MnemonicTable[] =
6337 "\007.insn_b\010.insn_ca\010.insn_cb\010.insn_ci\t.insn_ciw\010.insn_cj\010"
6338 ".insn_cl\010.insn_cr\010.insn_cs\t.insn_css\007.insn_i\007.insn_j\014.i"
6339 "nsn_qc.eai\013.insn_qc.eb\013.insn_qc.ei\013.insn_qc.ej\013.insn_qc.es\007"
6340 ".insn_r\010.insn_r4\007.insn_s\010.insn_sb\007.insn_u\010.insn_uj\004aa"
6341 "dd\005aaddu\003abs\004absw\003add\006add.uw\004addd\004addi\005addiw\004"
6342 "addw\010aes32dsi\taes32dsmi\010aes32esi\taes32esmi\007aes64ds\010aes64d"
6343 "sm\007aes64es\010aes64esm\007aes64im\taes64ks1i\010aes64ks2\015aif.amoa"
6344 "ddg.d\015aif.amoaddg.w\015aif.amoaddl.d\015aif.amoaddl.w\015aif.amoandg"
6345 ".d\015aif.amoandg.w\015aif.amoandl.d\015aif.amoandl.w\021aif.amocmpswap"
6346 "g.d\021aif.amocmpswapg.w\021aif.amocmpswapl.d\021aif.amocmpswapl.w\015a"
6347 "if.amomaxg.d\015aif.amomaxg.w\015aif.amomaxl.d\015aif.amomaxl.w\016aif."
6348 "amomaxug.d\016aif.amomaxug.w\016aif.amomaxul.d\016aif.amomaxul.w\015aif"
6349 ".amoming.d\015aif.amoming.w\015aif.amominl.d\015aif.amominl.w\016aif.am"
6350 "ominug.d\016aif.amominug.w\016aif.amominul.d\016aif.amominul.w\014aif.a"
6351 "moorg.d\014aif.amoorg.w\014aif.amoorl.d\014aif.amoorl.w\016aif.amoswapg"
6352 ".d\016aif.amoswapg.w\016aif.amoswapl.d\016aif.amoswapl.w\015aif.amoxorg"
6353 ".d\015aif.amoxorg.w\015aif.amoxorl.d\015aif.amoxorl.w\013aif.bitmixb\017"
6354 "aif.cubeface.ps\022aif.cubefaceidx.ps\020aif.cubesgnsc.ps\020aif.cubesg"
6355 "ntc.ps\013aif.fadd.pi\013aif.fadd.ps\014aif.faddi.pi\017aif.famoaddg.pi"
6356 "\017aif.famoaddl.pi\017aif.famoandg.pi\017aif.famoandl.pi\017aif.famoma"
6357 "xg.pi\017aif.famomaxg.ps\017aif.famomaxl.pi\017aif.famomaxl.ps\020aif.f"
6358 "amomaxug.pi\020aif.famomaxul.pi\017aif.famoming.pi\017aif.famoming.ps\017"
6359 "aif.famominl.pi\017aif.famominl.ps\020aif.famominug.pi\020aif.famominul"
6360 ".pi\016aif.famoorg.pi\016aif.famoorl.pi\020aif.famoswapg.pi\020aif.famo"
6361 "swapl.pi\017aif.famoxorg.pi\017aif.famoxorl.pi\013aif.fand.pi\014aif.fa"
6362 "ndi.pi\naif.fbc.ps\013aif.fbci.pi\013aif.fbci.ps\013aif.fbcx.ps\015aif."
6363 "fclass.ps\014aif.fcmov.ps\015aif.fcmovm.ps\017aif.fcvt.f10.ps\017aif.fc"
6364 "vt.f11.ps\017aif.fcvt.f16.ps\017aif.fcvt.ps.f10\017aif.fcvt.ps.f11\017a"
6365 "if.fcvt.ps.f16\016aif.fcvt.ps.pw\017aif.fcvt.ps.pwu\020aif.fcvt.ps.rast"
6366 "\020aif.fcvt.ps.sn16\017aif.fcvt.ps.sn8\020aif.fcvt.ps.un10\020aif.fcvt"
6367 ".ps.un16\017aif.fcvt.ps.un2\020aif.fcvt.ps.un24\017aif.fcvt.ps.un8\016a"
6368 "if.fcvt.pw.ps\017aif.fcvt.pwu.ps\020aif.fcvt.rast.ps\020aif.fcvt.sn16.p"
6369 "s\017aif.fcvt.sn8.ps\020aif.fcvt.un10.ps\020aif.fcvt.un16.ps\017aif.fcv"
6370 "t.un2.ps\020aif.fcvt.un24.ps\017aif.fcvt.un8.ps\013aif.fdiv.pi\013aif.f"
6371 "div.ps\014aif.fdivu.pi\naif.feq.pi\naif.feq.ps\013aif.feqm.ps\013aif.fe"
6372 "xp.ps\013aif.ffrc.ps\014aif.fg32b.ps\014aif.fg32h.ps\014aif.fg32w.ps\na"
6373 "if.fgb.ps\013aif.fgbg.ps\013aif.fgbl.ps\naif.fgh.ps\013aif.fghg.ps\013a"
6374 "if.fghl.ps\naif.fgw.ps\013aif.fgwg.ps\013aif.fgwl.ps\naif.fle.pi\naif.f"
6375 "le.ps\013aif.flem.ps\013aif.flog.ps\010aif.flq2\naif.flt.pi\naif.flt.ps"
6376 "\013aif.fltm.pi\013aif.fltm.ps\013aif.fltu.pi\naif.flw.ps\013aif.flwg.p"
6377 "s\013aif.flwl.ps\014aif.fmadd.ps\013aif.fmax.pi\013aif.fmax.ps\014aif.f"
6378 "maxu.pi\013aif.fmin.pi\013aif.fmin.ps\014aif.fminu.pi\014aif.fmsub.ps\013"
6379 "aif.fmul.pi\013aif.fmul.ps\014aif.fmulh.pi\015aif.fmulhu.pi\015aif.fmvs"
6380 ".x.ps\015aif.fmvz.x.ps\015aif.fnmadd.ps\015aif.fnmsub.ps\013aif.fnot.pi"
6381 "\naif.for.pi\020aif.fpackrepb.pi\020aif.fpackreph.pi\013aif.frcp.ps\021"
6382 "aif.frcp_fix.rast\013aif.frem.pi\014aif.fremu.pi\015aif.fround.ps\013ai"
6383 "f.frsq.ps\014aif.fsat8.pi\015aif.fsatu8.pi\015aif.fsc32b.ps\015aif.fsc3"
6384 "2h.ps\015aif.fsc32w.ps\013aif.fscb.ps\014aif.fscbg.ps\014aif.fscbl.ps\013"
6385 "aif.fsch.ps\014aif.fschg.ps\014aif.fschl.ps\013aif.fscw.ps\014aif.fscwg"
6386 ".ps\014aif.fscwl.ps\014aif.fsetm.pi\014aif.fsgnj.ps\015aif.fsgnjn.ps\015"
6387 "aif.fsgnjx.ps\013aif.fsin.ps\013aif.fsll.pi\014aif.fslli.pi\010aif.fsq2"
6388 "\014aif.fsqrt.ps\013aif.fsra.pi\014aif.fsrai.pi\013aif.fsrl.pi\014aif.f"
6389 "srli.pi\013aif.fsub.pi\013aif.fsub.ps\naif.fsw.ps\013aif.fswg.ps\015aif"
6390 ".fswizz.ps\013aif.fswl.ps\013aif.fxor.pi\013aif.maskand\013aif.masknot\n"
6391 "aif.maskor\014aif.maskpopc\021aif.maskpopc.rast\015aif.maskpopcz\013aif"
6392 ".maskxor\013aif.mov.m.x\014aif.mova.m.x\014aif.mova.x.m\taif.packb\007a"
6393 "if.sbg\007aif.sbl\007aif.shg\007aif.shl\010amoadd.b\013amoadd.b.aq\015a"
6394 "moadd.b.aqrl\013amoadd.b.rl\010amoadd.d\013amoadd.d.aq\015amoadd.d.aqrl"
6395 "\013amoadd.d.rl\010amoadd.h\013amoadd.h.aq\015amoadd.h.aqrl\013amoadd.h"
6396 ".rl\010amoadd.w\013amoadd.w.aq\015amoadd.w.aqrl\013amoadd.w.rl\010amoan"
6397 "d.b\013amoand.b.aq\015amoand.b.aqrl\013amoand.b.rl\010amoand.d\013amoan"
6398 "d.d.aq\015amoand.d.aqrl\013amoand.d.rl\010amoand.h\013amoand.h.aq\015am"
6399 "oand.h.aqrl\013amoand.h.rl\010amoand.w\013amoand.w.aq\015amoand.w.aqrl\013"
6400 "amoand.w.rl\010amocas.b\013amocas.b.aq\015amocas.b.aqrl\013amocas.b.rl\010"
6401 "amocas.d\013amocas.d.aq\015amocas.d.aqrl\013amocas.d.rl\010amocas.h\013"
6402 "amocas.h.aq\015amocas.h.aqrl\013amocas.h.rl\010amocas.q\013amocas.q.aq\015"
6403 "amocas.q.aqrl\013amocas.q.rl\010amocas.w\013amocas.w.aq\015amocas.w.aqr"
6404 "l\013amocas.w.rl\010amomax.b\013amomax.b.aq\015amomax.b.aqrl\013amomax."
6405 "b.rl\010amomax.d\013amomax.d.aq\015amomax.d.aqrl\013amomax.d.rl\010amom"
6406 "ax.h\013amomax.h.aq\015amomax.h.aqrl\013amomax.h.rl\010amomax.w\013amom"
6407 "ax.w.aq\015amomax.w.aqrl\013amomax.w.rl\tamomaxu.b\014amomaxu.b.aq\016a"
6408 "momaxu.b.aqrl\014amomaxu.b.rl\tamomaxu.d\014amomaxu.d.aq\016amomaxu.d.a"
6409 "qrl\014amomaxu.d.rl\tamomaxu.h\014amomaxu.h.aq\016amomaxu.h.aqrl\014amo"
6410 "maxu.h.rl\tamomaxu.w\014amomaxu.w.aq\016amomaxu.w.aqrl\014amomaxu.w.rl\010"
6411 "amomin.b\013amomin.b.aq\015amomin.b.aqrl\013amomin.b.rl\010amomin.d\013"
6412 "amomin.d.aq\015amomin.d.aqrl\013amomin.d.rl\010amomin.h\013amomin.h.aq\015"
6413 "amomin.h.aqrl\013amomin.h.rl\010amomin.w\013amomin.w.aq\015amomin.w.aqr"
6414 "l\013amomin.w.rl\tamominu.b\014amominu.b.aq\016amominu.b.aqrl\014amomin"
6415 "u.b.rl\tamominu.d\014amominu.d.aq\016amominu.d.aqrl\014amominu.d.rl\tam"
6416 "ominu.h\014amominu.h.aq\016amominu.h.aqrl\014amominu.h.rl\tamominu.w\014"
6417 "amominu.w.aq\016amominu.w.aqrl\014amominu.w.rl\007amoor.b\namoor.b.aq\014"
6418 "amoor.b.aqrl\namoor.b.rl\007amoor.d\namoor.d.aq\014amoor.d.aqrl\namoor."
6419 "d.rl\007amoor.h\namoor.h.aq\014amoor.h.aqrl\namoor.h.rl\007amoor.w\namo"
6420 "or.w.aq\014amoor.w.aqrl\namoor.w.rl\tamoswap.b\014amoswap.b.aq\016amosw"
6421 "ap.b.aqrl\014amoswap.b.rl\tamoswap.d\014amoswap.d.aq\016amoswap.d.aqrl\014"
6422 "amoswap.d.rl\tamoswap.h\014amoswap.h.aq\016amoswap.h.aqrl\014amoswap.h."
6423 "rl\tamoswap.w\014amoswap.w.aq\016amoswap.w.aqrl\014amoswap.w.rl\010amox"
6424 "or.b\013amoxor.b.aq\015amoxor.b.aqrl\013amoxor.b.rl\010amoxor.d\013amox"
6425 "or.d.aq\015amoxor.d.aqrl\013amoxor.d.rl\010amoxor.h\013amoxor.h.aq\015a"
6426 "moxor.h.aqrl\013amoxor.h.rl\010amoxor.w\013amoxor.w.aq\015amoxor.w.aqrl"
6427 "\013amoxor.w.rl\003and\004andi\004andn\004asub\005asubu\005auipc\004bcl"
6428 "r\005bclri\003beq\004beqi\004beqz\004bext\005bexti\003bge\004bgeu\004bg"
6429 "ez\003bgt\004bgtu\004bgtz\004binv\005binvi\003ble\004bleu\004blez\003bl"
6430 "t\004bltu\004bltz\003bne\004bnei\004bnez\005brev8\004bset\005bseti\005c"
6431 ".add\006c.addi\nc.addi16sp\nc.addi4spn\007c.addiw\006c.addw\005c.and\006"
6432 "c.andi\006c.beqz\006c.bnez\010c.ebreak\005c.fld\007c.fldsp\005c.flw\007"
6433 "c.flwsp\005c.fsd\007c.fsdsp\005c.fsw\007c.fswsp\003c.j\005c.jal\006c.ja"
6434 "lr\004c.jr\005c.lbu\004c.ld\006c.ldsp\004c.lh\005c.lhu\004c.li\005c.lui"
6435 "\004c.lw\006c.lwsp\007c.mop.1\010c.mop.11\010c.mop.13\010c.mop.15\007c."
6436 "mop.3\007c.mop.5\007c.mop.7\007c.mop.9\005c.mul\004c.mv\005c.nop\005c.n"
6437 "ot\tc.ntl.all\010c.ntl.p1\nc.ntl.pall\010c.ntl.s1\004c.or\004c.sb\004c."
6438 "sd\006c.sdsp\010c.sext.b\010c.sext.h\004c.sh\006c.slli\010c.slli64\006c"
6439 ".srai\010c.srai64\006c.srli\010c.srli64\nc.sspopchk\010c.sspush\005c.su"
6440 "b\006c.subw\004c.sw\006c.swsp\007c.unimp\005c.xor\010c.zext.b\010c.zext"
6441 ".h\010c.zext.w\004call\tcbo.clean\tcbo.flush\tcbo.inval\010cbo.zero\005"
6442 "clmul\006clmulh\006clmulr\003cls\004clsw\003clz\004clzw\007cm.jalt\005c"
6443 "m.jt\tcm.mva01s\tcm.mvsa01\006cm.pop\tcm.popret\ncm.popretz\007cm.push\004"
6444 "cpop\005cpopw\004csrc\005csrci\004csrr\005csrrc\006csrrci\005csrrs\006c"
6445 "srrsi\005csrrw\006csrrwi\004csrs\005csrsi\004csrw\005csrwi\003ctz\004ct"
6446 "zw\006cv.abs\010cv.abs.b\010cv.abs.h\010cv.add.b\013cv.add.div2\013cv.a"
6447 "dd.div4\013cv.add.div8\010cv.add.h\013cv.add.sc.b\013cv.add.sc.h\014cv."
6448 "add.sci.b\014cv.add.sci.h\007cv.addn\010cv.addnr\010cv.addrn\tcv.addrnr"
6449 "\010cv.addun\tcv.addunr\tcv.addurn\ncv.addurnr\010cv.and.b\010cv.and.h\013"
6450 "cv.and.sc.b\013cv.and.sc.h\014cv.and.sci.b\014cv.and.sci.h\010cv.avg.b\010"
6451 "cv.avg.h\013cv.avg.sc.b\013cv.avg.sc.h\014cv.avg.sci.b\014cv.avg.sci.h\t"
6452 "cv.avgu.b\tcv.avgu.h\014cv.avgu.sc.b\014cv.avgu.sc.h\015cv.avgu.sci.b\015"
6453 "cv.avgu.sci.h\007cv.bclr\010cv.bclrr\tcv.beqimm\tcv.bitrev\tcv.bneimm\007"
6454 "cv.bset\010cv.bsetr\006cv.clb\007cv.clip\010cv.clipr\010cv.clipu\tcv.cl"
6455 "ipur\ncv.cmpeq.b\ncv.cmpeq.h\015cv.cmpeq.sc.b\015cv.cmpeq.sc.h\016cv.cm"
6456 "peq.sci.b\016cv.cmpeq.sci.h\ncv.cmpge.b\ncv.cmpge.h\015cv.cmpge.sc.b\015"
6457 "cv.cmpge.sc.h\016cv.cmpge.sci.b\016cv.cmpge.sci.h\013cv.cmpgeu.b\013cv."
6458 "cmpgeu.h\016cv.cmpgeu.sc.b\016cv.cmpgeu.sc.h\017cv.cmpgeu.sci.b\017cv.c"
6459 "mpgeu.sci.h\ncv.cmpgt.b\ncv.cmpgt.h\015cv.cmpgt.sc.b\015cv.cmpgt.sc.h\016"
6460 "cv.cmpgt.sci.b\016cv.cmpgt.sci.h\013cv.cmpgtu.b\013cv.cmpgtu.h\016cv.cm"
6461 "pgtu.sc.b\016cv.cmpgtu.sc.h\017cv.cmpgtu.sci.b\017cv.cmpgtu.sci.h\ncv.c"
6462 "mple.b\ncv.cmple.h\015cv.cmple.sc.b\015cv.cmple.sc.h\016cv.cmple.sci.b\016"
6463 "cv.cmple.sci.h\013cv.cmpleu.b\013cv.cmpleu.h\016cv.cmpleu.sc.b\016cv.cm"
6464 "pleu.sc.h\017cv.cmpleu.sci.b\017cv.cmpleu.sci.h\ncv.cmplt.b\ncv.cmplt.h"
6465 "\015cv.cmplt.sc.b\015cv.cmplt.sc.h\016cv.cmplt.sci.b\016cv.cmplt.sci.h\013"
6466 "cv.cmpltu.b\013cv.cmpltu.h\016cv.cmpltu.sc.b\016cv.cmpltu.sc.h\017cv.cm"
6467 "pltu.sci.b\017cv.cmpltu.sci.h\ncv.cmpne.b\ncv.cmpne.h\015cv.cmpne.sc.b\015"
6468 "cv.cmpne.sc.h\016cv.cmpne.sci.b\016cv.cmpne.sci.h\006cv.cnt\013cv.cplxc"
6469 "onj\014cv.cplxmul.i\021cv.cplxmul.i.div2\021cv.cplxmul.i.div4\021cv.cpl"
6470 "xmul.i.div8\014cv.cplxmul.r\021cv.cplxmul.r.div2\021cv.cplxmul.r.div4\021"
6471 "cv.cplxmul.r.div8\ncv.dotsp.b\ncv.dotsp.h\015cv.dotsp.sc.b\015cv.dotsp."
6472 "sc.h\016cv.dotsp.sci.b\016cv.dotsp.sci.h\ncv.dotup.b\ncv.dotup.h\015cv."
6473 "dotup.sc.b\015cv.dotup.sc.h\016cv.dotup.sci.b\016cv.dotup.sci.h\013cv.d"
6474 "otusp.b\013cv.dotusp.h\016cv.dotusp.sc.b\016cv.dotusp.sc.h\017cv.dotusp"
6475 ".sci.b\017cv.dotusp.sci.h\006cv.elw\010cv.extbs\010cv.extbz\010cv.exths"
6476 "\010cv.exthz\ncv.extract\014cv.extract.b\014cv.extract.h\013cv.extractr"
6477 "\013cv.extractu\015cv.extractu.b\015cv.extractu.h\014cv.extractur\006cv"
6478 ".ff1\006cv.fl1\tcv.insert\013cv.insert.b\013cv.insert.h\ncv.insertr\005"
6479 "cv.lb\006cv.lbu\005cv.lh\006cv.lhu\005cv.lw\006cv.mac\ncv.machhsn\013cv"
6480 ".machhsrn\ncv.machhun\013cv.machhurn\010cv.macsn\tcv.macsrn\010cv.macun"
6481 "\tcv.macurn\006cv.max\010cv.max.b\010cv.max.h\013cv.max.sc.b\013cv.max."
6482 "sc.h\014cv.max.sci.b\014cv.max.sci.h\007cv.maxu\tcv.maxu.b\tcv.maxu.h\014"
6483 "cv.maxu.sc.b\014cv.maxu.sc.h\015cv.maxu.sci.b\015cv.maxu.sci.h\006cv.mi"
6484 "n\010cv.min.b\010cv.min.h\013cv.min.sc.b\013cv.min.sc.h\014cv.min.sci.b"
6485 "\014cv.min.sci.h\007cv.minu\tcv.minu.b\tcv.minu.h\014cv.minu.sc.b\014cv"
6486 ".minu.sc.h\015cv.minu.sci.b\015cv.minu.sci.h\006cv.msu\tcv.mulhhs\ncv.m"
6487 "ulhhsn\013cv.mulhhsrn\tcv.mulhhu\ncv.mulhhun\013cv.mulhhurn\007cv.muls\010"
6488 "cv.mulsn\tcv.mulsrn\007cv.mulu\010cv.mulun\tcv.mulurn\007cv.or.b\007cv."
6489 "or.h\ncv.or.sc.b\ncv.or.sc.h\013cv.or.sci.b\013cv.or.sci.h\007cv.pack\t"
6490 "cv.pack.h\013cv.packhi.b\013cv.packlo.b\006cv.ror\005cv.sb\013cv.sdotsp"
6491 ".b\013cv.sdotsp.h\016cv.sdotsp.sc.b\016cv.sdotsp.sc.h\017cv.sdotsp.sci."
6492 "b\017cv.sdotsp.sci.h\013cv.sdotup.b\013cv.sdotup.h\016cv.sdotup.sc.b\016"
6493 "cv.sdotup.sc.h\017cv.sdotup.sci.b\017cv.sdotup.sci.h\014cv.sdotusp.b\014"
6494 "cv.sdotusp.h\017cv.sdotusp.sc.b\017cv.sdotusp.sc.h\020cv.sdotusp.sci.b\020"
6495 "cv.sdotusp.sci.h\005cv.sh\014cv.shuffle.b\014cv.shuffle.h\020cv.shuffle"
6496 ".sci.h\015cv.shuffle2.b\015cv.shuffle2.h\022cv.shufflei0.sci.b\022cv.sh"
6497 "ufflei1.sci.b\022cv.shufflei2.sci.b\022cv.shufflei3.sci.b\006cv.sle\007"
6498 "cv.sleu\010cv.sll.b\010cv.sll.h\013cv.sll.sc.b\013cv.sll.sc.h\014cv.sll"
6499 ".sci.b\014cv.sll.sci.h\010cv.sra.b\010cv.sra.h\013cv.sra.sc.b\013cv.sra"
6500 ".sc.h\014cv.sra.sci.b\014cv.sra.sci.h\010cv.srl.b\010cv.srl.h\013cv.srl"
6501 ".sc.b\013cv.srl.sc.h\014cv.srl.sci.b\014cv.srl.sci.h\010cv.sub.b\013cv."
6502 "sub.div2\013cv.sub.div4\013cv.sub.div8\010cv.sub.h\013cv.sub.sc.b\013cv"
6503 ".sub.sc.h\014cv.sub.sci.b\014cv.sub.sci.h\007cv.subn\010cv.subnr\010cv."
6504 "subrn\tcv.subrnr\013cv.subrotmj\020cv.subrotmj.div2\020cv.subrotmj.div4"
6505 "\020cv.subrotmj.div8\010cv.subun\tcv.subunr\tcv.suburn\ncv.suburnr\005c"
6506 "v.sw\010cv.xor.b\010cv.xor.h\013cv.xor.sc.b\013cv.xor.sc.h\014cv.xor.sc"
6507 "i.b\014cv.xor.sci.h\tczero.eqz\tczero.nez\003div\004divu\005divuw\004di"
6508 "vw\004dret\006ebreak\005ecall\006fabs.d\006fabs.h\006fabs.q\006fabs.s\006"
6509 "fadd.d\006fadd.h\006fadd.q\006fadd.s\010fclass.d\010fclass.h\010fclass."
6510 "q\010fclass.s\013fcvt.bf16.s\010fcvt.d.h\010fcvt.d.l\tfcvt.d.lu\010fcvt"
6511 ".d.q\010fcvt.d.s\010fcvt.d.w\tfcvt.d.wu\010fcvt.h.d\010fcvt.h.l\tfcvt.h"
6512 ".lu\010fcvt.h.s\010fcvt.h.w\tfcvt.h.wu\010fcvt.l.d\010fcvt.l.h\010fcvt."
6513 "l.q\010fcvt.l.s\tfcvt.lu.d\tfcvt.lu.h\tfcvt.lu.q\tfcvt.lu.s\010fcvt.q.d"
6514 "\010fcvt.q.l\tfcvt.q.lu\010fcvt.q.s\010fcvt.q.w\tfcvt.q.wu\013fcvt.s.bf"
6515 "16\010fcvt.s.d\010fcvt.s.h\010fcvt.s.l\tfcvt.s.lu\010fcvt.s.q\010fcvt.s"
6516 ".w\tfcvt.s.wu\010fcvt.w.d\010fcvt.w.h\010fcvt.w.q\010fcvt.w.s\tfcvt.wu."
6517 "d\tfcvt.wu.h\tfcvt.wu.q\tfcvt.wu.s\013fcvtmod.w.d\006fdiv.d\006fdiv.h\006"
6518 "fdiv.q\006fdiv.s\005fence\007fence.i\tfence.tso\005feq.d\005feq.h\005fe"
6519 "q.q\005feq.s\005fge.d\005fge.h\005fge.q\005fge.s\006fgeq.d\006fgeq.h\006"
6520 "fgeq.q\006fgeq.s\005fgt.d\005fgt.h\005fgt.q\005fgt.s\006fgtq.d\006fgtq."
6521 "h\006fgtq.q\006fgtq.s\003fld\005fle.d\005fle.h\005fle.q\005fle.s\006fle"
6522 "q.d\006fleq.h\006fleq.q\006fleq.s\003flh\005fli.d\005fli.h\005fli.q\005"
6523 "fli.s\003flq\005flt.d\005flt.h\005flt.q\005flt.s\006fltq.d\006fltq.h\006"
6524 "fltq.q\006fltq.s\003flw\007fmadd.d\007fmadd.h\007fmadd.q\007fmadd.s\006"
6525 "fmax.d\006fmax.h\006fmax.q\006fmax.s\007fmaxm.d\007fmaxm.h\007fmaxm.q\007"
6526 "fmaxm.s\006fmin.d\006fmin.h\006fmin.q\006fmin.s\007fminm.d\007fminm.h\007"
6527 "fminm.q\007fminm.s\007fmsub.d\007fmsub.h\007fmsub.q\007fmsub.s\006fmul."
6528 "d\006fmul.h\006fmul.q\006fmul.s\005fmv.d\007fmv.d.x\005fmv.h\007fmv.h.x"
6529 "\005fmv.q\005fmv.s\007fmv.w.x\007fmv.x.d\007fmv.x.h\007fmv.x.w\010fmvh."
6530 "x.d\010fmvh.x.q\010fmvp.d.x\010fmvp.q.x\006fneg.d\006fneg.h\006fneg.q\006"
6531 "fneg.s\010fnmadd.d\010fnmadd.h\010fnmadd.q\010fnmadd.s\010fnmsub.d\010f"
6532 "nmsub.h\010fnmsub.q\010fnmsub.s\005frcsr\007frflags\010fround.d\010frou"
6533 "nd.h\010fround.q\010fround.s\nfroundnx.d\nfroundnx.h\nfroundnx.q\nfroun"
6534 "dnx.s\004frrm\005fscsr\003fsd\007fsflags\010fsflagsi\007fsgnj.d\007fsgn"
6535 "j.h\007fsgnj.q\007fsgnj.s\010fsgnjn.d\010fsgnjn.h\010fsgnjn.q\010fsgnjn"
6536 ".s\010fsgnjx.d\010fsgnjx.h\010fsgnjx.q\010fsgnjx.s\003fsh\003fsq\007fsq"
6537 "rt.d\007fsqrt.h\007fsqrt.q\007fsqrt.s\004fsrm\005fsrmi\006fsub.d\006fsu"
6538 "b.h\006fsub.q\006fsub.s\003fsw\013hfence.gvma\013hfence.vvma\013hinval."
6539 "gvma\013hinval.vvma\005hlv.b\006hlv.bu\005hlv.d\005hlv.h\006hlv.hu\005h"
6540 "lv.w\006hlv.wu\007hlvx.hu\007hlvx.wu\005hsv.b\005hsv.d\005hsv.h\005hsv."
6541 "w\001j\003jal\004jalr\002jr\004jump\002la\tla.tls.gd\tla.tls.ie\002lb\005"
6542 "lb.aq\007lb.aqrl\003lbu\002ld\005ld.aq\007ld.aqrl\003lga\002lh\005lh.aq"
6543 "\007lh.aqrl\003lhu\002li\003lla\004lpad\004lr.d\007lr.d.aq\tlr.d.aqrl\007"
6544 "lr.d.rl\004lr.w\007lr.w.aq\tlr.w.aqrl\007lr.w.rl\003lui\002lw\005lw.aq\007"
6545 "lw.aqrl\003lwu\010macc.h00\010macc.h01\010macc.h11\010macc.w00\010macc."
6546 "w01\010macc.w11\nmaccsu.h00\nmaccsu.h11\nmaccsu.w00\nmaccsu.w11\tmaccu."
6547 "h00\tmaccu.h01\tmaccu.h11\tmaccu.w00\tmaccu.w01\tmaccu.w11\003max\004ma"
6548 "xu\005merge\005mhacc\010mhacc.h0\010mhacc.h1\007mhaccsu\nmhaccsu.h0\nmh"
6549 "accsu.h1\006mhaccu\006mhracc\010mhraccsu\007mhraccu\003min\004minu\nmip"
6550 "s.ccmov\010mips.ehb\010mips.ihb\010mips.ldp\010mips.lwp\nmips.pause\tmi"
6551 "ps.pref\010mips.sdp\010mips.swp\005mnret\007mop.r.0\007mop.r.1\010mop.r"
6552 ".10\010mop.r.11\010mop.r.12\010mop.r.13\010mop.r.14\010mop.r.15\010mop."
6553 "r.16\010mop.r.17\010mop.r.18\010mop.r.19\007mop.r.2\010mop.r.20\010mop."
6554 "r.21\010mop.r.22\010mop.r.23\010mop.r.24\010mop.r.25\010mop.r.26\010mop"
6555 ".r.27\010mop.r.28\010mop.r.29\007mop.r.3\010mop.r.30\010mop.r.31\007mop"
6556 ".r.4\007mop.r.5\007mop.r.6\007mop.r.7\007mop.r.8\007mop.r.9\010mop.rr.0"
6557 "\010mop.rr.1\010mop.rr.2\010mop.rr.3\010mop.rr.4\010mop.rr.5\010mop.rr."
6558 "6\010mop.rr.7\tmqacc.h00\tmqacc.h01\tmqacc.h11\tmqacc.w00\tmqacc.w01\tm"
6559 "qacc.w11\nmqracc.h00\nmqracc.h01\nmqracc.h11\nmqracc.w00\nmqracc.w01\nm"
6560 "qracc.w11\007mqrwacc\006mqwacc\004mret\004mseq\005mseqz\004msgt\005msgt"
6561 "u\005msgtz\004mslt\005msltu\005msltz\005msnez\003mul\007mul.h00\007mul."
6562 "h01\007mul.h11\007mul.w00\007mul.w01\007mul.w11\004mulh\007mulh.h0\007m"
6563 "ulh.h1\005mulhr\007mulhrsu\006mulhru\006mulhsu\tmulhsu.h0\tmulhsu.h1\005"
6564 "mulhu\004mulq\005mulqr\tmulsu.h00\tmulsu.h11\tmulsu.w00\tmulsu.w11\010m"
6565 "ulu.h00\010mulu.h01\010mulu.h11\010mulu.w00\010mulu.w01\010mulu.w11\004"
6566 "mulw\002mv\003mvd\003mvm\004mvmn\005nclip\006nclipi\007nclipiu\006nclip"
6567 "r\007nclipri\010nclipriu\007nclipru\006nclipu\nnds.addigp\007nds.bbc\007"
6568 "nds.bbs\010nds.beqc\010nds.bfos\010nds.bfoz\010nds.bnec\017nds.fcvt.bf1"
6569 "6.s\017nds.fcvt.s.bf16\007nds.ffb\nnds.ffmism\013nds.ffzmism\nnds.flmis"
6570 "m\010nds.lbgp\tnds.lbugp\010nds.ldgp\014nds.lea.b.ze\tnds.lea.d\014nds."
6571 "lea.d.ze\tnds.lea.h\014nds.lea.h.ze\tnds.lea.w\014nds.lea.w.ze\010nds.l"
6572 "hgp\tnds.lhugp\010nds.lwgp\tnds.lwugp\010nds.sbgp\010nds.sdgp\010nds.sh"
6573 "gp\010nds.swgp\016nds.vd4dots.vv\017nds.vd4dotsu.vv\016nds.vd4dotu.vv\021"
6574 "nds.vfncvt.bf16.s\016nds.vfpmadb.vf\016nds.vfpmadt.vf\020nds.vfwcvt.f.b"
6575 ".v\021nds.vfwcvt.f.bu.v\020nds.vfwcvt.f.n.v\021nds.vfwcvt.f.nu.v\021nds"
6576 ".vfwcvt.s.bf16\nnds.vle4.v\nnds.vln8.v\013nds.vlnu8.v\003neg\004negd\004"
6577 "negw\003nop\003not\004nsra\005nsrai\005nsrar\006nsrari\004nsrl\005nsrli"
6578 "\007ntl.all\006ntl.p1\010ntl.pall\006ntl.s1\002or\005orc.b\003ori\003or"
6579 "n\007paadd.b\010paadd.db\010paadd.dh\010paadd.dw\007paadd.h\007paadd.w\010"
6580 "paaddu.b\tpaaddu.db\tpaaddu.dh\tpaaddu.dw\010paaddu.h\010paaddu.w\010pa"
6581 "as.dhx\007paas.hx\007paas.wx\006pabd.b\007pabd.db\007pabd.dh\006pabd.h\013"
6582 "pabdsumau.b\npabdsumu.b\007pabdu.b\010pabdu.db\010pabdu.dh\007pabdu.h\006"
6583 "pabs.b\007pabs.db\007pabs.dh\006pabs.h\004pack\005packh\005packw\005pac"
6584 "ky\006padd.b\007padd.bs\007padd.db\010padd.dbs\007padd.dh\010padd.dhs\007"
6585 "padd.dw\010padd.dws\006padd.h\007padd.hs\006padd.w\007padd.ws\007pas.dh"
6586 "x\006pas.hx\006pas.wx\010pasa.dhx\007pasa.hx\007pasa.wx\007pasub.b\010p"
6587 "asub.db\010pasub.dh\010pasub.dw\007pasub.h\007pasub.w\010pasubu.b\tpasu"
6588 "bu.db\tpasubu.dh\tpasubu.dw\010pasubu.h\010pasubu.w\005pause\005pli.b\006"
6589 "pli.db\006pli.dh\005pli.h\005pli.w\007plui.dh\006plui.h\006plui.w\010pm"
6590 "2add.h\tpm2add.hx\010pm2add.w\tpm2add.wx\tpm2adda.h\npm2adda.hx\tpm2add"
6591 "a.w\npm2adda.wx\013pm2addasu.h\013pm2addasu.w\npm2addau.h\npm2addau.w\n"
6592 "pm2addsu.h\npm2addsu.w\tpm2addu.h\tpm2addu.w\tpm2sadd.h\npm2sadd.hx\010"
6593 "pm2sub.h\tpm2sub.hx\010pm2sub.w\tpm2sub.wx\tpm2suba.h\npm2suba.hx\tpm2s"
6594 "uba.w\npm2suba.wx\tpm2wadd.h\npm2wadd.hx\npm2wadda.h\013pm2wadda.hx\014"
6595 "pm2waddasu.h\013pm2waddau.h\013pm2waddsu.h\npm2waddu.h\tpm2wsub.h\npm2w"
6596 "sub.hx\npm2wsuba.h\013pm2wsuba.hx\010pm4add.b\010pm4add.h\tpm4adda.b\tp"
6597 "m4adda.h\013pm4addasu.b\013pm4addasu.h\npm4addau.b\npm4addau.h\npm4adds"
6598 "u.b\npm4addsu.h\tpm4addu.b\tpm4addu.h\013pmacc.w.h00\013pmacc.w.h01\013"
6599 "pmacc.w.h11\015pmaccsu.w.h00\015pmaccsu.w.h11\014pmaccu.w.h00\014pmaccu"
6600 ".w.h01\014pmaccu.w.h11\006pmax.b\007pmax.db\007pmax.dh\007pmax.dw\006pm"
6601 "ax.h\006pmax.w\007pmaxu.b\010pmaxu.db\010pmaxu.dh\010pmaxu.dw\007pmaxu."
6602 "h\007pmaxu.w\010pmhacc.h\013pmhacc.h.b0\013pmhacc.h.b1\010pmhacc.w\013p"
6603 "mhacc.w.h0\013pmhacc.w.h1\npmhaccsu.h\015pmhaccsu.h.b0\015pmhaccsu.h.b1"
6604 "\npmhaccsu.w\015pmhaccsu.w.h0\015pmhaccsu.w.h1\tpmhaccu.h\tpmhaccu.w\tp"
6605 "mhracc.h\tpmhracc.w\013pmhraccsu.h\013pmhraccsu.w\npmhraccu.h\npmhraccu"
6606 ".w\006pmin.b\007pmin.db\007pmin.dh\007pmin.dw\006pmin.h\006pmin.w\007pm"
6607 "inu.b\010pminu.db\010pminu.dh\010pminu.dw\007pminu.h\007pminu.w\tpmq2ad"
6608 "d.h\tpmq2add.w\npmq2adda.h\npmq2adda.w\014pmqacc.w.h00\014pmqacc.w.h01\014"
6609 "pmqacc.w.h11\npmqr2add.h\npmqr2add.w\013pmqr2adda.h\013pmqr2adda.w\015p"
6610 "mqracc.w.h00\015pmqracc.w.h01\015pmqracc.w.h11\npmqrwacc.h\tpmqwacc.h\007"
6611 "pmseq.b\010pmseq.db\010pmseq.dh\010pmseq.dw\007pmseq.h\007pmseq.w\010pm"
6612 "seqz.b\tpmseqz.db\tpmseqz.dh\tpmseqz.dw\010pmseqz.h\010pmseqz.w\007pmsg"
6613 "t.b\010pmsgt.db\010pmsgt.dh\010pmsgt.dw\007pmsgt.h\007pmsgt.w\010pmsgtu"
6614 ".b\tpmsgtu.db\tpmsgtu.dh\tpmsgtu.dw\010pmsgtu.h\010pmsgtu.w\010pmsgtz.b"
6615 "\tpmsgtz.db\tpmsgtz.dh\tpmsgtz.dw\010pmsgtz.h\010pmsgtz.w\007pmslt.b\010"
6616 "pmslt.db\010pmslt.dh\010pmslt.dw\007pmslt.h\007pmslt.w\010pmsltu.b\tpms"
6617 "ltu.db\tpmsltu.dh\tpmsltu.dw\010pmsltu.h\010pmsltu.w\010pmsltz.b\tpmslt"
6618 "z.db\tpmsltz.dh\tpmsltz.dw\010pmsltz.h\010pmsltz.w\010pmsnez.b\tpmsnez."
6619 "db\tpmsnez.dh\tpmsnez.dw\010pmsnez.h\010pmsnez.w\npmul.h.b00\npmul.h.b0"
6620 "1\npmul.h.b11\npmul.w.h00\npmul.w.h01\npmul.w.h11\007pmulh.h\npmulh.h.b"
6621 "0\npmulh.h.b1\007pmulh.w\npmulh.w.h0\npmulh.w.h1\010pmulhr.h\010pmulhr."
6622 "w\npmulhrsu.h\npmulhrsu.w\tpmulhru.h\tpmulhru.w\tpmulhsu.h\014pmulhsu.h"
6623 ".b0\014pmulhsu.h.b1\tpmulhsu.w\014pmulhsu.w.h0\014pmulhsu.w.h1\010pmulh"
6624 "u.h\010pmulhu.w\007pmulq.h\007pmulq.w\010pmulqr.h\010pmulqr.w\014pmulsu"
6625 ".h.b00\014pmulsu.h.b11\014pmulsu.w.h00\014pmulsu.w.h11\013pmulu.h.b00\013"
6626 "pmulu.h.b01\013pmulu.h.b11\013pmulu.w.h00\013pmulu.w.h01\013pmulu.w.h11"
6627 "\006pmv.bs\007pmv.dbs\007pmv.dhs\007pmv.dws\006pmv.hs\006pmv.ws\tpnclip"
6628 ".bs\tpnclip.hs\tpnclipi.b\tpnclipi.h\npnclipiu.b\npnclipiu.h\tpnclipp.b"
6629 "\tpnclipp.h\tpnclipp.w\npnclipr.bs\npnclipr.hs\npnclipri.b\npnclipri.h\013"
6630 "pnclipriu.b\013pnclipriu.h\013pnclipru.bs\013pnclipru.hs\npnclipu.bs\np"
6631 "nclipu.hs\npnclipup.b\npnclipup.h\npnclipup.w\007pncvt.b\007pncvt.h\010"
6632 "pncvt.wb\010pncvt.wh\010pncvth.b\010pncvth.h\tpncvth.wb\tpncvth.wh\006p"
6633 "neg.b\007pneg.db\007pneg.dh\007pneg.dw\006pneg.h\006pneg.w\010pnsra.bs\010"
6634 "pnsra.hs\010pnsrai.b\010pnsrai.h\tpnsrar.bs\tpnsrar.hs\tpnsrari.b\tpnsr"
6635 "ari.h\010pnsrl.bs\010pnsrl.hs\010pnsrli.b\010pnsrli.h\010ppaire.b\tppai"
6636 "re.db\tppaire.dh\010ppaire.h\010ppaire.w\tppaireo.b\nppaireo.db\nppaire"
6637 "o.dh\tppaireo.h\tppaireo.w\010ppairo.b\tppairo.db\tppairo.dh\010ppairo."
6638 "h\010ppairo.w\tppairoe.b\nppairoe.db\nppairoe.dh\tppairoe.h\tppairoe.w\n"
6639 "predsum.bs\013predsum.dbs\013predsum.dhs\npredsum.hs\npredsum.ws\013pre"
6640 "dsumu.bs\014predsumu.dbs\014predsumu.dhs\013predsumu.hs\013predsumu.ws\n"
6641 "prefetch.i\nprefetch.r\nprefetch.w\007psa.dhx\006psa.hx\006psa.wx\007ps"
6642 "abs.b\010psabs.db\010psabs.dh\007psabs.h\007psadd.b\010psadd.db\010psad"
6643 "d.dh\010psadd.dw\007psadd.h\007psadd.w\010psaddu.b\tpsaddu.db\tpsaddu.d"
6644 "h\tpsaddu.dw\010psaddu.h\010psaddu.w\010psas.dhx\007psas.hx\007psas.wx\010"
6645 "psati.dh\010psati.dw\007psati.h\007psati.w\npsext.dh.b\npsext.dw.b\npse"
6646 "xt.dw.h\tpsext.h.b\tpsext.w.b\tpsext.w.h\npsh1add.dh\npsh1add.dw\tpsh1a"
6647 "dd.h\tpsh1add.w\007psll.bs\010psll.dbs\010psll.dhs\010psll.dws\007psll."
6648 "hs\007psll.ws\007pslli.b\010pslli.db\010pslli.dh\010pslli.dw\007pslli.h"
6649 "\007pslli.w\007psra.bs\010psra.dbs\010psra.dhs\010psra.dws\007psra.hs\007"
6650 "psra.ws\007psrai.b\010psrai.db\010psrai.dh\010psrai.dw\007psrai.h\007ps"
6651 "rai.w\tpsrari.dh\tpsrari.dw\010psrari.h\010psrari.w\007psrl.bs\010psrl."
6652 "dbs\010psrl.dhs\010psrl.dws\007psrl.hs\007psrl.ws\007psrli.b\010psrli.d"
6653 "b\010psrli.dh\010psrli.dw\007psrli.h\007psrli.w\010pssa.dhx\007pssa.hx\007"
6654 "pssa.wx\014pssh1sadd.dh\014pssh1sadd.dw\013pssh1sadd.h\013pssh1sadd.w\t"
6655 "pssha.dhs\tpssha.dws\010pssha.hs\010pssha.ws\npsshar.dhs\npsshar.dws\tp"
6656 "sshar.hs\tpsshar.ws\tpsshl.dhs\tpsshl.dws\010psshl.hs\010psshl.ws\npssh"
6657 "lr.dhs\npsshlr.dws\tpsshlr.hs\tpsshlr.ws\tpsslai.dh\tpsslai.dw\010pssla"
6658 "i.h\010psslai.w\007pssub.b\010pssub.db\010pssub.dh\010pssub.dw\007pssub"
6659 ".h\007pssub.w\010pssubu.b\tpssubu.db\tpssubu.dh\tpssubu.dw\010pssubu.h\010"
6660 "pssubu.w\006psub.b\007psub.db\007psub.dh\007psub.dw\006psub.h\006psub.w"
6661 "\tpusati.dh\tpusati.dw\010pusati.h\010pusati.w\007pwadd.b\007pwadd.h\010"
6662 "pwadda.b\010pwadda.h\tpwaddau.b\tpwaddau.h\010pwaddu.b\010pwaddu.h\007p"
6663 "wcvt.b\007pwcvt.h\010pwcvth.b\010pwcvth.h\tpwcvth.wb\tpwcvth.wh\010pwcv"
6664 "tu.b\010pwcvtu.h\tpwcvtu.wb\tpwcvtu.wh\010pwmacc.h\npwmaccsu.h\tpwmaccu"
6665 ".h\007pwmul.b\007pwmul.h\tpwmulsu.b\tpwmulsu.h\010pwmulu.b\010pwmulu.h\010"
6666 "pwsla.bs\010pwsla.hs\010pwslai.b\010pwslai.h\010pwsll.bs\010pwsll.hs\010"
6667 "pwslli.b\010pwslli.h\007pwsub.b\007pwsub.h\010pwsuba.b\010pwsuba.h\tpws"
6668 "ubau.b\tpwsubau.h\010pwsubu.b\010pwsubu.h\npzext.dh.b\npzext.dw.h\tpzex"
6669 "t.h.b\tpzext.w.h\tqc.addsat\nqc.addusat\007qc.beqi\007qc.bgei\010qc.bge"
6670 "ui\007qc.blti\010qc.bltui\007qc.bnei\tqc.brev32\nqc.c.bexti\nqc.c.bseti"
6671 "\013qc.c.clrint\nqc.c.delay\007qc.c.di\010qc.c.dir\007qc.c.ei\010qc.c.e"
6672 "ir\tqc.c.extu\014qc.c.mienter\021qc.c.mienter.nest\017qc.c.mileaveret\n"
6673 "qc.c.mnret\tqc.c.mret\014qc.c.muliadd\nqc.c.mveqz\013qc.c.ptrace\013qc."
6674 "c.setint\tqc.c.sync\nqc.c.syncr\013qc.c.syncwf\013qc.c.syncwl\006qc.clo"
6675 "\nqc.clrinti\nqc.cm.jalt\010qc.cm.jt\014qc.cm.mva01s\014qc.cm.mvsa01\tq"
6676 "c.cm.pop\014qc.cm.popret\015qc.cm.popretz\nqc.cm.push\014qc.cm.pushfp\014"
6677 "qc.compress2\014qc.compress3\tqc.csrrwr\nqc.csrrwri\006qc.cto\nqc.e.add"
6678 "ai\tqc.e.addi\nqc.e.andai\tqc.e.andi\tqc.e.beqi\tqc.e.bgei\nqc.e.bgeui\t"
6679 "qc.e.blti\nqc.e.bltui\tqc.e.bnei\006qc.e.j\010qc.e.jal\007qc.e.lb\010qc"
6680 ".e.lbu\007qc.e.lh\010qc.e.lhu\007qc.e.li\007qc.e.lw\tqc.e.orai\010qc.e."
6681 "ori\007qc.e.sb\007qc.e.sh\007qc.e.sw\nqc.e.xorai\tqc.e.xori\nqc.expand2"
6682 "\nqc.expand3\006qc.ext\007qc.extd\tqc.extdpr\nqc.extdprh\010qc.extdr\010"
6683 "qc.extdu\nqc.extdupr\013qc.extduprh\tqc.extdur\007qc.extu\007qc.insb\010"
6684 "qc.insbh\tqc.insbhr\010qc.insbi\tqc.insbpr\nqc.insbprh\010qc.insbr\tqc."
6685 "insbri\006qc.inw\005qc.li\007qc.lieq\010qc.lieqi\007qc.lige\010qc.ligei"
6686 "\010qc.ligeu\tqc.ligeui\007qc.lilt\010qc.lilti\010qc.liltu\tqc.liltui\007"
6687 "qc.line\010qc.linei\006qc.lrb\007qc.lrbu\006qc.lrh\007qc.lrhu\006qc.lrw"
6688 "\006qc.lwm\007qc.lwmi\nqc.muliadd\007qc.mveq\010qc.mveqi\007qc.mvge\010"
6689 "qc.mvgei\010qc.mvgeu\tqc.mvgeui\007qc.mvlt\010qc.mvlti\010qc.mvltu\tqc."
6690 "mvltui\007qc.mvne\010qc.mvnei\007qc.norm\tqc.normeu\010qc.normu\007qc.o"
6691 "utw\014qc.pcoredump\010qc.pexit\010qc.ppreg\tqc.ppregs\010qc.pputc\tqc."
6692 "pputci\010qc.pputs\013qc.psyscall\014qc.psyscalli\014qc.selecteqi\014qc"
6693 ".selectieq\015qc.selectieqi\015qc.selectiieq\015qc.selectiine\014qc.sel"
6694 "ectine\015qc.selectinei\014qc.selectnei\nqc.setinti\010qc.setwm\tqc.set"
6695 "wmi\tqc.shladd\tqc.shlsat\nqc.shlusat\006qc.srb\006qc.srh\006qc.srw\tqc"
6696 ".subsat\nqc.subusat\006qc.swm\007qc.swmi\007qc.sync\010qc.syncr\tqc.syn"
6697 "cwf\tqc.syncwl\007qc.wrap\010qc.wrapi\010qk.c.lbu\nqk.c.lbusp\010qk.c.l"
6698 "hu\nqk.c.lhusp\007qk.c.sb\tqk.c.sbsp\007qk.c.sh\tqk.c.shsp\007rdcycle\010"
6699 "rdcycleh\trdinstret\nrdinstreth\006rdtime\007rdtimeh\003rem\004remu\005"
6700 "remuw\004remw\003ret\003rev\005rev16\004rev8\003rol\004rolw\003ror\004r"
6701 "ori\005roriw\004rorw\004sadd\005saddu\004sati\002sb\007sb.aqrl\005sb.rl"
6702 "\004sc.d\007sc.d.aq\tsc.d.aqrl\007sc.d.rl\004sc.w\007sc.w.aq\tsc.w.aqrl"
6703 "\007sc.w.rl\007sctrclr\002sd\007sd.aqrl\005sd.rl\004seqz\006sext.b\006s"
6704 "ext.h\006sext.w\020sf.cdiscard.d.l1\010sf.cease\016sf.cflush.d.l1\017sf"
6705 ".mm.e4m3.e4m3\017sf.mm.e4m3.e5m2\017sf.mm.e5m2.e4m3\017sf.mm.e5m2.e5m2\t"
6706 "sf.mm.f.f\tsf.mm.s.s\tsf.mm.s.u\tsf.mm.u.s\tsf.mm.u.u\010sf.vc.fv\tsf.v"
6707 "c.fvv\tsf.vc.fvw\007sf.vc.i\010sf.vc.iv\tsf.vc.ivv\tsf.vc.ivw\nsf.vc.v."
6708 "fv\013sf.vc.v.fvv\013sf.vc.v.fvw\tsf.vc.v.i\nsf.vc.v.iv\013sf.vc.v.ivv\013"
6709 "sf.vc.v.ivw\nsf.vc.v.vv\013sf.vc.v.vvv\013sf.vc.v.vvw\tsf.vc.v.x\nsf.vc"
6710 ".v.xv\013sf.vc.v.xvv\013sf.vc.v.xvw\010sf.vc.vv\tsf.vc.vvv\tsf.vc.vvw\007"
6711 "sf.vc.x\010sf.vc.xv\tsf.vc.xvv\tsf.vc.xvw\nsf.vfexp.v\013sf.vfexpa.v\022"
6712 "sf.vfnrclip.x.f.qf\023sf.vfnrclip.xu.f.qf\020sf.vfwmacc.4x4x4\tsf.vlte1"
6713 "6\tsf.vlte32\tsf.vlte64\010sf.vlte8\017sf.vqmacc.2x8x2\017sf.vqmacc.4x8"
6714 "x4\021sf.vqmaccsu.2x8x2\021sf.vqmaccsu.4x8x4\020sf.vqmaccu.2x8x2\020sf."
6715 "vqmaccu.4x8x4\021sf.vqmaccus.2x8x2\021sf.vqmaccus.4x8x4\tsf.vsettk\tsf."
6716 "vsettm\tsf.vsettn\nsf.vsettnt\tsf.vste16\tsf.vste32\tsf.vste64\010sf.vs"
6717 "te8\014sf.vtdiscard\013sf.vtmv.t.v\013sf.vtmv.v.t\013sf.vtzero.t\017sfe"
6718 "nce.inval.ir\nsfence.vma\016sfence.w.inval\003sgt\004sgtu\004sgtz\002sh"
6719 "\007sh.aqrl\005sh.rl\006sh1add\tsh1add.uw\006sh2add\tsh2add.uw\006sh3ad"
6720 "d\tsh3add.uw\003sha\nsha256sig0\nsha256sig1\nsha256sum0\nsha256sum1\nsh"
6721 "a512sig0\013sha512sig0h\013sha512sig0l\nsha512sig1\013sha512sig1h\013sh"
6722 "a512sig1l\nsha512sum0\013sha512sum0r\nsha512sum1\013sha512sum1r\004shar"
6723 "\003shl\004shlr\nsinval.vma\003sll\004slli\007slli.uw\005slliw\004sllw\003"
6724 "slt\004slti\005sltiu\004sltu\004sltz\003slx\005sm3p0\005sm3p1\005sm4ed\005"
6725 "sm4ks\014smt.vfwmadot\015smt.vfwmadot1\015smt.vfwmadot2\015smt.vfwmadot"
6726 "3\nsmt.vmadot\015smt.vmadot.hp\015smt.vmadot.sp\013smt.vmadot1\015smt.v"
6727 "madot1su\014smt.vmadot1u\015smt.vmadot1us\013smt.vmadot2\015smt.vmadot2"
6728 "su\014smt.vmadot2u\015smt.vmadot2us\013smt.vmadot3\015smt.vmadot3su\014"
6729 "smt.vmadot3u\015smt.vmadot3us\014smt.vmadotsu\017smt.vmadotsu.hp\017smt"
6730 ".vmadotsu.sp\013smt.vmadotu\016smt.vmadotu.hp\016smt.vmadotu.sp\014smt."
6731 "vmadotus\017smt.vmadotus.hp\017smt.vmadotus.sp\015smt.vnpack.vv\016smt."
6732 "vnpack4.vv\016smt.vnspack.vv\017smt.vnspack4.vv\014smt.vpack.vv\015smt."
6733 "vupack.vv\004snez\003sra\004srai\005sraiw\005srari\004sraw\004sret\003s"
6734 "rl\004srli\005srliw\005srliy\004srlw\003srx\013ssamoswap.d\016ssamoswap"
6735 ".d.aq\020ssamoswap.d.aqrl\016ssamoswap.d.rl\013ssamoswap.w\016ssamoswap"
6736 ".w.aq\020ssamoswap.w.aqrl\016ssamoswap.w.rl\010ssh1sadd\004ssha\005ssha"
6737 "r\004sshl\005sshlr\005sslai\010sspopchk\006sspush\005ssrdp\004ssub\005s"
6738 "subu\003sub\004subd\004subw\002sw\007sw.aqrl\005sw.rl\004tail\010th.add"
6739 "sl\016th.dcache.call\017th.dcache.ciall\016th.dcache.cipa\016th.dcache."
6740 "cisw\016th.dcache.civa\015th.dcache.cpa\017th.dcache.cpal1\015th.dcache"
6741 ".csw\015th.dcache.cva\017th.dcache.cval1\016th.dcache.iall\015th.dcache"
6742 ".ipa\015th.dcache.isw\015th.dcache.iva\006th.ext\007th.extu\006th.ff0\006"
6743 "th.ff1\007th.flrd\007th.flrw\010th.flurd\010th.flurw\007th.fsrd\007th.f"
6744 "srw\010th.fsurd\010th.fsurw\016th.icache.iall\017th.icache.ialls\015th."
6745 "icache.ipa\015th.icache.iva\017th.l2cache.call\020th.l2cache.ciall\017t"
6746 "h.l2cache.iall\007th.lbia\007th.lbib\010th.lbuia\010th.lbuib\006th.ldd\007"
6747 "th.ldia\007th.ldib\007th.lhia\007th.lhib\010th.lhuia\010th.lhuib\006th."
6748 "lrb\007th.lrbu\006th.lrd\006th.lrh\007th.lrhu\006th.lrw\007th.lrwu\007t"
6749 "h.lurb\010th.lurbu\007th.lurd\007th.lurh\010th.lurhu\007th.lurw\010th.l"
6750 "urwu\006th.lwd\007th.lwia\007th.lwib\007th.lwud\010th.lwuia\010th.lwuib"
6751 "\007th.mula\010th.mulah\010th.mulaw\007th.muls\010th.mulsh\010th.mulsw\010"
6752 "th.mveqz\010th.mvnez\006th.rev\007th.revw\007th.sbia\007th.sbib\006th.s"
6753 "dd\007th.sdia\007th.sdib\016th.sfence.vmas\007th.shia\007th.shib\006th."
6754 "srb\006th.srd\006th.srh\007th.srri\010th.srriw\006th.srw\007th.surb\007"
6755 "th.surd\007th.surh\007th.surw\006th.swd\007th.swia\007th.swib\007th.syn"
6756 "c\tth.sync.i\nth.sync.is\tth.sync.s\006th.tst\tth.tstnbz\013th.vmaqa.vv"
6757 "\013th.vmaqa.vx\015th.vmaqasu.vv\015th.vmaqasu.vx\014th.vmaqau.vv\014th"
6758 ".vmaqau.vx\015th.vmaqaus.vx\005unimp\005unzip\tunzip16hp\010unzip16p\010"
6759 "unzip8hp\007unzip8p\005usati\013v8wmmacc.vv\010vaadd.vv\010vaadd.vx\tva"
6760 "addu.vv\tvaaddu.vx\007vabd.vv\010vabdu.vv\006vabs.v\010vadc.vim\010vadc"
6761 ".vvm\010vadc.vxm\007vadd.vi\007vadd.vv\007vadd.vx\tvaesdf.vs\tvaesdf.vv"
6762 "\tvaesdm.vs\tvaesdm.vv\tvaesef.vs\tvaesef.vv\tvaesem.vs\tvaesem.vv\nvae"
6763 "skf1.vi\nvaeskf2.vi\010vaesz.vs\007vand.vi\007vand.vv\007vand.vx\010van"
6764 "dn.vv\010vandn.vx\010vasub.vv\010vasub.vx\tvasubu.vv\tvasubu.vx\007vbre"
6765 "v.v\010vbrev8.v\tvclmul.vv\tvclmul.vx\nvclmulh.vv\nvclmulh.vx\006vclz.v"
6766 "\014vcompress.vm\007vcpop.m\007vcpop.v\006vctz.v\007vdiv.vv\007vdiv.vx\010"
6767 "vdivu.vv\010vdivu.vx\tvdot4a.vv\tvdot4a.vx\013vdot4asu.vv\013vdot4asu.v"
6768 "x\nvdot4au.vv\nvdot4au.vx\013vdot4aus.vx\015vf8wimmacc.vv\014vf8wmmacc."
6769 "vv\007vfabs.v\010vfadd.vf\010vfadd.vv\nvfbdota.vv\tvfclass.v\013vfcvt.f"
6770 ".x.v\014vfcvt.f.xu.v\017vfcvt.rtz.x.f.v\020vfcvt.rtz.xu.f.v\013vfcvt.x."
6771 "f.v\014vfcvt.xu.f.v\010vfdiv.vf\010vfdiv.vv\010vfirst.m\tvfmacc.vf\tvfm"
6772 "acc.vv\tvfmadd.vf\tvfmadd.vv\010vfmax.vf\010vfmax.vv\013vfmerge.vfm\010"
6773 "vfmin.vf\010vfmin.vv\nvfmmacc.vv\tvfmsac.vf\tvfmsac.vv\tvfmsub.vf\tvfms"
6774 "ub.vv\010vfmul.vf\010vfmul.vv\010vfmv.f.s\010vfmv.s.f\010vfmv.v.f\014vf"
6775 "ncvt.f.f.q\014vfncvt.f.f.w\014vfncvt.f.x.w\015vfncvt.f.xu.w\020vfncvt.r"
6776 "od.f.f.w\020vfncvt.rtz.x.f.w\021vfncvt.rtz.xu.f.w\020vfncvt.sat.f.f.q\014"
6777 "vfncvt.x.f.w\015vfncvt.xu.f.w\020vfncvtbf16.f.f.w\024vfncvtbf16.sat.f.f"
6778 ".w\007vfneg.v\nvfnmacc.vf\nvfnmacc.vv\nvfnmadd.vf\nvfnmadd.vv\nvfnmsac."
6779 "vf\nvfnmsac.vv\nvfnmsub.vf\nvfnmsub.vv\014vfqimmacc.vv\013vfqmmacc.vv\020"
6780 "vfqwbdota.alt.vv\014vfqwbdota.vv\017vfqwdota.alt.vv\013vfqwdota.vv\tvfr"
6781 "div.vf\010vfrec7.v\013vfredmax.vs\013vfredmin.vs\014vfredosum.vs\014vfr"
6782 "edusum.vs\nvfrsqrt7.v\tvfrsub.vf\tvfsgnj.vf\tvfsgnj.vv\nvfsgnjn.vf\nvfs"
6783 "gnjn.vv\nvfsgnjx.vf\nvfsgnjx.vv\017vfslide1down.vf\015vfslide1up.vf\010"
6784 "vfsqrt.v\010vfsub.vf\010vfsub.vv\tvfwadd.vf\tvfwadd.vv\tvfwadd.wf\tvfwa"
6785 "dd.wv\013vfwbdota.vv\014vfwcvt.f.f.v\014vfwcvt.f.x.v\015vfwcvt.f.xu.v\020"
6786 "vfwcvt.rtz.x.f.v\021vfwcvt.rtz.xu.f.v\014vfwcvt.x.f.v\015vfwcvt.xu.f.v\020"
6787 "vfwcvtbf16.f.f.v\nvfwdota.vv\014vfwimmacc.vv\nvfwmacc.vf\nvfwmacc.vv\016"
6788 "vfwmaccbf16.vf\016vfwmaccbf16.vv\013vfwmmacc.vv\nvfwmsac.vf\nvfwmsac.vv"
6789 "\tvfwmul.vf\tvfwmul.vv\013vfwnmacc.vf\013vfwnmacc.vv\013vfwnmsac.vf\013"
6790 "vfwnmsac.vv\015vfwredosum.vs\015vfwredusum.vs\tvfwsub.vf\tvfwsub.vv\tvf"
6791 "wsub.wf\tvfwsub.wv\010vghsh.vs\010vghsh.vv\010vgmul.vs\010vgmul.vv\005v"
6792 "id.v\007viota.m\006vl1r.v\tvl1re16.v\tvl1re32.v\tvl1re64.v\010vl1re8.v\006"
6793 "vl2r.v\tvl2re16.v\tvl2re32.v\tvl2re64.v\010vl2re8.v\006vl4r.v\tvl4re16."
6794 "v\tvl4re32.v\tvl4re64.v\010vl4re8.v\006vl8r.v\tvl8re16.v\tvl8re32.v\tvl"
6795 "8re64.v\010vl8re8.v\007vle16.v\tvle16ff.v\007vle32.v\tvle32ff.v\007vle6"
6796 "4.v\tvle64ff.v\006vle8.v\010vle8ff.v\005vlm.v\nvloxei16.v\nvloxei32.v\n"
6797 "vloxei64.v\tvloxei8.v\016vloxseg2ei16.v\016vloxseg2ei32.v\016vloxseg2ei"
6798 "64.v\015vloxseg2ei8.v\016vloxseg3ei16.v\016vloxseg3ei32.v\016vloxseg3ei"
6799 "64.v\015vloxseg3ei8.v\016vloxseg4ei16.v\016vloxseg4ei32.v\016vloxseg4ei"
6800 "64.v\015vloxseg4ei8.v\016vloxseg5ei16.v\016vloxseg5ei32.v\016vloxseg5ei"
6801 "64.v\015vloxseg5ei8.v\016vloxseg6ei16.v\016vloxseg6ei32.v\016vloxseg6ei"
6802 "64.v\015vloxseg6ei8.v\016vloxseg7ei16.v\016vloxseg7ei32.v\016vloxseg7ei"
6803 "64.v\015vloxseg7ei8.v\016vloxseg8ei16.v\016vloxseg8ei32.v\016vloxseg8ei"
6804 "64.v\015vloxseg8ei8.v\010vlse16.v\010vlse32.v\010vlse64.v\007vlse8.v\013"
6805 "vlseg2e16.v\015vlseg2e16ff.v\013vlseg2e32.v\015vlseg2e32ff.v\013vlseg2e"
6806 "64.v\015vlseg2e64ff.v\nvlseg2e8.v\014vlseg2e8ff.v\013vlseg3e16.v\015vls"
6807 "eg3e16ff.v\013vlseg3e32.v\015vlseg3e32ff.v\013vlseg3e64.v\015vlseg3e64f"
6808 "f.v\nvlseg3e8.v\014vlseg3e8ff.v\013vlseg4e16.v\015vlseg4e16ff.v\013vlse"
6809 "g4e32.v\015vlseg4e32ff.v\013vlseg4e64.v\015vlseg4e64ff.v\nvlseg4e8.v\014"
6810 "vlseg4e8ff.v\013vlseg5e16.v\015vlseg5e16ff.v\013vlseg5e32.v\015vlseg5e3"
6811 "2ff.v\013vlseg5e64.v\015vlseg5e64ff.v\nvlseg5e8.v\014vlseg5e8ff.v\013vl"
6812 "seg6e16.v\015vlseg6e16ff.v\013vlseg6e32.v\015vlseg6e32ff.v\013vlseg6e64"
6813 ".v\015vlseg6e64ff.v\nvlseg6e8.v\014vlseg6e8ff.v\013vlseg7e16.v\015vlseg"
6814 "7e16ff.v\013vlseg7e32.v\015vlseg7e32ff.v\013vlseg7e64.v\015vlseg7e64ff."
6815 "v\nvlseg7e8.v\014vlseg7e8ff.v\013vlseg8e16.v\015vlseg8e16ff.v\013vlseg8"
6816 "e32.v\015vlseg8e32ff.v\013vlseg8e64.v\015vlseg8e64ff.v\nvlseg8e8.v\014v"
6817 "lseg8e8ff.v\014vlsseg2e16.v\014vlsseg2e32.v\014vlsseg2e64.v\013vlsseg2e"
6818 "8.v\014vlsseg3e16.v\014vlsseg3e32.v\014vlsseg3e64.v\013vlsseg3e8.v\014v"
6819 "lsseg4e16.v\014vlsseg4e32.v\014vlsseg4e64.v\013vlsseg4e8.v\014vlsseg5e1"
6820 "6.v\014vlsseg5e32.v\014vlsseg5e64.v\013vlsseg5e8.v\014vlsseg6e16.v\014v"
6821 "lsseg6e32.v\014vlsseg6e64.v\013vlsseg6e8.v\014vlsseg7e16.v\014vlsseg7e3"
6822 "2.v\014vlsseg7e64.v\013vlsseg7e8.v\014vlsseg8e16.v\014vlsseg8e32.v\014v"
6823 "lsseg8e64.v\013vlsseg8e8.v\nvluxei16.v\nvluxei32.v\nvluxei64.v\tvluxei8"
6824 ".v\016vluxseg2ei16.v\016vluxseg2ei32.v\016vluxseg2ei64.v\015vluxseg2ei8"
6825 ".v\016vluxseg3ei16.v\016vluxseg3ei32.v\016vluxseg3ei64.v\015vluxseg3ei8"
6826 ".v\016vluxseg4ei16.v\016vluxseg4ei32.v\016vluxseg4ei64.v\015vluxseg4ei8"
6827 ".v\016vluxseg5ei16.v\016vluxseg5ei32.v\016vluxseg5ei64.v\015vluxseg5ei8"
6828 ".v\016vluxseg6ei16.v\016vluxseg6ei32.v\016vluxseg6ei64.v\015vluxseg6ei8"
6829 ".v\016vluxseg7ei16.v\016vluxseg7ei32.v\016vluxseg7ei64.v\015vluxseg7ei8"
6830 ".v\016vluxseg8ei16.v\016vluxseg8ei32.v\016vluxseg8ei64.v\015vluxseg8ei8"
6831 ".v\010vmacc.vv\010vmacc.vx\010vmadc.vi\tvmadc.vim\010vmadc.vv\tvmadc.vv"
6832 "m\010vmadc.vx\tvmadc.vxm\010vmadd.vv\010vmadd.vx\010vmand.mm\tvmandn.mm"
6833 "\007vmax.vv\007vmax.vx\010vmaxu.vv\010vmaxu.vx\007vmclr.m\nvmerge.vim\n"
6834 "vmerge.vvm\nvmerge.vxm\010vmfeq.vf\010vmfeq.vv\010vmfge.vf\010vmfge.vv\010"
6835 "vmfgt.vf\010vmfgt.vv\010vmfle.vf\010vmfle.vv\010vmflt.vf\010vmflt.vv\010"
6836 "vmfne.vf\010vmfne.vv\007vmin.vv\007vmin.vx\010vminu.vv\010vminu.vx\tvmm"
6837 "acc.vv\006vmmv.m\tvmnand.mm\010vmnor.mm\007vmnot.m\007vmor.mm\010vmorn."
6838 "mm\010vmsbc.vv\tvmsbc.vvm\010vmsbc.vx\tvmsbc.vxm\007vmsbf.m\010vmseq.vi"
6839 "\010vmseq.vv\010vmseq.vx\007vmset.m\010vmsge.vi\010vmsge.vv\010vmsge.vx"
6840 "\tvmsgeu.vi\tvmsgeu.vv\tvmsgeu.vx\010vmsgt.vi\010vmsgt.vv\010vmsgt.vx\t"
6841 "vmsgtu.vi\tvmsgtu.vv\tvmsgtu.vx\007vmsif.m\010vmsle.vi\010vmsle.vv\010v"
6842 "msle.vx\tvmsleu.vi\tvmsleu.vv\tvmsleu.vx\010vmslt.vi\010vmslt.vv\010vms"
6843 "lt.vx\tvmsltu.vi\tvmsltu.vv\tvmsltu.vx\010vmsne.vi\010vmsne.vv\010vmsne"
6844 ".vx\007vmsof.m\006vmtl.v\006vmts.v\007vmttl.v\007vmtts.v\007vmul.vv\007"
6845 "vmul.vx\010vmulh.vv\010vmulh.vx\nvmulhsu.vv\nvmulhsu.vx\tvmulhu.vv\tvmu"
6846 "lhu.vx\007vmv.s.x\007vmv.v.i\007vmv.v.v\007vmv.v.x\007vmv.x.s\007vmv1r."
6847 "v\007vmv2r.v\007vmv4r.v\007vmv8r.v\tvmxnor.mm\010vmxor.mm\tvnclip.wi\tv"
6848 "nclip.wv\tvnclip.wx\nvnclipu.wi\nvnclipu.wv\nvnclipu.wx\013vncvt.x.x.w\006"
6849 "vneg.v\tvnmsac.vv\tvnmsac.vx\tvnmsub.vv\tvnmsub.vx\006vnot.v\010vnsra.w"
6850 "i\010vnsra.wv\010vnsra.wx\010vnsrl.wi\010vnsrl.wv\010vnsrl.wx\006vor.vi"
6851 "\006vor.vv\006vor.vx\tvpaire.vv\tvpairo.vv\nvqmmacc.vv\014vqwbdotas.vv\014"
6852 "vqwbdotau.vv\013vqwdotas.vv\013vqwdotau.vv\nvredand.vs\nvredmax.vs\013v"
6853 "redmaxu.vs\nvredmin.vs\013vredminu.vs\tvredor.vs\nvredsum.vs\nvredxor.v"
6854 "s\007vrem.vv\007vrem.vx\010vremu.vv\010vremu.vx\007vrev8.v\013vrgather."
6855 "vi\013vrgather.vv\013vrgather.vx\017vrgatherei16.vv\007vrol.vv\007vrol."
6856 "vx\007vror.vi\007vror.vv\007vror.vx\010vrsub.vi\010vrsub.vx\006vs1r.v\006"
6857 "vs2r.v\006vs4r.v\006vs8r.v\010vsadd.vi\010vsadd.vv\010vsadd.vx\tvsaddu."
6858 "vi\tvsaddu.vv\tvsaddu.vx\010vsbc.vvm\010vsbc.vxm\007vse16.v\007vse32.v\007"
6859 "vse64.v\006vse8.v\010vsetivli\006vsetvl\007vsetvli\tvsext.vf2\tvsext.vf"
6860 "4\tvsext.vf8\nvsha2ch.vv\nvsha2cl.vv\nvsha2ms.vv\016vslide1down.vx\014v"
6861 "slide1up.vx\015vslidedown.vi\015vslidedown.vx\013vslideup.vi\013vslideu"
6862 "p.vx\007vsll.vi\007vsll.vv\007vsll.vx\005vsm.v\010vsm3c.vi\tvsm3me.vv\010"
6863 "vsm4k.vi\010vsm4r.vs\010vsm4r.vv\010vsmul.vv\010vsmul.vx\nvsoxei16.v\nv"
6864 "soxei32.v\nvsoxei64.v\tvsoxei8.v\016vsoxseg2ei16.v\016vsoxseg2ei32.v\016"
6865 "vsoxseg2ei64.v\015vsoxseg2ei8.v\016vsoxseg3ei16.v\016vsoxseg3ei32.v\016"
6866 "vsoxseg3ei64.v\015vsoxseg3ei8.v\016vsoxseg4ei16.v\016vsoxseg4ei32.v\016"
6867 "vsoxseg4ei64.v\015vsoxseg4ei8.v\016vsoxseg5ei16.v\016vsoxseg5ei32.v\016"
6868 "vsoxseg5ei64.v\015vsoxseg5ei8.v\016vsoxseg6ei16.v\016vsoxseg6ei32.v\016"
6869 "vsoxseg6ei64.v\015vsoxseg6ei8.v\016vsoxseg7ei16.v\016vsoxseg7ei32.v\016"
6870 "vsoxseg7ei64.v\015vsoxseg7ei8.v\016vsoxseg8ei16.v\016vsoxseg8ei32.v\016"
6871 "vsoxseg8ei64.v\015vsoxseg8ei8.v\007vsra.vi\007vsra.vv\007vsra.vx\007vsr"
6872 "l.vi\007vsrl.vv\007vsrl.vx\010vsse16.v\010vsse32.v\010vsse64.v\007vsse8"
6873 ".v\013vsseg2e16.v\013vsseg2e32.v\013vsseg2e64.v\nvsseg2e8.v\013vsseg3e1"
6874 "6.v\013vsseg3e32.v\013vsseg3e64.v\nvsseg3e8.v\013vsseg4e16.v\013vsseg4e"
6875 "32.v\013vsseg4e64.v\nvsseg4e8.v\013vsseg5e16.v\013vsseg5e32.v\013vsseg5"
6876 "e64.v\nvsseg5e8.v\013vsseg6e16.v\013vsseg6e32.v\013vsseg6e64.v\nvsseg6e"
6877 "8.v\013vsseg7e16.v\013vsseg7e32.v\013vsseg7e64.v\nvsseg7e8.v\013vsseg8e"
6878 "16.v\013vsseg8e32.v\013vsseg8e64.v\nvsseg8e8.v\010vssra.vi\010vssra.vv\010"
6879 "vssra.vx\010vssrl.vi\010vssrl.vv\010vssrl.vx\014vssseg2e16.v\014vssseg2"
6880 "e32.v\014vssseg2e64.v\013vssseg2e8.v\014vssseg3e16.v\014vssseg3e32.v\014"
6881 "vssseg3e64.v\013vssseg3e8.v\014vssseg4e16.v\014vssseg4e32.v\014vssseg4e"
6882 "64.v\013vssseg4e8.v\014vssseg5e16.v\014vssseg5e32.v\014vssseg5e64.v\013"
6883 "vssseg5e8.v\014vssseg6e16.v\014vssseg6e32.v\014vssseg6e64.v\013vssseg6e"
6884 "8.v\014vssseg7e16.v\014vssseg7e32.v\014vssseg7e64.v\013vssseg7e8.v\014v"
6885 "ssseg8e16.v\014vssseg8e32.v\014vssseg8e64.v\013vssseg8e8.v\010vssub.vv\010"
6886 "vssub.vx\tvssubu.vv\tvssubu.vx\007vsub.vv\007vsub.vx\nvsuxei16.v\nvsuxe"
6887 "i32.v\nvsuxei64.v\tvsuxei8.v\016vsuxseg2ei16.v\016vsuxseg2ei32.v\016vsu"
6888 "xseg2ei64.v\015vsuxseg2ei8.v\016vsuxseg3ei16.v\016vsuxseg3ei32.v\016vsu"
6889 "xseg3ei64.v\015vsuxseg3ei8.v\016vsuxseg4ei16.v\016vsuxseg4ei32.v\016vsu"
6890 "xseg4ei64.v\015vsuxseg4ei8.v\016vsuxseg5ei16.v\016vsuxseg5ei32.v\016vsu"
6891 "xseg5ei64.v\015vsuxseg5ei8.v\016vsuxseg6ei16.v\016vsuxseg6ei32.v\016vsu"
6892 "xseg6ei64.v\015vsuxseg6ei8.v\016vsuxseg7ei16.v\016vsuxseg7ei32.v\016vsu"
6893 "xseg7ei64.v\015vsuxseg7ei8.v\016vsuxseg8ei16.v\016vsuxseg8ei32.v\016vsu"
6894 "xseg8ei64.v\015vsuxseg8ei8.v\010vt.maskc\tvt.maskcn\tvunzipe.v\tvunzipo"
6895 ".v\tvwabda.vv\nvwabdau.vv\010vwadd.vv\010vwadd.vx\010vwadd.wv\010vwadd."
6896 "wx\tvwaddu.vv\tvwaddu.vx\tvwaddu.wv\tvwaddu.wx\013vwcvt.x.x.v\014vwcvtu"
6897 ".x.x.v\tvwmacc.vv\tvwmacc.vx\013vwmaccsu.vv\013vwmaccsu.vx\nvwmaccu.vv\n"
6898 "vwmaccu.vx\013vwmaccus.vx\nvwmmacc.vv\010vwmul.vv\010vwmul.vx\nvwmulsu."
6899 "vv\nvwmulsu.vx\tvwmulu.vv\tvwmulu.vx\013vwredsum.vs\014vwredsumu.vs\010"
6900 "vwsll.vi\010vwsll.vv\010vwsll.vx\010vwsub.vv\010vwsub.vx\010vwsub.wv\010"
6901 "vwsub.wx\tvwsubu.vv\tvwsubu.vx\tvwsubu.wv\tvwsubu.wx\007vxor.vi\007vxor"
6902 ".vv\007vxor.vx\tvzext.vf2\tvzext.vf4\tvzext.vf8\007vzip.vv\004wadd\005w"
6903 "adda\006waddau\005waddu\003wfi\005wmacc\007wmaccsu\006wmaccu\004wmul\006"
6904 "wmulsu\005wmulu\007wrs.nto\007wrs.sto\004wsla\005wslai\004wsll\005wslli"
6905 "\004wsub\005wsuba\006wsubau\005wsubu\007wzip16p\006wzip8p\004xnor\003xo"
6906 "r\004xori\006xperm4\006xperm8\004yadd\005yaddi\006yaddrw\006yamask\006y"
6907 "baser\004ybld\007ybndsrw\006ybndsw\007ybndswi\003yeq\004yhir\005ylenr\003"
6908 "ymv\006ypermc\006ypermr\003yss\010ysunseal\005ytagr\005ytopr\006ytyper\006"
6909 "zext.b\006zext.h\006zext.w\003zip\007zip16hp\006zip16p\006zip8hp\005zip"
6910 "8p";
6911
6912// Feature bitsets.
6913enum : uint8_t {
6914 AMFBS_None,
6915 AMFBS_HasHalfFPLoadStoreMove,
6916 AMFBS_HasStdExtD,
6917 AMFBS_HasStdExtF,
6918 AMFBS_HasStdExtFOrZfinx,
6919 AMFBS_HasStdExtH,
6920 AMFBS_HasStdExtM,
6921 AMFBS_HasStdExtP,
6922 AMFBS_HasStdExtQ,
6923 AMFBS_HasStdExtSmctrOrSsctr,
6924 AMFBS_HasStdExtSmrnmi,
6925 AMFBS_HasStdExtSvinval,
6926 AMFBS_HasStdExtY,
6927 AMFBS_HasStdExtZaamo,
6928 AMFBS_HasStdExtZabha,
6929 AMFBS_HasStdExtZacas,
6930 AMFBS_HasStdExtZalasr,
6931 AMFBS_HasStdExtZalrsc,
6932 AMFBS_HasStdExtZawrs,
6933 AMFBS_HasStdExtZba,
6934 AMFBS_HasStdExtZbb,
6935 AMFBS_HasStdExtZbbOrZbkb,
6936 AMFBS_HasStdExtZbc,
6937 AMFBS_HasStdExtZbkb,
6938 AMFBS_HasStdExtZbkbOrP,
6939 AMFBS_HasStdExtZbkc,
6940 AMFBS_HasStdExtZbkx,
6941 AMFBS_HasStdExtZbs,
6942 AMFBS_HasStdExtZca,
6943 AMFBS_HasStdExtZcb,
6944 AMFBS_HasStdExtZcd,
6945 AMFBS_HasStdExtZcmop,
6946 AMFBS_HasStdExtZcmp,
6947 AMFBS_HasStdExtZcmt,
6948 AMFBS_HasStdExtZfa,
6949 AMFBS_HasStdExtZfbfmin,
6950 AMFBS_HasStdExtZfh,
6951 AMFBS_HasStdExtZfhmin,
6952 AMFBS_HasStdExtZfinx,
6953 AMFBS_HasStdExtZhinx,
6954 AMFBS_HasStdExtZhinxmin,
6955 AMFBS_HasStdExtZibi,
6956 AMFBS_HasStdExtZicbom,
6957 AMFBS_HasStdExtZicboz,
6958 AMFBS_HasStdExtZicfiss,
6959 AMFBS_HasStdExtZicond,
6960 AMFBS_HasStdExtZimop,
6961 AMFBS_HasStdExtZknh,
6962 AMFBS_HasStdExtZksed,
6963 AMFBS_HasStdExtZksh,
6964 AMFBS_HasStdExtZmmul,
6965 AMFBS_HasStdExtZvabd,
6966 AMFBS_HasStdExtZvbb,
6967 AMFBS_HasStdExtZvbcOrZvbc32e,
6968 AMFBS_HasStdExtZvdot4a8i,
6969 AMFBS_HasStdExtZvfbdota32f,
6970 AMFBS_HasStdExtZvfbfminOrZvfofp8min,
6971 AMFBS_HasStdExtZvfbfwma,
6972 AMFBS_HasStdExtZvfofp8min,
6973 AMFBS_HasStdExtZvfqwbdota8f,
6974 AMFBS_HasStdExtZvfqwdota8f,
6975 AMFBS_HasStdExtZvfwbdota16bf,
6976 AMFBS_HasStdExtZvfwdota16bf,
6977 AMFBS_HasStdExtZvkb,
6978 AMFBS_HasStdExtZvkg,
6979 AMFBS_HasStdExtZvkgs,
6980 AMFBS_HasStdExtZvkned,
6981 AMFBS_HasStdExtZvknha,
6982 AMFBS_HasStdExtZvksed,
6983 AMFBS_HasStdExtZvksh,
6984 AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i,
6985 AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i,
6986 AMFBS_HasStdExtZvvfmm,
6987 AMFBS_HasStdExtZvvmm,
6988 AMFBS_HasStdExtZvvmtls,
6989 AMFBS_HasStdExtZvvmttls,
6990 AMFBS_HasStdExtZvzip,
6991 AMFBS_HasVInstructions,
6992 AMFBS_HasVInstructionsAnyF,
6993 AMFBS_HasVInstructionsI64,
6994 AMFBS_HasVendorXAndesBFHCvt,
6995 AMFBS_HasVendorXAndesPerf,
6996 AMFBS_HasVendorXAndesVBFHCvt,
6997 AMFBS_HasVendorXAndesVDot,
6998 AMFBS_HasVendorXAndesVPackFPH,
6999 AMFBS_HasVendorXAndesVSIntH,
7000 AMFBS_HasVendorXAndesVSIntLoad,
7001 AMFBS_HasVendorXMIPSCBOP,
7002 AMFBS_HasVendorXMIPSCMov,
7003 AMFBS_HasVendorXMIPSEXECTL,
7004 AMFBS_HasVendorXMIPSLSP,
7005 AMFBS_HasVendorXSfcease,
7006 AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f,
7007 AMFBS_HasVendorXSfmm32a8f,
7008 AMFBS_HasVendorXSfmm32a8i,
7009 AMFBS_HasVendorXSfmmbase,
7010 AMFBS_HasVendorXSfvcp,
7011 AMFBS_HasVendorXSfvfexpAny,
7012 AMFBS_HasVendorXSfvfexpa,
7013 AMFBS_HasVendorXSfvfnrclipxfqf,
7014 AMFBS_HasVendorXSfvfwmaccqqq,
7015 AMFBS_HasVendorXSfvqmaccdod,
7016 AMFBS_HasVendorXSfvqmaccqoq,
7017 AMFBS_HasVendorXSiFivecdiscarddlone,
7018 AMFBS_HasVendorXSiFivecflushdlone,
7019 AMFBS_HasVendorXTHeadBa,
7020 AMFBS_HasVendorXTHeadBb,
7021 AMFBS_HasVendorXTHeadBs,
7022 AMFBS_HasVendorXTHeadCmo,
7023 AMFBS_HasVendorXTHeadCondMov,
7024 AMFBS_HasVendorXTHeadMac,
7025 AMFBS_HasVendorXTHeadMemIdx,
7026 AMFBS_HasVendorXTHeadMemPair,
7027 AMFBS_HasVendorXTHeadSync,
7028 AMFBS_HasVendorXTHeadVdot,
7029 AMFBS_HasVendorXVentanaCondOps,
7030 AMFBS_HasVendorXqccmp,
7031 AMFBS_HasVendorXqccmt,
7032 AMFBS_HasVendorXwchc,
7033 AMFBS_HasXAIFET,
7034 AMFBS_IsRV32,
7035 AMFBS_IsRV64,
7036 AMFBS_HasStdExtD_IsRV64,
7037 AMFBS_HasStdExtF_IsRV64,
7038 AMFBS_HasStdExtM_IsRV64,
7039 AMFBS_HasStdExtP_IsRV32,
7040 AMFBS_HasStdExtP_IsRV64,
7041 AMFBS_HasStdExtQ_IsRV64,
7042 AMFBS_HasStdExtY_IsRV32,
7043 AMFBS_HasStdExtY_IsRV64,
7044 AMFBS_HasStdExtZaamo_IsRV64,
7045 AMFBS_HasStdExtZabha_HasStdExtZacas,
7046 AMFBS_HasStdExtZacas_IsRV32,
7047 AMFBS_HasStdExtZacas_IsRV64,
7048 AMFBS_HasStdExtZalasr_IsRV64,
7049 AMFBS_HasStdExtZalrsc_IsRV64,
7050 AMFBS_HasStdExtZba_IsRV64,
7051 AMFBS_HasStdExtZbb_IsRV64,
7052 AMFBS_HasStdExtZbbOrZbkb_IsRV32,
7053 AMFBS_HasStdExtZbbOrZbkb_IsRV64,
7054 AMFBS_HasStdExtZbkb_IsRV32,
7055 AMFBS_HasStdExtZbkb_IsRV64,
7056 AMFBS_HasStdExtZca_IsRV32,
7057 AMFBS_HasStdExtZca_IsRV64,
7058 AMFBS_HasStdExtZcb_HasStdExtZbb,
7059 AMFBS_HasStdExtZcb_HasStdExtZmmul,
7060 AMFBS_HasStdExtZcf_IsRV32,
7061 AMFBS_HasStdExtZclsd_IsRV32,
7062 AMFBS_HasStdExtZdinx_IsRV32,
7063 AMFBS_HasStdExtZdinx_IsRV64,
7064 AMFBS_HasStdExtZfa_HasStdExtD,
7065 AMFBS_HasStdExtZfa_HasStdExtQ,
7066 AMFBS_HasStdExtZfa_HasStdExtZfh,
7067 AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh,
7068 AMFBS_HasStdExtZfh_IsRV64,
7069 AMFBS_HasStdExtZfhmin_HasStdExtD,
7070 AMFBS_HasStdExtZfinx_IsRV64,
7071 AMFBS_HasStdExtZhinx_IsRV64,
7072 AMFBS_HasStdExtZicfiss_IsRV64,
7073 AMFBS_HasStdExtZilsd_IsRV32,
7074 AMFBS_HasStdExtZknd_IsRV32,
7075 AMFBS_HasStdExtZknd_IsRV64,
7076 AMFBS_HasStdExtZkndOrZkne_IsRV64,
7077 AMFBS_HasStdExtZkne_IsRV32,
7078 AMFBS_HasStdExtZkne_IsRV64,
7079 AMFBS_HasStdExtZknh_IsRV32,
7080 AMFBS_HasStdExtZknh_IsRV64,
7081 AMFBS_HasStdExtZmmul_IsRV64,
7082 AMFBS_HasVInstructionsI64_IsRV64,
7083 AMFBS_HasVendorXAndesPerf_IsRV64,
7084 AMFBS_HasVendorXCValu_IsRV32,
7085 AMFBS_HasVendorXCVbi_IsRV32,
7086 AMFBS_HasVendorXCVbitmanip_IsRV32,
7087 AMFBS_HasVendorXCVelw_IsRV32,
7088 AMFBS_HasVendorXCVmac_IsRV32,
7089 AMFBS_HasVendorXCVmem_IsRV32,
7090 AMFBS_HasVendorXCVsimd_IsRV32,
7091 AMFBS_HasVendorXSMTVDot_IsRV64,
7092 AMFBS_HasVendorXSMTVDotII_IsRV64,
7093 AMFBS_HasVendorXTHeadBb_IsRV64,
7094 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD,
7095 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF,
7096 AMFBS_HasVendorXTHeadMac_IsRV64,
7097 AMFBS_HasVendorXTHeadMemIdx_IsRV64,
7098 AMFBS_HasVendorXTHeadMemPair_IsRV64,
7099 AMFBS_HasVendorXqcia_IsRV32,
7100 AMFBS_HasVendorXqciac_IsRV32,
7101 AMFBS_HasVendorXqcibi_IsRV32,
7102 AMFBS_HasVendorXqcibm_IsRV32,
7103 AMFBS_HasVendorXqcicli_IsRV32,
7104 AMFBS_HasVendorXqcicm_IsRV32,
7105 AMFBS_HasVendorXqcics_IsRV32,
7106 AMFBS_HasVendorXqcicsr_IsRV32,
7107 AMFBS_HasVendorXqciint_IsRV32,
7108 AMFBS_HasVendorXqciio_IsRV32,
7109 AMFBS_HasVendorXqcilb_IsRV32,
7110 AMFBS_HasVendorXqcili_IsRV32,
7111 AMFBS_HasVendorXqcilia_IsRV32,
7112 AMFBS_HasVendorXqcilo_IsRV32,
7113 AMFBS_HasVendorXqcilsm_IsRV32,
7114 AMFBS_HasVendorXqcisim_IsRV32,
7115 AMFBS_HasVendorXqcisls_IsRV32,
7116 AMFBS_HasVendorXqcisync_IsRV32,
7117 AMFBS_IsRV32_HasStdExtZca,
7118 AMFBS_IsRV32_HasStdExtZcb,
7119 AMFBS_IsRV64_HasStdExtH,
7120 AMFBS_IsRV64_HasVInstructionsI64,
7121 AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64,
7122 AMFBS_HasStdExtZdinx_IsRV64_IsRV64,
7123 AMFBS_HasStdExtZfa_HasStdExtD_IsRV32,
7124 AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64,
7125 AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32,
7126 AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64,
7127 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64,
7128 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64,
7129 AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32,
7130};
7131
7132static constexpr FeatureBitset FeatureBitsets[] = {
7133 {}, // AMFBS_None
7134 {Feature_HasHalfFPLoadStoreMoveBit, }, // AMFBS_HasHalfFPLoadStoreMove
7135 {Feature_HasStdExtDBit, }, // AMFBS_HasStdExtD
7136 {Feature_HasStdExtFBit, }, // AMFBS_HasStdExtF
7137 {Feature_HasStdExtFOrZfinxBit, }, // AMFBS_HasStdExtFOrZfinx
7138 {Feature_HasStdExtHBit, }, // AMFBS_HasStdExtH
7139 {Feature_HasStdExtMBit, }, // AMFBS_HasStdExtM
7140 {Feature_HasStdExtPBit, }, // AMFBS_HasStdExtP
7141 {Feature_HasStdExtQBit, }, // AMFBS_HasStdExtQ
7142 {Feature_HasStdExtSmctrOrSsctrBit, }, // AMFBS_HasStdExtSmctrOrSsctr
7143 {Feature_HasStdExtSmrnmiBit, }, // AMFBS_HasStdExtSmrnmi
7144 {Feature_HasStdExtSvinvalBit, }, // AMFBS_HasStdExtSvinval
7145 {Feature_HasStdExtYBit, }, // AMFBS_HasStdExtY
7146 {Feature_HasStdExtZaamoBit, }, // AMFBS_HasStdExtZaamo
7147 {Feature_HasStdExtZabhaBit, }, // AMFBS_HasStdExtZabha
7148 {Feature_HasStdExtZacasBit, }, // AMFBS_HasStdExtZacas
7149 {Feature_HasStdExtZalasrBit, }, // AMFBS_HasStdExtZalasr
7150 {Feature_HasStdExtZalrscBit, }, // AMFBS_HasStdExtZalrsc
7151 {Feature_HasStdExtZawrsBit, }, // AMFBS_HasStdExtZawrs
7152 {Feature_HasStdExtZbaBit, }, // AMFBS_HasStdExtZba
7153 {Feature_HasStdExtZbbBit, }, // AMFBS_HasStdExtZbb
7154 {Feature_HasStdExtZbbOrZbkbBit, }, // AMFBS_HasStdExtZbbOrZbkb
7155 {Feature_HasStdExtZbcBit, }, // AMFBS_HasStdExtZbc
7156 {Feature_HasStdExtZbkbBit, }, // AMFBS_HasStdExtZbkb
7157 {Feature_HasStdExtZbkbOrPBit, }, // AMFBS_HasStdExtZbkbOrP
7158 {Feature_HasStdExtZbkcBit, }, // AMFBS_HasStdExtZbkc
7159 {Feature_HasStdExtZbkxBit, }, // AMFBS_HasStdExtZbkx
7160 {Feature_HasStdExtZbsBit, }, // AMFBS_HasStdExtZbs
7161 {Feature_HasStdExtZcaBit, }, // AMFBS_HasStdExtZca
7162 {Feature_HasStdExtZcbBit, }, // AMFBS_HasStdExtZcb
7163 {Feature_HasStdExtZcdBit, }, // AMFBS_HasStdExtZcd
7164 {Feature_HasStdExtZcmopBit, }, // AMFBS_HasStdExtZcmop
7165 {Feature_HasStdExtZcmpBit, }, // AMFBS_HasStdExtZcmp
7166 {Feature_HasStdExtZcmtBit, }, // AMFBS_HasStdExtZcmt
7167 {Feature_HasStdExtZfaBit, }, // AMFBS_HasStdExtZfa
7168 {Feature_HasStdExtZfbfminBit, }, // AMFBS_HasStdExtZfbfmin
7169 {Feature_HasStdExtZfhBit, }, // AMFBS_HasStdExtZfh
7170 {Feature_HasStdExtZfhminBit, }, // AMFBS_HasStdExtZfhmin
7171 {Feature_HasStdExtZfinxBit, }, // AMFBS_HasStdExtZfinx
7172 {Feature_HasStdExtZhinxBit, }, // AMFBS_HasStdExtZhinx
7173 {Feature_HasStdExtZhinxminBit, }, // AMFBS_HasStdExtZhinxmin
7174 {Feature_HasStdExtZibiBit, }, // AMFBS_HasStdExtZibi
7175 {Feature_HasStdExtZicbomBit, }, // AMFBS_HasStdExtZicbom
7176 {Feature_HasStdExtZicbozBit, }, // AMFBS_HasStdExtZicboz
7177 {Feature_HasStdExtZicfissBit, }, // AMFBS_HasStdExtZicfiss
7178 {Feature_HasStdExtZicondBit, }, // AMFBS_HasStdExtZicond
7179 {Feature_HasStdExtZimopBit, }, // AMFBS_HasStdExtZimop
7180 {Feature_HasStdExtZknhBit, }, // AMFBS_HasStdExtZknh
7181 {Feature_HasStdExtZksedBit, }, // AMFBS_HasStdExtZksed
7182 {Feature_HasStdExtZkshBit, }, // AMFBS_HasStdExtZksh
7183 {Feature_HasStdExtZmmulBit, }, // AMFBS_HasStdExtZmmul
7184 {Feature_HasStdExtZvabdBit, }, // AMFBS_HasStdExtZvabd
7185 {Feature_HasStdExtZvbbBit, }, // AMFBS_HasStdExtZvbb
7186 {Feature_HasStdExtZvbcOrZvbc32eBit, }, // AMFBS_HasStdExtZvbcOrZvbc32e
7187 {Feature_HasStdExtZvdot4a8iBit, }, // AMFBS_HasStdExtZvdot4a8i
7188 {Feature_HasStdExtZvfbdota32fBit, }, // AMFBS_HasStdExtZvfbdota32f
7189 {Feature_HasStdExtZvfbfminOrZvfofp8minBit, }, // AMFBS_HasStdExtZvfbfminOrZvfofp8min
7190 {Feature_HasStdExtZvfbfwmaBit, }, // AMFBS_HasStdExtZvfbfwma
7191 {Feature_HasStdExtZvfofp8minBit, }, // AMFBS_HasStdExtZvfofp8min
7192 {Feature_HasStdExtZvfqwbdota8fBit, }, // AMFBS_HasStdExtZvfqwbdota8f
7193 {Feature_HasStdExtZvfqwdota8fBit, }, // AMFBS_HasStdExtZvfqwdota8f
7194 {Feature_HasStdExtZvfwbdota16bfBit, }, // AMFBS_HasStdExtZvfwbdota16bf
7195 {Feature_HasStdExtZvfwdota16bfBit, }, // AMFBS_HasStdExtZvfwdota16bf
7196 {Feature_HasStdExtZvkbBit, }, // AMFBS_HasStdExtZvkb
7197 {Feature_HasStdExtZvkgBit, }, // AMFBS_HasStdExtZvkg
7198 {Feature_HasStdExtZvkgsBit, }, // AMFBS_HasStdExtZvkgs
7199 {Feature_HasStdExtZvknedBit, }, // AMFBS_HasStdExtZvkned
7200 {Feature_HasStdExtZvknhaBit, }, // AMFBS_HasStdExtZvknha
7201 {Feature_HasStdExtZvksedBit, }, // AMFBS_HasStdExtZvksed
7202 {Feature_HasStdExtZvkshBit, }, // AMFBS_HasStdExtZvksh
7203 {Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit, }, // AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i
7204 {Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit, }, // AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i
7205 {Feature_HasStdExtZvvfmmBit, }, // AMFBS_HasStdExtZvvfmm
7206 {Feature_HasStdExtZvvmmBit, }, // AMFBS_HasStdExtZvvmm
7207 {Feature_HasStdExtZvvmtlsBit, }, // AMFBS_HasStdExtZvvmtls
7208 {Feature_HasStdExtZvvmttlsBit, }, // AMFBS_HasStdExtZvvmttls
7209 {Feature_HasStdExtZvzipBit, }, // AMFBS_HasStdExtZvzip
7210 {Feature_HasVInstructionsBit, }, // AMFBS_HasVInstructions
7211 {Feature_HasVInstructionsAnyFBit, }, // AMFBS_HasVInstructionsAnyF
7212 {Feature_HasVInstructionsI64Bit, }, // AMFBS_HasVInstructionsI64
7213 {Feature_HasVendorXAndesBFHCvtBit, }, // AMFBS_HasVendorXAndesBFHCvt
7214 {Feature_HasVendorXAndesPerfBit, }, // AMFBS_HasVendorXAndesPerf
7215 {Feature_HasVendorXAndesVBFHCvtBit, }, // AMFBS_HasVendorXAndesVBFHCvt
7216 {Feature_HasVendorXAndesVDotBit, }, // AMFBS_HasVendorXAndesVDot
7217 {Feature_HasVendorXAndesVPackFPHBit, }, // AMFBS_HasVendorXAndesVPackFPH
7218 {Feature_HasVendorXAndesVSIntHBit, }, // AMFBS_HasVendorXAndesVSIntH
7219 {Feature_HasVendorXAndesVSIntLoadBit, }, // AMFBS_HasVendorXAndesVSIntLoad
7220 {Feature_HasVendorXMIPSCBOPBit, }, // AMFBS_HasVendorXMIPSCBOP
7221 {Feature_HasVendorXMIPSCMovBit, }, // AMFBS_HasVendorXMIPSCMov
7222 {Feature_HasVendorXMIPSEXECTLBit, }, // AMFBS_HasVendorXMIPSEXECTL
7223 {Feature_HasVendorXMIPSLSPBit, }, // AMFBS_HasVendorXMIPSLSP
7224 {Feature_HasVendorXSfceaseBit, }, // AMFBS_HasVendorXSfcease
7225 {Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit, }, // AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f
7226 {Feature_HasVendorXSfmm32a8fBit, }, // AMFBS_HasVendorXSfmm32a8f
7227 {Feature_HasVendorXSfmm32a8iBit, }, // AMFBS_HasVendorXSfmm32a8i
7228 {Feature_HasVendorXSfmmbaseBit, }, // AMFBS_HasVendorXSfmmbase
7229 {Feature_HasVendorXSfvcpBit, }, // AMFBS_HasVendorXSfvcp
7230 {Feature_HasVendorXSfvfexpAnyBit, }, // AMFBS_HasVendorXSfvfexpAny
7231 {Feature_HasVendorXSfvfexpaBit, }, // AMFBS_HasVendorXSfvfexpa
7232 {Feature_HasVendorXSfvfnrclipxfqfBit, }, // AMFBS_HasVendorXSfvfnrclipxfqf
7233 {Feature_HasVendorXSfvfwmaccqqqBit, }, // AMFBS_HasVendorXSfvfwmaccqqq
7234 {Feature_HasVendorXSfvqmaccdodBit, }, // AMFBS_HasVendorXSfvqmaccdod
7235 {Feature_HasVendorXSfvqmaccqoqBit, }, // AMFBS_HasVendorXSfvqmaccqoq
7236 {Feature_HasVendorXSiFivecdiscarddloneBit, }, // AMFBS_HasVendorXSiFivecdiscarddlone
7237 {Feature_HasVendorXSiFivecflushdloneBit, }, // AMFBS_HasVendorXSiFivecflushdlone
7238 {Feature_HasVendorXTHeadBaBit, }, // AMFBS_HasVendorXTHeadBa
7239 {Feature_HasVendorXTHeadBbBit, }, // AMFBS_HasVendorXTHeadBb
7240 {Feature_HasVendorXTHeadBsBit, }, // AMFBS_HasVendorXTHeadBs
7241 {Feature_HasVendorXTHeadCmoBit, }, // AMFBS_HasVendorXTHeadCmo
7242 {Feature_HasVendorXTHeadCondMovBit, }, // AMFBS_HasVendorXTHeadCondMov
7243 {Feature_HasVendorXTHeadMacBit, }, // AMFBS_HasVendorXTHeadMac
7244 {Feature_HasVendorXTHeadMemIdxBit, }, // AMFBS_HasVendorXTHeadMemIdx
7245 {Feature_HasVendorXTHeadMemPairBit, }, // AMFBS_HasVendorXTHeadMemPair
7246 {Feature_HasVendorXTHeadSyncBit, }, // AMFBS_HasVendorXTHeadSync
7247 {Feature_HasVendorXTHeadVdotBit, }, // AMFBS_HasVendorXTHeadVdot
7248 {Feature_HasVendorXVentanaCondOpsBit, }, // AMFBS_HasVendorXVentanaCondOps
7249 {Feature_HasVendorXqccmpBit, }, // AMFBS_HasVendorXqccmp
7250 {Feature_HasVendorXqccmtBit, }, // AMFBS_HasVendorXqccmt
7251 {Feature_HasVendorXwchcBit, }, // AMFBS_HasVendorXwchc
7252 {Feature_HasXAIFETBit, }, // AMFBS_HasXAIFET
7253 {Feature_IsRV32Bit, }, // AMFBS_IsRV32
7254 {Feature_IsRV64Bit, }, // AMFBS_IsRV64
7255 {Feature_HasStdExtDBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtD_IsRV64
7256 {Feature_HasStdExtFBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtF_IsRV64
7257 {Feature_HasStdExtMBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtM_IsRV64
7258 {Feature_HasStdExtPBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtP_IsRV32
7259 {Feature_HasStdExtPBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtP_IsRV64
7260 {Feature_HasStdExtQBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtQ_IsRV64
7261 {Feature_HasStdExtYBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtY_IsRV32
7262 {Feature_HasStdExtYBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtY_IsRV64
7263 {Feature_HasStdExtZaamoBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZaamo_IsRV64
7264 {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, }, // AMFBS_HasStdExtZabha_HasStdExtZacas
7265 {Feature_HasStdExtZacasBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZacas_IsRV32
7266 {Feature_HasStdExtZacasBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZacas_IsRV64
7267 {Feature_HasStdExtZalasrBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZalasr_IsRV64
7268 {Feature_HasStdExtZalrscBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZalrsc_IsRV64
7269 {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZba_IsRV64
7270 {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZbb_IsRV64
7271 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZbbOrZbkb_IsRV32
7272 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZbbOrZbkb_IsRV64
7273 {Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZbkb_IsRV32
7274 {Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZbkb_IsRV64
7275 {Feature_HasStdExtZcaBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZca_IsRV32
7276 {Feature_HasStdExtZcaBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZca_IsRV64
7277 {Feature_HasStdExtZcbBit, Feature_HasStdExtZbbBit, }, // AMFBS_HasStdExtZcb_HasStdExtZbb
7278 {Feature_HasStdExtZcbBit, Feature_HasStdExtZmmulBit, }, // AMFBS_HasStdExtZcb_HasStdExtZmmul
7279 {Feature_HasStdExtZcfBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZcf_IsRV32
7280 {Feature_HasStdExtZclsdBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZclsd_IsRV32
7281 {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZdinx_IsRV32
7282 {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZdinx_IsRV64
7283 {Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, }, // AMFBS_HasStdExtZfa_HasStdExtD
7284 {Feature_HasStdExtZfaBit, Feature_HasStdExtQBit, }, // AMFBS_HasStdExtZfa_HasStdExtQ
7285 {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, }, // AMFBS_HasStdExtZfa_HasStdExtZfh
7286 {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhOrZvfhBit, }, // AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh
7287 {Feature_HasStdExtZfhBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZfh_IsRV64
7288 {Feature_HasStdExtZfhminBit, Feature_HasStdExtDBit, }, // AMFBS_HasStdExtZfhmin_HasStdExtD
7289 {Feature_HasStdExtZfinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZfinx_IsRV64
7290 {Feature_HasStdExtZhinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZhinx_IsRV64
7291 {Feature_HasStdExtZicfissBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZicfiss_IsRV64
7292 {Feature_HasStdExtZilsdBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZilsd_IsRV32
7293 {Feature_HasStdExtZkndBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZknd_IsRV32
7294 {Feature_HasStdExtZkndBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZknd_IsRV64
7295 {Feature_HasStdExtZkndOrZkneBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZkndOrZkne_IsRV64
7296 {Feature_HasStdExtZkneBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZkne_IsRV32
7297 {Feature_HasStdExtZkneBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZkne_IsRV64
7298 {Feature_HasStdExtZknhBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZknh_IsRV32
7299 {Feature_HasStdExtZknhBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZknh_IsRV64
7300 {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZmmul_IsRV64
7301 {Feature_HasVInstructionsI64Bit, Feature_IsRV64Bit, }, // AMFBS_HasVInstructionsI64_IsRV64
7302 {Feature_HasVendorXAndesPerfBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXAndesPerf_IsRV64
7303 {Feature_HasVendorXCValuBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCValu_IsRV32
7304 {Feature_HasVendorXCVbiBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVbi_IsRV32
7305 {Feature_HasVendorXCVbitmanipBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVbitmanip_IsRV32
7306 {Feature_HasVendorXCVelwBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVelw_IsRV32
7307 {Feature_HasVendorXCVmacBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVmac_IsRV32
7308 {Feature_HasVendorXCVmemBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVmem_IsRV32
7309 {Feature_HasVendorXCVsimdBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVsimd_IsRV32
7310 {Feature_HasVendorXSMTVDotBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXSMTVDot_IsRV64
7311 {Feature_HasVendorXSMTVDotIIBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXSMTVDotII_IsRV64
7312 {Feature_HasVendorXTHeadBbBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadBb_IsRV64
7313 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD
7314 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF
7315 {Feature_HasVendorXTHeadMacBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadMac_IsRV64
7316 {Feature_HasVendorXTHeadMemIdxBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadMemIdx_IsRV64
7317 {Feature_HasVendorXTHeadMemPairBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadMemPair_IsRV64
7318 {Feature_HasVendorXqciaBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcia_IsRV32
7319 {Feature_HasVendorXqciacBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqciac_IsRV32
7320 {Feature_HasVendorXqcibiBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcibi_IsRV32
7321 {Feature_HasVendorXqcibmBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcibm_IsRV32
7322 {Feature_HasVendorXqcicliBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcicli_IsRV32
7323 {Feature_HasVendorXqcicmBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcicm_IsRV32
7324 {Feature_HasVendorXqcicsBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcics_IsRV32
7325 {Feature_HasVendorXqcicsrBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcicsr_IsRV32
7326 {Feature_HasVendorXqciintBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqciint_IsRV32
7327 {Feature_HasVendorXqciioBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqciio_IsRV32
7328 {Feature_HasVendorXqcilbBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilb_IsRV32
7329 {Feature_HasVendorXqciliBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcili_IsRV32
7330 {Feature_HasVendorXqciliaBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilia_IsRV32
7331 {Feature_HasVendorXqciloBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilo_IsRV32
7332 {Feature_HasVendorXqcilsmBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilsm_IsRV32
7333 {Feature_HasVendorXqcisimBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcisim_IsRV32
7334 {Feature_HasVendorXqcislsBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcisls_IsRV32
7335 {Feature_HasVendorXqcisyncBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcisync_IsRV32
7336 {Feature_IsRV32Bit, Feature_HasStdExtZcaBit, }, // AMFBS_IsRV32_HasStdExtZca
7337 {Feature_IsRV32Bit, Feature_HasStdExtZcbBit, }, // AMFBS_IsRV32_HasStdExtZcb
7338 {Feature_IsRV64Bit, Feature_HasStdExtHBit, }, // AMFBS_IsRV64_HasStdExtH
7339 {Feature_IsRV64Bit, Feature_HasVInstructionsI64Bit, }, // AMFBS_IsRV64_HasVInstructionsI64
7340 {Feature_HasStdExtZcbBit, Feature_HasStdExtZbaBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64
7341 {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZdinx_IsRV64_IsRV64
7342 {Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZfa_HasStdExtD_IsRV32
7343 {Feature_HasStdExtZfaBit, Feature_HasStdExtQBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64
7344 {Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32
7345 {Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64
7346 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64
7347 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64
7348 {Feature_HasVendorXqciloBit, Feature_HasVendorXqciliBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32
7349};
7350
7351namespace {
7352 struct MatchEntry {
7353 uint16_t Mnemonic;
7354 uint32_t Opcode;
7355 uint16_t ConvertFn;
7356 uint8_t RequiredFeaturesIdx;
7357 uint16_t Classes[8];
7358 StringRef getMnemonic() const {
7359 return StringRef(MnemonicTable + Mnemonic + 1,
7360 MnemonicTable[Mnemonic]);
7361 }
7362 };
7363
7364 // Predicate for searching for an opcode.
7365 struct LessOpcode {
7366 bool operator()(const MatchEntry &LHS, StringRef RHS) {
7367 return LHS.getMnemonic() < RHS;
7368 }
7369 bool operator()(StringRef LHS, const MatchEntry &RHS) {
7370 return LHS < RHS.getMnemonic();
7371 }
7372 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
7373 return LHS.getMnemonic() < RHS.getMnemonic();
7374 }
7375 };
7376} // end anonymous namespace
7377
7378static const MatchEntry MatchTable0[] = {
7379 { 0 /* .insn_b */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_BareSImm13Lsb0 }, },
7380 { 8 /* .insn_ca */, RISCV::InsnCA, Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm6, MCK_UImm2, MCK_AnyRegCOperand, MCK_AnyRegCOperand }, },
7381 { 17 /* .insn_cb */, RISCV::InsnCB, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_BareSImm9Lsb0 }, },
7382 { 26 /* .insn_ci */, RISCV::InsnCI, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm6 }, },
7383 { 35 /* .insn_ciw */, RISCV::InsnCIW, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm8 }, },
7384 { 45 /* .insn_cj */, RISCV::InsnCJ, Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_BareSImm12Lsb0 }, },
7385 { 54 /* .insn_cl */, RISCV::InsnCL, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7386 { 54 /* .insn_cl */, RISCV::InsnCL, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7387 { 63 /* .insn_cr */, RISCV::InsnCR, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm4, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7388 { 72 /* .insn_cs */, RISCV::InsnCS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7389 { 72 /* .insn_cs */, RISCV::InsnCS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7390 { 81 /* .insn_css */, RISCV::InsnCSS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_UImm6 }, },
7391 { 91 /* .insn_i */, RISCV::InsnI, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm12LO }, },
7392 { 91 /* .insn_i */, RISCV::InsnI_Mem, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7393 { 91 /* .insn_i */, RISCV::InsnI_Mem, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm12LO1_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm12LO, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7394 { 99 /* .insn_j */, RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_BareSImm21Lsb0 }, },
7395 { 107 /* .insn_qc.eai */, RISCV::InsnQC_EAI, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm1, MCK_AnyRegOperand, MCK_BareSImm32 }, },
7396 { 120 /* .insn_qc.eb */, RISCV::InsnQC_EB, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm5, MCK_AnyRegOperand, MCK_SImm16, MCK_BareSImm13Lsb0 }, },
7397 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm26 }, },
7398 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI_Mem, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_5__imm_95_0, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7399 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI_Mem, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__SImm261_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_SImm26, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7400 { 144 /* .insn_qc.ej */, RISCV::InsnQC_EJ, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_UImm5, MCK_BareSImm32Lsb0 }, },
7401 { 156 /* .insn_qc.es */, RISCV::InsnQC_ES, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_5__imm_95_0, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7402 { 156 /* .insn_qc.es */, RISCV::InsnQC_ES, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__SImm261_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_SImm26, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7403 { 168 /* .insn_r */, RISCV::InsnR, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm7, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7404 { 168 /* .insn_r */, RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7405 { 176 /* .insn_r4 */, RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7406 { 185 /* .insn_s */, RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7407 { 185 /* .insn_s */, RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm12LO1_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm12LO, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7408 { 193 /* .insn_sb */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_BareSImm13Lsb0 }, },
7409 { 202 /* .insn_u */, RISCV::InsnU, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_UImm20LUI }, },
7410 { 210 /* .insn_uj */, RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_BareSImm21Lsb0 }, },
7411 { 219 /* aadd */, RISCV::AADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7412 { 224 /* aaddu */, RISCV::AADDU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7413 { 230 /* abs */, RISCV::ABS, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
7414 { 234 /* absw */, RISCV::ABSW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
7415 { 239 /* add */, RISCV::ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7416 { 239 /* add */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7417 { 239 /* add */, RISCV::PseudoAddTPRel, Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_TPRelAddSymbol }, },
7418 { 243 /* add.uw */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7419 { 250 /* addd */, RISCV::ADDD, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
7420 { 255 /* addi */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7421 { 260 /* addiw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7422 { 266 /* addw */, RISCV::ADDW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7423 { 266 /* addw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7424 { 271 /* aes32dsi */, RISCV::AES32DSI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7425 { 280 /* aes32dsmi */, RISCV::AES32DSMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7426 { 290 /* aes32esi */, RISCV::AES32ESI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7427 { 299 /* aes32esmi */, RISCV::AES32ESMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7428 { 309 /* aes64ds */, RISCV::AES64DS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7429 { 317 /* aes64dsm */, RISCV::AES64DSM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7430 { 326 /* aes64es */, RISCV::AES64ES, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7431 { 334 /* aes64esm */, RISCV::AES64ESM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7432 { 343 /* aes64im */, RISCV::AES64IM, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR }, },
7433 { 351 /* aes64ks1i */, RISCV::AES64KS1I, Convert__Reg1_0__Reg1_1__RnumArg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_RnumArg }, },
7434 { 361 /* aes64ks2 */, RISCV::AES64KS2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7435 { 370 /* aif.amoaddg.d */, RISCV::AIF_AMOADDG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7436 { 384 /* aif.amoaddg.w */, RISCV::AIF_AMOADDG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7437 { 398 /* aif.amoaddl.d */, RISCV::AIF_AMOADDL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7438 { 412 /* aif.amoaddl.w */, RISCV::AIF_AMOADDL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7439 { 426 /* aif.amoandg.d */, RISCV::AIF_AMOANDG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7440 { 440 /* aif.amoandg.w */, RISCV::AIF_AMOANDG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7441 { 454 /* aif.amoandl.d */, RISCV::AIF_AMOANDL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7442 { 468 /* aif.amoandl.w */, RISCV::AIF_AMOANDL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7443 { 482 /* aif.amocmpswapg.d */, RISCV::AIF_AMOCMPSWAPG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7444 { 500 /* aif.amocmpswapg.w */, RISCV::AIF_AMOCMPSWAPG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7445 { 518 /* aif.amocmpswapl.d */, RISCV::AIF_AMOCMPSWAPL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7446 { 536 /* aif.amocmpswapl.w */, RISCV::AIF_AMOCMPSWAPL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7447 { 554 /* aif.amomaxg.d */, RISCV::AIF_AMOMAXG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7448 { 568 /* aif.amomaxg.w */, RISCV::AIF_AMOMAXG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7449 { 582 /* aif.amomaxl.d */, RISCV::AIF_AMOMAXL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7450 { 596 /* aif.amomaxl.w */, RISCV::AIF_AMOMAXL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7451 { 610 /* aif.amomaxug.d */, RISCV::AIF_AMOMAXUG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7452 { 625 /* aif.amomaxug.w */, RISCV::AIF_AMOMAXUG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7453 { 640 /* aif.amomaxul.d */, RISCV::AIF_AMOMAXUL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7454 { 655 /* aif.amomaxul.w */, RISCV::AIF_AMOMAXUL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7455 { 670 /* aif.amoming.d */, RISCV::AIF_AMOMING_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7456 { 684 /* aif.amoming.w */, RISCV::AIF_AMOMING_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7457 { 698 /* aif.amominl.d */, RISCV::AIF_AMOMINL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7458 { 712 /* aif.amominl.w */, RISCV::AIF_AMOMINL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7459 { 726 /* aif.amominug.d */, RISCV::AIF_AMOMINUG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7460 { 741 /* aif.amominug.w */, RISCV::AIF_AMOMINUG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7461 { 756 /* aif.amominul.d */, RISCV::AIF_AMOMINUL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7462 { 771 /* aif.amominul.w */, RISCV::AIF_AMOMINUL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7463 { 786 /* aif.amoorg.d */, RISCV::AIF_AMOORG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7464 { 799 /* aif.amoorg.w */, RISCV::AIF_AMOORG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7465 { 812 /* aif.amoorl.d */, RISCV::AIF_AMOORL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7466 { 825 /* aif.amoorl.w */, RISCV::AIF_AMOORL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7467 { 838 /* aif.amoswapg.d */, RISCV::AIF_AMOSWAPG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7468 { 853 /* aif.amoswapg.w */, RISCV::AIF_AMOSWAPG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7469 { 868 /* aif.amoswapl.d */, RISCV::AIF_AMOSWAPL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7470 { 883 /* aif.amoswapl.w */, RISCV::AIF_AMOSWAPL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7471 { 898 /* aif.amoxorg.d */, RISCV::AIF_AMOXORG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7472 { 912 /* aif.amoxorg.w */, RISCV::AIF_AMOXORG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7473 { 926 /* aif.amoxorl.d */, RISCV::AIF_AMOXORL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7474 { 940 /* aif.amoxorl.w */, RISCV::AIF_AMOXORL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7475 { 954 /* aif.bitmixb */, RISCV::AIF_BITMIXB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7476 { 966 /* aif.cubeface.ps */, RISCV::AIF_CUBEFACE_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7477 { 982 /* aif.cubefaceidx.ps */, RISCV::AIF_CUBEFACEIDX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7478 { 1001 /* aif.cubesgnsc.ps */, RISCV::AIF_CUBESGNSC_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7479 { 1018 /* aif.cubesgntc.ps */, RISCV::AIF_CUBESGNTC_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7480 { 1035 /* aif.fadd.pi */, RISCV::AIF_FADD_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7481 { 1047 /* aif.fadd.ps */, RISCV::AIF_FADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7482 { 1059 /* aif.faddi.pi */, RISCV::AIF_FADDI_PI, Convert__Reg1_0__Reg1_1__SImm101_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_SImm10 }, },
7483 { 1072 /* aif.famoaddg.pi */, RISCV::AIF_FAMOADDG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7484 { 1088 /* aif.famoaddl.pi */, RISCV::AIF_FAMOADDL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7485 { 1104 /* aif.famoandg.pi */, RISCV::AIF_FAMOANDG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7486 { 1120 /* aif.famoandl.pi */, RISCV::AIF_FAMOANDL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7487 { 1136 /* aif.famomaxg.pi */, RISCV::AIF_FAMOMAXG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7488 { 1152 /* aif.famomaxg.ps */, RISCV::AIF_FAMOMAXG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7489 { 1168 /* aif.famomaxl.pi */, RISCV::AIF_FAMOMAXL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7490 { 1184 /* aif.famomaxl.ps */, RISCV::AIF_FAMOMAXL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7491 { 1200 /* aif.famomaxug.pi */, RISCV::AIF_FAMOMAXUG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7492 { 1217 /* aif.famomaxul.pi */, RISCV::AIF_FAMOMAXUL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7493 { 1234 /* aif.famoming.pi */, RISCV::AIF_FAMOMING_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7494 { 1250 /* aif.famoming.ps */, RISCV::AIF_FAMOMING_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7495 { 1266 /* aif.famominl.pi */, RISCV::AIF_FAMOMINL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7496 { 1282 /* aif.famominl.ps */, RISCV::AIF_FAMOMINL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7497 { 1298 /* aif.famominug.pi */, RISCV::AIF_FAMOMINUG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7498 { 1315 /* aif.famominul.pi */, RISCV::AIF_FAMOMINUL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7499 { 1332 /* aif.famoorg.pi */, RISCV::AIF_FAMOORG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7500 { 1347 /* aif.famoorl.pi */, RISCV::AIF_FAMOORL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7501 { 1362 /* aif.famoswapg.pi */, RISCV::AIF_FAMOSWAPG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7502 { 1379 /* aif.famoswapl.pi */, RISCV::AIF_FAMOSWAPL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7503 { 1396 /* aif.famoxorg.pi */, RISCV::AIF_FAMOXORG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7504 { 1412 /* aif.famoxorl.pi */, RISCV::AIF_FAMOXORL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7505 { 1428 /* aif.fand.pi */, RISCV::AIF_FAND_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7506 { 1440 /* aif.fandi.pi */, RISCV::AIF_FANDI_PI, Convert__Reg1_0__Reg1_1__SImm101_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_SImm10 }, },
7507 { 1453 /* aif.fbc.ps */, RISCV::AIF_FBC_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7508 { 1464 /* aif.fbci.pi */, RISCV::AIF_FBCI_PI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_UImm20LUI }, },
7509 { 1476 /* aif.fbci.ps */, RISCV::AIF_FBCI_PS, Convert__Reg1_0__UImm20LUI1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_UImm20LUI }, },
7510 { 1488 /* aif.fbcx.ps */, RISCV::AIF_FBCX_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR }, },
7511 { 1500 /* aif.fclass.ps */, RISCV::AIF_FCLASS_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7512 { 1514 /* aif.fcmov.ps */, RISCV::AIF_FCMOV_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7513 { 1527 /* aif.fcmovm.ps */, RISCV::AIF_FCMOVM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7514 { 1541 /* aif.fcvt.f10.ps */, RISCV::AIF_FCVT_F10_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7515 { 1557 /* aif.fcvt.f11.ps */, RISCV::AIF_FCVT_F11_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7516 { 1573 /* aif.fcvt.f16.ps */, RISCV::AIF_FCVT_F16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7517 { 1589 /* aif.fcvt.ps.f10 */, RISCV::AIF_FCVT_PS_F10, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7518 { 1605 /* aif.fcvt.ps.f11 */, RISCV::AIF_FCVT_PS_F11, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7519 { 1621 /* aif.fcvt.ps.f16 */, RISCV::AIF_FCVT_PS_F16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7520 { 1637 /* aif.fcvt.ps.pw */, RISCV::AIF_FCVT_PS_PW, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7521 { 1652 /* aif.fcvt.ps.pwu */, RISCV::AIF_FCVT_PS_PWU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7522 { 1668 /* aif.fcvt.ps.rast */, RISCV::AIF_FCVT_PS_RAST, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7523 { 1685 /* aif.fcvt.ps.sn16 */, RISCV::AIF_FCVT_PS_SN16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7524 { 1702 /* aif.fcvt.ps.sn8 */, RISCV::AIF_FCVT_PS_SN8, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7525 { 1718 /* aif.fcvt.ps.un10 */, RISCV::AIF_FCVT_PS_UN10, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7526 { 1735 /* aif.fcvt.ps.un16 */, RISCV::AIF_FCVT_PS_UN16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7527 { 1752 /* aif.fcvt.ps.un2 */, RISCV::AIF_FCVT_PS_UN2, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7528 { 1768 /* aif.fcvt.ps.un24 */, RISCV::AIF_FCVT_PS_UN24, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7529 { 1785 /* aif.fcvt.ps.un8 */, RISCV::AIF_FCVT_PS_UN8, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7530 { 1801 /* aif.fcvt.pw.ps */, RISCV::AIF_FCVT_PW_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7531 { 1816 /* aif.fcvt.pwu.ps */, RISCV::AIF_FCVT_PWU_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7532 { 1832 /* aif.fcvt.rast.ps */, RISCV::AIF_FCVT_RAST_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7533 { 1849 /* aif.fcvt.sn16.ps */, RISCV::AIF_FCVT_SN16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7534 { 1866 /* aif.fcvt.sn8.ps */, RISCV::AIF_FCVT_SN8_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7535 { 1882 /* aif.fcvt.un10.ps */, RISCV::AIF_FCVT_UN10_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7536 { 1899 /* aif.fcvt.un16.ps */, RISCV::AIF_FCVT_UN16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7537 { 1916 /* aif.fcvt.un2.ps */, RISCV::AIF_FCVT_UN2_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7538 { 1932 /* aif.fcvt.un24.ps */, RISCV::AIF_FCVT_UN24_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7539 { 1949 /* aif.fcvt.un8.ps */, RISCV::AIF_FCVT_UN8_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7540 { 1965 /* aif.fdiv.pi */, RISCV::AIF_FDIV_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7541 { 1977 /* aif.fdiv.ps */, RISCV::AIF_FDIV_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7542 { 1989 /* aif.fdivu.pi */, RISCV::AIF_FDIVU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7543 { 2002 /* aif.feq.pi */, RISCV::AIF_FEQ_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7544 { 2013 /* aif.feq.ps */, RISCV::AIF_FEQ_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7545 { 2024 /* aif.feqm.ps */, RISCV::AIF_FEQM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7546 { 2036 /* aif.fexp.ps */, RISCV::AIF_FEXP_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7547 { 2048 /* aif.ffrc.ps */, RISCV::AIF_FFRC_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7548 { 2060 /* aif.fg32b.ps */, RISCV::AIF_FG32B_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7549 { 2073 /* aif.fg32h.ps */, RISCV::AIF_FG32H_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7550 { 2086 /* aif.fg32w.ps */, RISCV::AIF_FG32W_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7551 { 2099 /* aif.fgb.ps */, RISCV::AIF_FGB_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7552 { 2110 /* aif.fgbg.ps */, RISCV::AIF_FGBG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7553 { 2122 /* aif.fgbl.ps */, RISCV::AIF_FGBL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7554 { 2134 /* aif.fgh.ps */, RISCV::AIF_FGH_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7555 { 2145 /* aif.fghg.ps */, RISCV::AIF_FGHG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7556 { 2157 /* aif.fghl.ps */, RISCV::AIF_FGHL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7557 { 2169 /* aif.fgw.ps */, RISCV::AIF_FGW_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7558 { 2180 /* aif.fgwg.ps */, RISCV::AIF_FGWG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7559 { 2192 /* aif.fgwl.ps */, RISCV::AIF_FGWL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7560 { 2204 /* aif.fle.pi */, RISCV::AIF_FLE_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7561 { 2215 /* aif.fle.ps */, RISCV::AIF_FLE_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7562 { 2226 /* aif.flem.ps */, RISCV::AIF_FLEM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7563 { 2238 /* aif.flog.ps */, RISCV::AIF_FLOG_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7564 { 2250 /* aif.flq2 */, RISCV::AIF_FLQ2, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7565 { 2259 /* aif.flt.pi */, RISCV::AIF_FLT_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7566 { 2270 /* aif.flt.ps */, RISCV::AIF_FLT_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7567 { 2281 /* aif.fltm.pi */, RISCV::AIF_FLTM_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7568 { 2293 /* aif.fltm.ps */, RISCV::AIF_FLTM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7569 { 2305 /* aif.fltu.pi */, RISCV::AIF_FLTU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7570 { 2317 /* aif.flw.ps */, RISCV::AIF_FLW_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7571 { 2328 /* aif.flwg.ps */, RISCV::AIF_FLWG_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7572 { 2340 /* aif.flwl.ps */, RISCV::AIF_FLWL_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7573 { 2352 /* aif.fmadd.ps */, RISCV::AIF_FMADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7574 { 2365 /* aif.fmax.pi */, RISCV::AIF_FMAX_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7575 { 2377 /* aif.fmax.ps */, RISCV::AIF_FMAX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7576 { 2389 /* aif.fmaxu.pi */, RISCV::AIF_FMAXU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7577 { 2402 /* aif.fmin.pi */, RISCV::AIF_FMIN_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7578 { 2414 /* aif.fmin.ps */, RISCV::AIF_FMIN_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7579 { 2426 /* aif.fminu.pi */, RISCV::AIF_FMINU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7580 { 2439 /* aif.fmsub.ps */, RISCV::AIF_FMSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7581 { 2452 /* aif.fmul.pi */, RISCV::AIF_FMUL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7582 { 2464 /* aif.fmul.ps */, RISCV::AIF_FMUL_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7583 { 2476 /* aif.fmulh.pi */, RISCV::AIF_FMULH_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7584 { 2489 /* aif.fmulhu.pi */, RISCV::AIF_FMULHU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7585 { 2503 /* aif.fmvs.x.ps */, RISCV::AIF_FMVS_X_PS, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_FPR256, MCK_UImm3 }, },
7586 { 2517 /* aif.fmvz.x.ps */, RISCV::AIF_FMVZ_X_PS, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_FPR256, MCK_UImm3 }, },
7587 { 2531 /* aif.fnmadd.ps */, RISCV::AIF_FNMADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7588 { 2545 /* aif.fnmsub.ps */, RISCV::AIF_FNMSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7589 { 2559 /* aif.fnot.pi */, RISCV::AIF_FNOT_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7590 { 2571 /* aif.for.pi */, RISCV::AIF_FOR_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7591 { 2582 /* aif.fpackrepb.pi */, RISCV::AIF_FPACKREPB_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7592 { 2599 /* aif.fpackreph.pi */, RISCV::AIF_FPACKREPH_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7593 { 2616 /* aif.frcp.ps */, RISCV::AIF_FRCP_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7594 { 2628 /* aif.frcp_fix.rast */, RISCV::AIF_FRCP_FIX_RAST, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7595 { 2646 /* aif.frem.pi */, RISCV::AIF_FREM_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7596 { 2658 /* aif.fremu.pi */, RISCV::AIF_FREMU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7597 { 2671 /* aif.fround.ps */, RISCV::AIF_FROUND_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7598 { 2685 /* aif.frsq.ps */, RISCV::AIF_FRSQ_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7599 { 2697 /* aif.fsat8.pi */, RISCV::AIF_FSAT8_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7600 { 2710 /* aif.fsatu8.pi */, RISCV::AIF_FSATU8_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7601 { 2724 /* aif.fsc32b.ps */, RISCV::AIF_FSC32B_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7602 { 2738 /* aif.fsc32h.ps */, RISCV::AIF_FSC32H_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7603 { 2752 /* aif.fsc32w.ps */, RISCV::AIF_FSC32W_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7604 { 2766 /* aif.fscb.ps */, RISCV::AIF_FSCB_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7605 { 2778 /* aif.fscbg.ps */, RISCV::AIF_FSCBG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7606 { 2791 /* aif.fscbl.ps */, RISCV::AIF_FSCBL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7607 { 2804 /* aif.fsch.ps */, RISCV::AIF_FSCH_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7608 { 2816 /* aif.fschg.ps */, RISCV::AIF_FSCHG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7609 { 2829 /* aif.fschl.ps */, RISCV::AIF_FSCHL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7610 { 2842 /* aif.fscw.ps */, RISCV::AIF_FSCW_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7611 { 2854 /* aif.fscwg.ps */, RISCV::AIF_FSCWG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7612 { 2867 /* aif.fscwl.ps */, RISCV::AIF_FSCWL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7613 { 2880 /* aif.fsetm.pi */, RISCV::AIF_FSETM_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256 }, },
7614 { 2893 /* aif.fsgnj.ps */, RISCV::AIF_FSGNJ_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7615 { 2906 /* aif.fsgnjn.ps */, RISCV::AIF_FSGNJN_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7616 { 2920 /* aif.fsgnjx.ps */, RISCV::AIF_FSGNJX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7617 { 2934 /* aif.fsin.ps */, RISCV::AIF_FSIN_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7618 { 2946 /* aif.fsll.pi */, RISCV::AIF_FSLL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7619 { 2958 /* aif.fslli.pi */, RISCV::AIF_FSLLI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
7620 { 2971 /* aif.fsq2 */, RISCV::AIF_FSQ2, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7621 { 2980 /* aif.fsqrt.ps */, RISCV::AIF_FSQRT_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7622 { 2993 /* aif.fsra.pi */, RISCV::AIF_FSRA_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7623 { 3005 /* aif.fsrai.pi */, RISCV::AIF_FSRAI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
7624 { 3018 /* aif.fsrl.pi */, RISCV::AIF_FSRL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7625 { 3030 /* aif.fsrli.pi */, RISCV::AIF_FSRLI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
7626 { 3043 /* aif.fsub.pi */, RISCV::AIF_FSUB_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7627 { 3055 /* aif.fsub.ps */, RISCV::AIF_FSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7628 { 3067 /* aif.fsw.ps */, RISCV::AIF_FSW_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7629 { 3078 /* aif.fswg.ps */, RISCV::AIF_FSWG_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7630 { 3090 /* aif.fswizz.ps */, RISCV::AIF_FSWIZZ_PS, Convert__Reg1_0__Reg1_1__UImm81_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm8 }, },
7631 { 3104 /* aif.fswl.ps */, RISCV::AIF_FSWL_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7632 { 3116 /* aif.fxor.pi */, RISCV::AIF_FXOR_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7633 { 3128 /* aif.maskand */, RISCV::AIF_MASKAND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
7634 { 3140 /* aif.masknot */, RISCV::AIF_MASKNOT, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_MR, MCK_MR }, },
7635 { 3152 /* aif.maskor */, RISCV::AIF_MASKOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
7636 { 3163 /* aif.maskpopc */, RISCV::AIF_MASKPOPC, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_MR }, },
7637 { 3176 /* aif.maskpopc.rast */, RISCV::AIF_MASKPOPC_ET_RAST, Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR, MCK_UImm4 }, },
7638 { 3194 /* aif.maskpopcz */, RISCV::AIF_MASKPOPCZ, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_MR }, },
7639 { 3208 /* aif.maskxor */, RISCV::AIF_MASKXOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
7640 { 3220 /* aif.mov.m.x */, RISCV::AIF_MOV_M_X, Convert__Reg1_0__Reg1_1__UImm81_2, AMFBS_HasXAIFET, { MCK_MR, MCK_GPR, MCK_UImm8 }, },
7641 { 3232 /* aif.mova.m.x */, RISCV::AIF_MOVA_M_X, Convert__Reg1_0, AMFBS_HasXAIFET, { MCK_GPR }, },
7642 { 3245 /* aif.mova.x.m */, RISCV::AIF_MOVA_X_M, Convert__Reg1_0, AMFBS_HasXAIFET, { MCK_GPR }, },
7643 { 3258 /* aif.packb */, RISCV::AIF_PACKB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7644 { 3268 /* aif.sbg */, RISCV::AIF_SBG, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7645 { 3276 /* aif.sbl */, RISCV::AIF_SBL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7646 { 3284 /* aif.shg */, RISCV::AIF_SHG, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7647 { 3292 /* aif.shl */, RISCV::AIF_SHL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7648 { 3300 /* amoadd.b */, RISCV::AMOADD_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7649 { 3309 /* amoadd.b.aq */, RISCV::AMOADD_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7650 { 3321 /* amoadd.b.aqrl */, RISCV::AMOADD_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7651 { 3335 /* amoadd.b.rl */, RISCV::AMOADD_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7652 { 3347 /* amoadd.d */, RISCV::AMOADD_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7653 { 3356 /* amoadd.d.aq */, RISCV::AMOADD_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7654 { 3368 /* amoadd.d.aqrl */, RISCV::AMOADD_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7655 { 3382 /* amoadd.d.rl */, RISCV::AMOADD_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7656 { 3394 /* amoadd.h */, RISCV::AMOADD_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7657 { 3403 /* amoadd.h.aq */, RISCV::AMOADD_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7658 { 3415 /* amoadd.h.aqrl */, RISCV::AMOADD_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7659 { 3429 /* amoadd.h.rl */, RISCV::AMOADD_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7660 { 3441 /* amoadd.w */, RISCV::AMOADD_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7661 { 3450 /* amoadd.w.aq */, RISCV::AMOADD_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7662 { 3462 /* amoadd.w.aqrl */, RISCV::AMOADD_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7663 { 3476 /* amoadd.w.rl */, RISCV::AMOADD_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7664 { 3488 /* amoand.b */, RISCV::AMOAND_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7665 { 3497 /* amoand.b.aq */, RISCV::AMOAND_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7666 { 3509 /* amoand.b.aqrl */, RISCV::AMOAND_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7667 { 3523 /* amoand.b.rl */, RISCV::AMOAND_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7668 { 3535 /* amoand.d */, RISCV::AMOAND_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7669 { 3544 /* amoand.d.aq */, RISCV::AMOAND_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7670 { 3556 /* amoand.d.aqrl */, RISCV::AMOAND_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7671 { 3570 /* amoand.d.rl */, RISCV::AMOAND_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7672 { 3582 /* amoand.h */, RISCV::AMOAND_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7673 { 3591 /* amoand.h.aq */, RISCV::AMOAND_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7674 { 3603 /* amoand.h.aqrl */, RISCV::AMOAND_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7675 { 3617 /* amoand.h.rl */, RISCV::AMOAND_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7676 { 3629 /* amoand.w */, RISCV::AMOAND_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7677 { 3638 /* amoand.w.aq */, RISCV::AMOAND_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7678 { 3650 /* amoand.w.aqrl */, RISCV::AMOAND_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7679 { 3664 /* amoand.w.rl */, RISCV::AMOAND_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7680 { 3676 /* amocas.b */, RISCV::AMOCAS_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7681 { 3685 /* amocas.b.aq */, RISCV::AMOCAS_B_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7682 { 3697 /* amocas.b.aqrl */, RISCV::AMOCAS_B_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7683 { 3711 /* amocas.b.rl */, RISCV::AMOCAS_B_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7684 { 3723 /* amocas.d */, RISCV::AMOCAS_D_RV64, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7685 { 3723 /* amocas.d */, RISCV::AMOCAS_D_RV32, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7686 { 3732 /* amocas.d.aq */, RISCV::AMOCAS_D_RV64_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7687 { 3732 /* amocas.d.aq */, RISCV::AMOCAS_D_RV32_AQ, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7688 { 3744 /* amocas.d.aqrl */, RISCV::AMOCAS_D_RV64_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7689 { 3744 /* amocas.d.aqrl */, RISCV::AMOCAS_D_RV32_AQRL, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7690 { 3758 /* amocas.d.rl */, RISCV::AMOCAS_D_RV64_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7691 { 3758 /* amocas.d.rl */, RISCV::AMOCAS_D_RV32_RL, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7692 { 3770 /* amocas.h */, RISCV::AMOCAS_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7693 { 3779 /* amocas.h.aq */, RISCV::AMOCAS_H_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7694 { 3791 /* amocas.h.aqrl */, RISCV::AMOCAS_H_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7695 { 3805 /* amocas.h.rl */, RISCV::AMOCAS_H_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7696 { 3817 /* amocas.q */, RISCV::AMOCAS_Q, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7697 { 3826 /* amocas.q.aq */, RISCV::AMOCAS_Q_AQ, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7698 { 3838 /* amocas.q.aqrl */, RISCV::AMOCAS_Q_AQRL, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7699 { 3852 /* amocas.q.rl */, RISCV::AMOCAS_Q_RL, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7700 { 3864 /* amocas.w */, RISCV::AMOCAS_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7701 { 3873 /* amocas.w.aq */, RISCV::AMOCAS_W_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7702 { 3885 /* amocas.w.aqrl */, RISCV::AMOCAS_W_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7703 { 3899 /* amocas.w.rl */, RISCV::AMOCAS_W_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7704 { 3911 /* amomax.b */, RISCV::AMOMAX_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7705 { 3920 /* amomax.b.aq */, RISCV::AMOMAX_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7706 { 3932 /* amomax.b.aqrl */, RISCV::AMOMAX_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7707 { 3946 /* amomax.b.rl */, RISCV::AMOMAX_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7708 { 3958 /* amomax.d */, RISCV::AMOMAX_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7709 { 3967 /* amomax.d.aq */, RISCV::AMOMAX_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7710 { 3979 /* amomax.d.aqrl */, RISCV::AMOMAX_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7711 { 3993 /* amomax.d.rl */, RISCV::AMOMAX_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7712 { 4005 /* amomax.h */, RISCV::AMOMAX_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7713 { 4014 /* amomax.h.aq */, RISCV::AMOMAX_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7714 { 4026 /* amomax.h.aqrl */, RISCV::AMOMAX_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7715 { 4040 /* amomax.h.rl */, RISCV::AMOMAX_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7716 { 4052 /* amomax.w */, RISCV::AMOMAX_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7717 { 4061 /* amomax.w.aq */, RISCV::AMOMAX_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7718 { 4073 /* amomax.w.aqrl */, RISCV::AMOMAX_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7719 { 4087 /* amomax.w.rl */, RISCV::AMOMAX_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7720 { 4099 /* amomaxu.b */, RISCV::AMOMAXU_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7721 { 4109 /* amomaxu.b.aq */, RISCV::AMOMAXU_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7722 { 4122 /* amomaxu.b.aqrl */, RISCV::AMOMAXU_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7723 { 4137 /* amomaxu.b.rl */, RISCV::AMOMAXU_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7724 { 4150 /* amomaxu.d */, RISCV::AMOMAXU_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7725 { 4160 /* amomaxu.d.aq */, RISCV::AMOMAXU_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7726 { 4173 /* amomaxu.d.aqrl */, RISCV::AMOMAXU_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7727 { 4188 /* amomaxu.d.rl */, RISCV::AMOMAXU_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7728 { 4201 /* amomaxu.h */, RISCV::AMOMAXU_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7729 { 4211 /* amomaxu.h.aq */, RISCV::AMOMAXU_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7730 { 4224 /* amomaxu.h.aqrl */, RISCV::AMOMAXU_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7731 { 4239 /* amomaxu.h.rl */, RISCV::AMOMAXU_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7732 { 4252 /* amomaxu.w */, RISCV::AMOMAXU_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7733 { 4262 /* amomaxu.w.aq */, RISCV::AMOMAXU_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7734 { 4275 /* amomaxu.w.aqrl */, RISCV::AMOMAXU_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7735 { 4290 /* amomaxu.w.rl */, RISCV::AMOMAXU_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7736 { 4303 /* amomin.b */, RISCV::AMOMIN_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7737 { 4312 /* amomin.b.aq */, RISCV::AMOMIN_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7738 { 4324 /* amomin.b.aqrl */, RISCV::AMOMIN_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7739 { 4338 /* amomin.b.rl */, RISCV::AMOMIN_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7740 { 4350 /* amomin.d */, RISCV::AMOMIN_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7741 { 4359 /* amomin.d.aq */, RISCV::AMOMIN_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7742 { 4371 /* amomin.d.aqrl */, RISCV::AMOMIN_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7743 { 4385 /* amomin.d.rl */, RISCV::AMOMIN_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7744 { 4397 /* amomin.h */, RISCV::AMOMIN_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7745 { 4406 /* amomin.h.aq */, RISCV::AMOMIN_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7746 { 4418 /* amomin.h.aqrl */, RISCV::AMOMIN_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7747 { 4432 /* amomin.h.rl */, RISCV::AMOMIN_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7748 { 4444 /* amomin.w */, RISCV::AMOMIN_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7749 { 4453 /* amomin.w.aq */, RISCV::AMOMIN_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7750 { 4465 /* amomin.w.aqrl */, RISCV::AMOMIN_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7751 { 4479 /* amomin.w.rl */, RISCV::AMOMIN_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7752 { 4491 /* amominu.b */, RISCV::AMOMINU_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7753 { 4501 /* amominu.b.aq */, RISCV::AMOMINU_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7754 { 4514 /* amominu.b.aqrl */, RISCV::AMOMINU_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7755 { 4529 /* amominu.b.rl */, RISCV::AMOMINU_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7756 { 4542 /* amominu.d */, RISCV::AMOMINU_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7757 { 4552 /* amominu.d.aq */, RISCV::AMOMINU_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7758 { 4565 /* amominu.d.aqrl */, RISCV::AMOMINU_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7759 { 4580 /* amominu.d.rl */, RISCV::AMOMINU_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7760 { 4593 /* amominu.h */, RISCV::AMOMINU_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7761 { 4603 /* amominu.h.aq */, RISCV::AMOMINU_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7762 { 4616 /* amominu.h.aqrl */, RISCV::AMOMINU_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7763 { 4631 /* amominu.h.rl */, RISCV::AMOMINU_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7764 { 4644 /* amominu.w */, RISCV::AMOMINU_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7765 { 4654 /* amominu.w.aq */, RISCV::AMOMINU_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7766 { 4667 /* amominu.w.aqrl */, RISCV::AMOMINU_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7767 { 4682 /* amominu.w.rl */, RISCV::AMOMINU_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7768 { 4695 /* amoor.b */, RISCV::AMOOR_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7769 { 4703 /* amoor.b.aq */, RISCV::AMOOR_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7770 { 4714 /* amoor.b.aqrl */, RISCV::AMOOR_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7771 { 4727 /* amoor.b.rl */, RISCV::AMOOR_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7772 { 4738 /* amoor.d */, RISCV::AMOOR_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7773 { 4746 /* amoor.d.aq */, RISCV::AMOOR_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7774 { 4757 /* amoor.d.aqrl */, RISCV::AMOOR_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7775 { 4770 /* amoor.d.rl */, RISCV::AMOOR_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7776 { 4781 /* amoor.h */, RISCV::AMOOR_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7777 { 4789 /* amoor.h.aq */, RISCV::AMOOR_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7778 { 4800 /* amoor.h.aqrl */, RISCV::AMOOR_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7779 { 4813 /* amoor.h.rl */, RISCV::AMOOR_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7780 { 4824 /* amoor.w */, RISCV::AMOOR_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7781 { 4832 /* amoor.w.aq */, RISCV::AMOOR_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7782 { 4843 /* amoor.w.aqrl */, RISCV::AMOOR_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7783 { 4856 /* amoor.w.rl */, RISCV::AMOOR_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7784 { 4867 /* amoswap.b */, RISCV::AMOSWAP_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7785 { 4877 /* amoswap.b.aq */, RISCV::AMOSWAP_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7786 { 4890 /* amoswap.b.aqrl */, RISCV::AMOSWAP_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7787 { 4905 /* amoswap.b.rl */, RISCV::AMOSWAP_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7788 { 4918 /* amoswap.d */, RISCV::AMOSWAP_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7789 { 4928 /* amoswap.d.aq */, RISCV::AMOSWAP_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7790 { 4941 /* amoswap.d.aqrl */, RISCV::AMOSWAP_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7791 { 4956 /* amoswap.d.rl */, RISCV::AMOSWAP_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7792 { 4969 /* amoswap.h */, RISCV::AMOSWAP_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7793 { 4979 /* amoswap.h.aq */, RISCV::AMOSWAP_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7794 { 4992 /* amoswap.h.aqrl */, RISCV::AMOSWAP_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7795 { 5007 /* amoswap.h.rl */, RISCV::AMOSWAP_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7796 { 5020 /* amoswap.w */, RISCV::AMOSWAP_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7797 { 5030 /* amoswap.w.aq */, RISCV::AMOSWAP_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7798 { 5043 /* amoswap.w.aqrl */, RISCV::AMOSWAP_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7799 { 5058 /* amoswap.w.rl */, RISCV::AMOSWAP_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7800 { 5071 /* amoxor.b */, RISCV::AMOXOR_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7801 { 5080 /* amoxor.b.aq */, RISCV::AMOXOR_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7802 { 5092 /* amoxor.b.aqrl */, RISCV::AMOXOR_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7803 { 5106 /* amoxor.b.rl */, RISCV::AMOXOR_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7804 { 5118 /* amoxor.d */, RISCV::AMOXOR_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7805 { 5127 /* amoxor.d.aq */, RISCV::AMOXOR_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7806 { 5139 /* amoxor.d.aqrl */, RISCV::AMOXOR_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7807 { 5153 /* amoxor.d.rl */, RISCV::AMOXOR_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7808 { 5165 /* amoxor.h */, RISCV::AMOXOR_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7809 { 5174 /* amoxor.h.aq */, RISCV::AMOXOR_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7810 { 5186 /* amoxor.h.aqrl */, RISCV::AMOXOR_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7811 { 5200 /* amoxor.h.rl */, RISCV::AMOXOR_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7812 { 5212 /* amoxor.w */, RISCV::AMOXOR_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7813 { 5221 /* amoxor.w.aq */, RISCV::AMOXOR_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7814 { 5233 /* amoxor.w.aqrl */, RISCV::AMOXOR_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7815 { 5247 /* amoxor.w.rl */, RISCV::AMOXOR_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7816 { 5259 /* and */, RISCV::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7817 { 5259 /* and */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7818 { 5263 /* andi */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7819 { 5268 /* andn */, RISCV::ANDN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7820 { 5273 /* asub */, RISCV::ASUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7821 { 5278 /* asubu */, RISCV::ASUBU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7822 { 5284 /* auipc */, RISCV::AUIPC, Convert__Reg1_0__UImm20AUIPC1_1, AMFBS_None, { MCK_GPR, MCK_UImm20AUIPC }, },
7823 { 5290 /* bclr */, RISCV::BCLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7824 { 5290 /* bclr */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7825 { 5295 /* bclri */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7826 { 5301 /* beq */, RISCV::BEQ, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7827 { 5305 /* beqi */, RISCV::BEQI, Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2, AMFBS_HasStdExtZibi, { MCK_GPR, MCK_Imm5Zibi, MCK_BareSImm13Lsb0 }, },
7828 { 5310 /* beqz */, RISCV::BEQ, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7829 { 5315 /* bext */, RISCV::BEXT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7830 { 5315 /* bext */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7831 { 5320 /* bexti */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7832 { 5326 /* bge */, RISCV::BGE, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7833 { 5330 /* bgeu */, RISCV::BGEU, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7834 { 5335 /* bgez */, RISCV::BGE, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7835 { 5340 /* bgt */, RISCV::BLT, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7836 { 5344 /* bgtu */, RISCV::BLTU, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7837 { 5349 /* bgtz */, RISCV::BLT, Convert__regX0__Reg1_0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7838 { 5354 /* binv */, RISCV::BINV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7839 { 5354 /* binv */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7840 { 5359 /* binvi */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7841 { 5365 /* ble */, RISCV::BGE, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7842 { 5369 /* bleu */, RISCV::BGEU, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7843 { 5374 /* blez */, RISCV::BGE, Convert__regX0__Reg1_0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7844 { 5379 /* blt */, RISCV::BLT, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7845 { 5383 /* bltu */, RISCV::BLTU, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7846 { 5388 /* bltz */, RISCV::BLT, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7847 { 5393 /* bne */, RISCV::BNE, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7848 { 5397 /* bnei */, RISCV::BNEI, Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2, AMFBS_HasStdExtZibi, { MCK_GPR, MCK_Imm5Zibi, MCK_BareSImm13Lsb0 }, },
7849 { 5402 /* bnez */, RISCV::BNE, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7850 { 5407 /* brev8 */, RISCV::BREV8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR }, },
7851 { 5413 /* bset */, RISCV::BSET, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7852 { 5413 /* bset */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7853 { 5418 /* bseti */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7854 { 5424 /* c.add */, RISCV::C_ADD, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_GPRNoX0 }, },
7855 { 5430 /* c.addi */, RISCV::PseudoC_ADDI_NOP, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRX0, MCK_SImm6 }, },
7856 { 5430 /* c.addi */, RISCV::C_ADDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK_SImm6 }, },
7857 { 5437 /* c.addi16sp */, RISCV::C_ADDI16SP, Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, AMFBS_HasStdExtZca, { MCK_SP, MCK_SImm10Lsb0000NonZero }, },
7858 { 5448 /* c.addi4spn */, RISCV::C_ADDI4SPN, Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_SP, MCK_UImm10Lsb00NonZero }, },
7859 { 5459 /* c.addiw */, RISCV::C_ADDIW, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK_SImm6 }, },
7860 { 5467 /* c.addw */, RISCV::C_ADDW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
7861 { 5474 /* c.and */, RISCV::C_AND, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7862 { 5480 /* c.andi */, RISCV::C_ANDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_SImm6 }, },
7863 { 5487 /* c.beqz */, RISCV::C_BEQZ, Convert__Reg1_0__BareSImm9Lsb01_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_BareSImm9Lsb0 }, },
7864 { 5494 /* c.bnez */, RISCV::C_BNEZ, Convert__Reg1_0__BareSImm9Lsb01_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_BareSImm9Lsb0 }, },
7865 { 5501 /* c.ebreak */, RISCV::C_EBREAK, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
7866 { 5510 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7867 { 5510 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7868 { 5516 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK__40_, MCK_SP, MCK__41_ }, },
7869 { 5516 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7870 { 5524 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7871 { 5524 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7872 { 5530 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK__40_, MCK_SP, MCK__41_ }, },
7873 { 5530 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7874 { 5538 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7875 { 5538 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7876 { 5544 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK__40_, MCK_SP, MCK__41_ }, },
7877 { 5544 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7878 { 5552 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7879 { 5552 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7880 { 5558 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK__40_, MCK_SP, MCK__41_ }, },
7881 { 5558 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7882 { 5566 /* c.j */, RISCV::C_J, Convert__BareSImm12Lsb01_0, AMFBS_HasStdExtZca, { MCK_BareSImm12Lsb0 }, },
7883 { 5570 /* c.jal */, RISCV::C_JAL, Convert__BareSImm12Lsb01_0, AMFBS_HasStdExtZca_IsRV32, { MCK_BareSImm12Lsb0 }, },
7884 { 5576 /* c.jalr */, RISCV::C_JALR, Convert__Reg1_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0 }, },
7885 { 5583 /* c.jr */, RISCV::C_JR, Convert__Reg1_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0 }, },
7886 { 5588 /* c.lbu */, RISCV::C_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7887 { 5588 /* c.lbu */, RISCV::PseudoQCAccessC_LBU, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7888 { 5588 /* c.lbu */, RISCV::C_LBU, Convert__Reg1_0__Reg1_3__UImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
7889 { 5588 /* c.lbu */, RISCV::PseudoQCAccessC_LBU, Convert__Reg1_0__Reg1_3__UImm21_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7890 { 5594 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7891 { 5594 /* c.ld */, RISCV::C_LD_RV32, Convert__GPRPairCRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK__40_, MCK_GPRC, MCK__41_ }, },
7892 { 5594 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7893 { 5594 /* c.ld */, RISCV::C_LD_RV32, Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7894 { 5599 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
7895 { 5599 /* c.ldsp */, RISCV::C_LDSP_RV32, Convert__GPRPairNoX0RV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairNoX0RV32, MCK__40_, MCK_SP, MCK__41_ }, },
7896 { 5599 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7897 { 5599 /* c.ldsp */, RISCV::C_LDSP_RV32, Convert__GPRPairNoX0RV321_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairNoX0RV32, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7898 { 5606 /* c.lh */, RISCV::C_LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7899 { 5606 /* c.lh */, RISCV::PseudoQCAccessC_LH, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7900 { 5606 /* c.lh */, RISCV::C_LH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
7901 { 5606 /* c.lh */, RISCV::PseudoQCAccessC_LH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7902 { 5611 /* c.lhu */, RISCV::C_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7903 { 5611 /* c.lhu */, RISCV::PseudoQCAccessC_LHU, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7904 { 5611 /* c.lhu */, RISCV::C_LHU, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
7905 { 5611 /* c.lhu */, RISCV::PseudoQCAccessC_LHU, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7906 { 5617 /* c.li */, RISCV::C_LI, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_SImm6 }, },
7907 { 5622 /* c.lui */, RISCV::C_LUI, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtZca, { MCK_GPRNoX2, MCK_CLUIImm }, },
7908 { 5628 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7909 { 5628 /* c.lw */, RISCV::PseudoQCAccessC_LW, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7910 { 5628 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7911 { 5628 /* c.lw */, RISCV::PseudoQCAccessC_LW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7912 { 5633 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
7913 { 5633 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7914 { 5640 /* c.mop.1 */, RISCV::C_SSPUSH, Convert__regX1, AMFBS_HasStdExtZcmop, { }, },
7915 { 5648 /* c.mop.11 */, RISCV::C_MOP_11, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7916 { 5657 /* c.mop.13 */, RISCV::C_MOP_13, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7917 { 5666 /* c.mop.15 */, RISCV::C_MOP_15, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7918 { 5675 /* c.mop.3 */, RISCV::C_MOP_3, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7919 { 5683 /* c.mop.5 */, RISCV::C_SSPOPCHK, Convert__regX5, AMFBS_HasStdExtZcmop, { }, },
7920 { 5691 /* c.mop.7 */, RISCV::C_MOP_7, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7921 { 5699 /* c.mop.9 */, RISCV::C_MOP_9, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7922 { 5707 /* c.mul */, RISCV::C_MUL, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZcb_HasStdExtZmmul, { MCK_GPRC, MCK_GPRC }, },
7923 { 5713 /* c.mv */, RISCV::C_MV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_GPRNoX0 }, },
7924 { 5718 /* c.nop */, RISCV::C_NOP, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
7925 { 5718 /* c.nop */, RISCV::C_NOP_HINT, Convert__SImm6NonZero1_0, AMFBS_HasStdExtZca, { MCK_SImm6NonZero }, },
7926 { 5724 /* c.not */, RISCV::C_NOT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
7927 { 5730 /* c.ntl.all */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX5, AMFBS_HasStdExtZca, { }, },
7928 { 5740 /* c.ntl.p1 */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX2, AMFBS_HasStdExtZca, { }, },
7929 { 5749 /* c.ntl.pall */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX3, AMFBS_HasStdExtZca, { }, },
7930 { 5760 /* c.ntl.s1 */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX4, AMFBS_HasStdExtZca, { }, },
7931 { 5769 /* c.or */, RISCV::C_OR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7932 { 5774 /* c.sb */, RISCV::C_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7933 { 5774 /* c.sb */, RISCV::PseudoQCAccessC_SB, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7934 { 5774 /* c.sb */, RISCV::C_SB, Convert__Reg1_0__Reg1_3__UImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
7935 { 5774 /* c.sb */, RISCV::PseudoQCAccessC_SB, Convert__Reg1_0__Reg1_3__UImm21_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7936 { 5779 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7937 { 5779 /* c.sd */, RISCV::C_SD_RV32, Convert__GPRPairCRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK__40_, MCK_GPRC, MCK__41_ }, },
7938 { 5779 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7939 { 5779 /* c.sd */, RISCV::C_SD_RV32, Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7940 { 5784 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPR, MCK__40_, MCK_SP, MCK__41_ }, },
7941 { 5784 /* c.sdsp */, RISCV::C_SDSP_RV32, Convert__GPRPairRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairRV32, MCK__40_, MCK_SP, MCK__41_ }, },
7942 { 5784 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPR, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7943 { 5784 /* c.sdsp */, RISCV::C_SDSP_RV32, Convert__GPRPairRV321_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairRV32, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7944 { 5791 /* c.sext.b */, RISCV::C_SEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
7945 { 5800 /* c.sext.h */, RISCV::C_SEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
7946 { 5809 /* c.sh */, RISCV::C_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7947 { 5809 /* c.sh */, RISCV::PseudoQCAccessC_SH, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7948 { 5809 /* c.sh */, RISCV::C_SH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
7949 { 5809 /* c.sh */, RISCV::PseudoQCAccessC_SH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7950 { 5814 /* c.slli */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_UImmLog2XLen }, },
7951 { 5821 /* c.slli64 */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPR }, },
7952 { 5830 /* c.srai */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImmLog2XLen }, },
7953 { 5837 /* c.srai64 */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC }, },
7954 { 5846 /* c.srli */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImmLog2XLen }, },
7955 { 5853 /* c.srli64 */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC }, },
7956 { 5862 /* c.sspopchk */, RISCV::C_SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZcmop, { MCK_GPRX5 }, },
7957 { 5873 /* c.sspush */, RISCV::C_SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZcmop, { MCK_GPRX1 }, },
7958 { 5882 /* c.sub */, RISCV::C_SUB, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7959 { 5888 /* c.subw */, RISCV::C_SUBW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
7960 { 5895 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7961 { 5895 /* c.sw */, RISCV::PseudoQCAccessC_SW, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7962 { 5895 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7963 { 5895 /* c.sw */, RISCV::PseudoQCAccessC_SW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7964 { 5900 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPR, MCK__40_, MCK_SP, MCK__41_ }, },
7965 { 5900 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7966 { 5907 /* c.unimp */, RISCV::C_UNIMP, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
7967 { 5915 /* c.xor */, RISCV::C_XOR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7968 { 5921 /* c.zext.b */, RISCV::C_ZEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
7969 { 5930 /* c.zext.h */, RISCV::C_ZEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
7970 { 5939 /* c.zext.w */, RISCV::C_ZEXT_W, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64, { MCK_GPRC }, },
7971 { 5948 /* call */, RISCV::PseudoCALL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
7972 { 5948 /* call */, RISCV::PseudoCALLReg, Convert__Reg1_0__CallSymbol1_1, AMFBS_None, { MCK_GPR, MCK_CallSymbol }, },
7973 { 5953 /* cbo.clean */, RISCV::CBO_CLEAN, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
7974 { 5963 /* cbo.flush */, RISCV::CBO_FLUSH, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
7975 { 5973 /* cbo.inval */, RISCV::CBO_INVAL, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
7976 { 5983 /* cbo.zero */, RISCV::CBO_ZERO, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicboz, { MCK_ZeroOffsetMemOpOperand }, },
7977 { 5992 /* clmul */, RISCV::CLMUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7978 { 5998 /* clmulh */, RISCV::CLMULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7979 { 6005 /* clmulr */, RISCV::CLMULR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7980 { 6012 /* cls */, RISCV::CLS, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
7981 { 6016 /* clsw */, RISCV::CLSW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
7982 { 6021 /* clz */, RISCV::CLZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
7983 { 6025 /* clzw */, RISCV::CLZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
7984 { 6030 /* cm.jalt */, RISCV::CM_JALT, Convert__UImm8GE321_0, AMFBS_HasStdExtZcmt, { MCK_UImm8GE32 }, },
7985 { 6038 /* cm.jt */, RISCV::CM_JT, Convert__UImm51_0, AMFBS_HasStdExtZcmt, { MCK_UImm5 }, },
7986 { 6044 /* cm.mva01s */, RISCV::CM_MVA01S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_SR07, MCK_SR07 }, },
7987 { 6054 /* cm.mvsa01 */, RISCV::CM_MVSA01, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_SR07, MCK_SR07 }, },
7988 { 6064 /* cm.pop */, RISCV::CM_POP, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
7989 { 6071 /* cm.popret */, RISCV::CM_POPRET, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
7990 { 6081 /* cm.popretz */, RISCV::CM_POPRETZ, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
7991 { 6092 /* cm.push */, RISCV::CM_PUSH, Convert__RegList1_0__NegStackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_NegStackAdj }, },
7992 { 6100 /* cpop */, RISCV::CPOP, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
7993 { 6105 /* cpopw */, RISCV::CPOPW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
7994 { 6111 /* csrc */, RISCV::CSRRC, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
7995 { 6111 /* csrc */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7996 { 6116 /* csrci */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7997 { 6122 /* csrr */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, },
7998 { 6127 /* csrrc */, RISCV::CSRRC, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
7999 { 6127 /* csrrc */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8000 { 6133 /* csrrci */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8001 { 6140 /* csrrs */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
8002 { 6140 /* csrrs */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8003 { 6146 /* csrrsi */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8004 { 6153 /* csrrw */, RISCV::CSRRW, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
8005 { 6153 /* csrrw */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8006 { 6159 /* csrrwi */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8007 { 6166 /* csrs */, RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
8008 { 6166 /* csrs */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8009 { 6171 /* csrsi */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8010 { 6177 /* csrw */, RISCV::CSRRW, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
8011 { 6177 /* csrw */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8012 { 6182 /* csrwi */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8013 { 6188 /* ctz */, RISCV::CTZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
8014 { 6192 /* ctzw */, RISCV::CTZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
8015 { 6197 /* cv.abs */, RISCV::CV_ABS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8016 { 6204 /* cv.abs.b */, RISCV::CV_ABS_B, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
8017 { 6213 /* cv.abs.h */, RISCV::CV_ABS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
8018 { 6222 /* cv.add.b */, RISCV::CV_ADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8019 { 6231 /* cv.add.div2 */, RISCV::CV_ADD_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8020 { 6243 /* cv.add.div4 */, RISCV::CV_ADD_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8021 { 6255 /* cv.add.div8 */, RISCV::CV_ADD_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8022 { 6267 /* cv.add.h */, RISCV::CV_ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8023 { 6276 /* cv.add.sc.b */, RISCV::CV_ADD_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8024 { 6288 /* cv.add.sc.h */, RISCV::CV_ADD_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8025 { 6300 /* cv.add.sci.b */, RISCV::CV_ADD_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8026 { 6313 /* cv.add.sci.h */, RISCV::CV_ADD_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8027 { 6326 /* cv.addn */, RISCV::CV_ADDN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8028 { 6334 /* cv.addnr */, RISCV::CV_ADDNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8029 { 6343 /* cv.addrn */, RISCV::CV_ADDRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8030 { 6352 /* cv.addrnr */, RISCV::CV_ADDRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8031 { 6362 /* cv.addun */, RISCV::CV_ADDUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8032 { 6371 /* cv.addunr */, RISCV::CV_ADDUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8033 { 6381 /* cv.addurn */, RISCV::CV_ADDURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8034 { 6391 /* cv.addurnr */, RISCV::CV_ADDURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8035 { 6402 /* cv.and.b */, RISCV::CV_AND_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8036 { 6411 /* cv.and.h */, RISCV::CV_AND_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8037 { 6420 /* cv.and.sc.b */, RISCV::CV_AND_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8038 { 6432 /* cv.and.sc.h */, RISCV::CV_AND_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8039 { 6444 /* cv.and.sci.b */, RISCV::CV_AND_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8040 { 6457 /* cv.and.sci.h */, RISCV::CV_AND_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8041 { 6470 /* cv.avg.b */, RISCV::CV_AVG_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8042 { 6479 /* cv.avg.h */, RISCV::CV_AVG_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8043 { 6488 /* cv.avg.sc.b */, RISCV::CV_AVG_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8044 { 6500 /* cv.avg.sc.h */, RISCV::CV_AVG_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8045 { 6512 /* cv.avg.sci.b */, RISCV::CV_AVG_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8046 { 6525 /* cv.avg.sci.h */, RISCV::CV_AVG_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8047 { 6538 /* cv.avgu.b */, RISCV::CV_AVGU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8048 { 6548 /* cv.avgu.h */, RISCV::CV_AVGU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8049 { 6558 /* cv.avgu.sc.b */, RISCV::CV_AVGU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8050 { 6571 /* cv.avgu.sc.h */, RISCV::CV_AVGU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8051 { 6584 /* cv.avgu.sci.b */, RISCV::CV_AVGU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8052 { 6598 /* cv.avgu.sci.h */, RISCV::CV_AVGU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8053 { 6612 /* cv.bclr */, RISCV::CV_BCLR, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8054 { 6620 /* cv.bclrr */, RISCV::CV_BCLRR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8055 { 6629 /* cv.beqimm */, RISCV::CV_BEQIMM, Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_BareSImm13Lsb0 }, },
8056 { 6639 /* cv.bitrev */, RISCV::CV_BITREV, Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm2, MCK_UImm5 }, },
8057 { 6649 /* cv.bneimm */, RISCV::CV_BNEIMM, Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_BareSImm13Lsb0 }, },
8058 { 6659 /* cv.bset */, RISCV::CV_BSET, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8059 { 6667 /* cv.bsetr */, RISCV::CV_BSETR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8060 { 6676 /* cv.clb */, RISCV::CV_CLB, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8061 { 6683 /* cv.clip */, RISCV::CV_CLIP, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8062 { 6691 /* cv.clipr */, RISCV::CV_CLIPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8063 { 6700 /* cv.clipu */, RISCV::CV_CLIPU, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8064 { 6709 /* cv.clipur */, RISCV::CV_CLIPUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8065 { 6719 /* cv.cmpeq.b */, RISCV::CV_CMPEQ_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8066 { 6730 /* cv.cmpeq.h */, RISCV::CV_CMPEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8067 { 6741 /* cv.cmpeq.sc.b */, RISCV::CV_CMPEQ_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8068 { 6755 /* cv.cmpeq.sc.h */, RISCV::CV_CMPEQ_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8069 { 6769 /* cv.cmpeq.sci.b */, RISCV::CV_CMPEQ_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8070 { 6784 /* cv.cmpeq.sci.h */, RISCV::CV_CMPEQ_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8071 { 6799 /* cv.cmpge.b */, RISCV::CV_CMPGE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8072 { 6810 /* cv.cmpge.h */, RISCV::CV_CMPGE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8073 { 6821 /* cv.cmpge.sc.b */, RISCV::CV_CMPGE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8074 { 6835 /* cv.cmpge.sc.h */, RISCV::CV_CMPGE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8075 { 6849 /* cv.cmpge.sci.b */, RISCV::CV_CMPGE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8076 { 6864 /* cv.cmpge.sci.h */, RISCV::CV_CMPGE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8077 { 6879 /* cv.cmpgeu.b */, RISCV::CV_CMPGEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8078 { 6891 /* cv.cmpgeu.h */, RISCV::CV_CMPGEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8079 { 6903 /* cv.cmpgeu.sc.b */, RISCV::CV_CMPGEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8080 { 6918 /* cv.cmpgeu.sc.h */, RISCV::CV_CMPGEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8081 { 6933 /* cv.cmpgeu.sci.b */, RISCV::CV_CMPGEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8082 { 6949 /* cv.cmpgeu.sci.h */, RISCV::CV_CMPGEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8083 { 6965 /* cv.cmpgt.b */, RISCV::CV_CMPGT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8084 { 6976 /* cv.cmpgt.h */, RISCV::CV_CMPGT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8085 { 6987 /* cv.cmpgt.sc.b */, RISCV::CV_CMPGT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8086 { 7001 /* cv.cmpgt.sc.h */, RISCV::CV_CMPGT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8087 { 7015 /* cv.cmpgt.sci.b */, RISCV::CV_CMPGT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8088 { 7030 /* cv.cmpgt.sci.h */, RISCV::CV_CMPGT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8089 { 7045 /* cv.cmpgtu.b */, RISCV::CV_CMPGTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8090 { 7057 /* cv.cmpgtu.h */, RISCV::CV_CMPGTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8091 { 7069 /* cv.cmpgtu.sc.b */, RISCV::CV_CMPGTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8092 { 7084 /* cv.cmpgtu.sc.h */, RISCV::CV_CMPGTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8093 { 7099 /* cv.cmpgtu.sci.b */, RISCV::CV_CMPGTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8094 { 7115 /* cv.cmpgtu.sci.h */, RISCV::CV_CMPGTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8095 { 7131 /* cv.cmple.b */, RISCV::CV_CMPLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8096 { 7142 /* cv.cmple.h */, RISCV::CV_CMPLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8097 { 7153 /* cv.cmple.sc.b */, RISCV::CV_CMPLE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8098 { 7167 /* cv.cmple.sc.h */, RISCV::CV_CMPLE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8099 { 7181 /* cv.cmple.sci.b */, RISCV::CV_CMPLE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8100 { 7196 /* cv.cmple.sci.h */, RISCV::CV_CMPLE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8101 { 7211 /* cv.cmpleu.b */, RISCV::CV_CMPLEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8102 { 7223 /* cv.cmpleu.h */, RISCV::CV_CMPLEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8103 { 7235 /* cv.cmpleu.sc.b */, RISCV::CV_CMPLEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8104 { 7250 /* cv.cmpleu.sc.h */, RISCV::CV_CMPLEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8105 { 7265 /* cv.cmpleu.sci.b */, RISCV::CV_CMPLEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8106 { 7281 /* cv.cmpleu.sci.h */, RISCV::CV_CMPLEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8107 { 7297 /* cv.cmplt.b */, RISCV::CV_CMPLT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8108 { 7308 /* cv.cmplt.h */, RISCV::CV_CMPLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8109 { 7319 /* cv.cmplt.sc.b */, RISCV::CV_CMPLT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8110 { 7333 /* cv.cmplt.sc.h */, RISCV::CV_CMPLT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8111 { 7347 /* cv.cmplt.sci.b */, RISCV::CV_CMPLT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8112 { 7362 /* cv.cmplt.sci.h */, RISCV::CV_CMPLT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8113 { 7377 /* cv.cmpltu.b */, RISCV::CV_CMPLTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8114 { 7389 /* cv.cmpltu.h */, RISCV::CV_CMPLTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8115 { 7401 /* cv.cmpltu.sc.b */, RISCV::CV_CMPLTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8116 { 7416 /* cv.cmpltu.sc.h */, RISCV::CV_CMPLTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8117 { 7431 /* cv.cmpltu.sci.b */, RISCV::CV_CMPLTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8118 { 7447 /* cv.cmpltu.sci.h */, RISCV::CV_CMPLTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8119 { 7463 /* cv.cmpne.b */, RISCV::CV_CMPNE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8120 { 7474 /* cv.cmpne.h */, RISCV::CV_CMPNE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8121 { 7485 /* cv.cmpne.sc.b */, RISCV::CV_CMPNE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8122 { 7499 /* cv.cmpne.sc.h */, RISCV::CV_CMPNE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8123 { 7513 /* cv.cmpne.sci.b */, RISCV::CV_CMPNE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8124 { 7528 /* cv.cmpne.sci.h */, RISCV::CV_CMPNE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8125 { 7543 /* cv.cnt */, RISCV::CV_CNT, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8126 { 7550 /* cv.cplxconj */, RISCV::CV_CPLXCONJ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
8127 { 7562 /* cv.cplxmul.i */, RISCV::CV_CPLXMUL_I, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8128 { 7575 /* cv.cplxmul.i.div2 */, RISCV::CV_CPLXMUL_I_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8129 { 7593 /* cv.cplxmul.i.div4 */, RISCV::CV_CPLXMUL_I_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8130 { 7611 /* cv.cplxmul.i.div8 */, RISCV::CV_CPLXMUL_I_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8131 { 7629 /* cv.cplxmul.r */, RISCV::CV_CPLXMUL_R, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8132 { 7642 /* cv.cplxmul.r.div2 */, RISCV::CV_CPLXMUL_R_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8133 { 7660 /* cv.cplxmul.r.div4 */, RISCV::CV_CPLXMUL_R_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8134 { 7678 /* cv.cplxmul.r.div8 */, RISCV::CV_CPLXMUL_R_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8135 { 7696 /* cv.dotsp.b */, RISCV::CV_DOTSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8136 { 7707 /* cv.dotsp.h */, RISCV::CV_DOTSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8137 { 7718 /* cv.dotsp.sc.b */, RISCV::CV_DOTSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8138 { 7732 /* cv.dotsp.sc.h */, RISCV::CV_DOTSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8139 { 7746 /* cv.dotsp.sci.b */, RISCV::CV_DOTSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8140 { 7761 /* cv.dotsp.sci.h */, RISCV::CV_DOTSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8141 { 7776 /* cv.dotup.b */, RISCV::CV_DOTUP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8142 { 7787 /* cv.dotup.h */, RISCV::CV_DOTUP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8143 { 7798 /* cv.dotup.sc.b */, RISCV::CV_DOTUP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8144 { 7812 /* cv.dotup.sc.h */, RISCV::CV_DOTUP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8145 { 7826 /* cv.dotup.sci.b */, RISCV::CV_DOTUP_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8146 { 7841 /* cv.dotup.sci.h */, RISCV::CV_DOTUP_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8147 { 7856 /* cv.dotusp.b */, RISCV::CV_DOTUSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8148 { 7868 /* cv.dotusp.h */, RISCV::CV_DOTUSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8149 { 7880 /* cv.dotusp.sc.b */, RISCV::CV_DOTUSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8150 { 7895 /* cv.dotusp.sc.h */, RISCV::CV_DOTUSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8151 { 7910 /* cv.dotusp.sci.b */, RISCV::CV_DOTUSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8152 { 7926 /* cv.dotusp.sci.h */, RISCV::CV_DOTUSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8153 { 7942 /* cv.elw */, RISCV::PseudoCV_ELW, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXCVelw_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
8154 { 7942 /* cv.elw */, RISCV::CV_ELW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasVendorXCVelw_IsRV32, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8155 { 7949 /* cv.extbs */, RISCV::CV_EXTBS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8156 { 7958 /* cv.extbz */, RISCV::CV_EXTBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8157 { 7967 /* cv.exths */, RISCV::CV_EXTHS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8158 { 7976 /* cv.exthz */, RISCV::CV_EXTHZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8159 { 7985 /* cv.extract */, RISCV::CV_EXTRACT, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8160 { 7996 /* cv.extract.b */, RISCV::CV_EXTRACT_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8161 { 8009 /* cv.extract.h */, RISCV::CV_EXTRACT_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8162 { 8022 /* cv.extractr */, RISCV::CV_EXTRACTR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8163 { 8034 /* cv.extractu */, RISCV::CV_EXTRACTU, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8164 { 8046 /* cv.extractu.b */, RISCV::CV_EXTRACTU_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8165 { 8060 /* cv.extractu.h */, RISCV::CV_EXTRACTU_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8166 { 8074 /* cv.extractur */, RISCV::CV_EXTRACTUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8167 { 8087 /* cv.ff1 */, RISCV::CV_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8168 { 8094 /* cv.fl1 */, RISCV::CV_FL1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8169 { 8101 /* cv.insert */, RISCV::CV_INSERT, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8170 { 8111 /* cv.insert.b */, RISCV::CV_INSERT_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8171 { 8123 /* cv.insert.h */, RISCV::CV_INSERT_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8172 { 8135 /* cv.insertr */, RISCV::CV_INSERTR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8173 { 8146 /* cv.lb */, RISCV::CV_LB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8174 { 8146 /* cv.lb */, RISCV::CV_LB_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8175 { 8146 /* cv.lb */, RISCV::CV_LB_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8176 { 8152 /* cv.lbu */, RISCV::CV_LBU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8177 { 8152 /* cv.lbu */, RISCV::CV_LBU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8178 { 8152 /* cv.lbu */, RISCV::CV_LBU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8179 { 8159 /* cv.lh */, RISCV::CV_LH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8180 { 8159 /* cv.lh */, RISCV::CV_LH_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8181 { 8159 /* cv.lh */, RISCV::CV_LH_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8182 { 8165 /* cv.lhu */, RISCV::CV_LHU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8183 { 8165 /* cv.lhu */, RISCV::CV_LHU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8184 { 8165 /* cv.lhu */, RISCV::CV_LHU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8185 { 8172 /* cv.lw */, RISCV::CV_LW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8186 { 8172 /* cv.lw */, RISCV::CV_LW_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8187 { 8172 /* cv.lw */, RISCV::CV_LW_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8188 { 8178 /* cv.mac */, RISCV::CV_MAC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8189 { 8185 /* cv.machhsn */, RISCV::CV_MACHHSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8190 { 8196 /* cv.machhsrn */, RISCV::CV_MACHHSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8191 { 8208 /* cv.machhun */, RISCV::CV_MACHHUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8192 { 8219 /* cv.machhurn */, RISCV::CV_MACHHURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8193 { 8231 /* cv.macsn */, RISCV::CV_MACSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8194 { 8240 /* cv.macsrn */, RISCV::CV_MACSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8195 { 8250 /* cv.macun */, RISCV::CV_MACUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8196 { 8259 /* cv.macurn */, RISCV::CV_MACURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8197 { 8269 /* cv.max */, RISCV::CV_MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8198 { 8276 /* cv.max.b */, RISCV::CV_MAX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8199 { 8285 /* cv.max.h */, RISCV::CV_MAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8200 { 8294 /* cv.max.sc.b */, RISCV::CV_MAX_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8201 { 8306 /* cv.max.sc.h */, RISCV::CV_MAX_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8202 { 8318 /* cv.max.sci.b */, RISCV::CV_MAX_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8203 { 8331 /* cv.max.sci.h */, RISCV::CV_MAX_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8204 { 8344 /* cv.maxu */, RISCV::CV_MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8205 { 8352 /* cv.maxu.b */, RISCV::CV_MAXU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8206 { 8362 /* cv.maxu.h */, RISCV::CV_MAXU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8207 { 8372 /* cv.maxu.sc.b */, RISCV::CV_MAXU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8208 { 8385 /* cv.maxu.sc.h */, RISCV::CV_MAXU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8209 { 8398 /* cv.maxu.sci.b */, RISCV::CV_MAXU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8210 { 8412 /* cv.maxu.sci.h */, RISCV::CV_MAXU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8211 { 8426 /* cv.min */, RISCV::CV_MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8212 { 8433 /* cv.min.b */, RISCV::CV_MIN_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8213 { 8442 /* cv.min.h */, RISCV::CV_MIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8214 { 8451 /* cv.min.sc.b */, RISCV::CV_MIN_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8215 { 8463 /* cv.min.sc.h */, RISCV::CV_MIN_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8216 { 8475 /* cv.min.sci.b */, RISCV::CV_MIN_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8217 { 8488 /* cv.min.sci.h */, RISCV::CV_MIN_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8218 { 8501 /* cv.minu */, RISCV::CV_MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8219 { 8509 /* cv.minu.b */, RISCV::CV_MINU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8220 { 8519 /* cv.minu.h */, RISCV::CV_MINU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8221 { 8529 /* cv.minu.sc.b */, RISCV::CV_MINU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8222 { 8542 /* cv.minu.sc.h */, RISCV::CV_MINU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8223 { 8555 /* cv.minu.sci.b */, RISCV::CV_MINU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8224 { 8569 /* cv.minu.sci.h */, RISCV::CV_MINU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8225 { 8583 /* cv.msu */, RISCV::CV_MSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8226 { 8590 /* cv.mulhhs */, RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8227 { 8600 /* cv.mulhhsn */, RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8228 { 8611 /* cv.mulhhsrn */, RISCV::CV_MULHHSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8229 { 8623 /* cv.mulhhu */, RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8230 { 8633 /* cv.mulhhun */, RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8231 { 8644 /* cv.mulhhurn */, RISCV::CV_MULHHURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8232 { 8656 /* cv.muls */, RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8233 { 8664 /* cv.mulsn */, RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8234 { 8673 /* cv.mulsrn */, RISCV::CV_MULSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8235 { 8683 /* cv.mulu */, RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8236 { 8691 /* cv.mulun */, RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8237 { 8700 /* cv.mulurn */, RISCV::CV_MULURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8238 { 8710 /* cv.or.b */, RISCV::CV_OR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8239 { 8718 /* cv.or.h */, RISCV::CV_OR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8240 { 8726 /* cv.or.sc.b */, RISCV::CV_OR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8241 { 8737 /* cv.or.sc.h */, RISCV::CV_OR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8242 { 8748 /* cv.or.sci.b */, RISCV::CV_OR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8243 { 8760 /* cv.or.sci.h */, RISCV::CV_OR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8244 { 8772 /* cv.pack */, RISCV::CV_PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8245 { 8780 /* cv.pack.h */, RISCV::CV_PACK_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8246 { 8790 /* cv.packhi.b */, RISCV::CV_PACKHI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8247 { 8802 /* cv.packlo.b */, RISCV::CV_PACKLO_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8248 { 8814 /* cv.ror */, RISCV::CV_ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8249 { 8821 /* cv.sb */, RISCV::CV_SB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8250 { 8821 /* cv.sb */, RISCV::CV_SB_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8251 { 8821 /* cv.sb */, RISCV::CV_SB_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8252 { 8827 /* cv.sdotsp.b */, RISCV::CV_SDOTSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8253 { 8839 /* cv.sdotsp.h */, RISCV::CV_SDOTSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8254 { 8851 /* cv.sdotsp.sc.b */, RISCV::CV_SDOTSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8255 { 8866 /* cv.sdotsp.sc.h */, RISCV::CV_SDOTSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8256 { 8881 /* cv.sdotsp.sci.b */, RISCV::CV_SDOTSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8257 { 8897 /* cv.sdotsp.sci.h */, RISCV::CV_SDOTSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8258 { 8913 /* cv.sdotup.b */, RISCV::CV_SDOTUP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8259 { 8925 /* cv.sdotup.h */, RISCV::CV_SDOTUP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8260 { 8937 /* cv.sdotup.sc.b */, RISCV::CV_SDOTUP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8261 { 8952 /* cv.sdotup.sc.h */, RISCV::CV_SDOTUP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8262 { 8967 /* cv.sdotup.sci.b */, RISCV::CV_SDOTUP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8263 { 8983 /* cv.sdotup.sci.h */, RISCV::CV_SDOTUP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8264 { 8999 /* cv.sdotusp.b */, RISCV::CV_SDOTUSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8265 { 9012 /* cv.sdotusp.h */, RISCV::CV_SDOTUSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8266 { 9025 /* cv.sdotusp.sc.b */, RISCV::CV_SDOTUSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8267 { 9041 /* cv.sdotusp.sc.h */, RISCV::CV_SDOTUSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8268 { 9057 /* cv.sdotusp.sci.b */, RISCV::CV_SDOTUSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8269 { 9074 /* cv.sdotusp.sci.h */, RISCV::CV_SDOTUSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8270 { 9091 /* cv.sh */, RISCV::CV_SH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8271 { 9091 /* cv.sh */, RISCV::CV_SH_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8272 { 9091 /* cv.sh */, RISCV::CV_SH_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8273 { 9097 /* cv.shuffle.b */, RISCV::CV_SHUFFLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8274 { 9110 /* cv.shuffle.h */, RISCV::CV_SHUFFLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8275 { 9123 /* cv.shuffle.sci.h */, RISCV::CV_SHUFFLE_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8276 { 9140 /* cv.shuffle2.b */, RISCV::CV_SHUFFLE2_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8277 { 9154 /* cv.shuffle2.h */, RISCV::CV_SHUFFLE2_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8278 { 9168 /* cv.shufflei0.sci.b */, RISCV::CV_SHUFFLEI0_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8279 { 9187 /* cv.shufflei1.sci.b */, RISCV::CV_SHUFFLEI1_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8280 { 9206 /* cv.shufflei2.sci.b */, RISCV::CV_SHUFFLEI2_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8281 { 9225 /* cv.shufflei3.sci.b */, RISCV::CV_SHUFFLEI3_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8282 { 9244 /* cv.sle */, RISCV::CV_SLE, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8283 { 9251 /* cv.sleu */, RISCV::CV_SLEU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8284 { 9259 /* cv.sll.b */, RISCV::CV_SLL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8285 { 9268 /* cv.sll.h */, RISCV::CV_SLL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8286 { 9277 /* cv.sll.sc.b */, RISCV::CV_SLL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8287 { 9289 /* cv.sll.sc.h */, RISCV::CV_SLL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8288 { 9301 /* cv.sll.sci.b */, RISCV::CV_SLL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8289 { 9314 /* cv.sll.sci.h */, RISCV::CV_SLL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8290 { 9327 /* cv.sra.b */, RISCV::CV_SRA_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8291 { 9336 /* cv.sra.h */, RISCV::CV_SRA_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8292 { 9345 /* cv.sra.sc.b */, RISCV::CV_SRA_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8293 { 9357 /* cv.sra.sc.h */, RISCV::CV_SRA_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8294 { 9369 /* cv.sra.sci.b */, RISCV::CV_SRA_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8295 { 9382 /* cv.sra.sci.h */, RISCV::CV_SRA_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8296 { 9395 /* cv.srl.b */, RISCV::CV_SRL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8297 { 9404 /* cv.srl.h */, RISCV::CV_SRL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8298 { 9413 /* cv.srl.sc.b */, RISCV::CV_SRL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8299 { 9425 /* cv.srl.sc.h */, RISCV::CV_SRL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8300 { 9437 /* cv.srl.sci.b */, RISCV::CV_SRL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8301 { 9450 /* cv.srl.sci.h */, RISCV::CV_SRL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8302 { 9463 /* cv.sub.b */, RISCV::CV_SUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8303 { 9472 /* cv.sub.div2 */, RISCV::CV_SUB_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8304 { 9484 /* cv.sub.div4 */, RISCV::CV_SUB_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8305 { 9496 /* cv.sub.div8 */, RISCV::CV_SUB_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8306 { 9508 /* cv.sub.h */, RISCV::CV_SUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8307 { 9517 /* cv.sub.sc.b */, RISCV::CV_SUB_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8308 { 9529 /* cv.sub.sc.h */, RISCV::CV_SUB_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8309 { 9541 /* cv.sub.sci.b */, RISCV::CV_SUB_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8310 { 9554 /* cv.sub.sci.h */, RISCV::CV_SUB_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8311 { 9567 /* cv.subn */, RISCV::CV_SUBN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8312 { 9575 /* cv.subnr */, RISCV::CV_SUBNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8313 { 9584 /* cv.subrn */, RISCV::CV_SUBRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8314 { 9593 /* cv.subrnr */, RISCV::CV_SUBRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8315 { 9603 /* cv.subrotmj */, RISCV::CV_SUBROTMJ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8316 { 9615 /* cv.subrotmj.div2 */, RISCV::CV_SUBROTMJ_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8317 { 9632 /* cv.subrotmj.div4 */, RISCV::CV_SUBROTMJ_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8318 { 9649 /* cv.subrotmj.div8 */, RISCV::CV_SUBROTMJ_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8319 { 9666 /* cv.subun */, RISCV::CV_SUBUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8320 { 9675 /* cv.subunr */, RISCV::CV_SUBUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8321 { 9685 /* cv.suburn */, RISCV::CV_SUBURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8322 { 9695 /* cv.suburnr */, RISCV::CV_SUBURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8323 { 9706 /* cv.sw */, RISCV::CV_SW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8324 { 9706 /* cv.sw */, RISCV::CV_SW_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8325 { 9706 /* cv.sw */, RISCV::CV_SW_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8326 { 9712 /* cv.xor.b */, RISCV::CV_XOR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8327 { 9721 /* cv.xor.h */, RISCV::CV_XOR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8328 { 9730 /* cv.xor.sc.b */, RISCV::CV_XOR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8329 { 9742 /* cv.xor.sc.h */, RISCV::CV_XOR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8330 { 9754 /* cv.xor.sci.b */, RISCV::CV_XOR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8331 { 9767 /* cv.xor.sci.h */, RISCV::CV_XOR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8332 { 9780 /* czero.eqz */, RISCV::CZERO_EQZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8333 { 9790 /* czero.nez */, RISCV::CZERO_NEZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8334 { 9800 /* div */, RISCV::DIV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8335 { 9804 /* divu */, RISCV::DIVU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8336 { 9809 /* divuw */, RISCV::DIVUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8337 { 9815 /* divw */, RISCV::DIVW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8338 { 9820 /* dret */, RISCV::DRET, Convert_NoOperands, AMFBS_None, { }, },
8339 { 9825 /* ebreak */, RISCV::EBREAK, Convert_NoOperands, AMFBS_None, { }, },
8340 { 9832 /* ecall */, RISCV::ECALL, Convert_NoOperands, AMFBS_None, { }, },
8341 { 9838 /* fabs.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8342 { 9838 /* fabs.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8343 { 9838 /* fabs.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8344 { 9845 /* fabs.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8345 { 9845 /* fabs.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8346 { 9852 /* fabs.q */, RISCV::FSGNJX_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8347 { 9859 /* fabs.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8348 { 9859 /* fabs.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8349 { 9866 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8350 { 9866 /* fadd.d */, RISCV::FADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8351 { 9866 /* fadd.d */, RISCV::FADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8352 { 9873 /* fadd.h */, RISCV::FADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8353 { 9873 /* fadd.h */, RISCV::FADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8354 { 9880 /* fadd.q */, RISCV::FADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8355 { 9887 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8356 { 9887 /* fadd.s */, RISCV::FADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8357 { 9894 /* fclass.d */, RISCV::FCLASS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, },
8358 { 9894 /* fclass.d */, RISCV::FCLASS_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, },
8359 { 9894 /* fclass.d */, RISCV::FCLASS_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR }, },
8360 { 9903 /* fclass.h */, RISCV::FCLASS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16 }, },
8361 { 9903 /* fclass.h */, RISCV::FCLASS_H_INX, Convert__Reg1_0__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16 }, },
8362 { 9912 /* fclass.q */, RISCV::FCLASS_Q, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128 }, },
8363 { 9921 /* fclass.s */, RISCV::FCLASS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
8364 { 9921 /* fclass.s */, RISCV::FCLASS_S_INX, Convert__Reg1_0__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32 }, },
8365 { 9930 /* fcvt.bf16.s */, RISCV::FCVT_BF16_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
8366 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR64, MCK_FPR16, MCK_FRMArgLegacy }, },
8367 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8368 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8369 { 9951 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
8370 { 9951 /* fcvt.d.l */, RISCV::FCVT_D_L_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
8371 { 9960 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
8372 { 9960 /* fcvt.d.lu */, RISCV::FCVT_D_LU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
8373 { 9970 /* fcvt.d.q */, RISCV::FCVT_D_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR64, MCK_FPR128, MCK_FRMArg }, },
8374 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR32, MCK_FRMArgLegacy }, },
8375 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
8376 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
8377 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
8378 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8379 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8380 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
8381 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8382 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8383 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR16, MCK_FPR64, MCK_FRMArg }, },
8384 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D_INX, Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8385 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D_IN32X, Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR16, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8386 { 10016 /* fcvt.h.l */, RISCV::FCVT_H_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8387 { 10016 /* fcvt.h.l */, RISCV::FCVT_H_L_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8388 { 10025 /* fcvt.h.lu */, RISCV::FCVT_H_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8389 { 10025 /* fcvt.h.lu */, RISCV::FCVT_H_LU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8390 { 10035 /* fcvt.h.s */, RISCV::FCVT_H_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
8391 { 10035 /* fcvt.h.s */, RISCV::FCVT_H_S_INX, Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR16, MCK_GPRAsFPR32, MCK_FRMArg }, },
8392 { 10044 /* fcvt.h.w */, RISCV::FCVT_H_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8393 { 10044 /* fcvt.h.w */, RISCV::FCVT_H_W_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8394 { 10053 /* fcvt.h.wu */, RISCV::FCVT_H_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8395 { 10053 /* fcvt.h.wu */, RISCV::FCVT_H_WU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8396 { 10063 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8397 { 10063 /* fcvt.l.d */, RISCV::FCVT_L_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8398 { 10072 /* fcvt.l.h */, RISCV::FCVT_L_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8399 { 10072 /* fcvt.l.h */, RISCV::FCVT_L_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8400 { 10081 /* fcvt.l.q */, RISCV::FCVT_L_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8401 { 10090 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8402 { 10090 /* fcvt.l.s */, RISCV::FCVT_L_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8403 { 10099 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8404 { 10099 /* fcvt.lu.d */, RISCV::FCVT_LU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8405 { 10109 /* fcvt.lu.h */, RISCV::FCVT_LU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8406 { 10109 /* fcvt.lu.h */, RISCV::FCVT_LU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8407 { 10119 /* fcvt.lu.q */, RISCV::FCVT_LU_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8408 { 10129 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8409 { 10129 /* fcvt.lu.s */, RISCV::FCVT_LU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8410 { 10139 /* fcvt.q.d */, RISCV::FCVT_Q_D, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR64, MCK_FRMArgLegacy }, },
8411 { 10148 /* fcvt.q.l */, RISCV::FCVT_Q_L, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8412 { 10157 /* fcvt.q.lu */, RISCV::FCVT_Q_LU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8413 { 10167 /* fcvt.q.s */, RISCV::FCVT_Q_S, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR32, MCK_FRMArgLegacy }, },
8414 { 10176 /* fcvt.q.w */, RISCV::FCVT_Q_W, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8415 { 10185 /* fcvt.q.wu */, RISCV::FCVT_Q_WU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8416 { 10195 /* fcvt.s.bf16 */, RISCV::FCVT_S_BF16, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
8417 { 10207 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64, MCK_FRMArg }, },
8418 { 10207 /* fcvt.s.d */, RISCV::FCVT_S_D_INX, Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8419 { 10207 /* fcvt.s.d */, RISCV::FCVT_S_D_IN32X, Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR32, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8420 { 10216 /* fcvt.s.h */, RISCV::FCVT_S_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
8421 { 10216 /* fcvt.s.h */, RISCV::FCVT_S_H_INX, Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR32, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8422 { 10225 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8423 { 10225 /* fcvt.s.l */, RISCV::FCVT_S_L_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8424 { 10234 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8425 { 10234 /* fcvt.s.lu */, RISCV::FCVT_S_LU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8426 { 10244 /* fcvt.s.q */, RISCV::FCVT_S_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR32, MCK_FPR128, MCK_FRMArg }, },
8427 { 10253 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8428 { 10253 /* fcvt.s.w */, RISCV::FCVT_S_W_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8429 { 10262 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8430 { 10262 /* fcvt.s.wu */, RISCV::FCVT_S_WU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8431 { 10272 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8432 { 10272 /* fcvt.w.d */, RISCV::FCVT_W_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8433 { 10272 /* fcvt.w.d */, RISCV::FCVT_W_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8434 { 10281 /* fcvt.w.h */, RISCV::FCVT_W_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8435 { 10281 /* fcvt.w.h */, RISCV::FCVT_W_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8436 { 10290 /* fcvt.w.q */, RISCV::FCVT_W_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8437 { 10299 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8438 { 10299 /* fcvt.w.s */, RISCV::FCVT_W_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8439 { 10308 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8440 { 10308 /* fcvt.wu.d */, RISCV::FCVT_WU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8441 { 10308 /* fcvt.wu.d */, RISCV::FCVT_WU_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8442 { 10318 /* fcvt.wu.h */, RISCV::FCVT_WU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8443 { 10318 /* fcvt.wu.h */, RISCV::FCVT_WU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8444 { 10328 /* fcvt.wu.q */, RISCV::FCVT_WU_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8445 { 10338 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8446 { 10338 /* fcvt.wu.s */, RISCV::FCVT_WU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8447 { 10348 /* fcvtmod.w.d */, RISCV::FCVTMOD_W_D, Convert__Reg1_0__Reg1_1__RTZArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_RTZArg }, },
8448 { 10360 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8449 { 10360 /* fdiv.d */, RISCV::FDIV_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8450 { 10360 /* fdiv.d */, RISCV::FDIV_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8451 { 10367 /* fdiv.h */, RISCV::FDIV_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8452 { 10367 /* fdiv.h */, RISCV::FDIV_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8453 { 10374 /* fdiv.q */, RISCV::FDIV_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8454 { 10381 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8455 { 10381 /* fdiv.s */, RISCV::FDIV_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8456 { 10388 /* fence */, RISCV::FENCE, Convert__imm_95_15__imm_95_15, AMFBS_None, { }, },
8457 { 10388 /* fence */, RISCV::FENCE, Convert__FenceArg1_0__FenceArg1_1, AMFBS_None, { MCK_FenceArg, MCK_FenceArg }, },
8458 { 10394 /* fence.i */, RISCV::FENCE_I, Convert_NoOperands, AMFBS_None, { }, },
8459 { 10402 /* fence.tso */, RISCV::FENCE_TSO, Convert_NoOperands, AMFBS_None, { }, },
8460 { 10412 /* feq.d */, RISCV::FEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8461 { 10412 /* feq.d */, RISCV::FEQ_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8462 { 10412 /* feq.d */, RISCV::FEQ_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8463 { 10418 /* feq.h */, RISCV::FEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8464 { 10418 /* feq.h */, RISCV::FEQ_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8465 { 10424 /* feq.q */, RISCV::FEQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8466 { 10430 /* feq.s */, RISCV::FEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8467 { 10430 /* feq.s */, RISCV::FEQ_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8468 { 10436 /* fge.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8469 { 10436 /* fge.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8470 { 10436 /* fge.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8471 { 10442 /* fge.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8472 { 10442 /* fge.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8473 { 10448 /* fge.q */, RISCV::FLE_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8474 { 10454 /* fge.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8475 { 10454 /* fge.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8476 { 10460 /* fgeq.d */, RISCV::FLEQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8477 { 10467 /* fgeq.h */, RISCV::FLEQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8478 { 10474 /* fgeq.q */, RISCV::FLEQ_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8479 { 10481 /* fgeq.s */, RISCV::FLEQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8480 { 10488 /* fgt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8481 { 10488 /* fgt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8482 { 10488 /* fgt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8483 { 10494 /* fgt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8484 { 10494 /* fgt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8485 { 10500 /* fgt.q */, RISCV::FLT_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8486 { 10506 /* fgt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8487 { 10506 /* fgt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8488 { 10512 /* fgtq.d */, RISCV::FLTQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8489 { 10519 /* fgtq.h */, RISCV::FLTQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8490 { 10526 /* fgtq.q */, RISCV::FLTQ_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8491 { 10533 /* fgtq.s */, RISCV::FLTQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8492 { 10540 /* fld */, RISCV::PseudoFLD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
8493 { 10540 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
8494 { 10540 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8495 { 10544 /* fle.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8496 { 10544 /* fle.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8497 { 10544 /* fle.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8498 { 10550 /* fle.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8499 { 10550 /* fle.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8500 { 10556 /* fle.q */, RISCV::FLE_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8501 { 10562 /* fle.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8502 { 10562 /* fle.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8503 { 10568 /* fleq.d */, RISCV::FLEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8504 { 10575 /* fleq.h */, RISCV::FLEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8505 { 10582 /* fleq.q */, RISCV::FLEQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8506 { 10589 /* fleq.s */, RISCV::FLEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8507 { 10596 /* flh */, RISCV::PseudoFLH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, },
8508 { 10596 /* flh */, RISCV::FLH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, },
8509 { 10596 /* flh */, RISCV::FLH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8510 { 10600 /* fli.d */, RISCV::FLI_D, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_LoadFPImm }, },
8511 { 10606 /* fli.h */, RISCV::FLI_H, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh, { MCK_FPR16, MCK_LoadFPImm }, },
8512 { 10612 /* fli.q */, RISCV::FLI_Q, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_LoadFPImm }, },
8513 { 10618 /* fli.s */, RISCV::FLI_S, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_LoadFPImm }, },
8514 { 10624 /* flq */, RISCV::PseudoFLQ, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_BareSymbol, MCK_GPR }, },
8515 { 10624 /* flq */, RISCV::FLQ, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtQ, { MCK_FPR128, MCK__40_, MCK_GPR, MCK__41_ }, },
8516 { 10624 /* flq */, RISCV::FLQ, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8517 { 10628 /* flt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8518 { 10628 /* flt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8519 { 10628 /* flt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8520 { 10634 /* flt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8521 { 10634 /* flt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8522 { 10640 /* flt.q */, RISCV::FLT_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8523 { 10646 /* flt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8524 { 10646 /* flt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8525 { 10652 /* fltq.d */, RISCV::FLTQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8526 { 10659 /* fltq.h */, RISCV::FLTQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8527 { 10666 /* fltq.q */, RISCV::FLTQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8528 { 10673 /* fltq.s */, RISCV::FLTQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8529 { 10680 /* flw */, RISCV::PseudoFLW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
8530 { 10680 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
8531 { 10680 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8532 { 10684 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8533 { 10684 /* fmadd.d */, RISCV::FMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8534 { 10684 /* fmadd.d */, RISCV::FMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8535 { 10692 /* fmadd.h */, RISCV::FMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8536 { 10692 /* fmadd.h */, RISCV::FMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8537 { 10700 /* fmadd.q */, RISCV::FMADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8538 { 10708 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8539 { 10708 /* fmadd.s */, RISCV::FMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8540 { 10716 /* fmax.d */, RISCV::FMAX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8541 { 10716 /* fmax.d */, RISCV::FMAX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8542 { 10716 /* fmax.d */, RISCV::FMAX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8543 { 10723 /* fmax.h */, RISCV::FMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8544 { 10723 /* fmax.h */, RISCV::FMAX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8545 { 10730 /* fmax.q */, RISCV::FMAX_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8546 { 10737 /* fmax.s */, RISCV::FMAX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8547 { 10737 /* fmax.s */, RISCV::FMAX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8548 { 10744 /* fmaxm.d */, RISCV::FMAXM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8549 { 10752 /* fmaxm.h */, RISCV::FMAXM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8550 { 10760 /* fmaxm.q */, RISCV::FMAXM_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8551 { 10768 /* fmaxm.s */, RISCV::FMAXM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8552 { 10776 /* fmin.d */, RISCV::FMIN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8553 { 10776 /* fmin.d */, RISCV::FMIN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8554 { 10776 /* fmin.d */, RISCV::FMIN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8555 { 10783 /* fmin.h */, RISCV::FMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8556 { 10783 /* fmin.h */, RISCV::FMIN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8557 { 10790 /* fmin.q */, RISCV::FMIN_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8558 { 10797 /* fmin.s */, RISCV::FMIN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8559 { 10797 /* fmin.s */, RISCV::FMIN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8560 { 10804 /* fminm.d */, RISCV::FMINM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8561 { 10812 /* fminm.h */, RISCV::FMINM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8562 { 10820 /* fminm.q */, RISCV::FMINM_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8563 { 10828 /* fminm.s */, RISCV::FMINM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8564 { 10836 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8565 { 10836 /* fmsub.d */, RISCV::FMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8566 { 10836 /* fmsub.d */, RISCV::FMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8567 { 10844 /* fmsub.h */, RISCV::FMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8568 { 10844 /* fmsub.h */, RISCV::FMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8569 { 10852 /* fmsub.q */, RISCV::FMSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8570 { 10860 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8571 { 10860 /* fmsub.s */, RISCV::FMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8572 { 10868 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8573 { 10868 /* fmul.d */, RISCV::FMUL_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8574 { 10868 /* fmul.d */, RISCV::FMUL_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8575 { 10875 /* fmul.h */, RISCV::FMUL_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8576 { 10875 /* fmul.h */, RISCV::FMUL_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8577 { 10882 /* fmul.q */, RISCV::FMUL_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8578 { 10889 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8579 { 10889 /* fmul.s */, RISCV::FMUL_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8580 { 10896 /* fmv.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8581 { 10896 /* fmv.d */, RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8582 { 10896 /* fmv.d */, RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8583 { 10902 /* fmv.d.x */, RISCV::FMV_D_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, },
8584 { 10910 /* fmv.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8585 { 10910 /* fmv.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8586 { 10916 /* fmv.h.x */, RISCV::FMV_H_X, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_GPR }, },
8587 { 10924 /* fmv.q */, RISCV::FSGNJ_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8588 { 10930 /* fmv.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8589 { 10930 /* fmv.s */, RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8590 { 10936 /* fmv.w.x */, RISCV::FMV_W_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, },
8591 { 10944 /* fmv.x.d */, RISCV::FMV_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, },
8592 { 10952 /* fmv.x.h */, RISCV::FMV_X_H, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_GPR, MCK_FPR16 }, },
8593 { 10960 /* fmv.x.w */, RISCV::FMV_X_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
8594 { 10968 /* fmvh.x.d */, RISCV::FMVH_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_GPR, MCK_FPR64 }, },
8595 { 10977 /* fmvh.x.q */, RISCV::FMVH_X_Q, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128 }, },
8596 { 10986 /* fmvp.d.x */, RISCV::FMVP_D_X, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
8597 { 10995 /* fmvp.q.x */, RISCV::FMVP_Q_X, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_GPR }, },
8598 { 11004 /* fneg.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8599 { 11004 /* fneg.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8600 { 11004 /* fneg.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8601 { 11011 /* fneg.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8602 { 11011 /* fneg.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8603 { 11018 /* fneg.q */, RISCV::FSGNJN_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8604 { 11025 /* fneg.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8605 { 11025 /* fneg.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8606 { 11032 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8607 { 11032 /* fnmadd.d */, RISCV::FNMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8608 { 11032 /* fnmadd.d */, RISCV::FNMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8609 { 11041 /* fnmadd.h */, RISCV::FNMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8610 { 11041 /* fnmadd.h */, RISCV::FNMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8611 { 11050 /* fnmadd.q */, RISCV::FNMADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8612 { 11059 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8613 { 11059 /* fnmadd.s */, RISCV::FNMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8614 { 11068 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8615 { 11068 /* fnmsub.d */, RISCV::FNMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8616 { 11068 /* fnmsub.d */, RISCV::FNMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8617 { 11077 /* fnmsub.h */, RISCV::FNMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8618 { 11077 /* fnmsub.h */, RISCV::FNMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8619 { 11086 /* fnmsub.q */, RISCV::FNMSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8620 { 11095 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8621 { 11095 /* fnmsub.s */, RISCV::FNMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8622 { 11104 /* frcsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8623 { 11110 /* frflags */, RISCV::CSRRS, Convert__Reg1_0__imm_95_1__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8624 { 11118 /* fround.d */, RISCV::FROUND_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8625 { 11127 /* fround.h */, RISCV::FROUND_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8626 { 11136 /* fround.q */, RISCV::FROUND_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8627 { 11145 /* fround.s */, RISCV::FROUND_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8628 { 11154 /* froundnx.d */, RISCV::FROUNDNX_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8629 { 11165 /* froundnx.h */, RISCV::FROUNDNX_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8630 { 11176 /* froundnx.q */, RISCV::FROUNDNX_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8631 { 11187 /* froundnx.s */, RISCV::FROUNDNX_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8632 { 11198 /* frrm */, RISCV::CSRRS, Convert__Reg1_0__imm_95_2__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8633 { 11203 /* fscsr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8634 { 11203 /* fscsr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
8635 { 11209 /* fsd */, RISCV::PseudoFSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
8636 { 11209 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
8637 { 11209 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8638 { 11213 /* fsflags */, RISCV::CSRRW, Convert__regX0__imm_95_1__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8639 { 11213 /* fsflags */, RISCV::CSRRW, Convert__Reg1_0__imm_95_1__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
8640 { 11221 /* fsflagsi */, RISCV::CSRRWI, Convert__regX0__imm_95_1__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
8641 { 11221 /* fsflagsi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_1__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
8642 { 11230 /* fsgnj.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8643 { 11230 /* fsgnj.d */, RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8644 { 11230 /* fsgnj.d */, RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8645 { 11238 /* fsgnj.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8646 { 11238 /* fsgnj.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8647 { 11246 /* fsgnj.q */, RISCV::FSGNJ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8648 { 11254 /* fsgnj.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8649 { 11254 /* fsgnj.s */, RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8650 { 11262 /* fsgnjn.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8651 { 11262 /* fsgnjn.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8652 { 11262 /* fsgnjn.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8653 { 11271 /* fsgnjn.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8654 { 11271 /* fsgnjn.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8655 { 11280 /* fsgnjn.q */, RISCV::FSGNJN_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8656 { 11289 /* fsgnjn.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8657 { 11289 /* fsgnjn.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8658 { 11298 /* fsgnjx.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8659 { 11298 /* fsgnjx.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8660 { 11298 /* fsgnjx.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8661 { 11307 /* fsgnjx.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8662 { 11307 /* fsgnjx.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8663 { 11316 /* fsgnjx.q */, RISCV::FSGNJX_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8664 { 11325 /* fsgnjx.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8665 { 11325 /* fsgnjx.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8666 { 11334 /* fsh */, RISCV::PseudoFSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, },
8667 { 11334 /* fsh */, RISCV::FSH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, },
8668 { 11334 /* fsh */, RISCV::FSH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8669 { 11338 /* fsq */, RISCV::PseudoFSQ, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_BareSymbol, MCK_GPR }, },
8670 { 11338 /* fsq */, RISCV::FSQ, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtQ, { MCK_FPR128, MCK__40_, MCK_GPR, MCK__41_ }, },
8671 { 11338 /* fsq */, RISCV::FSQ, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8672 { 11342 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8673 { 11342 /* fsqrt.d */, RISCV::FSQRT_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8674 { 11342 /* fsqrt.d */, RISCV::FSQRT_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8675 { 11350 /* fsqrt.h */, RISCV::FSQRT_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8676 { 11350 /* fsqrt.h */, RISCV::FSQRT_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8677 { 11358 /* fsqrt.q */, RISCV::FSQRT_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8678 { 11366 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8679 { 11366 /* fsqrt.s */, RISCV::FSQRT_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8680 { 11374 /* fsrm */, RISCV::CSRRW, Convert__regX0__imm_95_2__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8681 { 11374 /* fsrm */, RISCV::CSRRW, Convert__Reg1_0__imm_95_2__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
8682 { 11379 /* fsrmi */, RISCV::CSRRWI, Convert__regX0__imm_95_2__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
8683 { 11379 /* fsrmi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_2__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
8684 { 11385 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8685 { 11385 /* fsub.d */, RISCV::FSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8686 { 11385 /* fsub.d */, RISCV::FSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8687 { 11392 /* fsub.h */, RISCV::FSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8688 { 11392 /* fsub.h */, RISCV::FSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8689 { 11399 /* fsub.q */, RISCV::FSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8690 { 11406 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8691 { 11406 /* fsub.s */, RISCV::FSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8692 { 11413 /* fsw */, RISCV::PseudoFSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
8693 { 11413 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
8694 { 11413 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8695 { 11417 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__regX0__regX0, AMFBS_HasStdExtH, { }, },
8696 { 11417 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__regX0, AMFBS_HasStdExtH, { MCK_GPR }, },
8697 { 11417 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
8698 { 11429 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__regX0__regX0, AMFBS_HasStdExtH, { }, },
8699 { 11429 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__regX0, AMFBS_HasStdExtH, { MCK_GPR }, },
8700 { 11429 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
8701 { 11441 /* hinval.gvma */, RISCV::HINVAL_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
8702 { 11453 /* hinval.vvma */, RISCV::HINVAL_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
8703 { 11465 /* hlv.b */, RISCV::HLV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8704 { 11471 /* hlv.bu */, RISCV::HLV_BU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8705 { 11478 /* hlv.d */, RISCV::HLV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8706 { 11484 /* hlv.h */, RISCV::HLV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8707 { 11490 /* hlv.hu */, RISCV::HLV_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8708 { 11497 /* hlv.w */, RISCV::HLV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8709 { 11503 /* hlv.wu */, RISCV::HLV_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8710 { 11510 /* hlvx.hu */, RISCV::HLVX_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8711 { 11518 /* hlvx.wu */, RISCV::HLVX_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8712 { 11526 /* hsv.b */, RISCV::HSV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8713 { 11532 /* hsv.d */, RISCV::HSV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8714 { 11538 /* hsv.h */, RISCV::HSV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8715 { 11544 /* hsv.w */, RISCV::HSV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8716 { 11550 /* j */, RISCV::JAL, Convert__regX0__BareSImm21Lsb01_0, AMFBS_None, { MCK_BareSImm21Lsb0 }, },
8717 { 11552 /* jal */, RISCV::JAL, Convert__regX1__BareSImm21Lsb01_0, AMFBS_None, { MCK_BareSImm21Lsb0 }, },
8718 { 11552 /* jal */, RISCV::JAL, Convert__Reg1_0__BareSImm21Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm21Lsb0 }, },
8719 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
8720 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8721 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
8722 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_1__imm_95_0, AMFBS_None, { MCK__40_, MCK_GPR, MCK__41_ }, },
8723 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
8724 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8725 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_2__SImm12LO1_0, AMFBS_None, { MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8726 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8727 { 11556 /* jalr */, RISCV::PseudoTLSDESCCall, Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_, MCK_TLSDESCCallSymbol }, },
8728 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
8729 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
8730 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_1__imm_95_0, AMFBS_None, { MCK__40_, MCK_GPR, MCK__41_ }, },
8731 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_2__SImm12LO1_0, AMFBS_None, { MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8732 { 11564 /* jump */, RISCV::PseudoJump, Convert__Reg1_1__PseudoJumpSymbol1_0, AMFBS_None, { MCK_PseudoJumpSymbol, MCK_GPR }, },
8733 { 11569 /* la */, RISCV::PseudoLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8734 { 11569 /* la */, RISCV::PseudoLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
8735 { 11572 /* la.tls.gd */, RISCV::PseudoLA_TLS_GD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8736 { 11582 /* la.tls.ie */, RISCV::PseudoLA_TLS_IE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8737 { 11592 /* lb */, RISCV::PseudoLB, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8738 { 11592 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8739 { 11592 /* lb */, RISCV::PseudoQCAccessLB, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8740 { 11592 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8741 { 11592 /* lb */, RISCV::PseudoQCAccessLB, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8742 { 11595 /* lb.aq */, RISCV::LB_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8743 { 11601 /* lb.aqrl */, RISCV::LB_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8744 { 11609 /* lbu */, RISCV::PseudoLBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8745 { 11609 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8746 { 11609 /* lbu */, RISCV::PseudoQCAccessLB, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8747 { 11609 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8748 { 11609 /* lbu */, RISCV::PseudoQCAccessLBU, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8749 { 11613 /* ld */, RISCV::PseudoLD, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
8750 { 11613 /* ld */, RISCV::PseudoLD_RV32, Convert__GPRPairRV321_0__BareSymbol1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_BareSymbol }, },
8751 { 11613 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8752 { 11613 /* ld */, RISCV::LD_RV32, Convert__GPRPairRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK__40_, MCK_GPR, MCK__41_ }, },
8753 { 11613 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8754 { 11613 /* ld */, RISCV::LD_RV32, Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8755 { 11616 /* ld.aq */, RISCV::LD_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8756 { 11622 /* ld.aqrl */, RISCV::LD_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8757 { 11630 /* lga */, RISCV::PseudoLGA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8758 { 11634 /* lh */, RISCV::PseudoLH, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8759 { 11634 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8760 { 11634 /* lh */, RISCV::PseudoQCAccessLH, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8761 { 11634 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8762 { 11634 /* lh */, RISCV::PseudoQCAccessLH, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8763 { 11637 /* lh.aq */, RISCV::LH_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8764 { 11643 /* lh.aqrl */, RISCV::LH_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8765 { 11651 /* lhu */, RISCV::PseudoLHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8766 { 11651 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8767 { 11651 /* lhu */, RISCV::PseudoQCAccessLHU, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8768 { 11651 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8769 { 11651 /* lhu */, RISCV::PseudoQCAccessLHU, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8770 { 11655 /* li */, RISCV::ADDI, Convert__Reg1_0__regX0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
8771 { 11655 /* li */, RISCV::PseudoLI, Convert__Reg1_0__ImmXLenLI1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI }, },
8772 { 11658 /* lla */, RISCV::PseudoLLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8773 { 11658 /* lla */, RISCV::PseudoLLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
8774 { 11662 /* lpad */, RISCV::AUIPC, Convert__regX0__UImm201_0, AMFBS_None, { MCK_UImm20 }, },
8775 { 11667 /* lr.d */, RISCV::LR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8776 { 11672 /* lr.d.aq */, RISCV::LR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8777 { 11680 /* lr.d.aqrl */, RISCV::LR_D_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8778 { 11690 /* lr.d.rl */, RISCV::LR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8779 { 11698 /* lr.w */, RISCV::LR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8780 { 11703 /* lr.w.aq */, RISCV::LR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8781 { 11711 /* lr.w.aqrl */, RISCV::LR_W_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8782 { 11721 /* lr.w.rl */, RISCV::LR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8783 { 11729 /* lui */, RISCV::LUI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_None, { MCK_GPR, MCK_UImm20LUI }, },
8784 { 11733 /* lw */, RISCV::PseudoLW, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8785 { 11733 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8786 { 11733 /* lw */, RISCV::PseudoQCAccessLW, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8787 { 11733 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8788 { 11733 /* lw */, RISCV::PseudoQCAccessLW, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8789 { 11736 /* lw.aq */, RISCV::LW_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8790 { 11742 /* lw.aqrl */, RISCV::LW_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8791 { 11750 /* lwu */, RISCV::PseudoLWU, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
8792 { 11750 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8793 { 11750 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8794 { 11754 /* macc.h00 */, RISCV::MACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8795 { 11763 /* macc.h01 */, RISCV::MACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8796 { 11772 /* macc.h11 */, RISCV::MACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8797 { 11781 /* macc.w00 */, RISCV::MACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8798 { 11790 /* macc.w01 */, RISCV::MACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8799 { 11799 /* macc.w11 */, RISCV::MACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8800 { 11808 /* maccsu.h00 */, RISCV::MACCSU_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8801 { 11819 /* maccsu.h11 */, RISCV::MACCSU_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8802 { 11830 /* maccsu.w00 */, RISCV::MACCSU_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8803 { 11841 /* maccsu.w11 */, RISCV::MACCSU_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8804 { 11852 /* maccu.h00 */, RISCV::MACCU_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8805 { 11862 /* maccu.h01 */, RISCV::MACCU_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8806 { 11872 /* maccu.h11 */, RISCV::MACCU_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8807 { 11882 /* maccu.w00 */, RISCV::MACCU_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8808 { 11892 /* maccu.w01 */, RISCV::MACCU_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8809 { 11902 /* maccu.w11 */, RISCV::MACCU_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8810 { 11912 /* max */, RISCV::MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8811 { 11916 /* maxu */, RISCV::MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8812 { 11921 /* merge */, RISCV::MERGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8813 { 11927 /* mhacc */, RISCV::MHACC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8814 { 11933 /* mhacc.h0 */, RISCV::MHACC_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8815 { 11942 /* mhacc.h1 */, RISCV::MHACC_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8816 { 11951 /* mhaccsu */, RISCV::MHACCSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8817 { 11959 /* mhaccsu.h0 */, RISCV::MHACCSU_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8818 { 11970 /* mhaccsu.h1 */, RISCV::MHACCSU_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8819 { 11981 /* mhaccu */, RISCV::MHACCU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8820 { 11988 /* mhracc */, RISCV::MHRACC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8821 { 11995 /* mhraccsu */, RISCV::MHRACCSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8822 { 12004 /* mhraccu */, RISCV::MHRACCU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8823 { 12012 /* min */, RISCV::MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8824 { 12016 /* minu */, RISCV::MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8825 { 12021 /* mips.ccmov */, RISCV::MIPS_CCMOV, Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3, AMFBS_HasVendorXMIPSCMov, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8826 { 12032 /* mips.ehb */, RISCV::MIPS_EHB, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
8827 { 12041 /* mips.ihb */, RISCV::MIPS_IHB, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
8828 { 12050 /* mips.ldp */, RISCV::MIPS_LDP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb000, MCK__40_, MCK_GPR, MCK__41_ }, },
8829 { 12059 /* mips.lwp */, RISCV::MIPS_LWP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
8830 { 12068 /* mips.pause */, RISCV::MIPS_PAUSE, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
8831 { 12079 /* mips.pref */, RISCV::MIPS_PREF, Convert__Reg1_3__UImm91_1__UImm51_0, AMFBS_HasVendorXMIPSCBOP, { MCK_UImm5, MCK_UImm9, MCK__40_, MCK_GPR, MCK__41_ }, },
8832 { 12089 /* mips.sdp */, RISCV::MIPS_SDP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb000, MCK__40_, MCK_GPR, MCK__41_ }, },
8833 { 12098 /* mips.swp */, RISCV::MIPS_SWP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
8834 { 12107 /* mnret */, RISCV::MNRET, Convert_NoOperands, AMFBS_HasStdExtSmrnmi, { }, },
8835 { 12113 /* mop.r.0 */, RISCV::MOP_R_0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8836 { 12121 /* mop.r.1 */, RISCV::MOP_R_1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8837 { 12129 /* mop.r.10 */, RISCV::MOP_R_10, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8838 { 12138 /* mop.r.11 */, RISCV::MOP_R_11, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8839 { 12147 /* mop.r.12 */, RISCV::MOP_R_12, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8840 { 12156 /* mop.r.13 */, RISCV::MOP_R_13, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8841 { 12165 /* mop.r.14 */, RISCV::MOP_R_14, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8842 { 12174 /* mop.r.15 */, RISCV::MOP_R_15, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8843 { 12183 /* mop.r.16 */, RISCV::MOP_R_16, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8844 { 12192 /* mop.r.17 */, RISCV::MOP_R_17, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8845 { 12201 /* mop.r.18 */, RISCV::MOP_R_18, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8846 { 12210 /* mop.r.19 */, RISCV::MOP_R_19, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8847 { 12219 /* mop.r.2 */, RISCV::MOP_R_2, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8848 { 12227 /* mop.r.20 */, RISCV::MOP_R_20, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8849 { 12236 /* mop.r.21 */, RISCV::MOP_R_21, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8850 { 12245 /* mop.r.22 */, RISCV::MOP_R_22, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8851 { 12254 /* mop.r.23 */, RISCV::MOP_R_23, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8852 { 12263 /* mop.r.24 */, RISCV::MOP_R_24, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8853 { 12272 /* mop.r.25 */, RISCV::MOP_R_25, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8854 { 12281 /* mop.r.26 */, RISCV::MOP_R_26, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8855 { 12290 /* mop.r.27 */, RISCV::MOP_R_27, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8856 { 12299 /* mop.r.28 */, RISCV::MOP_R_28, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8857 { 12308 /* mop.r.29 */, RISCV::MOP_R_29, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8858 { 12317 /* mop.r.3 */, RISCV::MOP_R_3, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8859 { 12325 /* mop.r.30 */, RISCV::MOP_R_30, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8860 { 12334 /* mop.r.31 */, RISCV::MOP_R_31, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8861 { 12343 /* mop.r.4 */, RISCV::MOP_R_4, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8862 { 12351 /* mop.r.5 */, RISCV::MOP_R_5, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8863 { 12359 /* mop.r.6 */, RISCV::MOP_R_6, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8864 { 12367 /* mop.r.7 */, RISCV::MOP_R_7, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8865 { 12375 /* mop.r.8 */, RISCV::MOP_R_8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8866 { 12383 /* mop.r.9 */, RISCV::MOP_R_9, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8867 { 12391 /* mop.rr.0 */, RISCV::MOP_RR_0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8868 { 12400 /* mop.rr.1 */, RISCV::MOP_RR_1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8869 { 12409 /* mop.rr.2 */, RISCV::MOP_RR_2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8870 { 12418 /* mop.rr.3 */, RISCV::MOP_RR_3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8871 { 12427 /* mop.rr.4 */, RISCV::MOP_RR_4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8872 { 12436 /* mop.rr.5 */, RISCV::MOP_RR_5, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8873 { 12445 /* mop.rr.6 */, RISCV::MOP_RR_6, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8874 { 12454 /* mop.rr.7 */, RISCV::MOP_RR_7, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8875 { 12463 /* mqacc.h00 */, RISCV::MQACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8876 { 12473 /* mqacc.h01 */, RISCV::MQACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8877 { 12483 /* mqacc.h11 */, RISCV::MQACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8878 { 12493 /* mqacc.w00 */, RISCV::MQACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8879 { 12503 /* mqacc.w01 */, RISCV::MQACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8880 { 12513 /* mqacc.w11 */, RISCV::MQACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8881 { 12523 /* mqracc.h00 */, RISCV::MQRACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8882 { 12534 /* mqracc.h01 */, RISCV::MQRACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8883 { 12545 /* mqracc.h11 */, RISCV::MQRACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8884 { 12556 /* mqracc.w00 */, RISCV::MQRACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8885 { 12567 /* mqracc.w01 */, RISCV::MQRACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8886 { 12578 /* mqracc.w11 */, RISCV::MQRACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8887 { 12589 /* mqrwacc */, RISCV::MQRWACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8888 { 12597 /* mqwacc */, RISCV::MQWACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8889 { 12604 /* mret */, RISCV::MRET, Convert_NoOperands, AMFBS_None, { }, },
8890 { 12609 /* mseq */, RISCV::MSEQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8891 { 12614 /* mseqz */, RISCV::MSEQ, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
8892 { 12620 /* msgt */, RISCV::MSLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8893 { 12625 /* msgtu */, RISCV::MSLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8894 { 12631 /* msgtz */, RISCV::MSLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
8895 { 12637 /* mslt */, RISCV::MSLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8896 { 12642 /* msltu */, RISCV::MSLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8897 { 12648 /* msltz */, RISCV::MSLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
8898 { 12654 /* msnez */, RISCV::MSLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
8899 { 12660 /* mul */, RISCV::MUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8900 { 12664 /* mul.h00 */, RISCV::MUL_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8901 { 12672 /* mul.h01 */, RISCV::MUL_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8902 { 12680 /* mul.h11 */, RISCV::MUL_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8903 { 12688 /* mul.w00 */, RISCV::MUL_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8904 { 12696 /* mul.w01 */, RISCV::MUL_W01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8905 { 12704 /* mul.w11 */, RISCV::MUL_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8906 { 12712 /* mulh */, RISCV::MULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8907 { 12717 /* mulh.h0 */, RISCV::MULH_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8908 { 12725 /* mulh.h1 */, RISCV::MULH_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8909 { 12733 /* mulhr */, RISCV::MULHR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8910 { 12739 /* mulhrsu */, RISCV::MULHRSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8911 { 12747 /* mulhru */, RISCV::MULHRU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8912 { 12754 /* mulhsu */, RISCV::MULHSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8913 { 12761 /* mulhsu.h0 */, RISCV::MULHSU_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8914 { 12771 /* mulhsu.h1 */, RISCV::MULHSU_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8915 { 12781 /* mulhu */, RISCV::MULHU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8916 { 12787 /* mulq */, RISCV::MULQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8917 { 12792 /* mulqr */, RISCV::MULQR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8918 { 12798 /* mulsu.h00 */, RISCV::MULSU_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8919 { 12808 /* mulsu.h11 */, RISCV::MULSU_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8920 { 12818 /* mulsu.w00 */, RISCV::MULSU_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8921 { 12828 /* mulsu.w11 */, RISCV::MULSU_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8922 { 12838 /* mulu.h00 */, RISCV::MULU_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8923 { 12847 /* mulu.h01 */, RISCV::MULU_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8924 { 12856 /* mulu.h11 */, RISCV::MULU_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8925 { 12865 /* mulu.w00 */, RISCV::MULU_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8926 { 12874 /* mulu.w01 */, RISCV::MULU_W01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8927 { 12883 /* mulu.w11 */, RISCV::MULU_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8928 { 12892 /* mulw */, RISCV::MULW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8929 { 12897 /* mv */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8930 { 12900 /* mvd */, RISCV::PADD_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8931 { 12904 /* mvm */, RISCV::MVM, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8932 { 12908 /* mvmn */, RISCV::MVMN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8933 { 12913 /* nclip */, RISCV::NCLIP, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8934 { 12919 /* nclipi */, RISCV::NCLIPI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8935 { 12926 /* nclipiu */, RISCV::NCLIPIU, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8936 { 12934 /* nclipr */, RISCV::NCLIPR, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8937 { 12941 /* nclipri */, RISCV::NCLIPRI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8938 { 12949 /* nclipriu */, RISCV::NCLIPRIU, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8939 { 12958 /* nclipru */, RISCV::NCLIPRU, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8940 { 12966 /* nclipu */, RISCV::NCLIPU, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8941 { 12973 /* nds.addigp */, RISCV::NDS_ADDIGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8942 { 12984 /* nds.bbc */, RISCV::NDS_BBC, Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImmLog2XLen, MCK_BareSImm11Lsb0 }, },
8943 { 12992 /* nds.bbs */, RISCV::NDS_BBS, Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImmLog2XLen, MCK_BareSImm11Lsb0 }, },
8944 { 13000 /* nds.beqc */, RISCV::NDS_BEQC, Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImm7, MCK_BareSImm11Lsb0 }, },
8945 { 13009 /* nds.bfos */, RISCV::NDS_BFOS, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
8946 { 13018 /* nds.bfoz */, RISCV::NDS_BFOZ, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
8947 { 13027 /* nds.bnec */, RISCV::NDS_BNEC, Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImm7, MCK_BareSImm11Lsb0 }, },
8948 { 13036 /* nds.fcvt.bf16.s */, RISCV::NDS_FCVT_BF16_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesBFHCvt, { MCK_FPR16, MCK_FPR32 }, },
8949 { 13052 /* nds.fcvt.s.bf16 */, RISCV::NDS_FCVT_S_BF16, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesBFHCvt, { MCK_FPR32, MCK_FPR16 }, },
8950 { 13068 /* nds.ffb */, RISCV::NDS_FFB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8951 { 13076 /* nds.ffmism */, RISCV::NDS_FFMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8952 { 13087 /* nds.ffzmism */, RISCV::NDS_FFZMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8953 { 13099 /* nds.flmism */, RISCV::NDS_FLMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8954 { 13110 /* nds.lbgp */, RISCV::NDS_LBGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8955 { 13119 /* nds.lbugp */, RISCV::NDS_LBUGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8956 { 13129 /* nds.ldgp */, RISCV::NDS_LDGP, Convert__Reg1_0__SImm20Lsb0001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm20Lsb000 }, },
8957 { 13138 /* nds.lea.b.ze */, RISCV::NDS_LEA_B_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8958 { 13151 /* nds.lea.d */, RISCV::NDS_LEA_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8959 { 13161 /* nds.lea.d.ze */, RISCV::NDS_LEA_D_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8960 { 13174 /* nds.lea.h */, RISCV::NDS_LEA_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8961 { 13184 /* nds.lea.h.ze */, RISCV::NDS_LEA_H_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8962 { 13197 /* nds.lea.w */, RISCV::NDS_LEA_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8963 { 13207 /* nds.lea.w.ze */, RISCV::NDS_LEA_W_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8964 { 13220 /* nds.lhgp */, RISCV::NDS_LHGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
8965 { 13229 /* nds.lhugp */, RISCV::NDS_LHUGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
8966 { 13239 /* nds.lwgp */, RISCV::NDS_LWGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm19Lsb00 }, },
8967 { 13248 /* nds.lwugp */, RISCV::NDS_LWUGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm19Lsb00 }, },
8968 { 13258 /* nds.sbgp */, RISCV::NDS_SBGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8969 { 13267 /* nds.sdgp */, RISCV::NDS_SDGP, Convert__Reg1_0__SImm20Lsb0001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm20Lsb000 }, },
8970 { 13276 /* nds.shgp */, RISCV::NDS_SHGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
8971 { 13285 /* nds.swgp */, RISCV::NDS_SWGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm19Lsb00 }, },
8972 { 13294 /* nds.vd4dots.vv */, RISCV::NDS_VD4DOTS_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8973 { 13309 /* nds.vd4dotsu.vv */, RISCV::NDS_VD4DOTSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8974 { 13325 /* nds.vd4dotu.vv */, RISCV::NDS_VD4DOTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8975 { 13340 /* nds.vfncvt.bf16.s */, RISCV::NDS_VFNCVT_BF16_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesVBFHCvt, { MCK_VR, MCK_VR }, },
8976 { 13358 /* nds.vfpmadb.vf */, RISCV::NDS_VFPMADB_VF, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVPackFPH, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8977 { 13373 /* nds.vfpmadt.vf */, RISCV::NDS_VFPMADT_VF, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVPackFPH, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8978 { 13388 /* nds.vfwcvt.f.b.v */, RISCV::NDS_VFWCVT_F_B, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8979 { 13405 /* nds.vfwcvt.f.bu.v */, RISCV::NDS_VFWCVT_F_BU, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8980 { 13423 /* nds.vfwcvt.f.n.v */, RISCV::NDS_VFWCVT_F_N, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8981 { 13440 /* nds.vfwcvt.f.nu.v */, RISCV::NDS_VFWCVT_F_NU, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8982 { 13458 /* nds.vfwcvt.s.bf16 */, RISCV::NDS_VFWCVT_S_BF16, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesVBFHCvt, { MCK_VR, MCK_VR }, },
8983 { 13476 /* nds.vle4.v */, RISCV::NDS_VLE4_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
8984 { 13487 /* nds.vln8.v */, RISCV::NDS_VLN8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntLoad, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
8985 { 13498 /* nds.vlnu8.v */, RISCV::NDS_VLNU8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntLoad, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
8986 { 13510 /* neg */, RISCV::SUB, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8987 { 13514 /* negd */, RISCV::SUBD, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8988 { 13519 /* negw */, RISCV::SUBW, Convert__Reg1_0__regX0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
8989 { 13524 /* nop */, RISCV::ADDI, Convert__regX0__regX0__imm_95_0, AMFBS_None, { }, },
8990 { 13528 /* not */, RISCV::XORI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8991 { 13532 /* nsra */, RISCV::NSRA, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8992 { 13537 /* nsrai */, RISCV::NSRAI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8993 { 13543 /* nsrar */, RISCV::NSRAR, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8994 { 13549 /* nsrari */, RISCV::NSRARI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8995 { 13556 /* nsrl */, RISCV::NSRL, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8996 { 13561 /* nsrli */, RISCV::NSRLI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8997 { 13567 /* ntl.all */, RISCV::ADD, Convert__regX0__regX0__regX5, AMFBS_None, { }, },
8998 { 13575 /* ntl.p1 */, RISCV::ADD, Convert__regX0__regX0__regX2, AMFBS_None, { }, },
8999 { 13582 /* ntl.pall */, RISCV::ADD, Convert__regX0__regX0__regX3, AMFBS_None, { }, },
9000 { 13591 /* ntl.s1 */, RISCV::ADD, Convert__regX0__regX0__regX4, AMFBS_None, { }, },
9001 { 13598 /* or */, RISCV::OR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9002 { 13598 /* or */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9003 { 13601 /* orc.b */, RISCV::ORC_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
9004 { 13607 /* ori */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9005 { 13611 /* orn */, RISCV::ORN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9006 { 13615 /* paadd.b */, RISCV::PAADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9007 { 13623 /* paadd.db */, RISCV::PAADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9008 { 13632 /* paadd.dh */, RISCV::PAADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9009 { 13641 /* paadd.dw */, RISCV::PAADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9010 { 13650 /* paadd.h */, RISCV::PAADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9011 { 13658 /* paadd.w */, RISCV::PAADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9012 { 13666 /* paaddu.b */, RISCV::PAADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9013 { 13675 /* paaddu.db */, RISCV::PAADDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9014 { 13685 /* paaddu.dh */, RISCV::PAADDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9015 { 13695 /* paaddu.dw */, RISCV::PAADDU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9016 { 13705 /* paaddu.h */, RISCV::PAADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9017 { 13714 /* paaddu.w */, RISCV::PAADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9018 { 13723 /* paas.dhx */, RISCV::PAAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9019 { 13732 /* paas.hx */, RISCV::PAAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9020 { 13740 /* paas.wx */, RISCV::PAAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9021 { 13748 /* pabd.b */, RISCV::PABD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9022 { 13755 /* pabd.db */, RISCV::PABD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9023 { 13763 /* pabd.dh */, RISCV::PABD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9024 { 13771 /* pabd.h */, RISCV::PABD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9025 { 13778 /* pabdsumau.b */, RISCV::PABDSUMAU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9026 { 13790 /* pabdsumu.b */, RISCV::PABDSUMU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9027 { 13801 /* pabdu.b */, RISCV::PABDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9028 { 13809 /* pabdu.db */, RISCV::PABDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9029 { 13818 /* pabdu.dh */, RISCV::PABDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9030 { 13827 /* pabdu.h */, RISCV::PABDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9031 { 13835 /* pabs.b */, RISCV::PABD_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9032 { 13842 /* pabs.db */, RISCV::PABD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9033 { 13850 /* pabs.dh */, RISCV::PABD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9034 { 13858 /* pabs.h */, RISCV::PABD_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9035 { 13865 /* pack */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkbOrP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9036 { 13870 /* packh */, RISCV::PACKH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9037 { 13876 /* packw */, RISCV::PACKW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9038 { 13882 /* packy */, RISCV::PACKY, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
9039 { 13888 /* padd.b */, RISCV::PADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9040 { 13895 /* padd.bs */, RISCV::PADD_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9041 { 13903 /* padd.db */, RISCV::PADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9042 { 13911 /* padd.dbs */, RISCV::PADD_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9043 { 13920 /* padd.dh */, RISCV::PADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9044 { 13928 /* padd.dhs */, RISCV::PADD_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9045 { 13937 /* padd.dw */, RISCV::PADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9046 { 13945 /* padd.dws */, RISCV::PADD_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9047 { 13954 /* padd.h */, RISCV::PADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9048 { 13961 /* padd.hs */, RISCV::PADD_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9049 { 13969 /* padd.w */, RISCV::PADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9050 { 13976 /* padd.ws */, RISCV::PADD_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9051 { 13984 /* pas.dhx */, RISCV::PAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9052 { 13992 /* pas.hx */, RISCV::PAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9053 { 13999 /* pas.wx */, RISCV::PAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9054 { 14006 /* pasa.dhx */, RISCV::PASA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9055 { 14015 /* pasa.hx */, RISCV::PASA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9056 { 14023 /* pasa.wx */, RISCV::PASA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9057 { 14031 /* pasub.b */, RISCV::PASUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9058 { 14039 /* pasub.db */, RISCV::PASUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9059 { 14048 /* pasub.dh */, RISCV::PASUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9060 { 14057 /* pasub.dw */, RISCV::PASUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9061 { 14066 /* pasub.h */, RISCV::PASUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9062 { 14074 /* pasub.w */, RISCV::PASUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9063 { 14082 /* pasubu.b */, RISCV::PASUBU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9064 { 14091 /* pasubu.db */, RISCV::PASUBU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9065 { 14101 /* pasubu.dh */, RISCV::PASUBU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9066 { 14111 /* pasubu.dw */, RISCV::PASUBU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9067 { 14121 /* pasubu.h */, RISCV::PASUBU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9068 { 14130 /* pasubu.w */, RISCV::PASUBU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9069 { 14139 /* pause */, RISCV::FENCE, Convert__imm_95_1__imm_95_0, AMFBS_None, { }, },
9070 { 14145 /* pli.b */, RISCV::PLI_B, Convert__Reg1_0__SImm8PLI_B1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm8PLI_B }, },
9071 { 14151 /* pli.db */, RISCV::PLI_DB, Convert__GPRPairRV321_0__SImm8PLI_B1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm8PLI_B }, },
9072 { 14158 /* pli.dh */, RISCV::PLI_DH, Convert__GPRPairRV321_0__SImm10PLI_H1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm10PLI_H }, },
9073 { 14165 /* pli.h */, RISCV::PLI_H, Convert__Reg1_0__SImm10PLI_H1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm10PLI_H }, },
9074 { 14171 /* pli.w */, RISCV::PLI_W, Convert__Reg1_0__SImm10PLI_W1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_SImm10PLI_W }, },
9075 { 14177 /* plui.dh */, RISCV::PLUI_DH, Convert__GPRPairRV321_0__SImm10PLUI1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm10PLUI }, },
9076 { 14185 /* plui.h */, RISCV::PLUI_H, Convert__Reg1_0__SImm10PLUI1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm10PLUI }, },
9077 { 14192 /* plui.w */, RISCV::PLUI_W, Convert__Reg1_0__SImm10PLUI1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_SImm10PLUI }, },
9078 { 14199 /* pm2add.h */, RISCV::PM2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9079 { 14208 /* pm2add.hx */, RISCV::PM2ADD_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9080 { 14218 /* pm2add.w */, RISCV::PM2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9081 { 14227 /* pm2add.wx */, RISCV::PM2ADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9082 { 14237 /* pm2adda.h */, RISCV::PM2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9083 { 14247 /* pm2adda.hx */, RISCV::PM2ADDA_HX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9084 { 14258 /* pm2adda.w */, RISCV::PM2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9085 { 14268 /* pm2adda.wx */, RISCV::PM2ADDA_WX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9086 { 14279 /* pm2addasu.h */, RISCV::PM2ADDASU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9087 { 14291 /* pm2addasu.w */, RISCV::PM2ADDASU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9088 { 14303 /* pm2addau.h */, RISCV::PM2ADDAU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9089 { 14314 /* pm2addau.w */, RISCV::PM2ADDAU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9090 { 14325 /* pm2addsu.h */, RISCV::PM2ADDSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9091 { 14336 /* pm2addsu.w */, RISCV::PM2ADDSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9092 { 14347 /* pm2addu.h */, RISCV::PM2ADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9093 { 14357 /* pm2addu.w */, RISCV::PM2ADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9094 { 14367 /* pm2sadd.h */, RISCV::PM2SADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9095 { 14377 /* pm2sadd.hx */, RISCV::PM2SADD_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9096 { 14388 /* pm2sub.h */, RISCV::PM2SUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9097 { 14397 /* pm2sub.hx */, RISCV::PM2SUB_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9098 { 14407 /* pm2sub.w */, RISCV::PM2SUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9099 { 14416 /* pm2sub.wx */, RISCV::PM2SUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9100 { 14426 /* pm2suba.h */, RISCV::PM2SUBA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9101 { 14436 /* pm2suba.hx */, RISCV::PM2SUBA_HX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9102 { 14447 /* pm2suba.w */, RISCV::PM2SUBA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9103 { 14457 /* pm2suba.wx */, RISCV::PM2SUBA_WX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9104 { 14468 /* pm2wadd.h */, RISCV::PM2WADD_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9105 { 14478 /* pm2wadd.hx */, RISCV::PM2WADD_HX, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9106 { 14489 /* pm2wadda.h */, RISCV::PM2WADDA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9107 { 14500 /* pm2wadda.hx */, RISCV::PM2WADDA_HX, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9108 { 14512 /* pm2waddasu.h */, RISCV::PM2WADDASU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9109 { 14525 /* pm2waddau.h */, RISCV::PM2WADDAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9110 { 14537 /* pm2waddsu.h */, RISCV::PM2WADDSU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9111 { 14549 /* pm2waddu.h */, RISCV::PM2WADDU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9112 { 14560 /* pm2wsub.h */, RISCV::PM2WSUB_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9113 { 14570 /* pm2wsub.hx */, RISCV::PM2WSUB_HX, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9114 { 14581 /* pm2wsuba.h */, RISCV::PM2WSUBA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9115 { 14592 /* pm2wsuba.hx */, RISCV::PM2WSUBA_HX, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9116 { 14604 /* pm4add.b */, RISCV::PM4ADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9117 { 14613 /* pm4add.h */, RISCV::PM4ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9118 { 14622 /* pm4adda.b */, RISCV::PM4ADDA_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9119 { 14632 /* pm4adda.h */, RISCV::PM4ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9120 { 14642 /* pm4addasu.b */, RISCV::PM4ADDASU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9121 { 14654 /* pm4addasu.h */, RISCV::PM4ADDASU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9122 { 14666 /* pm4addau.b */, RISCV::PM4ADDAU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9123 { 14677 /* pm4addau.h */, RISCV::PM4ADDAU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9124 { 14688 /* pm4addsu.b */, RISCV::PM4ADDSU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9125 { 14699 /* pm4addsu.h */, RISCV::PM4ADDSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9126 { 14710 /* pm4addu.b */, RISCV::PM4ADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9127 { 14720 /* pm4addu.h */, RISCV::PM4ADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9128 { 14730 /* pmacc.w.h00 */, RISCV::PMACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9129 { 14742 /* pmacc.w.h01 */, RISCV::PMACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9130 { 14754 /* pmacc.w.h11 */, RISCV::PMACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9131 { 14766 /* pmaccsu.w.h00 */, RISCV::PMACCSU_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9132 { 14780 /* pmaccsu.w.h11 */, RISCV::PMACCSU_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9133 { 14794 /* pmaccu.w.h00 */, RISCV::PMACCU_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9134 { 14807 /* pmaccu.w.h01 */, RISCV::PMACCU_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9135 { 14820 /* pmaccu.w.h11 */, RISCV::PMACCU_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9136 { 14833 /* pmax.b */, RISCV::PMAX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9137 { 14840 /* pmax.db */, RISCV::PMAX_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9138 { 14848 /* pmax.dh */, RISCV::PMAX_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9139 { 14856 /* pmax.dw */, RISCV::PMAX_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9140 { 14864 /* pmax.h */, RISCV::PMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9141 { 14871 /* pmax.w */, RISCV::PMAX_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9142 { 14878 /* pmaxu.b */, RISCV::PMAXU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9143 { 14886 /* pmaxu.db */, RISCV::PMAXU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9144 { 14895 /* pmaxu.dh */, RISCV::PMAXU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9145 { 14904 /* pmaxu.dw */, RISCV::PMAXU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9146 { 14913 /* pmaxu.h */, RISCV::PMAXU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9147 { 14921 /* pmaxu.w */, RISCV::PMAXU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9148 { 14929 /* pmhacc.h */, RISCV::PMHACC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9149 { 14938 /* pmhacc.h.b0 */, RISCV::PMHACC_H_B0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9150 { 14950 /* pmhacc.h.b1 */, RISCV::PMHACC_H_B1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9151 { 14962 /* pmhacc.w */, RISCV::PMHACC_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9152 { 14971 /* pmhacc.w.h0 */, RISCV::PMHACC_W_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9153 { 14983 /* pmhacc.w.h1 */, RISCV::PMHACC_W_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9154 { 14995 /* pmhaccsu.h */, RISCV::PMHACCSU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9155 { 15006 /* pmhaccsu.h.b0 */, RISCV::PMHACCSU_H_B0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9156 { 15020 /* pmhaccsu.h.b1 */, RISCV::PMHACCSU_H_B1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9157 { 15034 /* pmhaccsu.w */, RISCV::PMHACCSU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9158 { 15045 /* pmhaccsu.w.h0 */, RISCV::PMHACCSU_W_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9159 { 15059 /* pmhaccsu.w.h1 */, RISCV::PMHACCSU_W_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9160 { 15073 /* pmhaccu.h */, RISCV::PMHACCU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9161 { 15083 /* pmhaccu.w */, RISCV::PMHACCU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9162 { 15093 /* pmhracc.h */, RISCV::PMHRACC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9163 { 15103 /* pmhracc.w */, RISCV::PMHRACC_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9164 { 15113 /* pmhraccsu.h */, RISCV::PMHRACCSU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9165 { 15125 /* pmhraccsu.w */, RISCV::PMHRACCSU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9166 { 15137 /* pmhraccu.h */, RISCV::PMHRACCU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9167 { 15148 /* pmhraccu.w */, RISCV::PMHRACCU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9168 { 15159 /* pmin.b */, RISCV::PMIN_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9169 { 15166 /* pmin.db */, RISCV::PMIN_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9170 { 15174 /* pmin.dh */, RISCV::PMIN_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9171 { 15182 /* pmin.dw */, RISCV::PMIN_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9172 { 15190 /* pmin.h */, RISCV::PMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9173 { 15197 /* pmin.w */, RISCV::PMIN_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9174 { 15204 /* pminu.b */, RISCV::PMINU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9175 { 15212 /* pminu.db */, RISCV::PMINU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9176 { 15221 /* pminu.dh */, RISCV::PMINU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9177 { 15230 /* pminu.dw */, RISCV::PMINU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9178 { 15239 /* pminu.h */, RISCV::PMINU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9179 { 15247 /* pminu.w */, RISCV::PMINU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9180 { 15255 /* pmq2add.h */, RISCV::PMQ2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9181 { 15265 /* pmq2add.w */, RISCV::PMQ2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9182 { 15275 /* pmq2adda.h */, RISCV::PMQ2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9183 { 15286 /* pmq2adda.w */, RISCV::PMQ2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9184 { 15297 /* pmqacc.w.h00 */, RISCV::PMQACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9185 { 15310 /* pmqacc.w.h01 */, RISCV::PMQACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9186 { 15323 /* pmqacc.w.h11 */, RISCV::PMQACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9187 { 15336 /* pmqr2add.h */, RISCV::PMQR2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9188 { 15347 /* pmqr2add.w */, RISCV::PMQR2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9189 { 15358 /* pmqr2adda.h */, RISCV::PMQR2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9190 { 15370 /* pmqr2adda.w */, RISCV::PMQR2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9191 { 15382 /* pmqracc.w.h00 */, RISCV::PMQRACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9192 { 15396 /* pmqracc.w.h01 */, RISCV::PMQRACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9193 { 15410 /* pmqracc.w.h11 */, RISCV::PMQRACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9194 { 15424 /* pmqrwacc.h */, RISCV::PMQRWACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9195 { 15435 /* pmqwacc.h */, RISCV::PMQWACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9196 { 15445 /* pmseq.b */, RISCV::PMSEQ_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9197 { 15453 /* pmseq.db */, RISCV::PMSEQ_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9198 { 15462 /* pmseq.dh */, RISCV::PMSEQ_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9199 { 15471 /* pmseq.dw */, RISCV::PMSEQ_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9200 { 15480 /* pmseq.h */, RISCV::PMSEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9201 { 15488 /* pmseq.w */, RISCV::PMSEQ_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9202 { 15496 /* pmseqz.b */, RISCV::PMSEQ_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9203 { 15505 /* pmseqz.db */, RISCV::PMSEQ_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9204 { 15515 /* pmseqz.dh */, RISCV::PMSEQ_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9205 { 15525 /* pmseqz.dw */, RISCV::PMSEQ_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9206 { 15535 /* pmseqz.h */, RISCV::PMSEQ_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9207 { 15544 /* pmseqz.w */, RISCV::PMSEQ_W, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9208 { 15553 /* pmsgt.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9209 { 15561 /* pmsgt.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9210 { 15570 /* pmsgt.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9211 { 15579 /* pmsgt.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9212 { 15588 /* pmsgt.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9213 { 15596 /* pmsgt.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9214 { 15604 /* pmsgtu.b */, RISCV::PMSLTU_B, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9215 { 15613 /* pmsgtu.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9216 { 15623 /* pmsgtu.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9217 { 15633 /* pmsgtu.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9218 { 15643 /* pmsgtu.h */, RISCV::PMSLTU_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9219 { 15652 /* pmsgtu.w */, RISCV::PMSLTU_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9220 { 15661 /* pmsgtz.b */, RISCV::PMSLT_B, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9221 { 15670 /* pmsgtz.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9222 { 15680 /* pmsgtz.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9223 { 15690 /* pmsgtz.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9224 { 15700 /* pmsgtz.h */, RISCV::PMSLT_H, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9225 { 15709 /* pmsgtz.w */, RISCV::PMSLT_W, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9226 { 15718 /* pmslt.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9227 { 15726 /* pmslt.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9228 { 15735 /* pmslt.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9229 { 15744 /* pmslt.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9230 { 15753 /* pmslt.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9231 { 15761 /* pmslt.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9232 { 15769 /* pmsltu.b */, RISCV::PMSLTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9233 { 15778 /* pmsltu.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9234 { 15788 /* pmsltu.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9235 { 15798 /* pmsltu.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9236 { 15808 /* pmsltu.h */, RISCV::PMSLTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9237 { 15817 /* pmsltu.w */, RISCV::PMSLTU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9238 { 15826 /* pmsltz.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9239 { 15835 /* pmsltz.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9240 { 15845 /* pmsltz.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9241 { 15855 /* pmsltz.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9242 { 15865 /* pmsltz.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9243 { 15874 /* pmsltz.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9244 { 15883 /* pmsnez.b */, RISCV::PMSLTU_B, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9245 { 15892 /* pmsnez.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9246 { 15902 /* pmsnez.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9247 { 15912 /* pmsnez.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9248 { 15922 /* pmsnez.h */, RISCV::PMSLTU_H, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9249 { 15931 /* pmsnez.w */, RISCV::PMSLTU_W, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9250 { 15940 /* pmul.h.b00 */, RISCV::PMUL_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9251 { 15951 /* pmul.h.b01 */, RISCV::PMUL_H_B01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9252 { 15962 /* pmul.h.b11 */, RISCV::PMUL_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9253 { 15973 /* pmul.w.h00 */, RISCV::PMUL_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9254 { 15984 /* pmul.w.h01 */, RISCV::PMUL_W_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9255 { 15995 /* pmul.w.h11 */, RISCV::PMUL_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9256 { 16006 /* pmulh.h */, RISCV::PMULH_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9257 { 16014 /* pmulh.h.b0 */, RISCV::PMULH_H_B0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9258 { 16025 /* pmulh.h.b1 */, RISCV::PMULH_H_B1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9259 { 16036 /* pmulh.w */, RISCV::PMULH_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9260 { 16044 /* pmulh.w.h0 */, RISCV::PMULH_W_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9261 { 16055 /* pmulh.w.h1 */, RISCV::PMULH_W_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9262 { 16066 /* pmulhr.h */, RISCV::PMULHR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9263 { 16075 /* pmulhr.w */, RISCV::PMULHR_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9264 { 16084 /* pmulhrsu.h */, RISCV::PMULHRSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9265 { 16095 /* pmulhrsu.w */, RISCV::PMULHRSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9266 { 16106 /* pmulhru.h */, RISCV::PMULHRU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9267 { 16116 /* pmulhru.w */, RISCV::PMULHRU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9268 { 16126 /* pmulhsu.h */, RISCV::PMULHSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9269 { 16136 /* pmulhsu.h.b0 */, RISCV::PMULHSU_H_B0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9270 { 16149 /* pmulhsu.h.b1 */, RISCV::PMULHSU_H_B1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9271 { 16162 /* pmulhsu.w */, RISCV::PMULHSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9272 { 16172 /* pmulhsu.w.h0 */, RISCV::PMULHSU_W_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9273 { 16185 /* pmulhsu.w.h1 */, RISCV::PMULHSU_W_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9274 { 16198 /* pmulhu.h */, RISCV::PMULHU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9275 { 16207 /* pmulhu.w */, RISCV::PMULHU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9276 { 16216 /* pmulq.h */, RISCV::PMULQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9277 { 16224 /* pmulq.w */, RISCV::PMULQ_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9278 { 16232 /* pmulqr.h */, RISCV::PMULQR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9279 { 16241 /* pmulqr.w */, RISCV::PMULQR_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9280 { 16250 /* pmulsu.h.b00 */, RISCV::PMULSU_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9281 { 16263 /* pmulsu.h.b11 */, RISCV::PMULSU_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9282 { 16276 /* pmulsu.w.h00 */, RISCV::PMULSU_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9283 { 16289 /* pmulsu.w.h11 */, RISCV::PMULSU_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9284 { 16302 /* pmulu.h.b00 */, RISCV::PMULU_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9285 { 16314 /* pmulu.h.b01 */, RISCV::PMULU_H_B01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9286 { 16326 /* pmulu.h.b11 */, RISCV::PMULU_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9287 { 16338 /* pmulu.w.h00 */, RISCV::PMULU_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9288 { 16350 /* pmulu.w.h01 */, RISCV::PMULU_W_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9289 { 16362 /* pmulu.w.h11 */, RISCV::PMULU_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9290 { 16374 /* pmv.bs */, RISCV::PADD_BS, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9291 { 16381 /* pmv.dbs */, RISCV::PADD_DBS, Convert__GPRPairRV321_0__regX0_Pair__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9292 { 16389 /* pmv.dhs */, RISCV::PADD_DHS, Convert__GPRPairRV321_0__regX0_Pair__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9293 { 16397 /* pmv.dws */, RISCV::PADD_DWS, Convert__GPRPairRV321_0__regX0_Pair__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9294 { 16405 /* pmv.hs */, RISCV::PADD_HS, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9295 { 16412 /* pmv.ws */, RISCV::PADD_WS, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9296 { 16419 /* pnclip.bs */, RISCV::PNCLIP_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9297 { 16429 /* pnclip.hs */, RISCV::PNCLIP_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9298 { 16439 /* pnclipi.b */, RISCV::PNCLIPI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9299 { 16449 /* pnclipi.h */, RISCV::PNCLIPI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9300 { 16459 /* pnclipiu.b */, RISCV::PNCLIPIU_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9301 { 16470 /* pnclipiu.h */, RISCV::PNCLIPIU_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9302 { 16481 /* pnclipp.b */, RISCV::PNCLIPP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9303 { 16491 /* pnclipp.h */, RISCV::PNCLIPP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9304 { 16501 /* pnclipp.w */, RISCV::PNCLIPP_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9305 { 16511 /* pnclipr.bs */, RISCV::PNCLIPR_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9306 { 16522 /* pnclipr.hs */, RISCV::PNCLIPR_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9307 { 16533 /* pnclipri.b */, RISCV::PNCLIPRI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9308 { 16544 /* pnclipri.h */, RISCV::PNCLIPRI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9309 { 16555 /* pnclipriu.b */, RISCV::PNCLIPRIU_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9310 { 16567 /* pnclipriu.h */, RISCV::PNCLIPRIU_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9311 { 16579 /* pnclipru.bs */, RISCV::PNCLIPRU_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9312 { 16591 /* pnclipru.hs */, RISCV::PNCLIPRU_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9313 { 16603 /* pnclipu.bs */, RISCV::PNCLIPU_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9314 { 16614 /* pnclipu.hs */, RISCV::PNCLIPU_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9315 { 16625 /* pnclipup.b */, RISCV::PNCLIPUP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9316 { 16636 /* pnclipup.h */, RISCV::PNCLIPUP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9317 { 16647 /* pnclipup.w */, RISCV::PNCLIPUP_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9318 { 16658 /* pncvt.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__imm_95_0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9319 { 16666 /* pncvt.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__imm_95_0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9320 { 16674 /* pncvt.wb */, RISCV::UNZIP8P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9321 { 16683 /* pncvt.wh */, RISCV::UNZIP16P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9322 { 16692 /* pncvth.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__imm_95_8, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9323 { 16701 /* pncvth.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__imm_95_16, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9324 { 16710 /* pncvth.wb */, RISCV::UNZIP8HP, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9325 { 16720 /* pncvth.wh */, RISCV::UNZIP16HP, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9326 { 16730 /* pneg.b */, RISCV::PSUB_B, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9327 { 16737 /* pneg.db */, RISCV::PSUB_DB, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9328 { 16745 /* pneg.dh */, RISCV::PSUB_DH, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9329 { 16753 /* pneg.dw */, RISCV::PSUB_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9330 { 16761 /* pneg.h */, RISCV::PSUB_H, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9331 { 16768 /* pneg.w */, RISCV::PSUB_W, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9332 { 16775 /* pnsra.bs */, RISCV::PNSRA_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9333 { 16784 /* pnsra.hs */, RISCV::PNSRA_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9334 { 16793 /* pnsrai.b */, RISCV::PNSRAI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9335 { 16802 /* pnsrai.h */, RISCV::PNSRAI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9336 { 16811 /* pnsrar.bs */, RISCV::PNSRAR_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9337 { 16821 /* pnsrar.hs */, RISCV::PNSRAR_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9338 { 16831 /* pnsrari.b */, RISCV::PNSRARI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9339 { 16841 /* pnsrari.h */, RISCV::PNSRARI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9340 { 16851 /* pnsrl.bs */, RISCV::PNSRL_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9341 { 16860 /* pnsrl.hs */, RISCV::PNSRL_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9342 { 16869 /* pnsrli.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9343 { 16878 /* pnsrli.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9344 { 16887 /* ppaire.b */, RISCV::PPAIRE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9345 { 16896 /* ppaire.db */, RISCV::PPAIRE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9346 { 16906 /* ppaire.dh */, RISCV::PPAIRE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9347 { 16916 /* ppaire.h */, RISCV::PPAIRE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9348 { 16916 /* ppaire.h */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9349 { 16925 /* ppaire.w */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9350 { 16934 /* ppaireo.b */, RISCV::PPAIREO_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9351 { 16944 /* ppaireo.db */, RISCV::PPAIREO_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9352 { 16955 /* ppaireo.dh */, RISCV::PPAIREO_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9353 { 16966 /* ppaireo.h */, RISCV::PPAIREO_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9354 { 16976 /* ppaireo.w */, RISCV::PPAIREO_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9355 { 16986 /* ppairo.b */, RISCV::PPAIRO_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9356 { 16995 /* ppairo.db */, RISCV::PPAIRO_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9357 { 17005 /* ppairo.dh */, RISCV::PPAIRO_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9358 { 17015 /* ppairo.h */, RISCV::PPAIRO_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9359 { 17024 /* ppairo.w */, RISCV::PPAIRO_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9360 { 17033 /* ppairoe.b */, RISCV::PPAIROE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9361 { 17043 /* ppairoe.db */, RISCV::PPAIROE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9362 { 17054 /* ppairoe.dh */, RISCV::PPAIROE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9363 { 17065 /* ppairoe.h */, RISCV::PPAIROE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9364 { 17075 /* ppairoe.w */, RISCV::PPAIROE_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9365 { 17085 /* predsum.bs */, RISCV::PREDSUM_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9366 { 17096 /* predsum.dbs */, RISCV::PREDSUM_DBS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9367 { 17108 /* predsum.dhs */, RISCV::PREDSUM_DHS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9368 { 17120 /* predsum.hs */, RISCV::PREDSUM_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9369 { 17131 /* predsum.ws */, RISCV::PREDSUM_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9370 { 17142 /* predsumu.bs */, RISCV::PREDSUMU_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9371 { 17154 /* predsumu.dbs */, RISCV::PREDSUMU_DBS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9372 { 17167 /* predsumu.dhs */, RISCV::PREDSUMU_DHS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9373 { 17180 /* predsumu.hs */, RISCV::PREDSUMU_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9374 { 17192 /* predsumu.ws */, RISCV::PREDSUMU_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9375 { 17204 /* prefetch.i */, RISCV::PREFETCH_I, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_None, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
9376 { 17215 /* prefetch.r */, RISCV::PREFETCH_R, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_None, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
9377 { 17226 /* prefetch.w */, RISCV::PREFETCH_W, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_None, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
9378 { 17237 /* psa.dhx */, RISCV::PSA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9379 { 17245 /* psa.hx */, RISCV::PSA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9380 { 17252 /* psa.wx */, RISCV::PSA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9381 { 17259 /* psabs.b */, RISCV::PSABS_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9382 { 17267 /* psabs.db */, RISCV::PSABS_DB, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9383 { 17276 /* psabs.dh */, RISCV::PSABS_DH, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9384 { 17285 /* psabs.h */, RISCV::PSABS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9385 { 17293 /* psadd.b */, RISCV::PSADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9386 { 17301 /* psadd.db */, RISCV::PSADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9387 { 17310 /* psadd.dh */, RISCV::PSADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9388 { 17319 /* psadd.dw */, RISCV::PSADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9389 { 17328 /* psadd.h */, RISCV::PSADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9390 { 17336 /* psadd.w */, RISCV::PSADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9391 { 17344 /* psaddu.b */, RISCV::PSADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9392 { 17353 /* psaddu.db */, RISCV::PSADDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9393 { 17363 /* psaddu.dh */, RISCV::PSADDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9394 { 17373 /* psaddu.dw */, RISCV::PSADDU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9395 { 17383 /* psaddu.h */, RISCV::PSADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9396 { 17392 /* psaddu.w */, RISCV::PSADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9397 { 17401 /* psas.dhx */, RISCV::PSAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9398 { 17410 /* psas.hx */, RISCV::PSAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9399 { 17418 /* psas.wx */, RISCV::PSAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9400 { 17426 /* psati.dh */, RISCV::PSATI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9401 { 17435 /* psati.dw */, RISCV::PSATI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9402 { 17444 /* psati.h */, RISCV::PSATI_H, Convert__Reg1_0__Reg1_1__UImm4Plus11_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4Plus1 }, },
9403 { 17452 /* psati.w */, RISCV::PSATI_W, Convert__Reg1_0__Reg1_1__UImm5Plus11_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5Plus1 }, },
9404 { 17460 /* psext.dh.b */, RISCV::PSEXT_DH_B, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9405 { 17471 /* psext.dw.b */, RISCV::PSEXT_DW_B, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9406 { 17482 /* psext.dw.h */, RISCV::PSEXT_DW_H, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9407 { 17493 /* psext.h.b */, RISCV::PSEXT_H_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9408 { 17503 /* psext.w.b */, RISCV::PSEXT_W_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9409 { 17513 /* psext.w.h */, RISCV::PSEXT_W_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9410 { 17523 /* psh1add.dh */, RISCV::PSH1ADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9411 { 17534 /* psh1add.dw */, RISCV::PSH1ADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9412 { 17545 /* psh1add.h */, RISCV::PSH1ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9413 { 17555 /* psh1add.w */, RISCV::PSH1ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9414 { 17565 /* psll.bs */, RISCV::PSLL_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9415 { 17573 /* psll.dbs */, RISCV::PSLL_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9416 { 17582 /* psll.dhs */, RISCV::PSLL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9417 { 17591 /* psll.dws */, RISCV::PSLL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9418 { 17600 /* psll.hs */, RISCV::PSLL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9419 { 17608 /* psll.ws */, RISCV::PSLL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9420 { 17616 /* pslli.b */, RISCV::PSLLI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
9421 { 17624 /* pslli.db */, RISCV::PSLLI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
9422 { 17633 /* pslli.dh */, RISCV::PSLLI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9423 { 17642 /* pslli.dw */, RISCV::PSLLI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9424 { 17651 /* pslli.h */, RISCV::PSLLI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9425 { 17659 /* pslli.w */, RISCV::PSLLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9426 { 17667 /* psra.bs */, RISCV::PSRA_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9427 { 17675 /* psra.dbs */, RISCV::PSRA_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9428 { 17684 /* psra.dhs */, RISCV::PSRA_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9429 { 17693 /* psra.dws */, RISCV::PSRA_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9430 { 17702 /* psra.hs */, RISCV::PSRA_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9431 { 17710 /* psra.ws */, RISCV::PSRA_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9432 { 17718 /* psrai.b */, RISCV::PSRAI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
9433 { 17726 /* psrai.db */, RISCV::PSRAI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
9434 { 17735 /* psrai.dh */, RISCV::PSRAI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9435 { 17744 /* psrai.dw */, RISCV::PSRAI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9436 { 17753 /* psrai.h */, RISCV::PSRAI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9437 { 17761 /* psrai.w */, RISCV::PSRAI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9438 { 17769 /* psrari.dh */, RISCV::PSRARI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9439 { 17779 /* psrari.dw */, RISCV::PSRARI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9440 { 17789 /* psrari.h */, RISCV::PSRARI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9441 { 17798 /* psrari.w */, RISCV::PSRARI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9442 { 17807 /* psrl.bs */, RISCV::PSRL_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9443 { 17815 /* psrl.dbs */, RISCV::PSRL_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9444 { 17824 /* psrl.dhs */, RISCV::PSRL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9445 { 17833 /* psrl.dws */, RISCV::PSRL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9446 { 17842 /* psrl.hs */, RISCV::PSRL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9447 { 17850 /* psrl.ws */, RISCV::PSRL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9448 { 17858 /* psrli.b */, RISCV::PSRLI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
9449 { 17866 /* psrli.db */, RISCV::PSRLI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
9450 { 17875 /* psrli.dh */, RISCV::PSRLI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9451 { 17884 /* psrli.dw */, RISCV::PSRLI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9452 { 17893 /* psrli.h */, RISCV::PSRLI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9453 { 17901 /* psrli.w */, RISCV::PSRLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9454 { 17909 /* pssa.dhx */, RISCV::PSSA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9455 { 17918 /* pssa.hx */, RISCV::PSSA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9456 { 17926 /* pssa.wx */, RISCV::PSSA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9457 { 17934 /* pssh1sadd.dh */, RISCV::PSSH1SADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9458 { 17947 /* pssh1sadd.dw */, RISCV::PSSH1SADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9459 { 17960 /* pssh1sadd.h */, RISCV::PSSH1SADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9460 { 17972 /* pssh1sadd.w */, RISCV::PSSH1SADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9461 { 17984 /* pssha.dhs */, RISCV::PSSHA_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9462 { 17994 /* pssha.dws */, RISCV::PSSHA_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9463 { 18004 /* pssha.hs */, RISCV::PSSHA_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9464 { 18013 /* pssha.ws */, RISCV::PSSHA_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9465 { 18022 /* psshar.dhs */, RISCV::PSSHAR_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9466 { 18033 /* psshar.dws */, RISCV::PSSHAR_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9467 { 18044 /* psshar.hs */, RISCV::PSSHAR_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9468 { 18054 /* psshar.ws */, RISCV::PSSHAR_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9469 { 18064 /* psshl.dhs */, RISCV::PSSHL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9470 { 18074 /* psshl.dws */, RISCV::PSSHL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9471 { 18084 /* psshl.hs */, RISCV::PSSHL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9472 { 18093 /* psshl.ws */, RISCV::PSSHL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9473 { 18102 /* psshlr.dhs */, RISCV::PSSHLR_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9474 { 18113 /* psshlr.dws */, RISCV::PSSHLR_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9475 { 18124 /* psshlr.hs */, RISCV::PSSHLR_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9476 { 18134 /* psshlr.ws */, RISCV::PSSHLR_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9477 { 18144 /* psslai.dh */, RISCV::PSSLAI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9478 { 18154 /* psslai.dw */, RISCV::PSSLAI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9479 { 18164 /* psslai.h */, RISCV::PSSLAI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9480 { 18173 /* psslai.w */, RISCV::PSSLAI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9481 { 18182 /* pssub.b */, RISCV::PSSUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9482 { 18190 /* pssub.db */, RISCV::PSSUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9483 { 18199 /* pssub.dh */, RISCV::PSSUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9484 { 18208 /* pssub.dw */, RISCV::PSSUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9485 { 18217 /* pssub.h */, RISCV::PSSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9486 { 18225 /* pssub.w */, RISCV::PSSUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9487 { 18233 /* pssubu.b */, RISCV::PSSUBU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9488 { 18242 /* pssubu.db */, RISCV::PSSUBU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9489 { 18252 /* pssubu.dh */, RISCV::PSSUBU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9490 { 18262 /* pssubu.dw */, RISCV::PSSUBU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9491 { 18272 /* pssubu.h */, RISCV::PSSUBU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9492 { 18281 /* pssubu.w */, RISCV::PSSUBU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9493 { 18290 /* psub.b */, RISCV::PSUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9494 { 18297 /* psub.db */, RISCV::PSUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9495 { 18305 /* psub.dh */, RISCV::PSUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9496 { 18313 /* psub.dw */, RISCV::PSUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9497 { 18321 /* psub.h */, RISCV::PSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9498 { 18328 /* psub.w */, RISCV::PSUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9499 { 18335 /* pusati.dh */, RISCV::PUSATI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9500 { 18345 /* pusati.dw */, RISCV::PUSATI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9501 { 18355 /* pusati.h */, RISCV::PUSATI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9502 { 18364 /* pusati.w */, RISCV::PUSATI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9503 { 18373 /* pwadd.b */, RISCV::PWADD_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9504 { 18381 /* pwadd.h */, RISCV::PWADD_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9505 { 18389 /* pwadda.b */, RISCV::PWADDA_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9506 { 18398 /* pwadda.h */, RISCV::PWADDA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9507 { 18407 /* pwaddau.b */, RISCV::PWADDAU_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9508 { 18417 /* pwaddau.h */, RISCV::PWADDAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9509 { 18427 /* pwaddu.b */, RISCV::PWADDU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9510 { 18436 /* pwaddu.h */, RISCV::PWADDU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9511 { 18445 /* pwcvt.b */, RISCV::PWADD_B, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9512 { 18453 /* pwcvt.h */, RISCV::PWADD_H, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9513 { 18461 /* pwcvth.b */, RISCV::WZIP8P, Convert__GPRPairRV321_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9514 { 18470 /* pwcvth.h */, RISCV::WZIP16P, Convert__GPRPairRV321_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9515 { 18479 /* pwcvth.wb */, RISCV::ZIP8P, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9516 { 18489 /* pwcvth.wh */, RISCV::ZIP16P, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9517 { 18499 /* pwcvtu.b */, RISCV::WZIP8P, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9518 { 18508 /* pwcvtu.h */, RISCV::WZIP16P, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9519 { 18517 /* pwcvtu.wb */, RISCV::ZIP8P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9520 { 18527 /* pwcvtu.wh */, RISCV::ZIP16P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9521 { 18537 /* pwmacc.h */, RISCV::PWMACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9522 { 18546 /* pwmaccsu.h */, RISCV::PWMACCSU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9523 { 18557 /* pwmaccu.h */, RISCV::PWMACCU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9524 { 18567 /* pwmul.b */, RISCV::PWMUL_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9525 { 18575 /* pwmul.h */, RISCV::PWMUL_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9526 { 18583 /* pwmulsu.b */, RISCV::PWMULSU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9527 { 18593 /* pwmulsu.h */, RISCV::PWMULSU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9528 { 18603 /* pwmulu.b */, RISCV::PWMULU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9529 { 18612 /* pwmulu.h */, RISCV::PWMULU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9530 { 18621 /* pwsla.bs */, RISCV::PWSLA_BS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9531 { 18630 /* pwsla.hs */, RISCV::PWSLA_HS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9532 { 18639 /* pwslai.b */, RISCV::PWSLAI_B, Convert__GPRPairRV321_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm4 }, },
9533 { 18648 /* pwslai.h */, RISCV::PWSLAI_H, Convert__GPRPairRV321_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm5 }, },
9534 { 18657 /* pwsll.bs */, RISCV::PWSLL_BS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9535 { 18666 /* pwsll.hs */, RISCV::PWSLL_HS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9536 { 18675 /* pwslli.b */, RISCV::PWSLLI_B, Convert__GPRPairRV321_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm4 }, },
9537 { 18684 /* pwslli.h */, RISCV::PWSLLI_H, Convert__GPRPairRV321_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm5 }, },
9538 { 18693 /* pwsub.b */, RISCV::PWSUB_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9539 { 18701 /* pwsub.h */, RISCV::PWSUB_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9540 { 18709 /* pwsuba.b */, RISCV::PWSUBA_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9541 { 18718 /* pwsuba.h */, RISCV::PWSUBA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9542 { 18727 /* pwsubau.b */, RISCV::PWSUBAU_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9543 { 18737 /* pwsubau.h */, RISCV::PWSUBAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9544 { 18747 /* pwsubu.b */, RISCV::PWSUBU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9545 { 18756 /* pwsubu.h */, RISCV::PWSUBU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9546 { 18765 /* pzext.dh.b */, RISCV::PPAIRE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9547 { 18776 /* pzext.dw.h */, RISCV::PPAIRE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9548 { 18787 /* pzext.h.b */, RISCV::PPAIRE_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9549 { 18797 /* pzext.w.h */, RISCV::PPAIRE_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9550 { 18807 /* qc.addsat */, RISCV::QC_ADDSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9551 { 18817 /* qc.addusat */, RISCV::QC_ADDUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9552 { 18828 /* qc.beqi */, RISCV::QC_BEQI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9553 { 18836 /* qc.bgei */, RISCV::QC_BGEI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9554 { 18844 /* qc.bgeui */, RISCV::QC_BGEUI, Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_BareSImm13Lsb0 }, },
9555 { 18853 /* qc.blti */, RISCV::QC_BLTI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9556 { 18861 /* qc.bltui */, RISCV::QC_BLTUI, Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_BareSImm13Lsb0 }, },
9557 { 18870 /* qc.bnei */, RISCV::QC_BNEI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9558 { 18878 /* qc.brev32 */, RISCV::QC_BREV32, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9559 { 18888 /* qc.c.bexti */, RISCV::QC_C_BEXTI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
9560 { 18899 /* qc.c.bseti */, RISCV::QC_C_BSETI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
9561 { 18910 /* qc.c.clrint */, RISCV::QC_C_CLRINT, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9562 { 18922 /* qc.c.delay */, RISCV::C_SLLI, Convert__regX0__Tie0_1_1__UImm5NonZero1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5NonZero }, },
9563 { 18933 /* qc.c.di */, RISCV::QC_C_DI, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9564 { 18941 /* qc.c.dir */, RISCV::QC_C_DIR, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9565 { 18950 /* qc.c.ei */, RISCV::QC_C_EI, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9566 { 18958 /* qc.c.eir */, RISCV::QC_C_EIR, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9567 { 18967 /* qc.c.extu */, RISCV::QC_C_EXTU, Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_UImm5GE6Plus1 }, },
9568 { 18977 /* qc.c.mienter */, RISCV::QC_C_MIENTER, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9569 { 18990 /* qc.c.mienter.nest */, RISCV::QC_C_MIENTER_NEST, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9570 { 19008 /* qc.c.mileaveret */, RISCV::QC_C_MILEAVERET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9571 { 19024 /* qc.c.mnret */, RISCV::QC_C_MNRET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9572 { 19035 /* qc.c.mret */, RISCV::QC_C_MRET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9573 { 19045 /* qc.c.muliadd */, RISCV::QC_C_MULIADD, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRC, MCK_GPRC, MCK_UImm5 }, },
9574 { 19058 /* qc.c.mveqz */, RISCV::QC_C_MVEQZ, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRC, MCK_GPRC }, },
9575 { 19069 /* qc.c.ptrace */, RISCV::C_SLLI, Convert__regX0__Tie0_1_1__imm_95_0, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9576 { 19081 /* qc.c.setint */, RISCV::QC_C_SETINT, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9577 { 19093 /* qc.c.sync */, RISCV::QC_C_SYNC, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9578 { 19103 /* qc.c.syncr */, RISCV::QC_C_SYNCR, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9579 { 19114 /* qc.c.syncwf */, RISCV::QC_C_SYNCWF, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9580 { 19126 /* qc.c.syncwl */, RISCV::QC_C_SYNCWL, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9581 { 19138 /* qc.clo */, RISCV::QC_CLO, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9582 { 19145 /* qc.clrinti */, RISCV::QC_CLRINTI, Convert__UImm101_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_UImm10 }, },
9583 { 19156 /* qc.cm.jalt */, RISCV::QC_CM_JALT, Convert__UImm8GE321_0, AMFBS_HasVendorXqccmt, { MCK_UImm8GE32 }, },
9584 { 19167 /* qc.cm.jt */, RISCV::QC_CM_JT, Convert__UImm51_0, AMFBS_HasVendorXqccmt, { MCK_UImm5 }, },
9585 { 19176 /* qc.cm.mva01s */, RISCV::QC_CM_MVA01S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqccmp, { MCK_SR07, MCK_SR07 }, },
9586 { 19189 /* qc.cm.mvsa01 */, RISCV::QC_CM_MVSA01, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqccmp, { MCK_SR07, MCK_SR07 }, },
9587 { 19202 /* qc.cm.pop */, RISCV::QC_CM_POP, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9588 { 19212 /* qc.cm.popret */, RISCV::QC_CM_POPRET, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9589 { 19225 /* qc.cm.popretz */, RISCV::QC_CM_POPRETZ, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9590 { 19239 /* qc.cm.push */, RISCV::QC_CM_PUSH, Convert__RegList1_0__NegStackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_NegStackAdj }, },
9591 { 19250 /* qc.cm.pushfp */, RISCV::QC_CM_PUSHFP, Convert__RegListS01_0__NegStackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegListS0, MCK_NegStackAdj }, },
9592 { 19263 /* qc.compress2 */, RISCV::QC_COMPRESS2, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9593 { 19276 /* qc.compress3 */, RISCV::QC_COMPRESS3, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9594 { 19289 /* qc.csrrwr */, RISCV::QC_CSRRWR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcicsr_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0 }, },
9595 { 19299 /* qc.csrrwri */, RISCV::QC_CSRRWRI, Convert__Reg1_0__UImm51_1__Reg1_2, AMFBS_HasVendorXqcicsr_IsRV32, { MCK_GPR, MCK_UImm5, MCK_GPRNoX0 }, },
9596 { 19310 /* qc.cto */, RISCV::QC_CTO, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9597 { 19317 /* qc.e.addai */, RISCV::QC_E_ADDAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9598 { 19328 /* qc.e.addi */, RISCV::QC_E_ADDI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9599 { 19338 /* qc.e.andai */, RISCV::QC_E_ANDAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9600 { 19349 /* qc.e.andi */, RISCV::QC_E_ANDI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9601 { 19359 /* qc.e.beqi */, RISCV::QC_E_BEQI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9602 { 19369 /* qc.e.bgei */, RISCV::QC_E_BGEI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9603 { 19379 /* qc.e.bgeui */, RISCV::QC_E_BGEUI, Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm16NonZero, MCK_BareSImm13Lsb0 }, },
9604 { 19390 /* qc.e.blti */, RISCV::QC_E_BLTI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9605 { 19400 /* qc.e.bltui */, RISCV::QC_E_BLTUI, Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm16NonZero, MCK_BareSImm13Lsb0 }, },
9606 { 19411 /* qc.e.bnei */, RISCV::QC_E_BNEI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9607 { 19421 /* qc.e.j */, RISCV::QC_E_J, Convert__BareSImm32Lsb01_0, AMFBS_HasVendorXqcilb_IsRV32, { MCK_BareSImm32Lsb0 }, },
9608 { 19428 /* qc.e.jal */, RISCV::QC_E_JAL, Convert__BareSImm32Lsb01_0, AMFBS_HasVendorXqcilb_IsRV32, { MCK_BareSImm32Lsb0 }, },
9609 { 19437 /* qc.e.lb */, RISCV::PseudoQC_E_LB, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9610 { 19437 /* qc.e.lb */, RISCV::QC_E_LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9611 { 19437 /* qc.e.lb */, RISCV::QC_E_LB, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9612 { 19445 /* qc.e.lbu */, RISCV::PseudoQC_E_LBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9613 { 19445 /* qc.e.lbu */, RISCV::QC_E_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9614 { 19445 /* qc.e.lbu */, RISCV::QC_E_LBU, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9615 { 19454 /* qc.e.lh */, RISCV::PseudoQC_E_LH, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9616 { 19454 /* qc.e.lh */, RISCV::QC_E_LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9617 { 19454 /* qc.e.lh */, RISCV::QC_E_LH, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9618 { 19462 /* qc.e.lhu */, RISCV::PseudoQC_E_LHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9619 { 19462 /* qc.e.lhu */, RISCV::QC_E_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9620 { 19462 /* qc.e.lhu */, RISCV::QC_E_LHU, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9621 { 19471 /* qc.e.li */, RISCV::QC_E_LI, Convert__Reg1_0__BareSImm321_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9622 { 19471 /* qc.e.li */, RISCV::ADDI, Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbolQC_E_LI }, },
9623 { 19479 /* qc.e.lw */, RISCV::PseudoQC_E_LW, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9624 { 19479 /* qc.e.lw */, RISCV::QC_E_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9625 { 19479 /* qc.e.lw */, RISCV::QC_E_LW, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9626 { 19487 /* qc.e.orai */, RISCV::QC_E_ORAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9627 { 19497 /* qc.e.ori */, RISCV::QC_E_ORI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9628 { 19506 /* qc.e.sb */, RISCV::PseudoQC_E_SB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9629 { 19506 /* qc.e.sb */, RISCV::QC_E_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9630 { 19506 /* qc.e.sb */, RISCV::QC_E_SB, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9631 { 19514 /* qc.e.sh */, RISCV::PseudoQC_E_SH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9632 { 19514 /* qc.e.sh */, RISCV::QC_E_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9633 { 19514 /* qc.e.sh */, RISCV::QC_E_SH, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9634 { 19522 /* qc.e.sw */, RISCV::PseudoQC_E_SW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9635 { 19522 /* qc.e.sw */, RISCV::QC_E_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9636 { 19522 /* qc.e.sw */, RISCV::QC_E_SW, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9637 { 19530 /* qc.e.xorai */, RISCV::QC_E_XORAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9638 { 19541 /* qc.e.xori */, RISCV::QC_E_XORI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9639 { 19551 /* qc.expand2 */, RISCV::QC_EXPAND2, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9640 { 19562 /* qc.expand3 */, RISCV::QC_EXPAND3, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9641 { 19573 /* qc.ext */, RISCV::QC_EXT, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5Plus1, MCK_UImm5 }, },
9642 { 19580 /* qc.extd */, RISCV::QC_EXTD, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_UImm5Plus1, MCK_UImm5 }, },
9643 { 19588 /* qc.extdpr */, RISCV::QC_EXTDPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9644 { 19598 /* qc.extdprh */, RISCV::QC_EXTDPRH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9645 { 19609 /* qc.extdr */, RISCV::QC_EXTDR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9646 { 19618 /* qc.extdu */, RISCV::QC_EXTDU, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_UImm5Plus1, MCK_UImm5 }, },
9647 { 19627 /* qc.extdupr */, RISCV::QC_EXTDUPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9648 { 19638 /* qc.extduprh */, RISCV::QC_EXTDUPRH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9649 { 19650 /* qc.extdur */, RISCV::QC_EXTDUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9650 { 19660 /* qc.extu */, RISCV::QC_EXTU, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5Plus1, MCK_UImm5 }, },
9651 { 19668 /* qc.insb */, RISCV::QC_INSB, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_UImm5Plus1, MCK_UImm5 }, },
9652 { 19676 /* qc.insbh */, RISCV::QC_INSBH, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_UImm5Plus1, MCK_UImm5 }, },
9653 { 19685 /* qc.insbhr */, RISCV::QC_INSBHR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9654 { 19695 /* qc.insbi */, RISCV::QC_INSBI, Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_UImm5Plus1, MCK_UImm5 }, },
9655 { 19704 /* qc.insbpr */, RISCV::QC_INSBPR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9656 { 19714 /* qc.insbprh */, RISCV::QC_INSBPRH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9657 { 19725 /* qc.insbr */, RISCV::QC_INSBR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9658 { 19734 /* qc.insbri */, RISCV::QC_INSBRI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm11 }, },
9659 { 19744 /* qc.inw */, RISCV::QC_INW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9660 { 19744 /* qc.inw */, RISCV::QC_INW, Convert__Reg1_0__Reg1_3__UImm14Lsb001_1, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPRNoX0, MCK_UImm14Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9661 { 19751 /* qc.li */, RISCV::QC_LI, Convert__Reg1_0__SImm20LI1_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_SImm20LI }, },
9662 { 19757 /* qc.lieq */, RISCV::QC_LIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9663 { 19765 /* qc.lieqi */, RISCV::QC_LIEQI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9664 { 19774 /* qc.lige */, RISCV::QC_LIGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9665 { 19782 /* qc.ligei */, RISCV::QC_LIGEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9666 { 19791 /* qc.ligeu */, RISCV::QC_LIGEU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9667 { 19800 /* qc.ligeui */, RISCV::QC_LIGEUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_SImm5 }, },
9668 { 19810 /* qc.lilt */, RISCV::QC_LILT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9669 { 19818 /* qc.lilti */, RISCV::QC_LILTI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9670 { 19827 /* qc.liltu */, RISCV::QC_LILTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9671 { 19836 /* qc.liltui */, RISCV::QC_LILTUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_SImm5 }, },
9672 { 19846 /* qc.line */, RISCV::QC_LINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9673 { 19854 /* qc.linei */, RISCV::QC_LINEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9674 { 19863 /* qc.lrb */, RISCV::QC_LRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9675 { 19870 /* qc.lrbu */, RISCV::QC_LRBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9676 { 19878 /* qc.lrh */, RISCV::QC_LRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9677 { 19885 /* qc.lrhu */, RISCV::QC_LRHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9678 { 19893 /* qc.lrw */, RISCV::QC_LRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9679 { 19900 /* qc.lwm */, RISCV::QC_LWM, Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9680 { 19900 /* qc.lwm */, RISCV::QC_LWM, Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9681 { 19907 /* qc.lwmi */, RISCV::QC_LWMI, Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK__40_, MCK_GPR, MCK__41_ }, },
9682 { 19907 /* qc.lwmi */, RISCV::QC_LWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9683 { 19915 /* qc.muliadd */, RISCV::QC_MULIADD, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm12LO }, },
9684 { 19926 /* qc.mveq */, RISCV::QC_MVEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9685 { 19934 /* qc.mveqi */, RISCV::QC_MVEQI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9686 { 19943 /* qc.mvge */, RISCV::QC_MVGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9687 { 19951 /* qc.mvgei */, RISCV::QC_MVGEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9688 { 19960 /* qc.mvgeu */, RISCV::QC_MVGEU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9689 { 19969 /* qc.mvgeui */, RISCV::QC_MVGEUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_GPRNoX0 }, },
9690 { 19979 /* qc.mvlt */, RISCV::QC_MVLT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9691 { 19987 /* qc.mvlti */, RISCV::QC_MVLTI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9692 { 19996 /* qc.mvltu */, RISCV::QC_MVLTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9693 { 20005 /* qc.mvltui */, RISCV::QC_MVLTUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_GPRNoX0 }, },
9694 { 20015 /* qc.mvne */, RISCV::QC_MVNE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9695 { 20023 /* qc.mvnei */, RISCV::QC_MVNEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9696 { 20032 /* qc.norm */, RISCV::QC_NORM, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9697 { 20040 /* qc.normeu */, RISCV::QC_NORMEU, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9698 { 20050 /* qc.normu */, RISCV::QC_NORMU, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9699 { 20059 /* qc.outw */, RISCV::QC_OUTW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9700 { 20059 /* qc.outw */, RISCV::QC_OUTW, Convert__Reg1_0__Reg1_3__UImm14Lsb001_1, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPR, MCK_UImm14Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9701 { 20067 /* qc.pcoredump */, RISCV::SLTI, Convert__regX0__regX0__imm_95_1536, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9702 { 20080 /* qc.pexit */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1280, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9703 { 20089 /* qc.ppreg */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_2048, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9704 { 20098 /* qc.ppregs */, RISCV::SLTI, Convert__regX0__regX0__imm_95_1792, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9705 { 20108 /* qc.pputc */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1792, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9706 { 20117 /* qc.pputci */, RISCV::QC_PPUTCI, Convert__UImm81_0, AMFBS_HasVendorXqcisim_IsRV32, { MCK_UImm8 }, },
9707 { 20127 /* qc.pputs */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1536, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9708 { 20136 /* qc.psyscall */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1024, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9709 { 20148 /* qc.psyscalli */, RISCV::SLTI, Convert__regX0__regX0__UImm101_0, AMFBS_HasVendorXqcisim_IsRV32, { MCK_UImm10 }, },
9710 { 20161 /* qc.selecteqi */, RISCV::QC_SELECTEQI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9711 { 20174 /* qc.selectieq */, RISCV::QC_SELECTIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9712 { 20187 /* qc.selectieqi */, RISCV::QC_SELECTIEQI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_SImm5 }, },
9713 { 20201 /* qc.selectiieq */, RISCV::QC_SELECTIIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9714 { 20215 /* qc.selectiine */, RISCV::QC_SELECTIINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9715 { 20229 /* qc.selectine */, RISCV::QC_SELECTINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9716 { 20242 /* qc.selectinei */, RISCV::QC_SELECTINEI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_SImm5 }, },
9717 { 20256 /* qc.selectnei */, RISCV::QC_SELECTNEI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9718 { 20269 /* qc.setinti */, RISCV::QC_SETINTI, Convert__UImm101_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_UImm10 }, },
9719 { 20280 /* qc.setwm */, RISCV::QC_SETWM, Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9720 { 20280 /* qc.setwm */, RISCV::QC_SETWM, Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_GPRNoX0, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9721 { 20289 /* qc.setwmi */, RISCV::QC_SETWMI, Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_UImm5NonZero, MCK__40_, MCK_GPR, MCK__41_ }, },
9722 { 20289 /* qc.setwmi */, RISCV::QC_SETWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_UImm5NonZero, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9723 { 20299 /* qc.shladd */, RISCV::QC_SHLADD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5GT3 }, },
9724 { 20309 /* qc.shlsat */, RISCV::QC_SHLSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9725 { 20319 /* qc.shlusat */, RISCV::QC_SHLUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9726 { 20330 /* qc.srb */, RISCV::QC_SRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9727 { 20337 /* qc.srh */, RISCV::QC_SRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9728 { 20344 /* qc.srw */, RISCV::QC_SRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9729 { 20351 /* qc.subsat */, RISCV::QC_SUBSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9730 { 20361 /* qc.subusat */, RISCV::QC_SUBUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9731 { 20372 /* qc.swm */, RISCV::QC_SWM, Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9732 { 20372 /* qc.swm */, RISCV::QC_SWM, Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9733 { 20379 /* qc.swmi */, RISCV::QC_SWMI, Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK__40_, MCK_GPR, MCK__41_ }, },
9734 { 20379 /* qc.swmi */, RISCV::QC_SWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9735 { 20387 /* qc.sync */, RISCV::QC_SYNC, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9736 { 20395 /* qc.syncr */, RISCV::QC_SYNCR, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9737 { 20404 /* qc.syncwf */, RISCV::QC_SYNCWF, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9738 { 20414 /* qc.syncwl */, RISCV::QC_SYNCWL, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9739 { 20424 /* qc.wrap */, RISCV::QC_WRAP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9740 { 20432 /* qc.wrapi */, RISCV::QC_WRAPI, Convert__Reg1_0__Reg1_1__UImm111_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm11 }, },
9741 { 20441 /* qk.c.lbu */, RISCV::QK_C_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9742 { 20441 /* qk.c.lbu */, RISCV::QK_C_LBU, Convert__Reg1_0__Reg1_3__UImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
9743 { 20450 /* qk.c.lbusp */, RISCV::QK_C_LBUSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9744 { 20450 /* qk.c.lbusp */, RISCV::QK_C_LBUSP, Convert__Reg1_0__Reg1_3__UImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm4, MCK__40_, MCK_SP, MCK__41_ }, },
9745 { 20461 /* qk.c.lhu */, RISCV::QK_C_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9746 { 20461 /* qk.c.lhu */, RISCV::QK_C_LHU, Convert__Reg1_0__Reg1_3__UImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
9747 { 20470 /* qk.c.lhusp */, RISCV::QK_C_LHUSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9748 { 20470 /* qk.c.lhusp */, RISCV::QK_C_LHUSP, Convert__Reg1_0__Reg1_3__UImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
9749 { 20481 /* qk.c.sb */, RISCV::QK_C_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9750 { 20481 /* qk.c.sb */, RISCV::QK_C_SB, Convert__Reg1_0__Reg1_3__UImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
9751 { 20489 /* qk.c.sbsp */, RISCV::QK_C_SBSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9752 { 20489 /* qk.c.sbsp */, RISCV::QK_C_SBSP, Convert__Reg1_0__Reg1_3__UImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm4, MCK__40_, MCK_SP, MCK__41_ }, },
9753 { 20499 /* qk.c.sh */, RISCV::QK_C_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9754 { 20499 /* qk.c.sh */, RISCV::QK_C_SH, Convert__Reg1_0__Reg1_3__UImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
9755 { 20507 /* qk.c.shsp */, RISCV::QK_C_SHSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9756 { 20507 /* qk.c.shsp */, RISCV::QK_C_SHSP, Convert__Reg1_0__Reg1_3__UImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
9757 { 20517 /* rdcycle */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3072__regX0, AMFBS_None, { MCK_GPR }, },
9758 { 20525 /* rdcycleh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3200__regX0, AMFBS_IsRV32, { MCK_GPR }, },
9759 { 20534 /* rdinstret */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3074__regX0, AMFBS_None, { MCK_GPR }, },
9760 { 20544 /* rdinstreth */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3202__regX0, AMFBS_IsRV32, { MCK_GPR }, },
9761 { 20555 /* rdtime */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3073__regX0, AMFBS_None, { MCK_GPR }, },
9762 { 20562 /* rdtimeh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3201__regX0, AMFBS_IsRV32, { MCK_GPR }, },
9763 { 20570 /* rem */, RISCV::REM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9764 { 20574 /* remu */, RISCV::REMU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9765 { 20579 /* remuw */, RISCV::REMUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9766 { 20585 /* remw */, RISCV::REMW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9767 { 20590 /* ret */, RISCV::JALR, Convert__regX0__regX1__imm_95_0, AMFBS_None, { }, },
9768 { 20594 /* rev */, RISCV::REV_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
9769 { 20594 /* rev */, RISCV::REV_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9770 { 20598 /* rev16 */, RISCV::REV16_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9771 { 20604 /* rev8 */, RISCV::REV8_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
9772 { 20604 /* rev8 */, RISCV::REV8_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR }, },
9773 { 20609 /* rol */, RISCV::ROL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9774 { 20613 /* rolw */, RISCV::ROLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9775 { 20618 /* ror */, RISCV::ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9776 { 20618 /* ror */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9777 { 20622 /* rori */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9778 { 20627 /* roriw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9779 { 20633 /* rorw */, RISCV::RORW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9780 { 20633 /* rorw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9781 { 20638 /* sadd */, RISCV::SADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9782 { 20643 /* saddu */, RISCV::SADDU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9783 { 20649 /* sati */, RISCV::SATI_RV32, Convert__Reg1_0__Reg1_1__UImm5Plus11_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5Plus1 }, },
9784 { 20649 /* sati */, RISCV::SATI_RV64, Convert__Reg1_0__Reg1_1__UImm6Plus11_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6Plus1 }, },
9785 { 20654 /* sb */, RISCV::PseudoSB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9786 { 20654 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9787 { 20654 /* sb */, RISCV::PseudoQCAccessSB, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9788 { 20654 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9789 { 20654 /* sb */, RISCV::PseudoQCAccessSB, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9790 { 20657 /* sb.aqrl */, RISCV::SB_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9791 { 20665 /* sb.rl */, RISCV::SB_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9792 { 20671 /* sc.d */, RISCV::SC_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9793 { 20676 /* sc.d.aq */, RISCV::SC_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9794 { 20684 /* sc.d.aqrl */, RISCV::SC_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9795 { 20694 /* sc.d.rl */, RISCV::SC_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9796 { 20702 /* sc.w */, RISCV::SC_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9797 { 20707 /* sc.w.aq */, RISCV::SC_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9798 { 20715 /* sc.w.aqrl */, RISCV::SC_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9799 { 20725 /* sc.w.rl */, RISCV::SC_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9800 { 20733 /* sctrclr */, RISCV::SCTRCLR, Convert_NoOperands, AMFBS_HasStdExtSmctrOrSsctr, { }, },
9801 { 20741 /* sd */, RISCV::PseudoSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9802 { 20741 /* sd */, RISCV::PseudoSD_RV32, Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_BareSymbol, MCK_GPR }, },
9803 { 20741 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9804 { 20741 /* sd */, RISCV::SD_RV32, Convert__GPRPairRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK__40_, MCK_GPR, MCK__41_ }, },
9805 { 20741 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9806 { 20741 /* sd */, RISCV::SD_RV32, Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9807 { 20744 /* sd.aqrl */, RISCV::SD_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9808 { 20752 /* sd.rl */, RISCV::SD_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9809 { 20758 /* seqz */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__imm_95_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9810 { 20763 /* sext.b */, RISCV::SEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
9811 { 20763 /* sext.b */, RISCV::PseudoSEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9812 { 20770 /* sext.h */, RISCV::SEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
9813 { 20770 /* sext.h */, RISCV::PseudoSEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9814 { 20777 /* sext.w */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
9815 { 20784 /* sf.cdiscard.d.l1 */, RISCV::SF_CDISCARD_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecdiscarddlone, { }, },
9816 { 20784 /* sf.cdiscard.d.l1 */, RISCV::SF_CDISCARD_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecdiscarddlone, { MCK_GPR }, },
9817 { 20801 /* sf.cease */, RISCV::SF_CEASE, Convert_NoOperands, AMFBS_HasVendorXSfcease, { }, },
9818 { 20810 /* sf.cflush.d.l1 */, RISCV::SF_CFLUSH_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecflushdlone, { }, },
9819 { 20810 /* sf.cflush.d.l1 */, RISCV::SF_CFLUSH_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecflushdlone, { MCK_GPR }, },
9820 { 20825 /* sf.mm.e4m3.e4m3 */, RISCV::SF_MM_E4M3_E4M3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9821 { 20841 /* sf.mm.e4m3.e5m2 */, RISCV::SF_MM_E4M3_E5M2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9822 { 20857 /* sf.mm.e5m2.e4m3 */, RISCV::SF_MM_E5M2_E4M3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9823 { 20873 /* sf.mm.e5m2.e5m2 */, RISCV::SF_MM_E5M2_E5M2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9824 { 20889 /* sf.mm.f.f */, RISCV::SF_MM_F_F, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f, { MCK_TRM2, MCK_VR, MCK_VR }, },
9825 { 20899 /* sf.mm.s.s */, RISCV::SF_MM_S_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9826 { 20909 /* sf.mm.s.u */, RISCV::SF_MM_S_U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9827 { 20919 /* sf.mm.u.s */, RISCV::SF_MM_U_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9828 { 20929 /* sf.mm.u.u */, RISCV::SF_MM_U_U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9829 { 20939 /* sf.vc.fv */, RISCV::SF_VC_FV, Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_UImm5, MCK_VR, MCK_FPR32 }, },
9830 { 20948 /* sf.vc.fvv */, RISCV::SF_VC_FVV, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9831 { 20958 /* sf.vc.fvw */, RISCV::SF_VC_FVW, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9832 { 20968 /* sf.vc.i */, RISCV::SF_VC_I, Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_SImm5 }, },
9833 { 20976 /* sf.vc.iv */, RISCV::SF_VC_IV, Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_SImm5 }, },
9834 { 20985 /* sf.vc.ivv */, RISCV::SF_VC_IVV, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9835 { 20995 /* sf.vc.ivw */, RISCV::SF_VC_IVW, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9836 { 21005 /* sf.vc.v.fv */, RISCV::SF_VC_V_FV, Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9837 { 21016 /* sf.vc.v.fvv */, RISCV::SF_VC_V_FVV, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9838 { 21028 /* sf.vc.v.fvw */, RISCV::SF_VC_V_FVW, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9839 { 21040 /* sf.vc.v.i */, RISCV::SF_VC_V_I, Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_SImm5 }, },
9840 { 21050 /* sf.vc.v.iv */, RISCV::SF_VC_V_IV, Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9841 { 21061 /* sf.vc.v.ivv */, RISCV::SF_VC_V_IVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9842 { 21073 /* sf.vc.v.ivw */, RISCV::SF_VC_V_IVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9843 { 21085 /* sf.vc.v.vv */, RISCV::SF_VC_V_VV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9844 { 21096 /* sf.vc.v.vvv */, RISCV::SF_VC_V_VVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9845 { 21108 /* sf.vc.v.vvw */, RISCV::SF_VC_V_VVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9846 { 21120 /* sf.vc.v.x */, RISCV::SF_VC_V_X, Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_GPR }, },
9847 { 21130 /* sf.vc.v.xv */, RISCV::SF_VC_V_XV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9848 { 21141 /* sf.vc.v.xvv */, RISCV::SF_VC_V_XVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9849 { 21153 /* sf.vc.v.xvw */, RISCV::SF_VC_V_XVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9850 { 21165 /* sf.vc.vv */, RISCV::SF_VC_VV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_VR }, },
9851 { 21174 /* sf.vc.vvv */, RISCV::SF_VC_VVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9852 { 21184 /* sf.vc.vvw */, RISCV::SF_VC_VVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9853 { 21194 /* sf.vc.x */, RISCV::SF_VC_X, Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_GPR }, },
9854 { 21202 /* sf.vc.xv */, RISCV::SF_VC_XV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_GPR }, },
9855 { 21211 /* sf.vc.xvv */, RISCV::SF_VC_XVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9856 { 21221 /* sf.vc.xvw */, RISCV::SF_VC_XVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9857 { 21231 /* sf.vfexp.v */, RISCV::SF_VFEXP_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXSfvfexpAny, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9858 { 21242 /* sf.vfexpa.v */, RISCV::SF_VFEXPA_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXSfvfexpa, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9859 { 21254 /* sf.vfnrclip.x.f.qf */, RISCV::SF_VFNRCLIP_X_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9860 { 21273 /* sf.vfnrclip.xu.f.qf */, RISCV::SF_VFNRCLIP_XU_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9861 { 21293 /* sf.vfwmacc.4x4x4 */, RISCV::SF_VFWMACC_4x4x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvfwmaccqqq, { MCK_VR, MCK_VR, MCK_VR }, },
9862 { 21310 /* sf.vlte16 */, RISCV::SF_VLTE16, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9863 { 21320 /* sf.vlte32 */, RISCV::SF_VLTE32, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9864 { 21330 /* sf.vlte64 */, RISCV::SF_VLTE64, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9865 { 21340 /* sf.vlte8 */, RISCV::SF_VLTE8, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9866 { 21349 /* sf.vqmacc.2x8x2 */, RISCV::SF_VQMACC_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9867 { 21365 /* sf.vqmacc.4x8x4 */, RISCV::SF_VQMACC_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9868 { 21381 /* sf.vqmaccsu.2x8x2 */, RISCV::SF_VQMACCSU_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9869 { 21399 /* sf.vqmaccsu.4x8x4 */, RISCV::SF_VQMACCSU_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9870 { 21417 /* sf.vqmaccu.2x8x2 */, RISCV::SF_VQMACCU_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9871 { 21434 /* sf.vqmaccu.4x8x4 */, RISCV::SF_VQMACCU_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9872 { 21451 /* sf.vqmaccus.2x8x2 */, RISCV::SF_VQMACCUS_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9873 { 21469 /* sf.vqmaccus.4x8x4 */, RISCV::SF_VQMACCUS_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9874 { 21487 /* sf.vsettk */, RISCV::SF_VSETTK, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
9875 { 21497 /* sf.vsettm */, RISCV::SF_VSETTM, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
9876 { 21507 /* sf.vsettn */, RISCV::SF_VSETTN, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
9877 { 21517 /* sf.vsettnt */, RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__XSfmmVType1_2, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR, MCK_XSfmmVType }, },
9878 { 21528 /* sf.vste16 */, RISCV::SF_VSTE16, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9879 { 21538 /* sf.vste32 */, RISCV::SF_VSTE32, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9880 { 21548 /* sf.vste64 */, RISCV::SF_VSTE64, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9881 { 21558 /* sf.vste8 */, RISCV::SF_VSTE8, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9882 { 21567 /* sf.vtdiscard */, RISCV::SF_VTDISCARD, Convert_NoOperands, AMFBS_HasVendorXSfmmbase, { }, },
9883 { 21580 /* sf.vtmv.t.v */, RISCV::SF_VTMV_T_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_VR }, },
9884 { 21592 /* sf.vtmv.v.t */, RISCV::SF_VTMV_V_T, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_VR, MCK_GPR }, },
9885 { 21604 /* sf.vtzero.t */, RISCV::SF_VTZERO_T, Convert__Reg1_0, AMFBS_HasVendorXSfmmbase, { MCK_TR }, },
9886 { 21616 /* sfence.inval.ir */, RISCV::SFENCE_INVAL_IR, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
9887 { 21632 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__regX0__regX0, AMFBS_None, { }, },
9888 { 21632 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
9889 { 21632 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9890 { 21643 /* sfence.w.inval */, RISCV::SFENCE_W_INVAL, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
9891 { 21658 /* sgt */, RISCV::SLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9892 { 21662 /* sgtu */, RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9893 { 21667 /* sgtz */, RISCV::SLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9894 { 21672 /* sh */, RISCV::PseudoSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9895 { 21672 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9896 { 21672 /* sh */, RISCV::PseudoQCAccessSH, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9897 { 21672 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9898 { 21672 /* sh */, RISCV::PseudoQCAccessSH, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9899 { 21675 /* sh.aqrl */, RISCV::SH_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9900 { 21683 /* sh.rl */, RISCV::SH_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9901 { 21689 /* sh1add */, RISCV::SH1ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9902 { 21696 /* sh1add.uw */, RISCV::SH1ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9903 { 21706 /* sh2add */, RISCV::SH2ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9904 { 21713 /* sh2add.uw */, RISCV::SH2ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9905 { 21723 /* sh3add */, RISCV::SH3ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9906 { 21730 /* sh3add.uw */, RISCV::SH3ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9907 { 21740 /* sha */, RISCV::SHA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9908 { 21744 /* sha256sig0 */, RISCV::SHA256SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9909 { 21755 /* sha256sig1 */, RISCV::SHA256SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9910 { 21766 /* sha256sum0 */, RISCV::SHA256SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9911 { 21777 /* sha256sum1 */, RISCV::SHA256SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9912 { 21788 /* sha512sig0 */, RISCV::SHA512SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9913 { 21799 /* sha512sig0h */, RISCV::SHA512SIG0H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9914 { 21811 /* sha512sig0l */, RISCV::SHA512SIG0L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9915 { 21823 /* sha512sig1 */, RISCV::SHA512SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9916 { 21834 /* sha512sig1h */, RISCV::SHA512SIG1H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9917 { 21846 /* sha512sig1l */, RISCV::SHA512SIG1L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9918 { 21858 /* sha512sum0 */, RISCV::SHA512SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9919 { 21869 /* sha512sum0r */, RISCV::SHA512SUM0R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9920 { 21881 /* sha512sum1 */, RISCV::SHA512SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9921 { 21892 /* sha512sum1r */, RISCV::SHA512SUM1R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9922 { 21904 /* shar */, RISCV::SHAR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9923 { 21909 /* shl */, RISCV::SHL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9924 { 21913 /* shlr */, RISCV::SHLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9925 { 21918 /* sinval.vma */, RISCV::SINVAL_VMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
9926 { 21929 /* sll */, RISCV::SLL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9927 { 21929 /* sll */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9928 { 21933 /* slli */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9929 { 21938 /* slli.uw */, RISCV::SLLI_UW, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9930 { 21946 /* slliw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9931 { 21952 /* sllw */, RISCV::SLLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9932 { 21952 /* sllw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9933 { 21957 /* slt */, RISCV::SLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9934 { 21957 /* slt */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9935 { 21961 /* slti */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9936 { 21966 /* sltiu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9937 { 21972 /* sltu */, RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9938 { 21972 /* sltu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9939 { 21977 /* sltz */, RISCV::SLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9940 { 21982 /* slx */, RISCV::SLX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9941 { 21986 /* sm3p0 */, RISCV::SM3P0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
9942 { 21992 /* sm3p1 */, RISCV::SM3P1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
9943 { 21998 /* sm4ed */, RISCV::SM4ED, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9944 { 22004 /* sm4ks */, RISCV::SM4KS, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9945 { 22010 /* smt.vfwmadot */, RISCV::VFWMADOT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
9946 { 22023 /* smt.vfwmadot1 */, RISCV::VFWMADOT1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9947 { 22037 /* smt.vfwmadot2 */, RISCV::VFWMADOT2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9948 { 22051 /* smt.vfwmadot3 */, RISCV::VFWMADOT3, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9949 { 22065 /* smt.vmadot */, RISCV::SMT_VMADOT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
9950 { 22065 /* smt.vmadot */, RISCV::VMADOT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_SMTVType }, },
9951 { 22076 /* smt.vmadot.hp */, RISCV::VMADOT_HP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_VR, MCK_UImm3, MCK_SMTVType }, },
9952 { 22090 /* smt.vmadot.sp */, RISCV::VMADOT_SP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2, MCK_SMTVType }, },
9953 { 22104 /* smt.vmadot1 */, RISCV::SMT_VMADOT1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9954 { 22104 /* smt.vmadot1 */, RISCV::VMADOT1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9955 { 22116 /* smt.vmadot1su */, RISCV::SMT_VMADOT1SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9956 { 22116 /* smt.vmadot1su */, RISCV::VMADOT1SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9957 { 22130 /* smt.vmadot1u */, RISCV::SMT_VMADOT1U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9958 { 22130 /* smt.vmadot1u */, RISCV::VMADOT1U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9959 { 22143 /* smt.vmadot1us */, RISCV::SMT_VMADOT1US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9960 { 22143 /* smt.vmadot1us */, RISCV::VMADOT1US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9961 { 22157 /* smt.vmadot2 */, RISCV::SMT_VMADOT2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9962 { 22157 /* smt.vmadot2 */, RISCV::VMADOT2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9963 { 22169 /* smt.vmadot2su */, RISCV::SMT_VMADOT2SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9964 { 22169 /* smt.vmadot2su */, RISCV::VMADOT2SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9965 { 22183 /* smt.vmadot2u */, RISCV::SMT_VMADOT2U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9966 { 22183 /* smt.vmadot2u */, RISCV::VMADOT2U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9967 { 22196 /* smt.vmadot2us */, RISCV::SMT_VMADOT2US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9968 { 22196 /* smt.vmadot2us */, RISCV::VMADOT2US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9969 { 22210 /* smt.vmadot3 */, RISCV::SMT_VMADOT3, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9970 { 22210 /* smt.vmadot3 */, RISCV::VMADOT3, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9971 { 22222 /* smt.vmadot3su */, RISCV::SMT_VMADOT3SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9972 { 22222 /* smt.vmadot3su */, RISCV::VMADOT3SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9973 { 22236 /* smt.vmadot3u */, RISCV::SMT_VMADOT3U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9974 { 22236 /* smt.vmadot3u */, RISCV::VMADOT3U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9975 { 22249 /* smt.vmadot3us */, RISCV::SMT_VMADOT3US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9976 { 22249 /* smt.vmadot3us */, RISCV::VMADOT3US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
9977 { 22263 /* smt.vmadotsu */, RISCV::SMT_VMADOTSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
9978 { 22263 /* smt.vmadotsu */, RISCV::VMADOTSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_SMTVType }, },
9979 { 22276 /* smt.vmadotsu.hp */, RISCV::VMADOTSU_HP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_VR, MCK_UImm3, MCK_SMTVType }, },
9980 { 22292 /* smt.vmadotsu.sp */, RISCV::VMADOTSU_SP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2, MCK_SMTVType }, },
9981 { 22308 /* smt.vmadotu */, RISCV::SMT_VMADOTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
9982 { 22308 /* smt.vmadotu */, RISCV::VMADOTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_SMTVType }, },
9983 { 22320 /* smt.vmadotu.hp */, RISCV::VMADOTU_HP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_VR, MCK_UImm3, MCK_SMTVType }, },
9984 { 22335 /* smt.vmadotu.sp */, RISCV::VMADOTU_SP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2, MCK_SMTVType }, },
9985 { 22350 /* smt.vmadotus */, RISCV::SMT_VMADOTUS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
9986 { 22350 /* smt.vmadotus */, RISCV::VMADOTUS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_SMTVType }, },
9987 { 22363 /* smt.vmadotus.hp */, RISCV::VMADOTUS_HP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_VR, MCK_UImm3, MCK_SMTVType }, },
9988 { 22379 /* smt.vmadotus.sp */, RISCV::VMADOTUS_SP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2, MCK_SMTVType }, },
9989 { 22395 /* smt.vnpack.vv */, RISCV::VNPACK_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_UImm2 }, },
9990 { 22409 /* smt.vnpack4.vv */, RISCV::VNPACK4_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_UImm2 }, },
9991 { 22424 /* smt.vnspack.vv */, RISCV::VNSPACK_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_UImm2 }, },
9992 { 22439 /* smt.vnspack4.vv */, RISCV::VNSPACK4_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_UImm2 }, },
9993 { 22455 /* smt.vpack.vv */, RISCV::VPACK_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2 }, },
9994 { 22468 /* smt.vupack.vv */, RISCV::VUPACK_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2 }, },
9995 { 22482 /* snez */, RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9996 { 22487 /* sra */, RISCV::SRA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9997 { 22487 /* sra */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9998 { 22491 /* srai */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9999 { 22496 /* sraiw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10000 { 22502 /* srari */, RISCV::SRARI_RV32, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10001 { 22502 /* srari */, RISCV::SRARI_RV64, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
10002 { 22508 /* sraw */, RISCV::SRAW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10003 { 22508 /* sraw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10004 { 22513 /* sret */, RISCV::SRET, Convert_NoOperands, AMFBS_None, { }, },
10005 { 22518 /* srl */, RISCV::SRL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10006 { 22518 /* srl */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10007 { 22522 /* srli */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10008 { 22527 /* srliw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10009 { 22533 /* srliy */, RISCV::SRLIY, Convert__Reg1_0__Reg1_1__UImm7EqXLen1_2, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR, MCK_UImm7EqXLen }, },
10010 { 22539 /* srlw */, RISCV::SRLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10011 { 22539 /* srlw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10012 { 22544 /* srx */, RISCV::SRX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10013 { 22548 /* ssamoswap.d */, RISCV::SSAMOSWAP_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10014 { 22560 /* ssamoswap.d.aq */, RISCV::SSAMOSWAP_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10015 { 22575 /* ssamoswap.d.aqrl */, RISCV::SSAMOSWAP_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10016 { 22592 /* ssamoswap.d.rl */, RISCV::SSAMOSWAP_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10017 { 22607 /* ssamoswap.w */, RISCV::SSAMOSWAP_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10018 { 22619 /* ssamoswap.w.aq */, RISCV::SSAMOSWAP_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10019 { 22634 /* ssamoswap.w.aqrl */, RISCV::SSAMOSWAP_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10020 { 22651 /* ssamoswap.w.rl */, RISCV::SSAMOSWAP_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10021 { 22666 /* ssh1sadd */, RISCV::SSH1SADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10022 { 22675 /* ssha */, RISCV::SSHA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10023 { 22680 /* sshar */, RISCV::SSHAR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10024 { 22686 /* sshl */, RISCV::SSHL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10025 { 22691 /* sshlr */, RISCV::SSHLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10026 { 22697 /* sslai */, RISCV::SSLAI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10027 { 22703 /* sspopchk */, RISCV::SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRX1X5 }, },
10028 { 22712 /* sspush */, RISCV::SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRX1X5 }, },
10029 { 22719 /* ssrdp */, RISCV::SSRDP, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRNoX0 }, },
10030 { 22725 /* ssub */, RISCV::SSUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10031 { 22730 /* ssubu */, RISCV::SSUBU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10032 { 22736 /* sub */, RISCV::SUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10033 { 22740 /* subd */, RISCV::SUBD, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
10034 { 22745 /* subw */, RISCV::SUBW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10035 { 22750 /* sw */, RISCV::PseudoSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
10036 { 22750 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
10037 { 22750 /* sw */, RISCV::PseudoQCAccessSW, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
10038 { 22750 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
10039 { 22750 /* sw */, RISCV::PseudoQCAccessSW, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
10040 { 22753 /* sw.aqrl */, RISCV::SW_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10041 { 22761 /* sw.rl */, RISCV::SW_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10042 { 22767 /* tail */, RISCV::PseudoTAIL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
10043 { 22772 /* th.addsl */, RISCV::TH_ADDSL, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadBa, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10044 { 22781 /* th.dcache.call */, RISCV::TH_DCACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10045 { 22796 /* th.dcache.ciall */, RISCV::TH_DCACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10046 { 22812 /* th.dcache.cipa */, RISCV::TH_DCACHE_CIPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10047 { 22827 /* th.dcache.cisw */, RISCV::TH_DCACHE_CISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10048 { 22842 /* th.dcache.civa */, RISCV::TH_DCACHE_CIVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10049 { 22857 /* th.dcache.cpa */, RISCV::TH_DCACHE_CPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10050 { 22871 /* th.dcache.cpal1 */, RISCV::TH_DCACHE_CPAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10051 { 22887 /* th.dcache.csw */, RISCV::TH_DCACHE_CSW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10052 { 22901 /* th.dcache.cva */, RISCV::TH_DCACHE_CVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10053 { 22915 /* th.dcache.cval1 */, RISCV::TH_DCACHE_CVAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10054 { 22931 /* th.dcache.iall */, RISCV::TH_DCACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10055 { 22946 /* th.dcache.ipa */, RISCV::TH_DCACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10056 { 22960 /* th.dcache.isw */, RISCV::TH_DCACHE_ISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10057 { 22974 /* th.dcache.iva */, RISCV::TH_DCACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10058 { 22988 /* th.ext */, RISCV::TH_EXT, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
10059 { 22995 /* th.extu */, RISCV::TH_EXTU, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
10060 { 23003 /* th.ff0 */, RISCV::TH_FF0, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10061 { 23010 /* th.ff1 */, RISCV::TH_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10062 { 23017 /* th.flrd */, RISCV::TH_FLRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10063 { 23025 /* th.flrw */, RISCV::TH_FLRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10064 { 23033 /* th.flurd */, RISCV::TH_FLURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10065 { 23042 /* th.flurw */, RISCV::TH_FLURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10066 { 23051 /* th.fsrd */, RISCV::TH_FSRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10067 { 23059 /* th.fsrw */, RISCV::TH_FSRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10068 { 23067 /* th.fsurd */, RISCV::TH_FSURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10069 { 23076 /* th.fsurw */, RISCV::TH_FSURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10070 { 23085 /* th.icache.iall */, RISCV::TH_ICACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10071 { 23100 /* th.icache.ialls */, RISCV::TH_ICACHE_IALLS, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10072 { 23116 /* th.icache.ipa */, RISCV::TH_ICACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10073 { 23130 /* th.icache.iva */, RISCV::TH_ICACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10074 { 23144 /* th.l2cache.call */, RISCV::TH_L2CACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10075 { 23160 /* th.l2cache.ciall */, RISCV::TH_L2CACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10076 { 23177 /* th.l2cache.iall */, RISCV::TH_L2CACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10077 { 23193 /* th.lbia */, RISCV::TH_LBIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10078 { 23201 /* th.lbib */, RISCV::TH_LBIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10079 { 23209 /* th.lbuia */, RISCV::TH_LBUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10080 { 23218 /* th.lbuib */, RISCV::TH_LBUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10081 { 23227 /* th.ldd */, RISCV::TH_LDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmFour }, },
10082 { 23234 /* th.ldia */, RISCV::TH_LDIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10083 { 23242 /* th.ldib */, RISCV::TH_LDIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10084 { 23250 /* th.lhia */, RISCV::TH_LHIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10085 { 23258 /* th.lhib */, RISCV::TH_LHIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10086 { 23266 /* th.lhuia */, RISCV::TH_LHUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10087 { 23275 /* th.lhuib */, RISCV::TH_LHUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10088 { 23284 /* th.lrb */, RISCV::TH_LRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10089 { 23291 /* th.lrbu */, RISCV::TH_LRBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10090 { 23299 /* th.lrd */, RISCV::TH_LRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10091 { 23306 /* th.lrh */, RISCV::TH_LRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10092 { 23313 /* th.lrhu */, RISCV::TH_LRHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10093 { 23321 /* th.lrw */, RISCV::TH_LRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10094 { 23328 /* th.lrwu */, RISCV::TH_LRWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10095 { 23336 /* th.lurb */, RISCV::TH_LURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10096 { 23344 /* th.lurbu */, RISCV::TH_LURBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10097 { 23353 /* th.lurd */, RISCV::TH_LURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10098 { 23361 /* th.lurh */, RISCV::TH_LURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10099 { 23369 /* th.lurhu */, RISCV::TH_LURHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10100 { 23378 /* th.lurw */, RISCV::TH_LURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10101 { 23386 /* th.lurwu */, RISCV::TH_LURWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10102 { 23395 /* th.lwd */, RISCV::TH_LWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
10103 { 23402 /* th.lwia */, RISCV::TH_LWIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10104 { 23410 /* th.lwib */, RISCV::TH_LWIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10105 { 23418 /* th.lwud */, RISCV::TH_LWUD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
10106 { 23426 /* th.lwuia */, RISCV::TH_LWUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10107 { 23435 /* th.lwuib */, RISCV::TH_LWUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10108 { 23444 /* th.mula */, RISCV::TH_MULA, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10109 { 23452 /* th.mulah */, RISCV::TH_MULAH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10110 { 23461 /* th.mulaw */, RISCV::TH_MULAW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10111 { 23470 /* th.muls */, RISCV::TH_MULS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10112 { 23478 /* th.mulsh */, RISCV::TH_MULSH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10113 { 23487 /* th.mulsw */, RISCV::TH_MULSW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10114 { 23496 /* th.mveqz */, RISCV::TH_MVEQZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10115 { 23505 /* th.mvnez */, RISCV::TH_MVNEZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10116 { 23514 /* th.rev */, RISCV::TH_REV, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10117 { 23521 /* th.revw */, RISCV::TH_REVW, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR }, },
10118 { 23529 /* th.sbia */, RISCV::TH_SBIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10119 { 23537 /* th.sbib */, RISCV::TH_SBIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10120 { 23545 /* th.sdd */, RISCV::TH_SDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmFour }, },
10121 { 23552 /* th.sdia */, RISCV::TH_SDIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10122 { 23560 /* th.sdib */, RISCV::TH_SDIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10123 { 23568 /* th.sfence.vmas */, RISCV::TH_SFENCE_VMAS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadSync, { MCK_GPR, MCK_GPR }, },
10124 { 23583 /* th.shia */, RISCV::TH_SHIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10125 { 23591 /* th.shib */, RISCV::TH_SHIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10126 { 23599 /* th.srb */, RISCV::TH_SRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10127 { 23606 /* th.srd */, RISCV::TH_SRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10128 { 23613 /* th.srh */, RISCV::TH_SRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10129 { 23620 /* th.srri */, RISCV::TH_SRRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10130 { 23628 /* th.srriw */, RISCV::TH_SRRIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10131 { 23637 /* th.srw */, RISCV::TH_SRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10132 { 23644 /* th.surb */, RISCV::TH_SURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10133 { 23652 /* th.surd */, RISCV::TH_SURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10134 { 23660 /* th.surh */, RISCV::TH_SURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10135 { 23668 /* th.surw */, RISCV::TH_SURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10136 { 23676 /* th.swd */, RISCV::TH_SWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
10137 { 23683 /* th.swia */, RISCV::TH_SWIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10138 { 23691 /* th.swib */, RISCV::TH_SWIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10139 { 23699 /* th.sync */, RISCV::TH_SYNC, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10140 { 23707 /* th.sync.i */, RISCV::TH_SYNC_I, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10141 { 23717 /* th.sync.is */, RISCV::TH_SYNC_IS, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10142 { 23728 /* th.sync.s */, RISCV::TH_SYNC_S, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10143 { 23738 /* th.tst */, RISCV::TH_TST, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10144 { 23745 /* th.tstnbz */, RISCV::TH_TSTNBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10145 { 23755 /* th.vmaqa.vv */, RISCV::TH_VMAQA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10146 { 23767 /* th.vmaqa.vx */, RISCV::TH_VMAQA_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10147 { 23779 /* th.vmaqasu.vv */, RISCV::TH_VMAQASU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10148 { 23793 /* th.vmaqasu.vx */, RISCV::TH_VMAQASU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10149 { 23807 /* th.vmaqau.vv */, RISCV::TH_VMAQAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10150 { 23820 /* th.vmaqau.vx */, RISCV::TH_VMAQAU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10151 { 23833 /* th.vmaqaus.vx */, RISCV::TH_VMAQAUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10152 { 23847 /* unimp */, RISCV::UNIMP, Convert_NoOperands, AMFBS_None, { }, },
10153 { 23853 /* unzip */, RISCV::UNZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
10154 { 23859 /* unzip16hp */, RISCV::UNZIP16HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10155 { 23869 /* unzip16p */, RISCV::UNZIP16P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10156 { 23878 /* unzip8hp */, RISCV::UNZIP8HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10157 { 23887 /* unzip8p */, RISCV::UNZIP8P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10158 { 23895 /* usati */, RISCV::USATI_RV32, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10159 { 23895 /* usati */, RISCV::USATI_RV64, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
10160 { 23901 /* v8wmmacc.vv */, RISCV::V8WMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10161 { 23913 /* vaadd.vv */, RISCV::VAADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10162 { 23922 /* vaadd.vx */, RISCV::VAADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10163 { 23931 /* vaaddu.vv */, RISCV::VAADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10164 { 23941 /* vaaddu.vx */, RISCV::VAADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10165 { 23951 /* vabd.vv */, RISCV::VABD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10166 { 23959 /* vabdu.vv */, RISCV::VABDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10167 { 23968 /* vabs.v */, RISCV::VABS_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10168 { 23975 /* vadc.vim */, RISCV::VADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
10169 { 23984 /* vadc.vvm */, RISCV::VADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10170 { 23993 /* vadc.vxm */, RISCV::VADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10171 { 24002 /* vadd.vi */, RISCV::VADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10172 { 24010 /* vadd.vv */, RISCV::VADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10173 { 24018 /* vadd.vx */, RISCV::VADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10174 { 24026 /* vaesdf.vs */, RISCV::VAESDF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10175 { 24036 /* vaesdf.vv */, RISCV::VAESDF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10176 { 24046 /* vaesdm.vs */, RISCV::VAESDM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10177 { 24056 /* vaesdm.vv */, RISCV::VAESDM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10178 { 24066 /* vaesef.vs */, RISCV::VAESEF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10179 { 24076 /* vaesef.vv */, RISCV::VAESEF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10180 { 24086 /* vaesem.vs */, RISCV::VAESEM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10181 { 24096 /* vaesem.vv */, RISCV::VAESEM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10182 { 24106 /* vaeskf1.vi */, RISCV::VAESKF1_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10183 { 24117 /* vaeskf2.vi */, RISCV::VAESKF2_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10184 { 24128 /* vaesz.vs */, RISCV::VAESZ_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10185 { 24137 /* vand.vi */, RISCV::VAND_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10186 { 24145 /* vand.vv */, RISCV::VAND_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10187 { 24153 /* vand.vx */, RISCV::VAND_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10188 { 24161 /* vandn.vv */, RISCV::VANDN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10189 { 24170 /* vandn.vx */, RISCV::VANDN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10190 { 24179 /* vasub.vv */, RISCV::VASUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10191 { 24188 /* vasub.vx */, RISCV::VASUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10192 { 24197 /* vasubu.vv */, RISCV::VASUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10193 { 24207 /* vasubu.vx */, RISCV::VASUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10194 { 24217 /* vbrev.v */, RISCV::VBREV_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10195 { 24225 /* vbrev8.v */, RISCV::VBREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10196 { 24234 /* vclmul.vv */, RISCV::VCLMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10197 { 24244 /* vclmul.vx */, RISCV::VCLMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10198 { 24254 /* vclmulh.vv */, RISCV::VCLMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10199 { 24265 /* vclmulh.vx */, RISCV::VCLMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10200 { 24276 /* vclz.v */, RISCV::VCLZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10201 { 24283 /* vcompress.vm */, RISCV::VCOMPRESS_VM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10202 { 24296 /* vcpop.m */, RISCV::VCPOP_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10203 { 24304 /* vcpop.v */, RISCV::VCPOP_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10204 { 24312 /* vctz.v */, RISCV::VCTZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10205 { 24319 /* vdiv.vv */, RISCV::VDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10206 { 24327 /* vdiv.vx */, RISCV::VDIV_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10207 { 24335 /* vdivu.vv */, RISCV::VDIVU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10208 { 24344 /* vdivu.vx */, RISCV::VDIVU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10209 { 24353 /* vdot4a.vv */, RISCV::VDOT4A_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10210 { 24363 /* vdot4a.vx */, RISCV::VDOT4A_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10211 { 24373 /* vdot4asu.vv */, RISCV::VDOT4ASU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10212 { 24385 /* vdot4asu.vx */, RISCV::VDOT4ASU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10213 { 24397 /* vdot4au.vv */, RISCV::VDOT4AU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10214 { 24408 /* vdot4au.vx */, RISCV::VDOT4AU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10215 { 24419 /* vdot4aus.vx */, RISCV::VDOT4AUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10216 { 24431 /* vf8wimmacc.vv */, RISCV::VF8WIMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10217 { 24445 /* vf8wmmacc.vv */, RISCV::VF8WMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10218 { 24445 /* vf8wmmacc.vv */, RISCV::VF8WMMACC_VV_SCALE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10219 { 24458 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR }, },
10220 { 24458 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10221 { 24466 /* vfadd.vf */, RISCV::VFADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10222 { 24475 /* vfadd.vv */, RISCV::VFADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10223 { 24484 /* vfbdota.vv */, RISCV::VFBDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfbdota32f, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10224 { 24495 /* vfclass.v */, RISCV::VFCLASS_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10225 { 24505 /* vfcvt.f.x.v */, RISCV::VFCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10226 { 24517 /* vfcvt.f.xu.v */, RISCV::VFCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10227 { 24530 /* vfcvt.rtz.x.f.v */, RISCV::VFCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10228 { 24546 /* vfcvt.rtz.xu.f.v */, RISCV::VFCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10229 { 24563 /* vfcvt.x.f.v */, RISCV::VFCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10230 { 24575 /* vfcvt.xu.f.v */, RISCV::VFCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10231 { 24588 /* vfdiv.vf */, RISCV::VFDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10232 { 24597 /* vfdiv.vv */, RISCV::VFDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10233 { 24606 /* vfirst.m */, RISCV::VFIRST_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10234 { 24615 /* vfmacc.vf */, RISCV::VFMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10235 { 24625 /* vfmacc.vv */, RISCV::VFMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10236 { 24635 /* vfmadd.vf */, RISCV::VFMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10237 { 24645 /* vfmadd.vv */, RISCV::VFMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10238 { 24655 /* vfmax.vf */, RISCV::VFMAX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10239 { 24664 /* vfmax.vv */, RISCV::VFMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10240 { 24673 /* vfmerge.vfm */, RISCV::VFMERGE_VFM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskCarryInRegOpOperand }, },
10241 { 24685 /* vfmin.vf */, RISCV::VFMIN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10242 { 24694 /* vfmin.vv */, RISCV::VFMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10243 { 24703 /* vfmmacc.vv */, RISCV::VFMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10244 { 24714 /* vfmsac.vf */, RISCV::VFMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10245 { 24724 /* vfmsac.vv */, RISCV::VFMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10246 { 24734 /* vfmsub.vf */, RISCV::VFMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10247 { 24744 /* vfmsub.vv */, RISCV::VFMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10248 { 24754 /* vfmul.vf */, RISCV::VFMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10249 { 24763 /* vfmul.vv */, RISCV::VFMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10250 { 24772 /* vfmv.f.s */, RISCV::VFMV_F_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_FPR32, MCK_VR }, },
10251 { 24781 /* vfmv.s.f */, RISCV::VFMV_S_F, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32 }, },
10252 { 24790 /* vfmv.v.f */, RISCV::VFMV_V_F, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32 }, },
10253 { 24799 /* vfncvt.f.f.q */, RISCV::VFNCVT_F_F_Q, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10254 { 24812 /* vfncvt.f.f.w */, RISCV::VFNCVT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10255 { 24825 /* vfncvt.f.x.w */, RISCV::VFNCVT_F_X_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10256 { 24838 /* vfncvt.f.xu.w */, RISCV::VFNCVT_F_XU_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10257 { 24852 /* vfncvt.rod.f.f.w */, RISCV::VFNCVT_ROD_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10258 { 24869 /* vfncvt.rtz.x.f.w */, RISCV::VFNCVT_RTZ_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10259 { 24886 /* vfncvt.rtz.xu.f.w */, RISCV::VFNCVT_RTZ_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10260 { 24904 /* vfncvt.sat.f.f.q */, RISCV::VFNCVT_SAT_F_F_Q, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10261 { 24921 /* vfncvt.x.f.w */, RISCV::VFNCVT_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10262 { 24934 /* vfncvt.xu.f.w */, RISCV::VFNCVT_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10263 { 24948 /* vfncvtbf16.f.f.w */, RISCV::VFNCVTBF16_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfminOrZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10264 { 24965 /* vfncvtbf16.sat.f.f.w */, RISCV::VFNCVTBF16_SAT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10265 { 24986 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR }, },
10266 { 24986 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10267 { 24994 /* vfnmacc.vf */, RISCV::VFNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10268 { 25005 /* vfnmacc.vv */, RISCV::VFNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10269 { 25016 /* vfnmadd.vf */, RISCV::VFNMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10270 { 25027 /* vfnmadd.vv */, RISCV::VFNMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10271 { 25038 /* vfnmsac.vf */, RISCV::VFNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10272 { 25049 /* vfnmsac.vv */, RISCV::VFNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10273 { 25060 /* vfnmsub.vf */, RISCV::VFNMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10274 { 25071 /* vfnmsub.vv */, RISCV::VFNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10275 { 25082 /* vfqimmacc.vv */, RISCV::VFQIMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10276 { 25095 /* vfqmmacc.vv */, RISCV::VFQMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10277 { 25095 /* vfqmmacc.vv */, RISCV::VFQMMACC_VV_SCALE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10278 { 25107 /* vfqwbdota.alt.vv */, RISCV::VFQWBDOTA_ALT_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfqwbdota8f, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10279 { 25124 /* vfqwbdota.vv */, RISCV::VFQWBDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfqwbdota8f, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10280 { 25137 /* vfqwdota.alt.vv */, RISCV::VFQWDOTA_ALT_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfqwdota8f, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10281 { 25153 /* vfqwdota.vv */, RISCV::VFQWDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfqwdota8f, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10282 { 25165 /* vfrdiv.vf */, RISCV::VFRDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10283 { 25175 /* vfrec7.v */, RISCV::VFREC7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10284 { 25184 /* vfredmax.vs */, RISCV::VFREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10285 { 25196 /* vfredmin.vs */, RISCV::VFREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10286 { 25208 /* vfredosum.vs */, RISCV::VFREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10287 { 25221 /* vfredusum.vs */, RISCV::VFREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10288 { 25234 /* vfrsqrt7.v */, RISCV::VFRSQRT7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10289 { 25245 /* vfrsub.vf */, RISCV::VFRSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10290 { 25255 /* vfsgnj.vf */, RISCV::VFSGNJ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10291 { 25265 /* vfsgnj.vv */, RISCV::VFSGNJ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10292 { 25275 /* vfsgnjn.vf */, RISCV::VFSGNJN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10293 { 25286 /* vfsgnjn.vv */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10294 { 25297 /* vfsgnjx.vf */, RISCV::VFSGNJX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10295 { 25308 /* vfsgnjx.vv */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10296 { 25319 /* vfslide1down.vf */, RISCV::VFSLIDE1DOWN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10297 { 25335 /* vfslide1up.vf */, RISCV::VFSLIDE1UP_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10298 { 25349 /* vfsqrt.v */, RISCV::VFSQRT_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10299 { 25358 /* vfsub.vf */, RISCV::VFSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10300 { 25367 /* vfsub.vv */, RISCV::VFSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10301 { 25376 /* vfwadd.vf */, RISCV::VFWADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10302 { 25386 /* vfwadd.vv */, RISCV::VFWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10303 { 25396 /* vfwadd.wf */, RISCV::VFWADD_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10304 { 25406 /* vfwadd.wv */, RISCV::VFWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10305 { 25416 /* vfwbdota.vv */, RISCV::VFWBDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfwbdota16bf, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10306 { 25428 /* vfwcvt.f.f.v */, RISCV::VFWCVT_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10307 { 25441 /* vfwcvt.f.x.v */, RISCV::VFWCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10308 { 25454 /* vfwcvt.f.xu.v */, RISCV::VFWCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10309 { 25468 /* vfwcvt.rtz.x.f.v */, RISCV::VFWCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10310 { 25485 /* vfwcvt.rtz.xu.f.v */, RISCV::VFWCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10311 { 25503 /* vfwcvt.x.f.v */, RISCV::VFWCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10312 { 25516 /* vfwcvt.xu.f.v */, RISCV::VFWCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10313 { 25530 /* vfwcvtbf16.f.f.v */, RISCV::VFWCVTBF16_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfminOrZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10314 { 25547 /* vfwdota.vv */, RISCV::VFWDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfwdota16bf, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10315 { 25558 /* vfwimmacc.vv */, RISCV::VFWIMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10316 { 25571 /* vfwmacc.vf */, RISCV::VFWMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10317 { 25582 /* vfwmacc.vv */, RISCV::VFWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10318 { 25593 /* vfwmaccbf16.vf */, RISCV::VFWMACCBF16_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10319 { 25608 /* vfwmaccbf16.vv */, RISCV::VFWMACCBF16_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10320 { 25623 /* vfwmmacc.vv */, RISCV::VFWMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10321 { 25623 /* vfwmmacc.vv */, RISCV::VFWMMACC_VV_SCALE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10322 { 25635 /* vfwmsac.vf */, RISCV::VFWMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10323 { 25646 /* vfwmsac.vv */, RISCV::VFWMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10324 { 25657 /* vfwmul.vf */, RISCV::VFWMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10325 { 25667 /* vfwmul.vv */, RISCV::VFWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10326 { 25677 /* vfwnmacc.vf */, RISCV::VFWNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10327 { 25689 /* vfwnmacc.vv */, RISCV::VFWNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10328 { 25701 /* vfwnmsac.vf */, RISCV::VFWNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10329 { 25713 /* vfwnmsac.vv */, RISCV::VFWNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10330 { 25725 /* vfwredosum.vs */, RISCV::VFWREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10331 { 25739 /* vfwredusum.vs */, RISCV::VFWREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10332 { 25753 /* vfwsub.vf */, RISCV::VFWSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10333 { 25763 /* vfwsub.vv */, RISCV::VFWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10334 { 25773 /* vfwsub.wf */, RISCV::VFWSUB_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10335 { 25783 /* vfwsub.wv */, RISCV::VFWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10336 { 25793 /* vghsh.vs */, RISCV::VGHSH_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkgs, { MCK_VR, MCK_VR, MCK_VR }, },
10337 { 25802 /* vghsh.vv */, RISCV::VGHSH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkg, { MCK_VR, MCK_VR, MCK_VR }, },
10338 { 25811 /* vgmul.vs */, RISCV::VGMUL_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkgs, { MCK_VR, MCK_VR }, },
10339 { 25820 /* vgmul.vv */, RISCV::VGMUL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkg, { MCK_VR, MCK_VR }, },
10340 { 25829 /* vid.v */, RISCV::VID_V, Convert__Reg1_0__RVVMaskRegOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_RVVMaskRegOpOperand }, },
10341 { 25835 /* viota.m */, RISCV::VIOTA_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10342 { 25843 /* vl1r.v */, RISCV::VL1RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10343 { 25850 /* vl1re16.v */, RISCV::VL1RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10344 { 25860 /* vl1re32.v */, RISCV::VL1RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10345 { 25870 /* vl1re64.v */, RISCV::VL1RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10346 { 25880 /* vl1re8.v */, RISCV::VL1RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10347 { 25889 /* vl2r.v */, RISCV::VL2RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10348 { 25896 /* vl2re16.v */, RISCV::VL2RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10349 { 25906 /* vl2re32.v */, RISCV::VL2RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10350 { 25916 /* vl2re64.v */, RISCV::VL2RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10351 { 25926 /* vl2re8.v */, RISCV::VL2RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10352 { 25935 /* vl4r.v */, RISCV::VL4RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10353 { 25942 /* vl4re16.v */, RISCV::VL4RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10354 { 25952 /* vl4re32.v */, RISCV::VL4RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10355 { 25962 /* vl4re64.v */, RISCV::VL4RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10356 { 25972 /* vl4re8.v */, RISCV::VL4RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10357 { 25981 /* vl8r.v */, RISCV::VL8RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10358 { 25988 /* vl8re16.v */, RISCV::VL8RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10359 { 25998 /* vl8re32.v */, RISCV::VL8RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10360 { 26008 /* vl8re64.v */, RISCV::VL8RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10361 { 26018 /* vl8re8.v */, RISCV::VL8RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10362 { 26027 /* vle16.v */, RISCV::VLE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10363 { 26035 /* vle16ff.v */, RISCV::VLE16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10364 { 26045 /* vle32.v */, RISCV::VLE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10365 { 26053 /* vle32ff.v */, RISCV::VLE32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10366 { 26063 /* vle64.v */, RISCV::VLE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10367 { 26071 /* vle64ff.v */, RISCV::VLE64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10368 { 26081 /* vle8.v */, RISCV::VLE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10369 { 26088 /* vle8ff.v */, RISCV::VLE8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10370 { 26097 /* vlm.v */, RISCV::VLM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10371 { 26103 /* vloxei16.v */, RISCV::VLOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10372 { 26114 /* vloxei32.v */, RISCV::VLOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10373 { 26125 /* vloxei64.v */, RISCV::VLOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10374 { 26136 /* vloxei8.v */, RISCV::VLOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10375 { 26146 /* vloxseg2ei16.v */, RISCV::VLOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10376 { 26161 /* vloxseg2ei32.v */, RISCV::VLOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10377 { 26176 /* vloxseg2ei64.v */, RISCV::VLOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10378 { 26191 /* vloxseg2ei8.v */, RISCV::VLOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10379 { 26205 /* vloxseg3ei16.v */, RISCV::VLOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10380 { 26220 /* vloxseg3ei32.v */, RISCV::VLOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10381 { 26235 /* vloxseg3ei64.v */, RISCV::VLOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10382 { 26250 /* vloxseg3ei8.v */, RISCV::VLOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10383 { 26264 /* vloxseg4ei16.v */, RISCV::VLOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10384 { 26279 /* vloxseg4ei32.v */, RISCV::VLOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10385 { 26294 /* vloxseg4ei64.v */, RISCV::VLOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10386 { 26309 /* vloxseg4ei8.v */, RISCV::VLOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10387 { 26323 /* vloxseg5ei16.v */, RISCV::VLOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10388 { 26338 /* vloxseg5ei32.v */, RISCV::VLOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10389 { 26353 /* vloxseg5ei64.v */, RISCV::VLOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10390 { 26368 /* vloxseg5ei8.v */, RISCV::VLOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10391 { 26382 /* vloxseg6ei16.v */, RISCV::VLOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10392 { 26397 /* vloxseg6ei32.v */, RISCV::VLOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10393 { 26412 /* vloxseg6ei64.v */, RISCV::VLOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10394 { 26427 /* vloxseg6ei8.v */, RISCV::VLOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10395 { 26441 /* vloxseg7ei16.v */, RISCV::VLOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10396 { 26456 /* vloxseg7ei32.v */, RISCV::VLOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10397 { 26471 /* vloxseg7ei64.v */, RISCV::VLOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10398 { 26486 /* vloxseg7ei8.v */, RISCV::VLOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10399 { 26500 /* vloxseg8ei16.v */, RISCV::VLOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10400 { 26515 /* vloxseg8ei32.v */, RISCV::VLOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10401 { 26530 /* vloxseg8ei64.v */, RISCV::VLOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10402 { 26545 /* vloxseg8ei8.v */, RISCV::VLOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10403 { 26559 /* vlse16.v */, RISCV::VLSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10404 { 26568 /* vlse32.v */, RISCV::VLSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10405 { 26577 /* vlse64.v */, RISCV::VLSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10406 { 26586 /* vlse8.v */, RISCV::VLSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10407 { 26594 /* vlseg2e16.v */, RISCV::VLSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10408 { 26606 /* vlseg2e16ff.v */, RISCV::VLSEG2E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10409 { 26620 /* vlseg2e32.v */, RISCV::VLSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10410 { 26632 /* vlseg2e32ff.v */, RISCV::VLSEG2E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10411 { 26646 /* vlseg2e64.v */, RISCV::VLSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10412 { 26658 /* vlseg2e64ff.v */, RISCV::VLSEG2E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10413 { 26672 /* vlseg2e8.v */, RISCV::VLSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10414 { 26683 /* vlseg2e8ff.v */, RISCV::VLSEG2E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10415 { 26696 /* vlseg3e16.v */, RISCV::VLSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10416 { 26708 /* vlseg3e16ff.v */, RISCV::VLSEG3E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10417 { 26722 /* vlseg3e32.v */, RISCV::VLSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10418 { 26734 /* vlseg3e32ff.v */, RISCV::VLSEG3E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10419 { 26748 /* vlseg3e64.v */, RISCV::VLSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10420 { 26760 /* vlseg3e64ff.v */, RISCV::VLSEG3E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10421 { 26774 /* vlseg3e8.v */, RISCV::VLSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10422 { 26785 /* vlseg3e8ff.v */, RISCV::VLSEG3E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10423 { 26798 /* vlseg4e16.v */, RISCV::VLSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10424 { 26810 /* vlseg4e16ff.v */, RISCV::VLSEG4E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10425 { 26824 /* vlseg4e32.v */, RISCV::VLSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10426 { 26836 /* vlseg4e32ff.v */, RISCV::VLSEG4E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10427 { 26850 /* vlseg4e64.v */, RISCV::VLSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10428 { 26862 /* vlseg4e64ff.v */, RISCV::VLSEG4E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10429 { 26876 /* vlseg4e8.v */, RISCV::VLSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10430 { 26887 /* vlseg4e8ff.v */, RISCV::VLSEG4E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10431 { 26900 /* vlseg5e16.v */, RISCV::VLSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10432 { 26912 /* vlseg5e16ff.v */, RISCV::VLSEG5E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10433 { 26926 /* vlseg5e32.v */, RISCV::VLSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10434 { 26938 /* vlseg5e32ff.v */, RISCV::VLSEG5E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10435 { 26952 /* vlseg5e64.v */, RISCV::VLSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10436 { 26964 /* vlseg5e64ff.v */, RISCV::VLSEG5E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10437 { 26978 /* vlseg5e8.v */, RISCV::VLSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10438 { 26989 /* vlseg5e8ff.v */, RISCV::VLSEG5E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10439 { 27002 /* vlseg6e16.v */, RISCV::VLSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10440 { 27014 /* vlseg6e16ff.v */, RISCV::VLSEG6E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10441 { 27028 /* vlseg6e32.v */, RISCV::VLSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10442 { 27040 /* vlseg6e32ff.v */, RISCV::VLSEG6E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10443 { 27054 /* vlseg6e64.v */, RISCV::VLSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10444 { 27066 /* vlseg6e64ff.v */, RISCV::VLSEG6E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10445 { 27080 /* vlseg6e8.v */, RISCV::VLSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10446 { 27091 /* vlseg6e8ff.v */, RISCV::VLSEG6E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10447 { 27104 /* vlseg7e16.v */, RISCV::VLSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10448 { 27116 /* vlseg7e16ff.v */, RISCV::VLSEG7E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10449 { 27130 /* vlseg7e32.v */, RISCV::VLSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10450 { 27142 /* vlseg7e32ff.v */, RISCV::VLSEG7E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10451 { 27156 /* vlseg7e64.v */, RISCV::VLSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10452 { 27168 /* vlseg7e64ff.v */, RISCV::VLSEG7E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10453 { 27182 /* vlseg7e8.v */, RISCV::VLSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10454 { 27193 /* vlseg7e8ff.v */, RISCV::VLSEG7E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10455 { 27206 /* vlseg8e16.v */, RISCV::VLSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10456 { 27218 /* vlseg8e16ff.v */, RISCV::VLSEG8E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10457 { 27232 /* vlseg8e32.v */, RISCV::VLSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10458 { 27244 /* vlseg8e32ff.v */, RISCV::VLSEG8E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10459 { 27258 /* vlseg8e64.v */, RISCV::VLSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10460 { 27270 /* vlseg8e64ff.v */, RISCV::VLSEG8E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10461 { 27284 /* vlseg8e8.v */, RISCV::VLSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10462 { 27295 /* vlseg8e8ff.v */, RISCV::VLSEG8E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10463 { 27308 /* vlsseg2e16.v */, RISCV::VLSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10464 { 27321 /* vlsseg2e32.v */, RISCV::VLSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10465 { 27334 /* vlsseg2e64.v */, RISCV::VLSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10466 { 27347 /* vlsseg2e8.v */, RISCV::VLSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10467 { 27359 /* vlsseg3e16.v */, RISCV::VLSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10468 { 27372 /* vlsseg3e32.v */, RISCV::VLSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10469 { 27385 /* vlsseg3e64.v */, RISCV::VLSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10470 { 27398 /* vlsseg3e8.v */, RISCV::VLSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10471 { 27410 /* vlsseg4e16.v */, RISCV::VLSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10472 { 27423 /* vlsseg4e32.v */, RISCV::VLSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10473 { 27436 /* vlsseg4e64.v */, RISCV::VLSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10474 { 27449 /* vlsseg4e8.v */, RISCV::VLSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10475 { 27461 /* vlsseg5e16.v */, RISCV::VLSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10476 { 27474 /* vlsseg5e32.v */, RISCV::VLSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10477 { 27487 /* vlsseg5e64.v */, RISCV::VLSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10478 { 27500 /* vlsseg5e8.v */, RISCV::VLSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10479 { 27512 /* vlsseg6e16.v */, RISCV::VLSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10480 { 27525 /* vlsseg6e32.v */, RISCV::VLSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10481 { 27538 /* vlsseg6e64.v */, RISCV::VLSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10482 { 27551 /* vlsseg6e8.v */, RISCV::VLSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10483 { 27563 /* vlsseg7e16.v */, RISCV::VLSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10484 { 27576 /* vlsseg7e32.v */, RISCV::VLSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10485 { 27589 /* vlsseg7e64.v */, RISCV::VLSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10486 { 27602 /* vlsseg7e8.v */, RISCV::VLSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10487 { 27614 /* vlsseg8e16.v */, RISCV::VLSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10488 { 27627 /* vlsseg8e32.v */, RISCV::VLSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10489 { 27640 /* vlsseg8e64.v */, RISCV::VLSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10490 { 27653 /* vlsseg8e8.v */, RISCV::VLSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10491 { 27665 /* vluxei16.v */, RISCV::VLUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10492 { 27676 /* vluxei32.v */, RISCV::VLUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10493 { 27687 /* vluxei64.v */, RISCV::VLUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10494 { 27698 /* vluxei8.v */, RISCV::VLUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10495 { 27708 /* vluxseg2ei16.v */, RISCV::VLUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10496 { 27723 /* vluxseg2ei32.v */, RISCV::VLUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10497 { 27738 /* vluxseg2ei64.v */, RISCV::VLUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10498 { 27753 /* vluxseg2ei8.v */, RISCV::VLUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10499 { 27767 /* vluxseg3ei16.v */, RISCV::VLUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10500 { 27782 /* vluxseg3ei32.v */, RISCV::VLUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10501 { 27797 /* vluxseg3ei64.v */, RISCV::VLUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10502 { 27812 /* vluxseg3ei8.v */, RISCV::VLUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10503 { 27826 /* vluxseg4ei16.v */, RISCV::VLUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10504 { 27841 /* vluxseg4ei32.v */, RISCV::VLUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10505 { 27856 /* vluxseg4ei64.v */, RISCV::VLUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10506 { 27871 /* vluxseg4ei8.v */, RISCV::VLUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10507 { 27885 /* vluxseg5ei16.v */, RISCV::VLUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10508 { 27900 /* vluxseg5ei32.v */, RISCV::VLUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10509 { 27915 /* vluxseg5ei64.v */, RISCV::VLUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10510 { 27930 /* vluxseg5ei8.v */, RISCV::VLUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10511 { 27944 /* vluxseg6ei16.v */, RISCV::VLUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10512 { 27959 /* vluxseg6ei32.v */, RISCV::VLUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10513 { 27974 /* vluxseg6ei64.v */, RISCV::VLUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10514 { 27989 /* vluxseg6ei8.v */, RISCV::VLUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10515 { 28003 /* vluxseg7ei16.v */, RISCV::VLUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10516 { 28018 /* vluxseg7ei32.v */, RISCV::VLUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10517 { 28033 /* vluxseg7ei64.v */, RISCV::VLUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10518 { 28048 /* vluxseg7ei8.v */, RISCV::VLUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10519 { 28062 /* vluxseg8ei16.v */, RISCV::VLUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10520 { 28077 /* vluxseg8ei32.v */, RISCV::VLUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10521 { 28092 /* vluxseg8ei64.v */, RISCV::VLUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10522 { 28107 /* vluxseg8ei8.v */, RISCV::VLUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10523 { 28121 /* vmacc.vv */, RISCV::VMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10524 { 28130 /* vmacc.vx */, RISCV::VMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10525 { 28139 /* vmadc.vi */, RISCV::VMADC_VI, Convert__Reg1_0__Reg1_1__SImm51_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5 }, },
10526 { 28148 /* vmadc.vim */, RISCV::VMADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
10527 { 28158 /* vmadc.vv */, RISCV::VMADC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10528 { 28167 /* vmadc.vvm */, RISCV::VMADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10529 { 28177 /* vmadc.vx */, RISCV::VMADC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10530 { 28186 /* vmadc.vxm */, RISCV::VMADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10531 { 28196 /* vmadd.vv */, RISCV::VMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10532 { 28205 /* vmadd.vx */, RISCV::VMADD_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10533 { 28214 /* vmand.mm */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10534 { 28223 /* vmandn.mm */, RISCV::VMANDN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10535 { 28233 /* vmax.vv */, RISCV::VMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10536 { 28241 /* vmax.vx */, RISCV::VMAX_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10537 { 28249 /* vmaxu.vv */, RISCV::VMAXU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10538 { 28258 /* vmaxu.vx */, RISCV::VMAXU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10539 { 28267 /* vmclr.m */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VR }, },
10540 { 28275 /* vmerge.vim */, RISCV::VMERGE_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
10541 { 28286 /* vmerge.vvm */, RISCV::VMERGE_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10542 { 28297 /* vmerge.vxm */, RISCV::VMERGE_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10543 { 28308 /* vmfeq.vf */, RISCV::VMFEQ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10544 { 28317 /* vmfeq.vv */, RISCV::VMFEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10545 { 28326 /* vmfge.vf */, RISCV::VMFGE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10546 { 28335 /* vmfge.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10547 { 28344 /* vmfgt.vf */, RISCV::VMFGT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10548 { 28353 /* vmfgt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10549 { 28362 /* vmfle.vf */, RISCV::VMFLE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10550 { 28371 /* vmfle.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10551 { 28380 /* vmflt.vf */, RISCV::VMFLT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10552 { 28389 /* vmflt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10553 { 28398 /* vmfne.vf */, RISCV::VMFNE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10554 { 28407 /* vmfne.vv */, RISCV::VMFNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10555 { 28416 /* vmin.vv */, RISCV::VMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10556 { 28424 /* vmin.vx */, RISCV::VMIN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10557 { 28432 /* vminu.vv */, RISCV::VMINU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10558 { 28441 /* vminu.vx */, RISCV::VMINU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10559 { 28450 /* vmmacc.vv */, RISCV::VMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10560 { 28460 /* vmmv.m */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10561 { 28467 /* vmnand.mm */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10562 { 28477 /* vmnor.mm */, RISCV::VMNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10563 { 28486 /* vmnot.m */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10564 { 28494 /* vmor.mm */, RISCV::VMOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10565 { 28502 /* vmorn.mm */, RISCV::VMORN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10566 { 28511 /* vmsbc.vv */, RISCV::VMSBC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10567 { 28520 /* vmsbc.vvm */, RISCV::VMSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10568 { 28530 /* vmsbc.vx */, RISCV::VMSBC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10569 { 28539 /* vmsbc.vxm */, RISCV::VMSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10570 { 28549 /* vmsbf.m */, RISCV::VMSBF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10571 { 28557 /* vmseq.vi */, RISCV::VMSEQ_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10572 { 28566 /* vmseq.vv */, RISCV::VMSEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10573 { 28575 /* vmseq.vx */, RISCV::VMSEQ_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10574 { 28584 /* vmset.m */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VR }, },
10575 { 28592 /* vmsge.vi */, RISCV::PseudoVMSGE_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10576 { 28601 /* vmsge.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10577 { 28610 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10578 { 28610 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
10579 { 28619 /* vmsgeu.vi */, RISCV::PseudoVMSGEU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10580 { 28629 /* vmsgeu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10581 { 28639 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10582 { 28639 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
10583 { 28649 /* vmsgt.vi */, RISCV::VMSGT_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10584 { 28658 /* vmsgt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10585 { 28667 /* vmsgt.vx */, RISCV::VMSGT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10586 { 28676 /* vmsgtu.vi */, RISCV::VMSGTU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10587 { 28686 /* vmsgtu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10588 { 28696 /* vmsgtu.vx */, RISCV::VMSGTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10589 { 28706 /* vmsif.m */, RISCV::VMSIF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10590 { 28714 /* vmsle.vi */, RISCV::VMSLE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10591 { 28723 /* vmsle.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10592 { 28732 /* vmsle.vx */, RISCV::VMSLE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10593 { 28741 /* vmsleu.vi */, RISCV::VMSLEU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10594 { 28751 /* vmsleu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10595 { 28761 /* vmsleu.vx */, RISCV::VMSLEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10596 { 28771 /* vmslt.vi */, RISCV::PseudoVMSLT_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10597 { 28780 /* vmslt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10598 { 28789 /* vmslt.vx */, RISCV::VMSLT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10599 { 28798 /* vmsltu.vi */, RISCV::PseudoVMSLTU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10600 { 28808 /* vmsltu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10601 { 28818 /* vmsltu.vx */, RISCV::VMSLTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10602 { 28828 /* vmsne.vi */, RISCV::VMSNE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10603 { 28837 /* vmsne.vv */, RISCV::VMSNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10604 { 28846 /* vmsne.vx */, RISCV::VMSNE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10605 { 28855 /* vmsof.m */, RISCV::VMSOF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10606 { 28863 /* vmtl.v */, RISCV::VMTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10607 { 28863 /* vmtl.v */, RISCV::VMTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10608 { 28870 /* vmts.v */, RISCV::VMTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10609 { 28870 /* vmts.v */, RISCV::VMTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10610 { 28877 /* vmttl.v */, RISCV::VMTTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10611 { 28877 /* vmttl.v */, RISCV::VMTTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10612 { 28885 /* vmtts.v */, RISCV::VMTTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10613 { 28885 /* vmtts.v */, RISCV::VMTTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10614 { 28893 /* vmul.vv */, RISCV::VMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10615 { 28901 /* vmul.vx */, RISCV::VMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10616 { 28909 /* vmulh.vv */, RISCV::VMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10617 { 28918 /* vmulh.vx */, RISCV::VMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10618 { 28927 /* vmulhsu.vv */, RISCV::VMULHSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10619 { 28938 /* vmulhsu.vx */, RISCV::VMULHSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10620 { 28949 /* vmulhu.vv */, RISCV::VMULHU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10621 { 28959 /* vmulhu.vx */, RISCV::VMULHU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10622 { 28969 /* vmv.s.x */, RISCV::VMV_S_X, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR }, },
10623 { 28977 /* vmv.v.i */, RISCV::VMV_V_I, Convert__Reg1_0__SImm51_1, AMFBS_HasVInstructions, { MCK_VR, MCK_SImm5 }, },
10624 { 28985 /* vmv.v.v */, RISCV::VMV_V_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10625 { 28993 /* vmv.v.x */, RISCV::VMV_V_X, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR }, },
10626 { 29001 /* vmv.x.s */, RISCV::VMV_X_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR }, },
10627 { 29009 /* vmv1r.v */, RISCV::VMV1R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10628 { 29017 /* vmv2r.v */, RISCV::VMV2R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_VRM2 }, },
10629 { 29025 /* vmv4r.v */, RISCV::VMV4R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_VRM4 }, },
10630 { 29033 /* vmv8r.v */, RISCV::VMV8R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_VRM8 }, },
10631 { 29041 /* vmxnor.mm */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10632 { 29051 /* vmxor.mm */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10633 { 29060 /* vnclip.wi */, RISCV::VNCLIP_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10634 { 29070 /* vnclip.wv */, RISCV::VNCLIP_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10635 { 29080 /* vnclip.wx */, RISCV::VNCLIP_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10636 { 29090 /* vnclipu.wi */, RISCV::VNCLIPU_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10637 { 29101 /* vnclipu.wv */, RISCV::VNCLIPU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10638 { 29112 /* vnclipu.wx */, RISCV::VNCLIPU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10639 { 29123 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10640 { 29123 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10641 { 29135 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10642 { 29135 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10643 { 29142 /* vnmsac.vv */, RISCV::VNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10644 { 29152 /* vnmsac.vx */, RISCV::VNMSAC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10645 { 29162 /* vnmsub.vv */, RISCV::VNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10646 { 29172 /* vnmsub.vx */, RISCV::VNMSUB_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10647 { 29182 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10648 { 29182 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10649 { 29189 /* vnsra.wi */, RISCV::VNSRA_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10650 { 29198 /* vnsra.wv */, RISCV::VNSRA_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10651 { 29207 /* vnsra.wx */, RISCV::VNSRA_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10652 { 29216 /* vnsrl.wi */, RISCV::VNSRL_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10653 { 29225 /* vnsrl.wv */, RISCV::VNSRL_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10654 { 29234 /* vnsrl.wx */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10655 { 29243 /* vor.vi */, RISCV::VOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10656 { 29250 /* vor.vv */, RISCV::VOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10657 { 29257 /* vor.vx */, RISCV::VOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10658 { 29264 /* vpaire.vv */, RISCV::VPAIRE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10659 { 29274 /* vpairo.vv */, RISCV::VPAIRO_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10660 { 29284 /* vqmmacc.vv */, RISCV::VQMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10661 { 29295 /* vqwbdotas.vv */, RISCV::VQWBDOTAS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10662 { 29308 /* vqwbdotau.vv */, RISCV::VQWBDOTAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10663 { 29321 /* vqwdotas.vv */, RISCV::VQWDOTAS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10664 { 29333 /* vqwdotau.vv */, RISCV::VQWDOTAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10665 { 29345 /* vredand.vs */, RISCV::VREDAND_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10666 { 29356 /* vredmax.vs */, RISCV::VREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10667 { 29367 /* vredmaxu.vs */, RISCV::VREDMAXU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10668 { 29379 /* vredmin.vs */, RISCV::VREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10669 { 29390 /* vredminu.vs */, RISCV::VREDMINU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10670 { 29402 /* vredor.vs */, RISCV::VREDOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10671 { 29412 /* vredsum.vs */, RISCV::VREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10672 { 29423 /* vredxor.vs */, RISCV::VREDXOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10673 { 29434 /* vrem.vv */, RISCV::VREM_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10674 { 29442 /* vrem.vx */, RISCV::VREM_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10675 { 29450 /* vremu.vv */, RISCV::VREMU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10676 { 29459 /* vremu.vx */, RISCV::VREMU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10677 { 29468 /* vrev8.v */, RISCV::VREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10678 { 29476 /* vrgather.vi */, RISCV::VRGATHER_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10679 { 29488 /* vrgather.vv */, RISCV::VRGATHER_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10680 { 29500 /* vrgather.vx */, RISCV::VRGATHER_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10681 { 29512 /* vrgatherei16.vv */, RISCV::VRGATHEREI16_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10682 { 29528 /* vrol.vv */, RISCV::VROL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10683 { 29536 /* vrol.vx */, RISCV::VROL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10684 { 29544 /* vror.vi */, RISCV::VROR_VI, Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_UImm6, MCK_RVVMaskRegOpOperand }, },
10685 { 29552 /* vror.vv */, RISCV::VROR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10686 { 29560 /* vror.vx */, RISCV::VROR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10687 { 29568 /* vrsub.vi */, RISCV::VRSUB_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10688 { 29577 /* vrsub.vx */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10689 { 29586 /* vs1r.v */, RISCV::VS1R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10690 { 29593 /* vs2r.v */, RISCV::VS2R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10691 { 29600 /* vs4r.v */, RISCV::VS4R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10692 { 29607 /* vs8r.v */, RISCV::VS8R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10693 { 29614 /* vsadd.vi */, RISCV::VSADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10694 { 29623 /* vsadd.vv */, RISCV::VSADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10695 { 29632 /* vsadd.vx */, RISCV::VSADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10696 { 29641 /* vsaddu.vi */, RISCV::VSADDU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10697 { 29651 /* vsaddu.vv */, RISCV::VSADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10698 { 29661 /* vsaddu.vx */, RISCV::VSADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10699 { 29671 /* vsbc.vvm */, RISCV::VSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10700 { 29680 /* vsbc.vxm */, RISCV::VSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10701 { 29689 /* vse16.v */, RISCV::VSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10702 { 29697 /* vse32.v */, RISCV::VSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10703 { 29705 /* vse64.v */, RISCV::VSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10704 { 29713 /* vse8.v */, RISCV::VSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10705 { 29720 /* vsetivli */, RISCV::VSETIVLI, Convert__Reg1_0__UImm51_1__VTypeI101_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_UImm5, MCK_VTypeI10 }, },
10706 { 29729 /* vsetvl */, RISCV::VSETVL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10707 { 29736 /* vsetvli */, RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__VTypeI111_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_VTypeI11 }, },
10708 { 29744 /* vsext.vf2 */, RISCV::VSEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10709 { 29754 /* vsext.vf4 */, RISCV::VSEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10710 { 29764 /* vsext.vf8 */, RISCV::VSEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10711 { 29774 /* vsha2ch.vv */, RISCV::VSHA2CH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknha, { MCK_VR, MCK_VR, MCK_VR }, },
10712 { 29785 /* vsha2cl.vv */, RISCV::VSHA2CL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknha, { MCK_VR, MCK_VR, MCK_VR }, },
10713 { 29796 /* vsha2ms.vv */, RISCV::VSHA2MS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknha, { MCK_VR, MCK_VR, MCK_VR }, },
10714 { 29807 /* vslide1down.vx */, RISCV::VSLIDE1DOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10715 { 29822 /* vslide1up.vx */, RISCV::VSLIDE1UP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10716 { 29835 /* vslidedown.vi */, RISCV::VSLIDEDOWN_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10717 { 29849 /* vslidedown.vx */, RISCV::VSLIDEDOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10718 { 29863 /* vslideup.vi */, RISCV::VSLIDEUP_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10719 { 29875 /* vslideup.vx */, RISCV::VSLIDEUP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10720 { 29887 /* vsll.vi */, RISCV::VSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10721 { 29895 /* vsll.vv */, RISCV::VSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10722 { 29903 /* vsll.vx */, RISCV::VSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10723 { 29911 /* vsm.v */, RISCV::VSM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10724 { 29917 /* vsm3c.vi */, RISCV::VSM3C_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksh, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10725 { 29926 /* vsm3me.vv */, RISCV::VSM3ME_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZvksh, { MCK_VR, MCK_VR, MCK_VR }, },
10726 { 29936 /* vsm4k.vi */, RISCV::VSM4K_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10727 { 29945 /* vsm4r.vs */, RISCV::VSM4R_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR }, },
10728 { 29954 /* vsm4r.vv */, RISCV::VSM4R_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR }, },
10729 { 29963 /* vsmul.vv */, RISCV::VSMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10730 { 29972 /* vsmul.vx */, RISCV::VSMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10731 { 29981 /* vsoxei16.v */, RISCV::VSOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10732 { 29992 /* vsoxei32.v */, RISCV::VSOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10733 { 30003 /* vsoxei64.v */, RISCV::VSOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10734 { 30014 /* vsoxei8.v */, RISCV::VSOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10735 { 30024 /* vsoxseg2ei16.v */, RISCV::VSOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10736 { 30039 /* vsoxseg2ei32.v */, RISCV::VSOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10737 { 30054 /* vsoxseg2ei64.v */, RISCV::VSOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10738 { 30069 /* vsoxseg2ei8.v */, RISCV::VSOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10739 { 30083 /* vsoxseg3ei16.v */, RISCV::VSOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10740 { 30098 /* vsoxseg3ei32.v */, RISCV::VSOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10741 { 30113 /* vsoxseg3ei64.v */, RISCV::VSOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10742 { 30128 /* vsoxseg3ei8.v */, RISCV::VSOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10743 { 30142 /* vsoxseg4ei16.v */, RISCV::VSOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10744 { 30157 /* vsoxseg4ei32.v */, RISCV::VSOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10745 { 30172 /* vsoxseg4ei64.v */, RISCV::VSOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10746 { 30187 /* vsoxseg4ei8.v */, RISCV::VSOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10747 { 30201 /* vsoxseg5ei16.v */, RISCV::VSOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10748 { 30216 /* vsoxseg5ei32.v */, RISCV::VSOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10749 { 30231 /* vsoxseg5ei64.v */, RISCV::VSOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10750 { 30246 /* vsoxseg5ei8.v */, RISCV::VSOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10751 { 30260 /* vsoxseg6ei16.v */, RISCV::VSOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10752 { 30275 /* vsoxseg6ei32.v */, RISCV::VSOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10753 { 30290 /* vsoxseg6ei64.v */, RISCV::VSOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10754 { 30305 /* vsoxseg6ei8.v */, RISCV::VSOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10755 { 30319 /* vsoxseg7ei16.v */, RISCV::VSOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10756 { 30334 /* vsoxseg7ei32.v */, RISCV::VSOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10757 { 30349 /* vsoxseg7ei64.v */, RISCV::VSOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10758 { 30364 /* vsoxseg7ei8.v */, RISCV::VSOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10759 { 30378 /* vsoxseg8ei16.v */, RISCV::VSOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10760 { 30393 /* vsoxseg8ei32.v */, RISCV::VSOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10761 { 30408 /* vsoxseg8ei64.v */, RISCV::VSOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10762 { 30423 /* vsoxseg8ei8.v */, RISCV::VSOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10763 { 30437 /* vsra.vi */, RISCV::VSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10764 { 30445 /* vsra.vv */, RISCV::VSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10765 { 30453 /* vsra.vx */, RISCV::VSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10766 { 30461 /* vsrl.vi */, RISCV::VSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10767 { 30469 /* vsrl.vv */, RISCV::VSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10768 { 30477 /* vsrl.vx */, RISCV::VSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10769 { 30485 /* vsse16.v */, RISCV::VSSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10770 { 30494 /* vsse32.v */, RISCV::VSSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10771 { 30503 /* vsse64.v */, RISCV::VSSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10772 { 30512 /* vsse8.v */, RISCV::VSSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10773 { 30520 /* vsseg2e16.v */, RISCV::VSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10774 { 30532 /* vsseg2e32.v */, RISCV::VSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10775 { 30544 /* vsseg2e64.v */, RISCV::VSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10776 { 30556 /* vsseg2e8.v */, RISCV::VSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10777 { 30567 /* vsseg3e16.v */, RISCV::VSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10778 { 30579 /* vsseg3e32.v */, RISCV::VSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10779 { 30591 /* vsseg3e64.v */, RISCV::VSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10780 { 30603 /* vsseg3e8.v */, RISCV::VSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10781 { 30614 /* vsseg4e16.v */, RISCV::VSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10782 { 30626 /* vsseg4e32.v */, RISCV::VSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10783 { 30638 /* vsseg4e64.v */, RISCV::VSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10784 { 30650 /* vsseg4e8.v */, RISCV::VSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10785 { 30661 /* vsseg5e16.v */, RISCV::VSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10786 { 30673 /* vsseg5e32.v */, RISCV::VSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10787 { 30685 /* vsseg5e64.v */, RISCV::VSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10788 { 30697 /* vsseg5e8.v */, RISCV::VSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10789 { 30708 /* vsseg6e16.v */, RISCV::VSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10790 { 30720 /* vsseg6e32.v */, RISCV::VSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10791 { 30732 /* vsseg6e64.v */, RISCV::VSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10792 { 30744 /* vsseg6e8.v */, RISCV::VSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10793 { 30755 /* vsseg7e16.v */, RISCV::VSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10794 { 30767 /* vsseg7e32.v */, RISCV::VSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10795 { 30779 /* vsseg7e64.v */, RISCV::VSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10796 { 30791 /* vsseg7e8.v */, RISCV::VSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10797 { 30802 /* vsseg8e16.v */, RISCV::VSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10798 { 30814 /* vsseg8e32.v */, RISCV::VSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10799 { 30826 /* vsseg8e64.v */, RISCV::VSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10800 { 30838 /* vsseg8e8.v */, RISCV::VSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10801 { 30849 /* vssra.vi */, RISCV::VSSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10802 { 30858 /* vssra.vv */, RISCV::VSSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10803 { 30867 /* vssra.vx */, RISCV::VSSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10804 { 30876 /* vssrl.vi */, RISCV::VSSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10805 { 30885 /* vssrl.vv */, RISCV::VSSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10806 { 30894 /* vssrl.vx */, RISCV::VSSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10807 { 30903 /* vssseg2e16.v */, RISCV::VSSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10808 { 30916 /* vssseg2e32.v */, RISCV::VSSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10809 { 30929 /* vssseg2e64.v */, RISCV::VSSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10810 { 30942 /* vssseg2e8.v */, RISCV::VSSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10811 { 30954 /* vssseg3e16.v */, RISCV::VSSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10812 { 30967 /* vssseg3e32.v */, RISCV::VSSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10813 { 30980 /* vssseg3e64.v */, RISCV::VSSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10814 { 30993 /* vssseg3e8.v */, RISCV::VSSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10815 { 31005 /* vssseg4e16.v */, RISCV::VSSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10816 { 31018 /* vssseg4e32.v */, RISCV::VSSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10817 { 31031 /* vssseg4e64.v */, RISCV::VSSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10818 { 31044 /* vssseg4e8.v */, RISCV::VSSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10819 { 31056 /* vssseg5e16.v */, RISCV::VSSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10820 { 31069 /* vssseg5e32.v */, RISCV::VSSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10821 { 31082 /* vssseg5e64.v */, RISCV::VSSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10822 { 31095 /* vssseg5e8.v */, RISCV::VSSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10823 { 31107 /* vssseg6e16.v */, RISCV::VSSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10824 { 31120 /* vssseg6e32.v */, RISCV::VSSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10825 { 31133 /* vssseg6e64.v */, RISCV::VSSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10826 { 31146 /* vssseg6e8.v */, RISCV::VSSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10827 { 31158 /* vssseg7e16.v */, RISCV::VSSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10828 { 31171 /* vssseg7e32.v */, RISCV::VSSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10829 { 31184 /* vssseg7e64.v */, RISCV::VSSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10830 { 31197 /* vssseg7e8.v */, RISCV::VSSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10831 { 31209 /* vssseg8e16.v */, RISCV::VSSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10832 { 31222 /* vssseg8e32.v */, RISCV::VSSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10833 { 31235 /* vssseg8e64.v */, RISCV::VSSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10834 { 31248 /* vssseg8e8.v */, RISCV::VSSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10835 { 31260 /* vssub.vv */, RISCV::VSSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10836 { 31269 /* vssub.vx */, RISCV::VSSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10837 { 31278 /* vssubu.vv */, RISCV::VSSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10838 { 31288 /* vssubu.vx */, RISCV::VSSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10839 { 31298 /* vsub.vv */, RISCV::VSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10840 { 31306 /* vsub.vx */, RISCV::VSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10841 { 31314 /* vsuxei16.v */, RISCV::VSUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10842 { 31325 /* vsuxei32.v */, RISCV::VSUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10843 { 31336 /* vsuxei64.v */, RISCV::VSUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10844 { 31347 /* vsuxei8.v */, RISCV::VSUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10845 { 31357 /* vsuxseg2ei16.v */, RISCV::VSUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10846 { 31372 /* vsuxseg2ei32.v */, RISCV::VSUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10847 { 31387 /* vsuxseg2ei64.v */, RISCV::VSUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10848 { 31402 /* vsuxseg2ei8.v */, RISCV::VSUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10849 { 31416 /* vsuxseg3ei16.v */, RISCV::VSUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10850 { 31431 /* vsuxseg3ei32.v */, RISCV::VSUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10851 { 31446 /* vsuxseg3ei64.v */, RISCV::VSUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10852 { 31461 /* vsuxseg3ei8.v */, RISCV::VSUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10853 { 31475 /* vsuxseg4ei16.v */, RISCV::VSUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10854 { 31490 /* vsuxseg4ei32.v */, RISCV::VSUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10855 { 31505 /* vsuxseg4ei64.v */, RISCV::VSUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10856 { 31520 /* vsuxseg4ei8.v */, RISCV::VSUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10857 { 31534 /* vsuxseg5ei16.v */, RISCV::VSUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10858 { 31549 /* vsuxseg5ei32.v */, RISCV::VSUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10859 { 31564 /* vsuxseg5ei64.v */, RISCV::VSUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10860 { 31579 /* vsuxseg5ei8.v */, RISCV::VSUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10861 { 31593 /* vsuxseg6ei16.v */, RISCV::VSUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10862 { 31608 /* vsuxseg6ei32.v */, RISCV::VSUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10863 { 31623 /* vsuxseg6ei64.v */, RISCV::VSUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10864 { 31638 /* vsuxseg6ei8.v */, RISCV::VSUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10865 { 31652 /* vsuxseg7ei16.v */, RISCV::VSUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10866 { 31667 /* vsuxseg7ei32.v */, RISCV::VSUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10867 { 31682 /* vsuxseg7ei64.v */, RISCV::VSUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10868 { 31697 /* vsuxseg7ei8.v */, RISCV::VSUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10869 { 31711 /* vsuxseg8ei16.v */, RISCV::VSUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10870 { 31726 /* vsuxseg8ei32.v */, RISCV::VSUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10871 { 31741 /* vsuxseg8ei64.v */, RISCV::VSUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10872 { 31756 /* vsuxseg8ei8.v */, RISCV::VSUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10873 { 31770 /* vt.maskc */, RISCV::VT_MASKC, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10874 { 31779 /* vt.maskcn */, RISCV::VT_MASKCN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10875 { 31789 /* vunzipe.v */, RISCV::VUNZIPE_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10876 { 31799 /* vunzipo.v */, RISCV::VUNZIPO_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10877 { 31809 /* vwabda.vv */, RISCV::VWABDA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10878 { 31819 /* vwabdau.vv */, RISCV::VWABDAU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10879 { 31830 /* vwadd.vv */, RISCV::VWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10880 { 31839 /* vwadd.vx */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10881 { 31848 /* vwadd.wv */, RISCV::VWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10882 { 31857 /* vwadd.wx */, RISCV::VWADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10883 { 31866 /* vwaddu.vv */, RISCV::VWADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10884 { 31876 /* vwaddu.vx */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10885 { 31886 /* vwaddu.wv */, RISCV::VWADDU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10886 { 31896 /* vwaddu.wx */, RISCV::VWADDU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10887 { 31906 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10888 { 31906 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10889 { 31918 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10890 { 31918 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10891 { 31931 /* vwmacc.vv */, RISCV::VWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10892 { 31941 /* vwmacc.vx */, RISCV::VWMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10893 { 31951 /* vwmaccsu.vv */, RISCV::VWMACCSU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10894 { 31963 /* vwmaccsu.vx */, RISCV::VWMACCSU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10895 { 31975 /* vwmaccu.vv */, RISCV::VWMACCU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10896 { 31986 /* vwmaccu.vx */, RISCV::VWMACCU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10897 { 31997 /* vwmaccus.vx */, RISCV::VWMACCUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10898 { 32009 /* vwmmacc.vv */, RISCV::VWMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10899 { 32020 /* vwmul.vv */, RISCV::VWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10900 { 32029 /* vwmul.vx */, RISCV::VWMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10901 { 32038 /* vwmulsu.vv */, RISCV::VWMULSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10902 { 32049 /* vwmulsu.vx */, RISCV::VWMULSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10903 { 32060 /* vwmulu.vv */, RISCV::VWMULU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10904 { 32070 /* vwmulu.vx */, RISCV::VWMULU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10905 { 32080 /* vwredsum.vs */, RISCV::VWREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10906 { 32092 /* vwredsumu.vs */, RISCV::VWREDSUMU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10907 { 32105 /* vwsll.vi */, RISCV::VWSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10908 { 32114 /* vwsll.vv */, RISCV::VWSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10909 { 32123 /* vwsll.vx */, RISCV::VWSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10910 { 32132 /* vwsub.vv */, RISCV::VWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10911 { 32141 /* vwsub.vx */, RISCV::VWSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10912 { 32150 /* vwsub.wv */, RISCV::VWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10913 { 32159 /* vwsub.wx */, RISCV::VWSUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10914 { 32168 /* vwsubu.vv */, RISCV::VWSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10915 { 32178 /* vwsubu.vx */, RISCV::VWSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10916 { 32188 /* vwsubu.wv */, RISCV::VWSUBU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10917 { 32198 /* vwsubu.wx */, RISCV::VWSUBU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10918 { 32208 /* vxor.vi */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10919 { 32216 /* vxor.vv */, RISCV::VXOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10920 { 32224 /* vxor.vx */, RISCV::VXOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10921 { 32232 /* vzext.vf2 */, RISCV::VZEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10922 { 32242 /* vzext.vf4 */, RISCV::VZEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10923 { 32252 /* vzext.vf8 */, RISCV::VZEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10924 { 32262 /* vzip.vv */, RISCV::VZIP_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10925 { 32270 /* wadd */, RISCV::WADD, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10926 { 32275 /* wadda */, RISCV::WADDA, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10927 { 32281 /* waddau */, RISCV::WADDAU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10928 { 32288 /* waddu */, RISCV::WADDU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10929 { 32294 /* wfi */, RISCV::WFI, Convert_NoOperands, AMFBS_None, { }, },
10930 { 32298 /* wmacc */, RISCV::WMACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10931 { 32304 /* wmaccsu */, RISCV::WMACCSU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10932 { 32312 /* wmaccu */, RISCV::WMACCU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10933 { 32319 /* wmul */, RISCV::WMUL, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10934 { 32324 /* wmulsu */, RISCV::WMULSU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10935 { 32331 /* wmulu */, RISCV::WMULU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10936 { 32337 /* wrs.nto */, RISCV::WRS_NTO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
10937 { 32345 /* wrs.sto */, RISCV::WRS_STO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
10938 { 32353 /* wsla */, RISCV::WSLA, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10939 { 32358 /* wslai */, RISCV::WSLAI, Convert__GPRPairRV321_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm6 }, },
10940 { 32364 /* wsll */, RISCV::WSLL, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10941 { 32369 /* wslli */, RISCV::WSLLI, Convert__GPRPairRV321_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm6 }, },
10942 { 32375 /* wsub */, RISCV::WSUB, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10943 { 32380 /* wsuba */, RISCV::WSUBA, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10944 { 32386 /* wsubau */, RISCV::WSUBAU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10945 { 32393 /* wsubu */, RISCV::WSUBU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10946 { 32399 /* wzip16p */, RISCV::WZIP16P, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10947 { 32407 /* wzip8p */, RISCV::WZIP8P, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10948 { 32414 /* xnor */, RISCV::XNOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10949 { 32419 /* xor */, RISCV::XOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10950 { 32419 /* xor */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10951 { 32423 /* xori */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10952 { 32428 /* xperm4 */, RISCV::XPERM4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10953 { 32435 /* xperm8 */, RISCV::XPERM8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10954 { 32442 /* yadd */, RISCV::YADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPRNoX0 }, },
10955 { 32442 /* yadd */, RISCV::YADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_SImm12LO }, },
10956 { 32447 /* yaddi */, RISCV::YADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_SImm12LO }, },
10957 { 32453 /* yaddrw */, RISCV::YADDRW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
10958 { 32460 /* yamask */, RISCV::YAMASK, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_GPR }, },
10959 { 32467 /* ybaser */, RISCV::YBASER, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10960 { 32474 /* ybld */, RISCV::YBLD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YGPR }, },
10961 { 32479 /* ybndsrw */, RISCV::YBNDSRW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
10962 { 32487 /* ybndsw */, RISCV::YBNDSW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
10963 { 32487 /* ybndsw */, RISCV::YBNDSWI, Convert__Reg1_0__Reg1_1__YBNDSWImm1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YBNDSWImm }, },
10964 { 32494 /* ybndswi */, RISCV::YBNDSWI, Convert__Reg1_0__Reg1_1__YBNDSWImm1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YBNDSWImm }, },
10965 { 32502 /* yeq */, RISCV::YEQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR, MCK_YGPR }, },
10966 { 32506 /* yhir */, RISCV::SRLIY, Convert__Reg1_0__Reg1_1__imm_95_64, AMFBS_HasStdExtY_IsRV64, { MCK_GPR, MCK_YGPR }, },
10967 { 32506 /* yhir */, RISCV::SRLIY, Convert__Reg1_0__Reg1_1__imm_95_32, AMFBS_HasStdExtY_IsRV32, { MCK_GPR, MCK_YGPR }, },
10968 { 32511 /* ylenr */, RISCV::YLENR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10969 { 32517 /* ymv */, RISCV::YMV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR }, },
10970 { 32521 /* ypermc */, RISCV::YPERMC, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
10971 { 32528 /* ypermr */, RISCV::YPERMR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10972 { 32535 /* yss */, RISCV::YSS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR, MCK_YGPR }, },
10973 { 32539 /* ysunseal */, RISCV::YSUNSEAL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YGPR }, },
10974 { 32548 /* ytagr */, RISCV::YTAGR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10975 { 32554 /* ytopr */, RISCV::YTOPR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10976 { 32560 /* ytyper */, RISCV::YTYPER, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10977 { 32567 /* zext.b */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__imm_95_255, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10978 { 32574 /* zext.h */, RISCV::ZEXT_H_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
10979 { 32574 /* zext.h */, RISCV::ZEXT_H_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR }, },
10980 { 32574 /* zext.h */, RISCV::PseudoZEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10981 { 32581 /* zext.w */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR }, },
10982 { 32581 /* zext.w */, RISCV::PseudoZEXT_W, Convert__Reg1_0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
10983 { 32588 /* zip */, RISCV::ZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
10984 { 32592 /* zip16hp */, RISCV::ZIP16HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10985 { 32600 /* zip16p */, RISCV::ZIP16P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10986 { 32607 /* zip8hp */, RISCV::ZIP8HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10987 { 32614 /* zip8p */, RISCV::ZIP8P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10988};
10989
10990#include "llvm/Support/Debug.h"
10991#include "llvm/Support/Format.h"
10992
10993unsigned RISCVAsmParser::
10994MatchInstructionImpl(const OperandVector &Operands,
10995 MCInst &Inst,
10996 SmallVectorImpl<NearMissInfo> *NearMisses,
10997 bool matchingInlineAsm, unsigned VariantID) {
10998 // Get the current feature set.
10999 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
11000
11001 // Get the instruction mnemonic, which is the first token.
11002 StringRef Mnemonic = ((RISCVOperand &)*Operands[0]).getToken();
11003
11004 // Process all MnemonicAliases to remap the mnemonic.
11005 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
11006
11007 SmallBitVector OptionalOperandsMask(9);
11008 // Find the appropriate table for this asm variant.
11009 const MatchEntry *Start, *End;
11010 switch (VariantID) {
11011 default: llvm_unreachable("invalid variant!");
11012 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
11013 }
11014 // Search the table.
11015 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
11016
11017 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
11018 std::distance(MnemonicRange.first, MnemonicRange.second) <<
11019 " encodings with mnemonic '" << Mnemonic << "'\n");
11020
11021 // Return a more specific error code if no mnemonics match.
11022 if (MnemonicRange.first == MnemonicRange.second)
11023 return Match_MnemonicFail;
11024
11025 // First operand near-miss of each opcode that mismatched in
11026 // more than one operand. Used only if no opcode yields a
11027 // near-miss of its own (see below).
11028 SmallVector<NearMissInfo, 4> MultiMismatchFallback;
11029
11030 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
11031 it != ie; ++it) {
11032 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
11033 bool HasRequiredFeatures =
11034 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
11035 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
11036 << MII.getName(it->Opcode) << "\n");
11037 // Some state to record ways in which this instruction did not match.
11038 NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();
11039 NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();
11040 NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();
11041 NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();
11042 bool MultipleInvalidOperands = false;
11043 // equal_range guarantees that instruction mnemonic matches.
11044 assert(Mnemonic == it->getMnemonic());
11045 OptionalOperandsMask.reset(0, 9);
11046 unsigned ActualIdx = 1;
11047 for (unsigned FormalIdx = 0; FormalIdx != 8; ++FormalIdx) {
11048 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
11049 DEBUG_WITH_TYPE("asm-matcher",
11050 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
11051 << " against actual operand at index " << ActualIdx);
11052 if (ActualIdx < Operands.size())
11053 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
11054 Operands[ActualIdx]->print(dbgs(), getContext().getAsmInfo()); dbgs() << "): ");
11055 else
11056 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
11057 if (ActualIdx >= Operands.size()) {
11058 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
11059 bool ThisOperandValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
11060 if (!ThisOperandValid) {
11061 if (!OperandNearMiss) {
11062 // Record info about match failure for later use.
11063 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "recording too-few-operands near miss\n");
11064 OperandNearMiss =
11065 NearMissInfo::getTooFewOperands(Formal, it->Opcode);
11066 } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {
11067 // If more than one operand is invalid, give up on this match entry.
11068 DEBUG_WITH_TYPE(
11069 "asm-matcher",
11070 dbgs() << "second invalid operand, giving up on this opcode\n");
11071 MultipleInvalidOperands = true;
11072 break;
11073 }
11074 } else {
11075 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "but formal operand not required\n");
11076 if (isSubclass(Formal, OptionalMatchClass)) {
11077 OptionalOperandsMask.set(FormalIdx + 1);
11078 }
11079 }
11080 continue;
11081 }
11082 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
11083 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
11084 if (Diag == Match_Success) {
11085 DEBUG_WITH_TYPE("asm-matcher",
11086 dbgs() << "match success using generic matcher\n");
11087 ++ActualIdx;
11088 continue;
11089 }
11090 // If the generic handler indicates an invalid operand
11091 // failure, check for a special case.
11092 if (Diag != Match_Success) {
11093 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
11094 if (TargetDiag == Match_Success) {
11095 DEBUG_WITH_TYPE("asm-matcher",
11096 dbgs() << "match success using target matcher\n");
11097 ++ActualIdx;
11098 continue;
11099 }
11100 // If the target matcher returned a specific error code use
11101 // that, else use the one from the generic matcher.
11102 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
11103 Diag = TargetDiag;
11104 }
11105 // If current formal operand wasn't matched and it is optional
11106 // then try to match next formal operand
11107 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
11108 OptionalOperandsMask.set(FormalIdx + 1);
11109 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
11110 continue;
11111 }
11112 if (!OperandNearMiss) {
11113 // If this is the first invalid operand we have seen, record some
11114 // information about it.
11115 DEBUG_WITH_TYPE(
11116 "asm-matcher",
11117 dbgs()
11118 << "operand match failed, recording near-miss with diag code "
11119 << Diag << "\n");
11120 OperandNearMiss =
11121 NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);
11122 ++ActualIdx;
11123 } else {
11124 // If more than one operand is invalid, give up on this match entry.
11125 DEBUG_WITH_TYPE(
11126 "asm-matcher",
11127 dbgs() << "second operand mismatch, skipping this opcode\n");
11128 MultipleInvalidOperands = true;
11129 break;
11130 }
11131 }
11132
11133 // Reject surplus operands as one more operand mismatch.
11134 if (!MultipleInvalidOperands && ActualIdx < Operands.size()) {
11135 if (!OperandNearMiss) {
11136 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "too many operands, recording near-miss at index "
11137 << ActualIdx << "\n");
11138 OperandNearMiss = NearMissInfo::getMissedOperand(
11139 Match_InvalidOperand, InvalidMatchClass, it->Opcode, ActualIdx);
11140 } else {
11141 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "too many operands after an earlier mismatch, skipping this opcode\n");
11142 MultipleInvalidOperands = true;
11143 }
11144 }
11145
11146 if (MultipleInvalidOperands) {
11147 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11148 "operand mismatches, ignoring "
11149 "this opcode\n");
11150 // Too many invalid operands to report a single near-miss;
11151 // keep the first one as a fallback in case no opcode
11152 // matches more closely.
11153 if (OperandNearMiss)
11154 MultiMismatchFallback.push_back(OperandNearMiss);
11155 continue;
11156 }
11157 if (!HasRequiredFeatures) {
11158 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
11159 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
11160 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
11161 if (NewMissingFeatures[I])
11162 dbgs() << ' ' << I;
11163 dbgs() << "\n");
11164 FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);
11165 }
11166
11167 Inst.clear();
11168
11169 Inst.setOpcode(it->Opcode);
11170 // We have a potential match but have not rendered the operands.
11171 // Check the target predicate to handle any context sensitive
11172 // constraints.
11173 // For example, Ties that are referenced multiple times must be
11174 // checked here to ensure the input is the same for each match
11175 // constraints. If we leave it any later the ties will have been
11176 // canonicalized
11177 unsigned MatchResult;
11178 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
11179 Inst.clear();
11180 DEBUG_WITH_TYPE(
11181 "asm-matcher",
11182 dbgs() << "Early target match predicate failed with diag code "
11183 << MatchResult << "\n");
11184 EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
11185 }
11186
11187 // If we did not successfully match the operands, then we can't convert to
11188 // an MCInst, so bail out on this instruction variant now.
11189 if (OperandNearMiss) {
11190 // If the operand mismatch was the only problem, report it as a near-miss.
11191 if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) {
11192 DEBUG_WITH_TYPE(
11193 "asm-matcher",
11194 dbgs()
11195 << "Opcode result: one mismatched operand, adding near-miss\n");
11196 NearMisses->push_back(OperandNearMiss);
11197 } else {
11198 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11199 "types of mismatch, so not "
11200 "reporting near-miss\n");
11201 }
11202 continue;
11203 }
11204
11205 unsigned DefaultsOffset[9] = { 0 };
11206 assert(OptionalOperandsMask.size() == 9);
11207 for (unsigned i = 0, NumDefaults = 0; i < 8; ++i) {
11208 NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
11209 DefaultsOffset[i + 1] = NumDefaults;
11210 }
11211
11212 if (matchingInlineAsm) {
11213 convertToMapAndConstraints(it->ConvertFn, Operands);
11214 return Match_Success;
11215 }
11216
11217 // We have selected a definite instruction, convert the parsed
11218 // operands into the appropriate MCInst.
11219 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,
11220 OptionalOperandsMask, DefaultsOffset);
11221
11222 // We have a potential match. Check the target predicate to
11223 // handle any context sensitive constraints.
11224 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
11225 DEBUG_WITH_TYPE("asm-matcher",
11226 dbgs() << "Target match predicate failed with diag code "
11227 << MatchResult << "\n");
11228 Inst.clear();
11229 LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
11230 }
11231
11232 int NumNearMisses = ((int)(bool)OperandNearMiss +
11233 (int)(bool)FeaturesNearMiss +
11234 (int)(bool)EarlyPredicateNearMiss +
11235 (int)(bool)LatePredicateNearMiss);
11236 if (NumNearMisses == 1) {
11237 // We had exactly one type of near-miss, so add that to the list.
11238 assert(!OperandNearMiss && "OperandNearMiss was handled earlier");
11239 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: found one type of "
11240 "mismatch, so reporting a "
11241 "near-miss\n");
11242 if (NearMisses && FeaturesNearMiss)
11243 NearMisses->push_back(FeaturesNearMiss);
11244 else if (NearMisses && EarlyPredicateNearMiss)
11245 NearMisses->push_back(EarlyPredicateNearMiss);
11246 else if (NearMisses && LatePredicateNearMiss)
11247 NearMisses->push_back(LatePredicateNearMiss);
11248
11249 continue;
11250 } else if (NumNearMisses > 1) {
11251 // This instruction missed in more than one way, so ignore it.
11252 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11253 "types of mismatch, so not "
11254 "reporting near-miss\n");
11255 continue;
11256 }
11257 DEBUG_WITH_TYPE(
11258 "asm-matcher",
11259 dbgs() << "Opcode result: complete match, selecting this opcode\n");
11260 return Match_Success;
11261 }
11262
11263 // No instruction variants matched exactly. If nothing produced
11264 // a near-miss, fall back to the multi-mismatch list so we can
11265 // still give a specific diagnostic rather than a generic
11266 // "invalid instruction".
11267 if (NearMisses && NearMisses->empty())
11268 NearMisses->append(MultiMismatchFallback.begin(),
11269 MultiMismatchFallback.end());
11270 return Match_NearMisses;
11271}
11272
11273namespace {
11274 struct OperandMatchEntry {
11275 uint16_t Mnemonic;
11276 uint8_t OperandMask;
11277 uint16_t Class;
11278 uint8_t RequiredFeaturesIdx;
11279
11280 StringRef getMnemonic() const {
11281 return StringRef(MnemonicTable + Mnemonic + 1,
11282 MnemonicTable[Mnemonic]);
11283 }
11284 };
11285
11286 // Predicate for searching for an opcode.
11287 struct LessOpcodeOperand {
11288 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
11289 return LHS.getMnemonic() < RHS;
11290 }
11291 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
11292 return LHS < RHS.getMnemonic();
11293 }
11294 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
11295 return LHS.getMnemonic() < RHS.getMnemonic();
11296 }
11297 };
11298} // end anonymous namespace
11299
11300static const OperandMatchEntry OperandMatchTable[2125] = {
11301 /* Operand List Mnemonic, Mask, Operand Class, Features */
11302 { 0 /* .insn_b */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11303 { 8 /* .insn_ca */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11304 { 17 /* .insn_cb */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11305 { 26 /* .insn_ci */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11306 { 35 /* .insn_ciw */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11307 { 45 /* .insn_cj */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11308 { 54 /* .insn_cl */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11309 { 54 /* .insn_cl */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11310 { 63 /* .insn_cr */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11311 { 72 /* .insn_cs */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11312 { 72 /* .insn_cs */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11313 { 81 /* .insn_css */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11314 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11315 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11316 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11317 { 99 /* .insn_j */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11318 { 99 /* .insn_j */, 4 /* 2 */, MCK_BareSImm21Lsb0, AMFBS_None },
11319 { 107 /* .insn_qc.eai */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11320 { 120 /* .insn_qc.eb */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11321 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11322 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11323 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11324 { 144 /* .insn_qc.ej */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11325 { 156 /* .insn_qc.es */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11326 { 156 /* .insn_qc.es */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11327 { 168 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11328 { 168 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11329 { 176 /* .insn_r4 */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11330 { 185 /* .insn_s */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11331 { 185 /* .insn_s */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11332 { 193 /* .insn_sb */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11333 { 202 /* .insn_u */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11334 { 210 /* .insn_uj */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11335 { 210 /* .insn_uj */, 4 /* 2 */, MCK_BareSImm21Lsb0, AMFBS_None },
11336 { 239 /* add */, 8 /* 3 */, MCK_TPRelAddSymbol, AMFBS_None },
11337 { 250 /* addd */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11338 { 370 /* aif.amoaddg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11339 { 384 /* aif.amoaddg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11340 { 398 /* aif.amoaddl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11341 { 412 /* aif.amoaddl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11342 { 426 /* aif.amoandg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11343 { 440 /* aif.amoandg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11344 { 454 /* aif.amoandl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11345 { 468 /* aif.amoandl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11346 { 482 /* aif.amocmpswapg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11347 { 500 /* aif.amocmpswapg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11348 { 518 /* aif.amocmpswapl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11349 { 536 /* aif.amocmpswapl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11350 { 554 /* aif.amomaxg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11351 { 568 /* aif.amomaxg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11352 { 582 /* aif.amomaxl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11353 { 596 /* aif.amomaxl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11354 { 610 /* aif.amomaxug.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11355 { 625 /* aif.amomaxug.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11356 { 640 /* aif.amomaxul.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11357 { 655 /* aif.amomaxul.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11358 { 670 /* aif.amoming.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11359 { 684 /* aif.amoming.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11360 { 698 /* aif.amominl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11361 { 712 /* aif.amominl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11362 { 726 /* aif.amominug.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11363 { 741 /* aif.amominug.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11364 { 756 /* aif.amominul.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11365 { 771 /* aif.amominul.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11366 { 786 /* aif.amoorg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11367 { 799 /* aif.amoorg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11368 { 812 /* aif.amoorl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11369 { 825 /* aif.amoorl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11370 { 838 /* aif.amoswapg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11371 { 853 /* aif.amoswapg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11372 { 868 /* aif.amoswapl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11373 { 883 /* aif.amoswapl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11374 { 898 /* aif.amoxorg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11375 { 912 /* aif.amoxorg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11376 { 926 /* aif.amoxorl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11377 { 940 /* aif.amoxorl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11378 { 1047 /* aif.fadd.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11379 { 1072 /* aif.famoaddg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11380 { 1088 /* aif.famoaddl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11381 { 1104 /* aif.famoandg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11382 { 1120 /* aif.famoandl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11383 { 1136 /* aif.famomaxg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11384 { 1152 /* aif.famomaxg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11385 { 1168 /* aif.famomaxl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11386 { 1184 /* aif.famomaxl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11387 { 1200 /* aif.famomaxug.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11388 { 1217 /* aif.famomaxul.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11389 { 1234 /* aif.famoming.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11390 { 1250 /* aif.famoming.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11391 { 1266 /* aif.famominl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11392 { 1282 /* aif.famominl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11393 { 1298 /* aif.famominug.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11394 { 1315 /* aif.famominul.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11395 { 1332 /* aif.famoorg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11396 { 1347 /* aif.famoorl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11397 { 1362 /* aif.famoswapg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11398 { 1379 /* aif.famoswapl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11399 { 1396 /* aif.famoxorg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11400 { 1412 /* aif.famoxorl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11401 { 1637 /* aif.fcvt.ps.pw */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11402 { 1652 /* aif.fcvt.ps.pwu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11403 { 1801 /* aif.fcvt.pw.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11404 { 1816 /* aif.fcvt.pwu.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11405 { 1977 /* aif.fdiv.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11406 { 2060 /* aif.fg32b.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11407 { 2073 /* aif.fg32h.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11408 { 2086 /* aif.fg32w.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11409 { 2099 /* aif.fgb.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11410 { 2110 /* aif.fgbg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11411 { 2122 /* aif.fgbl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11412 { 2134 /* aif.fgh.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11413 { 2145 /* aif.fghg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11414 { 2157 /* aif.fghl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11415 { 2169 /* aif.fgw.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11416 { 2180 /* aif.fgwg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11417 { 2192 /* aif.fgwl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11418 { 2352 /* aif.fmadd.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11419 { 2439 /* aif.fmsub.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11420 { 2464 /* aif.fmul.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11421 { 2531 /* aif.fnmadd.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11422 { 2545 /* aif.fnmsub.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11423 { 2671 /* aif.fround.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11424 { 2724 /* aif.fsc32b.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11425 { 2738 /* aif.fsc32h.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11426 { 2752 /* aif.fsc32w.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11427 { 2766 /* aif.fscb.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11428 { 2778 /* aif.fscbg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11429 { 2791 /* aif.fscbl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11430 { 2804 /* aif.fsch.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11431 { 2816 /* aif.fschg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11432 { 2829 /* aif.fschl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11433 { 2842 /* aif.fscw.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11434 { 2854 /* aif.fscwg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11435 { 2867 /* aif.fscwl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11436 { 3055 /* aif.fsub.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11437 { 3268 /* aif.sbg */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11438 { 3276 /* aif.sbl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11439 { 3284 /* aif.shg */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11440 { 3292 /* aif.shl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11441 { 3300 /* amoadd.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11442 { 3309 /* amoadd.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11443 { 3321 /* amoadd.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11444 { 3335 /* amoadd.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11445 { 3347 /* amoadd.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11446 { 3356 /* amoadd.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11447 { 3368 /* amoadd.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11448 { 3382 /* amoadd.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11449 { 3394 /* amoadd.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11450 { 3403 /* amoadd.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11451 { 3415 /* amoadd.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11452 { 3429 /* amoadd.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11453 { 3441 /* amoadd.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11454 { 3450 /* amoadd.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11455 { 3462 /* amoadd.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11456 { 3476 /* amoadd.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11457 { 3488 /* amoand.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11458 { 3497 /* amoand.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11459 { 3509 /* amoand.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11460 { 3523 /* amoand.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11461 { 3535 /* amoand.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11462 { 3544 /* amoand.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11463 { 3556 /* amoand.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11464 { 3570 /* amoand.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11465 { 3582 /* amoand.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11466 { 3591 /* amoand.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11467 { 3603 /* amoand.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11468 { 3617 /* amoand.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11469 { 3629 /* amoand.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11470 { 3638 /* amoand.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11471 { 3650 /* amoand.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11472 { 3664 /* amoand.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11473 { 3676 /* amocas.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11474 { 3685 /* amocas.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11475 { 3697 /* amocas.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11476 { 3711 /* amocas.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11477 { 3723 /* amocas.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11478 { 3723 /* amocas.d */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11479 { 3723 /* amocas.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11480 { 3732 /* amocas.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11481 { 3732 /* amocas.d.aq */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11482 { 3732 /* amocas.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11483 { 3744 /* amocas.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11484 { 3744 /* amocas.d.aqrl */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11485 { 3744 /* amocas.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11486 { 3758 /* amocas.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11487 { 3758 /* amocas.d.rl */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11488 { 3758 /* amocas.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11489 { 3770 /* amocas.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11490 { 3779 /* amocas.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11491 { 3791 /* amocas.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11492 { 3805 /* amocas.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11493 { 3817 /* amocas.q */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11494 { 3817 /* amocas.q */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11495 { 3826 /* amocas.q.aq */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11496 { 3826 /* amocas.q.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11497 { 3838 /* amocas.q.aqrl */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11498 { 3838 /* amocas.q.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11499 { 3852 /* amocas.q.rl */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11500 { 3852 /* amocas.q.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11501 { 3864 /* amocas.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11502 { 3873 /* amocas.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11503 { 3885 /* amocas.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11504 { 3899 /* amocas.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11505 { 3911 /* amomax.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11506 { 3920 /* amomax.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11507 { 3932 /* amomax.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11508 { 3946 /* amomax.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11509 { 3958 /* amomax.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11510 { 3967 /* amomax.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11511 { 3979 /* amomax.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11512 { 3993 /* amomax.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11513 { 4005 /* amomax.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11514 { 4014 /* amomax.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11515 { 4026 /* amomax.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11516 { 4040 /* amomax.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11517 { 4052 /* amomax.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11518 { 4061 /* amomax.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11519 { 4073 /* amomax.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11520 { 4087 /* amomax.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11521 { 4099 /* amomaxu.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11522 { 4109 /* amomaxu.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11523 { 4122 /* amomaxu.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11524 { 4137 /* amomaxu.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11525 { 4150 /* amomaxu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11526 { 4160 /* amomaxu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11527 { 4173 /* amomaxu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11528 { 4188 /* amomaxu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11529 { 4201 /* amomaxu.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11530 { 4211 /* amomaxu.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11531 { 4224 /* amomaxu.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11532 { 4239 /* amomaxu.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11533 { 4252 /* amomaxu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11534 { 4262 /* amomaxu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11535 { 4275 /* amomaxu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11536 { 4290 /* amomaxu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11537 { 4303 /* amomin.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11538 { 4312 /* amomin.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11539 { 4324 /* amomin.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11540 { 4338 /* amomin.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11541 { 4350 /* amomin.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11542 { 4359 /* amomin.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11543 { 4371 /* amomin.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11544 { 4385 /* amomin.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11545 { 4397 /* amomin.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11546 { 4406 /* amomin.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11547 { 4418 /* amomin.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11548 { 4432 /* amomin.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11549 { 4444 /* amomin.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11550 { 4453 /* amomin.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11551 { 4465 /* amomin.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11552 { 4479 /* amomin.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11553 { 4491 /* amominu.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11554 { 4501 /* amominu.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11555 { 4514 /* amominu.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11556 { 4529 /* amominu.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11557 { 4542 /* amominu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11558 { 4552 /* amominu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11559 { 4565 /* amominu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11560 { 4580 /* amominu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11561 { 4593 /* amominu.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11562 { 4603 /* amominu.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11563 { 4616 /* amominu.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11564 { 4631 /* amominu.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11565 { 4644 /* amominu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11566 { 4654 /* amominu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11567 { 4667 /* amominu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11568 { 4682 /* amominu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11569 { 4695 /* amoor.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11570 { 4703 /* amoor.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11571 { 4714 /* amoor.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11572 { 4727 /* amoor.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11573 { 4738 /* amoor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11574 { 4746 /* amoor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11575 { 4757 /* amoor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11576 { 4770 /* amoor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11577 { 4781 /* amoor.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11578 { 4789 /* amoor.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11579 { 4800 /* amoor.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11580 { 4813 /* amoor.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11581 { 4824 /* amoor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11582 { 4832 /* amoor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11583 { 4843 /* amoor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11584 { 4856 /* amoor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11585 { 4867 /* amoswap.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11586 { 4877 /* amoswap.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11587 { 4890 /* amoswap.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11588 { 4905 /* amoswap.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11589 { 4918 /* amoswap.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11590 { 4928 /* amoswap.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11591 { 4941 /* amoswap.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11592 { 4956 /* amoswap.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11593 { 4969 /* amoswap.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11594 { 4979 /* amoswap.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11595 { 4992 /* amoswap.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11596 { 5007 /* amoswap.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11597 { 5020 /* amoswap.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11598 { 5030 /* amoswap.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11599 { 5043 /* amoswap.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11600 { 5058 /* amoswap.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11601 { 5071 /* amoxor.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11602 { 5080 /* amoxor.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11603 { 5092 /* amoxor.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11604 { 5106 /* amoxor.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11605 { 5118 /* amoxor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11606 { 5127 /* amoxor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11607 { 5139 /* amoxor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11608 { 5153 /* amoxor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11609 { 5165 /* amoxor.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11610 { 5174 /* amoxor.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11611 { 5186 /* amoxor.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11612 { 5200 /* amoxor.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11613 { 5212 /* amoxor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11614 { 5221 /* amoxor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11615 { 5233 /* amoxor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11616 { 5247 /* amoxor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11617 { 5588 /* c.lbu */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11618 { 5588 /* c.lbu */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11619 { 5594 /* c.ld */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11620 { 5594 /* c.ld */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11621 { 5599 /* c.ldsp */, 1 /* 0 */, MCK_GPRPairNoX0RV32, AMFBS_HasStdExtZclsd_IsRV32 },
11622 { 5599 /* c.ldsp */, 1 /* 0 */, MCK_GPRPairNoX0RV32, AMFBS_HasStdExtZclsd_IsRV32 },
11623 { 5606 /* c.lh */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11624 { 5606 /* c.lh */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11625 { 5611 /* c.lhu */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11626 { 5611 /* c.lhu */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11627 { 5628 /* c.lw */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11628 { 5628 /* c.lw */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11629 { 5774 /* c.sb */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11630 { 5774 /* c.sb */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11631 { 5779 /* c.sd */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11632 { 5779 /* c.sd */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11633 { 5784 /* c.sdsp */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11634 { 5784 /* c.sdsp */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11635 { 5809 /* c.sh */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11636 { 5809 /* c.sh */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11637 { 5895 /* c.sw */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11638 { 5895 /* c.sw */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11639 { 5948 /* call */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
11640 { 5948 /* call */, 2 /* 1 */, MCK_CallSymbol, AMFBS_None },
11641 { 5953 /* cbo.clean */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
11642 { 5963 /* cbo.flush */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
11643 { 5973 /* cbo.inval */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
11644 { 5983 /* cbo.zero */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicboz },
11645 { 6064 /* cm.pop */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11646 { 6064 /* cm.pop */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
11647 { 6071 /* cm.popret */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11648 { 6071 /* cm.popret */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
11649 { 6081 /* cm.popretz */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11650 { 6081 /* cm.popretz */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
11651 { 6092 /* cm.push */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasStdExtZcmp },
11652 { 6092 /* cm.push */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11653 { 6111 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11654 { 6111 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11655 { 6116 /* csrci */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11656 { 6122 /* csrr */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11657 { 6127 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11658 { 6127 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11659 { 6133 /* csrrci */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11660 { 6140 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11661 { 6140 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11662 { 6146 /* csrrsi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11663 { 6153 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11664 { 6153 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11665 { 6159 /* csrrwi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11666 { 6166 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11667 { 6166 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11668 { 6171 /* csrsi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11669 { 6177 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11670 { 6177 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11671 { 6182 /* csrwi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11672 { 7942 /* cv.elw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXCVelw_IsRV32 },
11673 { 8146 /* cv.lb */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11674 { 8152 /* cv.lbu */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11675 { 8159 /* cv.lh */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11676 { 8165 /* cv.lhu */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11677 { 8172 /* cv.lw */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11678 { 8821 /* cv.sb */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11679 { 9091 /* cv.sh */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11680 { 9706 /* cv.sw */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11681 { 9838 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11682 { 9838 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11683 { 9845 /* fabs.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11684 { 9859 /* fabs.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11685 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11686 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11687 { 9866 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11688 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11689 { 9866 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11690 { 9873 /* fadd.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11691 { 9873 /* fadd.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11692 { 9873 /* fadd.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11693 { 9880 /* fadd.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11694 { 9887 /* fadd.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11695 { 9887 /* fadd.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11696 { 9887 /* fadd.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11697 { 9894 /* fclass.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11698 { 9894 /* fclass.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11699 { 9903 /* fclass.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11700 { 9921 /* fclass.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11701 { 9930 /* fcvt.bf16.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfbfmin },
11702 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin_HasStdExtD },
11703 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11704 { 9942 /* fcvt.d.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11705 { 9942 /* fcvt.d.h */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11706 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11707 { 9942 /* fcvt.d.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11708 { 9942 /* fcvt.d.h */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11709 { 9951 /* fcvt.d.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11710 { 9951 /* fcvt.d.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11711 { 9951 /* fcvt.d.l */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11712 { 9960 /* fcvt.d.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11713 { 9960 /* fcvt.d.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11714 { 9960 /* fcvt.d.lu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11715 { 9970 /* fcvt.d.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11716 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
11717 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
11718 { 9979 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
11719 { 9979 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11720 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
11721 { 9979 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
11722 { 9979 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11723 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
11724 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
11725 { 9988 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11726 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
11727 { 9988 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11728 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
11729 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
11730 { 9997 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11731 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
11732 { 9997 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11733 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfhmin_HasStdExtD },
11734 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11735 { 10007 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11736 { 10007 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11737 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11738 { 10007 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11739 { 10007 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11740 { 10016 /* fcvt.h.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11741 { 10016 /* fcvt.h.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11742 { 10016 /* fcvt.h.l */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11743 { 10025 /* fcvt.h.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11744 { 10025 /* fcvt.h.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11745 { 10025 /* fcvt.h.lu */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11746 { 10035 /* fcvt.h.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfhmin },
11747 { 10035 /* fcvt.h.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin },
11748 { 10035 /* fcvt.h.s */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
11749 { 10035 /* fcvt.h.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
11750 { 10044 /* fcvt.h.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11751 { 10044 /* fcvt.h.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11752 { 10044 /* fcvt.h.w */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11753 { 10053 /* fcvt.h.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11754 { 10053 /* fcvt.h.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11755 { 10053 /* fcvt.h.wu */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11756 { 10063 /* fcvt.l.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11757 { 10063 /* fcvt.l.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11758 { 10063 /* fcvt.l.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11759 { 10072 /* fcvt.l.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11760 { 10072 /* fcvt.l.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11761 { 10072 /* fcvt.l.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11762 { 10081 /* fcvt.l.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ_IsRV64 },
11763 { 10090 /* fcvt.l.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11764 { 10090 /* fcvt.l.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11765 { 10090 /* fcvt.l.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11766 { 10099 /* fcvt.lu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11767 { 10099 /* fcvt.lu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11768 { 10099 /* fcvt.lu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11769 { 10109 /* fcvt.lu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11770 { 10109 /* fcvt.lu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11771 { 10109 /* fcvt.lu.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11772 { 10119 /* fcvt.lu.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ_IsRV64 },
11773 { 10129 /* fcvt.lu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11774 { 10129 /* fcvt.lu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11775 { 10129 /* fcvt.lu.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11776 { 10139 /* fcvt.q.d */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11777 { 10148 /* fcvt.q.l */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ_IsRV64 },
11778 { 10157 /* fcvt.q.lu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ_IsRV64 },
11779 { 10167 /* fcvt.q.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11780 { 10176 /* fcvt.q.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11781 { 10185 /* fcvt.q.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11782 { 10195 /* fcvt.s.bf16 */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfbfmin },
11783 { 10207 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11784 { 10207 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11785 { 10207 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
11786 { 10207 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11787 { 10207 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11788 { 10207 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
11789 { 10207 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11790 { 10216 /* fcvt.s.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin },
11791 { 10216 /* fcvt.s.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin },
11792 { 10216 /* fcvt.s.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
11793 { 10216 /* fcvt.s.h */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
11794 { 10225 /* fcvt.s.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11795 { 10225 /* fcvt.s.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11796 { 10225 /* fcvt.s.l */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11797 { 10234 /* fcvt.s.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11798 { 10234 /* fcvt.s.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11799 { 10234 /* fcvt.s.lu */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11800 { 10244 /* fcvt.s.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11801 { 10253 /* fcvt.s.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11802 { 10253 /* fcvt.s.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11803 { 10253 /* fcvt.s.w */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11804 { 10262 /* fcvt.s.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11805 { 10262 /* fcvt.s.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11806 { 10262 /* fcvt.s.wu */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11807 { 10272 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11808 { 10272 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11809 { 10272 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11810 { 10272 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11811 { 10272 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11812 { 10281 /* fcvt.w.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11813 { 10281 /* fcvt.w.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11814 { 10281 /* fcvt.w.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11815 { 10290 /* fcvt.w.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11816 { 10299 /* fcvt.w.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11817 { 10299 /* fcvt.w.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11818 { 10299 /* fcvt.w.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11819 { 10308 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11820 { 10308 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11821 { 10308 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11822 { 10308 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11823 { 10308 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11824 { 10318 /* fcvt.wu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11825 { 10318 /* fcvt.wu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11826 { 10318 /* fcvt.wu.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11827 { 10328 /* fcvt.wu.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11828 { 10338 /* fcvt.wu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11829 { 10338 /* fcvt.wu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11830 { 10338 /* fcvt.wu.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11831 { 10348 /* fcvtmod.w.d */, 4 /* 2 */, MCK_RTZArg, AMFBS_HasStdExtZfa_HasStdExtD },
11832 { 10360 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11833 { 10360 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11834 { 10360 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11835 { 10360 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11836 { 10360 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11837 { 10367 /* fdiv.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11838 { 10367 /* fdiv.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11839 { 10367 /* fdiv.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11840 { 10374 /* fdiv.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11841 { 10381 /* fdiv.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11842 { 10381 /* fdiv.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11843 { 10381 /* fdiv.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11844 { 10388 /* fence */, 3 /* 0, 1 */, MCK_FenceArg, AMFBS_None },
11845 { 10412 /* feq.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11846 { 10412 /* feq.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11847 { 10418 /* feq.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11848 { 10430 /* feq.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11849 { 10436 /* fge.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11850 { 10436 /* fge.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11851 { 10442 /* fge.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11852 { 10454 /* fge.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11853 { 10488 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11854 { 10488 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11855 { 10494 /* fgt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11856 { 10506 /* fgt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11857 { 10540 /* fld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
11858 { 10544 /* fle.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11859 { 10544 /* fle.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11860 { 10550 /* fle.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11861 { 10562 /* fle.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11862 { 10596 /* flh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasHalfFPLoadStoreMove },
11863 { 10600 /* fli.d */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtD },
11864 { 10606 /* fli.h */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh },
11865 { 10612 /* fli.q */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtQ },
11866 { 10618 /* fli.s */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa },
11867 { 10624 /* flq */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtQ },
11868 { 10628 /* flt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11869 { 10628 /* flt.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11870 { 10634 /* flt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11871 { 10646 /* flt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11872 { 10680 /* flw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
11873 { 10684 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11874 { 10684 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11875 { 10684 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11876 { 10684 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11877 { 10684 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11878 { 10692 /* fmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11879 { 10692 /* fmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11880 { 10692 /* fmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11881 { 10700 /* fmadd.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11882 { 10708 /* fmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11883 { 10708 /* fmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11884 { 10708 /* fmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11885 { 10716 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11886 { 10716 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11887 { 10723 /* fmax.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11888 { 10737 /* fmax.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11889 { 10776 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11890 { 10776 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11891 { 10783 /* fmin.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11892 { 10797 /* fmin.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11893 { 10836 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11894 { 10836 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11895 { 10836 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11896 { 10836 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11897 { 10836 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11898 { 10844 /* fmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11899 { 10844 /* fmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11900 { 10844 /* fmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11901 { 10852 /* fmsub.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11902 { 10860 /* fmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11903 { 10860 /* fmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11904 { 10860 /* fmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11905 { 10868 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11906 { 10868 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11907 { 10868 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11908 { 10868 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11909 { 10868 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11910 { 10875 /* fmul.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11911 { 10875 /* fmul.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11912 { 10875 /* fmul.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11913 { 10882 /* fmul.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11914 { 10889 /* fmul.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11915 { 10889 /* fmul.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11916 { 10889 /* fmul.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11917 { 10896 /* fmv.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11918 { 10896 /* fmv.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11919 { 10910 /* fmv.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11920 { 10930 /* fmv.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11921 { 11004 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11922 { 11004 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11923 { 11011 /* fneg.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11924 { 11025 /* fneg.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11925 { 11032 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11926 { 11032 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11927 { 11032 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11928 { 11032 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11929 { 11032 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11930 { 11041 /* fnmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11931 { 11041 /* fnmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11932 { 11041 /* fnmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11933 { 11050 /* fnmadd.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11934 { 11059 /* fnmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11935 { 11059 /* fnmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11936 { 11059 /* fnmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11937 { 11068 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11938 { 11068 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11939 { 11068 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11940 { 11068 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11941 { 11068 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11942 { 11077 /* fnmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11943 { 11077 /* fnmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11944 { 11077 /* fnmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11945 { 11086 /* fnmsub.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11946 { 11095 /* fnmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11947 { 11095 /* fnmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11948 { 11095 /* fnmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11949 { 11118 /* fround.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
11950 { 11127 /* fround.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
11951 { 11136 /* fround.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtQ },
11952 { 11145 /* fround.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa },
11953 { 11154 /* froundnx.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
11954 { 11165 /* froundnx.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
11955 { 11176 /* froundnx.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtQ },
11956 { 11187 /* froundnx.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa },
11957 { 11209 /* fsd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
11958 { 11230 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11959 { 11230 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11960 { 11238 /* fsgnj.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11961 { 11254 /* fsgnj.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11962 { 11262 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11963 { 11262 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11964 { 11271 /* fsgnjn.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11965 { 11289 /* fsgnjn.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11966 { 11298 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11967 { 11298 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11968 { 11307 /* fsgnjx.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11969 { 11325 /* fsgnjx.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11970 { 11334 /* fsh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasHalfFPLoadStoreMove },
11971 { 11338 /* fsq */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtQ },
11972 { 11342 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11973 { 11342 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11974 { 11342 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11975 { 11342 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11976 { 11342 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11977 { 11350 /* fsqrt.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11978 { 11350 /* fsqrt.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11979 { 11350 /* fsqrt.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11980 { 11358 /* fsqrt.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11981 { 11366 /* fsqrt.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11982 { 11366 /* fsqrt.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11983 { 11366 /* fsqrt.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11984 { 11385 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11985 { 11385 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11986 { 11385 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11987 { 11385 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11988 { 11385 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11989 { 11392 /* fsub.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11990 { 11392 /* fsub.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11991 { 11392 /* fsub.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11992 { 11399 /* fsub.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11993 { 11406 /* fsub.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11994 { 11406 /* fsub.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11995 { 11406 /* fsub.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11996 { 11413 /* fsw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
11997 { 11465 /* hlv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11998 { 11471 /* hlv.bu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11999 { 11478 /* hlv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
12000 { 11484 /* hlv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12001 { 11490 /* hlv.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12002 { 11497 /* hlv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12003 { 11503 /* hlv.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
12004 { 11510 /* hlvx.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12005 { 11518 /* hlvx.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12006 { 11526 /* hsv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12007 { 11532 /* hsv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
12008 { 11538 /* hsv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12009 { 11544 /* hsv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12010 { 11550 /* j */, 1 /* 0 */, MCK_BareSImm21Lsb0, AMFBS_None },
12011 { 11552 /* jal */, 1 /* 0 */, MCK_BareSImm21Lsb0, AMFBS_None },
12012 { 11552 /* jal */, 2 /* 1 */, MCK_BareSImm21Lsb0, AMFBS_None },
12013 { 11556 /* jalr */, 32 /* 5 */, MCK_TLSDESCCallSymbol, AMFBS_None },
12014 { 11564 /* jump */, 1 /* 0 */, MCK_PseudoJumpSymbol, AMFBS_None },
12015 { 11569 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12016 { 11572 /* la.tls.gd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12017 { 11582 /* la.tls.ie */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12018 { 11592 /* lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12019 { 11592 /* lb */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12020 { 11592 /* lb */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12021 { 11595 /* lb.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12022 { 11601 /* lb.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12023 { 11609 /* lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12024 { 11609 /* lbu */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12025 { 11609 /* lbu */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12026 { 11613 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
12027 { 11613 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZilsd_IsRV32 },
12028 { 11613 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12029 { 11613 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12030 { 11613 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12031 { 11616 /* ld.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12032 { 11622 /* ld.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12033 { 11630 /* lga */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12034 { 11634 /* lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12035 { 11634 /* lh */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12036 { 11634 /* lh */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12037 { 11637 /* lh.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12038 { 11643 /* lh.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12039 { 11651 /* lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12040 { 11651 /* lhu */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12041 { 11651 /* lhu */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12042 { 11658 /* lla */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12043 { 11667 /* lr.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12044 { 11672 /* lr.d.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12045 { 11680 /* lr.d.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12046 { 11690 /* lr.d.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12047 { 11698 /* lr.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12048 { 11703 /* lr.w.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12049 { 11711 /* lr.w.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12050 { 11721 /* lr.w.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12051 { 11733 /* lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12052 { 11733 /* lw */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12053 { 11733 /* lw */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12054 { 11736 /* lw.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12055 { 11742 /* lw.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12056 { 11750 /* lwu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
12057 { 12589 /* mqrwacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12058 { 12597 /* mqwacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12059 { 12900 /* mvd */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12060 { 12913 /* nclip */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12061 { 12919 /* nclipi */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12062 { 12926 /* nclipiu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12063 { 12934 /* nclipr */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12064 { 12941 /* nclipri */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12065 { 12949 /* nclipriu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12066 { 12958 /* nclipru */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12067 { 12966 /* nclipu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12068 { 13294 /* nds.vd4dots.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
12069 { 13309 /* nds.vd4dotsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
12070 { 13325 /* nds.vd4dotu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
12071 { 13358 /* nds.vfpmadb.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVPackFPH },
12072 { 13373 /* nds.vfpmadt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVPackFPH },
12073 { 13388 /* nds.vfwcvt.f.b.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
12074 { 13405 /* nds.vfwcvt.f.bu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
12075 { 13423 /* nds.vfwcvt.f.n.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
12076 { 13440 /* nds.vfwcvt.f.nu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
12077 { 13476 /* nds.vle4.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntH },
12078 { 13487 /* nds.vln8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
12079 { 13487 /* nds.vln8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
12080 { 13498 /* nds.vlnu8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
12081 { 13498 /* nds.vlnu8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
12082 { 13514 /* negd */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12083 { 13532 /* nsra */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12084 { 13537 /* nsrai */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12085 { 13543 /* nsrar */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12086 { 13549 /* nsrari */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12087 { 13556 /* nsrl */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12088 { 13561 /* nsrli */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12089 { 13623 /* paadd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12090 { 13632 /* paadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12091 { 13641 /* paadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12092 { 13675 /* paaddu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12093 { 13685 /* paaddu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12094 { 13695 /* paaddu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12095 { 13723 /* paas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12096 { 13755 /* pabd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12097 { 13763 /* pabd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12098 { 13809 /* pabdu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12099 { 13818 /* pabdu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12100 { 13842 /* pabs.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12101 { 13850 /* pabs.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12102 { 13903 /* padd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12103 { 13911 /* padd.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12104 { 13920 /* padd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12105 { 13928 /* padd.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12106 { 13937 /* padd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12107 { 13945 /* padd.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12108 { 13984 /* pas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12109 { 14006 /* pasa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12110 { 14039 /* pasub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12111 { 14048 /* pasub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12112 { 14057 /* pasub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12113 { 14091 /* pasubu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12114 { 14101 /* pasubu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12115 { 14111 /* pasubu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12116 { 14151 /* pli.db */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12117 { 14158 /* pli.dh */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12118 { 14177 /* plui.dh */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12119 { 14468 /* pm2wadd.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12120 { 14478 /* pm2wadd.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12121 { 14489 /* pm2wadda.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12122 { 14500 /* pm2wadda.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12123 { 14512 /* pm2waddasu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12124 { 14525 /* pm2waddau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12125 { 14537 /* pm2waddsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12126 { 14549 /* pm2waddu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12127 { 14560 /* pm2wsub.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12128 { 14570 /* pm2wsub.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12129 { 14581 /* pm2wsuba.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12130 { 14592 /* pm2wsuba.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12131 { 14840 /* pmax.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12132 { 14848 /* pmax.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12133 { 14856 /* pmax.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12134 { 14886 /* pmaxu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12135 { 14895 /* pmaxu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12136 { 14904 /* pmaxu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12137 { 15166 /* pmin.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12138 { 15174 /* pmin.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12139 { 15182 /* pmin.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12140 { 15212 /* pminu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12141 { 15221 /* pminu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12142 { 15230 /* pminu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12143 { 15424 /* pmqrwacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12144 { 15435 /* pmqwacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12145 { 15453 /* pmseq.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12146 { 15462 /* pmseq.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12147 { 15471 /* pmseq.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12148 { 15505 /* pmseqz.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12149 { 15515 /* pmseqz.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12150 { 15525 /* pmseqz.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12151 { 15561 /* pmsgt.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12152 { 15570 /* pmsgt.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12153 { 15579 /* pmsgt.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12154 { 15613 /* pmsgtu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12155 { 15623 /* pmsgtu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12156 { 15633 /* pmsgtu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12157 { 15670 /* pmsgtz.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12158 { 15680 /* pmsgtz.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12159 { 15690 /* pmsgtz.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12160 { 15726 /* pmslt.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12161 { 15735 /* pmslt.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12162 { 15744 /* pmslt.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12163 { 15778 /* pmsltu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12164 { 15788 /* pmsltu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12165 { 15798 /* pmsltu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12166 { 15835 /* pmsltz.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12167 { 15845 /* pmsltz.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12168 { 15855 /* pmsltz.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12169 { 15892 /* pmsnez.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12170 { 15902 /* pmsnez.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12171 { 15912 /* pmsnez.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12172 { 16381 /* pmv.dbs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12173 { 16389 /* pmv.dhs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12174 { 16397 /* pmv.dws */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12175 { 16419 /* pnclip.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12176 { 16429 /* pnclip.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12177 { 16439 /* pnclipi.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12178 { 16449 /* pnclipi.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12179 { 16459 /* pnclipiu.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12180 { 16470 /* pnclipiu.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12181 { 16511 /* pnclipr.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12182 { 16522 /* pnclipr.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12183 { 16533 /* pnclipri.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12184 { 16544 /* pnclipri.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12185 { 16555 /* pnclipriu.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12186 { 16567 /* pnclipriu.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12187 { 16579 /* pnclipru.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12188 { 16591 /* pnclipru.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12189 { 16603 /* pnclipu.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12190 { 16614 /* pnclipu.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12191 { 16658 /* pncvt.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12192 { 16666 /* pncvt.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12193 { 16692 /* pncvth.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12194 { 16701 /* pncvth.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12195 { 16737 /* pneg.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12196 { 16745 /* pneg.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12197 { 16753 /* pneg.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12198 { 16775 /* pnsra.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12199 { 16784 /* pnsra.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12200 { 16793 /* pnsrai.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12201 { 16802 /* pnsrai.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12202 { 16811 /* pnsrar.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12203 { 16821 /* pnsrar.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12204 { 16831 /* pnsrari.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12205 { 16841 /* pnsrari.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12206 { 16851 /* pnsrl.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12207 { 16860 /* pnsrl.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12208 { 16869 /* pnsrli.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12209 { 16878 /* pnsrli.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12210 { 16896 /* ppaire.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12211 { 16906 /* ppaire.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12212 { 16944 /* ppaireo.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12213 { 16955 /* ppaireo.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12214 { 16995 /* ppairo.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12215 { 17005 /* ppairo.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12216 { 17043 /* ppairoe.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12217 { 17054 /* ppairoe.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12218 { 17096 /* predsum.dbs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12219 { 17108 /* predsum.dhs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12220 { 17154 /* predsumu.dbs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12221 { 17167 /* predsumu.dhs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12222 { 17237 /* psa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12223 { 17267 /* psabs.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12224 { 17276 /* psabs.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12225 { 17301 /* psadd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12226 { 17310 /* psadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12227 { 17319 /* psadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12228 { 17353 /* psaddu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12229 { 17363 /* psaddu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12230 { 17373 /* psaddu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12231 { 17401 /* psas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12232 { 17426 /* psati.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12233 { 17435 /* psati.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12234 { 17460 /* psext.dh.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12235 { 17471 /* psext.dw.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12236 { 17482 /* psext.dw.h */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12237 { 17523 /* psh1add.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12238 { 17534 /* psh1add.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12239 { 17573 /* psll.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12240 { 17582 /* psll.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12241 { 17591 /* psll.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12242 { 17624 /* pslli.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12243 { 17633 /* pslli.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12244 { 17642 /* pslli.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12245 { 17675 /* psra.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12246 { 17684 /* psra.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12247 { 17693 /* psra.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12248 { 17726 /* psrai.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12249 { 17735 /* psrai.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12250 { 17744 /* psrai.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12251 { 17769 /* psrari.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12252 { 17779 /* psrari.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12253 { 17815 /* psrl.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12254 { 17824 /* psrl.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12255 { 17833 /* psrl.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12256 { 17866 /* psrli.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12257 { 17875 /* psrli.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12258 { 17884 /* psrli.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12259 { 17909 /* pssa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12260 { 17934 /* pssh1sadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12261 { 17947 /* pssh1sadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12262 { 17984 /* pssha.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12263 { 17994 /* pssha.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12264 { 18022 /* psshar.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12265 { 18033 /* psshar.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12266 { 18064 /* psshl.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12267 { 18074 /* psshl.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12268 { 18102 /* psshlr.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12269 { 18113 /* psshlr.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12270 { 18144 /* psslai.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12271 { 18154 /* psslai.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12272 { 18190 /* pssub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12273 { 18199 /* pssub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12274 { 18208 /* pssub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12275 { 18242 /* pssubu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12276 { 18252 /* pssubu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12277 { 18262 /* pssubu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12278 { 18297 /* psub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12279 { 18305 /* psub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12280 { 18313 /* psub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12281 { 18335 /* pusati.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12282 { 18345 /* pusati.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12283 { 18373 /* pwadd.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12284 { 18381 /* pwadd.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12285 { 18389 /* pwadda.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12286 { 18398 /* pwadda.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12287 { 18407 /* pwaddau.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12288 { 18417 /* pwaddau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12289 { 18427 /* pwaddu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12290 { 18436 /* pwaddu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12291 { 18445 /* pwcvt.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12292 { 18453 /* pwcvt.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12293 { 18461 /* pwcvth.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12294 { 18470 /* pwcvth.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12295 { 18499 /* pwcvtu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12296 { 18508 /* pwcvtu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12297 { 18537 /* pwmacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12298 { 18546 /* pwmaccsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12299 { 18557 /* pwmaccu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12300 { 18567 /* pwmul.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12301 { 18575 /* pwmul.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12302 { 18583 /* pwmulsu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12303 { 18593 /* pwmulsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12304 { 18603 /* pwmulu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12305 { 18612 /* pwmulu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12306 { 18621 /* pwsla.bs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12307 { 18630 /* pwsla.hs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12308 { 18639 /* pwslai.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12309 { 18648 /* pwslai.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12310 { 18657 /* pwsll.bs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12311 { 18666 /* pwsll.hs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12312 { 18675 /* pwslli.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12313 { 18684 /* pwslli.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12314 { 18693 /* pwsub.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12315 { 18701 /* pwsub.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12316 { 18709 /* pwsuba.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12317 { 18718 /* pwsuba.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12318 { 18727 /* pwsubau.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12319 { 18737 /* pwsubau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12320 { 18747 /* pwsubu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12321 { 18756 /* pwsubu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12322 { 18765 /* pzext.dh.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12323 { 18776 /* pzext.dw.h */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12324 { 19202 /* qc.cm.pop */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12325 { 19202 /* qc.cm.pop */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
12326 { 19212 /* qc.cm.popret */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12327 { 19212 /* qc.cm.popret */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
12328 { 19225 /* qc.cm.popretz */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12329 { 19225 /* qc.cm.popretz */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
12330 { 19239 /* qc.cm.push */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasVendorXqccmp },
12331 { 19239 /* qc.cm.push */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12332 { 19250 /* qc.cm.pushfp */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasVendorXqccmp },
12333 { 19250 /* qc.cm.pushfp */, 1 /* 0 */, MCK_RegListS0, AMFBS_HasVendorXqccmp },
12334 { 19437 /* qc.e.lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12335 { 19445 /* qc.e.lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12336 { 19454 /* qc.e.lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12337 { 19462 /* qc.e.lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12338 { 19471 /* qc.e.li */, 2 /* 1 */, MCK_BareSymbolQC_E_LI, AMFBS_HasVendorXqcili_IsRV32 },
12339 { 19479 /* qc.e.lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12340 { 19506 /* qc.e.sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12341 { 19514 /* qc.e.sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12342 { 19522 /* qc.e.sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12343 { 20654 /* sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12344 { 20654 /* sb */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12345 { 20654 /* sb */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12346 { 20657 /* sb.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12347 { 20665 /* sb.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12348 { 20671 /* sc.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12349 { 20676 /* sc.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12350 { 20684 /* sc.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12351 { 20694 /* sc.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12352 { 20702 /* sc.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12353 { 20707 /* sc.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12354 { 20715 /* sc.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12355 { 20725 /* sc.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12356 { 20741 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
12357 { 20741 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZilsd_IsRV32 },
12358 { 20741 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12359 { 20741 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12360 { 20741 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12361 { 20744 /* sd.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12362 { 20752 /* sd.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12363 { 21231 /* sf.vfexp.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfexpAny },
12364 { 21242 /* sf.vfexpa.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfexpa },
12365 { 21254 /* sf.vfnrclip.x.f.qf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
12366 { 21273 /* sf.vfnrclip.xu.f.qf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
12367 { 21310 /* sf.vlte16 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12368 { 21320 /* sf.vlte32 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12369 { 21330 /* sf.vlte64 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12370 { 21340 /* sf.vlte8 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12371 { 21517 /* sf.vsettnt */, 4 /* 2 */, MCK_XSfmmVType, AMFBS_HasVendorXSfmmbase },
12372 { 21528 /* sf.vste16 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12373 { 21538 /* sf.vste32 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12374 { 21548 /* sf.vste64 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12375 { 21558 /* sf.vste8 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12376 { 21672 /* sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12377 { 21672 /* sh */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12378 { 21672 /* sh */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12379 { 21675 /* sh.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12380 { 21683 /* sh.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12381 { 22065 /* smt.vmadot */, 8 /* 3 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12382 { 22076 /* smt.vmadot.hp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12383 { 22090 /* smt.vmadot.sp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12384 { 22104 /* smt.vmadot1 */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12385 { 22116 /* smt.vmadot1su */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12386 { 22130 /* smt.vmadot1u */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12387 { 22143 /* smt.vmadot1us */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12388 { 22157 /* smt.vmadot2 */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12389 { 22169 /* smt.vmadot2su */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12390 { 22183 /* smt.vmadot2u */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12391 { 22196 /* smt.vmadot2us */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12392 { 22210 /* smt.vmadot3 */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12393 { 22222 /* smt.vmadot3su */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12394 { 22236 /* smt.vmadot3u */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12395 { 22249 /* smt.vmadot3us */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12396 { 22263 /* smt.vmadotsu */, 8 /* 3 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12397 { 22276 /* smt.vmadotsu.hp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12398 { 22292 /* smt.vmadotsu.sp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12399 { 22308 /* smt.vmadotu */, 8 /* 3 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12400 { 22320 /* smt.vmadotu.hp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12401 { 22335 /* smt.vmadotu.sp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12402 { 22350 /* smt.vmadotus */, 8 /* 3 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12403 { 22363 /* smt.vmadotus.hp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12404 { 22379 /* smt.vmadotus.sp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12405 { 22548 /* ssamoswap.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12406 { 22560 /* ssamoswap.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12407 { 22575 /* ssamoswap.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12408 { 22592 /* ssamoswap.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12409 { 22607 /* ssamoswap.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12410 { 22619 /* ssamoswap.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12411 { 22634 /* ssamoswap.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12412 { 22651 /* ssamoswap.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12413 { 22740 /* subd */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12414 { 22750 /* sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12415 { 22750 /* sw */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12416 { 22750 /* sw */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12417 { 22753 /* sw.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12418 { 22761 /* sw.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12419 { 22767 /* tail */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
12420 { 23755 /* th.vmaqa.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12421 { 23767 /* th.vmaqa.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12422 { 23779 /* th.vmaqasu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12423 { 23793 /* th.vmaqasu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12424 { 23807 /* th.vmaqau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12425 { 23820 /* th.vmaqau.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12426 { 23833 /* th.vmaqaus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12427 { 23913 /* vaadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12428 { 23922 /* vaadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12429 { 23931 /* vaaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12430 { 23941 /* vaaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12431 { 23951 /* vabd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12432 { 23959 /* vabdu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12433 { 23968 /* vabs.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12434 { 24002 /* vadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12435 { 24010 /* vadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12436 { 24018 /* vadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12437 { 24137 /* vand.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12438 { 24145 /* vand.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12439 { 24153 /* vand.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12440 { 24161 /* vandn.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12441 { 24170 /* vandn.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12442 { 24179 /* vasub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12443 { 24188 /* vasub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12444 { 24197 /* vasubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12445 { 24207 /* vasubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12446 { 24217 /* vbrev.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12447 { 24225 /* vbrev8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12448 { 24234 /* vclmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12449 { 24244 /* vclmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12450 { 24254 /* vclmulh.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12451 { 24265 /* vclmulh.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12452 { 24276 /* vclz.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12453 { 24296 /* vcpop.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12454 { 24304 /* vcpop.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12455 { 24312 /* vctz.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12456 { 24319 /* vdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12457 { 24327 /* vdiv.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12458 { 24335 /* vdivu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12459 { 24344 /* vdivu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12460 { 24353 /* vdot4a.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12461 { 24363 /* vdot4a.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12462 { 24373 /* vdot4asu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12463 { 24385 /* vdot4asu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12464 { 24397 /* vdot4au.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12465 { 24408 /* vdot4au.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12466 { 24419 /* vdot4aus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12467 { 24431 /* vf8wimmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12468 { 24445 /* vf8wmmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12469 { 24458 /* vfabs.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12470 { 24466 /* vfadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12471 { 24475 /* vfadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12472 { 24484 /* vfbdota.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbdota32f },
12473 { 24495 /* vfclass.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12474 { 24505 /* vfcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12475 { 24517 /* vfcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12476 { 24530 /* vfcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12477 { 24546 /* vfcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12478 { 24563 /* vfcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12479 { 24575 /* vfcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12480 { 24588 /* vfdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12481 { 24597 /* vfdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12482 { 24606 /* vfirst.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12483 { 24615 /* vfmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12484 { 24625 /* vfmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12485 { 24635 /* vfmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12486 { 24645 /* vfmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12487 { 24655 /* vfmax.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12488 { 24664 /* vfmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12489 { 24685 /* vfmin.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12490 { 24694 /* vfmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12491 { 24714 /* vfmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12492 { 24724 /* vfmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12493 { 24734 /* vfmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12494 { 24744 /* vfmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12495 { 24754 /* vfmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12496 { 24763 /* vfmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12497 { 24799 /* vfncvt.f.f.q */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
12498 { 24812 /* vfncvt.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12499 { 24825 /* vfncvt.f.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12500 { 24838 /* vfncvt.f.xu.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12501 { 24852 /* vfncvt.rod.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12502 { 24869 /* vfncvt.rtz.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12503 { 24886 /* vfncvt.rtz.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12504 { 24904 /* vfncvt.sat.f.f.q */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
12505 { 24921 /* vfncvt.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12506 { 24934 /* vfncvt.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12507 { 24948 /* vfncvtbf16.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfminOrZvfofp8min },
12508 { 24965 /* vfncvtbf16.sat.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
12509 { 24986 /* vfneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12510 { 24994 /* vfnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12511 { 25005 /* vfnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12512 { 25016 /* vfnmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12513 { 25027 /* vfnmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12514 { 25038 /* vfnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12515 { 25049 /* vfnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12516 { 25060 /* vfnmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12517 { 25071 /* vfnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12518 { 25082 /* vfqimmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12519 { 25095 /* vfqmmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12520 { 25107 /* vfqwbdota.alt.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwbdota8f },
12521 { 25124 /* vfqwbdota.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwbdota8f },
12522 { 25137 /* vfqwdota.alt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwdota8f },
12523 { 25153 /* vfqwdota.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwdota8f },
12524 { 25165 /* vfrdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12525 { 25175 /* vfrec7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12526 { 25184 /* vfredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12527 { 25196 /* vfredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12528 { 25208 /* vfredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12529 { 25221 /* vfredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12530 { 25234 /* vfrsqrt7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12531 { 25245 /* vfrsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12532 { 25255 /* vfsgnj.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12533 { 25265 /* vfsgnj.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12534 { 25275 /* vfsgnjn.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12535 { 25286 /* vfsgnjn.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12536 { 25297 /* vfsgnjx.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12537 { 25308 /* vfsgnjx.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12538 { 25319 /* vfslide1down.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12539 { 25335 /* vfslide1up.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12540 { 25349 /* vfsqrt.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12541 { 25358 /* vfsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12542 { 25367 /* vfsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12543 { 25376 /* vfwadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12544 { 25386 /* vfwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12545 { 25396 /* vfwadd.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12546 { 25406 /* vfwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12547 { 25416 /* vfwbdota.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfwbdota16bf },
12548 { 25428 /* vfwcvt.f.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12549 { 25441 /* vfwcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12550 { 25454 /* vfwcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12551 { 25468 /* vfwcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12552 { 25485 /* vfwcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12553 { 25503 /* vfwcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12554 { 25516 /* vfwcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12555 { 25530 /* vfwcvtbf16.f.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfminOrZvfofp8min },
12556 { 25547 /* vfwdota.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfwdota16bf },
12557 { 25558 /* vfwimmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12558 { 25571 /* vfwmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12559 { 25582 /* vfwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12560 { 25593 /* vfwmaccbf16.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
12561 { 25608 /* vfwmaccbf16.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
12562 { 25623 /* vfwmmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12563 { 25635 /* vfwmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12564 { 25646 /* vfwmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12565 { 25657 /* vfwmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12566 { 25667 /* vfwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12567 { 25677 /* vfwnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12568 { 25689 /* vfwnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12569 { 25701 /* vfwnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12570 { 25713 /* vfwnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12571 { 25725 /* vfwredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12572 { 25739 /* vfwredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12573 { 25753 /* vfwsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12574 { 25763 /* vfwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12575 { 25773 /* vfwsub.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12576 { 25783 /* vfwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12577 { 25829 /* vid.v */, 2 /* 1 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12578 { 25835 /* viota.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12579 { 25843 /* vl1r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12580 { 25850 /* vl1re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12581 { 25860 /* vl1re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12582 { 25870 /* vl1re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12583 { 25880 /* vl1re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12584 { 25889 /* vl2r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12585 { 25896 /* vl2re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12586 { 25906 /* vl2re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12587 { 25916 /* vl2re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12588 { 25926 /* vl2re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12589 { 25935 /* vl4r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12590 { 25942 /* vl4re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12591 { 25952 /* vl4re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12592 { 25962 /* vl4re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12593 { 25972 /* vl4re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12594 { 25981 /* vl8r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12595 { 25988 /* vl8re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12596 { 25998 /* vl8re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12597 { 26008 /* vl8re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12598 { 26018 /* vl8re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12599 { 26027 /* vle16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12600 { 26027 /* vle16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12601 { 26035 /* vle16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12602 { 26035 /* vle16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12603 { 26045 /* vle32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12604 { 26045 /* vle32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12605 { 26053 /* vle32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12606 { 26053 /* vle32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12607 { 26063 /* vle64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12608 { 26063 /* vle64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12609 { 26071 /* vle64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12610 { 26071 /* vle64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12611 { 26081 /* vle8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12612 { 26081 /* vle8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12613 { 26088 /* vle8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12614 { 26088 /* vle8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12615 { 26097 /* vlm.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12616 { 26103 /* vloxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12617 { 26103 /* vloxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12618 { 26114 /* vloxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12619 { 26114 /* vloxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12620 { 26125 /* vloxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12621 { 26125 /* vloxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12622 { 26136 /* vloxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12623 { 26136 /* vloxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12624 { 26146 /* vloxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12625 { 26146 /* vloxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12626 { 26161 /* vloxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12627 { 26161 /* vloxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12628 { 26176 /* vloxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12629 { 26176 /* vloxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12630 { 26191 /* vloxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12631 { 26191 /* vloxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12632 { 26205 /* vloxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12633 { 26205 /* vloxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12634 { 26220 /* vloxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12635 { 26220 /* vloxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12636 { 26235 /* vloxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12637 { 26235 /* vloxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12638 { 26250 /* vloxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12639 { 26250 /* vloxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12640 { 26264 /* vloxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12641 { 26264 /* vloxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12642 { 26279 /* vloxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12643 { 26279 /* vloxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12644 { 26294 /* vloxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12645 { 26294 /* vloxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12646 { 26309 /* vloxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12647 { 26309 /* vloxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12648 { 26323 /* vloxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12649 { 26323 /* vloxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12650 { 26338 /* vloxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12651 { 26338 /* vloxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12652 { 26353 /* vloxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12653 { 26353 /* vloxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12654 { 26368 /* vloxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12655 { 26368 /* vloxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12656 { 26382 /* vloxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12657 { 26382 /* vloxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12658 { 26397 /* vloxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12659 { 26397 /* vloxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12660 { 26412 /* vloxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12661 { 26412 /* vloxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12662 { 26427 /* vloxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12663 { 26427 /* vloxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12664 { 26441 /* vloxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12665 { 26441 /* vloxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12666 { 26456 /* vloxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12667 { 26456 /* vloxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12668 { 26471 /* vloxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12669 { 26471 /* vloxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12670 { 26486 /* vloxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12671 { 26486 /* vloxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12672 { 26500 /* vloxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12673 { 26500 /* vloxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12674 { 26515 /* vloxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12675 { 26515 /* vloxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12676 { 26530 /* vloxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12677 { 26530 /* vloxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12678 { 26545 /* vloxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12679 { 26545 /* vloxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12680 { 26559 /* vlse16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12681 { 26559 /* vlse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12682 { 26568 /* vlse32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12683 { 26568 /* vlse32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12684 { 26577 /* vlse64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12685 { 26577 /* vlse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12686 { 26586 /* vlse8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12687 { 26586 /* vlse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12688 { 26594 /* vlseg2e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12689 { 26594 /* vlseg2e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12690 { 26606 /* vlseg2e16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12691 { 26606 /* vlseg2e16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12692 { 26620 /* vlseg2e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12693 { 26620 /* vlseg2e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12694 { 26632 /* vlseg2e32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12695 { 26632 /* vlseg2e32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12696 { 26646 /* vlseg2e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12697 { 26646 /* vlseg2e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12698 { 26658 /* vlseg2e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12699 { 26658 /* vlseg2e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12700 { 26672 /* vlseg2e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12701 { 26672 /* vlseg2e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12702 { 26683 /* vlseg2e8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12703 { 26683 /* vlseg2e8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12704 { 26696 /* vlseg3e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12705 { 26696 /* vlseg3e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12706 { 26708 /* vlseg3e16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12707 { 26708 /* vlseg3e16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12708 { 26722 /* vlseg3e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12709 { 26722 /* vlseg3e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12710 { 26734 /* vlseg3e32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12711 { 26734 /* vlseg3e32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12712 { 26748 /* vlseg3e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12713 { 26748 /* vlseg3e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12714 { 26760 /* vlseg3e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12715 { 26760 /* vlseg3e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12716 { 26774 /* vlseg3e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12717 { 26774 /* vlseg3e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12718 { 26785 /* vlseg3e8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12719 { 26785 /* vlseg3e8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12720 { 26798 /* vlseg4e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12721 { 26798 /* vlseg4e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12722 { 26810 /* vlseg4e16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12723 { 26810 /* vlseg4e16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12724 { 26824 /* vlseg4e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12725 { 26824 /* vlseg4e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12726 { 26836 /* vlseg4e32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12727 { 26836 /* vlseg4e32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12728 { 26850 /* vlseg4e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12729 { 26850 /* vlseg4e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12730 { 26862 /* vlseg4e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12731 { 26862 /* vlseg4e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12732 { 26876 /* vlseg4e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12733 { 26876 /* vlseg4e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12734 { 26887 /* vlseg4e8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12735 { 26887 /* vlseg4e8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12736 { 26900 /* vlseg5e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12737 { 26900 /* vlseg5e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12738 { 26912 /* vlseg5e16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12739 { 26912 /* vlseg5e16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12740 { 26926 /* vlseg5e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12741 { 26926 /* vlseg5e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12742 { 26938 /* vlseg5e32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12743 { 26938 /* vlseg5e32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12744 { 26952 /* vlseg5e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12745 { 26952 /* vlseg5e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12746 { 26964 /* vlseg5e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12747 { 26964 /* vlseg5e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12748 { 26978 /* vlseg5e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12749 { 26978 /* vlseg5e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12750 { 26989 /* vlseg5e8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12751 { 26989 /* vlseg5e8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12752 { 27002 /* vlseg6e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12753 { 27002 /* vlseg6e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12754 { 27014 /* vlseg6e16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12755 { 27014 /* vlseg6e16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12756 { 27028 /* vlseg6e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12757 { 27028 /* vlseg6e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12758 { 27040 /* vlseg6e32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12759 { 27040 /* vlseg6e32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12760 { 27054 /* vlseg6e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12761 { 27054 /* vlseg6e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12762 { 27066 /* vlseg6e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12763 { 27066 /* vlseg6e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12764 { 27080 /* vlseg6e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12765 { 27080 /* vlseg6e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12766 { 27091 /* vlseg6e8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12767 { 27091 /* vlseg6e8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12768 { 27104 /* vlseg7e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12769 { 27104 /* vlseg7e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12770 { 27116 /* vlseg7e16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12771 { 27116 /* vlseg7e16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12772 { 27130 /* vlseg7e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12773 { 27130 /* vlseg7e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12774 { 27142 /* vlseg7e32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12775 { 27142 /* vlseg7e32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12776 { 27156 /* vlseg7e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12777 { 27156 /* vlseg7e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12778 { 27168 /* vlseg7e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12779 { 27168 /* vlseg7e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12780 { 27182 /* vlseg7e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12781 { 27182 /* vlseg7e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12782 { 27193 /* vlseg7e8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12783 { 27193 /* vlseg7e8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12784 { 27206 /* vlseg8e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12785 { 27206 /* vlseg8e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12786 { 27218 /* vlseg8e16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12787 { 27218 /* vlseg8e16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12788 { 27232 /* vlseg8e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12789 { 27232 /* vlseg8e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12790 { 27244 /* vlseg8e32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12791 { 27244 /* vlseg8e32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12792 { 27258 /* vlseg8e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12793 { 27258 /* vlseg8e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12794 { 27270 /* vlseg8e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12795 { 27270 /* vlseg8e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12796 { 27284 /* vlseg8e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12797 { 27284 /* vlseg8e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12798 { 27295 /* vlseg8e8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12799 { 27295 /* vlseg8e8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12800 { 27308 /* vlsseg2e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12801 { 27308 /* vlsseg2e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12802 { 27321 /* vlsseg2e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12803 { 27321 /* vlsseg2e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12804 { 27334 /* vlsseg2e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12805 { 27334 /* vlsseg2e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12806 { 27347 /* vlsseg2e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12807 { 27347 /* vlsseg2e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12808 { 27359 /* vlsseg3e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12809 { 27359 /* vlsseg3e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12810 { 27372 /* vlsseg3e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12811 { 27372 /* vlsseg3e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12812 { 27385 /* vlsseg3e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12813 { 27385 /* vlsseg3e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12814 { 27398 /* vlsseg3e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12815 { 27398 /* vlsseg3e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12816 { 27410 /* vlsseg4e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12817 { 27410 /* vlsseg4e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12818 { 27423 /* vlsseg4e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12819 { 27423 /* vlsseg4e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12820 { 27436 /* vlsseg4e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12821 { 27436 /* vlsseg4e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12822 { 27449 /* vlsseg4e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12823 { 27449 /* vlsseg4e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12824 { 27461 /* vlsseg5e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12825 { 27461 /* vlsseg5e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12826 { 27474 /* vlsseg5e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12827 { 27474 /* vlsseg5e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12828 { 27487 /* vlsseg5e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12829 { 27487 /* vlsseg5e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12830 { 27500 /* vlsseg5e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12831 { 27500 /* vlsseg5e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12832 { 27512 /* vlsseg6e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12833 { 27512 /* vlsseg6e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12834 { 27525 /* vlsseg6e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12835 { 27525 /* vlsseg6e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12836 { 27538 /* vlsseg6e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12837 { 27538 /* vlsseg6e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12838 { 27551 /* vlsseg6e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12839 { 27551 /* vlsseg6e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12840 { 27563 /* vlsseg7e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12841 { 27563 /* vlsseg7e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12842 { 27576 /* vlsseg7e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12843 { 27576 /* vlsseg7e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12844 { 27589 /* vlsseg7e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12845 { 27589 /* vlsseg7e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12846 { 27602 /* vlsseg7e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12847 { 27602 /* vlsseg7e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12848 { 27614 /* vlsseg8e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12849 { 27614 /* vlsseg8e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12850 { 27627 /* vlsseg8e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12851 { 27627 /* vlsseg8e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12852 { 27640 /* vlsseg8e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12853 { 27640 /* vlsseg8e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12854 { 27653 /* vlsseg8e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12855 { 27653 /* vlsseg8e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12856 { 27665 /* vluxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12857 { 27665 /* vluxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12858 { 27676 /* vluxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12859 { 27676 /* vluxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12860 { 27687 /* vluxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12861 { 27687 /* vluxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12862 { 27698 /* vluxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12863 { 27698 /* vluxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12864 { 27708 /* vluxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12865 { 27708 /* vluxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12866 { 27723 /* vluxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12867 { 27723 /* vluxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12868 { 27738 /* vluxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12869 { 27738 /* vluxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12870 { 27753 /* vluxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12871 { 27753 /* vluxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12872 { 27767 /* vluxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12873 { 27767 /* vluxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12874 { 27782 /* vluxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12875 { 27782 /* vluxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12876 { 27797 /* vluxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12877 { 27797 /* vluxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12878 { 27812 /* vluxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12879 { 27812 /* vluxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12880 { 27826 /* vluxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12881 { 27826 /* vluxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12882 { 27841 /* vluxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12883 { 27841 /* vluxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12884 { 27856 /* vluxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12885 { 27856 /* vluxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12886 { 27871 /* vluxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12887 { 27871 /* vluxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12888 { 27885 /* vluxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12889 { 27885 /* vluxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12890 { 27900 /* vluxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12891 { 27900 /* vluxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12892 { 27915 /* vluxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12893 { 27915 /* vluxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12894 { 27930 /* vluxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12895 { 27930 /* vluxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12896 { 27944 /* vluxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12897 { 27944 /* vluxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12898 { 27959 /* vluxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12899 { 27959 /* vluxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12900 { 27974 /* vluxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12901 { 27974 /* vluxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12902 { 27989 /* vluxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12903 { 27989 /* vluxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12904 { 28003 /* vluxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12905 { 28003 /* vluxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12906 { 28018 /* vluxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12907 { 28018 /* vluxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12908 { 28033 /* vluxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12909 { 28033 /* vluxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12910 { 28048 /* vluxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12911 { 28048 /* vluxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12912 { 28062 /* vluxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12913 { 28062 /* vluxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12914 { 28077 /* vluxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12915 { 28077 /* vluxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12916 { 28092 /* vluxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12917 { 28092 /* vluxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12918 { 28107 /* vluxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12919 { 28107 /* vluxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12920 { 28121 /* vmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12921 { 28130 /* vmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12922 { 28196 /* vmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12923 { 28205 /* vmadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12924 { 28233 /* vmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12925 { 28241 /* vmax.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12926 { 28249 /* vmaxu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12927 { 28258 /* vmaxu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12928 { 28308 /* vmfeq.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12929 { 28317 /* vmfeq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12930 { 28326 /* vmfge.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12931 { 28335 /* vmfge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12932 { 28344 /* vmfgt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12933 { 28353 /* vmfgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12934 { 28362 /* vmfle.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12935 { 28371 /* vmfle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12936 { 28380 /* vmflt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12937 { 28389 /* vmflt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12938 { 28398 /* vmfne.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12939 { 28407 /* vmfne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12940 { 28416 /* vmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12941 { 28424 /* vmin.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12942 { 28432 /* vminu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12943 { 28441 /* vminu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12944 { 28549 /* vmsbf.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12945 { 28557 /* vmseq.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12946 { 28566 /* vmseq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12947 { 28575 /* vmseq.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12948 { 28592 /* vmsge.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12949 { 28601 /* vmsge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12950 { 28610 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12951 { 28610 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12952 { 28619 /* vmsgeu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12953 { 28629 /* vmsgeu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12954 { 28639 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12955 { 28639 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12956 { 28649 /* vmsgt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12957 { 28658 /* vmsgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12958 { 28667 /* vmsgt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12959 { 28676 /* vmsgtu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12960 { 28686 /* vmsgtu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12961 { 28696 /* vmsgtu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12962 { 28706 /* vmsif.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12963 { 28714 /* vmsle.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12964 { 28723 /* vmsle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12965 { 28732 /* vmsle.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12966 { 28741 /* vmsleu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12967 { 28751 /* vmsleu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12968 { 28761 /* vmsleu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12969 { 28771 /* vmslt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12970 { 28780 /* vmslt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12971 { 28789 /* vmslt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12972 { 28798 /* vmsltu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12973 { 28808 /* vmsltu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12974 { 28818 /* vmsltu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12975 { 28828 /* vmsne.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12976 { 28837 /* vmsne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12977 { 28846 /* vmsne.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12978 { 28855 /* vmsof.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12979 { 28863 /* vmtl.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
12980 { 28863 /* vmtl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
12981 { 28863 /* vmtl.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmtls },
12982 { 28863 /* vmtl.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
12983 { 28863 /* vmtl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
12984 { 28870 /* vmts.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
12985 { 28870 /* vmts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
12986 { 28870 /* vmts.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmtls },
12987 { 28870 /* vmts.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
12988 { 28870 /* vmts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
12989 { 28877 /* vmttl.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
12990 { 28877 /* vmttl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
12991 { 28877 /* vmttl.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmttls },
12992 { 28877 /* vmttl.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
12993 { 28877 /* vmttl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
12994 { 28885 /* vmtts.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
12995 { 28885 /* vmtts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
12996 { 28885 /* vmtts.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmttls },
12997 { 28885 /* vmtts.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
12998 { 28885 /* vmtts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
12999 { 28893 /* vmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13000 { 28901 /* vmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13001 { 28909 /* vmulh.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13002 { 28918 /* vmulh.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13003 { 28927 /* vmulhsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13004 { 28938 /* vmulhsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13005 { 28949 /* vmulhu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13006 { 28959 /* vmulhu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13007 { 29060 /* vnclip.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13008 { 29070 /* vnclip.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13009 { 29080 /* vnclip.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13010 { 29090 /* vnclipu.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13011 { 29101 /* vnclipu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13012 { 29112 /* vnclipu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13013 { 29123 /* vncvt.x.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13014 { 29135 /* vneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13015 { 29142 /* vnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13016 { 29152 /* vnmsac.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13017 { 29162 /* vnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13018 { 29172 /* vnmsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13019 { 29182 /* vnot.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13020 { 29189 /* vnsra.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13021 { 29198 /* vnsra.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13022 { 29207 /* vnsra.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13023 { 29216 /* vnsrl.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13024 { 29225 /* vnsrl.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13025 { 29234 /* vnsrl.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13026 { 29243 /* vor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13027 { 29250 /* vor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13028 { 29257 /* vor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13029 { 29264 /* vpaire.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13030 { 29274 /* vpairo.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13031 { 29295 /* vqwbdotas.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i },
13032 { 29308 /* vqwbdotau.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i },
13033 { 29321 /* vqwdotas.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i },
13034 { 29333 /* vqwdotau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i },
13035 { 29345 /* vredand.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13036 { 29356 /* vredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13037 { 29367 /* vredmaxu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13038 { 29379 /* vredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13039 { 29390 /* vredminu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13040 { 29402 /* vredor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13041 { 29412 /* vredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13042 { 29423 /* vredxor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13043 { 29434 /* vrem.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13044 { 29442 /* vrem.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13045 { 29450 /* vremu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13046 { 29459 /* vremu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13047 { 29468 /* vrev8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13048 { 29476 /* vrgather.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13049 { 29488 /* vrgather.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13050 { 29500 /* vrgather.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13051 { 29512 /* vrgatherei16.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13052 { 29528 /* vrol.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13053 { 29536 /* vrol.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13054 { 29544 /* vror.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13055 { 29552 /* vror.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13056 { 29560 /* vror.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13057 { 29568 /* vrsub.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13058 { 29577 /* vrsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13059 { 29586 /* vs1r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13060 { 29593 /* vs2r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13061 { 29600 /* vs4r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13062 { 29607 /* vs8r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13063 { 29614 /* vsadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13064 { 29623 /* vsadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13065 { 29632 /* vsadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13066 { 29641 /* vsaddu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13067 { 29651 /* vsaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13068 { 29661 /* vsaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13069 { 29689 /* vse16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13070 { 29689 /* vse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13071 { 29697 /* vse32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13072 { 29697 /* vse32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13073 { 29705 /* vse64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13074 { 29705 /* vse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13075 { 29713 /* vse8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13076 { 29713 /* vse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13077 { 29720 /* vsetivli */, 4 /* 2 */, MCK_VTypeI10, AMFBS_HasVInstructions },
13078 { 29736 /* vsetvli */, 4 /* 2 */, MCK_VTypeI11, AMFBS_HasVInstructions },
13079 { 29744 /* vsext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13080 { 29754 /* vsext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13081 { 29764 /* vsext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13082 { 29807 /* vslide1down.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13083 { 29822 /* vslide1up.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13084 { 29835 /* vslidedown.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13085 { 29849 /* vslidedown.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13086 { 29863 /* vslideup.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13087 { 29875 /* vslideup.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13088 { 29887 /* vsll.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13089 { 29895 /* vsll.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13090 { 29903 /* vsll.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13091 { 29911 /* vsm.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13092 { 29963 /* vsmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13093 { 29972 /* vsmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13094 { 29981 /* vsoxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13095 { 29981 /* vsoxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13096 { 29992 /* vsoxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13097 { 29992 /* vsoxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13098 { 30003 /* vsoxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13099 { 30003 /* vsoxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13100 { 30014 /* vsoxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13101 { 30014 /* vsoxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13102 { 30024 /* vsoxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13103 { 30024 /* vsoxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13104 { 30039 /* vsoxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13105 { 30039 /* vsoxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13106 { 30054 /* vsoxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13107 { 30054 /* vsoxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13108 { 30069 /* vsoxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13109 { 30069 /* vsoxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13110 { 30083 /* vsoxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13111 { 30083 /* vsoxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13112 { 30098 /* vsoxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13113 { 30098 /* vsoxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13114 { 30113 /* vsoxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13115 { 30113 /* vsoxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13116 { 30128 /* vsoxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13117 { 30128 /* vsoxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13118 { 30142 /* vsoxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13119 { 30142 /* vsoxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13120 { 30157 /* vsoxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13121 { 30157 /* vsoxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13122 { 30172 /* vsoxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13123 { 30172 /* vsoxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13124 { 30187 /* vsoxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13125 { 30187 /* vsoxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13126 { 30201 /* vsoxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13127 { 30201 /* vsoxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13128 { 30216 /* vsoxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13129 { 30216 /* vsoxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13130 { 30231 /* vsoxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13131 { 30231 /* vsoxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13132 { 30246 /* vsoxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13133 { 30246 /* vsoxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13134 { 30260 /* vsoxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13135 { 30260 /* vsoxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13136 { 30275 /* vsoxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13137 { 30275 /* vsoxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13138 { 30290 /* vsoxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13139 { 30290 /* vsoxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13140 { 30305 /* vsoxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13141 { 30305 /* vsoxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13142 { 30319 /* vsoxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13143 { 30319 /* vsoxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13144 { 30334 /* vsoxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13145 { 30334 /* vsoxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13146 { 30349 /* vsoxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13147 { 30349 /* vsoxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13148 { 30364 /* vsoxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13149 { 30364 /* vsoxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13150 { 30378 /* vsoxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13151 { 30378 /* vsoxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13152 { 30393 /* vsoxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13153 { 30393 /* vsoxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13154 { 30408 /* vsoxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13155 { 30408 /* vsoxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13156 { 30423 /* vsoxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13157 { 30423 /* vsoxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13158 { 30437 /* vsra.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13159 { 30445 /* vsra.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13160 { 30453 /* vsra.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13161 { 30461 /* vsrl.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13162 { 30469 /* vsrl.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13163 { 30477 /* vsrl.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13164 { 30485 /* vsse16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13165 { 30485 /* vsse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13166 { 30494 /* vsse32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13167 { 30494 /* vsse32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13168 { 30503 /* vsse64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13169 { 30503 /* vsse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13170 { 30512 /* vsse8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13171 { 30512 /* vsse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13172 { 30520 /* vsseg2e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13173 { 30520 /* vsseg2e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13174 { 30532 /* vsseg2e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13175 { 30532 /* vsseg2e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13176 { 30544 /* vsseg2e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13177 { 30544 /* vsseg2e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13178 { 30556 /* vsseg2e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13179 { 30556 /* vsseg2e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13180 { 30567 /* vsseg3e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13181 { 30567 /* vsseg3e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13182 { 30579 /* vsseg3e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13183 { 30579 /* vsseg3e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13184 { 30591 /* vsseg3e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13185 { 30591 /* vsseg3e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13186 { 30603 /* vsseg3e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13187 { 30603 /* vsseg3e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13188 { 30614 /* vsseg4e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13189 { 30614 /* vsseg4e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13190 { 30626 /* vsseg4e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13191 { 30626 /* vsseg4e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13192 { 30638 /* vsseg4e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13193 { 30638 /* vsseg4e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13194 { 30650 /* vsseg4e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13195 { 30650 /* vsseg4e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13196 { 30661 /* vsseg5e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13197 { 30661 /* vsseg5e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13198 { 30673 /* vsseg5e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13199 { 30673 /* vsseg5e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13200 { 30685 /* vsseg5e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13201 { 30685 /* vsseg5e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13202 { 30697 /* vsseg5e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13203 { 30697 /* vsseg5e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13204 { 30708 /* vsseg6e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13205 { 30708 /* vsseg6e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13206 { 30720 /* vsseg6e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13207 { 30720 /* vsseg6e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13208 { 30732 /* vsseg6e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13209 { 30732 /* vsseg6e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13210 { 30744 /* vsseg6e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13211 { 30744 /* vsseg6e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13212 { 30755 /* vsseg7e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13213 { 30755 /* vsseg7e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13214 { 30767 /* vsseg7e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13215 { 30767 /* vsseg7e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13216 { 30779 /* vsseg7e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13217 { 30779 /* vsseg7e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13218 { 30791 /* vsseg7e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13219 { 30791 /* vsseg7e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13220 { 30802 /* vsseg8e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13221 { 30802 /* vsseg8e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13222 { 30814 /* vsseg8e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13223 { 30814 /* vsseg8e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13224 { 30826 /* vsseg8e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13225 { 30826 /* vsseg8e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13226 { 30838 /* vsseg8e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13227 { 30838 /* vsseg8e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13228 { 30849 /* vssra.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13229 { 30858 /* vssra.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13230 { 30867 /* vssra.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13231 { 30876 /* vssrl.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13232 { 30885 /* vssrl.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13233 { 30894 /* vssrl.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13234 { 30903 /* vssseg2e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13235 { 30903 /* vssseg2e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13236 { 30916 /* vssseg2e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13237 { 30916 /* vssseg2e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13238 { 30929 /* vssseg2e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13239 { 30929 /* vssseg2e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13240 { 30942 /* vssseg2e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13241 { 30942 /* vssseg2e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13242 { 30954 /* vssseg3e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13243 { 30954 /* vssseg3e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13244 { 30967 /* vssseg3e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13245 { 30967 /* vssseg3e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13246 { 30980 /* vssseg3e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13247 { 30980 /* vssseg3e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13248 { 30993 /* vssseg3e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13249 { 30993 /* vssseg3e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13250 { 31005 /* vssseg4e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13251 { 31005 /* vssseg4e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13252 { 31018 /* vssseg4e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13253 { 31018 /* vssseg4e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13254 { 31031 /* vssseg4e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13255 { 31031 /* vssseg4e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13256 { 31044 /* vssseg4e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13257 { 31044 /* vssseg4e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13258 { 31056 /* vssseg5e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13259 { 31056 /* vssseg5e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13260 { 31069 /* vssseg5e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13261 { 31069 /* vssseg5e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13262 { 31082 /* vssseg5e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13263 { 31082 /* vssseg5e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13264 { 31095 /* vssseg5e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13265 { 31095 /* vssseg5e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13266 { 31107 /* vssseg6e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13267 { 31107 /* vssseg6e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13268 { 31120 /* vssseg6e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13269 { 31120 /* vssseg6e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13270 { 31133 /* vssseg6e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13271 { 31133 /* vssseg6e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13272 { 31146 /* vssseg6e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13273 { 31146 /* vssseg6e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13274 { 31158 /* vssseg7e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13275 { 31158 /* vssseg7e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13276 { 31171 /* vssseg7e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13277 { 31171 /* vssseg7e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13278 { 31184 /* vssseg7e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13279 { 31184 /* vssseg7e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13280 { 31197 /* vssseg7e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13281 { 31197 /* vssseg7e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13282 { 31209 /* vssseg8e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13283 { 31209 /* vssseg8e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13284 { 31222 /* vssseg8e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13285 { 31222 /* vssseg8e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13286 { 31235 /* vssseg8e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13287 { 31235 /* vssseg8e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13288 { 31248 /* vssseg8e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13289 { 31248 /* vssseg8e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13290 { 31260 /* vssub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13291 { 31269 /* vssub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13292 { 31278 /* vssubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13293 { 31288 /* vssubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13294 { 31298 /* vsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13295 { 31306 /* vsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13296 { 31314 /* vsuxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13297 { 31314 /* vsuxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13298 { 31325 /* vsuxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13299 { 31325 /* vsuxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13300 { 31336 /* vsuxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13301 { 31336 /* vsuxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13302 { 31347 /* vsuxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13303 { 31347 /* vsuxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13304 { 31357 /* vsuxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13305 { 31357 /* vsuxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13306 { 31372 /* vsuxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13307 { 31372 /* vsuxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13308 { 31387 /* vsuxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13309 { 31387 /* vsuxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13310 { 31402 /* vsuxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13311 { 31402 /* vsuxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13312 { 31416 /* vsuxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13313 { 31416 /* vsuxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13314 { 31431 /* vsuxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13315 { 31431 /* vsuxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13316 { 31446 /* vsuxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13317 { 31446 /* vsuxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13318 { 31461 /* vsuxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13319 { 31461 /* vsuxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13320 { 31475 /* vsuxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13321 { 31475 /* vsuxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13322 { 31490 /* vsuxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13323 { 31490 /* vsuxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13324 { 31505 /* vsuxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13325 { 31505 /* vsuxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13326 { 31520 /* vsuxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13327 { 31520 /* vsuxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13328 { 31534 /* vsuxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13329 { 31534 /* vsuxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13330 { 31549 /* vsuxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13331 { 31549 /* vsuxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13332 { 31564 /* vsuxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13333 { 31564 /* vsuxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13334 { 31579 /* vsuxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13335 { 31579 /* vsuxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13336 { 31593 /* vsuxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13337 { 31593 /* vsuxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13338 { 31608 /* vsuxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13339 { 31608 /* vsuxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13340 { 31623 /* vsuxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13341 { 31623 /* vsuxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13342 { 31638 /* vsuxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13343 { 31638 /* vsuxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13344 { 31652 /* vsuxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13345 { 31652 /* vsuxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13346 { 31667 /* vsuxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13347 { 31667 /* vsuxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13348 { 31682 /* vsuxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13349 { 31682 /* vsuxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13350 { 31697 /* vsuxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13351 { 31697 /* vsuxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13352 { 31711 /* vsuxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13353 { 31711 /* vsuxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13354 { 31726 /* vsuxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13355 { 31726 /* vsuxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13356 { 31741 /* vsuxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13357 { 31741 /* vsuxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13358 { 31756 /* vsuxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13359 { 31756 /* vsuxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13360 { 31789 /* vunzipe.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13361 { 31799 /* vunzipo.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13362 { 31809 /* vwabda.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
13363 { 31819 /* vwabdau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
13364 { 31830 /* vwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13365 { 31839 /* vwadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13366 { 31848 /* vwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13367 { 31857 /* vwadd.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13368 { 31866 /* vwaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13369 { 31876 /* vwaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13370 { 31886 /* vwaddu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13371 { 31896 /* vwaddu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13372 { 31906 /* vwcvt.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13373 { 31918 /* vwcvtu.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13374 { 31931 /* vwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13375 { 31941 /* vwmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13376 { 31951 /* vwmaccsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13377 { 31963 /* vwmaccsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13378 { 31975 /* vwmaccu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13379 { 31986 /* vwmaccu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13380 { 31997 /* vwmaccus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13381 { 32020 /* vwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13382 { 32029 /* vwmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13383 { 32038 /* vwmulsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13384 { 32049 /* vwmulsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13385 { 32060 /* vwmulu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13386 { 32070 /* vwmulu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13387 { 32080 /* vwredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13388 { 32092 /* vwredsumu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13389 { 32105 /* vwsll.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
13390 { 32114 /* vwsll.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
13391 { 32123 /* vwsll.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
13392 { 32132 /* vwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13393 { 32141 /* vwsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13394 { 32150 /* vwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13395 { 32159 /* vwsub.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13396 { 32168 /* vwsubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13397 { 32178 /* vwsubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13398 { 32188 /* vwsubu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13399 { 32198 /* vwsubu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13400 { 32208 /* vxor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13401 { 32216 /* vxor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13402 { 32224 /* vxor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13403 { 32232 /* vzext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13404 { 32242 /* vzext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13405 { 32252 /* vzext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13406 { 32262 /* vzip.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13407 { 32270 /* wadd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13408 { 32275 /* wadda */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13409 { 32281 /* waddau */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13410 { 32288 /* waddu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13411 { 32298 /* wmacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13412 { 32304 /* wmaccsu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13413 { 32312 /* wmaccu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13414 { 32319 /* wmul */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13415 { 32324 /* wmulsu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13416 { 32331 /* wmulu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13417 { 32353 /* wsla */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13418 { 32358 /* wslai */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13419 { 32364 /* wsll */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13420 { 32369 /* wslli */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13421 { 32375 /* wsub */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13422 { 32380 /* wsuba */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13423 { 32386 /* wsubau */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13424 { 32393 /* wsubu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13425 { 32399 /* wzip16p */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13426 { 32407 /* wzip8p */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13427};
13428
13429ParseStatus RISCVAsmParser::
13430tryCustomParseOperand(OperandVector &Operands,
13431 unsigned MCK) {
13432
13433 switch(MCK) {
13434 case MCK_BareSymbol:
13435 return parseBareSymbol(Operands);
13436 case MCK_BareSymbolQC_E_LI:
13437 return parseBareSymbol(Operands);
13438 case MCK_CSRSystemRegister:
13439 return parseCSRSystemRegister(Operands);
13440 case MCK_RegReg:
13441 return parseRegReg(Operands);
13442 case MCK_CallSymbol:
13443 return parseCallSymbol(Operands);
13444 case MCK_FRMArg:
13445 return parseFRMArg(Operands);
13446 case MCK_FRMArgLegacy:
13447 return parseFRMArg(Operands);
13448 case MCK_FenceArg:
13449 return parseFenceArg(Operands);
13450 case MCK_GPRAsFPR16:
13451 return parseGPRAsFPR(Operands);
13452 case MCK_GPRAsFPR32:
13453 return parseGPRAsFPR(Operands);
13454 case MCK_GPRF64AsFPR:
13455 return parseGPRAsFPR64(Operands);
13456 case MCK_GPRPairAsFPR:
13457 return parseGPRPairAsFPR64(Operands);
13458 case MCK_GPRPairCRV32:
13459 return parseGPRPair<false>(Operands);
13460 case MCK_GPRPairNoX0RV32:
13461 return parseGPRPair<false>(Operands);
13462 case MCK_GPRPairRV32:
13463 return parseGPRPair<false>(Operands);
13464 case MCK_GPRPairRV64:
13465 return parseGPRPair<true>(Operands);
13466 case MCK_InsnCDirectiveOpcode:
13467 return parseInsnCDirectiveOpcode(Operands);
13468 case MCK_InsnDirectiveOpcode:
13469 return parseInsnDirectiveOpcode(Operands);
13470 case MCK_LoadFPImm:
13471 return parseFPImm(Operands);
13472 case MCK_NegStackAdj:
13473 return parseZcmpNegStackAdj(Operands);
13474 case MCK_PseudoJumpSymbol:
13475 return parsePseudoJumpSymbol(Operands);
13476 case MCK_QCAccessSymbol:
13477 return parseOperandWithSpecifier(Operands);
13478 case MCK_RTZArg:
13479 return parseFRMArg(Operands);
13480 case MCK_RegList:
13481 return parseRegList(Operands);
13482 case MCK_RegListS0:
13483 return parseRegListS0(Operands);
13484 case MCK_SMTI8:
13485 return parseSMTVType(Operands);
13486 case MCK_SMTVType:
13487 return parseSMTVType(Operands);
13488 case MCK_BareSImm21Lsb0:
13489 return parseJALOffset(Operands);
13490 case MCK_StackAdj:
13491 return parseZcmpStackAdj(Operands);
13492 case MCK_TLSDESCCallSymbol:
13493 return parseOperandWithSpecifier(Operands);
13494 case MCK_TPRelAddSymbol:
13495 return parseOperandWithSpecifier(Operands);
13496 case MCK_TileLambda:
13497 return parseTileLambda(Operands);
13498 case MCK_RVVMaskRegOpOperand:
13499 return parseMaskReg(Operands);
13500 case MCK_RVVScaleRegOpOperand:
13501 return parseVScaleReg(Operands);
13502 case MCK_XSfmmVType:
13503 return parseXSfmmVType(Operands);
13504 case MCK_ZeroOffsetMemOpOperand:
13505 return parseZeroOffsetMemOp(Operands);
13506 case MCK_VTypeI10:
13507 return parseVTypeI(Operands);
13508 case MCK_VTypeI11:
13509 return parseVTypeI(Operands);
13510 default:
13511 return ParseStatus::NoMatch;
13512 }
13513 return ParseStatus::NoMatch;
13514}
13515
13516ParseStatus RISCVAsmParser::
13517MatchOperandParserImpl(OperandVector &Operands,
13518 StringRef Mnemonic,
13519 bool ParseForAllFeatures) {
13520 // Get the current feature set.
13521 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
13522
13523 // Get the next operand index.
13524 unsigned NextOpNum = Operands.size() - 1;
13525 // Search the table.
13526 auto MnemonicRange =
13527 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
13528 Mnemonic, LessOpcodeOperand());
13529
13530 if (MnemonicRange.first == MnemonicRange.second)
13531 return ParseStatus::NoMatch;
13532
13533 for (const OperandMatchEntry *it = MnemonicRange.first,
13534 *ie = MnemonicRange.second; it != ie; ++it) {
13535 // equal_range guarantees that instruction mnemonic matches.
13536 assert(Mnemonic == it->getMnemonic());
13537
13538 // check if the available features match
13539 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
13540 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
13541 continue;
13542
13543 // check if the operand in question has a custom parser.
13544 if (!(it->OperandMask & (1 << NextOpNum)))
13545 continue;
13546
13547 // call custom parse method to handle the operand
13548 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
13549 if (!Result.isNoMatch())
13550 return Result;
13551 }
13552
13553 // Okay, we had no match.
13554 return ParseStatus::NoMatch;
13555}
13556
13557#endif // GET_MATCHER_IMPLEMENTATION
13558
13559
13560#ifdef GET_MNEMONIC_SPELL_CHECKER
13561#undef GET_MNEMONIC_SPELL_CHECKER
13562
13563static std::string RISCVMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
13564 const unsigned MaxEditDist = 2;
13565 std::vector<StringRef> Candidates;
13566 StringRef Prev = "";
13567
13568 // Find the appropriate table for this asm variant.
13569 const MatchEntry *Start, *End;
13570 switch (VariantID) {
13571 default: llvm_unreachable("invalid variant!");
13572 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
13573 }
13574
13575 for (auto I = Start; I < End; I++) {
13576 // Ignore unsupported instructions.
13577 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
13578 if ((FBS & RequiredFeatures) != RequiredFeatures)
13579 continue;
13580
13581 StringRef T = I->getMnemonic();
13582 // Avoid recomputing the edit distance for the same string.
13583 if (T == Prev)
13584 continue;
13585
13586 Prev = T;
13587 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
13588 if (Dist <= MaxEditDist)
13589 Candidates.push_back(T);
13590 }
13591
13592 if (Candidates.empty())
13593 return "";
13594
13595 std::string Res = ", did you mean: ";
13596 unsigned i = 0;
13597 for (; i < Candidates.size() - 1; i++)
13598 Res += Candidates[i].str() + ", ";
13599 return Res + Candidates[i].str() + "?";
13600}
13601
13602#endif // GET_MNEMONIC_SPELL_CHECKER
13603
13604
13605#ifdef GET_MNEMONIC_CHECKER
13606#undef GET_MNEMONIC_CHECKER
13607
13608static bool RISCVCheckMnemonic(StringRef Mnemonic,
13609 const FeatureBitset &AvailableFeatures,
13610 unsigned VariantID) {
13611 // Process all MnemonicAliases to remap the mnemonic.
13612 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
13613
13614 // Find the appropriate table for this asm variant.
13615 const MatchEntry *Start, *End;
13616 switch (VariantID) {
13617 default: llvm_unreachable("invalid variant!");
13618 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
13619 }
13620
13621 // Search the table.
13622 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
13623
13624 if (MnemonicRange.first == MnemonicRange.second)
13625 return false;
13626
13627 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
13628 it != ie; ++it) {
13629 const FeatureBitset &RequiredFeatures =
13630 FeatureBitsets[it->RequiredFeaturesIdx];
13631 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
13632 return true;
13633 }
13634 return false;
13635}
13636
13637#endif // GET_MNEMONIC_CHECKER
13638
13639