1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: RISCV.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands,
18 const SmallBitVector &OptionalOperandsMask,
19 ArrayRef<unsigned> DefaultsOffset);
20 void convertToMapAndConstraints(unsigned Kind,
21 const OperandVector &Operands) override;
22 unsigned MatchInstructionImpl(const OperandVector &Operands,
23 MCInst &Inst,
24 uint64_t &ErrorInfo,
25 FeatureBitset &MissingFeatures,
26 bool matchingInlineAsm,
27 unsigned VariantID = 0);
28 unsigned MatchInstructionImpl(const OperandVector &Operands,
29 MCInst &Inst,
30 uint64_t &ErrorInfo,
31 bool matchingInlineAsm,
32 unsigned VariantID = 0) {
33 FeatureBitset MissingFeatures;
34 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
35 matchingInlineAsm, VariantID);
36 }
37
38 ParseStatus MatchOperandParserImpl(
39 OperandVector &Operands,
40 StringRef Mnemonic,
41 bool ParseForAllFeatures = false);
42 ParseStatus tryCustomParseOperand(
43 OperandVector &Operands,
44 unsigned MCK);
45
46#endif // GET_ASSEMBLER_HEADER
47
48
49#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
50#undef GET_OPERAND_DIAGNOSTIC_TYPES
51
52 Match_InvalidBareSImm11Lsb0,
53 Match_InvalidBareSImm12Lsb0,
54 Match_InvalidBareSImm13Lsb0,
55 Match_InvalidBareSImm21Lsb0,
56 Match_InvalidBareSImm32,
57 Match_InvalidBareSImm32Lsb0,
58 Match_InvalidBareSImm9Lsb0,
59 Match_InvalidBareSymbol,
60 Match_InvalidBareSymbolQC_E_LI,
61 Match_InvalidCLUIImm,
62 Match_InvalidCSRSystemRegister,
63 Match_InvalidCallSymbol,
64 Match_InvalidImm5Zibi,
65 Match_InvalidImmFour,
66 Match_InvalidImmThree,
67 Match_InvalidImmXLenLI,
68 Match_InvalidImmXLenLI_Restricted,
69 Match_InvalidImmZero,
70 Match_InvalidLoadFPImm,
71 Match_InvalidPseudoJumpSymbol,
72 Match_InvalidRTZArg,
73 Match_InvalidRegClassGPRNoX0,
74 Match_InvalidRegClassGPRNoX0X2,
75 Match_InvalidRegClassGPRNoX2,
76 Match_InvalidRegClassGPRX1,
77 Match_InvalidRegClassGPRX1X5,
78 Match_InvalidRegClassGPRX31,
79 Match_InvalidRegClassGPRX5,
80 Match_InvalidRegClassSP,
81 Match_InvalidRegList,
82 Match_InvalidRegListS0,
83 Match_InvalidRnumArg,
84 Match_InvalidSImm10,
85 Match_InvalidSImm10Lsb0000NonZero,
86 Match_InvalidSImm10Unsigned,
87 Match_InvalidSImm11,
88 Match_InvalidSImm12,
89 Match_InvalidSImm12LO,
90 Match_InvalidSImm12Lsb00000,
91 Match_InvalidSImm16,
92 Match_InvalidSImm16NonZero,
93 Match_InvalidSImm18,
94 Match_InvalidSImm18Lsb0,
95 Match_InvalidSImm19Lsb00,
96 Match_InvalidSImm20LI,
97 Match_InvalidSImm20Lsb000,
98 Match_InvalidSImm26,
99 Match_InvalidSImm5,
100 Match_InvalidSImm5NonZero,
101 Match_InvalidSImm5Plus1,
102 Match_InvalidSImm6,
103 Match_InvalidSImm6NonZero,
104 Match_InvalidSImm8Unsigned,
105 Match_InvalidStackAdj,
106 Match_InvalidTLSDESCCallSymbol,
107 Match_InvalidTPRelAddSymbol,
108 Match_InvalidUImm1,
109 Match_InvalidUImm10,
110 Match_InvalidUImm10Lsb00NonZero,
111 Match_InvalidUImm11,
112 Match_InvalidUImm14Lsb00,
113 Match_InvalidUImm16,
114 Match_InvalidUImm16NonZero,
115 Match_InvalidUImm2,
116 Match_InvalidUImm20,
117 Match_InvalidUImm20AUIPC,
118 Match_InvalidUImm20LUI,
119 Match_InvalidUImm2Lsb0,
120 Match_InvalidUImm3,
121 Match_InvalidUImm32,
122 Match_InvalidUImm4,
123 Match_InvalidUImm48,
124 Match_InvalidUImm5,
125 Match_InvalidUImm5GE6Plus1,
126 Match_InvalidUImm5GT3,
127 Match_InvalidUImm5Lsb0,
128 Match_InvalidUImm5NonZero,
129 Match_InvalidUImm5Plus1,
130 Match_InvalidUImm5Slist,
131 Match_InvalidUImm6,
132 Match_InvalidUImm64,
133 Match_InvalidUImm6Lsb0,
134 Match_InvalidUImm7,
135 Match_InvalidUImm7Lsb00,
136 Match_InvalidUImm7Lsb000,
137 Match_InvalidUImm8,
138 Match_InvalidUImm8GE32,
139 Match_InvalidUImm8Lsb00,
140 Match_InvalidUImm8Lsb000,
141 Match_InvalidUImm9,
142 Match_InvalidUImm9Lsb000,
143 Match_InvalidUImmLog2XLen,
144 Match_InvalidUImmLog2XLenNonZero,
145 Match_InvalidVMaskCarryInRegister,
146 Match_InvalidVMaskRegister,
147 Match_InvalidVTypeI,
148 END_OPERAND_DIAGNOSTIC_TYPES
149#endif // GET_OPERAND_DIAGNOSTIC_TYPES
150
151
152#ifdef GET_REGISTER_MATCHER
153#undef GET_REGISTER_MATCHER
154
155// Bits for subtarget features that participate in instruction matching.
156enum SubtargetFeatureBits : uint8_t {
157 Feature_HasStdExtZibiBit = 47,
158 Feature_HasStdExtZicbomBit = 48,
159 Feature_HasStdExtZicbopBit = 49,
160 Feature_HasStdExtZicbozBit = 50,
161 Feature_HasStdExtZicsrBit = 54,
162 Feature_HasStdExtZicondBit = 53,
163 Feature_HasStdExtZifenceiBit = 55,
164 Feature_HasStdExtZihintpauseBit = 57,
165 Feature_HasStdExtZihintntlBit = 56,
166 Feature_HasStdExtZimopBit = 59,
167 Feature_HasStdExtZicfilpBit = 51,
168 Feature_NoStdExtZicfilpBit = 163,
169 Feature_HasStdExtZicfissBit = 52,
170 Feature_HasStdExtZilsdBit = 58,
171 Feature_HasStdExtZmmulBit = 67,
172 Feature_HasStdExtMBit = 9,
173 Feature_HasStdExtZaamoBit = 16,
174 Feature_HasStdExtZalrscBit = 20,
175 Feature_HasStdExtABit = 1,
176 Feature_HasStdExtZtsoBit = 68,
177 Feature_HasStdExtZabhaBit = 17,
178 Feature_HasStdExtZacasBit = 18,
179 Feature_HasStdExtZalasrBit = 19,
180 Feature_HasStdExtZawrsBit = 21,
181 Feature_HasStdExtFBit = 6,
182 Feature_HasStdExtDBit = 5,
183 Feature_HasStdExtQBit = 11,
184 Feature_HasStdExtZfhminBit = 43,
185 Feature_HasStdExtZfhBit = 41,
186 Feature_HasStdExtZfbfminBit = 40,
187 Feature_HasHalfFPLoadStoreMoveBit = 0,
188 Feature_HasStdExtZfaBit = 39,
189 Feature_HasStdExtZfinxBit = 44,
190 Feature_HasStdExtFOrZfinxBit = 7,
191 Feature_HasStdExtZdinxBit = 38,
192 Feature_HasStdExtZhinxminBit = 46,
193 Feature_HasStdExtZhinxBit = 45,
194 Feature_HasStdExtZcaBit = 32,
195 Feature_HasStdExtCBit = 2,
196 Feature_HasStdExtZcbBit = 33,
197 Feature_HasStdExtCOrZcdBit = 3,
198 Feature_HasStdExtZclsdBit = 34,
199 Feature_HasStdExtZcmpBit = 36,
200 Feature_HasStdExtZcmtBit = 37,
201 Feature_HasStdExtCOrZcfOrZceBit = 4,
202 Feature_HasStdExtZcmopBit = 35,
203 Feature_HasStdExtZbaBit = 22,
204 Feature_HasStdExtZbbBit = 23,
205 Feature_NoStdExtZbbBit = 161,
206 Feature_HasStdExtZbcBit = 25,
207 Feature_HasStdExtZbsBit = 31,
208 Feature_HasStdExtZbkbBit = 27,
209 Feature_NoStdExtZbkbBit = 162,
210 Feature_HasStdExtZbkxBit = 30,
211 Feature_HasStdExtZbbOrZbkbBit = 24,
212 Feature_HasStdExtZbkcBit = 29,
213 Feature_HasStdExtZbcOrZbkcBit = 26,
214 Feature_HasStdExtZkndBit = 60,
215 Feature_HasStdExtZkneBit = 62,
216 Feature_HasStdExtZkndOrZkneBit = 61,
217 Feature_HasStdExtZknhBit = 63,
218 Feature_HasStdExtZksedBit = 65,
219 Feature_HasStdExtZkshBit = 66,
220 Feature_HasStdExtZkrBit = 64,
221 Feature_HasStdExtZvfbfaBit = 72,
222 Feature_HasStdExtZvfbfminBit = 73,
223 Feature_HasStdExtZvfbfwmaBit = 75,
224 Feature_HasStdExtZfhOrZvfhBit = 42,
225 Feature_HasStdExtZvfofp8minBit = 76,
226 Feature_HasStdExtZvfbfminOrZvfofp8minBit = 74,
227 Feature_HasStdExtZvkbBit = 77,
228 Feature_HasStdExtZvbbBit = 69,
229 Feature_HasStdExtZvbcBit = 70,
230 Feature_HasStdExtZvbcOrZvbc32eBit = 71,
231 Feature_HasStdExtZvkgBit = 78,
232 Feature_HasStdExtZvkgsBit = 79,
233 Feature_HasStdExtZvknedBit = 80,
234 Feature_HasStdExtZvknhaBit = 81,
235 Feature_HasStdExtZvknhbBit = 83,
236 Feature_HasStdExtZvknhaOrZvknhbBit = 82,
237 Feature_HasStdExtZvksedBit = 84,
238 Feature_HasStdExtZvkshBit = 85,
239 Feature_HasStdExtZvqdotqBit = 86,
240 Feature_HasVInstructionsBit = 87,
241 Feature_HasVInstructionsI64Bit = 90,
242 Feature_HasVInstructionsAnyFBit = 88,
243 Feature_HasVInstructionsF16MinimalBit = 89,
244 Feature_HasStdExtHBit = 8,
245 Feature_HasStdExtSmrnmiBit = 13,
246 Feature_HasStdExtSvinvalBit = 14,
247 Feature_HasStdExtSmctrOrSsctrBit = 12,
248 Feature_HasStdExtPBit = 10,
249 Feature_HasStdExtZbkbOrPBit = 28,
250 Feature_HasStdExtYBit = 15,
251 Feature_HasVendorXVentanaCondOpsBit = 137,
252 Feature_HasVendorXTHeadBaBit = 126,
253 Feature_HasVendorXTHeadBbBit = 127,
254 Feature_HasVendorXTHeadBsBit = 128,
255 Feature_HasVendorXTHeadCondMovBit = 130,
256 Feature_HasVendorXTHeadCmoBit = 129,
257 Feature_HasVendorXTHeadFMemIdxBit = 131,
258 Feature_HasVendorXTHeadMacBit = 132,
259 Feature_HasVendorXTHeadMemIdxBit = 133,
260 Feature_HasVendorXTHeadMemPairBit = 134,
261 Feature_HasVendorXTHeadSyncBit = 135,
262 Feature_HasVendorXTHeadVdotBit = 136,
263 Feature_HasVendorXSfvcpBit = 117,
264 Feature_HasVendorXSfmmbaseBit = 116,
265 Feature_HasVendorXSfmm32a8fBit = 113,
266 Feature_HasVendorXSfmm32a8iBit = 114,
267 Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit = 115,
268 Feature_HasVendorXSfvqmaccdodBit = 122,
269 Feature_HasVendorXSfvqmaccqoqBit = 123,
270 Feature_HasVendorXSfvfwmaccqqqBit = 121,
271 Feature_HasVendorXSfvfnrclipxfqfBit = 120,
272 Feature_HasVendorXSfvfexpAnyBit = 118,
273 Feature_HasVendorXSfvfexpaBit = 119,
274 Feature_HasVendorXSiFivecdiscarddloneBit = 124,
275 Feature_HasVendorXSiFivecflushdloneBit = 125,
276 Feature_HasVendorXSfceaseBit = 112,
277 Feature_HasVendorXCVelwBit = 101,
278 Feature_HasVendorXCVbitmanipBit = 100,
279 Feature_HasVendorXCVmacBit = 102,
280 Feature_HasVendorXCVmemBit = 103,
281 Feature_HasVendorXCValuBit = 98,
282 Feature_HasVendorXCVsimdBit = 104,
283 Feature_HasVendorXCVbiBit = 99,
284 Feature_HasVendorXMIPSCMovBit = 106,
285 Feature_HasVendorXMIPSLSPBit = 108,
286 Feature_HasVendorXMIPSCBOPBit = 105,
287 Feature_HasVendorXMIPSEXECTLBit = 107,
288 Feature_HasVendorXwchcBit = 157,
289 Feature_HasVendorXqccmpBit = 138,
290 Feature_HasVendorXqciaBit = 139,
291 Feature_HasVendorXqciacBit = 140,
292 Feature_HasVendorXqcibiBit = 141,
293 Feature_HasVendorXqcibmBit = 142,
294 Feature_HasVendorXqcicliBit = 143,
295 Feature_HasVendorXqcicmBit = 144,
296 Feature_HasVendorXqcicsBit = 145,
297 Feature_HasVendorXqcicsrBit = 146,
298 Feature_HasVendorXqciintBit = 147,
299 Feature_HasVendorXqciioBit = 148,
300 Feature_HasVendorXqcilbBit = 149,
301 Feature_HasVendorXqciliBit = 150,
302 Feature_HasVendorXqciliaBit = 151,
303 Feature_HasVendorXqciloBit = 152,
304 Feature_HasVendorXqcilsmBit = 153,
305 Feature_HasVendorXqcisimBit = 154,
306 Feature_HasVendorXqcislsBit = 155,
307 Feature_HasVendorXqcisyncBit = 156,
308 Feature_HasVendorXRivosVisniBit = 109,
309 Feature_HasVendorXRivosVizipBit = 110,
310 Feature_HasVendorXAndesPerfBit = 92,
311 Feature_HasVendorXAndesBFHCvtBit = 91,
312 Feature_HasVendorXAndesVBFHCvtBit = 93,
313 Feature_HasVendorXAndesVSIntHBit = 96,
314 Feature_HasVendorXAndesVSIntLoadBit = 97,
315 Feature_HasVendorXAndesVPackFPHBit = 95,
316 Feature_HasVendorXAndesVDotBit = 94,
317 Feature_HasVendorXSMTVDotBit = 111,
318 Feature_HasXAIFETBit = 158,
319 Feature_IsRV64Bit = 160,
320 Feature_IsRV32Bit = 159,
321};
322
323static MCRegister MatchRegisterName(StringRef Name) {
324 switch (Name.size()) {
325 default: break;
326 case 1: // 1 string to match.
327 if (Name[0] != '0')
328 break;
329 return RISCV::DUMMY_REG_PAIR_WITH_X0; // "0"
330 case 2: // 212 strings to match.
331 switch (Name[0]) {
332 default: break;
333 case 'f': // 50 strings to match.
334 switch (Name[1]) {
335 default: break;
336 case '0': // 5 strings to match.
337 return RISCV::F0_D; // "f0"
338 case '1': // 5 strings to match.
339 return RISCV::F1_D; // "f1"
340 case '2': // 5 strings to match.
341 return RISCV::F2_D; // "f2"
342 case '3': // 5 strings to match.
343 return RISCV::F3_D; // "f3"
344 case '4': // 5 strings to match.
345 return RISCV::F4_D; // "f4"
346 case '5': // 5 strings to match.
347 return RISCV::F5_D; // "f5"
348 case '6': // 5 strings to match.
349 return RISCV::F6_D; // "f6"
350 case '7': // 5 strings to match.
351 return RISCV::F7_D; // "f7"
352 case '8': // 5 strings to match.
353 return RISCV::F8_D; // "f8"
354 case '9': // 5 strings to match.
355 return RISCV::F9_D; // "f9"
356 }
357 break;
358 case 'm': // 8 strings to match.
359 switch (Name[1]) {
360 default: break;
361 case '0': // 1 string to match.
362 return RISCV::M0; // "m0"
363 case '1': // 1 string to match.
364 return RISCV::M1; // "m1"
365 case '2': // 1 string to match.
366 return RISCV::M2; // "m2"
367 case '3': // 1 string to match.
368 return RISCV::M3; // "m3"
369 case '4': // 1 string to match.
370 return RISCV::M4; // "m4"
371 case '5': // 1 string to match.
372 return RISCV::M5; // "m5"
373 case '6': // 1 string to match.
374 return RISCV::M6; // "m6"
375 case '7': // 1 string to match.
376 return RISCV::M7; // "m7"
377 }
378 break;
379 case 'v': // 109 strings to match.
380 switch (Name[1]) {
381 default: break;
382 case '0': // 15 strings to match.
383 return RISCV::V0; // "v0"
384 case '1': // 8 strings to match.
385 return RISCV::V1; // "v1"
386 case '2': // 12 strings to match.
387 return RISCV::V2; // "v2"
388 case '3': // 8 strings to match.
389 return RISCV::V3; // "v3"
390 case '4': // 14 strings to match.
391 return RISCV::V4; // "v4"
392 case '5': // 8 strings to match.
393 return RISCV::V5; // "v5"
394 case '6': // 12 strings to match.
395 return RISCV::V6; // "v6"
396 case '7': // 8 strings to match.
397 return RISCV::V7; // "v7"
398 case '8': // 15 strings to match.
399 return RISCV::V8; // "v8"
400 case '9': // 8 strings to match.
401 return RISCV::V9; // "v9"
402 case 'l': // 1 string to match.
403 return RISCV::VL; // "vl"
404 }
405 break;
406 case 'x': // 45 strings to match.
407 switch (Name[1]) {
408 default: break;
409 case '0': // 5 strings to match.
410 return RISCV::X0; // "x0"
411 case '1': // 4 strings to match.
412 return RISCV::X1; // "x1"
413 case '2': // 5 strings to match.
414 return RISCV::X2; // "x2"
415 case '3': // 4 strings to match.
416 return RISCV::X3; // "x3"
417 case '4': // 5 strings to match.
418 return RISCV::X4; // "x4"
419 case '5': // 4 strings to match.
420 return RISCV::X5; // "x5"
421 case '6': // 5 strings to match.
422 return RISCV::X6; // "x6"
423 case '7': // 4 strings to match.
424 return RISCV::X7; // "x7"
425 case '8': // 5 strings to match.
426 return RISCV::X8; // "x8"
427 case '9': // 4 strings to match.
428 return RISCV::X9; // "x9"
429 }
430 break;
431 }
432 break;
433 case 3: // 418 strings to match.
434 switch (Name[0]) {
435 default: break;
436 case 'f': // 111 strings to match.
437 switch (Name[1]) {
438 default: break;
439 case '1': // 50 strings to match.
440 switch (Name[2]) {
441 default: break;
442 case '0': // 5 strings to match.
443 return RISCV::F10_D; // "f10"
444 case '1': // 5 strings to match.
445 return RISCV::F11_D; // "f11"
446 case '2': // 5 strings to match.
447 return RISCV::F12_D; // "f12"
448 case '3': // 5 strings to match.
449 return RISCV::F13_D; // "f13"
450 case '4': // 5 strings to match.
451 return RISCV::F14_D; // "f14"
452 case '5': // 5 strings to match.
453 return RISCV::F15_D; // "f15"
454 case '6': // 5 strings to match.
455 return RISCV::F16_D; // "f16"
456 case '7': // 5 strings to match.
457 return RISCV::F17_D; // "f17"
458 case '8': // 5 strings to match.
459 return RISCV::F18_D; // "f18"
460 case '9': // 5 strings to match.
461 return RISCV::F19_D; // "f19"
462 }
463 break;
464 case '2': // 50 strings to match.
465 switch (Name[2]) {
466 default: break;
467 case '0': // 5 strings to match.
468 return RISCV::F20_D; // "f20"
469 case '1': // 5 strings to match.
470 return RISCV::F21_D; // "f21"
471 case '2': // 5 strings to match.
472 return RISCV::F22_D; // "f22"
473 case '3': // 5 strings to match.
474 return RISCV::F23_D; // "f23"
475 case '4': // 5 strings to match.
476 return RISCV::F24_D; // "f24"
477 case '5': // 5 strings to match.
478 return RISCV::F25_D; // "f25"
479 case '6': // 5 strings to match.
480 return RISCV::F26_D; // "f26"
481 case '7': // 5 strings to match.
482 return RISCV::F27_D; // "f27"
483 case '8': // 5 strings to match.
484 return RISCV::F28_D; // "f28"
485 case '9': // 5 strings to match.
486 return RISCV::F29_D; // "f29"
487 }
488 break;
489 case '3': // 10 strings to match.
490 switch (Name[2]) {
491 default: break;
492 case '0': // 5 strings to match.
493 return RISCV::F30_D; // "f30"
494 case '1': // 5 strings to match.
495 return RISCV::F31_D; // "f31"
496 }
497 break;
498 case 'r': // 1 string to match.
499 if (Name[2] != 'm')
500 break;
501 return RISCV::FRM; // "frm"
502 }
503 break;
504 case 'm': // 10 strings to match.
505 if (Name[1] != 't')
506 break;
507 switch (Name[2]) {
508 default: break;
509 case '0': // 1 string to match.
510 return RISCV::T0; // "mt0"
511 case '1': // 1 string to match.
512 return RISCV::T1; // "mt1"
513 case '2': // 1 string to match.
514 return RISCV::T2; // "mt2"
515 case '3': // 1 string to match.
516 return RISCV::T3; // "mt3"
517 case '4': // 1 string to match.
518 return RISCV::T4; // "mt4"
519 case '5': // 1 string to match.
520 return RISCV::T5; // "mt5"
521 case '6': // 1 string to match.
522 return RISCV::T6; // "mt6"
523 case '7': // 1 string to match.
524 return RISCV::T7; // "mt7"
525 case '8': // 1 string to match.
526 return RISCV::T8; // "mt8"
527 case '9': // 1 string to match.
528 return RISCV::T9; // "mt9"
529 }
530 break;
531 case 's': // 1 string to match.
532 if (memcmp(Name.data()+1, "sp", 2) != 0)
533 break;
534 return RISCV::SSP; // "ssp"
535 case 'v': // 197 strings to match.
536 switch (Name[1]) {
537 default: break;
538 case '1': // 105 strings to match.
539 switch (Name[2]) {
540 default: break;
541 case '0': // 12 strings to match.
542 return RISCV::V10; // "v10"
543 case '1': // 8 strings to match.
544 return RISCV::V11; // "v11"
545 case '2': // 14 strings to match.
546 return RISCV::V12; // "v12"
547 case '3': // 8 strings to match.
548 return RISCV::V13; // "v13"
549 case '4': // 12 strings to match.
550 return RISCV::V14; // "v14"
551 case '5': // 8 strings to match.
552 return RISCV::V15; // "v15"
553 case '6': // 15 strings to match.
554 return RISCV::V16; // "v16"
555 case '7': // 8 strings to match.
556 return RISCV::V17; // "v17"
557 case '8': // 12 strings to match.
558 return RISCV::V18; // "v18"
559 case '9': // 8 strings to match.
560 return RISCV::V19; // "v19"
561 }
562 break;
563 case '2': // 88 strings to match.
564 switch (Name[2]) {
565 default: break;
566 case '0': // 14 strings to match.
567 return RISCV::V20; // "v20"
568 case '1': // 8 strings to match.
569 return RISCV::V21; // "v21"
570 case '2': // 12 strings to match.
571 return RISCV::V22; // "v22"
572 case '3': // 8 strings to match.
573 return RISCV::V23; // "v23"
574 case '4': // 15 strings to match.
575 return RISCV::V24; // "v24"
576 case '5': // 7 strings to match.
577 return RISCV::V25; // "v25"
578 case '6': // 9 strings to match.
579 return RISCV::V26; // "v26"
580 case '7': // 5 strings to match.
581 return RISCV::V27; // "v27"
582 case '8': // 7 strings to match.
583 return RISCV::V28; // "v28"
584 case '9': // 3 strings to match.
585 return RISCV::V29; // "v29"
586 }
587 break;
588 case '3': // 4 strings to match.
589 switch (Name[2]) {
590 default: break;
591 case '0': // 3 strings to match.
592 return RISCV::V30; // "v30"
593 case '1': // 1 string to match.
594 return RISCV::V31; // "v31"
595 }
596 break;
597 }
598 break;
599 case 'x': // 99 strings to match.
600 switch (Name[1]) {
601 default: break;
602 case '1': // 45 strings to match.
603 switch (Name[2]) {
604 default: break;
605 case '0': // 5 strings to match.
606 return RISCV::X10; // "x10"
607 case '1': // 4 strings to match.
608 return RISCV::X11; // "x11"
609 case '2': // 5 strings to match.
610 return RISCV::X12; // "x12"
611 case '3': // 4 strings to match.
612 return RISCV::X13; // "x13"
613 case '4': // 5 strings to match.
614 return RISCV::X14; // "x14"
615 case '5': // 4 strings to match.
616 return RISCV::X15; // "x15"
617 case '6': // 5 strings to match.
618 return RISCV::X16; // "x16"
619 case '7': // 4 strings to match.
620 return RISCV::X17; // "x17"
621 case '8': // 5 strings to match.
622 return RISCV::X18; // "x18"
623 case '9': // 4 strings to match.
624 return RISCV::X19; // "x19"
625 }
626 break;
627 case '2': // 45 strings to match.
628 switch (Name[2]) {
629 default: break;
630 case '0': // 5 strings to match.
631 return RISCV::X20; // "x20"
632 case '1': // 4 strings to match.
633 return RISCV::X21; // "x21"
634 case '2': // 5 strings to match.
635 return RISCV::X22; // "x22"
636 case '3': // 4 strings to match.
637 return RISCV::X23; // "x23"
638 case '4': // 5 strings to match.
639 return RISCV::X24; // "x24"
640 case '5': // 4 strings to match.
641 return RISCV::X25; // "x25"
642 case '6': // 5 strings to match.
643 return RISCV::X26; // "x26"
644 case '7': // 4 strings to match.
645 return RISCV::X27; // "x27"
646 case '8': // 5 strings to match.
647 return RISCV::X28; // "x28"
648 case '9': // 4 strings to match.
649 return RISCV::X29; // "x29"
650 }
651 break;
652 case '3': // 9 strings to match.
653 switch (Name[2]) {
654 default: break;
655 case '0': // 5 strings to match.
656 return RISCV::X30; // "x30"
657 case '1': // 4 strings to match.
658 return RISCV::X31; // "x31"
659 }
660 break;
661 }
662 break;
663 }
664 break;
665 case 4: // 8 strings to match.
666 switch (Name[0]) {
667 default: break;
668 case 'f': // 1 string to match.
669 if (memcmp(Name.data()+1, "csr", 3) != 0)
670 break;
671 return RISCV::FCSR; // "fcsr"
672 case 'm': // 6 strings to match.
673 if (memcmp(Name.data()+1, "t1", 2) != 0)
674 break;
675 switch (Name[3]) {
676 default: break;
677 case '0': // 1 string to match.
678 return RISCV::T10; // "mt10"
679 case '1': // 1 string to match.
680 return RISCV::T11; // "mt11"
681 case '2': // 1 string to match.
682 return RISCV::T12; // "mt12"
683 case '3': // 1 string to match.
684 return RISCV::T13; // "mt13"
685 case '4': // 1 string to match.
686 return RISCV::T14; // "mt14"
687 case '5': // 1 string to match.
688 return RISCV::T15; // "mt15"
689 }
690 break;
691 case 'v': // 1 string to match.
692 if (memcmp(Name.data()+1, "xrm", 3) != 0)
693 break;
694 return RISCV::VXRM; // "vxrm"
695 }
696 break;
697 case 5: // 3 strings to match.
698 if (Name[0] != 'v')
699 break;
700 switch (Name[1]) {
701 default: break;
702 case 'l': // 1 string to match.
703 if (memcmp(Name.data()+2, "enb", 3) != 0)
704 break;
705 return RISCV::VLENB; // "vlenb"
706 case 't': // 1 string to match.
707 if (memcmp(Name.data()+2, "ype", 3) != 0)
708 break;
709 return RISCV::VTYPE; // "vtype"
710 case 'x': // 1 string to match.
711 if (memcmp(Name.data()+2, "sat", 3) != 0)
712 break;
713 return RISCV::VXSAT; // "vxsat"
714 }
715 break;
716 case 6: // 1 string to match.
717 if (memcmp(Name.data()+0, "fflags", 6) != 0)
718 break;
719 return RISCV::FFLAGS; // "fflags"
720 case 13: // 1 string to match.
721 if (memcmp(Name.data()+0, "sf.vcix_state", 13) != 0)
722 break;
723 return RISCV::SF_VCIX_STATE; // "sf.vcix_state"
724 }
725 return RISCV::NoRegister;
726}
727
728static MCRegister MatchRegisterAltName(StringRef Name) {
729 switch (Name.size()) {
730 default: break;
731 case 2: // 143 strings to match.
732 switch (Name[0]) {
733 default: break;
734 case 'a': // 36 strings to match.
735 switch (Name[1]) {
736 default: break;
737 case '0': // 5 strings to match.
738 return RISCV::X10; // "a0"
739 case '1': // 4 strings to match.
740 return RISCV::X11; // "a1"
741 case '2': // 5 strings to match.
742 return RISCV::X12; // "a2"
743 case '3': // 4 strings to match.
744 return RISCV::X13; // "a3"
745 case '4': // 5 strings to match.
746 return RISCV::X14; // "a4"
747 case '5': // 4 strings to match.
748 return RISCV::X15; // "a5"
749 case '6': // 5 strings to match.
750 return RISCV::X16; // "a6"
751 case '7': // 4 strings to match.
752 return RISCV::X17; // "a7"
753 }
754 break;
755 case 'f': // 5 strings to match.
756 if (Name[1] != 'p')
757 break;
758 return RISCV::X8; // "fp"
759 case 'g': // 4 strings to match.
760 if (Name[1] != 'p')
761 break;
762 return RISCV::X3; // "gp"
763 case 'm': // 8 strings to match.
764 switch (Name[1]) {
765 default: break;
766 case '0': // 1 string to match.
767 return RISCV::M0; // "m0"
768 case '1': // 1 string to match.
769 return RISCV::M1; // "m1"
770 case '2': // 1 string to match.
771 return RISCV::M2; // "m2"
772 case '3': // 1 string to match.
773 return RISCV::M3; // "m3"
774 case '4': // 1 string to match.
775 return RISCV::M4; // "m4"
776 case '5': // 1 string to match.
777 return RISCV::M5; // "m5"
778 case '6': // 1 string to match.
779 return RISCV::M6; // "m6"
780 case '7': // 1 string to match.
781 return RISCV::M7; // "m7"
782 }
783 break;
784 case 'r': // 4 strings to match.
785 if (Name[1] != 'a')
786 break;
787 return RISCV::X1; // "ra"
788 case 's': // 50 strings to match.
789 switch (Name[1]) {
790 default: break;
791 case '0': // 5 strings to match.
792 return RISCV::X8; // "s0"
793 case '1': // 4 strings to match.
794 return RISCV::X9; // "s1"
795 case '2': // 5 strings to match.
796 return RISCV::X18; // "s2"
797 case '3': // 4 strings to match.
798 return RISCV::X19; // "s3"
799 case '4': // 5 strings to match.
800 return RISCV::X20; // "s4"
801 case '5': // 4 strings to match.
802 return RISCV::X21; // "s5"
803 case '6': // 5 strings to match.
804 return RISCV::X22; // "s6"
805 case '7': // 4 strings to match.
806 return RISCV::X23; // "s7"
807 case '8': // 5 strings to match.
808 return RISCV::X24; // "s8"
809 case '9': // 4 strings to match.
810 return RISCV::X25; // "s9"
811 case 'p': // 5 strings to match.
812 return RISCV::X2; // "sp"
813 }
814 break;
815 case 't': // 36 strings to match.
816 switch (Name[1]) {
817 default: break;
818 case '0': // 4 strings to match.
819 return RISCV::X5; // "t0"
820 case '1': // 5 strings to match.
821 return RISCV::X6; // "t1"
822 case '2': // 4 strings to match.
823 return RISCV::X7; // "t2"
824 case '3': // 5 strings to match.
825 return RISCV::X28; // "t3"
826 case '4': // 4 strings to match.
827 return RISCV::X29; // "t4"
828 case '5': // 5 strings to match.
829 return RISCV::X30; // "t5"
830 case '6': // 4 strings to match.
831 return RISCV::X31; // "t6"
832 case 'p': // 5 strings to match.
833 return RISCV::X4; // "tp"
834 }
835 break;
836 }
837 break;
838 case 3: // 149 strings to match.
839 switch (Name[0]) {
840 default: break;
841 case 'f': // 140 strings to match.
842 switch (Name[1]) {
843 default: break;
844 case 'a': // 40 strings to match.
845 switch (Name[2]) {
846 default: break;
847 case '0': // 5 strings to match.
848 return RISCV::F10_D; // "fa0"
849 case '1': // 5 strings to match.
850 return RISCV::F11_D; // "fa1"
851 case '2': // 5 strings to match.
852 return RISCV::F12_D; // "fa2"
853 case '3': // 5 strings to match.
854 return RISCV::F13_D; // "fa3"
855 case '4': // 5 strings to match.
856 return RISCV::F14_D; // "fa4"
857 case '5': // 5 strings to match.
858 return RISCV::F15_D; // "fa5"
859 case '6': // 5 strings to match.
860 return RISCV::F16_D; // "fa6"
861 case '7': // 5 strings to match.
862 return RISCV::F17_D; // "fa7"
863 }
864 break;
865 case 's': // 50 strings to match.
866 switch (Name[2]) {
867 default: break;
868 case '0': // 5 strings to match.
869 return RISCV::F8_D; // "fs0"
870 case '1': // 5 strings to match.
871 return RISCV::F9_D; // "fs1"
872 case '2': // 5 strings to match.
873 return RISCV::F18_D; // "fs2"
874 case '3': // 5 strings to match.
875 return RISCV::F19_D; // "fs3"
876 case '4': // 5 strings to match.
877 return RISCV::F20_D; // "fs4"
878 case '5': // 5 strings to match.
879 return RISCV::F21_D; // "fs5"
880 case '6': // 5 strings to match.
881 return RISCV::F22_D; // "fs6"
882 case '7': // 5 strings to match.
883 return RISCV::F23_D; // "fs7"
884 case '8': // 5 strings to match.
885 return RISCV::F24_D; // "fs8"
886 case '9': // 5 strings to match.
887 return RISCV::F25_D; // "fs9"
888 }
889 break;
890 case 't': // 50 strings to match.
891 switch (Name[2]) {
892 default: break;
893 case '0': // 5 strings to match.
894 return RISCV::F0_D; // "ft0"
895 case '1': // 5 strings to match.
896 return RISCV::F1_D; // "ft1"
897 case '2': // 5 strings to match.
898 return RISCV::F2_D; // "ft2"
899 case '3': // 5 strings to match.
900 return RISCV::F3_D; // "ft3"
901 case '4': // 5 strings to match.
902 return RISCV::F4_D; // "ft4"
903 case '5': // 5 strings to match.
904 return RISCV::F5_D; // "ft5"
905 case '6': // 5 strings to match.
906 return RISCV::F6_D; // "ft6"
907 case '7': // 5 strings to match.
908 return RISCV::F7_D; // "ft7"
909 case '8': // 5 strings to match.
910 return RISCV::F28_D; // "ft8"
911 case '9': // 5 strings to match.
912 return RISCV::F29_D; // "ft9"
913 }
914 break;
915 }
916 break;
917 case 's': // 9 strings to match.
918 if (Name[1] != '1')
919 break;
920 switch (Name[2]) {
921 default: break;
922 case '0': // 5 strings to match.
923 return RISCV::X26; // "s10"
924 case '1': // 4 strings to match.
925 return RISCV::X27; // "s11"
926 }
927 break;
928 }
929 break;
930 case 4: // 26 strings to match.
931 switch (Name[0]) {
932 default: break;
933 case 'f': // 20 strings to match.
934 switch (Name[1]) {
935 default: break;
936 case 's': // 10 strings to match.
937 if (Name[2] != '1')
938 break;
939 switch (Name[3]) {
940 default: break;
941 case '0': // 5 strings to match.
942 return RISCV::F26_D; // "fs10"
943 case '1': // 5 strings to match.
944 return RISCV::F27_D; // "fs11"
945 }
946 break;
947 case 't': // 10 strings to match.
948 if (Name[2] != '1')
949 break;
950 switch (Name[3]) {
951 default: break;
952 case '0': // 5 strings to match.
953 return RISCV::F30_D; // "ft10"
954 case '1': // 5 strings to match.
955 return RISCV::F31_D; // "ft11"
956 }
957 break;
958 }
959 break;
960 case 'n': // 1 string to match.
961 if (memcmp(Name.data()+1, "ull", 3) != 0)
962 break;
963 return RISCV::X0_Y; // "null"
964 case 'z': // 5 strings to match.
965 if (memcmp(Name.data()+1, "ero", 3) != 0)
966 break;
967 return RISCV::X0; // "zero"
968 }
969 break;
970 }
971 return RISCV::NoRegister;
972}
973
974#endif // GET_REGISTER_MATCHER
975
976
977#ifdef GET_SUBTARGET_FEATURE_NAME
978#undef GET_SUBTARGET_FEATURE_NAME
979
980// User-level names for subtarget features that participate in
981// instruction matching.
982static const char *getSubtargetFeatureName(uint64_t Val) {
983 switch(Val) {
984 case Feature_HasStdExtZibiBit: return "'Zibi' (Branch with Immediate)";
985 case Feature_HasStdExtZicbomBit: return "'Zicbom' (Cache-Block Management Instructions)";
986 case Feature_HasStdExtZicbopBit: return "'Zicbop' (Cache-Block Prefetch Instructions)";
987 case Feature_HasStdExtZicbozBit: return "'Zicboz' (Cache-Block Zero Instructions)";
988 case Feature_HasStdExtZicsrBit: return "'Zicsr' (CSRs)";
989 case Feature_HasStdExtZicondBit: return "(Integer Conditional Operations)";
990 case Feature_HasStdExtZifenceiBit: return "'Zifencei' (fence.i)";
991 case Feature_HasStdExtZihintpauseBit: return "'Zihintpause' (Pause Hint)";
992 case Feature_HasStdExtZihintntlBit: return "'Zihintntl' (Non-Temporal Locality Hints)";
993 case Feature_HasStdExtZimopBit: return "'Zimop' (May-Be-Operations)";
994 case Feature_HasStdExtZicfilpBit: return "'Zicfilp' (Landing pad)";
995 case Feature_NoStdExtZicfilpBit: return "";
996 case Feature_HasStdExtZicfissBit: return "'Zicfiss' (Shadow stack)";
997 case Feature_HasStdExtZilsdBit: return "'Zilsd' (Load/Store pair instructions)";
998 case Feature_HasStdExtZmmulBit: return "'Zmmul' (Integer Multiplication)";
999 case Feature_HasStdExtMBit: return "'M' (Integer Multiplication and Division)";
1000 case Feature_HasStdExtZaamoBit: return "'Zaamo' (Atomic Memory Operations)";
1001 case Feature_HasStdExtZalrscBit: return "'Zalrsc' (Load-Reserved/Store-Conditional)";
1002 case Feature_HasStdExtABit: return "'A' (Atomic Instructions)";
1003 case Feature_HasStdExtZtsoBit: return "'Ztso' (Memory Model - Total Store Order)";
1004 case Feature_HasStdExtZabhaBit: return "'Zabha' (Byte and Halfword Atomic Memory Operations)";
1005 case Feature_HasStdExtZacasBit: return "'Zacas' (Atomic Compare-And-Swap Instructions)";
1006 case Feature_HasStdExtZalasrBit: return "'Zalasr' (Load-Acquire and Store-Release Instructions)";
1007 case Feature_HasStdExtZawrsBit: return "'Zawrs' (Wait on Reservation Set)";
1008 case Feature_HasStdExtFBit: return "'F' (Single-Precision Floating-Point)";
1009 case Feature_HasStdExtDBit: return "'D' (Double-Precision Floating-Point)";
1010 case Feature_HasStdExtQBit: return "'Q' (Quad-Precision Floating-Point)";
1011 case Feature_HasStdExtZfhminBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)";
1012 case Feature_HasStdExtZfhBit: return "'Zfh' (Half-Precision Floating-Point)";
1013 case Feature_HasStdExtZfbfminBit: return "'Zfbfmin' (Scalar BF16 Converts)";
1014 case Feature_HasHalfFPLoadStoreMoveBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts)";
1015 case Feature_HasStdExtZfaBit: return "'Zfa' (Additional Floating-Point)";
1016 case Feature_HasStdExtZfinxBit: return "'Zfinx' (Float in Integer)";
1017 case Feature_HasStdExtFOrZfinxBit: return "'F' (Single-Precision Floating-Point) or 'Zfinx' (Float in Integer)";
1018 case Feature_HasStdExtZdinxBit: return "'Zdinx' (Double in Integer)";
1019 case Feature_HasStdExtZhinxminBit: return "'Zhinx' (Half Float in Integer) or 'Zhinxmin' (Half Float in Integer Minimal)";
1020 case Feature_HasStdExtZhinxBit: return "'Zhinx' (Half Float in Integer)";
1021 case Feature_HasStdExtZcaBit: return "'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores)";
1022 case Feature_HasStdExtCBit: return "'C' (Compressed Instructions)";
1023 case Feature_HasStdExtZcbBit: return "'Zcb' (Compressed basic bit manipulation instructions)";
1024 case Feature_HasStdExtCOrZcdBit: return "'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions)";
1025 case Feature_HasStdExtZclsdBit: return "'Zclsd' (Compressed Load/Store pair instructions)";
1026 case Feature_HasStdExtZcmpBit: return "'Zcmp' (sequenced instructions for code-size reduction)";
1027 case Feature_HasStdExtZcmtBit: return "'Zcmt' (table jump instructions for code-size reduction)";
1028 case Feature_HasStdExtCOrZcfOrZceBit: return "'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions)";
1029 case Feature_HasStdExtZcmopBit: return "'Zcmop' (Compressed May-Be-Operations)";
1030 case Feature_HasStdExtZbaBit: return "'Zba' (Address Generation Instructions)";
1031 case Feature_HasStdExtZbbBit: return "'Zbb' (Basic Bit-Manipulation)";
1032 case Feature_NoStdExtZbbBit: return "";
1033 case Feature_HasStdExtZbcBit: return "'Zbc' (Carry-Less Multiplication)";
1034 case Feature_HasStdExtZbsBit: return "'Zbs' (Single-Bit Instructions)";
1035 case Feature_HasStdExtZbkbBit: return "'Zbkb' (Bitmanip instructions for Cryptography)";
1036 case Feature_NoStdExtZbkbBit: return "";
1037 case Feature_HasStdExtZbkxBit: return "'Zbkx' (Crossbar permutation instructions)";
1038 case Feature_HasStdExtZbbOrZbkbBit: return "'Zbb' (Basic Bit-Manipulation) or 'Zbkb' (Bitmanip instructions for Cryptography)";
1039 case Feature_HasStdExtZbkcBit: return "'Zbkc' (Carry-less multiply instructions for Cryptography)";
1040 case Feature_HasStdExtZbcOrZbkcBit: return "'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography)";
1041 case Feature_HasStdExtZkndBit: return "'Zknd' (NIST Suite: AES Decryption)";
1042 case Feature_HasStdExtZkneBit: return "'Zkne' (NIST Suite: AES Encryption)";
1043 case Feature_HasStdExtZkndOrZkneBit: return "'Zknd' (NIST Suite: AES Decryption) or 'Zkne' (NIST Suite: AES Encryption)";
1044 case Feature_HasStdExtZknhBit: return "'Zknh' (NIST Suite: Hash Function Instructions)";
1045 case Feature_HasStdExtZksedBit: return "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)";
1046 case Feature_HasStdExtZkshBit: return "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)";
1047 case Feature_HasStdExtZkrBit: return "'Zkr' (Entropy Source Extension)";
1048 case Feature_HasStdExtZvfbfaBit: return "'Zvfbfa' (Additional BF16 vector compute support)";
1049 case Feature_HasStdExtZvfbfminBit: return "'Zvfbfmin' (Vector BF16 Converts)";
1050 case Feature_HasStdExtZvfbfwmaBit: return "'Zvfbfwma' (Vector BF16 widening mul-add)";
1051 case Feature_HasStdExtZfhOrZvfhBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zvfh' (Vector Half-Precision Floating-Point)";
1052 case Feature_HasStdExtZvfofp8minBit: return "'Zvfofp8min' (Vector OFP8 Converts)";
1053 case Feature_HasStdExtZvfbfminOrZvfofp8minBit: return "'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts)";
1054 case Feature_HasStdExtZvkbBit: return "'Zvkb' (Vector Bit-manipulation used in Cryptography)";
1055 case Feature_HasStdExtZvbbBit: return "'Zvbb' (Vector basic bit-manipulation instructions)";
1056 case Feature_HasStdExtZvbcBit: return "'Zvbc' (Vector Carryless Multiplication)";
1057 case Feature_HasStdExtZvbcOrZvbc32eBit: return "'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)";
1058 case Feature_HasStdExtZvkgBit: return "'Zvkg' (Vector GCM instructions for Cryptography)";
1059 case Feature_HasStdExtZvkgsBit: return "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)";
1060 case Feature_HasStdExtZvknedBit: return "'Zvkned' (Vector AES Encryption & Decryption (Single Round))";
1061 case Feature_HasStdExtZvknhaBit: return "'Zvknha' (Vector SHA-2 (SHA-256 only))";
1062 case Feature_HasStdExtZvknhbBit: return "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))";
1063 case Feature_HasStdExtZvknhaOrZvknhbBit: return "'Zvknha' or 'Zvknhb' (Vector SHA-2)";
1064 case Feature_HasStdExtZvksedBit: return "'Zvksed' (SM4 Block Cipher Instructions)";
1065 case Feature_HasStdExtZvkshBit: return "'Zvksh' (SM3 Hash Function Instructions)";
1066 case Feature_HasStdExtZvqdotqBit: return "'Zvqdotq' (Vector quad widening 4D Dot Product)";
1067 case Feature_HasVInstructionsBit: return "'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors)";
1068 case Feature_HasVInstructionsI64Bit: return "'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors)";
1069 case Feature_HasVInstructionsAnyFBit: return "'V' (Vector Extension for Application Processors), 'Zve32f' (Vector Extensions for Embedded Processors)";
1070 case Feature_HasVInstructionsF16MinimalBit: return "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or 'Zvfh' (Vector Half-Precision Floating-Point)";
1071 case Feature_HasStdExtHBit: return "'H' (Hypervisor)";
1072 case Feature_HasStdExtSmrnmiBit: return "'Smrnmi' (Resumable Non-Maskable Interrupts)";
1073 case Feature_HasStdExtSvinvalBit: return "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)";
1074 case Feature_HasStdExtSmctrOrSsctrBit: return "'Smctr' (Control Transfer Records Machine Level) or 'Ssctr' (Control Transfer Records Supervisor Level)";
1075 case Feature_HasStdExtPBit: return "'Base P' (Packed SIMD)";
1076 case Feature_HasStdExtZbkbOrPBit: return "'Zbkb' (Bitmanip instructions for Cryptography) or 'Base P' (Packed-SIMD)";
1077 case Feature_HasStdExtYBit: return "'Base Y' (CHERI)";
1078 case Feature_HasVendorXVentanaCondOpsBit: return "'XVentanaCondOps' (Ventana Conditional Ops)";
1079 case Feature_HasVendorXTHeadBaBit: return "'XTHeadBa' (T-Head address calculation instructions)";
1080 case Feature_HasVendorXTHeadBbBit: return "'XTHeadBb' (T-Head basic bit-manipulation instructions)";
1081 case Feature_HasVendorXTHeadBsBit: return "'XTHeadBs' (T-Head single-bit instructions)";
1082 case Feature_HasVendorXTHeadCondMovBit: return "'XTHeadCondMov' (T-Head conditional move instructions)";
1083 case Feature_HasVendorXTHeadCmoBit: return "'XTHeadCmo' (T-Head cache management instructions)";
1084 case Feature_HasVendorXTHeadFMemIdxBit: return "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)";
1085 case Feature_HasVendorXTHeadMacBit: return "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)";
1086 case Feature_HasVendorXTHeadMemIdxBit: return "'XTHeadMemIdx' (T-Head Indexed Memory Operations)";
1087 case Feature_HasVendorXTHeadMemPairBit: return "'XTHeadMemPair' (T-Head two-GPR Memory Operations)";
1088 case Feature_HasVendorXTHeadSyncBit: return "'XTHeadSync' (T-Head multicore synchronization instructions)";
1089 case Feature_HasVendorXTHeadVdotBit: return "'XTHeadVdot' (T-Head Vector Extensions for Dot)";
1090 case Feature_HasVendorXSfvcpBit: return "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)";
1091 case Feature_HasVendorXSfmmbaseBit: return "'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)";
1092 case Feature_HasVendorXSfmm32a8fBit: return "'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)";
1093 case Feature_HasVendorXSfmm32a8iBit: return "'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)";
1094 case Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit: return "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF)), or 'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b), or 'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)";
1095 case Feature_HasVendorXSfvqmaccdodBit: return "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))";
1096 case Feature_HasVendorXSfvqmaccqoqBit: return "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))";
1097 case Feature_HasVendorXSfvfwmaccqqqBit: return "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))";
1098 case Feature_HasVendorXSfvfnrclipxfqfBit: return "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)";
1099 case Feature_HasVendorXSfvfexpAnyBit: return "'Xsfvfbfexp16e', 'Xsfvfexp16e', or 'Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction)";
1100 case Feature_HasVendorXSfvfexpaBit: return "'Xsfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)";
1101 case Feature_HasVendorXSiFivecdiscarddloneBit: return "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)";
1102 case Feature_HasVendorXSiFivecflushdloneBit: return "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)";
1103 case Feature_HasVendorXSfceaseBit: return "'XSfcease' (SiFive sf.cease Instruction)";
1104 case Feature_HasVendorXCVelwBit: return "'XCVelw' (CORE-V Event Load Word)";
1105 case Feature_HasVendorXCVbitmanipBit: return "'XCVbitmanip' (CORE-V Bit Manipulation)";
1106 case Feature_HasVendorXCVmacBit: return "'XCVmac' (CORE-V Multiply-Accumulate)";
1107 case Feature_HasVendorXCVmemBit: return "'XCVmem' (CORE-V Post-incrementing Load & Store)";
1108 case Feature_HasVendorXCValuBit: return "'XCValu' (CORE-V ALU Operations)";
1109 case Feature_HasVendorXCVsimdBit: return "'XCVsimd' (CORE-V SIMD ALU)";
1110 case Feature_HasVendorXCVbiBit: return "'XCVbi' (CORE-V Immediate Branching)";
1111 case Feature_HasVendorXMIPSCMovBit: return "'Xmipscmov' ('mips.ccmov' instruction)";
1112 case Feature_HasVendorXMIPSLSPBit: return "'Xmipslsp' (load and store pair instructions)";
1113 case Feature_HasVendorXMIPSCBOPBit: return "'Xmipscbop' (MIPS hardware prefetch)";
1114 case Feature_HasVendorXMIPSEXECTLBit: return "'Xmipsexectl' (MIPS execution control)";
1115 case Feature_HasVendorXwchcBit: return "'Xwchc' (WCH/QingKe additional compressed opcodes)";
1116 case Feature_HasVendorXqccmpBit: return "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)";
1117 case Feature_HasVendorXqciaBit: return "'Xqcia' (Qualcomm uC Arithmetic Extension)";
1118 case Feature_HasVendorXqciacBit: return "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)";
1119 case Feature_HasVendorXqcibiBit: return "'Xqcibi' (Qualcomm uC Branch Immediate Extension)";
1120 case Feature_HasVendorXqcibmBit: return "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)";
1121 case Feature_HasVendorXqcicliBit: return "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)";
1122 case Feature_HasVendorXqcicmBit: return "'Xqcicm' (Qualcomm uC Conditional Move Extension)";
1123 case Feature_HasVendorXqcicsBit: return "'Xqcics' (Qualcomm uC Conditional Select Extension)";
1124 case Feature_HasVendorXqcicsrBit: return "'Xqcicsr' (Qualcomm uC CSR Extension)";
1125 case Feature_HasVendorXqciintBit: return "'Xqciint' (Qualcomm uC Interrupts Extension)";
1126 case Feature_HasVendorXqciioBit: return "'Xqciio' (Qualcomm uC External Input Output Extension)";
1127 case Feature_HasVendorXqcilbBit: return "'Xqcilb' (Qualcomm uC Long Branch Extension)";
1128 case Feature_HasVendorXqciliBit: return "'Xqcili' (Qualcomm uC Load Large Immediate Extension)";
1129 case Feature_HasVendorXqciliaBit: return "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)";
1130 case Feature_HasVendorXqciloBit: return "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)";
1131 case Feature_HasVendorXqcilsmBit: return "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)";
1132 case Feature_HasVendorXqcisimBit: return "'Xqcisim' (Qualcomm uC Simulation Hint Extension)";
1133 case Feature_HasVendorXqcislsBit: return "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)";
1134 case Feature_HasVendorXqcisyncBit: return "'Xqcisync' (Qualcomm uC Sync Delay Extension)";
1135 case Feature_HasVendorXRivosVisniBit: return "'XRivosVisni' (Rivos Vector Integer Small New)";
1136 case Feature_HasVendorXRivosVizipBit: return "'XRivosVizip' (Rivos Vector Register Zips)";
1137 case Feature_HasVendorXAndesPerfBit: return "'XAndesPerf' (Andes Performance Extension)";
1138 case Feature_HasVendorXAndesBFHCvtBit: return "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)";
1139 case Feature_HasVendorXAndesVBFHCvtBit: return "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)";
1140 case Feature_HasVendorXAndesVSIntHBit: return "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)";
1141 case Feature_HasVendorXAndesVSIntLoadBit: return "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)";
1142 case Feature_HasVendorXAndesVPackFPHBit: return "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)";
1143 case Feature_HasVendorXAndesVDotBit: return "'XAndesVDot' (Andes Vector Dot Product Extension)";
1144 case Feature_HasVendorXSMTVDotBit: return "'XSMTVDot' (SpacemiT Vector Dot Product Extension)";
1145 case Feature_HasXAIFETBit: return "'XAIFET' (AI Foundry ET Extension)";
1146 case Feature_IsRV64Bit: return "RV64I Base Instruction Set";
1147 case Feature_IsRV32Bit: return "RV32I Base Instruction Set";
1148 default: return "(unknown)";
1149 }
1150}
1151
1152#endif // GET_SUBTARGET_FEATURE_NAME
1153
1154
1155#ifdef GET_MATCHER_IMPLEMENTATION
1156#undef GET_MATCHER_IMPLEMENTATION
1157
1158static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
1159 switch (Mnemonic.size()) {
1160 default: break;
1161 case 4: // 3 strings to match.
1162 switch (Mnemonic[0]) {
1163 default: break;
1164 case 'f': // 2 strings to match.
1165 switch (Mnemonic[1]) {
1166 default: break;
1167 case 'r': // 1 string to match.
1168 if (memcmp(Mnemonic.data()+2, "sr", 2) != 0)
1169 break;
1170 if (Features.test(Feature_HasStdExtFOrZfinxBit)) // "frsr"
1171 Mnemonic = "frcsr";
1172 return;
1173 case 's': // 1 string to match.
1174 if (memcmp(Mnemonic.data()+2, "sr", 2) != 0)
1175 break;
1176 if (Features.test(Feature_HasStdExtFOrZfinxBit)) // "fssr"
1177 Mnemonic = "fscsr";
1178 return;
1179 }
1180 break;
1181 case 'm': // 1 string to match.
1182 if (memcmp(Mnemonic.data()+1, "ove", 3) != 0)
1183 break;
1184 Mnemonic = "mv"; // "move"
1185 return;
1186 }
1187 break;
1188 case 5: // 1 string to match.
1189 if (memcmp(Mnemonic.data()+0, "scall", 5) != 0)
1190 break;
1191 Mnemonic = "ecall"; // "scall"
1192 return;
1193 case 6: // 3 strings to match.
1194 switch (Mnemonic[0]) {
1195 default: break;
1196 case 's': // 1 string to match.
1197 if (memcmp(Mnemonic.data()+1, "break", 5) != 0)
1198 break;
1199 Mnemonic = "ebreak"; // "sbreak"
1200 return;
1201 case 'v': // 2 strings to match.
1202 switch (Mnemonic[1]) {
1203 default: break;
1204 case 'l': // 1 string to match.
1205 if (memcmp(Mnemonic.data()+2, "e1.v", 4) != 0)
1206 break;
1207 if (Features.test(Feature_HasVInstructionsBit)) // "vle1.v"
1208 Mnemonic = "vlm.v";
1209 return;
1210 case 's': // 1 string to match.
1211 if (memcmp(Mnemonic.data()+2, "e1.v", 4) != 0)
1212 break;
1213 if (Features.test(Feature_HasVInstructionsBit)) // "vse1.v"
1214 Mnemonic = "vsm.v";
1215 return;
1216 }
1217 break;
1218 }
1219 break;
1220 case 7: // 4 strings to match.
1221 switch (Mnemonic[0]) {
1222 default: break;
1223 case 'c': // 1 string to match.
1224 if (memcmp(Mnemonic.data()+1, "v.slet", 6) != 0)
1225 break;
1226 if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit)) // "cv.slet"
1227 Mnemonic = "cv.sle";
1228 return;
1229 case 'f': // 2 strings to match.
1230 if (memcmp(Mnemonic.data()+1, "mv.", 3) != 0)
1231 break;
1232 switch (Mnemonic[4]) {
1233 default: break;
1234 case 's': // 1 string to match.
1235 if (memcmp(Mnemonic.data()+5, ".x", 2) != 0)
1236 break;
1237 if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x"
1238 Mnemonic = "fmv.w.x";
1239 return;
1240 case 'x': // 1 string to match.
1241 if (memcmp(Mnemonic.data()+5, ".s", 2) != 0)
1242 break;
1243 if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s"
1244 Mnemonic = "fmv.x.w";
1245 return;
1246 }
1247 break;
1248 case 'v': // 1 string to match.
1249 if (memcmp(Mnemonic.data()+1, "popc.m", 6) != 0)
1250 break;
1251 if (Features.test(Feature_HasVInstructionsBit)) // "vpopc.m"
1252 Mnemonic = "vcpop.m";
1253 return;
1254 }
1255 break;
1256 case 8: // 1 string to match.
1257 if (memcmp(Mnemonic.data()+0, "cv.sletu", 8) != 0)
1258 break;
1259 if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit)) // "cv.sletu"
1260 Mnemonic = "cv.sleu";
1261 return;
1262 case 10: // 1 string to match.
1263 if (memcmp(Mnemonic.data()+0, "vmornot.mm", 10) != 0)
1264 break;
1265 if (Features.test(Feature_HasVInstructionsBit)) // "vmornot.mm"
1266 Mnemonic = "vmorn.mm";
1267 return;
1268 case 11: // 2 strings to match.
1269 if (Mnemonic[0] != 'v')
1270 break;
1271 switch (Mnemonic[1]) {
1272 default: break;
1273 case 'f': // 1 string to match.
1274 if (memcmp(Mnemonic.data()+2, "redsum.vs", 9) != 0)
1275 break;
1276 if (Features.test(Feature_HasVInstructionsAnyFBit)) // "vfredsum.vs"
1277 Mnemonic = "vfredusum.vs";
1278 return;
1279 case 'm': // 1 string to match.
1280 if (memcmp(Mnemonic.data()+2, "andnot.mm", 9) != 0)
1281 break;
1282 if (Features.test(Feature_HasVInstructionsBit)) // "vmandnot.mm"
1283 Mnemonic = "vmandn.mm";
1284 return;
1285 }
1286 break;
1287 case 12: // 1 string to match.
1288 if (memcmp(Mnemonic.data()+0, "vfwredsum.vs", 12) != 0)
1289 break;
1290 if (Features.test(Feature_HasVInstructionsAnyFBit)) // "vfwredsum.vs"
1291 Mnemonic = "vfwredusum.vs";
1292 return;
1293 }
1294}
1295
1296enum {
1297 Tie0_1_1,
1298 Tie0_2_2,
1299 Tie0_3_3,
1300 Tie1_3_3,
1301};
1302
1303static const uint8_t TiedAsmOperandTable[][3] = {
1304 /* Tie0_1_1 */ { 0, 1, 1 },
1305 /* Tie0_2_2 */ { 0, 2, 2 },
1306 /* Tie0_3_3 */ { 0, 3, 3 },
1307 /* Tie1_3_3 */ { 1, 3, 3 },
1308};
1309
1310namespace {
1311enum OperatorConversionKind {
1312 CVT_Done,
1313 CVT_Reg,
1314 CVT_Tied,
1315 CVT_95_addImmOperands,
1316 CVT_95_addRegOperands,
1317 CVT_imm_95_0,
1318 CVT_95_Reg,
1319 CVT_95_addFRMArgOperands_95_defaultFRMArgOp,
1320 CVT_regX0,
1321 CVT_regX1,
1322 CVT_regX5,
1323 CVT_regX2,
1324 CVT_regX3,
1325 CVT_regX4,
1326 CVT_95_addRegListOperands,
1327 CVT_95_addStackAdjOperands,
1328 CVT_95_addCSRSystemRegisterOperands,
1329 CVT_95_addRegRegOperands,
1330 CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp,
1331 CVT_95_addFRMArgOperands,
1332 CVT_imm_95_15,
1333 CVT_95_addFenceArgOperands,
1334 CVT_95_addFPImmOperands,
1335 CVT_imm_95_3,
1336 CVT_imm_95_1,
1337 CVT_imm_95_2,
1338 CVT_95_addRegOperands_95_defaultMaskRegOp,
1339 CVT_imm_95__MINUS_1,
1340 CVT_95_addSImm8UnsignedOperands,
1341 CVT_95_addSImm10UnsignedOperands,
1342 CVT_imm_95_1536,
1343 CVT_imm_95__MINUS_1280,
1344 CVT_imm_95__MINUS_2048,
1345 CVT_imm_95_1792,
1346 CVT_imm_95__MINUS_1792,
1347 CVT_imm_95__MINUS_1536,
1348 CVT_imm_95__MINUS_1024,
1349 CVT_imm_95_3072,
1350 CVT_imm_95_3200,
1351 CVT_imm_95_3074,
1352 CVT_imm_95_3202,
1353 CVT_imm_95_3073,
1354 CVT_imm_95_3201,
1355 CVT_95_addVTypeIOperands,
1356 CVT_reg0,
1357 CVT_imm_95_255,
1358 CVT_NUM_CONVERTERS
1359};
1360
1361enum InstructionConversionKind {
1362 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4,
1363 Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4,
1364 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3,
1365 Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3,
1366 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3,
1367 Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2,
1368 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0,
1369 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3,
1370 Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3,
1371 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0,
1372 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3,
1373 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3,
1374 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4,
1375 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0,
1376 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm12LO1_3,
1377 Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2,
1378 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4,
1379 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5,
1380 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5,
1381 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_5__imm_95_0,
1382 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__SImm261_4,
1383 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4,
1384 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_5__imm_95_0,
1385 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__SImm261_4,
1386 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5,
1387 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6,
1388 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0,
1389 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm12LO1_3,
1390 Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2,
1391 Convert__Reg1_0__Reg1_1__Reg1_2,
1392 Convert__Reg1_0__Reg1_1,
1393 Convert__Reg1_0__Reg1_1__SImm12LO1_2,
1394 Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3,
1395 Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2,
1396 Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3,
1397 Convert__Reg1_0__Reg1_1__RnumArg1_2,
1398 Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2,
1399 Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3,
1400 Convert__Reg1_0__Reg1_1__SImm101_2,
1401 Convert__Reg1_0__SImm12LO1_1__Reg1_3,
1402 Convert__Reg1_0__UImm20LUI1_1,
1403 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
1404 Convert__Reg1_0__Reg1_1__FRMArg1_2,
1405 Convert__Reg1_0__Reg1_2,
1406 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4,
1407 Convert__Reg1_0__Reg1_1__UImm31_2,
1408 Convert__Reg1_0__Reg1_1__UImm51_2,
1409 Convert__Reg1_0__Reg1_1__UImm81_2,
1410 Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3,
1411 Convert__Reg1_0,
1412 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1,
1413 Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2,
1414 Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2,
1415 Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2,
1416 Convert__Reg1_0__UImm20AUIPC1_1,
1417 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2,
1418 Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2,
1419 Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2,
1420 Convert__Reg1_0__regX0__BareSImm13Lsb01_1,
1421 Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2,
1422 Convert__regX0__Reg1_0__BareSImm13Lsb01_1,
1423 Convert__Reg1_0__Tie0_1_1__Reg1_1,
1424 Convert__Reg1_0__Tie0_1_1__SImm61_1,
1425 Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1,
1426 Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2,
1427 Convert__Reg1_0__BareSImm9Lsb01_1,
1428 Convert_NoOperands,
1429 Convert__Reg1_0__Reg1_2__imm_95_0,
1430 Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1,
1431 Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1,
1432 Convert__Reg1_0__Reg1_3__UImm7Lsb001_1,
1433 Convert__Reg1_0__Reg1_3__UImm8Lsb001_1,
1434 Convert__BareSImm12Lsb01_0,
1435 Convert__Reg1_0__Reg1_3__UImm21_1,
1436 Convert__GPRPairCRV321_0__Reg1_2__imm_95_0,
1437 Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1,
1438 Convert__GPRPairNoX0RV321_0__Reg1_2__imm_95_0,
1439 Convert__GPRPairNoX0RV321_0__Reg1_3__UImm9Lsb0001_1,
1440 Convert__Reg1_0__Reg1_3__UImm2Lsb01_1,
1441 Convert__Reg1_0__SImm61_1,
1442 Convert__Reg1_0__CLUIImm1_1,
1443 Convert__regX1,
1444 Convert__regX5,
1445 Convert__SImm6NonZero1_0,
1446 Convert__Reg1_0__Tie0_1_1,
1447 Convert__regX0__Tie0_1_1__regX5,
1448 Convert__regX0__Tie0_1_1__regX2,
1449 Convert__regX0__Tie0_1_1__regX3,
1450 Convert__regX0__Tie0_1_1__regX4,
1451 Convert__GPRPairRV321_0__Reg1_2__imm_95_0,
1452 Convert__GPRPairRV321_0__Reg1_3__UImm9Lsb0001_1,
1453 Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1,
1454 Convert__Reg1_0__Tie0_1_1__imm_95_0,
1455 Convert__CallSymbol1_0,
1456 Convert__Reg1_0__CallSymbol1_1,
1457 Convert__ZeroOffsetMemOpOperand1_0,
1458 Convert__UImm8GE321_0,
1459 Convert__UImm51_0,
1460 Convert__RegList1_0__StackAdj1_1,
1461 Convert__RegList1_0__NegStackAdj1_1,
1462 Convert__regX0__CSRSystemRegister1_0__Reg1_1,
1463 Convert__regX0__CSRSystemRegister1_0__UImm51_1,
1464 Convert__Reg1_0__CSRSystemRegister1_1__regX0,
1465 Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2,
1466 Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2,
1467 Convert__Reg1_0__Reg1_1__SImm61_2,
1468 Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3,
1469 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
1470 Convert__Reg1_0__Reg1_1__UImm61_2,
1471 Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3,
1472 Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2,
1473 Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3,
1474 Convert__Reg1_0__BareSymbol1_1,
1475 Convert__Reg1_0__Reg1_3__SImm12LO1_1,
1476 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3,
1477 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2,
1478 Convert__Reg1_0__RegReg2_1,
1479 Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4,
1480 Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4,
1481 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3,
1482 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
1483 Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4,
1484 Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4,
1485 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2,
1486 Convert__Reg1_0__Reg1_1__UImm41_2,
1487 Convert__Reg1_0__Reg1_1__Reg1_1,
1488 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1,
1489 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1,
1490 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1,
1491 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1,
1492 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3,
1493 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3,
1494 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3,
1495 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3,
1496 Convert__Reg1_0__GPRF64AsFPR1_1,
1497 Convert__Reg1_0__GPRPairAsFPR1_1,
1498 Convert__Reg1_0__GPRAsFPR161_1,
1499 Convert__Reg1_0__GPRAsFPR321_1,
1500 Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2,
1501 Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1502 Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1503 Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2,
1504 Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
1505 Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
1506 Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2,
1507 Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2,
1508 Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2,
1509 Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2,
1510 Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2,
1511 Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2,
1512 Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2,
1513 Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2,
1514 Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2,
1515 Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2,
1516 Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2,
1517 Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1518 Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2,
1519 Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2,
1520 Convert__Reg1_0__Reg1_1__RTZArg1_2,
1521 Convert__imm_95_15__imm_95_15,
1522 Convert__FenceArg1_0__FenceArg1_1,
1523 Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
1524 Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
1525 Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2,
1526 Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2,
1527 Convert__Reg1_0__Reg1_2__Reg1_1,
1528 Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1,
1529 Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1,
1530 Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1,
1531 Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1,
1532 Convert__Reg1_2__Reg1_0__BareSymbol1_1,
1533 Convert__Reg1_0__LoadFPImm1_1,
1534 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4,
1535 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4,
1536 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4,
1537 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4,
1538 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
1539 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
1540 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2,
1541 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2,
1542 Convert__Reg1_0__imm_95_3__regX0,
1543 Convert__Reg1_0__imm_95_1__regX0,
1544 Convert__Reg1_0__imm_95_2__regX0,
1545 Convert__regX0__imm_95_3__Reg1_0,
1546 Convert__Reg1_0__imm_95_3__Reg1_1,
1547 Convert__regX0__imm_95_1__Reg1_0,
1548 Convert__Reg1_0__imm_95_1__Reg1_1,
1549 Convert__regX0__imm_95_1__UImm51_0,
1550 Convert__Reg1_0__imm_95_1__UImm51_1,
1551 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2,
1552 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2,
1553 Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2,
1554 Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2,
1555 Convert__regX0__imm_95_2__Reg1_0,
1556 Convert__Reg1_0__imm_95_2__Reg1_1,
1557 Convert__regX0__imm_95_2__UImm51_0,
1558 Convert__Reg1_0__imm_95_2__UImm51_1,
1559 Convert__regX0__regX0,
1560 Convert__Reg1_0__regX0,
1561 Convert__regX0__BareSImm21Lsb01_0,
1562 Convert__regX1__BareSImm21Lsb01_0,
1563 Convert__Reg1_0__BareSImm21Lsb01_1,
1564 Convert__regX1__Reg1_0__imm_95_0,
1565 Convert__Reg1_0__Reg1_1__imm_95_0,
1566 Convert__regX1__Reg1_0__SImm12LO1_1,
1567 Convert__regX1__Reg1_1__imm_95_0,
1568 Convert__regX1__Reg1_2__SImm12LO1_0,
1569 Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5,
1570 Convert__regX0__Reg1_0__imm_95_0,
1571 Convert__regX0__Reg1_0__SImm12LO1_1,
1572 Convert__regX0__Reg1_1__imm_95_0,
1573 Convert__regX0__Reg1_2__SImm12LO1_0,
1574 Convert__Reg1_1__PseudoJumpSymbol1_0,
1575 Convert__Reg1_0__ImmXLenLI_Restricted1_1,
1576 Convert__GPRPairRV321_0__BareSymbol1_1,
1577 Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1,
1578 Convert__Reg1_0__regX0__SImm12LO1_1,
1579 Convert__Reg1_0__ImmXLenLI1_1,
1580 Convert__regX0__UImm201_0,
1581 Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3,
1582 Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2,
1583 Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2,
1584 Convert__Reg1_3__UImm91_1__UImm51_0,
1585 Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2,
1586 Convert__Reg1_0__GPRPairRV321_1__Reg1_2,
1587 Convert__Reg1_0__GPRPairRV321_1__UImm61_2,
1588 Convert__Reg1_0__SImm181_1,
1589 Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2,
1590 Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2,
1591 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3,
1592 Convert__Reg1_0__SImm20Lsb0001_1,
1593 Convert__Reg1_0__SImm18Lsb01_1,
1594 Convert__Reg1_0__SImm19Lsb001_1,
1595 Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1596 Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3,
1597 Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2,
1598 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2,
1599 Convert__Reg1_0__regX0__Reg1_1,
1600 Convert__regX0__regX0__imm_95_0,
1601 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1,
1602 Convert__regX0__regX0__regX5,
1603 Convert__regX0__regX0__regX2,
1604 Convert__regX0__regX0__regX3,
1605 Convert__regX0__regX0__regX4,
1606 Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2,
1607 Convert__imm_95_1__imm_95_0,
1608 Convert__Reg1_0__SImm8Unsigned1_1,
1609 Convert__GPRPairRV321_0__SImm8Unsigned1_1,
1610 Convert__GPRPairRV321_0__SImm101_1,
1611 Convert__Reg1_0__SImm101_1,
1612 Convert__GPRPairRV321_0__SImm10Unsigned1_1,
1613 Convert__Reg1_0__SImm10Unsigned1_1,
1614 Convert__GPRPairRV321_0__Reg1_1__Reg1_2,
1615 Convert__Reg1_0__GPRPairRV321_1__UImm41_2,
1616 Convert__Reg1_0__GPRPairRV321_1__UImm51_2,
1617 Convert__Reg1_2__SImm12Lsb000001_0,
1618 Convert__GPRPairRV321_0__GPRPairRV321_1,
1619 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2,
1620 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2,
1621 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2,
1622 Convert__GPRPairRV321_0__Reg1_1__UImm41_2,
1623 Convert__GPRPairRV321_0__Reg1_1__UImm51_2,
1624 Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2,
1625 Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2,
1626 Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1,
1627 Convert__regX0__Tie0_1_1__UImm5NonZero1_0,
1628 Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1,
1629 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2,
1630 Convert__regX0__Tie0_1_1__imm_95_0,
1631 Convert__UImm5Slist1_0,
1632 Convert__UImm101_0,
1633 Convert__RegListS01_0__NegStackAdj1_1,
1634 Convert__Reg1_0__UImm51_1__Reg1_2,
1635 Convert__Reg1_0__Tie0_1_1__BareSImm321_1,
1636 Convert__Reg1_0__Reg1_1__SImm261_2,
1637 Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2,
1638 Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2,
1639 Convert__BareSImm32Lsb01_0,
1640 Convert__Reg1_0__Reg1_3__SImm261_1,
1641 Convert__Reg1_0__BareSImm321_1,
1642 Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1,
1643 Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3,
1644 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3,
1645 Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3,
1646 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2,
1647 Convert__Reg1_0__Reg1_3__UImm14Lsb001_1,
1648 Convert__Reg1_0__SImm20LI1_1,
1649 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3,
1650 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3,
1651 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3,
1652 Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3,
1653 Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0,
1654 Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2,
1655 Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0,
1656 Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2,
1657 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2,
1658 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3,
1659 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3,
1660 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3,
1661 Convert__regX0__regX0__imm_95_1536,
1662 Convert__regX0__Reg1_0__imm_95__MINUS_1280,
1663 Convert__regX0__Reg1_0__imm_95__MINUS_2048,
1664 Convert__regX0__regX0__imm_95_1792,
1665 Convert__regX0__Reg1_0__imm_95__MINUS_1792,
1666 Convert__UImm81_0,
1667 Convert__regX0__Reg1_0__imm_95__MINUS_1536,
1668 Convert__regX0__Reg1_0__imm_95__MINUS_1024,
1669 Convert__regX0__regX0__UImm101_0,
1670 Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3,
1671 Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3,
1672 Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3,
1673 Convert__Reg1_0__Reg1_1__UImm111_2,
1674 Convert__Reg1_0__Reg1_3__UImm51_1,
1675 Convert__Reg1_0__Reg1_3__UImm41_1,
1676 Convert__Reg1_0__Reg1_3__UImm6Lsb01_1,
1677 Convert__Reg1_0__Reg1_3__UImm5Lsb01_1,
1678 Convert__Reg1_0__imm_95_3072__regX0,
1679 Convert__Reg1_0__imm_95_3200__regX0,
1680 Convert__Reg1_0__imm_95_3074__regX0,
1681 Convert__Reg1_0__imm_95_3202__regX0,
1682 Convert__Reg1_0__imm_95_3073__regX0,
1683 Convert__Reg1_0__imm_95_3201__regX0,
1684 Convert__regX0__regX1__imm_95_0,
1685 Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1,
1686 Convert__Reg1_0__Reg1_1__imm_95_1,
1687 Convert__regX0,
1688 Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3,
1689 Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3,
1690 Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3,
1691 Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3,
1692 Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3,
1693 Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3,
1694 Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3,
1695 Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3,
1696 Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3,
1697 Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3,
1698 Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3,
1699 Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3,
1700 Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3,
1701 Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3,
1702 Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3,
1703 Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3,
1704 Convert__Reg1_0__Reg1_1__XSfmmVType1_2,
1705 Convert__Reg1_0__Reg1_1__regX0,
1706 Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5,
1707 Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6,
1708 Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6,
1709 Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5,
1710 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1711 Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3,
1712 Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3,
1713 Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3,
1714 Convert__Reg1_0__Reg1_1__Reg1_1__reg0,
1715 Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2,
1716 Convert__Reg1_0__RVVMaskRegOpOperand1_1,
1717 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1718 Convert__Reg1_0__Reg1_1__SImm51_2,
1719 Convert__Reg1_0__Reg1_0__Reg1_0,
1720 Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3,
1721 Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1722 Convert__Reg1_0__SImm51_1,
1723 Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3,
1724 Convert__Reg1_0__Reg1_1__regX0__reg0,
1725 Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2,
1726 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0,
1727 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2,
1728 Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3,
1729 Convert__Reg1_0__UImm51_1__VTypeI101_2,
1730 Convert__Reg1_0__Reg1_1__VTypeI111_2,
1731 Convert__GPRPairRV321_0__Reg1_1__UImm61_2,
1732 Convert__Reg1_0__Reg1_1__imm_95_255,
1733 CVT_NUM_SIGNATURES
1734};
1735
1736} // end anonymous namespace
1737
1738static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][15] = {
1739 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4
1740 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1741 // Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4
1742 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_Done },
1743 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3
1744 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1745 // Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3
1746 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
1747 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3
1748 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
1749 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2
1750 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1751 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0
1752 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1753 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3
1754 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1755 // Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3
1756 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_Done },
1757 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0
1758 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1759 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3
1760 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1761 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3
1762 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1763 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4
1764 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1765 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0
1766 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1767 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm12LO1_3
1768 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1769 // Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2
1770 { CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
1771 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4
1772 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
1773 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5
1774 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1775 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5
1776 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1777 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_5__imm_95_0
1778 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
1779 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__SImm261_4
1780 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 7, CVT_95_addImmOperands, 5, CVT_Done },
1781 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4
1782 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1783 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_5__imm_95_0
1784 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
1785 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__SImm261_4
1786 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addRegOperands, 7, CVT_95_addImmOperands, 5, CVT_Done },
1787 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5
1788 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
1789 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6
1790 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_95_addRegOperands, 7, CVT_Done },
1791 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0
1792 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1793 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm12LO1_3
1794 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1795 // Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2
1796 { CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
1797 // Convert__Reg1_0__Reg1_1__Reg1_2
1798 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1799 // Convert__Reg1_0__Reg1_1
1800 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1801 // Convert__Reg1_0__Reg1_1__SImm12LO1_2
1802 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1803 // Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3
1804 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1805 // Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2
1806 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1807 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3
1808 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1809 // Convert__Reg1_0__Reg1_1__RnumArg1_2
1810 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1811 // Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2
1812 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands, 3, CVT_Done },
1813 // Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3
1814 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
1815 // Convert__Reg1_0__Reg1_1__SImm101_2
1816 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1817 // Convert__Reg1_0__SImm12LO1_1__Reg1_3
1818 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_Done },
1819 // Convert__Reg1_0__UImm20LUI1_1
1820 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1821 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
1822 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
1823 // Convert__Reg1_0__Reg1_1__FRMArg1_2
1824 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
1825 // Convert__Reg1_0__Reg1_2
1826 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
1827 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4
1828 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
1829 // Convert__Reg1_0__Reg1_1__UImm31_2
1830 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1831 // Convert__Reg1_0__Reg1_1__UImm51_2
1832 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1833 // Convert__Reg1_0__Reg1_1__UImm81_2
1834 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1835 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3
1836 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1837 // Convert__Reg1_0
1838 { CVT_95_Reg, 1, CVT_Done },
1839 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1
1840 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
1841 // Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2
1842 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addRegOperands, 3, CVT_Done },
1843 // Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2
1844 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1845 // Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2
1846 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1847 // Convert__Reg1_0__UImm20AUIPC1_1
1848 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1849 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2
1850 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1851 // Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2
1852 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1853 // Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2
1854 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1855 // Convert__Reg1_0__regX0__BareSImm13Lsb01_1
1856 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
1857 // Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2
1858 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },
1859 // Convert__regX0__Reg1_0__BareSImm13Lsb01_1
1860 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1861 // Convert__Reg1_0__Tie0_1_1__Reg1_1
1862 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
1863 // Convert__Reg1_0__Tie0_1_1__SImm61_1
1864 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1865 // Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1
1866 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1867 // Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2
1868 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1869 // Convert__Reg1_0__BareSImm9Lsb01_1
1870 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1871 // Convert_NoOperands
1872 { CVT_Done },
1873 // Convert__Reg1_0__Reg1_2__imm_95_0
1874 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1875 // Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1
1876 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1877 // Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1
1878 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1879 // Convert__Reg1_0__Reg1_3__UImm7Lsb001_1
1880 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1881 // Convert__Reg1_0__Reg1_3__UImm8Lsb001_1
1882 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1883 // Convert__BareSImm12Lsb01_0
1884 { CVT_95_addImmOperands, 1, CVT_Done },
1885 // Convert__Reg1_0__Reg1_3__UImm21_1
1886 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1887 // Convert__GPRPairCRV321_0__Reg1_2__imm_95_0
1888 { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1889 // Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1
1890 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1891 // Convert__GPRPairNoX0RV321_0__Reg1_2__imm_95_0
1892 { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1893 // Convert__GPRPairNoX0RV321_0__Reg1_3__UImm9Lsb0001_1
1894 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1895 // Convert__Reg1_0__Reg1_3__UImm2Lsb01_1
1896 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1897 // Convert__Reg1_0__SImm61_1
1898 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1899 // Convert__Reg1_0__CLUIImm1_1
1900 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1901 // Convert__regX1
1902 { CVT_regX1, 0, CVT_Done },
1903 // Convert__regX5
1904 { CVT_regX5, 0, CVT_Done },
1905 // Convert__SImm6NonZero1_0
1906 { CVT_95_addImmOperands, 1, CVT_Done },
1907 // Convert__Reg1_0__Tie0_1_1
1908 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1909 // Convert__regX0__Tie0_1_1__regX5
1910 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX5, 0, CVT_Done },
1911 // Convert__regX0__Tie0_1_1__regX2
1912 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX2, 0, CVT_Done },
1913 // Convert__regX0__Tie0_1_1__regX3
1914 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX3, 0, CVT_Done },
1915 // Convert__regX0__Tie0_1_1__regX4
1916 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX4, 0, CVT_Done },
1917 // Convert__GPRPairRV321_0__Reg1_2__imm_95_0
1918 { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1919 // Convert__GPRPairRV321_0__Reg1_3__UImm9Lsb0001_1
1920 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1921 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1
1922 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1923 // Convert__Reg1_0__Tie0_1_1__imm_95_0
1924 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
1925 // Convert__CallSymbol1_0
1926 { CVT_95_addImmOperands, 1, CVT_Done },
1927 // Convert__Reg1_0__CallSymbol1_1
1928 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1929 // Convert__ZeroOffsetMemOpOperand1_0
1930 { CVT_95_addRegOperands, 1, CVT_Done },
1931 // Convert__UImm8GE321_0
1932 { CVT_95_addImmOperands, 1, CVT_Done },
1933 // Convert__UImm51_0
1934 { CVT_95_addImmOperands, 1, CVT_Done },
1935 // Convert__RegList1_0__StackAdj1_1
1936 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
1937 // Convert__RegList1_0__NegStackAdj1_1
1938 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
1939 // Convert__regX0__CSRSystemRegister1_0__Reg1_1
1940 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
1941 // Convert__regX0__CSRSystemRegister1_0__UImm51_1
1942 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1943 // Convert__Reg1_0__CSRSystemRegister1_1__regX0
1944 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_regX0, 0, CVT_Done },
1945 // Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2
1946 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_Reg, 3, CVT_Done },
1947 // Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2
1948 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1949 // Convert__Reg1_0__Reg1_1__SImm61_2
1950 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1951 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3
1952 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1953 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
1954 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1955 // Convert__Reg1_0__Reg1_1__UImm61_2
1956 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1957 // Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3
1958 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1959 // Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2
1960 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1961 // Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3
1962 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1963 // Convert__Reg1_0__BareSymbol1_1
1964 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1965 // Convert__Reg1_0__Reg1_3__SImm12LO1_1
1966 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1967 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3
1968 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1969 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2
1970 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1971 // Convert__Reg1_0__RegReg2_1
1972 { CVT_95_Reg, 1, CVT_95_addRegRegOperands, 2, CVT_Done },
1973 // Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4
1974 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_Reg, 5, CVT_Done },
1975 // Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4
1976 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_Done },
1977 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3
1978 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1979 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
1980 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1981 // Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4
1982 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
1983 // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4
1984 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
1985 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2
1986 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1987 // Convert__Reg1_0__Reg1_1__UImm41_2
1988 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1989 // Convert__Reg1_0__Reg1_1__Reg1_1
1990 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_Done },
1991 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1
1992 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
1993 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1
1994 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
1995 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1
1996 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
1997 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1
1998 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
1999 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3
2000 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2001 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3
2002 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2003 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3
2004 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2005 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3
2006 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2007 // Convert__Reg1_0__GPRF64AsFPR1_1
2008 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2009 // Convert__Reg1_0__GPRPairAsFPR1_1
2010 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2011 // Convert__Reg1_0__GPRAsFPR161_1
2012 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2013 // Convert__Reg1_0__GPRAsFPR321_1
2014 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2015 // Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2
2016 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2017 // Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2
2018 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2019 // Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2
2020 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2021 // Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2
2022 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2023 // Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2
2024 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2025 // Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2
2026 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2027 // Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2
2028 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2029 // Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2
2030 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2031 // Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2
2032 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2033 // Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2
2034 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2035 // Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2
2036 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2037 // Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2
2038 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2039 // Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2
2040 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2041 // Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2
2042 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2043 // Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2
2044 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2045 // Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2
2046 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2047 // Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2
2048 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2049 // Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2
2050 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2051 // Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2
2052 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2053 // Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2
2054 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2055 // Convert__Reg1_0__Reg1_1__RTZArg1_2
2056 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
2057 // Convert__imm_95_15__imm_95_15
2058 { CVT_imm_95_15, 0, CVT_imm_95_15, 0, CVT_Done },
2059 // Convert__FenceArg1_0__FenceArg1_1
2060 { CVT_95_addFenceArgOperands, 1, CVT_95_addFenceArgOperands, 2, CVT_Done },
2061 // Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
2062 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2063 // Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2
2064 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2065 // Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2
2066 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2067 // Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2
2068 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2069 // Convert__Reg1_0__Reg1_2__Reg1_1
2070 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
2071 // Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1
2072 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2073 // Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1
2074 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2075 // Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1
2076 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2077 // Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1
2078 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2079 // Convert__Reg1_2__Reg1_0__BareSymbol1_1
2080 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2081 // Convert__Reg1_0__LoadFPImm1_1
2082 { CVT_95_Reg, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
2083 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4
2084 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2085 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4
2086 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2087 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4
2088 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2089 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4
2090 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2091 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
2092 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2093 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2
2094 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2095 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2
2096 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2097 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2
2098 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2099 // Convert__Reg1_0__imm_95_3__regX0
2100 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_regX0, 0, CVT_Done },
2101 // Convert__Reg1_0__imm_95_1__regX0
2102 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_regX0, 0, CVT_Done },
2103 // Convert__Reg1_0__imm_95_2__regX0
2104 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_regX0, 0, CVT_Done },
2105 // Convert__regX0__imm_95_3__Reg1_0
2106 { CVT_regX0, 0, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
2107 // Convert__Reg1_0__imm_95_3__Reg1_1
2108 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
2109 // Convert__regX0__imm_95_1__Reg1_0
2110 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
2111 // Convert__Reg1_0__imm_95_1__Reg1_1
2112 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
2113 // Convert__regX0__imm_95_1__UImm51_0
2114 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_addImmOperands, 1, CVT_Done },
2115 // Convert__Reg1_0__imm_95_1__UImm51_1
2116 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_addImmOperands, 2, CVT_Done },
2117 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2
2118 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2119 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2
2120 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2121 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2
2122 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2123 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2
2124 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2125 // Convert__regX0__imm_95_2__Reg1_0
2126 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
2127 // Convert__Reg1_0__imm_95_2__Reg1_1
2128 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
2129 // Convert__regX0__imm_95_2__UImm51_0
2130 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_addImmOperands, 1, CVT_Done },
2131 // Convert__Reg1_0__imm_95_2__UImm51_1
2132 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_addImmOperands, 2, CVT_Done },
2133 // Convert__regX0__regX0
2134 { CVT_regX0, 0, CVT_regX0, 0, CVT_Done },
2135 // Convert__Reg1_0__regX0
2136 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_Done },
2137 // Convert__regX0__BareSImm21Lsb01_0
2138 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2139 // Convert__regX1__BareSImm21Lsb01_0
2140 { CVT_regX1, 0, CVT_95_addImmOperands, 1, CVT_Done },
2141 // Convert__Reg1_0__BareSImm21Lsb01_1
2142 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2143 // Convert__regX1__Reg1_0__imm_95_0
2144 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2145 // Convert__Reg1_0__Reg1_1__imm_95_0
2146 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2147 // Convert__regX1__Reg1_0__SImm12LO1_1
2148 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2149 // Convert__regX1__Reg1_1__imm_95_0
2150 { CVT_regX1, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2151 // Convert__regX1__Reg1_2__SImm12LO1_0
2152 { CVT_regX1, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2153 // Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5
2154 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
2155 // Convert__regX0__Reg1_0__imm_95_0
2156 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2157 // Convert__regX0__Reg1_0__SImm12LO1_1
2158 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2159 // Convert__regX0__Reg1_1__imm_95_0
2160 { CVT_regX0, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2161 // Convert__regX0__Reg1_2__SImm12LO1_0
2162 { CVT_regX0, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2163 // Convert__Reg1_1__PseudoJumpSymbol1_0
2164 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
2165 // Convert__Reg1_0__ImmXLenLI_Restricted1_1
2166 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2167 // Convert__GPRPairRV321_0__BareSymbol1_1
2168 { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2169 // Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1
2170 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2171 // Convert__Reg1_0__regX0__SImm12LO1_1
2172 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
2173 // Convert__Reg1_0__ImmXLenLI1_1
2174 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2175 // Convert__regX0__UImm201_0
2176 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2177 // Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3
2178 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Done },
2179 // Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2
2180 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_95_addImmOperands, 3, CVT_Done },
2181 // Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2
2182 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_95_addImmOperands, 3, CVT_Done },
2183 // Convert__Reg1_3__UImm91_1__UImm51_0
2184 { CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2185 // Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2
2186 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2187 // Convert__Reg1_0__GPRPairRV321_1__Reg1_2
2188 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_Done },
2189 // Convert__Reg1_0__GPRPairRV321_1__UImm61_2
2190 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2191 // Convert__Reg1_0__SImm181_1
2192 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2193 // Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2
2194 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2195 // Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2
2196 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2197 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3
2198 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2199 // Convert__Reg1_0__SImm20Lsb0001_1
2200 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2201 // Convert__Reg1_0__SImm18Lsb01_1
2202 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2203 // Convert__Reg1_0__SImm19Lsb001_1
2204 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2205 // Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2206 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2207 // Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3
2208 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2209 // Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2
2210 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2211 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2
2212 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2213 // Convert__Reg1_0__regX0__Reg1_1
2214 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
2215 // Convert__regX0__regX0__imm_95_0
2216 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done },
2217 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1
2218 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_Done },
2219 // Convert__regX0__regX0__regX5
2220 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX5, 0, CVT_Done },
2221 // Convert__regX0__regX0__regX2
2222 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX2, 0, CVT_Done },
2223 // Convert__regX0__regX0__regX3
2224 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX3, 0, CVT_Done },
2225 // Convert__regX0__regX0__regX4
2226 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX4, 0, CVT_Done },
2227 // Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2
2228 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_Done },
2229 // Convert__imm_95_1__imm_95_0
2230 { CVT_imm_95_1, 0, CVT_imm_95_0, 0, CVT_Done },
2231 // Convert__Reg1_0__SImm8Unsigned1_1
2232 { CVT_95_Reg, 1, CVT_95_addSImm8UnsignedOperands, 2, CVT_Done },
2233 // Convert__GPRPairRV321_0__SImm8Unsigned1_1
2234 { CVT_95_addRegOperands, 1, CVT_95_addSImm8UnsignedOperands, 2, CVT_Done },
2235 // Convert__GPRPairRV321_0__SImm101_1
2236 { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2237 // Convert__Reg1_0__SImm101_1
2238 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2239 // Convert__GPRPairRV321_0__SImm10Unsigned1_1
2240 { CVT_95_addRegOperands, 1, CVT_95_addSImm10UnsignedOperands, 2, CVT_Done },
2241 // Convert__Reg1_0__SImm10Unsigned1_1
2242 { CVT_95_Reg, 1, CVT_95_addSImm10UnsignedOperands, 2, CVT_Done },
2243 // Convert__GPRPairRV321_0__Reg1_1__Reg1_2
2244 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2245 // Convert__Reg1_0__GPRPairRV321_1__UImm41_2
2246 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2247 // Convert__Reg1_0__GPRPairRV321_1__UImm51_2
2248 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2249 // Convert__Reg1_2__SImm12Lsb000001_0
2250 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2251 // Convert__GPRPairRV321_0__GPRPairRV321_1
2252 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
2253 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2
2254 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2255 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2
2256 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2257 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2
2258 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2259 // Convert__GPRPairRV321_0__Reg1_1__UImm41_2
2260 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2261 // Convert__GPRPairRV321_0__Reg1_1__UImm51_2
2262 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2263 // Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2
2264 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2265 // Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2
2266 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2267 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1
2268 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2269 // Convert__regX0__Tie0_1_1__UImm5NonZero1_0
2270 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2271 // Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1
2272 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2273 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2
2274 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2275 // Convert__regX0__Tie0_1_1__imm_95_0
2276 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
2277 // Convert__UImm5Slist1_0
2278 { CVT_95_addImmOperands, 1, CVT_Done },
2279 // Convert__UImm101_0
2280 { CVT_95_addImmOperands, 1, CVT_Done },
2281 // Convert__RegListS01_0__NegStackAdj1_1
2282 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
2283 // Convert__Reg1_0__UImm51_1__Reg1_2
2284 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
2285 // Convert__Reg1_0__Tie0_1_1__BareSImm321_1
2286 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2287 // Convert__Reg1_0__Reg1_1__SImm261_2
2288 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2289 // Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2
2290 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2291 // Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2
2292 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2293 // Convert__BareSImm32Lsb01_0
2294 { CVT_95_addImmOperands, 1, CVT_Done },
2295 // Convert__Reg1_0__Reg1_3__SImm261_1
2296 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2297 // Convert__Reg1_0__BareSImm321_1
2298 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2299 // Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1
2300 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
2301 // Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3
2302 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2303 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3
2304 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2305 // Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3
2306 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2307 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2
2308 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2309 // Convert__Reg1_0__Reg1_3__UImm14Lsb001_1
2310 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2311 // Convert__Reg1_0__SImm20LI1_1
2312 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2313 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3
2314 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2315 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3
2316 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2317 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3
2318 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2319 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3
2320 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2321 // Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0
2322 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2323 // Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2
2324 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2325 // Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0
2326 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2327 // Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2
2328 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2329 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2
2330 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2331 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3
2332 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2333 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3
2334 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2335 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3
2336 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2337 // Convert__regX0__regX0__imm_95_1536
2338 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_1536, 0, CVT_Done },
2339 // Convert__regX0__Reg1_0__imm_95__MINUS_1280
2340 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1280, 0, CVT_Done },
2341 // Convert__regX0__Reg1_0__imm_95__MINUS_2048
2342 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_2048, 0, CVT_Done },
2343 // Convert__regX0__regX0__imm_95_1792
2344 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_1792, 0, CVT_Done },
2345 // Convert__regX0__Reg1_0__imm_95__MINUS_1792
2346 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1792, 0, CVT_Done },
2347 // Convert__UImm81_0
2348 { CVT_95_addImmOperands, 1, CVT_Done },
2349 // Convert__regX0__Reg1_0__imm_95__MINUS_1536
2350 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1536, 0, CVT_Done },
2351 // Convert__regX0__Reg1_0__imm_95__MINUS_1024
2352 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1024, 0, CVT_Done },
2353 // Convert__regX0__regX0__UImm101_0
2354 { CVT_regX0, 0, CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2355 // Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3
2356 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2357 // Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3
2358 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2359 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3
2360 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2361 // Convert__Reg1_0__Reg1_1__UImm111_2
2362 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2363 // Convert__Reg1_0__Reg1_3__UImm51_1
2364 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2365 // Convert__Reg1_0__Reg1_3__UImm41_1
2366 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2367 // Convert__Reg1_0__Reg1_3__UImm6Lsb01_1
2368 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2369 // Convert__Reg1_0__Reg1_3__UImm5Lsb01_1
2370 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2371 // Convert__Reg1_0__imm_95_3072__regX0
2372 { CVT_95_Reg, 1, CVT_imm_95_3072, 0, CVT_regX0, 0, CVT_Done },
2373 // Convert__Reg1_0__imm_95_3200__regX0
2374 { CVT_95_Reg, 1, CVT_imm_95_3200, 0, CVT_regX0, 0, CVT_Done },
2375 // Convert__Reg1_0__imm_95_3074__regX0
2376 { CVT_95_Reg, 1, CVT_imm_95_3074, 0, CVT_regX0, 0, CVT_Done },
2377 // Convert__Reg1_0__imm_95_3202__regX0
2378 { CVT_95_Reg, 1, CVT_imm_95_3202, 0, CVT_regX0, 0, CVT_Done },
2379 // Convert__Reg1_0__imm_95_3073__regX0
2380 { CVT_95_Reg, 1, CVT_imm_95_3073, 0, CVT_regX0, 0, CVT_Done },
2381 // Convert__Reg1_0__imm_95_3201__regX0
2382 { CVT_95_Reg, 1, CVT_imm_95_3201, 0, CVT_regX0, 0, CVT_Done },
2383 // Convert__regX0__regX1__imm_95_0
2384 { CVT_regX0, 0, CVT_regX1, 0, CVT_imm_95_0, 0, CVT_Done },
2385 // Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1
2386 { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2387 // Convert__Reg1_0__Reg1_1__imm_95_1
2388 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
2389 // Convert__regX0
2390 { CVT_regX0, 0, CVT_Done },
2391 // Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3
2392 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2393 // Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3
2394 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2395 // Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3
2396 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2397 // Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3
2398 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2399 // Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3
2400 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2401 // Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3
2402 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2403 // Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3
2404 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2405 // Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3
2406 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
2407 // Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3
2408 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2409 // Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3
2410 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2411 // Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3
2412 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2413 // Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3
2414 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2415 // Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3
2416 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_Done },
2417 // Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3
2418 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2419 // Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3
2420 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2421 // Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3
2422 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2423 // Convert__Reg1_0__Reg1_1__XSfmmVType1_2
2424 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2425 // Convert__Reg1_0__Reg1_1__regX0
2426 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
2427 // Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5
2428 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2429 // Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6
2430 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
2431 // Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6
2432 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
2433 // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5
2434 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2435 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2436 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2437 // Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3
2438 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
2439 // Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3
2440 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 4, CVT_Done },
2441 // Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3
2442 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2443 // Convert__Reg1_0__Reg1_1__Reg1_1__reg0
2444 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_reg0, 0, CVT_Done },
2445 // Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2
2446 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2447 // Convert__Reg1_0__RVVMaskRegOpOperand1_1
2448 { CVT_95_Reg, 1, CVT_95_addRegOperands_95_defaultMaskRegOp, 2, CVT_Done },
2449 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3
2450 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2451 // Convert__Reg1_0__Reg1_1__SImm51_2
2452 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2453 // Convert__Reg1_0__Reg1_0__Reg1_0
2454 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_Done },
2455 // Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3
2456 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2457 // Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2458 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2459 // Convert__Reg1_0__SImm51_1
2460 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2461 // Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3
2462 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2463 // Convert__Reg1_0__Reg1_1__regX0__reg0
2464 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_reg0, 0, CVT_Done },
2465 // Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2
2466 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2467 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0
2468 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_reg0, 0, CVT_Done },
2469 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2
2470 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2471 // Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3
2472 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2473 // Convert__Reg1_0__UImm51_1__VTypeI101_2
2474 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2475 // Convert__Reg1_0__Reg1_1__VTypeI111_2
2476 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2477 // Convert__GPRPairRV321_0__Reg1_1__UImm61_2
2478 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2479 // Convert__Reg1_0__Reg1_1__imm_95_255
2480 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_255, 0, CVT_Done },
2481};
2482
2483void RISCVAsmParser::
2484convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2485 const OperandVector &Operands,
2486 const SmallBitVector &OptionalOperandsMask,
2487 ArrayRef<unsigned> DefaultsOffset) {
2488 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2489 const uint8_t *Converter = ConversionTable[Kind];
2490 Inst.setOpcode(Opcode);
2491 for (const uint8_t *p = Converter; *p; p += 2) {
2492 unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
2493 switch (*p) {
2494 default: llvm_unreachable("invalid conversion entry!");
2495 case CVT_Reg:
2496 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2497 break;
2498 case CVT_Tied: {
2499 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
2500 std::begin(TiedAsmOperandTable)) &&
2501 "Tied operand not found");
2502 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
2503 if (TiedResOpnd != (uint8_t)-1)
2504 Inst.addOperand(Inst.getOperand(TiedResOpnd));
2505 break;
2506 }
2507 case CVT_95_addImmOperands:
2508 static_cast<RISCVOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2509 break;
2510 case CVT_95_addRegOperands:
2511 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2512 break;
2513 case CVT_imm_95_0:
2514 Inst.addOperand(MCOperand::createImm(0));
2515 break;
2516 case CVT_95_Reg:
2517 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2518 break;
2519 case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
2520 if (OptionalOperandsMask[*(p + 1)]) {
2521 defaultFRMArgOp()->addFRMArgOperands(Inst, 1);
2522 } else {
2523 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2524 }
2525 break;
2526 case CVT_regX0:
2527 Inst.addOperand(MCOperand::createReg(RISCV::X0));
2528 break;
2529 case CVT_regX1:
2530 Inst.addOperand(MCOperand::createReg(RISCV::X1));
2531 break;
2532 case CVT_regX5:
2533 Inst.addOperand(MCOperand::createReg(RISCV::X5));
2534 break;
2535 case CVT_regX2:
2536 Inst.addOperand(MCOperand::createReg(RISCV::X2));
2537 break;
2538 case CVT_regX3:
2539 Inst.addOperand(MCOperand::createReg(RISCV::X3));
2540 break;
2541 case CVT_regX4:
2542 Inst.addOperand(MCOperand::createReg(RISCV::X4));
2543 break;
2544 case CVT_95_addRegListOperands:
2545 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
2546 break;
2547 case CVT_95_addStackAdjOperands:
2548 static_cast<RISCVOperand &>(*Operands[OpIdx]).addStackAdjOperands(Inst, 1);
2549 break;
2550 case CVT_95_addCSRSystemRegisterOperands:
2551 static_cast<RISCVOperand &>(*Operands[OpIdx]).addCSRSystemRegisterOperands(Inst, 1);
2552 break;
2553 case CVT_95_addRegRegOperands:
2554 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegRegOperands(Inst, 2);
2555 break;
2556 case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
2557 if (OptionalOperandsMask[*(p + 1)]) {
2558 defaultFRMArgLegacyOp()->addFRMArgOperands(Inst, 1);
2559 } else {
2560 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2561 }
2562 break;
2563 case CVT_95_addFRMArgOperands:
2564 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2565 break;
2566 case CVT_imm_95_15:
2567 Inst.addOperand(MCOperand::createImm(15));
2568 break;
2569 case CVT_95_addFenceArgOperands:
2570 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFenceArgOperands(Inst, 1);
2571 break;
2572 case CVT_95_addFPImmOperands:
2573 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
2574 break;
2575 case CVT_imm_95_3:
2576 Inst.addOperand(MCOperand::createImm(3));
2577 break;
2578 case CVT_imm_95_1:
2579 Inst.addOperand(MCOperand::createImm(1));
2580 break;
2581 case CVT_imm_95_2:
2582 Inst.addOperand(MCOperand::createImm(2));
2583 break;
2584 case CVT_95_addRegOperands_95_defaultMaskRegOp:
2585 if (OptionalOperandsMask[*(p + 1)]) {
2586 defaultMaskRegOp()->addRegOperands(Inst, 1);
2587 } else {
2588 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2589 }
2590 break;
2591 case CVT_imm_95__MINUS_1:
2592 Inst.addOperand(MCOperand::createImm(-1));
2593 break;
2594 case CVT_95_addSImm8UnsignedOperands:
2595 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSImm8UnsignedOperands(Inst, 1);
2596 break;
2597 case CVT_95_addSImm10UnsignedOperands:
2598 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSImm10UnsignedOperands(Inst, 1);
2599 break;
2600 case CVT_imm_95_1536:
2601 Inst.addOperand(MCOperand::createImm(1536));
2602 break;
2603 case CVT_imm_95__MINUS_1280:
2604 Inst.addOperand(MCOperand::createImm(-1280));
2605 break;
2606 case CVT_imm_95__MINUS_2048:
2607 Inst.addOperand(MCOperand::createImm(-2048));
2608 break;
2609 case CVT_imm_95_1792:
2610 Inst.addOperand(MCOperand::createImm(1792));
2611 break;
2612 case CVT_imm_95__MINUS_1792:
2613 Inst.addOperand(MCOperand::createImm(-1792));
2614 break;
2615 case CVT_imm_95__MINUS_1536:
2616 Inst.addOperand(MCOperand::createImm(-1536));
2617 break;
2618 case CVT_imm_95__MINUS_1024:
2619 Inst.addOperand(MCOperand::createImm(-1024));
2620 break;
2621 case CVT_imm_95_3072:
2622 Inst.addOperand(MCOperand::createImm(3072));
2623 break;
2624 case CVT_imm_95_3200:
2625 Inst.addOperand(MCOperand::createImm(3200));
2626 break;
2627 case CVT_imm_95_3074:
2628 Inst.addOperand(MCOperand::createImm(3074));
2629 break;
2630 case CVT_imm_95_3202:
2631 Inst.addOperand(MCOperand::createImm(3202));
2632 break;
2633 case CVT_imm_95_3073:
2634 Inst.addOperand(MCOperand::createImm(3073));
2635 break;
2636 case CVT_imm_95_3201:
2637 Inst.addOperand(MCOperand::createImm(3201));
2638 break;
2639 case CVT_95_addVTypeIOperands:
2640 static_cast<RISCVOperand &>(*Operands[OpIdx]).addVTypeIOperands(Inst, 1);
2641 break;
2642 case CVT_reg0:
2643 Inst.addOperand(MCOperand::createReg(0));
2644 break;
2645 case CVT_imm_95_255:
2646 Inst.addOperand(MCOperand::createImm(255));
2647 break;
2648 }
2649 }
2650}
2651
2652void RISCVAsmParser::
2653convertToMapAndConstraints(unsigned Kind,
2654 const OperandVector &Operands) {
2655 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2656 unsigned NumMCOperands = 0;
2657 const uint8_t *Converter = ConversionTable[Kind];
2658 for (const uint8_t *p = Converter; *p; p += 2) {
2659 switch (*p) {
2660 default: llvm_unreachable("invalid conversion entry!");
2661 case CVT_Reg:
2662 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2663 Operands[*(p + 1)]->setConstraint("r");
2664 ++NumMCOperands;
2665 break;
2666 case CVT_Tied:
2667 ++NumMCOperands;
2668 break;
2669 case CVT_95_addImmOperands:
2670 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2671 Operands[*(p + 1)]->setConstraint("m");
2672 NumMCOperands += 1;
2673 break;
2674 case CVT_95_addRegOperands:
2675 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2676 Operands[*(p + 1)]->setConstraint("m");
2677 NumMCOperands += 1;
2678 break;
2679 case CVT_imm_95_0:
2680 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2681 Operands[*(p + 1)]->setConstraint("");
2682 ++NumMCOperands;
2683 break;
2684 case CVT_95_Reg:
2685 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2686 Operands[*(p + 1)]->setConstraint("r");
2687 NumMCOperands += 1;
2688 break;
2689 case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
2690 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2691 Operands[*(p + 1)]->setConstraint("m");
2692 NumMCOperands += 1;
2693 break;
2694 case CVT_regX0:
2695 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2696 Operands[*(p + 1)]->setConstraint("m");
2697 ++NumMCOperands;
2698 break;
2699 case CVT_regX1:
2700 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2701 Operands[*(p + 1)]->setConstraint("m");
2702 ++NumMCOperands;
2703 break;
2704 case CVT_regX5:
2705 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2706 Operands[*(p + 1)]->setConstraint("m");
2707 ++NumMCOperands;
2708 break;
2709 case CVT_regX2:
2710 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2711 Operands[*(p + 1)]->setConstraint("m");
2712 ++NumMCOperands;
2713 break;
2714 case CVT_regX3:
2715 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2716 Operands[*(p + 1)]->setConstraint("m");
2717 ++NumMCOperands;
2718 break;
2719 case CVT_regX4:
2720 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2721 Operands[*(p + 1)]->setConstraint("m");
2722 ++NumMCOperands;
2723 break;
2724 case CVT_95_addRegListOperands:
2725 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2726 Operands[*(p + 1)]->setConstraint("m");
2727 NumMCOperands += 1;
2728 break;
2729 case CVT_95_addStackAdjOperands:
2730 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2731 Operands[*(p + 1)]->setConstraint("m");
2732 NumMCOperands += 1;
2733 break;
2734 case CVT_95_addCSRSystemRegisterOperands:
2735 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2736 Operands[*(p + 1)]->setConstraint("m");
2737 NumMCOperands += 1;
2738 break;
2739 case CVT_95_addRegRegOperands:
2740 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2741 Operands[*(p + 1)]->setConstraint("m");
2742 NumMCOperands += 2;
2743 break;
2744 case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
2745 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2746 Operands[*(p + 1)]->setConstraint("m");
2747 NumMCOperands += 1;
2748 break;
2749 case CVT_95_addFRMArgOperands:
2750 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2751 Operands[*(p + 1)]->setConstraint("m");
2752 NumMCOperands += 1;
2753 break;
2754 case CVT_imm_95_15:
2755 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2756 Operands[*(p + 1)]->setConstraint("");
2757 ++NumMCOperands;
2758 break;
2759 case CVT_95_addFenceArgOperands:
2760 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2761 Operands[*(p + 1)]->setConstraint("m");
2762 NumMCOperands += 1;
2763 break;
2764 case CVT_95_addFPImmOperands:
2765 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2766 Operands[*(p + 1)]->setConstraint("m");
2767 NumMCOperands += 1;
2768 break;
2769 case CVT_imm_95_3:
2770 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2771 Operands[*(p + 1)]->setConstraint("");
2772 ++NumMCOperands;
2773 break;
2774 case CVT_imm_95_1:
2775 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2776 Operands[*(p + 1)]->setConstraint("");
2777 ++NumMCOperands;
2778 break;
2779 case CVT_imm_95_2:
2780 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2781 Operands[*(p + 1)]->setConstraint("");
2782 ++NumMCOperands;
2783 break;
2784 case CVT_95_addRegOperands_95_defaultMaskRegOp:
2785 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2786 Operands[*(p + 1)]->setConstraint("m");
2787 NumMCOperands += 1;
2788 break;
2789 case CVT_imm_95__MINUS_1:
2790 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2791 Operands[*(p + 1)]->setConstraint("");
2792 ++NumMCOperands;
2793 break;
2794 case CVT_95_addSImm8UnsignedOperands:
2795 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2796 Operands[*(p + 1)]->setConstraint("m");
2797 NumMCOperands += 1;
2798 break;
2799 case CVT_95_addSImm10UnsignedOperands:
2800 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2801 Operands[*(p + 1)]->setConstraint("m");
2802 NumMCOperands += 1;
2803 break;
2804 case CVT_imm_95_1536:
2805 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2806 Operands[*(p + 1)]->setConstraint("");
2807 ++NumMCOperands;
2808 break;
2809 case CVT_imm_95__MINUS_1280:
2810 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2811 Operands[*(p + 1)]->setConstraint("");
2812 ++NumMCOperands;
2813 break;
2814 case CVT_imm_95__MINUS_2048:
2815 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2816 Operands[*(p + 1)]->setConstraint("");
2817 ++NumMCOperands;
2818 break;
2819 case CVT_imm_95_1792:
2820 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2821 Operands[*(p + 1)]->setConstraint("");
2822 ++NumMCOperands;
2823 break;
2824 case CVT_imm_95__MINUS_1792:
2825 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2826 Operands[*(p + 1)]->setConstraint("");
2827 ++NumMCOperands;
2828 break;
2829 case CVT_imm_95__MINUS_1536:
2830 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2831 Operands[*(p + 1)]->setConstraint("");
2832 ++NumMCOperands;
2833 break;
2834 case CVT_imm_95__MINUS_1024:
2835 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2836 Operands[*(p + 1)]->setConstraint("");
2837 ++NumMCOperands;
2838 break;
2839 case CVT_imm_95_3072:
2840 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2841 Operands[*(p + 1)]->setConstraint("");
2842 ++NumMCOperands;
2843 break;
2844 case CVT_imm_95_3200:
2845 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2846 Operands[*(p + 1)]->setConstraint("");
2847 ++NumMCOperands;
2848 break;
2849 case CVT_imm_95_3074:
2850 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2851 Operands[*(p + 1)]->setConstraint("");
2852 ++NumMCOperands;
2853 break;
2854 case CVT_imm_95_3202:
2855 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2856 Operands[*(p + 1)]->setConstraint("");
2857 ++NumMCOperands;
2858 break;
2859 case CVT_imm_95_3073:
2860 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2861 Operands[*(p + 1)]->setConstraint("");
2862 ++NumMCOperands;
2863 break;
2864 case CVT_imm_95_3201:
2865 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2866 Operands[*(p + 1)]->setConstraint("");
2867 ++NumMCOperands;
2868 break;
2869 case CVT_95_addVTypeIOperands:
2870 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2871 Operands[*(p + 1)]->setConstraint("m");
2872 NumMCOperands += 1;
2873 break;
2874 case CVT_reg0:
2875 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2876 Operands[*(p + 1)]->setConstraint("m");
2877 ++NumMCOperands;
2878 break;
2879 case CVT_imm_95_255:
2880 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2881 Operands[*(p + 1)]->setConstraint("");
2882 ++NumMCOperands;
2883 break;
2884 }
2885 }
2886}
2887
2888namespace {
2889
2890/// MatchClassKind - The kinds of classes which participate in
2891/// instruction matching.
2892enum MatchClassKind {
2893 InvalidMatchClass = 0,
2894 OptionalMatchClass = 1,
2895 MCK__40_, // '('
2896 MCK__41_, // ')'
2897 MCK_LAST_TOKEN = MCK__41_,
2898 MCK_Reg142, // derived register class
2899 MCK_Reg139, // derived register class
2900 MCK_Reg136, // derived register class
2901 MCK_Reg133, // derived register class
2902 MCK_Reg130, // derived register class
2903 MCK_Reg127, // derived register class
2904 MCK_Reg124, // derived register class
2905 MCK_Reg121, // derived register class
2906 MCK_Reg118, // derived register class
2907 MCK_Reg115, // derived register class
2908 MCK_Reg112, // derived register class
2909 MCK_Reg98, // derived register class
2910 MCK_Reg95, // derived register class
2911 MCK_Reg92, // derived register class
2912 MCK_Reg73, // derived register class
2913 MCK_Reg68, // derived register class
2914 MCK_Reg65, // derived register class
2915 MCK_Reg62, // derived register class
2916 MCK_Reg59, // derived register class
2917 MCK_Reg54, // derived register class
2918 MCK_Reg45, // derived register class
2919 MCK_Reg44, // derived register class
2920 MCK_Reg38, // derived register class
2921 MCK_Reg33, // derived register class
2922 MCK_GPRX0, // register class 'GPRX0'
2923 MCK_GPRX1, // register class 'GPRX1'
2924 MCK_GPRX5, // register class 'GPRX5'
2925 MCK_GPRX7, // register class 'GPRX7'
2926 MCK_MR0, // register class 'MR0'
2927 MCK_SP, // register class 'SP'
2928 MCK_VMV0, // register class 'VMV0'
2929 MCK_anonymous_15375, // register class 'anonymous_15375'
2930 MCK_Reg55, // derived register class
2931 MCK_Reg43, // derived register class
2932 MCK_Reg29, // derived register class
2933 MCK_GPRX1X5, // register class 'GPRX1X5'
2934 MCK_Reg78, // derived register class
2935 MCK_VCSR, // register class 'VCSR'
2936 MCK_VRM8NoV0, // register class 'VRM8NoV0'
2937 MCK_Reg77, // derived register class
2938 MCK_GPRPairC, // register class 'GPRPairC'
2939 MCK_TRM4, // register class 'TRM4'
2940 MCK_VRM8, // register class 'VRM8'
2941 MCK_Reg79, // derived register class
2942 MCK_Reg80, // derived register class
2943 MCK_Reg71, // derived register class
2944 MCK_Reg58, // derived register class
2945 MCK_Reg32, // derived register class
2946 MCK_VRN2M4NoV0, // register class 'VRN2M4NoV0'
2947 MCK_Reg72, // derived register class
2948 MCK_VRM4NoV0, // register class 'VRM4NoV0'
2949 MCK_VRN2M4, // register class 'VRN2M4'
2950 MCK_Reg107, // derived register class
2951 MCK_Reg88, // derived register class
2952 MCK_Reg57, // derived register class
2953 MCK_Reg56, // derived register class
2954 MCK_FPR16C, // register class 'FPR16C'
2955 MCK_FPR32C, // register class 'FPR32C'
2956 MCK_FPR64C, // register class 'FPR64C'
2957 MCK_GPRC, // register class 'GPRC'
2958 MCK_GPRF16C, // register class 'GPRF16C'
2959 MCK_GPRF32C, // register class 'GPRF32C'
2960 MCK_MR, // register class 'MR'
2961 MCK_SR07, // register class 'SR07'
2962 MCK_TRM2, // register class 'TRM2'
2963 MCK_VRM4, // register class 'VRM4'
2964 MCK_Reg75, // derived register class
2965 MCK_Reg76, // derived register class
2966 MCK_Reg69, // derived register class
2967 MCK_Reg52, // derived register class
2968 MCK_Reg26, // derived register class
2969 MCK_VRN4M2NoV0, // register class 'VRN4M2NoV0'
2970 MCK_Reg70, // derived register class
2971 MCK_Reg66, // derived register class
2972 MCK_Reg53, // derived register class
2973 MCK_Reg48, // derived register class
2974 MCK_Reg22, // derived register class
2975 MCK_GPRTCNonX7, // register class 'GPRTCNonX7'
2976 MCK_VRN3M2NoV0, // register class 'VRN3M2NoV0'
2977 MCK_VRN4M2, // register class 'VRN4M2'
2978 MCK_Reg67, // derived register class
2979 MCK_Reg63, // derived register class
2980 MCK_Reg49, // derived register class
2981 MCK_GPRTC, // register class 'GPRTC'
2982 MCK_VRN2M2NoV0, // register class 'VRN2M2NoV0'
2983 MCK_VRN3M2, // register class 'VRN3M2'
2984 MCK_Reg61, // derived register class
2985 MCK_GPRPairNoX0, // register class 'GPRPairNoX0'
2986 MCK_VRM2NoV0, // register class 'VRM2NoV0'
2987 MCK_VRN2M2, // register class 'VRN2M2'
2988 MCK_GPRPair, // register class 'GPRPair'
2989 MCK_TR, // register class 'TR'
2990 MCK_VRM2, // register class 'VRM2'
2991 MCK_Reg50, // derived register class
2992 MCK_Reg24, // derived register class
2993 MCK_VRN8M1NoV0, // register class 'VRN8M1NoV0'
2994 MCK_Reg51, // derived register class
2995 MCK_Reg46, // derived register class
2996 MCK_Reg20, // derived register class
2997 MCK_GPRJALRNonX7, // register class 'GPRJALRNonX7'
2998 MCK_VRN7M1NoV0, // register class 'VRN7M1NoV0'
2999 MCK_VRN8M1, // register class 'VRN8M1'
3000 MCK_Reg47, // derived register class
3001 MCK_GPRJALR, // register class 'GPRJALR'
3002 MCK_VRN6M1NoV0, // register class 'VRN6M1NoV0'
3003 MCK_VRN7M1, // register class 'VRN7M1'
3004 MCK_VRN5M1NoV0, // register class 'VRN5M1NoV0'
3005 MCK_VRN6M1, // register class 'VRN6M1'
3006 MCK_VRN4M1NoV0, // register class 'VRN4M1NoV0'
3007 MCK_VRN5M1, // register class 'VRN5M1'
3008 MCK_Reg41, // derived register class
3009 MCK_Reg15, // derived register class
3010 MCK_VRN3M1NoV0, // register class 'VRN3M1NoV0'
3011 MCK_VRN4M1, // register class 'VRN4M1'
3012 MCK_Reg42, // derived register class
3013 MCK_Reg39, // derived register class
3014 MCK_Reg36, // derived register class
3015 MCK_Reg13, // derived register class
3016 MCK_Reg10, // derived register class
3017 MCK_GPRNoX0X2, // register class 'GPRNoX0X2'
3018 MCK_VRN2M1NoV0, // register class 'VRN2M1NoV0'
3019 MCK_VRN3M1, // register class 'VRN3M1'
3020 MCK_Reg40, // derived register class
3021 MCK_Reg37, // derived register class
3022 MCK_Reg34, // derived register class
3023 MCK_GPRF16NoX0, // register class 'GPRF16NoX0'
3024 MCK_GPRF32NoX0, // register class 'GPRF32NoX0'
3025 MCK_GPRNoX0, // register class 'GPRNoX0'
3026 MCK_GPRNoX2, // register class 'GPRNoX2'
3027 MCK_GPRNoX31, // register class 'GPRNoX31'
3028 MCK_VRN2M1, // register class 'VRN2M1'
3029 MCK_VRNoV0, // register class 'VRNoV0,ZZZ_VMNoV0,ZZZ_VRMF2NoV0,ZZZ_VRMF4NoV0,ZZZ_VRMF8NoV0'
3030 MCK_FPR128, // register class 'FPR128'
3031 MCK_FPR16, // register class 'FPR16'
3032 MCK_FPR256, // register class 'FPR256'
3033 MCK_FPR32, // register class 'FPR32'
3034 MCK_FPR64, // register class 'FPR64'
3035 MCK_GPR, // register class 'GPR'
3036 MCK_GPRF16, // register class 'GPRF16'
3037 MCK_GPRF32, // register class 'GPRF32'
3038 MCK_VR, // register class 'VR,ZZZ_VM,ZZZ_VRMF2,ZZZ_VRMF4,ZZZ_VRMF8'
3039 MCK_YGPR, // register class 'YGPR'
3040 MCK_GPRAll, // register class 'GPRAll'
3041 MCK_LAST_REGISTER = MCK_GPRAll,
3042 MCK_AnyRegCOperand, // user defined class 'AnyRegCOperand'
3043 MCK_AnyRegOperand, // user defined class 'AnyRegOperand'
3044 MCK_BareSymbol, // user defined class 'BareSymbol'
3045 MCK_BareSymbolQC_E_LI, // user defined class 'BareSymbolQC_E_LI'
3046 MCK_CLUIImm, // user defined class 'CLUIImmAsmOperand'
3047 MCK_CSRSystemRegister, // user defined class 'CSRSystemRegister'
3048 MCK_RegReg, // user defined class 'CVrrAsmOperand'
3049 MCK_CallSymbol, // user defined class 'CallSymbol'
3050 MCK_FRMArg, // user defined class 'FRMArg'
3051 MCK_FRMArgLegacy, // user defined class 'FRMArgLegacy'
3052 MCK_FenceArg, // user defined class 'FenceArg'
3053 MCK_GPRAsFPR16, // user defined class 'GPRAsFPR16'
3054 MCK_GPRAsFPR32, // user defined class 'GPRAsFPR32'
3055 MCK_GPRF64AsFPR, // user defined class 'GPRF64AsFPR'
3056 MCK_GPRPairAsFPR, // user defined class 'GPRPairAsFPR'
3057 MCK_GPRPairCRV32, // user defined class 'GPRPairCRV32Operand'
3058 MCK_GPRPairNoX0RV32, // user defined class 'GPRPairNoX0RV32Operand'
3059 MCK_GPRPairRV32, // user defined class 'GPRPairRV32Operand'
3060 MCK_GPRPairRV64, // user defined class 'GPRPairRV64Operand'
3061 MCK_Imm, // user defined class 'ImmAsmOperand'
3062 MCK_ImmFour, // user defined class 'ImmFourAsmOperand'
3063 MCK_ImmThree, // user defined class 'ImmThreeAsmOperand'
3064 MCK_ImmZero, // user defined class 'ImmZeroAsmOperand'
3065 MCK_InsnCDirectiveOpcode, // user defined class 'InsnCDirectiveOpcode'
3066 MCK_InsnDirectiveOpcode, // user defined class 'InsnDirectiveOpcode'
3067 MCK_LoadFPImm, // user defined class 'LoadFPImmOperand'
3068 MCK_NegStackAdj, // user defined class 'NegStackAdjAsmOperand'
3069 MCK_PseudoJumpSymbol, // user defined class 'PseudoJumpSymbol'
3070 MCK_RTZArg, // user defined class 'RTZArg'
3071 MCK_RegList, // user defined class 'RegListAsmOperand'
3072 MCK_RegListS0, // user defined class 'RegListS0AsmOperand'
3073 MCK_RnumArg, // user defined class 'RnumArg'
3074 MCK_SImm10Unsigned, // user defined class 'SImm10UnsignedAsmOperand'
3075 MCK_SImm8Unsigned, // user defined class 'SImm8UnsignedAsmOperand'
3076 MCK_BareSImm21Lsb0, // user defined class 'Simm21Lsb0JALAsmOperand'
3077 MCK_StackAdj, // user defined class 'StackAdjAsmOperand'
3078 MCK_TLSDESCCallSymbol, // user defined class 'TLSDESCCallSymbol'
3079 MCK_TPRelAddSymbol, // user defined class 'TPRelAddSymbol'
3080 MCK_UImm5Plus1, // user defined class 'UImm5Plus1AsmOperand'
3081 MCK_UImmLog2XLen, // user defined class 'UImmLog2XLenAsmOperand'
3082 MCK_UImmLog2XLenNonZero, // user defined class 'UImmLog2XLenNonZeroAsmOperand'
3083 MCK_RVVMaskRegOpOperand, // user defined class 'VMaskAsmOperand'
3084 MCK_RVVMaskCarryInRegOpOperand, // user defined class 'VMaskCarryInAsmOperand'
3085 MCK_XSfmmVType, // user defined class 'XSfmmVTypeAsmOperand'
3086 MCK_ZeroOffsetMemOpOperand, // user defined class 'ZeroOffsetMemOpOperand'
3087 MCK_UImm1, // user defined class 'anonymous_15772'
3088 MCK_UImm2, // user defined class 'anonymous_15773'
3089 MCK_UImm3, // user defined class 'anonymous_15774'
3090 MCK_UImm4, // user defined class 'anonymous_15775'
3091 MCK_UImm5, // user defined class 'anonymous_15776'
3092 MCK_UImm6, // user defined class 'anonymous_15777'
3093 MCK_UImm7, // user defined class 'anonymous_15778'
3094 MCK_UImm8, // user defined class 'anonymous_15779'
3095 MCK_UImm16, // user defined class 'anonymous_15780'
3096 MCK_UImm32, // user defined class 'anonymous_15781'
3097 MCK_UImm48, // user defined class 'anonymous_15782'
3098 MCK_UImm64, // user defined class 'anonymous_15783'
3099 MCK_SImm12, // user defined class 'anonymous_15784'
3100 MCK_SImm12LO, // user defined class 'anonymous_15785'
3101 MCK_BareSImm13Lsb0, // user defined class 'anonymous_15786'
3102 MCK_UImm20, // user defined class 'anonymous_15787'
3103 MCK_UImm20LUI, // user defined class 'anonymous_15788'
3104 MCK_UImm20AUIPC, // user defined class 'anonymous_15789'
3105 MCK_ImmXLenLI, // user defined class 'anonymous_15790'
3106 MCK_ImmXLenLI_Restricted, // user defined class 'anonymous_15791'
3107 MCK_SImm12Lsb00000, // user defined class 'anonymous_16767'
3108 MCK_Imm5Zibi, // user defined class 'anonymous_16779'
3109 MCK_VTypeI10, // user defined class 'anonymous_17474'
3110 MCK_VTypeI11, // user defined class 'anonymous_17475'
3111 MCK_SImm5, // user defined class 'anonymous_17476'
3112 MCK_SImm5Plus1, // user defined class 'anonymous_17477'
3113 MCK_SImm10, // user defined class 'anonymous_60170'
3114 MCK_SImm6, // user defined class 'anonymous_60324'
3115 MCK_SImm6NonZero, // user defined class 'anonymous_60325'
3116 MCK_UImm7Lsb00, // user defined class 'anonymous_60326'
3117 MCK_UImm8Lsb00, // user defined class 'anonymous_60327'
3118 MCK_UImm8Lsb000, // user defined class 'anonymous_60328'
3119 MCK_BareSImm9Lsb0, // user defined class 'anonymous_60329'
3120 MCK_UImm9Lsb000, // user defined class 'anonymous_60330'
3121 MCK_UImm10Lsb00NonZero, // user defined class 'anonymous_60331'
3122 MCK_SImm10Lsb0000NonZero, // user defined class 'anonymous_60332'
3123 MCK_BareSImm12Lsb0, // user defined class 'anonymous_60333'
3124 MCK_UImm2Lsb0, // user defined class 'anonymous_60425'
3125 MCK_UImm8GE32, // user defined class 'anonymous_60426'
3126 MCK_UImm5Lsb0, // user defined class 'anonymous_62346'
3127 MCK_UImm6Lsb0, // user defined class 'anonymous_62347'
3128 MCK_UImm5NonZero, // user defined class 'anonymous_62365'
3129 MCK_UImm5GT3, // user defined class 'anonymous_62366'
3130 MCK_UImm5GE6Plus1, // user defined class 'anonymous_62367'
3131 MCK_UImm5Slist, // user defined class 'anonymous_62368'
3132 MCK_UImm10, // user defined class 'anonymous_62369'
3133 MCK_UImm11, // user defined class 'anonymous_62370'
3134 MCK_UImm14Lsb00, // user defined class 'anonymous_62371'
3135 MCK_UImm16NonZero, // user defined class 'anonymous_62372'
3136 MCK_SImm5NonZero, // user defined class 'anonymous_62373'
3137 MCK_SImm11, // user defined class 'anonymous_62374'
3138 MCK_SImm16, // user defined class 'anonymous_62375'
3139 MCK_SImm16NonZero, // user defined class 'anonymous_62376'
3140 MCK_SImm20LI, // user defined class 'anonymous_62377'
3141 MCK_SImm26, // user defined class 'anonymous_62378'
3142 MCK_BareSImm32, // user defined class 'anonymous_62379'
3143 MCK_BareSImm32Lsb0, // user defined class 'anonymous_62380'
3144 MCK_UImm7Lsb000, // user defined class 'anonymous_62610'
3145 MCK_UImm9, // user defined class 'anonymous_62611'
3146 MCK_BareSImm11Lsb0, // user defined class 'anonymous_62890'
3147 MCK_SImm18, // user defined class 'anonymous_62891'
3148 MCK_SImm18Lsb0, // user defined class 'anonymous_62892'
3149 MCK_SImm19Lsb00, // user defined class 'anonymous_62893'
3150 MCK_SImm20Lsb000, // user defined class 'anonymous_62894'
3151 NumMatchClassKinds
3152};
3153
3154} // end anonymous namespace
3155
3156static const char *getMatchKindDiag(RISCVAsmParser::RISCVMatchResultTy MatchResult) {
3157 switch (MatchResult) {
3158 case RISCVAsmParser::Match_InvalidRegClassGPRX1:
3159 return "register must be ra (x1)";
3160 case RISCVAsmParser::Match_InvalidRegClassGPRX5:
3161 return "register must be t0 (x5)";
3162 case RISCVAsmParser::Match_InvalidRegClassSP:
3163 return "register must be sp (x2)";
3164 case RISCVAsmParser::Match_InvalidRegClassGPRX1X5:
3165 return "register must be ra or t0 (x1 or x5)";
3166 case RISCVAsmParser::Match_InvalidRegClassGPRNoX0X2:
3167 return "register must be a GPR excluding zero (x0) and sp (x2)";
3168 case RISCVAsmParser::Match_InvalidRegClassGPRNoX0:
3169 return "register must be a GPR excluding zero (x0)";
3170 case RISCVAsmParser::Match_InvalidRegClassGPRNoX2:
3171 return "register must be a GPR excluding sp (x2)";
3172 case RISCVAsmParser::Match_InvalidRegClassGPRX31:
3173 return "register must be a GPR excluding t6 (x31)";
3174 case RISCVAsmParser::Match_InvalidBareSymbol:
3175 return "operand must be a bare symbol name";
3176 case RISCVAsmParser::Match_InvalidCallSymbol:
3177 return "operand must be a bare symbol name";
3178 case RISCVAsmParser::Match_InvalidImmFour:
3179 return "operand must be constant 4";
3180 case RISCVAsmParser::Match_InvalidImmThree:
3181 return "operand must be constant 3";
3182 case RISCVAsmParser::Match_InvalidImmZero:
3183 return "immediate must be zero";
3184 case RISCVAsmParser::Match_InvalidLoadFPImm:
3185 return "operand must be a valid floating-point constant";
3186 case RISCVAsmParser::Match_InvalidPseudoJumpSymbol:
3187 return "operand must be a valid jump target";
3188 case RISCVAsmParser::Match_InvalidRTZArg:
3189 return "operand must be 'rtz' floating-point rounding mode";
3190 case RISCVAsmParser::Match_InvalidRegList:
3191 return "operand must be {ra [, s0[-sN]]} or {x1 [, x8[-x9][, x18[-xN]]]}";
3192 case RISCVAsmParser::Match_InvalidRegListS0:
3193 return "operand must be {ra, s0[-sN]} or {x1, x8[-x9][, x18[-xN]]}";
3194 case RISCVAsmParser::Match_InvalidTLSDESCCallSymbol:
3195 return "operand must be a symbol with %tlsdesc_call specifier";
3196 case RISCVAsmParser::Match_InvalidTPRelAddSymbol:
3197 return "operand must be a symbol with %tprel_add specifier";
3198 case RISCVAsmParser::Match_InvalidVMaskRegister:
3199 return "operand must be v0.t";
3200 case RISCVAsmParser::Match_InvalidVMaskCarryInRegister:
3201 return "operand must be v0";
3202 default:
3203 return nullptr;
3204 }
3205}
3206
3207static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
3208 switch (RegisterClass) {
3209 case MCK_GPRX1:
3210 return RISCVAsmParser::Match_InvalidRegClassGPRX1;
3211 case MCK_GPRX5:
3212 return RISCVAsmParser::Match_InvalidRegClassGPRX5;
3213 case MCK_SP:
3214 return RISCVAsmParser::Match_InvalidRegClassSP;
3215 case MCK_GPRX1X5:
3216 return RISCVAsmParser::Match_InvalidRegClassGPRX1X5;
3217 case MCK_GPRNoX0X2:
3218 return RISCVAsmParser::Match_InvalidRegClassGPRNoX0X2;
3219 case MCK_GPRNoX0:
3220 return RISCVAsmParser::Match_InvalidRegClassGPRNoX0;
3221 case MCK_GPRNoX2:
3222 return RISCVAsmParser::Match_InvalidRegClassGPRNoX2;
3223 case MCK_GPRNoX31:
3224 return RISCVAsmParser::Match_InvalidRegClassGPRX31;
3225 default:
3226 return MCTargetAsmParser::Match_InvalidOperand;
3227 }
3228}
3229
3230static MatchClassKind matchTokenString(StringRef Name) {
3231 switch (Name.size()) {
3232 default: break;
3233 case 1: // 2 strings to match.
3234 switch (Name[0]) {
3235 default: break;
3236 case '(': // 1 string to match.
3237 return MCK__40_; // "("
3238 case ')': // 1 string to match.
3239 return MCK__41_; // ")"
3240 }
3241 break;
3242 }
3243 return InvalidMatchClass;
3244}
3245
3246/// isSubclass - Compute whether \p A is a subclass of \p B.
3247static bool isSubclass(MatchClassKind A, MatchClassKind B) {
3248 if (A == B)
3249 return true;
3250
3251 [[maybe_unused]] static constexpr struct {
3252 uint32_t Offset;
3253 uint16_t Start;
3254 uint16_t Length;
3255 } Table[] = {
3256 {0, 0, 0},
3257 {0, 0, 0},
3258 {0, 0, 0},
3259 {0, 0, 0},
3260 {0, 105, 1},
3261 {1, 109, 1},
3262 {2, 111, 1},
3263 {3, 113, 1},
3264 {4, 83, 1},
3265 {5, 117, 1},
3266 {6, 89, 1},
3267 {7, 125, 1},
3268 {8, 55, 1},
3269 {9, 93, 1},
3270 {10, 134, 1},
3271 {11, 46, 1},
3272 {12, 69, 1},
3273 {13, 96, 1},
3274 {14, 43, 52},
3275 {66, 49, 46},
3276 {112, 77, 18},
3277 {130, 85, 10},
3278 {140, 90, 5},
3279 {145, 79, 67},
3280 {212, 37, 109},
3281 {321, 119, 27},
3282 {348, 37, 109},
3283 {457, 120, 26},
3284 {483, 122, 25},
3285 {508, 39, 108},
3286 {616, 39, 108},
3287 {724, 80, 67},
3288 {791, 66, 1},
3289 {792, 121, 26},
3290 {818, 144, 1},
3291 {819, 0, 0},
3292 {819, 58, 88},
3293 {907, 114, 32},
3294 {939, 63, 84},
3295 {1023, 115, 32},
3296 {1055, 44, 51},
3297 {1106, 0, 0},
3298 {1106, 46, 1},
3299 {1107, 70, 25},
3300 {1132, 70, 25},
3301 {1157, 68, 28},
3302 {1185, 0, 0},
3303 {1185, 48, 47},
3304 {1232, 53, 42},
3305 {1274, 53, 42},
3306 {1316, 59, 87},
3307 {1403, 63, 84},
3308 {1487, 55, 1},
3309 {1488, 76, 19},
3310 {1507, 69, 1},
3311 {1508, 0, 0},
3312 {1508, 138, 1},
3313 {1509, 136, 1},
3314 {1510, 97, 49},
3315 {1559, 97, 49},
3316 {1608, 137, 1},
3317 {1609, 139, 1},
3318 {1610, 140, 1},
3319 {1611, 98, 49},
3320 {1660, 129, 14},
3321 {1674, 130, 14},
3322 {1688, 0, 0},
3323 {1688, 98, 49},
3324 {1737, 95, 1},
3325 {1738, 0, 0},
3326 {1738, 71, 24},
3327 {1762, 76, 19},
3328 {1781, 76, 19},
3329 {1800, 78, 68},
3330 {1868, 80, 67},
3331 {1935, 83, 1},
3332 {1936, 84, 11},
3333 {1947, 84, 11},
3334 {1958, 86, 60},
3335 {2018, 86, 60},
3336 {2078, 87, 60},
3337 {2138, 87, 60},
3338 {2198, 89, 1},
3339 {2199, 0, 0},
3340 {2199, 90, 5},
3341 {2204, 91, 4},
3342 {2208, 106, 40},
3343 {2248, 107, 40},
3344 {2288, 93, 1},
3345 {2289, 0, 0},
3346 {2289, 94, 1},
3347 {2290, 94, 1},
3348 {2291, 96, 1},
3349 {2292, 0, 0},
3350 {2292, 0, 0},
3351 {2292, 0, 0},
3352 {2292, 0, 0},
3353 {2292, 100, 46},
3354 {2338, 102, 45},
3355 {2383, 105, 1},
3356 {2384, 106, 40},
3357 {2424, 106, 40},
3358 {2464, 107, 40},
3359 {2504, 107, 40},
3360 {2544, 109, 1},
3361 {2545, 0, 0},
3362 {2545, 118, 28},
3363 {2573, 123, 24},
3364 {2597, 111, 1},
3365 {2598, 0, 0},
3366 {2598, 113, 1},
3367 {2599, 0, 0},
3368 {2599, 117, 1},
3369 {2600, 0, 0},
3370 {2600, 118, 28},
3371 {2628, 121, 26},
3372 {2654, 125, 1},
3373 {2655, 0, 0},
3374 {2655, 126, 20},
3375 {2675, 126, 20},
3376 {2695, 127, 19},
3377 {2714, 131, 16},
3378 {2730, 132, 15},
3379 {2745, 131, 16},
3380 {2761, 134, 1},
3381 {2762, 0, 0},
3382 {2762, 145, 1},
3383 {2763, 145, 1},
3384 {2764, 145, 1},
3385 {2765, 142, 1},
3386 {2766, 143, 1},
3387 {2767, 141, 6},
3388 {2773, 141, 6},
3389 {2779, 141, 6},
3390 {2785, 0, 0},
3391 {2785, 144, 1},
3392 {2786, 0, 0},
3393 {2786, 0, 0},
3394 {2786, 0, 0},
3395 {2786, 0, 0},
3396 {2786, 0, 0},
3397 {2786, 146, 1},
3398 {2787, 0, 0},
3399 {2787, 0, 0},
3400 {2787, 0, 0},
3401 {2787, 0, 0},
3402 {2787, 0, 0},
3403 {2787, 0, 0},
3404 {2787, 0, 0},
3405 {2787, 0, 0},
3406 {2787, 0, 0},
3407 {2787, 0, 0},
3408 {2787, 0, 0},
3409 {2787, 0, 0},
3410 {2787, 0, 0},
3411 {2787, 1, 1},
3412 {2788, 1, 1},
3413 {2789, 0, 0},
3414 {2789, 0, 0},
3415 {2789, 0, 0},
3416 {2789, 0, 0},
3417 {2789, 0, 0},
3418 {2789, 0, 0},
3419 {2789, 0, 0},
3420 {2789, 0, 0},
3421 {2789, 0, 0},
3422 {2789, 0, 0},
3423 {2789, 0, 0},
3424 {2789, 0, 0},
3425 {2789, 0, 0},
3426 {2789, 0, 0},
3427 {2789, 0, 0},
3428 {2789, 0, 0},
3429 {2789, 0, 0},
3430 {2789, 0, 0},
3431 {2789, 0, 0},
3432 {2789, 0, 0},
3433 {2789, 0, 0},
3434 {2789, 0, 0},
3435 {2789, 0, 0},
3436 {2789, 0, 0},
3437 {2789, 0, 0},
3438 {2789, 0, 0},
3439 {2789, 0, 0},
3440 {2789, 0, 0},
3441 {2789, 0, 0},
3442 {2789, 0, 0},
3443 {2789, 0, 0},
3444 {2789, 1, 1},
3445 {2790, 0, 0},
3446 {2790, 0, 0},
3447 {2790, 0, 0},
3448 {2790, 0, 0},
3449 {2790, 0, 0},
3450 {2790, 0, 0},
3451 {2790, 0, 0},
3452 {2790, 0, 0},
3453 {2790, 0, 0},
3454 {2790, 0, 0},
3455 {2790, 0, 0},
3456 {2790, 0, 0},
3457 {2790, 0, 0},
3458 {2790, 0, 0},
3459 {2790, 0, 0},
3460 {2790, 0, 0},
3461 {2790, 0, 0},
3462 {2790, 0, 0},
3463 {2790, 0, 0},
3464 {2790, 0, 0},
3465 {2790, 0, 0},
3466 {2790, 0, 0},
3467 {2790, 0, 0},
3468 {2790, 0, 0},
3469 {2790, 0, 0},
3470 {2790, 0, 0},
3471 {2790, 0, 0},
3472 {2790, 0, 0},
3473 {2790, 0, 0},
3474 {2790, 0, 0},
3475 {2790, 0, 0},
3476 {2790, 0, 0},
3477 {2790, 0, 0},
3478 {2790, 0, 0},
3479 {2790, 0, 0},
3480 {2790, 0, 0},
3481 {2790, 0, 0},
3482 {2790, 0, 0},
3483 {2790, 0, 0},
3484 {2790, 0, 0},
3485 {2790, 0, 0},
3486 {2790, 0, 0},
3487 {2790, 0, 0},
3488 {2790, 0, 0},
3489 {2790, 0, 0},
3490 {2790, 0, 0},
3491 {2790, 0, 0},
3492 {2790, 0, 0},
3493 {2790, 0, 0},
3494 {2790, 0, 0},
3495 {2790, 0, 0},
3496 {2790, 0, 0},
3497 {2790, 0, 0},
3498 {2790, 0, 0},
3499 {2790, 0, 0},
3500 {2790, 0, 0},
3501 {2790, 0, 0},
3502 {2790, 0, 0},
3503 {2790, 0, 0},
3504 {2790, 0, 0},
3505 {2790, 0, 0},
3506 {2790, 0, 0},
3507 {2790, 0, 0},
3508 {2790, 0, 0},
3509 {2790, 0, 0},
3510 {2790, 0, 0},
3511 {2790, 0, 0},
3512 };
3513
3514 static constexpr uint8_t Data[] = {
3515 0xFF,
3516 0xFF,
3517 0x00,
3518 0x00,
3519 0x00,
3520 0x8E,
3521 0x81,
3522 0x61,
3523 0x46,
3524 0x00,
3525 0x00,
3526 0x62,
3527 0x60,
3528 0x98,
3529 0x81,
3530 0x61,
3531 0x06,
3532 0x19,
3533 0x03,
3534 0x01,
3535 0x80,
3536 0x10,
3537 0x10,
3538 0x07,
3539 0x07,
3540 0x00,
3541 0x18,
3542 0x00,
3543 0x00,
3544 0x00,
3545 0x00,
3546 0x00,
3547 0x00,
3548 0x00,
3549 0x00,
3550 0x00,
3551 0xE2,
3552 0xE0,
3553 0x00,
3554 0x00,
3555 0x03,
3556 0x05,
3557 0x00,
3558 0x18,
3559 0x00,
3560 0x00,
3561 0x00,
3562 0x00,
3563 0x00,
3564 0x00,
3565 0x00,
3566 0x00,
3567 0x00,
3568 0xE2,
3569 0xE0,
3570 0x00,
3571 0x00,
3572 0x03,
3573 0x03,
3574 0x00,
3575 0x0C,
3576 0x60,
3577 0x40,
3578 0x18,
3579 0x00,
3580 0x00,
3581 0x00,
3582 0x00,
3583 0x00,
3584 0x00,
3585 0x00,
3586 0x00,
3587 0x00,
3588 0xC1,
3589 0x01,
3590 0x07,
3591 0x84,
3592 0x01,
3593 0x00,
3594 0x00,
3595 0x00,
3596 0x00,
3597 0x00,
3598 0x00,
3599 0x00,
3600 0x00,
3601 0x10,
3602 0x1C,
3603 0x70,
3604 0x40,
3605 0x18,
3606 0x08,
3607 0x00,
3608 0x84,
3609 0x80,
3610 0xE0,
3611 0x80,
3612 0x03,
3613 0xC2,
3614 0x01,
3615 0x14,
3616 0x10,
3617 0x1E,
3618 0x00,
3619 0x00,
3620 0x00,
3621 0x00,
3622 0x64,
3623 0x08,
3624 0x88,
3625 0x83,
3626 0x03,
3627 0x00,
3628 0x8C,
3629 0x83,
3630 0x03,
3631 0x00,
3632 0x8C,
3633 0x00,
3634 0x00,
3635 0x00,
3636 0x40,
3637 0x8C,
3638 0x80,
3639 0xE0,
3640 0x80,
3641 0x03,
3642 0xC2,
3643 0xE0,
3644 0x80,
3645 0x03,
3646 0xC2,
3647 0x1C,
3648 0x01,
3649 0x00,
3650 0x8E,
3651 0x81,
3652 0x61,
3653 0x3E,
3654 0x06,
3655 0x86,
3656 0x79,
3657 0x0C,
3658 0x0C,
3659 0x33,
3660 0x00,
3661 0x00,
3662 0x00,
3663 0x47,
3664 0x00,
3665 0x80,
3666 0x63,
3667 0x60,
3668 0x98,
3669 0x01,
3670 0x00,
3671 0x84,
3672 0x80,
3673 0x60,
3674 0x06,
3675 0x00,
3676 0x20,
3677 0x06,
3678 0x86,
3679 0x19,
3680 0x00,
3681 0x84,
3682 0x81,
3683 0x00,
3684 0x64,
3685 0x08,
3686 0x88,
3687 0x83,
3688 0x03,
3689 0x00,
3690 0x0C,
3691 0x40,
3692 0x30,
3693 0x08,
3694 0x40,
3695 0x8C,
3696 0x80,
3697 0xE0,
3698 0x80,
3699 0x03,
3700 0xC2,
3701 0x01,
3702 0xC1,
3703 0x7C,
3704 0x86,
3705 0x80,
3706 0x38,
3707 0x38,
3708 0x00,
3709 0xC0,
3710 0x0C,
3711 0x01,
3712 0x71,
3713 0x70,
3714 0x00,
3715 0x80,
3716 0x8F,
3717 0x11,
3718 0x10,
3719 0x1C,
3720 0x70,
3721 0x40,
3722 0x18,
3723 0x00,
3724 0x06,
3725 0x80,
3726 0x31,
3727 0x02,
3728 0x82,
3729 0x03,
3730 0x0E,
3731 0x08,
3732 0x8F,
3733 0x81,
3734 0x61,
3735 0x06,
3736 0x04,
3737 0x73,
3738 0x60,
3739 0x98,
3740 0x03,
3741 0x01,
3742 0xC8,
3743 0x10,
3744 0x10,
3745 0x07,
3746 0x07,
3747 0x00,
3748 0x38,
3749 0x08,
3750 0x40,
3751 0x8C,
3752 0x80,
3753 0xE0,
3754 0x80,
3755 0x03,
3756 0xC2,
3757 0xC1,
3758 0x1C,
3759 0x66,
3760 0x00,
3761 0x10,
3762 0x04,
3763 0x40,
3764 0xC0,
3765 0x00,
3766 0x00,
3767 0x06,
3768 0x00,
3769 0x42,
3770 0x40,
3771 0x1C,
3772 0x1C,
3773 0x00,
3774 0x60,
3775 0x00,
3776 0x20,
3777 0x04,
3778 0x04,
3779 0x07,
3780 0x1C,
3781 0x10,
3782 0x06,
3783 0x00,
3784 0x44,
3785 0x00,
3786 0x40,
3787 0xC0,
3788 0x00,
3789 0xE1,
3790 0x99,
3791 0x01,
3792 0x10,
3793 0x30,
3794 0x00,
3795 0x80,
3796 0x01,
3797 0x00,
3798 0x01,
3799 0x03,
3800 0x84,
3801 0x3F,
3802 0x04,
3803 0xC4,
3804 0xC1,
3805 0x01,
3806 0x00,
3807 0x8E,
3808 0x80,
3809 0xE0,
3810 0x80,
3811 0x03,
3812 0xC2,
3813 0x01,
3814 0x10,
3815 0x30,
3816 0x00,
3817 0x80,
3818 0x01,
3819 0x71,
3820 0x70,
3821 0x00,
3822 0x80,
3823 0x01,
3824 0xC1,
3825 0x01,
3826 0x07,
3827 0x84,
3828 0x01,
3829 0x00,
3830 0x01,
3831 0x03,
3832 0x84,
3833 0x03,
3834 0x06,
3835 0x00,
3836 0x30,
3837 0x60,
3838 0x80,
3839 0xF0,
3840 0x07,
3841 0x07,
3842 0x00,
3843 0x78,
3844 0xC0,
3845 0x01,
3846 0xE1,
3847 0x01,
3848 0x00,
3849 0x2C,
3850 0x00,
3851 0xC0,
3852 0x01,
3853 0x00,
3854 0x16,
3855 0x10,
3856 0x0E,
3857 0x08,
3858 0x07,
3859 0x08,
3860 0xFF,
3861 0x30,
3862 0x0C,
3863 0x3F,
3864 };
3865
3866 auto &Entry = Table[A];
3867 unsigned Idx = B - Entry.Start;
3868 if (Idx >= Entry.Length)
3869 return false;
3870 Idx += Entry.Offset;
3871 return (Data[Idx / 8] >> (Idx % 8)) & 1;
3872}
3873
3874static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
3875 RISCVOperand &Operand = (RISCVOperand &)GOp;
3876 if (Kind == InvalidMatchClass)
3877 return MCTargetAsmParser::Match_InvalidOperand;
3878
3879 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
3880 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
3881 MCTargetAsmParser::Match_Success :
3882 MCTargetAsmParser::Match_InvalidOperand;
3883
3884 switch (Kind) {
3885 default: break;
3886 case MCK_AnyRegCOperand: {
3887 DiagnosticPredicate DP(Operand.isAnyRegC());
3888 if (DP.isMatch())
3889 return MCTargetAsmParser::Match_Success;
3890 break;
3891 }
3892 case MCK_AnyRegOperand: {
3893 DiagnosticPredicate DP(Operand.isAnyReg());
3894 if (DP.isMatch())
3895 return MCTargetAsmParser::Match_Success;
3896 break;
3897 }
3898 case MCK_BareSymbol: {
3899 DiagnosticPredicate DP(Operand.isBareSymbol());
3900 if (DP.isMatch())
3901 return MCTargetAsmParser::Match_Success;
3902 if (DP.isNearMatch())
3903 return RISCVAsmParser::Match_InvalidBareSymbol;
3904 break;
3905 }
3906 case MCK_BareSymbolQC_E_LI: {
3907 DiagnosticPredicate DP(Operand.isBareSymbol());
3908 if (DP.isMatch())
3909 return MCTargetAsmParser::Match_Success;
3910 if (DP.isNearMatch())
3911 return RISCVAsmParser::Match_InvalidBareSymbolQC_E_LI;
3912 break;
3913 }
3914 case MCK_CLUIImm: {
3915 DiagnosticPredicate DP(Operand.isCLUIImm());
3916 if (DP.isMatch())
3917 return MCTargetAsmParser::Match_Success;
3918 if (DP.isNearMatch())
3919 return RISCVAsmParser::Match_InvalidCLUIImm;
3920 break;
3921 }
3922 case MCK_CSRSystemRegister: {
3923 DiagnosticPredicate DP(Operand.isCSRSystemRegister());
3924 if (DP.isMatch())
3925 return MCTargetAsmParser::Match_Success;
3926 if (DP.isNearMatch())
3927 return RISCVAsmParser::Match_InvalidCSRSystemRegister;
3928 break;
3929 }
3930 case MCK_RegReg: {
3931 DiagnosticPredicate DP(Operand.isRegReg());
3932 if (DP.isMatch())
3933 return MCTargetAsmParser::Match_Success;
3934 break;
3935 }
3936 case MCK_CallSymbol: {
3937 DiagnosticPredicate DP(Operand.isCallSymbol());
3938 if (DP.isMatch())
3939 return MCTargetAsmParser::Match_Success;
3940 if (DP.isNearMatch())
3941 return RISCVAsmParser::Match_InvalidCallSymbol;
3942 break;
3943 }
3944 case MCK_FRMArg: {
3945 DiagnosticPredicate DP(Operand.isFRMArg());
3946 if (DP.isMatch())
3947 return MCTargetAsmParser::Match_Success;
3948 break;
3949 }
3950 case MCK_FRMArgLegacy: {
3951 DiagnosticPredicate DP(Operand.isFRMArgLegacy());
3952 if (DP.isMatch())
3953 return MCTargetAsmParser::Match_Success;
3954 break;
3955 }
3956 case MCK_FenceArg: {
3957 DiagnosticPredicate DP(Operand.isFenceArg());
3958 if (DP.isMatch())
3959 return MCTargetAsmParser::Match_Success;
3960 break;
3961 }
3962 case MCK_GPRAsFPR16: {
3963 DiagnosticPredicate DP(Operand.isGPRAsFPR16());
3964 if (DP.isMatch())
3965 return MCTargetAsmParser::Match_Success;
3966 break;
3967 }
3968 case MCK_GPRAsFPR32: {
3969 DiagnosticPredicate DP(Operand.isGPRAsFPR32());
3970 if (DP.isMatch())
3971 return MCTargetAsmParser::Match_Success;
3972 break;
3973 }
3974 case MCK_GPRF64AsFPR: {
3975 DiagnosticPredicate DP(Operand.isGPRAsFPR());
3976 if (DP.isMatch())
3977 return MCTargetAsmParser::Match_Success;
3978 break;
3979 }
3980 case MCK_GPRPairAsFPR: {
3981 DiagnosticPredicate DP(Operand.isGPRPairAsFPR64());
3982 if (DP.isMatch())
3983 return MCTargetAsmParser::Match_Success;
3984 break;
3985 }
3986 case MCK_GPRPairCRV32: {
3987 DiagnosticPredicate DP(Operand.isGPRPairC());
3988 if (DP.isMatch())
3989 return MCTargetAsmParser::Match_Success;
3990 break;
3991 }
3992 case MCK_GPRPairNoX0RV32: {
3993 DiagnosticPredicate DP(Operand.isGPRPairNoX0());
3994 if (DP.isMatch())
3995 return MCTargetAsmParser::Match_Success;
3996 break;
3997 }
3998 case MCK_GPRPairRV32: {
3999 DiagnosticPredicate DP(Operand.isGPRPair());
4000 if (DP.isMatch())
4001 return MCTargetAsmParser::Match_Success;
4002 break;
4003 }
4004 case MCK_GPRPairRV64: {
4005 DiagnosticPredicate DP(Operand.isGPRPair());
4006 if (DP.isMatch())
4007 return MCTargetAsmParser::Match_Success;
4008 break;
4009 }
4010 case MCK_Imm: {
4011 DiagnosticPredicate DP(Operand.isImm());
4012 if (DP.isMatch())
4013 return MCTargetAsmParser::Match_Success;
4014 break;
4015 }
4016 case MCK_ImmFour: {
4017 DiagnosticPredicate DP(Operand.isImmFour());
4018 if (DP.isMatch())
4019 return MCTargetAsmParser::Match_Success;
4020 if (DP.isNearMatch())
4021 return RISCVAsmParser::Match_InvalidImmFour;
4022 break;
4023 }
4024 case MCK_ImmThree: {
4025 DiagnosticPredicate DP(Operand.isImmThree());
4026 if (DP.isMatch())
4027 return MCTargetAsmParser::Match_Success;
4028 if (DP.isNearMatch())
4029 return RISCVAsmParser::Match_InvalidImmThree;
4030 break;
4031 }
4032 case MCK_ImmZero: {
4033 DiagnosticPredicate DP(Operand.isImmZero());
4034 if (DP.isMatch())
4035 return MCTargetAsmParser::Match_Success;
4036 if (DP.isNearMatch())
4037 return RISCVAsmParser::Match_InvalidImmZero;
4038 break;
4039 }
4040 case MCK_InsnCDirectiveOpcode: {
4041 DiagnosticPredicate DP(Operand.isImm());
4042 if (DP.isMatch())
4043 return MCTargetAsmParser::Match_Success;
4044 break;
4045 }
4046 case MCK_InsnDirectiveOpcode: {
4047 DiagnosticPredicate DP(Operand.isImm());
4048 if (DP.isMatch())
4049 return MCTargetAsmParser::Match_Success;
4050 break;
4051 }
4052 case MCK_LoadFPImm: {
4053 DiagnosticPredicate DP(Operand.isLoadFPImm());
4054 if (DP.isMatch())
4055 return MCTargetAsmParser::Match_Success;
4056 if (DP.isNearMatch())
4057 return RISCVAsmParser::Match_InvalidLoadFPImm;
4058 break;
4059 }
4060 case MCK_NegStackAdj: {
4061 DiagnosticPredicate DP(Operand.isStackAdj());
4062 if (DP.isMatch())
4063 return MCTargetAsmParser::Match_Success;
4064 if (DP.isNearMatch())
4065 return RISCVAsmParser::Match_InvalidStackAdj;
4066 break;
4067 }
4068 case MCK_PseudoJumpSymbol: {
4069 DiagnosticPredicate DP(Operand.isPseudoJumpSymbol());
4070 if (DP.isMatch())
4071 return MCTargetAsmParser::Match_Success;
4072 if (DP.isNearMatch())
4073 return RISCVAsmParser::Match_InvalidPseudoJumpSymbol;
4074 break;
4075 }
4076 case MCK_RTZArg: {
4077 DiagnosticPredicate DP(Operand.isRTZArg());
4078 if (DP.isMatch())
4079 return MCTargetAsmParser::Match_Success;
4080 if (DP.isNearMatch())
4081 return RISCVAsmParser::Match_InvalidRTZArg;
4082 break;
4083 }
4084 case MCK_RegList: {
4085 DiagnosticPredicate DP(Operand.isRegList());
4086 if (DP.isMatch())
4087 return MCTargetAsmParser::Match_Success;
4088 if (DP.isNearMatch())
4089 return RISCVAsmParser::Match_InvalidRegList;
4090 break;
4091 }
4092 case MCK_RegListS0: {
4093 DiagnosticPredicate DP(Operand.isRegListS0());
4094 if (DP.isMatch())
4095 return MCTargetAsmParser::Match_Success;
4096 if (DP.isNearMatch())
4097 return RISCVAsmParser::Match_InvalidRegListS0;
4098 break;
4099 }
4100 case MCK_RnumArg: {
4101 DiagnosticPredicate DP(Operand.isRnumArg());
4102 if (DP.isMatch())
4103 return MCTargetAsmParser::Match_Success;
4104 if (DP.isNearMatch())
4105 return RISCVAsmParser::Match_InvalidRnumArg;
4106 break;
4107 }
4108 case MCK_SImm10Unsigned: {
4109 DiagnosticPredicate DP(Operand.isSImm10Unsigned());
4110 if (DP.isMatch())
4111 return MCTargetAsmParser::Match_Success;
4112 if (DP.isNearMatch())
4113 return RISCVAsmParser::Match_InvalidSImm10Unsigned;
4114 break;
4115 }
4116 case MCK_SImm8Unsigned: {
4117 DiagnosticPredicate DP(Operand.isSImm8Unsigned());
4118 if (DP.isMatch())
4119 return MCTargetAsmParser::Match_Success;
4120 if (DP.isNearMatch())
4121 return RISCVAsmParser::Match_InvalidSImm8Unsigned;
4122 break;
4123 }
4124 case MCK_BareSImm21Lsb0: {
4125 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<21>());
4126 if (DP.isMatch())
4127 return MCTargetAsmParser::Match_Success;
4128 if (DP.isNearMatch())
4129 return RISCVAsmParser::Match_InvalidBareSImm21Lsb0;
4130 break;
4131 }
4132 case MCK_StackAdj: {
4133 DiagnosticPredicate DP(Operand.isStackAdj());
4134 if (DP.isMatch())
4135 return MCTargetAsmParser::Match_Success;
4136 if (DP.isNearMatch())
4137 return RISCVAsmParser::Match_InvalidStackAdj;
4138 break;
4139 }
4140 case MCK_TLSDESCCallSymbol: {
4141 DiagnosticPredicate DP(Operand.isTLSDESCCallSymbol());
4142 if (DP.isMatch())
4143 return MCTargetAsmParser::Match_Success;
4144 if (DP.isNearMatch())
4145 return RISCVAsmParser::Match_InvalidTLSDESCCallSymbol;
4146 break;
4147 }
4148 case MCK_TPRelAddSymbol: {
4149 DiagnosticPredicate DP(Operand.isTPRelAddSymbol());
4150 if (DP.isMatch())
4151 return MCTargetAsmParser::Match_Success;
4152 if (DP.isNearMatch())
4153 return RISCVAsmParser::Match_InvalidTPRelAddSymbol;
4154 break;
4155 }
4156 case MCK_UImm5Plus1: {
4157 DiagnosticPredicate DP(Operand.isUImm5Plus1());
4158 if (DP.isMatch())
4159 return MCTargetAsmParser::Match_Success;
4160 if (DP.isNearMatch())
4161 return RISCVAsmParser::Match_InvalidUImm5Plus1;
4162 break;
4163 }
4164 case MCK_UImmLog2XLen: {
4165 DiagnosticPredicate DP(Operand.isUImmLog2XLen());
4166 if (DP.isMatch())
4167 return MCTargetAsmParser::Match_Success;
4168 if (DP.isNearMatch())
4169 return RISCVAsmParser::Match_InvalidUImmLog2XLen;
4170 break;
4171 }
4172 case MCK_UImmLog2XLenNonZero: {
4173 DiagnosticPredicate DP(Operand.isUImmLog2XLenNonZero());
4174 if (DP.isMatch())
4175 return MCTargetAsmParser::Match_Success;
4176 if (DP.isNearMatch())
4177 return RISCVAsmParser::Match_InvalidUImmLog2XLenNonZero;
4178 break;
4179 }
4180 case MCK_RVVMaskRegOpOperand: {
4181 DiagnosticPredicate DP(Operand.isV0Reg());
4182 if (DP.isMatch())
4183 return MCTargetAsmParser::Match_Success;
4184 if (DP.isNearMatch())
4185 return RISCVAsmParser::Match_InvalidVMaskRegister;
4186 break;
4187 }
4188 case MCK_RVVMaskCarryInRegOpOperand: {
4189 DiagnosticPredicate DP(Operand.isV0Reg());
4190 if (DP.isMatch())
4191 return MCTargetAsmParser::Match_Success;
4192 if (DP.isNearMatch())
4193 return RISCVAsmParser::Match_InvalidVMaskCarryInRegister;
4194 break;
4195 }
4196 case MCK_XSfmmVType: {
4197 DiagnosticPredicate DP(Operand.isXSfmmVType());
4198 if (DP.isMatch())
4199 return MCTargetAsmParser::Match_Success;
4200 break;
4201 }
4202 case MCK_ZeroOffsetMemOpOperand: {
4203 DiagnosticPredicate DP(Operand.isGPR());
4204 if (DP.isMatch())
4205 return MCTargetAsmParser::Match_Success;
4206 break;
4207 }
4208 case MCK_UImm1: {
4209 DiagnosticPredicate DP(Operand.isUImm1());
4210 if (DP.isMatch())
4211 return MCTargetAsmParser::Match_Success;
4212 if (DP.isNearMatch())
4213 return RISCVAsmParser::Match_InvalidUImm1;
4214 break;
4215 }
4216 case MCK_UImm2: {
4217 DiagnosticPredicate DP(Operand.isUImm2());
4218 if (DP.isMatch())
4219 return MCTargetAsmParser::Match_Success;
4220 if (DP.isNearMatch())
4221 return RISCVAsmParser::Match_InvalidUImm2;
4222 break;
4223 }
4224 case MCK_UImm3: {
4225 DiagnosticPredicate DP(Operand.isUImm3());
4226 if (DP.isMatch())
4227 return MCTargetAsmParser::Match_Success;
4228 if (DP.isNearMatch())
4229 return RISCVAsmParser::Match_InvalidUImm3;
4230 break;
4231 }
4232 case MCK_UImm4: {
4233 DiagnosticPredicate DP(Operand.isUImm4());
4234 if (DP.isMatch())
4235 return MCTargetAsmParser::Match_Success;
4236 if (DP.isNearMatch())
4237 return RISCVAsmParser::Match_InvalidUImm4;
4238 break;
4239 }
4240 case MCK_UImm5: {
4241 DiagnosticPredicate DP(Operand.isUImm5());
4242 if (DP.isMatch())
4243 return MCTargetAsmParser::Match_Success;
4244 if (DP.isNearMatch())
4245 return RISCVAsmParser::Match_InvalidUImm5;
4246 break;
4247 }
4248 case MCK_UImm6: {
4249 DiagnosticPredicate DP(Operand.isUImm6());
4250 if (DP.isMatch())
4251 return MCTargetAsmParser::Match_Success;
4252 if (DP.isNearMatch())
4253 return RISCVAsmParser::Match_InvalidUImm6;
4254 break;
4255 }
4256 case MCK_UImm7: {
4257 DiagnosticPredicate DP(Operand.isUImm7());
4258 if (DP.isMatch())
4259 return MCTargetAsmParser::Match_Success;
4260 if (DP.isNearMatch())
4261 return RISCVAsmParser::Match_InvalidUImm7;
4262 break;
4263 }
4264 case MCK_UImm8: {
4265 DiagnosticPredicate DP(Operand.isUImm8());
4266 if (DP.isMatch())
4267 return MCTargetAsmParser::Match_Success;
4268 if (DP.isNearMatch())
4269 return RISCVAsmParser::Match_InvalidUImm8;
4270 break;
4271 }
4272 case MCK_UImm16: {
4273 DiagnosticPredicate DP(Operand.isUImm16());
4274 if (DP.isMatch())
4275 return MCTargetAsmParser::Match_Success;
4276 if (DP.isNearMatch())
4277 return RISCVAsmParser::Match_InvalidUImm16;
4278 break;
4279 }
4280 case MCK_UImm32: {
4281 DiagnosticPredicate DP(Operand.isUImm32());
4282 if (DP.isMatch())
4283 return MCTargetAsmParser::Match_Success;
4284 if (DP.isNearMatch())
4285 return RISCVAsmParser::Match_InvalidUImm32;
4286 break;
4287 }
4288 case MCK_UImm48: {
4289 DiagnosticPredicate DP(Operand.isUImm48());
4290 if (DP.isMatch())
4291 return MCTargetAsmParser::Match_Success;
4292 if (DP.isNearMatch())
4293 return RISCVAsmParser::Match_InvalidUImm48;
4294 break;
4295 }
4296 case MCK_UImm64: {
4297 DiagnosticPredicate DP(Operand.isUImm64());
4298 if (DP.isMatch())
4299 return MCTargetAsmParser::Match_Success;
4300 if (DP.isNearMatch())
4301 return RISCVAsmParser::Match_InvalidUImm64;
4302 break;
4303 }
4304 case MCK_SImm12: {
4305 DiagnosticPredicate DP(Operand.isSImm12());
4306 if (DP.isMatch())
4307 return MCTargetAsmParser::Match_Success;
4308 if (DP.isNearMatch())
4309 return RISCVAsmParser::Match_InvalidSImm12;
4310 break;
4311 }
4312 case MCK_SImm12LO: {
4313 DiagnosticPredicate DP(Operand.isSImm12LO());
4314 if (DP.isMatch())
4315 return MCTargetAsmParser::Match_Success;
4316 if (DP.isNearMatch())
4317 return RISCVAsmParser::Match_InvalidSImm12LO;
4318 break;
4319 }
4320 case MCK_BareSImm13Lsb0: {
4321 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<13>());
4322 if (DP.isMatch())
4323 return MCTargetAsmParser::Match_Success;
4324 if (DP.isNearMatch())
4325 return RISCVAsmParser::Match_InvalidBareSImm13Lsb0;
4326 break;
4327 }
4328 case MCK_UImm20: {
4329 DiagnosticPredicate DP(Operand.isUImm20());
4330 if (DP.isMatch())
4331 return MCTargetAsmParser::Match_Success;
4332 if (DP.isNearMatch())
4333 return RISCVAsmParser::Match_InvalidUImm20;
4334 break;
4335 }
4336 case MCK_UImm20LUI: {
4337 DiagnosticPredicate DP(Operand.isUImm20LUI());
4338 if (DP.isMatch())
4339 return MCTargetAsmParser::Match_Success;
4340 if (DP.isNearMatch())
4341 return RISCVAsmParser::Match_InvalidUImm20LUI;
4342 break;
4343 }
4344 case MCK_UImm20AUIPC: {
4345 DiagnosticPredicate DP(Operand.isUImm20AUIPC());
4346 if (DP.isMatch())
4347 return MCTargetAsmParser::Match_Success;
4348 if (DP.isNearMatch())
4349 return RISCVAsmParser::Match_InvalidUImm20AUIPC;
4350 break;
4351 }
4352 case MCK_ImmXLenLI: {
4353 DiagnosticPredicate DP(Operand.isImmXLenLI());
4354 if (DP.isMatch())
4355 return MCTargetAsmParser::Match_Success;
4356 if (DP.isNearMatch())
4357 return RISCVAsmParser::Match_InvalidImmXLenLI;
4358 break;
4359 }
4360 case MCK_ImmXLenLI_Restricted: {
4361 DiagnosticPredicate DP(Operand.isImmXLenLI_Restricted());
4362 if (DP.isMatch())
4363 return MCTargetAsmParser::Match_Success;
4364 if (DP.isNearMatch())
4365 return RISCVAsmParser::Match_InvalidImmXLenLI_Restricted;
4366 break;
4367 }
4368 case MCK_SImm12Lsb00000: {
4369 DiagnosticPredicate DP(Operand.isSImm12Lsb00000());
4370 if (DP.isMatch())
4371 return MCTargetAsmParser::Match_Success;
4372 if (DP.isNearMatch())
4373 return RISCVAsmParser::Match_InvalidSImm12Lsb00000;
4374 break;
4375 }
4376 case MCK_Imm5Zibi: {
4377 DiagnosticPredicate DP(Operand.isImm5Zibi());
4378 if (DP.isMatch())
4379 return MCTargetAsmParser::Match_Success;
4380 if (DP.isNearMatch())
4381 return RISCVAsmParser::Match_InvalidImm5Zibi;
4382 break;
4383 }
4384 case MCK_VTypeI10: {
4385 DiagnosticPredicate DP(Operand.isVTypeI10());
4386 if (DP.isMatch())
4387 return MCTargetAsmParser::Match_Success;
4388 if (DP.isNearMatch())
4389 return RISCVAsmParser::Match_InvalidVTypeI;
4390 break;
4391 }
4392 case MCK_VTypeI11: {
4393 DiagnosticPredicate DP(Operand.isVTypeI11());
4394 if (DP.isMatch())
4395 return MCTargetAsmParser::Match_Success;
4396 if (DP.isNearMatch())
4397 return RISCVAsmParser::Match_InvalidVTypeI;
4398 break;
4399 }
4400 case MCK_SImm5: {
4401 DiagnosticPredicate DP(Operand.isSImm5());
4402 if (DP.isMatch())
4403 return MCTargetAsmParser::Match_Success;
4404 if (DP.isNearMatch())
4405 return RISCVAsmParser::Match_InvalidSImm5;
4406 break;
4407 }
4408 case MCK_SImm5Plus1: {
4409 DiagnosticPredicate DP(Operand.isSImm5Plus1());
4410 if (DP.isMatch())
4411 return MCTargetAsmParser::Match_Success;
4412 if (DP.isNearMatch())
4413 return RISCVAsmParser::Match_InvalidSImm5Plus1;
4414 break;
4415 }
4416 case MCK_SImm10: {
4417 DiagnosticPredicate DP(Operand.isSImm10());
4418 if (DP.isMatch())
4419 return MCTargetAsmParser::Match_Success;
4420 if (DP.isNearMatch())
4421 return RISCVAsmParser::Match_InvalidSImm10;
4422 break;
4423 }
4424 case MCK_SImm6: {
4425 DiagnosticPredicate DP(Operand.isSImm6());
4426 if (DP.isMatch())
4427 return MCTargetAsmParser::Match_Success;
4428 if (DP.isNearMatch())
4429 return RISCVAsmParser::Match_InvalidSImm6;
4430 break;
4431 }
4432 case MCK_SImm6NonZero: {
4433 DiagnosticPredicate DP(Operand.isSImm6NonZero());
4434 if (DP.isMatch())
4435 return MCTargetAsmParser::Match_Success;
4436 if (DP.isNearMatch())
4437 return RISCVAsmParser::Match_InvalidSImm6NonZero;
4438 break;
4439 }
4440 case MCK_UImm7Lsb00: {
4441 DiagnosticPredicate DP(Operand.isUImm7Lsb00());
4442 if (DP.isMatch())
4443 return MCTargetAsmParser::Match_Success;
4444 if (DP.isNearMatch())
4445 return RISCVAsmParser::Match_InvalidUImm7Lsb00;
4446 break;
4447 }
4448 case MCK_UImm8Lsb00: {
4449 DiagnosticPredicate DP(Operand.isUImm8Lsb00());
4450 if (DP.isMatch())
4451 return MCTargetAsmParser::Match_Success;
4452 if (DP.isNearMatch())
4453 return RISCVAsmParser::Match_InvalidUImm8Lsb00;
4454 break;
4455 }
4456 case MCK_UImm8Lsb000: {
4457 DiagnosticPredicate DP(Operand.isUImm8Lsb000());
4458 if (DP.isMatch())
4459 return MCTargetAsmParser::Match_Success;
4460 if (DP.isNearMatch())
4461 return RISCVAsmParser::Match_InvalidUImm8Lsb000;
4462 break;
4463 }
4464 case MCK_BareSImm9Lsb0: {
4465 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<9>());
4466 if (DP.isMatch())
4467 return MCTargetAsmParser::Match_Success;
4468 if (DP.isNearMatch())
4469 return RISCVAsmParser::Match_InvalidBareSImm9Lsb0;
4470 break;
4471 }
4472 case MCK_UImm9Lsb000: {
4473 DiagnosticPredicate DP(Operand.isUImm9Lsb000());
4474 if (DP.isMatch())
4475 return MCTargetAsmParser::Match_Success;
4476 if (DP.isNearMatch())
4477 return RISCVAsmParser::Match_InvalidUImm9Lsb000;
4478 break;
4479 }
4480 case MCK_UImm10Lsb00NonZero: {
4481 DiagnosticPredicate DP(Operand.isUImm10Lsb00NonZero());
4482 if (DP.isMatch())
4483 return MCTargetAsmParser::Match_Success;
4484 if (DP.isNearMatch())
4485 return RISCVAsmParser::Match_InvalidUImm10Lsb00NonZero;
4486 break;
4487 }
4488 case MCK_SImm10Lsb0000NonZero: {
4489 DiagnosticPredicate DP(Operand.isSImm10Lsb0000NonZero());
4490 if (DP.isMatch())
4491 return MCTargetAsmParser::Match_Success;
4492 if (DP.isNearMatch())
4493 return RISCVAsmParser::Match_InvalidSImm10Lsb0000NonZero;
4494 break;
4495 }
4496 case MCK_BareSImm12Lsb0: {
4497 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<12>());
4498 if (DP.isMatch())
4499 return MCTargetAsmParser::Match_Success;
4500 if (DP.isNearMatch())
4501 return RISCVAsmParser::Match_InvalidBareSImm12Lsb0;
4502 break;
4503 }
4504 case MCK_UImm2Lsb0: {
4505 DiagnosticPredicate DP(Operand.isUImm2Lsb0());
4506 if (DP.isMatch())
4507 return MCTargetAsmParser::Match_Success;
4508 if (DP.isNearMatch())
4509 return RISCVAsmParser::Match_InvalidUImm2Lsb0;
4510 break;
4511 }
4512 case MCK_UImm8GE32: {
4513 DiagnosticPredicate DP(Operand.isUImm8GE32());
4514 if (DP.isMatch())
4515 return MCTargetAsmParser::Match_Success;
4516 if (DP.isNearMatch())
4517 return RISCVAsmParser::Match_InvalidUImm8GE32;
4518 break;
4519 }
4520 case MCK_UImm5Lsb0: {
4521 DiagnosticPredicate DP(Operand.isUImm5Lsb0());
4522 if (DP.isMatch())
4523 return MCTargetAsmParser::Match_Success;
4524 if (DP.isNearMatch())
4525 return RISCVAsmParser::Match_InvalidUImm5Lsb0;
4526 break;
4527 }
4528 case MCK_UImm6Lsb0: {
4529 DiagnosticPredicate DP(Operand.isUImm6Lsb0());
4530 if (DP.isMatch())
4531 return MCTargetAsmParser::Match_Success;
4532 if (DP.isNearMatch())
4533 return RISCVAsmParser::Match_InvalidUImm6Lsb0;
4534 break;
4535 }
4536 case MCK_UImm5NonZero: {
4537 DiagnosticPredicate DP(Operand.isUImm5NonZero());
4538 if (DP.isMatch())
4539 return MCTargetAsmParser::Match_Success;
4540 if (DP.isNearMatch())
4541 return RISCVAsmParser::Match_InvalidUImm5NonZero;
4542 break;
4543 }
4544 case MCK_UImm5GT3: {
4545 DiagnosticPredicate DP(Operand.isUImm5GT3());
4546 if (DP.isMatch())
4547 return MCTargetAsmParser::Match_Success;
4548 if (DP.isNearMatch())
4549 return RISCVAsmParser::Match_InvalidUImm5GT3;
4550 break;
4551 }
4552 case MCK_UImm5GE6Plus1: {
4553 DiagnosticPredicate DP(Operand.isUImm5GE6Plus1());
4554 if (DP.isMatch())
4555 return MCTargetAsmParser::Match_Success;
4556 if (DP.isNearMatch())
4557 return RISCVAsmParser::Match_InvalidUImm5GE6Plus1;
4558 break;
4559 }
4560 case MCK_UImm5Slist: {
4561 DiagnosticPredicate DP(Operand.isUImm5Slist());
4562 if (DP.isMatch())
4563 return MCTargetAsmParser::Match_Success;
4564 if (DP.isNearMatch())
4565 return RISCVAsmParser::Match_InvalidUImm5Slist;
4566 break;
4567 }
4568 case MCK_UImm10: {
4569 DiagnosticPredicate DP(Operand.isUImm10());
4570 if (DP.isMatch())
4571 return MCTargetAsmParser::Match_Success;
4572 if (DP.isNearMatch())
4573 return RISCVAsmParser::Match_InvalidUImm10;
4574 break;
4575 }
4576 case MCK_UImm11: {
4577 DiagnosticPredicate DP(Operand.isUImm11());
4578 if (DP.isMatch())
4579 return MCTargetAsmParser::Match_Success;
4580 if (DP.isNearMatch())
4581 return RISCVAsmParser::Match_InvalidUImm11;
4582 break;
4583 }
4584 case MCK_UImm14Lsb00: {
4585 DiagnosticPredicate DP(Operand.isUImm14Lsb00());
4586 if (DP.isMatch())
4587 return MCTargetAsmParser::Match_Success;
4588 if (DP.isNearMatch())
4589 return RISCVAsmParser::Match_InvalidUImm14Lsb00;
4590 break;
4591 }
4592 case MCK_UImm16NonZero: {
4593 DiagnosticPredicate DP(Operand.isUImm16NonZero());
4594 if (DP.isMatch())
4595 return MCTargetAsmParser::Match_Success;
4596 if (DP.isNearMatch())
4597 return RISCVAsmParser::Match_InvalidUImm16NonZero;
4598 break;
4599 }
4600 case MCK_SImm5NonZero: {
4601 DiagnosticPredicate DP(Operand.isSImm5NonZero());
4602 if (DP.isMatch())
4603 return MCTargetAsmParser::Match_Success;
4604 if (DP.isNearMatch())
4605 return RISCVAsmParser::Match_InvalidSImm5NonZero;
4606 break;
4607 }
4608 case MCK_SImm11: {
4609 DiagnosticPredicate DP(Operand.isSImm11());
4610 if (DP.isMatch())
4611 return MCTargetAsmParser::Match_Success;
4612 if (DP.isNearMatch())
4613 return RISCVAsmParser::Match_InvalidSImm11;
4614 break;
4615 }
4616 case MCK_SImm16: {
4617 DiagnosticPredicate DP(Operand.isSImm16());
4618 if (DP.isMatch())
4619 return MCTargetAsmParser::Match_Success;
4620 if (DP.isNearMatch())
4621 return RISCVAsmParser::Match_InvalidSImm16;
4622 break;
4623 }
4624 case MCK_SImm16NonZero: {
4625 DiagnosticPredicate DP(Operand.isSImm16NonZero());
4626 if (DP.isMatch())
4627 return MCTargetAsmParser::Match_Success;
4628 if (DP.isNearMatch())
4629 return RISCVAsmParser::Match_InvalidSImm16NonZero;
4630 break;
4631 }
4632 case MCK_SImm20LI: {
4633 DiagnosticPredicate DP(Operand.isSImm20LI());
4634 if (DP.isMatch())
4635 return MCTargetAsmParser::Match_Success;
4636 if (DP.isNearMatch())
4637 return RISCVAsmParser::Match_InvalidSImm20LI;
4638 break;
4639 }
4640 case MCK_SImm26: {
4641 DiagnosticPredicate DP(Operand.isSImm26());
4642 if (DP.isMatch())
4643 return MCTargetAsmParser::Match_Success;
4644 if (DP.isNearMatch())
4645 return RISCVAsmParser::Match_InvalidSImm26;
4646 break;
4647 }
4648 case MCK_BareSImm32: {
4649 DiagnosticPredicate DP(Operand.isBareSimmN<32>());
4650 if (DP.isMatch())
4651 return MCTargetAsmParser::Match_Success;
4652 if (DP.isNearMatch())
4653 return RISCVAsmParser::Match_InvalidBareSImm32;
4654 break;
4655 }
4656 case MCK_BareSImm32Lsb0: {
4657 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<32>());
4658 if (DP.isMatch())
4659 return MCTargetAsmParser::Match_Success;
4660 if (DP.isNearMatch())
4661 return RISCVAsmParser::Match_InvalidBareSImm32Lsb0;
4662 break;
4663 }
4664 case MCK_UImm7Lsb000: {
4665 DiagnosticPredicate DP(Operand.isUImm7Lsb000());
4666 if (DP.isMatch())
4667 return MCTargetAsmParser::Match_Success;
4668 if (DP.isNearMatch())
4669 return RISCVAsmParser::Match_InvalidUImm7Lsb000;
4670 break;
4671 }
4672 case MCK_UImm9: {
4673 DiagnosticPredicate DP(Operand.isUImm9());
4674 if (DP.isMatch())
4675 return MCTargetAsmParser::Match_Success;
4676 if (DP.isNearMatch())
4677 return RISCVAsmParser::Match_InvalidUImm9;
4678 break;
4679 }
4680 case MCK_BareSImm11Lsb0: {
4681 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<11>());
4682 if (DP.isMatch())
4683 return MCTargetAsmParser::Match_Success;
4684 if (DP.isNearMatch())
4685 return RISCVAsmParser::Match_InvalidBareSImm11Lsb0;
4686 break;
4687 }
4688 case MCK_SImm18: {
4689 DiagnosticPredicate DP(Operand.isSImm18());
4690 if (DP.isMatch())
4691 return MCTargetAsmParser::Match_Success;
4692 if (DP.isNearMatch())
4693 return RISCVAsmParser::Match_InvalidSImm18;
4694 break;
4695 }
4696 case MCK_SImm18Lsb0: {
4697 DiagnosticPredicate DP(Operand.isSImm18Lsb0());
4698 if (DP.isMatch())
4699 return MCTargetAsmParser::Match_Success;
4700 if (DP.isNearMatch())
4701 return RISCVAsmParser::Match_InvalidSImm18Lsb0;
4702 break;
4703 }
4704 case MCK_SImm19Lsb00: {
4705 DiagnosticPredicate DP(Operand.isSImm19Lsb00());
4706 if (DP.isMatch())
4707 return MCTargetAsmParser::Match_Success;
4708 if (DP.isNearMatch())
4709 return RISCVAsmParser::Match_InvalidSImm19Lsb00;
4710 break;
4711 }
4712 case MCK_SImm20Lsb000: {
4713 DiagnosticPredicate DP(Operand.isSImm20Lsb000());
4714 if (DP.isMatch())
4715 return MCTargetAsmParser::Match_Success;
4716 if (DP.isNearMatch())
4717 return RISCVAsmParser::Match_InvalidSImm20Lsb000;
4718 break;
4719 }
4720 } // end switch (Kind)
4721
4722 if (Operand.isReg()) {
4723 static constexpr uint16_t Table[RISCV::NUM_TARGET_REGS] = {
4724 InvalidMatchClass,
4725 InvalidMatchClass,
4726 InvalidMatchClass,
4727 InvalidMatchClass,
4728 MCK_anonymous_15375,
4729 InvalidMatchClass,
4730 MCK_VCSR,
4731 MCK_VCSR,
4732 MCK_VCSR,
4733 InvalidMatchClass,
4734 InvalidMatchClass,
4735 MCK_GPRAll,
4736 MCK_MR0,
4737 MCK_MR,
4738 MCK_MR,
4739 MCK_MR,
4740 MCK_MR,
4741 MCK_MR,
4742 MCK_MR,
4743 MCK_MR,
4744 MCK_TRM4,
4745 MCK_TR,
4746 MCK_TRM2,
4747 MCK_TR,
4748 MCK_TRM4,
4749 MCK_TR,
4750 MCK_TRM2,
4751 MCK_TR,
4752 MCK_TRM4,
4753 MCK_TR,
4754 MCK_TRM2,
4755 MCK_TR,
4756 MCK_TRM4,
4757 MCK_TR,
4758 MCK_TRM2,
4759 MCK_TR,
4760 MCK_VMV0,
4761 MCK_VRNoV0,
4762 MCK_VRNoV0,
4763 MCK_VRNoV0,
4764 MCK_VRNoV0,
4765 MCK_VRNoV0,
4766 MCK_VRNoV0,
4767 MCK_VRNoV0,
4768 MCK_VRNoV0,
4769 MCK_VRNoV0,
4770 MCK_VRNoV0,
4771 MCK_VRNoV0,
4772 MCK_VRNoV0,
4773 MCK_VRNoV0,
4774 MCK_VRNoV0,
4775 MCK_VRNoV0,
4776 MCK_VRNoV0,
4777 MCK_VRNoV0,
4778 MCK_VRNoV0,
4779 MCK_VRNoV0,
4780 MCK_VRNoV0,
4781 MCK_VRNoV0,
4782 MCK_VRNoV0,
4783 MCK_VRNoV0,
4784 MCK_VRNoV0,
4785 MCK_VRNoV0,
4786 MCK_VRNoV0,
4787 MCK_VRNoV0,
4788 MCK_VRNoV0,
4789 MCK_VRNoV0,
4790 MCK_VRNoV0,
4791 MCK_VRNoV0,
4792 MCK_GPRX0,
4793 MCK_GPRX1,
4794 MCK_SP,
4795 MCK_Reg15,
4796 MCK_Reg15,
4797 MCK_GPRX5,
4798 MCK_Reg26,
4799 MCK_GPRX7,
4800 MCK_Reg29,
4801 MCK_Reg29,
4802 MCK_Reg32,
4803 MCK_Reg32,
4804 MCK_Reg32,
4805 MCK_Reg32,
4806 MCK_Reg32,
4807 MCK_Reg32,
4808 MCK_Reg26,
4809 MCK_Reg26,
4810 MCK_SR07,
4811 MCK_SR07,
4812 MCK_SR07,
4813 MCK_SR07,
4814 MCK_SR07,
4815 MCK_SR07,
4816 MCK_Reg24,
4817 MCK_Reg24,
4818 MCK_Reg24,
4819 MCK_Reg24,
4820 MCK_Reg26,
4821 MCK_Reg26,
4822 MCK_Reg26,
4823 MCK_GPRTCNonX7,
4824 MCK_FPR64,
4825 MCK_FPR64,
4826 MCK_FPR64,
4827 MCK_FPR64,
4828 MCK_FPR64,
4829 MCK_FPR64,
4830 MCK_FPR64,
4831 MCK_FPR64,
4832 MCK_FPR64C,
4833 MCK_FPR64C,
4834 MCK_FPR64C,
4835 MCK_FPR64C,
4836 MCK_FPR64C,
4837 MCK_FPR64C,
4838 MCK_FPR64C,
4839 MCK_FPR64C,
4840 MCK_FPR64,
4841 MCK_FPR64,
4842 MCK_FPR64,
4843 MCK_FPR64,
4844 MCK_FPR64,
4845 MCK_FPR64,
4846 MCK_FPR64,
4847 MCK_FPR64,
4848 MCK_FPR64,
4849 MCK_FPR64,
4850 MCK_FPR64,
4851 MCK_FPR64,
4852 MCK_FPR64,
4853 MCK_FPR64,
4854 MCK_FPR64,
4855 MCK_FPR64,
4856 MCK_FPR32,
4857 MCK_FPR32,
4858 MCK_FPR32,
4859 MCK_FPR32,
4860 MCK_FPR32,
4861 MCK_FPR32,
4862 MCK_FPR32,
4863 MCK_FPR32,
4864 MCK_FPR32C,
4865 MCK_FPR32C,
4866 MCK_FPR32C,
4867 MCK_FPR32C,
4868 MCK_FPR32C,
4869 MCK_FPR32C,
4870 MCK_FPR32C,
4871 MCK_FPR32C,
4872 MCK_FPR32,
4873 MCK_FPR32,
4874 MCK_FPR32,
4875 MCK_FPR32,
4876 MCK_FPR32,
4877 MCK_FPR32,
4878 MCK_FPR32,
4879 MCK_FPR32,
4880 MCK_FPR32,
4881 MCK_FPR32,
4882 MCK_FPR32,
4883 MCK_FPR32,
4884 MCK_FPR32,
4885 MCK_FPR32,
4886 MCK_FPR32,
4887 MCK_FPR32,
4888 MCK_FPR16,
4889 MCK_FPR16,
4890 MCK_FPR16,
4891 MCK_FPR16,
4892 MCK_FPR16,
4893 MCK_FPR16,
4894 MCK_FPR16,
4895 MCK_FPR16,
4896 MCK_FPR16C,
4897 MCK_FPR16C,
4898 MCK_FPR16C,
4899 MCK_FPR16C,
4900 MCK_FPR16C,
4901 MCK_FPR16C,
4902 MCK_FPR16C,
4903 MCK_FPR16C,
4904 MCK_FPR16,
4905 MCK_FPR16,
4906 MCK_FPR16,
4907 MCK_FPR16,
4908 MCK_FPR16,
4909 MCK_FPR16,
4910 MCK_FPR16,
4911 MCK_FPR16,
4912 MCK_FPR16,
4913 MCK_FPR16,
4914 MCK_FPR16,
4915 MCK_FPR16,
4916 MCK_FPR16,
4917 MCK_FPR16,
4918 MCK_FPR16,
4919 MCK_FPR16,
4920 MCK_FPR128,
4921 MCK_FPR128,
4922 MCK_FPR128,
4923 MCK_FPR128,
4924 MCK_FPR128,
4925 MCK_FPR128,
4926 MCK_FPR128,
4927 MCK_FPR128,
4928 MCK_Reg88,
4929 MCK_Reg88,
4930 MCK_Reg88,
4931 MCK_Reg88,
4932 MCK_Reg88,
4933 MCK_Reg88,
4934 MCK_Reg88,
4935 MCK_Reg88,
4936 MCK_FPR128,
4937 MCK_FPR128,
4938 MCK_FPR128,
4939 MCK_FPR128,
4940 MCK_FPR128,
4941 MCK_FPR128,
4942 MCK_FPR128,
4943 MCK_FPR128,
4944 MCK_FPR128,
4945 MCK_FPR128,
4946 MCK_FPR128,
4947 MCK_FPR128,
4948 MCK_FPR128,
4949 MCK_FPR128,
4950 MCK_FPR128,
4951 MCK_FPR128,
4952 MCK_GPRF16,
4953 MCK_GPRF16NoX0,
4954 MCK_GPRF16NoX0,
4955 MCK_GPRF16NoX0,
4956 MCK_GPRF16NoX0,
4957 MCK_GPRF16NoX0,
4958 MCK_GPRF16NoX0,
4959 MCK_GPRF16NoX0,
4960 MCK_GPRF16C,
4961 MCK_GPRF16C,
4962 MCK_GPRF16C,
4963 MCK_GPRF16C,
4964 MCK_GPRF16C,
4965 MCK_GPRF16C,
4966 MCK_GPRF16C,
4967 MCK_GPRF16C,
4968 MCK_GPRF16NoX0,
4969 MCK_GPRF16NoX0,
4970 MCK_GPRF16NoX0,
4971 MCK_GPRF16NoX0,
4972 MCK_GPRF16NoX0,
4973 MCK_GPRF16NoX0,
4974 MCK_GPRF16NoX0,
4975 MCK_GPRF16NoX0,
4976 MCK_GPRF16NoX0,
4977 MCK_GPRF16NoX0,
4978 MCK_GPRF16NoX0,
4979 MCK_GPRF16NoX0,
4980 MCK_GPRF16NoX0,
4981 MCK_GPRF16NoX0,
4982 MCK_GPRF16NoX0,
4983 MCK_GPRF16NoX0,
4984 MCK_Reg59,
4985 MCK_GPRF32,
4986 MCK_GPRF32NoX0,
4987 MCK_GPRF32NoX0,
4988 MCK_GPRF32NoX0,
4989 MCK_GPRF32NoX0,
4990 MCK_GPRF32NoX0,
4991 MCK_GPRF32NoX0,
4992 MCK_GPRF32NoX0,
4993 MCK_GPRF32C,
4994 MCK_GPRF32C,
4995 MCK_GPRF32C,
4996 MCK_GPRF32C,
4997 MCK_GPRF32C,
4998 MCK_GPRF32C,
4999 MCK_GPRF32C,
5000 MCK_GPRF32C,
5001 MCK_GPRF32NoX0,
5002 MCK_GPRF32NoX0,
5003 MCK_GPRF32NoX0,
5004 MCK_GPRF32NoX0,
5005 MCK_GPRF32NoX0,
5006 MCK_GPRF32NoX0,
5007 MCK_GPRF32NoX0,
5008 MCK_GPRF32NoX0,
5009 MCK_GPRF32NoX0,
5010 MCK_GPRF32NoX0,
5011 MCK_GPRF32NoX0,
5012 MCK_GPRF32NoX0,
5013 MCK_GPRF32NoX0,
5014 MCK_GPRF32NoX0,
5015 MCK_GPRF32NoX0,
5016 MCK_GPRF32NoX0,
5017 MCK_Reg33,
5018 MCK_Reg38,
5019 MCK_Reg44,
5020 MCK_Reg41,
5021 MCK_Reg41,
5022 MCK_Reg45,
5023 MCK_Reg52,
5024 MCK_Reg54,
5025 MCK_Reg55,
5026 MCK_Reg55,
5027 MCK_Reg58,
5028 MCK_Reg58,
5029 MCK_Reg58,
5030 MCK_Reg58,
5031 MCK_Reg58,
5032 MCK_Reg58,
5033 MCK_Reg52,
5034 MCK_Reg52,
5035 MCK_Reg57,
5036 MCK_Reg57,
5037 MCK_Reg57,
5038 MCK_Reg57,
5039 MCK_Reg57,
5040 MCK_Reg57,
5041 MCK_Reg50,
5042 MCK_Reg50,
5043 MCK_Reg50,
5044 MCK_Reg50,
5045 MCK_Reg52,
5046 MCK_Reg52,
5047 MCK_Reg52,
5048 MCK_Reg53,
5049 MCK_FPR256,
5050 MCK_FPR256,
5051 MCK_FPR256,
5052 MCK_FPR256,
5053 MCK_FPR256,
5054 MCK_FPR256,
5055 MCK_FPR256,
5056 MCK_FPR256,
5057 MCK_Reg107,
5058 MCK_Reg107,
5059 MCK_Reg107,
5060 MCK_Reg107,
5061 MCK_Reg107,
5062 MCK_Reg107,
5063 MCK_Reg107,
5064 MCK_Reg107,
5065 MCK_FPR256,
5066 MCK_FPR256,
5067 MCK_FPR256,
5068 MCK_FPR256,
5069 MCK_FPR256,
5070 MCK_FPR256,
5071 MCK_FPR256,
5072 MCK_FPR256,
5073 MCK_FPR256,
5074 MCK_FPR256,
5075 MCK_FPR256,
5076 MCK_FPR256,
5077 MCK_FPR256,
5078 MCK_FPR256,
5079 MCK_FPR256,
5080 MCK_FPR256,
5081 MCK_Reg92,
5082 MCK_Reg95,
5083 MCK_Reg98,
5084 MCK_VRM2NoV0,
5085 MCK_VRM2NoV0,
5086 MCK_VRM4NoV0,
5087 MCK_VRM2NoV0,
5088 MCK_VRM2NoV0,
5089 MCK_VRM4NoV0,
5090 MCK_VRM8NoV0,
5091 MCK_VRM2NoV0,
5092 MCK_VRM2NoV0,
5093 MCK_VRM4NoV0,
5094 MCK_VRM2NoV0,
5095 MCK_VRM2NoV0,
5096 MCK_VRM4NoV0,
5097 MCK_VRM8NoV0,
5098 MCK_VRM2NoV0,
5099 MCK_VRM2NoV0,
5100 MCK_VRM4NoV0,
5101 MCK_VRM2NoV0,
5102 MCK_VRM2NoV0,
5103 MCK_VRM4NoV0,
5104 MCK_VRM8NoV0,
5105 MCK_VRM2NoV0,
5106 MCK_VRM2NoV0,
5107 MCK_VRM4NoV0,
5108 MCK_VRM2NoV0,
5109 MCK_Reg62,
5110 MCK_Reg65,
5111 MCK_Reg68,
5112 MCK_Reg73,
5113 MCK_Reg78,
5114 MCK_Reg78,
5115 MCK_Reg78,
5116 MCK_Reg79,
5117 MCK_Reg77,
5118 MCK_Reg77,
5119 MCK_Reg77,
5120 MCK_Reg75,
5121 MCK_Reg75,
5122 MCK_Reg79,
5123 MCK_Reg80,
5124 MCK_VRN2M1NoV0,
5125 MCK_VRN2M1NoV0,
5126 MCK_VRN2M1NoV0,
5127 MCK_VRN2M1NoV0,
5128 MCK_VRN2M1NoV0,
5129 MCK_VRN2M1NoV0,
5130 MCK_VRN2M1NoV0,
5131 MCK_VRN2M1NoV0,
5132 MCK_VRN2M1NoV0,
5133 MCK_VRN2M1NoV0,
5134 MCK_VRN2M1NoV0,
5135 MCK_VRN2M1NoV0,
5136 MCK_VRN2M1NoV0,
5137 MCK_VRN2M1NoV0,
5138 MCK_VRN2M1NoV0,
5139 MCK_VRN2M1NoV0,
5140 MCK_VRN2M1NoV0,
5141 MCK_VRN2M1NoV0,
5142 MCK_VRN2M1NoV0,
5143 MCK_VRN2M1NoV0,
5144 MCK_VRN2M1NoV0,
5145 MCK_VRN2M1NoV0,
5146 MCK_VRN2M1NoV0,
5147 MCK_VRN2M1NoV0,
5148 MCK_VRN2M1NoV0,
5149 MCK_VRN2M1NoV0,
5150 MCK_VRN2M1NoV0,
5151 MCK_VRN2M1NoV0,
5152 MCK_VRN2M1NoV0,
5153 MCK_VRN2M1NoV0,
5154 MCK_Reg112,
5155 MCK_VRN2M2NoV0,
5156 MCK_VRN2M2NoV0,
5157 MCK_VRN2M2NoV0,
5158 MCK_VRN2M2NoV0,
5159 MCK_VRN2M2NoV0,
5160 MCK_VRN2M2NoV0,
5161 MCK_VRN2M2NoV0,
5162 MCK_VRN2M2NoV0,
5163 MCK_VRN2M2NoV0,
5164 MCK_VRN2M2NoV0,
5165 MCK_VRN2M2NoV0,
5166 MCK_VRN2M2NoV0,
5167 MCK_VRN2M2NoV0,
5168 MCK_VRN2M2NoV0,
5169 MCK_Reg115,
5170 MCK_VRN2M4NoV0,
5171 MCK_VRN2M4NoV0,
5172 MCK_VRN2M4NoV0,
5173 MCK_VRN2M4NoV0,
5174 MCK_VRN2M4NoV0,
5175 MCK_VRN2M4NoV0,
5176 MCK_Reg118,
5177 MCK_VRN3M1NoV0,
5178 MCK_VRN3M1NoV0,
5179 MCK_VRN3M1NoV0,
5180 MCK_VRN3M1NoV0,
5181 MCK_VRN3M1NoV0,
5182 MCK_VRN3M1NoV0,
5183 MCK_VRN3M1NoV0,
5184 MCK_VRN3M1NoV0,
5185 MCK_VRN3M1NoV0,
5186 MCK_VRN3M1NoV0,
5187 MCK_VRN3M1NoV0,
5188 MCK_VRN3M1NoV0,
5189 MCK_VRN3M1NoV0,
5190 MCK_VRN3M1NoV0,
5191 MCK_VRN3M1NoV0,
5192 MCK_VRN3M1NoV0,
5193 MCK_VRN3M1NoV0,
5194 MCK_VRN3M1NoV0,
5195 MCK_VRN3M1NoV0,
5196 MCK_VRN3M1NoV0,
5197 MCK_VRN3M1NoV0,
5198 MCK_VRN3M1NoV0,
5199 MCK_VRN3M1NoV0,
5200 MCK_VRN3M1NoV0,
5201 MCK_VRN3M1NoV0,
5202 MCK_VRN3M1NoV0,
5203 MCK_VRN3M1NoV0,
5204 MCK_VRN3M1NoV0,
5205 MCK_VRN3M1NoV0,
5206 MCK_Reg121,
5207 MCK_VRN3M2NoV0,
5208 MCK_VRN3M2NoV0,
5209 MCK_VRN3M2NoV0,
5210 MCK_VRN3M2NoV0,
5211 MCK_VRN3M2NoV0,
5212 MCK_VRN3M2NoV0,
5213 MCK_VRN3M2NoV0,
5214 MCK_VRN3M2NoV0,
5215 MCK_VRN3M2NoV0,
5216 MCK_VRN3M2NoV0,
5217 MCK_VRN3M2NoV0,
5218 MCK_VRN3M2NoV0,
5219 MCK_VRN3M2NoV0,
5220 MCK_Reg124,
5221 MCK_VRN4M1NoV0,
5222 MCK_VRN4M1NoV0,
5223 MCK_VRN4M1NoV0,
5224 MCK_VRN4M1NoV0,
5225 MCK_VRN4M1NoV0,
5226 MCK_VRN4M1NoV0,
5227 MCK_VRN4M1NoV0,
5228 MCK_VRN4M1NoV0,
5229 MCK_VRN4M1NoV0,
5230 MCK_VRN4M1NoV0,
5231 MCK_VRN4M1NoV0,
5232 MCK_VRN4M1NoV0,
5233 MCK_VRN4M1NoV0,
5234 MCK_VRN4M1NoV0,
5235 MCK_VRN4M1NoV0,
5236 MCK_VRN4M1NoV0,
5237 MCK_VRN4M1NoV0,
5238 MCK_VRN4M1NoV0,
5239 MCK_VRN4M1NoV0,
5240 MCK_VRN4M1NoV0,
5241 MCK_VRN4M1NoV0,
5242 MCK_VRN4M1NoV0,
5243 MCK_VRN4M1NoV0,
5244 MCK_VRN4M1NoV0,
5245 MCK_VRN4M1NoV0,
5246 MCK_VRN4M1NoV0,
5247 MCK_VRN4M1NoV0,
5248 MCK_VRN4M1NoV0,
5249 MCK_Reg127,
5250 MCK_VRN4M2NoV0,
5251 MCK_VRN4M2NoV0,
5252 MCK_VRN4M2NoV0,
5253 MCK_VRN4M2NoV0,
5254 MCK_VRN4M2NoV0,
5255 MCK_VRN4M2NoV0,
5256 MCK_VRN4M2NoV0,
5257 MCK_VRN4M2NoV0,
5258 MCK_VRN4M2NoV0,
5259 MCK_VRN4M2NoV0,
5260 MCK_VRN4M2NoV0,
5261 MCK_VRN4M2NoV0,
5262 MCK_Reg130,
5263 MCK_VRN5M1NoV0,
5264 MCK_VRN5M1NoV0,
5265 MCK_VRN5M1NoV0,
5266 MCK_VRN5M1NoV0,
5267 MCK_VRN5M1NoV0,
5268 MCK_VRN5M1NoV0,
5269 MCK_VRN5M1NoV0,
5270 MCK_VRN5M1NoV0,
5271 MCK_VRN5M1NoV0,
5272 MCK_VRN5M1NoV0,
5273 MCK_VRN5M1NoV0,
5274 MCK_VRN5M1NoV0,
5275 MCK_VRN5M1NoV0,
5276 MCK_VRN5M1NoV0,
5277 MCK_VRN5M1NoV0,
5278 MCK_VRN5M1NoV0,
5279 MCK_VRN5M1NoV0,
5280 MCK_VRN5M1NoV0,
5281 MCK_VRN5M1NoV0,
5282 MCK_VRN5M1NoV0,
5283 MCK_VRN5M1NoV0,
5284 MCK_VRN5M1NoV0,
5285 MCK_VRN5M1NoV0,
5286 MCK_VRN5M1NoV0,
5287 MCK_VRN5M1NoV0,
5288 MCK_VRN5M1NoV0,
5289 MCK_VRN5M1NoV0,
5290 MCK_Reg133,
5291 MCK_VRN6M1NoV0,
5292 MCK_VRN6M1NoV0,
5293 MCK_VRN6M1NoV0,
5294 MCK_VRN6M1NoV0,
5295 MCK_VRN6M1NoV0,
5296 MCK_VRN6M1NoV0,
5297 MCK_VRN6M1NoV0,
5298 MCK_VRN6M1NoV0,
5299 MCK_VRN6M1NoV0,
5300 MCK_VRN6M1NoV0,
5301 MCK_VRN6M1NoV0,
5302 MCK_VRN6M1NoV0,
5303 MCK_VRN6M1NoV0,
5304 MCK_VRN6M1NoV0,
5305 MCK_VRN6M1NoV0,
5306 MCK_VRN6M1NoV0,
5307 MCK_VRN6M1NoV0,
5308 MCK_VRN6M1NoV0,
5309 MCK_VRN6M1NoV0,
5310 MCK_VRN6M1NoV0,
5311 MCK_VRN6M1NoV0,
5312 MCK_VRN6M1NoV0,
5313 MCK_VRN6M1NoV0,
5314 MCK_VRN6M1NoV0,
5315 MCK_VRN6M1NoV0,
5316 MCK_VRN6M1NoV0,
5317 MCK_Reg136,
5318 MCK_VRN7M1NoV0,
5319 MCK_VRN7M1NoV0,
5320 MCK_VRN7M1NoV0,
5321 MCK_VRN7M1NoV0,
5322 MCK_VRN7M1NoV0,
5323 MCK_VRN7M1NoV0,
5324 MCK_VRN7M1NoV0,
5325 MCK_VRN7M1NoV0,
5326 MCK_VRN7M1NoV0,
5327 MCK_VRN7M1NoV0,
5328 MCK_VRN7M1NoV0,
5329 MCK_VRN7M1NoV0,
5330 MCK_VRN7M1NoV0,
5331 MCK_VRN7M1NoV0,
5332 MCK_VRN7M1NoV0,
5333 MCK_VRN7M1NoV0,
5334 MCK_VRN7M1NoV0,
5335 MCK_VRN7M1NoV0,
5336 MCK_VRN7M1NoV0,
5337 MCK_VRN7M1NoV0,
5338 MCK_VRN7M1NoV0,
5339 MCK_VRN7M1NoV0,
5340 MCK_VRN7M1NoV0,
5341 MCK_VRN7M1NoV0,
5342 MCK_VRN7M1NoV0,
5343 MCK_Reg139,
5344 MCK_VRN8M1NoV0,
5345 MCK_VRN8M1NoV0,
5346 MCK_VRN8M1NoV0,
5347 MCK_VRN8M1NoV0,
5348 MCK_VRN8M1NoV0,
5349 MCK_VRN8M1NoV0,
5350 MCK_VRN8M1NoV0,
5351 MCK_VRN8M1NoV0,
5352 MCK_VRN8M1NoV0,
5353 MCK_VRN8M1NoV0,
5354 MCK_VRN8M1NoV0,
5355 MCK_VRN8M1NoV0,
5356 MCK_VRN8M1NoV0,
5357 MCK_VRN8M1NoV0,
5358 MCK_VRN8M1NoV0,
5359 MCK_VRN8M1NoV0,
5360 MCK_VRN8M1NoV0,
5361 MCK_VRN8M1NoV0,
5362 MCK_VRN8M1NoV0,
5363 MCK_VRN8M1NoV0,
5364 MCK_VRN8M1NoV0,
5365 MCK_VRN8M1NoV0,
5366 MCK_VRN8M1NoV0,
5367 MCK_VRN8M1NoV0,
5368 MCK_Reg142,
5369 };
5370
5371 MCRegister Reg = Operand.getReg();
5372 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
5373 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
5374 getDiagKindFromRegisterClass(Kind);
5375 }
5376
5377 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
5378 return getDiagKindFromRegisterClass(Kind);
5379
5380 return MCTargetAsmParser::Match_InvalidOperand;
5381}
5382
5383#ifndef NDEBUG
5384const char *getMatchClassName(MatchClassKind Kind) {
5385 switch (Kind) {
5386 case InvalidMatchClass: return "InvalidMatchClass";
5387 case OptionalMatchClass: return "OptionalMatchClass";
5388 case MCK__40_: return "MCK__40_";
5389 case MCK__41_: return "MCK__41_";
5390 case MCK_Reg142: return "MCK_Reg142";
5391 case MCK_Reg139: return "MCK_Reg139";
5392 case MCK_Reg136: return "MCK_Reg136";
5393 case MCK_Reg133: return "MCK_Reg133";
5394 case MCK_Reg130: return "MCK_Reg130";
5395 case MCK_Reg127: return "MCK_Reg127";
5396 case MCK_Reg124: return "MCK_Reg124";
5397 case MCK_Reg121: return "MCK_Reg121";
5398 case MCK_Reg118: return "MCK_Reg118";
5399 case MCK_Reg115: return "MCK_Reg115";
5400 case MCK_Reg112: return "MCK_Reg112";
5401 case MCK_Reg98: return "MCK_Reg98";
5402 case MCK_Reg95: return "MCK_Reg95";
5403 case MCK_Reg92: return "MCK_Reg92";
5404 case MCK_Reg73: return "MCK_Reg73";
5405 case MCK_Reg68: return "MCK_Reg68";
5406 case MCK_Reg65: return "MCK_Reg65";
5407 case MCK_Reg62: return "MCK_Reg62";
5408 case MCK_Reg59: return "MCK_Reg59";
5409 case MCK_Reg54: return "MCK_Reg54";
5410 case MCK_Reg45: return "MCK_Reg45";
5411 case MCK_Reg44: return "MCK_Reg44";
5412 case MCK_Reg38: return "MCK_Reg38";
5413 case MCK_Reg33: return "MCK_Reg33";
5414 case MCK_GPRX0: return "MCK_GPRX0";
5415 case MCK_GPRX1: return "MCK_GPRX1";
5416 case MCK_GPRX5: return "MCK_GPRX5";
5417 case MCK_GPRX7: return "MCK_GPRX7";
5418 case MCK_MR0: return "MCK_MR0";
5419 case MCK_SP: return "MCK_SP";
5420 case MCK_VMV0: return "MCK_VMV0";
5421 case MCK_anonymous_15375: return "MCK_anonymous_15375";
5422 case MCK_Reg55: return "MCK_Reg55";
5423 case MCK_Reg43: return "MCK_Reg43";
5424 case MCK_Reg29: return "MCK_Reg29";
5425 case MCK_GPRX1X5: return "MCK_GPRX1X5";
5426 case MCK_Reg78: return "MCK_Reg78";
5427 case MCK_VCSR: return "MCK_VCSR";
5428 case MCK_VRM8NoV0: return "MCK_VRM8NoV0";
5429 case MCK_Reg77: return "MCK_Reg77";
5430 case MCK_GPRPairC: return "MCK_GPRPairC";
5431 case MCK_TRM4: return "MCK_TRM4";
5432 case MCK_VRM8: return "MCK_VRM8";
5433 case MCK_Reg79: return "MCK_Reg79";
5434 case MCK_Reg80: return "MCK_Reg80";
5435 case MCK_Reg71: return "MCK_Reg71";
5436 case MCK_Reg58: return "MCK_Reg58";
5437 case MCK_Reg32: return "MCK_Reg32";
5438 case MCK_VRN2M4NoV0: return "MCK_VRN2M4NoV0";
5439 case MCK_Reg72: return "MCK_Reg72";
5440 case MCK_VRM4NoV0: return "MCK_VRM4NoV0";
5441 case MCK_VRN2M4: return "MCK_VRN2M4";
5442 case MCK_Reg107: return "MCK_Reg107";
5443 case MCK_Reg88: return "MCK_Reg88";
5444 case MCK_Reg57: return "MCK_Reg57";
5445 case MCK_Reg56: return "MCK_Reg56";
5446 case MCK_FPR16C: return "MCK_FPR16C";
5447 case MCK_FPR32C: return "MCK_FPR32C";
5448 case MCK_FPR64C: return "MCK_FPR64C";
5449 case MCK_GPRC: return "MCK_GPRC";
5450 case MCK_GPRF16C: return "MCK_GPRF16C";
5451 case MCK_GPRF32C: return "MCK_GPRF32C";
5452 case MCK_MR: return "MCK_MR";
5453 case MCK_SR07: return "MCK_SR07";
5454 case MCK_TRM2: return "MCK_TRM2";
5455 case MCK_VRM4: return "MCK_VRM4";
5456 case MCK_Reg75: return "MCK_Reg75";
5457 case MCK_Reg76: return "MCK_Reg76";
5458 case MCK_Reg69: return "MCK_Reg69";
5459 case MCK_Reg52: return "MCK_Reg52";
5460 case MCK_Reg26: return "MCK_Reg26";
5461 case MCK_VRN4M2NoV0: return "MCK_VRN4M2NoV0";
5462 case MCK_Reg70: return "MCK_Reg70";
5463 case MCK_Reg66: return "MCK_Reg66";
5464 case MCK_Reg53: return "MCK_Reg53";
5465 case MCK_Reg48: return "MCK_Reg48";
5466 case MCK_Reg22: return "MCK_Reg22";
5467 case MCK_GPRTCNonX7: return "MCK_GPRTCNonX7";
5468 case MCK_VRN3M2NoV0: return "MCK_VRN3M2NoV0";
5469 case MCK_VRN4M2: return "MCK_VRN4M2";
5470 case MCK_Reg67: return "MCK_Reg67";
5471 case MCK_Reg63: return "MCK_Reg63";
5472 case MCK_Reg49: return "MCK_Reg49";
5473 case MCK_GPRTC: return "MCK_GPRTC";
5474 case MCK_VRN2M2NoV0: return "MCK_VRN2M2NoV0";
5475 case MCK_VRN3M2: return "MCK_VRN3M2";
5476 case MCK_Reg61: return "MCK_Reg61";
5477 case MCK_GPRPairNoX0: return "MCK_GPRPairNoX0";
5478 case MCK_VRM2NoV0: return "MCK_VRM2NoV0";
5479 case MCK_VRN2M2: return "MCK_VRN2M2";
5480 case MCK_GPRPair: return "MCK_GPRPair";
5481 case MCK_TR: return "MCK_TR";
5482 case MCK_VRM2: return "MCK_VRM2";
5483 case MCK_Reg50: return "MCK_Reg50";
5484 case MCK_Reg24: return "MCK_Reg24";
5485 case MCK_VRN8M1NoV0: return "MCK_VRN8M1NoV0";
5486 case MCK_Reg51: return "MCK_Reg51";
5487 case MCK_Reg46: return "MCK_Reg46";
5488 case MCK_Reg20: return "MCK_Reg20";
5489 case MCK_GPRJALRNonX7: return "MCK_GPRJALRNonX7";
5490 case MCK_VRN7M1NoV0: return "MCK_VRN7M1NoV0";
5491 case MCK_VRN8M1: return "MCK_VRN8M1";
5492 case MCK_Reg47: return "MCK_Reg47";
5493 case MCK_GPRJALR: return "MCK_GPRJALR";
5494 case MCK_VRN6M1NoV0: return "MCK_VRN6M1NoV0";
5495 case MCK_VRN7M1: return "MCK_VRN7M1";
5496 case MCK_VRN5M1NoV0: return "MCK_VRN5M1NoV0";
5497 case MCK_VRN6M1: return "MCK_VRN6M1";
5498 case MCK_VRN4M1NoV0: return "MCK_VRN4M1NoV0";
5499 case MCK_VRN5M1: return "MCK_VRN5M1";
5500 case MCK_Reg41: return "MCK_Reg41";
5501 case MCK_Reg15: return "MCK_Reg15";
5502 case MCK_VRN3M1NoV0: return "MCK_VRN3M1NoV0";
5503 case MCK_VRN4M1: return "MCK_VRN4M1";
5504 case MCK_Reg42: return "MCK_Reg42";
5505 case MCK_Reg39: return "MCK_Reg39";
5506 case MCK_Reg36: return "MCK_Reg36";
5507 case MCK_Reg13: return "MCK_Reg13";
5508 case MCK_Reg10: return "MCK_Reg10";
5509 case MCK_GPRNoX0X2: return "MCK_GPRNoX0X2";
5510 case MCK_VRN2M1NoV0: return "MCK_VRN2M1NoV0";
5511 case MCK_VRN3M1: return "MCK_VRN3M1";
5512 case MCK_Reg40: return "MCK_Reg40";
5513 case MCK_Reg37: return "MCK_Reg37";
5514 case MCK_Reg34: return "MCK_Reg34";
5515 case MCK_GPRF16NoX0: return "MCK_GPRF16NoX0";
5516 case MCK_GPRF32NoX0: return "MCK_GPRF32NoX0";
5517 case MCK_GPRNoX0: return "MCK_GPRNoX0";
5518 case MCK_GPRNoX2: return "MCK_GPRNoX2";
5519 case MCK_GPRNoX31: return "MCK_GPRNoX31";
5520 case MCK_VRN2M1: return "MCK_VRN2M1";
5521 case MCK_VRNoV0: return "MCK_VRNoV0";
5522 case MCK_FPR128: return "MCK_FPR128";
5523 case MCK_FPR16: return "MCK_FPR16";
5524 case MCK_FPR256: return "MCK_FPR256";
5525 case MCK_FPR32: return "MCK_FPR32";
5526 case MCK_FPR64: return "MCK_FPR64";
5527 case MCK_GPR: return "MCK_GPR";
5528 case MCK_GPRF16: return "MCK_GPRF16";
5529 case MCK_GPRF32: return "MCK_GPRF32";
5530 case MCK_VR: return "MCK_VR";
5531 case MCK_YGPR: return "MCK_YGPR";
5532 case MCK_GPRAll: return "MCK_GPRAll";
5533 case MCK_AnyRegCOperand: return "MCK_AnyRegCOperand";
5534 case MCK_AnyRegOperand: return "MCK_AnyRegOperand";
5535 case MCK_BareSymbol: return "MCK_BareSymbol";
5536 case MCK_BareSymbolQC_E_LI: return "MCK_BareSymbolQC_E_LI";
5537 case MCK_CLUIImm: return "MCK_CLUIImm";
5538 case MCK_CSRSystemRegister: return "MCK_CSRSystemRegister";
5539 case MCK_RegReg: return "MCK_RegReg";
5540 case MCK_CallSymbol: return "MCK_CallSymbol";
5541 case MCK_FRMArg: return "MCK_FRMArg";
5542 case MCK_FRMArgLegacy: return "MCK_FRMArgLegacy";
5543 case MCK_FenceArg: return "MCK_FenceArg";
5544 case MCK_GPRAsFPR16: return "MCK_GPRAsFPR16";
5545 case MCK_GPRAsFPR32: return "MCK_GPRAsFPR32";
5546 case MCK_GPRF64AsFPR: return "MCK_GPRF64AsFPR";
5547 case MCK_GPRPairAsFPR: return "MCK_GPRPairAsFPR";
5548 case MCK_GPRPairCRV32: return "MCK_GPRPairCRV32";
5549 case MCK_GPRPairNoX0RV32: return "MCK_GPRPairNoX0RV32";
5550 case MCK_GPRPairRV32: return "MCK_GPRPairRV32";
5551 case MCK_GPRPairRV64: return "MCK_GPRPairRV64";
5552 case MCK_Imm: return "MCK_Imm";
5553 case MCK_ImmFour: return "MCK_ImmFour";
5554 case MCK_ImmThree: return "MCK_ImmThree";
5555 case MCK_ImmZero: return "MCK_ImmZero";
5556 case MCK_InsnCDirectiveOpcode: return "MCK_InsnCDirectiveOpcode";
5557 case MCK_InsnDirectiveOpcode: return "MCK_InsnDirectiveOpcode";
5558 case MCK_LoadFPImm: return "MCK_LoadFPImm";
5559 case MCK_NegStackAdj: return "MCK_NegStackAdj";
5560 case MCK_PseudoJumpSymbol: return "MCK_PseudoJumpSymbol";
5561 case MCK_RTZArg: return "MCK_RTZArg";
5562 case MCK_RegList: return "MCK_RegList";
5563 case MCK_RegListS0: return "MCK_RegListS0";
5564 case MCK_RnumArg: return "MCK_RnumArg";
5565 case MCK_SImm10Unsigned: return "MCK_SImm10Unsigned";
5566 case MCK_SImm8Unsigned: return "MCK_SImm8Unsigned";
5567 case MCK_BareSImm21Lsb0: return "MCK_BareSImm21Lsb0";
5568 case MCK_StackAdj: return "MCK_StackAdj";
5569 case MCK_TLSDESCCallSymbol: return "MCK_TLSDESCCallSymbol";
5570 case MCK_TPRelAddSymbol: return "MCK_TPRelAddSymbol";
5571 case MCK_UImm5Plus1: return "MCK_UImm5Plus1";
5572 case MCK_UImmLog2XLen: return "MCK_UImmLog2XLen";
5573 case MCK_UImmLog2XLenNonZero: return "MCK_UImmLog2XLenNonZero";
5574 case MCK_RVVMaskRegOpOperand: return "MCK_RVVMaskRegOpOperand";
5575 case MCK_RVVMaskCarryInRegOpOperand: return "MCK_RVVMaskCarryInRegOpOperand";
5576 case MCK_XSfmmVType: return "MCK_XSfmmVType";
5577 case MCK_ZeroOffsetMemOpOperand: return "MCK_ZeroOffsetMemOpOperand";
5578 case MCK_UImm1: return "MCK_UImm1";
5579 case MCK_UImm2: return "MCK_UImm2";
5580 case MCK_UImm3: return "MCK_UImm3";
5581 case MCK_UImm4: return "MCK_UImm4";
5582 case MCK_UImm5: return "MCK_UImm5";
5583 case MCK_UImm6: return "MCK_UImm6";
5584 case MCK_UImm7: return "MCK_UImm7";
5585 case MCK_UImm8: return "MCK_UImm8";
5586 case MCK_UImm16: return "MCK_UImm16";
5587 case MCK_UImm32: return "MCK_UImm32";
5588 case MCK_UImm48: return "MCK_UImm48";
5589 case MCK_UImm64: return "MCK_UImm64";
5590 case MCK_SImm12: return "MCK_SImm12";
5591 case MCK_SImm12LO: return "MCK_SImm12LO";
5592 case MCK_BareSImm13Lsb0: return "MCK_BareSImm13Lsb0";
5593 case MCK_UImm20: return "MCK_UImm20";
5594 case MCK_UImm20LUI: return "MCK_UImm20LUI";
5595 case MCK_UImm20AUIPC: return "MCK_UImm20AUIPC";
5596 case MCK_ImmXLenLI: return "MCK_ImmXLenLI";
5597 case MCK_ImmXLenLI_Restricted: return "MCK_ImmXLenLI_Restricted";
5598 case MCK_SImm12Lsb00000: return "MCK_SImm12Lsb00000";
5599 case MCK_Imm5Zibi: return "MCK_Imm5Zibi";
5600 case MCK_VTypeI10: return "MCK_VTypeI10";
5601 case MCK_VTypeI11: return "MCK_VTypeI11";
5602 case MCK_SImm5: return "MCK_SImm5";
5603 case MCK_SImm5Plus1: return "MCK_SImm5Plus1";
5604 case MCK_SImm10: return "MCK_SImm10";
5605 case MCK_SImm6: return "MCK_SImm6";
5606 case MCK_SImm6NonZero: return "MCK_SImm6NonZero";
5607 case MCK_UImm7Lsb00: return "MCK_UImm7Lsb00";
5608 case MCK_UImm8Lsb00: return "MCK_UImm8Lsb00";
5609 case MCK_UImm8Lsb000: return "MCK_UImm8Lsb000";
5610 case MCK_BareSImm9Lsb0: return "MCK_BareSImm9Lsb0";
5611 case MCK_UImm9Lsb000: return "MCK_UImm9Lsb000";
5612 case MCK_UImm10Lsb00NonZero: return "MCK_UImm10Lsb00NonZero";
5613 case MCK_SImm10Lsb0000NonZero: return "MCK_SImm10Lsb0000NonZero";
5614 case MCK_BareSImm12Lsb0: return "MCK_BareSImm12Lsb0";
5615 case MCK_UImm2Lsb0: return "MCK_UImm2Lsb0";
5616 case MCK_UImm8GE32: return "MCK_UImm8GE32";
5617 case MCK_UImm5Lsb0: return "MCK_UImm5Lsb0";
5618 case MCK_UImm6Lsb0: return "MCK_UImm6Lsb0";
5619 case MCK_UImm5NonZero: return "MCK_UImm5NonZero";
5620 case MCK_UImm5GT3: return "MCK_UImm5GT3";
5621 case MCK_UImm5GE6Plus1: return "MCK_UImm5GE6Plus1";
5622 case MCK_UImm5Slist: return "MCK_UImm5Slist";
5623 case MCK_UImm10: return "MCK_UImm10";
5624 case MCK_UImm11: return "MCK_UImm11";
5625 case MCK_UImm14Lsb00: return "MCK_UImm14Lsb00";
5626 case MCK_UImm16NonZero: return "MCK_UImm16NonZero";
5627 case MCK_SImm5NonZero: return "MCK_SImm5NonZero";
5628 case MCK_SImm11: return "MCK_SImm11";
5629 case MCK_SImm16: return "MCK_SImm16";
5630 case MCK_SImm16NonZero: return "MCK_SImm16NonZero";
5631 case MCK_SImm20LI: return "MCK_SImm20LI";
5632 case MCK_SImm26: return "MCK_SImm26";
5633 case MCK_BareSImm32: return "MCK_BareSImm32";
5634 case MCK_BareSImm32Lsb0: return "MCK_BareSImm32Lsb0";
5635 case MCK_UImm7Lsb000: return "MCK_UImm7Lsb000";
5636 case MCK_UImm9: return "MCK_UImm9";
5637 case MCK_BareSImm11Lsb0: return "MCK_BareSImm11Lsb0";
5638 case MCK_SImm18: return "MCK_SImm18";
5639 case MCK_SImm18Lsb0: return "MCK_SImm18Lsb0";
5640 case MCK_SImm19Lsb00: return "MCK_SImm19Lsb00";
5641 case MCK_SImm20Lsb000: return "MCK_SImm20Lsb000";
5642 case NumMatchClassKinds: return "NumMatchClassKinds";
5643 }
5644 llvm_unreachable("unhandled MatchClassKind!");
5645}
5646
5647#endif // NDEBUG
5648FeatureBitset RISCVAsmParser::
5649ComputeAvailableFeatures(const FeatureBitset &FB) const {
5650 FeatureBitset Features;
5651 if (FB[RISCV::FeatureStdExtZibi])
5652 Features.set(Feature_HasStdExtZibiBit);
5653 if (FB[RISCV::FeatureStdExtZicbom])
5654 Features.set(Feature_HasStdExtZicbomBit);
5655 if (FB[RISCV::FeatureStdExtZicbop])
5656 Features.set(Feature_HasStdExtZicbopBit);
5657 if (FB[RISCV::FeatureStdExtZicboz])
5658 Features.set(Feature_HasStdExtZicbozBit);
5659 if (FB[RISCV::FeatureStdExtZicsr])
5660 Features.set(Feature_HasStdExtZicsrBit);
5661 if (FB[RISCV::FeatureStdExtZicond])
5662 Features.set(Feature_HasStdExtZicondBit);
5663 if (FB[RISCV::FeatureStdExtZifencei])
5664 Features.set(Feature_HasStdExtZifenceiBit);
5665 if (FB[RISCV::FeatureStdExtZihintpause])
5666 Features.set(Feature_HasStdExtZihintpauseBit);
5667 if (FB[RISCV::FeatureStdExtZihintntl])
5668 Features.set(Feature_HasStdExtZihintntlBit);
5669 if (FB[RISCV::FeatureStdExtZimop])
5670 Features.set(Feature_HasStdExtZimopBit);
5671 if (FB[RISCV::FeatureStdExtZicfilp])
5672 Features.set(Feature_HasStdExtZicfilpBit);
5673 if (!FB[RISCV::FeatureStdExtZicfilp])
5674 Features.set(Feature_NoStdExtZicfilpBit);
5675 if (FB[RISCV::FeatureStdExtZicfiss])
5676 Features.set(Feature_HasStdExtZicfissBit);
5677 if (FB[RISCV::FeatureStdExtZilsd])
5678 Features.set(Feature_HasStdExtZilsdBit);
5679 if (FB[RISCV::FeatureStdExtZmmul])
5680 Features.set(Feature_HasStdExtZmmulBit);
5681 if (FB[RISCV::FeatureStdExtM])
5682 Features.set(Feature_HasStdExtMBit);
5683 if (FB[RISCV::FeatureStdExtZaamo])
5684 Features.set(Feature_HasStdExtZaamoBit);
5685 if (FB[RISCV::FeatureStdExtZalrsc])
5686 Features.set(Feature_HasStdExtZalrscBit);
5687 if (FB[RISCV::FeatureStdExtA])
5688 Features.set(Feature_HasStdExtABit);
5689 if (FB[RISCV::FeatureStdExtZtso])
5690 Features.set(Feature_HasStdExtZtsoBit);
5691 if (FB[RISCV::FeatureStdExtZabha])
5692 Features.set(Feature_HasStdExtZabhaBit);
5693 if (FB[RISCV::FeatureStdExtZacas])
5694 Features.set(Feature_HasStdExtZacasBit);
5695 if (FB[RISCV::FeatureStdExtZalasr])
5696 Features.set(Feature_HasStdExtZalasrBit);
5697 if (FB[RISCV::FeatureStdExtZawrs])
5698 Features.set(Feature_HasStdExtZawrsBit);
5699 if (FB[RISCV::FeatureStdExtF])
5700 Features.set(Feature_HasStdExtFBit);
5701 if (FB[RISCV::FeatureStdExtD])
5702 Features.set(Feature_HasStdExtDBit);
5703 if (FB[RISCV::FeatureStdExtQ])
5704 Features.set(Feature_HasStdExtQBit);
5705 if (FB[RISCV::FeatureStdExtZfhmin])
5706 Features.set(Feature_HasStdExtZfhminBit);
5707 if (FB[RISCV::FeatureStdExtZfh])
5708 Features.set(Feature_HasStdExtZfhBit);
5709 if (FB[RISCV::FeatureStdExtZfbfmin])
5710 Features.set(Feature_HasStdExtZfbfminBit);
5711 if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZfhmin] || FB[RISCV::FeatureStdExtZfbfmin])
5712 Features.set(Feature_HasHalfFPLoadStoreMoveBit);
5713 if (FB[RISCV::FeatureStdExtZfa])
5714 Features.set(Feature_HasStdExtZfaBit);
5715 if (FB[RISCV::FeatureStdExtZfinx])
5716 Features.set(Feature_HasStdExtZfinxBit);
5717 if (FB[RISCV::FeatureStdExtF] || FB[RISCV::FeatureStdExtZfinx])
5718 Features.set(Feature_HasStdExtFOrZfinxBit);
5719 if (FB[RISCV::FeatureStdExtZdinx])
5720 Features.set(Feature_HasStdExtZdinxBit);
5721 if (FB[RISCV::FeatureStdExtZhinxmin])
5722 Features.set(Feature_HasStdExtZhinxminBit);
5723 if (FB[RISCV::FeatureStdExtZhinx])
5724 Features.set(Feature_HasStdExtZhinxBit);
5725 if (FB[RISCV::FeatureStdExtZca])
5726 Features.set(Feature_HasStdExtZcaBit);
5727 if (FB[RISCV::FeatureStdExtC])
5728 Features.set(Feature_HasStdExtCBit);
5729 if (FB[RISCV::FeatureStdExtZcb])
5730 Features.set(Feature_HasStdExtZcbBit);
5731 if (FB[RISCV::FeatureStdExtC] || FB[RISCV::FeatureStdExtZcd])
5732 Features.set(Feature_HasStdExtCOrZcdBit);
5733 if (FB[RISCV::FeatureStdExtZclsd])
5734 Features.set(Feature_HasStdExtZclsdBit);
5735 if (FB[RISCV::FeatureStdExtZcmp])
5736 Features.set(Feature_HasStdExtZcmpBit);
5737 if (FB[RISCV::FeatureStdExtZcmt])
5738 Features.set(Feature_HasStdExtZcmtBit);
5739 if (FB[RISCV::FeatureStdExtC] || FB[RISCV::FeatureStdExtZcf] || FB[RISCV::FeatureStdExtZce])
5740 Features.set(Feature_HasStdExtCOrZcfOrZceBit);
5741 if (FB[RISCV::FeatureStdExtZcmop])
5742 Features.set(Feature_HasStdExtZcmopBit);
5743 if (FB[RISCV::FeatureStdExtZba])
5744 Features.set(Feature_HasStdExtZbaBit);
5745 if (FB[RISCV::FeatureStdExtZbb])
5746 Features.set(Feature_HasStdExtZbbBit);
5747 if (!FB[RISCV::FeatureStdExtZbb])
5748 Features.set(Feature_NoStdExtZbbBit);
5749 if (FB[RISCV::FeatureStdExtZbc])
5750 Features.set(Feature_HasStdExtZbcBit);
5751 if (FB[RISCV::FeatureStdExtZbs])
5752 Features.set(Feature_HasStdExtZbsBit);
5753 if (FB[RISCV::FeatureStdExtZbkb])
5754 Features.set(Feature_HasStdExtZbkbBit);
5755 if (!FB[RISCV::FeatureStdExtZbkb])
5756 Features.set(Feature_NoStdExtZbkbBit);
5757 if (FB[RISCV::FeatureStdExtZbkx])
5758 Features.set(Feature_HasStdExtZbkxBit);
5759 if (FB[RISCV::FeatureStdExtZbb] || FB[RISCV::FeatureStdExtZbkb])
5760 Features.set(Feature_HasStdExtZbbOrZbkbBit);
5761 if (FB[RISCV::FeatureStdExtZbkc])
5762 Features.set(Feature_HasStdExtZbkcBit);
5763 if (FB[RISCV::FeatureStdExtZbc] || FB[RISCV::FeatureStdExtZbkc])
5764 Features.set(Feature_HasStdExtZbcOrZbkcBit);
5765 if (FB[RISCV::FeatureStdExtZknd])
5766 Features.set(Feature_HasStdExtZkndBit);
5767 if (FB[RISCV::FeatureStdExtZkne])
5768 Features.set(Feature_HasStdExtZkneBit);
5769 if (FB[RISCV::FeatureStdExtZknd] || FB[RISCV::FeatureStdExtZkne])
5770 Features.set(Feature_HasStdExtZkndOrZkneBit);
5771 if (FB[RISCV::FeatureStdExtZknh])
5772 Features.set(Feature_HasStdExtZknhBit);
5773 if (FB[RISCV::FeatureStdExtZksed])
5774 Features.set(Feature_HasStdExtZksedBit);
5775 if (FB[RISCV::FeatureStdExtZksh])
5776 Features.set(Feature_HasStdExtZkshBit);
5777 if (FB[RISCV::FeatureStdExtZkr])
5778 Features.set(Feature_HasStdExtZkrBit);
5779 if (FB[RISCV::FeatureStdExtZvfbfa])
5780 Features.set(Feature_HasStdExtZvfbfaBit);
5781 if (FB[RISCV::FeatureStdExtZvfbfmin])
5782 Features.set(Feature_HasStdExtZvfbfminBit);
5783 if (FB[RISCV::FeatureStdExtZvfbfwma])
5784 Features.set(Feature_HasStdExtZvfbfwmaBit);
5785 if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZvfh])
5786 Features.set(Feature_HasStdExtZfhOrZvfhBit);
5787 if (FB[RISCV::FeatureStdExtZvfofp8min])
5788 Features.set(Feature_HasStdExtZvfofp8minBit);
5789 if (FB[RISCV::FeatureStdExtZvfbfmin] || FB[RISCV::FeatureStdExtZvfofp8min])
5790 Features.set(Feature_HasStdExtZvfbfminOrZvfofp8minBit);
5791 if (FB[RISCV::FeatureStdExtZvkb])
5792 Features.set(Feature_HasStdExtZvkbBit);
5793 if (FB[RISCV::FeatureStdExtZvbb])
5794 Features.set(Feature_HasStdExtZvbbBit);
5795 if (FB[RISCV::FeatureStdExtZvbc])
5796 Features.set(Feature_HasStdExtZvbcBit);
5797 if (FB[RISCV::FeatureStdExtZvbc] || FB[RISCV::FeatureStdExtZvbc32e])
5798 Features.set(Feature_HasStdExtZvbcOrZvbc32eBit);
5799 if (FB[RISCV::FeatureStdExtZvkg])
5800 Features.set(Feature_HasStdExtZvkgBit);
5801 if (FB[RISCV::FeatureStdExtZvkgs])
5802 Features.set(Feature_HasStdExtZvkgsBit);
5803 if (FB[RISCV::FeatureStdExtZvkned])
5804 Features.set(Feature_HasStdExtZvknedBit);
5805 if (FB[RISCV::FeatureStdExtZvknha])
5806 Features.set(Feature_HasStdExtZvknhaBit);
5807 if (FB[RISCV::FeatureStdExtZvknhb])
5808 Features.set(Feature_HasStdExtZvknhbBit);
5809 if (FB[RISCV::FeatureStdExtZvknha] || FB[RISCV::FeatureStdExtZvknhb])
5810 Features.set(Feature_HasStdExtZvknhaOrZvknhbBit);
5811 if (FB[RISCV::FeatureStdExtZvksed])
5812 Features.set(Feature_HasStdExtZvksedBit);
5813 if (FB[RISCV::FeatureStdExtZvksh])
5814 Features.set(Feature_HasStdExtZvkshBit);
5815 if (FB[RISCV::FeatureStdExtZvqdotq])
5816 Features.set(Feature_HasStdExtZvqdotqBit);
5817 if (FB[RISCV::FeatureStdExtZve32x])
5818 Features.set(Feature_HasVInstructionsBit);
5819 if (FB[RISCV::FeatureStdExtZve64x])
5820 Features.set(Feature_HasVInstructionsI64Bit);
5821 if (FB[RISCV::FeatureStdExtZve32f])
5822 Features.set(Feature_HasVInstructionsAnyFBit);
5823 if (FB[RISCV::FeatureStdExtZvfhmin] || FB[RISCV::FeatureStdExtZvfh])
5824 Features.set(Feature_HasVInstructionsF16MinimalBit);
5825 if (FB[RISCV::FeatureStdExtH])
5826 Features.set(Feature_HasStdExtHBit);
5827 if (FB[RISCV::FeatureStdExtSmrnmi])
5828 Features.set(Feature_HasStdExtSmrnmiBit);
5829 if (FB[RISCV::FeatureStdExtSvinval])
5830 Features.set(Feature_HasStdExtSvinvalBit);
5831 if (FB[RISCV::FeatureStdExtSmctr] || FB[RISCV::FeatureStdExtSsctr])
5832 Features.set(Feature_HasStdExtSmctrOrSsctrBit);
5833 if (FB[RISCV::FeatureStdExtP])
5834 Features.set(Feature_HasStdExtPBit);
5835 if (FB[RISCV::FeatureStdExtZbkb] || FB[RISCV::FeatureStdExtP])
5836 Features.set(Feature_HasStdExtZbkbOrPBit);
5837 if (FB[RISCV::FeatureStdExtY])
5838 Features.set(Feature_HasStdExtYBit);
5839 if (FB[RISCV::FeatureVendorXVentanaCondOps])
5840 Features.set(Feature_HasVendorXVentanaCondOpsBit);
5841 if (FB[RISCV::FeatureVendorXTHeadBa])
5842 Features.set(Feature_HasVendorXTHeadBaBit);
5843 if (FB[RISCV::FeatureVendorXTHeadBb])
5844 Features.set(Feature_HasVendorXTHeadBbBit);
5845 if (FB[RISCV::FeatureVendorXTHeadBs])
5846 Features.set(Feature_HasVendorXTHeadBsBit);
5847 if (FB[RISCV::FeatureVendorXTHeadCondMov])
5848 Features.set(Feature_HasVendorXTHeadCondMovBit);
5849 if (FB[RISCV::FeatureVendorXTHeadCmo])
5850 Features.set(Feature_HasVendorXTHeadCmoBit);
5851 if (FB[RISCV::FeatureVendorXTHeadFMemIdx])
5852 Features.set(Feature_HasVendorXTHeadFMemIdxBit);
5853 if (FB[RISCV::FeatureVendorXTHeadMac])
5854 Features.set(Feature_HasVendorXTHeadMacBit);
5855 if (FB[RISCV::FeatureVendorXTHeadMemIdx])
5856 Features.set(Feature_HasVendorXTHeadMemIdxBit);
5857 if (FB[RISCV::FeatureVendorXTHeadMemPair])
5858 Features.set(Feature_HasVendorXTHeadMemPairBit);
5859 if (FB[RISCV::FeatureVendorXTHeadSync])
5860 Features.set(Feature_HasVendorXTHeadSyncBit);
5861 if (FB[RISCV::FeatureVendorXTHeadVdot])
5862 Features.set(Feature_HasVendorXTHeadVdotBit);
5863 if (FB[RISCV::FeatureVendorXSfvcp])
5864 Features.set(Feature_HasVendorXSfvcpBit);
5865 if (FB[RISCV::FeatureVendorXSfmmbase])
5866 Features.set(Feature_HasVendorXSfmmbaseBit);
5867 if (FB[RISCV::FeatureVendorXSfmm32a8f])
5868 Features.set(Feature_HasVendorXSfmm32a8fBit);
5869 if (FB[RISCV::FeatureVendorXSfmm32a8i])
5870 Features.set(Feature_HasVendorXSfmm32a8iBit);
5871 if (FB[RISCV::FeatureVendorXSfmm32a16f] || FB[RISCV::FeatureVendorXSfmm32a32f] || FB[RISCV::FeatureVendorXSfmm64a64f])
5872 Features.set(Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit);
5873 if (FB[RISCV::FeatureVendorXSfvqmaccdod])
5874 Features.set(Feature_HasVendorXSfvqmaccdodBit);
5875 if (FB[RISCV::FeatureVendorXSfvqmaccqoq])
5876 Features.set(Feature_HasVendorXSfvqmaccqoqBit);
5877 if (FB[RISCV::FeatureVendorXSfvfwmaccqqq])
5878 Features.set(Feature_HasVendorXSfvfwmaccqqqBit);
5879 if (FB[RISCV::FeatureVendorXSfvfnrclipxfqf])
5880 Features.set(Feature_HasVendorXSfvfnrclipxfqfBit);
5881 if (FB[RISCV::FeatureVendorXSfvfbfexp16e] || FB[RISCV::FeatureVendorXSfvfexp16e] || FB[RISCV::FeatureVendorXSfvfexp32e])
5882 Features.set(Feature_HasVendorXSfvfexpAnyBit);
5883 if (FB[RISCV::FeatureVendorXSfvfexpa])
5884 Features.set(Feature_HasVendorXSfvfexpaBit);
5885 if (FB[RISCV::FeatureVendorXSiFivecdiscarddlone])
5886 Features.set(Feature_HasVendorXSiFivecdiscarddloneBit);
5887 if (FB[RISCV::FeatureVendorXSiFivecflushdlone])
5888 Features.set(Feature_HasVendorXSiFivecflushdloneBit);
5889 if (FB[RISCV::FeatureVendorXSfcease])
5890 Features.set(Feature_HasVendorXSfceaseBit);
5891 if (FB[RISCV::FeatureVendorXCVelw])
5892 Features.set(Feature_HasVendorXCVelwBit);
5893 if (FB[RISCV::FeatureVendorXCVbitmanip])
5894 Features.set(Feature_HasVendorXCVbitmanipBit);
5895 if (FB[RISCV::FeatureVendorXCVmac])
5896 Features.set(Feature_HasVendorXCVmacBit);
5897 if (FB[RISCV::FeatureVendorXCVmem])
5898 Features.set(Feature_HasVendorXCVmemBit);
5899 if (FB[RISCV::FeatureVendorXCValu])
5900 Features.set(Feature_HasVendorXCValuBit);
5901 if (FB[RISCV::FeatureVendorXCVsimd])
5902 Features.set(Feature_HasVendorXCVsimdBit);
5903 if (FB[RISCV::FeatureVendorXCVbi])
5904 Features.set(Feature_HasVendorXCVbiBit);
5905 if (FB[RISCV::FeatureVendorXMIPSCMov])
5906 Features.set(Feature_HasVendorXMIPSCMovBit);
5907 if (FB[RISCV::FeatureVendorXMIPSLSP])
5908 Features.set(Feature_HasVendorXMIPSLSPBit);
5909 if (FB[RISCV::FeatureVendorXMIPSCBOP])
5910 Features.set(Feature_HasVendorXMIPSCBOPBit);
5911 if (FB[RISCV::FeatureVendorXMIPSEXECTL])
5912 Features.set(Feature_HasVendorXMIPSEXECTLBit);
5913 if (FB[RISCV::FeatureVendorXwchc])
5914 Features.set(Feature_HasVendorXwchcBit);
5915 if (FB[RISCV::FeatureVendorXqccmp])
5916 Features.set(Feature_HasVendorXqccmpBit);
5917 if (FB[RISCV::FeatureVendorXqcia])
5918 Features.set(Feature_HasVendorXqciaBit);
5919 if (FB[RISCV::FeatureVendorXqciac])
5920 Features.set(Feature_HasVendorXqciacBit);
5921 if (FB[RISCV::FeatureVendorXqcibi])
5922 Features.set(Feature_HasVendorXqcibiBit);
5923 if (FB[RISCV::FeatureVendorXqcibm])
5924 Features.set(Feature_HasVendorXqcibmBit);
5925 if (FB[RISCV::FeatureVendorXqcicli])
5926 Features.set(Feature_HasVendorXqcicliBit);
5927 if (FB[RISCV::FeatureVendorXqcicm])
5928 Features.set(Feature_HasVendorXqcicmBit);
5929 if (FB[RISCV::FeatureVendorXqcics])
5930 Features.set(Feature_HasVendorXqcicsBit);
5931 if (FB[RISCV::FeatureVendorXqcicsr])
5932 Features.set(Feature_HasVendorXqcicsrBit);
5933 if (FB[RISCV::FeatureVendorXqciint])
5934 Features.set(Feature_HasVendorXqciintBit);
5935 if (FB[RISCV::FeatureVendorXqciio])
5936 Features.set(Feature_HasVendorXqciioBit);
5937 if (FB[RISCV::FeatureVendorXqcilb])
5938 Features.set(Feature_HasVendorXqcilbBit);
5939 if (FB[RISCV::FeatureVendorXqcili])
5940 Features.set(Feature_HasVendorXqciliBit);
5941 if (FB[RISCV::FeatureVendorXqcilia])
5942 Features.set(Feature_HasVendorXqciliaBit);
5943 if (FB[RISCV::FeatureVendorXqcilo])
5944 Features.set(Feature_HasVendorXqciloBit);
5945 if (FB[RISCV::FeatureVendorXqcilsm])
5946 Features.set(Feature_HasVendorXqcilsmBit);
5947 if (FB[RISCV::FeatureVendorXqcisim])
5948 Features.set(Feature_HasVendorXqcisimBit);
5949 if (FB[RISCV::FeatureVendorXqcisls])
5950 Features.set(Feature_HasVendorXqcislsBit);
5951 if (FB[RISCV::FeatureVendorXqcisync])
5952 Features.set(Feature_HasVendorXqcisyncBit);
5953 if (FB[RISCV::FeatureVendorXRivosVisni])
5954 Features.set(Feature_HasVendorXRivosVisniBit);
5955 if (FB[RISCV::FeatureVendorXRivosVizip])
5956 Features.set(Feature_HasVendorXRivosVizipBit);
5957 if (FB[RISCV::FeatureVendorXAndesPerf])
5958 Features.set(Feature_HasVendorXAndesPerfBit);
5959 if (FB[RISCV::FeatureVendorXAndesBFHCvt])
5960 Features.set(Feature_HasVendorXAndesBFHCvtBit);
5961 if (FB[RISCV::FeatureVendorXAndesVBFHCvt])
5962 Features.set(Feature_HasVendorXAndesVBFHCvtBit);
5963 if (FB[RISCV::FeatureVendorXAndesVSIntH])
5964 Features.set(Feature_HasVendorXAndesVSIntHBit);
5965 if (FB[RISCV::FeatureVendorXAndesVSIntLoad])
5966 Features.set(Feature_HasVendorXAndesVSIntLoadBit);
5967 if (FB[RISCV::FeatureVendorXAndesVPackFPH])
5968 Features.set(Feature_HasVendorXAndesVPackFPHBit);
5969 if (FB[RISCV::FeatureVendorXAndesVDot])
5970 Features.set(Feature_HasVendorXAndesVDotBit);
5971 if (FB[RISCV::FeatureVendorXSMTVDot])
5972 Features.set(Feature_HasVendorXSMTVDotBit);
5973 if (FB[RISCV::FeatureVendorXAIFET])
5974 Features.set(Feature_HasXAIFETBit);
5975 if (FB[RISCV::Feature64Bit])
5976 Features.set(Feature_IsRV64Bit);
5977 if (!FB[RISCV::Feature64Bit])
5978 Features.set(Feature_IsRV32Bit);
5979 return Features;
5980}
5981
5982static bool checkAsmTiedOperandConstraints(const RISCVAsmParser&AsmParser,
5983 unsigned Kind, const OperandVector &Operands,
5984 ArrayRef<unsigned> DefaultsOffset,
5985 uint64_t &ErrorInfo) {
5986 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
5987 const uint8_t *Converter = ConversionTable[Kind];
5988 for (const uint8_t *p = Converter; *p; p += 2) {
5989 switch (*p) {
5990 case CVT_Tied: {
5991 unsigned OpIdx = *(p + 1);
5992 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
5993 std::begin(TiedAsmOperandTable)) &&
5994 "Tied operand not found");
5995 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
5996 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
5997 OpndNum1 = OpndNum1 - DefaultsOffset[OpndNum1];
5998 OpndNum2 = OpndNum2 - DefaultsOffset[OpndNum2];
5999 if (OpndNum1 != OpndNum2) {
6000 auto &SrcOp1 = Operands[OpndNum1];
6001 auto &SrcOp2 = Operands[OpndNum2];
6002 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
6003 ErrorInfo = OpndNum2;
6004 return false;
6005 }
6006 }
6007 break;
6008 }
6009 default:
6010 break;
6011 }
6012 }
6013 return true;
6014}
6015
6016static const char MnemonicTable[] =
6017 "\007.insn_b\010.insn_ca\010.insn_cb\010.insn_ci\t.insn_ciw\010.insn_cj\010"
6018 ".insn_cl\010.insn_cr\010.insn_cs\t.insn_css\007.insn_i\007.insn_j\014.i"
6019 "nsn_qc.eai\013.insn_qc.eb\013.insn_qc.ei\013.insn_qc.ej\013.insn_qc.es\007"
6020 ".insn_r\010.insn_r4\007.insn_s\010.insn_sb\007.insn_u\010.insn_uj\004aa"
6021 "dd\005aaddu\003abs\004absw\003add\006add.uw\004addd\004addi\005addiw\004"
6022 "addw\010aes32dsi\taes32dsmi\010aes32esi\taes32esmi\007aes64ds\010aes64d"
6023 "sm\007aes64es\010aes64esm\007aes64im\taes64ks1i\010aes64ks2\015aif.amoa"
6024 "ddg.d\015aif.amoaddg.w\015aif.amoaddl.d\015aif.amoaddl.w\015aif.amoandg"
6025 ".d\015aif.amoandg.w\015aif.amoandl.d\015aif.amoandl.w\021aif.amocmpswap"
6026 "g.d\021aif.amocmpswapg.w\021aif.amocmpswapl.d\021aif.amocmpswapl.w\015a"
6027 "if.amomaxg.d\015aif.amomaxg.w\015aif.amomaxl.d\015aif.amomaxl.w\016aif."
6028 "amomaxug.d\016aif.amomaxug.w\016aif.amomaxul.d\016aif.amomaxul.w\015aif"
6029 ".amoming.d\015aif.amoming.w\015aif.amominl.d\015aif.amominl.w\016aif.am"
6030 "ominug.d\016aif.amominug.w\016aif.amominul.d\016aif.amominul.w\014aif.a"
6031 "moorg.d\014aif.amoorg.w\014aif.amoorl.d\014aif.amoorl.w\016aif.amoswapg"
6032 ".d\016aif.amoswapg.w\016aif.amoswapl.d\016aif.amoswapl.w\015aif.amoxorg"
6033 ".d\015aif.amoxorg.w\015aif.amoxorl.d\015aif.amoxorl.w\013aif.bitmixb\017"
6034 "aif.cubeface.ps\022aif.cubefaceidx.ps\020aif.cubesgnsc.ps\020aif.cubesg"
6035 "ntc.ps\013aif.fadd.pi\013aif.fadd.ps\014aif.faddi.pi\017aif.famoaddg.pi"
6036 "\017aif.famoaddl.pi\017aif.famoandg.pi\017aif.famoandl.pi\017aif.famoma"
6037 "xg.pi\017aif.famomaxg.ps\017aif.famomaxl.pi\017aif.famomaxl.ps\020aif.f"
6038 "amomaxug.pi\020aif.famomaxul.pi\017aif.famoming.pi\017aif.famoming.ps\017"
6039 "aif.famominl.pi\017aif.famominl.ps\020aif.famominug.pi\020aif.famominul"
6040 ".pi\016aif.famoorg.pi\016aif.famoorl.pi\020aif.famoswapg.pi\020aif.famo"
6041 "swapl.pi\017aif.famoxorg.pi\017aif.famoxorl.pi\013aif.fand.pi\014aif.fa"
6042 "ndi.pi\naif.fbc.ps\013aif.fbci.pi\013aif.fbci.ps\013aif.fbcx.ps\015aif."
6043 "fclass.ps\014aif.fcmov.ps\015aif.fcmovm.ps\017aif.fcvt.f10.ps\017aif.fc"
6044 "vt.f11.ps\017aif.fcvt.f16.ps\017aif.fcvt.ps.f10\017aif.fcvt.ps.f11\017a"
6045 "if.fcvt.ps.f16\016aif.fcvt.ps.pw\017aif.fcvt.ps.pwu\020aif.fcvt.ps.rast"
6046 "\020aif.fcvt.ps.sn16\017aif.fcvt.ps.sn8\020aif.fcvt.ps.un10\020aif.fcvt"
6047 ".ps.un16\017aif.fcvt.ps.un2\020aif.fcvt.ps.un24\017aif.fcvt.ps.un8\016a"
6048 "if.fcvt.pw.ps\017aif.fcvt.pwu.ps\020aif.fcvt.rast.ps\020aif.fcvt.sn16.p"
6049 "s\017aif.fcvt.sn8.ps\020aif.fcvt.un10.ps\020aif.fcvt.un16.ps\017aif.fcv"
6050 "t.un2.ps\020aif.fcvt.un24.ps\017aif.fcvt.un8.ps\013aif.fdiv.pi\013aif.f"
6051 "div.ps\014aif.fdivu.pi\naif.feq.pi\naif.feq.ps\013aif.feqm.ps\013aif.fe"
6052 "xp.ps\013aif.ffrc.ps\014aif.fg32b.ps\014aif.fg32h.ps\014aif.fg32w.ps\na"
6053 "if.fgb.ps\013aif.fgbg.ps\013aif.fgbl.ps\naif.fgh.ps\013aif.fghg.ps\013a"
6054 "if.fghl.ps\naif.fgw.ps\013aif.fgwg.ps\013aif.fgwl.ps\naif.fle.pi\naif.f"
6055 "le.ps\013aif.flem.ps\013aif.flog.ps\010aif.flq2\naif.flt.pi\naif.flt.ps"
6056 "\013aif.fltm.pi\013aif.fltm.ps\013aif.fltu.pi\naif.flw.ps\013aif.flwg.p"
6057 "s\013aif.flwl.ps\014aif.fmadd.ps\013aif.fmax.pi\013aif.fmax.ps\014aif.f"
6058 "maxu.pi\013aif.fmin.pi\013aif.fmin.ps\014aif.fminu.pi\014aif.fmsub.ps\013"
6059 "aif.fmul.pi\013aif.fmul.ps\014aif.fmulh.pi\015aif.fmulhu.pi\015aif.fmvs"
6060 ".x.ps\015aif.fmvz.x.ps\015aif.fnmadd.ps\015aif.fnmsub.ps\013aif.fnot.pi"
6061 "\naif.for.pi\020aif.fpackrepb.pi\020aif.fpackreph.pi\013aif.frcp.ps\021"
6062 "aif.frcp_fix.rast\013aif.frem.pi\014aif.fremu.pi\015aif.fround.ps\013ai"
6063 "f.frsq.ps\014aif.fsat8.pi\015aif.fsatu8.pi\015aif.fsc32b.ps\015aif.fsc3"
6064 "2h.ps\015aif.fsc32w.ps\013aif.fscb.ps\014aif.fscbg.ps\014aif.fscbl.ps\013"
6065 "aif.fsch.ps\014aif.fschg.ps\014aif.fschl.ps\013aif.fscw.ps\014aif.fscwg"
6066 ".ps\014aif.fscwl.ps\014aif.fsetm.pi\014aif.fsgnj.ps\015aif.fsgnjn.ps\015"
6067 "aif.fsgnjx.ps\013aif.fsin.ps\013aif.fsll.pi\014aif.fslli.pi\010aif.fsq2"
6068 "\014aif.fsqrt.ps\013aif.fsra.pi\014aif.fsrai.pi\013aif.fsrl.pi\014aif.f"
6069 "srli.pi\013aif.fsub.pi\013aif.fsub.ps\naif.fsw.ps\013aif.fswg.ps\015aif"
6070 ".fswizz.ps\013aif.fswl.ps\013aif.fxor.pi\013aif.maskand\013aif.masknot\n"
6071 "aif.maskor\014aif.maskpopc\021aif.maskpopc.rast\015aif.maskpopcz\013aif"
6072 ".maskxor\013aif.mov.m.x\014aif.mova.m.x\014aif.mova.x.m\taif.packb\007a"
6073 "if.sbg\007aif.sbl\007aif.shg\007aif.shl\010amoadd.b\013amoadd.b.aq\015a"
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6239 "\tmqacc.w01\tmqacc.w11\nmqracc.h00\nmqracc.h01\nmqracc.h11\nmqracc.w00\n"
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6407 "iva\017th.l2cache.call\020th.l2cache.ciall\017th.l2cache.iall\007th.lbi"
6408 "a\007th.lbib\010th.lbuia\010th.lbuib\006th.ldd\007th.ldia\007th.ldib\007"
6409 "th.lhia\007th.lhib\010th.lhuia\010th.lhuib\006th.lrb\007th.lrbu\006th.l"
6410 "rd\006th.lrh\007th.lrhu\006th.lrw\007th.lrwu\007th.lurb\010th.lurbu\007"
6411 "th.lurd\007th.lurh\010th.lurhu\007th.lurw\010th.lurwu\006th.lwd\007th.l"
6412 "wia\007th.lwib\007th.lwud\010th.lwuia\010th.lwuib\007th.mula\010th.mula"
6413 "h\010th.mulaw\007th.muls\010th.mulsh\010th.mulsw\010th.mveqz\010th.mvne"
6414 "z\006th.rev\007th.revw\007th.sbia\007th.sbib\006th.sdd\007th.sdia\007th"
6415 ".sdib\016th.sfence.vmas\007th.shia\007th.shib\006th.srb\006th.srd\006th"
6416 ".srh\007th.srri\010th.srriw\006th.srw\007th.surb\007th.surd\007th.surh\007"
6417 "th.surw\006th.swd\007th.swia\007th.swib\007th.sync\tth.sync.i\nth.sync."
6418 "is\tth.sync.s\006th.tst\tth.tstnbz\013th.vmaqa.vv\013th.vmaqa.vx\015th."
6419 "vmaqasu.vv\015th.vmaqasu.vx\014th.vmaqau.vv\014th.vmaqau.vx\015th.vmaqa"
6420 "us.vx\005unimp\005unzip\tunzip16hp\010unzip16p\010unzip8hp\007unzip8p\005"
6421 "usati\010vaadd.vv\010vaadd.vx\tvaaddu.vv\tvaaddu.vx\010vadc.vim\010vadc"
6422 ".vvm\010vadc.vxm\007vadd.vi\007vadd.vv\007vadd.vx\tvaesdf.vs\tvaesdf.vv"
6423 "\tvaesdm.vs\tvaesdm.vv\tvaesef.vs\tvaesef.vv\tvaesem.vs\tvaesem.vv\nvae"
6424 "skf1.vi\nvaeskf2.vi\010vaesz.vs\007vand.vi\007vand.vv\007vand.vx\010van"
6425 "dn.vv\010vandn.vx\010vasub.vv\010vasub.vx\tvasubu.vv\tvasubu.vx\007vbre"
6426 "v.v\010vbrev8.v\tvclmul.vv\tvclmul.vx\nvclmulh.vv\nvclmulh.vx\006vclz.v"
6427 "\014vcompress.vm\007vcpop.m\007vcpop.v\006vctz.v\007vdiv.vv\007vdiv.vx\010"
6428 "vdivu.vv\010vdivu.vx\007vfabs.v\010vfadd.vf\010vfadd.vv\tvfclass.v\013v"
6429 "fcvt.f.x.v\014vfcvt.f.xu.v\017vfcvt.rtz.x.f.v\020vfcvt.rtz.xu.f.v\013vf"
6430 "cvt.x.f.v\014vfcvt.xu.f.v\010vfdiv.vf\010vfdiv.vv\010vfirst.m\tvfmacc.v"
6431 "f\tvfmacc.vv\tvfmadd.vf\tvfmadd.vv\010vfmax.vf\010vfmax.vv\013vfmerge.v"
6432 "fm\010vfmin.vf\010vfmin.vv\tvfmsac.vf\tvfmsac.vv\tvfmsub.vf\tvfmsub.vv\010"
6433 "vfmul.vf\010vfmul.vv\010vfmv.f.s\010vfmv.s.f\010vfmv.v.f\014vfncvt.f.f."
6434 "q\014vfncvt.f.f.w\014vfncvt.f.x.w\015vfncvt.f.xu.w\020vfncvt.rod.f.f.w\020"
6435 "vfncvt.rtz.x.f.w\021vfncvt.rtz.xu.f.w\020vfncvt.sat.f.f.q\014vfncvt.x.f"
6436 ".w\015vfncvt.xu.f.w\020vfncvtbf16.f.f.w\024vfncvtbf16.sat.f.f.w\007vfne"
6437 "g.v\nvfnmacc.vf\nvfnmacc.vv\nvfnmadd.vf\nvfnmadd.vv\nvfnmsac.vf\nvfnmsa"
6438 "c.vv\nvfnmsub.vf\nvfnmsub.vv\tvfrdiv.vf\010vfrec7.v\013vfredmax.vs\013v"
6439 "fredmin.vs\014vfredosum.vs\014vfredusum.vs\nvfrsqrt7.v\tvfrsub.vf\tvfsg"
6440 "nj.vf\tvfsgnj.vv\nvfsgnjn.vf\nvfsgnjn.vv\nvfsgnjx.vf\nvfsgnjx.vv\017vfs"
6441 "lide1down.vf\015vfslide1up.vf\010vfsqrt.v\010vfsub.vf\010vfsub.vv\tvfwa"
6442 "dd.vf\tvfwadd.vv\tvfwadd.wf\tvfwadd.wv\014vfwcvt.f.f.v\014vfwcvt.f.x.v\015"
6443 "vfwcvt.f.xu.v\020vfwcvt.rtz.x.f.v\021vfwcvt.rtz.xu.f.v\014vfwcvt.x.f.v\015"
6444 "vfwcvt.xu.f.v\020vfwcvtbf16.f.f.v\nvfwmacc.vf\nvfwmacc.vv\016vfwmaccbf1"
6445 "6.vf\016vfwmaccbf16.vv\nvfwmsac.vf\nvfwmsac.vv\tvfwmul.vf\tvfwmul.vv\013"
6446 "vfwnmacc.vf\013vfwnmacc.vv\013vfwnmsac.vf\013vfwnmsac.vv\015vfwredosum."
6447 "vs\015vfwredusum.vs\tvfwsub.vf\tvfwsub.vv\tvfwsub.wf\tvfwsub.wv\010vghs"
6448 "h.vs\010vghsh.vv\010vgmul.vs\010vgmul.vv\005vid.v\007viota.m\006vl1r.v\t"
6449 "vl1re16.v\tvl1re32.v\tvl1re64.v\010vl1re8.v\006vl2r.v\tvl2re16.v\tvl2re"
6450 "32.v\tvl2re64.v\010vl2re8.v\006vl4r.v\tvl4re16.v\tvl4re32.v\tvl4re64.v\010"
6451 "vl4re8.v\006vl8r.v\tvl8re16.v\tvl8re32.v\tvl8re64.v\010vl8re8.v\007vle1"
6452 "6.v\tvle16ff.v\007vle32.v\tvle32ff.v\007vle64.v\tvle64ff.v\006vle8.v\010"
6453 "vle8ff.v\005vlm.v\nvloxei16.v\nvloxei32.v\nvloxei64.v\tvloxei8.v\016vlo"
6454 "xseg2ei16.v\016vloxseg2ei32.v\016vloxseg2ei64.v\015vloxseg2ei8.v\016vlo"
6455 "xseg3ei16.v\016vloxseg3ei32.v\016vloxseg3ei64.v\015vloxseg3ei8.v\016vlo"
6456 "xseg4ei16.v\016vloxseg4ei32.v\016vloxseg4ei64.v\015vloxseg4ei8.v\016vlo"
6457 "xseg5ei16.v\016vloxseg5ei32.v\016vloxseg5ei64.v\015vloxseg5ei8.v\016vlo"
6458 "xseg6ei16.v\016vloxseg6ei32.v\016vloxseg6ei64.v\015vloxseg6ei8.v\016vlo"
6459 "xseg7ei16.v\016vloxseg7ei32.v\016vloxseg7ei64.v\015vloxseg7ei8.v\016vlo"
6460 "xseg8ei16.v\016vloxseg8ei32.v\016vloxseg8ei64.v\015vloxseg8ei8.v\010vls"
6461 "e16.v\010vlse32.v\010vlse64.v\007vlse8.v\013vlseg2e16.v\015vlseg2e16ff."
6462 "v\013vlseg2e32.v\015vlseg2e32ff.v\013vlseg2e64.v\015vlseg2e64ff.v\nvlse"
6463 "g2e8.v\014vlseg2e8ff.v\013vlseg3e16.v\015vlseg3e16ff.v\013vlseg3e32.v\015"
6464 "vlseg3e32ff.v\013vlseg3e64.v\015vlseg3e64ff.v\nvlseg3e8.v\014vlseg3e8ff"
6465 ".v\013vlseg4e16.v\015vlseg4e16ff.v\013vlseg4e32.v\015vlseg4e32ff.v\013v"
6466 "lseg4e64.v\015vlseg4e64ff.v\nvlseg4e8.v\014vlseg4e8ff.v\013vlseg5e16.v\015"
6467 "vlseg5e16ff.v\013vlseg5e32.v\015vlseg5e32ff.v\013vlseg5e64.v\015vlseg5e"
6468 "64ff.v\nvlseg5e8.v\014vlseg5e8ff.v\013vlseg6e16.v\015vlseg6e16ff.v\013v"
6469 "lseg6e32.v\015vlseg6e32ff.v\013vlseg6e64.v\015vlseg6e64ff.v\nvlseg6e8.v"
6470 "\014vlseg6e8ff.v\013vlseg7e16.v\015vlseg7e16ff.v\013vlseg7e32.v\015vlse"
6471 "g7e32ff.v\013vlseg7e64.v\015vlseg7e64ff.v\nvlseg7e8.v\014vlseg7e8ff.v\013"
6472 "vlseg8e16.v\015vlseg8e16ff.v\013vlseg8e32.v\015vlseg8e32ff.v\013vlseg8e"
6473 "64.v\015vlseg8e64ff.v\nvlseg8e8.v\014vlseg8e8ff.v\014vlsseg2e16.v\014vl"
6474 "sseg2e32.v\014vlsseg2e64.v\013vlsseg2e8.v\014vlsseg3e16.v\014vlsseg3e32"
6475 ".v\014vlsseg3e64.v\013vlsseg3e8.v\014vlsseg4e16.v\014vlsseg4e32.v\014vl"
6476 "sseg4e64.v\013vlsseg4e8.v\014vlsseg5e16.v\014vlsseg5e32.v\014vlsseg5e64"
6477 ".v\013vlsseg5e8.v\014vlsseg6e16.v\014vlsseg6e32.v\014vlsseg6e64.v\013vl"
6478 "sseg6e8.v\014vlsseg7e16.v\014vlsseg7e32.v\014vlsseg7e64.v\013vlsseg7e8."
6479 "v\014vlsseg8e16.v\014vlsseg8e32.v\014vlsseg8e64.v\013vlsseg8e8.v\nvluxe"
6480 "i16.v\nvluxei32.v\nvluxei64.v\tvluxei8.v\016vluxseg2ei16.v\016vluxseg2e"
6481 "i32.v\016vluxseg2ei64.v\015vluxseg2ei8.v\016vluxseg3ei16.v\016vluxseg3e"
6482 "i32.v\016vluxseg3ei64.v\015vluxseg3ei8.v\016vluxseg4ei16.v\016vluxseg4e"
6483 "i32.v\016vluxseg4ei64.v\015vluxseg4ei8.v\016vluxseg5ei16.v\016vluxseg5e"
6484 "i32.v\016vluxseg5ei64.v\015vluxseg5ei8.v\016vluxseg6ei16.v\016vluxseg6e"
6485 "i32.v\016vluxseg6ei64.v\015vluxseg6ei8.v\016vluxseg7ei16.v\016vluxseg7e"
6486 "i32.v\016vluxseg7ei64.v\015vluxseg7ei8.v\016vluxseg8ei16.v\016vluxseg8e"
6487 "i32.v\016vluxseg8ei64.v\015vluxseg8ei8.v\010vmacc.vv\010vmacc.vx\010vma"
6488 "dc.vi\tvmadc.vim\010vmadc.vv\tvmadc.vvm\010vmadc.vx\tvmadc.vxm\010vmadd"
6489 ".vv\010vmadd.vx\010vmand.mm\tvmandn.mm\007vmax.vv\007vmax.vx\010vmaxu.v"
6490 "v\010vmaxu.vx\007vmclr.m\nvmerge.vim\nvmerge.vvm\nvmerge.vxm\010vmfeq.v"
6491 "f\010vmfeq.vv\010vmfge.vf\010vmfge.vv\010vmfgt.vf\010vmfgt.vv\010vmfle."
6492 "vf\010vmfle.vv\010vmflt.vf\010vmflt.vv\010vmfne.vf\010vmfne.vv\007vmin."
6493 "vv\007vmin.vx\010vminu.vv\010vminu.vx\006vmmv.m\tvmnand.mm\010vmnor.mm\007"
6494 "vmnot.m\007vmor.mm\010vmorn.mm\010vmsbc.vv\tvmsbc.vvm\010vmsbc.vx\tvmsb"
6495 "c.vxm\007vmsbf.m\010vmseq.vi\010vmseq.vv\010vmseq.vx\007vmset.m\010vmsg"
6496 "e.vi\010vmsge.vv\010vmsge.vx\tvmsgeu.vi\tvmsgeu.vv\tvmsgeu.vx\010vmsgt."
6497 "vi\010vmsgt.vv\010vmsgt.vx\tvmsgtu.vi\tvmsgtu.vv\tvmsgtu.vx\007vmsif.m\010"
6498 "vmsle.vi\010vmsle.vv\010vmsle.vx\tvmsleu.vi\tvmsleu.vv\tvmsleu.vx\010vm"
6499 "slt.vi\010vmslt.vv\010vmslt.vx\tvmsltu.vi\tvmsltu.vv\tvmsltu.vx\010vmsn"
6500 "e.vi\010vmsne.vv\010vmsne.vx\007vmsof.m\007vmul.vv\007vmul.vx\010vmulh."
6501 "vv\010vmulh.vx\nvmulhsu.vv\nvmulhsu.vx\tvmulhu.vv\tvmulhu.vx\007vmv.s.x"
6502 "\007vmv.v.i\007vmv.v.v\007vmv.v.x\007vmv.x.s\007vmv1r.v\007vmv2r.v\007v"
6503 "mv4r.v\007vmv8r.v\tvmxnor.mm\010vmxor.mm\tvnclip.wi\tvnclip.wv\tvnclip."
6504 "wx\nvnclipu.wi\nvnclipu.wv\nvnclipu.wx\013vncvt.x.x.w\006vneg.v\tvnmsac"
6505 ".vv\tvnmsac.vx\tvnmsub.vv\tvnmsub.vx\006vnot.v\010vnsra.wi\010vnsra.wv\010"
6506 "vnsra.wx\010vnsrl.wi\010vnsrl.wv\010vnsrl.wx\006vor.vi\006vor.vv\006vor"
6507 ".vx\010vqdot.vv\010vqdot.vx\nvqdotsu.vv\nvqdotsu.vx\tvqdotu.vv\tvqdotu."
6508 "vx\nvqdotus.vx\nvredand.vs\nvredmax.vs\013vredmaxu.vs\nvredmin.vs\013vr"
6509 "edminu.vs\tvredor.vs\nvredsum.vs\nvredxor.vs\007vrem.vv\007vrem.vx\010v"
6510 "remu.vv\010vremu.vx\007vrev8.v\013vrgather.vi\013vrgather.vv\013vrgathe"
6511 "r.vx\017vrgatherei16.vv\007vrol.vv\007vrol.vx\007vror.vi\007vror.vv\007"
6512 "vror.vx\010vrsub.vi\010vrsub.vx\006vs1r.v\006vs2r.v\006vs4r.v\006vs8r.v"
6513 "\010vsadd.vi\010vsadd.vv\010vsadd.vx\tvsaddu.vi\tvsaddu.vv\tvsaddu.vx\010"
6514 "vsbc.vvm\010vsbc.vxm\007vse16.v\007vse32.v\007vse64.v\006vse8.v\010vset"
6515 "ivli\006vsetvl\007vsetvli\tvsext.vf2\tvsext.vf4\tvsext.vf8\nvsha2ch.vv\n"
6516 "vsha2cl.vv\nvsha2ms.vv\016vslide1down.vx\014vslide1up.vx\015vslidedown."
6517 "vi\015vslidedown.vx\013vslideup.vi\013vslideup.vx\007vsll.vi\007vsll.vv"
6518 "\007vsll.vx\005vsm.v\010vsm3c.vi\tvsm3me.vv\010vsm4k.vi\010vsm4r.vs\010"
6519 "vsm4r.vv\010vsmul.vv\010vsmul.vx\nvsoxei16.v\nvsoxei32.v\nvsoxei64.v\tv"
6520 "soxei8.v\016vsoxseg2ei16.v\016vsoxseg2ei32.v\016vsoxseg2ei64.v\015vsoxs"
6521 "eg2ei8.v\016vsoxseg3ei16.v\016vsoxseg3ei32.v\016vsoxseg3ei64.v\015vsoxs"
6522 "eg3ei8.v\016vsoxseg4ei16.v\016vsoxseg4ei32.v\016vsoxseg4ei64.v\015vsoxs"
6523 "eg4ei8.v\016vsoxseg5ei16.v\016vsoxseg5ei32.v\016vsoxseg5ei64.v\015vsoxs"
6524 "eg5ei8.v\016vsoxseg6ei16.v\016vsoxseg6ei32.v\016vsoxseg6ei64.v\015vsoxs"
6525 "eg6ei8.v\016vsoxseg7ei16.v\016vsoxseg7ei32.v\016vsoxseg7ei64.v\015vsoxs"
6526 "eg7ei8.v\016vsoxseg8ei16.v\016vsoxseg8ei32.v\016vsoxseg8ei64.v\015vsoxs"
6527 "eg8ei8.v\007vsra.vi\007vsra.vv\007vsra.vx\007vsrl.vi\007vsrl.vv\007vsrl"
6528 ".vx\010vsse16.v\010vsse32.v\010vsse64.v\007vsse8.v\013vsseg2e16.v\013vs"
6529 "seg2e32.v\013vsseg2e64.v\nvsseg2e8.v\013vsseg3e16.v\013vsseg3e32.v\013v"
6530 "sseg3e64.v\nvsseg3e8.v\013vsseg4e16.v\013vsseg4e32.v\013vsseg4e64.v\nvs"
6531 "seg4e8.v\013vsseg5e16.v\013vsseg5e32.v\013vsseg5e64.v\nvsseg5e8.v\013vs"
6532 "seg6e16.v\013vsseg6e32.v\013vsseg6e64.v\nvsseg6e8.v\013vsseg7e16.v\013v"
6533 "sseg7e32.v\013vsseg7e64.v\nvsseg7e8.v\013vsseg8e16.v\013vsseg8e32.v\013"
6534 "vsseg8e64.v\nvsseg8e8.v\010vssra.vi\010vssra.vv\010vssra.vx\010vssrl.vi"
6535 "\010vssrl.vv\010vssrl.vx\014vssseg2e16.v\014vssseg2e32.v\014vssseg2e64."
6536 "v\013vssseg2e8.v\014vssseg3e16.v\014vssseg3e32.v\014vssseg3e64.v\013vss"
6537 "seg3e8.v\014vssseg4e16.v\014vssseg4e32.v\014vssseg4e64.v\013vssseg4e8.v"
6538 "\014vssseg5e16.v\014vssseg5e32.v\014vssseg5e64.v\013vssseg5e8.v\014vsss"
6539 "eg6e16.v\014vssseg6e32.v\014vssseg6e64.v\013vssseg6e8.v\014vssseg7e16.v"
6540 "\014vssseg7e32.v\014vssseg7e64.v\013vssseg7e8.v\014vssseg8e16.v\014vsss"
6541 "eg8e32.v\014vssseg8e64.v\013vssseg8e8.v\010vssub.vv\010vssub.vx\tvssubu"
6542 ".vv\tvssubu.vx\007vsub.vv\007vsub.vx\nvsuxei16.v\nvsuxei32.v\nvsuxei64."
6543 "v\tvsuxei8.v\016vsuxseg2ei16.v\016vsuxseg2ei32.v\016vsuxseg2ei64.v\015v"
6544 "suxseg2ei8.v\016vsuxseg3ei16.v\016vsuxseg3ei32.v\016vsuxseg3ei64.v\015v"
6545 "suxseg3ei8.v\016vsuxseg4ei16.v\016vsuxseg4ei32.v\016vsuxseg4ei64.v\015v"
6546 "suxseg4ei8.v\016vsuxseg5ei16.v\016vsuxseg5ei32.v\016vsuxseg5ei64.v\015v"
6547 "suxseg5ei8.v\016vsuxseg6ei16.v\016vsuxseg6ei32.v\016vsuxseg6ei64.v\015v"
6548 "suxseg6ei8.v\016vsuxseg7ei16.v\016vsuxseg7ei32.v\016vsuxseg7ei64.v\015v"
6549 "suxseg7ei8.v\016vsuxseg8ei16.v\016vsuxseg8ei32.v\016vsuxseg8ei64.v\015v"
6550 "suxseg8ei8.v\010vt.maskc\tvt.maskcn\010vwadd.vv\010vwadd.vx\010vwadd.wv"
6551 "\010vwadd.wx\tvwaddu.vv\tvwaddu.vx\tvwaddu.wv\tvwaddu.wx\013vwcvt.x.x.v"
6552 "\014vwcvtu.x.x.v\tvwmacc.vv\tvwmacc.vx\013vwmaccsu.vv\013vwmaccsu.vx\nv"
6553 "wmaccu.vv\nvwmaccu.vx\013vwmaccus.vx\010vwmul.vv\010vwmul.vx\nvwmulsu.v"
6554 "v\nvwmulsu.vx\tvwmulu.vv\tvwmulu.vx\013vwredsum.vs\014vwredsumu.vs\010v"
6555 "wsll.vi\010vwsll.vv\010vwsll.vx\010vwsub.vv\010vwsub.vx\010vwsub.wv\010"
6556 "vwsub.wx\tvwsubu.vv\tvwsubu.vx\tvwsubu.wv\tvwsubu.wx\007vxor.vi\007vxor"
6557 ".vv\007vxor.vx\tvzext.vf2\tvzext.vf4\tvzext.vf8\004wadd\005wadda\006wad"
6558 "dau\005waddu\003wfi\005wmacc\007wmaccsu\006wmaccu\004wmul\006wmulsu\005"
6559 "wmulu\007wrs.nto\007wrs.sto\004wsla\005wslai\004wsll\005wslli\004wsub\005"
6560 "wsuba\006wsubau\005wsubu\007wzip16p\006wzip8p\004xnor\003xor\004xori\006"
6561 "xperm4\006xperm8\006zext.b\006zext.h\006zext.w\003zip\007zip16hp\006zip"
6562 "16p\006zip8hp\005zip8p";
6563
6564// Feature bitsets.
6565enum : uint8_t {
6566 AMFBS_None,
6567 AMFBS_HasHalfFPLoadStoreMove,
6568 AMFBS_HasStdExtD,
6569 AMFBS_HasStdExtF,
6570 AMFBS_HasStdExtFOrZfinx,
6571 AMFBS_HasStdExtH,
6572 AMFBS_HasStdExtM,
6573 AMFBS_HasStdExtP,
6574 AMFBS_HasStdExtQ,
6575 AMFBS_HasStdExtSmctrOrSsctr,
6576 AMFBS_HasStdExtSmrnmi,
6577 AMFBS_HasStdExtSvinval,
6578 AMFBS_HasStdExtZaamo,
6579 AMFBS_HasStdExtZabha,
6580 AMFBS_HasStdExtZacas,
6581 AMFBS_HasStdExtZalasr,
6582 AMFBS_HasStdExtZalrsc,
6583 AMFBS_HasStdExtZawrs,
6584 AMFBS_HasStdExtZba,
6585 AMFBS_HasStdExtZbb,
6586 AMFBS_HasStdExtZbbOrZbkb,
6587 AMFBS_HasStdExtZbc,
6588 AMFBS_HasStdExtZbcOrZbkc,
6589 AMFBS_HasStdExtZbkb,
6590 AMFBS_HasStdExtZbkbOrP,
6591 AMFBS_HasStdExtZbkx,
6592 AMFBS_HasStdExtZbs,
6593 AMFBS_HasStdExtZca,
6594 AMFBS_HasStdExtZcb,
6595 AMFBS_HasStdExtZcmop,
6596 AMFBS_HasStdExtZcmp,
6597 AMFBS_HasStdExtZcmt,
6598 AMFBS_HasStdExtZfa,
6599 AMFBS_HasStdExtZfbfmin,
6600 AMFBS_HasStdExtZfh,
6601 AMFBS_HasStdExtZfhmin,
6602 AMFBS_HasStdExtZfinx,
6603 AMFBS_HasStdExtZhinx,
6604 AMFBS_HasStdExtZhinxmin,
6605 AMFBS_HasStdExtZibi,
6606 AMFBS_HasStdExtZicbom,
6607 AMFBS_HasStdExtZicbop,
6608 AMFBS_HasStdExtZicboz,
6609 AMFBS_HasStdExtZicfiss,
6610 AMFBS_HasStdExtZicond,
6611 AMFBS_HasStdExtZimop,
6612 AMFBS_HasStdExtZknh,
6613 AMFBS_HasStdExtZksed,
6614 AMFBS_HasStdExtZksh,
6615 AMFBS_HasStdExtZmmul,
6616 AMFBS_HasStdExtZvbb,
6617 AMFBS_HasStdExtZvbcOrZvbc32e,
6618 AMFBS_HasStdExtZvfbfminOrZvfofp8min,
6619 AMFBS_HasStdExtZvfbfwma,
6620 AMFBS_HasStdExtZvfofp8min,
6621 AMFBS_HasStdExtZvkb,
6622 AMFBS_HasStdExtZvkg,
6623 AMFBS_HasStdExtZvkgs,
6624 AMFBS_HasStdExtZvkned,
6625 AMFBS_HasStdExtZvknhaOrZvknhb,
6626 AMFBS_HasStdExtZvksed,
6627 AMFBS_HasStdExtZvksh,
6628 AMFBS_HasStdExtZvqdotq,
6629 AMFBS_HasVInstructions,
6630 AMFBS_HasVInstructionsAnyF,
6631 AMFBS_HasVInstructionsI64,
6632 AMFBS_HasVendorXAndesBFHCvt,
6633 AMFBS_HasVendorXAndesPerf,
6634 AMFBS_HasVendorXAndesVBFHCvt,
6635 AMFBS_HasVendorXAndesVDot,
6636 AMFBS_HasVendorXAndesVPackFPH,
6637 AMFBS_HasVendorXAndesVSIntH,
6638 AMFBS_HasVendorXAndesVSIntLoad,
6639 AMFBS_HasVendorXMIPSCBOP,
6640 AMFBS_HasVendorXMIPSCMov,
6641 AMFBS_HasVendorXMIPSEXECTL,
6642 AMFBS_HasVendorXMIPSLSP,
6643 AMFBS_HasVendorXRivosVisni,
6644 AMFBS_HasVendorXRivosVizip,
6645 AMFBS_HasVendorXSMTVDot,
6646 AMFBS_HasVendorXSfcease,
6647 AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f,
6648 AMFBS_HasVendorXSfmm32a8f,
6649 AMFBS_HasVendorXSfmm32a8i,
6650 AMFBS_HasVendorXSfmmbase,
6651 AMFBS_HasVendorXSfvcp,
6652 AMFBS_HasVendorXSfvfexpAny,
6653 AMFBS_HasVendorXSfvfexpa,
6654 AMFBS_HasVendorXSfvfnrclipxfqf,
6655 AMFBS_HasVendorXSfvfwmaccqqq,
6656 AMFBS_HasVendorXSfvqmaccdod,
6657 AMFBS_HasVendorXSfvqmaccqoq,
6658 AMFBS_HasVendorXSiFivecdiscarddlone,
6659 AMFBS_HasVendorXSiFivecflushdlone,
6660 AMFBS_HasVendorXTHeadBa,
6661 AMFBS_HasVendorXTHeadBb,
6662 AMFBS_HasVendorXTHeadBs,
6663 AMFBS_HasVendorXTHeadCmo,
6664 AMFBS_HasVendorXTHeadCondMov,
6665 AMFBS_HasVendorXTHeadMac,
6666 AMFBS_HasVendorXTHeadMemIdx,
6667 AMFBS_HasVendorXTHeadMemPair,
6668 AMFBS_HasVendorXTHeadSync,
6669 AMFBS_HasVendorXTHeadVdot,
6670 AMFBS_HasVendorXVentanaCondOps,
6671 AMFBS_HasVendorXqccmp,
6672 AMFBS_HasVendorXwchc,
6673 AMFBS_HasXAIFET,
6674 AMFBS_IsRV32,
6675 AMFBS_IsRV64,
6676 AMFBS_HasStdExtCOrZcd_HasStdExtD,
6677 AMFBS_HasStdExtD_IsRV64,
6678 AMFBS_HasStdExtF_IsRV64,
6679 AMFBS_HasStdExtM_IsRV64,
6680 AMFBS_HasStdExtP_IsRV32,
6681 AMFBS_HasStdExtP_IsRV64,
6682 AMFBS_HasStdExtQ_IsRV64,
6683 AMFBS_HasStdExtZaamo_IsRV64,
6684 AMFBS_HasStdExtZabha_HasStdExtZacas,
6685 AMFBS_HasStdExtZacas_IsRV32,
6686 AMFBS_HasStdExtZacas_IsRV64,
6687 AMFBS_HasStdExtZalasr_IsRV64,
6688 AMFBS_HasStdExtZalrsc_IsRV64,
6689 AMFBS_HasStdExtZba_IsRV64,
6690 AMFBS_HasStdExtZbb_IsRV32,
6691 AMFBS_HasStdExtZbb_IsRV64,
6692 AMFBS_HasStdExtZbbOrZbkb_IsRV32,
6693 AMFBS_HasStdExtZbbOrZbkb_IsRV64,
6694 AMFBS_HasStdExtZbkb_IsRV32,
6695 AMFBS_HasStdExtZbkb_IsRV64,
6696 AMFBS_HasStdExtZca_IsRV32,
6697 AMFBS_HasStdExtZca_IsRV64,
6698 AMFBS_HasStdExtZcb_HasStdExtZbb,
6699 AMFBS_HasStdExtZcb_HasStdExtZmmul,
6700 AMFBS_HasStdExtZclsd_IsRV32,
6701 AMFBS_HasStdExtZdinx_IsRV32,
6702 AMFBS_HasStdExtZdinx_IsRV64,
6703 AMFBS_HasStdExtZfa_HasStdExtD,
6704 AMFBS_HasStdExtZfa_HasStdExtQ,
6705 AMFBS_HasStdExtZfa_HasStdExtZfh,
6706 AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh,
6707 AMFBS_HasStdExtZfh_IsRV64,
6708 AMFBS_HasStdExtZfhmin_HasStdExtD,
6709 AMFBS_HasStdExtZfinx_IsRV64,
6710 AMFBS_HasStdExtZhinx_IsRV64,
6711 AMFBS_HasStdExtZicfiss_IsRV64,
6712 AMFBS_HasStdExtZilsd_IsRV32,
6713 AMFBS_HasStdExtZknd_IsRV32,
6714 AMFBS_HasStdExtZknd_IsRV64,
6715 AMFBS_HasStdExtZkndOrZkne_IsRV64,
6716 AMFBS_HasStdExtZkne_IsRV32,
6717 AMFBS_HasStdExtZkne_IsRV64,
6718 AMFBS_HasStdExtZknh_IsRV32,
6719 AMFBS_HasStdExtZknh_IsRV64,
6720 AMFBS_HasStdExtZmmul_IsRV64,
6721 AMFBS_HasVInstructionsI64_IsRV64,
6722 AMFBS_HasVendorXAndesPerf_IsRV64,
6723 AMFBS_HasVendorXCValu_IsRV32,
6724 AMFBS_HasVendorXCVbi_IsRV32,
6725 AMFBS_HasVendorXCVbitmanip_IsRV32,
6726 AMFBS_HasVendorXCVelw_IsRV32,
6727 AMFBS_HasVendorXCVmac_IsRV32,
6728 AMFBS_HasVendorXCVmem_IsRV32,
6729 AMFBS_HasVendorXCVsimd_IsRV32,
6730 AMFBS_HasVendorXTHeadBb_IsRV64,
6731 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD,
6732 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF,
6733 AMFBS_HasVendorXTHeadMac_IsRV64,
6734 AMFBS_HasVendorXTHeadMemIdx_IsRV64,
6735 AMFBS_HasVendorXTHeadMemPair_IsRV64,
6736 AMFBS_HasVendorXqcia_IsRV32,
6737 AMFBS_HasVendorXqciac_IsRV32,
6738 AMFBS_HasVendorXqcibi_IsRV32,
6739 AMFBS_HasVendorXqcibm_IsRV32,
6740 AMFBS_HasVendorXqcicli_IsRV32,
6741 AMFBS_HasVendorXqcicm_IsRV32,
6742 AMFBS_HasVendorXqcics_IsRV32,
6743 AMFBS_HasVendorXqcicsr_IsRV32,
6744 AMFBS_HasVendorXqciint_IsRV32,
6745 AMFBS_HasVendorXqciio_IsRV32,
6746 AMFBS_HasVendorXqcilb_IsRV32,
6747 AMFBS_HasVendorXqcili_IsRV32,
6748 AMFBS_HasVendorXqcilia_IsRV32,
6749 AMFBS_HasVendorXqcilo_IsRV32,
6750 AMFBS_HasVendorXqcilsm_IsRV32,
6751 AMFBS_HasVendorXqcisim_IsRV32,
6752 AMFBS_HasVendorXqcisls_IsRV32,
6753 AMFBS_HasVendorXqcisync_IsRV32,
6754 AMFBS_IsRV64_HasStdExtH,
6755 AMFBS_IsRV64_HasVInstructionsI64,
6756 AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32,
6757 AMFBS_HasStdExtZbkb_NoStdExtZbb_IsRV64,
6758 AMFBS_HasStdExtZbkbOrP_NoStdExtZbb_IsRV32,
6759 AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64,
6760 AMFBS_HasStdExtZdinx_IsRV64_IsRV64,
6761 AMFBS_HasStdExtZfa_HasStdExtD_IsRV32,
6762 AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64,
6763 AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32,
6764 AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64,
6765 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64,
6766 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64,
6767};
6768
6769static constexpr FeatureBitset FeatureBitsets[] = {
6770 {}, // AMFBS_None
6771 {Feature_HasHalfFPLoadStoreMoveBit, },
6772 {Feature_HasStdExtDBit, },
6773 {Feature_HasStdExtFBit, },
6774 {Feature_HasStdExtFOrZfinxBit, },
6775 {Feature_HasStdExtHBit, },
6776 {Feature_HasStdExtMBit, },
6777 {Feature_HasStdExtPBit, },
6778 {Feature_HasStdExtQBit, },
6779 {Feature_HasStdExtSmctrOrSsctrBit, },
6780 {Feature_HasStdExtSmrnmiBit, },
6781 {Feature_HasStdExtSvinvalBit, },
6782 {Feature_HasStdExtZaamoBit, },
6783 {Feature_HasStdExtZabhaBit, },
6784 {Feature_HasStdExtZacasBit, },
6785 {Feature_HasStdExtZalasrBit, },
6786 {Feature_HasStdExtZalrscBit, },
6787 {Feature_HasStdExtZawrsBit, },
6788 {Feature_HasStdExtZbaBit, },
6789 {Feature_HasStdExtZbbBit, },
6790 {Feature_HasStdExtZbbOrZbkbBit, },
6791 {Feature_HasStdExtZbcBit, },
6792 {Feature_HasStdExtZbcOrZbkcBit, },
6793 {Feature_HasStdExtZbkbBit, },
6794 {Feature_HasStdExtZbkbOrPBit, },
6795 {Feature_HasStdExtZbkxBit, },
6796 {Feature_HasStdExtZbsBit, },
6797 {Feature_HasStdExtZcaBit, },
6798 {Feature_HasStdExtZcbBit, },
6799 {Feature_HasStdExtZcmopBit, },
6800 {Feature_HasStdExtZcmpBit, },
6801 {Feature_HasStdExtZcmtBit, },
6802 {Feature_HasStdExtZfaBit, },
6803 {Feature_HasStdExtZfbfminBit, },
6804 {Feature_HasStdExtZfhBit, },
6805 {Feature_HasStdExtZfhminBit, },
6806 {Feature_HasStdExtZfinxBit, },
6807 {Feature_HasStdExtZhinxBit, },
6808 {Feature_HasStdExtZhinxminBit, },
6809 {Feature_HasStdExtZibiBit, },
6810 {Feature_HasStdExtZicbomBit, },
6811 {Feature_HasStdExtZicbopBit, },
6812 {Feature_HasStdExtZicbozBit, },
6813 {Feature_HasStdExtZicfissBit, },
6814 {Feature_HasStdExtZicondBit, },
6815 {Feature_HasStdExtZimopBit, },
6816 {Feature_HasStdExtZknhBit, },
6817 {Feature_HasStdExtZksedBit, },
6818 {Feature_HasStdExtZkshBit, },
6819 {Feature_HasStdExtZmmulBit, },
6820 {Feature_HasStdExtZvbbBit, },
6821 {Feature_HasStdExtZvbcOrZvbc32eBit, },
6822 {Feature_HasStdExtZvfbfminOrZvfofp8minBit, },
6823 {Feature_HasStdExtZvfbfwmaBit, },
6824 {Feature_HasStdExtZvfofp8minBit, },
6825 {Feature_HasStdExtZvkbBit, },
6826 {Feature_HasStdExtZvkgBit, },
6827 {Feature_HasStdExtZvkgsBit, },
6828 {Feature_HasStdExtZvknedBit, },
6829 {Feature_HasStdExtZvknhaOrZvknhbBit, },
6830 {Feature_HasStdExtZvksedBit, },
6831 {Feature_HasStdExtZvkshBit, },
6832 {Feature_HasStdExtZvqdotqBit, },
6833 {Feature_HasVInstructionsBit, },
6834 {Feature_HasVInstructionsAnyFBit, },
6835 {Feature_HasVInstructionsI64Bit, },
6836 {Feature_HasVendorXAndesBFHCvtBit, },
6837 {Feature_HasVendorXAndesPerfBit, },
6838 {Feature_HasVendorXAndesVBFHCvtBit, },
6839 {Feature_HasVendorXAndesVDotBit, },
6840 {Feature_HasVendorXAndesVPackFPHBit, },
6841 {Feature_HasVendorXAndesVSIntHBit, },
6842 {Feature_HasVendorXAndesVSIntLoadBit, },
6843 {Feature_HasVendorXMIPSCBOPBit, },
6844 {Feature_HasVendorXMIPSCMovBit, },
6845 {Feature_HasVendorXMIPSEXECTLBit, },
6846 {Feature_HasVendorXMIPSLSPBit, },
6847 {Feature_HasVendorXRivosVisniBit, },
6848 {Feature_HasVendorXRivosVizipBit, },
6849 {Feature_HasVendorXSMTVDotBit, },
6850 {Feature_HasVendorXSfceaseBit, },
6851 {Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit, },
6852 {Feature_HasVendorXSfmm32a8fBit, },
6853 {Feature_HasVendorXSfmm32a8iBit, },
6854 {Feature_HasVendorXSfmmbaseBit, },
6855 {Feature_HasVendorXSfvcpBit, },
6856 {Feature_HasVendorXSfvfexpAnyBit, },
6857 {Feature_HasVendorXSfvfexpaBit, },
6858 {Feature_HasVendorXSfvfnrclipxfqfBit, },
6859 {Feature_HasVendorXSfvfwmaccqqqBit, },
6860 {Feature_HasVendorXSfvqmaccdodBit, },
6861 {Feature_HasVendorXSfvqmaccqoqBit, },
6862 {Feature_HasVendorXSiFivecdiscarddloneBit, },
6863 {Feature_HasVendorXSiFivecflushdloneBit, },
6864 {Feature_HasVendorXTHeadBaBit, },
6865 {Feature_HasVendorXTHeadBbBit, },
6866 {Feature_HasVendorXTHeadBsBit, },
6867 {Feature_HasVendorXTHeadCmoBit, },
6868 {Feature_HasVendorXTHeadCondMovBit, },
6869 {Feature_HasVendorXTHeadMacBit, },
6870 {Feature_HasVendorXTHeadMemIdxBit, },
6871 {Feature_HasVendorXTHeadMemPairBit, },
6872 {Feature_HasVendorXTHeadSyncBit, },
6873 {Feature_HasVendorXTHeadVdotBit, },
6874 {Feature_HasVendorXVentanaCondOpsBit, },
6875 {Feature_HasVendorXqccmpBit, },
6876 {Feature_HasVendorXwchcBit, },
6877 {Feature_HasXAIFETBit, },
6878 {Feature_IsRV32Bit, },
6879 {Feature_IsRV64Bit, },
6880 {Feature_HasStdExtCOrZcdBit, Feature_HasStdExtDBit, },
6881 {Feature_HasStdExtDBit, Feature_IsRV64Bit, },
6882 {Feature_HasStdExtFBit, Feature_IsRV64Bit, },
6883 {Feature_HasStdExtMBit, Feature_IsRV64Bit, },
6884 {Feature_HasStdExtPBit, Feature_IsRV32Bit, },
6885 {Feature_HasStdExtPBit, Feature_IsRV64Bit, },
6886 {Feature_HasStdExtQBit, Feature_IsRV64Bit, },
6887 {Feature_HasStdExtZaamoBit, Feature_IsRV64Bit, },
6888 {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, },
6889 {Feature_HasStdExtZacasBit, Feature_IsRV32Bit, },
6890 {Feature_HasStdExtZacasBit, Feature_IsRV64Bit, },
6891 {Feature_HasStdExtZalasrBit, Feature_IsRV64Bit, },
6892 {Feature_HasStdExtZalrscBit, Feature_IsRV64Bit, },
6893 {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, },
6894 {Feature_HasStdExtZbbBit, Feature_IsRV32Bit, },
6895 {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, },
6896 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, },
6897 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, },
6898 {Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, },
6899 {Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, },
6900 {Feature_HasStdExtZcaBit, Feature_IsRV32Bit, },
6901 {Feature_HasStdExtZcaBit, Feature_IsRV64Bit, },
6902 {Feature_HasStdExtZcbBit, Feature_HasStdExtZbbBit, },
6903 {Feature_HasStdExtZcbBit, Feature_HasStdExtZmmulBit, },
6904 {Feature_HasStdExtZclsdBit, Feature_IsRV32Bit, },
6905 {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, },
6906 {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, },
6907 {Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, },
6908 {Feature_HasStdExtZfaBit, Feature_HasStdExtQBit, },
6909 {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, },
6910 {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhOrZvfhBit, },
6911 {Feature_HasStdExtZfhBit, Feature_IsRV64Bit, },
6912 {Feature_HasStdExtZfhminBit, Feature_HasStdExtDBit, },
6913 {Feature_HasStdExtZfinxBit, Feature_IsRV64Bit, },
6914 {Feature_HasStdExtZhinxBit, Feature_IsRV64Bit, },
6915 {Feature_HasStdExtZicfissBit, Feature_IsRV64Bit, },
6916 {Feature_HasStdExtZilsdBit, Feature_IsRV32Bit, },
6917 {Feature_HasStdExtZkndBit, Feature_IsRV32Bit, },
6918 {Feature_HasStdExtZkndBit, Feature_IsRV64Bit, },
6919 {Feature_HasStdExtZkndOrZkneBit, Feature_IsRV64Bit, },
6920 {Feature_HasStdExtZkneBit, Feature_IsRV32Bit, },
6921 {Feature_HasStdExtZkneBit, Feature_IsRV64Bit, },
6922 {Feature_HasStdExtZknhBit, Feature_IsRV32Bit, },
6923 {Feature_HasStdExtZknhBit, Feature_IsRV64Bit, },
6924 {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, },
6925 {Feature_HasVInstructionsI64Bit, Feature_IsRV64Bit, },
6926 {Feature_HasVendorXAndesPerfBit, Feature_IsRV64Bit, },
6927 {Feature_HasVendorXCValuBit, Feature_IsRV32Bit, },
6928 {Feature_HasVendorXCVbiBit, Feature_IsRV32Bit, },
6929 {Feature_HasVendorXCVbitmanipBit, Feature_IsRV32Bit, },
6930 {Feature_HasVendorXCVelwBit, Feature_IsRV32Bit, },
6931 {Feature_HasVendorXCVmacBit, Feature_IsRV32Bit, },
6932 {Feature_HasVendorXCVmemBit, Feature_IsRV32Bit, },
6933 {Feature_HasVendorXCVsimdBit, Feature_IsRV32Bit, },
6934 {Feature_HasVendorXTHeadBbBit, Feature_IsRV64Bit, },
6935 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, },
6936 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, },
6937 {Feature_HasVendorXTHeadMacBit, Feature_IsRV64Bit, },
6938 {Feature_HasVendorXTHeadMemIdxBit, Feature_IsRV64Bit, },
6939 {Feature_HasVendorXTHeadMemPairBit, Feature_IsRV64Bit, },
6940 {Feature_HasVendorXqciaBit, Feature_IsRV32Bit, },
6941 {Feature_HasVendorXqciacBit, Feature_IsRV32Bit, },
6942 {Feature_HasVendorXqcibiBit, Feature_IsRV32Bit, },
6943 {Feature_HasVendorXqcibmBit, Feature_IsRV32Bit, },
6944 {Feature_HasVendorXqcicliBit, Feature_IsRV32Bit, },
6945 {Feature_HasVendorXqcicmBit, Feature_IsRV32Bit, },
6946 {Feature_HasVendorXqcicsBit, Feature_IsRV32Bit, },
6947 {Feature_HasVendorXqcicsrBit, Feature_IsRV32Bit, },
6948 {Feature_HasVendorXqciintBit, Feature_IsRV32Bit, },
6949 {Feature_HasVendorXqciioBit, Feature_IsRV32Bit, },
6950 {Feature_HasVendorXqcilbBit, Feature_IsRV32Bit, },
6951 {Feature_HasVendorXqciliBit, Feature_IsRV32Bit, },
6952 {Feature_HasVendorXqciliaBit, Feature_IsRV32Bit, },
6953 {Feature_HasVendorXqciloBit, Feature_IsRV32Bit, },
6954 {Feature_HasVendorXqcilsmBit, Feature_IsRV32Bit, },
6955 {Feature_HasVendorXqcisimBit, Feature_IsRV32Bit, },
6956 {Feature_HasVendorXqcislsBit, Feature_IsRV32Bit, },
6957 {Feature_HasVendorXqcisyncBit, Feature_IsRV32Bit, },
6958 {Feature_IsRV64Bit, Feature_HasStdExtHBit, },
6959 {Feature_IsRV64Bit, Feature_HasVInstructionsI64Bit, },
6960 {Feature_HasStdExtCOrZcfOrZceBit, Feature_HasStdExtFBit, Feature_IsRV32Bit, },
6961 {Feature_HasStdExtZbkbBit, Feature_NoStdExtZbbBit, Feature_IsRV64Bit, },
6962 {Feature_HasStdExtZbkbOrPBit, Feature_NoStdExtZbbBit, Feature_IsRV32Bit, },
6963 {Feature_HasStdExtZcbBit, Feature_HasStdExtZbaBit, Feature_IsRV64Bit, },
6964 {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, Feature_IsRV64Bit, },
6965 {Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, Feature_IsRV32Bit, },
6966 {Feature_HasStdExtZfaBit, Feature_HasStdExtQBit, Feature_IsRV64Bit, },
6967 {Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, },
6968 {Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, },
6969 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, Feature_IsRV64Bit, },
6970 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, Feature_IsRV64Bit, },
6971};
6972
6973namespace {
6974 struct MatchEntry {
6975 uint16_t Mnemonic;
6976 uint16_t Opcode;
6977 uint16_t ConvertFn;
6978 uint8_t RequiredFeaturesIdx;
6979 uint16_t Classes[8];
6980 StringRef getMnemonic() const {
6981 return StringRef(MnemonicTable + Mnemonic + 1,
6982 MnemonicTable[Mnemonic]);
6983 }
6984 };
6985
6986 // Predicate for searching for an opcode.
6987 struct LessOpcode {
6988 bool operator()(const MatchEntry &LHS, StringRef RHS) {
6989 return LHS.getMnemonic() < RHS;
6990 }
6991 bool operator()(StringRef LHS, const MatchEntry &RHS) {
6992 return LHS < RHS.getMnemonic();
6993 }
6994 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
6995 return LHS.getMnemonic() < RHS.getMnemonic();
6996 }
6997 };
6998} // end anonymous namespace
6999
7000static const MatchEntry MatchTable0[] = {
7001 { 0 /* .insn_b */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_BareSImm13Lsb0 }, },
7002 { 8 /* .insn_ca */, RISCV::InsnCA, Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm6, MCK_UImm2, MCK_AnyRegCOperand, MCK_AnyRegCOperand }, },
7003 { 17 /* .insn_cb */, RISCV::InsnCB, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_BareSImm9Lsb0 }, },
7004 { 26 /* .insn_ci */, RISCV::InsnCI, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm6 }, },
7005 { 35 /* .insn_ciw */, RISCV::InsnCIW, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm8 }, },
7006 { 45 /* .insn_cj */, RISCV::InsnCJ, Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_BareSImm12Lsb0 }, },
7007 { 54 /* .insn_cl */, RISCV::InsnCL, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7008 { 54 /* .insn_cl */, RISCV::InsnCL, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7009 { 63 /* .insn_cr */, RISCV::InsnCR, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm4, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7010 { 72 /* .insn_cs */, RISCV::InsnCS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7011 { 72 /* .insn_cs */, RISCV::InsnCS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7012 { 81 /* .insn_css */, RISCV::InsnCSS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_UImm6 }, },
7013 { 91 /* .insn_i */, RISCV::InsnI, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm12LO }, },
7014 { 91 /* .insn_i */, RISCV::InsnI_Mem, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7015 { 91 /* .insn_i */, RISCV::InsnI_Mem, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm12LO1_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm12LO, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7016 { 99 /* .insn_j */, RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_BareSImm21Lsb0 }, },
7017 { 107 /* .insn_qc.eai */, RISCV::InsnQC_EAI, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm1, MCK_AnyRegOperand, MCK_BareSImm32 }, },
7018 { 120 /* .insn_qc.eb */, RISCV::InsnQC_EB, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm5, MCK_AnyRegOperand, MCK_SImm16, MCK_BareSImm13Lsb0 }, },
7019 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm26 }, },
7020 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI_Mem, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_5__imm_95_0, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7021 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI_Mem, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__SImm261_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_SImm26, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7022 { 144 /* .insn_qc.ej */, RISCV::InsnQC_EJ, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_UImm5, MCK_BareSImm32Lsb0 }, },
7023 { 156 /* .insn_qc.es */, RISCV::InsnQC_ES, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_5__imm_95_0, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7024 { 156 /* .insn_qc.es */, RISCV::InsnQC_ES, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__SImm261_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_SImm26, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7025 { 168 /* .insn_r */, RISCV::InsnR, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm7, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7026 { 168 /* .insn_r */, RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7027 { 176 /* .insn_r4 */, RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7028 { 185 /* .insn_s */, RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7029 { 185 /* .insn_s */, RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm12LO1_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm12LO, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7030 { 193 /* .insn_sb */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_BareSImm13Lsb0 }, },
7031 { 202 /* .insn_u */, RISCV::InsnU, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_UImm20LUI }, },
7032 { 210 /* .insn_uj */, RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_BareSImm21Lsb0 }, },
7033 { 219 /* aadd */, RISCV::AADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7034 { 224 /* aaddu */, RISCV::AADDU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7035 { 230 /* abs */, RISCV::ABS, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
7036 { 234 /* absw */, RISCV::ABSW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
7037 { 239 /* add */, RISCV::ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7038 { 239 /* add */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7039 { 239 /* add */, RISCV::PseudoAddTPRel, Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_TPRelAddSymbol }, },
7040 { 243 /* add.uw */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7041 { 250 /* addd */, RISCV::ADDD, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
7042 { 255 /* addi */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7043 { 260 /* addiw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7044 { 266 /* addw */, RISCV::ADDW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7045 { 266 /* addw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7046 { 271 /* aes32dsi */, RISCV::AES32DSI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7047 { 280 /* aes32dsmi */, RISCV::AES32DSMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7048 { 290 /* aes32esi */, RISCV::AES32ESI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7049 { 299 /* aes32esmi */, RISCV::AES32ESMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7050 { 309 /* aes64ds */, RISCV::AES64DS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7051 { 317 /* aes64dsm */, RISCV::AES64DSM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7052 { 326 /* aes64es */, RISCV::AES64ES, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7053 { 334 /* aes64esm */, RISCV::AES64ESM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7054 { 343 /* aes64im */, RISCV::AES64IM, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR }, },
7055 { 351 /* aes64ks1i */, RISCV::AES64KS1I, Convert__Reg1_0__Reg1_1__RnumArg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_RnumArg }, },
7056 { 361 /* aes64ks2 */, RISCV::AES64KS2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7057 { 370 /* aif.amoaddg.d */, RISCV::AIF_AMOADDG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7058 { 384 /* aif.amoaddg.w */, RISCV::AIF_AMOADDG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7059 { 398 /* aif.amoaddl.d */, RISCV::AIF_AMOADDL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7060 { 412 /* aif.amoaddl.w */, RISCV::AIF_AMOADDL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7061 { 426 /* aif.amoandg.d */, RISCV::AIF_AMOANDG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7062 { 440 /* aif.amoandg.w */, RISCV::AIF_AMOANDG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7063 { 454 /* aif.amoandl.d */, RISCV::AIF_AMOANDL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7064 { 468 /* aif.amoandl.w */, RISCV::AIF_AMOANDL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7065 { 482 /* aif.amocmpswapg.d */, RISCV::AIF_AMOCMPSWAPG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7066 { 500 /* aif.amocmpswapg.w */, RISCV::AIF_AMOCMPSWAPG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7067 { 518 /* aif.amocmpswapl.d */, RISCV::AIF_AMOCMPSWAPL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7068 { 536 /* aif.amocmpswapl.w */, RISCV::AIF_AMOCMPSWAPL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7069 { 554 /* aif.amomaxg.d */, RISCV::AIF_AMOMAXG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7070 { 568 /* aif.amomaxg.w */, RISCV::AIF_AMOMAXG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7071 { 582 /* aif.amomaxl.d */, RISCV::AIF_AMOMAXL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7072 { 596 /* aif.amomaxl.w */, RISCV::AIF_AMOMAXL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7073 { 610 /* aif.amomaxug.d */, RISCV::AIF_AMOMAXUG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7074 { 625 /* aif.amomaxug.w */, RISCV::AIF_AMOMAXUG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7075 { 640 /* aif.amomaxul.d */, RISCV::AIF_AMOMAXUL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7076 { 655 /* aif.amomaxul.w */, RISCV::AIF_AMOMAXUL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7077 { 670 /* aif.amoming.d */, RISCV::AIF_AMOMING_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7078 { 684 /* aif.amoming.w */, RISCV::AIF_AMOMING_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7079 { 698 /* aif.amominl.d */, RISCV::AIF_AMOMINL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7080 { 712 /* aif.amominl.w */, RISCV::AIF_AMOMINL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7081 { 726 /* aif.amominug.d */, RISCV::AIF_AMOMINUG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7082 { 741 /* aif.amominug.w */, RISCV::AIF_AMOMINUG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7083 { 756 /* aif.amominul.d */, RISCV::AIF_AMOMINUL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7084 { 771 /* aif.amominul.w */, RISCV::AIF_AMOMINUL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7085 { 786 /* aif.amoorg.d */, RISCV::AIF_AMOORG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7086 { 799 /* aif.amoorg.w */, RISCV::AIF_AMOORG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7087 { 812 /* aif.amoorl.d */, RISCV::AIF_AMOORL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7088 { 825 /* aif.amoorl.w */, RISCV::AIF_AMOORL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7089 { 838 /* aif.amoswapg.d */, RISCV::AIF_AMOSWAPG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7090 { 853 /* aif.amoswapg.w */, RISCV::AIF_AMOSWAPG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7091 { 868 /* aif.amoswapl.d */, RISCV::AIF_AMOSWAPL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7092 { 883 /* aif.amoswapl.w */, RISCV::AIF_AMOSWAPL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7093 { 898 /* aif.amoxorg.d */, RISCV::AIF_AMOXORG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7094 { 912 /* aif.amoxorg.w */, RISCV::AIF_AMOXORG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7095 { 926 /* aif.amoxorl.d */, RISCV::AIF_AMOXORL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7096 { 940 /* aif.amoxorl.w */, RISCV::AIF_AMOXORL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7097 { 954 /* aif.bitmixb */, RISCV::AIF_BITMIXB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7098 { 966 /* aif.cubeface.ps */, RISCV::AIF_CUBEFACE_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7099 { 982 /* aif.cubefaceidx.ps */, RISCV::AIF_CUBEFACEIDX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7100 { 1001 /* aif.cubesgnsc.ps */, RISCV::AIF_CUBESGNSC_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7101 { 1018 /* aif.cubesgntc.ps */, RISCV::AIF_CUBESGNTC_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7102 { 1035 /* aif.fadd.pi */, RISCV::AIF_FADD_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7103 { 1047 /* aif.fadd.ps */, RISCV::AIF_FADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7104 { 1059 /* aif.faddi.pi */, RISCV::AIF_FADDI_PI, Convert__Reg1_0__Reg1_1__SImm101_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_SImm10 }, },
7105 { 1072 /* aif.famoaddg.pi */, RISCV::AIF_FAMOADDG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7106 { 1088 /* aif.famoaddl.pi */, RISCV::AIF_FAMOADDL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7107 { 1104 /* aif.famoandg.pi */, RISCV::AIF_FAMOANDG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7108 { 1120 /* aif.famoandl.pi */, RISCV::AIF_FAMOANDL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7109 { 1136 /* aif.famomaxg.pi */, RISCV::AIF_FAMOMAXG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7110 { 1152 /* aif.famomaxg.ps */, RISCV::AIF_FAMOMAXG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7111 { 1168 /* aif.famomaxl.pi */, RISCV::AIF_FAMOMAXL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7112 { 1184 /* aif.famomaxl.ps */, RISCV::AIF_FAMOMAXL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7113 { 1200 /* aif.famomaxug.pi */, RISCV::AIF_FAMOMAXUG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7114 { 1217 /* aif.famomaxul.pi */, RISCV::AIF_FAMOMAXUL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7115 { 1234 /* aif.famoming.pi */, RISCV::AIF_FAMOMING_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7116 { 1250 /* aif.famoming.ps */, RISCV::AIF_FAMOMING_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7117 { 1266 /* aif.famominl.pi */, RISCV::AIF_FAMOMINL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7118 { 1282 /* aif.famominl.ps */, RISCV::AIF_FAMOMINL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7119 { 1298 /* aif.famominug.pi */, RISCV::AIF_FAMOMINUG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7120 { 1315 /* aif.famominul.pi */, RISCV::AIF_FAMOMINUL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7121 { 1332 /* aif.famoorg.pi */, RISCV::AIF_FAMOORG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7122 { 1347 /* aif.famoorl.pi */, RISCV::AIF_FAMOORL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7123 { 1362 /* aif.famoswapg.pi */, RISCV::AIF_FAMOSWAPG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7124 { 1379 /* aif.famoswapl.pi */, RISCV::AIF_FAMOSWAPL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7125 { 1396 /* aif.famoxorg.pi */, RISCV::AIF_FAMOXORG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7126 { 1412 /* aif.famoxorl.pi */, RISCV::AIF_FAMOXORL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7127 { 1428 /* aif.fand.pi */, RISCV::AIF_FAND_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7128 { 1440 /* aif.fandi.pi */, RISCV::AIF_FANDI_PI, Convert__Reg1_0__Reg1_1__SImm101_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_SImm10 }, },
7129 { 1453 /* aif.fbc.ps */, RISCV::AIF_FBC_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7130 { 1464 /* aif.fbci.pi */, RISCV::AIF_FBCI_PI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_UImm20LUI }, },
7131 { 1476 /* aif.fbci.ps */, RISCV::AIF_FBCI_PS, Convert__Reg1_0__UImm20LUI1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_UImm20LUI }, },
7132 { 1488 /* aif.fbcx.ps */, RISCV::AIF_FBCX_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR }, },
7133 { 1500 /* aif.fclass.ps */, RISCV::AIF_FCLASS_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7134 { 1514 /* aif.fcmov.ps */, RISCV::AIF_FCMOV_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7135 { 1527 /* aif.fcmovm.ps */, RISCV::AIF_FCMOVM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7136 { 1541 /* aif.fcvt.f10.ps */, RISCV::AIF_FCVT_F10_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7137 { 1557 /* aif.fcvt.f11.ps */, RISCV::AIF_FCVT_F11_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7138 { 1573 /* aif.fcvt.f16.ps */, RISCV::AIF_FCVT_F16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7139 { 1589 /* aif.fcvt.ps.f10 */, RISCV::AIF_FCVT_PS_F10, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7140 { 1605 /* aif.fcvt.ps.f11 */, RISCV::AIF_FCVT_PS_F11, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7141 { 1621 /* aif.fcvt.ps.f16 */, RISCV::AIF_FCVT_PS_F16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7142 { 1637 /* aif.fcvt.ps.pw */, RISCV::AIF_FCVT_PS_PW, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7143 { 1652 /* aif.fcvt.ps.pwu */, RISCV::AIF_FCVT_PS_PWU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7144 { 1668 /* aif.fcvt.ps.rast */, RISCV::AIF_FCVT_PS_RAST, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7145 { 1685 /* aif.fcvt.ps.sn16 */, RISCV::AIF_FCVT_PS_SN16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7146 { 1702 /* aif.fcvt.ps.sn8 */, RISCV::AIF_FCVT_PS_SN8, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7147 { 1718 /* aif.fcvt.ps.un10 */, RISCV::AIF_FCVT_PS_UN10, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7148 { 1735 /* aif.fcvt.ps.un16 */, RISCV::AIF_FCVT_PS_UN16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7149 { 1752 /* aif.fcvt.ps.un2 */, RISCV::AIF_FCVT_PS_UN2, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7150 { 1768 /* aif.fcvt.ps.un24 */, RISCV::AIF_FCVT_PS_UN24, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7151 { 1785 /* aif.fcvt.ps.un8 */, RISCV::AIF_FCVT_PS_UN8, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7152 { 1801 /* aif.fcvt.pw.ps */, RISCV::AIF_FCVT_PW_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7153 { 1816 /* aif.fcvt.pwu.ps */, RISCV::AIF_FCVT_PWU_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7154 { 1832 /* aif.fcvt.rast.ps */, RISCV::AIF_FCVT_RAST_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7155 { 1849 /* aif.fcvt.sn16.ps */, RISCV::AIF_FCVT_SN16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7156 { 1866 /* aif.fcvt.sn8.ps */, RISCV::AIF_FCVT_SN8_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7157 { 1882 /* aif.fcvt.un10.ps */, RISCV::AIF_FCVT_UN10_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7158 { 1899 /* aif.fcvt.un16.ps */, RISCV::AIF_FCVT_UN16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7159 { 1916 /* aif.fcvt.un2.ps */, RISCV::AIF_FCVT_UN2_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7160 { 1932 /* aif.fcvt.un24.ps */, RISCV::AIF_FCVT_UN24_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7161 { 1949 /* aif.fcvt.un8.ps */, RISCV::AIF_FCVT_UN8_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7162 { 1965 /* aif.fdiv.pi */, RISCV::AIF_FDIV_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7163 { 1977 /* aif.fdiv.ps */, RISCV::AIF_FDIV_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7164 { 1989 /* aif.fdivu.pi */, RISCV::AIF_FDIVU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7165 { 2002 /* aif.feq.pi */, RISCV::AIF_FEQ_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7166 { 2013 /* aif.feq.ps */, RISCV::AIF_FEQ_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7167 { 2024 /* aif.feqm.ps */, RISCV::AIF_FEQM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7168 { 2036 /* aif.fexp.ps */, RISCV::AIF_FEXP_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7169 { 2048 /* aif.ffrc.ps */, RISCV::AIF_FFRC_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7170 { 2060 /* aif.fg32b.ps */, RISCV::AIF_FG32B_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7171 { 2073 /* aif.fg32h.ps */, RISCV::AIF_FG32H_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7172 { 2086 /* aif.fg32w.ps */, RISCV::AIF_FG32W_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7173 { 2099 /* aif.fgb.ps */, RISCV::AIF_FGB_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7174 { 2110 /* aif.fgbg.ps */, RISCV::AIF_FGBG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7175 { 2122 /* aif.fgbl.ps */, RISCV::AIF_FGBL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7176 { 2134 /* aif.fgh.ps */, RISCV::AIF_FGH_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7177 { 2145 /* aif.fghg.ps */, RISCV::AIF_FGHG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7178 { 2157 /* aif.fghl.ps */, RISCV::AIF_FGHL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7179 { 2169 /* aif.fgw.ps */, RISCV::AIF_FGW_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7180 { 2180 /* aif.fgwg.ps */, RISCV::AIF_FGWG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7181 { 2192 /* aif.fgwl.ps */, RISCV::AIF_FGWL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7182 { 2204 /* aif.fle.pi */, RISCV::AIF_FLE_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7183 { 2215 /* aif.fle.ps */, RISCV::AIF_FLE_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7184 { 2226 /* aif.flem.ps */, RISCV::AIF_FLEM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7185 { 2238 /* aif.flog.ps */, RISCV::AIF_FLOG_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7186 { 2250 /* aif.flq2 */, RISCV::AIF_FLQ2, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7187 { 2259 /* aif.flt.pi */, RISCV::AIF_FLT_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7188 { 2270 /* aif.flt.ps */, RISCV::AIF_FLT_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7189 { 2281 /* aif.fltm.pi */, RISCV::AIF_FLTM_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7190 { 2293 /* aif.fltm.ps */, RISCV::AIF_FLTM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7191 { 2305 /* aif.fltu.pi */, RISCV::AIF_FLTU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7192 { 2317 /* aif.flw.ps */, RISCV::AIF_FLW_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7193 { 2328 /* aif.flwg.ps */, RISCV::AIF_FLWG_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7194 { 2340 /* aif.flwl.ps */, RISCV::AIF_FLWL_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7195 { 2352 /* aif.fmadd.ps */, RISCV::AIF_FMADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7196 { 2365 /* aif.fmax.pi */, RISCV::AIF_FMAX_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7197 { 2377 /* aif.fmax.ps */, RISCV::AIF_FMAX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7198 { 2389 /* aif.fmaxu.pi */, RISCV::AIF_FMAXU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7199 { 2402 /* aif.fmin.pi */, RISCV::AIF_FMIN_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7200 { 2414 /* aif.fmin.ps */, RISCV::AIF_FMIN_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7201 { 2426 /* aif.fminu.pi */, RISCV::AIF_FMINU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7202 { 2439 /* aif.fmsub.ps */, RISCV::AIF_FMSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7203 { 2452 /* aif.fmul.pi */, RISCV::AIF_FMUL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7204 { 2464 /* aif.fmul.ps */, RISCV::AIF_FMUL_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7205 { 2476 /* aif.fmulh.pi */, RISCV::AIF_FMULH_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7206 { 2489 /* aif.fmulhu.pi */, RISCV::AIF_FMULHU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7207 { 2503 /* aif.fmvs.x.ps */, RISCV::AIF_FMVS_X_PS, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_FPR256, MCK_UImm3 }, },
7208 { 2517 /* aif.fmvz.x.ps */, RISCV::AIF_FMVZ_X_PS, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_FPR256, MCK_UImm3 }, },
7209 { 2531 /* aif.fnmadd.ps */, RISCV::AIF_FNMADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7210 { 2545 /* aif.fnmsub.ps */, RISCV::AIF_FNMSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7211 { 2559 /* aif.fnot.pi */, RISCV::AIF_FNOT_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7212 { 2571 /* aif.for.pi */, RISCV::AIF_FOR_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7213 { 2582 /* aif.fpackrepb.pi */, RISCV::AIF_FPACKREPB_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7214 { 2599 /* aif.fpackreph.pi */, RISCV::AIF_FPACKREPH_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7215 { 2616 /* aif.frcp.ps */, RISCV::AIF_FRCP_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7216 { 2628 /* aif.frcp_fix.rast */, RISCV::AIF_FRCP_FIX_RAST, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7217 { 2646 /* aif.frem.pi */, RISCV::AIF_FREM_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7218 { 2658 /* aif.fremu.pi */, RISCV::AIF_FREMU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7219 { 2671 /* aif.fround.ps */, RISCV::AIF_FROUND_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7220 { 2685 /* aif.frsq.ps */, RISCV::AIF_FRSQ_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7221 { 2697 /* aif.fsat8.pi */, RISCV::AIF_FSAT8_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7222 { 2710 /* aif.fsatu8.pi */, RISCV::AIF_FSATU8_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7223 { 2724 /* aif.fsc32b.ps */, RISCV::AIF_FSC32B_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7224 { 2738 /* aif.fsc32h.ps */, RISCV::AIF_FSC32H_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7225 { 2752 /* aif.fsc32w.ps */, RISCV::AIF_FSC32W_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7226 { 2766 /* aif.fscb.ps */, RISCV::AIF_FSCB_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7227 { 2778 /* aif.fscbg.ps */, RISCV::AIF_FSCBG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7228 { 2791 /* aif.fscbl.ps */, RISCV::AIF_FSCBL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7229 { 2804 /* aif.fsch.ps */, RISCV::AIF_FSCH_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7230 { 2816 /* aif.fschg.ps */, RISCV::AIF_FSCHG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7231 { 2829 /* aif.fschl.ps */, RISCV::AIF_FSCHL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7232 { 2842 /* aif.fscw.ps */, RISCV::AIF_FSCW_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7233 { 2854 /* aif.fscwg.ps */, RISCV::AIF_FSCWG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7234 { 2867 /* aif.fscwl.ps */, RISCV::AIF_FSCWL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7235 { 2880 /* aif.fsetm.pi */, RISCV::AIF_FSETM_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256 }, },
7236 { 2893 /* aif.fsgnj.ps */, RISCV::AIF_FSGNJ_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7237 { 2906 /* aif.fsgnjn.ps */, RISCV::AIF_FSGNJN_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7238 { 2920 /* aif.fsgnjx.ps */, RISCV::AIF_FSGNJX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7239 { 2934 /* aif.fsin.ps */, RISCV::AIF_FSIN_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7240 { 2946 /* aif.fsll.pi */, RISCV::AIF_FSLL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7241 { 2958 /* aif.fslli.pi */, RISCV::AIF_FSLLI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
7242 { 2971 /* aif.fsq2 */, RISCV::AIF_FSQ2, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7243 { 2980 /* aif.fsqrt.ps */, RISCV::AIF_FSQRT_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7244 { 2993 /* aif.fsra.pi */, RISCV::AIF_FSRA_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7245 { 3005 /* aif.fsrai.pi */, RISCV::AIF_FSRAI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
7246 { 3018 /* aif.fsrl.pi */, RISCV::AIF_FSRL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7247 { 3030 /* aif.fsrli.pi */, RISCV::AIF_FSRLI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
7248 { 3043 /* aif.fsub.pi */, RISCV::AIF_FSUB_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7249 { 3055 /* aif.fsub.ps */, RISCV::AIF_FSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7250 { 3067 /* aif.fsw.ps */, RISCV::AIF_FSW_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7251 { 3078 /* aif.fswg.ps */, RISCV::AIF_FSWG_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7252 { 3090 /* aif.fswizz.ps */, RISCV::AIF_FSWIZZ_PS, Convert__Reg1_0__Reg1_1__UImm81_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm8 }, },
7253 { 3104 /* aif.fswl.ps */, RISCV::AIF_FSWL_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7254 { 3116 /* aif.fxor.pi */, RISCV::AIF_FXOR_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7255 { 3128 /* aif.maskand */, RISCV::AIF_MASKAND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
7256 { 3140 /* aif.masknot */, RISCV::AIF_MASKNOT, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_MR, MCK_MR }, },
7257 { 3152 /* aif.maskor */, RISCV::AIF_MASKOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
7258 { 3163 /* aif.maskpopc */, RISCV::AIF_MASKPOPC, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_MR }, },
7259 { 3176 /* aif.maskpopc.rast */, RISCV::AIF_MASKPOPC_ET_RAST, Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR, MCK_UImm4 }, },
7260 { 3194 /* aif.maskpopcz */, RISCV::AIF_MASKPOPCZ, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_MR }, },
7261 { 3208 /* aif.maskxor */, RISCV::AIF_MASKXOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
7262 { 3220 /* aif.mov.m.x */, RISCV::AIF_MOV_M_X, Convert__Reg1_0__Reg1_1__UImm81_2, AMFBS_HasXAIFET, { MCK_MR, MCK_GPR, MCK_UImm8 }, },
7263 { 3232 /* aif.mova.m.x */, RISCV::AIF_MOVA_M_X, Convert__Reg1_0, AMFBS_HasXAIFET, { MCK_GPR }, },
7264 { 3245 /* aif.mova.x.m */, RISCV::AIF_MOVA_X_M, Convert__Reg1_0, AMFBS_HasXAIFET, { MCK_GPR }, },
7265 { 3258 /* aif.packb */, RISCV::AIF_PACKB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7266 { 3268 /* aif.sbg */, RISCV::AIF_SBG, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7267 { 3276 /* aif.sbl */, RISCV::AIF_SBL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7268 { 3284 /* aif.shg */, RISCV::AIF_SHG, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7269 { 3292 /* aif.shl */, RISCV::AIF_SHL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7270 { 3300 /* amoadd.b */, RISCV::AMOADD_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7271 { 3309 /* amoadd.b.aq */, RISCV::AMOADD_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7272 { 3321 /* amoadd.b.aqrl */, RISCV::AMOADD_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7273 { 3335 /* amoadd.b.rl */, RISCV::AMOADD_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7274 { 3347 /* amoadd.d */, RISCV::AMOADD_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7275 { 3356 /* amoadd.d.aq */, RISCV::AMOADD_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7276 { 3368 /* amoadd.d.aqrl */, RISCV::AMOADD_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7277 { 3382 /* amoadd.d.rl */, RISCV::AMOADD_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7278 { 3394 /* amoadd.h */, RISCV::AMOADD_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7279 { 3403 /* amoadd.h.aq */, RISCV::AMOADD_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7280 { 3415 /* amoadd.h.aqrl */, RISCV::AMOADD_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7281 { 3429 /* amoadd.h.rl */, RISCV::AMOADD_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7282 { 3441 /* amoadd.w */, RISCV::AMOADD_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7283 { 3450 /* amoadd.w.aq */, RISCV::AMOADD_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7284 { 3462 /* amoadd.w.aqrl */, RISCV::AMOADD_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7285 { 3476 /* amoadd.w.rl */, RISCV::AMOADD_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7286 { 3488 /* amoand.b */, RISCV::AMOAND_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7287 { 3497 /* amoand.b.aq */, RISCV::AMOAND_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7288 { 3509 /* amoand.b.aqrl */, RISCV::AMOAND_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7289 { 3523 /* amoand.b.rl */, RISCV::AMOAND_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7290 { 3535 /* amoand.d */, RISCV::AMOAND_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7291 { 3544 /* amoand.d.aq */, RISCV::AMOAND_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7292 { 3556 /* amoand.d.aqrl */, RISCV::AMOAND_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7293 { 3570 /* amoand.d.rl */, RISCV::AMOAND_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7294 { 3582 /* amoand.h */, RISCV::AMOAND_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7295 { 3591 /* amoand.h.aq */, RISCV::AMOAND_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7296 { 3603 /* amoand.h.aqrl */, RISCV::AMOAND_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7297 { 3617 /* amoand.h.rl */, RISCV::AMOAND_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7298 { 3629 /* amoand.w */, RISCV::AMOAND_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7299 { 3638 /* amoand.w.aq */, RISCV::AMOAND_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7300 { 3650 /* amoand.w.aqrl */, RISCV::AMOAND_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7301 { 3664 /* amoand.w.rl */, RISCV::AMOAND_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7302 { 3676 /* amocas.b */, RISCV::AMOCAS_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7303 { 3685 /* amocas.b.aq */, RISCV::AMOCAS_B_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7304 { 3697 /* amocas.b.aqrl */, RISCV::AMOCAS_B_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7305 { 3711 /* amocas.b.rl */, RISCV::AMOCAS_B_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7306 { 3723 /* amocas.d */, RISCV::AMOCAS_D_RV64, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7307 { 3723 /* amocas.d */, RISCV::AMOCAS_D_RV32, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7308 { 3732 /* amocas.d.aq */, RISCV::AMOCAS_D_RV64_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7309 { 3732 /* amocas.d.aq */, RISCV::AMOCAS_D_RV32_AQ, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7310 { 3744 /* amocas.d.aqrl */, RISCV::AMOCAS_D_RV64_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7311 { 3744 /* amocas.d.aqrl */, RISCV::AMOCAS_D_RV32_AQRL, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7312 { 3758 /* amocas.d.rl */, RISCV::AMOCAS_D_RV64_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7313 { 3758 /* amocas.d.rl */, RISCV::AMOCAS_D_RV32_RL, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7314 { 3770 /* amocas.h */, RISCV::AMOCAS_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7315 { 3779 /* amocas.h.aq */, RISCV::AMOCAS_H_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7316 { 3791 /* amocas.h.aqrl */, RISCV::AMOCAS_H_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7317 { 3805 /* amocas.h.rl */, RISCV::AMOCAS_H_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7318 { 3817 /* amocas.q */, RISCV::AMOCAS_Q, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7319 { 3826 /* amocas.q.aq */, RISCV::AMOCAS_Q_AQ, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7320 { 3838 /* amocas.q.aqrl */, RISCV::AMOCAS_Q_AQRL, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7321 { 3852 /* amocas.q.rl */, RISCV::AMOCAS_Q_RL, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7322 { 3864 /* amocas.w */, RISCV::AMOCAS_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7323 { 3873 /* amocas.w.aq */, RISCV::AMOCAS_W_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7324 { 3885 /* amocas.w.aqrl */, RISCV::AMOCAS_W_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7325 { 3899 /* amocas.w.rl */, RISCV::AMOCAS_W_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7326 { 3911 /* amomax.b */, RISCV::AMOMAX_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7327 { 3920 /* amomax.b.aq */, RISCV::AMOMAX_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7328 { 3932 /* amomax.b.aqrl */, RISCV::AMOMAX_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7329 { 3946 /* amomax.b.rl */, RISCV::AMOMAX_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7330 { 3958 /* amomax.d */, RISCV::AMOMAX_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7331 { 3967 /* amomax.d.aq */, RISCV::AMOMAX_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7332 { 3979 /* amomax.d.aqrl */, RISCV::AMOMAX_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7333 { 3993 /* amomax.d.rl */, RISCV::AMOMAX_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7334 { 4005 /* amomax.h */, RISCV::AMOMAX_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7335 { 4014 /* amomax.h.aq */, RISCV::AMOMAX_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7336 { 4026 /* amomax.h.aqrl */, RISCV::AMOMAX_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7337 { 4040 /* amomax.h.rl */, RISCV::AMOMAX_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7338 { 4052 /* amomax.w */, RISCV::AMOMAX_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7339 { 4061 /* amomax.w.aq */, RISCV::AMOMAX_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7340 { 4073 /* amomax.w.aqrl */, RISCV::AMOMAX_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7341 { 4087 /* amomax.w.rl */, RISCV::AMOMAX_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7342 { 4099 /* amomaxu.b */, RISCV::AMOMAXU_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7343 { 4109 /* amomaxu.b.aq */, RISCV::AMOMAXU_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7344 { 4122 /* amomaxu.b.aqrl */, RISCV::AMOMAXU_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7345 { 4137 /* amomaxu.b.rl */, RISCV::AMOMAXU_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7346 { 4150 /* amomaxu.d */, RISCV::AMOMAXU_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7347 { 4160 /* amomaxu.d.aq */, RISCV::AMOMAXU_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7348 { 4173 /* amomaxu.d.aqrl */, RISCV::AMOMAXU_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7349 { 4188 /* amomaxu.d.rl */, RISCV::AMOMAXU_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7350 { 4201 /* amomaxu.h */, RISCV::AMOMAXU_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7351 { 4211 /* amomaxu.h.aq */, RISCV::AMOMAXU_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7352 { 4224 /* amomaxu.h.aqrl */, RISCV::AMOMAXU_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7353 { 4239 /* amomaxu.h.rl */, RISCV::AMOMAXU_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7354 { 4252 /* amomaxu.w */, RISCV::AMOMAXU_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7355 { 4262 /* amomaxu.w.aq */, RISCV::AMOMAXU_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7356 { 4275 /* amomaxu.w.aqrl */, RISCV::AMOMAXU_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7357 { 4290 /* amomaxu.w.rl */, RISCV::AMOMAXU_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7358 { 4303 /* amomin.b */, RISCV::AMOMIN_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7359 { 4312 /* amomin.b.aq */, RISCV::AMOMIN_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7360 { 4324 /* amomin.b.aqrl */, RISCV::AMOMIN_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7361 { 4338 /* amomin.b.rl */, RISCV::AMOMIN_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7362 { 4350 /* amomin.d */, RISCV::AMOMIN_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7363 { 4359 /* amomin.d.aq */, RISCV::AMOMIN_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7364 { 4371 /* amomin.d.aqrl */, RISCV::AMOMIN_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7365 { 4385 /* amomin.d.rl */, RISCV::AMOMIN_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7366 { 4397 /* amomin.h */, RISCV::AMOMIN_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7367 { 4406 /* amomin.h.aq */, RISCV::AMOMIN_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7368 { 4418 /* amomin.h.aqrl */, RISCV::AMOMIN_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7369 { 4432 /* amomin.h.rl */, RISCV::AMOMIN_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7370 { 4444 /* amomin.w */, RISCV::AMOMIN_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7371 { 4453 /* amomin.w.aq */, RISCV::AMOMIN_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7372 { 4465 /* amomin.w.aqrl */, RISCV::AMOMIN_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7373 { 4479 /* amomin.w.rl */, RISCV::AMOMIN_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7374 { 4491 /* amominu.b */, RISCV::AMOMINU_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7375 { 4501 /* amominu.b.aq */, RISCV::AMOMINU_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7376 { 4514 /* amominu.b.aqrl */, RISCV::AMOMINU_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7377 { 4529 /* amominu.b.rl */, RISCV::AMOMINU_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7378 { 4542 /* amominu.d */, RISCV::AMOMINU_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7379 { 4552 /* amominu.d.aq */, RISCV::AMOMINU_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7380 { 4565 /* amominu.d.aqrl */, RISCV::AMOMINU_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7381 { 4580 /* amominu.d.rl */, RISCV::AMOMINU_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7382 { 4593 /* amominu.h */, RISCV::AMOMINU_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7383 { 4603 /* amominu.h.aq */, RISCV::AMOMINU_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7384 { 4616 /* amominu.h.aqrl */, RISCV::AMOMINU_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7385 { 4631 /* amominu.h.rl */, RISCV::AMOMINU_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7386 { 4644 /* amominu.w */, RISCV::AMOMINU_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7387 { 4654 /* amominu.w.aq */, RISCV::AMOMINU_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7388 { 4667 /* amominu.w.aqrl */, RISCV::AMOMINU_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7389 { 4682 /* amominu.w.rl */, RISCV::AMOMINU_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7390 { 4695 /* amoor.b */, RISCV::AMOOR_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7391 { 4703 /* amoor.b.aq */, RISCV::AMOOR_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7392 { 4714 /* amoor.b.aqrl */, RISCV::AMOOR_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7393 { 4727 /* amoor.b.rl */, RISCV::AMOOR_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7394 { 4738 /* amoor.d */, RISCV::AMOOR_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7395 { 4746 /* amoor.d.aq */, RISCV::AMOOR_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7396 { 4757 /* amoor.d.aqrl */, RISCV::AMOOR_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7397 { 4770 /* amoor.d.rl */, RISCV::AMOOR_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7398 { 4781 /* amoor.h */, RISCV::AMOOR_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7399 { 4789 /* amoor.h.aq */, RISCV::AMOOR_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7400 { 4800 /* amoor.h.aqrl */, RISCV::AMOOR_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7401 { 4813 /* amoor.h.rl */, RISCV::AMOOR_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7402 { 4824 /* amoor.w */, RISCV::AMOOR_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7403 { 4832 /* amoor.w.aq */, RISCV::AMOOR_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7404 { 4843 /* amoor.w.aqrl */, RISCV::AMOOR_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7405 { 4856 /* amoor.w.rl */, RISCV::AMOOR_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7406 { 4867 /* amoswap.b */, RISCV::AMOSWAP_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7407 { 4877 /* amoswap.b.aq */, RISCV::AMOSWAP_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7408 { 4890 /* amoswap.b.aqrl */, RISCV::AMOSWAP_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7409 { 4905 /* amoswap.b.rl */, RISCV::AMOSWAP_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7410 { 4918 /* amoswap.d */, RISCV::AMOSWAP_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7411 { 4928 /* amoswap.d.aq */, RISCV::AMOSWAP_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7412 { 4941 /* amoswap.d.aqrl */, RISCV::AMOSWAP_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7413 { 4956 /* amoswap.d.rl */, RISCV::AMOSWAP_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7414 { 4969 /* amoswap.h */, RISCV::AMOSWAP_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7415 { 4979 /* amoswap.h.aq */, RISCV::AMOSWAP_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7416 { 4992 /* amoswap.h.aqrl */, RISCV::AMOSWAP_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7417 { 5007 /* amoswap.h.rl */, RISCV::AMOSWAP_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7418 { 5020 /* amoswap.w */, RISCV::AMOSWAP_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7419 { 5030 /* amoswap.w.aq */, RISCV::AMOSWAP_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7420 { 5043 /* amoswap.w.aqrl */, RISCV::AMOSWAP_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7421 { 5058 /* amoswap.w.rl */, RISCV::AMOSWAP_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7422 { 5071 /* amoxor.b */, RISCV::AMOXOR_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7423 { 5080 /* amoxor.b.aq */, RISCV::AMOXOR_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7424 { 5092 /* amoxor.b.aqrl */, RISCV::AMOXOR_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7425 { 5106 /* amoxor.b.rl */, RISCV::AMOXOR_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7426 { 5118 /* amoxor.d */, RISCV::AMOXOR_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7427 { 5127 /* amoxor.d.aq */, RISCV::AMOXOR_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7428 { 5139 /* amoxor.d.aqrl */, RISCV::AMOXOR_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7429 { 5153 /* amoxor.d.rl */, RISCV::AMOXOR_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7430 { 5165 /* amoxor.h */, RISCV::AMOXOR_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7431 { 5174 /* amoxor.h.aq */, RISCV::AMOXOR_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7432 { 5186 /* amoxor.h.aqrl */, RISCV::AMOXOR_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7433 { 5200 /* amoxor.h.rl */, RISCV::AMOXOR_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7434 { 5212 /* amoxor.w */, RISCV::AMOXOR_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7435 { 5221 /* amoxor.w.aq */, RISCV::AMOXOR_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7436 { 5233 /* amoxor.w.aqrl */, RISCV::AMOXOR_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7437 { 5247 /* amoxor.w.rl */, RISCV::AMOXOR_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7438 { 5259 /* and */, RISCV::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7439 { 5259 /* and */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7440 { 5263 /* andi */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7441 { 5268 /* andn */, RISCV::ANDN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7442 { 5273 /* asub */, RISCV::ASUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7443 { 5278 /* asubu */, RISCV::ASUBU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7444 { 5284 /* auipc */, RISCV::AUIPC, Convert__Reg1_0__UImm20AUIPC1_1, AMFBS_None, { MCK_GPR, MCK_UImm20AUIPC }, },
7445 { 5290 /* bclr */, RISCV::BCLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7446 { 5290 /* bclr */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7447 { 5295 /* bclri */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7448 { 5301 /* beq */, RISCV::BEQ, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7449 { 5305 /* beqi */, RISCV::BEQI, Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2, AMFBS_HasStdExtZibi, { MCK_GPR, MCK_Imm5Zibi, MCK_BareSImm13Lsb0 }, },
7450 { 5310 /* beqz */, RISCV::BEQ, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7451 { 5315 /* bext */, RISCV::BEXT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7452 { 5315 /* bext */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7453 { 5320 /* bexti */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7454 { 5326 /* bge */, RISCV::BGE, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7455 { 5330 /* bgeu */, RISCV::BGEU, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7456 { 5335 /* bgez */, RISCV::BGE, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7457 { 5340 /* bgt */, RISCV::BLT, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7458 { 5344 /* bgtu */, RISCV::BLTU, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7459 { 5349 /* bgtz */, RISCV::BLT, Convert__regX0__Reg1_0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7460 { 5354 /* binv */, RISCV::BINV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7461 { 5354 /* binv */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7462 { 5359 /* binvi */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7463 { 5365 /* ble */, RISCV::BGE, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7464 { 5369 /* bleu */, RISCV::BGEU, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7465 { 5374 /* blez */, RISCV::BGE, Convert__regX0__Reg1_0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7466 { 5379 /* blt */, RISCV::BLT, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7467 { 5383 /* bltu */, RISCV::BLTU, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7468 { 5388 /* bltz */, RISCV::BLT, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7469 { 5393 /* bne */, RISCV::BNE, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7470 { 5397 /* bnei */, RISCV::BNEI, Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2, AMFBS_HasStdExtZibi, { MCK_GPR, MCK_Imm5Zibi, MCK_BareSImm13Lsb0 }, },
7471 { 5402 /* bnez */, RISCV::BNE, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7472 { 5407 /* brev8 */, RISCV::BREV8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR }, },
7473 { 5413 /* bset */, RISCV::BSET, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7474 { 5413 /* bset */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7475 { 5418 /* bseti */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7476 { 5424 /* c.add */, RISCV::C_ADD, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_GPRNoX0 }, },
7477 { 5430 /* c.addi */, RISCV::PseudoC_ADDI_NOP, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRX0, MCK_SImm6 }, },
7478 { 5430 /* c.addi */, RISCV::C_ADDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK_SImm6 }, },
7479 { 5437 /* c.addi16sp */, RISCV::C_ADDI16SP, Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, AMFBS_HasStdExtZca, { MCK_SP, MCK_SImm10Lsb0000NonZero }, },
7480 { 5448 /* c.addi4spn */, RISCV::C_ADDI4SPN, Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_SP, MCK_UImm10Lsb00NonZero }, },
7481 { 5459 /* c.addiw */, RISCV::C_ADDIW, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK_SImm6 }, },
7482 { 5467 /* c.addw */, RISCV::C_ADDW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
7483 { 5474 /* c.and */, RISCV::C_AND, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7484 { 5480 /* c.andi */, RISCV::C_ANDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_SImm6 }, },
7485 { 5487 /* c.beqz */, RISCV::C_BEQZ, Convert__Reg1_0__BareSImm9Lsb01_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_BareSImm9Lsb0 }, },
7486 { 5494 /* c.bnez */, RISCV::C_BNEZ, Convert__Reg1_0__BareSImm9Lsb01_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_BareSImm9Lsb0 }, },
7487 { 5501 /* c.ebreak */, RISCV::C_EBREAK, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
7488 { 5510 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7489 { 5510 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7490 { 5516 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_SP, MCK__41_ }, },
7491 { 5516 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7492 { 5524 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7493 { 5524 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7494 { 5530 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32, MCK__40_, MCK_SP, MCK__41_ }, },
7495 { 5530 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7496 { 5538 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7497 { 5538 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7498 { 5544 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_SP, MCK__41_ }, },
7499 { 5544 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7500 { 5552 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7501 { 5552 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7502 { 5558 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32, MCK__40_, MCK_SP, MCK__41_ }, },
7503 { 5558 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7504 { 5566 /* c.j */, RISCV::C_J, Convert__BareSImm12Lsb01_0, AMFBS_HasStdExtZca, { MCK_BareSImm12Lsb0 }, },
7505 { 5570 /* c.jal */, RISCV::C_JAL, Convert__BareSImm12Lsb01_0, AMFBS_HasStdExtZca_IsRV32, { MCK_BareSImm12Lsb0 }, },
7506 { 5576 /* c.jalr */, RISCV::C_JALR, Convert__Reg1_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0 }, },
7507 { 5583 /* c.jr */, RISCV::C_JR, Convert__Reg1_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0 }, },
7508 { 5588 /* c.lbu */, RISCV::C_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7509 { 5588 /* c.lbu */, RISCV::C_LBU, Convert__Reg1_0__Reg1_3__UImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
7510 { 5594 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7511 { 5594 /* c.ld */, RISCV::C_LD_RV32, Convert__GPRPairCRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK__40_, MCK_GPRC, MCK__41_ }, },
7512 { 5594 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7513 { 5594 /* c.ld */, RISCV::C_LD_RV32, Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7514 { 5599 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
7515 { 5599 /* c.ldsp */, RISCV::C_LDSP_RV32, Convert__GPRPairNoX0RV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairNoX0RV32, MCK__40_, MCK_SP, MCK__41_ }, },
7516 { 5599 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7517 { 5599 /* c.ldsp */, RISCV::C_LDSP_RV32, Convert__GPRPairNoX0RV321_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairNoX0RV32, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7518 { 5606 /* c.lh */, RISCV::C_LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7519 { 5606 /* c.lh */, RISCV::C_LH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
7520 { 5611 /* c.lhu */, RISCV::C_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7521 { 5611 /* c.lhu */, RISCV::C_LHU, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
7522 { 5617 /* c.li */, RISCV::C_LI, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_SImm6 }, },
7523 { 5622 /* c.lui */, RISCV::C_LUI, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtZca, { MCK_GPRNoX2, MCK_CLUIImm }, },
7524 { 5628 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7525 { 5628 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7526 { 5633 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
7527 { 5633 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7528 { 5640 /* c.mop.1 */, RISCV::C_SSPUSH, Convert__regX1, AMFBS_HasStdExtZcmop, { }, },
7529 { 5648 /* c.mop.11 */, RISCV::C_MOP_11, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7530 { 5657 /* c.mop.13 */, RISCV::C_MOP_13, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7531 { 5666 /* c.mop.15 */, RISCV::C_MOP_15, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7532 { 5675 /* c.mop.3 */, RISCV::C_MOP_3, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7533 { 5683 /* c.mop.5 */, RISCV::C_SSPOPCHK, Convert__regX5, AMFBS_HasStdExtZcmop, { }, },
7534 { 5691 /* c.mop.7 */, RISCV::C_MOP_7, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7535 { 5699 /* c.mop.9 */, RISCV::C_MOP_9, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7536 { 5707 /* c.mul */, RISCV::C_MUL, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZcb_HasStdExtZmmul, { MCK_GPRC, MCK_GPRC }, },
7537 { 5713 /* c.mv */, RISCV::C_MV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_GPRNoX0 }, },
7538 { 5718 /* c.nop */, RISCV::C_NOP, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
7539 { 5718 /* c.nop */, RISCV::C_NOP_HINT, Convert__SImm6NonZero1_0, AMFBS_HasStdExtZca, { MCK_SImm6NonZero }, },
7540 { 5724 /* c.not */, RISCV::C_NOT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
7541 { 5730 /* c.ntl.all */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX5, AMFBS_HasStdExtZca, { }, },
7542 { 5740 /* c.ntl.p1 */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX2, AMFBS_HasStdExtZca, { }, },
7543 { 5749 /* c.ntl.pall */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX3, AMFBS_HasStdExtZca, { }, },
7544 { 5760 /* c.ntl.s1 */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX4, AMFBS_HasStdExtZca, { }, },
7545 { 5769 /* c.or */, RISCV::C_OR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7546 { 5774 /* c.sb */, RISCV::C_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7547 { 5774 /* c.sb */, RISCV::C_SB, Convert__Reg1_0__Reg1_3__UImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
7548 { 5779 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7549 { 5779 /* c.sd */, RISCV::C_SD_RV32, Convert__GPRPairCRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK__40_, MCK_GPRC, MCK__41_ }, },
7550 { 5779 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7551 { 5779 /* c.sd */, RISCV::C_SD_RV32, Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7552 { 5784 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPR, MCK__40_, MCK_SP, MCK__41_ }, },
7553 { 5784 /* c.sdsp */, RISCV::C_SDSP_RV32, Convert__GPRPairRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairRV32, MCK__40_, MCK_SP, MCK__41_ }, },
7554 { 5784 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPR, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7555 { 5784 /* c.sdsp */, RISCV::C_SDSP_RV32, Convert__GPRPairRV321_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairRV32, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7556 { 5791 /* c.sext.b */, RISCV::C_SEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
7557 { 5800 /* c.sext.h */, RISCV::C_SEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
7558 { 5809 /* c.sh */, RISCV::C_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7559 { 5809 /* c.sh */, RISCV::C_SH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
7560 { 5814 /* c.slli */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_UImmLog2XLen }, },
7561 { 5821 /* c.slli64 */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPR }, },
7562 { 5830 /* c.srai */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImmLog2XLen }, },
7563 { 5837 /* c.srai64 */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC }, },
7564 { 5846 /* c.srli */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImmLog2XLen }, },
7565 { 5853 /* c.srli64 */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC }, },
7566 { 5862 /* c.sspopchk */, RISCV::C_SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZcmop, { MCK_GPRX5 }, },
7567 { 5873 /* c.sspush */, RISCV::C_SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZcmop, { MCK_GPRX1 }, },
7568 { 5882 /* c.sub */, RISCV::C_SUB, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7569 { 5888 /* c.subw */, RISCV::C_SUBW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
7570 { 5895 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7571 { 5895 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7572 { 5900 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPR, MCK__40_, MCK_SP, MCK__41_ }, },
7573 { 5900 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7574 { 5907 /* c.unimp */, RISCV::C_UNIMP, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
7575 { 5915 /* c.xor */, RISCV::C_XOR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7576 { 5921 /* c.zext.b */, RISCV::C_ZEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
7577 { 5930 /* c.zext.h */, RISCV::C_ZEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
7578 { 5939 /* c.zext.w */, RISCV::C_ZEXT_W, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64, { MCK_GPRC }, },
7579 { 5948 /* call */, RISCV::PseudoCALL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
7580 { 5948 /* call */, RISCV::PseudoCALLReg, Convert__Reg1_0__CallSymbol1_1, AMFBS_None, { MCK_GPR, MCK_CallSymbol }, },
7581 { 5953 /* cbo.clean */, RISCV::CBO_CLEAN, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
7582 { 5963 /* cbo.flush */, RISCV::CBO_FLUSH, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
7583 { 5973 /* cbo.inval */, RISCV::CBO_INVAL, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
7584 { 5983 /* cbo.zero */, RISCV::CBO_ZERO, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicboz, { MCK_ZeroOffsetMemOpOperand }, },
7585 { 5992 /* clmul */, RISCV::CLMUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbcOrZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7586 { 5998 /* clmulh */, RISCV::CLMULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbcOrZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7587 { 6005 /* clmulr */, RISCV::CLMULR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7588 { 6012 /* cls */, RISCV::CLS, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
7589 { 6016 /* clsw */, RISCV::CLSW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
7590 { 6021 /* clz */, RISCV::CLZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
7591 { 6025 /* clzw */, RISCV::CLZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
7592 { 6030 /* cm.jalt */, RISCV::CM_JALT, Convert__UImm8GE321_0, AMFBS_HasStdExtZcmt, { MCK_UImm8GE32 }, },
7593 { 6038 /* cm.jt */, RISCV::CM_JT, Convert__UImm51_0, AMFBS_HasStdExtZcmt, { MCK_UImm5 }, },
7594 { 6044 /* cm.mva01s */, RISCV::CM_MVA01S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_SR07, MCK_SR07 }, },
7595 { 6054 /* cm.mvsa01 */, RISCV::CM_MVSA01, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_SR07, MCK_SR07 }, },
7596 { 6064 /* cm.pop */, RISCV::CM_POP, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
7597 { 6071 /* cm.popret */, RISCV::CM_POPRET, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
7598 { 6081 /* cm.popretz */, RISCV::CM_POPRETZ, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
7599 { 6092 /* cm.push */, RISCV::CM_PUSH, Convert__RegList1_0__NegStackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_NegStackAdj }, },
7600 { 6100 /* cpop */, RISCV::CPOP, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
7601 { 6105 /* cpopw */, RISCV::CPOPW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
7602 { 6111 /* csrc */, RISCV::CSRRC, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
7603 { 6111 /* csrc */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7604 { 6116 /* csrci */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7605 { 6122 /* csrr */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, },
7606 { 6127 /* csrrc */, RISCV::CSRRC, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
7607 { 6127 /* csrrc */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7608 { 6133 /* csrrci */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7609 { 6140 /* csrrs */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
7610 { 6140 /* csrrs */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7611 { 6146 /* csrrsi */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7612 { 6153 /* csrrw */, RISCV::CSRRW, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
7613 { 6153 /* csrrw */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7614 { 6159 /* csrrwi */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7615 { 6166 /* csrs */, RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
7616 { 6166 /* csrs */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7617 { 6171 /* csrsi */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7618 { 6177 /* csrw */, RISCV::CSRRW, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
7619 { 6177 /* csrw */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7620 { 6182 /* csrwi */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7621 { 6188 /* ctz */, RISCV::CTZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
7622 { 6192 /* ctzw */, RISCV::CTZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
7623 { 6197 /* cv.abs */, RISCV::CV_ABS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
7624 { 6204 /* cv.abs.b */, RISCV::CV_ABS_B, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
7625 { 6213 /* cv.abs.h */, RISCV::CV_ABS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
7626 { 6222 /* cv.add.b */, RISCV::CV_ADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7627 { 6231 /* cv.add.div2 */, RISCV::CV_ADD_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7628 { 6243 /* cv.add.div4 */, RISCV::CV_ADD_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7629 { 6255 /* cv.add.div8 */, RISCV::CV_ADD_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7630 { 6267 /* cv.add.h */, RISCV::CV_ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7631 { 6276 /* cv.add.sc.b */, RISCV::CV_ADD_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7632 { 6288 /* cv.add.sc.h */, RISCV::CV_ADD_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7633 { 6300 /* cv.add.sci.b */, RISCV::CV_ADD_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7634 { 6313 /* cv.add.sci.h */, RISCV::CV_ADD_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7635 { 6326 /* cv.addn */, RISCV::CV_ADDN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7636 { 6334 /* cv.addnr */, RISCV::CV_ADDNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7637 { 6343 /* cv.addrn */, RISCV::CV_ADDRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7638 { 6352 /* cv.addrnr */, RISCV::CV_ADDRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7639 { 6362 /* cv.addun */, RISCV::CV_ADDUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7640 { 6371 /* cv.addunr */, RISCV::CV_ADDUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7641 { 6381 /* cv.addurn */, RISCV::CV_ADDURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7642 { 6391 /* cv.addurnr */, RISCV::CV_ADDURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7643 { 6402 /* cv.and.b */, RISCV::CV_AND_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7644 { 6411 /* cv.and.h */, RISCV::CV_AND_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7645 { 6420 /* cv.and.sc.b */, RISCV::CV_AND_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7646 { 6432 /* cv.and.sc.h */, RISCV::CV_AND_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7647 { 6444 /* cv.and.sci.b */, RISCV::CV_AND_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7648 { 6457 /* cv.and.sci.h */, RISCV::CV_AND_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7649 { 6470 /* cv.avg.b */, RISCV::CV_AVG_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7650 { 6479 /* cv.avg.h */, RISCV::CV_AVG_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7651 { 6488 /* cv.avg.sc.b */, RISCV::CV_AVG_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7652 { 6500 /* cv.avg.sc.h */, RISCV::CV_AVG_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7653 { 6512 /* cv.avg.sci.b */, RISCV::CV_AVG_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7654 { 6525 /* cv.avg.sci.h */, RISCV::CV_AVG_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7655 { 6538 /* cv.avgu.b */, RISCV::CV_AVGU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7656 { 6548 /* cv.avgu.h */, RISCV::CV_AVGU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7657 { 6558 /* cv.avgu.sc.b */, RISCV::CV_AVGU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7658 { 6571 /* cv.avgu.sc.h */, RISCV::CV_AVGU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7659 { 6584 /* cv.avgu.sci.b */, RISCV::CV_AVGU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7660 { 6598 /* cv.avgu.sci.h */, RISCV::CV_AVGU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7661 { 6612 /* cv.bclr */, RISCV::CV_BCLR, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
7662 { 6620 /* cv.bclrr */, RISCV::CV_BCLRR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7663 { 6629 /* cv.beqimm */, RISCV::CV_BEQIMM, Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_BareSImm13Lsb0 }, },
7664 { 6639 /* cv.bitrev */, RISCV::CV_BITREV, Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm2, MCK_UImm5 }, },
7665 { 6649 /* cv.bneimm */, RISCV::CV_BNEIMM, Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_BareSImm13Lsb0 }, },
7666 { 6659 /* cv.bset */, RISCV::CV_BSET, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
7667 { 6667 /* cv.bsetr */, RISCV::CV_BSETR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7668 { 6676 /* cv.clb */, RISCV::CV_CLB, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
7669 { 6683 /* cv.clip */, RISCV::CV_CLIP, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7670 { 6691 /* cv.clipr */, RISCV::CV_CLIPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7671 { 6700 /* cv.clipu */, RISCV::CV_CLIPU, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7672 { 6709 /* cv.clipur */, RISCV::CV_CLIPUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7673 { 6719 /* cv.cmpeq.b */, RISCV::CV_CMPEQ_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7674 { 6730 /* cv.cmpeq.h */, RISCV::CV_CMPEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7675 { 6741 /* cv.cmpeq.sc.b */, RISCV::CV_CMPEQ_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7676 { 6755 /* cv.cmpeq.sc.h */, RISCV::CV_CMPEQ_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7677 { 6769 /* cv.cmpeq.sci.b */, RISCV::CV_CMPEQ_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7678 { 6784 /* cv.cmpeq.sci.h */, RISCV::CV_CMPEQ_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7679 { 6799 /* cv.cmpge.b */, RISCV::CV_CMPGE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7680 { 6810 /* cv.cmpge.h */, RISCV::CV_CMPGE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7681 { 6821 /* cv.cmpge.sc.b */, RISCV::CV_CMPGE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7682 { 6835 /* cv.cmpge.sc.h */, RISCV::CV_CMPGE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7683 { 6849 /* cv.cmpge.sci.b */, RISCV::CV_CMPGE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7684 { 6864 /* cv.cmpge.sci.h */, RISCV::CV_CMPGE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7685 { 6879 /* cv.cmpgeu.b */, RISCV::CV_CMPGEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7686 { 6891 /* cv.cmpgeu.h */, RISCV::CV_CMPGEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7687 { 6903 /* cv.cmpgeu.sc.b */, RISCV::CV_CMPGEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7688 { 6918 /* cv.cmpgeu.sc.h */, RISCV::CV_CMPGEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7689 { 6933 /* cv.cmpgeu.sci.b */, RISCV::CV_CMPGEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7690 { 6949 /* cv.cmpgeu.sci.h */, RISCV::CV_CMPGEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7691 { 6965 /* cv.cmpgt.b */, RISCV::CV_CMPGT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7692 { 6976 /* cv.cmpgt.h */, RISCV::CV_CMPGT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7693 { 6987 /* cv.cmpgt.sc.b */, RISCV::CV_CMPGT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7694 { 7001 /* cv.cmpgt.sc.h */, RISCV::CV_CMPGT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7695 { 7015 /* cv.cmpgt.sci.b */, RISCV::CV_CMPGT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7696 { 7030 /* cv.cmpgt.sci.h */, RISCV::CV_CMPGT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7697 { 7045 /* cv.cmpgtu.b */, RISCV::CV_CMPGTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7698 { 7057 /* cv.cmpgtu.h */, RISCV::CV_CMPGTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7699 { 7069 /* cv.cmpgtu.sc.b */, RISCV::CV_CMPGTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7700 { 7084 /* cv.cmpgtu.sc.h */, RISCV::CV_CMPGTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7701 { 7099 /* cv.cmpgtu.sci.b */, RISCV::CV_CMPGTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7702 { 7115 /* cv.cmpgtu.sci.h */, RISCV::CV_CMPGTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7703 { 7131 /* cv.cmple.b */, RISCV::CV_CMPLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7704 { 7142 /* cv.cmple.h */, RISCV::CV_CMPLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7705 { 7153 /* cv.cmple.sc.b */, RISCV::CV_CMPLE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7706 { 7167 /* cv.cmple.sc.h */, RISCV::CV_CMPLE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7707 { 7181 /* cv.cmple.sci.b */, RISCV::CV_CMPLE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7708 { 7196 /* cv.cmple.sci.h */, RISCV::CV_CMPLE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7709 { 7211 /* cv.cmpleu.b */, RISCV::CV_CMPLEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7710 { 7223 /* cv.cmpleu.h */, RISCV::CV_CMPLEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7711 { 7235 /* cv.cmpleu.sc.b */, RISCV::CV_CMPLEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7712 { 7250 /* cv.cmpleu.sc.h */, RISCV::CV_CMPLEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7713 { 7265 /* cv.cmpleu.sci.b */, RISCV::CV_CMPLEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7714 { 7281 /* cv.cmpleu.sci.h */, RISCV::CV_CMPLEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7715 { 7297 /* cv.cmplt.b */, RISCV::CV_CMPLT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7716 { 7308 /* cv.cmplt.h */, RISCV::CV_CMPLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7717 { 7319 /* cv.cmplt.sc.b */, RISCV::CV_CMPLT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7718 { 7333 /* cv.cmplt.sc.h */, RISCV::CV_CMPLT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7719 { 7347 /* cv.cmplt.sci.b */, RISCV::CV_CMPLT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7720 { 7362 /* cv.cmplt.sci.h */, RISCV::CV_CMPLT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7721 { 7377 /* cv.cmpltu.b */, RISCV::CV_CMPLTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7722 { 7389 /* cv.cmpltu.h */, RISCV::CV_CMPLTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7723 { 7401 /* cv.cmpltu.sc.b */, RISCV::CV_CMPLTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7724 { 7416 /* cv.cmpltu.sc.h */, RISCV::CV_CMPLTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7725 { 7431 /* cv.cmpltu.sci.b */, RISCV::CV_CMPLTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7726 { 7447 /* cv.cmpltu.sci.h */, RISCV::CV_CMPLTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7727 { 7463 /* cv.cmpne.b */, RISCV::CV_CMPNE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7728 { 7474 /* cv.cmpne.h */, RISCV::CV_CMPNE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7729 { 7485 /* cv.cmpne.sc.b */, RISCV::CV_CMPNE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7730 { 7499 /* cv.cmpne.sc.h */, RISCV::CV_CMPNE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7731 { 7513 /* cv.cmpne.sci.b */, RISCV::CV_CMPNE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7732 { 7528 /* cv.cmpne.sci.h */, RISCV::CV_CMPNE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7733 { 7543 /* cv.cnt */, RISCV::CV_CNT, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
7734 { 7550 /* cv.cplxconj */, RISCV::CV_CPLXCONJ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
7735 { 7562 /* cv.cplxmul.i */, RISCV::CV_CPLXMUL_I, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7736 { 7575 /* cv.cplxmul.i.div2 */, RISCV::CV_CPLXMUL_I_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7737 { 7593 /* cv.cplxmul.i.div4 */, RISCV::CV_CPLXMUL_I_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7738 { 7611 /* cv.cplxmul.i.div8 */, RISCV::CV_CPLXMUL_I_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7739 { 7629 /* cv.cplxmul.r */, RISCV::CV_CPLXMUL_R, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7740 { 7642 /* cv.cplxmul.r.div2 */, RISCV::CV_CPLXMUL_R_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7741 { 7660 /* cv.cplxmul.r.div4 */, RISCV::CV_CPLXMUL_R_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7742 { 7678 /* cv.cplxmul.r.div8 */, RISCV::CV_CPLXMUL_R_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7743 { 7696 /* cv.dotsp.b */, RISCV::CV_DOTSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7744 { 7707 /* cv.dotsp.h */, RISCV::CV_DOTSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7745 { 7718 /* cv.dotsp.sc.b */, RISCV::CV_DOTSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7746 { 7732 /* cv.dotsp.sc.h */, RISCV::CV_DOTSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7747 { 7746 /* cv.dotsp.sci.b */, RISCV::CV_DOTSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7748 { 7761 /* cv.dotsp.sci.h */, RISCV::CV_DOTSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7749 { 7776 /* cv.dotup.b */, RISCV::CV_DOTUP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7750 { 7787 /* cv.dotup.h */, RISCV::CV_DOTUP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7751 { 7798 /* cv.dotup.sc.b */, RISCV::CV_DOTUP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7752 { 7812 /* cv.dotup.sc.h */, RISCV::CV_DOTUP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7753 { 7826 /* cv.dotup.sci.b */, RISCV::CV_DOTUP_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7754 { 7841 /* cv.dotup.sci.h */, RISCV::CV_DOTUP_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7755 { 7856 /* cv.dotusp.b */, RISCV::CV_DOTUSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7756 { 7868 /* cv.dotusp.h */, RISCV::CV_DOTUSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7757 { 7880 /* cv.dotusp.sc.b */, RISCV::CV_DOTUSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7758 { 7895 /* cv.dotusp.sc.h */, RISCV::CV_DOTUSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7759 { 7910 /* cv.dotusp.sci.b */, RISCV::CV_DOTUSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7760 { 7926 /* cv.dotusp.sci.h */, RISCV::CV_DOTUSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7761 { 7942 /* cv.elw */, RISCV::PseudoCV_ELW, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXCVelw_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
7762 { 7942 /* cv.elw */, RISCV::CV_ELW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasVendorXCVelw_IsRV32, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7763 { 7949 /* cv.extbs */, RISCV::CV_EXTBS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
7764 { 7958 /* cv.extbz */, RISCV::CV_EXTBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
7765 { 7967 /* cv.exths */, RISCV::CV_EXTHS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
7766 { 7976 /* cv.exthz */, RISCV::CV_EXTHZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
7767 { 7985 /* cv.extract */, RISCV::CV_EXTRACT, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
7768 { 7996 /* cv.extract.b */, RISCV::CV_EXTRACT_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7769 { 8009 /* cv.extract.h */, RISCV::CV_EXTRACT_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7770 { 8022 /* cv.extractr */, RISCV::CV_EXTRACTR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7771 { 8034 /* cv.extractu */, RISCV::CV_EXTRACTU, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
7772 { 8046 /* cv.extractu.b */, RISCV::CV_EXTRACTU_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7773 { 8060 /* cv.extractu.h */, RISCV::CV_EXTRACTU_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7774 { 8074 /* cv.extractur */, RISCV::CV_EXTRACTUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7775 { 8087 /* cv.ff1 */, RISCV::CV_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
7776 { 8094 /* cv.fl1 */, RISCV::CV_FL1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
7777 { 8101 /* cv.insert */, RISCV::CV_INSERT, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
7778 { 8111 /* cv.insert.b */, RISCV::CV_INSERT_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7779 { 8123 /* cv.insert.h */, RISCV::CV_INSERT_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7780 { 8135 /* cv.insertr */, RISCV::CV_INSERTR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7781 { 8146 /* cv.lb */, RISCV::CV_LB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
7782 { 8146 /* cv.lb */, RISCV::CV_LB_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
7783 { 8146 /* cv.lb */, RISCV::CV_LB_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
7784 { 8152 /* cv.lbu */, RISCV::CV_LBU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
7785 { 8152 /* cv.lbu */, RISCV::CV_LBU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
7786 { 8152 /* cv.lbu */, RISCV::CV_LBU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
7787 { 8159 /* cv.lh */, RISCV::CV_LH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
7788 { 8159 /* cv.lh */, RISCV::CV_LH_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
7789 { 8159 /* cv.lh */, RISCV::CV_LH_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
7790 { 8165 /* cv.lhu */, RISCV::CV_LHU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
7791 { 8165 /* cv.lhu */, RISCV::CV_LHU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
7792 { 8165 /* cv.lhu */, RISCV::CV_LHU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
7793 { 8172 /* cv.lw */, RISCV::CV_LW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
7794 { 8172 /* cv.lw */, RISCV::CV_LW_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
7795 { 8172 /* cv.lw */, RISCV::CV_LW_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
7796 { 8178 /* cv.mac */, RISCV::CV_MAC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7797 { 8185 /* cv.machhsn */, RISCV::CV_MACHHSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7798 { 8196 /* cv.machhsrn */, RISCV::CV_MACHHSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7799 { 8208 /* cv.machhun */, RISCV::CV_MACHHUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7800 { 8219 /* cv.machhurn */, RISCV::CV_MACHHURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7801 { 8231 /* cv.macsn */, RISCV::CV_MACSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7802 { 8240 /* cv.macsrn */, RISCV::CV_MACSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7803 { 8250 /* cv.macun */, RISCV::CV_MACUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7804 { 8259 /* cv.macurn */, RISCV::CV_MACURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7805 { 8269 /* cv.max */, RISCV::CV_MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7806 { 8276 /* cv.max.b */, RISCV::CV_MAX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7807 { 8285 /* cv.max.h */, RISCV::CV_MAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7808 { 8294 /* cv.max.sc.b */, RISCV::CV_MAX_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7809 { 8306 /* cv.max.sc.h */, RISCV::CV_MAX_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7810 { 8318 /* cv.max.sci.b */, RISCV::CV_MAX_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7811 { 8331 /* cv.max.sci.h */, RISCV::CV_MAX_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7812 { 8344 /* cv.maxu */, RISCV::CV_MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7813 { 8352 /* cv.maxu.b */, RISCV::CV_MAXU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7814 { 8362 /* cv.maxu.h */, RISCV::CV_MAXU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7815 { 8372 /* cv.maxu.sc.b */, RISCV::CV_MAXU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7816 { 8385 /* cv.maxu.sc.h */, RISCV::CV_MAXU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7817 { 8398 /* cv.maxu.sci.b */, RISCV::CV_MAXU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7818 { 8412 /* cv.maxu.sci.h */, RISCV::CV_MAXU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7819 { 8426 /* cv.min */, RISCV::CV_MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7820 { 8433 /* cv.min.b */, RISCV::CV_MIN_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7821 { 8442 /* cv.min.h */, RISCV::CV_MIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7822 { 8451 /* cv.min.sc.b */, RISCV::CV_MIN_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7823 { 8463 /* cv.min.sc.h */, RISCV::CV_MIN_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7824 { 8475 /* cv.min.sci.b */, RISCV::CV_MIN_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7825 { 8488 /* cv.min.sci.h */, RISCV::CV_MIN_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7826 { 8501 /* cv.minu */, RISCV::CV_MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7827 { 8509 /* cv.minu.b */, RISCV::CV_MINU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7828 { 8519 /* cv.minu.h */, RISCV::CV_MINU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7829 { 8529 /* cv.minu.sc.b */, RISCV::CV_MINU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7830 { 8542 /* cv.minu.sc.h */, RISCV::CV_MINU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7831 { 8555 /* cv.minu.sci.b */, RISCV::CV_MINU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7832 { 8569 /* cv.minu.sci.h */, RISCV::CV_MINU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7833 { 8583 /* cv.msu */, RISCV::CV_MSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7834 { 8590 /* cv.mulhhs */, RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7835 { 8600 /* cv.mulhhsn */, RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7836 { 8611 /* cv.mulhhsrn */, RISCV::CV_MULHHSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7837 { 8623 /* cv.mulhhu */, RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7838 { 8633 /* cv.mulhhun */, RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7839 { 8644 /* cv.mulhhurn */, RISCV::CV_MULHHURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7840 { 8656 /* cv.muls */, RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7841 { 8664 /* cv.mulsn */, RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7842 { 8673 /* cv.mulsrn */, RISCV::CV_MULSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7843 { 8683 /* cv.mulu */, RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7844 { 8691 /* cv.mulun */, RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7845 { 8700 /* cv.mulurn */, RISCV::CV_MULURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7846 { 8710 /* cv.or.b */, RISCV::CV_OR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7847 { 8718 /* cv.or.h */, RISCV::CV_OR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7848 { 8726 /* cv.or.sc.b */, RISCV::CV_OR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7849 { 8737 /* cv.or.sc.h */, RISCV::CV_OR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7850 { 8748 /* cv.or.sci.b */, RISCV::CV_OR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7851 { 8760 /* cv.or.sci.h */, RISCV::CV_OR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7852 { 8772 /* cv.pack */, RISCV::CV_PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7853 { 8780 /* cv.pack.h */, RISCV::CV_PACK_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7854 { 8790 /* cv.packhi.b */, RISCV::CV_PACKHI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7855 { 8802 /* cv.packlo.b */, RISCV::CV_PACKLO_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7856 { 8814 /* cv.ror */, RISCV::CV_ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7857 { 8821 /* cv.sb */, RISCV::CV_SB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
7858 { 8821 /* cv.sb */, RISCV::CV_SB_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
7859 { 8821 /* cv.sb */, RISCV::CV_SB_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
7860 { 8827 /* cv.sdotsp.b */, RISCV::CV_SDOTSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7861 { 8839 /* cv.sdotsp.h */, RISCV::CV_SDOTSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7862 { 8851 /* cv.sdotsp.sc.b */, RISCV::CV_SDOTSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7863 { 8866 /* cv.sdotsp.sc.h */, RISCV::CV_SDOTSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7864 { 8881 /* cv.sdotsp.sci.b */, RISCV::CV_SDOTSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7865 { 8897 /* cv.sdotsp.sci.h */, RISCV::CV_SDOTSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7866 { 8913 /* cv.sdotup.b */, RISCV::CV_SDOTUP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7867 { 8925 /* cv.sdotup.h */, RISCV::CV_SDOTUP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7868 { 8937 /* cv.sdotup.sc.b */, RISCV::CV_SDOTUP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7869 { 8952 /* cv.sdotup.sc.h */, RISCV::CV_SDOTUP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7870 { 8967 /* cv.sdotup.sci.b */, RISCV::CV_SDOTUP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7871 { 8983 /* cv.sdotup.sci.h */, RISCV::CV_SDOTUP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7872 { 8999 /* cv.sdotusp.b */, RISCV::CV_SDOTUSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7873 { 9012 /* cv.sdotusp.h */, RISCV::CV_SDOTUSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7874 { 9025 /* cv.sdotusp.sc.b */, RISCV::CV_SDOTUSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7875 { 9041 /* cv.sdotusp.sc.h */, RISCV::CV_SDOTUSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7876 { 9057 /* cv.sdotusp.sci.b */, RISCV::CV_SDOTUSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7877 { 9074 /* cv.sdotusp.sci.h */, RISCV::CV_SDOTUSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7878 { 9091 /* cv.sh */, RISCV::CV_SH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
7879 { 9091 /* cv.sh */, RISCV::CV_SH_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
7880 { 9091 /* cv.sh */, RISCV::CV_SH_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
7881 { 9097 /* cv.shuffle.b */, RISCV::CV_SHUFFLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7882 { 9110 /* cv.shuffle.h */, RISCV::CV_SHUFFLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7883 { 9123 /* cv.shuffle.sci.h */, RISCV::CV_SHUFFLE_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7884 { 9140 /* cv.shuffle2.b */, RISCV::CV_SHUFFLE2_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7885 { 9154 /* cv.shuffle2.h */, RISCV::CV_SHUFFLE2_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7886 { 9168 /* cv.shufflei0.sci.b */, RISCV::CV_SHUFFLEI0_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7887 { 9187 /* cv.shufflei1.sci.b */, RISCV::CV_SHUFFLEI1_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7888 { 9206 /* cv.shufflei2.sci.b */, RISCV::CV_SHUFFLEI2_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7889 { 9225 /* cv.shufflei3.sci.b */, RISCV::CV_SHUFFLEI3_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
7890 { 9244 /* cv.sle */, RISCV::CV_SLE, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7891 { 9251 /* cv.sleu */, RISCV::CV_SLEU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7892 { 9259 /* cv.sll.b */, RISCV::CV_SLL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7893 { 9268 /* cv.sll.h */, RISCV::CV_SLL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7894 { 9277 /* cv.sll.sc.b */, RISCV::CV_SLL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7895 { 9289 /* cv.sll.sc.h */, RISCV::CV_SLL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7896 { 9301 /* cv.sll.sci.b */, RISCV::CV_SLL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
7897 { 9314 /* cv.sll.sci.h */, RISCV::CV_SLL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
7898 { 9327 /* cv.sra.b */, RISCV::CV_SRA_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7899 { 9336 /* cv.sra.h */, RISCV::CV_SRA_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7900 { 9345 /* cv.sra.sc.b */, RISCV::CV_SRA_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7901 { 9357 /* cv.sra.sc.h */, RISCV::CV_SRA_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7902 { 9369 /* cv.sra.sci.b */, RISCV::CV_SRA_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
7903 { 9382 /* cv.sra.sci.h */, RISCV::CV_SRA_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
7904 { 9395 /* cv.srl.b */, RISCV::CV_SRL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7905 { 9404 /* cv.srl.h */, RISCV::CV_SRL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7906 { 9413 /* cv.srl.sc.b */, RISCV::CV_SRL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7907 { 9425 /* cv.srl.sc.h */, RISCV::CV_SRL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7908 { 9437 /* cv.srl.sci.b */, RISCV::CV_SRL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
7909 { 9450 /* cv.srl.sci.h */, RISCV::CV_SRL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
7910 { 9463 /* cv.sub.b */, RISCV::CV_SUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7911 { 9472 /* cv.sub.div2 */, RISCV::CV_SUB_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7912 { 9484 /* cv.sub.div4 */, RISCV::CV_SUB_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7913 { 9496 /* cv.sub.div8 */, RISCV::CV_SUB_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7914 { 9508 /* cv.sub.h */, RISCV::CV_SUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7915 { 9517 /* cv.sub.sc.b */, RISCV::CV_SUB_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7916 { 9529 /* cv.sub.sc.h */, RISCV::CV_SUB_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7917 { 9541 /* cv.sub.sci.b */, RISCV::CV_SUB_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7918 { 9554 /* cv.sub.sci.h */, RISCV::CV_SUB_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7919 { 9567 /* cv.subn */, RISCV::CV_SUBN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7920 { 9575 /* cv.subnr */, RISCV::CV_SUBNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7921 { 9584 /* cv.subrn */, RISCV::CV_SUBRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7922 { 9593 /* cv.subrnr */, RISCV::CV_SUBRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7923 { 9603 /* cv.subrotmj */, RISCV::CV_SUBROTMJ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7924 { 9615 /* cv.subrotmj.div2 */, RISCV::CV_SUBROTMJ_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7925 { 9632 /* cv.subrotmj.div4 */, RISCV::CV_SUBROTMJ_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7926 { 9649 /* cv.subrotmj.div8 */, RISCV::CV_SUBROTMJ_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7927 { 9666 /* cv.subun */, RISCV::CV_SUBUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7928 { 9675 /* cv.subunr */, RISCV::CV_SUBUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7929 { 9685 /* cv.suburn */, RISCV::CV_SUBURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7930 { 9695 /* cv.suburnr */, RISCV::CV_SUBURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7931 { 9706 /* cv.sw */, RISCV::CV_SW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
7932 { 9706 /* cv.sw */, RISCV::CV_SW_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
7933 { 9706 /* cv.sw */, RISCV::CV_SW_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
7934 { 9712 /* cv.xor.b */, RISCV::CV_XOR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7935 { 9721 /* cv.xor.h */, RISCV::CV_XOR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7936 { 9730 /* cv.xor.sc.b */, RISCV::CV_XOR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7937 { 9742 /* cv.xor.sc.h */, RISCV::CV_XOR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7938 { 9754 /* cv.xor.sci.b */, RISCV::CV_XOR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7939 { 9767 /* cv.xor.sci.h */, RISCV::CV_XOR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7940 { 9780 /* czero.eqz */, RISCV::CZERO_EQZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7941 { 9790 /* czero.nez */, RISCV::CZERO_NEZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7942 { 9800 /* div */, RISCV::DIV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7943 { 9804 /* divu */, RISCV::DIVU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7944 { 9809 /* divuw */, RISCV::DIVUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7945 { 9815 /* divw */, RISCV::DIVW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7946 { 9820 /* dret */, RISCV::DRET, Convert_NoOperands, AMFBS_None, { }, },
7947 { 9825 /* ebreak */, RISCV::EBREAK, Convert_NoOperands, AMFBS_None, { }, },
7948 { 9832 /* ecall */, RISCV::ECALL, Convert_NoOperands, AMFBS_None, { }, },
7949 { 9838 /* fabs.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
7950 { 9838 /* fabs.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
7951 { 9838 /* fabs.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
7952 { 9845 /* fabs.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
7953 { 9845 /* fabs.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
7954 { 9852 /* fabs.q */, RISCV::FSGNJX_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
7955 { 9859 /* fabs.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
7956 { 9859 /* fabs.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
7957 { 9866 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
7958 { 9866 /* fadd.d */, RISCV::FADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
7959 { 9866 /* fadd.d */, RISCV::FADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
7960 { 9873 /* fadd.h */, RISCV::FADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
7961 { 9873 /* fadd.h */, RISCV::FADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
7962 { 9880 /* fadd.q */, RISCV::FADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
7963 { 9887 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
7964 { 9887 /* fadd.s */, RISCV::FADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
7965 { 9894 /* fclass.d */, RISCV::FCLASS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, },
7966 { 9894 /* fclass.d */, RISCV::FCLASS_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, },
7967 { 9894 /* fclass.d */, RISCV::FCLASS_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR }, },
7968 { 9903 /* fclass.h */, RISCV::FCLASS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16 }, },
7969 { 9903 /* fclass.h */, RISCV::FCLASS_H_INX, Convert__Reg1_0__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16 }, },
7970 { 9912 /* fclass.q */, RISCV::FCLASS_Q, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128 }, },
7971 { 9921 /* fclass.s */, RISCV::FCLASS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
7972 { 9921 /* fclass.s */, RISCV::FCLASS_S_INX, Convert__Reg1_0__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32 }, },
7973 { 9930 /* fcvt.bf16.s */, RISCV::FCVT_BF16_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
7974 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR64, MCK_FPR16, MCK_FRMArgLegacy }, },
7975 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
7976 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
7977 { 9951 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
7978 { 9951 /* fcvt.d.l */, RISCV::FCVT_D_L_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
7979 { 9960 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
7980 { 9960 /* fcvt.d.lu */, RISCV::FCVT_D_LU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
7981 { 9970 /* fcvt.d.q */, RISCV::FCVT_D_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR64, MCK_FPR128, MCK_FRMArg }, },
7982 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR32, MCK_FRMArgLegacy }, },
7983 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
7984 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
7985 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
7986 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
7987 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
7988 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
7989 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
7990 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
7991 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR16, MCK_FPR64, MCK_FRMArg }, },
7992 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D_INX, Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPRF64AsFPR, MCK_FRMArg }, },
7993 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D_IN32X, Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR16, MCK_GPRPairAsFPR, MCK_FRMArg }, },
7994 { 10016 /* fcvt.h.l */, RISCV::FCVT_H_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
7995 { 10016 /* fcvt.h.l */, RISCV::FCVT_H_L_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
7996 { 10025 /* fcvt.h.lu */, RISCV::FCVT_H_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
7997 { 10025 /* fcvt.h.lu */, RISCV::FCVT_H_LU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
7998 { 10035 /* fcvt.h.s */, RISCV::FCVT_H_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
7999 { 10035 /* fcvt.h.s */, RISCV::FCVT_H_S_INX, Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR16, MCK_GPRAsFPR32, MCK_FRMArg }, },
8000 { 10044 /* fcvt.h.w */, RISCV::FCVT_H_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8001 { 10044 /* fcvt.h.w */, RISCV::FCVT_H_W_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8002 { 10053 /* fcvt.h.wu */, RISCV::FCVT_H_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8003 { 10053 /* fcvt.h.wu */, RISCV::FCVT_H_WU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8004 { 10063 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8005 { 10063 /* fcvt.l.d */, RISCV::FCVT_L_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8006 { 10072 /* fcvt.l.h */, RISCV::FCVT_L_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8007 { 10072 /* fcvt.l.h */, RISCV::FCVT_L_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8008 { 10081 /* fcvt.l.q */, RISCV::FCVT_L_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8009 { 10090 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8010 { 10090 /* fcvt.l.s */, RISCV::FCVT_L_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8011 { 10099 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8012 { 10099 /* fcvt.lu.d */, RISCV::FCVT_LU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8013 { 10109 /* fcvt.lu.h */, RISCV::FCVT_LU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8014 { 10109 /* fcvt.lu.h */, RISCV::FCVT_LU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8015 { 10119 /* fcvt.lu.q */, RISCV::FCVT_LU_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8016 { 10129 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8017 { 10129 /* fcvt.lu.s */, RISCV::FCVT_LU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8018 { 10139 /* fcvt.q.d */, RISCV::FCVT_Q_D, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR64, MCK_FRMArgLegacy }, },
8019 { 10148 /* fcvt.q.l */, RISCV::FCVT_Q_L, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8020 { 10157 /* fcvt.q.lu */, RISCV::FCVT_Q_LU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8021 { 10167 /* fcvt.q.s */, RISCV::FCVT_Q_S, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR32, MCK_FRMArgLegacy }, },
8022 { 10176 /* fcvt.q.w */, RISCV::FCVT_Q_W, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8023 { 10185 /* fcvt.q.wu */, RISCV::FCVT_Q_WU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8024 { 10195 /* fcvt.s.bf16 */, RISCV::FCVT_S_BF16, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
8025 { 10207 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64, MCK_FRMArg }, },
8026 { 10207 /* fcvt.s.d */, RISCV::FCVT_S_D_INX, Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8027 { 10207 /* fcvt.s.d */, RISCV::FCVT_S_D_IN32X, Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR32, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8028 { 10216 /* fcvt.s.h */, RISCV::FCVT_S_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
8029 { 10216 /* fcvt.s.h */, RISCV::FCVT_S_H_INX, Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR32, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8030 { 10225 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8031 { 10225 /* fcvt.s.l */, RISCV::FCVT_S_L_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8032 { 10234 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8033 { 10234 /* fcvt.s.lu */, RISCV::FCVT_S_LU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8034 { 10244 /* fcvt.s.q */, RISCV::FCVT_S_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR32, MCK_FPR128, MCK_FRMArg }, },
8035 { 10253 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8036 { 10253 /* fcvt.s.w */, RISCV::FCVT_S_W_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8037 { 10262 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8038 { 10262 /* fcvt.s.wu */, RISCV::FCVT_S_WU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8039 { 10272 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8040 { 10272 /* fcvt.w.d */, RISCV::FCVT_W_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8041 { 10272 /* fcvt.w.d */, RISCV::FCVT_W_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8042 { 10281 /* fcvt.w.h */, RISCV::FCVT_W_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8043 { 10281 /* fcvt.w.h */, RISCV::FCVT_W_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8044 { 10290 /* fcvt.w.q */, RISCV::FCVT_W_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8045 { 10299 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8046 { 10299 /* fcvt.w.s */, RISCV::FCVT_W_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8047 { 10308 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8048 { 10308 /* fcvt.wu.d */, RISCV::FCVT_WU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8049 { 10308 /* fcvt.wu.d */, RISCV::FCVT_WU_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8050 { 10318 /* fcvt.wu.h */, RISCV::FCVT_WU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8051 { 10318 /* fcvt.wu.h */, RISCV::FCVT_WU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8052 { 10328 /* fcvt.wu.q */, RISCV::FCVT_WU_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8053 { 10338 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8054 { 10338 /* fcvt.wu.s */, RISCV::FCVT_WU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8055 { 10348 /* fcvtmod.w.d */, RISCV::FCVTMOD_W_D, Convert__Reg1_0__Reg1_1__RTZArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_RTZArg }, },
8056 { 10360 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8057 { 10360 /* fdiv.d */, RISCV::FDIV_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8058 { 10360 /* fdiv.d */, RISCV::FDIV_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8059 { 10367 /* fdiv.h */, RISCV::FDIV_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8060 { 10367 /* fdiv.h */, RISCV::FDIV_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8061 { 10374 /* fdiv.q */, RISCV::FDIV_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8062 { 10381 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8063 { 10381 /* fdiv.s */, RISCV::FDIV_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8064 { 10388 /* fence */, RISCV::FENCE, Convert__imm_95_15__imm_95_15, AMFBS_None, { }, },
8065 { 10388 /* fence */, RISCV::FENCE, Convert__FenceArg1_0__FenceArg1_1, AMFBS_None, { MCK_FenceArg, MCK_FenceArg }, },
8066 { 10394 /* fence.i */, RISCV::FENCE_I, Convert_NoOperands, AMFBS_None, { }, },
8067 { 10402 /* fence.tso */, RISCV::FENCE_TSO, Convert_NoOperands, AMFBS_None, { }, },
8068 { 10412 /* feq.d */, RISCV::FEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8069 { 10412 /* feq.d */, RISCV::FEQ_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8070 { 10412 /* feq.d */, RISCV::FEQ_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8071 { 10418 /* feq.h */, RISCV::FEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8072 { 10418 /* feq.h */, RISCV::FEQ_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8073 { 10424 /* feq.q */, RISCV::FEQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8074 { 10430 /* feq.s */, RISCV::FEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8075 { 10430 /* feq.s */, RISCV::FEQ_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8076 { 10436 /* fge.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8077 { 10436 /* fge.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8078 { 10436 /* fge.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8079 { 10442 /* fge.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8080 { 10442 /* fge.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8081 { 10448 /* fge.q */, RISCV::FLE_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8082 { 10454 /* fge.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8083 { 10454 /* fge.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8084 { 10460 /* fgeq.d */, RISCV::FLEQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8085 { 10467 /* fgeq.h */, RISCV::FLEQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8086 { 10474 /* fgeq.q */, RISCV::FLEQ_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8087 { 10481 /* fgeq.s */, RISCV::FLEQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8088 { 10488 /* fgt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8089 { 10488 /* fgt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8090 { 10488 /* fgt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8091 { 10494 /* fgt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8092 { 10494 /* fgt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8093 { 10500 /* fgt.q */, RISCV::FLT_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8094 { 10506 /* fgt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8095 { 10506 /* fgt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8096 { 10512 /* fgtq.d */, RISCV::FLTQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8097 { 10519 /* fgtq.h */, RISCV::FLTQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8098 { 10526 /* fgtq.q */, RISCV::FLTQ_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8099 { 10533 /* fgtq.s */, RISCV::FLTQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8100 { 10540 /* fld */, RISCV::PseudoFLD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
8101 { 10540 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
8102 { 10540 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8103 { 10544 /* fle.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8104 { 10544 /* fle.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8105 { 10544 /* fle.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8106 { 10550 /* fle.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8107 { 10550 /* fle.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8108 { 10556 /* fle.q */, RISCV::FLE_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8109 { 10562 /* fle.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8110 { 10562 /* fle.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8111 { 10568 /* fleq.d */, RISCV::FLEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8112 { 10575 /* fleq.h */, RISCV::FLEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8113 { 10582 /* fleq.q */, RISCV::FLEQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8114 { 10589 /* fleq.s */, RISCV::FLEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8115 { 10596 /* flh */, RISCV::PseudoFLH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, },
8116 { 10596 /* flh */, RISCV::FLH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, },
8117 { 10596 /* flh */, RISCV::FLH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8118 { 10600 /* fli.d */, RISCV::FLI_D, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_LoadFPImm }, },
8119 { 10606 /* fli.h */, RISCV::FLI_H, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh, { MCK_FPR16, MCK_LoadFPImm }, },
8120 { 10612 /* fli.q */, RISCV::FLI_Q, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_LoadFPImm }, },
8121 { 10618 /* fli.s */, RISCV::FLI_S, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_LoadFPImm }, },
8122 { 10624 /* flq */, RISCV::PseudoFLQ, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_BareSymbol, MCK_GPR }, },
8123 { 10624 /* flq */, RISCV::FLQ, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtQ, { MCK_FPR128, MCK__40_, MCK_GPR, MCK__41_ }, },
8124 { 10624 /* flq */, RISCV::FLQ, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8125 { 10628 /* flt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8126 { 10628 /* flt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8127 { 10628 /* flt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8128 { 10634 /* flt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8129 { 10634 /* flt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8130 { 10640 /* flt.q */, RISCV::FLT_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8131 { 10646 /* flt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8132 { 10646 /* flt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8133 { 10652 /* fltq.d */, RISCV::FLTQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8134 { 10659 /* fltq.h */, RISCV::FLTQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8135 { 10666 /* fltq.q */, RISCV::FLTQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8136 { 10673 /* fltq.s */, RISCV::FLTQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8137 { 10680 /* flw */, RISCV::PseudoFLW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
8138 { 10680 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
8139 { 10680 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8140 { 10684 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8141 { 10684 /* fmadd.d */, RISCV::FMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8142 { 10684 /* fmadd.d */, RISCV::FMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8143 { 10692 /* fmadd.h */, RISCV::FMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8144 { 10692 /* fmadd.h */, RISCV::FMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8145 { 10700 /* fmadd.q */, RISCV::FMADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8146 { 10708 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8147 { 10708 /* fmadd.s */, RISCV::FMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8148 { 10716 /* fmax.d */, RISCV::FMAX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8149 { 10716 /* fmax.d */, RISCV::FMAX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8150 { 10716 /* fmax.d */, RISCV::FMAX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8151 { 10723 /* fmax.h */, RISCV::FMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8152 { 10723 /* fmax.h */, RISCV::FMAX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8153 { 10730 /* fmax.q */, RISCV::FMAX_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8154 { 10737 /* fmax.s */, RISCV::FMAX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8155 { 10737 /* fmax.s */, RISCV::FMAX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8156 { 10744 /* fmaxm.d */, RISCV::FMAXM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8157 { 10752 /* fmaxm.h */, RISCV::FMAXM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8158 { 10760 /* fmaxm.q */, RISCV::FMAXM_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8159 { 10768 /* fmaxm.s */, RISCV::FMAXM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8160 { 10776 /* fmin.d */, RISCV::FMIN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8161 { 10776 /* fmin.d */, RISCV::FMIN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8162 { 10776 /* fmin.d */, RISCV::FMIN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8163 { 10783 /* fmin.h */, RISCV::FMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8164 { 10783 /* fmin.h */, RISCV::FMIN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8165 { 10790 /* fmin.q */, RISCV::FMIN_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8166 { 10797 /* fmin.s */, RISCV::FMIN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8167 { 10797 /* fmin.s */, RISCV::FMIN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8168 { 10804 /* fminm.d */, RISCV::FMINM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8169 { 10812 /* fminm.h */, RISCV::FMINM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8170 { 10820 /* fminm.q */, RISCV::FMINM_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8171 { 10828 /* fminm.s */, RISCV::FMINM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8172 { 10836 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8173 { 10836 /* fmsub.d */, RISCV::FMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8174 { 10836 /* fmsub.d */, RISCV::FMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8175 { 10844 /* fmsub.h */, RISCV::FMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8176 { 10844 /* fmsub.h */, RISCV::FMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8177 { 10852 /* fmsub.q */, RISCV::FMSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8178 { 10860 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8179 { 10860 /* fmsub.s */, RISCV::FMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8180 { 10868 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8181 { 10868 /* fmul.d */, RISCV::FMUL_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8182 { 10868 /* fmul.d */, RISCV::FMUL_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8183 { 10875 /* fmul.h */, RISCV::FMUL_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8184 { 10875 /* fmul.h */, RISCV::FMUL_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8185 { 10882 /* fmul.q */, RISCV::FMUL_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8186 { 10889 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8187 { 10889 /* fmul.s */, RISCV::FMUL_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8188 { 10896 /* fmv.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8189 { 10896 /* fmv.d */, RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8190 { 10896 /* fmv.d */, RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8191 { 10902 /* fmv.d.x */, RISCV::FMV_D_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, },
8192 { 10910 /* fmv.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8193 { 10910 /* fmv.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8194 { 10916 /* fmv.h.x */, RISCV::FMV_H_X, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_GPR }, },
8195 { 10924 /* fmv.q */, RISCV::FSGNJ_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8196 { 10930 /* fmv.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8197 { 10930 /* fmv.s */, RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8198 { 10936 /* fmv.w.x */, RISCV::FMV_W_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, },
8199 { 10944 /* fmv.x.d */, RISCV::FMV_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, },
8200 { 10952 /* fmv.x.h */, RISCV::FMV_X_H, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_GPR, MCK_FPR16 }, },
8201 { 10960 /* fmv.x.w */, RISCV::FMV_X_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
8202 { 10968 /* fmvh.x.d */, RISCV::FMVH_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_GPR, MCK_FPR64 }, },
8203 { 10977 /* fmvh.x.q */, RISCV::FMVH_X_Q, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128 }, },
8204 { 10986 /* fmvp.d.x */, RISCV::FMVP_D_X, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
8205 { 10995 /* fmvp.q.x */, RISCV::FMVP_Q_X, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_GPR }, },
8206 { 11004 /* fneg.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8207 { 11004 /* fneg.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8208 { 11004 /* fneg.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8209 { 11011 /* fneg.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8210 { 11011 /* fneg.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8211 { 11018 /* fneg.q */, RISCV::FSGNJN_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8212 { 11025 /* fneg.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8213 { 11025 /* fneg.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8214 { 11032 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8215 { 11032 /* fnmadd.d */, RISCV::FNMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8216 { 11032 /* fnmadd.d */, RISCV::FNMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8217 { 11041 /* fnmadd.h */, RISCV::FNMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8218 { 11041 /* fnmadd.h */, RISCV::FNMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8219 { 11050 /* fnmadd.q */, RISCV::FNMADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8220 { 11059 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8221 { 11059 /* fnmadd.s */, RISCV::FNMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8222 { 11068 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8223 { 11068 /* fnmsub.d */, RISCV::FNMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8224 { 11068 /* fnmsub.d */, RISCV::FNMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8225 { 11077 /* fnmsub.h */, RISCV::FNMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8226 { 11077 /* fnmsub.h */, RISCV::FNMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8227 { 11086 /* fnmsub.q */, RISCV::FNMSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8228 { 11095 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8229 { 11095 /* fnmsub.s */, RISCV::FNMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8230 { 11104 /* frcsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8231 { 11110 /* frflags */, RISCV::CSRRS, Convert__Reg1_0__imm_95_1__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8232 { 11118 /* fround.d */, RISCV::FROUND_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8233 { 11127 /* fround.h */, RISCV::FROUND_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8234 { 11136 /* fround.q */, RISCV::FROUND_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8235 { 11145 /* fround.s */, RISCV::FROUND_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8236 { 11154 /* froundnx.d */, RISCV::FROUNDNX_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8237 { 11165 /* froundnx.h */, RISCV::FROUNDNX_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8238 { 11176 /* froundnx.q */, RISCV::FROUNDNX_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8239 { 11187 /* froundnx.s */, RISCV::FROUNDNX_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8240 { 11198 /* frrm */, RISCV::CSRRS, Convert__Reg1_0__imm_95_2__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8241 { 11203 /* fscsr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8242 { 11203 /* fscsr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
8243 { 11209 /* fsd */, RISCV::PseudoFSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
8244 { 11209 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
8245 { 11209 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8246 { 11213 /* fsflags */, RISCV::CSRRW, Convert__regX0__imm_95_1__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8247 { 11213 /* fsflags */, RISCV::CSRRW, Convert__Reg1_0__imm_95_1__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
8248 { 11221 /* fsflagsi */, RISCV::CSRRWI, Convert__regX0__imm_95_1__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
8249 { 11221 /* fsflagsi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_1__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
8250 { 11230 /* fsgnj.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8251 { 11230 /* fsgnj.d */, RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8252 { 11230 /* fsgnj.d */, RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8253 { 11238 /* fsgnj.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8254 { 11238 /* fsgnj.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8255 { 11246 /* fsgnj.q */, RISCV::FSGNJ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8256 { 11254 /* fsgnj.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8257 { 11254 /* fsgnj.s */, RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8258 { 11262 /* fsgnjn.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8259 { 11262 /* fsgnjn.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8260 { 11262 /* fsgnjn.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8261 { 11271 /* fsgnjn.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8262 { 11271 /* fsgnjn.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8263 { 11280 /* fsgnjn.q */, RISCV::FSGNJN_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8264 { 11289 /* fsgnjn.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8265 { 11289 /* fsgnjn.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8266 { 11298 /* fsgnjx.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8267 { 11298 /* fsgnjx.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8268 { 11298 /* fsgnjx.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8269 { 11307 /* fsgnjx.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8270 { 11307 /* fsgnjx.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8271 { 11316 /* fsgnjx.q */, RISCV::FSGNJX_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8272 { 11325 /* fsgnjx.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8273 { 11325 /* fsgnjx.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8274 { 11334 /* fsh */, RISCV::PseudoFSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, },
8275 { 11334 /* fsh */, RISCV::FSH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, },
8276 { 11334 /* fsh */, RISCV::FSH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8277 { 11338 /* fsq */, RISCV::PseudoFSQ, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_BareSymbol, MCK_GPR }, },
8278 { 11338 /* fsq */, RISCV::FSQ, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtQ, { MCK_FPR128, MCK__40_, MCK_GPR, MCK__41_ }, },
8279 { 11338 /* fsq */, RISCV::FSQ, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8280 { 11342 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8281 { 11342 /* fsqrt.d */, RISCV::FSQRT_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8282 { 11342 /* fsqrt.d */, RISCV::FSQRT_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8283 { 11350 /* fsqrt.h */, RISCV::FSQRT_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8284 { 11350 /* fsqrt.h */, RISCV::FSQRT_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8285 { 11358 /* fsqrt.q */, RISCV::FSQRT_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8286 { 11366 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8287 { 11366 /* fsqrt.s */, RISCV::FSQRT_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8288 { 11374 /* fsrm */, RISCV::CSRRW, Convert__regX0__imm_95_2__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8289 { 11374 /* fsrm */, RISCV::CSRRW, Convert__Reg1_0__imm_95_2__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
8290 { 11379 /* fsrmi */, RISCV::CSRRWI, Convert__regX0__imm_95_2__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
8291 { 11379 /* fsrmi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_2__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
8292 { 11385 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8293 { 11385 /* fsub.d */, RISCV::FSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8294 { 11385 /* fsub.d */, RISCV::FSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8295 { 11392 /* fsub.h */, RISCV::FSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8296 { 11392 /* fsub.h */, RISCV::FSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8297 { 11399 /* fsub.q */, RISCV::FSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8298 { 11406 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8299 { 11406 /* fsub.s */, RISCV::FSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8300 { 11413 /* fsw */, RISCV::PseudoFSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
8301 { 11413 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
8302 { 11413 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8303 { 11417 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__regX0__regX0, AMFBS_None, { }, },
8304 { 11417 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
8305 { 11417 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
8306 { 11429 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__regX0__regX0, AMFBS_None, { }, },
8307 { 11429 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
8308 { 11429 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
8309 { 11441 /* hinval.gvma */, RISCV::HINVAL_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
8310 { 11453 /* hinval.vvma */, RISCV::HINVAL_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
8311 { 11465 /* hlv.b */, RISCV::HLV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8312 { 11471 /* hlv.bu */, RISCV::HLV_BU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8313 { 11478 /* hlv.d */, RISCV::HLV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8314 { 11484 /* hlv.h */, RISCV::HLV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8315 { 11490 /* hlv.hu */, RISCV::HLV_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8316 { 11497 /* hlv.w */, RISCV::HLV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8317 { 11503 /* hlv.wu */, RISCV::HLV_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8318 { 11510 /* hlvx.hu */, RISCV::HLVX_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8319 { 11518 /* hlvx.wu */, RISCV::HLVX_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8320 { 11526 /* hsv.b */, RISCV::HSV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8321 { 11532 /* hsv.d */, RISCV::HSV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8322 { 11538 /* hsv.h */, RISCV::HSV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8323 { 11544 /* hsv.w */, RISCV::HSV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8324 { 11550 /* j */, RISCV::JAL, Convert__regX0__BareSImm21Lsb01_0, AMFBS_None, { MCK_BareSImm21Lsb0 }, },
8325 { 11552 /* jal */, RISCV::JAL, Convert__regX1__BareSImm21Lsb01_0, AMFBS_None, { MCK_BareSImm21Lsb0 }, },
8326 { 11552 /* jal */, RISCV::JAL, Convert__Reg1_0__BareSImm21Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm21Lsb0 }, },
8327 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
8328 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8329 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
8330 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_1__imm_95_0, AMFBS_None, { MCK__40_, MCK_GPR, MCK__41_ }, },
8331 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
8332 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8333 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_2__SImm12LO1_0, AMFBS_None, { MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8334 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8335 { 11556 /* jalr */, RISCV::PseudoTLSDESCCall, Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_, MCK_TLSDESCCallSymbol }, },
8336 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
8337 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
8338 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_1__imm_95_0, AMFBS_None, { MCK__40_, MCK_GPR, MCK__41_ }, },
8339 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_2__SImm12LO1_0, AMFBS_None, { MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8340 { 11564 /* jump */, RISCV::PseudoJump, Convert__Reg1_1__PseudoJumpSymbol1_0, AMFBS_None, { MCK_PseudoJumpSymbol, MCK_GPR }, },
8341 { 11569 /* la */, RISCV::PseudoLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8342 { 11569 /* la */, RISCV::PseudoLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
8343 { 11572 /* la.tls.gd */, RISCV::PseudoLA_TLS_GD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8344 { 11582 /* la.tls.ie */, RISCV::PseudoLA_TLS_IE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8345 { 11592 /* la.tlsdesc */, RISCV::PseudoLA_TLSDESC, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8346 { 11603 /* lb */, RISCV::PseudoLB, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8347 { 11603 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8348 { 11603 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8349 { 11606 /* lb.aq */, RISCV::LB_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8350 { 11612 /* lb.aqrl */, RISCV::LB_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8351 { 11620 /* lbu */, RISCV::PseudoLBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8352 { 11620 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8353 { 11620 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8354 { 11624 /* ld */, RISCV::PseudoLD, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
8355 { 11624 /* ld */, RISCV::PseudoLD_RV32, Convert__GPRPairRV321_0__BareSymbol1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_BareSymbol }, },
8356 { 11624 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8357 { 11624 /* ld */, RISCV::LD_RV32, Convert__GPRPairRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK__40_, MCK_GPR, MCK__41_ }, },
8358 { 11624 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8359 { 11624 /* ld */, RISCV::LD_RV32, Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8360 { 11627 /* ld.aq */, RISCV::LD_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8361 { 11633 /* ld.aqrl */, RISCV::LD_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8362 { 11641 /* lga */, RISCV::PseudoLGA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8363 { 11645 /* lh */, RISCV::PseudoLH, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8364 { 11645 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8365 { 11645 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8366 { 11648 /* lh.aq */, RISCV::LH_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8367 { 11654 /* lh.aqrl */, RISCV::LH_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8368 { 11662 /* lhu */, RISCV::PseudoLHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8369 { 11662 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8370 { 11662 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8371 { 11666 /* li */, RISCV::ADDI, Convert__Reg1_0__regX0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
8372 { 11666 /* li */, RISCV::PseudoLI, Convert__Reg1_0__ImmXLenLI1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI }, },
8373 { 11669 /* lla */, RISCV::PseudoLLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8374 { 11669 /* lla */, RISCV::PseudoLLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
8375 { 11673 /* lpad */, RISCV::AUIPC, Convert__regX0__UImm201_0, AMFBS_None, { MCK_UImm20 }, },
8376 { 11678 /* lr.d */, RISCV::LR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8377 { 11683 /* lr.d.aq */, RISCV::LR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8378 { 11691 /* lr.d.aqrl */, RISCV::LR_D_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8379 { 11701 /* lr.d.rl */, RISCV::LR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8380 { 11709 /* lr.w */, RISCV::LR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8381 { 11714 /* lr.w.aq */, RISCV::LR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8382 { 11722 /* lr.w.aqrl */, RISCV::LR_W_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8383 { 11732 /* lr.w.rl */, RISCV::LR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8384 { 11740 /* lui */, RISCV::LUI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_None, { MCK_GPR, MCK_UImm20LUI }, },
8385 { 11744 /* lw */, RISCV::PseudoLW, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8386 { 11744 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8387 { 11744 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8388 { 11747 /* lw.aq */, RISCV::LW_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8389 { 11753 /* lw.aqrl */, RISCV::LW_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8390 { 11761 /* lwu */, RISCV::PseudoLWU, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
8391 { 11761 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8392 { 11761 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8393 { 11765 /* macc.h00 */, RISCV::MACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8394 { 11774 /* macc.h01 */, RISCV::MACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8395 { 11783 /* macc.h11 */, RISCV::MACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8396 { 11792 /* macc.w00 */, RISCV::MACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8397 { 11801 /* macc.w01 */, RISCV::MACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8398 { 11810 /* macc.w11 */, RISCV::MACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8399 { 11819 /* maccsu.h00 */, RISCV::MACCSU_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8400 { 11830 /* maccsu.h11 */, RISCV::MACCSU_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8401 { 11841 /* maccsu.w00 */, RISCV::MACCSU_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8402 { 11852 /* maccsu.w11 */, RISCV::MACCSU_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8403 { 11863 /* maccu.h00 */, RISCV::MACCU_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8404 { 11873 /* maccu.h01 */, RISCV::MACCU_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8405 { 11883 /* maccu.h11 */, RISCV::MACCU_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8406 { 11893 /* maccu.w00 */, RISCV::MACCU_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8407 { 11903 /* maccu.w01 */, RISCV::MACCU_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8408 { 11913 /* maccu.w11 */, RISCV::MACCU_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8409 { 11923 /* max */, RISCV::MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8410 { 11927 /* maxu */, RISCV::MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8411 { 11932 /* merge */, RISCV::MERGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8412 { 11938 /* mhacc */, RISCV::MHACC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8413 { 11944 /* mhacc.h0 */, RISCV::MHACC_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8414 { 11953 /* mhacc.h1 */, RISCV::MHACC_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8415 { 11962 /* mhaccsu */, RISCV::MHACCSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8416 { 11970 /* mhaccsu.h0 */, RISCV::MHACCSU_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8417 { 11981 /* mhaccsu.h1 */, RISCV::MHACCSU_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8418 { 11992 /* mhaccu */, RISCV::MHACCU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8419 { 11999 /* mhracc */, RISCV::MHRACC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8420 { 12006 /* mhraccsu */, RISCV::MHRACCSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8421 { 12015 /* mhraccu */, RISCV::MHRACCU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8422 { 12023 /* min */, RISCV::MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8423 { 12027 /* minu */, RISCV::MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8424 { 12032 /* mips.ccmov */, RISCV::MIPS_CCMOV, Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3, AMFBS_HasVendorXMIPSCMov, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8425 { 12043 /* mips.ehb */, RISCV::MIPS_EHB, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
8426 { 12052 /* mips.ihb */, RISCV::MIPS_IHB, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
8427 { 12061 /* mips.ldp */, RISCV::MIPS_LDP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb000, MCK__40_, MCK_GPR, MCK__41_ }, },
8428 { 12070 /* mips.lwp */, RISCV::MIPS_LWP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
8429 { 12079 /* mips.pause */, RISCV::MIPS_PAUSE, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
8430 { 12090 /* mips.pref */, RISCV::MIPS_PREF, Convert__Reg1_3__UImm91_1__UImm51_0, AMFBS_HasVendorXMIPSCBOP, { MCK_UImm5, MCK_UImm9, MCK__40_, MCK_GPR, MCK__41_ }, },
8431 { 12100 /* mips.sdp */, RISCV::MIPS_SDP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb000, MCK__40_, MCK_GPR, MCK__41_ }, },
8432 { 12109 /* mips.swp */, RISCV::MIPS_SWP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
8433 { 12118 /* mnret */, RISCV::MNRET, Convert_NoOperands, AMFBS_HasStdExtSmrnmi, { }, },
8434 { 12124 /* mop.r.0 */, RISCV::MOP_R_0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8435 { 12132 /* mop.r.1 */, RISCV::MOP_R_1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8436 { 12140 /* mop.r.10 */, RISCV::MOP_R_10, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8437 { 12149 /* mop.r.11 */, RISCV::MOP_R_11, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8438 { 12158 /* mop.r.12 */, RISCV::MOP_R_12, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8439 { 12167 /* mop.r.13 */, RISCV::MOP_R_13, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8440 { 12176 /* mop.r.14 */, RISCV::MOP_R_14, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8441 { 12185 /* mop.r.15 */, RISCV::MOP_R_15, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8442 { 12194 /* mop.r.16 */, RISCV::MOP_R_16, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8443 { 12203 /* mop.r.17 */, RISCV::MOP_R_17, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8444 { 12212 /* mop.r.18 */, RISCV::MOP_R_18, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8445 { 12221 /* mop.r.19 */, RISCV::MOP_R_19, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8446 { 12230 /* mop.r.2 */, RISCV::MOP_R_2, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8447 { 12238 /* mop.r.20 */, RISCV::MOP_R_20, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8448 { 12247 /* mop.r.21 */, RISCV::MOP_R_21, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8449 { 12256 /* mop.r.22 */, RISCV::MOP_R_22, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8450 { 12265 /* mop.r.23 */, RISCV::MOP_R_23, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8451 { 12274 /* mop.r.24 */, RISCV::MOP_R_24, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8452 { 12283 /* mop.r.25 */, RISCV::MOP_R_25, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8453 { 12292 /* mop.r.26 */, RISCV::MOP_R_26, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8454 { 12301 /* mop.r.27 */, RISCV::MOP_R_27, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8455 { 12310 /* mop.r.28 */, RISCV::MOP_R_28, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8456 { 12319 /* mop.r.29 */, RISCV::MOP_R_29, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8457 { 12328 /* mop.r.3 */, RISCV::MOP_R_3, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8458 { 12336 /* mop.r.30 */, RISCV::MOP_R_30, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8459 { 12345 /* mop.r.31 */, RISCV::MOP_R_31, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8460 { 12354 /* mop.r.4 */, RISCV::MOP_R_4, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8461 { 12362 /* mop.r.5 */, RISCV::MOP_R_5, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8462 { 12370 /* mop.r.6 */, RISCV::MOP_R_6, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8463 { 12378 /* mop.r.7 */, RISCV::MOP_R_7, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8464 { 12386 /* mop.r.8 */, RISCV::MOP_R_8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8465 { 12394 /* mop.r.9 */, RISCV::MOP_R_9, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8466 { 12402 /* mop.rr.0 */, RISCV::MOP_RR_0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8467 { 12411 /* mop.rr.1 */, RISCV::MOP_RR_1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8468 { 12420 /* mop.rr.2 */, RISCV::MOP_RR_2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8469 { 12429 /* mop.rr.3 */, RISCV::MOP_RR_3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8470 { 12438 /* mop.rr.4 */, RISCV::MOP_RR_4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8471 { 12447 /* mop.rr.5 */, RISCV::MOP_RR_5, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8472 { 12456 /* mop.rr.6 */, RISCV::MOP_RR_6, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8473 { 12465 /* mop.rr.7 */, RISCV::MOP_RR_7, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8474 { 12474 /* mqacc.h00 */, RISCV::MQACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8475 { 12484 /* mqacc.h01 */, RISCV::MQACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8476 { 12494 /* mqacc.h11 */, RISCV::MQACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8477 { 12504 /* mqacc.w00 */, RISCV::MQACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8478 { 12514 /* mqacc.w01 */, RISCV::MQACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8479 { 12524 /* mqacc.w11 */, RISCV::MQACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8480 { 12534 /* mqracc.h00 */, RISCV::MQRACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8481 { 12545 /* mqracc.h01 */, RISCV::MQRACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8482 { 12556 /* mqracc.h11 */, RISCV::MQRACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8483 { 12567 /* mqracc.w00 */, RISCV::MQRACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8484 { 12578 /* mqracc.w01 */, RISCV::MQRACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8485 { 12589 /* mqracc.w11 */, RISCV::MQRACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8486 { 12600 /* mqrwacc */, RISCV::MQRWACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8487 { 12608 /* mqwacc */, RISCV::MQWACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8488 { 12615 /* mret */, RISCV::MRET, Convert_NoOperands, AMFBS_None, { }, },
8489 { 12620 /* mseq */, RISCV::MSEQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8490 { 12625 /* mslt */, RISCV::MSLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8491 { 12630 /* msltu */, RISCV::MSLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8492 { 12636 /* mul */, RISCV::MUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8493 { 12640 /* mul.h00 */, RISCV::MUL_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8494 { 12648 /* mul.h01 */, RISCV::MUL_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8495 { 12656 /* mul.h11 */, RISCV::MUL_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8496 { 12664 /* mul.w00 */, RISCV::MUL_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8497 { 12672 /* mul.w01 */, RISCV::MUL_W01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8498 { 12680 /* mul.w11 */, RISCV::MUL_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8499 { 12688 /* mulh */, RISCV::MULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8500 { 12693 /* mulh.h0 */, RISCV::MULH_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8501 { 12701 /* mulh.h1 */, RISCV::MULH_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8502 { 12709 /* mulhr */, RISCV::MULHR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8503 { 12715 /* mulhrsu */, RISCV::MULHRSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8504 { 12723 /* mulhru */, RISCV::MULHRU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8505 { 12730 /* mulhsu */, RISCV::MULHSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8506 { 12737 /* mulhsu.h0 */, RISCV::MULHSU_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8507 { 12747 /* mulhsu.h1 */, RISCV::MULHSU_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8508 { 12757 /* mulhu */, RISCV::MULHU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8509 { 12763 /* mulq */, RISCV::MULQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8510 { 12768 /* mulqr */, RISCV::MULQR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8511 { 12774 /* mulsu.h00 */, RISCV::MULSU_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8512 { 12784 /* mulsu.h11 */, RISCV::MULSU_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8513 { 12794 /* mulsu.w00 */, RISCV::MULSU_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8514 { 12804 /* mulsu.w11 */, RISCV::MULSU_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8515 { 12814 /* mulu.h00 */, RISCV::MULU_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8516 { 12823 /* mulu.h01 */, RISCV::MULU_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8517 { 12832 /* mulu.h11 */, RISCV::MULU_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8518 { 12841 /* mulu.w00 */, RISCV::MULU_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8519 { 12850 /* mulu.w01 */, RISCV::MULU_W01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8520 { 12859 /* mulu.w11 */, RISCV::MULU_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8521 { 12868 /* mulw */, RISCV::MULW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8522 { 12873 /* mv */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8523 { 12876 /* mvm */, RISCV::MVM, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8524 { 12880 /* mvmn */, RISCV::MVMN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8525 { 12885 /* nclip */, RISCV::NCLIP, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8526 { 12891 /* nclipi */, RISCV::NCLIPI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8527 { 12898 /* nclipiu */, RISCV::NCLIPIU, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8528 { 12906 /* nclipr */, RISCV::NCLIPR, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8529 { 12913 /* nclipri */, RISCV::NCLIPRI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8530 { 12921 /* nclipriu */, RISCV::NCLIPRIU, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8531 { 12930 /* nclipru */, RISCV::NCLIPRU, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8532 { 12938 /* nclipu */, RISCV::NCLIPU, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8533 { 12945 /* nds.addigp */, RISCV::NDS_ADDIGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8534 { 12956 /* nds.bbc */, RISCV::NDS_BBC, Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImmLog2XLen, MCK_BareSImm11Lsb0 }, },
8535 { 12964 /* nds.bbs */, RISCV::NDS_BBS, Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImmLog2XLen, MCK_BareSImm11Lsb0 }, },
8536 { 12972 /* nds.beqc */, RISCV::NDS_BEQC, Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImm7, MCK_BareSImm11Lsb0 }, },
8537 { 12981 /* nds.bfos */, RISCV::NDS_BFOS, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
8538 { 12990 /* nds.bfoz */, RISCV::NDS_BFOZ, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
8539 { 12999 /* nds.bnec */, RISCV::NDS_BNEC, Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImm7, MCK_BareSImm11Lsb0 }, },
8540 { 13008 /* nds.fcvt.bf16.s */, RISCV::NDS_FCVT_BF16_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesBFHCvt, { MCK_FPR16, MCK_FPR32 }, },
8541 { 13024 /* nds.fcvt.s.bf16 */, RISCV::NDS_FCVT_S_BF16, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesBFHCvt, { MCK_FPR32, MCK_FPR16 }, },
8542 { 13040 /* nds.ffb */, RISCV::NDS_FFB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8543 { 13048 /* nds.ffmism */, RISCV::NDS_FFMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8544 { 13059 /* nds.ffzmism */, RISCV::NDS_FFZMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8545 { 13071 /* nds.flmism */, RISCV::NDS_FLMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8546 { 13082 /* nds.lbgp */, RISCV::NDS_LBGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8547 { 13091 /* nds.lbugp */, RISCV::NDS_LBUGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8548 { 13101 /* nds.ldgp */, RISCV::NDS_LDGP, Convert__Reg1_0__SImm20Lsb0001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm20Lsb000 }, },
8549 { 13110 /* nds.lea.b.ze */, RISCV::NDS_LEA_B_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8550 { 13123 /* nds.lea.d */, RISCV::NDS_LEA_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8551 { 13133 /* nds.lea.d.ze */, RISCV::NDS_LEA_D_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8552 { 13146 /* nds.lea.h */, RISCV::NDS_LEA_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8553 { 13156 /* nds.lea.h.ze */, RISCV::NDS_LEA_H_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8554 { 13169 /* nds.lea.w */, RISCV::NDS_LEA_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8555 { 13179 /* nds.lea.w.ze */, RISCV::NDS_LEA_W_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8556 { 13192 /* nds.lhgp */, RISCV::NDS_LHGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
8557 { 13201 /* nds.lhugp */, RISCV::NDS_LHUGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
8558 { 13211 /* nds.lwgp */, RISCV::NDS_LWGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm19Lsb00 }, },
8559 { 13220 /* nds.lwugp */, RISCV::NDS_LWUGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm19Lsb00 }, },
8560 { 13230 /* nds.sbgp */, RISCV::NDS_SBGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8561 { 13239 /* nds.sdgp */, RISCV::NDS_SDGP, Convert__Reg1_0__SImm20Lsb0001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm20Lsb000 }, },
8562 { 13248 /* nds.shgp */, RISCV::NDS_SHGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
8563 { 13257 /* nds.swgp */, RISCV::NDS_SWGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm19Lsb00 }, },
8564 { 13266 /* nds.vd4dots.vv */, RISCV::NDS_VD4DOTS_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8565 { 13281 /* nds.vd4dotsu.vv */, RISCV::NDS_VD4DOTSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8566 { 13297 /* nds.vd4dotu.vv */, RISCV::NDS_VD4DOTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8567 { 13312 /* nds.vfncvt.bf16.s */, RISCV::NDS_VFNCVT_BF16_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesVBFHCvt, { MCK_VR, MCK_VR }, },
8568 { 13330 /* nds.vfpmadb.vf */, RISCV::NDS_VFPMADB_VF, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVPackFPH, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8569 { 13345 /* nds.vfpmadt.vf */, RISCV::NDS_VFPMADT_VF, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVPackFPH, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8570 { 13360 /* nds.vfwcvt.f.b.v */, RISCV::NDS_VFWCVT_F_B, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8571 { 13377 /* nds.vfwcvt.f.bu.v */, RISCV::NDS_VFWCVT_F_BU, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8572 { 13395 /* nds.vfwcvt.f.n.v */, RISCV::NDS_VFWCVT_F_N, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8573 { 13412 /* nds.vfwcvt.f.nu.v */, RISCV::NDS_VFWCVT_F_NU, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8574 { 13430 /* nds.vfwcvt.s.bf16 */, RISCV::NDS_VFWCVT_S_BF16, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesVBFHCvt, { MCK_VR, MCK_VR }, },
8575 { 13448 /* nds.vle4.v */, RISCV::NDS_VLE4_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
8576 { 13459 /* nds.vln8.v */, RISCV::NDS_VLN8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntLoad, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
8577 { 13470 /* nds.vlnu8.v */, RISCV::NDS_VLNU8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntLoad, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
8578 { 13482 /* neg */, RISCV::SUB, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8579 { 13486 /* negw */, RISCV::SUBW, Convert__Reg1_0__regX0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
8580 { 13491 /* nop */, RISCV::ADDI, Convert__regX0__regX0__imm_95_0, AMFBS_None, { }, },
8581 { 13495 /* not */, RISCV::XORI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8582 { 13499 /* nsari */, RISCV::NSARI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8583 { 13505 /* nsra */, RISCV::NSRA, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8584 { 13510 /* nsrai */, RISCV::NSRAI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8585 { 13516 /* nsrar */, RISCV::NSRAR, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8586 { 13522 /* nsrl */, RISCV::NSRL, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8587 { 13527 /* nsrli */, RISCV::NSRLI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8588 { 13533 /* ntl.all */, RISCV::ADD, Convert__regX0__regX0__regX5, AMFBS_None, { }, },
8589 { 13541 /* ntl.p1 */, RISCV::ADD, Convert__regX0__regX0__regX2, AMFBS_None, { }, },
8590 { 13548 /* ntl.pall */, RISCV::ADD, Convert__regX0__regX0__regX3, AMFBS_None, { }, },
8591 { 13557 /* ntl.s1 */, RISCV::ADD, Convert__regX0__regX0__regX4, AMFBS_None, { }, },
8592 { 13564 /* or */, RISCV::OR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8593 { 13564 /* or */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
8594 { 13567 /* orc.b */, RISCV::ORC_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
8595 { 13573 /* ori */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
8596 { 13577 /* orn */, RISCV::ORN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8597 { 13581 /* paadd.b */, RISCV::PAADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8598 { 13589 /* paadd.db */, RISCV::PAADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8599 { 13598 /* paadd.dh */, RISCV::PAADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8600 { 13607 /* paadd.dw */, RISCV::PAADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8601 { 13616 /* paadd.h */, RISCV::PAADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8602 { 13624 /* paadd.w */, RISCV::PAADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8603 { 13632 /* paaddu.b */, RISCV::PAADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8604 { 13641 /* paaddu.db */, RISCV::PAADDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8605 { 13651 /* paaddu.dh */, RISCV::PAADDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8606 { 13661 /* paaddu.dw */, RISCV::PAADDU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8607 { 13671 /* paaddu.h */, RISCV::PAADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8608 { 13680 /* paaddu.w */, RISCV::PAADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8609 { 13689 /* paas.hx */, RISCV::PAAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8610 { 13697 /* paas.wx */, RISCV::PAAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8611 { 13705 /* paax.dhx */, RISCV::PAAX_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8612 { 13714 /* pabd.b */, RISCV::PABD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8613 { 13721 /* pabd.db */, RISCV::PABD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8614 { 13729 /* pabd.dh */, RISCV::PABD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8615 { 13737 /* pabd.h */, RISCV::PABD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8616 { 13744 /* pabdsumau.b */, RISCV::PABDSUMAU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8617 { 13756 /* pabdsumu.b */, RISCV::PABDSUMU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8618 { 13767 /* pabdu.b */, RISCV::PABDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8619 { 13775 /* pabdu.db */, RISCV::PABDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8620 { 13784 /* pabdu.dh */, RISCV::PABDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8621 { 13793 /* pabdu.h */, RISCV::PABDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8622 { 13801 /* pack */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkbOrP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8623 { 13806 /* packh */, RISCV::PACKH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8624 { 13812 /* packw */, RISCV::PACKW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8625 { 13818 /* padd.b */, RISCV::PADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8626 { 13825 /* padd.bs */, RISCV::PADD_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8627 { 13833 /* padd.db */, RISCV::PADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8628 { 13841 /* padd.dbs */, RISCV::PADD_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8629 { 13850 /* padd.dh */, RISCV::PADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8630 { 13858 /* padd.dhs */, RISCV::PADD_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8631 { 13867 /* padd.dw */, RISCV::PADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8632 { 13875 /* padd.dws */, RISCV::PADD_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8633 { 13884 /* padd.h */, RISCV::PADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8634 { 13891 /* padd.hs */, RISCV::PADD_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8635 { 13899 /* padd.w */, RISCV::PADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8636 { 13906 /* padd.ws */, RISCV::PADD_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8637 { 13914 /* pas.dhx */, RISCV::PAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8638 { 13922 /* pas.hx */, RISCV::PAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8639 { 13929 /* pas.wx */, RISCV::PAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8640 { 13936 /* pasa.dhx */, RISCV::PASA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8641 { 13945 /* pasa.hx */, RISCV::PASA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8642 { 13953 /* pasa.wx */, RISCV::PASA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8643 { 13961 /* pasub.b */, RISCV::PASUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8644 { 13969 /* pasub.db */, RISCV::PASUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8645 { 13978 /* pasub.dh */, RISCV::PASUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8646 { 13987 /* pasub.dw */, RISCV::PASUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8647 { 13996 /* pasub.h */, RISCV::PASUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8648 { 14004 /* pasub.w */, RISCV::PASUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8649 { 14012 /* pasubu.b */, RISCV::PASUBU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8650 { 14021 /* pasubu.db */, RISCV::PASUBU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8651 { 14031 /* pasubu.dh */, RISCV::PASUBU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8652 { 14041 /* pasubu.dw */, RISCV::PASUBU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8653 { 14051 /* pasubu.h */, RISCV::PASUBU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8654 { 14060 /* pasubu.w */, RISCV::PASUBU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8655 { 14069 /* pause */, RISCV::FENCE, Convert__imm_95_1__imm_95_0, AMFBS_None, { }, },
8656 { 14075 /* pli.b */, RISCV::PLI_B, Convert__Reg1_0__SImm8Unsigned1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm8Unsigned }, },
8657 { 14081 /* pli.db */, RISCV::PLI_DB, Convert__GPRPairRV321_0__SImm8Unsigned1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm8Unsigned }, },
8658 { 14088 /* pli.dh */, RISCV::PLI_DH, Convert__GPRPairRV321_0__SImm101_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm10 }, },
8659 { 14095 /* pli.h */, RISCV::PLI_H, Convert__Reg1_0__SImm101_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm10 }, },
8660 { 14101 /* pli.w */, RISCV::PLI_W, Convert__Reg1_0__SImm101_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_SImm10 }, },
8661 { 14107 /* plui.dh */, RISCV::PLUI_DH, Convert__GPRPairRV321_0__SImm10Unsigned1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm10Unsigned }, },
8662 { 14115 /* plui.h */, RISCV::PLUI_H, Convert__Reg1_0__SImm10Unsigned1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm10Unsigned }, },
8663 { 14122 /* plui.w */, RISCV::PLUI_W, Convert__Reg1_0__SImm10Unsigned1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_SImm10Unsigned }, },
8664 { 14129 /* pm2add.h */, RISCV::PM2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8665 { 14138 /* pm2add.hx */, RISCV::PM2ADD_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8666 { 14148 /* pm2add.w */, RISCV::PM2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8667 { 14157 /* pm2add.wx */, RISCV::PM2ADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8668 { 14167 /* pm2adda.h */, RISCV::PM2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8669 { 14177 /* pm2adda.hx */, RISCV::PM2ADDA_HX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8670 { 14188 /* pm2adda.w */, RISCV::PM2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8671 { 14198 /* pm2adda.wx */, RISCV::PM2ADDA_WX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8672 { 14209 /* pm2addasu.h */, RISCV::PM2ADDASU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8673 { 14221 /* pm2addasu.w */, RISCV::PM2ADDASU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8674 { 14233 /* pm2addau.h */, RISCV::PM2ADDAU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8675 { 14244 /* pm2addau.w */, RISCV::PM2ADDAU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8676 { 14255 /* pm2addsu.h */, RISCV::PM2ADDSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8677 { 14266 /* pm2addsu.w */, RISCV::PM2ADDSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8678 { 14277 /* pm2addu.h */, RISCV::PM2ADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8679 { 14287 /* pm2addu.w */, RISCV::PM2ADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8680 { 14297 /* pm2sadd.h */, RISCV::PM2SADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8681 { 14307 /* pm2sadd.hx */, RISCV::PM2SADD_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8682 { 14318 /* pm2sub.h */, RISCV::PM2SUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8683 { 14327 /* pm2sub.hx */, RISCV::PM2SUB_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8684 { 14337 /* pm2sub.w */, RISCV::PM2SUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8685 { 14346 /* pm2sub.wx */, RISCV::PM2SUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8686 { 14356 /* pm2suba.h */, RISCV::PM2SUBA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8687 { 14366 /* pm2suba.hx */, RISCV::PM2SUBA_HX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8688 { 14377 /* pm2suba.w */, RISCV::PM2SUBA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8689 { 14387 /* pm2suba.wx */, RISCV::PM2SUBA_WX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8690 { 14398 /* pm2wadd.h */, RISCV::PM2WADD_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8691 { 14408 /* pm2wadd.hx */, RISCV::PM2WADD_HX, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8692 { 14419 /* pm2wadda.h */, RISCV::PM2WADDA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8693 { 14430 /* pm2wadda.hx */, RISCV::PM2WADDA_HX, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8694 { 14442 /* pm2waddasu.h */, RISCV::PM2WADDASU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8695 { 14455 /* pm2waddau.h */, RISCV::PM2WADDAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8696 { 14467 /* pm2waddsu.h */, RISCV::PM2WADDSU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8697 { 14479 /* pm2waddu.h */, RISCV::PM2WADDU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8698 { 14490 /* pm2wsub.h */, RISCV::PM2WSUB_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8699 { 14500 /* pm2wsub.hx */, RISCV::PM2WSUB_HX, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8700 { 14511 /* pm2wsuba.h */, RISCV::PM2WSUBA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8701 { 14522 /* pm2wsuba.hx */, RISCV::PM2WSUBA_HX, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8702 { 14534 /* pm4add.b */, RISCV::PM4ADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8703 { 14543 /* pm4add.h */, RISCV::PM4ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8704 { 14552 /* pm4adda.b */, RISCV::PM4ADDA_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8705 { 14562 /* pm4adda.h */, RISCV::PM4ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8706 { 14572 /* pm4addasu.b */, RISCV::PM4ADDASU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8707 { 14584 /* pm4addasu.h */, RISCV::PM4ADDASU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8708 { 14596 /* pm4addau.b */, RISCV::PM4ADDAU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8709 { 14607 /* pm4addau.h */, RISCV::PM4ADDAU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8710 { 14618 /* pm4addsu.b */, RISCV::PM4ADDSU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8711 { 14629 /* pm4addsu.h */, RISCV::PM4ADDSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8712 { 14640 /* pm4addu.b */, RISCV::PM4ADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8713 { 14650 /* pm4addu.h */, RISCV::PM4ADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8714 { 14660 /* pmacc.w.h00 */, RISCV::PMACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8715 { 14672 /* pmacc.w.h01 */, RISCV::PMACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8716 { 14684 /* pmacc.w.h11 */, RISCV::PMACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8717 { 14696 /* pmaccsu.w.h00 */, RISCV::PMACCSU_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8718 { 14710 /* pmaccsu.w.h11 */, RISCV::PMACCSU_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8719 { 14724 /* pmaccu.w.h00 */, RISCV::PMACCU_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8720 { 14737 /* pmaccu.w.h01 */, RISCV::PMACCU_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8721 { 14750 /* pmaccu.w.h11 */, RISCV::PMACCU_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8722 { 14763 /* pmax.b */, RISCV::PMAX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8723 { 14770 /* pmax.db */, RISCV::PMAX_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8724 { 14778 /* pmax.dh */, RISCV::PMAX_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8725 { 14786 /* pmax.dw */, RISCV::PMAX_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8726 { 14794 /* pmax.h */, RISCV::PMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8727 { 14801 /* pmax.w */, RISCV::PMAX_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8728 { 14808 /* pmaxu.b */, RISCV::PMAXU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8729 { 14816 /* pmaxu.db */, RISCV::PMAXU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8730 { 14825 /* pmaxu.dh */, RISCV::PMAXU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8731 { 14834 /* pmaxu.dw */, RISCV::PMAXU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8732 { 14843 /* pmaxu.h */, RISCV::PMAXU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8733 { 14851 /* pmaxu.w */, RISCV::PMAXU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8734 { 14859 /* pmhacc.h */, RISCV::PMHACC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8735 { 14868 /* pmhacc.h.b0 */, RISCV::PMHACC_H_B0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8736 { 14880 /* pmhacc.h.b1 */, RISCV::PMHACC_H_B1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8737 { 14892 /* pmhacc.w */, RISCV::PMHACC_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8738 { 14901 /* pmhacc.w.h0 */, RISCV::PMHACC_W_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8739 { 14913 /* pmhacc.w.h1 */, RISCV::PMHACC_W_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8740 { 14925 /* pmhaccsu.h */, RISCV::PMHACCSU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8741 { 14936 /* pmhaccsu.h.b0 */, RISCV::PMHACCSU_H_B0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8742 { 14950 /* pmhaccsu.h.b1 */, RISCV::PMHACCSU_H_B1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8743 { 14964 /* pmhaccsu.w */, RISCV::PMHACCSU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8744 { 14975 /* pmhaccsu.w.h0 */, RISCV::PMHACCSU_W_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8745 { 14989 /* pmhaccsu.w.h1 */, RISCV::PMHACCSU_W_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8746 { 15003 /* pmhaccu.h */, RISCV::PMHACCU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8747 { 15013 /* pmhaccu.w */, RISCV::PMHACCU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8748 { 15023 /* pmhracc.h */, RISCV::PMHRACC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8749 { 15033 /* pmhracc.w */, RISCV::PMHRACC_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8750 { 15043 /* pmhraccsu.h */, RISCV::PMHRACCSU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8751 { 15055 /* pmhraccsu.w */, RISCV::PMHRACCSU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8752 { 15067 /* pmhraccu.h */, RISCV::PMHRACCU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8753 { 15078 /* pmhraccu.w */, RISCV::PMHRACCU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8754 { 15089 /* pmin.b */, RISCV::PMIN_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8755 { 15096 /* pmin.db */, RISCV::PMIN_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8756 { 15104 /* pmin.dh */, RISCV::PMIN_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8757 { 15112 /* pmin.dw */, RISCV::PMIN_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8758 { 15120 /* pmin.h */, RISCV::PMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8759 { 15127 /* pmin.w */, RISCV::PMIN_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8760 { 15134 /* pminu.b */, RISCV::PMINU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8761 { 15142 /* pminu.db */, RISCV::PMINU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8762 { 15151 /* pminu.dh */, RISCV::PMINU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8763 { 15160 /* pminu.dw */, RISCV::PMINU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8764 { 15169 /* pminu.h */, RISCV::PMINU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8765 { 15177 /* pminu.w */, RISCV::PMINU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8766 { 15185 /* pmq2add.h */, RISCV::PMQ2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8767 { 15195 /* pmq2add.w */, RISCV::PMQ2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8768 { 15205 /* pmq2adda.h */, RISCV::PMQ2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8769 { 15216 /* pmq2adda.w */, RISCV::PMQ2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8770 { 15227 /* pmqacc.w.h00 */, RISCV::PMQACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8771 { 15240 /* pmqacc.w.h01 */, RISCV::PMQACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8772 { 15253 /* pmqacc.w.h11 */, RISCV::PMQACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8773 { 15266 /* pmqr2add.h */, RISCV::PMQR2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8774 { 15277 /* pmqr2add.w */, RISCV::PMQR2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8775 { 15288 /* pmqr2adda.h */, RISCV::PMQR2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8776 { 15300 /* pmqr2adda.w */, RISCV::PMQR2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8777 { 15312 /* pmqracc.w.h00 */, RISCV::PMQRACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8778 { 15326 /* pmqracc.w.h01 */, RISCV::PMQRACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8779 { 15340 /* pmqracc.w.h11 */, RISCV::PMQRACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8780 { 15354 /* pmqrwacc.h */, RISCV::PMQRWACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8781 { 15365 /* pmqwacc.h */, RISCV::PMQWACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8782 { 15375 /* pmseq.b */, RISCV::PMSEQ_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8783 { 15383 /* pmseq.db */, RISCV::PMSEQ_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8784 { 15392 /* pmseq.dh */, RISCV::PMSEQ_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8785 { 15401 /* pmseq.dw */, RISCV::PMSEQ_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8786 { 15410 /* pmseq.h */, RISCV::PMSEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8787 { 15418 /* pmseq.w */, RISCV::PMSEQ_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8788 { 15426 /* pmslt.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8789 { 15434 /* pmslt.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8790 { 15443 /* pmslt.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8791 { 15452 /* pmslt.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8792 { 15461 /* pmslt.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8793 { 15469 /* pmslt.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8794 { 15477 /* pmsltu.b */, RISCV::PMSLTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8795 { 15486 /* pmsltu.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8796 { 15496 /* pmsltu.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8797 { 15506 /* pmsltu.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8798 { 15516 /* pmsltu.h */, RISCV::PMSLTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8799 { 15525 /* pmsltu.w */, RISCV::PMSLTU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8800 { 15534 /* pmul.h.b00 */, RISCV::PMUL_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8801 { 15545 /* pmul.h.b01 */, RISCV::PMUL_H_B01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8802 { 15556 /* pmul.h.b11 */, RISCV::PMUL_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8803 { 15567 /* pmul.w.h00 */, RISCV::PMUL_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8804 { 15578 /* pmul.w.h01 */, RISCV::PMUL_W_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8805 { 15589 /* pmul.w.h11 */, RISCV::PMUL_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8806 { 15600 /* pmulh.h */, RISCV::PMULH_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8807 { 15608 /* pmulh.h.b0 */, RISCV::PMULH_H_B0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8808 { 15619 /* pmulh.h.b1 */, RISCV::PMULH_H_B1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8809 { 15630 /* pmulh.w */, RISCV::PMULH_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8810 { 15638 /* pmulh.w.h0 */, RISCV::PMULH_W_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8811 { 15649 /* pmulh.w.h1 */, RISCV::PMULH_W_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8812 { 15660 /* pmulhr.h */, RISCV::PMULHR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8813 { 15669 /* pmulhr.w */, RISCV::PMULHR_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8814 { 15678 /* pmulhrsu.h */, RISCV::PMULHRSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8815 { 15689 /* pmulhrsu.w */, RISCV::PMULHRSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8816 { 15700 /* pmulhru.h */, RISCV::PMULHRU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8817 { 15710 /* pmulhru.w */, RISCV::PMULHRU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8818 { 15720 /* pmulhsu.h */, RISCV::PMULHSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8819 { 15730 /* pmulhsu.h.b0 */, RISCV::PMULHSU_H_B0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8820 { 15743 /* pmulhsu.h.b1 */, RISCV::PMULHSU_H_B1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8821 { 15756 /* pmulhsu.w */, RISCV::PMULHSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8822 { 15766 /* pmulhsu.w.h0 */, RISCV::PMULHSU_W_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8823 { 15779 /* pmulhsu.w.h1 */, RISCV::PMULHSU_W_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8824 { 15792 /* pmulhu.h */, RISCV::PMULHU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8825 { 15801 /* pmulhu.w */, RISCV::PMULHU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8826 { 15810 /* pmulq.h */, RISCV::PMULQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8827 { 15818 /* pmulq.w */, RISCV::PMULQ_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8828 { 15826 /* pmulqr.h */, RISCV::PMULQR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8829 { 15835 /* pmulqr.w */, RISCV::PMULQR_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8830 { 15844 /* pmulsu.h.b00 */, RISCV::PMULSU_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8831 { 15857 /* pmulsu.h.b11 */, RISCV::PMULSU_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8832 { 15870 /* pmulsu.w.h00 */, RISCV::PMULSU_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8833 { 15883 /* pmulsu.w.h11 */, RISCV::PMULSU_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8834 { 15896 /* pmulu.h.b00 */, RISCV::PMULU_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8835 { 15908 /* pmulu.h.b01 */, RISCV::PMULU_H_B01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8836 { 15920 /* pmulu.h.b11 */, RISCV::PMULU_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8837 { 15932 /* pmulu.w.h00 */, RISCV::PMULU_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8838 { 15944 /* pmulu.w.h01 */, RISCV::PMULU_W_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8839 { 15956 /* pmulu.w.h11 */, RISCV::PMULU_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8840 { 15968 /* pnclip.bs */, RISCV::PNCLIP_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8841 { 15978 /* pnclip.hs */, RISCV::PNCLIP_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8842 { 15988 /* pnclipi.b */, RISCV::PNCLIPI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
8843 { 15998 /* pnclipi.h */, RISCV::PNCLIPI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
8844 { 16008 /* pnclipiu.b */, RISCV::PNCLIPIU_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
8845 { 16019 /* pnclipiu.h */, RISCV::PNCLIPIU_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
8846 { 16030 /* pnclipr.bs */, RISCV::PNCLIPR_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8847 { 16041 /* pnclipr.hs */, RISCV::PNCLIPR_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8848 { 16052 /* pnclipri.b */, RISCV::PNCLIPRI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
8849 { 16063 /* pnclipri.h */, RISCV::PNCLIPRI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
8850 { 16074 /* pnclipriu.b */, RISCV::PNCLIPRIU_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
8851 { 16086 /* pnclipriu.h */, RISCV::PNCLIPRIU_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
8852 { 16098 /* pnclipru.bs */, RISCV::PNCLIPRU_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8853 { 16110 /* pnclipru.hs */, RISCV::PNCLIPRU_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8854 { 16122 /* pnclipu.bs */, RISCV::PNCLIPU_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8855 { 16133 /* pnclipu.hs */, RISCV::PNCLIPU_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8856 { 16144 /* pnsari.b */, RISCV::PNSARI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
8857 { 16153 /* pnsari.h */, RISCV::PNSARI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
8858 { 16162 /* pnsra.bs */, RISCV::PNSRA_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8859 { 16171 /* pnsra.hs */, RISCV::PNSRA_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8860 { 16180 /* pnsrai.b */, RISCV::PNSRAI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
8861 { 16189 /* pnsrai.h */, RISCV::PNSRAI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
8862 { 16198 /* pnsrar.bs */, RISCV::PNSRAR_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8863 { 16208 /* pnsrar.hs */, RISCV::PNSRAR_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8864 { 16218 /* pnsrl.bs */, RISCV::PNSRL_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8865 { 16227 /* pnsrl.hs */, RISCV::PNSRL_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8866 { 16236 /* pnsrli.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
8867 { 16245 /* pnsrli.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
8868 { 16254 /* ppaire.b */, RISCV::PPAIRE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8869 { 16263 /* ppaire.db */, RISCV::PPAIRE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8870 { 16273 /* ppaire.dh */, RISCV::PPAIRE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8871 { 16283 /* ppaire.h */, RISCV::PPAIRE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8872 { 16292 /* ppaireo.b */, RISCV::PPAIREO_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8873 { 16302 /* ppaireo.db */, RISCV::PPAIREO_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8874 { 16313 /* ppaireo.dh */, RISCV::PPAIREO_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8875 { 16324 /* ppaireo.h */, RISCV::PPAIREO_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8876 { 16334 /* ppaireo.w */, RISCV::PPAIREO_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8877 { 16344 /* ppairo.b */, RISCV::PPAIRO_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8878 { 16353 /* ppairo.db */, RISCV::PPAIRO_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8879 { 16363 /* ppairo.dh */, RISCV::PPAIRO_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8880 { 16373 /* ppairo.h */, RISCV::PPAIRO_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8881 { 16382 /* ppairo.w */, RISCV::PPAIRO_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8882 { 16391 /* ppairoe.b */, RISCV::PPAIROE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8883 { 16401 /* ppairoe.db */, RISCV::PPAIROE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8884 { 16412 /* ppairoe.dh */, RISCV::PPAIROE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8885 { 16423 /* ppairoe.h */, RISCV::PPAIROE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8886 { 16433 /* ppairoe.w */, RISCV::PPAIROE_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8887 { 16443 /* predsum.bs */, RISCV::PREDSUM_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8888 { 16454 /* predsum.dbs */, RISCV::PREDSUM_DBS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8889 { 16466 /* predsum.dhs */, RISCV::PREDSUM_DHS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8890 { 16478 /* predsum.hs */, RISCV::PREDSUM_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8891 { 16489 /* predsum.ws */, RISCV::PREDSUM_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8892 { 16500 /* predsumu.bs */, RISCV::PREDSUMU_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8893 { 16512 /* predsumu.dbs */, RISCV::PREDSUMU_DBS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8894 { 16525 /* predsumu.dhs */, RISCV::PREDSUMU_DHS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8895 { 16538 /* predsumu.hs */, RISCV::PREDSUMU_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8896 { 16550 /* predsumu.ws */, RISCV::PREDSUMU_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8897 { 16562 /* prefetch.i */, RISCV::PREFETCH_I, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_HasStdExtZicbop, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
8898 { 16573 /* prefetch.r */, RISCV::PREFETCH_R, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_HasStdExtZicbop, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
8899 { 16584 /* prefetch.w */, RISCV::PREFETCH_W, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_HasStdExtZicbop, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
8900 { 16595 /* psa.dhx */, RISCV::PSA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8901 { 16603 /* psa.hx */, RISCV::PSA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8902 { 16610 /* psa.wx */, RISCV::PSA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8903 { 16617 /* psabs.b */, RISCV::PSABS_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
8904 { 16625 /* psabs.db */, RISCV::PSABS_DB, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8905 { 16634 /* psabs.dh */, RISCV::PSABS_DH, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8906 { 16643 /* psabs.h */, RISCV::PSABS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
8907 { 16651 /* psadd.b */, RISCV::PSADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8908 { 16659 /* psadd.db */, RISCV::PSADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8909 { 16668 /* psadd.dh */, RISCV::PSADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8910 { 16677 /* psadd.dw */, RISCV::PSADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8911 { 16686 /* psadd.h */, RISCV::PSADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8912 { 16694 /* psadd.w */, RISCV::PSADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8913 { 16702 /* psaddu.b */, RISCV::PSADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8914 { 16711 /* psaddu.db */, RISCV::PSADDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8915 { 16721 /* psaddu.dh */, RISCV::PSADDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8916 { 16731 /* psaddu.dw */, RISCV::PSADDU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8917 { 16741 /* psaddu.h */, RISCV::PSADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8918 { 16750 /* psaddu.w */, RISCV::PSADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8919 { 16759 /* psas.dhx */, RISCV::PSAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8920 { 16768 /* psas.hx */, RISCV::PSAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8921 { 16776 /* psas.wx */, RISCV::PSAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8922 { 16784 /* psati.dh */, RISCV::PSATI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
8923 { 16793 /* psati.dw */, RISCV::PSATI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
8924 { 16802 /* psati.h */, RISCV::PSATI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8925 { 16810 /* psati.w */, RISCV::PSATI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8926 { 16818 /* psext.dh.b */, RISCV::PSEXT_DH_B, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8927 { 16829 /* psext.dw.b */, RISCV::PSEXT_DW_B, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8928 { 16840 /* psext.dw.h */, RISCV::PSEXT_DW_H, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8929 { 16851 /* psext.h.b */, RISCV::PSEXT_H_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
8930 { 16861 /* psext.w.b */, RISCV::PSEXT_W_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
8931 { 16871 /* psext.w.h */, RISCV::PSEXT_W_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
8932 { 16881 /* psh1add.dh */, RISCV::PSH1ADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8933 { 16892 /* psh1add.dw */, RISCV::PSH1ADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8934 { 16903 /* psh1add.h */, RISCV::PSH1ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8935 { 16913 /* psh1add.w */, RISCV::PSH1ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8936 { 16923 /* psll.bs */, RISCV::PSLL_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8937 { 16931 /* psll.dbs */, RISCV::PSLL_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8938 { 16940 /* psll.dhs */, RISCV::PSLL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8939 { 16949 /* psll.dws */, RISCV::PSLL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8940 { 16958 /* psll.hs */, RISCV::PSLL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8941 { 16966 /* psll.ws */, RISCV::PSLL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8942 { 16974 /* pslli.b */, RISCV::PSLLI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8943 { 16982 /* pslli.db */, RISCV::PSLLI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
8944 { 16991 /* pslli.dh */, RISCV::PSLLI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
8945 { 17000 /* pslli.dw */, RISCV::PSLLI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
8946 { 17009 /* pslli.h */, RISCV::PSLLI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8947 { 17017 /* pslli.w */, RISCV::PSLLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8948 { 17025 /* psra.bs */, RISCV::PSRA_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8949 { 17033 /* psra.dbs */, RISCV::PSRA_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8950 { 17042 /* psra.dhs */, RISCV::PSRA_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8951 { 17051 /* psra.dws */, RISCV::PSRA_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8952 { 17060 /* psra.hs */, RISCV::PSRA_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8953 { 17068 /* psra.ws */, RISCV::PSRA_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8954 { 17076 /* psrai.b */, RISCV::PSRAI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8955 { 17084 /* psrai.db */, RISCV::PSRAI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
8956 { 17093 /* psrai.dh */, RISCV::PSRAI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
8957 { 17102 /* psrai.dw */, RISCV::PSRAI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
8958 { 17111 /* psrai.h */, RISCV::PSRAI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8959 { 17119 /* psrai.w */, RISCV::PSRAI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8960 { 17127 /* psrari.dh */, RISCV::PSRARI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
8961 { 17137 /* psrari.dw */, RISCV::PSRARI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
8962 { 17147 /* psrari.h */, RISCV::PSRARI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8963 { 17156 /* psrari.w */, RISCV::PSRARI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8964 { 17165 /* psrl.bs */, RISCV::PSRL_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8965 { 17173 /* psrl.dbs */, RISCV::PSRL_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8966 { 17182 /* psrl.dhs */, RISCV::PSRL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8967 { 17191 /* psrl.dws */, RISCV::PSRL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8968 { 17200 /* psrl.hs */, RISCV::PSRL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8969 { 17208 /* psrl.ws */, RISCV::PSRL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8970 { 17216 /* psrli.b */, RISCV::PSRLI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8971 { 17224 /* psrli.db */, RISCV::PSRLI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
8972 { 17233 /* psrli.dh */, RISCV::PSRLI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
8973 { 17242 /* psrli.dw */, RISCV::PSRLI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
8974 { 17251 /* psrli.h */, RISCV::PSRLI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8975 { 17259 /* psrli.w */, RISCV::PSRLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8976 { 17267 /* pssa.dhx */, RISCV::PSSA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8977 { 17276 /* pssa.hx */, RISCV::PSSA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8978 { 17284 /* pssa.wx */, RISCV::PSSA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8979 { 17292 /* pssh1sadd.dh */, RISCV::PSSH1SADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8980 { 17305 /* pssh1sadd.dw */, RISCV::PSSH1SADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8981 { 17318 /* pssh1sadd.h */, RISCV::PSSH1SADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8982 { 17330 /* pssh1sadd.w */, RISCV::PSSH1SADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8983 { 17342 /* pssha.dhs */, RISCV::PSSHA_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8984 { 17352 /* pssha.dws */, RISCV::PSSHA_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8985 { 17362 /* pssha.hs */, RISCV::PSSHA_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8986 { 17371 /* pssha.ws */, RISCV::PSSHA_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8987 { 17380 /* psshar.dhs */, RISCV::PSSHAR_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8988 { 17391 /* psshar.dws */, RISCV::PSSHAR_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8989 { 17402 /* psshar.hs */, RISCV::PSSHAR_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8990 { 17412 /* psshar.ws */, RISCV::PSSHAR_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8991 { 17422 /* psslai.dh */, RISCV::PSSLAI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
8992 { 17432 /* psslai.dw */, RISCV::PSSLAI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
8993 { 17442 /* psslai.h */, RISCV::PSSLAI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8994 { 17451 /* psslai.w */, RISCV::PSSLAI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8995 { 17460 /* pssub.b */, RISCV::PSSUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8996 { 17468 /* pssub.db */, RISCV::PSSUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8997 { 17477 /* pssub.dh */, RISCV::PSSUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8998 { 17486 /* pssub.dw */, RISCV::PSSUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8999 { 17495 /* pssub.h */, RISCV::PSSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9000 { 17503 /* pssub.w */, RISCV::PSSUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9001 { 17511 /* pssubu.b */, RISCV::PSSUBU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9002 { 17520 /* pssubu.db */, RISCV::PSSUBU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9003 { 17530 /* pssubu.dh */, RISCV::PSSUBU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9004 { 17540 /* pssubu.dw */, RISCV::PSSUBU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9005 { 17550 /* pssubu.h */, RISCV::PSSUBU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9006 { 17559 /* pssubu.w */, RISCV::PSSUBU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9007 { 17568 /* psub.b */, RISCV::PSUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9008 { 17575 /* psub.db */, RISCV::PSUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9009 { 17583 /* psub.dh */, RISCV::PSUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9010 { 17591 /* psub.dw */, RISCV::PSUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9011 { 17599 /* psub.h */, RISCV::PSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9012 { 17606 /* psub.w */, RISCV::PSUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9013 { 17613 /* pusati.dh */, RISCV::PUSATI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9014 { 17623 /* pusati.dw */, RISCV::PUSATI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9015 { 17633 /* pusati.h */, RISCV::PUSATI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9016 { 17642 /* pusati.w */, RISCV::PUSATI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9017 { 17651 /* pwadd.b */, RISCV::PWADD_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9018 { 17659 /* pwadd.h */, RISCV::PWADD_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9019 { 17667 /* pwadda.b */, RISCV::PWADDA_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9020 { 17676 /* pwadda.h */, RISCV::PWADDA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9021 { 17685 /* pwaddau.b */, RISCV::PWADDAU_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9022 { 17695 /* pwaddau.h */, RISCV::PWADDAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9023 { 17705 /* pwaddu.b */, RISCV::PWADDU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9024 { 17714 /* pwaddu.h */, RISCV::PWADDU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9025 { 17723 /* pwmacc.h */, RISCV::PWMACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9026 { 17732 /* pwmaccsu.h */, RISCV::PWMACCSU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9027 { 17743 /* pwmaccu.h */, RISCV::PWMACCU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9028 { 17753 /* pwmul.b */, RISCV::PWMUL_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9029 { 17761 /* pwmul.h */, RISCV::PWMUL_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9030 { 17769 /* pwmulsu.b */, RISCV::PWMULSU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9031 { 17779 /* pwmulsu.h */, RISCV::PWMULSU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9032 { 17789 /* pwmulu.b */, RISCV::PWMULU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9033 { 17798 /* pwmulu.h */, RISCV::PWMULU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9034 { 17807 /* pwsla.bs */, RISCV::PWSLA_BS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9035 { 17816 /* pwsla.hs */, RISCV::PWSLA_HS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9036 { 17825 /* pwslai.b */, RISCV::PWSLAI_B, Convert__GPRPairRV321_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm4 }, },
9037 { 17834 /* pwslai.h */, RISCV::PWSLAI_H, Convert__GPRPairRV321_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm5 }, },
9038 { 17843 /* pwsll.bs */, RISCV::PWSLL_BS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9039 { 17852 /* pwsll.hs */, RISCV::PWSLL_HS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9040 { 17861 /* pwslli.b */, RISCV::PWSLLI_B, Convert__GPRPairRV321_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm4 }, },
9041 { 17870 /* pwslli.h */, RISCV::PWSLLI_H, Convert__GPRPairRV321_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm5 }, },
9042 { 17879 /* pwsub.b */, RISCV::PWSUB_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9043 { 17887 /* pwsub.h */, RISCV::PWSUB_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9044 { 17895 /* pwsuba.b */, RISCV::PWSUBA_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9045 { 17904 /* pwsuba.h */, RISCV::PWSUBA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9046 { 17913 /* pwsubau.b */, RISCV::PWSUBAU_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9047 { 17923 /* pwsubau.h */, RISCV::PWSUBAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9048 { 17933 /* pwsubu.b */, RISCV::PWSUBU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9049 { 17942 /* pwsubu.h */, RISCV::PWSUBU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9050 { 17951 /* qc.addsat */, RISCV::QC_ADDSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9051 { 17961 /* qc.addusat */, RISCV::QC_ADDUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9052 { 17972 /* qc.beqi */, RISCV::QC_BEQI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9053 { 17980 /* qc.bgei */, RISCV::QC_BGEI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9054 { 17988 /* qc.bgeui */, RISCV::QC_BGEUI, Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_BareSImm13Lsb0 }, },
9055 { 17997 /* qc.blti */, RISCV::QC_BLTI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9056 { 18005 /* qc.bltui */, RISCV::QC_BLTUI, Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_BareSImm13Lsb0 }, },
9057 { 18014 /* qc.bnei */, RISCV::QC_BNEI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9058 { 18022 /* qc.brev32 */, RISCV::QC_BREV32, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9059 { 18032 /* qc.c.bexti */, RISCV::QC_C_BEXTI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
9060 { 18043 /* qc.c.bseti */, RISCV::QC_C_BSETI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
9061 { 18054 /* qc.c.clrint */, RISCV::QC_C_CLRINT, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9062 { 18066 /* qc.c.delay */, RISCV::C_SLLI, Convert__regX0__Tie0_1_1__UImm5NonZero1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5NonZero }, },
9063 { 18077 /* qc.c.di */, RISCV::QC_C_DI, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9064 { 18085 /* qc.c.dir */, RISCV::QC_C_DIR, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9065 { 18094 /* qc.c.ei */, RISCV::QC_C_EI, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9066 { 18102 /* qc.c.eir */, RISCV::QC_C_EIR, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9067 { 18111 /* qc.c.extu */, RISCV::QC_C_EXTU, Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_UImm5GE6Plus1 }, },
9068 { 18121 /* qc.c.mienter */, RISCV::QC_C_MIENTER, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9069 { 18134 /* qc.c.mienter.nest */, RISCV::QC_C_MIENTER_NEST, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9070 { 18152 /* qc.c.mileaveret */, RISCV::QC_C_MILEAVERET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9071 { 18168 /* qc.c.mnret */, RISCV::QC_C_MNRET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9072 { 18179 /* qc.c.mret */, RISCV::QC_C_MRET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9073 { 18189 /* qc.c.muliadd */, RISCV::QC_C_MULIADD, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRC, MCK_GPRC, MCK_UImm5 }, },
9074 { 18202 /* qc.c.mveqz */, RISCV::QC_C_MVEQZ, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRC, MCK_GPRC }, },
9075 { 18213 /* qc.c.ptrace */, RISCV::C_SLLI, Convert__regX0__Tie0_1_1__imm_95_0, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9076 { 18225 /* qc.c.setint */, RISCV::QC_C_SETINT, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9077 { 18237 /* qc.c.sync */, RISCV::QC_C_SYNC, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9078 { 18247 /* qc.c.syncr */, RISCV::QC_C_SYNCR, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9079 { 18258 /* qc.c.syncwf */, RISCV::QC_C_SYNCWF, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9080 { 18270 /* qc.c.syncwl */, RISCV::QC_C_SYNCWL, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9081 { 18282 /* qc.clo */, RISCV::QC_CLO, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9082 { 18289 /* qc.clrinti */, RISCV::QC_CLRINTI, Convert__UImm101_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_UImm10 }, },
9083 { 18300 /* qc.cm.mva01s */, RISCV::QC_CM_MVA01S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqccmp, { MCK_SR07, MCK_SR07 }, },
9084 { 18313 /* qc.cm.mvsa01 */, RISCV::QC_CM_MVSA01, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqccmp, { MCK_SR07, MCK_SR07 }, },
9085 { 18326 /* qc.cm.pop */, RISCV::QC_CM_POP, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9086 { 18336 /* qc.cm.popret */, RISCV::QC_CM_POPRET, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9087 { 18349 /* qc.cm.popretz */, RISCV::QC_CM_POPRETZ, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9088 { 18363 /* qc.cm.push */, RISCV::QC_CM_PUSH, Convert__RegList1_0__NegStackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_NegStackAdj }, },
9089 { 18374 /* qc.cm.pushfp */, RISCV::QC_CM_PUSHFP, Convert__RegListS01_0__NegStackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegListS0, MCK_NegStackAdj }, },
9090 { 18387 /* qc.compress2 */, RISCV::QC_COMPRESS2, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9091 { 18400 /* qc.compress3 */, RISCV::QC_COMPRESS3, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9092 { 18413 /* qc.csrrwr */, RISCV::QC_CSRRWR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcicsr_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0 }, },
9093 { 18423 /* qc.csrrwri */, RISCV::QC_CSRRWRI, Convert__Reg1_0__UImm51_1__Reg1_2, AMFBS_HasVendorXqcicsr_IsRV32, { MCK_GPR, MCK_UImm5, MCK_GPRNoX0 }, },
9094 { 18434 /* qc.cto */, RISCV::QC_CTO, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9095 { 18441 /* qc.e.addai */, RISCV::QC_E_ADDAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9096 { 18452 /* qc.e.addi */, RISCV::QC_E_ADDI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9097 { 18462 /* qc.e.andai */, RISCV::QC_E_ANDAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9098 { 18473 /* qc.e.andi */, RISCV::QC_E_ANDI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9099 { 18483 /* qc.e.beqi */, RISCV::QC_E_BEQI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9100 { 18493 /* qc.e.bgei */, RISCV::QC_E_BGEI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9101 { 18503 /* qc.e.bgeui */, RISCV::QC_E_BGEUI, Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm16NonZero, MCK_BareSImm13Lsb0 }, },
9102 { 18514 /* qc.e.blti */, RISCV::QC_E_BLTI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9103 { 18524 /* qc.e.bltui */, RISCV::QC_E_BLTUI, Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm16NonZero, MCK_BareSImm13Lsb0 }, },
9104 { 18535 /* qc.e.bnei */, RISCV::QC_E_BNEI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9105 { 18545 /* qc.e.j */, RISCV::QC_E_J, Convert__BareSImm32Lsb01_0, AMFBS_HasVendorXqcilb_IsRV32, { MCK_BareSImm32Lsb0 }, },
9106 { 18552 /* qc.e.jal */, RISCV::QC_E_JAL, Convert__BareSImm32Lsb01_0, AMFBS_HasVendorXqcilb_IsRV32, { MCK_BareSImm32Lsb0 }, },
9107 { 18561 /* qc.e.lb */, RISCV::PseudoQC_E_LB, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9108 { 18561 /* qc.e.lb */, RISCV::QC_E_LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9109 { 18561 /* qc.e.lb */, RISCV::QC_E_LB, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9110 { 18569 /* qc.e.lbu */, RISCV::PseudoQC_E_LBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9111 { 18569 /* qc.e.lbu */, RISCV::QC_E_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9112 { 18569 /* qc.e.lbu */, RISCV::QC_E_LBU, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9113 { 18578 /* qc.e.lh */, RISCV::PseudoQC_E_LH, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9114 { 18578 /* qc.e.lh */, RISCV::QC_E_LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9115 { 18578 /* qc.e.lh */, RISCV::QC_E_LH, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9116 { 18586 /* qc.e.lhu */, RISCV::PseudoQC_E_LHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9117 { 18586 /* qc.e.lhu */, RISCV::QC_E_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9118 { 18586 /* qc.e.lhu */, RISCV::QC_E_LHU, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9119 { 18595 /* qc.e.li */, RISCV::QC_E_LI, Convert__Reg1_0__BareSImm321_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9120 { 18595 /* qc.e.li */, RISCV::ADDI, Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbolQC_E_LI }, },
9121 { 18603 /* qc.e.lw */, RISCV::PseudoQC_E_LW, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9122 { 18603 /* qc.e.lw */, RISCV::QC_E_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9123 { 18603 /* qc.e.lw */, RISCV::QC_E_LW, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9124 { 18611 /* qc.e.orai */, RISCV::QC_E_ORAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9125 { 18621 /* qc.e.ori */, RISCV::QC_E_ORI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9126 { 18630 /* qc.e.sb */, RISCV::PseudoQC_E_SB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9127 { 18630 /* qc.e.sb */, RISCV::QC_E_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9128 { 18630 /* qc.e.sb */, RISCV::QC_E_SB, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9129 { 18638 /* qc.e.sh */, RISCV::PseudoQC_E_SH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9130 { 18638 /* qc.e.sh */, RISCV::QC_E_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9131 { 18638 /* qc.e.sh */, RISCV::QC_E_SH, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9132 { 18646 /* qc.e.sw */, RISCV::PseudoQC_E_SW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9133 { 18646 /* qc.e.sw */, RISCV::QC_E_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9134 { 18646 /* qc.e.sw */, RISCV::QC_E_SW, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9135 { 18654 /* qc.e.xorai */, RISCV::QC_E_XORAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9136 { 18665 /* qc.e.xori */, RISCV::QC_E_XORI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9137 { 18675 /* qc.expand2 */, RISCV::QC_EXPAND2, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9138 { 18686 /* qc.expand3 */, RISCV::QC_EXPAND3, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9139 { 18697 /* qc.ext */, RISCV::QC_EXT, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5Plus1, MCK_UImm5 }, },
9140 { 18704 /* qc.extd */, RISCV::QC_EXTD, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_UImm5Plus1, MCK_UImm5 }, },
9141 { 18712 /* qc.extdpr */, RISCV::QC_EXTDPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9142 { 18722 /* qc.extdprh */, RISCV::QC_EXTDPRH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9143 { 18733 /* qc.extdr */, RISCV::QC_EXTDR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9144 { 18742 /* qc.extdu */, RISCV::QC_EXTDU, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_UImm5Plus1, MCK_UImm5 }, },
9145 { 18751 /* qc.extdupr */, RISCV::QC_EXTDUPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9146 { 18762 /* qc.extduprh */, RISCV::QC_EXTDUPRH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9147 { 18774 /* qc.extdur */, RISCV::QC_EXTDUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9148 { 18784 /* qc.extu */, RISCV::QC_EXTU, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5Plus1, MCK_UImm5 }, },
9149 { 18792 /* qc.insb */, RISCV::QC_INSB, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_UImm5Plus1, MCK_UImm5 }, },
9150 { 18800 /* qc.insbh */, RISCV::QC_INSBH, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_UImm5Plus1, MCK_UImm5 }, },
9151 { 18809 /* qc.insbhr */, RISCV::QC_INSBHR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9152 { 18819 /* qc.insbi */, RISCV::QC_INSBI, Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_UImm5Plus1, MCK_UImm5 }, },
9153 { 18828 /* qc.insbpr */, RISCV::QC_INSBPR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9154 { 18838 /* qc.insbprh */, RISCV::QC_INSBPRH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9155 { 18849 /* qc.insbr */, RISCV::QC_INSBR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9156 { 18858 /* qc.insbri */, RISCV::QC_INSBRI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm11 }, },
9157 { 18868 /* qc.inw */, RISCV::QC_INW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9158 { 18868 /* qc.inw */, RISCV::QC_INW, Convert__Reg1_0__Reg1_3__UImm14Lsb001_1, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPRNoX0, MCK_UImm14Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9159 { 18875 /* qc.li */, RISCV::QC_LI, Convert__Reg1_0__SImm20LI1_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_SImm20LI }, },
9160 { 18881 /* qc.lieq */, RISCV::QC_LIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9161 { 18889 /* qc.lieqi */, RISCV::QC_LIEQI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9162 { 18898 /* qc.lige */, RISCV::QC_LIGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9163 { 18906 /* qc.ligei */, RISCV::QC_LIGEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9164 { 18915 /* qc.ligeu */, RISCV::QC_LIGEU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9165 { 18924 /* qc.ligeui */, RISCV::QC_LIGEUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_SImm5 }, },
9166 { 18934 /* qc.lilt */, RISCV::QC_LILT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9167 { 18942 /* qc.lilti */, RISCV::QC_LILTI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9168 { 18951 /* qc.liltu */, RISCV::QC_LILTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9169 { 18960 /* qc.liltui */, RISCV::QC_LILTUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_SImm5 }, },
9170 { 18970 /* qc.line */, RISCV::QC_LINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9171 { 18978 /* qc.linei */, RISCV::QC_LINEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9172 { 18987 /* qc.lrb */, RISCV::QC_LRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9173 { 18994 /* qc.lrbu */, RISCV::QC_LRBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9174 { 19002 /* qc.lrh */, RISCV::QC_LRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9175 { 19009 /* qc.lrhu */, RISCV::QC_LRHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9176 { 19017 /* qc.lrw */, RISCV::QC_LRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9177 { 19024 /* qc.lwm */, RISCV::QC_LWM, Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9178 { 19024 /* qc.lwm */, RISCV::QC_LWM, Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9179 { 19031 /* qc.lwmi */, RISCV::QC_LWMI, Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK__40_, MCK_GPR, MCK__41_ }, },
9180 { 19031 /* qc.lwmi */, RISCV::QC_LWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9181 { 19039 /* qc.muliadd */, RISCV::QC_MULIADD, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm12LO }, },
9182 { 19050 /* qc.mveq */, RISCV::QC_MVEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9183 { 19058 /* qc.mveqi */, RISCV::QC_MVEQI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9184 { 19067 /* qc.mvge */, RISCV::QC_MVGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9185 { 19075 /* qc.mvgei */, RISCV::QC_MVGEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9186 { 19084 /* qc.mvgeu */, RISCV::QC_MVGEU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9187 { 19093 /* qc.mvgeui */, RISCV::QC_MVGEUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_GPRNoX0 }, },
9188 { 19103 /* qc.mvlt */, RISCV::QC_MVLT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9189 { 19111 /* qc.mvlti */, RISCV::QC_MVLTI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9190 { 19120 /* qc.mvltu */, RISCV::QC_MVLTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9191 { 19129 /* qc.mvltui */, RISCV::QC_MVLTUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_GPRNoX0 }, },
9192 { 19139 /* qc.mvne */, RISCV::QC_MVNE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9193 { 19147 /* qc.mvnei */, RISCV::QC_MVNEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9194 { 19156 /* qc.norm */, RISCV::QC_NORM, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9195 { 19164 /* qc.normeu */, RISCV::QC_NORMEU, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9196 { 19174 /* qc.normu */, RISCV::QC_NORMU, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9197 { 19183 /* qc.outw */, RISCV::QC_OUTW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9198 { 19183 /* qc.outw */, RISCV::QC_OUTW, Convert__Reg1_0__Reg1_3__UImm14Lsb001_1, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPR, MCK_UImm14Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9199 { 19191 /* qc.pcoredump */, RISCV::SLTI, Convert__regX0__regX0__imm_95_1536, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9200 { 19204 /* qc.pexit */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1280, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9201 { 19213 /* qc.ppreg */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_2048, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9202 { 19222 /* qc.ppregs */, RISCV::SLTI, Convert__regX0__regX0__imm_95_1792, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9203 { 19232 /* qc.pputc */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1792, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9204 { 19241 /* qc.pputci */, RISCV::QC_PPUTCI, Convert__UImm81_0, AMFBS_HasVendorXqcisim_IsRV32, { MCK_UImm8 }, },
9205 { 19251 /* qc.pputs */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1536, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9206 { 19260 /* qc.psyscall */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1024, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9207 { 19272 /* qc.psyscalli */, RISCV::SLTI, Convert__regX0__regX0__UImm101_0, AMFBS_HasVendorXqcisim_IsRV32, { MCK_UImm10 }, },
9208 { 19285 /* qc.selecteqi */, RISCV::QC_SELECTEQI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9209 { 19298 /* qc.selectieq */, RISCV::QC_SELECTIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9210 { 19311 /* qc.selectieqi */, RISCV::QC_SELECTIEQI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_SImm5 }, },
9211 { 19325 /* qc.selectiieq */, RISCV::QC_SELECTIIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9212 { 19339 /* qc.selectiine */, RISCV::QC_SELECTIINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9213 { 19353 /* qc.selectine */, RISCV::QC_SELECTINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9214 { 19366 /* qc.selectinei */, RISCV::QC_SELECTINEI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_SImm5 }, },
9215 { 19380 /* qc.selectnei */, RISCV::QC_SELECTNEI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9216 { 19393 /* qc.setinti */, RISCV::QC_SETINTI, Convert__UImm101_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_UImm10 }, },
9217 { 19404 /* qc.setwm */, RISCV::QC_SETWM, Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9218 { 19404 /* qc.setwm */, RISCV::QC_SETWM, Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_GPRNoX0, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9219 { 19413 /* qc.setwmi */, RISCV::QC_SETWMI, Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_UImm5NonZero, MCK__40_, MCK_GPR, MCK__41_ }, },
9220 { 19413 /* qc.setwmi */, RISCV::QC_SETWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_UImm5NonZero, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9221 { 19423 /* qc.shladd */, RISCV::QC_SHLADD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5GT3 }, },
9222 { 19433 /* qc.shlsat */, RISCV::QC_SHLSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9223 { 19443 /* qc.shlusat */, RISCV::QC_SHLUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9224 { 19454 /* qc.srb */, RISCV::QC_SRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9225 { 19461 /* qc.srh */, RISCV::QC_SRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9226 { 19468 /* qc.srw */, RISCV::QC_SRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9227 { 19475 /* qc.subsat */, RISCV::QC_SUBSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9228 { 19485 /* qc.subusat */, RISCV::QC_SUBUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9229 { 19496 /* qc.swm */, RISCV::QC_SWM, Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9230 { 19496 /* qc.swm */, RISCV::QC_SWM, Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9231 { 19503 /* qc.swmi */, RISCV::QC_SWMI, Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK__40_, MCK_GPR, MCK__41_ }, },
9232 { 19503 /* qc.swmi */, RISCV::QC_SWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9233 { 19511 /* qc.sync */, RISCV::QC_SYNC, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9234 { 19519 /* qc.syncr */, RISCV::QC_SYNCR, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9235 { 19528 /* qc.syncwf */, RISCV::QC_SYNCWF, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9236 { 19538 /* qc.syncwl */, RISCV::QC_SYNCWL, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9237 { 19548 /* qc.wrap */, RISCV::QC_WRAP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9238 { 19556 /* qc.wrapi */, RISCV::QC_WRAPI, Convert__Reg1_0__Reg1_1__UImm111_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm11 }, },
9239 { 19565 /* qk.c.lbu */, RISCV::QK_C_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9240 { 19565 /* qk.c.lbu */, RISCV::QK_C_LBU, Convert__Reg1_0__Reg1_3__UImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
9241 { 19574 /* qk.c.lbusp */, RISCV::QK_C_LBUSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9242 { 19574 /* qk.c.lbusp */, RISCV::QK_C_LBUSP, Convert__Reg1_0__Reg1_3__UImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm4, MCK__40_, MCK_SP, MCK__41_ }, },
9243 { 19585 /* qk.c.lhu */, RISCV::QK_C_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9244 { 19585 /* qk.c.lhu */, RISCV::QK_C_LHU, Convert__Reg1_0__Reg1_3__UImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
9245 { 19594 /* qk.c.lhusp */, RISCV::QK_C_LHUSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9246 { 19594 /* qk.c.lhusp */, RISCV::QK_C_LHUSP, Convert__Reg1_0__Reg1_3__UImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
9247 { 19605 /* qk.c.sb */, RISCV::QK_C_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9248 { 19605 /* qk.c.sb */, RISCV::QK_C_SB, Convert__Reg1_0__Reg1_3__UImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
9249 { 19613 /* qk.c.sbsp */, RISCV::QK_C_SBSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9250 { 19613 /* qk.c.sbsp */, RISCV::QK_C_SBSP, Convert__Reg1_0__Reg1_3__UImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm4, MCK__40_, MCK_SP, MCK__41_ }, },
9251 { 19623 /* qk.c.sh */, RISCV::QK_C_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9252 { 19623 /* qk.c.sh */, RISCV::QK_C_SH, Convert__Reg1_0__Reg1_3__UImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
9253 { 19631 /* qk.c.shsp */, RISCV::QK_C_SHSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9254 { 19631 /* qk.c.shsp */, RISCV::QK_C_SHSP, Convert__Reg1_0__Reg1_3__UImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
9255 { 19641 /* rdcycle */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3072__regX0, AMFBS_None, { MCK_GPR }, },
9256 { 19649 /* rdcycleh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3200__regX0, AMFBS_IsRV32, { MCK_GPR }, },
9257 { 19658 /* rdinstret */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3074__regX0, AMFBS_None, { MCK_GPR }, },
9258 { 19668 /* rdinstreth */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3202__regX0, AMFBS_IsRV32, { MCK_GPR }, },
9259 { 19679 /* rdtime */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3073__regX0, AMFBS_None, { MCK_GPR }, },
9260 { 19686 /* rdtimeh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3201__regX0, AMFBS_IsRV32, { MCK_GPR }, },
9261 { 19694 /* rem */, RISCV::REM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9262 { 19698 /* remu */, RISCV::REMU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9263 { 19703 /* remuw */, RISCV::REMUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9264 { 19709 /* remw */, RISCV::REMW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9265 { 19714 /* ret */, RISCV::JALR, Convert__regX0__regX1__imm_95_0, AMFBS_None, { }, },
9266 { 19718 /* rev */, RISCV::REV_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
9267 { 19718 /* rev */, RISCV::REV_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9268 { 19722 /* rev16 */, RISCV::REV16, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9269 { 19728 /* rev8 */, RISCV::REV8_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
9270 { 19728 /* rev8 */, RISCV::REV8_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR }, },
9271 { 19733 /* ri.vextract.x.v */, RISCV::RI_VEXTRACT, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXRivosVisni, { MCK_GPR, MCK_VR, MCK_UImm5 }, },
9272 { 19749 /* ri.vinsert.v.x */, RISCV::RI_VINSERT, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasVendorXRivosVisni, { MCK_VR, MCK_GPR, MCK_UImm5 }, },
9273 { 19764 /* ri.vunzip2a.vv */, RISCV::RI_VUNZIP2A_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXRivosVizip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9274 { 19779 /* ri.vunzip2b.vv */, RISCV::RI_VUNZIP2B_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXRivosVizip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9275 { 19794 /* ri.vzero.v */, RISCV::RI_VZERO, Convert__Reg1_0, AMFBS_HasVendorXRivosVisni, { MCK_VR }, },
9276 { 19805 /* ri.vzip2a.vv */, RISCV::RI_VZIP2A_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXRivosVizip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9277 { 19818 /* ri.vzip2b.vv */, RISCV::RI_VZIP2B_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXRivosVizip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9278 { 19831 /* ri.vzipeven.vv */, RISCV::RI_VZIPEVEN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXRivosVizip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9279 { 19846 /* ri.vzipodd.vv */, RISCV::RI_VZIPODD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXRivosVizip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9280 { 19860 /* rol */, RISCV::ROL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9281 { 19864 /* rolw */, RISCV::ROLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9282 { 19869 /* ror */, RISCV::ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9283 { 19869 /* ror */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9284 { 19873 /* rori */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9285 { 19878 /* roriw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9286 { 19884 /* rorw */, RISCV::RORW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9287 { 19884 /* rorw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9288 { 19889 /* sadd */, RISCV::SADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9289 { 19894 /* saddu */, RISCV::SADDU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9290 { 19900 /* sati */, RISCV::SATI_RV32, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9291 { 19900 /* sati */, RISCV::SATI_RV64, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
9292 { 19905 /* sb */, RISCV::PseudoSB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9293 { 19905 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9294 { 19905 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9295 { 19908 /* sb.aqrl */, RISCV::SB_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9296 { 19916 /* sb.rl */, RISCV::SB_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9297 { 19922 /* sc.d */, RISCV::SC_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9298 { 19927 /* sc.d.aq */, RISCV::SC_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9299 { 19935 /* sc.d.aqrl */, RISCV::SC_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9300 { 19945 /* sc.d.rl */, RISCV::SC_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9301 { 19953 /* sc.w */, RISCV::SC_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9302 { 19958 /* sc.w.aq */, RISCV::SC_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9303 { 19966 /* sc.w.aqrl */, RISCV::SC_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9304 { 19976 /* sc.w.rl */, RISCV::SC_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9305 { 19984 /* sctrclr */, RISCV::SCTRCLR, Convert_NoOperands, AMFBS_HasStdExtSmctrOrSsctr, { }, },
9306 { 19992 /* sd */, RISCV::PseudoSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9307 { 19992 /* sd */, RISCV::PseudoSD_RV32, Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_BareSymbol, MCK_GPR }, },
9308 { 19992 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9309 { 19992 /* sd */, RISCV::SD_RV32, Convert__GPRPairRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK__40_, MCK_GPR, MCK__41_ }, },
9310 { 19992 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9311 { 19992 /* sd */, RISCV::SD_RV32, Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9312 { 19995 /* sd.aqrl */, RISCV::SD_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9313 { 20003 /* sd.rl */, RISCV::SD_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9314 { 20009 /* seqz */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__imm_95_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9315 { 20014 /* sext.b */, RISCV::SEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
9316 { 20014 /* sext.b */, RISCV::PseudoSEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9317 { 20021 /* sext.h */, RISCV::SEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
9318 { 20021 /* sext.h */, RISCV::PseudoSEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9319 { 20028 /* sext.w */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
9320 { 20035 /* sf.cdiscard.d.l1 */, RISCV::SF_CDISCARD_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecdiscarddlone, { }, },
9321 { 20035 /* sf.cdiscard.d.l1 */, RISCV::SF_CDISCARD_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecdiscarddlone, { MCK_GPR }, },
9322 { 20052 /* sf.cease */, RISCV::SF_CEASE, Convert_NoOperands, AMFBS_HasVendorXSfcease, { }, },
9323 { 20061 /* sf.cflush.d.l1 */, RISCV::SF_CFLUSH_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecflushdlone, { }, },
9324 { 20061 /* sf.cflush.d.l1 */, RISCV::SF_CFLUSH_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecflushdlone, { MCK_GPR }, },
9325 { 20076 /* sf.mm.e4m3.e4m3 */, RISCV::SF_MM_E4M3_E4M3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9326 { 20092 /* sf.mm.e4m3.e5m2 */, RISCV::SF_MM_E4M3_E5M2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9327 { 20108 /* sf.mm.e5m2.e4m3 */, RISCV::SF_MM_E5M2_E4M3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9328 { 20124 /* sf.mm.e5m2.e5m2 */, RISCV::SF_MM_E5M2_E5M2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9329 { 20140 /* sf.mm.f.f */, RISCV::SF_MM_F_F, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f, { MCK_TRM2, MCK_VR, MCK_VR }, },
9330 { 20150 /* sf.mm.s.s */, RISCV::SF_MM_S_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9331 { 20160 /* sf.mm.s.u */, RISCV::SF_MM_S_U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9332 { 20170 /* sf.mm.u.s */, RISCV::SF_MM_U_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9333 { 20180 /* sf.mm.u.u */, RISCV::SF_MM_U_U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9334 { 20190 /* sf.vc.fv */, RISCV::SF_VC_FV, Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_UImm5, MCK_VR, MCK_FPR32 }, },
9335 { 20199 /* sf.vc.fvv */, RISCV::SF_VC_FVV, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9336 { 20209 /* sf.vc.fvw */, RISCV::SF_VC_FVW, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9337 { 20219 /* sf.vc.i */, RISCV::SF_VC_I, Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_SImm5 }, },
9338 { 20227 /* sf.vc.iv */, RISCV::SF_VC_IV, Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_SImm5 }, },
9339 { 20236 /* sf.vc.ivv */, RISCV::SF_VC_IVV, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9340 { 20246 /* sf.vc.ivw */, RISCV::SF_VC_IVW, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9341 { 20256 /* sf.vc.v.fv */, RISCV::SF_VC_V_FV, Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9342 { 20267 /* sf.vc.v.fvv */, RISCV::SF_VC_V_FVV, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9343 { 20279 /* sf.vc.v.fvw */, RISCV::SF_VC_V_FVW, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9344 { 20291 /* sf.vc.v.i */, RISCV::SF_VC_V_I, Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_SImm5 }, },
9345 { 20301 /* sf.vc.v.iv */, RISCV::SF_VC_V_IV, Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9346 { 20312 /* sf.vc.v.ivv */, RISCV::SF_VC_V_IVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9347 { 20324 /* sf.vc.v.ivw */, RISCV::SF_VC_V_IVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9348 { 20336 /* sf.vc.v.vv */, RISCV::SF_VC_V_VV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9349 { 20347 /* sf.vc.v.vvv */, RISCV::SF_VC_V_VVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9350 { 20359 /* sf.vc.v.vvw */, RISCV::SF_VC_V_VVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9351 { 20371 /* sf.vc.v.x */, RISCV::SF_VC_V_X, Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_GPR }, },
9352 { 20381 /* sf.vc.v.xv */, RISCV::SF_VC_V_XV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9353 { 20392 /* sf.vc.v.xvv */, RISCV::SF_VC_V_XVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9354 { 20404 /* sf.vc.v.xvw */, RISCV::SF_VC_V_XVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9355 { 20416 /* sf.vc.vv */, RISCV::SF_VC_VV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_VR }, },
9356 { 20425 /* sf.vc.vvv */, RISCV::SF_VC_VVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9357 { 20435 /* sf.vc.vvw */, RISCV::SF_VC_VVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9358 { 20445 /* sf.vc.x */, RISCV::SF_VC_X, Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_GPR }, },
9359 { 20453 /* sf.vc.xv */, RISCV::SF_VC_XV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_GPR }, },
9360 { 20462 /* sf.vc.xvv */, RISCV::SF_VC_XVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9361 { 20472 /* sf.vc.xvw */, RISCV::SF_VC_XVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9362 { 20482 /* sf.vfexp.v */, RISCV::SF_VFEXP_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXSfvfexpAny, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9363 { 20493 /* sf.vfexpa.v */, RISCV::SF_VFEXPA_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXSfvfexpa, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9364 { 20505 /* sf.vfnrclip.x.f.qf */, RISCV::SF_VFNRCLIP_X_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9365 { 20524 /* sf.vfnrclip.xu.f.qf */, RISCV::SF_VFNRCLIP_XU_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9366 { 20544 /* sf.vfwmacc.4x4x4 */, RISCV::SF_VFWMACC_4x4x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvfwmaccqqq, { MCK_VR, MCK_VR, MCK_VR }, },
9367 { 20561 /* sf.vlte16 */, RISCV::SF_VLTE16, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9368 { 20571 /* sf.vlte32 */, RISCV::SF_VLTE32, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9369 { 20581 /* sf.vlte64 */, RISCV::SF_VLTE64, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9370 { 20591 /* sf.vlte8 */, RISCV::SF_VLTE8, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9371 { 20600 /* sf.vqmacc.2x8x2 */, RISCV::SF_VQMACC_2x8x2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9372 { 20616 /* sf.vqmacc.4x8x4 */, RISCV::SF_VQMACC_4x8x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9373 { 20632 /* sf.vqmaccsu.2x8x2 */, RISCV::SF_VQMACCSU_2x8x2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9374 { 20650 /* sf.vqmaccsu.4x8x4 */, RISCV::SF_VQMACCSU_4x8x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9375 { 20668 /* sf.vqmaccu.2x8x2 */, RISCV::SF_VQMACCU_2x8x2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9376 { 20685 /* sf.vqmaccu.4x8x4 */, RISCV::SF_VQMACCU_4x8x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9377 { 20702 /* sf.vqmaccus.2x8x2 */, RISCV::SF_VQMACCUS_2x8x2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9378 { 20720 /* sf.vqmaccus.4x8x4 */, RISCV::SF_VQMACCUS_4x8x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9379 { 20738 /* sf.vsettk */, RISCV::SF_VSETTK, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
9380 { 20748 /* sf.vsettm */, RISCV::SF_VSETTM, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
9381 { 20758 /* sf.vsettn */, RISCV::SF_VSETTN, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
9382 { 20768 /* sf.vsettnt */, RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__XSfmmVType1_2, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR, MCK_XSfmmVType }, },
9383 { 20779 /* sf.vste16 */, RISCV::SF_VSTE16, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9384 { 20789 /* sf.vste32 */, RISCV::SF_VSTE32, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9385 { 20799 /* sf.vste64 */, RISCV::SF_VSTE64, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9386 { 20809 /* sf.vste8 */, RISCV::SF_VSTE8, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9387 { 20818 /* sf.vtdiscard */, RISCV::SF_VTDISCARD, Convert_NoOperands, AMFBS_HasVendorXSfmmbase, { }, },
9388 { 20831 /* sf.vtmv.t.v */, RISCV::SF_VTMV_T_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_VR }, },
9389 { 20843 /* sf.vtmv.v.t */, RISCV::SF_VTMV_V_T, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_VR, MCK_GPR }, },
9390 { 20855 /* sf.vtzero.t */, RISCV::SF_VTZERO_T, Convert__Reg1_0, AMFBS_HasVendorXSfmmbase, { MCK_TR }, },
9391 { 20867 /* sfence.inval.ir */, RISCV::SFENCE_INVAL_IR, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
9392 { 20883 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__regX0__regX0, AMFBS_None, { }, },
9393 { 20883 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
9394 { 20883 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9395 { 20894 /* sfence.w.inval */, RISCV::SFENCE_W_INVAL, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
9396 { 20909 /* sgt */, RISCV::SLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9397 { 20913 /* sgtu */, RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9398 { 20918 /* sgtz */, RISCV::SLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9399 { 20923 /* sh */, RISCV::PseudoSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9400 { 20923 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9401 { 20923 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9402 { 20926 /* sh.aqrl */, RISCV::SH_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9403 { 20934 /* sh.rl */, RISCV::SH_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9404 { 20940 /* sh1add */, RISCV::SH1ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9405 { 20947 /* sh1add.uw */, RISCV::SH1ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9406 { 20957 /* sh2add */, RISCV::SH2ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9407 { 20964 /* sh2add.uw */, RISCV::SH2ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9408 { 20974 /* sh3add */, RISCV::SH3ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9409 { 20981 /* sh3add.uw */, RISCV::SH3ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9410 { 20991 /* sha */, RISCV::SHA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9411 { 20995 /* sha256sig0 */, RISCV::SHA256SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9412 { 21006 /* sha256sig1 */, RISCV::SHA256SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9413 { 21017 /* sha256sum0 */, RISCV::SHA256SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9414 { 21028 /* sha256sum1 */, RISCV::SHA256SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9415 { 21039 /* sha512sig0 */, RISCV::SHA512SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9416 { 21050 /* sha512sig0h */, RISCV::SHA512SIG0H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9417 { 21062 /* sha512sig0l */, RISCV::SHA512SIG0L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9418 { 21074 /* sha512sig1 */, RISCV::SHA512SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9419 { 21085 /* sha512sig1h */, RISCV::SHA512SIG1H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9420 { 21097 /* sha512sig1l */, RISCV::SHA512SIG1L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9421 { 21109 /* sha512sum0 */, RISCV::SHA512SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9422 { 21120 /* sha512sum0r */, RISCV::SHA512SUM0R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9423 { 21132 /* sha512sum1 */, RISCV::SHA512SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9424 { 21143 /* sha512sum1r */, RISCV::SHA512SUM1R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9425 { 21155 /* shar */, RISCV::SHAR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9426 { 21160 /* sinval.vma */, RISCV::SINVAL_VMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
9427 { 21171 /* sll */, RISCV::SLL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9428 { 21171 /* sll */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9429 { 21175 /* slli */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9430 { 21180 /* slli.uw */, RISCV::SLLI_UW, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9431 { 21188 /* slliw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9432 { 21194 /* sllw */, RISCV::SLLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9433 { 21194 /* sllw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9434 { 21199 /* slt */, RISCV::SLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9435 { 21199 /* slt */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9436 { 21203 /* slti */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9437 { 21208 /* sltiu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9438 { 21214 /* sltu */, RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9439 { 21214 /* sltu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9440 { 21219 /* sltz */, RISCV::SLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9441 { 21224 /* slx */, RISCV::SLX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9442 { 21228 /* sm3p0 */, RISCV::SM3P0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
9443 { 21234 /* sm3p1 */, RISCV::SM3P1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
9444 { 21240 /* sm4ed */, RISCV::SM4ED, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9445 { 21246 /* sm4ks */, RISCV::SM4KS, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9446 { 21252 /* smt.vmadot */, RISCV::SMT_VMADOT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VR, MCK_VR }, },
9447 { 21263 /* smt.vmadot1 */, RISCV::SMT_VMADOT1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9448 { 21275 /* smt.vmadot1su */, RISCV::SMT_VMADOT1SU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9449 { 21289 /* smt.vmadot1u */, RISCV::SMT_VMADOT1U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9450 { 21302 /* smt.vmadot1us */, RISCV::SMT_VMADOT1US, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9451 { 21316 /* smt.vmadot2 */, RISCV::SMT_VMADOT2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9452 { 21328 /* smt.vmadot2su */, RISCV::SMT_VMADOT2SU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9453 { 21342 /* smt.vmadot2u */, RISCV::SMT_VMADOT2U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9454 { 21355 /* smt.vmadot2us */, RISCV::SMT_VMADOT2US, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9455 { 21369 /* smt.vmadot3 */, RISCV::SMT_VMADOT3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9456 { 21381 /* smt.vmadot3su */, RISCV::SMT_VMADOT3SU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9457 { 21395 /* smt.vmadot3u */, RISCV::SMT_VMADOT3U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9458 { 21408 /* smt.vmadot3us */, RISCV::SMT_VMADOT3US, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9459 { 21422 /* smt.vmadotsu */, RISCV::SMT_VMADOTSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VR, MCK_VR }, },
9460 { 21435 /* smt.vmadotu */, RISCV::SMT_VMADOTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VR, MCK_VR }, },
9461 { 21447 /* smt.vmadotus */, RISCV::SMT_VMADOTUS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot, { MCK_VRM2, MCK_VR, MCK_VR }, },
9462 { 21460 /* snez */, RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9463 { 21465 /* sra */, RISCV::SRA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9464 { 21465 /* sra */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9465 { 21469 /* srai */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9466 { 21474 /* sraiw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9467 { 21480 /* srari */, RISCV::SRARI_RV32, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9468 { 21480 /* srari */, RISCV::SRARI_RV64, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
9469 { 21486 /* sraw */, RISCV::SRAW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9470 { 21486 /* sraw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9471 { 21491 /* sret */, RISCV::SRET, Convert_NoOperands, AMFBS_None, { }, },
9472 { 21496 /* srl */, RISCV::SRL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9473 { 21496 /* srl */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9474 { 21500 /* srli */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9475 { 21505 /* srliw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9476 { 21511 /* srlw */, RISCV::SRLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9477 { 21511 /* srlw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9478 { 21516 /* srx */, RISCV::SRX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9479 { 21520 /* ssamoswap.d */, RISCV::SSAMOSWAP_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9480 { 21532 /* ssamoswap.d.aq */, RISCV::SSAMOSWAP_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9481 { 21547 /* ssamoswap.d.aqrl */, RISCV::SSAMOSWAP_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9482 { 21564 /* ssamoswap.d.rl */, RISCV::SSAMOSWAP_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9483 { 21579 /* ssamoswap.w */, RISCV::SSAMOSWAP_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9484 { 21591 /* ssamoswap.w.aq */, RISCV::SSAMOSWAP_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9485 { 21606 /* ssamoswap.w.aqrl */, RISCV::SSAMOSWAP_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9486 { 21623 /* ssamoswap.w.rl */, RISCV::SSAMOSWAP_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9487 { 21638 /* ssh1sadd */, RISCV::SSH1SADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9488 { 21647 /* ssha */, RISCV::SSHA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9489 { 21652 /* sshar */, RISCV::SSHAR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9490 { 21658 /* sslai */, RISCV::SSLAI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9491 { 21664 /* sspopchk */, RISCV::SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRX1X5 }, },
9492 { 21673 /* sspush */, RISCV::SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRX1X5 }, },
9493 { 21680 /* ssrdp */, RISCV::SSRDP, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRNoX0 }, },
9494 { 21686 /* ssub */, RISCV::SSUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9495 { 21691 /* ssubu */, RISCV::SSUBU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9496 { 21697 /* sub */, RISCV::SUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9497 { 21701 /* subd */, RISCV::SUBD, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9498 { 21706 /* subw */, RISCV::SUBW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9499 { 21711 /* sw */, RISCV::PseudoSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9500 { 21711 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9501 { 21711 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9502 { 21714 /* sw.aqrl */, RISCV::SW_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9503 { 21722 /* sw.rl */, RISCV::SW_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9504 { 21728 /* tail */, RISCV::PseudoTAIL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
9505 { 21733 /* th.addsl */, RISCV::TH_ADDSL, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadBa, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9506 { 21742 /* th.dcache.call */, RISCV::TH_DCACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9507 { 21757 /* th.dcache.ciall */, RISCV::TH_DCACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9508 { 21773 /* th.dcache.cipa */, RISCV::TH_DCACHE_CIPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9509 { 21788 /* th.dcache.cisw */, RISCV::TH_DCACHE_CISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9510 { 21803 /* th.dcache.civa */, RISCV::TH_DCACHE_CIVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9511 { 21818 /* th.dcache.cpa */, RISCV::TH_DCACHE_CPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9512 { 21832 /* th.dcache.cpal1 */, RISCV::TH_DCACHE_CPAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9513 { 21848 /* th.dcache.csw */, RISCV::TH_DCACHE_CSW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9514 { 21862 /* th.dcache.cva */, RISCV::TH_DCACHE_CVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9515 { 21876 /* th.dcache.cval1 */, RISCV::TH_DCACHE_CVAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9516 { 21892 /* th.dcache.iall */, RISCV::TH_DCACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9517 { 21907 /* th.dcache.ipa */, RISCV::TH_DCACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9518 { 21921 /* th.dcache.isw */, RISCV::TH_DCACHE_ISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9519 { 21935 /* th.dcache.iva */, RISCV::TH_DCACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9520 { 21949 /* th.ext */, RISCV::TH_EXT, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
9521 { 21956 /* th.extu */, RISCV::TH_EXTU, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
9522 { 21964 /* th.ff0 */, RISCV::TH_FF0, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
9523 { 21971 /* th.ff1 */, RISCV::TH_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
9524 { 21978 /* th.flrd */, RISCV::TH_FLRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9525 { 21986 /* th.flrw */, RISCV::TH_FLRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9526 { 21994 /* th.flurd */, RISCV::TH_FLURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9527 { 22003 /* th.flurw */, RISCV::TH_FLURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9528 { 22012 /* th.fsrd */, RISCV::TH_FSRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9529 { 22020 /* th.fsrw */, RISCV::TH_FSRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9530 { 22028 /* th.fsurd */, RISCV::TH_FSURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9531 { 22037 /* th.fsurw */, RISCV::TH_FSURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9532 { 22046 /* th.icache.iall */, RISCV::TH_ICACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9533 { 22061 /* th.icache.ialls */, RISCV::TH_ICACHE_IALLS, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9534 { 22077 /* th.icache.ipa */, RISCV::TH_ICACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9535 { 22091 /* th.icache.iva */, RISCV::TH_ICACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9536 { 22105 /* th.l2cache.call */, RISCV::TH_L2CACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9537 { 22121 /* th.l2cache.ciall */, RISCV::TH_L2CACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9538 { 22138 /* th.l2cache.iall */, RISCV::TH_L2CACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9539 { 22154 /* th.lbia */, RISCV::TH_LBIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9540 { 22162 /* th.lbib */, RISCV::TH_LBIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9541 { 22170 /* th.lbuia */, RISCV::TH_LBUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9542 { 22179 /* th.lbuib */, RISCV::TH_LBUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9543 { 22188 /* th.ldd */, RISCV::TH_LDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmFour }, },
9544 { 22195 /* th.ldia */, RISCV::TH_LDIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9545 { 22203 /* th.ldib */, RISCV::TH_LDIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9546 { 22211 /* th.lhia */, RISCV::TH_LHIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9547 { 22219 /* th.lhib */, RISCV::TH_LHIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9548 { 22227 /* th.lhuia */, RISCV::TH_LHUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9549 { 22236 /* th.lhuib */, RISCV::TH_LHUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9550 { 22245 /* th.lrb */, RISCV::TH_LRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9551 { 22252 /* th.lrbu */, RISCV::TH_LRBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9552 { 22260 /* th.lrd */, RISCV::TH_LRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9553 { 22267 /* th.lrh */, RISCV::TH_LRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9554 { 22274 /* th.lrhu */, RISCV::TH_LRHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9555 { 22282 /* th.lrw */, RISCV::TH_LRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9556 { 22289 /* th.lrwu */, RISCV::TH_LRWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9557 { 22297 /* th.lurb */, RISCV::TH_LURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9558 { 22305 /* th.lurbu */, RISCV::TH_LURBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9559 { 22314 /* th.lurd */, RISCV::TH_LURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9560 { 22322 /* th.lurh */, RISCV::TH_LURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9561 { 22330 /* th.lurhu */, RISCV::TH_LURHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9562 { 22339 /* th.lurw */, RISCV::TH_LURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9563 { 22347 /* th.lurwu */, RISCV::TH_LURWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9564 { 22356 /* th.lwd */, RISCV::TH_LWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
9565 { 22363 /* th.lwia */, RISCV::TH_LWIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9566 { 22371 /* th.lwib */, RISCV::TH_LWIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9567 { 22379 /* th.lwud */, RISCV::TH_LWUD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
9568 { 22387 /* th.lwuia */, RISCV::TH_LWUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9569 { 22396 /* th.lwuib */, RISCV::TH_LWUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9570 { 22405 /* th.mula */, RISCV::TH_MULA, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9571 { 22413 /* th.mulah */, RISCV::TH_MULAH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9572 { 22422 /* th.mulaw */, RISCV::TH_MULAW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9573 { 22431 /* th.muls */, RISCV::TH_MULS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9574 { 22439 /* th.mulsh */, RISCV::TH_MULSH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9575 { 22448 /* th.mulsw */, RISCV::TH_MULSW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9576 { 22457 /* th.mveqz */, RISCV::TH_MVEQZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9577 { 22466 /* th.mvnez */, RISCV::TH_MVNEZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9578 { 22475 /* th.rev */, RISCV::TH_REV, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
9579 { 22482 /* th.revw */, RISCV::TH_REVW, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR }, },
9580 { 22490 /* th.sbia */, RISCV::TH_SBIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9581 { 22498 /* th.sbib */, RISCV::TH_SBIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9582 { 22506 /* th.sdd */, RISCV::TH_SDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmFour }, },
9583 { 22513 /* th.sdia */, RISCV::TH_SDIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9584 { 22521 /* th.sdib */, RISCV::TH_SDIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9585 { 22529 /* th.sfence.vmas */, RISCV::TH_SFENCE_VMAS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadSync, { MCK_GPR, MCK_GPR }, },
9586 { 22544 /* th.shia */, RISCV::TH_SHIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9587 { 22552 /* th.shib */, RISCV::TH_SHIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9588 { 22560 /* th.srb */, RISCV::TH_SRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9589 { 22567 /* th.srd */, RISCV::TH_SRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9590 { 22574 /* th.srh */, RISCV::TH_SRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9591 { 22581 /* th.srri */, RISCV::TH_SRRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9592 { 22589 /* th.srriw */, RISCV::TH_SRRIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9593 { 22598 /* th.srw */, RISCV::TH_SRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9594 { 22605 /* th.surb */, RISCV::TH_SURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9595 { 22613 /* th.surd */, RISCV::TH_SURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9596 { 22621 /* th.surh */, RISCV::TH_SURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9597 { 22629 /* th.surw */, RISCV::TH_SURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9598 { 22637 /* th.swd */, RISCV::TH_SWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
9599 { 22644 /* th.swia */, RISCV::TH_SWIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9600 { 22652 /* th.swib */, RISCV::TH_SWIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9601 { 22660 /* th.sync */, RISCV::TH_SYNC, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
9602 { 22668 /* th.sync.i */, RISCV::TH_SYNC_I, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
9603 { 22678 /* th.sync.is */, RISCV::TH_SYNC_IS, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
9604 { 22689 /* th.sync.s */, RISCV::TH_SYNC_S, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
9605 { 22699 /* th.tst */, RISCV::TH_TST, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9606 { 22706 /* th.tstnbz */, RISCV::TH_TSTNBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
9607 { 22716 /* th.vmaqa.vv */, RISCV::TH_VMAQA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9608 { 22728 /* th.vmaqa.vx */, RISCV::TH_VMAQA_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9609 { 22740 /* th.vmaqasu.vv */, RISCV::TH_VMAQASU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9610 { 22754 /* th.vmaqasu.vx */, RISCV::TH_VMAQASU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9611 { 22768 /* th.vmaqau.vv */, RISCV::TH_VMAQAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9612 { 22781 /* th.vmaqau.vx */, RISCV::TH_VMAQAU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9613 { 22794 /* th.vmaqaus.vx */, RISCV::TH_VMAQAUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9614 { 22808 /* unimp */, RISCV::UNIMP, Convert_NoOperands, AMFBS_None, { }, },
9615 { 22814 /* unzip */, RISCV::UNZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
9616 { 22820 /* unzip16hp */, RISCV::UNZIP16HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9617 { 22830 /* unzip16p */, RISCV::UNZIP16P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9618 { 22839 /* unzip8hp */, RISCV::UNZIP8HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9619 { 22848 /* unzip8p */, RISCV::UNZIP8P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9620 { 22856 /* usati */, RISCV::USATI_RV32, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9621 { 22856 /* usati */, RISCV::USATI_RV64, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
9622 { 22862 /* vaadd.vv */, RISCV::VAADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9623 { 22871 /* vaadd.vx */, RISCV::VAADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9624 { 22880 /* vaaddu.vv */, RISCV::VAADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9625 { 22890 /* vaaddu.vx */, RISCV::VAADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9626 { 22900 /* vadc.vim */, RISCV::VADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
9627 { 22909 /* vadc.vvm */, RISCV::VADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
9628 { 22918 /* vadc.vxm */, RISCV::VADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
9629 { 22927 /* vadd.vi */, RISCV::VADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
9630 { 22935 /* vadd.vv */, RISCV::VADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9631 { 22943 /* vadd.vx */, RISCV::VADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9632 { 22951 /* vaesdf.vs */, RISCV::VAESDF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
9633 { 22961 /* vaesdf.vv */, RISCV::VAESDF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
9634 { 22971 /* vaesdm.vs */, RISCV::VAESDM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
9635 { 22981 /* vaesdm.vv */, RISCV::VAESDM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
9636 { 22991 /* vaesef.vs */, RISCV::VAESEF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
9637 { 23001 /* vaesef.vv */, RISCV::VAESEF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
9638 { 23011 /* vaesem.vs */, RISCV::VAESEM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
9639 { 23021 /* vaesem.vv */, RISCV::VAESEM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
9640 { 23031 /* vaeskf1.vi */, RISCV::VAESKF1_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR, MCK_UImm5 }, },
9641 { 23042 /* vaeskf2.vi */, RISCV::VAESKF2_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR, MCK_UImm5 }, },
9642 { 23053 /* vaesz.vs */, RISCV::VAESZ_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
9643 { 23062 /* vand.vi */, RISCV::VAND_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
9644 { 23070 /* vand.vv */, RISCV::VAND_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9645 { 23078 /* vand.vx */, RISCV::VAND_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9646 { 23086 /* vandn.vv */, RISCV::VANDN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9647 { 23095 /* vandn.vx */, RISCV::VANDN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9648 { 23104 /* vasub.vv */, RISCV::VASUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9649 { 23113 /* vasub.vx */, RISCV::VASUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9650 { 23122 /* vasubu.vv */, RISCV::VASUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9651 { 23132 /* vasubu.vx */, RISCV::VASUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9652 { 23142 /* vbrev.v */, RISCV::VBREV_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9653 { 23150 /* vbrev8.v */, RISCV::VBREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9654 { 23159 /* vclmul.vv */, RISCV::VCLMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9655 { 23169 /* vclmul.vx */, RISCV::VCLMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9656 { 23179 /* vclmulh.vv */, RISCV::VCLMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9657 { 23190 /* vclmulh.vx */, RISCV::VCLMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9658 { 23201 /* vclz.v */, RISCV::VCLZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9659 { 23208 /* vcompress.vm */, RISCV::VCOMPRESS_VM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
9660 { 23221 /* vcpop.m */, RISCV::VCPOP_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9661 { 23229 /* vcpop.v */, RISCV::VCPOP_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9662 { 23237 /* vctz.v */, RISCV::VCTZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9663 { 23244 /* vdiv.vv */, RISCV::VDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9664 { 23252 /* vdiv.vx */, RISCV::VDIV_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9665 { 23260 /* vdivu.vv */, RISCV::VDIVU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9666 { 23269 /* vdivu.vx */, RISCV::VDIVU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9667 { 23278 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR }, },
9668 { 23278 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9669 { 23286 /* vfadd.vf */, RISCV::VFADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9670 { 23295 /* vfadd.vv */, RISCV::VFADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9671 { 23304 /* vfclass.v */, RISCV::VFCLASS_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9672 { 23314 /* vfcvt.f.x.v */, RISCV::VFCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9673 { 23326 /* vfcvt.f.xu.v */, RISCV::VFCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9674 { 23339 /* vfcvt.rtz.x.f.v */, RISCV::VFCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9675 { 23355 /* vfcvt.rtz.xu.f.v */, RISCV::VFCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9676 { 23372 /* vfcvt.x.f.v */, RISCV::VFCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9677 { 23384 /* vfcvt.xu.f.v */, RISCV::VFCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9678 { 23397 /* vfdiv.vf */, RISCV::VFDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9679 { 23406 /* vfdiv.vv */, RISCV::VFDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9680 { 23415 /* vfirst.m */, RISCV::VFIRST_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9681 { 23424 /* vfmacc.vf */, RISCV::VFMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9682 { 23434 /* vfmacc.vv */, RISCV::VFMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9683 { 23444 /* vfmadd.vf */, RISCV::VFMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9684 { 23454 /* vfmadd.vv */, RISCV::VFMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9685 { 23464 /* vfmax.vf */, RISCV::VFMAX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9686 { 23473 /* vfmax.vv */, RISCV::VFMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9687 { 23482 /* vfmerge.vfm */, RISCV::VFMERGE_VFM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskCarryInRegOpOperand }, },
9688 { 23494 /* vfmin.vf */, RISCV::VFMIN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9689 { 23503 /* vfmin.vv */, RISCV::VFMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9690 { 23512 /* vfmsac.vf */, RISCV::VFMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9691 { 23522 /* vfmsac.vv */, RISCV::VFMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9692 { 23532 /* vfmsub.vf */, RISCV::VFMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9693 { 23542 /* vfmsub.vv */, RISCV::VFMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9694 { 23552 /* vfmul.vf */, RISCV::VFMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9695 { 23561 /* vfmul.vv */, RISCV::VFMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9696 { 23570 /* vfmv.f.s */, RISCV::VFMV_F_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_FPR32, MCK_VR }, },
9697 { 23579 /* vfmv.s.f */, RISCV::VFMV_S_F, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32 }, },
9698 { 23588 /* vfmv.v.f */, RISCV::VFMV_V_F, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32 }, },
9699 { 23597 /* vfncvt.f.f.q */, RISCV::VFNCVT_F_F_Q, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9700 { 23610 /* vfncvt.f.f.w */, RISCV::VFNCVT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9701 { 23623 /* vfncvt.f.x.w */, RISCV::VFNCVT_F_X_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9702 { 23636 /* vfncvt.f.xu.w */, RISCV::VFNCVT_F_XU_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9703 { 23650 /* vfncvt.rod.f.f.w */, RISCV::VFNCVT_ROD_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9704 { 23667 /* vfncvt.rtz.x.f.w */, RISCV::VFNCVT_RTZ_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9705 { 23684 /* vfncvt.rtz.xu.f.w */, RISCV::VFNCVT_RTZ_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9706 { 23702 /* vfncvt.sat.f.f.q */, RISCV::VFNCVT_SAT_F_F_Q, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9707 { 23719 /* vfncvt.x.f.w */, RISCV::VFNCVT_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9708 { 23732 /* vfncvt.xu.f.w */, RISCV::VFNCVT_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9709 { 23746 /* vfncvtbf16.f.f.w */, RISCV::VFNCVTBF16_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfminOrZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9710 { 23763 /* vfncvtbf16.sat.f.f.w */, RISCV::VFNCVTBF16_SAT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9711 { 23784 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR }, },
9712 { 23784 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9713 { 23792 /* vfnmacc.vf */, RISCV::VFNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9714 { 23803 /* vfnmacc.vv */, RISCV::VFNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9715 { 23814 /* vfnmadd.vf */, RISCV::VFNMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9716 { 23825 /* vfnmadd.vv */, RISCV::VFNMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9717 { 23836 /* vfnmsac.vf */, RISCV::VFNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9718 { 23847 /* vfnmsac.vv */, RISCV::VFNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9719 { 23858 /* vfnmsub.vf */, RISCV::VFNMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9720 { 23869 /* vfnmsub.vv */, RISCV::VFNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9721 { 23880 /* vfrdiv.vf */, RISCV::VFRDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9722 { 23890 /* vfrec7.v */, RISCV::VFREC7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9723 { 23899 /* vfredmax.vs */, RISCV::VFREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9724 { 23911 /* vfredmin.vs */, RISCV::VFREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9725 { 23923 /* vfredosum.vs */, RISCV::VFREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9726 { 23936 /* vfredusum.vs */, RISCV::VFREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9727 { 23949 /* vfrsqrt7.v */, RISCV::VFRSQRT7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9728 { 23960 /* vfrsub.vf */, RISCV::VFRSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9729 { 23970 /* vfsgnj.vf */, RISCV::VFSGNJ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9730 { 23980 /* vfsgnj.vv */, RISCV::VFSGNJ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9731 { 23990 /* vfsgnjn.vf */, RISCV::VFSGNJN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9732 { 24001 /* vfsgnjn.vv */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9733 { 24012 /* vfsgnjx.vf */, RISCV::VFSGNJX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9734 { 24023 /* vfsgnjx.vv */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9735 { 24034 /* vfslide1down.vf */, RISCV::VFSLIDE1DOWN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9736 { 24050 /* vfslide1up.vf */, RISCV::VFSLIDE1UP_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9737 { 24064 /* vfsqrt.v */, RISCV::VFSQRT_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9738 { 24073 /* vfsub.vf */, RISCV::VFSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9739 { 24082 /* vfsub.vv */, RISCV::VFSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9740 { 24091 /* vfwadd.vf */, RISCV::VFWADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9741 { 24101 /* vfwadd.vv */, RISCV::VFWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9742 { 24111 /* vfwadd.wf */, RISCV::VFWADD_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9743 { 24121 /* vfwadd.wv */, RISCV::VFWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9744 { 24131 /* vfwcvt.f.f.v */, RISCV::VFWCVT_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9745 { 24144 /* vfwcvt.f.x.v */, RISCV::VFWCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9746 { 24157 /* vfwcvt.f.xu.v */, RISCV::VFWCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9747 { 24171 /* vfwcvt.rtz.x.f.v */, RISCV::VFWCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9748 { 24188 /* vfwcvt.rtz.xu.f.v */, RISCV::VFWCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9749 { 24206 /* vfwcvt.x.f.v */, RISCV::VFWCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9750 { 24219 /* vfwcvt.xu.f.v */, RISCV::VFWCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9751 { 24233 /* vfwcvtbf16.f.f.v */, RISCV::VFWCVTBF16_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfminOrZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9752 { 24250 /* vfwmacc.vf */, RISCV::VFWMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9753 { 24261 /* vfwmacc.vv */, RISCV::VFWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9754 { 24272 /* vfwmaccbf16.vf */, RISCV::VFWMACCBF16_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9755 { 24287 /* vfwmaccbf16.vv */, RISCV::VFWMACCBF16_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9756 { 24302 /* vfwmsac.vf */, RISCV::VFWMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9757 { 24313 /* vfwmsac.vv */, RISCV::VFWMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9758 { 24324 /* vfwmul.vf */, RISCV::VFWMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9759 { 24334 /* vfwmul.vv */, RISCV::VFWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9760 { 24344 /* vfwnmacc.vf */, RISCV::VFWNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9761 { 24356 /* vfwnmacc.vv */, RISCV::VFWNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9762 { 24368 /* vfwnmsac.vf */, RISCV::VFWNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9763 { 24380 /* vfwnmsac.vv */, RISCV::VFWNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9764 { 24392 /* vfwredosum.vs */, RISCV::VFWREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9765 { 24406 /* vfwredusum.vs */, RISCV::VFWREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9766 { 24420 /* vfwsub.vf */, RISCV::VFWSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9767 { 24430 /* vfwsub.vv */, RISCV::VFWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9768 { 24440 /* vfwsub.wf */, RISCV::VFWSUB_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9769 { 24450 /* vfwsub.wv */, RISCV::VFWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9770 { 24460 /* vghsh.vs */, RISCV::VGHSH_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkgs, { MCK_VR, MCK_VR, MCK_VR }, },
9771 { 24469 /* vghsh.vv */, RISCV::VGHSH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkg, { MCK_VR, MCK_VR, MCK_VR }, },
9772 { 24478 /* vgmul.vs */, RISCV::VGMUL_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkgs, { MCK_VR, MCK_VR }, },
9773 { 24487 /* vgmul.vv */, RISCV::VGMUL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkg, { MCK_VR, MCK_VR }, },
9774 { 24496 /* vid.v */, RISCV::VID_V, Convert__Reg1_0__RVVMaskRegOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_RVVMaskRegOpOperand }, },
9775 { 24502 /* viota.m */, RISCV::VIOTA_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9776 { 24510 /* vl1r.v */, RISCV::VL1RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
9777 { 24517 /* vl1re16.v */, RISCV::VL1RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
9778 { 24527 /* vl1re32.v */, RISCV::VL1RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
9779 { 24537 /* vl1re64.v */, RISCV::VL1RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
9780 { 24547 /* vl1re8.v */, RISCV::VL1RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
9781 { 24556 /* vl2r.v */, RISCV::VL2RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
9782 { 24563 /* vl2re16.v */, RISCV::VL2RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
9783 { 24573 /* vl2re32.v */, RISCV::VL2RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
9784 { 24583 /* vl2re64.v */, RISCV::VL2RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
9785 { 24593 /* vl2re8.v */, RISCV::VL2RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
9786 { 24602 /* vl4r.v */, RISCV::VL4RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
9787 { 24609 /* vl4re16.v */, RISCV::VL4RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
9788 { 24619 /* vl4re32.v */, RISCV::VL4RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
9789 { 24629 /* vl4re64.v */, RISCV::VL4RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
9790 { 24639 /* vl4re8.v */, RISCV::VL4RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
9791 { 24648 /* vl8r.v */, RISCV::VL8RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
9792 { 24655 /* vl8re16.v */, RISCV::VL8RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
9793 { 24665 /* vl8re32.v */, RISCV::VL8RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
9794 { 24675 /* vl8re64.v */, RISCV::VL8RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
9795 { 24685 /* vl8re8.v */, RISCV::VL8RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
9796 { 24694 /* vle16.v */, RISCV::VLE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9797 { 24702 /* vle16ff.v */, RISCV::VLE16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9798 { 24712 /* vle32.v */, RISCV::VLE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9799 { 24720 /* vle32ff.v */, RISCV::VLE32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9800 { 24730 /* vle64.v */, RISCV::VLE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9801 { 24738 /* vle64ff.v */, RISCV::VLE64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9802 { 24748 /* vle8.v */, RISCV::VLE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9803 { 24755 /* vle8ff.v */, RISCV::VLE8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9804 { 24764 /* vlm.v */, RISCV::VLM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
9805 { 24770 /* vloxei16.v */, RISCV::VLOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9806 { 24781 /* vloxei32.v */, RISCV::VLOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9807 { 24792 /* vloxei64.v */, RISCV::VLOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9808 { 24803 /* vloxei8.v */, RISCV::VLOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9809 { 24813 /* vloxseg2ei16.v */, RISCV::VLOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9810 { 24828 /* vloxseg2ei32.v */, RISCV::VLOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9811 { 24843 /* vloxseg2ei64.v */, RISCV::VLOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9812 { 24858 /* vloxseg2ei8.v */, RISCV::VLOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9813 { 24872 /* vloxseg3ei16.v */, RISCV::VLOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9814 { 24887 /* vloxseg3ei32.v */, RISCV::VLOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9815 { 24902 /* vloxseg3ei64.v */, RISCV::VLOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9816 { 24917 /* vloxseg3ei8.v */, RISCV::VLOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9817 { 24931 /* vloxseg4ei16.v */, RISCV::VLOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9818 { 24946 /* vloxseg4ei32.v */, RISCV::VLOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9819 { 24961 /* vloxseg4ei64.v */, RISCV::VLOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9820 { 24976 /* vloxseg4ei8.v */, RISCV::VLOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9821 { 24990 /* vloxseg5ei16.v */, RISCV::VLOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9822 { 25005 /* vloxseg5ei32.v */, RISCV::VLOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9823 { 25020 /* vloxseg5ei64.v */, RISCV::VLOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9824 { 25035 /* vloxseg5ei8.v */, RISCV::VLOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9825 { 25049 /* vloxseg6ei16.v */, RISCV::VLOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9826 { 25064 /* vloxseg6ei32.v */, RISCV::VLOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9827 { 25079 /* vloxseg6ei64.v */, RISCV::VLOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9828 { 25094 /* vloxseg6ei8.v */, RISCV::VLOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9829 { 25108 /* vloxseg7ei16.v */, RISCV::VLOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9830 { 25123 /* vloxseg7ei32.v */, RISCV::VLOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9831 { 25138 /* vloxseg7ei64.v */, RISCV::VLOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9832 { 25153 /* vloxseg7ei8.v */, RISCV::VLOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9833 { 25167 /* vloxseg8ei16.v */, RISCV::VLOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9834 { 25182 /* vloxseg8ei32.v */, RISCV::VLOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9835 { 25197 /* vloxseg8ei64.v */, RISCV::VLOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9836 { 25212 /* vloxseg8ei8.v */, RISCV::VLOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9837 { 25226 /* vlse16.v */, RISCV::VLSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9838 { 25235 /* vlse32.v */, RISCV::VLSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9839 { 25244 /* vlse64.v */, RISCV::VLSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9840 { 25253 /* vlse8.v */, RISCV::VLSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9841 { 25261 /* vlseg2e16.v */, RISCV::VLSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9842 { 25273 /* vlseg2e16ff.v */, RISCV::VLSEG2E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9843 { 25287 /* vlseg2e32.v */, RISCV::VLSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9844 { 25299 /* vlseg2e32ff.v */, RISCV::VLSEG2E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9845 { 25313 /* vlseg2e64.v */, RISCV::VLSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9846 { 25325 /* vlseg2e64ff.v */, RISCV::VLSEG2E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9847 { 25339 /* vlseg2e8.v */, RISCV::VLSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9848 { 25350 /* vlseg2e8ff.v */, RISCV::VLSEG2E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9849 { 25363 /* vlseg3e16.v */, RISCV::VLSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9850 { 25375 /* vlseg3e16ff.v */, RISCV::VLSEG3E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9851 { 25389 /* vlseg3e32.v */, RISCV::VLSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9852 { 25401 /* vlseg3e32ff.v */, RISCV::VLSEG3E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9853 { 25415 /* vlseg3e64.v */, RISCV::VLSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9854 { 25427 /* vlseg3e64ff.v */, RISCV::VLSEG3E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9855 { 25441 /* vlseg3e8.v */, RISCV::VLSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9856 { 25452 /* vlseg3e8ff.v */, RISCV::VLSEG3E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9857 { 25465 /* vlseg4e16.v */, RISCV::VLSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9858 { 25477 /* vlseg4e16ff.v */, RISCV::VLSEG4E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9859 { 25491 /* vlseg4e32.v */, RISCV::VLSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9860 { 25503 /* vlseg4e32ff.v */, RISCV::VLSEG4E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9861 { 25517 /* vlseg4e64.v */, RISCV::VLSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9862 { 25529 /* vlseg4e64ff.v */, RISCV::VLSEG4E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9863 { 25543 /* vlseg4e8.v */, RISCV::VLSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9864 { 25554 /* vlseg4e8ff.v */, RISCV::VLSEG4E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9865 { 25567 /* vlseg5e16.v */, RISCV::VLSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9866 { 25579 /* vlseg5e16ff.v */, RISCV::VLSEG5E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9867 { 25593 /* vlseg5e32.v */, RISCV::VLSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9868 { 25605 /* vlseg5e32ff.v */, RISCV::VLSEG5E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9869 { 25619 /* vlseg5e64.v */, RISCV::VLSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9870 { 25631 /* vlseg5e64ff.v */, RISCV::VLSEG5E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9871 { 25645 /* vlseg5e8.v */, RISCV::VLSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9872 { 25656 /* vlseg5e8ff.v */, RISCV::VLSEG5E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9873 { 25669 /* vlseg6e16.v */, RISCV::VLSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9874 { 25681 /* vlseg6e16ff.v */, RISCV::VLSEG6E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9875 { 25695 /* vlseg6e32.v */, RISCV::VLSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9876 { 25707 /* vlseg6e32ff.v */, RISCV::VLSEG6E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9877 { 25721 /* vlseg6e64.v */, RISCV::VLSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9878 { 25733 /* vlseg6e64ff.v */, RISCV::VLSEG6E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9879 { 25747 /* vlseg6e8.v */, RISCV::VLSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9880 { 25758 /* vlseg6e8ff.v */, RISCV::VLSEG6E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9881 { 25771 /* vlseg7e16.v */, RISCV::VLSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9882 { 25783 /* vlseg7e16ff.v */, RISCV::VLSEG7E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9883 { 25797 /* vlseg7e32.v */, RISCV::VLSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9884 { 25809 /* vlseg7e32ff.v */, RISCV::VLSEG7E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9885 { 25823 /* vlseg7e64.v */, RISCV::VLSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9886 { 25835 /* vlseg7e64ff.v */, RISCV::VLSEG7E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9887 { 25849 /* vlseg7e8.v */, RISCV::VLSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9888 { 25860 /* vlseg7e8ff.v */, RISCV::VLSEG7E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9889 { 25873 /* vlseg8e16.v */, RISCV::VLSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9890 { 25885 /* vlseg8e16ff.v */, RISCV::VLSEG8E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9891 { 25899 /* vlseg8e32.v */, RISCV::VLSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9892 { 25911 /* vlseg8e32ff.v */, RISCV::VLSEG8E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9893 { 25925 /* vlseg8e64.v */, RISCV::VLSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9894 { 25937 /* vlseg8e64ff.v */, RISCV::VLSEG8E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9895 { 25951 /* vlseg8e8.v */, RISCV::VLSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9896 { 25962 /* vlseg8e8ff.v */, RISCV::VLSEG8E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9897 { 25975 /* vlsseg2e16.v */, RISCV::VLSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9898 { 25988 /* vlsseg2e32.v */, RISCV::VLSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9899 { 26001 /* vlsseg2e64.v */, RISCV::VLSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9900 { 26014 /* vlsseg2e8.v */, RISCV::VLSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9901 { 26026 /* vlsseg3e16.v */, RISCV::VLSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9902 { 26039 /* vlsseg3e32.v */, RISCV::VLSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9903 { 26052 /* vlsseg3e64.v */, RISCV::VLSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9904 { 26065 /* vlsseg3e8.v */, RISCV::VLSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9905 { 26077 /* vlsseg4e16.v */, RISCV::VLSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9906 { 26090 /* vlsseg4e32.v */, RISCV::VLSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9907 { 26103 /* vlsseg4e64.v */, RISCV::VLSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9908 { 26116 /* vlsseg4e8.v */, RISCV::VLSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9909 { 26128 /* vlsseg5e16.v */, RISCV::VLSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9910 { 26141 /* vlsseg5e32.v */, RISCV::VLSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9911 { 26154 /* vlsseg5e64.v */, RISCV::VLSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9912 { 26167 /* vlsseg5e8.v */, RISCV::VLSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9913 { 26179 /* vlsseg6e16.v */, RISCV::VLSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9914 { 26192 /* vlsseg6e32.v */, RISCV::VLSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9915 { 26205 /* vlsseg6e64.v */, RISCV::VLSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9916 { 26218 /* vlsseg6e8.v */, RISCV::VLSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9917 { 26230 /* vlsseg7e16.v */, RISCV::VLSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9918 { 26243 /* vlsseg7e32.v */, RISCV::VLSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9919 { 26256 /* vlsseg7e64.v */, RISCV::VLSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9920 { 26269 /* vlsseg7e8.v */, RISCV::VLSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9921 { 26281 /* vlsseg8e16.v */, RISCV::VLSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9922 { 26294 /* vlsseg8e32.v */, RISCV::VLSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9923 { 26307 /* vlsseg8e64.v */, RISCV::VLSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9924 { 26320 /* vlsseg8e8.v */, RISCV::VLSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9925 { 26332 /* vluxei16.v */, RISCV::VLUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9926 { 26343 /* vluxei32.v */, RISCV::VLUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9927 { 26354 /* vluxei64.v */, RISCV::VLUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9928 { 26365 /* vluxei8.v */, RISCV::VLUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9929 { 26375 /* vluxseg2ei16.v */, RISCV::VLUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9930 { 26390 /* vluxseg2ei32.v */, RISCV::VLUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9931 { 26405 /* vluxseg2ei64.v */, RISCV::VLUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9932 { 26420 /* vluxseg2ei8.v */, RISCV::VLUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9933 { 26434 /* vluxseg3ei16.v */, RISCV::VLUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9934 { 26449 /* vluxseg3ei32.v */, RISCV::VLUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9935 { 26464 /* vluxseg3ei64.v */, RISCV::VLUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9936 { 26479 /* vluxseg3ei8.v */, RISCV::VLUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9937 { 26493 /* vluxseg4ei16.v */, RISCV::VLUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9938 { 26508 /* vluxseg4ei32.v */, RISCV::VLUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9939 { 26523 /* vluxseg4ei64.v */, RISCV::VLUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9940 { 26538 /* vluxseg4ei8.v */, RISCV::VLUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9941 { 26552 /* vluxseg5ei16.v */, RISCV::VLUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9942 { 26567 /* vluxseg5ei32.v */, RISCV::VLUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9943 { 26582 /* vluxseg5ei64.v */, RISCV::VLUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9944 { 26597 /* vluxseg5ei8.v */, RISCV::VLUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9945 { 26611 /* vluxseg6ei16.v */, RISCV::VLUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9946 { 26626 /* vluxseg6ei32.v */, RISCV::VLUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9947 { 26641 /* vluxseg6ei64.v */, RISCV::VLUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9948 { 26656 /* vluxseg6ei8.v */, RISCV::VLUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9949 { 26670 /* vluxseg7ei16.v */, RISCV::VLUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9950 { 26685 /* vluxseg7ei32.v */, RISCV::VLUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9951 { 26700 /* vluxseg7ei64.v */, RISCV::VLUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9952 { 26715 /* vluxseg7ei8.v */, RISCV::VLUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9953 { 26729 /* vluxseg8ei16.v */, RISCV::VLUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9954 { 26744 /* vluxseg8ei32.v */, RISCV::VLUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9955 { 26759 /* vluxseg8ei64.v */, RISCV::VLUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9956 { 26774 /* vluxseg8ei8.v */, RISCV::VLUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9957 { 26788 /* vmacc.vv */, RISCV::VMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9958 { 26797 /* vmacc.vx */, RISCV::VMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9959 { 26806 /* vmadc.vi */, RISCV::VMADC_VI, Convert__Reg1_0__Reg1_1__SImm51_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5 }, },
9960 { 26815 /* vmadc.vim */, RISCV::VMADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
9961 { 26825 /* vmadc.vv */, RISCV::VMADC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
9962 { 26834 /* vmadc.vvm */, RISCV::VMADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
9963 { 26844 /* vmadc.vx */, RISCV::VMADC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
9964 { 26853 /* vmadc.vxm */, RISCV::VMADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
9965 { 26863 /* vmadd.vv */, RISCV::VMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9966 { 26872 /* vmadd.vx */, RISCV::VMADD_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9967 { 26881 /* vmand.mm */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
9968 { 26890 /* vmandn.mm */, RISCV::VMANDN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
9969 { 26900 /* vmax.vv */, RISCV::VMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9970 { 26908 /* vmax.vx */, RISCV::VMAX_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9971 { 26916 /* vmaxu.vv */, RISCV::VMAXU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9972 { 26925 /* vmaxu.vx */, RISCV::VMAXU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9973 { 26934 /* vmclr.m */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VR }, },
9974 { 26942 /* vmerge.vim */, RISCV::VMERGE_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
9975 { 26953 /* vmerge.vvm */, RISCV::VMERGE_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
9976 { 26964 /* vmerge.vxm */, RISCV::VMERGE_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
9977 { 26975 /* vmfeq.vf */, RISCV::VMFEQ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9978 { 26984 /* vmfeq.vv */, RISCV::VMFEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9979 { 26993 /* vmfge.vf */, RISCV::VMFGE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9980 { 27002 /* vmfge.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9981 { 27011 /* vmfgt.vf */, RISCV::VMFGT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9982 { 27020 /* vmfgt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9983 { 27029 /* vmfle.vf */, RISCV::VMFLE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9984 { 27038 /* vmfle.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9985 { 27047 /* vmflt.vf */, RISCV::VMFLT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9986 { 27056 /* vmflt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9987 { 27065 /* vmfne.vf */, RISCV::VMFNE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9988 { 27074 /* vmfne.vv */, RISCV::VMFNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9989 { 27083 /* vmin.vv */, RISCV::VMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9990 { 27091 /* vmin.vx */, RISCV::VMIN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9991 { 27099 /* vminu.vv */, RISCV::VMINU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9992 { 27108 /* vminu.vx */, RISCV::VMINU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
9993 { 27117 /* vmmv.m */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
9994 { 27124 /* vmnand.mm */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
9995 { 27134 /* vmnor.mm */, RISCV::VMNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
9996 { 27143 /* vmnot.m */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
9997 { 27151 /* vmor.mm */, RISCV::VMOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
9998 { 27159 /* vmorn.mm */, RISCV::VMORN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
9999 { 27168 /* vmsbc.vv */, RISCV::VMSBC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10000 { 27177 /* vmsbc.vvm */, RISCV::VMSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10001 { 27187 /* vmsbc.vx */, RISCV::VMSBC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10002 { 27196 /* vmsbc.vxm */, RISCV::VMSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10003 { 27206 /* vmsbf.m */, RISCV::VMSBF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10004 { 27214 /* vmseq.vi */, RISCV::VMSEQ_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10005 { 27223 /* vmseq.vv */, RISCV::VMSEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10006 { 27232 /* vmseq.vx */, RISCV::VMSEQ_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10007 { 27241 /* vmset.m */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VR }, },
10008 { 27249 /* vmsge.vi */, RISCV::PseudoVMSGE_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10009 { 27258 /* vmsge.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10010 { 27267 /* vmsge.vx */, RISCV::PseudoVMSGE_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10011 { 27267 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VRNoV0, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10012 { 27267 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
10013 { 27276 /* vmsgeu.vi */, RISCV::PseudoVMSGEU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10014 { 27286 /* vmsgeu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10015 { 27296 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10016 { 27296 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VRNoV0, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10017 { 27296 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
10018 { 27306 /* vmsgt.vi */, RISCV::VMSGT_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10019 { 27315 /* vmsgt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10020 { 27324 /* vmsgt.vx */, RISCV::VMSGT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10021 { 27333 /* vmsgtu.vi */, RISCV::VMSGTU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10022 { 27343 /* vmsgtu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10023 { 27353 /* vmsgtu.vx */, RISCV::VMSGTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10024 { 27363 /* vmsif.m */, RISCV::VMSIF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10025 { 27371 /* vmsle.vi */, RISCV::VMSLE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10026 { 27380 /* vmsle.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10027 { 27389 /* vmsle.vx */, RISCV::VMSLE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10028 { 27398 /* vmsleu.vi */, RISCV::VMSLEU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10029 { 27408 /* vmsleu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10030 { 27418 /* vmsleu.vx */, RISCV::VMSLEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10031 { 27428 /* vmslt.vi */, RISCV::PseudoVMSLT_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10032 { 27437 /* vmslt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10033 { 27446 /* vmslt.vx */, RISCV::VMSLT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10034 { 27455 /* vmsltu.vi */, RISCV::PseudoVMSLTU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10035 { 27465 /* vmsltu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10036 { 27475 /* vmsltu.vx */, RISCV::VMSLTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10037 { 27485 /* vmsne.vi */, RISCV::VMSNE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10038 { 27494 /* vmsne.vv */, RISCV::VMSNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10039 { 27503 /* vmsne.vx */, RISCV::VMSNE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10040 { 27512 /* vmsof.m */, RISCV::VMSOF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10041 { 27520 /* vmul.vv */, RISCV::VMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10042 { 27528 /* vmul.vx */, RISCV::VMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10043 { 27536 /* vmulh.vv */, RISCV::VMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10044 { 27545 /* vmulh.vx */, RISCV::VMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10045 { 27554 /* vmulhsu.vv */, RISCV::VMULHSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10046 { 27565 /* vmulhsu.vx */, RISCV::VMULHSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10047 { 27576 /* vmulhu.vv */, RISCV::VMULHU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10048 { 27586 /* vmulhu.vx */, RISCV::VMULHU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10049 { 27596 /* vmv.s.x */, RISCV::VMV_S_X, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR }, },
10050 { 27604 /* vmv.v.i */, RISCV::VMV_V_I, Convert__Reg1_0__SImm51_1, AMFBS_HasVInstructions, { MCK_VR, MCK_SImm5 }, },
10051 { 27612 /* vmv.v.v */, RISCV::VMV_V_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10052 { 27620 /* vmv.v.x */, RISCV::VMV_V_X, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR }, },
10053 { 27628 /* vmv.x.s */, RISCV::VMV_X_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR }, },
10054 { 27636 /* vmv1r.v */, RISCV::VMV1R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10055 { 27644 /* vmv2r.v */, RISCV::VMV2R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_VRM2 }, },
10056 { 27652 /* vmv4r.v */, RISCV::VMV4R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_VRM4 }, },
10057 { 27660 /* vmv8r.v */, RISCV::VMV8R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_VRM8 }, },
10058 { 27668 /* vmxnor.mm */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10059 { 27678 /* vmxor.mm */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10060 { 27687 /* vnclip.wi */, RISCV::VNCLIP_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10061 { 27697 /* vnclip.wv */, RISCV::VNCLIP_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10062 { 27707 /* vnclip.wx */, RISCV::VNCLIP_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10063 { 27717 /* vnclipu.wi */, RISCV::VNCLIPU_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10064 { 27728 /* vnclipu.wv */, RISCV::VNCLIPU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10065 { 27739 /* vnclipu.wx */, RISCV::VNCLIPU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10066 { 27750 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10067 { 27750 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10068 { 27762 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10069 { 27762 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10070 { 27769 /* vnmsac.vv */, RISCV::VNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10071 { 27779 /* vnmsac.vx */, RISCV::VNMSAC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10072 { 27789 /* vnmsub.vv */, RISCV::VNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10073 { 27799 /* vnmsub.vx */, RISCV::VNMSUB_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10074 { 27809 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10075 { 27809 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10076 { 27816 /* vnsra.wi */, RISCV::VNSRA_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10077 { 27825 /* vnsra.wv */, RISCV::VNSRA_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10078 { 27834 /* vnsra.wx */, RISCV::VNSRA_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10079 { 27843 /* vnsrl.wi */, RISCV::VNSRL_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10080 { 27852 /* vnsrl.wv */, RISCV::VNSRL_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10081 { 27861 /* vnsrl.wx */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10082 { 27870 /* vor.vi */, RISCV::VOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10083 { 27877 /* vor.vv */, RISCV::VOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10084 { 27884 /* vor.vx */, RISCV::VOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10085 { 27891 /* vqdot.vv */, RISCV::VQDOT_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqdotq, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10086 { 27900 /* vqdot.vx */, RISCV::VQDOT_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqdotq, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10087 { 27909 /* vqdotsu.vv */, RISCV::VQDOTSU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqdotq, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10088 { 27920 /* vqdotsu.vx */, RISCV::VQDOTSU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqdotq, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10089 { 27931 /* vqdotu.vv */, RISCV::VQDOTU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqdotq, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10090 { 27941 /* vqdotu.vx */, RISCV::VQDOTU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqdotq, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10091 { 27951 /* vqdotus.vx */, RISCV::VQDOTUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqdotq, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10092 { 27962 /* vredand.vs */, RISCV::VREDAND_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10093 { 27973 /* vredmax.vs */, RISCV::VREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10094 { 27984 /* vredmaxu.vs */, RISCV::VREDMAXU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10095 { 27996 /* vredmin.vs */, RISCV::VREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10096 { 28007 /* vredminu.vs */, RISCV::VREDMINU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10097 { 28019 /* vredor.vs */, RISCV::VREDOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10098 { 28029 /* vredsum.vs */, RISCV::VREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10099 { 28040 /* vredxor.vs */, RISCV::VREDXOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10100 { 28051 /* vrem.vv */, RISCV::VREM_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10101 { 28059 /* vrem.vx */, RISCV::VREM_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10102 { 28067 /* vremu.vv */, RISCV::VREMU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10103 { 28076 /* vremu.vx */, RISCV::VREMU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10104 { 28085 /* vrev8.v */, RISCV::VREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10105 { 28093 /* vrgather.vi */, RISCV::VRGATHER_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10106 { 28105 /* vrgather.vv */, RISCV::VRGATHER_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10107 { 28117 /* vrgather.vx */, RISCV::VRGATHER_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10108 { 28129 /* vrgatherei16.vv */, RISCV::VRGATHEREI16_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10109 { 28145 /* vrol.vv */, RISCV::VROL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10110 { 28153 /* vrol.vx */, RISCV::VROL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10111 { 28161 /* vror.vi */, RISCV::VROR_VI, Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_UImm6, MCK_RVVMaskRegOpOperand }, },
10112 { 28169 /* vror.vv */, RISCV::VROR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10113 { 28177 /* vror.vx */, RISCV::VROR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10114 { 28185 /* vrsub.vi */, RISCV::VRSUB_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10115 { 28194 /* vrsub.vx */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10116 { 28203 /* vs1r.v */, RISCV::VS1R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10117 { 28210 /* vs2r.v */, RISCV::VS2R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10118 { 28217 /* vs4r.v */, RISCV::VS4R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10119 { 28224 /* vs8r.v */, RISCV::VS8R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10120 { 28231 /* vsadd.vi */, RISCV::VSADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10121 { 28240 /* vsadd.vv */, RISCV::VSADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10122 { 28249 /* vsadd.vx */, RISCV::VSADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10123 { 28258 /* vsaddu.vi */, RISCV::VSADDU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10124 { 28268 /* vsaddu.vv */, RISCV::VSADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10125 { 28278 /* vsaddu.vx */, RISCV::VSADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10126 { 28288 /* vsbc.vvm */, RISCV::VSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10127 { 28297 /* vsbc.vxm */, RISCV::VSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10128 { 28306 /* vse16.v */, RISCV::VSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10129 { 28314 /* vse32.v */, RISCV::VSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10130 { 28322 /* vse64.v */, RISCV::VSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10131 { 28330 /* vse8.v */, RISCV::VSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10132 { 28337 /* vsetivli */, RISCV::VSETIVLI, Convert__Reg1_0__UImm51_1__VTypeI101_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_UImm5, MCK_VTypeI10 }, },
10133 { 28346 /* vsetvl */, RISCV::VSETVL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10134 { 28353 /* vsetvli */, RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__VTypeI111_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_VTypeI11 }, },
10135 { 28361 /* vsext.vf2 */, RISCV::VSEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10136 { 28371 /* vsext.vf4 */, RISCV::VSEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10137 { 28381 /* vsext.vf8 */, RISCV::VSEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10138 { 28391 /* vsha2ch.vv */, RISCV::VSHA2CH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknhaOrZvknhb, { MCK_VR, MCK_VR, MCK_VR }, },
10139 { 28402 /* vsha2cl.vv */, RISCV::VSHA2CL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknhaOrZvknhb, { MCK_VR, MCK_VR, MCK_VR }, },
10140 { 28413 /* vsha2ms.vv */, RISCV::VSHA2MS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknhaOrZvknhb, { MCK_VR, MCK_VR, MCK_VR }, },
10141 { 28424 /* vslide1down.vx */, RISCV::VSLIDE1DOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10142 { 28439 /* vslide1up.vx */, RISCV::VSLIDE1UP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10143 { 28452 /* vslidedown.vi */, RISCV::VSLIDEDOWN_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10144 { 28466 /* vslidedown.vx */, RISCV::VSLIDEDOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10145 { 28480 /* vslideup.vi */, RISCV::VSLIDEUP_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10146 { 28492 /* vslideup.vx */, RISCV::VSLIDEUP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10147 { 28504 /* vsll.vi */, RISCV::VSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10148 { 28512 /* vsll.vv */, RISCV::VSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10149 { 28520 /* vsll.vx */, RISCV::VSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10150 { 28528 /* vsm.v */, RISCV::VSM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10151 { 28534 /* vsm3c.vi */, RISCV::VSM3C_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksh, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10152 { 28543 /* vsm3me.vv */, RISCV::VSM3ME_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZvksh, { MCK_VR, MCK_VR, MCK_VR }, },
10153 { 28553 /* vsm4k.vi */, RISCV::VSM4K_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10154 { 28562 /* vsm4r.vs */, RISCV::VSM4R_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR }, },
10155 { 28571 /* vsm4r.vv */, RISCV::VSM4R_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR }, },
10156 { 28580 /* vsmul.vv */, RISCV::VSMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10157 { 28589 /* vsmul.vx */, RISCV::VSMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10158 { 28598 /* vsoxei16.v */, RISCV::VSOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10159 { 28609 /* vsoxei32.v */, RISCV::VSOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10160 { 28620 /* vsoxei64.v */, RISCV::VSOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10161 { 28631 /* vsoxei8.v */, RISCV::VSOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10162 { 28641 /* vsoxseg2ei16.v */, RISCV::VSOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10163 { 28656 /* vsoxseg2ei32.v */, RISCV::VSOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10164 { 28671 /* vsoxseg2ei64.v */, RISCV::VSOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10165 { 28686 /* vsoxseg2ei8.v */, RISCV::VSOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10166 { 28700 /* vsoxseg3ei16.v */, RISCV::VSOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10167 { 28715 /* vsoxseg3ei32.v */, RISCV::VSOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10168 { 28730 /* vsoxseg3ei64.v */, RISCV::VSOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10169 { 28745 /* vsoxseg3ei8.v */, RISCV::VSOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10170 { 28759 /* vsoxseg4ei16.v */, RISCV::VSOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10171 { 28774 /* vsoxseg4ei32.v */, RISCV::VSOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10172 { 28789 /* vsoxseg4ei64.v */, RISCV::VSOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10173 { 28804 /* vsoxseg4ei8.v */, RISCV::VSOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10174 { 28818 /* vsoxseg5ei16.v */, RISCV::VSOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10175 { 28833 /* vsoxseg5ei32.v */, RISCV::VSOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10176 { 28848 /* vsoxseg5ei64.v */, RISCV::VSOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10177 { 28863 /* vsoxseg5ei8.v */, RISCV::VSOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10178 { 28877 /* vsoxseg6ei16.v */, RISCV::VSOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10179 { 28892 /* vsoxseg6ei32.v */, RISCV::VSOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10180 { 28907 /* vsoxseg6ei64.v */, RISCV::VSOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10181 { 28922 /* vsoxseg6ei8.v */, RISCV::VSOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10182 { 28936 /* vsoxseg7ei16.v */, RISCV::VSOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10183 { 28951 /* vsoxseg7ei32.v */, RISCV::VSOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10184 { 28966 /* vsoxseg7ei64.v */, RISCV::VSOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10185 { 28981 /* vsoxseg7ei8.v */, RISCV::VSOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10186 { 28995 /* vsoxseg8ei16.v */, RISCV::VSOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10187 { 29010 /* vsoxseg8ei32.v */, RISCV::VSOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10188 { 29025 /* vsoxseg8ei64.v */, RISCV::VSOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10189 { 29040 /* vsoxseg8ei8.v */, RISCV::VSOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10190 { 29054 /* vsra.vi */, RISCV::VSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10191 { 29062 /* vsra.vv */, RISCV::VSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10192 { 29070 /* vsra.vx */, RISCV::VSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10193 { 29078 /* vsrl.vi */, RISCV::VSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10194 { 29086 /* vsrl.vv */, RISCV::VSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10195 { 29094 /* vsrl.vx */, RISCV::VSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10196 { 29102 /* vsse16.v */, RISCV::VSSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10197 { 29111 /* vsse32.v */, RISCV::VSSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10198 { 29120 /* vsse64.v */, RISCV::VSSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10199 { 29129 /* vsse8.v */, RISCV::VSSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10200 { 29137 /* vsseg2e16.v */, RISCV::VSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10201 { 29149 /* vsseg2e32.v */, RISCV::VSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10202 { 29161 /* vsseg2e64.v */, RISCV::VSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10203 { 29173 /* vsseg2e8.v */, RISCV::VSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10204 { 29184 /* vsseg3e16.v */, RISCV::VSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10205 { 29196 /* vsseg3e32.v */, RISCV::VSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10206 { 29208 /* vsseg3e64.v */, RISCV::VSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10207 { 29220 /* vsseg3e8.v */, RISCV::VSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10208 { 29231 /* vsseg4e16.v */, RISCV::VSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10209 { 29243 /* vsseg4e32.v */, RISCV::VSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10210 { 29255 /* vsseg4e64.v */, RISCV::VSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10211 { 29267 /* vsseg4e8.v */, RISCV::VSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10212 { 29278 /* vsseg5e16.v */, RISCV::VSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10213 { 29290 /* vsseg5e32.v */, RISCV::VSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10214 { 29302 /* vsseg5e64.v */, RISCV::VSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10215 { 29314 /* vsseg5e8.v */, RISCV::VSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10216 { 29325 /* vsseg6e16.v */, RISCV::VSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10217 { 29337 /* vsseg6e32.v */, RISCV::VSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10218 { 29349 /* vsseg6e64.v */, RISCV::VSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10219 { 29361 /* vsseg6e8.v */, RISCV::VSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10220 { 29372 /* vsseg7e16.v */, RISCV::VSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10221 { 29384 /* vsseg7e32.v */, RISCV::VSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10222 { 29396 /* vsseg7e64.v */, RISCV::VSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10223 { 29408 /* vsseg7e8.v */, RISCV::VSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10224 { 29419 /* vsseg8e16.v */, RISCV::VSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10225 { 29431 /* vsseg8e32.v */, RISCV::VSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10226 { 29443 /* vsseg8e64.v */, RISCV::VSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10227 { 29455 /* vsseg8e8.v */, RISCV::VSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10228 { 29466 /* vssra.vi */, RISCV::VSSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10229 { 29475 /* vssra.vv */, RISCV::VSSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10230 { 29484 /* vssra.vx */, RISCV::VSSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10231 { 29493 /* vssrl.vi */, RISCV::VSSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10232 { 29502 /* vssrl.vv */, RISCV::VSSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10233 { 29511 /* vssrl.vx */, RISCV::VSSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10234 { 29520 /* vssseg2e16.v */, RISCV::VSSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10235 { 29533 /* vssseg2e32.v */, RISCV::VSSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10236 { 29546 /* vssseg2e64.v */, RISCV::VSSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10237 { 29559 /* vssseg2e8.v */, RISCV::VSSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10238 { 29571 /* vssseg3e16.v */, RISCV::VSSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10239 { 29584 /* vssseg3e32.v */, RISCV::VSSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10240 { 29597 /* vssseg3e64.v */, RISCV::VSSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10241 { 29610 /* vssseg3e8.v */, RISCV::VSSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10242 { 29622 /* vssseg4e16.v */, RISCV::VSSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10243 { 29635 /* vssseg4e32.v */, RISCV::VSSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10244 { 29648 /* vssseg4e64.v */, RISCV::VSSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10245 { 29661 /* vssseg4e8.v */, RISCV::VSSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10246 { 29673 /* vssseg5e16.v */, RISCV::VSSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10247 { 29686 /* vssseg5e32.v */, RISCV::VSSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10248 { 29699 /* vssseg5e64.v */, RISCV::VSSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10249 { 29712 /* vssseg5e8.v */, RISCV::VSSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10250 { 29724 /* vssseg6e16.v */, RISCV::VSSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10251 { 29737 /* vssseg6e32.v */, RISCV::VSSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10252 { 29750 /* vssseg6e64.v */, RISCV::VSSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10253 { 29763 /* vssseg6e8.v */, RISCV::VSSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10254 { 29775 /* vssseg7e16.v */, RISCV::VSSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10255 { 29788 /* vssseg7e32.v */, RISCV::VSSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10256 { 29801 /* vssseg7e64.v */, RISCV::VSSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10257 { 29814 /* vssseg7e8.v */, RISCV::VSSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10258 { 29826 /* vssseg8e16.v */, RISCV::VSSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10259 { 29839 /* vssseg8e32.v */, RISCV::VSSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10260 { 29852 /* vssseg8e64.v */, RISCV::VSSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10261 { 29865 /* vssseg8e8.v */, RISCV::VSSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10262 { 29877 /* vssub.vv */, RISCV::VSSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10263 { 29886 /* vssub.vx */, RISCV::VSSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10264 { 29895 /* vssubu.vv */, RISCV::VSSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10265 { 29905 /* vssubu.vx */, RISCV::VSSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10266 { 29915 /* vsub.vv */, RISCV::VSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10267 { 29923 /* vsub.vx */, RISCV::VSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10268 { 29931 /* vsuxei16.v */, RISCV::VSUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10269 { 29942 /* vsuxei32.v */, RISCV::VSUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10270 { 29953 /* vsuxei64.v */, RISCV::VSUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10271 { 29964 /* vsuxei8.v */, RISCV::VSUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10272 { 29974 /* vsuxseg2ei16.v */, RISCV::VSUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10273 { 29989 /* vsuxseg2ei32.v */, RISCV::VSUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10274 { 30004 /* vsuxseg2ei64.v */, RISCV::VSUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10275 { 30019 /* vsuxseg2ei8.v */, RISCV::VSUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10276 { 30033 /* vsuxseg3ei16.v */, RISCV::VSUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10277 { 30048 /* vsuxseg3ei32.v */, RISCV::VSUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10278 { 30063 /* vsuxseg3ei64.v */, RISCV::VSUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10279 { 30078 /* vsuxseg3ei8.v */, RISCV::VSUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10280 { 30092 /* vsuxseg4ei16.v */, RISCV::VSUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10281 { 30107 /* vsuxseg4ei32.v */, RISCV::VSUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10282 { 30122 /* vsuxseg4ei64.v */, RISCV::VSUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10283 { 30137 /* vsuxseg4ei8.v */, RISCV::VSUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10284 { 30151 /* vsuxseg5ei16.v */, RISCV::VSUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10285 { 30166 /* vsuxseg5ei32.v */, RISCV::VSUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10286 { 30181 /* vsuxseg5ei64.v */, RISCV::VSUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10287 { 30196 /* vsuxseg5ei8.v */, RISCV::VSUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10288 { 30210 /* vsuxseg6ei16.v */, RISCV::VSUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10289 { 30225 /* vsuxseg6ei32.v */, RISCV::VSUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10290 { 30240 /* vsuxseg6ei64.v */, RISCV::VSUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10291 { 30255 /* vsuxseg6ei8.v */, RISCV::VSUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10292 { 30269 /* vsuxseg7ei16.v */, RISCV::VSUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10293 { 30284 /* vsuxseg7ei32.v */, RISCV::VSUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10294 { 30299 /* vsuxseg7ei64.v */, RISCV::VSUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10295 { 30314 /* vsuxseg7ei8.v */, RISCV::VSUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10296 { 30328 /* vsuxseg8ei16.v */, RISCV::VSUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10297 { 30343 /* vsuxseg8ei32.v */, RISCV::VSUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10298 { 30358 /* vsuxseg8ei64.v */, RISCV::VSUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10299 { 30373 /* vsuxseg8ei8.v */, RISCV::VSUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10300 { 30387 /* vt.maskc */, RISCV::VT_MASKC, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10301 { 30396 /* vt.maskcn */, RISCV::VT_MASKCN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10302 { 30406 /* vwadd.vv */, RISCV::VWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10303 { 30415 /* vwadd.vx */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10304 { 30424 /* vwadd.wv */, RISCV::VWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10305 { 30433 /* vwadd.wx */, RISCV::VWADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10306 { 30442 /* vwaddu.vv */, RISCV::VWADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10307 { 30452 /* vwaddu.vx */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10308 { 30462 /* vwaddu.wv */, RISCV::VWADDU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10309 { 30472 /* vwaddu.wx */, RISCV::VWADDU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10310 { 30482 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10311 { 30482 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10312 { 30494 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10313 { 30494 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10314 { 30507 /* vwmacc.vv */, RISCV::VWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10315 { 30517 /* vwmacc.vx */, RISCV::VWMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10316 { 30527 /* vwmaccsu.vv */, RISCV::VWMACCSU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10317 { 30539 /* vwmaccsu.vx */, RISCV::VWMACCSU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10318 { 30551 /* vwmaccu.vv */, RISCV::VWMACCU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10319 { 30562 /* vwmaccu.vx */, RISCV::VWMACCU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10320 { 30573 /* vwmaccus.vx */, RISCV::VWMACCUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10321 { 30585 /* vwmul.vv */, RISCV::VWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10322 { 30594 /* vwmul.vx */, RISCV::VWMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10323 { 30603 /* vwmulsu.vv */, RISCV::VWMULSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10324 { 30614 /* vwmulsu.vx */, RISCV::VWMULSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10325 { 30625 /* vwmulu.vv */, RISCV::VWMULU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10326 { 30635 /* vwmulu.vx */, RISCV::VWMULU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10327 { 30645 /* vwredsum.vs */, RISCV::VWREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10328 { 30657 /* vwredsumu.vs */, RISCV::VWREDSUMU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10329 { 30670 /* vwsll.vi */, RISCV::VWSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10330 { 30679 /* vwsll.vv */, RISCV::VWSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10331 { 30688 /* vwsll.vx */, RISCV::VWSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10332 { 30697 /* vwsub.vv */, RISCV::VWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10333 { 30706 /* vwsub.vx */, RISCV::VWSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10334 { 30715 /* vwsub.wv */, RISCV::VWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10335 { 30724 /* vwsub.wx */, RISCV::VWSUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10336 { 30733 /* vwsubu.vv */, RISCV::VWSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10337 { 30743 /* vwsubu.vx */, RISCV::VWSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10338 { 30753 /* vwsubu.wv */, RISCV::VWSUBU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10339 { 30763 /* vwsubu.wx */, RISCV::VWSUBU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10340 { 30773 /* vxor.vi */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10341 { 30781 /* vxor.vv */, RISCV::VXOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10342 { 30789 /* vxor.vx */, RISCV::VXOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10343 { 30797 /* vzext.vf2 */, RISCV::VZEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10344 { 30807 /* vzext.vf4 */, RISCV::VZEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10345 { 30817 /* vzext.vf8 */, RISCV::VZEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10346 { 30827 /* wadd */, RISCV::WADD, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10347 { 30832 /* wadda */, RISCV::WADDA, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10348 { 30838 /* waddau */, RISCV::WADDAU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10349 { 30845 /* waddu */, RISCV::WADDU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10350 { 30851 /* wfi */, RISCV::WFI, Convert_NoOperands, AMFBS_None, { }, },
10351 { 30855 /* wmacc */, RISCV::WMACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10352 { 30861 /* wmaccsu */, RISCV::WMACCSU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10353 { 30869 /* wmaccu */, RISCV::WMACCU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10354 { 30876 /* wmul */, RISCV::WMUL, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10355 { 30881 /* wmulsu */, RISCV::WMULSU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10356 { 30888 /* wmulu */, RISCV::WMULU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10357 { 30894 /* wrs.nto */, RISCV::WRS_NTO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
10358 { 30902 /* wrs.sto */, RISCV::WRS_STO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
10359 { 30910 /* wsla */, RISCV::WSLA, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10360 { 30915 /* wslai */, RISCV::WSLAI, Convert__GPRPairRV321_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm6 }, },
10361 { 30921 /* wsll */, RISCV::WSLL, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10362 { 30926 /* wslli */, RISCV::WSLLI, Convert__GPRPairRV321_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm6 }, },
10363 { 30932 /* wsub */, RISCV::WSUB, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10364 { 30937 /* wsuba */, RISCV::WSUBA, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10365 { 30943 /* wsubau */, RISCV::WSUBAU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10366 { 30950 /* wsubu */, RISCV::WSUBU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10367 { 30956 /* wzip16p */, RISCV::WZIP16P, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10368 { 30964 /* wzip8p */, RISCV::WZIP8P, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10369 { 30971 /* xnor */, RISCV::XNOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10370 { 30976 /* xor */, RISCV::XOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10371 { 30976 /* xor */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10372 { 30980 /* xori */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10373 { 30985 /* xperm4 */, RISCV::XPERM4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10374 { 30992 /* xperm8 */, RISCV::XPERM8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10375 { 30999 /* zext.b */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__imm_95_255, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10376 { 31006 /* zext.h */, RISCV::PACK, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZbkbOrP_NoStdExtZbb_IsRV32, { MCK_GPR, MCK_GPR }, },
10377 { 31006 /* zext.h */, RISCV::PACKW, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZbkb_NoStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
10378 { 31006 /* zext.h */, RISCV::ZEXT_H_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV32, { MCK_GPR, MCK_GPR }, },
10379 { 31006 /* zext.h */, RISCV::ZEXT_H_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
10380 { 31006 /* zext.h */, RISCV::PseudoZEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10381 { 31013 /* zext.w */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR }, },
10382 { 31013 /* zext.w */, RISCV::PseudoZEXT_W, Convert__Reg1_0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
10383 { 31020 /* zip */, RISCV::ZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
10384 { 31024 /* zip16hp */, RISCV::ZIP16HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10385 { 31032 /* zip16p */, RISCV::ZIP16P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10386 { 31039 /* zip8hp */, RISCV::ZIP8HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10387 { 31046 /* zip8p */, RISCV::ZIP8P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10388};
10389
10390#include "llvm/Support/Debug.h"
10391#include "llvm/Support/Format.h"
10392
10393unsigned RISCVAsmParser::
10394MatchInstructionImpl(const OperandVector &Operands,
10395 MCInst &Inst,
10396 uint64_t &ErrorInfo,
10397 FeatureBitset &MissingFeatures,
10398 bool matchingInlineAsm, unsigned VariantID) {
10399 // Eliminate obvious mismatches.
10400 if (Operands.size() > 9) {
10401 ErrorInfo = 9;
10402 return Match_InvalidOperand;
10403 }
10404
10405 // Get the current feature set.
10406 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
10407
10408 // Get the instruction mnemonic, which is the first token.
10409 StringRef Mnemonic = ((RISCVOperand &)*Operands[0]).getToken();
10410
10411 // Process all MnemonicAliases to remap the mnemonic.
10412 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
10413
10414 // Some state to try to produce better error messages.
10415 bool HadMatchOtherThanFeatures = false;
10416 bool HadMatchOtherThanPredicate = false;
10417 unsigned RetCode = Match_InvalidOperand;
10418 MissingFeatures.set();
10419 // Set ErrorInfo to the operand that mismatches if it is
10420 // wrong for all instances of the instruction.
10421 ErrorInfo = ~0ULL;
10422 SmallBitVector OptionalOperandsMask(9);
10423 // Find the appropriate table for this asm variant.
10424 const MatchEntry *Start, *End;
10425 switch (VariantID) {
10426 default: llvm_unreachable("invalid variant!");
10427 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
10428 }
10429 // Search the table.
10430 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
10431
10432 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
10433 std::distance(MnemonicRange.first, MnemonicRange.second) <<
10434 " encodings with mnemonic '" << Mnemonic << "'\n");
10435
10436 // Return a more specific error code if no mnemonics match.
10437 if (MnemonicRange.first == MnemonicRange.second)
10438 return Match_MnemonicFail;
10439
10440 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
10441 it != ie; ++it) {
10442 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
10443 bool HasRequiredFeatures =
10444 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
10445 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
10446 << MII.getName(it->Opcode) << "\n");
10447 // equal_range guarantees that instruction mnemonic matches.
10448 assert(Mnemonic == it->getMnemonic());
10449 bool OperandsValid = true;
10450 OptionalOperandsMask.reset(0, 9);
10451 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx) {
10452 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
10453 DEBUG_WITH_TYPE("asm-matcher",
10454 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
10455 << " against actual operand at index " << ActualIdx);
10456 if (ActualIdx < Operands.size())
10457 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
10458 Operands[ActualIdx]->print(dbgs(), *getContext().getAsmInfo()); dbgs() << "): ");
10459 else
10460 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
10461 if (ActualIdx >= Operands.size()) {
10462 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
10463 if (Formal == InvalidMatchClass) {
10464 OptionalOperandsMask.set(FormalIdx + 1, 9);
10465 break;
10466 }
10467 if (isSubclass(Formal, OptionalMatchClass)) {
10468 OptionalOperandsMask.set(FormalIdx + 1);
10469 continue;
10470 }
10471 OperandsValid = false;
10472 ErrorInfo = ActualIdx;
10473 break;
10474 }
10475 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
10476 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
10477 if (Diag == Match_Success) {
10478 DEBUG_WITH_TYPE("asm-matcher",
10479 dbgs() << "match success using generic matcher\n");
10480 ++ActualIdx;
10481 continue;
10482 }
10483 // If the generic handler indicates an invalid operand
10484 // failure, check for a special case.
10485 if (Diag != Match_Success) {
10486 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
10487 if (TargetDiag == Match_Success) {
10488 DEBUG_WITH_TYPE("asm-matcher",
10489 dbgs() << "match success using target matcher\n");
10490 ++ActualIdx;
10491 continue;
10492 }
10493 // If the target matcher returned a specific error code use
10494 // that, else use the one from the generic matcher.
10495 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
10496 Diag = TargetDiag;
10497 }
10498 // If current formal operand wasn't matched and it is optional
10499 // then try to match next formal operand
10500 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
10501 OptionalOperandsMask.set(FormalIdx + 1);
10502 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
10503 continue;
10504 }
10505 // If this operand is broken for all of the instances of this
10506 // mnemonic, keep track of it so we can report loc info.
10507 // If we already had a match that only failed due to a
10508 // target predicate, that diagnostic is preferred.
10509 if (!HadMatchOtherThanPredicate &&
10510 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
10511 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
10512 RetCode = Diag;
10513 ErrorInfo = ActualIdx;
10514 }
10515 // Otherwise, just reject this instance of the mnemonic.
10516 OperandsValid = false;
10517 break;
10518 }
10519
10520 if (!OperandsValid) {
10521 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
10522 "operand mismatches, ignoring "
10523 "this opcode\n");
10524 continue;
10525 }
10526 if (!HasRequiredFeatures) {
10527 HadMatchOtherThanFeatures = true;
10528 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
10529 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
10530 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
10531 if (NewMissingFeatures[I])
10532 dbgs() << ' ' << I;
10533 dbgs() << "\n");
10534 if (NewMissingFeatures.count() <=
10535 MissingFeatures.count())
10536 MissingFeatures = NewMissingFeatures;
10537 continue;
10538 }
10539
10540 Inst.clear();
10541
10542 Inst.setOpcode(it->Opcode);
10543 // We have a potential match but have not rendered the operands.
10544 // Check the target predicate to handle any context sensitive
10545 // constraints.
10546 // For example, Ties that are referenced multiple times must be
10547 // checked here to ensure the input is the same for each match
10548 // constraints. If we leave it any later the ties will have been
10549 // canonicalized
10550 unsigned MatchResult;
10551 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
10552 Inst.clear();
10553 DEBUG_WITH_TYPE(
10554 "asm-matcher",
10555 dbgs() << "Early target match predicate failed with diag code "
10556 << MatchResult << "\n");
10557 RetCode = MatchResult;
10558 HadMatchOtherThanPredicate = true;
10559 continue;
10560 }
10561
10562 unsigned DefaultsOffset[9] = { 0 };
10563 assert(OptionalOperandsMask.size() == 9);
10564 for (unsigned i = 0, NumDefaults = 0; i < 8; ++i) {
10565 NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
10566 DefaultsOffset[i + 1] = NumDefaults;
10567 }
10568
10569 if (matchingInlineAsm) {
10570 convertToMapAndConstraints(it->ConvertFn, Operands);
10571 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
10572 DefaultsOffset, ErrorInfo))
10573 return Match_InvalidTiedOperand;
10574
10575 return Match_Success;
10576 }
10577
10578 // We have selected a definite instruction, convert the parsed
10579 // operands into the appropriate MCInst.
10580 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,
10581 OptionalOperandsMask, DefaultsOffset);
10582
10583 // We have a potential match. Check the target predicate to
10584 // handle any context sensitive constraints.
10585 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
10586 DEBUG_WITH_TYPE("asm-matcher",
10587 dbgs() << "Target match predicate failed with diag code "
10588 << MatchResult << "\n");
10589 Inst.clear();
10590 RetCode = MatchResult;
10591 HadMatchOtherThanPredicate = true;
10592 continue;
10593 }
10594
10595 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
10596 DefaultsOffset, ErrorInfo))
10597 return Match_InvalidTiedOperand;
10598
10599 DEBUG_WITH_TYPE(
10600 "asm-matcher",
10601 dbgs() << "Opcode result: complete match, selecting this opcode\n");
10602 return Match_Success;
10603 }
10604
10605 // Okay, we had no match. Try to return a useful error code.
10606 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
10607 return RetCode;
10608
10609 ErrorInfo = 0;
10610 return Match_MissingFeature;
10611}
10612
10613namespace {
10614 struct OperandMatchEntry {
10615 uint16_t Mnemonic;
10616 uint8_t OperandMask;
10617 uint16_t Class;
10618 uint8_t RequiredFeaturesIdx;
10619
10620 StringRef getMnemonic() const {
10621 return StringRef(MnemonicTable + Mnemonic + 1,
10622 MnemonicTable[Mnemonic]);
10623 }
10624 };
10625
10626 // Predicate for searching for an opcode.
10627 struct LessOpcodeOperand {
10628 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
10629 return LHS.getMnemonic() < RHS;
10630 }
10631 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
10632 return LHS < RHS.getMnemonic();
10633 }
10634 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
10635 return LHS.getMnemonic() < RHS.getMnemonic();
10636 }
10637 };
10638} // end anonymous namespace
10639
10640static const OperandMatchEntry OperandMatchTable[1987] = {
10641 /* Operand List Mnemonic, Mask, Operand Class, Features */
10642 { 0 /* .insn_b */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10643 { 8 /* .insn_ca */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10644 { 17 /* .insn_cb */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10645 { 26 /* .insn_ci */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10646 { 35 /* .insn_ciw */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10647 { 45 /* .insn_cj */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10648 { 54 /* .insn_cl */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10649 { 54 /* .insn_cl */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10650 { 63 /* .insn_cr */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10651 { 72 /* .insn_cs */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10652 { 72 /* .insn_cs */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10653 { 81 /* .insn_css */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
10654 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10655 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10656 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10657 { 99 /* .insn_j */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10658 { 99 /* .insn_j */, 4 /* 2 */, MCK_BareSImm21Lsb0, AMFBS_None },
10659 { 107 /* .insn_qc.eai */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
10660 { 120 /* .insn_qc.eb */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
10661 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
10662 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
10663 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
10664 { 144 /* .insn_qc.ej */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
10665 { 156 /* .insn_qc.es */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
10666 { 156 /* .insn_qc.es */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
10667 { 168 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10668 { 168 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10669 { 176 /* .insn_r4 */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10670 { 185 /* .insn_s */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10671 { 185 /* .insn_s */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10672 { 193 /* .insn_sb */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10673 { 202 /* .insn_u */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10674 { 210 /* .insn_uj */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
10675 { 210 /* .insn_uj */, 4 /* 2 */, MCK_BareSImm21Lsb0, AMFBS_None },
10676 { 239 /* add */, 8 /* 3 */, MCK_TPRelAddSymbol, AMFBS_None },
10677 { 250 /* addd */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
10678 { 370 /* aif.amoaddg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10679 { 384 /* aif.amoaddg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10680 { 398 /* aif.amoaddl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10681 { 412 /* aif.amoaddl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10682 { 426 /* aif.amoandg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10683 { 440 /* aif.amoandg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10684 { 454 /* aif.amoandl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10685 { 468 /* aif.amoandl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10686 { 482 /* aif.amocmpswapg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10687 { 500 /* aif.amocmpswapg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10688 { 518 /* aif.amocmpswapl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10689 { 536 /* aif.amocmpswapl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10690 { 554 /* aif.amomaxg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10691 { 568 /* aif.amomaxg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10692 { 582 /* aif.amomaxl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10693 { 596 /* aif.amomaxl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10694 { 610 /* aif.amomaxug.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10695 { 625 /* aif.amomaxug.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10696 { 640 /* aif.amomaxul.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10697 { 655 /* aif.amomaxul.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10698 { 670 /* aif.amoming.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10699 { 684 /* aif.amoming.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10700 { 698 /* aif.amominl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10701 { 712 /* aif.amominl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10702 { 726 /* aif.amominug.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10703 { 741 /* aif.amominug.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10704 { 756 /* aif.amominul.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10705 { 771 /* aif.amominul.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10706 { 786 /* aif.amoorg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10707 { 799 /* aif.amoorg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10708 { 812 /* aif.amoorl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10709 { 825 /* aif.amoorl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10710 { 838 /* aif.amoswapg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10711 { 853 /* aif.amoswapg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10712 { 868 /* aif.amoswapl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10713 { 883 /* aif.amoswapl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10714 { 898 /* aif.amoxorg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10715 { 912 /* aif.amoxorg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10716 { 926 /* aif.amoxorl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10717 { 940 /* aif.amoxorl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10718 { 1047 /* aif.fadd.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
10719 { 1072 /* aif.famoaddg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10720 { 1088 /* aif.famoaddl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10721 { 1104 /* aif.famoandg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10722 { 1120 /* aif.famoandl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10723 { 1136 /* aif.famomaxg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10724 { 1152 /* aif.famomaxg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10725 { 1168 /* aif.famomaxl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10726 { 1184 /* aif.famomaxl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10727 { 1200 /* aif.famomaxug.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10728 { 1217 /* aif.famomaxul.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10729 { 1234 /* aif.famoming.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10730 { 1250 /* aif.famoming.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10731 { 1266 /* aif.famominl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10732 { 1282 /* aif.famominl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10733 { 1298 /* aif.famominug.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10734 { 1315 /* aif.famominul.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10735 { 1332 /* aif.famoorg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10736 { 1347 /* aif.famoorl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10737 { 1362 /* aif.famoswapg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10738 { 1379 /* aif.famoswapl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10739 { 1396 /* aif.famoxorg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10740 { 1412 /* aif.famoxorl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10741 { 1637 /* aif.fcvt.ps.pw */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
10742 { 1652 /* aif.fcvt.ps.pwu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
10743 { 1801 /* aif.fcvt.pw.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
10744 { 1816 /* aif.fcvt.pwu.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
10745 { 1977 /* aif.fdiv.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
10746 { 2060 /* aif.fg32b.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10747 { 2073 /* aif.fg32h.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10748 { 2086 /* aif.fg32w.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10749 { 2099 /* aif.fgb.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10750 { 2110 /* aif.fgbg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10751 { 2122 /* aif.fgbl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10752 { 2134 /* aif.fgh.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10753 { 2145 /* aif.fghg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10754 { 2157 /* aif.fghl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10755 { 2169 /* aif.fgw.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10756 { 2180 /* aif.fgwg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10757 { 2192 /* aif.fgwl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10758 { 2352 /* aif.fmadd.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
10759 { 2439 /* aif.fmsub.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
10760 { 2464 /* aif.fmul.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
10761 { 2531 /* aif.fnmadd.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
10762 { 2545 /* aif.fnmsub.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
10763 { 2671 /* aif.fround.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
10764 { 2724 /* aif.fsc32b.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10765 { 2738 /* aif.fsc32h.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10766 { 2752 /* aif.fsc32w.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10767 { 2766 /* aif.fscb.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10768 { 2778 /* aif.fscbg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10769 { 2791 /* aif.fscbl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10770 { 2804 /* aif.fsch.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10771 { 2816 /* aif.fschg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10772 { 2829 /* aif.fschl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10773 { 2842 /* aif.fscw.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10774 { 2854 /* aif.fscwg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10775 { 2867 /* aif.fscwl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10776 { 3055 /* aif.fsub.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
10777 { 3268 /* aif.sbg */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10778 { 3276 /* aif.sbl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10779 { 3284 /* aif.shg */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10780 { 3292 /* aif.shl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
10781 { 3300 /* amoadd.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10782 { 3309 /* amoadd.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10783 { 3321 /* amoadd.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10784 { 3335 /* amoadd.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10785 { 3347 /* amoadd.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10786 { 3356 /* amoadd.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10787 { 3368 /* amoadd.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10788 { 3382 /* amoadd.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10789 { 3394 /* amoadd.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10790 { 3403 /* amoadd.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10791 { 3415 /* amoadd.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10792 { 3429 /* amoadd.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10793 { 3441 /* amoadd.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10794 { 3450 /* amoadd.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10795 { 3462 /* amoadd.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10796 { 3476 /* amoadd.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10797 { 3488 /* amoand.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10798 { 3497 /* amoand.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10799 { 3509 /* amoand.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10800 { 3523 /* amoand.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10801 { 3535 /* amoand.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10802 { 3544 /* amoand.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10803 { 3556 /* amoand.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10804 { 3570 /* amoand.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10805 { 3582 /* amoand.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10806 { 3591 /* amoand.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10807 { 3603 /* amoand.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10808 { 3617 /* amoand.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10809 { 3629 /* amoand.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10810 { 3638 /* amoand.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10811 { 3650 /* amoand.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10812 { 3664 /* amoand.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10813 { 3676 /* amocas.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
10814 { 3685 /* amocas.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
10815 { 3697 /* amocas.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
10816 { 3711 /* amocas.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
10817 { 3723 /* amocas.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
10818 { 3723 /* amocas.d */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
10819 { 3723 /* amocas.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
10820 { 3732 /* amocas.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
10821 { 3732 /* amocas.d.aq */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
10822 { 3732 /* amocas.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
10823 { 3744 /* amocas.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
10824 { 3744 /* amocas.d.aqrl */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
10825 { 3744 /* amocas.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
10826 { 3758 /* amocas.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
10827 { 3758 /* amocas.d.rl */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
10828 { 3758 /* amocas.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
10829 { 3770 /* amocas.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
10830 { 3779 /* amocas.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
10831 { 3791 /* amocas.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
10832 { 3805 /* amocas.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
10833 { 3817 /* amocas.q */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
10834 { 3817 /* amocas.q */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
10835 { 3826 /* amocas.q.aq */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
10836 { 3826 /* amocas.q.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
10837 { 3838 /* amocas.q.aqrl */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
10838 { 3838 /* amocas.q.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
10839 { 3852 /* amocas.q.rl */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
10840 { 3852 /* amocas.q.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
10841 { 3864 /* amocas.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
10842 { 3873 /* amocas.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
10843 { 3885 /* amocas.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
10844 { 3899 /* amocas.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
10845 { 3911 /* amomax.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10846 { 3920 /* amomax.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10847 { 3932 /* amomax.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10848 { 3946 /* amomax.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10849 { 3958 /* amomax.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10850 { 3967 /* amomax.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10851 { 3979 /* amomax.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10852 { 3993 /* amomax.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10853 { 4005 /* amomax.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10854 { 4014 /* amomax.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10855 { 4026 /* amomax.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10856 { 4040 /* amomax.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10857 { 4052 /* amomax.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10858 { 4061 /* amomax.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10859 { 4073 /* amomax.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10860 { 4087 /* amomax.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10861 { 4099 /* amomaxu.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10862 { 4109 /* amomaxu.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10863 { 4122 /* amomaxu.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10864 { 4137 /* amomaxu.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10865 { 4150 /* amomaxu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10866 { 4160 /* amomaxu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10867 { 4173 /* amomaxu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10868 { 4188 /* amomaxu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10869 { 4201 /* amomaxu.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10870 { 4211 /* amomaxu.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10871 { 4224 /* amomaxu.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10872 { 4239 /* amomaxu.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10873 { 4252 /* amomaxu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10874 { 4262 /* amomaxu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10875 { 4275 /* amomaxu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10876 { 4290 /* amomaxu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10877 { 4303 /* amomin.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10878 { 4312 /* amomin.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10879 { 4324 /* amomin.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10880 { 4338 /* amomin.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10881 { 4350 /* amomin.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10882 { 4359 /* amomin.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10883 { 4371 /* amomin.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10884 { 4385 /* amomin.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10885 { 4397 /* amomin.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10886 { 4406 /* amomin.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10887 { 4418 /* amomin.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10888 { 4432 /* amomin.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10889 { 4444 /* amomin.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10890 { 4453 /* amomin.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10891 { 4465 /* amomin.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10892 { 4479 /* amomin.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10893 { 4491 /* amominu.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10894 { 4501 /* amominu.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10895 { 4514 /* amominu.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10896 { 4529 /* amominu.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10897 { 4542 /* amominu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10898 { 4552 /* amominu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10899 { 4565 /* amominu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10900 { 4580 /* amominu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10901 { 4593 /* amominu.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10902 { 4603 /* amominu.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10903 { 4616 /* amominu.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10904 { 4631 /* amominu.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10905 { 4644 /* amominu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10906 { 4654 /* amominu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10907 { 4667 /* amominu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10908 { 4682 /* amominu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10909 { 4695 /* amoor.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10910 { 4703 /* amoor.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10911 { 4714 /* amoor.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10912 { 4727 /* amoor.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10913 { 4738 /* amoor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10914 { 4746 /* amoor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10915 { 4757 /* amoor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10916 { 4770 /* amoor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10917 { 4781 /* amoor.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10918 { 4789 /* amoor.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10919 { 4800 /* amoor.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10920 { 4813 /* amoor.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10921 { 4824 /* amoor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10922 { 4832 /* amoor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10923 { 4843 /* amoor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10924 { 4856 /* amoor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10925 { 4867 /* amoswap.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10926 { 4877 /* amoswap.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10927 { 4890 /* amoswap.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10928 { 4905 /* amoswap.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10929 { 4918 /* amoswap.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10930 { 4928 /* amoswap.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10931 { 4941 /* amoswap.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10932 { 4956 /* amoswap.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10933 { 4969 /* amoswap.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10934 { 4979 /* amoswap.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10935 { 4992 /* amoswap.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10936 { 5007 /* amoswap.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10937 { 5020 /* amoswap.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10938 { 5030 /* amoswap.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10939 { 5043 /* amoswap.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10940 { 5058 /* amoswap.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10941 { 5071 /* amoxor.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10942 { 5080 /* amoxor.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10943 { 5092 /* amoxor.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10944 { 5106 /* amoxor.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10945 { 5118 /* amoxor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10946 { 5127 /* amoxor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10947 { 5139 /* amoxor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10948 { 5153 /* amoxor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
10949 { 5165 /* amoxor.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10950 { 5174 /* amoxor.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10951 { 5186 /* amoxor.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10952 { 5200 /* amoxor.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
10953 { 5212 /* amoxor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10954 { 5221 /* amoxor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10955 { 5233 /* amoxor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10956 { 5247 /* amoxor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
10957 { 5594 /* c.ld */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
10958 { 5594 /* c.ld */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
10959 { 5599 /* c.ldsp */, 1 /* 0 */, MCK_GPRPairNoX0RV32, AMFBS_HasStdExtZclsd_IsRV32 },
10960 { 5599 /* c.ldsp */, 1 /* 0 */, MCK_GPRPairNoX0RV32, AMFBS_HasStdExtZclsd_IsRV32 },
10961 { 5779 /* c.sd */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
10962 { 5779 /* c.sd */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
10963 { 5784 /* c.sdsp */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZclsd_IsRV32 },
10964 { 5784 /* c.sdsp */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZclsd_IsRV32 },
10965 { 5948 /* call */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
10966 { 5948 /* call */, 2 /* 1 */, MCK_CallSymbol, AMFBS_None },
10967 { 5953 /* cbo.clean */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
10968 { 5963 /* cbo.flush */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
10969 { 5973 /* cbo.inval */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
10970 { 5983 /* cbo.zero */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicboz },
10971 { 6064 /* cm.pop */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
10972 { 6064 /* cm.pop */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
10973 { 6071 /* cm.popret */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
10974 { 6071 /* cm.popret */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
10975 { 6081 /* cm.popretz */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
10976 { 6081 /* cm.popretz */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
10977 { 6092 /* cm.push */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasStdExtZcmp },
10978 { 6092 /* cm.push */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
10979 { 6111 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
10980 { 6111 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
10981 { 6116 /* csrci */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
10982 { 6122 /* csrr */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10983 { 6127 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10984 { 6127 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10985 { 6133 /* csrrci */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10986 { 6140 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10987 { 6140 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10988 { 6146 /* csrrsi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10989 { 6153 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10990 { 6153 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10991 { 6159 /* csrrwi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
10992 { 6166 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
10993 { 6166 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
10994 { 6171 /* csrsi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
10995 { 6177 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
10996 { 6177 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
10997 { 6182 /* csrwi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
10998 { 7942 /* cv.elw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXCVelw_IsRV32 },
10999 { 8146 /* cv.lb */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11000 { 8152 /* cv.lbu */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11001 { 8159 /* cv.lh */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11002 { 8165 /* cv.lhu */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11003 { 8172 /* cv.lw */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11004 { 8821 /* cv.sb */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11005 { 9091 /* cv.sh */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11006 { 9706 /* cv.sw */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11007 { 9838 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11008 { 9838 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11009 { 9845 /* fabs.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11010 { 9859 /* fabs.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11011 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11012 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11013 { 9866 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11014 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11015 { 9866 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11016 { 9873 /* fadd.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11017 { 9873 /* fadd.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11018 { 9873 /* fadd.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11019 { 9880 /* fadd.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11020 { 9887 /* fadd.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11021 { 9887 /* fadd.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11022 { 9887 /* fadd.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11023 { 9894 /* fclass.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11024 { 9894 /* fclass.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11025 { 9903 /* fclass.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11026 { 9921 /* fclass.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11027 { 9930 /* fcvt.bf16.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfbfmin },
11028 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin_HasStdExtD },
11029 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11030 { 9942 /* fcvt.d.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11031 { 9942 /* fcvt.d.h */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11032 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11033 { 9942 /* fcvt.d.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11034 { 9942 /* fcvt.d.h */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11035 { 9951 /* fcvt.d.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11036 { 9951 /* fcvt.d.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11037 { 9951 /* fcvt.d.l */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11038 { 9960 /* fcvt.d.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11039 { 9960 /* fcvt.d.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11040 { 9960 /* fcvt.d.lu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11041 { 9970 /* fcvt.d.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11042 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
11043 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
11044 { 9979 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
11045 { 9979 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11046 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
11047 { 9979 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
11048 { 9979 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11049 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
11050 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
11051 { 9988 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11052 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
11053 { 9988 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11054 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
11055 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
11056 { 9997 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11057 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
11058 { 9997 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11059 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfhmin_HasStdExtD },
11060 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11061 { 10007 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11062 { 10007 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11063 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11064 { 10007 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11065 { 10007 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11066 { 10016 /* fcvt.h.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11067 { 10016 /* fcvt.h.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11068 { 10016 /* fcvt.h.l */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11069 { 10025 /* fcvt.h.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11070 { 10025 /* fcvt.h.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11071 { 10025 /* fcvt.h.lu */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11072 { 10035 /* fcvt.h.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfhmin },
11073 { 10035 /* fcvt.h.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin },
11074 { 10035 /* fcvt.h.s */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
11075 { 10035 /* fcvt.h.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
11076 { 10044 /* fcvt.h.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11077 { 10044 /* fcvt.h.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11078 { 10044 /* fcvt.h.w */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11079 { 10053 /* fcvt.h.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11080 { 10053 /* fcvt.h.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11081 { 10053 /* fcvt.h.wu */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11082 { 10063 /* fcvt.l.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11083 { 10063 /* fcvt.l.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11084 { 10063 /* fcvt.l.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11085 { 10072 /* fcvt.l.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11086 { 10072 /* fcvt.l.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11087 { 10072 /* fcvt.l.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11088 { 10081 /* fcvt.l.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ_IsRV64 },
11089 { 10090 /* fcvt.l.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11090 { 10090 /* fcvt.l.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11091 { 10090 /* fcvt.l.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11092 { 10099 /* fcvt.lu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11093 { 10099 /* fcvt.lu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11094 { 10099 /* fcvt.lu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11095 { 10109 /* fcvt.lu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11096 { 10109 /* fcvt.lu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11097 { 10109 /* fcvt.lu.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11098 { 10119 /* fcvt.lu.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ_IsRV64 },
11099 { 10129 /* fcvt.lu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11100 { 10129 /* fcvt.lu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11101 { 10129 /* fcvt.lu.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11102 { 10139 /* fcvt.q.d */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11103 { 10148 /* fcvt.q.l */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ_IsRV64 },
11104 { 10157 /* fcvt.q.lu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ_IsRV64 },
11105 { 10167 /* fcvt.q.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11106 { 10176 /* fcvt.q.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11107 { 10185 /* fcvt.q.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11108 { 10195 /* fcvt.s.bf16 */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfbfmin },
11109 { 10207 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11110 { 10207 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11111 { 10207 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
11112 { 10207 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11113 { 10207 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11114 { 10207 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
11115 { 10207 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11116 { 10216 /* fcvt.s.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin },
11117 { 10216 /* fcvt.s.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin },
11118 { 10216 /* fcvt.s.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
11119 { 10216 /* fcvt.s.h */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
11120 { 10225 /* fcvt.s.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11121 { 10225 /* fcvt.s.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11122 { 10225 /* fcvt.s.l */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11123 { 10234 /* fcvt.s.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11124 { 10234 /* fcvt.s.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11125 { 10234 /* fcvt.s.lu */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11126 { 10244 /* fcvt.s.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11127 { 10253 /* fcvt.s.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11128 { 10253 /* fcvt.s.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11129 { 10253 /* fcvt.s.w */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11130 { 10262 /* fcvt.s.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11131 { 10262 /* fcvt.s.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11132 { 10262 /* fcvt.s.wu */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11133 { 10272 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11134 { 10272 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11135 { 10272 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11136 { 10272 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11137 { 10272 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11138 { 10281 /* fcvt.w.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11139 { 10281 /* fcvt.w.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11140 { 10281 /* fcvt.w.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11141 { 10290 /* fcvt.w.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11142 { 10299 /* fcvt.w.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11143 { 10299 /* fcvt.w.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11144 { 10299 /* fcvt.w.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11145 { 10308 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11146 { 10308 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11147 { 10308 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11148 { 10308 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11149 { 10308 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11150 { 10318 /* fcvt.wu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11151 { 10318 /* fcvt.wu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11152 { 10318 /* fcvt.wu.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11153 { 10328 /* fcvt.wu.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11154 { 10338 /* fcvt.wu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11155 { 10338 /* fcvt.wu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11156 { 10338 /* fcvt.wu.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11157 { 10348 /* fcvtmod.w.d */, 4 /* 2 */, MCK_RTZArg, AMFBS_HasStdExtZfa_HasStdExtD },
11158 { 10360 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11159 { 10360 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11160 { 10360 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11161 { 10360 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11162 { 10360 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11163 { 10367 /* fdiv.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11164 { 10367 /* fdiv.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11165 { 10367 /* fdiv.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11166 { 10374 /* fdiv.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11167 { 10381 /* fdiv.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11168 { 10381 /* fdiv.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11169 { 10381 /* fdiv.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11170 { 10388 /* fence */, 3 /* 0, 1 */, MCK_FenceArg, AMFBS_None },
11171 { 10412 /* feq.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11172 { 10412 /* feq.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11173 { 10418 /* feq.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11174 { 10430 /* feq.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11175 { 10436 /* fge.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11176 { 10436 /* fge.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11177 { 10442 /* fge.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11178 { 10454 /* fge.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11179 { 10488 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11180 { 10488 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11181 { 10494 /* fgt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11182 { 10506 /* fgt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11183 { 10540 /* fld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
11184 { 10544 /* fle.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11185 { 10544 /* fle.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11186 { 10550 /* fle.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11187 { 10562 /* fle.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11188 { 10596 /* flh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasHalfFPLoadStoreMove },
11189 { 10600 /* fli.d */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtD },
11190 { 10606 /* fli.h */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh },
11191 { 10612 /* fli.q */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtQ },
11192 { 10618 /* fli.s */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa },
11193 { 10624 /* flq */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtQ },
11194 { 10628 /* flt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11195 { 10628 /* flt.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11196 { 10634 /* flt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11197 { 10646 /* flt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11198 { 10680 /* flw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
11199 { 10684 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11200 { 10684 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11201 { 10684 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11202 { 10684 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11203 { 10684 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11204 { 10692 /* fmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11205 { 10692 /* fmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11206 { 10692 /* fmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11207 { 10700 /* fmadd.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11208 { 10708 /* fmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11209 { 10708 /* fmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11210 { 10708 /* fmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11211 { 10716 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11212 { 10716 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11213 { 10723 /* fmax.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11214 { 10737 /* fmax.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11215 { 10776 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11216 { 10776 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11217 { 10783 /* fmin.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11218 { 10797 /* fmin.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11219 { 10836 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11220 { 10836 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11221 { 10836 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11222 { 10836 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11223 { 10836 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11224 { 10844 /* fmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11225 { 10844 /* fmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11226 { 10844 /* fmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11227 { 10852 /* fmsub.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11228 { 10860 /* fmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11229 { 10860 /* fmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11230 { 10860 /* fmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11231 { 10868 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11232 { 10868 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11233 { 10868 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11234 { 10868 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11235 { 10868 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11236 { 10875 /* fmul.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11237 { 10875 /* fmul.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11238 { 10875 /* fmul.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11239 { 10882 /* fmul.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11240 { 10889 /* fmul.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11241 { 10889 /* fmul.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11242 { 10889 /* fmul.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11243 { 10896 /* fmv.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11244 { 10896 /* fmv.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11245 { 10910 /* fmv.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11246 { 10930 /* fmv.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11247 { 11004 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11248 { 11004 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11249 { 11011 /* fneg.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11250 { 11025 /* fneg.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11251 { 11032 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11252 { 11032 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11253 { 11032 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11254 { 11032 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11255 { 11032 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11256 { 11041 /* fnmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11257 { 11041 /* fnmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11258 { 11041 /* fnmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11259 { 11050 /* fnmadd.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11260 { 11059 /* fnmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11261 { 11059 /* fnmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11262 { 11059 /* fnmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11263 { 11068 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11264 { 11068 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11265 { 11068 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11266 { 11068 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11267 { 11068 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11268 { 11077 /* fnmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11269 { 11077 /* fnmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11270 { 11077 /* fnmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11271 { 11086 /* fnmsub.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11272 { 11095 /* fnmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11273 { 11095 /* fnmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11274 { 11095 /* fnmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11275 { 11118 /* fround.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
11276 { 11127 /* fround.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
11277 { 11136 /* fround.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtQ },
11278 { 11145 /* fround.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa },
11279 { 11154 /* froundnx.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
11280 { 11165 /* froundnx.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
11281 { 11176 /* froundnx.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtQ },
11282 { 11187 /* froundnx.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa },
11283 { 11209 /* fsd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
11284 { 11230 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11285 { 11230 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11286 { 11238 /* fsgnj.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11287 { 11254 /* fsgnj.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11288 { 11262 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11289 { 11262 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11290 { 11271 /* fsgnjn.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11291 { 11289 /* fsgnjn.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11292 { 11298 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11293 { 11298 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11294 { 11307 /* fsgnjx.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11295 { 11325 /* fsgnjx.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11296 { 11334 /* fsh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasHalfFPLoadStoreMove },
11297 { 11338 /* fsq */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtQ },
11298 { 11342 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11299 { 11342 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11300 { 11342 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11301 { 11342 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11302 { 11342 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11303 { 11350 /* fsqrt.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11304 { 11350 /* fsqrt.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11305 { 11350 /* fsqrt.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11306 { 11358 /* fsqrt.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11307 { 11366 /* fsqrt.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11308 { 11366 /* fsqrt.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11309 { 11366 /* fsqrt.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11310 { 11385 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11311 { 11385 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11312 { 11385 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11313 { 11385 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11314 { 11385 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11315 { 11392 /* fsub.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11316 { 11392 /* fsub.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11317 { 11392 /* fsub.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11318 { 11399 /* fsub.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11319 { 11406 /* fsub.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11320 { 11406 /* fsub.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11321 { 11406 /* fsub.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11322 { 11413 /* fsw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
11323 { 11465 /* hlv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11324 { 11471 /* hlv.bu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11325 { 11478 /* hlv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
11326 { 11484 /* hlv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11327 { 11490 /* hlv.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11328 { 11497 /* hlv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11329 { 11503 /* hlv.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
11330 { 11510 /* hlvx.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11331 { 11518 /* hlvx.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11332 { 11526 /* hsv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11333 { 11532 /* hsv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
11334 { 11538 /* hsv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11335 { 11544 /* hsv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11336 { 11550 /* j */, 1 /* 0 */, MCK_BareSImm21Lsb0, AMFBS_None },
11337 { 11552 /* jal */, 1 /* 0 */, MCK_BareSImm21Lsb0, AMFBS_None },
11338 { 11552 /* jal */, 2 /* 1 */, MCK_BareSImm21Lsb0, AMFBS_None },
11339 { 11556 /* jalr */, 32 /* 5 */, MCK_TLSDESCCallSymbol, AMFBS_None },
11340 { 11564 /* jump */, 1 /* 0 */, MCK_PseudoJumpSymbol, AMFBS_None },
11341 { 11569 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11342 { 11572 /* la.tls.gd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11343 { 11582 /* la.tls.ie */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11344 { 11592 /* la.tlsdesc */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11345 { 11603 /* lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11346 { 11606 /* lb.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11347 { 11612 /* lb.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11348 { 11620 /* lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11349 { 11624 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
11350 { 11624 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZilsd_IsRV32 },
11351 { 11624 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
11352 { 11624 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
11353 { 11624 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
11354 { 11627 /* ld.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
11355 { 11633 /* ld.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
11356 { 11641 /* lga */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11357 { 11645 /* lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11358 { 11648 /* lh.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11359 { 11654 /* lh.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11360 { 11662 /* lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11361 { 11669 /* lla */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11362 { 11678 /* lr.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11363 { 11683 /* lr.d.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11364 { 11691 /* lr.d.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11365 { 11701 /* lr.d.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11366 { 11709 /* lr.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11367 { 11714 /* lr.w.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11368 { 11722 /* lr.w.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11369 { 11732 /* lr.w.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11370 { 11744 /* lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11371 { 11747 /* lw.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11372 { 11753 /* lw.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11373 { 11761 /* lwu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
11374 { 12600 /* mqrwacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11375 { 12608 /* mqwacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11376 { 12885 /* nclip */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11377 { 12891 /* nclipi */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11378 { 12898 /* nclipiu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11379 { 12906 /* nclipr */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11380 { 12913 /* nclipri */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11381 { 12921 /* nclipriu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11382 { 12930 /* nclipru */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11383 { 12938 /* nclipu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11384 { 13266 /* nds.vd4dots.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
11385 { 13281 /* nds.vd4dotsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
11386 { 13297 /* nds.vd4dotu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
11387 { 13330 /* nds.vfpmadb.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVPackFPH },
11388 { 13345 /* nds.vfpmadt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVPackFPH },
11389 { 13360 /* nds.vfwcvt.f.b.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
11390 { 13377 /* nds.vfwcvt.f.bu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
11391 { 13395 /* nds.vfwcvt.f.n.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
11392 { 13412 /* nds.vfwcvt.f.nu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
11393 { 13448 /* nds.vle4.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntH },
11394 { 13459 /* nds.vln8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
11395 { 13459 /* nds.vln8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
11396 { 13470 /* nds.vlnu8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
11397 { 13470 /* nds.vlnu8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
11398 { 13499 /* nsari */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11399 { 13505 /* nsra */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11400 { 13510 /* nsrai */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11401 { 13516 /* nsrar */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11402 { 13522 /* nsrl */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11403 { 13527 /* nsrli */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11404 { 13589 /* paadd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11405 { 13598 /* paadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11406 { 13607 /* paadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11407 { 13641 /* paaddu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11408 { 13651 /* paaddu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11409 { 13661 /* paaddu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11410 { 13705 /* paax.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11411 { 13721 /* pabd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11412 { 13729 /* pabd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11413 { 13775 /* pabdu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11414 { 13784 /* pabdu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11415 { 13833 /* padd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11416 { 13841 /* padd.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11417 { 13850 /* padd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11418 { 13858 /* padd.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11419 { 13867 /* padd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11420 { 13875 /* padd.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11421 { 13914 /* pas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11422 { 13936 /* pasa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11423 { 13969 /* pasub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11424 { 13978 /* pasub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11425 { 13987 /* pasub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11426 { 14021 /* pasubu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11427 { 14031 /* pasubu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11428 { 14041 /* pasubu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11429 { 14081 /* pli.db */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11430 { 14088 /* pli.dh */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11431 { 14107 /* plui.dh */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11432 { 14398 /* pm2wadd.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11433 { 14408 /* pm2wadd.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11434 { 14419 /* pm2wadda.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11435 { 14430 /* pm2wadda.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11436 { 14442 /* pm2waddasu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11437 { 14455 /* pm2waddau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11438 { 14467 /* pm2waddsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11439 { 14479 /* pm2waddu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11440 { 14490 /* pm2wsub.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11441 { 14500 /* pm2wsub.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11442 { 14511 /* pm2wsuba.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11443 { 14522 /* pm2wsuba.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11444 { 14770 /* pmax.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11445 { 14778 /* pmax.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11446 { 14786 /* pmax.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11447 { 14816 /* pmaxu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11448 { 14825 /* pmaxu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11449 { 14834 /* pmaxu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11450 { 15096 /* pmin.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11451 { 15104 /* pmin.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11452 { 15112 /* pmin.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11453 { 15142 /* pminu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11454 { 15151 /* pminu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11455 { 15160 /* pminu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11456 { 15354 /* pmqrwacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11457 { 15365 /* pmqwacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11458 { 15383 /* pmseq.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11459 { 15392 /* pmseq.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11460 { 15401 /* pmseq.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11461 { 15434 /* pmslt.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11462 { 15443 /* pmslt.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11463 { 15452 /* pmslt.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11464 { 15486 /* pmsltu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11465 { 15496 /* pmsltu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11466 { 15506 /* pmsltu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11467 { 15968 /* pnclip.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11468 { 15978 /* pnclip.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11469 { 15988 /* pnclipi.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11470 { 15998 /* pnclipi.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11471 { 16008 /* pnclipiu.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11472 { 16019 /* pnclipiu.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11473 { 16030 /* pnclipr.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11474 { 16041 /* pnclipr.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11475 { 16052 /* pnclipri.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11476 { 16063 /* pnclipri.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11477 { 16074 /* pnclipriu.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11478 { 16086 /* pnclipriu.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11479 { 16098 /* pnclipru.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11480 { 16110 /* pnclipru.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11481 { 16122 /* pnclipu.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11482 { 16133 /* pnclipu.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11483 { 16144 /* pnsari.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11484 { 16153 /* pnsari.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11485 { 16162 /* pnsra.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11486 { 16171 /* pnsra.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11487 { 16180 /* pnsrai.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11488 { 16189 /* pnsrai.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11489 { 16198 /* pnsrar.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11490 { 16208 /* pnsrar.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11491 { 16218 /* pnsrl.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11492 { 16227 /* pnsrl.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11493 { 16236 /* pnsrli.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11494 { 16245 /* pnsrli.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11495 { 16263 /* ppaire.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11496 { 16273 /* ppaire.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11497 { 16302 /* ppaireo.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11498 { 16313 /* ppaireo.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11499 { 16353 /* ppairo.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11500 { 16363 /* ppairo.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11501 { 16401 /* ppairoe.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11502 { 16412 /* ppairoe.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11503 { 16454 /* predsum.dbs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11504 { 16466 /* predsum.dhs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11505 { 16512 /* predsumu.dbs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11506 { 16525 /* predsumu.dhs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11507 { 16595 /* psa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11508 { 16625 /* psabs.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11509 { 16634 /* psabs.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11510 { 16659 /* psadd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11511 { 16668 /* psadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11512 { 16677 /* psadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11513 { 16711 /* psaddu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11514 { 16721 /* psaddu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11515 { 16731 /* psaddu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11516 { 16759 /* psas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11517 { 16784 /* psati.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11518 { 16793 /* psati.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11519 { 16818 /* psext.dh.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11520 { 16829 /* psext.dw.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11521 { 16840 /* psext.dw.h */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11522 { 16881 /* psh1add.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11523 { 16892 /* psh1add.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11524 { 16931 /* psll.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11525 { 16940 /* psll.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11526 { 16949 /* psll.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11527 { 16982 /* pslli.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11528 { 16991 /* pslli.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11529 { 17000 /* pslli.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11530 { 17033 /* psra.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11531 { 17042 /* psra.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11532 { 17051 /* psra.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11533 { 17084 /* psrai.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11534 { 17093 /* psrai.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11535 { 17102 /* psrai.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11536 { 17127 /* psrari.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11537 { 17137 /* psrari.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11538 { 17173 /* psrl.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11539 { 17182 /* psrl.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11540 { 17191 /* psrl.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11541 { 17224 /* psrli.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11542 { 17233 /* psrli.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11543 { 17242 /* psrli.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11544 { 17267 /* pssa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11545 { 17292 /* pssh1sadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11546 { 17305 /* pssh1sadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11547 { 17342 /* pssha.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11548 { 17352 /* pssha.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11549 { 17380 /* psshar.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11550 { 17391 /* psshar.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11551 { 17422 /* psslai.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11552 { 17432 /* psslai.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11553 { 17468 /* pssub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11554 { 17477 /* pssub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11555 { 17486 /* pssub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11556 { 17520 /* pssubu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11557 { 17530 /* pssubu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11558 { 17540 /* pssubu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11559 { 17575 /* psub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11560 { 17583 /* psub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11561 { 17591 /* psub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11562 { 17613 /* pusati.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11563 { 17623 /* pusati.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11564 { 17651 /* pwadd.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11565 { 17659 /* pwadd.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11566 { 17667 /* pwadda.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11567 { 17676 /* pwadda.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11568 { 17685 /* pwaddau.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11569 { 17695 /* pwaddau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11570 { 17705 /* pwaddu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11571 { 17714 /* pwaddu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11572 { 17723 /* pwmacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11573 { 17732 /* pwmaccsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11574 { 17743 /* pwmaccu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11575 { 17753 /* pwmul.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11576 { 17761 /* pwmul.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11577 { 17769 /* pwmulsu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11578 { 17779 /* pwmulsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11579 { 17789 /* pwmulu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11580 { 17798 /* pwmulu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11581 { 17807 /* pwsla.bs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11582 { 17816 /* pwsla.hs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11583 { 17825 /* pwslai.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11584 { 17834 /* pwslai.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11585 { 17843 /* pwsll.bs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11586 { 17852 /* pwsll.hs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11587 { 17861 /* pwslli.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11588 { 17870 /* pwslli.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11589 { 17879 /* pwsub.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11590 { 17887 /* pwsub.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11591 { 17895 /* pwsuba.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11592 { 17904 /* pwsuba.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11593 { 17913 /* pwsubau.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11594 { 17923 /* pwsubau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11595 { 17933 /* pwsubu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11596 { 17942 /* pwsubu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11597 { 18326 /* qc.cm.pop */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
11598 { 18326 /* qc.cm.pop */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
11599 { 18336 /* qc.cm.popret */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
11600 { 18336 /* qc.cm.popret */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
11601 { 18349 /* qc.cm.popretz */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
11602 { 18349 /* qc.cm.popretz */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
11603 { 18363 /* qc.cm.push */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasVendorXqccmp },
11604 { 18363 /* qc.cm.push */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
11605 { 18374 /* qc.cm.pushfp */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasVendorXqccmp },
11606 { 18374 /* qc.cm.pushfp */, 1 /* 0 */, MCK_RegListS0, AMFBS_HasVendorXqccmp },
11607 { 18561 /* qc.e.lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_IsRV32 },
11608 { 18569 /* qc.e.lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_IsRV32 },
11609 { 18578 /* qc.e.lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_IsRV32 },
11610 { 18586 /* qc.e.lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_IsRV32 },
11611 { 18595 /* qc.e.li */, 2 /* 1 */, MCK_BareSymbolQC_E_LI, AMFBS_HasVendorXqcili_IsRV32 },
11612 { 18603 /* qc.e.lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_IsRV32 },
11613 { 18630 /* qc.e.sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_IsRV32 },
11614 { 18638 /* qc.e.sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_IsRV32 },
11615 { 18646 /* qc.e.sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_IsRV32 },
11616 { 19764 /* ri.vunzip2a.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXRivosVizip },
11617 { 19779 /* ri.vunzip2b.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXRivosVizip },
11618 { 19805 /* ri.vzip2a.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXRivosVizip },
11619 { 19818 /* ri.vzip2b.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXRivosVizip },
11620 { 19831 /* ri.vzipeven.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXRivosVizip },
11621 { 19846 /* ri.vzipodd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXRivosVizip },
11622 { 19905 /* sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11623 { 19908 /* sb.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11624 { 19916 /* sb.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11625 { 19922 /* sc.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11626 { 19927 /* sc.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11627 { 19935 /* sc.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11628 { 19945 /* sc.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11629 { 19953 /* sc.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11630 { 19958 /* sc.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11631 { 19966 /* sc.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11632 { 19976 /* sc.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11633 { 19992 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
11634 { 19992 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZilsd_IsRV32 },
11635 { 19992 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
11636 { 19992 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
11637 { 19992 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
11638 { 19995 /* sd.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
11639 { 20003 /* sd.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
11640 { 20482 /* sf.vfexp.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfexpAny },
11641 { 20493 /* sf.vfexpa.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfexpa },
11642 { 20505 /* sf.vfnrclip.x.f.qf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
11643 { 20524 /* sf.vfnrclip.xu.f.qf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
11644 { 20561 /* sf.vlte16 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
11645 { 20571 /* sf.vlte32 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
11646 { 20581 /* sf.vlte64 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
11647 { 20591 /* sf.vlte8 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
11648 { 20768 /* sf.vsettnt */, 4 /* 2 */, MCK_XSfmmVType, AMFBS_HasVendorXSfmmbase },
11649 { 20779 /* sf.vste16 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
11650 { 20789 /* sf.vste32 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
11651 { 20799 /* sf.vste64 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
11652 { 20809 /* sf.vste8 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
11653 { 20923 /* sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11654 { 20926 /* sh.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11655 { 20934 /* sh.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11656 { 21520 /* ssamoswap.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
11657 { 21532 /* ssamoswap.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
11658 { 21547 /* ssamoswap.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
11659 { 21564 /* ssamoswap.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
11660 { 21579 /* ssamoswap.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
11661 { 21591 /* ssamoswap.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
11662 { 21606 /* ssamoswap.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
11663 { 21623 /* ssamoswap.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
11664 { 21701 /* subd */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11665 { 21711 /* sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11666 { 21714 /* sw.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11667 { 21722 /* sw.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11668 { 21728 /* tail */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
11669 { 22716 /* th.vmaqa.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
11670 { 22728 /* th.vmaqa.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
11671 { 22740 /* th.vmaqasu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
11672 { 22754 /* th.vmaqasu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
11673 { 22768 /* th.vmaqau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
11674 { 22781 /* th.vmaqau.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
11675 { 22794 /* th.vmaqaus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
11676 { 22862 /* vaadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11677 { 22871 /* vaadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11678 { 22880 /* vaaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11679 { 22890 /* vaaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11680 { 22927 /* vadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11681 { 22935 /* vadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11682 { 22943 /* vadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11683 { 23062 /* vand.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11684 { 23070 /* vand.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11685 { 23078 /* vand.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11686 { 23086 /* vandn.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
11687 { 23095 /* vandn.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
11688 { 23104 /* vasub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11689 { 23113 /* vasub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11690 { 23122 /* vasubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11691 { 23132 /* vasubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11692 { 23142 /* vbrev.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
11693 { 23150 /* vbrev8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
11694 { 23159 /* vclmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
11695 { 23169 /* vclmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
11696 { 23179 /* vclmulh.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
11697 { 23190 /* vclmulh.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
11698 { 23201 /* vclz.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
11699 { 23221 /* vcpop.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11700 { 23229 /* vcpop.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
11701 { 23237 /* vctz.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
11702 { 23244 /* vdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11703 { 23252 /* vdiv.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11704 { 23260 /* vdivu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11705 { 23269 /* vdivu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11706 { 23278 /* vfabs.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11707 { 23286 /* vfadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11708 { 23295 /* vfadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11709 { 23304 /* vfclass.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11710 { 23314 /* vfcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11711 { 23326 /* vfcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11712 { 23339 /* vfcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11713 { 23355 /* vfcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11714 { 23372 /* vfcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11715 { 23384 /* vfcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11716 { 23397 /* vfdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11717 { 23406 /* vfdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11718 { 23415 /* vfirst.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11719 { 23424 /* vfmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11720 { 23434 /* vfmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11721 { 23444 /* vfmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11722 { 23454 /* vfmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11723 { 23464 /* vfmax.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11724 { 23473 /* vfmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11725 { 23494 /* vfmin.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11726 { 23503 /* vfmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11727 { 23512 /* vfmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11728 { 23522 /* vfmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11729 { 23532 /* vfmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11730 { 23542 /* vfmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11731 { 23552 /* vfmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11732 { 23561 /* vfmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11733 { 23597 /* vfncvt.f.f.q */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
11734 { 23610 /* vfncvt.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11735 { 23623 /* vfncvt.f.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11736 { 23636 /* vfncvt.f.xu.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11737 { 23650 /* vfncvt.rod.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11738 { 23667 /* vfncvt.rtz.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11739 { 23684 /* vfncvt.rtz.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11740 { 23702 /* vfncvt.sat.f.f.q */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
11741 { 23719 /* vfncvt.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11742 { 23732 /* vfncvt.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11743 { 23746 /* vfncvtbf16.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfminOrZvfofp8min },
11744 { 23763 /* vfncvtbf16.sat.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
11745 { 23784 /* vfneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11746 { 23792 /* vfnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11747 { 23803 /* vfnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11748 { 23814 /* vfnmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11749 { 23825 /* vfnmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11750 { 23836 /* vfnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11751 { 23847 /* vfnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11752 { 23858 /* vfnmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11753 { 23869 /* vfnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11754 { 23880 /* vfrdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11755 { 23890 /* vfrec7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11756 { 23899 /* vfredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11757 { 23911 /* vfredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11758 { 23923 /* vfredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11759 { 23936 /* vfredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11760 { 23949 /* vfrsqrt7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11761 { 23960 /* vfrsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11762 { 23970 /* vfsgnj.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11763 { 23980 /* vfsgnj.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11764 { 23990 /* vfsgnjn.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11765 { 24001 /* vfsgnjn.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11766 { 24012 /* vfsgnjx.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11767 { 24023 /* vfsgnjx.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11768 { 24034 /* vfslide1down.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11769 { 24050 /* vfslide1up.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11770 { 24064 /* vfsqrt.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11771 { 24073 /* vfsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11772 { 24082 /* vfsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11773 { 24091 /* vfwadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11774 { 24101 /* vfwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11775 { 24111 /* vfwadd.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11776 { 24121 /* vfwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11777 { 24131 /* vfwcvt.f.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11778 { 24144 /* vfwcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11779 { 24157 /* vfwcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11780 { 24171 /* vfwcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11781 { 24188 /* vfwcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11782 { 24206 /* vfwcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11783 { 24219 /* vfwcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11784 { 24233 /* vfwcvtbf16.f.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfminOrZvfofp8min },
11785 { 24250 /* vfwmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11786 { 24261 /* vfwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11787 { 24272 /* vfwmaccbf16.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
11788 { 24287 /* vfwmaccbf16.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
11789 { 24302 /* vfwmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11790 { 24313 /* vfwmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11791 { 24324 /* vfwmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11792 { 24334 /* vfwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11793 { 24344 /* vfwnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11794 { 24356 /* vfwnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11795 { 24368 /* vfwnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11796 { 24380 /* vfwnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11797 { 24392 /* vfwredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11798 { 24406 /* vfwredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11799 { 24420 /* vfwsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11800 { 24430 /* vfwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11801 { 24440 /* vfwsub.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11802 { 24450 /* vfwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
11803 { 24496 /* vid.v */, 2 /* 1 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11804 { 24502 /* viota.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11805 { 24510 /* vl1r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11806 { 24517 /* vl1re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11807 { 24527 /* vl1re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11808 { 24537 /* vl1re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
11809 { 24547 /* vl1re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11810 { 24556 /* vl2r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11811 { 24563 /* vl2re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11812 { 24573 /* vl2re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11813 { 24583 /* vl2re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
11814 { 24593 /* vl2re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11815 { 24602 /* vl4r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11816 { 24609 /* vl4re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11817 { 24619 /* vl4re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11818 { 24629 /* vl4re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
11819 { 24639 /* vl4re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11820 { 24648 /* vl8r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11821 { 24655 /* vl8re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11822 { 24665 /* vl8re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11823 { 24675 /* vl8re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
11824 { 24685 /* vl8re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11825 { 24694 /* vle16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11826 { 24694 /* vle16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11827 { 24702 /* vle16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11828 { 24702 /* vle16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11829 { 24712 /* vle32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11830 { 24712 /* vle32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11831 { 24720 /* vle32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11832 { 24720 /* vle32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11833 { 24730 /* vle64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
11834 { 24730 /* vle64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
11835 { 24738 /* vle64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
11836 { 24738 /* vle64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
11837 { 24748 /* vle8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11838 { 24748 /* vle8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11839 { 24755 /* vle8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11840 { 24755 /* vle8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11841 { 24764 /* vlm.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11842 { 24770 /* vloxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11843 { 24770 /* vloxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11844 { 24781 /* vloxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11845 { 24781 /* vloxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11846 { 24792 /* vloxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
11847 { 24792 /* vloxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
11848 { 24803 /* vloxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11849 { 24803 /* vloxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11850 { 24813 /* vloxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11851 { 24813 /* vloxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11852 { 24828 /* vloxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11853 { 24828 /* vloxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11854 { 24843 /* vloxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11855 { 24843 /* vloxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11856 { 24858 /* vloxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11857 { 24858 /* vloxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11858 { 24872 /* vloxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11859 { 24872 /* vloxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11860 { 24887 /* vloxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11861 { 24887 /* vloxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11862 { 24902 /* vloxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11863 { 24902 /* vloxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11864 { 24917 /* vloxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11865 { 24917 /* vloxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11866 { 24931 /* vloxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11867 { 24931 /* vloxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11868 { 24946 /* vloxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11869 { 24946 /* vloxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11870 { 24961 /* vloxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11871 { 24961 /* vloxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11872 { 24976 /* vloxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11873 { 24976 /* vloxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11874 { 24990 /* vloxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11875 { 24990 /* vloxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11876 { 25005 /* vloxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11877 { 25005 /* vloxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11878 { 25020 /* vloxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11879 { 25020 /* vloxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11880 { 25035 /* vloxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11881 { 25035 /* vloxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11882 { 25049 /* vloxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11883 { 25049 /* vloxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11884 { 25064 /* vloxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11885 { 25064 /* vloxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11886 { 25079 /* vloxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11887 { 25079 /* vloxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11888 { 25094 /* vloxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11889 { 25094 /* vloxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11890 { 25108 /* vloxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11891 { 25108 /* vloxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11892 { 25123 /* vloxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11893 { 25123 /* vloxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11894 { 25138 /* vloxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11895 { 25138 /* vloxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
11896 { 25153 /* vloxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11897 { 25153 /* vloxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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11903 { 25197 /* vloxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
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11905 { 25212 /* vloxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11906 { 25226 /* vlse16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11907 { 25226 /* vlse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
11908 { 25235 /* vlse32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11909 { 25235 /* vlse32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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11911 { 25244 /* vlse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
11912 { 25253 /* vlse8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
11913 { 25253 /* vlse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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11957 { 25529 /* vlseg4e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
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11973 { 25631 /* vlseg5e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
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11988 { 25733 /* vlseg6e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
11989 { 25733 /* vlseg6e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
11990 { 25747 /* vlseg6e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
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11993 { 25758 /* vlseg6e8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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12004 { 25835 /* vlseg7e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12005 { 25835 /* vlseg7e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
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12081 { 26320 /* vlsseg8e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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12084 { 26343 /* vluxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12085 { 26343 /* vluxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12086 { 26354 /* vluxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12087 { 26354 /* vluxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12088 { 26365 /* vluxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12089 { 26365 /* vluxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12090 { 26375 /* vluxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12091 { 26375 /* vluxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12092 { 26390 /* vluxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12093 { 26390 /* vluxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12094 { 26405 /* vluxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12095 { 26405 /* vluxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12096 { 26420 /* vluxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12097 { 26420 /* vluxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12098 { 26434 /* vluxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12099 { 26434 /* vluxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12100 { 26449 /* vluxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12101 { 26449 /* vluxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12102 { 26464 /* vluxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12103 { 26464 /* vluxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12104 { 26479 /* vluxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12105 { 26479 /* vluxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12106 { 26493 /* vluxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12107 { 26493 /* vluxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12108 { 26508 /* vluxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12109 { 26508 /* vluxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12110 { 26523 /* vluxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12111 { 26523 /* vluxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12112 { 26538 /* vluxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12113 { 26538 /* vluxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12114 { 26552 /* vluxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12115 { 26552 /* vluxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12116 { 26567 /* vluxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12117 { 26567 /* vluxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12118 { 26582 /* vluxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12119 { 26582 /* vluxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12120 { 26597 /* vluxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12121 { 26597 /* vluxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12122 { 26611 /* vluxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12123 { 26611 /* vluxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12124 { 26626 /* vluxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12125 { 26626 /* vluxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12126 { 26641 /* vluxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12127 { 26641 /* vluxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12128 { 26656 /* vluxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12129 { 26656 /* vluxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12130 { 26670 /* vluxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12131 { 26670 /* vluxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12132 { 26685 /* vluxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12133 { 26685 /* vluxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12134 { 26700 /* vluxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12135 { 26700 /* vluxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12136 { 26715 /* vluxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12137 { 26715 /* vluxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12138 { 26729 /* vluxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12139 { 26729 /* vluxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12140 { 26744 /* vluxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12141 { 26744 /* vluxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12142 { 26759 /* vluxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12143 { 26759 /* vluxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12144 { 26774 /* vluxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12145 { 26774 /* vluxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12146 { 26788 /* vmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12147 { 26797 /* vmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12148 { 26863 /* vmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12149 { 26872 /* vmadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12150 { 26900 /* vmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12151 { 26908 /* vmax.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12152 { 26916 /* vmaxu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12153 { 26925 /* vmaxu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12154 { 26975 /* vmfeq.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12155 { 26984 /* vmfeq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12156 { 26993 /* vmfge.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12157 { 27002 /* vmfge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12158 { 27011 /* vmfgt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12159 { 27020 /* vmfgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12160 { 27029 /* vmfle.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12161 { 27038 /* vmfle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12162 { 27047 /* vmflt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12163 { 27056 /* vmflt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12164 { 27065 /* vmfne.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12165 { 27074 /* vmfne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12166 { 27083 /* vmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12167 { 27091 /* vmin.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12168 { 27099 /* vminu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12169 { 27108 /* vminu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12170 { 27206 /* vmsbf.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12171 { 27214 /* vmseq.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12172 { 27223 /* vmseq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12173 { 27232 /* vmseq.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12174 { 27249 /* vmsge.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12175 { 27258 /* vmsge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12176 { 27267 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12177 { 27267 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12178 { 27276 /* vmsgeu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12179 { 27286 /* vmsgeu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12180 { 27296 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12181 { 27296 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12182 { 27306 /* vmsgt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12183 { 27315 /* vmsgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12184 { 27324 /* vmsgt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12185 { 27333 /* vmsgtu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12186 { 27343 /* vmsgtu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12187 { 27353 /* vmsgtu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12188 { 27363 /* vmsif.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12189 { 27371 /* vmsle.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12190 { 27380 /* vmsle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12191 { 27389 /* vmsle.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12192 { 27398 /* vmsleu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12193 { 27408 /* vmsleu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12194 { 27418 /* vmsleu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12195 { 27428 /* vmslt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12196 { 27437 /* vmslt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12197 { 27446 /* vmslt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12198 { 27455 /* vmsltu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12199 { 27465 /* vmsltu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12200 { 27475 /* vmsltu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12201 { 27485 /* vmsne.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12202 { 27494 /* vmsne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12203 { 27503 /* vmsne.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12204 { 27512 /* vmsof.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12205 { 27520 /* vmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12206 { 27528 /* vmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12207 { 27536 /* vmulh.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12208 { 27545 /* vmulh.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12209 { 27554 /* vmulhsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12210 { 27565 /* vmulhsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12211 { 27576 /* vmulhu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12212 { 27586 /* vmulhu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12213 { 27687 /* vnclip.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12214 { 27697 /* vnclip.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12215 { 27707 /* vnclip.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12216 { 27717 /* vnclipu.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12217 { 27728 /* vnclipu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12218 { 27739 /* vnclipu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12219 { 27750 /* vncvt.x.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12220 { 27762 /* vneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12221 { 27769 /* vnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12222 { 27779 /* vnmsac.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12223 { 27789 /* vnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12224 { 27799 /* vnmsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12225 { 27809 /* vnot.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12226 { 27816 /* vnsra.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12227 { 27825 /* vnsra.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12228 { 27834 /* vnsra.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12229 { 27843 /* vnsrl.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12230 { 27852 /* vnsrl.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12231 { 27861 /* vnsrl.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12232 { 27870 /* vor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12233 { 27877 /* vor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12234 { 27884 /* vor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12235 { 27891 /* vqdot.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqdotq },
12236 { 27900 /* vqdot.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqdotq },
12237 { 27909 /* vqdotsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqdotq },
12238 { 27920 /* vqdotsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqdotq },
12239 { 27931 /* vqdotu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqdotq },
12240 { 27941 /* vqdotu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqdotq },
12241 { 27951 /* vqdotus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqdotq },
12242 { 27962 /* vredand.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12243 { 27973 /* vredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12244 { 27984 /* vredmaxu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12245 { 27996 /* vredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12246 { 28007 /* vredminu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12247 { 28019 /* vredor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12248 { 28029 /* vredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12249 { 28040 /* vredxor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12250 { 28051 /* vrem.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12251 { 28059 /* vrem.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12252 { 28067 /* vremu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12253 { 28076 /* vremu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12254 { 28085 /* vrev8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12255 { 28093 /* vrgather.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12256 { 28105 /* vrgather.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12257 { 28117 /* vrgather.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12258 { 28129 /* vrgatherei16.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12259 { 28145 /* vrol.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12260 { 28153 /* vrol.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12261 { 28161 /* vror.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12262 { 28169 /* vror.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12263 { 28177 /* vror.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12264 { 28185 /* vrsub.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12265 { 28194 /* vrsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12266 { 28203 /* vs1r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12267 { 28210 /* vs2r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12268 { 28217 /* vs4r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12269 { 28224 /* vs8r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12270 { 28231 /* vsadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12271 { 28240 /* vsadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12272 { 28249 /* vsadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12273 { 28258 /* vsaddu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12274 { 28268 /* vsaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12275 { 28278 /* vsaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12276 { 28306 /* vse16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12277 { 28306 /* vse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12278 { 28314 /* vse32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12279 { 28314 /* vse32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12280 { 28322 /* vse64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12281 { 28322 /* vse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12282 { 28330 /* vse8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12283 { 28330 /* vse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12284 { 28337 /* vsetivli */, 4 /* 2 */, MCK_VTypeI10, AMFBS_HasVInstructions },
12285 { 28353 /* vsetvli */, 4 /* 2 */, MCK_VTypeI11, AMFBS_HasVInstructions },
12286 { 28361 /* vsext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12287 { 28371 /* vsext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12288 { 28381 /* vsext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12289 { 28424 /* vslide1down.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12290 { 28439 /* vslide1up.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
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12487 { 29814 /* vssseg7e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12488 { 29814 /* vssseg7e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12489 { 29826 /* vssseg8e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12490 { 29826 /* vssseg8e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12491 { 29839 /* vssseg8e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12492 { 29839 /* vssseg8e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12493 { 29852 /* vssseg8e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12494 { 29852 /* vssseg8e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12495 { 29865 /* vssseg8e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12496 { 29865 /* vssseg8e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12497 { 29877 /* vssub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12498 { 29886 /* vssub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12499 { 29895 /* vssubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12500 { 29905 /* vssubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12501 { 29915 /* vsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12502 { 29923 /* vsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12503 { 29931 /* vsuxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12504 { 29931 /* vsuxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12505 { 29942 /* vsuxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12506 { 29942 /* vsuxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12507 { 29953 /* vsuxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12508 { 29953 /* vsuxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12509 { 29964 /* vsuxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12510 { 29964 /* vsuxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12511 { 29974 /* vsuxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12512 { 29974 /* vsuxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12513 { 29989 /* vsuxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12514 { 29989 /* vsuxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12515 { 30004 /* vsuxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12516 { 30004 /* vsuxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12517 { 30019 /* vsuxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12518 { 30019 /* vsuxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12519 { 30033 /* vsuxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12520 { 30033 /* vsuxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12521 { 30048 /* vsuxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12522 { 30048 /* vsuxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12523 { 30063 /* vsuxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12524 { 30063 /* vsuxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12525 { 30078 /* vsuxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12526 { 30078 /* vsuxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12527 { 30092 /* vsuxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12528 { 30092 /* vsuxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12529 { 30107 /* vsuxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12530 { 30107 /* vsuxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12531 { 30122 /* vsuxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12532 { 30122 /* vsuxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12533 { 30137 /* vsuxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12534 { 30137 /* vsuxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12535 { 30151 /* vsuxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12536 { 30151 /* vsuxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12537 { 30166 /* vsuxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12538 { 30166 /* vsuxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12539 { 30181 /* vsuxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12540 { 30181 /* vsuxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12541 { 30196 /* vsuxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12542 { 30196 /* vsuxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12543 { 30210 /* vsuxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12544 { 30210 /* vsuxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12545 { 30225 /* vsuxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12546 { 30225 /* vsuxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12547 { 30240 /* vsuxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12548 { 30240 /* vsuxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12549 { 30255 /* vsuxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12550 { 30255 /* vsuxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12551 { 30269 /* vsuxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12552 { 30269 /* vsuxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12553 { 30284 /* vsuxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12554 { 30284 /* vsuxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12555 { 30299 /* vsuxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12556 { 30299 /* vsuxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12557 { 30314 /* vsuxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12558 { 30314 /* vsuxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12559 { 30328 /* vsuxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12560 { 30328 /* vsuxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12561 { 30343 /* vsuxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12562 { 30343 /* vsuxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12563 { 30358 /* vsuxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12564 { 30358 /* vsuxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12565 { 30373 /* vsuxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12566 { 30373 /* vsuxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12567 { 30406 /* vwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12568 { 30415 /* vwadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12569 { 30424 /* vwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12570 { 30433 /* vwadd.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12571 { 30442 /* vwaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12572 { 30452 /* vwaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12573 { 30462 /* vwaddu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12574 { 30472 /* vwaddu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12575 { 30482 /* vwcvt.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12576 { 30494 /* vwcvtu.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12577 { 30507 /* vwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12578 { 30517 /* vwmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12579 { 30527 /* vwmaccsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12580 { 30539 /* vwmaccsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12581 { 30551 /* vwmaccu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12582 { 30562 /* vwmaccu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12583 { 30573 /* vwmaccus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12584 { 30585 /* vwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12585 { 30594 /* vwmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12586 { 30603 /* vwmulsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12587 { 30614 /* vwmulsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12588 { 30625 /* vwmulu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12589 { 30635 /* vwmulu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12590 { 30645 /* vwredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12591 { 30657 /* vwredsumu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12592 { 30670 /* vwsll.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12593 { 30679 /* vwsll.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12594 { 30688 /* vwsll.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12595 { 30697 /* vwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12596 { 30706 /* vwsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12597 { 30715 /* vwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12598 { 30724 /* vwsub.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12599 { 30733 /* vwsubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12600 { 30743 /* vwsubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12601 { 30753 /* vwsubu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12602 { 30763 /* vwsubu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12603 { 30773 /* vxor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12604 { 30781 /* vxor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12605 { 30789 /* vxor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12606 { 30797 /* vzext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12607 { 30807 /* vzext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12608 { 30817 /* vzext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12609 { 30827 /* wadd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12610 { 30832 /* wadda */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12611 { 30838 /* waddau */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12612 { 30845 /* waddu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12613 { 30855 /* wmacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12614 { 30861 /* wmaccsu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12615 { 30869 /* wmaccu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12616 { 30876 /* wmul */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12617 { 30881 /* wmulsu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12618 { 30888 /* wmulu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12619 { 30910 /* wsla */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12620 { 30915 /* wslai */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12621 { 30921 /* wsll */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12622 { 30926 /* wslli */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12623 { 30932 /* wsub */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12624 { 30937 /* wsuba */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12625 { 30943 /* wsubau */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12626 { 30950 /* wsubu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12627 { 30956 /* wzip16p */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12628 { 30964 /* wzip8p */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12629};
12630
12631ParseStatus RISCVAsmParser::
12632tryCustomParseOperand(OperandVector &Operands,
12633 unsigned MCK) {
12634
12635 switch(MCK) {
12636 case MCK_BareSymbol:
12637 return parseBareSymbol(Operands);
12638 case MCK_BareSymbolQC_E_LI:
12639 return parseBareSymbol(Operands);
12640 case MCK_CSRSystemRegister:
12641 return parseCSRSystemRegister(Operands);
12642 case MCK_RegReg:
12643 return parseRegReg(Operands);
12644 case MCK_CallSymbol:
12645 return parseCallSymbol(Operands);
12646 case MCK_FRMArg:
12647 return parseFRMArg(Operands);
12648 case MCK_FRMArgLegacy:
12649 return parseFRMArg(Operands);
12650 case MCK_FenceArg:
12651 return parseFenceArg(Operands);
12652 case MCK_GPRAsFPR16:
12653 return parseGPRAsFPR(Operands);
12654 case MCK_GPRAsFPR32:
12655 return parseGPRAsFPR(Operands);
12656 case MCK_GPRF64AsFPR:
12657 return parseGPRAsFPR64(Operands);
12658 case MCK_GPRPairAsFPR:
12659 return parseGPRPairAsFPR64(Operands);
12660 case MCK_GPRPairCRV32:
12661 return parseGPRPair<false>(Operands);
12662 case MCK_GPRPairNoX0RV32:
12663 return parseGPRPair<false>(Operands);
12664 case MCK_GPRPairRV32:
12665 return parseGPRPair<false>(Operands);
12666 case MCK_GPRPairRV64:
12667 return parseGPRPair<true>(Operands);
12668 case MCK_InsnCDirectiveOpcode:
12669 return parseInsnCDirectiveOpcode(Operands);
12670 case MCK_InsnDirectiveOpcode:
12671 return parseInsnDirectiveOpcode(Operands);
12672 case MCK_LoadFPImm:
12673 return parseFPImm(Operands);
12674 case MCK_NegStackAdj:
12675 return parseZcmpNegStackAdj(Operands);
12676 case MCK_PseudoJumpSymbol:
12677 return parsePseudoJumpSymbol(Operands);
12678 case MCK_RTZArg:
12679 return parseFRMArg(Operands);
12680 case MCK_RegList:
12681 return parseRegList(Operands);
12682 case MCK_RegListS0:
12683 return parseRegListS0(Operands);
12684 case MCK_BareSImm21Lsb0:
12685 return parseJALOffset(Operands);
12686 case MCK_StackAdj:
12687 return parseZcmpStackAdj(Operands);
12688 case MCK_TLSDESCCallSymbol:
12689 return parseOperandWithSpecifier(Operands);
12690 case MCK_TPRelAddSymbol:
12691 return parseOperandWithSpecifier(Operands);
12692 case MCK_RVVMaskRegOpOperand:
12693 return parseMaskReg(Operands);
12694 case MCK_XSfmmVType:
12695 return parseXSfmmVType(Operands);
12696 case MCK_ZeroOffsetMemOpOperand:
12697 return parseZeroOffsetMemOp(Operands);
12698 case MCK_VTypeI10:
12699 return parseVTypeI(Operands);
12700 case MCK_VTypeI11:
12701 return parseVTypeI(Operands);
12702 default:
12703 return ParseStatus::NoMatch;
12704 }
12705 return ParseStatus::NoMatch;
12706}
12707
12708ParseStatus RISCVAsmParser::
12709MatchOperandParserImpl(OperandVector &Operands,
12710 StringRef Mnemonic,
12711 bool ParseForAllFeatures) {
12712 // Get the current feature set.
12713 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
12714
12715 // Get the next operand index.
12716 unsigned NextOpNum = Operands.size() - 1;
12717 // Search the table.
12718 auto MnemonicRange =
12719 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
12720 Mnemonic, LessOpcodeOperand());
12721
12722 if (MnemonicRange.first == MnemonicRange.second)
12723 return ParseStatus::NoMatch;
12724
12725 for (const OperandMatchEntry *it = MnemonicRange.first,
12726 *ie = MnemonicRange.second; it != ie; ++it) {
12727 // equal_range guarantees that instruction mnemonic matches.
12728 assert(Mnemonic == it->getMnemonic());
12729
12730 // check if the available features match
12731 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
12732 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
12733 continue;
12734
12735 // check if the operand in question has a custom parser.
12736 if (!(it->OperandMask & (1 << NextOpNum)))
12737 continue;
12738
12739 // call custom parse method to handle the operand
12740 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
12741 if (!Result.isNoMatch())
12742 return Result;
12743 }
12744
12745 // Okay, we had no match.
12746 return ParseStatus::NoMatch;
12747}
12748
12749#endif // GET_MATCHER_IMPLEMENTATION
12750
12751
12752#ifdef GET_MNEMONIC_SPELL_CHECKER
12753#undef GET_MNEMONIC_SPELL_CHECKER
12754
12755static std::string RISCVMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
12756 const unsigned MaxEditDist = 2;
12757 std::vector<StringRef> Candidates;
12758 StringRef Prev = "";
12759
12760 // Find the appropriate table for this asm variant.
12761 const MatchEntry *Start, *End;
12762 switch (VariantID) {
12763 default: llvm_unreachable("invalid variant!");
12764 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
12765 }
12766
12767 for (auto I = Start; I < End; I++) {
12768 // Ignore unsupported instructions.
12769 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
12770 if ((FBS & RequiredFeatures) != RequiredFeatures)
12771 continue;
12772
12773 StringRef T = I->getMnemonic();
12774 // Avoid recomputing the edit distance for the same string.
12775 if (T == Prev)
12776 continue;
12777
12778 Prev = T;
12779 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
12780 if (Dist <= MaxEditDist)
12781 Candidates.push_back(T);
12782 }
12783
12784 if (Candidates.empty())
12785 return "";
12786
12787 std::string Res = ", did you mean: ";
12788 unsigned i = 0;
12789 for (; i < Candidates.size() - 1; i++)
12790 Res += Candidates[i].str() + ", ";
12791 return Res + Candidates[i].str() + "?";
12792}
12793
12794#endif // GET_MNEMONIC_SPELL_CHECKER
12795
12796
12797#ifdef GET_MNEMONIC_CHECKER
12798#undef GET_MNEMONIC_CHECKER
12799
12800static bool RISCVCheckMnemonic(StringRef Mnemonic,
12801 const FeatureBitset &AvailableFeatures,
12802 unsigned VariantID) {
12803 // Process all MnemonicAliases to remap the mnemonic.
12804 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
12805
12806 // Find the appropriate table for this asm variant.
12807 const MatchEntry *Start, *End;
12808 switch (VariantID) {
12809 default: llvm_unreachable("invalid variant!");
12810 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
12811 }
12812
12813 // Search the table.
12814 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
12815
12816 if (MnemonicRange.first == MnemonicRange.second)
12817 return false;
12818
12819 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
12820 it != ie; ++it) {
12821 const FeatureBitset &RequiredFeatures =
12822 FeatureBitsets[it->RequiredFeaturesIdx];
12823 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
12824 return true;
12825 }
12826 return false;
12827}
12828
12829#endif // GET_MNEMONIC_CHECKER
12830
12831