1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: RISCV.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands,
18 const SmallBitVector &OptionalOperandsMask,
19 ArrayRef<unsigned> DefaultsOffset);
20 void convertToMapAndConstraints(unsigned Kind,
21 const OperandVector &Operands) override;
22 unsigned MatchInstructionImpl(const OperandVector &Operands,
23 MCInst &Inst,
24 SmallVectorImpl<NearMissInfo> *NearMisses,
25 bool matchingInlineAsm,
26 unsigned VariantID = 0);
27 ParseStatus MatchOperandParserImpl(
28 OperandVector &Operands,
29 StringRef Mnemonic,
30 bool ParseForAllFeatures = false);
31 ParseStatus tryCustomParseOperand(
32 OperandVector &Operands,
33 unsigned MCK);
34
35#endif // GET_ASSEMBLER_HEADER
36
37
38#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
39#undef GET_OPERAND_DIAGNOSTIC_TYPES
40
41 Match_GPRAsFPR16,
42 Match_GPRAsFPR32,
43 Match_GPRC,
44 Match_GPRF64AsFPR,
45 Match_GPRPairAsFPR,
46 Match_InvalidBareSImm11Lsb0,
47 Match_InvalidBareSImm12Lsb0,
48 Match_InvalidBareSImm13Lsb0,
49 Match_InvalidBareSImm21Lsb0,
50 Match_InvalidBareSImm32,
51 Match_InvalidBareSImm32Lsb0,
52 Match_InvalidBareSImm9Lsb0,
53 Match_InvalidBareSymbol,
54 Match_InvalidBareSymbolQC_E_LI,
55 Match_InvalidCLUIImm,
56 Match_InvalidCSRSystemRegister,
57 Match_InvalidCallSymbol,
58 Match_InvalidGPRPairCRV32,
59 Match_InvalidGPRPairNoX0RV32,
60 Match_InvalidImm5Zibi,
61 Match_InvalidImmFour,
62 Match_InvalidImmThree,
63 Match_InvalidImmXLenLI,
64 Match_InvalidImmXLenLI_Restricted,
65 Match_InvalidImmZero,
66 Match_InvalidLoadFPImm,
67 Match_InvalidPseudoJumpSymbol,
68 Match_InvalidQCAccessSymbol,
69 Match_InvalidRTZArg,
70 Match_InvalidRegClassFPR128,
71 Match_InvalidRegClassFPR16,
72 Match_InvalidRegClassFPR16C,
73 Match_InvalidRegClassFPR256,
74 Match_InvalidRegClassFPR32,
75 Match_InvalidRegClassFPR32C,
76 Match_InvalidRegClassFPR64,
77 Match_InvalidRegClassFPR64C,
78 Match_InvalidRegClassGPR,
79 Match_InvalidRegClassGPRNoX0,
80 Match_InvalidRegClassGPRNoX0X2,
81 Match_InvalidRegClassGPRNoX2,
82 Match_InvalidRegClassGPRS07,
83 Match_InvalidRegClassGPRX0,
84 Match_InvalidRegClassGPRX1,
85 Match_InvalidRegClassGPRX1X5,
86 Match_InvalidRegClassGPRX31,
87 Match_InvalidRegClassGPRX5,
88 Match_InvalidRegClassSP,
89 Match_InvalidRegList,
90 Match_InvalidRegListS0,
91 Match_InvalidRnumArg,
92 Match_InvalidSImm10,
93 Match_InvalidSImm10Lsb0000NonZero,
94 Match_InvalidSImm10PLI_H,
95 Match_InvalidSImm10PLI_W,
96 Match_InvalidSImm10PLUI,
97 Match_InvalidSImm11,
98 Match_InvalidSImm12,
99 Match_InvalidSImm12LO,
100 Match_InvalidSImm12Lsb00000,
101 Match_InvalidSImm16,
102 Match_InvalidSImm16NonZero,
103 Match_InvalidSImm18,
104 Match_InvalidSImm18Lsb0,
105 Match_InvalidSImm19Lsb00,
106 Match_InvalidSImm20LI,
107 Match_InvalidSImm20Lsb000,
108 Match_InvalidSImm26,
109 Match_InvalidSImm5,
110 Match_InvalidSImm5NonZero,
111 Match_InvalidSImm5Plus1,
112 Match_InvalidSImm6,
113 Match_InvalidSImm6NonZero,
114 Match_InvalidSImm8PLI_B,
115 Match_InvalidSMTI8,
116 Match_InvalidSMTType,
117 Match_InvalidStackAdj,
118 Match_InvalidTLSDESCCallSymbol,
119 Match_InvalidTPRelAddSymbol,
120 Match_InvalidTailCallSymbol,
121 Match_InvalidTileLambda,
122 Match_InvalidToken_40_,
123 Match_InvalidToken_41_,
124 Match_InvalidUImm1,
125 Match_InvalidUImm10,
126 Match_InvalidUImm10Lsb00NonZero,
127 Match_InvalidUImm11,
128 Match_InvalidUImm14Lsb00,
129 Match_InvalidUImm16,
130 Match_InvalidUImm16NonZero,
131 Match_InvalidUImm2,
132 Match_InvalidUImm20,
133 Match_InvalidUImm20AUIPC,
134 Match_InvalidUImm20LUI,
135 Match_InvalidUImm2Lsb0,
136 Match_InvalidUImm3,
137 Match_InvalidUImm32,
138 Match_InvalidUImm4,
139 Match_InvalidUImm48,
140 Match_InvalidUImm4Plus1,
141 Match_InvalidUImm5,
142 Match_InvalidUImm5GE6Plus1,
143 Match_InvalidUImm5GT3,
144 Match_InvalidUImm5Lsb0,
145 Match_InvalidUImm5NonZero,
146 Match_InvalidUImm5Plus1,
147 Match_InvalidUImm5Slist,
148 Match_InvalidUImm6,
149 Match_InvalidUImm64,
150 Match_InvalidUImm6Lsb0,
151 Match_InvalidUImm6Lsb000,
152 Match_InvalidUImm6Plus1,
153 Match_InvalidUImm7,
154 Match_InvalidUImm7Lsb00,
155 Match_InvalidUImm7Lsb000,
156 Match_InvalidUImm8,
157 Match_InvalidUImm8GE32,
158 Match_InvalidUImm8Lsb00,
159 Match_InvalidUImm8Lsb000,
160 Match_InvalidUImm9,
161 Match_InvalidUImm9Lsb000,
162 Match_InvalidUImmLog2XLen,
163 Match_InvalidUImmLog2XLenNonZero,
164 Match_InvalidVMaskCarryInRegister,
165 Match_InvalidVMaskRegister,
166 Match_InvalidVScaleRegister,
167 Match_InvalidVTypeI,
168 Match_InvalidYBNDSWImm,
169 END_OPERAND_DIAGNOSTIC_TYPES
170#endif // GET_OPERAND_DIAGNOSTIC_TYPES
171
172
173#ifdef GET_REGISTER_MATCHER
174#undef GET_REGISTER_MATCHER
175
176// Bits for subtarget features that participate in instruction matching.
177enum SubtargetFeatureBits : uint8_t {
178 Feature_HasStdExtZibiBit = 50,
179 Feature_HasStdExtZicbomBit = 51,
180 Feature_HasStdExtZicbopBit = 52,
181 Feature_HasStdExtZicbozBit = 53,
182 Feature_HasStdExtZicsrBit = 56,
183 Feature_HasStdExtZicondBit = 55,
184 Feature_HasStdExtZifenceiBit = 57,
185 Feature_HasStdExtZihintpauseBit = 59,
186 Feature_HasStdExtZihintntlBit = 58,
187 Feature_HasStdExtZimopBit = 62,
188 Feature_HasStdExtZicfissBit = 54,
189 Feature_HasStdExtZilsdBit = 60,
190 Feature_HasStdExtZilxBit = 61,
191 Feature_HasStdExtZmmulBit = 70,
192 Feature_HasStdExtMBit = 7,
193 Feature_HasStdExtZaamoBit = 18,
194 Feature_HasStdExtZalrscBit = 22,
195 Feature_HasStdExtABit = 2,
196 Feature_HasStdExtZtsoBit = 71,
197 Feature_HasStdExtZabhaBit = 19,
198 Feature_HasStdExtZacasBit = 20,
199 Feature_HasStdExtZalasrBit = 21,
200 Feature_HasStdExtZawrsBit = 23,
201 Feature_HasStdExtFBit = 4,
202 Feature_HasStdExtDBit = 3,
203 Feature_HasStdExtQBit = 9,
204 Feature_HasStdExtZfhminBit = 46,
205 Feature_HasStdExtZfhBit = 44,
206 Feature_HasStdExtZfbfminBit = 43,
207 Feature_HasHalfFPLoadStoreMoveBit = 1,
208 Feature_HasStdExtZfaBit = 42,
209 Feature_HasStdExtZfinxBit = 47,
210 Feature_HasStdExtFOrZfinxBit = 5,
211 Feature_HasStdExtZdinxBit = 41,
212 Feature_HasStdExtZhinxminBit = 49,
213 Feature_HasStdExtZhinxBit = 48,
214 Feature_HasStdExtZcaBit = 33,
215 Feature_HasStdExtZcbBit = 34,
216 Feature_HasStdExtZcfBit = 36,
217 Feature_HasStdExtZcdBit = 35,
218 Feature_HasStdExtZclsdBit = 37,
219 Feature_HasStdExtZcmpBit = 39,
220 Feature_HasStdExtZcmtBit = 40,
221 Feature_HasStdExtZcmopBit = 38,
222 Feature_HasStdExtZbaBit = 24,
223 Feature_HasStdExtZbbBit = 25,
224 Feature_NoStdExtZbbBit = 175,
225 Feature_HasStdExtZbsBit = 32,
226 Feature_HasStdExtZbkbBit = 28,
227 Feature_NoStdExtZbkbBit = 176,
228 Feature_HasStdExtZbkxBit = 31,
229 Feature_HasStdExtZbbOrZbkbBit = 26,
230 Feature_HasStdExtZbkcBit = 30,
231 Feature_HasStdExtZbcBit = 27,
232 Feature_HasStdExtZkndBit = 63,
233 Feature_HasStdExtZkneBit = 65,
234 Feature_HasStdExtZkndOrZkneBit = 64,
235 Feature_HasStdExtZknhBit = 66,
236 Feature_HasStdExtZksedBit = 68,
237 Feature_HasStdExtZkshBit = 69,
238 Feature_HasStdExtZkrBit = 67,
239 Feature_HasStdExtZvabdBit = 72,
240 Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit = 95,
241 Feature_HasStdExtZvfwdota16bfBit = 85,
242 Feature_HasStdExtZvfqwdota8fBit = 83,
243 Feature_HasStdExtZvfbfminBit = 78,
244 Feature_HasStdExtZvfbfwmaBit = 80,
245 Feature_HasStdExtZfhOrZvfhBit = 45,
246 Feature_HasStdExtZvfofp8minBit = 81,
247 Feature_HasStdExtZvfbfminOrZvfofp8minBit = 79,
248 Feature_HasStdExtZvkbBit = 86,
249 Feature_HasStdExtZvbbBit = 73,
250 Feature_HasStdExtZvbcBit = 74,
251 Feature_HasStdExtZvbcOrZvbc32eBit = 75,
252 Feature_HasStdExtZvkgBit = 87,
253 Feature_HasStdExtZvkgsBit = 88,
254 Feature_HasStdExtZvknedBit = 89,
255 Feature_HasStdExtZvknhaBit = 90,
256 Feature_HasStdExtZvknhbBit = 91,
257 Feature_HasStdExtZvksedBit = 92,
258 Feature_HasStdExtZvkshBit = 93,
259 Feature_HasStdExtZvdot4a8iBit = 76,
260 Feature_HasStdExtZvzipBit = 100,
261 Feature_HasStdExtZvvmmBit = 97,
262 Feature_HasStdExtZvvfmmBit = 96,
263 Feature_HasStdExtZvvmtlsBit = 98,
264 Feature_HasStdExtZvvmttlsBit = 99,
265 Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit = 94,
266 Feature_HasStdExtZvfwbdota16bfBit = 84,
267 Feature_HasStdExtZvfqwbdota8fBit = 82,
268 Feature_HasStdExtZvfbdota32fBit = 77,
269 Feature_HasVInstructionsBit = 101,
270 Feature_HasVInstructionsI64Bit = 104,
271 Feature_HasVInstructionsAnyFBit = 102,
272 Feature_HasVInstructionsF16MinimalBit = 103,
273 Feature_HasStdExtHBit = 6,
274 Feature_HasStdExtSmcspsBit = 10,
275 Feature_HasStdExtSscspsBit = 14,
276 Feature_HasStdExtSmipBit = 12,
277 Feature_HasStdExtSsipBit = 15,
278 Feature_HasStdExtSmrnmiBit = 13,
279 Feature_HasStdExtSvinvalBit = 16,
280 Feature_HasStdExtSmctrOrSsctrBit = 11,
281 Feature_HasStdExtPBit = 8,
282 Feature_HasStdExtZbkbOrPBit = 29,
283 Feature_HasStdExtYBit = 17,
284 Feature_HasVendorXTHeadBaBit = 139,
285 Feature_HasVendorXTHeadBbBit = 140,
286 Feature_HasVendorXTHeadBsBit = 141,
287 Feature_HasVendorXTHeadCondMovBit = 143,
288 Feature_HasVendorXTHeadCmoBit = 142,
289 Feature_HasVendorXTHeadFMemIdxBit = 144,
290 Feature_HasVendorXTHeadMacBit = 145,
291 Feature_HasVendorXTHeadMemIdxBit = 146,
292 Feature_HasVendorXTHeadMemPairBit = 147,
293 Feature_HasVendorXTHeadSyncBit = 148,
294 Feature_HasVendorXTHeadVdotBit = 149,
295 Feature_HasVendorXSfvcpBit = 130,
296 Feature_HasVendorXSfmmbaseBit = 129,
297 Feature_HasVendorXSfmm32a8fBit = 126,
298 Feature_HasVendorXSfmm32a8iBit = 127,
299 Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit = 128,
300 Feature_HasVendorXSfvqmaccdodBit = 135,
301 Feature_HasVendorXSfvqmaccqoqBit = 136,
302 Feature_HasVendorXSfvfwmaccqqqBit = 134,
303 Feature_HasVendorXSfvfnrclipxfqfBit = 133,
304 Feature_HasVendorXSfvfexpAnyBit = 131,
305 Feature_HasVendorXSfvfexpaBit = 132,
306 Feature_HasVendorXSiFivecdiscarddloneBit = 137,
307 Feature_HasVendorXSiFivecflushdloneBit = 138,
308 Feature_HasVendorXSfceaseBit = 125,
309 Feature_HasVendorXCVelwBit = 115,
310 Feature_HasVendorXCVbitmanipBit = 114,
311 Feature_HasVendorXCVmacBit = 116,
312 Feature_HasVendorXCVmemBit = 117,
313 Feature_HasVendorXCValuBit = 112,
314 Feature_HasVendorXCVsimdBit = 118,
315 Feature_HasVendorXCVbiBit = 113,
316 Feature_HasVendorXMIPSCMovBit = 120,
317 Feature_HasVendorXMIPSLSPBit = 122,
318 Feature_HasVendorXMIPSCBOPBit = 119,
319 Feature_HasVendorXMIPSEXECTLBit = 121,
320 Feature_HasVendorXwchcBit = 171,
321 Feature_HasVendorXqccmpBit = 151,
322 Feature_HasVendorXqccmiBit = 150,
323 Feature_HasVendorXqccmtBit = 152,
324 Feature_HasVendorXqciaBit = 153,
325 Feature_HasVendorXqciacBit = 154,
326 Feature_HasVendorXqcibiBit = 155,
327 Feature_HasVendorXqcibmBit = 156,
328 Feature_HasVendorXqcicliBit = 157,
329 Feature_HasVendorXqcicmBit = 158,
330 Feature_HasVendorXqcicsBit = 159,
331 Feature_HasVendorXqcicsrBit = 160,
332 Feature_HasVendorXqciintBit = 161,
333 Feature_HasVendorXqciioBit = 162,
334 Feature_HasVendorXqcilbBit = 163,
335 Feature_HasVendorXqciliBit = 164,
336 Feature_HasVendorXqciliaBit = 165,
337 Feature_HasVendorXqciloBit = 166,
338 Feature_HasVendorXqcilsmBit = 167,
339 Feature_HasVendorXqcisimBit = 168,
340 Feature_HasVendorXqcislsBit = 169,
341 Feature_HasVendorXqcisyncBit = 170,
342 Feature_HasVendorXAndesPerfBit = 106,
343 Feature_HasVendorXAndesBFHCvtBit = 105,
344 Feature_HasVendorXAndesVBFHCvtBit = 107,
345 Feature_HasVendorXAndesVSIntHBit = 110,
346 Feature_HasVendorXAndesVSIntLoadBit = 111,
347 Feature_HasVendorXAndesVPackFPHBit = 109,
348 Feature_HasVendorXAndesVDotBit = 108,
349 Feature_HasVendorXSMTVDotBit = 123,
350 Feature_HasVendorXSMTVDotIIBit = 124,
351 Feature_HasXAIFETBit = 172,
352 Feature_HasCheriotBit = 0,
353 Feature_IsRV64Bit = 174,
354 Feature_IsRV32Bit = 173,
355};
356
357[[maybe_unused]] static MCRegister MatchRegisterName(StringRef Name) {
358 switch (Name.size()) {
359 default: break;
360 case 2: // 212 strings to match.
361 switch (Name[0]) {
362 default: break;
363 case 'f': // 50 strings to match.
364 switch (Name[1]) {
365 default: break;
366 case '0': // 5 strings to match.
367 return RISCV::F0_D; // "f0"
368 case '1': // 5 strings to match.
369 return RISCV::F1_D; // "f1"
370 case '2': // 5 strings to match.
371 return RISCV::F2_D; // "f2"
372 case '3': // 5 strings to match.
373 return RISCV::F3_D; // "f3"
374 case '4': // 5 strings to match.
375 return RISCV::F4_D; // "f4"
376 case '5': // 5 strings to match.
377 return RISCV::F5_D; // "f5"
378 case '6': // 5 strings to match.
379 return RISCV::F6_D; // "f6"
380 case '7': // 5 strings to match.
381 return RISCV::F7_D; // "f7"
382 case '8': // 5 strings to match.
383 return RISCV::F8_D; // "f8"
384 case '9': // 5 strings to match.
385 return RISCV::F9_D; // "f9"
386 }
387 break;
388 case 'm': // 8 strings to match.
389 switch (Name[1]) {
390 default: break;
391 case '0': // 1 string to match.
392 return RISCV::M0; // "m0"
393 case '1': // 1 string to match.
394 return RISCV::M1; // "m1"
395 case '2': // 1 string to match.
396 return RISCV::M2; // "m2"
397 case '3': // 1 string to match.
398 return RISCV::M3; // "m3"
399 case '4': // 1 string to match.
400 return RISCV::M4; // "m4"
401 case '5': // 1 string to match.
402 return RISCV::M5; // "m5"
403 case '6': // 1 string to match.
404 return RISCV::M6; // "m6"
405 case '7': // 1 string to match.
406 return RISCV::M7; // "m7"
407 }
408 break;
409 case 'v': // 109 strings to match.
410 switch (Name[1]) {
411 default: break;
412 case '0': // 15 strings to match.
413 return RISCV::V0; // "v0"
414 case '1': // 8 strings to match.
415 return RISCV::V1; // "v1"
416 case '2': // 12 strings to match.
417 return RISCV::V2; // "v2"
418 case '3': // 8 strings to match.
419 return RISCV::V3; // "v3"
420 case '4': // 14 strings to match.
421 return RISCV::V4; // "v4"
422 case '5': // 8 strings to match.
423 return RISCV::V5; // "v5"
424 case '6': // 12 strings to match.
425 return RISCV::V6; // "v6"
426 case '7': // 8 strings to match.
427 return RISCV::V7; // "v7"
428 case '8': // 15 strings to match.
429 return RISCV::V8; // "v8"
430 case '9': // 8 strings to match.
431 return RISCV::V9; // "v9"
432 case 'l': // 1 string to match.
433 return RISCV::VL; // "vl"
434 }
435 break;
436 case 'x': // 45 strings to match.
437 switch (Name[1]) {
438 default: break;
439 case '0': // 5 strings to match.
440 return RISCV::X0; // "x0"
441 case '1': // 4 strings to match.
442 return RISCV::X1; // "x1"
443 case '2': // 5 strings to match.
444 return RISCV::X2; // "x2"
445 case '3': // 4 strings to match.
446 return RISCV::X3; // "x3"
447 case '4': // 5 strings to match.
448 return RISCV::X4; // "x4"
449 case '5': // 4 strings to match.
450 return RISCV::X5; // "x5"
451 case '6': // 5 strings to match.
452 return RISCV::X6; // "x6"
453 case '7': // 4 strings to match.
454 return RISCV::X7; // "x7"
455 case '8': // 5 strings to match.
456 return RISCV::X8; // "x8"
457 case '9': // 4 strings to match.
458 return RISCV::X9; // "x9"
459 }
460 break;
461 }
462 break;
463 case 3: // 418 strings to match.
464 switch (Name[0]) {
465 default: break;
466 case 'f': // 111 strings to match.
467 switch (Name[1]) {
468 default: break;
469 case '1': // 50 strings to match.
470 switch (Name[2]) {
471 default: break;
472 case '0': // 5 strings to match.
473 return RISCV::F10_D; // "f10"
474 case '1': // 5 strings to match.
475 return RISCV::F11_D; // "f11"
476 case '2': // 5 strings to match.
477 return RISCV::F12_D; // "f12"
478 case '3': // 5 strings to match.
479 return RISCV::F13_D; // "f13"
480 case '4': // 5 strings to match.
481 return RISCV::F14_D; // "f14"
482 case '5': // 5 strings to match.
483 return RISCV::F15_D; // "f15"
484 case '6': // 5 strings to match.
485 return RISCV::F16_D; // "f16"
486 case '7': // 5 strings to match.
487 return RISCV::F17_D; // "f17"
488 case '8': // 5 strings to match.
489 return RISCV::F18_D; // "f18"
490 case '9': // 5 strings to match.
491 return RISCV::F19_D; // "f19"
492 }
493 break;
494 case '2': // 50 strings to match.
495 switch (Name[2]) {
496 default: break;
497 case '0': // 5 strings to match.
498 return RISCV::F20_D; // "f20"
499 case '1': // 5 strings to match.
500 return RISCV::F21_D; // "f21"
501 case '2': // 5 strings to match.
502 return RISCV::F22_D; // "f22"
503 case '3': // 5 strings to match.
504 return RISCV::F23_D; // "f23"
505 case '4': // 5 strings to match.
506 return RISCV::F24_D; // "f24"
507 case '5': // 5 strings to match.
508 return RISCV::F25_D; // "f25"
509 case '6': // 5 strings to match.
510 return RISCV::F26_D; // "f26"
511 case '7': // 5 strings to match.
512 return RISCV::F27_D; // "f27"
513 case '8': // 5 strings to match.
514 return RISCV::F28_D; // "f28"
515 case '9': // 5 strings to match.
516 return RISCV::F29_D; // "f29"
517 }
518 break;
519 case '3': // 10 strings to match.
520 switch (Name[2]) {
521 default: break;
522 case '0': // 5 strings to match.
523 return RISCV::F30_D; // "f30"
524 case '1': // 5 strings to match.
525 return RISCV::F31_D; // "f31"
526 }
527 break;
528 case 'r': // 1 string to match.
529 if (Name[2] != 'm')
530 break;
531 return RISCV::FRM; // "frm"
532 }
533 break;
534 case 'm': // 10 strings to match.
535 if (Name[1] != 't')
536 break;
537 switch (Name[2]) {
538 default: break;
539 case '0': // 1 string to match.
540 return RISCV::T0; // "mt0"
541 case '1': // 1 string to match.
542 return RISCV::T1; // "mt1"
543 case '2': // 1 string to match.
544 return RISCV::T2; // "mt2"
545 case '3': // 1 string to match.
546 return RISCV::T3; // "mt3"
547 case '4': // 1 string to match.
548 return RISCV::T4; // "mt4"
549 case '5': // 1 string to match.
550 return RISCV::T5; // "mt5"
551 case '6': // 1 string to match.
552 return RISCV::T6; // "mt6"
553 case '7': // 1 string to match.
554 return RISCV::T7; // "mt7"
555 case '8': // 1 string to match.
556 return RISCV::T8; // "mt8"
557 case '9': // 1 string to match.
558 return RISCV::T9; // "mt9"
559 }
560 break;
561 case 's': // 1 string to match.
562 if (memcmp(Name.data()+1, "sp", 2) != 0)
563 break;
564 return RISCV::SSP; // "ssp"
565 case 'v': // 197 strings to match.
566 switch (Name[1]) {
567 default: break;
568 case '1': // 105 strings to match.
569 switch (Name[2]) {
570 default: break;
571 case '0': // 12 strings to match.
572 return RISCV::V10; // "v10"
573 case '1': // 8 strings to match.
574 return RISCV::V11; // "v11"
575 case '2': // 14 strings to match.
576 return RISCV::V12; // "v12"
577 case '3': // 8 strings to match.
578 return RISCV::V13; // "v13"
579 case '4': // 12 strings to match.
580 return RISCV::V14; // "v14"
581 case '5': // 8 strings to match.
582 return RISCV::V15; // "v15"
583 case '6': // 15 strings to match.
584 return RISCV::V16; // "v16"
585 case '7': // 8 strings to match.
586 return RISCV::V17; // "v17"
587 case '8': // 12 strings to match.
588 return RISCV::V18; // "v18"
589 case '9': // 8 strings to match.
590 return RISCV::V19; // "v19"
591 }
592 break;
593 case '2': // 88 strings to match.
594 switch (Name[2]) {
595 default: break;
596 case '0': // 14 strings to match.
597 return RISCV::V20; // "v20"
598 case '1': // 8 strings to match.
599 return RISCV::V21; // "v21"
600 case '2': // 12 strings to match.
601 return RISCV::V22; // "v22"
602 case '3': // 8 strings to match.
603 return RISCV::V23; // "v23"
604 case '4': // 15 strings to match.
605 return RISCV::V24; // "v24"
606 case '5': // 7 strings to match.
607 return RISCV::V25; // "v25"
608 case '6': // 9 strings to match.
609 return RISCV::V26; // "v26"
610 case '7': // 5 strings to match.
611 return RISCV::V27; // "v27"
612 case '8': // 7 strings to match.
613 return RISCV::V28; // "v28"
614 case '9': // 3 strings to match.
615 return RISCV::V29; // "v29"
616 }
617 break;
618 case '3': // 4 strings to match.
619 switch (Name[2]) {
620 default: break;
621 case '0': // 3 strings to match.
622 return RISCV::V30; // "v30"
623 case '1': // 1 string to match.
624 return RISCV::V31; // "v31"
625 }
626 break;
627 }
628 break;
629 case 'x': // 99 strings to match.
630 switch (Name[1]) {
631 default: break;
632 case '1': // 45 strings to match.
633 switch (Name[2]) {
634 default: break;
635 case '0': // 5 strings to match.
636 return RISCV::X10; // "x10"
637 case '1': // 4 strings to match.
638 return RISCV::X11; // "x11"
639 case '2': // 5 strings to match.
640 return RISCV::X12; // "x12"
641 case '3': // 4 strings to match.
642 return RISCV::X13; // "x13"
643 case '4': // 5 strings to match.
644 return RISCV::X14; // "x14"
645 case '5': // 4 strings to match.
646 return RISCV::X15; // "x15"
647 case '6': // 5 strings to match.
648 return RISCV::X16; // "x16"
649 case '7': // 4 strings to match.
650 return RISCV::X17; // "x17"
651 case '8': // 5 strings to match.
652 return RISCV::X18; // "x18"
653 case '9': // 4 strings to match.
654 return RISCV::X19; // "x19"
655 }
656 break;
657 case '2': // 45 strings to match.
658 switch (Name[2]) {
659 default: break;
660 case '0': // 5 strings to match.
661 return RISCV::X20; // "x20"
662 case '1': // 4 strings to match.
663 return RISCV::X21; // "x21"
664 case '2': // 5 strings to match.
665 return RISCV::X22; // "x22"
666 case '3': // 4 strings to match.
667 return RISCV::X23; // "x23"
668 case '4': // 5 strings to match.
669 return RISCV::X24; // "x24"
670 case '5': // 4 strings to match.
671 return RISCV::X25; // "x25"
672 case '6': // 5 strings to match.
673 return RISCV::X26; // "x26"
674 case '7': // 4 strings to match.
675 return RISCV::X27; // "x27"
676 case '8': // 5 strings to match.
677 return RISCV::X28; // "x28"
678 case '9': // 4 strings to match.
679 return RISCV::X29; // "x29"
680 }
681 break;
682 case '3': // 9 strings to match.
683 switch (Name[2]) {
684 default: break;
685 case '0': // 5 strings to match.
686 return RISCV::X30; // "x30"
687 case '1': // 4 strings to match.
688 return RISCV::X31; // "x31"
689 }
690 break;
691 }
692 break;
693 }
694 break;
695 case 4: // 8 strings to match.
696 switch (Name[0]) {
697 default: break;
698 case 'f': // 1 string to match.
699 if (memcmp(Name.data()+1, "csr", 3) != 0)
700 break;
701 return RISCV::FCSR; // "fcsr"
702 case 'm': // 6 strings to match.
703 if (memcmp(Name.data()+1, "t1", 2) != 0)
704 break;
705 switch (Name[3]) {
706 default: break;
707 case '0': // 1 string to match.
708 return RISCV::T10; // "mt10"
709 case '1': // 1 string to match.
710 return RISCV::T11; // "mt11"
711 case '2': // 1 string to match.
712 return RISCV::T12; // "mt12"
713 case '3': // 1 string to match.
714 return RISCV::T13; // "mt13"
715 case '4': // 1 string to match.
716 return RISCV::T14; // "mt14"
717 case '5': // 1 string to match.
718 return RISCV::T15; // "mt15"
719 }
720 break;
721 case 'v': // 1 string to match.
722 if (memcmp(Name.data()+1, "xrm", 3) != 0)
723 break;
724 return RISCV::VXRM; // "vxrm"
725 }
726 break;
727 case 5: // 3 strings to match.
728 if (Name[0] != 'v')
729 break;
730 switch (Name[1]) {
731 default: break;
732 case 'l': // 1 string to match.
733 if (memcmp(Name.data()+2, "enb", 3) != 0)
734 break;
735 return RISCV::VLENB; // "vlenb"
736 case 't': // 1 string to match.
737 if (memcmp(Name.data()+2, "ype", 3) != 0)
738 break;
739 return RISCV::VTYPE; // "vtype"
740 case 'x': // 1 string to match.
741 if (memcmp(Name.data()+2, "sat", 3) != 0)
742 break;
743 return RISCV::VXSAT; // "vxsat"
744 }
745 break;
746 case 6: // 1 string to match.
747 if (memcmp(Name.data()+0, "fflags", 6) != 0)
748 break;
749 return RISCV::FFLAGS; // "fflags"
750 case 13: // 1 string to match.
751 if (memcmp(Name.data()+0, "sf.vcix_state", 13) != 0)
752 break;
753 return RISCV::SF_VCIX_STATE; // "sf.vcix_state"
754 }
755 return RISCV::NoRegister;
756}
757
758[[maybe_unused]] static MCRegister MatchRegisterAltName(StringRef Name) {
759 switch (Name.size()) {
760 default: break;
761 case 2: // 143 strings to match.
762 switch (Name[0]) {
763 default: break;
764 case 'a': // 36 strings to match.
765 switch (Name[1]) {
766 default: break;
767 case '0': // 5 strings to match.
768 return RISCV::X10; // "a0"
769 case '1': // 4 strings to match.
770 return RISCV::X11; // "a1"
771 case '2': // 5 strings to match.
772 return RISCV::X12; // "a2"
773 case '3': // 4 strings to match.
774 return RISCV::X13; // "a3"
775 case '4': // 5 strings to match.
776 return RISCV::X14; // "a4"
777 case '5': // 4 strings to match.
778 return RISCV::X15; // "a5"
779 case '6': // 5 strings to match.
780 return RISCV::X16; // "a6"
781 case '7': // 4 strings to match.
782 return RISCV::X17; // "a7"
783 }
784 break;
785 case 'f': // 5 strings to match.
786 if (Name[1] != 'p')
787 break;
788 return RISCV::X8; // "fp"
789 case 'g': // 4 strings to match.
790 if (Name[1] != 'p')
791 break;
792 return RISCV::X3; // "gp"
793 case 'm': // 8 strings to match.
794 switch (Name[1]) {
795 default: break;
796 case '0': // 1 string to match.
797 return RISCV::M0; // "m0"
798 case '1': // 1 string to match.
799 return RISCV::M1; // "m1"
800 case '2': // 1 string to match.
801 return RISCV::M2; // "m2"
802 case '3': // 1 string to match.
803 return RISCV::M3; // "m3"
804 case '4': // 1 string to match.
805 return RISCV::M4; // "m4"
806 case '5': // 1 string to match.
807 return RISCV::M5; // "m5"
808 case '6': // 1 string to match.
809 return RISCV::M6; // "m6"
810 case '7': // 1 string to match.
811 return RISCV::M7; // "m7"
812 }
813 break;
814 case 'r': // 4 strings to match.
815 if (Name[1] != 'a')
816 break;
817 return RISCV::X1; // "ra"
818 case 's': // 50 strings to match.
819 switch (Name[1]) {
820 default: break;
821 case '0': // 5 strings to match.
822 return RISCV::X8; // "s0"
823 case '1': // 4 strings to match.
824 return RISCV::X9; // "s1"
825 case '2': // 5 strings to match.
826 return RISCV::X18; // "s2"
827 case '3': // 4 strings to match.
828 return RISCV::X19; // "s3"
829 case '4': // 5 strings to match.
830 return RISCV::X20; // "s4"
831 case '5': // 4 strings to match.
832 return RISCV::X21; // "s5"
833 case '6': // 5 strings to match.
834 return RISCV::X22; // "s6"
835 case '7': // 4 strings to match.
836 return RISCV::X23; // "s7"
837 case '8': // 5 strings to match.
838 return RISCV::X24; // "s8"
839 case '9': // 4 strings to match.
840 return RISCV::X25; // "s9"
841 case 'p': // 5 strings to match.
842 return RISCV::X2; // "sp"
843 }
844 break;
845 case 't': // 36 strings to match.
846 switch (Name[1]) {
847 default: break;
848 case '0': // 4 strings to match.
849 return RISCV::X5; // "t0"
850 case '1': // 5 strings to match.
851 return RISCV::X6; // "t1"
852 case '2': // 4 strings to match.
853 return RISCV::X7; // "t2"
854 case '3': // 5 strings to match.
855 return RISCV::X28; // "t3"
856 case '4': // 4 strings to match.
857 return RISCV::X29; // "t4"
858 case '5': // 5 strings to match.
859 return RISCV::X30; // "t5"
860 case '6': // 4 strings to match.
861 return RISCV::X31; // "t6"
862 case 'p': // 5 strings to match.
863 return RISCV::X4; // "tp"
864 }
865 break;
866 }
867 break;
868 case 3: // 149 strings to match.
869 switch (Name[0]) {
870 default: break;
871 case 'f': // 140 strings to match.
872 switch (Name[1]) {
873 default: break;
874 case 'a': // 40 strings to match.
875 switch (Name[2]) {
876 default: break;
877 case '0': // 5 strings to match.
878 return RISCV::F10_D; // "fa0"
879 case '1': // 5 strings to match.
880 return RISCV::F11_D; // "fa1"
881 case '2': // 5 strings to match.
882 return RISCV::F12_D; // "fa2"
883 case '3': // 5 strings to match.
884 return RISCV::F13_D; // "fa3"
885 case '4': // 5 strings to match.
886 return RISCV::F14_D; // "fa4"
887 case '5': // 5 strings to match.
888 return RISCV::F15_D; // "fa5"
889 case '6': // 5 strings to match.
890 return RISCV::F16_D; // "fa6"
891 case '7': // 5 strings to match.
892 return RISCV::F17_D; // "fa7"
893 }
894 break;
895 case 's': // 50 strings to match.
896 switch (Name[2]) {
897 default: break;
898 case '0': // 5 strings to match.
899 return RISCV::F8_D; // "fs0"
900 case '1': // 5 strings to match.
901 return RISCV::F9_D; // "fs1"
902 case '2': // 5 strings to match.
903 return RISCV::F18_D; // "fs2"
904 case '3': // 5 strings to match.
905 return RISCV::F19_D; // "fs3"
906 case '4': // 5 strings to match.
907 return RISCV::F20_D; // "fs4"
908 case '5': // 5 strings to match.
909 return RISCV::F21_D; // "fs5"
910 case '6': // 5 strings to match.
911 return RISCV::F22_D; // "fs6"
912 case '7': // 5 strings to match.
913 return RISCV::F23_D; // "fs7"
914 case '8': // 5 strings to match.
915 return RISCV::F24_D; // "fs8"
916 case '9': // 5 strings to match.
917 return RISCV::F25_D; // "fs9"
918 }
919 break;
920 case 't': // 50 strings to match.
921 switch (Name[2]) {
922 default: break;
923 case '0': // 5 strings to match.
924 return RISCV::F0_D; // "ft0"
925 case '1': // 5 strings to match.
926 return RISCV::F1_D; // "ft1"
927 case '2': // 5 strings to match.
928 return RISCV::F2_D; // "ft2"
929 case '3': // 5 strings to match.
930 return RISCV::F3_D; // "ft3"
931 case '4': // 5 strings to match.
932 return RISCV::F4_D; // "ft4"
933 case '5': // 5 strings to match.
934 return RISCV::F5_D; // "ft5"
935 case '6': // 5 strings to match.
936 return RISCV::F6_D; // "ft6"
937 case '7': // 5 strings to match.
938 return RISCV::F7_D; // "ft7"
939 case '8': // 5 strings to match.
940 return RISCV::F28_D; // "ft8"
941 case '9': // 5 strings to match.
942 return RISCV::F29_D; // "ft9"
943 }
944 break;
945 }
946 break;
947 case 's': // 9 strings to match.
948 if (Name[1] != '1')
949 break;
950 switch (Name[2]) {
951 default: break;
952 case '0': // 5 strings to match.
953 return RISCV::X26; // "s10"
954 case '1': // 4 strings to match.
955 return RISCV::X27; // "s11"
956 }
957 break;
958 }
959 break;
960 case 4: // 26 strings to match.
961 switch (Name[0]) {
962 default: break;
963 case 'f': // 20 strings to match.
964 switch (Name[1]) {
965 default: break;
966 case 's': // 10 strings to match.
967 if (Name[2] != '1')
968 break;
969 switch (Name[3]) {
970 default: break;
971 case '0': // 5 strings to match.
972 return RISCV::F26_D; // "fs10"
973 case '1': // 5 strings to match.
974 return RISCV::F27_D; // "fs11"
975 }
976 break;
977 case 't': // 10 strings to match.
978 if (Name[2] != '1')
979 break;
980 switch (Name[3]) {
981 default: break;
982 case '0': // 5 strings to match.
983 return RISCV::F30_D; // "ft10"
984 case '1': // 5 strings to match.
985 return RISCV::F31_D; // "ft11"
986 }
987 break;
988 }
989 break;
990 case 'n': // 1 string to match.
991 if (memcmp(Name.data()+1, "ull", 3) != 0)
992 break;
993 return RISCV::X0_Y; // "null"
994 case 'z': // 5 strings to match.
995 if (memcmp(Name.data()+1, "ero", 3) != 0)
996 break;
997 return RISCV::X0; // "zero"
998 }
999 break;
1000 }
1001 return RISCV::NoRegister;
1002}
1003
1004#endif // GET_REGISTER_MATCHER
1005
1006
1007#ifdef GET_SUBTARGET_FEATURE_NAME
1008#undef GET_SUBTARGET_FEATURE_NAME
1009
1010// User-level names for subtarget features that participate in
1011// instruction matching.
1012static const char *getSubtargetFeatureName(uint64_t Val) {
1013 switch(Val) {
1014 case Feature_HasStdExtZibiBit: return "'Zibi' (Branch with Immediate)";
1015 case Feature_HasStdExtZicbomBit: return "'Zicbom' (Cache-Block Management Instructions)";
1016 case Feature_HasStdExtZicbopBit: return "'Zicbop' (Cache-Block Prefetch Instructions)";
1017 case Feature_HasStdExtZicbozBit: return "'Zicboz' (Cache-Block Zero Instructions)";
1018 case Feature_HasStdExtZicsrBit: return "'Zicsr' (CSRs)";
1019 case Feature_HasStdExtZicondBit: return "(Integer Conditional Operations)";
1020 case Feature_HasStdExtZifenceiBit: return "'Zifencei' (fence.i)";
1021 case Feature_HasStdExtZihintpauseBit: return "'Zihintpause' (Pause Hint)";
1022 case Feature_HasStdExtZihintntlBit: return "'Zihintntl' (Non-Temporal Locality Hints)";
1023 case Feature_HasStdExtZimopBit: return "'Zimop' (May-Be-Operations)";
1024 case Feature_HasStdExtZicfissBit: return "'Zicfiss' (Shadow stack)";
1025 case Feature_HasStdExtZilsdBit: return "'Zilsd' (Load/Store pair instructions)";
1026 case Feature_HasStdExtZilxBit: return "'Zilx' (Indexed Integer Load Instructions)";
1027 case Feature_HasStdExtZmmulBit: return "'Zmmul' (Integer Multiplication)";
1028 case Feature_HasStdExtMBit: return "'M' (Integer Multiplication and Division)";
1029 case Feature_HasStdExtZaamoBit: return "'Zaamo' (Atomic Memory Operations)";
1030 case Feature_HasStdExtZalrscBit: return "'Zalrsc' (Load-Reserved/Store-Conditional)";
1031 case Feature_HasStdExtABit: return "'A' (Atomic Instructions)";
1032 case Feature_HasStdExtZtsoBit: return "'Ztso' (Memory Model - Total Store Order)";
1033 case Feature_HasStdExtZabhaBit: return "'Zabha' (Byte and Halfword Atomic Memory Operations)";
1034 case Feature_HasStdExtZacasBit: return "'Zacas' (Atomic Compare-And-Swap Instructions)";
1035 case Feature_HasStdExtZalasrBit: return "'Zalasr' (Load-Acquire and Store-Release Instructions)";
1036 case Feature_HasStdExtZawrsBit: return "'Zawrs' (Wait on Reservation Set)";
1037 case Feature_HasStdExtFBit: return "'F' (Single-Precision Floating-Point)";
1038 case Feature_HasStdExtDBit: return "'D' (Double-Precision Floating-Point)";
1039 case Feature_HasStdExtQBit: return "'Q' (Quad-Precision Floating-Point)";
1040 case Feature_HasStdExtZfhminBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)";
1041 case Feature_HasStdExtZfhBit: return "'Zfh' (Half-Precision Floating-Point)";
1042 case Feature_HasStdExtZfbfminBit: return "'Zfbfmin' (Scalar BF16 Converts)";
1043 case Feature_HasHalfFPLoadStoreMoveBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts)";
1044 case Feature_HasStdExtZfaBit: return "'Zfa' (Additional Floating-Point)";
1045 case Feature_HasStdExtZfinxBit: return "'Zfinx' (Float in Integer)";
1046 case Feature_HasStdExtFOrZfinxBit: return "'F' (Single-Precision Floating-Point) or 'Zfinx' (Float in Integer)";
1047 case Feature_HasStdExtZdinxBit: return "'Zdinx' (Double in Integer)";
1048 case Feature_HasStdExtZhinxminBit: return "'Zhinx' (Half Float in Integer) or 'Zhinxmin' (Half Float in Integer Minimal)";
1049 case Feature_HasStdExtZhinxBit: return "'Zhinx' (Half Float in Integer)";
1050 case Feature_HasStdExtZcaBit: return "'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores)";
1051 case Feature_HasStdExtZcbBit: return "'Zcb' (Compressed basic bit manipulation instructions)";
1052 case Feature_HasStdExtZcfBit: return "'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions)";
1053 case Feature_HasStdExtZcdBit: return "'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions)";
1054 case Feature_HasStdExtZclsdBit: return "'Zclsd' (Compressed Load/Store pair instructions)";
1055 case Feature_HasStdExtZcmpBit: return "'Zcmp' (sequenced instructions for code-size reduction)";
1056 case Feature_HasStdExtZcmtBit: return "'Zcmt' (table jump instructions for code-size reduction)";
1057 case Feature_HasStdExtZcmopBit: return "'Zcmop' (Compressed May-Be-Operations)";
1058 case Feature_HasStdExtZbaBit: return "'Zba' (Address Generation Instructions)";
1059 case Feature_HasStdExtZbbBit: return "'Zbb' (Basic Bit-Manipulation)";
1060 case Feature_NoStdExtZbbBit: return "";
1061 case Feature_HasStdExtZbsBit: return "'Zbs' (Single-Bit Instructions)";
1062 case Feature_HasStdExtZbkbBit: return "'Zbkb' (Bitmanip instructions for Cryptography)";
1063 case Feature_NoStdExtZbkbBit: return "";
1064 case Feature_HasStdExtZbkxBit: return "'Zbkx' (Crossbar permutation instructions)";
1065 case Feature_HasStdExtZbbOrZbkbBit: return "'Zbb' (Basic Bit-Manipulation) or 'Zbkb' (Bitmanip instructions for Cryptography)";
1066 case Feature_HasStdExtZbkcBit: return "'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography)";
1067 case Feature_HasStdExtZbcBit: return "'Zbc' (Carry-Less Multiplication)";
1068 case Feature_HasStdExtZkndBit: return "'Zknd' (NIST Suite: AES Decryption)";
1069 case Feature_HasStdExtZkneBit: return "'Zkne' (NIST Suite: AES Encryption)";
1070 case Feature_HasStdExtZkndOrZkneBit: return "'Zknd' (NIST Suite: AES Decryption) or 'Zkne' (NIST Suite: AES Encryption)";
1071 case Feature_HasStdExtZknhBit: return "'Zknh' (NIST Suite: Hash Function Instructions)";
1072 case Feature_HasStdExtZksedBit: return "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)";
1073 case Feature_HasStdExtZkshBit: return "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)";
1074 case Feature_HasStdExtZkrBit: return "'Zkr' (Entropy Source Extension)";
1075 case Feature_HasStdExtZvabdBit: return "'Zvabd' (Vector Absolute Difference)";
1076 case Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit: return "'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Product)";
1077 case Feature_HasStdExtZvfwdota16bfBit: return "'Zvfwdota16bf' (BF16 Dot-Product)";
1078 case Feature_HasStdExtZvfqwdota8fBit: return "'Zvfqwdota8f' (OCP FP8 Dot-Product)";
1079 case Feature_HasStdExtZvfbfminBit: return "'Zvfbfmin' (Vector BF16 Converts)";
1080 case Feature_HasStdExtZvfbfwmaBit: return "'Zvfbfwma' (Vector BF16 widening mul-add)";
1081 case Feature_HasStdExtZfhOrZvfhBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zvfh' (Vector Half-Precision Floating-Point)";
1082 case Feature_HasStdExtZvfofp8minBit: return "'Zvfofp8min' (Vector OFP8 Converts)";
1083 case Feature_HasStdExtZvfbfminOrZvfofp8minBit: return "'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts)";
1084 case Feature_HasStdExtZvkbBit: return "'Zvkb' (Vector Bit-manipulation used in Cryptography)";
1085 case Feature_HasStdExtZvbbBit: return "'Zvbb' (Vector basic bit-manipulation instructions)";
1086 case Feature_HasStdExtZvbcBit: return "'Zvbc' (Vector Carryless Multiplication)";
1087 case Feature_HasStdExtZvbcOrZvbc32eBit: return "'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)";
1088 case Feature_HasStdExtZvkgBit: return "'Zvkg' (Vector GCM instructions for Cryptography)";
1089 case Feature_HasStdExtZvkgsBit: return "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)";
1090 case Feature_HasStdExtZvknedBit: return "'Zvkned' (Vector AES Encryption & Decryption (Single Round))";
1091 case Feature_HasStdExtZvknhaBit: return "'Zvknha' (Vector SHA-2 (SHA-256 only))";
1092 case Feature_HasStdExtZvknhbBit: return "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))";
1093 case Feature_HasStdExtZvksedBit: return "'Zvksed' (SM4 Block Cipher Instructions)";
1094 case Feature_HasStdExtZvkshBit: return "'Zvksh' (SM3 Hash Function Instructions)";
1095 case Feature_HasStdExtZvdot4a8iBit: return "'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers)";
1096 case Feature_HasStdExtZvzipBit: return "'Zvzip' (Vector Reordering Structured Data)";
1097 case Feature_HasStdExtZvvmmBit: return "'Zvvmm' (Integer Matrix Multiply-Accumulate)";
1098 case Feature_HasStdExtZvvfmmBit: return "'Zvvfmm' (Floating-Point Matrix Multiply-Accumulate)";
1099 case Feature_HasStdExtZvvmtlsBit: return "'Zvvmtls' (Matrix Tile Load/Store)";
1100 case Feature_HasStdExtZvvmttlsBit: return "'Zvvmttls' (Transposing Matrix Tile Load/Store)";
1101 case Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit: return "'Zvqwbdota8i' or 'Zvqwbdota16i' (8-bit or 16-bit integer batched dot-product extension)";
1102 case Feature_HasStdExtZvfwbdota16bfBit: return "'Zvfwbdota16bf' (BF16 batched dot-product extension)";
1103 case Feature_HasStdExtZvfqwbdota8fBit: return "'Zvfqwbdota8f' (OCP FP8 batched dot-product extension)";
1104 case Feature_HasStdExtZvfbdota32fBit: return "'Zvfbdota32f' (FP32 batched dot-product extension)";
1105 case Feature_HasVInstructionsBit: return "'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors)";
1106 case Feature_HasVInstructionsI64Bit: return "'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors)";
1107 case Feature_HasVInstructionsAnyFBit: return "'V' (Vector Extension for Application Processors), 'Zve32f' (Vector Extensions for Embedded Processors)";
1108 case Feature_HasVInstructionsF16MinimalBit: return "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or 'Zvfh' (Vector Half-Precision Floating-Point)";
1109 case Feature_HasStdExtHBit: return "'H' (Hypervisor)";
1110 case Feature_HasStdExtSmcspsBit: return "'Smcsps' (Conditional Stack Pointer Swap at Machine Level)";
1111 case Feature_HasStdExtSscspsBit: return "'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level)";
1112 case Feature_HasStdExtSmipBit: return "'Smip' (Support for Interrupt Handler Push/Pop at Machine Level)";
1113 case Feature_HasStdExtSsipBit: return "'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level)";
1114 case Feature_HasStdExtSmrnmiBit: return "'Smrnmi' (Resumable Non-Maskable Interrupts)";
1115 case Feature_HasStdExtSvinvalBit: return "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)";
1116 case Feature_HasStdExtSmctrOrSsctrBit: return "'Smctr' (Control Transfer Records Machine Level) or 'Ssctr' (Control Transfer Records Supervisor Level)";
1117 case Feature_HasStdExtPBit: return "'Base P' (Packed SIMD)";
1118 case Feature_HasStdExtZbkbOrPBit: return "'Zbkb' (Bitmanip instructions for Cryptography) or 'Base P' (Packed-SIMD)";
1119 case Feature_HasStdExtYBit: return "'Base Y' (CHERI)";
1120 case Feature_HasVendorXTHeadBaBit: return "'XTHeadBa' (T-Head address calculation instructions)";
1121 case Feature_HasVendorXTHeadBbBit: return "'XTHeadBb' (T-Head basic bit-manipulation instructions)";
1122 case Feature_HasVendorXTHeadBsBit: return "'XTHeadBs' (T-Head single-bit instructions)";
1123 case Feature_HasVendorXTHeadCondMovBit: return "'XTHeadCondMov' (T-Head conditional move instructions)";
1124 case Feature_HasVendorXTHeadCmoBit: return "'XTHeadCmo' (T-Head cache management instructions)";
1125 case Feature_HasVendorXTHeadFMemIdxBit: return "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)";
1126 case Feature_HasVendorXTHeadMacBit: return "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)";
1127 case Feature_HasVendorXTHeadMemIdxBit: return "'XTHeadMemIdx' (T-Head Indexed Memory Operations)";
1128 case Feature_HasVendorXTHeadMemPairBit: return "'XTHeadMemPair' (T-Head two-GPR Memory Operations)";
1129 case Feature_HasVendorXTHeadSyncBit: return "'XTHeadSync' (T-Head multicore synchronization instructions)";
1130 case Feature_HasVendorXTHeadVdotBit: return "'XTHeadVdot' (T-Head Vector Extensions for Dot)";
1131 case Feature_HasVendorXSfvcpBit: return "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)";
1132 case Feature_HasVendorXSfmmbaseBit: return "'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)";
1133 case Feature_HasVendorXSfmm32a8fBit: return "'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)";
1134 case Feature_HasVendorXSfmm32a8iBit: return "'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)";
1135 case Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit: return "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF)), or 'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b), or 'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)";
1136 case Feature_HasVendorXSfvqmaccdodBit: return "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))";
1137 case Feature_HasVendorXSfvqmaccqoqBit: return "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))";
1138 case Feature_HasVendorXSfvfwmaccqqqBit: return "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))";
1139 case Feature_HasVendorXSfvfnrclipxfqfBit: return "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)";
1140 case Feature_HasVendorXSfvfexpAnyBit: return "'Xsfvfbfexp16e', 'Xsfvfexp16e', or 'Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction)";
1141 case Feature_HasVendorXSfvfexpaBit: return "'Xsfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)";
1142 case Feature_HasVendorXSiFivecdiscarddloneBit: return "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)";
1143 case Feature_HasVendorXSiFivecflushdloneBit: return "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)";
1144 case Feature_HasVendorXSfceaseBit: return "'XSfcease' (SiFive sf.cease Instruction)";
1145 case Feature_HasVendorXCVelwBit: return "'XCVelw' (CORE-V Event Load Word)";
1146 case Feature_HasVendorXCVbitmanipBit: return "'XCVbitmanip' (CORE-V Bit Manipulation)";
1147 case Feature_HasVendorXCVmacBit: return "'XCVmac' (CORE-V Multiply-Accumulate)";
1148 case Feature_HasVendorXCVmemBit: return "'XCVmem' (CORE-V Post-incrementing Load & Store)";
1149 case Feature_HasVendorXCValuBit: return "'XCValu' (CORE-V ALU Operations)";
1150 case Feature_HasVendorXCVsimdBit: return "'XCVsimd' (CORE-V SIMD ALU)";
1151 case Feature_HasVendorXCVbiBit: return "'XCVbi' (CORE-V Immediate Branching)";
1152 case Feature_HasVendorXMIPSCMovBit: return "'Xmipscmov' ('mips.ccmov' instruction)";
1153 case Feature_HasVendorXMIPSLSPBit: return "'Xmipslsp' (load and store pair instructions)";
1154 case Feature_HasVendorXMIPSCBOPBit: return "'Xmipscbop' (MIPS hardware prefetch)";
1155 case Feature_HasVendorXMIPSEXECTLBit: return "'Xmipsexectl' (MIPS execution control)";
1156 case Feature_HasVendorXwchcBit: return "'Xwchc' (WCH/QingKe additional compressed opcodes)";
1157 case Feature_HasVendorXqccmpBit: return "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)";
1158 case Feature_HasVendorXqccmiBit: return "'Xqccmi' (Qualcomm 16-bit Instruction Lookup Table)";
1159 case Feature_HasVendorXqccmtBit: return "'Xqccmt' (Qualcomm 16-bit Table Jump)";
1160 case Feature_HasVendorXqciaBit: return "'Xqcia' (Qualcomm uC Arithmetic Extension)";
1161 case Feature_HasVendorXqciacBit: return "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)";
1162 case Feature_HasVendorXqcibiBit: return "'Xqcibi' (Qualcomm uC Branch Immediate Extension)";
1163 case Feature_HasVendorXqcibmBit: return "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)";
1164 case Feature_HasVendorXqcicliBit: return "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)";
1165 case Feature_HasVendorXqcicmBit: return "'Xqcicm' (Qualcomm uC Conditional Move Extension)";
1166 case Feature_HasVendorXqcicsBit: return "'Xqcics' (Qualcomm uC Conditional Select Extension)";
1167 case Feature_HasVendorXqcicsrBit: return "'Xqcicsr' (Qualcomm uC CSR Extension)";
1168 case Feature_HasVendorXqciintBit: return "'Xqciint' (Qualcomm uC Interrupts Extension)";
1169 case Feature_HasVendorXqciioBit: return "'Xqciio' (Qualcomm uC External Input Output Extension)";
1170 case Feature_HasVendorXqcilbBit: return "'Xqcilb' (Qualcomm uC Long Branch Extension)";
1171 case Feature_HasVendorXqciliBit: return "'Xqcili' (Qualcomm uC Load Large Immediate Extension)";
1172 case Feature_HasVendorXqciliaBit: return "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)";
1173 case Feature_HasVendorXqciloBit: return "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)";
1174 case Feature_HasVendorXqcilsmBit: return "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)";
1175 case Feature_HasVendorXqcisimBit: return "'Xqcisim' (Qualcomm uC Simulation Hint Extension)";
1176 case Feature_HasVendorXqcislsBit: return "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)";
1177 case Feature_HasVendorXqcisyncBit: return "'Xqcisync' (Qualcomm uC Sync Delay Extension)";
1178 case Feature_HasVendorXAndesPerfBit: return "'XAndesPerf' (Andes Performance Extension)";
1179 case Feature_HasVendorXAndesBFHCvtBit: return "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)";
1180 case Feature_HasVendorXAndesVBFHCvtBit: return "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)";
1181 case Feature_HasVendorXAndesVSIntHBit: return "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)";
1182 case Feature_HasVendorXAndesVSIntLoadBit: return "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)";
1183 case Feature_HasVendorXAndesVPackFPHBit: return "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)";
1184 case Feature_HasVendorXAndesVDotBit: return "'XAndesVDot' (Andes Vector Dot Product Extension)";
1185 case Feature_HasVendorXSMTVDotBit: return "'XSMTVDot' (SpacemiT Vector Dot Product Extension)";
1186 case Feature_HasVendorXSMTVDotIIBit: return "'XSMTVDotII' (SpacemiT Vector Extension for Matrix 2.0)";
1187 case Feature_HasXAIFETBit: return "'XAIFET' (AI Foundry ET Extension)";
1188 case Feature_HasCheriotBit: return "'XCheriot' (CHERIoT Extension)";
1189 case Feature_IsRV64Bit: return "RV64I Base Instruction Set";
1190 case Feature_IsRV32Bit: return "RV32I Base Instruction Set";
1191 default: return "(unknown)";
1192 }
1193}
1194
1195#endif // GET_SUBTARGET_FEATURE_NAME
1196
1197
1198#ifdef GET_MATCHER_IMPLEMENTATION
1199#undef GET_MATCHER_IMPLEMENTATION
1200
1201static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
1202 switch (Mnemonic.size()) {
1203 default: break;
1204 case 4: // 3 strings to match.
1205 switch (Mnemonic[0]) {
1206 default: break;
1207 case 'f': // 2 strings to match.
1208 switch (Mnemonic[1]) {
1209 default: break;
1210 case 'r': // 1 string to match.
1211 if (memcmp(Mnemonic.data()+2, "sr", 2) != 0)
1212 break;
1213 if (Features.test(Feature_HasStdExtFOrZfinxBit)) // "frsr"
1214 Mnemonic = "frcsr";
1215 return;
1216 case 's': // 1 string to match.
1217 if (memcmp(Mnemonic.data()+2, "sr", 2) != 0)
1218 break;
1219 if (Features.test(Feature_HasStdExtFOrZfinxBit)) // "fssr"
1220 Mnemonic = "fscsr";
1221 return;
1222 }
1223 break;
1224 case 'm': // 1 string to match.
1225 if (memcmp(Mnemonic.data()+1, "ove", 3) != 0)
1226 break;
1227 Mnemonic = "mv"; // "move"
1228 return;
1229 }
1230 break;
1231 case 5: // 1 string to match.
1232 if (memcmp(Mnemonic.data()+0, "scall", 5) != 0)
1233 break;
1234 Mnemonic = "ecall"; // "scall"
1235 return;
1236 case 6: // 3 strings to match.
1237 switch (Mnemonic[0]) {
1238 default: break;
1239 case 's': // 1 string to match.
1240 if (memcmp(Mnemonic.data()+1, "break", 5) != 0)
1241 break;
1242 Mnemonic = "ebreak"; // "sbreak"
1243 return;
1244 case 'v': // 2 strings to match.
1245 switch (Mnemonic[1]) {
1246 default: break;
1247 case 'l': // 1 string to match.
1248 if (memcmp(Mnemonic.data()+2, "e1.v", 4) != 0)
1249 break;
1250 if (Features.test(Feature_HasVInstructionsBit)) // "vle1.v"
1251 Mnemonic = "vlm.v";
1252 return;
1253 case 's': // 1 string to match.
1254 if (memcmp(Mnemonic.data()+2, "e1.v", 4) != 0)
1255 break;
1256 if (Features.test(Feature_HasVInstructionsBit)) // "vse1.v"
1257 Mnemonic = "vsm.v";
1258 return;
1259 }
1260 break;
1261 }
1262 break;
1263 case 7: // 4 strings to match.
1264 switch (Mnemonic[0]) {
1265 default: break;
1266 case 'c': // 1 string to match.
1267 if (memcmp(Mnemonic.data()+1, "v.slet", 6) != 0)
1268 break;
1269 if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit)) // "cv.slet"
1270 Mnemonic = "cv.sle";
1271 return;
1272 case 'f': // 2 strings to match.
1273 if (memcmp(Mnemonic.data()+1, "mv.", 3) != 0)
1274 break;
1275 switch (Mnemonic[4]) {
1276 default: break;
1277 case 's': // 1 string to match.
1278 if (memcmp(Mnemonic.data()+5, ".x", 2) != 0)
1279 break;
1280 if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x"
1281 Mnemonic = "fmv.w.x";
1282 return;
1283 case 'x': // 1 string to match.
1284 if (memcmp(Mnemonic.data()+5, ".s", 2) != 0)
1285 break;
1286 if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s"
1287 Mnemonic = "fmv.x.w";
1288 return;
1289 }
1290 break;
1291 case 'v': // 1 string to match.
1292 if (memcmp(Mnemonic.data()+1, "popc.m", 6) != 0)
1293 break;
1294 if (Features.test(Feature_HasVInstructionsBit)) // "vpopc.m"
1295 Mnemonic = "vcpop.m";
1296 return;
1297 }
1298 break;
1299 case 8: // 1 string to match.
1300 if (memcmp(Mnemonic.data()+0, "cv.sletu", 8) != 0)
1301 break;
1302 if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit)) // "cv.sletu"
1303 Mnemonic = "cv.sleu";
1304 return;
1305 case 10: // 1 string to match.
1306 if (memcmp(Mnemonic.data()+0, "vmornot.mm", 10) != 0)
1307 break;
1308 if (Features.test(Feature_HasVInstructionsBit)) // "vmornot.mm"
1309 Mnemonic = "vmorn.mm";
1310 return;
1311 case 11: // 2 strings to match.
1312 if (Mnemonic[0] != 'v')
1313 break;
1314 switch (Mnemonic[1]) {
1315 default: break;
1316 case 'f': // 1 string to match.
1317 if (memcmp(Mnemonic.data()+2, "redsum.vs", 9) != 0)
1318 break;
1319 if (Features.test(Feature_HasVInstructionsAnyFBit)) // "vfredsum.vs"
1320 Mnemonic = "vfredusum.vs";
1321 return;
1322 case 'm': // 1 string to match.
1323 if (memcmp(Mnemonic.data()+2, "andnot.mm", 9) != 0)
1324 break;
1325 if (Features.test(Feature_HasVInstructionsBit)) // "vmandnot.mm"
1326 Mnemonic = "vmandn.mm";
1327 return;
1328 }
1329 break;
1330 case 12: // 1 string to match.
1331 if (memcmp(Mnemonic.data()+0, "vfwredsum.vs", 12) != 0)
1332 break;
1333 if (Features.test(Feature_HasVInstructionsAnyFBit)) // "vfwredsum.vs"
1334 Mnemonic = "vfwredusum.vs";
1335 return;
1336 }
1337}
1338
1339enum {
1340 Tie0_1_1,
1341 Tie0_2_2,
1342 Tie0_3_3,
1343 Tie1_3_3,
1344};
1345
1346static const uint8_t TiedAsmOperandTable[][3] = {
1347 /* Tie0_1_1 */ { 0, 1, 1 },
1348 /* Tie0_2_2 */ { 0, 2, 2 },
1349 /* Tie0_3_3 */ { 0, 3, 3 },
1350 /* Tie1_3_3 */ { 1, 3, 3 },
1351};
1352
1353namespace {
1354enum OperatorConversionKind {
1355 CVT_Done,
1356 CVT_Reg,
1357 CVT_Tied,
1358 CVT_95_addImmOperands,
1359 CVT_95_addRegOperands,
1360 CVT_95_addImmOperands_95_defaultZeroOffset,
1361 CVT_95_Reg,
1362 CVT_95_addFRMArgOperands_95_defaultFRMArgOp,
1363 CVT_regX0,
1364 CVT_regX1,
1365 CVT_regX5,
1366 CVT_regX2,
1367 CVT_regX3,
1368 CVT_regX4,
1369 CVT_imm_95_0,
1370 CVT_95_addRegListOperands,
1371 CVT_95_addStackAdjOperands,
1372 CVT_95_addCSRSystemRegisterOperands,
1373 CVT_95_addRegRegOperands,
1374 CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp,
1375 CVT_95_addFRMArgOperands,
1376 CVT_imm_95_15,
1377 CVT_95_addFenceArgOperands,
1378 CVT_95_addFPImmOperands,
1379 CVT_imm_95_3,
1380 CVT_imm_95_1,
1381 CVT_imm_95_2,
1382 CVT_regX0_Pair,
1383 CVT_95_addRegOperands_95_defaultMaskRegOp,
1384 CVT_imm_95__MINUS_1,
1385 CVT_95_addSExtImmOperands_LT_8_GT_,
1386 CVT_95_addSExtImmOperands_LT_10_GT_,
1387 CVT_imm_95_8,
1388 CVT_imm_95_16,
1389 CVT_imm_95_1536,
1390 CVT_imm_95__MINUS_1280,
1391 CVT_imm_95__MINUS_2048,
1392 CVT_imm_95_1792,
1393 CVT_imm_95__MINUS_1792,
1394 CVT_imm_95__MINUS_1536,
1395 CVT_imm_95__MINUS_1024,
1396 CVT_imm_95_3072,
1397 CVT_imm_95_3200,
1398 CVT_imm_95_3074,
1399 CVT_imm_95_3202,
1400 CVT_imm_95_3073,
1401 CVT_imm_95_3201,
1402 CVT_95_addVTypeIOperands,
1403 CVT_95_addSMTVTypeOperand_95_defaultSMTVType,
1404 CVT_reg0,
1405 CVT_imm_95_255,
1406 CVT_NUM_CONVERTERS
1407};
1408
1409enum InstructionConversionKind {
1410 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4,
1411 Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4,
1412 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3,
1413 Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3,
1414 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3,
1415 Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2,
1416 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__OptionalUImm51_3,
1417 Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3,
1418 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__OptionalUImm51_3,
1419 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3,
1420 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4,
1421 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__OptionalSImm12LO1_3,
1422 Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2,
1423 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4,
1424 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5,
1425 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5,
1426 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__OptionalSImm261_4,
1427 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4,
1428 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__OptionalSImm261_4,
1429 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5,
1430 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6,
1431 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__OptionalSImm12LO1_3,
1432 Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2,
1433 Convert__Reg1_0__Reg1_1__Reg1_2,
1434 Convert__Reg1_0__Reg1_1,
1435 Convert__Reg1_0__Reg1_1__SImm12LO1_2,
1436 Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3,
1437 Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2,
1438 Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3,
1439 Convert__Reg1_0__Reg1_1__RnumArg1_2,
1440 Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2,
1441 Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3,
1442 Convert__Reg1_0__Reg1_1__SImm101_2,
1443 Convert__Reg1_0__SImm12LO1_1__Reg1_3,
1444 Convert__Reg1_0__UImm20LUI1_1,
1445 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
1446 Convert__Reg1_0__Reg1_1__FRMArg1_2,
1447 Convert__Reg1_0__Reg1_2,
1448 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4,
1449 Convert__Reg1_0__Reg1_1__UImm31_2,
1450 Convert__Reg1_0__Reg1_1__UImm51_2,
1451 Convert__Reg1_0__Reg1_1__UImm81_2,
1452 Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3,
1453 Convert__Reg1_0,
1454 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1,
1455 Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2,
1456 Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2,
1457 Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2,
1458 Convert__Reg1_0__UImm20AUIPC1_1,
1459 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2,
1460 Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2,
1461 Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2,
1462 Convert__Reg1_0__regX0__BareSImm13Lsb01_1,
1463 Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2,
1464 Convert__regX0__Reg1_0__BareSImm13Lsb01_1,
1465 Convert__Reg1_0__Tie0_1_1__Reg1_1,
1466 Convert__Reg1_0__Tie0_1_1__SImm61_1,
1467 Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1,
1468 Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2,
1469 Convert__Reg1_0__BareSImm9Lsb01_1,
1470 Convert_NoOperands,
1471 Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb0001_1,
1472 Convert__Reg1_0__Reg1_3__OptionalUImm9Lsb0001_1,
1473 Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1,
1474 Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb001_1,
1475 Convert__BareSImm12Lsb01_0,
1476 Convert__Reg1_0__Reg1_3__OptionalUImm21_1,
1477 Convert__Reg1_0__Reg1_3__OptionalUImm21_1__QCAccessSymbol1_5,
1478 Convert__GPRPairCRV321_0__Reg1_3__OptionalUImm8Lsb0001_1,
1479 Convert__GPRPairNoX0RV321_0__Reg1_3__OptionalUImm9Lsb0001_1,
1480 Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1,
1481 Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1__QCAccessSymbol1_5,
1482 Convert__Reg1_0__SImm61_1,
1483 Convert__Reg1_0__CLUIImm1_1,
1484 Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1__QCAccessSymbol1_5,
1485 Convert__regX1,
1486 Convert__regX5,
1487 Convert__SImm6NonZero1_0,
1488 Convert__Reg1_0__Tie0_1_1,
1489 Convert__regX0__Tie0_1_1__regX5,
1490 Convert__regX0__Tie0_1_1__regX2,
1491 Convert__regX0__Tie0_1_1__regX3,
1492 Convert__regX0__Tie0_1_1__regX4,
1493 Convert__GPRPairRV321_0__Reg1_3__OptionalUImm9Lsb0001_1,
1494 Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1,
1495 Convert__Reg1_0__Tie0_1_1__imm_95_0,
1496 Convert__CallSymbol1_0,
1497 Convert__Reg1_0__CallSymbol1_1,
1498 Convert__ZeroOffsetMemOpOperand1_0,
1499 Convert__UImm8GE321_0,
1500 Convert__UImm51_0,
1501 Convert__RegList1_0__StackAdj1_1,
1502 Convert__RegList1_0__NegStackAdj1_1,
1503 Convert__regX0__CSRSystemRegister1_0__Reg1_1,
1504 Convert__regX0__CSRSystemRegister1_0__UImm51_1,
1505 Convert__Reg1_0__CSRSystemRegister1_1__regX0,
1506 Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2,
1507 Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2,
1508 Convert__Reg1_0__Reg1_1__SImm61_2,
1509 Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3,
1510 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
1511 Convert__Reg1_0__Reg1_1__UImm61_2,
1512 Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3,
1513 Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2,
1514 Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3,
1515 Convert__Reg1_0__BareSymbol1_1,
1516 Convert__Reg1_0__Reg1_3__SImm12LO1_1,
1517 Convert__Reg1_0__Reg1_1__UImm21_2,
1518 Convert__Reg1_0__Reg1_1__UImm11_2,
1519 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3,
1520 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm21_2,
1521 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm11_2,
1522 Convert__Reg1_0__RegReg2_1,
1523 Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4,
1524 Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4,
1525 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3,
1526 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
1527 Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4,
1528 Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4,
1529 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2,
1530 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2,
1531 Convert__Reg1_0__Reg1_1__UImm41_2,
1532 Convert__Reg1_0__Reg1_1__Reg1_1,
1533 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1,
1534 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1,
1535 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1,
1536 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1,
1537 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3,
1538 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3,
1539 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3,
1540 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3,
1541 Convert__Reg1_0__GPRF64AsFPR1_1,
1542 Convert__Reg1_0__GPRPairAsFPR1_1,
1543 Convert__Reg1_0__GPRAsFPR161_1,
1544 Convert__Reg1_0__GPRAsFPR321_1,
1545 Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2,
1546 Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1547 Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1548 Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2,
1549 Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
1550 Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
1551 Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2,
1552 Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2,
1553 Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2,
1554 Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2,
1555 Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2,
1556 Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2,
1557 Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2,
1558 Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2,
1559 Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2,
1560 Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2,
1561 Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2,
1562 Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1563 Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2,
1564 Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2,
1565 Convert__Reg1_0__Reg1_1__RTZArg1_2,
1566 Convert__imm_95_15__imm_95_15,
1567 Convert__FenceArg1_0__FenceArg1_1,
1568 Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
1569 Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
1570 Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2,
1571 Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2,
1572 Convert__Reg1_0__Reg1_2__Reg1_1,
1573 Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1,
1574 Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1,
1575 Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1,
1576 Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1,
1577 Convert__Reg1_2__Reg1_0__BareSymbol1_1,
1578 Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1,
1579 Convert__Reg1_0__LoadFPImm1_1,
1580 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4,
1581 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4,
1582 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4,
1583 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4,
1584 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
1585 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
1586 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2,
1587 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2,
1588 Convert__Reg1_0__imm_95_3__regX0,
1589 Convert__Reg1_0__imm_95_1__regX0,
1590 Convert__Reg1_0__imm_95_2__regX0,
1591 Convert__regX0__imm_95_3__Reg1_0,
1592 Convert__Reg1_0__imm_95_3__Reg1_1,
1593 Convert__regX0__imm_95_1__Reg1_0,
1594 Convert__Reg1_0__imm_95_1__Reg1_1,
1595 Convert__regX0__imm_95_1__UImm51_0,
1596 Convert__Reg1_0__imm_95_1__UImm51_1,
1597 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2,
1598 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2,
1599 Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2,
1600 Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2,
1601 Convert__regX0__imm_95_2__Reg1_0,
1602 Convert__Reg1_0__imm_95_2__Reg1_1,
1603 Convert__regX0__imm_95_2__UImm51_0,
1604 Convert__Reg1_0__imm_95_2__UImm51_1,
1605 Convert__regX0__regX0,
1606 Convert__Reg1_0__regX0,
1607 Convert__regX0__BareSImm21Lsb01_0,
1608 Convert__regX1__BareSImm21Lsb01_0,
1609 Convert__Reg1_0__BareSImm21Lsb01_1,
1610 Convert__regX1__Reg1_0__imm_95_0,
1611 Convert__Reg1_0__Reg1_1__imm_95_0,
1612 Convert__regX1__Reg1_0__SImm12LO1_1,
1613 Convert__regX1__Reg1_2__OptionalSImm12LO1_0,
1614 Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5,
1615 Convert__regX0__Reg1_0__imm_95_0,
1616 Convert__regX0__Reg1_0__SImm12LO1_1,
1617 Convert__regX0__Reg1_2__OptionalSImm12LO1_0,
1618 Convert__Reg1_1__PseudoJumpSymbol1_0,
1619 Convert__Reg1_0__ImmXLenLI_Restricted1_1,
1620 Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5,
1621 Convert__GPRPairNoX0RV321_0__BareSymbol1_1,
1622 Convert__GPRPairRV321_0__Reg1_3__OptionalSImm12LO1_1,
1623 Convert__Reg1_0__regX0__SImm12LO1_1,
1624 Convert__Reg1_0__ImmXLenLI1_1,
1625 Convert__regX0__UImm201_0,
1626 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2,
1627 Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3,
1628 Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2,
1629 Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2,
1630 Convert__Reg1_3__UImm91_1__UImm51_0,
1631 Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2,
1632 Convert__Reg1_0__Reg1_1__regX0,
1633 Convert__Reg1_0__regX0__Reg1_1,
1634 Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1,
1635 Convert__Reg1_0__GPRPairRV321_1__Reg1_2,
1636 Convert__Reg1_0__GPRPairRV321_1__UImm61_2,
1637 Convert__Reg1_0__SImm181_1,
1638 Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2,
1639 Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2,
1640 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3,
1641 Convert__Reg1_0__SImm20Lsb0001_1,
1642 Convert__Reg1_0__SImm18Lsb01_1,
1643 Convert__Reg1_0__SImm19Lsb001_1,
1644 Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1645 Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3,
1646 Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2,
1647 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2,
1648 Convert__regX0__regX0__imm_95_0,
1649 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1,
1650 Convert__regX0__regX0__regX5,
1651 Convert__regX0__regX0__regX2,
1652 Convert__regX0__regX0__regX3,
1653 Convert__regX0__regX0__regX4,
1654 Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair,
1655 Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2,
1656 Convert__imm_95_1__imm_95_0,
1657 Convert__Reg1_0__SImm8PLI_B1_1,
1658 Convert__GPRPairRV321_0__SImm8PLI_B1_1,
1659 Convert__GPRPairRV321_0__SImm10PLI_H1_1,
1660 Convert__Reg1_0__SImm10PLI_H1_1,
1661 Convert__Reg1_0__SImm10PLI_W1_1,
1662 Convert__GPRPairRV321_0__SImm10PLUI1_1,
1663 Convert__Reg1_0__SImm10PLUI1_1,
1664 Convert__GPRPairRV321_0__Reg1_1__Reg1_2,
1665 Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1,
1666 Convert__GPRPairRV321_0__regX0_Pair__Reg1_1,
1667 Convert__Reg1_0__GPRPairRV321_1__UImm41_2,
1668 Convert__Reg1_0__GPRPairRV321_1__UImm51_2,
1669 Convert__Reg1_0__GPRPairRV321_1__imm_95_0,
1670 Convert__Reg1_0__GPRPairRV321_1__imm_95_8,
1671 Convert__Reg1_0__GPRPairRV321_1__imm_95_16,
1672 Convert__Reg1_2__SImm12Lsb000001_0,
1673 Convert__GPRPairRV321_0__GPRPairRV321_1,
1674 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm4Plus11_2,
1675 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm5Plus11_2,
1676 Convert__Reg1_0__Reg1_1__UImm4Plus11_2,
1677 Convert__Reg1_0__Reg1_1__UImm5Plus11_2,
1678 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2,
1679 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2,
1680 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2,
1681 Convert__GPRPairRV321_0__Reg1_1__regX0,
1682 Convert__GPRPairRV321_0__regX0__Reg1_1,
1683 Convert__GPRPairRV321_0__Reg1_1__UImm41_2,
1684 Convert__GPRPairRV321_0__Reg1_1__UImm51_2,
1685 Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2,
1686 Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2,
1687 Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1,
1688 Convert__regX0__Tie0_1_1__UImm5NonZero1_0,
1689 Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1,
1690 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2,
1691 Convert__regX0__Tie0_1_1__imm_95_0,
1692 Convert__UImm5Slist1_0,
1693 Convert__UImm101_0,
1694 Convert__UImm111_0,
1695 Convert__RegListS01_0__NegStackAdj1_1,
1696 Convert__Reg1_0__UImm51_1__Reg1_2,
1697 Convert__Reg1_0__Tie0_1_1__BareSImm321_1,
1698 Convert__Reg1_0__Reg1_1__SImm261_2,
1699 Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2,
1700 Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2,
1701 Convert__BareSImm32Lsb01_0,
1702 Convert__Reg1_0__Reg1_3__OptionalSImm261_1,
1703 Convert__Reg1_0__BareSImm321_1,
1704 Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1,
1705 Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3,
1706 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3,
1707 Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3,
1708 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2,
1709 Convert__Reg1_0__Reg1_3__OptionalUImm14Lsb001_1,
1710 Convert__Reg1_0__SImm20LI1_1,
1711 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3,
1712 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3,
1713 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3,
1714 Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3,
1715 Convert__Reg1_0__Reg1_4__Reg1_1__OptionalUImm7Lsb001_2,
1716 Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__OptionalUImm7Lsb001_2,
1717 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2,
1718 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3,
1719 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3,
1720 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3,
1721 Convert__regX0__regX0__imm_95_1536,
1722 Convert__regX0__Reg1_0__imm_95__MINUS_1280,
1723 Convert__regX0__Reg1_0__imm_95__MINUS_2048,
1724 Convert__regX0__regX0__imm_95_1792,
1725 Convert__regX0__Reg1_0__imm_95__MINUS_1792,
1726 Convert__UImm81_0,
1727 Convert__regX0__Reg1_0__imm_95__MINUS_1536,
1728 Convert__regX0__Reg1_0__imm_95__MINUS_1024,
1729 Convert__regX0__regX0__UImm101_0,
1730 Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3,
1731 Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3,
1732 Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3,
1733 Convert__Reg1_0__Reg1_1__UImm111_2,
1734 Convert__Reg1_0__Reg1_3__OptionalUImm51_1,
1735 Convert__Reg1_0__Reg1_3__OptionalUImm41_1,
1736 Convert__Reg1_0__Reg1_3__OptionalUImm6Lsb01_1,
1737 Convert__Reg1_0__Reg1_3__OptionalUImm5Lsb01_1,
1738 Convert__Reg1_0__imm_95_3072__regX0,
1739 Convert__Reg1_0__imm_95_3200__regX0,
1740 Convert__Reg1_0__imm_95_3074__regX0,
1741 Convert__Reg1_0__imm_95_3202__regX0,
1742 Convert__Reg1_0__imm_95_3073__regX0,
1743 Convert__Reg1_0__imm_95_3201__regX0,
1744 Convert__regX0__regX1__imm_95_0,
1745 Convert__Reg1_0__Reg1_1__UImm6Plus11_2,
1746 Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1,
1747 Convert__Reg1_0__Reg1_1__imm_95_1,
1748 Convert__regX0,
1749 Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3,
1750 Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3,
1751 Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3,
1752 Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3,
1753 Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3,
1754 Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3,
1755 Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3,
1756 Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3,
1757 Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3,
1758 Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3,
1759 Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3,
1760 Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3,
1761 Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3,
1762 Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3,
1763 Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3,
1764 Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3,
1765 Convert__Reg1_0__Reg1_1__XSfmmVType1_2,
1766 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3,
1767 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5,
1768 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5,
1769 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3,
1770 Convert__TailCallSymbol1_0__Reg1_1,
1771 Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5,
1772 Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6,
1773 Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6,
1774 Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5,
1775 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1776 Convert__Reg1_0__Reg1_1__regX0__reg0,
1777 Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2,
1778 Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3,
1779 Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3,
1780 Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3,
1781 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3,
1782 Convert__Reg1_0__Reg1_1__Reg1_1__reg0,
1783 Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2,
1784 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm6Lsb0001_3__RVVMaskRegOpOperand1_4,
1785 Convert__Reg1_0__RVVMaskRegOpOperand1_1,
1786 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1787 Convert__Reg1_0__Reg1_1__SImm51_2,
1788 Convert__Reg1_0__Reg1_0__Reg1_0,
1789 Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3,
1790 Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1791 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3,
1792 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4,
1793 Convert__Reg1_0__SImm51_1,
1794 Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3,
1795 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0,
1796 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2,
1797 Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3,
1798 Convert__Reg1_0__UImm51_1__VTypeI101_2,
1799 Convert__Reg1_0__Reg1_1__VTypeI111_2,
1800 Convert__GPRPairRV321_0__Reg1_1__UImm61_2,
1801 Convert__Reg1_0__Reg1_1__YBNDSWImm1_2,
1802 Convert__Reg1_0__Reg1_1__imm_95_255,
1803 CVT_NUM_SIGNATURES
1804};
1805
1806} // end anonymous namespace
1807
1808static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][15] = {
1809 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4
1810 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1811 // Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4
1812 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_Done },
1813 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3
1814 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1815 // Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3
1816 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
1817 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3
1818 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
1819 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2
1820 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1821 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__OptionalUImm51_3
1822 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands_95_defaultZeroOffset, 4, CVT_Done },
1823 // Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3
1824 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_Done },
1825 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__OptionalUImm51_3
1826 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands_95_defaultZeroOffset, 4, CVT_Done },
1827 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3
1828 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1829 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4
1830 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1831 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__OptionalSImm12LO1_3
1832 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands_95_defaultZeroOffset, 4, CVT_Done },
1833 // Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2
1834 { CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
1835 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4
1836 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
1837 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5
1838 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1839 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5
1840 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1841 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__OptionalSImm261_4
1842 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 7, CVT_95_addImmOperands_95_defaultZeroOffset, 5, CVT_Done },
1843 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4
1844 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1845 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__OptionalSImm261_4
1846 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addRegOperands, 7, CVT_95_addImmOperands_95_defaultZeroOffset, 5, CVT_Done },
1847 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5
1848 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
1849 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6
1850 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_95_addRegOperands, 7, CVT_Done },
1851 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__OptionalSImm12LO1_3
1852 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands_95_defaultZeroOffset, 4, CVT_Done },
1853 // Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2
1854 { CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
1855 // Convert__Reg1_0__Reg1_1__Reg1_2
1856 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1857 // Convert__Reg1_0__Reg1_1
1858 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1859 // Convert__Reg1_0__Reg1_1__SImm12LO1_2
1860 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1861 // Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3
1862 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1863 // Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2
1864 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1865 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3
1866 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1867 // Convert__Reg1_0__Reg1_1__RnumArg1_2
1868 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1869 // Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2
1870 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands, 3, CVT_Done },
1871 // Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3
1872 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
1873 // Convert__Reg1_0__Reg1_1__SImm101_2
1874 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1875 // Convert__Reg1_0__SImm12LO1_1__Reg1_3
1876 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_Done },
1877 // Convert__Reg1_0__UImm20LUI1_1
1878 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1879 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
1880 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
1881 // Convert__Reg1_0__Reg1_1__FRMArg1_2
1882 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
1883 // Convert__Reg1_0__Reg1_2
1884 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
1885 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4
1886 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
1887 // Convert__Reg1_0__Reg1_1__UImm31_2
1888 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1889 // Convert__Reg1_0__Reg1_1__UImm51_2
1890 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1891 // Convert__Reg1_0__Reg1_1__UImm81_2
1892 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1893 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3
1894 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1895 // Convert__Reg1_0
1896 { CVT_95_Reg, 1, CVT_Done },
1897 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1
1898 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
1899 // Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2
1900 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addRegOperands, 3, CVT_Done },
1901 // Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2
1902 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1903 // Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2
1904 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1905 // Convert__Reg1_0__UImm20AUIPC1_1
1906 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1907 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2
1908 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1909 // Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2
1910 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1911 // Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2
1912 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1913 // Convert__Reg1_0__regX0__BareSImm13Lsb01_1
1914 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
1915 // Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2
1916 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },
1917 // Convert__regX0__Reg1_0__BareSImm13Lsb01_1
1918 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1919 // Convert__Reg1_0__Tie0_1_1__Reg1_1
1920 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
1921 // Convert__Reg1_0__Tie0_1_1__SImm61_1
1922 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1923 // Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1
1924 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1925 // Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2
1926 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1927 // Convert__Reg1_0__BareSImm9Lsb01_1
1928 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1929 // Convert_NoOperands
1930 { CVT_Done },
1931 // Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb0001_1
1932 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
1933 // Convert__Reg1_0__Reg1_3__OptionalUImm9Lsb0001_1
1934 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
1935 // Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1
1936 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
1937 // Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb001_1
1938 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
1939 // Convert__BareSImm12Lsb01_0
1940 { CVT_95_addImmOperands, 1, CVT_Done },
1941 // Convert__Reg1_0__Reg1_3__OptionalUImm21_1
1942 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
1943 // Convert__Reg1_0__Reg1_3__OptionalUImm21_1__QCAccessSymbol1_5
1944 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_95_addImmOperands, 6, CVT_Done },
1945 // Convert__GPRPairCRV321_0__Reg1_3__OptionalUImm8Lsb0001_1
1946 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
1947 // Convert__GPRPairNoX0RV321_0__Reg1_3__OptionalUImm9Lsb0001_1
1948 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
1949 // Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1
1950 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
1951 // Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1__QCAccessSymbol1_5
1952 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_95_addImmOperands, 6, CVT_Done },
1953 // Convert__Reg1_0__SImm61_1
1954 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1955 // Convert__Reg1_0__CLUIImm1_1
1956 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1957 // Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1__QCAccessSymbol1_5
1958 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_95_addImmOperands, 6, CVT_Done },
1959 // Convert__regX1
1960 { CVT_regX1, 0, CVT_Done },
1961 // Convert__regX5
1962 { CVT_regX5, 0, CVT_Done },
1963 // Convert__SImm6NonZero1_0
1964 { CVT_95_addImmOperands, 1, CVT_Done },
1965 // Convert__Reg1_0__Tie0_1_1
1966 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1967 // Convert__regX0__Tie0_1_1__regX5
1968 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX5, 0, CVT_Done },
1969 // Convert__regX0__Tie0_1_1__regX2
1970 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX2, 0, CVT_Done },
1971 // Convert__regX0__Tie0_1_1__regX3
1972 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX3, 0, CVT_Done },
1973 // Convert__regX0__Tie0_1_1__regX4
1974 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX4, 0, CVT_Done },
1975 // Convert__GPRPairRV321_0__Reg1_3__OptionalUImm9Lsb0001_1
1976 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
1977 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1
1978 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1979 // Convert__Reg1_0__Tie0_1_1__imm_95_0
1980 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
1981 // Convert__CallSymbol1_0
1982 { CVT_95_addImmOperands, 1, CVT_Done },
1983 // Convert__Reg1_0__CallSymbol1_1
1984 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1985 // Convert__ZeroOffsetMemOpOperand1_0
1986 { CVT_95_addRegOperands, 1, CVT_Done },
1987 // Convert__UImm8GE321_0
1988 { CVT_95_addImmOperands, 1, CVT_Done },
1989 // Convert__UImm51_0
1990 { CVT_95_addImmOperands, 1, CVT_Done },
1991 // Convert__RegList1_0__StackAdj1_1
1992 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
1993 // Convert__RegList1_0__NegStackAdj1_1
1994 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
1995 // Convert__regX0__CSRSystemRegister1_0__Reg1_1
1996 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
1997 // Convert__regX0__CSRSystemRegister1_0__UImm51_1
1998 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1999 // Convert__Reg1_0__CSRSystemRegister1_1__regX0
2000 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_regX0, 0, CVT_Done },
2001 // Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2
2002 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_Reg, 3, CVT_Done },
2003 // Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2
2004 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2005 // Convert__Reg1_0__Reg1_1__SImm61_2
2006 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2007 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3
2008 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2009 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
2010 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2011 // Convert__Reg1_0__Reg1_1__UImm61_2
2012 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2013 // Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3
2014 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2015 // Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2
2016 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2017 // Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3
2018 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2019 // Convert__Reg1_0__BareSymbol1_1
2020 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2021 // Convert__Reg1_0__Reg1_3__SImm12LO1_1
2022 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2023 // Convert__Reg1_0__Reg1_1__UImm21_2
2024 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2025 // Convert__Reg1_0__Reg1_1__UImm11_2
2026 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2027 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3
2028 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2029 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm21_2
2030 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2031 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm11_2
2032 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2033 // Convert__Reg1_0__RegReg2_1
2034 { CVT_95_Reg, 1, CVT_95_addRegRegOperands, 2, CVT_Done },
2035 // Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4
2036 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_Reg, 5, CVT_Done },
2037 // Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4
2038 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_Done },
2039 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3
2040 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2041 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
2042 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
2043 // Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4
2044 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
2045 // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4
2046 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
2047 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2
2048 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2049 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2
2050 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2051 // Convert__Reg1_0__Reg1_1__UImm41_2
2052 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2053 // Convert__Reg1_0__Reg1_1__Reg1_1
2054 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_Done },
2055 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1
2056 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2057 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1
2058 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2059 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1
2060 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2061 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1
2062 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2063 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3
2064 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2065 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3
2066 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2067 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3
2068 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2069 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3
2070 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2071 // Convert__Reg1_0__GPRF64AsFPR1_1
2072 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2073 // Convert__Reg1_0__GPRPairAsFPR1_1
2074 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2075 // Convert__Reg1_0__GPRAsFPR161_1
2076 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2077 // Convert__Reg1_0__GPRAsFPR321_1
2078 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2079 // Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2
2080 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2081 // Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2
2082 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2083 // Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2
2084 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2085 // Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2
2086 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2087 // Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2
2088 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2089 // Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2
2090 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2091 // Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2
2092 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2093 // Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2
2094 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2095 // Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2
2096 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2097 // Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2
2098 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2099 // Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2
2100 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2101 // Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2
2102 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2103 // Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2
2104 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2105 // Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2
2106 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2107 // Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2
2108 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2109 // Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2
2110 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2111 // Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2
2112 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2113 // Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2
2114 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2115 // Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2
2116 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2117 // Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2
2118 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2119 // Convert__Reg1_0__Reg1_1__RTZArg1_2
2120 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
2121 // Convert__imm_95_15__imm_95_15
2122 { CVT_imm_95_15, 0, CVT_imm_95_15, 0, CVT_Done },
2123 // Convert__FenceArg1_0__FenceArg1_1
2124 { CVT_95_addFenceArgOperands, 1, CVT_95_addFenceArgOperands, 2, CVT_Done },
2125 // Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
2126 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2127 // Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2
2128 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2129 // Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2
2130 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2131 // Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2
2132 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2133 // Convert__Reg1_0__Reg1_2__Reg1_1
2134 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
2135 // Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1
2136 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2137 // Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1
2138 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2139 // Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1
2140 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2141 // Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1
2142 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2143 // Convert__Reg1_2__Reg1_0__BareSymbol1_1
2144 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2145 // Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1
2146 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
2147 // Convert__Reg1_0__LoadFPImm1_1
2148 { CVT_95_Reg, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
2149 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4
2150 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2151 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4
2152 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2153 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4
2154 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2155 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4
2156 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2157 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
2158 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2159 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2
2160 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2161 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2
2162 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2163 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2
2164 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2165 // Convert__Reg1_0__imm_95_3__regX0
2166 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_regX0, 0, CVT_Done },
2167 // Convert__Reg1_0__imm_95_1__regX0
2168 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_regX0, 0, CVT_Done },
2169 // Convert__Reg1_0__imm_95_2__regX0
2170 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_regX0, 0, CVT_Done },
2171 // Convert__regX0__imm_95_3__Reg1_0
2172 { CVT_regX0, 0, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
2173 // Convert__Reg1_0__imm_95_3__Reg1_1
2174 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
2175 // Convert__regX0__imm_95_1__Reg1_0
2176 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
2177 // Convert__Reg1_0__imm_95_1__Reg1_1
2178 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
2179 // Convert__regX0__imm_95_1__UImm51_0
2180 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_addImmOperands, 1, CVT_Done },
2181 // Convert__Reg1_0__imm_95_1__UImm51_1
2182 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_addImmOperands, 2, CVT_Done },
2183 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2
2184 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2185 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2
2186 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2187 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2
2188 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2189 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2
2190 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2191 // Convert__regX0__imm_95_2__Reg1_0
2192 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
2193 // Convert__Reg1_0__imm_95_2__Reg1_1
2194 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
2195 // Convert__regX0__imm_95_2__UImm51_0
2196 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_addImmOperands, 1, CVT_Done },
2197 // Convert__Reg1_0__imm_95_2__UImm51_1
2198 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_addImmOperands, 2, CVT_Done },
2199 // Convert__regX0__regX0
2200 { CVT_regX0, 0, CVT_regX0, 0, CVT_Done },
2201 // Convert__Reg1_0__regX0
2202 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_Done },
2203 // Convert__regX0__BareSImm21Lsb01_0
2204 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2205 // Convert__regX1__BareSImm21Lsb01_0
2206 { CVT_regX1, 0, CVT_95_addImmOperands, 1, CVT_Done },
2207 // Convert__Reg1_0__BareSImm21Lsb01_1
2208 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2209 // Convert__regX1__Reg1_0__imm_95_0
2210 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2211 // Convert__Reg1_0__Reg1_1__imm_95_0
2212 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2213 // Convert__regX1__Reg1_0__SImm12LO1_1
2214 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2215 // Convert__regX1__Reg1_2__OptionalSImm12LO1_0
2216 { CVT_regX1, 0, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultZeroOffset, 1, CVT_Done },
2217 // Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5
2218 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
2219 // Convert__regX0__Reg1_0__imm_95_0
2220 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2221 // Convert__regX0__Reg1_0__SImm12LO1_1
2222 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2223 // Convert__regX0__Reg1_2__OptionalSImm12LO1_0
2224 { CVT_regX0, 0, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultZeroOffset, 1, CVT_Done },
2225 // Convert__Reg1_1__PseudoJumpSymbol1_0
2226 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
2227 // Convert__Reg1_0__ImmXLenLI_Restricted1_1
2228 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2229 // Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5
2230 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_95_addImmOperands, 6, CVT_Done },
2231 // Convert__GPRPairNoX0RV321_0__BareSymbol1_1
2232 { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2233 // Convert__GPRPairRV321_0__Reg1_3__OptionalSImm12LO1_1
2234 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
2235 // Convert__Reg1_0__regX0__SImm12LO1_1
2236 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
2237 // Convert__Reg1_0__ImmXLenLI1_1
2238 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2239 // Convert__regX0__UImm201_0
2240 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2241 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2
2242 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_Done },
2243 // Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3
2244 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Done },
2245 // Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2
2246 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_95_addImmOperands, 3, CVT_Done },
2247 // Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2
2248 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_95_addImmOperands, 3, CVT_Done },
2249 // Convert__Reg1_3__UImm91_1__UImm51_0
2250 { CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2251 // Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2
2252 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2253 // Convert__Reg1_0__Reg1_1__regX0
2254 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
2255 // Convert__Reg1_0__regX0__Reg1_1
2256 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
2257 // Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1
2258 { CVT_95_addRegOperands, 1, CVT_regX0_Pair, 0, CVT_95_addRegOperands, 2, CVT_Done },
2259 // Convert__Reg1_0__GPRPairRV321_1__Reg1_2
2260 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_Done },
2261 // Convert__Reg1_0__GPRPairRV321_1__UImm61_2
2262 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2263 // Convert__Reg1_0__SImm181_1
2264 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2265 // Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2
2266 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2267 // Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2
2268 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2269 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3
2270 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2271 // Convert__Reg1_0__SImm20Lsb0001_1
2272 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2273 // Convert__Reg1_0__SImm18Lsb01_1
2274 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2275 // Convert__Reg1_0__SImm19Lsb001_1
2276 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2277 // Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2278 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2279 // Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3
2280 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2281 // Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2
2282 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2283 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2
2284 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2285 // Convert__regX0__regX0__imm_95_0
2286 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done },
2287 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1
2288 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_Done },
2289 // Convert__regX0__regX0__regX5
2290 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX5, 0, CVT_Done },
2291 // Convert__regX0__regX0__regX2
2292 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX2, 0, CVT_Done },
2293 // Convert__regX0__regX0__regX3
2294 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX3, 0, CVT_Done },
2295 // Convert__regX0__regX0__regX4
2296 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX4, 0, CVT_Done },
2297 // Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair
2298 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_regX0_Pair, 0, CVT_Done },
2299 // Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2
2300 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_Done },
2301 // Convert__imm_95_1__imm_95_0
2302 { CVT_imm_95_1, 0, CVT_imm_95_0, 0, CVT_Done },
2303 // Convert__Reg1_0__SImm8PLI_B1_1
2304 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_8_GT_, 2, CVT_Done },
2305 // Convert__GPRPairRV321_0__SImm8PLI_B1_1
2306 { CVT_95_addRegOperands, 1, CVT_95_addSExtImmOperands_LT_8_GT_, 2, CVT_Done },
2307 // Convert__GPRPairRV321_0__SImm10PLI_H1_1
2308 { CVT_95_addRegOperands, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2309 // Convert__Reg1_0__SImm10PLI_H1_1
2310 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2311 // Convert__Reg1_0__SImm10PLI_W1_1
2312 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2313 // Convert__GPRPairRV321_0__SImm10PLUI1_1
2314 { CVT_95_addRegOperands, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2315 // Convert__Reg1_0__SImm10PLUI1_1
2316 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2317 // Convert__GPRPairRV321_0__Reg1_1__Reg1_2
2318 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2319 // Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1
2320 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2321 // Convert__GPRPairRV321_0__regX0_Pair__Reg1_1
2322 { CVT_95_addRegOperands, 1, CVT_regX0_Pair, 0, CVT_95_Reg, 2, CVT_Done },
2323 // Convert__Reg1_0__GPRPairRV321_1__UImm41_2
2324 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2325 // Convert__Reg1_0__GPRPairRV321_1__UImm51_2
2326 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2327 // Convert__Reg1_0__GPRPairRV321_1__imm_95_0
2328 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2329 // Convert__Reg1_0__GPRPairRV321_1__imm_95_8
2330 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_8, 0, CVT_Done },
2331 // Convert__Reg1_0__GPRPairRV321_1__imm_95_16
2332 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_16, 0, CVT_Done },
2333 // Convert__Reg1_2__SImm12Lsb000001_0
2334 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2335 // Convert__GPRPairRV321_0__GPRPairRV321_1
2336 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
2337 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm4Plus11_2
2338 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2339 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm5Plus11_2
2340 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2341 // Convert__Reg1_0__Reg1_1__UImm4Plus11_2
2342 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2343 // Convert__Reg1_0__Reg1_1__UImm5Plus11_2
2344 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2345 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2
2346 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2347 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2
2348 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2349 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2
2350 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2351 // Convert__GPRPairRV321_0__Reg1_1__regX0
2352 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
2353 // Convert__GPRPairRV321_0__regX0__Reg1_1
2354 { CVT_95_addRegOperands, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
2355 // Convert__GPRPairRV321_0__Reg1_1__UImm41_2
2356 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2357 // Convert__GPRPairRV321_0__Reg1_1__UImm51_2
2358 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2359 // Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2
2360 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2361 // Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2
2362 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2363 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1
2364 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2365 // Convert__regX0__Tie0_1_1__UImm5NonZero1_0
2366 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2367 // Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1
2368 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2369 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2
2370 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2371 // Convert__regX0__Tie0_1_1__imm_95_0
2372 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
2373 // Convert__UImm5Slist1_0
2374 { CVT_95_addImmOperands, 1, CVT_Done },
2375 // Convert__UImm101_0
2376 { CVT_95_addImmOperands, 1, CVT_Done },
2377 // Convert__UImm111_0
2378 { CVT_95_addImmOperands, 1, CVT_Done },
2379 // Convert__RegListS01_0__NegStackAdj1_1
2380 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
2381 // Convert__Reg1_0__UImm51_1__Reg1_2
2382 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
2383 // Convert__Reg1_0__Tie0_1_1__BareSImm321_1
2384 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2385 // Convert__Reg1_0__Reg1_1__SImm261_2
2386 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2387 // Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2
2388 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2389 // Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2
2390 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2391 // Convert__BareSImm32Lsb01_0
2392 { CVT_95_addImmOperands, 1, CVT_Done },
2393 // Convert__Reg1_0__Reg1_3__OptionalSImm261_1
2394 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
2395 // Convert__Reg1_0__BareSImm321_1
2396 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2397 // Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1
2398 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
2399 // Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3
2400 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2401 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3
2402 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2403 // Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3
2404 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2405 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2
2406 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2407 // Convert__Reg1_0__Reg1_3__OptionalUImm14Lsb001_1
2408 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
2409 // Convert__Reg1_0__SImm20LI1_1
2410 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2411 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3
2412 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2413 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3
2414 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2415 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3
2416 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2417 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3
2418 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2419 // Convert__Reg1_0__Reg1_4__Reg1_1__OptionalUImm7Lsb001_2
2420 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultZeroOffset, 3, CVT_Done },
2421 // Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__OptionalUImm7Lsb001_2
2422 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_addImmOperands, 2, CVT_95_addImmOperands_95_defaultZeroOffset, 3, CVT_Done },
2423 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2
2424 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2425 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3
2426 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2427 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3
2428 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2429 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3
2430 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2431 // Convert__regX0__regX0__imm_95_1536
2432 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_1536, 0, CVT_Done },
2433 // Convert__regX0__Reg1_0__imm_95__MINUS_1280
2434 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1280, 0, CVT_Done },
2435 // Convert__regX0__Reg1_0__imm_95__MINUS_2048
2436 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_2048, 0, CVT_Done },
2437 // Convert__regX0__regX0__imm_95_1792
2438 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_1792, 0, CVT_Done },
2439 // Convert__regX0__Reg1_0__imm_95__MINUS_1792
2440 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1792, 0, CVT_Done },
2441 // Convert__UImm81_0
2442 { CVT_95_addImmOperands, 1, CVT_Done },
2443 // Convert__regX0__Reg1_0__imm_95__MINUS_1536
2444 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1536, 0, CVT_Done },
2445 // Convert__regX0__Reg1_0__imm_95__MINUS_1024
2446 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1024, 0, CVT_Done },
2447 // Convert__regX0__regX0__UImm101_0
2448 { CVT_regX0, 0, CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2449 // Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3
2450 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2451 // Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3
2452 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2453 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3
2454 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2455 // Convert__Reg1_0__Reg1_1__UImm111_2
2456 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2457 // Convert__Reg1_0__Reg1_3__OptionalUImm51_1
2458 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
2459 // Convert__Reg1_0__Reg1_3__OptionalUImm41_1
2460 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
2461 // Convert__Reg1_0__Reg1_3__OptionalUImm6Lsb01_1
2462 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
2463 // Convert__Reg1_0__Reg1_3__OptionalUImm5Lsb01_1
2464 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultZeroOffset, 2, CVT_Done },
2465 // Convert__Reg1_0__imm_95_3072__regX0
2466 { CVT_95_Reg, 1, CVT_imm_95_3072, 0, CVT_regX0, 0, CVT_Done },
2467 // Convert__Reg1_0__imm_95_3200__regX0
2468 { CVT_95_Reg, 1, CVT_imm_95_3200, 0, CVT_regX0, 0, CVT_Done },
2469 // Convert__Reg1_0__imm_95_3074__regX0
2470 { CVT_95_Reg, 1, CVT_imm_95_3074, 0, CVT_regX0, 0, CVT_Done },
2471 // Convert__Reg1_0__imm_95_3202__regX0
2472 { CVT_95_Reg, 1, CVT_imm_95_3202, 0, CVT_regX0, 0, CVT_Done },
2473 // Convert__Reg1_0__imm_95_3073__regX0
2474 { CVT_95_Reg, 1, CVT_imm_95_3073, 0, CVT_regX0, 0, CVT_Done },
2475 // Convert__Reg1_0__imm_95_3201__regX0
2476 { CVT_95_Reg, 1, CVT_imm_95_3201, 0, CVT_regX0, 0, CVT_Done },
2477 // Convert__regX0__regX1__imm_95_0
2478 { CVT_regX0, 0, CVT_regX1, 0, CVT_imm_95_0, 0, CVT_Done },
2479 // Convert__Reg1_0__Reg1_1__UImm6Plus11_2
2480 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2481 // Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1
2482 { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2483 // Convert__Reg1_0__Reg1_1__imm_95_1
2484 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
2485 // Convert__regX0
2486 { CVT_regX0, 0, CVT_Done },
2487 // Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3
2488 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2489 // Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3
2490 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2491 // Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3
2492 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2493 // Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3
2494 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2495 // Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3
2496 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2497 // Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3
2498 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2499 // Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3
2500 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2501 // Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3
2502 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
2503 // Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3
2504 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2505 // Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3
2506 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2507 // Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3
2508 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2509 // Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3
2510 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2511 // Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3
2512 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_Done },
2513 // Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3
2514 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2515 // Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3
2516 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2517 // Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3
2518 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2519 // Convert__Reg1_0__Reg1_1__XSfmmVType1_2
2520 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2521 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3
2522 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addSMTVTypeOperand_95_defaultSMTVType, 4, CVT_Done },
2523 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5
2524 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addSMTVTypeOperand_95_defaultSMTVType, 6, CVT_Done },
2525 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5
2526 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addSMTVTypeOperand_95_defaultSMTVType, 6, CVT_Done },
2527 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3
2528 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addSMTVTypeOperand_95_defaultSMTVType, 4, CVT_Done },
2529 // Convert__TailCallSymbol1_0__Reg1_1
2530 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
2531 // Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5
2532 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2533 // Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6
2534 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
2535 // Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6
2536 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
2537 // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5
2538 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2539 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2540 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2541 // Convert__Reg1_0__Reg1_1__regX0__reg0
2542 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_reg0, 0, CVT_Done },
2543 // Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2
2544 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2545 // Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3
2546 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
2547 // Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3
2548 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 4, CVT_Done },
2549 // Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3
2550 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2551 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3
2552 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 4, CVT_Done },
2553 // Convert__Reg1_0__Reg1_1__Reg1_1__reg0
2554 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_reg0, 0, CVT_Done },
2555 // Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2
2556 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2557 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm6Lsb0001_3__RVVMaskRegOpOperand1_4
2558 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addRegOperands_95_defaultMaskRegOp, 5, CVT_Done },
2559 // Convert__Reg1_0__RVVMaskRegOpOperand1_1
2560 { CVT_95_Reg, 1, CVT_95_addRegOperands_95_defaultMaskRegOp, 2, CVT_Done },
2561 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3
2562 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2563 // Convert__Reg1_0__Reg1_1__SImm51_2
2564 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2565 // Convert__Reg1_0__Reg1_0__Reg1_0
2566 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_Done },
2567 // Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3
2568 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2569 // Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2570 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2571 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3
2572 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2573 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4
2574 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addRegOperands_95_defaultMaskRegOp, 5, CVT_Done },
2575 // Convert__Reg1_0__SImm51_1
2576 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2577 // Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3
2578 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2579 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0
2580 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_reg0, 0, CVT_Done },
2581 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2
2582 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2583 // Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3
2584 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2585 // Convert__Reg1_0__UImm51_1__VTypeI101_2
2586 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2587 // Convert__Reg1_0__Reg1_1__VTypeI111_2
2588 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2589 // Convert__GPRPairRV321_0__Reg1_1__UImm61_2
2590 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2591 // Convert__Reg1_0__Reg1_1__YBNDSWImm1_2
2592 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2593 // Convert__Reg1_0__Reg1_1__imm_95_255
2594 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_255, 0, CVT_Done },
2595};
2596
2597void RISCVAsmParser::
2598convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2599 const OperandVector &Operands,
2600 const SmallBitVector &OptionalOperandsMask,
2601 ArrayRef<unsigned> DefaultsOffset) {
2602 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2603 const uint8_t *Converter = ConversionTable[Kind];
2604 Inst.setOpcode(Opcode);
2605 for (const uint8_t *p = Converter; *p; p += 2) {
2606 unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
2607 switch (*p) {
2608 default: llvm_unreachable("invalid conversion entry!");
2609 case CVT_Reg:
2610 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2611 break;
2612 case CVT_Tied: {
2613 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
2614 std::begin(TiedAsmOperandTable)) &&
2615 "Tied operand not found");
2616 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
2617 if (TiedResOpnd != (uint8_t)-1)
2618 Inst.addOperand(Inst.getOperand(TiedResOpnd));
2619 break;
2620 }
2621 case CVT_95_addImmOperands:
2622 static_cast<RISCVOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2623 break;
2624 case CVT_95_addRegOperands:
2625 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2626 break;
2627 case CVT_95_addImmOperands_95_defaultZeroOffset:
2628 if (OptionalOperandsMask[*(p + 1)]) {
2629 defaultZeroOffset()->addImmOperands(Inst, 1);
2630 } else {
2631 static_cast<RISCVOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2632 }
2633 break;
2634 case CVT_95_Reg:
2635 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2636 break;
2637 case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
2638 if (OptionalOperandsMask[*(p + 1)]) {
2639 defaultFRMArgOp()->addFRMArgOperands(Inst, 1);
2640 } else {
2641 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2642 }
2643 break;
2644 case CVT_regX0:
2645 Inst.addOperand(MCOperand::createReg(RISCV::X0));
2646 break;
2647 case CVT_regX1:
2648 Inst.addOperand(MCOperand::createReg(RISCV::X1));
2649 break;
2650 case CVT_regX5:
2651 Inst.addOperand(MCOperand::createReg(RISCV::X5));
2652 break;
2653 case CVT_regX2:
2654 Inst.addOperand(MCOperand::createReg(RISCV::X2));
2655 break;
2656 case CVT_regX3:
2657 Inst.addOperand(MCOperand::createReg(RISCV::X3));
2658 break;
2659 case CVT_regX4:
2660 Inst.addOperand(MCOperand::createReg(RISCV::X4));
2661 break;
2662 case CVT_imm_95_0:
2663 Inst.addOperand(MCOperand::createImm(0));
2664 break;
2665 case CVT_95_addRegListOperands:
2666 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
2667 break;
2668 case CVT_95_addStackAdjOperands:
2669 static_cast<RISCVOperand &>(*Operands[OpIdx]).addStackAdjOperands(Inst, 1);
2670 break;
2671 case CVT_95_addCSRSystemRegisterOperands:
2672 static_cast<RISCVOperand &>(*Operands[OpIdx]).addCSRSystemRegisterOperands(Inst, 1);
2673 break;
2674 case CVT_95_addRegRegOperands:
2675 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegRegOperands(Inst, 2);
2676 break;
2677 case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
2678 if (OptionalOperandsMask[*(p + 1)]) {
2679 defaultFRMArgLegacyOp()->addFRMArgOperands(Inst, 1);
2680 } else {
2681 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2682 }
2683 break;
2684 case CVT_95_addFRMArgOperands:
2685 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2686 break;
2687 case CVT_imm_95_15:
2688 Inst.addOperand(MCOperand::createImm(15));
2689 break;
2690 case CVT_95_addFenceArgOperands:
2691 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFenceArgOperands(Inst, 1);
2692 break;
2693 case CVT_95_addFPImmOperands:
2694 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
2695 break;
2696 case CVT_imm_95_3:
2697 Inst.addOperand(MCOperand::createImm(3));
2698 break;
2699 case CVT_imm_95_1:
2700 Inst.addOperand(MCOperand::createImm(1));
2701 break;
2702 case CVT_imm_95_2:
2703 Inst.addOperand(MCOperand::createImm(2));
2704 break;
2705 case CVT_regX0_Pair:
2706 Inst.addOperand(MCOperand::createReg(RISCV::X0_Pair));
2707 break;
2708 case CVT_95_addRegOperands_95_defaultMaskRegOp:
2709 if (OptionalOperandsMask[*(p + 1)]) {
2710 defaultMaskRegOp()->addRegOperands(Inst, 1);
2711 } else {
2712 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2713 }
2714 break;
2715 case CVT_imm_95__MINUS_1:
2716 Inst.addOperand(MCOperand::createImm(-1));
2717 break;
2718 case CVT_95_addSExtImmOperands_LT_8_GT_:
2719 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSExtImmOperands<8>(Inst, 1);
2720 break;
2721 case CVT_95_addSExtImmOperands_LT_10_GT_:
2722 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSExtImmOperands<10>(Inst, 1);
2723 break;
2724 case CVT_imm_95_8:
2725 Inst.addOperand(MCOperand::createImm(8));
2726 break;
2727 case CVT_imm_95_16:
2728 Inst.addOperand(MCOperand::createImm(16));
2729 break;
2730 case CVT_imm_95_1536:
2731 Inst.addOperand(MCOperand::createImm(1536));
2732 break;
2733 case CVT_imm_95__MINUS_1280:
2734 Inst.addOperand(MCOperand::createImm(-1280));
2735 break;
2736 case CVT_imm_95__MINUS_2048:
2737 Inst.addOperand(MCOperand::createImm(-2048));
2738 break;
2739 case CVT_imm_95_1792:
2740 Inst.addOperand(MCOperand::createImm(1792));
2741 break;
2742 case CVT_imm_95__MINUS_1792:
2743 Inst.addOperand(MCOperand::createImm(-1792));
2744 break;
2745 case CVT_imm_95__MINUS_1536:
2746 Inst.addOperand(MCOperand::createImm(-1536));
2747 break;
2748 case CVT_imm_95__MINUS_1024:
2749 Inst.addOperand(MCOperand::createImm(-1024));
2750 break;
2751 case CVT_imm_95_3072:
2752 Inst.addOperand(MCOperand::createImm(3072));
2753 break;
2754 case CVT_imm_95_3200:
2755 Inst.addOperand(MCOperand::createImm(3200));
2756 break;
2757 case CVT_imm_95_3074:
2758 Inst.addOperand(MCOperand::createImm(3074));
2759 break;
2760 case CVT_imm_95_3202:
2761 Inst.addOperand(MCOperand::createImm(3202));
2762 break;
2763 case CVT_imm_95_3073:
2764 Inst.addOperand(MCOperand::createImm(3073));
2765 break;
2766 case CVT_imm_95_3201:
2767 Inst.addOperand(MCOperand::createImm(3201));
2768 break;
2769 case CVT_95_addVTypeIOperands:
2770 static_cast<RISCVOperand &>(*Operands[OpIdx]).addVTypeIOperands(Inst, 1);
2771 break;
2772 case CVT_95_addSMTVTypeOperand_95_defaultSMTVType:
2773 if (OptionalOperandsMask[*(p + 1)]) {
2774 defaultSMTVType()->addSMTVTypeOperand(Inst, 1);
2775 } else {
2776 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSMTVTypeOperand(Inst, 1);
2777 }
2778 break;
2779 case CVT_reg0:
2780 Inst.addOperand(MCOperand::createReg(0));
2781 break;
2782 case CVT_imm_95_255:
2783 Inst.addOperand(MCOperand::createImm(255));
2784 break;
2785 }
2786 }
2787}
2788
2789void RISCVAsmParser::
2790convertToMapAndConstraints(unsigned Kind,
2791 const OperandVector &Operands) {
2792 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2793 unsigned NumMCOperands = 0;
2794 const uint8_t *Converter = ConversionTable[Kind];
2795 for (const uint8_t *p = Converter; *p; p += 2) {
2796 switch (*p) {
2797 default: llvm_unreachable("invalid conversion entry!");
2798 case CVT_Reg:
2799 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2800 Operands[*(p + 1)]->setConstraint("r");
2801 ++NumMCOperands;
2802 break;
2803 case CVT_Tied:
2804 ++NumMCOperands;
2805 break;
2806 case CVT_95_addImmOperands:
2807 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2808 Operands[*(p + 1)]->setConstraint("m");
2809 NumMCOperands += 1;
2810 break;
2811 case CVT_95_addRegOperands:
2812 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2813 Operands[*(p + 1)]->setConstraint("m");
2814 NumMCOperands += 1;
2815 break;
2816 case CVT_95_addImmOperands_95_defaultZeroOffset:
2817 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2818 Operands[*(p + 1)]->setConstraint("m");
2819 NumMCOperands += 1;
2820 break;
2821 case CVT_95_Reg:
2822 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2823 Operands[*(p + 1)]->setConstraint("r");
2824 NumMCOperands += 1;
2825 break;
2826 case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
2827 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2828 Operands[*(p + 1)]->setConstraint("m");
2829 NumMCOperands += 1;
2830 break;
2831 case CVT_regX0:
2832 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2833 Operands[*(p + 1)]->setConstraint("m");
2834 ++NumMCOperands;
2835 break;
2836 case CVT_regX1:
2837 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2838 Operands[*(p + 1)]->setConstraint("m");
2839 ++NumMCOperands;
2840 break;
2841 case CVT_regX5:
2842 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2843 Operands[*(p + 1)]->setConstraint("m");
2844 ++NumMCOperands;
2845 break;
2846 case CVT_regX2:
2847 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2848 Operands[*(p + 1)]->setConstraint("m");
2849 ++NumMCOperands;
2850 break;
2851 case CVT_regX3:
2852 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2853 Operands[*(p + 1)]->setConstraint("m");
2854 ++NumMCOperands;
2855 break;
2856 case CVT_regX4:
2857 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2858 Operands[*(p + 1)]->setConstraint("m");
2859 ++NumMCOperands;
2860 break;
2861 case CVT_imm_95_0:
2862 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2863 Operands[*(p + 1)]->setConstraint("");
2864 ++NumMCOperands;
2865 break;
2866 case CVT_95_addRegListOperands:
2867 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2868 Operands[*(p + 1)]->setConstraint("m");
2869 NumMCOperands += 1;
2870 break;
2871 case CVT_95_addStackAdjOperands:
2872 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2873 Operands[*(p + 1)]->setConstraint("m");
2874 NumMCOperands += 1;
2875 break;
2876 case CVT_95_addCSRSystemRegisterOperands:
2877 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2878 Operands[*(p + 1)]->setConstraint("m");
2879 NumMCOperands += 1;
2880 break;
2881 case CVT_95_addRegRegOperands:
2882 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2883 Operands[*(p + 1)]->setConstraint("m");
2884 NumMCOperands += 2;
2885 break;
2886 case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
2887 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2888 Operands[*(p + 1)]->setConstraint("m");
2889 NumMCOperands += 1;
2890 break;
2891 case CVT_95_addFRMArgOperands:
2892 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2893 Operands[*(p + 1)]->setConstraint("m");
2894 NumMCOperands += 1;
2895 break;
2896 case CVT_imm_95_15:
2897 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2898 Operands[*(p + 1)]->setConstraint("");
2899 ++NumMCOperands;
2900 break;
2901 case CVT_95_addFenceArgOperands:
2902 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2903 Operands[*(p + 1)]->setConstraint("m");
2904 NumMCOperands += 1;
2905 break;
2906 case CVT_95_addFPImmOperands:
2907 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2908 Operands[*(p + 1)]->setConstraint("m");
2909 NumMCOperands += 1;
2910 break;
2911 case CVT_imm_95_3:
2912 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2913 Operands[*(p + 1)]->setConstraint("");
2914 ++NumMCOperands;
2915 break;
2916 case CVT_imm_95_1:
2917 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2918 Operands[*(p + 1)]->setConstraint("");
2919 ++NumMCOperands;
2920 break;
2921 case CVT_imm_95_2:
2922 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2923 Operands[*(p + 1)]->setConstraint("");
2924 ++NumMCOperands;
2925 break;
2926 case CVT_regX0_Pair:
2927 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2928 Operands[*(p + 1)]->setConstraint("m");
2929 ++NumMCOperands;
2930 break;
2931 case CVT_95_addRegOperands_95_defaultMaskRegOp:
2932 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2933 Operands[*(p + 1)]->setConstraint("m");
2934 NumMCOperands += 1;
2935 break;
2936 case CVT_imm_95__MINUS_1:
2937 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2938 Operands[*(p + 1)]->setConstraint("");
2939 ++NumMCOperands;
2940 break;
2941 case CVT_95_addSExtImmOperands_LT_8_GT_:
2942 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2943 Operands[*(p + 1)]->setConstraint("m");
2944 NumMCOperands += 1;
2945 break;
2946 case CVT_95_addSExtImmOperands_LT_10_GT_:
2947 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2948 Operands[*(p + 1)]->setConstraint("m");
2949 NumMCOperands += 1;
2950 break;
2951 case CVT_imm_95_8:
2952 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2953 Operands[*(p + 1)]->setConstraint("");
2954 ++NumMCOperands;
2955 break;
2956 case CVT_imm_95_16:
2957 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2958 Operands[*(p + 1)]->setConstraint("");
2959 ++NumMCOperands;
2960 break;
2961 case CVT_imm_95_1536:
2962 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2963 Operands[*(p + 1)]->setConstraint("");
2964 ++NumMCOperands;
2965 break;
2966 case CVT_imm_95__MINUS_1280:
2967 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2968 Operands[*(p + 1)]->setConstraint("");
2969 ++NumMCOperands;
2970 break;
2971 case CVT_imm_95__MINUS_2048:
2972 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2973 Operands[*(p + 1)]->setConstraint("");
2974 ++NumMCOperands;
2975 break;
2976 case CVT_imm_95_1792:
2977 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2978 Operands[*(p + 1)]->setConstraint("");
2979 ++NumMCOperands;
2980 break;
2981 case CVT_imm_95__MINUS_1792:
2982 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2983 Operands[*(p + 1)]->setConstraint("");
2984 ++NumMCOperands;
2985 break;
2986 case CVT_imm_95__MINUS_1536:
2987 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2988 Operands[*(p + 1)]->setConstraint("");
2989 ++NumMCOperands;
2990 break;
2991 case CVT_imm_95__MINUS_1024:
2992 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2993 Operands[*(p + 1)]->setConstraint("");
2994 ++NumMCOperands;
2995 break;
2996 case CVT_imm_95_3072:
2997 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2998 Operands[*(p + 1)]->setConstraint("");
2999 ++NumMCOperands;
3000 break;
3001 case CVT_imm_95_3200:
3002 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3003 Operands[*(p + 1)]->setConstraint("");
3004 ++NumMCOperands;
3005 break;
3006 case CVT_imm_95_3074:
3007 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3008 Operands[*(p + 1)]->setConstraint("");
3009 ++NumMCOperands;
3010 break;
3011 case CVT_imm_95_3202:
3012 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3013 Operands[*(p + 1)]->setConstraint("");
3014 ++NumMCOperands;
3015 break;
3016 case CVT_imm_95_3073:
3017 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3018 Operands[*(p + 1)]->setConstraint("");
3019 ++NumMCOperands;
3020 break;
3021 case CVT_imm_95_3201:
3022 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3023 Operands[*(p + 1)]->setConstraint("");
3024 ++NumMCOperands;
3025 break;
3026 case CVT_95_addVTypeIOperands:
3027 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3028 Operands[*(p + 1)]->setConstraint("m");
3029 NumMCOperands += 1;
3030 break;
3031 case CVT_95_addSMTVTypeOperand_95_defaultSMTVType:
3032 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3033 Operands[*(p + 1)]->setConstraint("m");
3034 NumMCOperands += 1;
3035 break;
3036 case CVT_reg0:
3037 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3038 Operands[*(p + 1)]->setConstraint("m");
3039 ++NumMCOperands;
3040 break;
3041 case CVT_imm_95_255:
3042 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3043 Operands[*(p + 1)]->setConstraint("");
3044 ++NumMCOperands;
3045 break;
3046 }
3047 }
3048}
3049
3050namespace {
3051
3052/// MatchClassKind - The kinds of classes which participate in
3053/// instruction matching.
3054enum MatchClassKind {
3055 InvalidMatchClass = 0,
3056 OptionalMatchClass = 1,
3057 MCK__40_, // '('
3058 MCK__41_, // ')'
3059 MCK_LAST_TOKEN = MCK__41_,
3060 MCK_Reg143, // derived register class
3061 MCK_Reg140, // derived register class
3062 MCK_Reg137, // derived register class
3063 MCK_Reg134, // derived register class
3064 MCK_Reg131, // derived register class
3065 MCK_Reg128, // derived register class
3066 MCK_Reg125, // derived register class
3067 MCK_Reg122, // derived register class
3068 MCK_Reg119, // derived register class
3069 MCK_Reg116, // derived register class
3070 MCK_Reg113, // derived register class
3071 MCK_Reg99, // derived register class
3072 MCK_Reg96, // derived register class
3073 MCK_Reg93, // derived register class
3074 MCK_Reg74, // derived register class
3075 MCK_Reg69, // derived register class
3076 MCK_Reg66, // derived register class
3077 MCK_Reg63, // derived register class
3078 MCK_Reg60, // derived register class
3079 MCK_Reg55, // derived register class
3080 MCK_Reg46, // derived register class
3081 MCK_Reg45, // derived register class
3082 MCK_Reg39, // derived register class
3083 MCK_Reg34, // derived register class
3084 MCK_GPRF16X0, // register class 'GPRF16X0'
3085 MCK_GPRF32X0, // register class 'GPRF32X0'
3086 MCK_GPRX0, // register class 'GPRX0'
3087 MCK_GPRX1, // register class 'GPRX1'
3088 MCK_GPRX5, // register class 'GPRX5'
3089 MCK_GPRX7, // register class 'GPRX7'
3090 MCK_MR0, // register class 'MR0'
3091 MCK_SP, // register class 'SP'
3092 MCK_VMV0, // register class 'VMV0'
3093 MCK_anonymous_15514, // register class 'anonymous_15514'
3094 MCK_Reg56, // derived register class
3095 MCK_Reg44, // derived register class
3096 MCK_Reg30, // derived register class
3097 MCK_GPRX1X5, // register class 'GPRX1X5'
3098 MCK_Reg79, // derived register class
3099 MCK_VCSR, // register class 'VCSR'
3100 MCK_VRM8NoV0, // register class 'VRM8NoV0'
3101 MCK_Reg78, // derived register class
3102 MCK_GPRPairC, // register class 'GPRPairC'
3103 MCK_TRM4, // register class 'TRM4'
3104 MCK_VRM8, // register class 'VRM8'
3105 MCK_Reg80, // derived register class
3106 MCK_Reg81, // derived register class
3107 MCK_Reg72, // derived register class
3108 MCK_Reg59, // derived register class
3109 MCK_Reg33, // derived register class
3110 MCK_VRN2M4NoV0, // register class 'VRN2M4NoV0'
3111 MCK_Reg73, // derived register class
3112 MCK_VRM4NoV0, // register class 'VRM4NoV0'
3113 MCK_VRN2M4, // register class 'VRN2M4'
3114 MCK_Reg108, // derived register class
3115 MCK_Reg89, // derived register class
3116 MCK_Reg58, // derived register class
3117 MCK_Reg57, // derived register class
3118 MCK_FPR16C, // register class 'FPR16C'
3119 MCK_FPR32C, // register class 'FPR32C'
3120 MCK_FPR64C, // register class 'FPR64C'
3121 MCK_GPRC, // register class 'GPRC'
3122 MCK_GPRF16C, // register class 'GPRF16C'
3123 MCK_GPRF32C, // register class 'GPRF32C'
3124 MCK_GPRS07, // register class 'GPRS07'
3125 MCK_MR, // register class 'MR'
3126 MCK_TRM2, // register class 'TRM2'
3127 MCK_VRM4, // register class 'VRM4'
3128 MCK_Reg76, // derived register class
3129 MCK_Reg77, // derived register class
3130 MCK_Reg70, // derived register class
3131 MCK_Reg53, // derived register class
3132 MCK_Reg27, // derived register class
3133 MCK_VRN4M2NoV0, // register class 'VRN4M2NoV0'
3134 MCK_Reg71, // derived register class
3135 MCK_Reg67, // derived register class
3136 MCK_Reg54, // derived register class
3137 MCK_Reg49, // derived register class
3138 MCK_Reg23, // derived register class
3139 MCK_GPRTCNonX7, // register class 'GPRTCNonX7'
3140 MCK_VRN3M2NoV0, // register class 'VRN3M2NoV0'
3141 MCK_VRN4M2, // register class 'VRN4M2'
3142 MCK_Reg68, // derived register class
3143 MCK_Reg64, // derived register class
3144 MCK_Reg50, // derived register class
3145 MCK_GPRTC, // register class 'GPRTC'
3146 MCK_VRN2M2NoV0, // register class 'VRN2M2NoV0'
3147 MCK_VRN3M2, // register class 'VRN3M2'
3148 MCK_Reg62, // derived register class
3149 MCK_GPRPairNoX0, // register class 'GPRPairNoX0'
3150 MCK_VRM2NoV0, // register class 'VRM2NoV0'
3151 MCK_VRN2M2, // register class 'VRN2M2'
3152 MCK_GPRPair, // register class 'GPRPair'
3153 MCK_TR, // register class 'TR'
3154 MCK_VRM2, // register class 'VRM2'
3155 MCK_Reg51, // derived register class
3156 MCK_Reg25, // derived register class
3157 MCK_VRN8M1NoV0, // register class 'VRN8M1NoV0'
3158 MCK_Reg52, // derived register class
3159 MCK_Reg47, // derived register class
3160 MCK_Reg21, // derived register class
3161 MCK_GPRJALRNonX7, // register class 'GPRJALRNonX7'
3162 MCK_VRN7M1NoV0, // register class 'VRN7M1NoV0'
3163 MCK_VRN8M1, // register class 'VRN8M1'
3164 MCK_Reg48, // derived register class
3165 MCK_GPRJALR, // register class 'GPRJALR'
3166 MCK_VRN6M1NoV0, // register class 'VRN6M1NoV0'
3167 MCK_VRN7M1, // register class 'VRN7M1'
3168 MCK_VRN5M1NoV0, // register class 'VRN5M1NoV0'
3169 MCK_VRN6M1, // register class 'VRN6M1'
3170 MCK_VRN4M1NoV0, // register class 'VRN4M1NoV0'
3171 MCK_VRN5M1, // register class 'VRN5M1'
3172 MCK_Reg42, // derived register class
3173 MCK_Reg16, // derived register class
3174 MCK_VRN3M1NoV0, // register class 'VRN3M1NoV0'
3175 MCK_VRN4M1, // register class 'VRN4M1'
3176 MCK_Reg43, // derived register class
3177 MCK_Reg40, // derived register class
3178 MCK_Reg37, // derived register class
3179 MCK_Reg14, // derived register class
3180 MCK_Reg11, // derived register class
3181 MCK_GPRNoX0X2, // register class 'GPRNoX0X2'
3182 MCK_VRN2M1NoV0, // register class 'VRN2M1NoV0'
3183 MCK_VRN3M1, // register class 'VRN3M1'
3184 MCK_Reg41, // derived register class
3185 MCK_Reg38, // derived register class
3186 MCK_Reg35, // derived register class
3187 MCK_GPRF16NoX0, // register class 'GPRF16NoX0'
3188 MCK_GPRF32NoX0, // register class 'GPRF32NoX0'
3189 MCK_GPRNoX0, // register class 'GPRNoX0'
3190 MCK_GPRNoX2, // register class 'GPRNoX2'
3191 MCK_GPRNoX31, // register class 'GPRNoX31'
3192 MCK_VRN2M1, // register class 'VRN2M1'
3193 MCK_VRNoV0, // register class 'VRNoV0,ZZZ_VMNoV0,ZZZ_VRMF2NoV0,ZZZ_VRMF4NoV0,ZZZ_VRMF8NoV0'
3194 MCK_FPR128, // register class 'FPR128'
3195 MCK_FPR16, // register class 'FPR16'
3196 MCK_FPR256, // register class 'FPR256'
3197 MCK_FPR32, // register class 'FPR32'
3198 MCK_FPR64, // register class 'FPR64'
3199 MCK_GPR, // register class 'GPR'
3200 MCK_GPRF16, // register class 'GPRF16'
3201 MCK_GPRF32, // register class 'GPRF32'
3202 MCK_VR, // register class 'VR,ZZZ_VM,ZZZ_VRMF2,ZZZ_VRMF4,ZZZ_VRMF8'
3203 MCK_YGPR, // register class 'YGPR'
3204 MCK_LAST_REGISTER = MCK_YGPR,
3205 MCK_AnyRegCOperand, // user defined class 'AnyRegCOperand'
3206 MCK_AnyRegOperand, // user defined class 'AnyRegOperand'
3207 MCK_BareSymbol, // user defined class 'BareSymbol'
3208 MCK_BareSymbolQC_E_LI, // user defined class 'BareSymbolQC_E_LI'
3209 MCK_CLUIImm, // user defined class 'CLUIImmAsmOperand'
3210 MCK_CSRSystemRegister, // user defined class 'CSRSystemRegister'
3211 MCK_RegReg, // user defined class 'CVrrAsmOperand'
3212 MCK_TailCallSymbol, // user defined class 'TailCallSymbol'
3213 MCK_CallSymbol, // user defined class 'CallSymbol'
3214 MCK_FRMArg, // user defined class 'FRMArg'
3215 MCK_FRMArgLegacy, // user defined class 'FRMArgLegacy'
3216 MCK_FenceArg, // user defined class 'FenceArg'
3217 MCK_GPRAsFPR16, // user defined class 'GPRAsFPR16'
3218 MCK_GPRAsFPR32, // user defined class 'GPRAsFPR32'
3219 MCK_GPRF64AsFPR, // user defined class 'GPRF64AsFPR'
3220 MCK_GPRPairAsFPR, // user defined class 'GPRPairAsFPR'
3221 MCK_GPRPairCRV32, // user defined class 'GPRPairCRV32Operand'
3222 MCK_GPRPairNoX0RV32, // user defined class 'GPRPairNoX0RV32Operand'
3223 MCK_GPRPairRV32, // user defined class 'GPRPairRV32Operand'
3224 MCK_GPRPairRV64, // user defined class 'GPRPairRV64Operand'
3225 MCK_Imm, // user defined class 'ImmAsmOperand'
3226 MCK_ImmFour, // user defined class 'ImmFourAsmOperand'
3227 MCK_ImmThree, // user defined class 'ImmThreeAsmOperand'
3228 MCK_ImmZero, // user defined class 'ImmZeroAsmOperand'
3229 MCK_InsnCDirectiveOpcode, // user defined class 'InsnCDirectiveOpcode'
3230 MCK_InsnDirectiveOpcode, // user defined class 'InsnDirectiveOpcode'
3231 MCK_LoadFPImm, // user defined class 'LoadFPImmOperand'
3232 MCK_NegStackAdj, // user defined class 'NegStackAdjAsmOperand'
3233 MCK_PseudoJumpSymbol, // user defined class 'PseudoJumpSymbol'
3234 MCK_QCAccessSymbol, // user defined class 'QCAccessSymbol'
3235 MCK_RTZArg, // user defined class 'RTZArg'
3236 MCK_RegList, // user defined class 'RegListAsmOperand'
3237 MCK_RegListS0, // user defined class 'RegListS0AsmOperand'
3238 MCK_RnumArg, // user defined class 'RnumArg'
3239 MCK_SImm10PLI_H, // user defined class 'SImm10PLI_HAsmOperand'
3240 MCK_SImm10PLI_W, // user defined class 'SImm10PLI_WAsmOperand'
3241 MCK_SImm10PLUI, // user defined class 'SImm10PLUIAsmOperand'
3242 MCK_SImm8PLI_B, // user defined class 'SImm8PLI_BAsmOperand'
3243 MCK_SMTI8, // user defined class 'SMTI8'
3244 MCK_SMTVType, // user defined class 'SMTVType'
3245 MCK_BareSImm21Lsb0, // user defined class 'Simm21Lsb0JALAsmOperand'
3246 MCK_StackAdj, // user defined class 'StackAdjAsmOperand'
3247 MCK_TLSDESCCallSymbol, // user defined class 'TLSDESCCallSymbol'
3248 MCK_TPRelAddSymbol, // user defined class 'TPRelAddSymbol'
3249 MCK_TileLambda, // user defined class 'TileLambdaAsmOperand'
3250 MCK_UImmLog2XLen, // user defined class 'UImmLog2XLenAsmOperand'
3251 MCK_UImmLog2XLenNonZero, // user defined class 'UImmLog2XLenNonZeroAsmOperand'
3252 MCK_RVVMaskRegOpOperand, // user defined class 'VMaskAsmOperand'
3253 MCK_RVVMaskCarryInRegOpOperand, // user defined class 'VMaskCarryInAsmOperand'
3254 MCK_RVVScaleRegOpOperand, // user defined class 'VScaleAsmOperand'
3255 MCK_XSfmmVType, // user defined class 'XSfmmVTypeAsmOperand'
3256 MCK_YBNDSWImm, // user defined class 'YBNDSWImmOperand'
3257 MCK_ZeroOffsetMemOpOperand, // user defined class 'ZeroOffsetMemOpOperand'
3258 MCK_UImm1, // user defined class 'anonymous_15909'
3259 MCK_UImm2, // user defined class 'anonymous_15910'
3260 MCK_UImm3, // user defined class 'anonymous_15911'
3261 MCK_UImm4, // user defined class 'anonymous_15912'
3262 MCK_UImm5, // user defined class 'anonymous_15913'
3263 MCK_UImm6, // user defined class 'anonymous_15914'
3264 MCK_UImm7, // user defined class 'anonymous_15915'
3265 MCK_UImm8, // user defined class 'anonymous_15916'
3266 MCK_UImm16, // user defined class 'anonymous_15917'
3267 MCK_UImm32, // user defined class 'anonymous_15918'
3268 MCK_UImm48, // user defined class 'anonymous_15919'
3269 MCK_UImm64, // user defined class 'anonymous_15920'
3270 MCK_SImm12, // user defined class 'anonymous_15921'
3271 MCK_SImm12LO, // user defined class 'anonymous_15922'
3272 MCK_OptionalSImm12, // user defined class 'anonymous_15923'
3273 MCK_OptionalSImm12LO, // user defined class 'anonymous_15924'
3274 MCK_BareSImm13Lsb0, // user defined class 'anonymous_15925'
3275 MCK_UImm20, // user defined class 'anonymous_15926'
3276 MCK_UImm20LUI, // user defined class 'anonymous_15927'
3277 MCK_UImm20AUIPC, // user defined class 'anonymous_15928'
3278 MCK_ImmXLenLI, // user defined class 'anonymous_15929'
3279 MCK_ImmXLenLI_Restricted, // user defined class 'anonymous_15930'
3280 MCK_SImm12Lsb00000, // user defined class 'anonymous_16886'
3281 MCK_Imm5Zibi, // user defined class 'anonymous_16899'
3282 MCK_VTypeI10, // user defined class 'anonymous_17614'
3283 MCK_VTypeI11, // user defined class 'anonymous_17615'
3284 MCK_SImm5, // user defined class 'anonymous_17616'
3285 MCK_SImm5Plus1, // user defined class 'anonymous_17617'
3286 MCK_UImm6Lsb000, // user defined class 'anonymous_62619'
3287 MCK_UImm4Plus1, // user defined class 'anonymous_62620'
3288 MCK_UImm5Plus1, // user defined class 'anonymous_62621'
3289 MCK_UImm6Plus1, // user defined class 'anonymous_62622'
3290 MCK_SImm6, // user defined class 'anonymous_63404'
3291 MCK_SImm6NonZero, // user defined class 'anonymous_63405'
3292 MCK_UImm7Lsb00, // user defined class 'anonymous_63406'
3293 MCK_OptionalUImm7Lsb00, // user defined class 'anonymous_63407'
3294 MCK_UImm8Lsb00, // user defined class 'anonymous_63408'
3295 MCK_OptionalUImm8Lsb00, // user defined class 'anonymous_63409'
3296 MCK_UImm8Lsb000, // user defined class 'anonymous_63410'
3297 MCK_OptionalUImm8Lsb000, // user defined class 'anonymous_63411'
3298 MCK_BareSImm9Lsb0, // user defined class 'anonymous_63412'
3299 MCK_UImm9Lsb000, // user defined class 'anonymous_63413'
3300 MCK_OptionalUImm9Lsb000, // user defined class 'anonymous_63414'
3301 MCK_UImm10Lsb00NonZero, // user defined class 'anonymous_63415'
3302 MCK_SImm10Lsb0000NonZero, // user defined class 'anonymous_63416'
3303 MCK_BareSImm12Lsb0, // user defined class 'anonymous_63417'
3304 MCK_OptionalUImm5, // user defined class 'anonymous_63418'
3305 MCK_OptionalUImm2, // user defined class 'anonymous_63492'
3306 MCK_UImm2Lsb0, // user defined class 'anonymous_63493'
3307 MCK_OptionalUImm2Lsb0, // user defined class 'anonymous_63494'
3308 MCK_UImm8GE32, // user defined class 'anonymous_63495'
3309 MCK_OptionalUImm4, // user defined class 'anonymous_65388'
3310 MCK_UImm5Lsb0, // user defined class 'anonymous_65389'
3311 MCK_OptionalUImm5Lsb0, // user defined class 'anonymous_65390'
3312 MCK_UImm6Lsb0, // user defined class 'anonymous_65391'
3313 MCK_OptionalUImm6Lsb0, // user defined class 'anonymous_65392'
3314 MCK_UImm5NonZero, // user defined class 'anonymous_65402'
3315 MCK_UImm5GT3, // user defined class 'anonymous_65403'
3316 MCK_UImm5GE6Plus1, // user defined class 'anonymous_65404'
3317 MCK_UImm5Slist, // user defined class 'anonymous_65405'
3318 MCK_UImm10, // user defined class 'anonymous_65406'
3319 MCK_UImm11, // user defined class 'anonymous_65407'
3320 MCK_UImm14Lsb00, // user defined class 'anonymous_65408'
3321 MCK_OptionalUImm14Lsb00, // user defined class 'anonymous_65409'
3322 MCK_UImm16NonZero, // user defined class 'anonymous_65410'
3323 MCK_SImm5NonZero, // user defined class 'anonymous_65411'
3324 MCK_SImm11, // user defined class 'anonymous_65412'
3325 MCK_SImm16, // user defined class 'anonymous_65413'
3326 MCK_SImm16NonZero, // user defined class 'anonymous_65414'
3327 MCK_SImm20LI, // user defined class 'anonymous_65415'
3328 MCK_SImm26, // user defined class 'anonymous_65416'
3329 MCK_OptionalSImm26, // user defined class 'anonymous_65417'
3330 MCK_BareSImm32, // user defined class 'anonymous_65418'
3331 MCK_BareSImm32Lsb0, // user defined class 'anonymous_65419'
3332 MCK_UImm7Lsb000, // user defined class 'anonymous_65628'
3333 MCK_UImm9, // user defined class 'anonymous_65629'
3334 MCK_BareSImm11Lsb0, // user defined class 'anonymous_65640'
3335 MCK_SImm18, // user defined class 'anonymous_65641'
3336 MCK_SImm18Lsb0, // user defined class 'anonymous_65642'
3337 MCK_SImm19Lsb00, // user defined class 'anonymous_65643'
3338 MCK_SImm20Lsb000, // user defined class 'anonymous_65644'
3339 MCK_SImm10, // user defined class 'anonymous_65915'
3340 NumMatchClassKinds
3341};
3342
3343} // end anonymous namespace
3344
3345static const char *getMatchKindDiag(RISCVAsmParser::RISCVMatchResultTy MatchResult) {
3346 switch (MatchResult) {
3347 case RISCVAsmParser::Match_InvalidToken_40_:
3348 return "expected '('";
3349 case RISCVAsmParser::Match_InvalidToken_41_:
3350 return "expected ')'";
3351 case RISCVAsmParser::Match_InvalidRegClassGPRX0:
3352 return "register must be zero (x0)";
3353 case RISCVAsmParser::Match_InvalidRegClassGPRX1:
3354 return "register must be ra (x1)";
3355 case RISCVAsmParser::Match_InvalidRegClassGPRX5:
3356 return "register must be t0 (x5)";
3357 case RISCVAsmParser::Match_InvalidRegClassSP:
3358 return "register must be sp (x2)";
3359 case RISCVAsmParser::Match_InvalidRegClassGPRX1X5:
3360 return "register must be ra or t0 (x1 or x5)";
3361 case RISCVAsmParser::Match_InvalidRegClassFPR16C:
3362 return "register must be a FPR from f8 to f15 (fs0-fs1, fa0-fa5)";
3363 case RISCVAsmParser::Match_InvalidRegClassFPR32C:
3364 return "register must be a FPR from f8 to f15 (fs0-fs1, fa0-fa5)";
3365 case RISCVAsmParser::Match_InvalidRegClassFPR64C:
3366 return "register must be a FPR from f8 to f15 (fs0-fs1, fa0-fa5)";
3367 case RISCVAsmParser::Match_GPRC:
3368 return "register must be a GPR from x8 to x15";
3369 case RISCVAsmParser::Match_InvalidRegClassGPRS07:
3370 return "register must be GPR from s0 to s7 (x8, x9 or x18-x23)";
3371 case RISCVAsmParser::Match_InvalidRegClassGPRNoX0X2:
3372 return "register must be a GPR excluding zero (x0) and sp (x2)";
3373 case RISCVAsmParser::Match_InvalidRegClassGPRNoX0:
3374 return "register must be a GPR excluding zero (x0)";
3375 case RISCVAsmParser::Match_InvalidRegClassGPRNoX2:
3376 return "register must be a GPR excluding sp (x2)";
3377 case RISCVAsmParser::Match_InvalidRegClassGPRX31:
3378 return "register must be a GPR excluding t6 (x31)";
3379 case RISCVAsmParser::Match_InvalidRegClassFPR128:
3380 return "register must be a FPR";
3381 case RISCVAsmParser::Match_InvalidRegClassFPR16:
3382 return "register must be a FPR";
3383 case RISCVAsmParser::Match_InvalidRegClassFPR256:
3384 return "register must be a FPR";
3385 case RISCVAsmParser::Match_InvalidRegClassFPR32:
3386 return "register must be a FPR";
3387 case RISCVAsmParser::Match_InvalidRegClassFPR64:
3388 return "register must be a FPR";
3389 case RISCVAsmParser::Match_InvalidRegClassGPR:
3390 return "register must be a GPR";
3391 case RISCVAsmParser::Match_InvalidBareSymbol:
3392 return "operand must be a bare symbol name";
3393 case RISCVAsmParser::Match_InvalidTailCallSymbol:
3394 return "operand must be a bare symbol name";
3395 case RISCVAsmParser::Match_InvalidCallSymbol:
3396 return "operand must be a bare symbol name";
3397 case RISCVAsmParser::Match_GPRAsFPR16:
3398 return "register must be a GPR when used as an FP operand";
3399 case RISCVAsmParser::Match_GPRAsFPR32:
3400 return "register must be a GPR when used as an FP operand";
3401 case RISCVAsmParser::Match_GPRF64AsFPR:
3402 return "register must be a GPR when used as an FP operand";
3403 case RISCVAsmParser::Match_GPRPairAsFPR:
3404 return "register must be an even-numbered GPR when used as an FP operand";
3405 case RISCVAsmParser::Match_InvalidGPRPairCRV32:
3406 return "register pair must start with x8, x10, x12, or x14";
3407 case RISCVAsmParser::Match_InvalidGPRPairNoX0RV32:
3408 return "register pair must start with an even GPR other than x0";
3409 case RISCVAsmParser::Match_InvalidImmFour:
3410 return "operand must be constant 4";
3411 case RISCVAsmParser::Match_InvalidImmThree:
3412 return "operand must be constant 3";
3413 case RISCVAsmParser::Match_InvalidImmZero:
3414 return "immediate must be zero";
3415 case RISCVAsmParser::Match_InvalidLoadFPImm:
3416 return "operand must be a valid floating-point constant";
3417 case RISCVAsmParser::Match_InvalidPseudoJumpSymbol:
3418 return "operand must be a valid jump target";
3419 case RISCVAsmParser::Match_InvalidQCAccessSymbol:
3420 return "operand must be a symbol with a %qc.access specifier";
3421 case RISCVAsmParser::Match_InvalidRTZArg:
3422 return "operand must be 'rtz' floating-point rounding mode";
3423 case RISCVAsmParser::Match_InvalidRegList:
3424 return "operand must be {ra [, s0[-sN]]} or {x1 [, x8[-x9][, x18[-xN]]]}";
3425 case RISCVAsmParser::Match_InvalidRegListS0:
3426 return "operand must be {ra, s0[-sN]} or {x1, x8[-x9][, x18[-xN]]}";
3427 case RISCVAsmParser::Match_InvalidSMTI8:
3428 return "smt.vmadot with slide only supports i8 type";
3429 case RISCVAsmParser::Match_InvalidSMTType:
3430 return "This Inst only supports i4 and i8, i8 is the default type";
3431 case RISCVAsmParser::Match_InvalidTLSDESCCallSymbol:
3432 return "operand must be a symbol with %tlsdesc_call specifier";
3433 case RISCVAsmParser::Match_InvalidTPRelAddSymbol:
3434 return "operand must be a symbol with %tprel_add specifier";
3435 case RISCVAsmParser::Match_InvalidTileLambda:
3436 return "operand must be L1, L2, L4, L8, L16, L32, or L64";
3437 case RISCVAsmParser::Match_InvalidVMaskRegister:
3438 return "operand must be v0.t";
3439 case RISCVAsmParser::Match_InvalidVMaskCarryInRegister:
3440 return "operand must be v0";
3441 case RISCVAsmParser::Match_InvalidVScaleRegister:
3442 return "operand must be v0.scale";
3443 default:
3444 return nullptr;
3445 }
3446}
3447
3448static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
3449 switch (RegisterClass) {
3450 case MCK_GPRX0:
3451 return RISCVAsmParser::Match_InvalidRegClassGPRX0;
3452 case MCK_GPRX1:
3453 return RISCVAsmParser::Match_InvalidRegClassGPRX1;
3454 case MCK_GPRX5:
3455 return RISCVAsmParser::Match_InvalidRegClassGPRX5;
3456 case MCK_SP:
3457 return RISCVAsmParser::Match_InvalidRegClassSP;
3458 case MCK_GPRX1X5:
3459 return RISCVAsmParser::Match_InvalidRegClassGPRX1X5;
3460 case MCK_FPR16C:
3461 return RISCVAsmParser::Match_InvalidRegClassFPR16C;
3462 case MCK_FPR32C:
3463 return RISCVAsmParser::Match_InvalidRegClassFPR32C;
3464 case MCK_FPR64C:
3465 return RISCVAsmParser::Match_InvalidRegClassFPR64C;
3466 case MCK_GPRC:
3467 return RISCVAsmParser::Match_GPRC;
3468 case MCK_GPRS07:
3469 return RISCVAsmParser::Match_InvalidRegClassGPRS07;
3470 case MCK_GPRNoX0X2:
3471 return RISCVAsmParser::Match_InvalidRegClassGPRNoX0X2;
3472 case MCK_GPRNoX0:
3473 return RISCVAsmParser::Match_InvalidRegClassGPRNoX0;
3474 case MCK_GPRNoX2:
3475 return RISCVAsmParser::Match_InvalidRegClassGPRNoX2;
3476 case MCK_GPRNoX31:
3477 return RISCVAsmParser::Match_InvalidRegClassGPRX31;
3478 case MCK_FPR128:
3479 return RISCVAsmParser::Match_InvalidRegClassFPR128;
3480 case MCK_FPR16:
3481 return RISCVAsmParser::Match_InvalidRegClassFPR16;
3482 case MCK_FPR256:
3483 return RISCVAsmParser::Match_InvalidRegClassFPR256;
3484 case MCK_FPR32:
3485 return RISCVAsmParser::Match_InvalidRegClassFPR32;
3486 case MCK_FPR64:
3487 return RISCVAsmParser::Match_InvalidRegClassFPR64;
3488 case MCK_GPR:
3489 return RISCVAsmParser::Match_InvalidRegClassGPR;
3490 default:
3491 return MCTargetAsmParser::Match_InvalidOperand;
3492 }
3493}
3494
3495[[maybe_unused]] static const MCRegisterClass *getRegClassFromMatchKind(MatchClassKind Kind) {
3496 switch (Kind) {
3497 case MCK_GPRF16X0:
3498 return &getRISCVMCRegisterClass(RISCV::GPRF16X0RegClassID);
3499 case MCK_GPRF32X0:
3500 return &getRISCVMCRegisterClass(RISCV::GPRF32X0RegClassID);
3501 case MCK_GPRX0:
3502 return &getRISCVMCRegisterClass(RISCV::GPRX0RegClassID);
3503 case MCK_GPRX1:
3504 return &getRISCVMCRegisterClass(RISCV::GPRX1RegClassID);
3505 case MCK_GPRX5:
3506 return &getRISCVMCRegisterClass(RISCV::GPRX5RegClassID);
3507 case MCK_GPRX7:
3508 return &getRISCVMCRegisterClass(RISCV::GPRX7RegClassID);
3509 case MCK_MR0:
3510 return &getRISCVMCRegisterClass(RISCV::MR0RegClassID);
3511 case MCK_SP:
3512 return &getRISCVMCRegisterClass(RISCV::SPRegClassID);
3513 case MCK_VMV0:
3514 return &getRISCVMCRegisterClass(RISCV::VMV0RegClassID);
3515 case MCK_anonymous_15514:
3516 return &getRISCVMCRegisterClass(RISCV::anonymous_15514RegClassID);
3517 case MCK_GPRX1X5:
3518 return &getRISCVMCRegisterClass(RISCV::GPRX1X5RegClassID);
3519 case MCK_VCSR:
3520 return &getRISCVMCRegisterClass(RISCV::VCSRRegClassID);
3521 case MCK_VRM8NoV0:
3522 return &getRISCVMCRegisterClass(RISCV::VRM8NoV0RegClassID);
3523 case MCK_GPRPairC:
3524 return &getRISCVMCRegisterClass(RISCV::GPRPairCRegClassID);
3525 case MCK_TRM4:
3526 return &getRISCVMCRegisterClass(RISCV::TRM4RegClassID);
3527 case MCK_VRM8:
3528 return &getRISCVMCRegisterClass(RISCV::VRM8RegClassID);
3529 case MCK_VRN2M4NoV0:
3530 return &getRISCVMCRegisterClass(RISCV::VRN2M4NoV0RegClassID);
3531 case MCK_VRM4NoV0:
3532 return &getRISCVMCRegisterClass(RISCV::VRM4NoV0RegClassID);
3533 case MCK_VRN2M4:
3534 return &getRISCVMCRegisterClass(RISCV::VRN2M4RegClassID);
3535 case MCK_FPR16C:
3536 return &getRISCVMCRegisterClass(RISCV::FPR16CRegClassID);
3537 case MCK_FPR32C:
3538 return &getRISCVMCRegisterClass(RISCV::FPR32CRegClassID);
3539 case MCK_FPR64C:
3540 return &getRISCVMCRegisterClass(RISCV::FPR64CRegClassID);
3541 case MCK_GPRC:
3542 return &getRISCVMCRegisterClass(RISCV::GPRCRegClassID);
3543 case MCK_GPRF16C:
3544 return &getRISCVMCRegisterClass(RISCV::GPRF16CRegClassID);
3545 case MCK_GPRF32C:
3546 return &getRISCVMCRegisterClass(RISCV::GPRF32CRegClassID);
3547 case MCK_GPRS07:
3548 return &getRISCVMCRegisterClass(RISCV::GPRS07RegClassID);
3549 case MCK_MR:
3550 return &getRISCVMCRegisterClass(RISCV::MRRegClassID);
3551 case MCK_TRM2:
3552 return &getRISCVMCRegisterClass(RISCV::TRM2RegClassID);
3553 case MCK_VRM4:
3554 return &getRISCVMCRegisterClass(RISCV::VRM4RegClassID);
3555 case MCK_VRN4M2NoV0:
3556 return &getRISCVMCRegisterClass(RISCV::VRN4M2NoV0RegClassID);
3557 case MCK_GPRTCNonX7:
3558 return &getRISCVMCRegisterClass(RISCV::GPRTCNonX7RegClassID);
3559 case MCK_VRN3M2NoV0:
3560 return &getRISCVMCRegisterClass(RISCV::VRN3M2NoV0RegClassID);
3561 case MCK_VRN4M2:
3562 return &getRISCVMCRegisterClass(RISCV::VRN4M2RegClassID);
3563 case MCK_GPRTC:
3564 return &getRISCVMCRegisterClass(RISCV::GPRTCRegClassID);
3565 case MCK_VRN2M2NoV0:
3566 return &getRISCVMCRegisterClass(RISCV::VRN2M2NoV0RegClassID);
3567 case MCK_VRN3M2:
3568 return &getRISCVMCRegisterClass(RISCV::VRN3M2RegClassID);
3569 case MCK_GPRPairNoX0:
3570 return &getRISCVMCRegisterClass(RISCV::GPRPairNoX0RegClassID);
3571 case MCK_VRM2NoV0:
3572 return &getRISCVMCRegisterClass(RISCV::VRM2NoV0RegClassID);
3573 case MCK_VRN2M2:
3574 return &getRISCVMCRegisterClass(RISCV::VRN2M2RegClassID);
3575 case MCK_GPRPair:
3576 return &getRISCVMCRegisterClass(RISCV::GPRPairRegClassID);
3577 case MCK_TR:
3578 return &getRISCVMCRegisterClass(RISCV::TRRegClassID);
3579 case MCK_VRM2:
3580 return &getRISCVMCRegisterClass(RISCV::VRM2RegClassID);
3581 case MCK_VRN8M1NoV0:
3582 return &getRISCVMCRegisterClass(RISCV::VRN8M1NoV0RegClassID);
3583 case MCK_GPRJALRNonX7:
3584 return &getRISCVMCRegisterClass(RISCV::GPRJALRNonX7RegClassID);
3585 case MCK_VRN7M1NoV0:
3586 return &getRISCVMCRegisterClass(RISCV::VRN7M1NoV0RegClassID);
3587 case MCK_VRN8M1:
3588 return &getRISCVMCRegisterClass(RISCV::VRN8M1RegClassID);
3589 case MCK_GPRJALR:
3590 return &getRISCVMCRegisterClass(RISCV::GPRJALRRegClassID);
3591 case MCK_VRN6M1NoV0:
3592 return &getRISCVMCRegisterClass(RISCV::VRN6M1NoV0RegClassID);
3593 case MCK_VRN7M1:
3594 return &getRISCVMCRegisterClass(RISCV::VRN7M1RegClassID);
3595 case MCK_VRN5M1NoV0:
3596 return &getRISCVMCRegisterClass(RISCV::VRN5M1NoV0RegClassID);
3597 case MCK_VRN6M1:
3598 return &getRISCVMCRegisterClass(RISCV::VRN6M1RegClassID);
3599 case MCK_VRN4M1NoV0:
3600 return &getRISCVMCRegisterClass(RISCV::VRN4M1NoV0RegClassID);
3601 case MCK_VRN5M1:
3602 return &getRISCVMCRegisterClass(RISCV::VRN5M1RegClassID);
3603 case MCK_VRN3M1NoV0:
3604 return &getRISCVMCRegisterClass(RISCV::VRN3M1NoV0RegClassID);
3605 case MCK_VRN4M1:
3606 return &getRISCVMCRegisterClass(RISCV::VRN4M1RegClassID);
3607 case MCK_GPRNoX0X2:
3608 return &getRISCVMCRegisterClass(RISCV::GPRNoX0X2RegClassID);
3609 case MCK_VRN2M1NoV0:
3610 return &getRISCVMCRegisterClass(RISCV::VRN2M1NoV0RegClassID);
3611 case MCK_VRN3M1:
3612 return &getRISCVMCRegisterClass(RISCV::VRN3M1RegClassID);
3613 case MCK_GPRF16NoX0:
3614 return &getRISCVMCRegisterClass(RISCV::GPRF16NoX0RegClassID);
3615 case MCK_GPRF32NoX0:
3616 return &getRISCVMCRegisterClass(RISCV::GPRF32NoX0RegClassID);
3617 case MCK_GPRNoX0:
3618 return &getRISCVMCRegisterClass(RISCV::GPRNoX0RegClassID);
3619 case MCK_GPRNoX2:
3620 return &getRISCVMCRegisterClass(RISCV::GPRNoX2RegClassID);
3621 case MCK_GPRNoX31:
3622 return &getRISCVMCRegisterClass(RISCV::GPRNoX31RegClassID);
3623 case MCK_VRN2M1:
3624 return &getRISCVMCRegisterClass(RISCV::VRN2M1RegClassID);
3625 case MCK_VRNoV0:
3626 return &getRISCVMCRegisterClass(RISCV::VRNoV0RegClassID);
3627 case MCK_FPR128:
3628 return &getRISCVMCRegisterClass(RISCV::FPR128RegClassID);
3629 case MCK_FPR16:
3630 return &getRISCVMCRegisterClass(RISCV::FPR16RegClassID);
3631 case MCK_FPR256:
3632 return &getRISCVMCRegisterClass(RISCV::FPR256RegClassID);
3633 case MCK_FPR32:
3634 return &getRISCVMCRegisterClass(RISCV::FPR32RegClassID);
3635 case MCK_FPR64:
3636 return &getRISCVMCRegisterClass(RISCV::FPR64RegClassID);
3637 case MCK_GPR:
3638 return &getRISCVMCRegisterClass(RISCV::GPRRegClassID);
3639 case MCK_GPRF16:
3640 return &getRISCVMCRegisterClass(RISCV::GPRF16RegClassID);
3641 case MCK_GPRF32:
3642 return &getRISCVMCRegisterClass(RISCV::GPRF32RegClassID);
3643 case MCK_VR:
3644 return &getRISCVMCRegisterClass(RISCV::VRRegClassID);
3645 case MCK_YGPR:
3646 return &getRISCVMCRegisterClass(RISCV::YGPRRegClassID);
3647 case MCK_GPRAsFPR16:
3648 return &getRISCVMCRegisterClass(RISCV::GPRF16RegClassID);
3649 case MCK_GPRAsFPR32:
3650 return &getRISCVMCRegisterClass(RISCV::GPRF32RegClassID);
3651 case MCK_GPRF64AsFPR:
3652 return &getRISCVMCRegisterClass(RISCV::GPRRegClassID);
3653 case MCK_GPRPairAsFPR:
3654 return &getRISCVMCRegisterClass(RISCV::GPRPairRegClassID);
3655 case MCK_GPRPairCRV32:
3656 return &getRISCVMCRegisterClass(RISCV::GPRPairCRegClassID);
3657 case MCK_GPRPairNoX0RV32:
3658 return &getRISCVMCRegisterClass(RISCV::GPRPairNoX0RegClassID);
3659 case MCK_GPRPairRV32:
3660 return &getRISCVMCRegisterClass(RISCV::GPRPairRegClassID);
3661 case MCK_GPRPairRV64:
3662 return &getRISCVMCRegisterClass(RISCV::GPRPairRegClassID);
3663 case MCK_RVVMaskRegOpOperand:
3664 return &getRISCVMCRegisterClass(RISCV::VMV0RegClassID);
3665 case MCK_RVVMaskCarryInRegOpOperand:
3666 return &getRISCVMCRegisterClass(RISCV::VMV0RegClassID);
3667 case MCK_RVVScaleRegOpOperand:
3668 return &getRISCVMCRegisterClass(RISCV::VMV0RegClassID);
3669 case MCK_ZeroOffsetMemOpOperand:
3670 return &getRISCVMCRegisterClass(RISCV::GPRRegClassID);
3671 default:
3672 return nullptr;
3673 }
3674}
3675
3676static MatchClassKind matchTokenString(StringRef Name) {
3677 switch (Name.size()) {
3678 default: break;
3679 case 1: // 2 strings to match.
3680 switch (Name[0]) {
3681 default: break;
3682 case '(': // 1 string to match.
3683 return MCK__40_; // "("
3684 case ')': // 1 string to match.
3685 return MCK__41_; // ")"
3686 }
3687 break;
3688 }
3689 return InvalidMatchClass;
3690}
3691
3692/// isSubclass - Compute whether \p A is a subclass of \p B.
3693static bool isSubclass(MatchClassKind A, MatchClassKind B) {
3694 if (A == B)
3695 return true;
3696
3697 [[maybe_unused]] static constexpr struct {
3698 uint32_t Offset;
3699 uint16_t Start;
3700 uint16_t Length;
3701 } Table[] = {
3702 {0, 0, 0},
3703 {0, 0, 0},
3704 {0, 0, 0},
3705 {0, 0, 0},
3706 {0, 107, 1},
3707 {1, 111, 1},
3708 {2, 113, 1},
3709 {3, 115, 1},
3710 {4, 85, 1},
3711 {5, 119, 1},
3712 {6, 91, 1},
3713 {7, 127, 1},
3714 {8, 57, 1},
3715 {9, 95, 1},
3716 {10, 136, 1},
3717 {11, 48, 1},
3718 {12, 71, 1},
3719 {13, 98, 1},
3720 {14, 45, 52},
3721 {66, 51, 46},
3722 {112, 79, 18},
3723 {130, 87, 10},
3724 {140, 92, 5},
3725 {145, 81, 67},
3726 {212, 39, 109},
3727 {321, 121, 27},
3728 {348, 39, 109},
3729 {457, 122, 26},
3730 {483, 144, 1},
3731 {484, 145, 1},
3732 {485, 124, 20},
3733 {505, 41, 103},
3734 {608, 41, 103},
3735 {711, 82, 62},
3736 {773, 69, 1},
3737 {774, 123, 21},
3738 {795, 146, 1},
3739 {796, 0, 0},
3740 {796, 60, 88},
3741 {884, 116, 32},
3742 {916, 65, 79},
3743 {995, 117, 27},
3744 {1022, 46, 51},
3745 {1073, 0, 0},
3746 {1073, 48, 1},
3747 {1074, 72, 25},
3748 {1099, 72, 25},
3749 {1124, 70, 28},
3750 {1152, 0, 0},
3751 {1152, 50, 47},
3752 {1199, 55, 42},
3753 {1241, 55, 42},
3754 {1283, 61, 87},
3755 {1370, 65, 79},
3756 {1449, 57, 1},
3757 {1450, 78, 19},
3758 {1469, 71, 1},
3759 {1470, 0, 0},
3760 {1470, 140, 1},
3761 {1471, 138, 1},
3762 {1472, 99, 49},
3763 {1521, 99, 49},
3764 {1570, 139, 1},
3765 {1571, 141, 1},
3766 {1572, 142, 1},
3767 {1573, 100, 44},
3768 {1617, 131, 14},
3769 {1631, 132, 14},
3770 {1645, 100, 44},
3771 {1689, 0, 0},
3772 {1689, 97, 1},
3773 {1690, 0, 0},
3774 {1690, 73, 24},
3775 {1714, 78, 19},
3776 {1733, 78, 19},
3777 {1752, 80, 68},
3778 {1820, 82, 62},
3779 {1882, 85, 1},
3780 {1883, 86, 11},
3781 {1894, 86, 11},
3782 {1905, 88, 60},
3783 {1965, 88, 60},
3784 {2025, 89, 55},
3785 {2080, 89, 55},
3786 {2135, 91, 1},
3787 {2136, 0, 0},
3788 {2136, 92, 5},
3789 {2141, 93, 4},
3790 {2145, 108, 40},
3791 {2185, 109, 35},
3792 {2220, 95, 1},
3793 {2221, 0, 0},
3794 {2221, 96, 1},
3795 {2222, 96, 1},
3796 {2223, 98, 1},
3797 {2224, 0, 0},
3798 {2224, 0, 0},
3799 {2224, 0, 0},
3800 {2224, 0, 0},
3801 {2224, 102, 46},
3802 {2270, 104, 40},
3803 {2310, 107, 1},
3804 {2311, 108, 40},
3805 {2351, 108, 40},
3806 {2391, 109, 35},
3807 {2426, 109, 35},
3808 {2461, 111, 1},
3809 {2462, 0, 0},
3810 {2462, 120, 28},
3811 {2490, 125, 19},
3812 {2509, 113, 1},
3813 {2510, 0, 0},
3814 {2510, 115, 1},
3815 {2511, 0, 0},
3816 {2511, 119, 1},
3817 {2512, 0, 0},
3818 {2512, 120, 28},
3819 {2540, 123, 21},
3820 {2561, 127, 1},
3821 {2562, 0, 0},
3822 {2562, 128, 20},
3823 {2582, 128, 20},
3824 {2602, 129, 19},
3825 {2621, 133, 11},
3826 {2632, 134, 10},
3827 {2642, 133, 11},
3828 {2653, 136, 1},
3829 {2654, 0, 0},
3830 {2654, 147, 1},
3831 {2655, 147, 1},
3832 {2656, 147, 1},
3833 {2657, 144, 1},
3834 {2658, 145, 1},
3835 {2659, 143, 1},
3836 {2660, 143, 1},
3837 {2661, 143, 1},
3838 {2662, 0, 0},
3839 {2662, 146, 1},
3840 {2663, 0, 0},
3841 {2663, 0, 0},
3842 {2663, 0, 0},
3843 {2663, 0, 0},
3844 {2663, 0, 0},
3845 {2663, 0, 0},
3846 {2663, 0, 0},
3847 {2663, 0, 0},
3848 {2663, 0, 0},
3849 {2663, 0, 0},
3850 {2663, 0, 0},
3851 {2663, 0, 0},
3852 {2663, 0, 0},
3853 {2663, 0, 0},
3854 {2663, 0, 0},
3855 {2663, 0, 0},
3856 {2663, 0, 0},
3857 {2663, 156, 1},
3858 {2664, 0, 0},
3859 {2664, 1, 1},
3860 {2665, 1, 1},
3861 {2666, 0, 0},
3862 {2666, 0, 0},
3863 {2666, 0, 0},
3864 {2666, 0, 0},
3865 {2666, 0, 0},
3866 {2666, 0, 0},
3867 {2666, 0, 0},
3868 {2666, 0, 0},
3869 {2666, 0, 0},
3870 {2666, 0, 0},
3871 {2666, 0, 0},
3872 {2666, 0, 0},
3873 {2666, 0, 0},
3874 {2666, 0, 0},
3875 {2666, 0, 0},
3876 {2666, 0, 0},
3877 {2666, 0, 0},
3878 {2666, 0, 0},
3879 {2666, 0, 0},
3880 {2666, 0, 0},
3881 {2666, 0, 0},
3882 {2666, 0, 0},
3883 {2666, 0, 0},
3884 {2666, 0, 0},
3885 {2666, 0, 0},
3886 {2666, 0, 0},
3887 {2666, 0, 0},
3888 {2666, 1, 1},
3889 {2667, 1, 1},
3890 {2668, 0, 0},
3891 {2668, 0, 0},
3892 {2668, 0, 0},
3893 {2668, 0, 0},
3894 {2668, 0, 0},
3895 {2668, 0, 0},
3896 {2668, 0, 0},
3897 {2668, 1, 1},
3898 {2669, 0, 0},
3899 {2669, 0, 0},
3900 {2669, 0, 0},
3901 {2669, 0, 0},
3902 {2669, 0, 0},
3903 {2669, 0, 0},
3904 {2669, 0, 0},
3905 {2669, 0, 0},
3906 {2669, 0, 0},
3907 {2669, 0, 0},
3908 {2669, 0, 0},
3909 {2669, 0, 0},
3910 {2669, 0, 0},
3911 {2669, 0, 0},
3912 {2669, 0, 0},
3913 {2669, 0, 0},
3914 {2669, 0, 0},
3915 {2669, 0, 0},
3916 {2669, 0, 0},
3917 {2669, 1, 1},
3918 {2670, 1, 1},
3919 {2671, 0, 0},
3920 {2671, 0, 0},
3921 {2671, 0, 0},
3922 {2671, 0, 0},
3923 {2671, 0, 0},
3924 {2671, 0, 0},
3925 {2671, 0, 0},
3926 {2671, 0, 0},
3927 {2671, 0, 0},
3928 {2671, 0, 0},
3929 {2671, 0, 0},
3930 {2671, 0, 0},
3931 {2671, 0, 0},
3932 {2671, 0, 0},
3933 {2671, 0, 0},
3934 {2671, 0, 0},
3935 {2671, 0, 0},
3936 {2671, 0, 0},
3937 {2671, 0, 0},
3938 {2671, 1, 1},
3939 {2672, 0, 0},
3940 {2672, 1, 1},
3941 {2673, 0, 0},
3942 {2673, 1, 1},
3943 {2674, 0, 0},
3944 {2674, 0, 0},
3945 {2674, 1, 1},
3946 {2675, 0, 0},
3947 {2675, 0, 0},
3948 {2675, 0, 0},
3949 {2675, 1, 1},
3950 {2676, 1, 1},
3951 {2677, 0, 0},
3952 {2677, 1, 1},
3953 {2678, 0, 0},
3954 {2678, 1, 1},
3955 {2679, 0, 0},
3956 {2679, 1, 1},
3957 {2680, 0, 0},
3958 {2680, 1, 1},
3959 {2681, 0, 0},
3960 {2681, 0, 0},
3961 {2681, 0, 0},
3962 {2681, 0, 0},
3963 {2681, 0, 0},
3964 {2681, 0, 0},
3965 {2681, 0, 0},
3966 {2681, 1, 1},
3967 {2682, 0, 0},
3968 {2682, 0, 0},
3969 {2682, 0, 0},
3970 {2682, 0, 0},
3971 {2682, 0, 0},
3972 {2682, 0, 0},
3973 {2682, 0, 0},
3974 {2682, 1, 1},
3975 {2683, 0, 0},
3976 {2683, 0, 0},
3977 {2683, 0, 0},
3978 {2683, 0, 0},
3979 {2683, 0, 0},
3980 {2683, 0, 0},
3981 {2683, 0, 0},
3982 {2683, 0, 0},
3983 {2683, 0, 0},
3984 {2683, 0, 0},
3985 };
3986
3987 static constexpr uint8_t Data[] = {
3988 0xFF,
3989 0xFF,
3990 0x00,
3991 0x00,
3992 0x00,
3993 0x8E,
3994 0x81,
3995 0x61,
3996 0x46,
3997 0x00,
3998 0x00,
3999 0x62,
4000 0x60,
4001 0x98,
4002 0x81,
4003 0x61,
4004 0x06,
4005 0x19,
4006 0x03,
4007 0x01,
4008 0x80,
4009 0x10,
4010 0x10,
4011 0x07,
4012 0x07,
4013 0x00,
4014 0x18,
4015 0x00,
4016 0x00,
4017 0x00,
4018 0x00,
4019 0x00,
4020 0x00,
4021 0x00,
4022 0x00,
4023 0x00,
4024 0xE2,
4025 0xE0,
4026 0x00,
4027 0x00,
4028 0x03,
4029 0x05,
4030 0x00,
4031 0x18,
4032 0x00,
4033 0x00,
4034 0x00,
4035 0x00,
4036 0x00,
4037 0x00,
4038 0x00,
4039 0x00,
4040 0x00,
4041 0xE2,
4042 0xE0,
4043 0x00,
4044 0x00,
4045 0x03,
4046 0x03,
4047 0x00,
4048 0x3C,
4049 0x80,
4050 0x01,
4051 0x03,
4052 0x00,
4053 0x00,
4054 0x00,
4055 0x00,
4056 0x00,
4057 0x00,
4058 0x00,
4059 0x00,
4060 0x20,
4061 0x38,
4062 0xE0,
4063 0x80,
4064 0x01,
4065 0x00,
4066 0x00,
4067 0x00,
4068 0x00,
4069 0x00,
4070 0x00,
4071 0x00,
4072 0x00,
4073 0x10,
4074 0x1C,
4075 0x70,
4076 0xC0,
4077 0x40,
4078 0x00,
4079 0x20,
4080 0x04,
4081 0x04,
4082 0x07,
4083 0x1C,
4084 0x70,
4085 0x00,
4086 0x05,
4087 0x3C,
4088 0x00,
4089 0x00,
4090 0x00,
4091 0x00,
4092 0xC8,
4093 0x10,
4094 0x10,
4095 0x07,
4096 0x07,
4097 0x00,
4098 0x18,
4099 0x07,
4100 0x07,
4101 0x00,
4102 0x98,
4103 0x00,
4104 0x00,
4105 0x00,
4106 0x80,
4107 0x18,
4108 0x01,
4109 0xC1,
4110 0x01,
4111 0x07,
4112 0x0C,
4113 0x0E,
4114 0x38,
4115 0x60,
4116 0x8E,
4117 0x00,
4118 0x00,
4119 0xC7,
4120 0xC0,
4121 0x30,
4122 0x1F,
4123 0x03,
4124 0xC3,
4125 0x3C,
4126 0x06,
4127 0x86,
4128 0x19,
4129 0x00,
4130 0x00,
4131 0x80,
4132 0x23,
4133 0x00,
4134 0xC0,
4135 0x31,
4136 0x30,
4137 0xCC,
4138 0x00,
4139 0x00,
4140 0x42,
4141 0x40,
4142 0x30,
4143 0x03,
4144 0x00,
4145 0x10,
4146 0x03,
4147 0xC3,
4148 0x0C,
4149 0x00,
4150 0xC2,
4151 0x40,
4152 0x00,
4153 0x32,
4154 0x04,
4155 0xC4,
4156 0xC1,
4157 0x01,
4158 0x00,
4159 0x06,
4160 0x20,
4161 0x18,
4162 0x04,
4163 0x20,
4164 0x46,
4165 0x40,
4166 0x70,
4167 0xC0,
4168 0x01,
4169 0x07,
4170 0x04,
4171 0xF3,
4172 0x19,
4173 0x02,
4174 0xE2,
4175 0xE0,
4176 0x00,
4177 0x00,
4178 0x33,
4179 0x04,
4180 0xC4,
4181 0xC1,
4182 0x01,
4183 0x00,
4184 0x3E,
4185 0x46,
4186 0x40,
4187 0x70,
4188 0xC0,
4189 0x01,
4190 0x03,
4191 0xC0,
4192 0x00,
4193 0x30,
4194 0x46,
4195 0x40,
4196 0x70,
4197 0xC0,
4198 0x01,
4199 0x8F,
4200 0x81,
4201 0x61,
4202 0x06,
4203 0x04,
4204 0x73,
4205 0x60,
4206 0x98,
4207 0x03,
4208 0x01,
4209 0xC8,
4210 0x10,
4211 0x10,
4212 0x07,
4213 0x07,
4214 0x00,
4215 0x38,
4216 0x08,
4217 0x40,
4218 0x8C,
4219 0x80,
4220 0xE0,
4221 0x80,
4222 0x03,
4223 0x0E,
4224 0xE6,
4225 0x30,
4226 0x03,
4227 0x80,
4228 0x20,
4229 0x00,
4230 0x02,
4231 0x06,
4232 0x00,
4233 0x30,
4234 0x00,
4235 0x10,
4236 0x02,
4237 0xE2,
4238 0xE0,
4239 0x00,
4240 0x00,
4241 0x03,
4242 0x00,
4243 0x21,
4244 0x20,
4245 0x38,
4246 0xE0,
4247 0x80,
4248 0x01,
4249 0x00,
4250 0x11,
4251 0x00,
4252 0x10,
4253 0x30,
4254 0xC0,
4255 0x33,
4256 0x03,
4257 0x20,
4258 0x60,
4259 0x00,
4260 0x00,
4261 0x03,
4262 0x00,
4263 0x02,
4264 0x06,
4265 0xF8,
4266 0x43,
4267 0x40,
4268 0x1C,
4269 0x1C,
4270 0x00,
4271 0xE0,
4272 0x08,
4273 0x08,
4274 0x0E,
4275 0x38,
4276 0xE0,
4277 0x00,
4278 0x08,
4279 0x18,
4280 0x00,
4281 0xC0,
4282 0x80,
4283 0x38,
4284 0x38,
4285 0x00,
4286 0xC0,
4287 0x80,
4288 0xE0,
4289 0x80,
4290 0x03,
4291 0x06,
4292 0x00,
4293 0x04,
4294 0x0C,
4295 0x70,
4296 0xC0,
4297 0x00,
4298 0x00,
4299 0x06,
4300 0x0C,
4301 0xF0,
4302 0x07,
4303 0x07,
4304 0x00,
4305 0x78,
4306 0xC0,
4307 0x01,
4308 0x0F,
4309 0x00,
4310 0x60,
4311 0x01,
4312 0x00,
4313 0x0E,
4314 0x00,
4315 0xB0,
4316 0x80,
4317 0x03,
4318 0x0E,
4319 0xF0,
4320 0xFF,
4321 0xFF,
4322 0xFF,
4323 0x07,
4324 };
4325
4326 auto &Entry = Table[A];
4327 unsigned Idx = B - Entry.Start;
4328 if (Idx >= Entry.Length)
4329 return false;
4330 Idx += Entry.Offset;
4331 return (Data[Idx / 8] >> (Idx % 8)) & 1;
4332}
4333
4334static unsigned getDiagKindFromTokenClass(MatchClassKind Kind) {
4335 switch (Kind) {
4336 default:
4337 return MCTargetAsmParser::Match_InvalidOperand;
4338 case MCK__40_:
4339 return RISCVAsmParser::Match_InvalidToken_40_;
4340 case MCK__41_:
4341 return RISCVAsmParser::Match_InvalidToken_41_;
4342 }
4343}
4344
4345static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
4346 RISCVOperand &Operand = (RISCVOperand &)GOp;
4347 if (Kind == InvalidMatchClass)
4348 return MCTargetAsmParser::Match_InvalidOperand;
4349
4350 if (Kind <= MCK_LAST_TOKEN) {
4351 if (Operand.isToken() &&
4352 isSubclass(matchTokenString(Operand.getToken()), Kind))
4353 return MCTargetAsmParser::Match_Success;
4354 return getDiagKindFromTokenClass(Kind);
4355 }
4356
4357 switch (Kind) {
4358 default: break;
4359 case MCK_AnyRegCOperand: {
4360 DiagnosticPredicate DP(Operand.isAnyRegC());
4361 if (DP.isMatch())
4362 return MCTargetAsmParser::Match_Success;
4363 break;
4364 }
4365 case MCK_AnyRegOperand: {
4366 DiagnosticPredicate DP(Operand.isAnyReg());
4367 if (DP.isMatch())
4368 return MCTargetAsmParser::Match_Success;
4369 break;
4370 }
4371 case MCK_BareSymbol: {
4372 DiagnosticPredicate DP(Operand.isBareSymbol());
4373 if (DP.isMatch())
4374 return MCTargetAsmParser::Match_Success;
4375 if (DP.isNearMatch())
4376 return RISCVAsmParser::Match_InvalidBareSymbol;
4377 break;
4378 }
4379 case MCK_BareSymbolQC_E_LI: {
4380 DiagnosticPredicate DP(Operand.isBareSymbol());
4381 if (DP.isMatch())
4382 return MCTargetAsmParser::Match_Success;
4383 if (DP.isNearMatch())
4384 return RISCVAsmParser::Match_InvalidBareSymbolQC_E_LI;
4385 break;
4386 }
4387 case MCK_CLUIImm: {
4388 DiagnosticPredicate DP(Operand.isCLUIImm());
4389 if (DP.isMatch())
4390 return MCTargetAsmParser::Match_Success;
4391 if (DP.isNearMatch())
4392 return RISCVAsmParser::Match_InvalidCLUIImm;
4393 break;
4394 }
4395 case MCK_CSRSystemRegister: {
4396 DiagnosticPredicate DP(Operand.isCSRSystemRegister());
4397 if (DP.isMatch())
4398 return MCTargetAsmParser::Match_Success;
4399 if (DP.isNearMatch())
4400 return RISCVAsmParser::Match_InvalidCSRSystemRegister;
4401 break;
4402 }
4403 case MCK_RegReg: {
4404 DiagnosticPredicate DP(Operand.isRegReg());
4405 if (DP.isMatch())
4406 return MCTargetAsmParser::Match_Success;
4407 break;
4408 }
4409 case MCK_TailCallSymbol: {
4410 DiagnosticPredicate DP(Operand.isTailCallSymbol());
4411 if (DP.isMatch())
4412 return MCTargetAsmParser::Match_Success;
4413 if (DP.isNearMatch())
4414 return RISCVAsmParser::Match_InvalidTailCallSymbol;
4415 break;
4416 }
4417 case MCK_CallSymbol: {
4418 DiagnosticPredicate DP(Operand.isCallSymbol());
4419 if (DP.isMatch())
4420 return MCTargetAsmParser::Match_Success;
4421 if (DP.isNearMatch())
4422 return RISCVAsmParser::Match_InvalidCallSymbol;
4423 break;
4424 }
4425 case MCK_FRMArg: {
4426 DiagnosticPredicate DP(Operand.isFRMArg());
4427 if (DP.isMatch())
4428 return MCTargetAsmParser::Match_Success;
4429 break;
4430 }
4431 case MCK_FRMArgLegacy: {
4432 DiagnosticPredicate DP(Operand.isFRMArgLegacy());
4433 if (DP.isMatch())
4434 return MCTargetAsmParser::Match_Success;
4435 break;
4436 }
4437 case MCK_FenceArg: {
4438 DiagnosticPredicate DP(Operand.isFenceArg());
4439 if (DP.isMatch())
4440 return MCTargetAsmParser::Match_Success;
4441 break;
4442 }
4443 case MCK_GPRAsFPR16: {
4444 DiagnosticPredicate DP(Operand.isGPRAsFPR16());
4445 if (DP.isMatch())
4446 return MCTargetAsmParser::Match_Success;
4447 if (DP.isNearMatch())
4448 return RISCVAsmParser::Match_GPRAsFPR16;
4449 break;
4450 }
4451 case MCK_GPRAsFPR32: {
4452 DiagnosticPredicate DP(Operand.isGPRAsFPR32());
4453 if (DP.isMatch())
4454 return MCTargetAsmParser::Match_Success;
4455 if (DP.isNearMatch())
4456 return RISCVAsmParser::Match_GPRAsFPR32;
4457 break;
4458 }
4459 case MCK_GPRF64AsFPR: {
4460 DiagnosticPredicate DP(Operand.isGPRAsFPR());
4461 if (DP.isMatch())
4462 return MCTargetAsmParser::Match_Success;
4463 if (DP.isNearMatch())
4464 return RISCVAsmParser::Match_GPRF64AsFPR;
4465 break;
4466 }
4467 case MCK_GPRPairAsFPR: {
4468 DiagnosticPredicate DP(Operand.isGPRPairAsFPR64());
4469 if (DP.isMatch())
4470 return MCTargetAsmParser::Match_Success;
4471 if (DP.isNearMatch())
4472 return RISCVAsmParser::Match_GPRPairAsFPR;
4473 break;
4474 }
4475 case MCK_GPRPairCRV32: {
4476 DiagnosticPredicate DP(Operand.isGPRPairC());
4477 if (DP.isMatch())
4478 return MCTargetAsmParser::Match_Success;
4479 if (DP.isNearMatch())
4480 return RISCVAsmParser::Match_InvalidGPRPairCRV32;
4481 break;
4482 }
4483 case MCK_GPRPairNoX0RV32: {
4484 DiagnosticPredicate DP(Operand.isGPRPairNoX0());
4485 if (DP.isMatch())
4486 return MCTargetAsmParser::Match_Success;
4487 if (DP.isNearMatch())
4488 return RISCVAsmParser::Match_InvalidGPRPairNoX0RV32;
4489 break;
4490 }
4491 case MCK_GPRPairRV32: {
4492 DiagnosticPredicate DP(Operand.isGPRPair());
4493 if (DP.isMatch())
4494 return MCTargetAsmParser::Match_Success;
4495 break;
4496 }
4497 case MCK_GPRPairRV64: {
4498 DiagnosticPredicate DP(Operand.isGPRPair());
4499 if (DP.isMatch())
4500 return MCTargetAsmParser::Match_Success;
4501 break;
4502 }
4503 case MCK_Imm: {
4504 DiagnosticPredicate DP(Operand.isImm());
4505 if (DP.isMatch())
4506 return MCTargetAsmParser::Match_Success;
4507 break;
4508 }
4509 case MCK_ImmFour: {
4510 DiagnosticPredicate DP(Operand.isImmFour());
4511 if (DP.isMatch())
4512 return MCTargetAsmParser::Match_Success;
4513 if (DP.isNearMatch())
4514 return RISCVAsmParser::Match_InvalidImmFour;
4515 break;
4516 }
4517 case MCK_ImmThree: {
4518 DiagnosticPredicate DP(Operand.isImmThree());
4519 if (DP.isMatch())
4520 return MCTargetAsmParser::Match_Success;
4521 if (DP.isNearMatch())
4522 return RISCVAsmParser::Match_InvalidImmThree;
4523 break;
4524 }
4525 case MCK_ImmZero: {
4526 DiagnosticPredicate DP(Operand.isImmZero());
4527 if (DP.isMatch())
4528 return MCTargetAsmParser::Match_Success;
4529 if (DP.isNearMatch())
4530 return RISCVAsmParser::Match_InvalidImmZero;
4531 break;
4532 }
4533 case MCK_InsnCDirectiveOpcode: {
4534 DiagnosticPredicate DP(Operand.isImm());
4535 if (DP.isMatch())
4536 return MCTargetAsmParser::Match_Success;
4537 break;
4538 }
4539 case MCK_InsnDirectiveOpcode: {
4540 DiagnosticPredicate DP(Operand.isImm());
4541 if (DP.isMatch())
4542 return MCTargetAsmParser::Match_Success;
4543 break;
4544 }
4545 case MCK_LoadFPImm: {
4546 DiagnosticPredicate DP(Operand.isLoadFPImm());
4547 if (DP.isMatch())
4548 return MCTargetAsmParser::Match_Success;
4549 if (DP.isNearMatch())
4550 return RISCVAsmParser::Match_InvalidLoadFPImm;
4551 break;
4552 }
4553 case MCK_NegStackAdj: {
4554 DiagnosticPredicate DP(Operand.isStackAdj());
4555 if (DP.isMatch())
4556 return MCTargetAsmParser::Match_Success;
4557 if (DP.isNearMatch())
4558 return RISCVAsmParser::Match_InvalidStackAdj;
4559 break;
4560 }
4561 case MCK_PseudoJumpSymbol: {
4562 DiagnosticPredicate DP(Operand.isPseudoJumpSymbol());
4563 if (DP.isMatch())
4564 return MCTargetAsmParser::Match_Success;
4565 if (DP.isNearMatch())
4566 return RISCVAsmParser::Match_InvalidPseudoJumpSymbol;
4567 break;
4568 }
4569 case MCK_QCAccessSymbol: {
4570 DiagnosticPredicate DP(Operand.isQCAccessSymbol());
4571 if (DP.isMatch())
4572 return MCTargetAsmParser::Match_Success;
4573 if (DP.isNearMatch())
4574 return RISCVAsmParser::Match_InvalidQCAccessSymbol;
4575 break;
4576 }
4577 case MCK_RTZArg: {
4578 DiagnosticPredicate DP(Operand.isRTZArg());
4579 if (DP.isMatch())
4580 return MCTargetAsmParser::Match_Success;
4581 if (DP.isNearMatch())
4582 return RISCVAsmParser::Match_InvalidRTZArg;
4583 break;
4584 }
4585 case MCK_RegList: {
4586 DiagnosticPredicate DP(Operand.isRegList());
4587 if (DP.isMatch())
4588 return MCTargetAsmParser::Match_Success;
4589 if (DP.isNearMatch())
4590 return RISCVAsmParser::Match_InvalidRegList;
4591 break;
4592 }
4593 case MCK_RegListS0: {
4594 DiagnosticPredicate DP(Operand.isRegListS0());
4595 if (DP.isMatch())
4596 return MCTargetAsmParser::Match_Success;
4597 if (DP.isNearMatch())
4598 return RISCVAsmParser::Match_InvalidRegListS0;
4599 break;
4600 }
4601 case MCK_RnumArg: {
4602 DiagnosticPredicate DP(Operand.isRnumArg());
4603 if (DP.isMatch())
4604 return MCTargetAsmParser::Match_Success;
4605 if (DP.isNearMatch())
4606 return RISCVAsmParser::Match_InvalidRnumArg;
4607 break;
4608 }
4609 case MCK_SImm10PLI_H: {
4610 DiagnosticPredicate DP(Operand.isSImm10PLI_H());
4611 if (DP.isMatch())
4612 return MCTargetAsmParser::Match_Success;
4613 if (DP.isNearMatch())
4614 return RISCVAsmParser::Match_InvalidSImm10PLI_H;
4615 break;
4616 }
4617 case MCK_SImm10PLI_W: {
4618 DiagnosticPredicate DP(Operand.isSImm10PLI_W());
4619 if (DP.isMatch())
4620 return MCTargetAsmParser::Match_Success;
4621 if (DP.isNearMatch())
4622 return RISCVAsmParser::Match_InvalidSImm10PLI_W;
4623 break;
4624 }
4625 case MCK_SImm10PLUI: {
4626 DiagnosticPredicate DP(Operand.isSImm10PLUI());
4627 if (DP.isMatch())
4628 return MCTargetAsmParser::Match_Success;
4629 if (DP.isNearMatch())
4630 return RISCVAsmParser::Match_InvalidSImm10PLUI;
4631 break;
4632 }
4633 case MCK_SImm8PLI_B: {
4634 DiagnosticPredicate DP(Operand.isSImm8PLI_B());
4635 if (DP.isMatch())
4636 return MCTargetAsmParser::Match_Success;
4637 if (DP.isNearMatch())
4638 return RISCVAsmParser::Match_InvalidSImm8PLI_B;
4639 break;
4640 }
4641 case MCK_SMTI8: {
4642 DiagnosticPredicate DP(Operand.isSMTI8());
4643 if (DP.isMatch())
4644 return MCTargetAsmParser::Match_Success;
4645 if (DP.isNearMatch())
4646 return RISCVAsmParser::Match_InvalidSMTI8;
4647 break;
4648 }
4649 case MCK_SMTVType: {
4650 DiagnosticPredicate DP(Operand.isSMTVType());
4651 if (DP.isMatch())
4652 return MCTargetAsmParser::Match_Success;
4653 if (DP.isNearMatch())
4654 return RISCVAsmParser::Match_InvalidSMTType;
4655 break;
4656 }
4657 case MCK_BareSImm21Lsb0: {
4658 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<21>());
4659 if (DP.isMatch())
4660 return MCTargetAsmParser::Match_Success;
4661 if (DP.isNearMatch())
4662 return RISCVAsmParser::Match_InvalidBareSImm21Lsb0;
4663 break;
4664 }
4665 case MCK_StackAdj: {
4666 DiagnosticPredicate DP(Operand.isStackAdj());
4667 if (DP.isMatch())
4668 return MCTargetAsmParser::Match_Success;
4669 if (DP.isNearMatch())
4670 return RISCVAsmParser::Match_InvalidStackAdj;
4671 break;
4672 }
4673 case MCK_TLSDESCCallSymbol: {
4674 DiagnosticPredicate DP(Operand.isTLSDESCCallSymbol());
4675 if (DP.isMatch())
4676 return MCTargetAsmParser::Match_Success;
4677 if (DP.isNearMatch())
4678 return RISCVAsmParser::Match_InvalidTLSDESCCallSymbol;
4679 break;
4680 }
4681 case MCK_TPRelAddSymbol: {
4682 DiagnosticPredicate DP(Operand.isTPRelAddSymbol());
4683 if (DP.isMatch())
4684 return MCTargetAsmParser::Match_Success;
4685 if (DP.isNearMatch())
4686 return RISCVAsmParser::Match_InvalidTPRelAddSymbol;
4687 break;
4688 }
4689 case MCK_TileLambda: {
4690 DiagnosticPredicate DP(Operand.isTileLambda());
4691 if (DP.isMatch())
4692 return MCTargetAsmParser::Match_Success;
4693 if (DP.isNearMatch())
4694 return RISCVAsmParser::Match_InvalidTileLambda;
4695 break;
4696 }
4697 case MCK_UImmLog2XLen: {
4698 DiagnosticPredicate DP(Operand.isUImmLog2XLen());
4699 if (DP.isMatch())
4700 return MCTargetAsmParser::Match_Success;
4701 if (DP.isNearMatch())
4702 return RISCVAsmParser::Match_InvalidUImmLog2XLen;
4703 break;
4704 }
4705 case MCK_UImmLog2XLenNonZero: {
4706 DiagnosticPredicate DP(Operand.isUImmLog2XLenNonZero());
4707 if (DP.isMatch())
4708 return MCTargetAsmParser::Match_Success;
4709 if (DP.isNearMatch())
4710 return RISCVAsmParser::Match_InvalidUImmLog2XLenNonZero;
4711 break;
4712 }
4713 case MCK_RVVMaskRegOpOperand: {
4714 DiagnosticPredicate DP(Operand.isV0Reg());
4715 if (DP.isMatch())
4716 return MCTargetAsmParser::Match_Success;
4717 if (DP.isNearMatch())
4718 return RISCVAsmParser::Match_InvalidVMaskRegister;
4719 break;
4720 }
4721 case MCK_RVVMaskCarryInRegOpOperand: {
4722 DiagnosticPredicate DP(Operand.isV0Reg());
4723 if (DP.isMatch())
4724 return MCTargetAsmParser::Match_Success;
4725 if (DP.isNearMatch())
4726 return RISCVAsmParser::Match_InvalidVMaskCarryInRegister;
4727 break;
4728 }
4729 case MCK_RVVScaleRegOpOperand: {
4730 DiagnosticPredicate DP(Operand.isV0Reg());
4731 if (DP.isMatch())
4732 return MCTargetAsmParser::Match_Success;
4733 if (DP.isNearMatch())
4734 return RISCVAsmParser::Match_InvalidVScaleRegister;
4735 break;
4736 }
4737 case MCK_XSfmmVType: {
4738 DiagnosticPredicate DP(Operand.isXSfmmVType());
4739 if (DP.isMatch())
4740 return MCTargetAsmParser::Match_Success;
4741 break;
4742 }
4743 case MCK_YBNDSWImm: {
4744 DiagnosticPredicate DP(Operand.isYBNDSWImm());
4745 if (DP.isMatch())
4746 return MCTargetAsmParser::Match_Success;
4747 if (DP.isNearMatch())
4748 return RISCVAsmParser::Match_InvalidYBNDSWImm;
4749 break;
4750 }
4751 case MCK_ZeroOffsetMemOpOperand: {
4752 DiagnosticPredicate DP(Operand.isGPR());
4753 if (DP.isMatch())
4754 return MCTargetAsmParser::Match_Success;
4755 break;
4756 }
4757 case MCK_UImm1: {
4758 DiagnosticPredicate DP(Operand.isUImm<1>());
4759 if (DP.isMatch())
4760 return MCTargetAsmParser::Match_Success;
4761 if (DP.isNearMatch())
4762 return RISCVAsmParser::Match_InvalidUImm1;
4763 break;
4764 }
4765 case MCK_UImm2: {
4766 DiagnosticPredicate DP(Operand.isUImm<2>());
4767 if (DP.isMatch())
4768 return MCTargetAsmParser::Match_Success;
4769 if (DP.isNearMatch())
4770 return RISCVAsmParser::Match_InvalidUImm2;
4771 break;
4772 }
4773 case MCK_UImm3: {
4774 DiagnosticPredicate DP(Operand.isUImm<3>());
4775 if (DP.isMatch())
4776 return MCTargetAsmParser::Match_Success;
4777 if (DP.isNearMatch())
4778 return RISCVAsmParser::Match_InvalidUImm3;
4779 break;
4780 }
4781 case MCK_UImm4: {
4782 DiagnosticPredicate DP(Operand.isUImm<4>());
4783 if (DP.isMatch())
4784 return MCTargetAsmParser::Match_Success;
4785 if (DP.isNearMatch())
4786 return RISCVAsmParser::Match_InvalidUImm4;
4787 break;
4788 }
4789 case MCK_UImm5: {
4790 DiagnosticPredicate DP(Operand.isUImm<5>());
4791 if (DP.isMatch())
4792 return MCTargetAsmParser::Match_Success;
4793 if (DP.isNearMatch())
4794 return RISCVAsmParser::Match_InvalidUImm5;
4795 break;
4796 }
4797 case MCK_UImm6: {
4798 DiagnosticPredicate DP(Operand.isUImm<6>());
4799 if (DP.isMatch())
4800 return MCTargetAsmParser::Match_Success;
4801 if (DP.isNearMatch())
4802 return RISCVAsmParser::Match_InvalidUImm6;
4803 break;
4804 }
4805 case MCK_UImm7: {
4806 DiagnosticPredicate DP(Operand.isUImm<7>());
4807 if (DP.isMatch())
4808 return MCTargetAsmParser::Match_Success;
4809 if (DP.isNearMatch())
4810 return RISCVAsmParser::Match_InvalidUImm7;
4811 break;
4812 }
4813 case MCK_UImm8: {
4814 DiagnosticPredicate DP(Operand.isUImm<8>());
4815 if (DP.isMatch())
4816 return MCTargetAsmParser::Match_Success;
4817 if (DP.isNearMatch())
4818 return RISCVAsmParser::Match_InvalidUImm8;
4819 break;
4820 }
4821 case MCK_UImm16: {
4822 DiagnosticPredicate DP(Operand.isUImm<16>());
4823 if (DP.isMatch())
4824 return MCTargetAsmParser::Match_Success;
4825 if (DP.isNearMatch())
4826 return RISCVAsmParser::Match_InvalidUImm16;
4827 break;
4828 }
4829 case MCK_UImm32: {
4830 DiagnosticPredicate DP(Operand.isUImm<32>());
4831 if (DP.isMatch())
4832 return MCTargetAsmParser::Match_Success;
4833 if (DP.isNearMatch())
4834 return RISCVAsmParser::Match_InvalidUImm32;
4835 break;
4836 }
4837 case MCK_UImm48: {
4838 DiagnosticPredicate DP(Operand.isUImm<48>());
4839 if (DP.isMatch())
4840 return MCTargetAsmParser::Match_Success;
4841 if (DP.isNearMatch())
4842 return RISCVAsmParser::Match_InvalidUImm48;
4843 break;
4844 }
4845 case MCK_UImm64: {
4846 DiagnosticPredicate DP(Operand.isUImm<64>());
4847 if (DP.isMatch())
4848 return MCTargetAsmParser::Match_Success;
4849 if (DP.isNearMatch())
4850 return RISCVAsmParser::Match_InvalidUImm64;
4851 break;
4852 }
4853 case MCK_SImm12: {
4854 DiagnosticPredicate DP(Operand.isSImm<12>());
4855 if (DP.isMatch())
4856 return MCTargetAsmParser::Match_Success;
4857 if (DP.isNearMatch())
4858 return RISCVAsmParser::Match_InvalidSImm12;
4859 break;
4860 }
4861 case MCK_SImm12LO: {
4862 DiagnosticPredicate DP(Operand.isSImm12LO());
4863 if (DP.isMatch())
4864 return MCTargetAsmParser::Match_Success;
4865 if (DP.isNearMatch())
4866 return RISCVAsmParser::Match_InvalidSImm12LO;
4867 break;
4868 }
4869 case MCK_OptionalSImm12: {
4870 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isSImm<12>>());
4871 if (DP.isMatch())
4872 return MCTargetAsmParser::Match_Success;
4873 if (DP.isNearMatch())
4874 return RISCVAsmParser::Match_InvalidSImm12;
4875 break;
4876 }
4877 case MCK_OptionalSImm12LO: {
4878 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isSImm12LO>());
4879 if (DP.isMatch())
4880 return MCTargetAsmParser::Match_Success;
4881 if (DP.isNearMatch())
4882 return RISCVAsmParser::Match_InvalidSImm12LO;
4883 break;
4884 }
4885 case MCK_BareSImm13Lsb0: {
4886 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<13>());
4887 if (DP.isMatch())
4888 return MCTargetAsmParser::Match_Success;
4889 if (DP.isNearMatch())
4890 return RISCVAsmParser::Match_InvalidBareSImm13Lsb0;
4891 break;
4892 }
4893 case MCK_UImm20: {
4894 DiagnosticPredicate DP(Operand.isUImm<20>());
4895 if (DP.isMatch())
4896 return MCTargetAsmParser::Match_Success;
4897 if (DP.isNearMatch())
4898 return RISCVAsmParser::Match_InvalidUImm20;
4899 break;
4900 }
4901 case MCK_UImm20LUI: {
4902 DiagnosticPredicate DP(Operand.isUImm20LUI());
4903 if (DP.isMatch())
4904 return MCTargetAsmParser::Match_Success;
4905 if (DP.isNearMatch())
4906 return RISCVAsmParser::Match_InvalidUImm20LUI;
4907 break;
4908 }
4909 case MCK_UImm20AUIPC: {
4910 DiagnosticPredicate DP(Operand.isUImm20AUIPC());
4911 if (DP.isMatch())
4912 return MCTargetAsmParser::Match_Success;
4913 if (DP.isNearMatch())
4914 return RISCVAsmParser::Match_InvalidUImm20AUIPC;
4915 break;
4916 }
4917 case MCK_ImmXLenLI: {
4918 DiagnosticPredicate DP(Operand.isImmXLenLI());
4919 if (DP.isMatch())
4920 return MCTargetAsmParser::Match_Success;
4921 if (DP.isNearMatch())
4922 return RISCVAsmParser::Match_InvalidImmXLenLI;
4923 break;
4924 }
4925 case MCK_ImmXLenLI_Restricted: {
4926 DiagnosticPredicate DP(Operand.isImmXLenLI_Restricted());
4927 if (DP.isMatch())
4928 return MCTargetAsmParser::Match_Success;
4929 if (DP.isNearMatch())
4930 return RISCVAsmParser::Match_InvalidImmXLenLI_Restricted;
4931 break;
4932 }
4933 case MCK_SImm12Lsb00000: {
4934 DiagnosticPredicate DP(Operand.isSImm12Lsb00000());
4935 if (DP.isMatch())
4936 return MCTargetAsmParser::Match_Success;
4937 if (DP.isNearMatch())
4938 return RISCVAsmParser::Match_InvalidSImm12Lsb00000;
4939 break;
4940 }
4941 case MCK_Imm5Zibi: {
4942 DiagnosticPredicate DP(Operand.isImm5Zibi());
4943 if (DP.isMatch())
4944 return MCTargetAsmParser::Match_Success;
4945 if (DP.isNearMatch())
4946 return RISCVAsmParser::Match_InvalidImm5Zibi;
4947 break;
4948 }
4949 case MCK_VTypeI10: {
4950 DiagnosticPredicate DP(Operand.isVTypeI10());
4951 if (DP.isMatch())
4952 return MCTargetAsmParser::Match_Success;
4953 if (DP.isNearMatch())
4954 return RISCVAsmParser::Match_InvalidVTypeI;
4955 break;
4956 }
4957 case MCK_VTypeI11: {
4958 DiagnosticPredicate DP(Operand.isVTypeI11());
4959 if (DP.isMatch())
4960 return MCTargetAsmParser::Match_Success;
4961 if (DP.isNearMatch())
4962 return RISCVAsmParser::Match_InvalidVTypeI;
4963 break;
4964 }
4965 case MCK_SImm5: {
4966 DiagnosticPredicate DP(Operand.isSImm<5>());
4967 if (DP.isMatch())
4968 return MCTargetAsmParser::Match_Success;
4969 if (DP.isNearMatch())
4970 return RISCVAsmParser::Match_InvalidSImm5;
4971 break;
4972 }
4973 case MCK_SImm5Plus1: {
4974 DiagnosticPredicate DP(Operand.isSImm5Plus1());
4975 if (DP.isMatch())
4976 return MCTargetAsmParser::Match_Success;
4977 if (DP.isNearMatch())
4978 return RISCVAsmParser::Match_InvalidSImm5Plus1;
4979 break;
4980 }
4981 case MCK_UImm6Lsb000: {
4982 DiagnosticPredicate DP(Operand.isUImmShifted<3, 3>());
4983 if (DP.isMatch())
4984 return MCTargetAsmParser::Match_Success;
4985 if (DP.isNearMatch())
4986 return RISCVAsmParser::Match_InvalidUImm6Lsb000;
4987 break;
4988 }
4989 case MCK_UImm4Plus1: {
4990 DiagnosticPredicate DP(Operand.isUImm4Plus1());
4991 if (DP.isMatch())
4992 return MCTargetAsmParser::Match_Success;
4993 if (DP.isNearMatch())
4994 return RISCVAsmParser::Match_InvalidUImm4Plus1;
4995 break;
4996 }
4997 case MCK_UImm5Plus1: {
4998 DiagnosticPredicate DP(Operand.isUImm5Plus1());
4999 if (DP.isMatch())
5000 return MCTargetAsmParser::Match_Success;
5001 if (DP.isNearMatch())
5002 return RISCVAsmParser::Match_InvalidUImm5Plus1;
5003 break;
5004 }
5005 case MCK_UImm6Plus1: {
5006 DiagnosticPredicate DP(Operand.isUImm6Plus1());
5007 if (DP.isMatch())
5008 return MCTargetAsmParser::Match_Success;
5009 if (DP.isNearMatch())
5010 return RISCVAsmParser::Match_InvalidUImm6Plus1;
5011 break;
5012 }
5013 case MCK_SImm6: {
5014 DiagnosticPredicate DP(Operand.isSImm<6>());
5015 if (DP.isMatch())
5016 return MCTargetAsmParser::Match_Success;
5017 if (DP.isNearMatch())
5018 return RISCVAsmParser::Match_InvalidSImm6;
5019 break;
5020 }
5021 case MCK_SImm6NonZero: {
5022 DiagnosticPredicate DP(Operand.isSImm6NonZero());
5023 if (DP.isMatch())
5024 return MCTargetAsmParser::Match_Success;
5025 if (DP.isNearMatch())
5026 return RISCVAsmParser::Match_InvalidSImm6NonZero;
5027 break;
5028 }
5029 case MCK_UImm7Lsb00: {
5030 DiagnosticPredicate DP(Operand.isUImmShifted<5, 2>());
5031 if (DP.isMatch())
5032 return MCTargetAsmParser::Match_Success;
5033 if (DP.isNearMatch())
5034 return RISCVAsmParser::Match_InvalidUImm7Lsb00;
5035 break;
5036 }
5037 case MCK_OptionalUImm7Lsb00: {
5038 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImmShifted<5, 2>>());
5039 if (DP.isMatch())
5040 return MCTargetAsmParser::Match_Success;
5041 if (DP.isNearMatch())
5042 return RISCVAsmParser::Match_InvalidUImm7Lsb00;
5043 break;
5044 }
5045 case MCK_UImm8Lsb00: {
5046 DiagnosticPredicate DP(Operand.isUImmShifted<6, 2>());
5047 if (DP.isMatch())
5048 return MCTargetAsmParser::Match_Success;
5049 if (DP.isNearMatch())
5050 return RISCVAsmParser::Match_InvalidUImm8Lsb00;
5051 break;
5052 }
5053 case MCK_OptionalUImm8Lsb00: {
5054 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImmShifted<6, 2>>());
5055 if (DP.isMatch())
5056 return MCTargetAsmParser::Match_Success;
5057 if (DP.isNearMatch())
5058 return RISCVAsmParser::Match_InvalidUImm8Lsb00;
5059 break;
5060 }
5061 case MCK_UImm8Lsb000: {
5062 DiagnosticPredicate DP(Operand.isUImmShifted<5, 3>());
5063 if (DP.isMatch())
5064 return MCTargetAsmParser::Match_Success;
5065 if (DP.isNearMatch())
5066 return RISCVAsmParser::Match_InvalidUImm8Lsb000;
5067 break;
5068 }
5069 case MCK_OptionalUImm8Lsb000: {
5070 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImmShifted<5, 3>>());
5071 if (DP.isMatch())
5072 return MCTargetAsmParser::Match_Success;
5073 if (DP.isNearMatch())
5074 return RISCVAsmParser::Match_InvalidUImm8Lsb000;
5075 break;
5076 }
5077 case MCK_BareSImm9Lsb0: {
5078 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<9>());
5079 if (DP.isMatch())
5080 return MCTargetAsmParser::Match_Success;
5081 if (DP.isNearMatch())
5082 return RISCVAsmParser::Match_InvalidBareSImm9Lsb0;
5083 break;
5084 }
5085 case MCK_UImm9Lsb000: {
5086 DiagnosticPredicate DP(Operand.isUImmShifted<6, 3>());
5087 if (DP.isMatch())
5088 return MCTargetAsmParser::Match_Success;
5089 if (DP.isNearMatch())
5090 return RISCVAsmParser::Match_InvalidUImm9Lsb000;
5091 break;
5092 }
5093 case MCK_OptionalUImm9Lsb000: {
5094 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImmShifted<6, 3>>());
5095 if (DP.isMatch())
5096 return MCTargetAsmParser::Match_Success;
5097 if (DP.isNearMatch())
5098 return RISCVAsmParser::Match_InvalidUImm9Lsb000;
5099 break;
5100 }
5101 case MCK_UImm10Lsb00NonZero: {
5102 DiagnosticPredicate DP(Operand.isUImm10Lsb00NonZero());
5103 if (DP.isMatch())
5104 return MCTargetAsmParser::Match_Success;
5105 if (DP.isNearMatch())
5106 return RISCVAsmParser::Match_InvalidUImm10Lsb00NonZero;
5107 break;
5108 }
5109 case MCK_SImm10Lsb0000NonZero: {
5110 DiagnosticPredicate DP(Operand.isSImm10Lsb0000NonZero());
5111 if (DP.isMatch())
5112 return MCTargetAsmParser::Match_Success;
5113 if (DP.isNearMatch())
5114 return RISCVAsmParser::Match_InvalidSImm10Lsb0000NonZero;
5115 break;
5116 }
5117 case MCK_BareSImm12Lsb0: {
5118 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<12>());
5119 if (DP.isMatch())
5120 return MCTargetAsmParser::Match_Success;
5121 if (DP.isNearMatch())
5122 return RISCVAsmParser::Match_InvalidBareSImm12Lsb0;
5123 break;
5124 }
5125 case MCK_OptionalUImm5: {
5126 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImm<5>>());
5127 if (DP.isMatch())
5128 return MCTargetAsmParser::Match_Success;
5129 if (DP.isNearMatch())
5130 return RISCVAsmParser::Match_InvalidUImm5;
5131 break;
5132 }
5133 case MCK_OptionalUImm2: {
5134 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImm<2>>());
5135 if (DP.isMatch())
5136 return MCTargetAsmParser::Match_Success;
5137 if (DP.isNearMatch())
5138 return RISCVAsmParser::Match_InvalidUImm2;
5139 break;
5140 }
5141 case MCK_UImm2Lsb0: {
5142 DiagnosticPredicate DP(Operand.isUImmShifted<1, 1>());
5143 if (DP.isMatch())
5144 return MCTargetAsmParser::Match_Success;
5145 if (DP.isNearMatch())
5146 return RISCVAsmParser::Match_InvalidUImm2Lsb0;
5147 break;
5148 }
5149 case MCK_OptionalUImm2Lsb0: {
5150 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImmShifted<1, 1>>());
5151 if (DP.isMatch())
5152 return MCTargetAsmParser::Match_Success;
5153 if (DP.isNearMatch())
5154 return RISCVAsmParser::Match_InvalidUImm2Lsb0;
5155 break;
5156 }
5157 case MCK_UImm8GE32: {
5158 DiagnosticPredicate DP(Operand.isUImm8GE32());
5159 if (DP.isMatch())
5160 return MCTargetAsmParser::Match_Success;
5161 if (DP.isNearMatch())
5162 return RISCVAsmParser::Match_InvalidUImm8GE32;
5163 break;
5164 }
5165 case MCK_OptionalUImm4: {
5166 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImm<4>>());
5167 if (DP.isMatch())
5168 return MCTargetAsmParser::Match_Success;
5169 if (DP.isNearMatch())
5170 return RISCVAsmParser::Match_InvalidUImm4;
5171 break;
5172 }
5173 case MCK_UImm5Lsb0: {
5174 DiagnosticPredicate DP(Operand.isUImmShifted<4, 1>());
5175 if (DP.isMatch())
5176 return MCTargetAsmParser::Match_Success;
5177 if (DP.isNearMatch())
5178 return RISCVAsmParser::Match_InvalidUImm5Lsb0;
5179 break;
5180 }
5181 case MCK_OptionalUImm5Lsb0: {
5182 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImmShifted<4, 1>>());
5183 if (DP.isMatch())
5184 return MCTargetAsmParser::Match_Success;
5185 if (DP.isNearMatch())
5186 return RISCVAsmParser::Match_InvalidUImm5Lsb0;
5187 break;
5188 }
5189 case MCK_UImm6Lsb0: {
5190 DiagnosticPredicate DP(Operand.isUImmShifted<5, 1>());
5191 if (DP.isMatch())
5192 return MCTargetAsmParser::Match_Success;
5193 if (DP.isNearMatch())
5194 return RISCVAsmParser::Match_InvalidUImm6Lsb0;
5195 break;
5196 }
5197 case MCK_OptionalUImm6Lsb0: {
5198 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImmShifted<5, 1>>());
5199 if (DP.isMatch())
5200 return MCTargetAsmParser::Match_Success;
5201 if (DP.isNearMatch())
5202 return RISCVAsmParser::Match_InvalidUImm6Lsb0;
5203 break;
5204 }
5205 case MCK_UImm5NonZero: {
5206 DiagnosticPredicate DP(Operand.isUImm5NonZero());
5207 if (DP.isMatch())
5208 return MCTargetAsmParser::Match_Success;
5209 if (DP.isNearMatch())
5210 return RISCVAsmParser::Match_InvalidUImm5NonZero;
5211 break;
5212 }
5213 case MCK_UImm5GT3: {
5214 DiagnosticPredicate DP(Operand.isUImm5GT3());
5215 if (DP.isMatch())
5216 return MCTargetAsmParser::Match_Success;
5217 if (DP.isNearMatch())
5218 return RISCVAsmParser::Match_InvalidUImm5GT3;
5219 break;
5220 }
5221 case MCK_UImm5GE6Plus1: {
5222 DiagnosticPredicate DP(Operand.isUImm5GE6Plus1());
5223 if (DP.isMatch())
5224 return MCTargetAsmParser::Match_Success;
5225 if (DP.isNearMatch())
5226 return RISCVAsmParser::Match_InvalidUImm5GE6Plus1;
5227 break;
5228 }
5229 case MCK_UImm5Slist: {
5230 DiagnosticPredicate DP(Operand.isUImm5Slist());
5231 if (DP.isMatch())
5232 return MCTargetAsmParser::Match_Success;
5233 if (DP.isNearMatch())
5234 return RISCVAsmParser::Match_InvalidUImm5Slist;
5235 break;
5236 }
5237 case MCK_UImm10: {
5238 DiagnosticPredicate DP(Operand.isUImm<10>());
5239 if (DP.isMatch())
5240 return MCTargetAsmParser::Match_Success;
5241 if (DP.isNearMatch())
5242 return RISCVAsmParser::Match_InvalidUImm10;
5243 break;
5244 }
5245 case MCK_UImm11: {
5246 DiagnosticPredicate DP(Operand.isUImm<11>());
5247 if (DP.isMatch())
5248 return MCTargetAsmParser::Match_Success;
5249 if (DP.isNearMatch())
5250 return RISCVAsmParser::Match_InvalidUImm11;
5251 break;
5252 }
5253 case MCK_UImm14Lsb00: {
5254 DiagnosticPredicate DP(Operand.isUImmShifted<12, 2>());
5255 if (DP.isMatch())
5256 return MCTargetAsmParser::Match_Success;
5257 if (DP.isNearMatch())
5258 return RISCVAsmParser::Match_InvalidUImm14Lsb00;
5259 break;
5260 }
5261 case MCK_OptionalUImm14Lsb00: {
5262 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isUImmShifted<12, 2>>());
5263 if (DP.isMatch())
5264 return MCTargetAsmParser::Match_Success;
5265 if (DP.isNearMatch())
5266 return RISCVAsmParser::Match_InvalidUImm14Lsb00;
5267 break;
5268 }
5269 case MCK_UImm16NonZero: {
5270 DiagnosticPredicate DP(Operand.isUImm16NonZero());
5271 if (DP.isMatch())
5272 return MCTargetAsmParser::Match_Success;
5273 if (DP.isNearMatch())
5274 return RISCVAsmParser::Match_InvalidUImm16NonZero;
5275 break;
5276 }
5277 case MCK_SImm5NonZero: {
5278 DiagnosticPredicate DP(Operand.isSImm5NonZero());
5279 if (DP.isMatch())
5280 return MCTargetAsmParser::Match_Success;
5281 if (DP.isNearMatch())
5282 return RISCVAsmParser::Match_InvalidSImm5NonZero;
5283 break;
5284 }
5285 case MCK_SImm11: {
5286 DiagnosticPredicate DP(Operand.isSImm<11>());
5287 if (DP.isMatch())
5288 return MCTargetAsmParser::Match_Success;
5289 if (DP.isNearMatch())
5290 return RISCVAsmParser::Match_InvalidSImm11;
5291 break;
5292 }
5293 case MCK_SImm16: {
5294 DiagnosticPredicate DP(Operand.isSImm<16>());
5295 if (DP.isMatch())
5296 return MCTargetAsmParser::Match_Success;
5297 if (DP.isNearMatch())
5298 return RISCVAsmParser::Match_InvalidSImm16;
5299 break;
5300 }
5301 case MCK_SImm16NonZero: {
5302 DiagnosticPredicate DP(Operand.isSImm16NonZero());
5303 if (DP.isMatch())
5304 return MCTargetAsmParser::Match_Success;
5305 if (DP.isNearMatch())
5306 return RISCVAsmParser::Match_InvalidSImm16NonZero;
5307 break;
5308 }
5309 case MCK_SImm20LI: {
5310 DiagnosticPredicate DP(Operand.isSImm20LI());
5311 if (DP.isMatch())
5312 return MCTargetAsmParser::Match_Success;
5313 if (DP.isNearMatch())
5314 return RISCVAsmParser::Match_InvalidSImm20LI;
5315 break;
5316 }
5317 case MCK_SImm26: {
5318 DiagnosticPredicate DP(Operand.isSImm<26>());
5319 if (DP.isMatch())
5320 return MCTargetAsmParser::Match_Success;
5321 if (DP.isNearMatch())
5322 return RISCVAsmParser::Match_InvalidSImm26;
5323 break;
5324 }
5325 case MCK_OptionalSImm26: {
5326 DiagnosticPredicate DP(Operand.isOptionalMemOffset<&RISCVOperand::isSImm<26>>());
5327 if (DP.isMatch())
5328 return MCTargetAsmParser::Match_Success;
5329 if (DP.isNearMatch())
5330 return RISCVAsmParser::Match_InvalidSImm26;
5331 break;
5332 }
5333 case MCK_BareSImm32: {
5334 DiagnosticPredicate DP(Operand.isBareSimmN<32>());
5335 if (DP.isMatch())
5336 return MCTargetAsmParser::Match_Success;
5337 if (DP.isNearMatch())
5338 return RISCVAsmParser::Match_InvalidBareSImm32;
5339 break;
5340 }
5341 case MCK_BareSImm32Lsb0: {
5342 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<32>());
5343 if (DP.isMatch())
5344 return MCTargetAsmParser::Match_Success;
5345 if (DP.isNearMatch())
5346 return RISCVAsmParser::Match_InvalidBareSImm32Lsb0;
5347 break;
5348 }
5349 case MCK_UImm7Lsb000: {
5350 DiagnosticPredicate DP(Operand.isUImmShifted<4, 3>());
5351 if (DP.isMatch())
5352 return MCTargetAsmParser::Match_Success;
5353 if (DP.isNearMatch())
5354 return RISCVAsmParser::Match_InvalidUImm7Lsb000;
5355 break;
5356 }
5357 case MCK_UImm9: {
5358 DiagnosticPredicate DP(Operand.isUImm<9>());
5359 if (DP.isMatch())
5360 return MCTargetAsmParser::Match_Success;
5361 if (DP.isNearMatch())
5362 return RISCVAsmParser::Match_InvalidUImm9;
5363 break;
5364 }
5365 case MCK_BareSImm11Lsb0: {
5366 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<11>());
5367 if (DP.isMatch())
5368 return MCTargetAsmParser::Match_Success;
5369 if (DP.isNearMatch())
5370 return RISCVAsmParser::Match_InvalidBareSImm11Lsb0;
5371 break;
5372 }
5373 case MCK_SImm18: {
5374 DiagnosticPredicate DP(Operand.isSImm<18>());
5375 if (DP.isMatch())
5376 return MCTargetAsmParser::Match_Success;
5377 if (DP.isNearMatch())
5378 return RISCVAsmParser::Match_InvalidSImm18;
5379 break;
5380 }
5381 case MCK_SImm18Lsb0: {
5382 DiagnosticPredicate DP(Operand.isSImm18Lsb0());
5383 if (DP.isMatch())
5384 return MCTargetAsmParser::Match_Success;
5385 if (DP.isNearMatch())
5386 return RISCVAsmParser::Match_InvalidSImm18Lsb0;
5387 break;
5388 }
5389 case MCK_SImm19Lsb00: {
5390 DiagnosticPredicate DP(Operand.isSImm19Lsb00());
5391 if (DP.isMatch())
5392 return MCTargetAsmParser::Match_Success;
5393 if (DP.isNearMatch())
5394 return RISCVAsmParser::Match_InvalidSImm19Lsb00;
5395 break;
5396 }
5397 case MCK_SImm20Lsb000: {
5398 DiagnosticPredicate DP(Operand.isSImm20Lsb000());
5399 if (DP.isMatch())
5400 return MCTargetAsmParser::Match_Success;
5401 if (DP.isNearMatch())
5402 return RISCVAsmParser::Match_InvalidSImm20Lsb000;
5403 break;
5404 }
5405 case MCK_SImm10: {
5406 DiagnosticPredicate DP(Operand.isSImm<10>());
5407 if (DP.isMatch())
5408 return MCTargetAsmParser::Match_Success;
5409 if (DP.isNearMatch())
5410 return RISCVAsmParser::Match_InvalidSImm10;
5411 break;
5412 }
5413 } // end switch (Kind)
5414
5415 if (Operand.isReg()) {
5416 static constexpr uint16_t Table[RISCV::NUM_TARGET_REGS] = {
5417 InvalidMatchClass,
5418 InvalidMatchClass,
5419 InvalidMatchClass,
5420 InvalidMatchClass,
5421 MCK_anonymous_15514,
5422 InvalidMatchClass,
5423 MCK_VCSR,
5424 MCK_VCSR,
5425 MCK_VCSR,
5426 InvalidMatchClass,
5427 InvalidMatchClass,
5428 MCK_MR0,
5429 MCK_MR,
5430 MCK_MR,
5431 MCK_MR,
5432 MCK_MR,
5433 MCK_MR,
5434 MCK_MR,
5435 MCK_MR,
5436 MCK_TRM4,
5437 MCK_TR,
5438 MCK_TRM2,
5439 MCK_TR,
5440 MCK_TRM4,
5441 MCK_TR,
5442 MCK_TRM2,
5443 MCK_TR,
5444 MCK_TRM4,
5445 MCK_TR,
5446 MCK_TRM2,
5447 MCK_TR,
5448 MCK_TRM4,
5449 MCK_TR,
5450 MCK_TRM2,
5451 MCK_TR,
5452 MCK_VMV0,
5453 MCK_VRNoV0,
5454 MCK_VRNoV0,
5455 MCK_VRNoV0,
5456 MCK_VRNoV0,
5457 MCK_VRNoV0,
5458 MCK_VRNoV0,
5459 MCK_VRNoV0,
5460 MCK_VRNoV0,
5461 MCK_VRNoV0,
5462 MCK_VRNoV0,
5463 MCK_VRNoV0,
5464 MCK_VRNoV0,
5465 MCK_VRNoV0,
5466 MCK_VRNoV0,
5467 MCK_VRNoV0,
5468 MCK_VRNoV0,
5469 MCK_VRNoV0,
5470 MCK_VRNoV0,
5471 MCK_VRNoV0,
5472 MCK_VRNoV0,
5473 MCK_VRNoV0,
5474 MCK_VRNoV0,
5475 MCK_VRNoV0,
5476 MCK_VRNoV0,
5477 MCK_VRNoV0,
5478 MCK_VRNoV0,
5479 MCK_VRNoV0,
5480 MCK_VRNoV0,
5481 MCK_VRNoV0,
5482 MCK_VRNoV0,
5483 MCK_VRNoV0,
5484 MCK_GPRX0,
5485 MCK_GPRX1,
5486 MCK_SP,
5487 MCK_Reg16,
5488 MCK_Reg16,
5489 MCK_GPRX5,
5490 MCK_Reg27,
5491 MCK_GPRX7,
5492 MCK_Reg30,
5493 MCK_Reg30,
5494 MCK_Reg33,
5495 MCK_Reg33,
5496 MCK_Reg33,
5497 MCK_Reg33,
5498 MCK_Reg33,
5499 MCK_Reg33,
5500 MCK_Reg27,
5501 MCK_Reg27,
5502 MCK_GPRS07,
5503 MCK_GPRS07,
5504 MCK_GPRS07,
5505 MCK_GPRS07,
5506 MCK_GPRS07,
5507 MCK_GPRS07,
5508 MCK_Reg25,
5509 MCK_Reg25,
5510 MCK_Reg25,
5511 MCK_Reg25,
5512 MCK_Reg27,
5513 MCK_Reg27,
5514 MCK_Reg27,
5515 MCK_GPRTCNonX7,
5516 MCK_FPR64,
5517 MCK_FPR64,
5518 MCK_FPR64,
5519 MCK_FPR64,
5520 MCK_FPR64,
5521 MCK_FPR64,
5522 MCK_FPR64,
5523 MCK_FPR64,
5524 MCK_FPR64C,
5525 MCK_FPR64C,
5526 MCK_FPR64C,
5527 MCK_FPR64C,
5528 MCK_FPR64C,
5529 MCK_FPR64C,
5530 MCK_FPR64C,
5531 MCK_FPR64C,
5532 MCK_FPR64,
5533 MCK_FPR64,
5534 MCK_FPR64,
5535 MCK_FPR64,
5536 MCK_FPR64,
5537 MCK_FPR64,
5538 MCK_FPR64,
5539 MCK_FPR64,
5540 MCK_FPR64,
5541 MCK_FPR64,
5542 MCK_FPR64,
5543 MCK_FPR64,
5544 MCK_FPR64,
5545 MCK_FPR64,
5546 MCK_FPR64,
5547 MCK_FPR64,
5548 MCK_FPR32,
5549 MCK_FPR32,
5550 MCK_FPR32,
5551 MCK_FPR32,
5552 MCK_FPR32,
5553 MCK_FPR32,
5554 MCK_FPR32,
5555 MCK_FPR32,
5556 MCK_FPR32C,
5557 MCK_FPR32C,
5558 MCK_FPR32C,
5559 MCK_FPR32C,
5560 MCK_FPR32C,
5561 MCK_FPR32C,
5562 MCK_FPR32C,
5563 MCK_FPR32C,
5564 MCK_FPR32,
5565 MCK_FPR32,
5566 MCK_FPR32,
5567 MCK_FPR32,
5568 MCK_FPR32,
5569 MCK_FPR32,
5570 MCK_FPR32,
5571 MCK_FPR32,
5572 MCK_FPR32,
5573 MCK_FPR32,
5574 MCK_FPR32,
5575 MCK_FPR32,
5576 MCK_FPR32,
5577 MCK_FPR32,
5578 MCK_FPR32,
5579 MCK_FPR32,
5580 MCK_FPR16,
5581 MCK_FPR16,
5582 MCK_FPR16,
5583 MCK_FPR16,
5584 MCK_FPR16,
5585 MCK_FPR16,
5586 MCK_FPR16,
5587 MCK_FPR16,
5588 MCK_FPR16C,
5589 MCK_FPR16C,
5590 MCK_FPR16C,
5591 MCK_FPR16C,
5592 MCK_FPR16C,
5593 MCK_FPR16C,
5594 MCK_FPR16C,
5595 MCK_FPR16C,
5596 MCK_FPR16,
5597 MCK_FPR16,
5598 MCK_FPR16,
5599 MCK_FPR16,
5600 MCK_FPR16,
5601 MCK_FPR16,
5602 MCK_FPR16,
5603 MCK_FPR16,
5604 MCK_FPR16,
5605 MCK_FPR16,
5606 MCK_FPR16,
5607 MCK_FPR16,
5608 MCK_FPR16,
5609 MCK_FPR16,
5610 MCK_FPR16,
5611 MCK_FPR16,
5612 MCK_FPR128,
5613 MCK_FPR128,
5614 MCK_FPR128,
5615 MCK_FPR128,
5616 MCK_FPR128,
5617 MCK_FPR128,
5618 MCK_FPR128,
5619 MCK_FPR128,
5620 MCK_Reg89,
5621 MCK_Reg89,
5622 MCK_Reg89,
5623 MCK_Reg89,
5624 MCK_Reg89,
5625 MCK_Reg89,
5626 MCK_Reg89,
5627 MCK_Reg89,
5628 MCK_FPR128,
5629 MCK_FPR128,
5630 MCK_FPR128,
5631 MCK_FPR128,
5632 MCK_FPR128,
5633 MCK_FPR128,
5634 MCK_FPR128,
5635 MCK_FPR128,
5636 MCK_FPR128,
5637 MCK_FPR128,
5638 MCK_FPR128,
5639 MCK_FPR128,
5640 MCK_FPR128,
5641 MCK_FPR128,
5642 MCK_FPR128,
5643 MCK_FPR128,
5644 MCK_GPRF16X0,
5645 MCK_GPRF16NoX0,
5646 MCK_GPRF16NoX0,
5647 MCK_GPRF16NoX0,
5648 MCK_GPRF16NoX0,
5649 MCK_GPRF16NoX0,
5650 MCK_GPRF16NoX0,
5651 MCK_GPRF16NoX0,
5652 MCK_GPRF16C,
5653 MCK_GPRF16C,
5654 MCK_GPRF16C,
5655 MCK_GPRF16C,
5656 MCK_GPRF16C,
5657 MCK_GPRF16C,
5658 MCK_GPRF16C,
5659 MCK_GPRF16C,
5660 MCK_GPRF16NoX0,
5661 MCK_GPRF16NoX0,
5662 MCK_GPRF16NoX0,
5663 MCK_GPRF16NoX0,
5664 MCK_GPRF16NoX0,
5665 MCK_GPRF16NoX0,
5666 MCK_GPRF16NoX0,
5667 MCK_GPRF16NoX0,
5668 MCK_GPRF16NoX0,
5669 MCK_GPRF16NoX0,
5670 MCK_GPRF16NoX0,
5671 MCK_GPRF16NoX0,
5672 MCK_GPRF16NoX0,
5673 MCK_GPRF16NoX0,
5674 MCK_GPRF16NoX0,
5675 MCK_GPRF16NoX0,
5676 MCK_Reg60,
5677 MCK_GPRF32X0,
5678 MCK_GPRF32NoX0,
5679 MCK_GPRF32NoX0,
5680 MCK_GPRF32NoX0,
5681 MCK_GPRF32NoX0,
5682 MCK_GPRF32NoX0,
5683 MCK_GPRF32NoX0,
5684 MCK_GPRF32NoX0,
5685 MCK_GPRF32C,
5686 MCK_GPRF32C,
5687 MCK_GPRF32C,
5688 MCK_GPRF32C,
5689 MCK_GPRF32C,
5690 MCK_GPRF32C,
5691 MCK_GPRF32C,
5692 MCK_GPRF32C,
5693 MCK_GPRF32NoX0,
5694 MCK_GPRF32NoX0,
5695 MCK_GPRF32NoX0,
5696 MCK_GPRF32NoX0,
5697 MCK_GPRF32NoX0,
5698 MCK_GPRF32NoX0,
5699 MCK_GPRF32NoX0,
5700 MCK_GPRF32NoX0,
5701 MCK_GPRF32NoX0,
5702 MCK_GPRF32NoX0,
5703 MCK_GPRF32NoX0,
5704 MCK_GPRF32NoX0,
5705 MCK_GPRF32NoX0,
5706 MCK_GPRF32NoX0,
5707 MCK_GPRF32NoX0,
5708 MCK_GPRF32NoX0,
5709 MCK_Reg34,
5710 MCK_Reg39,
5711 MCK_Reg45,
5712 MCK_Reg42,
5713 MCK_Reg42,
5714 MCK_Reg46,
5715 MCK_Reg53,
5716 MCK_Reg55,
5717 MCK_Reg56,
5718 MCK_Reg56,
5719 MCK_Reg59,
5720 MCK_Reg59,
5721 MCK_Reg59,
5722 MCK_Reg59,
5723 MCK_Reg59,
5724 MCK_Reg59,
5725 MCK_Reg53,
5726 MCK_Reg53,
5727 MCK_Reg58,
5728 MCK_Reg58,
5729 MCK_Reg58,
5730 MCK_Reg58,
5731 MCK_Reg58,
5732 MCK_Reg58,
5733 MCK_Reg51,
5734 MCK_Reg51,
5735 MCK_Reg51,
5736 MCK_Reg51,
5737 MCK_Reg53,
5738 MCK_Reg53,
5739 MCK_Reg53,
5740 MCK_Reg54,
5741 MCK_FPR256,
5742 MCK_FPR256,
5743 MCK_FPR256,
5744 MCK_FPR256,
5745 MCK_FPR256,
5746 MCK_FPR256,
5747 MCK_FPR256,
5748 MCK_FPR256,
5749 MCK_Reg108,
5750 MCK_Reg108,
5751 MCK_Reg108,
5752 MCK_Reg108,
5753 MCK_Reg108,
5754 MCK_Reg108,
5755 MCK_Reg108,
5756 MCK_Reg108,
5757 MCK_FPR256,
5758 MCK_FPR256,
5759 MCK_FPR256,
5760 MCK_FPR256,
5761 MCK_FPR256,
5762 MCK_FPR256,
5763 MCK_FPR256,
5764 MCK_FPR256,
5765 MCK_FPR256,
5766 MCK_FPR256,
5767 MCK_FPR256,
5768 MCK_FPR256,
5769 MCK_FPR256,
5770 MCK_FPR256,
5771 MCK_FPR256,
5772 MCK_FPR256,
5773 MCK_Reg93,
5774 MCK_Reg96,
5775 MCK_Reg99,
5776 MCK_VRM2NoV0,
5777 MCK_VRM2NoV0,
5778 MCK_VRM4NoV0,
5779 MCK_VRM2NoV0,
5780 MCK_VRM2NoV0,
5781 MCK_VRM4NoV0,
5782 MCK_VRM8NoV0,
5783 MCK_VRM2NoV0,
5784 MCK_VRM2NoV0,
5785 MCK_VRM4NoV0,
5786 MCK_VRM2NoV0,
5787 MCK_VRM2NoV0,
5788 MCK_VRM4NoV0,
5789 MCK_VRM8NoV0,
5790 MCK_VRM2NoV0,
5791 MCK_VRM2NoV0,
5792 MCK_VRM4NoV0,
5793 MCK_VRM2NoV0,
5794 MCK_VRM2NoV0,
5795 MCK_VRM4NoV0,
5796 MCK_VRM8NoV0,
5797 MCK_VRM2NoV0,
5798 MCK_VRM2NoV0,
5799 MCK_VRM4NoV0,
5800 MCK_VRM2NoV0,
5801 MCK_Reg63,
5802 MCK_Reg66,
5803 MCK_Reg69,
5804 MCK_Reg74,
5805 MCK_Reg79,
5806 MCK_Reg79,
5807 MCK_Reg79,
5808 MCK_Reg80,
5809 MCK_Reg78,
5810 MCK_Reg78,
5811 MCK_Reg78,
5812 MCK_Reg76,
5813 MCK_Reg76,
5814 MCK_Reg80,
5815 MCK_Reg81,
5816 MCK_VRN2M1NoV0,
5817 MCK_VRN2M1NoV0,
5818 MCK_VRN2M1NoV0,
5819 MCK_VRN2M1NoV0,
5820 MCK_VRN2M1NoV0,
5821 MCK_VRN2M1NoV0,
5822 MCK_VRN2M1NoV0,
5823 MCK_VRN2M1NoV0,
5824 MCK_VRN2M1NoV0,
5825 MCK_VRN2M1NoV0,
5826 MCK_VRN2M1NoV0,
5827 MCK_VRN2M1NoV0,
5828 MCK_VRN2M1NoV0,
5829 MCK_VRN2M1NoV0,
5830 MCK_VRN2M1NoV0,
5831 MCK_VRN2M1NoV0,
5832 MCK_VRN2M1NoV0,
5833 MCK_VRN2M1NoV0,
5834 MCK_VRN2M1NoV0,
5835 MCK_VRN2M1NoV0,
5836 MCK_VRN2M1NoV0,
5837 MCK_VRN2M1NoV0,
5838 MCK_VRN2M1NoV0,
5839 MCK_VRN2M1NoV0,
5840 MCK_VRN2M1NoV0,
5841 MCK_VRN2M1NoV0,
5842 MCK_VRN2M1NoV0,
5843 MCK_VRN2M1NoV0,
5844 MCK_VRN2M1NoV0,
5845 MCK_VRN2M1NoV0,
5846 MCK_Reg113,
5847 MCK_VRN2M2NoV0,
5848 MCK_VRN2M2NoV0,
5849 MCK_VRN2M2NoV0,
5850 MCK_VRN2M2NoV0,
5851 MCK_VRN2M2NoV0,
5852 MCK_VRN2M2NoV0,
5853 MCK_VRN2M2NoV0,
5854 MCK_VRN2M2NoV0,
5855 MCK_VRN2M2NoV0,
5856 MCK_VRN2M2NoV0,
5857 MCK_VRN2M2NoV0,
5858 MCK_VRN2M2NoV0,
5859 MCK_VRN2M2NoV0,
5860 MCK_VRN2M2NoV0,
5861 MCK_Reg116,
5862 MCK_VRN2M4NoV0,
5863 MCK_VRN2M4NoV0,
5864 MCK_VRN2M4NoV0,
5865 MCK_VRN2M4NoV0,
5866 MCK_VRN2M4NoV0,
5867 MCK_VRN2M4NoV0,
5868 MCK_Reg119,
5869 MCK_VRN3M1NoV0,
5870 MCK_VRN3M1NoV0,
5871 MCK_VRN3M1NoV0,
5872 MCK_VRN3M1NoV0,
5873 MCK_VRN3M1NoV0,
5874 MCK_VRN3M1NoV0,
5875 MCK_VRN3M1NoV0,
5876 MCK_VRN3M1NoV0,
5877 MCK_VRN3M1NoV0,
5878 MCK_VRN3M1NoV0,
5879 MCK_VRN3M1NoV0,
5880 MCK_VRN3M1NoV0,
5881 MCK_VRN3M1NoV0,
5882 MCK_VRN3M1NoV0,
5883 MCK_VRN3M1NoV0,
5884 MCK_VRN3M1NoV0,
5885 MCK_VRN3M1NoV0,
5886 MCK_VRN3M1NoV0,
5887 MCK_VRN3M1NoV0,
5888 MCK_VRN3M1NoV0,
5889 MCK_VRN3M1NoV0,
5890 MCK_VRN3M1NoV0,
5891 MCK_VRN3M1NoV0,
5892 MCK_VRN3M1NoV0,
5893 MCK_VRN3M1NoV0,
5894 MCK_VRN3M1NoV0,
5895 MCK_VRN3M1NoV0,
5896 MCK_VRN3M1NoV0,
5897 MCK_VRN3M1NoV0,
5898 MCK_Reg122,
5899 MCK_VRN3M2NoV0,
5900 MCK_VRN3M2NoV0,
5901 MCK_VRN3M2NoV0,
5902 MCK_VRN3M2NoV0,
5903 MCK_VRN3M2NoV0,
5904 MCK_VRN3M2NoV0,
5905 MCK_VRN3M2NoV0,
5906 MCK_VRN3M2NoV0,
5907 MCK_VRN3M2NoV0,
5908 MCK_VRN3M2NoV0,
5909 MCK_VRN3M2NoV0,
5910 MCK_VRN3M2NoV0,
5911 MCK_VRN3M2NoV0,
5912 MCK_Reg125,
5913 MCK_VRN4M1NoV0,
5914 MCK_VRN4M1NoV0,
5915 MCK_VRN4M1NoV0,
5916 MCK_VRN4M1NoV0,
5917 MCK_VRN4M1NoV0,
5918 MCK_VRN4M1NoV0,
5919 MCK_VRN4M1NoV0,
5920 MCK_VRN4M1NoV0,
5921 MCK_VRN4M1NoV0,
5922 MCK_VRN4M1NoV0,
5923 MCK_VRN4M1NoV0,
5924 MCK_VRN4M1NoV0,
5925 MCK_VRN4M1NoV0,
5926 MCK_VRN4M1NoV0,
5927 MCK_VRN4M1NoV0,
5928 MCK_VRN4M1NoV0,
5929 MCK_VRN4M1NoV0,
5930 MCK_VRN4M1NoV0,
5931 MCK_VRN4M1NoV0,
5932 MCK_VRN4M1NoV0,
5933 MCK_VRN4M1NoV0,
5934 MCK_VRN4M1NoV0,
5935 MCK_VRN4M1NoV0,
5936 MCK_VRN4M1NoV0,
5937 MCK_VRN4M1NoV0,
5938 MCK_VRN4M1NoV0,
5939 MCK_VRN4M1NoV0,
5940 MCK_VRN4M1NoV0,
5941 MCK_Reg128,
5942 MCK_VRN4M2NoV0,
5943 MCK_VRN4M2NoV0,
5944 MCK_VRN4M2NoV0,
5945 MCK_VRN4M2NoV0,
5946 MCK_VRN4M2NoV0,
5947 MCK_VRN4M2NoV0,
5948 MCK_VRN4M2NoV0,
5949 MCK_VRN4M2NoV0,
5950 MCK_VRN4M2NoV0,
5951 MCK_VRN4M2NoV0,
5952 MCK_VRN4M2NoV0,
5953 MCK_VRN4M2NoV0,
5954 MCK_Reg131,
5955 MCK_VRN5M1NoV0,
5956 MCK_VRN5M1NoV0,
5957 MCK_VRN5M1NoV0,
5958 MCK_VRN5M1NoV0,
5959 MCK_VRN5M1NoV0,
5960 MCK_VRN5M1NoV0,
5961 MCK_VRN5M1NoV0,
5962 MCK_VRN5M1NoV0,
5963 MCK_VRN5M1NoV0,
5964 MCK_VRN5M1NoV0,
5965 MCK_VRN5M1NoV0,
5966 MCK_VRN5M1NoV0,
5967 MCK_VRN5M1NoV0,
5968 MCK_VRN5M1NoV0,
5969 MCK_VRN5M1NoV0,
5970 MCK_VRN5M1NoV0,
5971 MCK_VRN5M1NoV0,
5972 MCK_VRN5M1NoV0,
5973 MCK_VRN5M1NoV0,
5974 MCK_VRN5M1NoV0,
5975 MCK_VRN5M1NoV0,
5976 MCK_VRN5M1NoV0,
5977 MCK_VRN5M1NoV0,
5978 MCK_VRN5M1NoV0,
5979 MCK_VRN5M1NoV0,
5980 MCK_VRN5M1NoV0,
5981 MCK_VRN5M1NoV0,
5982 MCK_Reg134,
5983 MCK_VRN6M1NoV0,
5984 MCK_VRN6M1NoV0,
5985 MCK_VRN6M1NoV0,
5986 MCK_VRN6M1NoV0,
5987 MCK_VRN6M1NoV0,
5988 MCK_VRN6M1NoV0,
5989 MCK_VRN6M1NoV0,
5990 MCK_VRN6M1NoV0,
5991 MCK_VRN6M1NoV0,
5992 MCK_VRN6M1NoV0,
5993 MCK_VRN6M1NoV0,
5994 MCK_VRN6M1NoV0,
5995 MCK_VRN6M1NoV0,
5996 MCK_VRN6M1NoV0,
5997 MCK_VRN6M1NoV0,
5998 MCK_VRN6M1NoV0,
5999 MCK_VRN6M1NoV0,
6000 MCK_VRN6M1NoV0,
6001 MCK_VRN6M1NoV0,
6002 MCK_VRN6M1NoV0,
6003 MCK_VRN6M1NoV0,
6004 MCK_VRN6M1NoV0,
6005 MCK_VRN6M1NoV0,
6006 MCK_VRN6M1NoV0,
6007 MCK_VRN6M1NoV0,
6008 MCK_VRN6M1NoV0,
6009 MCK_Reg137,
6010 MCK_VRN7M1NoV0,
6011 MCK_VRN7M1NoV0,
6012 MCK_VRN7M1NoV0,
6013 MCK_VRN7M1NoV0,
6014 MCK_VRN7M1NoV0,
6015 MCK_VRN7M1NoV0,
6016 MCK_VRN7M1NoV0,
6017 MCK_VRN7M1NoV0,
6018 MCK_VRN7M1NoV0,
6019 MCK_VRN7M1NoV0,
6020 MCK_VRN7M1NoV0,
6021 MCK_VRN7M1NoV0,
6022 MCK_VRN7M1NoV0,
6023 MCK_VRN7M1NoV0,
6024 MCK_VRN7M1NoV0,
6025 MCK_VRN7M1NoV0,
6026 MCK_VRN7M1NoV0,
6027 MCK_VRN7M1NoV0,
6028 MCK_VRN7M1NoV0,
6029 MCK_VRN7M1NoV0,
6030 MCK_VRN7M1NoV0,
6031 MCK_VRN7M1NoV0,
6032 MCK_VRN7M1NoV0,
6033 MCK_VRN7M1NoV0,
6034 MCK_VRN7M1NoV0,
6035 MCK_Reg140,
6036 MCK_VRN8M1NoV0,
6037 MCK_VRN8M1NoV0,
6038 MCK_VRN8M1NoV0,
6039 MCK_VRN8M1NoV0,
6040 MCK_VRN8M1NoV0,
6041 MCK_VRN8M1NoV0,
6042 MCK_VRN8M1NoV0,
6043 MCK_VRN8M1NoV0,
6044 MCK_VRN8M1NoV0,
6045 MCK_VRN8M1NoV0,
6046 MCK_VRN8M1NoV0,
6047 MCK_VRN8M1NoV0,
6048 MCK_VRN8M1NoV0,
6049 MCK_VRN8M1NoV0,
6050 MCK_VRN8M1NoV0,
6051 MCK_VRN8M1NoV0,
6052 MCK_VRN8M1NoV0,
6053 MCK_VRN8M1NoV0,
6054 MCK_VRN8M1NoV0,
6055 MCK_VRN8M1NoV0,
6056 MCK_VRN8M1NoV0,
6057 MCK_VRN8M1NoV0,
6058 MCK_VRN8M1NoV0,
6059 MCK_VRN8M1NoV0,
6060 MCK_Reg143,
6061 };
6062
6063 MCRegister Reg = Operand.getReg();
6064 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
6065 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
6066 getDiagKindFromRegisterClass(Kind);
6067 }
6068
6069 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
6070 return getDiagKindFromRegisterClass(Kind);
6071
6072 return MCTargetAsmParser::Match_InvalidOperand;
6073}
6074
6075#ifndef NDEBUG
6076const char *getMatchClassName(MatchClassKind Kind) {
6077 switch (Kind) {
6078 case InvalidMatchClass: return "InvalidMatchClass";
6079 case OptionalMatchClass: return "OptionalMatchClass";
6080 case MCK__40_: return "MCK__40_";
6081 case MCK__41_: return "MCK__41_";
6082 case MCK_Reg143: return "MCK_Reg143";
6083 case MCK_Reg140: return "MCK_Reg140";
6084 case MCK_Reg137: return "MCK_Reg137";
6085 case MCK_Reg134: return "MCK_Reg134";
6086 case MCK_Reg131: return "MCK_Reg131";
6087 case MCK_Reg128: return "MCK_Reg128";
6088 case MCK_Reg125: return "MCK_Reg125";
6089 case MCK_Reg122: return "MCK_Reg122";
6090 case MCK_Reg119: return "MCK_Reg119";
6091 case MCK_Reg116: return "MCK_Reg116";
6092 case MCK_Reg113: return "MCK_Reg113";
6093 case MCK_Reg99: return "MCK_Reg99";
6094 case MCK_Reg96: return "MCK_Reg96";
6095 case MCK_Reg93: return "MCK_Reg93";
6096 case MCK_Reg74: return "MCK_Reg74";
6097 case MCK_Reg69: return "MCK_Reg69";
6098 case MCK_Reg66: return "MCK_Reg66";
6099 case MCK_Reg63: return "MCK_Reg63";
6100 case MCK_Reg60: return "MCK_Reg60";
6101 case MCK_Reg55: return "MCK_Reg55";
6102 case MCK_Reg46: return "MCK_Reg46";
6103 case MCK_Reg45: return "MCK_Reg45";
6104 case MCK_Reg39: return "MCK_Reg39";
6105 case MCK_Reg34: return "MCK_Reg34";
6106 case MCK_GPRF16X0: return "MCK_GPRF16X0";
6107 case MCK_GPRF32X0: return "MCK_GPRF32X0";
6108 case MCK_GPRX0: return "MCK_GPRX0";
6109 case MCK_GPRX1: return "MCK_GPRX1";
6110 case MCK_GPRX5: return "MCK_GPRX5";
6111 case MCK_GPRX7: return "MCK_GPRX7";
6112 case MCK_MR0: return "MCK_MR0";
6113 case MCK_SP: return "MCK_SP";
6114 case MCK_VMV0: return "MCK_VMV0";
6115 case MCK_anonymous_15514: return "MCK_anonymous_15514";
6116 case MCK_Reg56: return "MCK_Reg56";
6117 case MCK_Reg44: return "MCK_Reg44";
6118 case MCK_Reg30: return "MCK_Reg30";
6119 case MCK_GPRX1X5: return "MCK_GPRX1X5";
6120 case MCK_Reg79: return "MCK_Reg79";
6121 case MCK_VCSR: return "MCK_VCSR";
6122 case MCK_VRM8NoV0: return "MCK_VRM8NoV0";
6123 case MCK_Reg78: return "MCK_Reg78";
6124 case MCK_GPRPairC: return "MCK_GPRPairC";
6125 case MCK_TRM4: return "MCK_TRM4";
6126 case MCK_VRM8: return "MCK_VRM8";
6127 case MCK_Reg80: return "MCK_Reg80";
6128 case MCK_Reg81: return "MCK_Reg81";
6129 case MCK_Reg72: return "MCK_Reg72";
6130 case MCK_Reg59: return "MCK_Reg59";
6131 case MCK_Reg33: return "MCK_Reg33";
6132 case MCK_VRN2M4NoV0: return "MCK_VRN2M4NoV0";
6133 case MCK_Reg73: return "MCK_Reg73";
6134 case MCK_VRM4NoV0: return "MCK_VRM4NoV0";
6135 case MCK_VRN2M4: return "MCK_VRN2M4";
6136 case MCK_Reg108: return "MCK_Reg108";
6137 case MCK_Reg89: return "MCK_Reg89";
6138 case MCK_Reg58: return "MCK_Reg58";
6139 case MCK_Reg57: return "MCK_Reg57";
6140 case MCK_FPR16C: return "MCK_FPR16C";
6141 case MCK_FPR32C: return "MCK_FPR32C";
6142 case MCK_FPR64C: return "MCK_FPR64C";
6143 case MCK_GPRC: return "MCK_GPRC";
6144 case MCK_GPRF16C: return "MCK_GPRF16C";
6145 case MCK_GPRF32C: return "MCK_GPRF32C";
6146 case MCK_GPRS07: return "MCK_GPRS07";
6147 case MCK_MR: return "MCK_MR";
6148 case MCK_TRM2: return "MCK_TRM2";
6149 case MCK_VRM4: return "MCK_VRM4";
6150 case MCK_Reg76: return "MCK_Reg76";
6151 case MCK_Reg77: return "MCK_Reg77";
6152 case MCK_Reg70: return "MCK_Reg70";
6153 case MCK_Reg53: return "MCK_Reg53";
6154 case MCK_Reg27: return "MCK_Reg27";
6155 case MCK_VRN4M2NoV0: return "MCK_VRN4M2NoV0";
6156 case MCK_Reg71: return "MCK_Reg71";
6157 case MCK_Reg67: return "MCK_Reg67";
6158 case MCK_Reg54: return "MCK_Reg54";
6159 case MCK_Reg49: return "MCK_Reg49";
6160 case MCK_Reg23: return "MCK_Reg23";
6161 case MCK_GPRTCNonX7: return "MCK_GPRTCNonX7";
6162 case MCK_VRN3M2NoV0: return "MCK_VRN3M2NoV0";
6163 case MCK_VRN4M2: return "MCK_VRN4M2";
6164 case MCK_Reg68: return "MCK_Reg68";
6165 case MCK_Reg64: return "MCK_Reg64";
6166 case MCK_Reg50: return "MCK_Reg50";
6167 case MCK_GPRTC: return "MCK_GPRTC";
6168 case MCK_VRN2M2NoV0: return "MCK_VRN2M2NoV0";
6169 case MCK_VRN3M2: return "MCK_VRN3M2";
6170 case MCK_Reg62: return "MCK_Reg62";
6171 case MCK_GPRPairNoX0: return "MCK_GPRPairNoX0";
6172 case MCK_VRM2NoV0: return "MCK_VRM2NoV0";
6173 case MCK_VRN2M2: return "MCK_VRN2M2";
6174 case MCK_GPRPair: return "MCK_GPRPair";
6175 case MCK_TR: return "MCK_TR";
6176 case MCK_VRM2: return "MCK_VRM2";
6177 case MCK_Reg51: return "MCK_Reg51";
6178 case MCK_Reg25: return "MCK_Reg25";
6179 case MCK_VRN8M1NoV0: return "MCK_VRN8M1NoV0";
6180 case MCK_Reg52: return "MCK_Reg52";
6181 case MCK_Reg47: return "MCK_Reg47";
6182 case MCK_Reg21: return "MCK_Reg21";
6183 case MCK_GPRJALRNonX7: return "MCK_GPRJALRNonX7";
6184 case MCK_VRN7M1NoV0: return "MCK_VRN7M1NoV0";
6185 case MCK_VRN8M1: return "MCK_VRN8M1";
6186 case MCK_Reg48: return "MCK_Reg48";
6187 case MCK_GPRJALR: return "MCK_GPRJALR";
6188 case MCK_VRN6M1NoV0: return "MCK_VRN6M1NoV0";
6189 case MCK_VRN7M1: return "MCK_VRN7M1";
6190 case MCK_VRN5M1NoV0: return "MCK_VRN5M1NoV0";
6191 case MCK_VRN6M1: return "MCK_VRN6M1";
6192 case MCK_VRN4M1NoV0: return "MCK_VRN4M1NoV0";
6193 case MCK_VRN5M1: return "MCK_VRN5M1";
6194 case MCK_Reg42: return "MCK_Reg42";
6195 case MCK_Reg16: return "MCK_Reg16";
6196 case MCK_VRN3M1NoV0: return "MCK_VRN3M1NoV0";
6197 case MCK_VRN4M1: return "MCK_VRN4M1";
6198 case MCK_Reg43: return "MCK_Reg43";
6199 case MCK_Reg40: return "MCK_Reg40";
6200 case MCK_Reg37: return "MCK_Reg37";
6201 case MCK_Reg14: return "MCK_Reg14";
6202 case MCK_Reg11: return "MCK_Reg11";
6203 case MCK_GPRNoX0X2: return "MCK_GPRNoX0X2";
6204 case MCK_VRN2M1NoV0: return "MCK_VRN2M1NoV0";
6205 case MCK_VRN3M1: return "MCK_VRN3M1";
6206 case MCK_Reg41: return "MCK_Reg41";
6207 case MCK_Reg38: return "MCK_Reg38";
6208 case MCK_Reg35: return "MCK_Reg35";
6209 case MCK_GPRF16NoX0: return "MCK_GPRF16NoX0";
6210 case MCK_GPRF32NoX0: return "MCK_GPRF32NoX0";
6211 case MCK_GPRNoX0: return "MCK_GPRNoX0";
6212 case MCK_GPRNoX2: return "MCK_GPRNoX2";
6213 case MCK_GPRNoX31: return "MCK_GPRNoX31";
6214 case MCK_VRN2M1: return "MCK_VRN2M1";
6215 case MCK_VRNoV0: return "MCK_VRNoV0";
6216 case MCK_FPR128: return "MCK_FPR128";
6217 case MCK_FPR16: return "MCK_FPR16";
6218 case MCK_FPR256: return "MCK_FPR256";
6219 case MCK_FPR32: return "MCK_FPR32";
6220 case MCK_FPR64: return "MCK_FPR64";
6221 case MCK_GPR: return "MCK_GPR";
6222 case MCK_GPRF16: return "MCK_GPRF16";
6223 case MCK_GPRF32: return "MCK_GPRF32";
6224 case MCK_VR: return "MCK_VR";
6225 case MCK_YGPR: return "MCK_YGPR";
6226 case MCK_AnyRegCOperand: return "MCK_AnyRegCOperand";
6227 case MCK_AnyRegOperand: return "MCK_AnyRegOperand";
6228 case MCK_BareSymbol: return "MCK_BareSymbol";
6229 case MCK_BareSymbolQC_E_LI: return "MCK_BareSymbolQC_E_LI";
6230 case MCK_CLUIImm: return "MCK_CLUIImm";
6231 case MCK_CSRSystemRegister: return "MCK_CSRSystemRegister";
6232 case MCK_RegReg: return "MCK_RegReg";
6233 case MCK_TailCallSymbol: return "MCK_TailCallSymbol";
6234 case MCK_CallSymbol: return "MCK_CallSymbol";
6235 case MCK_FRMArg: return "MCK_FRMArg";
6236 case MCK_FRMArgLegacy: return "MCK_FRMArgLegacy";
6237 case MCK_FenceArg: return "MCK_FenceArg";
6238 case MCK_GPRAsFPR16: return "MCK_GPRAsFPR16";
6239 case MCK_GPRAsFPR32: return "MCK_GPRAsFPR32";
6240 case MCK_GPRF64AsFPR: return "MCK_GPRF64AsFPR";
6241 case MCK_GPRPairAsFPR: return "MCK_GPRPairAsFPR";
6242 case MCK_GPRPairCRV32: return "MCK_GPRPairCRV32";
6243 case MCK_GPRPairNoX0RV32: return "MCK_GPRPairNoX0RV32";
6244 case MCK_GPRPairRV32: return "MCK_GPRPairRV32";
6245 case MCK_GPRPairRV64: return "MCK_GPRPairRV64";
6246 case MCK_Imm: return "MCK_Imm";
6247 case MCK_ImmFour: return "MCK_ImmFour";
6248 case MCK_ImmThree: return "MCK_ImmThree";
6249 case MCK_ImmZero: return "MCK_ImmZero";
6250 case MCK_InsnCDirectiveOpcode: return "MCK_InsnCDirectiveOpcode";
6251 case MCK_InsnDirectiveOpcode: return "MCK_InsnDirectiveOpcode";
6252 case MCK_LoadFPImm: return "MCK_LoadFPImm";
6253 case MCK_NegStackAdj: return "MCK_NegStackAdj";
6254 case MCK_PseudoJumpSymbol: return "MCK_PseudoJumpSymbol";
6255 case MCK_QCAccessSymbol: return "MCK_QCAccessSymbol";
6256 case MCK_RTZArg: return "MCK_RTZArg";
6257 case MCK_RegList: return "MCK_RegList";
6258 case MCK_RegListS0: return "MCK_RegListS0";
6259 case MCK_RnumArg: return "MCK_RnumArg";
6260 case MCK_SImm10PLI_H: return "MCK_SImm10PLI_H";
6261 case MCK_SImm10PLI_W: return "MCK_SImm10PLI_W";
6262 case MCK_SImm10PLUI: return "MCK_SImm10PLUI";
6263 case MCK_SImm8PLI_B: return "MCK_SImm8PLI_B";
6264 case MCK_SMTI8: return "MCK_SMTI8";
6265 case MCK_SMTVType: return "MCK_SMTVType";
6266 case MCK_BareSImm21Lsb0: return "MCK_BareSImm21Lsb0";
6267 case MCK_StackAdj: return "MCK_StackAdj";
6268 case MCK_TLSDESCCallSymbol: return "MCK_TLSDESCCallSymbol";
6269 case MCK_TPRelAddSymbol: return "MCK_TPRelAddSymbol";
6270 case MCK_TileLambda: return "MCK_TileLambda";
6271 case MCK_UImmLog2XLen: return "MCK_UImmLog2XLen";
6272 case MCK_UImmLog2XLenNonZero: return "MCK_UImmLog2XLenNonZero";
6273 case MCK_RVVMaskRegOpOperand: return "MCK_RVVMaskRegOpOperand";
6274 case MCK_RVVMaskCarryInRegOpOperand: return "MCK_RVVMaskCarryInRegOpOperand";
6275 case MCK_RVVScaleRegOpOperand: return "MCK_RVVScaleRegOpOperand";
6276 case MCK_XSfmmVType: return "MCK_XSfmmVType";
6277 case MCK_YBNDSWImm: return "MCK_YBNDSWImm";
6278 case MCK_ZeroOffsetMemOpOperand: return "MCK_ZeroOffsetMemOpOperand";
6279 case MCK_UImm1: return "MCK_UImm1";
6280 case MCK_UImm2: return "MCK_UImm2";
6281 case MCK_UImm3: return "MCK_UImm3";
6282 case MCK_UImm4: return "MCK_UImm4";
6283 case MCK_UImm5: return "MCK_UImm5";
6284 case MCK_UImm6: return "MCK_UImm6";
6285 case MCK_UImm7: return "MCK_UImm7";
6286 case MCK_UImm8: return "MCK_UImm8";
6287 case MCK_UImm16: return "MCK_UImm16";
6288 case MCK_UImm32: return "MCK_UImm32";
6289 case MCK_UImm48: return "MCK_UImm48";
6290 case MCK_UImm64: return "MCK_UImm64";
6291 case MCK_SImm12: return "MCK_SImm12";
6292 case MCK_SImm12LO: return "MCK_SImm12LO";
6293 case MCK_OptionalSImm12: return "MCK_OptionalSImm12";
6294 case MCK_OptionalSImm12LO: return "MCK_OptionalSImm12LO";
6295 case MCK_BareSImm13Lsb0: return "MCK_BareSImm13Lsb0";
6296 case MCK_UImm20: return "MCK_UImm20";
6297 case MCK_UImm20LUI: return "MCK_UImm20LUI";
6298 case MCK_UImm20AUIPC: return "MCK_UImm20AUIPC";
6299 case MCK_ImmXLenLI: return "MCK_ImmXLenLI";
6300 case MCK_ImmXLenLI_Restricted: return "MCK_ImmXLenLI_Restricted";
6301 case MCK_SImm12Lsb00000: return "MCK_SImm12Lsb00000";
6302 case MCK_Imm5Zibi: return "MCK_Imm5Zibi";
6303 case MCK_VTypeI10: return "MCK_VTypeI10";
6304 case MCK_VTypeI11: return "MCK_VTypeI11";
6305 case MCK_SImm5: return "MCK_SImm5";
6306 case MCK_SImm5Plus1: return "MCK_SImm5Plus1";
6307 case MCK_UImm6Lsb000: return "MCK_UImm6Lsb000";
6308 case MCK_UImm4Plus1: return "MCK_UImm4Plus1";
6309 case MCK_UImm5Plus1: return "MCK_UImm5Plus1";
6310 case MCK_UImm6Plus1: return "MCK_UImm6Plus1";
6311 case MCK_SImm6: return "MCK_SImm6";
6312 case MCK_SImm6NonZero: return "MCK_SImm6NonZero";
6313 case MCK_UImm7Lsb00: return "MCK_UImm7Lsb00";
6314 case MCK_OptionalUImm7Lsb00: return "MCK_OptionalUImm7Lsb00";
6315 case MCK_UImm8Lsb00: return "MCK_UImm8Lsb00";
6316 case MCK_OptionalUImm8Lsb00: return "MCK_OptionalUImm8Lsb00";
6317 case MCK_UImm8Lsb000: return "MCK_UImm8Lsb000";
6318 case MCK_OptionalUImm8Lsb000: return "MCK_OptionalUImm8Lsb000";
6319 case MCK_BareSImm9Lsb0: return "MCK_BareSImm9Lsb0";
6320 case MCK_UImm9Lsb000: return "MCK_UImm9Lsb000";
6321 case MCK_OptionalUImm9Lsb000: return "MCK_OptionalUImm9Lsb000";
6322 case MCK_UImm10Lsb00NonZero: return "MCK_UImm10Lsb00NonZero";
6323 case MCK_SImm10Lsb0000NonZero: return "MCK_SImm10Lsb0000NonZero";
6324 case MCK_BareSImm12Lsb0: return "MCK_BareSImm12Lsb0";
6325 case MCK_OptionalUImm5: return "MCK_OptionalUImm5";
6326 case MCK_OptionalUImm2: return "MCK_OptionalUImm2";
6327 case MCK_UImm2Lsb0: return "MCK_UImm2Lsb0";
6328 case MCK_OptionalUImm2Lsb0: return "MCK_OptionalUImm2Lsb0";
6329 case MCK_UImm8GE32: return "MCK_UImm8GE32";
6330 case MCK_OptionalUImm4: return "MCK_OptionalUImm4";
6331 case MCK_UImm5Lsb0: return "MCK_UImm5Lsb0";
6332 case MCK_OptionalUImm5Lsb0: return "MCK_OptionalUImm5Lsb0";
6333 case MCK_UImm6Lsb0: return "MCK_UImm6Lsb0";
6334 case MCK_OptionalUImm6Lsb0: return "MCK_OptionalUImm6Lsb0";
6335 case MCK_UImm5NonZero: return "MCK_UImm5NonZero";
6336 case MCK_UImm5GT3: return "MCK_UImm5GT3";
6337 case MCK_UImm5GE6Plus1: return "MCK_UImm5GE6Plus1";
6338 case MCK_UImm5Slist: return "MCK_UImm5Slist";
6339 case MCK_UImm10: return "MCK_UImm10";
6340 case MCK_UImm11: return "MCK_UImm11";
6341 case MCK_UImm14Lsb00: return "MCK_UImm14Lsb00";
6342 case MCK_OptionalUImm14Lsb00: return "MCK_OptionalUImm14Lsb00";
6343 case MCK_UImm16NonZero: return "MCK_UImm16NonZero";
6344 case MCK_SImm5NonZero: return "MCK_SImm5NonZero";
6345 case MCK_SImm11: return "MCK_SImm11";
6346 case MCK_SImm16: return "MCK_SImm16";
6347 case MCK_SImm16NonZero: return "MCK_SImm16NonZero";
6348 case MCK_SImm20LI: return "MCK_SImm20LI";
6349 case MCK_SImm26: return "MCK_SImm26";
6350 case MCK_OptionalSImm26: return "MCK_OptionalSImm26";
6351 case MCK_BareSImm32: return "MCK_BareSImm32";
6352 case MCK_BareSImm32Lsb0: return "MCK_BareSImm32Lsb0";
6353 case MCK_UImm7Lsb000: return "MCK_UImm7Lsb000";
6354 case MCK_UImm9: return "MCK_UImm9";
6355 case MCK_BareSImm11Lsb0: return "MCK_BareSImm11Lsb0";
6356 case MCK_SImm18: return "MCK_SImm18";
6357 case MCK_SImm18Lsb0: return "MCK_SImm18Lsb0";
6358 case MCK_SImm19Lsb00: return "MCK_SImm19Lsb00";
6359 case MCK_SImm20Lsb000: return "MCK_SImm20Lsb000";
6360 case MCK_SImm10: return "MCK_SImm10";
6361 case NumMatchClassKinds: return "NumMatchClassKinds";
6362 }
6363 llvm_unreachable("unhandled MatchClassKind!");
6364}
6365
6366#endif // NDEBUG
6367FeatureBitset RISCVAsmParser::
6368ComputeAvailableFeatures(const FeatureBitset &FB) const {
6369 FeatureBitset Features;
6370 if (FB[RISCV::FeatureStdExtZibi])
6371 Features.set(Feature_HasStdExtZibiBit);
6372 if (FB[RISCV::FeatureStdExtZicbom])
6373 Features.set(Feature_HasStdExtZicbomBit);
6374 if (FB[RISCV::FeatureStdExtZicbop])
6375 Features.set(Feature_HasStdExtZicbopBit);
6376 if (FB[RISCV::FeatureStdExtZicboz])
6377 Features.set(Feature_HasStdExtZicbozBit);
6378 if (FB[RISCV::FeatureStdExtZicsr])
6379 Features.set(Feature_HasStdExtZicsrBit);
6380 if (FB[RISCV::FeatureStdExtZicond])
6381 Features.set(Feature_HasStdExtZicondBit);
6382 if (FB[RISCV::FeatureStdExtZifencei])
6383 Features.set(Feature_HasStdExtZifenceiBit);
6384 if (FB[RISCV::FeatureStdExtZihintpause])
6385 Features.set(Feature_HasStdExtZihintpauseBit);
6386 if (FB[RISCV::FeatureStdExtZihintntl])
6387 Features.set(Feature_HasStdExtZihintntlBit);
6388 if (FB[RISCV::FeatureStdExtZimop])
6389 Features.set(Feature_HasStdExtZimopBit);
6390 if (FB[RISCV::FeatureStdExtZicfiss])
6391 Features.set(Feature_HasStdExtZicfissBit);
6392 if (FB[RISCV::FeatureStdExtZilsd])
6393 Features.set(Feature_HasStdExtZilsdBit);
6394 if (FB[RISCV::FeatureStdExtZilx])
6395 Features.set(Feature_HasStdExtZilxBit);
6396 if (FB[RISCV::FeatureStdExtZmmul])
6397 Features.set(Feature_HasStdExtZmmulBit);
6398 if (FB[RISCV::FeatureStdExtM])
6399 Features.set(Feature_HasStdExtMBit);
6400 if (FB[RISCV::FeatureStdExtZaamo])
6401 Features.set(Feature_HasStdExtZaamoBit);
6402 if (FB[RISCV::FeatureStdExtZalrsc])
6403 Features.set(Feature_HasStdExtZalrscBit);
6404 if (FB[RISCV::FeatureStdExtA])
6405 Features.set(Feature_HasStdExtABit);
6406 if (FB[RISCV::FeatureStdExtZtso])
6407 Features.set(Feature_HasStdExtZtsoBit);
6408 if (FB[RISCV::FeatureStdExtZabha])
6409 Features.set(Feature_HasStdExtZabhaBit);
6410 if (FB[RISCV::FeatureStdExtZacas])
6411 Features.set(Feature_HasStdExtZacasBit);
6412 if (FB[RISCV::FeatureStdExtZalasr])
6413 Features.set(Feature_HasStdExtZalasrBit);
6414 if (FB[RISCV::FeatureStdExtZawrs])
6415 Features.set(Feature_HasStdExtZawrsBit);
6416 if (FB[RISCV::FeatureStdExtF])
6417 Features.set(Feature_HasStdExtFBit);
6418 if (FB[RISCV::FeatureStdExtD])
6419 Features.set(Feature_HasStdExtDBit);
6420 if (FB[RISCV::FeatureStdExtQ])
6421 Features.set(Feature_HasStdExtQBit);
6422 if (FB[RISCV::FeatureStdExtZfhmin])
6423 Features.set(Feature_HasStdExtZfhminBit);
6424 if (FB[RISCV::FeatureStdExtZfh])
6425 Features.set(Feature_HasStdExtZfhBit);
6426 if (FB[RISCV::FeatureStdExtZfbfmin])
6427 Features.set(Feature_HasStdExtZfbfminBit);
6428 if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZfhmin] || FB[RISCV::FeatureStdExtZfbfmin])
6429 Features.set(Feature_HasHalfFPLoadStoreMoveBit);
6430 if (FB[RISCV::FeatureStdExtZfa])
6431 Features.set(Feature_HasStdExtZfaBit);
6432 if (FB[RISCV::FeatureStdExtZfinx])
6433 Features.set(Feature_HasStdExtZfinxBit);
6434 if (FB[RISCV::FeatureStdExtF] || FB[RISCV::FeatureStdExtZfinx])
6435 Features.set(Feature_HasStdExtFOrZfinxBit);
6436 if (FB[RISCV::FeatureStdExtZdinx])
6437 Features.set(Feature_HasStdExtZdinxBit);
6438 if (FB[RISCV::FeatureStdExtZhinxmin])
6439 Features.set(Feature_HasStdExtZhinxminBit);
6440 if (FB[RISCV::FeatureStdExtZhinx])
6441 Features.set(Feature_HasStdExtZhinxBit);
6442 if (FB[RISCV::FeatureStdExtZca])
6443 Features.set(Feature_HasStdExtZcaBit);
6444 if (FB[RISCV::FeatureStdExtZcb])
6445 Features.set(Feature_HasStdExtZcbBit);
6446 if (FB[RISCV::FeatureStdExtZcf])
6447 Features.set(Feature_HasStdExtZcfBit);
6448 if (FB[RISCV::FeatureStdExtZcd])
6449 Features.set(Feature_HasStdExtZcdBit);
6450 if (FB[RISCV::FeatureStdExtZclsd])
6451 Features.set(Feature_HasStdExtZclsdBit);
6452 if (FB[RISCV::FeatureStdExtZcmp])
6453 Features.set(Feature_HasStdExtZcmpBit);
6454 if (FB[RISCV::FeatureStdExtZcmt])
6455 Features.set(Feature_HasStdExtZcmtBit);
6456 if (FB[RISCV::FeatureStdExtZcmop])
6457 Features.set(Feature_HasStdExtZcmopBit);
6458 if (FB[RISCV::FeatureStdExtZba])
6459 Features.set(Feature_HasStdExtZbaBit);
6460 if (FB[RISCV::FeatureStdExtZbb])
6461 Features.set(Feature_HasStdExtZbbBit);
6462 if (!(FB[RISCV::FeatureStdExtZbb]))
6463 Features.set(Feature_NoStdExtZbbBit);
6464 if (FB[RISCV::FeatureStdExtZbs])
6465 Features.set(Feature_HasStdExtZbsBit);
6466 if (FB[RISCV::FeatureStdExtZbkb])
6467 Features.set(Feature_HasStdExtZbkbBit);
6468 if (!(FB[RISCV::FeatureStdExtZbkb]))
6469 Features.set(Feature_NoStdExtZbkbBit);
6470 if (FB[RISCV::FeatureStdExtZbkx])
6471 Features.set(Feature_HasStdExtZbkxBit);
6472 if (FB[RISCV::FeatureStdExtZbb] || FB[RISCV::FeatureStdExtZbkb])
6473 Features.set(Feature_HasStdExtZbbOrZbkbBit);
6474 if (FB[RISCV::FeatureStdExtZbkc])
6475 Features.set(Feature_HasStdExtZbkcBit);
6476 if (FB[RISCV::FeatureStdExtZbc])
6477 Features.set(Feature_HasStdExtZbcBit);
6478 if (FB[RISCV::FeatureStdExtZknd])
6479 Features.set(Feature_HasStdExtZkndBit);
6480 if (FB[RISCV::FeatureStdExtZkne])
6481 Features.set(Feature_HasStdExtZkneBit);
6482 if (FB[RISCV::FeatureStdExtZknd] || FB[RISCV::FeatureStdExtZkne])
6483 Features.set(Feature_HasStdExtZkndOrZkneBit);
6484 if (FB[RISCV::FeatureStdExtZknh])
6485 Features.set(Feature_HasStdExtZknhBit);
6486 if (FB[RISCV::FeatureStdExtZksed])
6487 Features.set(Feature_HasStdExtZksedBit);
6488 if (FB[RISCV::FeatureStdExtZksh])
6489 Features.set(Feature_HasStdExtZkshBit);
6490 if (FB[RISCV::FeatureStdExtZkr])
6491 Features.set(Feature_HasStdExtZkrBit);
6492 if (FB[RISCV::FeatureStdExtZvabd])
6493 Features.set(Feature_HasStdExtZvabdBit);
6494 if (FB[RISCV::FeatureStdExtZvqwdota8i] || FB[RISCV::FeatureStdExtZvqwdota16i])
6495 Features.set(Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit);
6496 if (FB[RISCV::FeatureStdExtZvfwdota16bf])
6497 Features.set(Feature_HasStdExtZvfwdota16bfBit);
6498 if (FB[RISCV::FeatureStdExtZvfqwdota8f])
6499 Features.set(Feature_HasStdExtZvfqwdota8fBit);
6500 if (FB[RISCV::FeatureStdExtZvfbfmin])
6501 Features.set(Feature_HasStdExtZvfbfminBit);
6502 if (FB[RISCV::FeatureStdExtZvfbfwma])
6503 Features.set(Feature_HasStdExtZvfbfwmaBit);
6504 if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZvfh])
6505 Features.set(Feature_HasStdExtZfhOrZvfhBit);
6506 if (FB[RISCV::FeatureStdExtZvfofp8min])
6507 Features.set(Feature_HasStdExtZvfofp8minBit);
6508 if (FB[RISCV::FeatureStdExtZvfbfmin] || FB[RISCV::FeatureStdExtZvfofp8min])
6509 Features.set(Feature_HasStdExtZvfbfminOrZvfofp8minBit);
6510 if (FB[RISCV::FeatureStdExtZvkb])
6511 Features.set(Feature_HasStdExtZvkbBit);
6512 if (FB[RISCV::FeatureStdExtZvbb])
6513 Features.set(Feature_HasStdExtZvbbBit);
6514 if (FB[RISCV::FeatureStdExtZvbc])
6515 Features.set(Feature_HasStdExtZvbcBit);
6516 if (FB[RISCV::FeatureStdExtZvbc] || FB[RISCV::FeatureStdExtZvbc32e])
6517 Features.set(Feature_HasStdExtZvbcOrZvbc32eBit);
6518 if (FB[RISCV::FeatureStdExtZvkg])
6519 Features.set(Feature_HasStdExtZvkgBit);
6520 if (FB[RISCV::FeatureStdExtZvkgs])
6521 Features.set(Feature_HasStdExtZvkgsBit);
6522 if (FB[RISCV::FeatureStdExtZvkned])
6523 Features.set(Feature_HasStdExtZvknedBit);
6524 if (FB[RISCV::FeatureStdExtZvknha])
6525 Features.set(Feature_HasStdExtZvknhaBit);
6526 if (FB[RISCV::FeatureStdExtZvknhb])
6527 Features.set(Feature_HasStdExtZvknhbBit);
6528 if (FB[RISCV::FeatureStdExtZvksed])
6529 Features.set(Feature_HasStdExtZvksedBit);
6530 if (FB[RISCV::FeatureStdExtZvksh])
6531 Features.set(Feature_HasStdExtZvkshBit);
6532 if (FB[RISCV::FeatureStdExtZvdot4a8i])
6533 Features.set(Feature_HasStdExtZvdot4a8iBit);
6534 if (FB[RISCV::FeatureStdExtZvzip])
6535 Features.set(Feature_HasStdExtZvzipBit);
6536 if (FB[RISCV::FeatureStdExtZvvmm])
6537 Features.set(Feature_HasStdExtZvvmmBit);
6538 if (FB[RISCV::FeatureStdExtZvvfmm])
6539 Features.set(Feature_HasStdExtZvvfmmBit);
6540 if (FB[RISCV::FeatureStdExtZvvmtls])
6541 Features.set(Feature_HasStdExtZvvmtlsBit);
6542 if (FB[RISCV::FeatureStdExtZvvmttls])
6543 Features.set(Feature_HasStdExtZvvmttlsBit);
6544 if (FB[RISCV::FeatureStdExtZvqwbdota8i] || FB[RISCV::FeatureStdExtZvqwbdota16i])
6545 Features.set(Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit);
6546 if (FB[RISCV::FeatureStdExtZvfwbdota16bf])
6547 Features.set(Feature_HasStdExtZvfwbdota16bfBit);
6548 if (FB[RISCV::FeatureStdExtZvfqwbdota8f])
6549 Features.set(Feature_HasStdExtZvfqwbdota8fBit);
6550 if (FB[RISCV::FeatureStdExtZvfbdota32f])
6551 Features.set(Feature_HasStdExtZvfbdota32fBit);
6552 if (FB[RISCV::FeatureStdExtZve32x])
6553 Features.set(Feature_HasVInstructionsBit);
6554 if (FB[RISCV::FeatureStdExtZve64x])
6555 Features.set(Feature_HasVInstructionsI64Bit);
6556 if (FB[RISCV::FeatureStdExtZve32f])
6557 Features.set(Feature_HasVInstructionsAnyFBit);
6558 if (FB[RISCV::FeatureStdExtZvfhmin] || FB[RISCV::FeatureStdExtZvfh])
6559 Features.set(Feature_HasVInstructionsF16MinimalBit);
6560 if (FB[RISCV::FeatureStdExtH])
6561 Features.set(Feature_HasStdExtHBit);
6562 if (FB[RISCV::FeatureStdExtSmcsps])
6563 Features.set(Feature_HasStdExtSmcspsBit);
6564 if (FB[RISCV::FeatureStdExtSscsps])
6565 Features.set(Feature_HasStdExtSscspsBit);
6566 if (FB[RISCV::FeatureStdExtSmip])
6567 Features.set(Feature_HasStdExtSmipBit);
6568 if (FB[RISCV::FeatureStdExtSsip])
6569 Features.set(Feature_HasStdExtSsipBit);
6570 if (FB[RISCV::FeatureStdExtSmrnmi])
6571 Features.set(Feature_HasStdExtSmrnmiBit);
6572 if (FB[RISCV::FeatureStdExtSvinval])
6573 Features.set(Feature_HasStdExtSvinvalBit);
6574 if (FB[RISCV::FeatureStdExtSmctr] || FB[RISCV::FeatureStdExtSsctr])
6575 Features.set(Feature_HasStdExtSmctrOrSsctrBit);
6576 if (FB[RISCV::FeatureStdExtP])
6577 Features.set(Feature_HasStdExtPBit);
6578 if (FB[RISCV::FeatureStdExtZbkb] || FB[RISCV::FeatureStdExtP])
6579 Features.set(Feature_HasStdExtZbkbOrPBit);
6580 if (FB[RISCV::FeatureStdExtY])
6581 Features.set(Feature_HasStdExtYBit);
6582 if (FB[RISCV::FeatureVendorXTHeadBa])
6583 Features.set(Feature_HasVendorXTHeadBaBit);
6584 if (FB[RISCV::FeatureVendorXTHeadBb])
6585 Features.set(Feature_HasVendorXTHeadBbBit);
6586 if (FB[RISCV::FeatureVendorXTHeadBs])
6587 Features.set(Feature_HasVendorXTHeadBsBit);
6588 if (FB[RISCV::FeatureVendorXTHeadCondMov])
6589 Features.set(Feature_HasVendorXTHeadCondMovBit);
6590 if (FB[RISCV::FeatureVendorXTHeadCmo])
6591 Features.set(Feature_HasVendorXTHeadCmoBit);
6592 if (FB[RISCV::FeatureVendorXTHeadFMemIdx])
6593 Features.set(Feature_HasVendorXTHeadFMemIdxBit);
6594 if (FB[RISCV::FeatureVendorXTHeadMac])
6595 Features.set(Feature_HasVendorXTHeadMacBit);
6596 if (FB[RISCV::FeatureVendorXTHeadMemIdx])
6597 Features.set(Feature_HasVendorXTHeadMemIdxBit);
6598 if (FB[RISCV::FeatureVendorXTHeadMemPair])
6599 Features.set(Feature_HasVendorXTHeadMemPairBit);
6600 if (FB[RISCV::FeatureVendorXTHeadSync])
6601 Features.set(Feature_HasVendorXTHeadSyncBit);
6602 if (FB[RISCV::FeatureVendorXTHeadVdot])
6603 Features.set(Feature_HasVendorXTHeadVdotBit);
6604 if (FB[RISCV::FeatureVendorXSfvcp])
6605 Features.set(Feature_HasVendorXSfvcpBit);
6606 if (FB[RISCV::FeatureVendorXSfmmbase])
6607 Features.set(Feature_HasVendorXSfmmbaseBit);
6608 if (FB[RISCV::FeatureVendorXSfmm32a8f])
6609 Features.set(Feature_HasVendorXSfmm32a8fBit);
6610 if (FB[RISCV::FeatureVendorXSfmm32a8i])
6611 Features.set(Feature_HasVendorXSfmm32a8iBit);
6612 if (FB[RISCV::FeatureVendorXSfmm32a16f] || FB[RISCV::FeatureVendorXSfmm32a32f] || FB[RISCV::FeatureVendorXSfmm64a64f])
6613 Features.set(Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit);
6614 if (FB[RISCV::FeatureVendorXSfvqmaccdod])
6615 Features.set(Feature_HasVendorXSfvqmaccdodBit);
6616 if (FB[RISCV::FeatureVendorXSfvqmaccqoq])
6617 Features.set(Feature_HasVendorXSfvqmaccqoqBit);
6618 if (FB[RISCV::FeatureVendorXSfvfwmaccqqq])
6619 Features.set(Feature_HasVendorXSfvfwmaccqqqBit);
6620 if (FB[RISCV::FeatureVendorXSfvfnrclipxfqf])
6621 Features.set(Feature_HasVendorXSfvfnrclipxfqfBit);
6622 if (FB[RISCV::FeatureVendorXSfvfbfexp16e] || FB[RISCV::FeatureVendorXSfvfexp16e] || FB[RISCV::FeatureVendorXSfvfexp32e])
6623 Features.set(Feature_HasVendorXSfvfexpAnyBit);
6624 if (FB[RISCV::FeatureVendorXSfvfexpa])
6625 Features.set(Feature_HasVendorXSfvfexpaBit);
6626 if (FB[RISCV::FeatureVendorXSiFivecdiscarddlone])
6627 Features.set(Feature_HasVendorXSiFivecdiscarddloneBit);
6628 if (FB[RISCV::FeatureVendorXSiFivecflushdlone])
6629 Features.set(Feature_HasVendorXSiFivecflushdloneBit);
6630 if (FB[RISCV::FeatureVendorXSfcease])
6631 Features.set(Feature_HasVendorXSfceaseBit);
6632 if (FB[RISCV::FeatureVendorXCVelw])
6633 Features.set(Feature_HasVendorXCVelwBit);
6634 if (FB[RISCV::FeatureVendorXCVbitmanip])
6635 Features.set(Feature_HasVendorXCVbitmanipBit);
6636 if (FB[RISCV::FeatureVendorXCVmac])
6637 Features.set(Feature_HasVendorXCVmacBit);
6638 if (FB[RISCV::FeatureVendorXCVmem])
6639 Features.set(Feature_HasVendorXCVmemBit);
6640 if (FB[RISCV::FeatureVendorXCValu])
6641 Features.set(Feature_HasVendorXCValuBit);
6642 if (FB[RISCV::FeatureVendorXCVsimd])
6643 Features.set(Feature_HasVendorXCVsimdBit);
6644 if (FB[RISCV::FeatureVendorXCVbi])
6645 Features.set(Feature_HasVendorXCVbiBit);
6646 if (FB[RISCV::FeatureVendorXMIPSCMov])
6647 Features.set(Feature_HasVendorXMIPSCMovBit);
6648 if (FB[RISCV::FeatureVendorXMIPSLSP])
6649 Features.set(Feature_HasVendorXMIPSLSPBit);
6650 if (FB[RISCV::FeatureVendorXMIPSCBOP])
6651 Features.set(Feature_HasVendorXMIPSCBOPBit);
6652 if (FB[RISCV::FeatureVendorXMIPSEXECTL])
6653 Features.set(Feature_HasVendorXMIPSEXECTLBit);
6654 if (FB[RISCV::FeatureVendorXwchc])
6655 Features.set(Feature_HasVendorXwchcBit);
6656 if (FB[RISCV::FeatureVendorXqccmp])
6657 Features.set(Feature_HasVendorXqccmpBit);
6658 if (FB[RISCV::FeatureVendorXqccmi])
6659 Features.set(Feature_HasVendorXqccmiBit);
6660 if (FB[RISCV::FeatureVendorXqccmt])
6661 Features.set(Feature_HasVendorXqccmtBit);
6662 if (FB[RISCV::FeatureVendorXqcia])
6663 Features.set(Feature_HasVendorXqciaBit);
6664 if (FB[RISCV::FeatureVendorXqciac])
6665 Features.set(Feature_HasVendorXqciacBit);
6666 if (FB[RISCV::FeatureVendorXqcibi])
6667 Features.set(Feature_HasVendorXqcibiBit);
6668 if (FB[RISCV::FeatureVendorXqcibm])
6669 Features.set(Feature_HasVendorXqcibmBit);
6670 if (FB[RISCV::FeatureVendorXqcicli])
6671 Features.set(Feature_HasVendorXqcicliBit);
6672 if (FB[RISCV::FeatureVendorXqcicm])
6673 Features.set(Feature_HasVendorXqcicmBit);
6674 if (FB[RISCV::FeatureVendorXqcics])
6675 Features.set(Feature_HasVendorXqcicsBit);
6676 if (FB[RISCV::FeatureVendorXqcicsr])
6677 Features.set(Feature_HasVendorXqcicsrBit);
6678 if (FB[RISCV::FeatureVendorXqciint])
6679 Features.set(Feature_HasVendorXqciintBit);
6680 if (FB[RISCV::FeatureVendorXqciio])
6681 Features.set(Feature_HasVendorXqciioBit);
6682 if (FB[RISCV::FeatureVendorXqcilb])
6683 Features.set(Feature_HasVendorXqcilbBit);
6684 if (FB[RISCV::FeatureVendorXqcili])
6685 Features.set(Feature_HasVendorXqciliBit);
6686 if (FB[RISCV::FeatureVendorXqcilia])
6687 Features.set(Feature_HasVendorXqciliaBit);
6688 if (FB[RISCV::FeatureVendorXqcilo])
6689 Features.set(Feature_HasVendorXqciloBit);
6690 if (FB[RISCV::FeatureVendorXqcilsm])
6691 Features.set(Feature_HasVendorXqcilsmBit);
6692 if (FB[RISCV::FeatureVendorXqcisim])
6693 Features.set(Feature_HasVendorXqcisimBit);
6694 if (FB[RISCV::FeatureVendorXqcisls])
6695 Features.set(Feature_HasVendorXqcislsBit);
6696 if (FB[RISCV::FeatureVendorXqcisync])
6697 Features.set(Feature_HasVendorXqcisyncBit);
6698 if (FB[RISCV::FeatureVendorXAndesPerf])
6699 Features.set(Feature_HasVendorXAndesPerfBit);
6700 if (FB[RISCV::FeatureVendorXAndesBFHCvt])
6701 Features.set(Feature_HasVendorXAndesBFHCvtBit);
6702 if (FB[RISCV::FeatureVendorXAndesVBFHCvt])
6703 Features.set(Feature_HasVendorXAndesVBFHCvtBit);
6704 if (FB[RISCV::FeatureVendorXAndesVSIntH])
6705 Features.set(Feature_HasVendorXAndesVSIntHBit);
6706 if (FB[RISCV::FeatureVendorXAndesVSIntLoad])
6707 Features.set(Feature_HasVendorXAndesVSIntLoadBit);
6708 if (FB[RISCV::FeatureVendorXAndesVPackFPH])
6709 Features.set(Feature_HasVendorXAndesVPackFPHBit);
6710 if (FB[RISCV::FeatureVendorXAndesVDot])
6711 Features.set(Feature_HasVendorXAndesVDotBit);
6712 if (FB[RISCV::FeatureVendorXSMTVDot])
6713 Features.set(Feature_HasVendorXSMTVDotBit);
6714 if (FB[RISCV::FeatureVendorXSMTVDotII])
6715 Features.set(Feature_HasVendorXSMTVDotIIBit);
6716 if (FB[RISCV::FeatureVendorXAIFET])
6717 Features.set(Feature_HasXAIFETBit);
6718 if (FB[RISCV::FeatureVendorXCheriot])
6719 Features.set(Feature_HasCheriotBit);
6720 if (FB[RISCV::Feature64Bit])
6721 Features.set(Feature_IsRV64Bit);
6722 if (!(FB[RISCV::Feature64Bit]))
6723 Features.set(Feature_IsRV32Bit);
6724 return Features;
6725}
6726
6727static const char MnemonicTable[] =
6728 "\007.insn_b\010.insn_ca\010.insn_cb\010.insn_ci\t.insn_ciw\010.insn_cj\010"
6729 ".insn_cl\010.insn_cr\010.insn_cs\t.insn_css\007.insn_i\007.insn_j\014.i"
6730 "nsn_qc.eai\013.insn_qc.eb\013.insn_qc.ei\013.insn_qc.ej\013.insn_qc.es\007"
6731 ".insn_r\010.insn_r4\007.insn_s\010.insn_sb\007.insn_u\010.insn_uj\004aa"
6732 "dd\005aaddu\003abs\004absw\003add\006add.uw\004addd\004addi\005addiw\004"
6733 "addw\010aes32dsi\taes32dsmi\010aes32esi\taes32esmi\007aes64ds\010aes64d"
6734 "sm\007aes64es\010aes64esm\007aes64im\taes64ks1i\010aes64ks2\015aif.amoa"
6735 "ddg.d\015aif.amoaddg.w\015aif.amoaddl.d\015aif.amoaddl.w\015aif.amoandg"
6736 ".d\015aif.amoandg.w\015aif.amoandl.d\015aif.amoandl.w\021aif.amocmpswap"
6737 "g.d\021aif.amocmpswapg.w\021aif.amocmpswapl.d\021aif.amocmpswapl.w\015a"
6738 "if.amomaxg.d\015aif.amomaxg.w\015aif.amomaxl.d\015aif.amomaxl.w\016aif."
6739 "amomaxug.d\016aif.amomaxug.w\016aif.amomaxul.d\016aif.amomaxul.w\015aif"
6740 ".amoming.d\015aif.amoming.w\015aif.amominl.d\015aif.amominl.w\016aif.am"
6741 "ominug.d\016aif.amominug.w\016aif.amominul.d\016aif.amominul.w\014aif.a"
6742 "moorg.d\014aif.amoorg.w\014aif.amoorl.d\014aif.amoorl.w\016aif.amoswapg"
6743 ".d\016aif.amoswapg.w\016aif.amoswapl.d\016aif.amoswapl.w\015aif.amoxorg"
6744 ".d\015aif.amoxorg.w\015aif.amoxorl.d\015aif.amoxorl.w\013aif.bitmixb\017"
6745 "aif.cubeface.ps\022aif.cubefaceidx.ps\020aif.cubesgnsc.ps\020aif.cubesg"
6746 "ntc.ps\013aif.fadd.pi\013aif.fadd.ps\014aif.faddi.pi\017aif.famoaddg.pi"
6747 "\017aif.famoaddl.pi\017aif.famoandg.pi\017aif.famoandl.pi\017aif.famoma"
6748 "xg.pi\017aif.famomaxg.ps\017aif.famomaxl.pi\017aif.famomaxl.ps\020aif.f"
6749 "amomaxug.pi\020aif.famomaxul.pi\017aif.famoming.pi\017aif.famoming.ps\017"
6750 "aif.famominl.pi\017aif.famominl.ps\020aif.famominug.pi\020aif.famominul"
6751 ".pi\016aif.famoorg.pi\016aif.famoorl.pi\020aif.famoswapg.pi\020aif.famo"
6752 "swapl.pi\017aif.famoxorg.pi\017aif.famoxorl.pi\013aif.fand.pi\014aif.fa"
6753 "ndi.pi\naif.fbc.ps\013aif.fbci.pi\013aif.fbci.ps\013aif.fbcx.ps\015aif."
6754 "fclass.ps\014aif.fcmov.ps\015aif.fcmovm.ps\017aif.fcvt.f10.ps\017aif.fc"
6755 "vt.f11.ps\017aif.fcvt.f16.ps\017aif.fcvt.ps.f10\017aif.fcvt.ps.f11\017a"
6756 "if.fcvt.ps.f16\016aif.fcvt.ps.pw\017aif.fcvt.ps.pwu\020aif.fcvt.ps.rast"
6757 "\020aif.fcvt.ps.sn16\017aif.fcvt.ps.sn8\020aif.fcvt.ps.un10\020aif.fcvt"
6758 ".ps.un16\017aif.fcvt.ps.un2\020aif.fcvt.ps.un24\017aif.fcvt.ps.un8\016a"
6759 "if.fcvt.pw.ps\017aif.fcvt.pwu.ps\020aif.fcvt.rast.ps\020aif.fcvt.sn16.p"
6760 "s\017aif.fcvt.sn8.ps\020aif.fcvt.un10.ps\020aif.fcvt.un16.ps\017aif.fcv"
6761 "t.un2.ps\020aif.fcvt.un24.ps\017aif.fcvt.un8.ps\013aif.fdiv.pi\013aif.f"
6762 "div.ps\014aif.fdivu.pi\naif.feq.pi\naif.feq.ps\013aif.feqm.ps\013aif.fe"
6763 "xp.ps\013aif.ffrc.ps\014aif.fg32b.ps\014aif.fg32h.ps\014aif.fg32w.ps\na"
6764 "if.fgb.ps\013aif.fgbg.ps\013aif.fgbl.ps\naif.fgh.ps\013aif.fghg.ps\013a"
6765 "if.fghl.ps\naif.fgw.ps\013aif.fgwg.ps\013aif.fgwl.ps\naif.fle.pi\naif.f"
6766 "le.ps\013aif.flem.ps\013aif.flog.ps\010aif.flq2\naif.flt.pi\naif.flt.ps"
6767 "\013aif.fltm.pi\013aif.fltm.ps\013aif.fltu.pi\naif.flw.ps\013aif.flwg.p"
6768 "s\013aif.flwl.ps\014aif.fmadd.ps\013aif.fmax.pi\013aif.fmax.ps\014aif.f"
6769 "maxu.pi\013aif.fmin.pi\013aif.fmin.ps\014aif.fminu.pi\014aif.fmsub.ps\013"
6770 "aif.fmul.pi\013aif.fmul.ps\014aif.fmulh.pi\015aif.fmulhu.pi\015aif.fmvs"
6771 ".x.ps\015aif.fmvz.x.ps\015aif.fnmadd.ps\015aif.fnmsub.ps\013aif.fnot.pi"
6772 "\naif.for.pi\020aif.fpackrepb.pi\020aif.fpackreph.pi\013aif.frcp.ps\021"
6773 "aif.frcp_fix.rast\013aif.frem.pi\014aif.fremu.pi\015aif.fround.ps\013ai"
6774 "f.frsq.ps\014aif.fsat8.pi\015aif.fsatu8.pi\015aif.fsc32b.ps\015aif.fsc3"
6775 "2h.ps\015aif.fsc32w.ps\013aif.fscb.ps\014aif.fscbg.ps\014aif.fscbl.ps\013"
6776 "aif.fsch.ps\014aif.fschg.ps\014aif.fschl.ps\013aif.fscw.ps\014aif.fscwg"
6777 ".ps\014aif.fscwl.ps\014aif.fsetm.pi\014aif.fsgnj.ps\015aif.fsgnjn.ps\015"
6778 "aif.fsgnjx.ps\013aif.fsin.ps\013aif.fsll.pi\014aif.fslli.pi\010aif.fsq2"
6779 "\014aif.fsqrt.ps\013aif.fsra.pi\014aif.fsrai.pi\013aif.fsrl.pi\014aif.f"
6780 "srli.pi\013aif.fsub.pi\013aif.fsub.ps\naif.fsw.ps\013aif.fswg.ps\015aif"
6781 ".fswizz.ps\013aif.fswl.ps\013aif.fxor.pi\013aif.maskand\013aif.masknot\n"
6782 "aif.maskor\014aif.maskpopc\021aif.maskpopc.rast\015aif.maskpopcz\013aif"
6783 ".maskxor\013aif.mov.m.x\014aif.mova.m.x\014aif.mova.x.m\taif.packb\007a"
6784 "if.sbg\007aif.sbl\007aif.shg\007aif.shl\010amoadd.b\013amoadd.b.aq\015a"
6785 "moadd.b.aqrl\013amoadd.b.rl\010amoadd.d\013amoadd.d.aq\015amoadd.d.aqrl"
6786 "\013amoadd.d.rl\010amoadd.h\013amoadd.h.aq\015amoadd.h.aqrl\013amoadd.h"
6787 ".rl\010amoadd.w\013amoadd.w.aq\015amoadd.w.aqrl\013amoadd.w.rl\010amoan"
6788 "d.b\013amoand.b.aq\015amoand.b.aqrl\013amoand.b.rl\010amoand.d\013amoan"
6789 "d.d.aq\015amoand.d.aqrl\013amoand.d.rl\010amoand.h\013amoand.h.aq\015am"
6790 "oand.h.aqrl\013amoand.h.rl\010amoand.w\013amoand.w.aq\015amoand.w.aqrl\013"
6791 "amoand.w.rl\010amocas.b\013amocas.b.aq\015amocas.b.aqrl\013amocas.b.rl\010"
6792 "amocas.d\013amocas.d.aq\015amocas.d.aqrl\013amocas.d.rl\010amocas.h\013"
6793 "amocas.h.aq\015amocas.h.aqrl\013amocas.h.rl\010amocas.q\013amocas.q.aq\015"
6794 "amocas.q.aqrl\013amocas.q.rl\010amocas.w\013amocas.w.aq\015amocas.w.aqr"
6795 "l\013amocas.w.rl\010amomax.b\013amomax.b.aq\015amomax.b.aqrl\013amomax."
6796 "b.rl\010amomax.d\013amomax.d.aq\015amomax.d.aqrl\013amomax.d.rl\010amom"
6797 "ax.h\013amomax.h.aq\015amomax.h.aqrl\013amomax.h.rl\010amomax.w\013amom"
6798 "ax.w.aq\015amomax.w.aqrl\013amomax.w.rl\tamomaxu.b\014amomaxu.b.aq\016a"
6799 "momaxu.b.aqrl\014amomaxu.b.rl\tamomaxu.d\014amomaxu.d.aq\016amomaxu.d.a"
6800 "qrl\014amomaxu.d.rl\tamomaxu.h\014amomaxu.h.aq\016amomaxu.h.aqrl\014amo"
6801 "maxu.h.rl\tamomaxu.w\014amomaxu.w.aq\016amomaxu.w.aqrl\014amomaxu.w.rl\010"
6802 "amomin.b\013amomin.b.aq\015amomin.b.aqrl\013amomin.b.rl\010amomin.d\013"
6803 "amomin.d.aq\015amomin.d.aqrl\013amomin.d.rl\010amomin.h\013amomin.h.aq\015"
6804 "amomin.h.aqrl\013amomin.h.rl\010amomin.w\013amomin.w.aq\015amomin.w.aqr"
6805 "l\013amomin.w.rl\tamominu.b\014amominu.b.aq\016amominu.b.aqrl\014amomin"
6806 "u.b.rl\tamominu.d\014amominu.d.aq\016amominu.d.aqrl\014amominu.d.rl\tam"
6807 "ominu.h\014amominu.h.aq\016amominu.h.aqrl\014amominu.h.rl\tamominu.w\014"
6808 "amominu.w.aq\016amominu.w.aqrl\014amominu.w.rl\007amoor.b\namoor.b.aq\014"
6809 "amoor.b.aqrl\namoor.b.rl\007amoor.d\namoor.d.aq\014amoor.d.aqrl\namoor."
6810 "d.rl\007amoor.h\namoor.h.aq\014amoor.h.aqrl\namoor.h.rl\007amoor.w\namo"
6811 "or.w.aq\014amoor.w.aqrl\namoor.w.rl\tamoswap.b\014amoswap.b.aq\016amosw"
6812 "ap.b.aqrl\014amoswap.b.rl\tamoswap.d\014amoswap.d.aq\016amoswap.d.aqrl\014"
6813 "amoswap.d.rl\tamoswap.h\014amoswap.h.aq\016amoswap.h.aqrl\014amoswap.h."
6814 "rl\tamoswap.w\014amoswap.w.aq\016amoswap.w.aqrl\014amoswap.w.rl\010amox"
6815 "or.b\013amoxor.b.aq\015amoxor.b.aqrl\013amoxor.b.rl\010amoxor.d\013amox"
6816 "or.d.aq\015amoxor.d.aqrl\013amoxor.d.rl\010amoxor.h\013amoxor.h.aq\015a"
6817 "moxor.h.aqrl\013amoxor.h.rl\010amoxor.w\013amoxor.w.aq\015amoxor.w.aqrl"
6818 "\013amoxor.w.rl\003and\004andi\004andn\004asub\005asubu\005auipc\004bcl"
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7152 "vmaqa.vx\015th.vmaqasu.vv\015th.vmaqasu.vx\014th.vmaqau.vv\014th.vmaqau"
7153 ".vx\015th.vmaqaus.vx\005unimp\005unzip\tunzip16hp\010unzip16p\010unzip8"
7154 "hp\007unzip8p\005usati\013v8wmmacc.vv\010vaadd.vv\010vaadd.vx\tvaaddu.v"
7155 "v\tvaaddu.vx\007vabd.vv\007vabd.vx\010vabdu.vv\010vabdu.vx\006vabs.v\010"
7156 "vadc.vim\010vadc.vvm\010vadc.vxm\007vadd.vi\007vadd.vv\007vadd.vx\tvaes"
7157 "df.vs\tvaesdf.vv\tvaesdm.vs\tvaesdm.vv\tvaesef.vs\tvaesef.vv\tvaesem.vs"
7158 "\tvaesem.vv\nvaeskf1.vi\nvaeskf2.vi\010vaesz.vs\007vand.vi\007vand.vv\007"
7159 "vand.vx\010vandn.vv\010vandn.vx\010vasub.vv\010vasub.vx\tvasubu.vv\tvas"
7160 "ubu.vx\007vbrev.v\010vbrev8.v\tvclmul.vv\tvclmul.vx\nvclmulh.vv\nvclmul"
7161 "h.vx\006vclz.v\014vcompress.vm\007vcpop.m\007vcpop.v\006vctz.v\007vdiv."
7162 "vv\007vdiv.vx\010vdivu.vv\010vdivu.vx\tvdot4a.vv\tvdot4a.vx\013vdot4asu"
7163 ".vv\013vdot4asu.vx\nvdot4au.vv\nvdot4au.vx\013vdot4aus.vx\015vf8wimmacc"
7164 ".vv\014vf8wmmacc.vv\007vfabs.v\010vfadd.vf\010vfadd.vv\nvfbdota.vv\tvfc"
7165 "lass.v\013vfcvt.f.x.v\014vfcvt.f.xu.v\017vfcvt.rtz.x.f.v\020vfcvt.rtz.x"
7166 "u.f.v\013vfcvt.x.f.v\014vfcvt.xu.f.v\010vfdiv.vf\010vfdiv.vv\010vfirst."
7167 "m\tvfmacc.vf\tvfmacc.vv\tvfmadd.vf\tvfmadd.vv\010vfmax.vf\010vfmax.vv\013"
7168 "vfmerge.vfm\010vfmin.vf\010vfmin.vv\nvfmmacc.vv\tvfmsac.vf\tvfmsac.vv\t"
7169 "vfmsub.vf\tvfmsub.vv\010vfmul.vf\010vfmul.vv\010vfmv.f.s\010vfmv.s.f\010"
7170 "vfmv.v.f\014vfncvt.f.f.q\014vfncvt.f.f.w\014vfncvt.f.x.w\015vfncvt.f.xu"
7171 ".w\020vfncvt.rod.f.f.w\020vfncvt.rtz.x.f.w\021vfncvt.rtz.xu.f.w\020vfnc"
7172 "vt.sat.f.f.q\014vfncvt.x.f.w\015vfncvt.xu.f.w\020vfncvtbf16.f.f.w\024vf"
7173 "ncvtbf16.sat.f.f.w\007vfneg.v\nvfnmacc.vf\nvfnmacc.vv\nvfnmadd.vf\nvfnm"
7174 "add.vv\nvfnmsac.vf\nvfnmsac.vv\nvfnmsub.vf\nvfnmsub.vv\014vfqimmacc.vv\013"
7175 "vfqmmacc.vv\020vfqwbdota.alt.vv\014vfqwbdota.vv\017vfqwdota.alt.vv\013v"
7176 "fqwdota.vv\tvfrdiv.vf\010vfrec7.v\013vfredmax.vs\013vfredmin.vs\014vfre"
7177 "dosum.vs\014vfredusum.vs\nvfrsqrt7.v\tvfrsub.vf\tvfsgnj.vf\tvfsgnj.vv\n"
7178 "vfsgnjn.vf\nvfsgnjn.vv\nvfsgnjx.vf\nvfsgnjx.vv\017vfslide1down.vf\015vf"
7179 "slide1up.vf\010vfsqrt.v\010vfsub.vf\010vfsub.vv\tvfwadd.vf\tvfwadd.vv\t"
7180 "vfwadd.wf\tvfwadd.wv\013vfwbdota.vv\014vfwcvt.f.f.v\014vfwcvt.f.x.v\015"
7181 "vfwcvt.f.xu.v\020vfwcvt.rtz.x.f.v\021vfwcvt.rtz.xu.f.v\014vfwcvt.x.f.v\015"
7182 "vfwcvt.xu.f.v\020vfwcvtbf16.f.f.v\nvfwdota.vv\014vfwimmacc.vv\nvfwmacc."
7183 "vf\nvfwmacc.vv\016vfwmaccbf16.vf\016vfwmaccbf16.vv\013vfwmmacc.vv\nvfwm"
7184 "sac.vf\nvfwmsac.vv\tvfwmul.vf\tvfwmul.vv\013vfwnmacc.vf\013vfwnmacc.vv\013"
7185 "vfwnmsac.vf\013vfwnmsac.vv\015vfwredosum.vs\015vfwredusum.vs\tvfwsub.vf"
7186 "\tvfwsub.vv\tvfwsub.wf\tvfwsub.wv\010vghsh.vs\010vghsh.vv\010vgmul.vs\010"
7187 "vgmul.vv\005vid.v\007viota.m\006vl1r.v\tvl1re16.v\tvl1re32.v\tvl1re64.v"
7188 "\010vl1re8.v\006vl2r.v\tvl2re16.v\tvl2re32.v\tvl2re64.v\010vl2re8.v\006"
7189 "vl4r.v\tvl4re16.v\tvl4re32.v\tvl4re64.v\010vl4re8.v\006vl8r.v\tvl8re16."
7190 "v\tvl8re32.v\tvl8re64.v\010vl8re8.v\007vle16.v\tvle16ff.v\007vle32.v\tv"
7191 "le32ff.v\007vle64.v\tvle64ff.v\006vle8.v\010vle8ff.v\005vlm.v\nvloxei16"
7192 ".v\nvloxei32.v\nvloxei64.v\tvloxei8.v\016vloxseg2ei16.v\016vloxseg2ei32"
7193 ".v\016vloxseg2ei64.v\015vloxseg2ei8.v\016vloxseg3ei16.v\016vloxseg3ei32"
7194 ".v\016vloxseg3ei64.v\015vloxseg3ei8.v\016vloxseg4ei16.v\016vloxseg4ei32"
7195 ".v\016vloxseg4ei64.v\015vloxseg4ei8.v\016vloxseg5ei16.v\016vloxseg5ei32"
7196 ".v\016vloxseg5ei64.v\015vloxseg5ei8.v\016vloxseg6ei16.v\016vloxseg6ei32"
7197 ".v\016vloxseg6ei64.v\015vloxseg6ei8.v\016vloxseg7ei16.v\016vloxseg7ei32"
7198 ".v\016vloxseg7ei64.v\015vloxseg7ei8.v\016vloxseg8ei16.v\016vloxseg8ei32"
7199 ".v\016vloxseg8ei64.v\015vloxseg8ei8.v\010vlse16.v\010vlse32.v\010vlse64"
7200 ".v\007vlse8.v\013vlseg2e16.v\015vlseg2e16ff.v\013vlseg2e32.v\015vlseg2e"
7201 "32ff.v\013vlseg2e64.v\015vlseg2e64ff.v\nvlseg2e8.v\014vlseg2e8ff.v\013v"
7202 "lseg3e16.v\015vlseg3e16ff.v\013vlseg3e32.v\015vlseg3e32ff.v\013vlseg3e6"
7203 "4.v\015vlseg3e64ff.v\nvlseg3e8.v\014vlseg3e8ff.v\013vlseg4e16.v\015vlse"
7204 "g4e16ff.v\013vlseg4e32.v\015vlseg4e32ff.v\013vlseg4e64.v\015vlseg4e64ff"
7205 ".v\nvlseg4e8.v\014vlseg4e8ff.v\013vlseg5e16.v\015vlseg5e16ff.v\013vlseg"
7206 "5e32.v\015vlseg5e32ff.v\013vlseg5e64.v\015vlseg5e64ff.v\nvlseg5e8.v\014"
7207 "vlseg5e8ff.v\013vlseg6e16.v\015vlseg6e16ff.v\013vlseg6e32.v\015vlseg6e3"
7208 "2ff.v\013vlseg6e64.v\015vlseg6e64ff.v\nvlseg6e8.v\014vlseg6e8ff.v\013vl"
7209 "seg7e16.v\015vlseg7e16ff.v\013vlseg7e32.v\015vlseg7e32ff.v\013vlseg7e64"
7210 ".v\015vlseg7e64ff.v\nvlseg7e8.v\014vlseg7e8ff.v\013vlseg8e16.v\015vlseg"
7211 "8e16ff.v\013vlseg8e32.v\015vlseg8e32ff.v\013vlseg8e64.v\015vlseg8e64ff."
7212 "v\nvlseg8e8.v\014vlseg8e8ff.v\014vlsseg2e16.v\014vlsseg2e32.v\014vlsseg"
7213 "2e64.v\013vlsseg2e8.v\014vlsseg3e16.v\014vlsseg3e32.v\014vlsseg3e64.v\013"
7214 "vlsseg3e8.v\014vlsseg4e16.v\014vlsseg4e32.v\014vlsseg4e64.v\013vlsseg4e"
7215 "8.v\014vlsseg5e16.v\014vlsseg5e32.v\014vlsseg5e64.v\013vlsseg5e8.v\014v"
7216 "lsseg6e16.v\014vlsseg6e32.v\014vlsseg6e64.v\013vlsseg6e8.v\014vlsseg7e1"
7217 "6.v\014vlsseg7e32.v\014vlsseg7e64.v\013vlsseg7e8.v\014vlsseg8e16.v\014v"
7218 "lsseg8e32.v\014vlsseg8e64.v\013vlsseg8e8.v\nvluxei16.v\nvluxei32.v\nvlu"
7219 "xei64.v\tvluxei8.v\016vluxseg2ei16.v\016vluxseg2ei32.v\016vluxseg2ei64."
7220 "v\015vluxseg2ei8.v\016vluxseg3ei16.v\016vluxseg3ei32.v\016vluxseg3ei64."
7221 "v\015vluxseg3ei8.v\016vluxseg4ei16.v\016vluxseg4ei32.v\016vluxseg4ei64."
7222 "v\015vluxseg4ei8.v\016vluxseg5ei16.v\016vluxseg5ei32.v\016vluxseg5ei64."
7223 "v\015vluxseg5ei8.v\016vluxseg6ei16.v\016vluxseg6ei32.v\016vluxseg6ei64."
7224 "v\015vluxseg6ei8.v\016vluxseg7ei16.v\016vluxseg7ei32.v\016vluxseg7ei64."
7225 "v\015vluxseg7ei8.v\016vluxseg8ei16.v\016vluxseg8ei32.v\016vluxseg8ei64."
7226 "v\015vluxseg8ei8.v\010vmacc.vv\010vmacc.vx\010vmadc.vi\tvmadc.vim\010vm"
7227 "adc.vv\tvmadc.vvm\010vmadc.vx\tvmadc.vxm\010vmadd.vv\010vmadd.vx\010vma"
7228 "nd.mm\tvmandn.mm\007vmax.vv\007vmax.vx\010vmaxu.vv\010vmaxu.vx\007vmclr"
7229 ".m\nvmerge.vim\nvmerge.vvm\nvmerge.vxm\010vmfeq.vf\010vmfeq.vv\010vmfge"
7230 ".vf\010vmfge.vv\010vmfgt.vf\010vmfgt.vv\010vmfle.vf\010vmfle.vv\010vmfl"
7231 "t.vf\010vmflt.vv\010vmfne.vf\010vmfne.vv\007vmin.vv\007vmin.vx\010vminu"
7232 ".vv\010vminu.vx\tvmmacc.vv\006vmmv.m\tvmnand.mm\010vmnor.mm\007vmnot.m\007"
7233 "vmor.mm\010vmorn.mm\010vmsbc.vv\tvmsbc.vvm\010vmsbc.vx\tvmsbc.vxm\007vm"
7234 "sbf.m\010vmseq.vi\010vmseq.vv\010vmseq.vx\007vmset.m\010vmsge.vi\010vms"
7235 "ge.vv\010vmsge.vx\tvmsgeu.vi\tvmsgeu.vv\tvmsgeu.vx\010vmsgt.vi\010vmsgt"
7236 ".vv\010vmsgt.vx\tvmsgtu.vi\tvmsgtu.vv\tvmsgtu.vx\007vmsif.m\010vmsle.vi"
7237 "\010vmsle.vv\010vmsle.vx\tvmsleu.vi\tvmsleu.vv\tvmsleu.vx\010vmslt.vi\010"
7238 "vmslt.vv\010vmslt.vx\tvmsltu.vi\tvmsltu.vv\tvmsltu.vx\010vmsne.vi\010vm"
7239 "sne.vv\010vmsne.vx\007vmsof.m\006vmtl.v\006vmts.v\007vmttl.v\007vmtts.v"
7240 "\007vmul.vv\007vmul.vx\010vmulh.vv\010vmulh.vx\nvmulhsu.vv\nvmulhsu.vx\t"
7241 "vmulhu.vv\tvmulhu.vx\007vmv.s.x\007vmv.v.i\007vmv.v.v\007vmv.v.x\007vmv"
7242 ".x.s\007vmv1r.v\007vmv2r.v\007vmv4r.v\007vmv8r.v\tvmxnor.mm\010vmxor.mm"
7243 "\tvnclip.wi\tvnclip.wv\tvnclip.wx\nvnclipu.wi\nvnclipu.wv\nvnclipu.wx\013"
7244 "vncvt.x.x.w\006vneg.v\tvnmsac.vv\tvnmsac.vx\tvnmsub.vv\tvnmsub.vx\006vn"
7245 "ot.v\010vnsra.wi\010vnsra.wv\010vnsra.wx\010vnsrl.wi\010vnsrl.wv\010vns"
7246 "rl.wx\006vor.vi\006vor.vv\006vor.vx\tvpaire.vv\tvpairo.vv\nvqmmacc.vv\014"
7247 "vqwbdotas.vv\014vqwbdotau.vv\013vqwdotas.vv\013vqwdotau.vv\nvredand.vs\n"
7248 "vredmax.vs\013vredmaxu.vs\nvredmin.vs\013vredminu.vs\tvredor.vs\nvredsu"
7249 "m.vs\nvredxor.vs\007vrem.vv\007vrem.vx\010vremu.vv\010vremu.vx\007vrev8"
7250 ".v\013vrgather.vi\013vrgather.vv\013vrgather.vx\017vrgatherei16.vv\007v"
7251 "rol.vv\007vrol.vx\007vror.vi\007vror.vv\007vror.vx\010vrsub.vi\010vrsub"
7252 ".vx\006vs1r.v\006vs2r.v\006vs4r.v\006vs8r.v\010vsadd.vi\010vsadd.vv\010"
7253 "vsadd.vx\tvsaddu.vi\tvsaddu.vv\tvsaddu.vx\010vsbc.vvm\010vsbc.vxm\007vs"
7254 "e16.v\007vse32.v\007vse64.v\006vse8.v\010vsetivli\006vsetvl\007vsetvli\t"
7255 "vsext.vf2\tvsext.vf4\tvsext.vf8\nvsha2ch.vv\nvsha2cl.vv\nvsha2ms.vv\016"
7256 "vslide1down.vx\014vslide1up.vx\015vslidedown.vi\015vslidedown.vx\013vsl"
7257 "ideup.vi\013vslideup.vx\007vsll.vi\007vsll.vv\007vsll.vx\005vsm.v\010vs"
7258 "m3c.vi\tvsm3me.vv\010vsm4k.vi\010vsm4r.vs\010vsm4r.vv\010vsmul.vv\010vs"
7259 "mul.vx\nvsoxei16.v\nvsoxei32.v\nvsoxei64.v\tvsoxei8.v\016vsoxseg2ei16.v"
7260 "\016vsoxseg2ei32.v\016vsoxseg2ei64.v\015vsoxseg2ei8.v\016vsoxseg3ei16.v"
7261 "\016vsoxseg3ei32.v\016vsoxseg3ei64.v\015vsoxseg3ei8.v\016vsoxseg4ei16.v"
7262 "\016vsoxseg4ei32.v\016vsoxseg4ei64.v\015vsoxseg4ei8.v\016vsoxseg5ei16.v"
7263 "\016vsoxseg5ei32.v\016vsoxseg5ei64.v\015vsoxseg5ei8.v\016vsoxseg6ei16.v"
7264 "\016vsoxseg6ei32.v\016vsoxseg6ei64.v\015vsoxseg6ei8.v\016vsoxseg7ei16.v"
7265 "\016vsoxseg7ei32.v\016vsoxseg7ei64.v\015vsoxseg7ei8.v\016vsoxseg8ei16.v"
7266 "\016vsoxseg8ei32.v\016vsoxseg8ei64.v\015vsoxseg8ei8.v\007vsra.vi\007vsr"
7267 "a.vv\007vsra.vx\007vsrl.vi\007vsrl.vv\007vsrl.vx\010vsse16.v\010vsse32."
7268 "v\010vsse64.v\007vsse8.v\013vsseg2e16.v\013vsseg2e32.v\013vsseg2e64.v\n"
7269 "vsseg2e8.v\013vsseg3e16.v\013vsseg3e32.v\013vsseg3e64.v\nvsseg3e8.v\013"
7270 "vsseg4e16.v\013vsseg4e32.v\013vsseg4e64.v\nvsseg4e8.v\013vsseg5e16.v\013"
7271 "vsseg5e32.v\013vsseg5e64.v\nvsseg5e8.v\013vsseg6e16.v\013vsseg6e32.v\013"
7272 "vsseg6e64.v\nvsseg6e8.v\013vsseg7e16.v\013vsseg7e32.v\013vsseg7e64.v\nv"
7273 "sseg7e8.v\013vsseg8e16.v\013vsseg8e32.v\013vsseg8e64.v\nvsseg8e8.v\010v"
7274 "ssra.vi\010vssra.vv\010vssra.vx\010vssrl.vi\010vssrl.vv\010vssrl.vx\014"
7275 "vssseg2e16.v\014vssseg2e32.v\014vssseg2e64.v\013vssseg2e8.v\014vssseg3e"
7276 "16.v\014vssseg3e32.v\014vssseg3e64.v\013vssseg3e8.v\014vssseg4e16.v\014"
7277 "vssseg4e32.v\014vssseg4e64.v\013vssseg4e8.v\014vssseg5e16.v\014vssseg5e"
7278 "32.v\014vssseg5e64.v\013vssseg5e8.v\014vssseg6e16.v\014vssseg6e32.v\014"
7279 "vssseg6e64.v\013vssseg6e8.v\014vssseg7e16.v\014vssseg7e32.v\014vssseg7e"
7280 "64.v\013vssseg7e8.v\014vssseg8e16.v\014vssseg8e32.v\014vssseg8e64.v\013"
7281 "vssseg8e8.v\010vssub.vv\010vssub.vx\tvssubu.vv\tvssubu.vx\007vsub.vv\007"
7282 "vsub.vx\nvsuxei16.v\nvsuxei32.v\nvsuxei64.v\tvsuxei8.v\016vsuxseg2ei16."
7283 "v\016vsuxseg2ei32.v\016vsuxseg2ei64.v\015vsuxseg2ei8.v\016vsuxseg3ei16."
7284 "v\016vsuxseg3ei32.v\016vsuxseg3ei64.v\015vsuxseg3ei8.v\016vsuxseg4ei16."
7285 "v\016vsuxseg4ei32.v\016vsuxseg4ei64.v\015vsuxseg4ei8.v\016vsuxseg5ei16."
7286 "v\016vsuxseg5ei32.v\016vsuxseg5ei64.v\015vsuxseg5ei8.v\016vsuxseg6ei16."
7287 "v\016vsuxseg6ei32.v\016vsuxseg6ei64.v\015vsuxseg6ei8.v\016vsuxseg7ei16."
7288 "v\016vsuxseg7ei32.v\016vsuxseg7ei64.v\015vsuxseg7ei8.v\016vsuxseg8ei16."
7289 "v\016vsuxseg8ei32.v\016vsuxseg8ei64.v\015vsuxseg8ei8.v\tvunzipe.v\tvunz"
7290 "ipo.v\tvwabda.vv\tvwabda.vx\nvwabdau.vv\nvwabdau.vx\010vwadd.vv\010vwad"
7291 "d.vx\010vwadd.wv\010vwadd.wx\tvwaddu.vv\tvwaddu.vx\tvwaddu.wv\tvwaddu.w"
7292 "x\013vwcvt.x.x.v\014vwcvtu.x.x.v\tvwmacc.vv\tvwmacc.vx\013vwmaccsu.vv\013"
7293 "vwmaccsu.vx\nvwmaccu.vv\nvwmaccu.vx\013vwmaccus.vx\nvwmmacc.vv\010vwmul"
7294 ".vv\010vwmul.vx\nvwmulsu.vv\nvwmulsu.vx\tvwmulu.vv\tvwmulu.vx\013vwreds"
7295 "um.vs\014vwredsumu.vs\010vwsll.vi\010vwsll.vv\010vwsll.vx\010vwsub.vv\010"
7296 "vwsub.vx\010vwsub.wv\010vwsub.wx\tvwsubu.vv\tvwsubu.vx\tvwsubu.wv\tvwsu"
7297 "bu.wx\007vxor.vi\007vxor.vv\007vxor.vx\tvzext.vf2\tvzext.vf4\tvzext.vf8"
7298 "\007vzip.vv\004wadd\005wadda\006waddau\005waddu\003wfi\005wmacc\007wmac"
7299 "csu\006wmaccu\004wmul\006wmulsu\005wmulu\007wrs.nto\007wrs.sto\004wsla\005"
7300 "wslai\004wsll\005wslli\004wsub\005wsuba\006wsubau\005wsubu\007wzip16p\006"
7301 "wzip8p\004xnor\003xor\004xori\006xperm4\006xperm8\004yadd\005yaddi\006y"
7302 "addrw\006yamask\006ybaser\004ybld\007ybndsrw\006ybndsw\007ybndswi\003ye"
7303 "q\004yhir\004yhiw\005ylenr\003ymv\006ypermc\006ypermr\006yseale\003yss\005"
7304 "ytagr\005ytopr\006ytyper\010yunseals\006zext.b\006zext.h\006zext.w\003z"
7305 "ip\007zip16hp\006zip16p\006zip8hp\005zip8p";
7306
7307// Feature bitsets.
7308enum : uint8_t {
7309 AMFBS_None,
7310 AMFBS_HasHalfFPLoadStoreMove,
7311 AMFBS_HasStdExtD,
7312 AMFBS_HasStdExtF,
7313 AMFBS_HasStdExtFOrZfinx,
7314 AMFBS_HasStdExtH,
7315 AMFBS_HasStdExtM,
7316 AMFBS_HasStdExtP,
7317 AMFBS_HasStdExtQ,
7318 AMFBS_HasStdExtSmcsps,
7319 AMFBS_HasStdExtSmctrOrSsctr,
7320 AMFBS_HasStdExtSmip,
7321 AMFBS_HasStdExtSmrnmi,
7322 AMFBS_HasStdExtSscsps,
7323 AMFBS_HasStdExtSsip,
7324 AMFBS_HasStdExtSvinval,
7325 AMFBS_HasStdExtY,
7326 AMFBS_HasStdExtZaamo,
7327 AMFBS_HasStdExtZabha,
7328 AMFBS_HasStdExtZacas,
7329 AMFBS_HasStdExtZalasr,
7330 AMFBS_HasStdExtZalrsc,
7331 AMFBS_HasStdExtZawrs,
7332 AMFBS_HasStdExtZba,
7333 AMFBS_HasStdExtZbb,
7334 AMFBS_HasStdExtZbbOrZbkb,
7335 AMFBS_HasStdExtZbc,
7336 AMFBS_HasStdExtZbkb,
7337 AMFBS_HasStdExtZbkbOrP,
7338 AMFBS_HasStdExtZbkc,
7339 AMFBS_HasStdExtZbkx,
7340 AMFBS_HasStdExtZbs,
7341 AMFBS_HasStdExtZca,
7342 AMFBS_HasStdExtZcb,
7343 AMFBS_HasStdExtZcd,
7344 AMFBS_HasStdExtZcmop,
7345 AMFBS_HasStdExtZcmp,
7346 AMFBS_HasStdExtZcmt,
7347 AMFBS_HasStdExtZfa,
7348 AMFBS_HasStdExtZfbfmin,
7349 AMFBS_HasStdExtZfh,
7350 AMFBS_HasStdExtZfhmin,
7351 AMFBS_HasStdExtZfinx,
7352 AMFBS_HasStdExtZhinx,
7353 AMFBS_HasStdExtZhinxmin,
7354 AMFBS_HasStdExtZibi,
7355 AMFBS_HasStdExtZicbom,
7356 AMFBS_HasStdExtZicboz,
7357 AMFBS_HasStdExtZicfiss,
7358 AMFBS_HasStdExtZicond,
7359 AMFBS_HasStdExtZilx,
7360 AMFBS_HasStdExtZimop,
7361 AMFBS_HasStdExtZknh,
7362 AMFBS_HasStdExtZksed,
7363 AMFBS_HasStdExtZksh,
7364 AMFBS_HasStdExtZmmul,
7365 AMFBS_HasStdExtZvabd,
7366 AMFBS_HasStdExtZvbb,
7367 AMFBS_HasStdExtZvbcOrZvbc32e,
7368 AMFBS_HasStdExtZvdot4a8i,
7369 AMFBS_HasStdExtZvfbdota32f,
7370 AMFBS_HasStdExtZvfbfminOrZvfofp8min,
7371 AMFBS_HasStdExtZvfbfwma,
7372 AMFBS_HasStdExtZvfofp8min,
7373 AMFBS_HasStdExtZvfqwbdota8f,
7374 AMFBS_HasStdExtZvfqwdota8f,
7375 AMFBS_HasStdExtZvfwbdota16bf,
7376 AMFBS_HasStdExtZvfwdota16bf,
7377 AMFBS_HasStdExtZvkb,
7378 AMFBS_HasStdExtZvkg,
7379 AMFBS_HasStdExtZvkgs,
7380 AMFBS_HasStdExtZvkned,
7381 AMFBS_HasStdExtZvknha,
7382 AMFBS_HasStdExtZvksed,
7383 AMFBS_HasStdExtZvksh,
7384 AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i,
7385 AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i,
7386 AMFBS_HasStdExtZvvfmm,
7387 AMFBS_HasStdExtZvvmm,
7388 AMFBS_HasStdExtZvvmtls,
7389 AMFBS_HasStdExtZvvmttls,
7390 AMFBS_HasStdExtZvzip,
7391 AMFBS_HasVInstructions,
7392 AMFBS_HasVInstructionsAnyF,
7393 AMFBS_HasVInstructionsI64,
7394 AMFBS_HasVendorXAndesBFHCvt,
7395 AMFBS_HasVendorXAndesPerf,
7396 AMFBS_HasVendorXAndesVBFHCvt,
7397 AMFBS_HasVendorXAndesVDot,
7398 AMFBS_HasVendorXAndesVPackFPH,
7399 AMFBS_HasVendorXAndesVSIntH,
7400 AMFBS_HasVendorXAndesVSIntLoad,
7401 AMFBS_HasVendorXMIPSCBOP,
7402 AMFBS_HasVendorXMIPSCMov,
7403 AMFBS_HasVendorXMIPSEXECTL,
7404 AMFBS_HasVendorXMIPSLSP,
7405 AMFBS_HasVendorXSfcease,
7406 AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f,
7407 AMFBS_HasVendorXSfmm32a8f,
7408 AMFBS_HasVendorXSfmm32a8i,
7409 AMFBS_HasVendorXSfmmbase,
7410 AMFBS_HasVendorXSfvcp,
7411 AMFBS_HasVendorXSfvfexpAny,
7412 AMFBS_HasVendorXSfvfexpa,
7413 AMFBS_HasVendorXSfvfnrclipxfqf,
7414 AMFBS_HasVendorXSfvfwmaccqqq,
7415 AMFBS_HasVendorXSfvqmaccdod,
7416 AMFBS_HasVendorXSfvqmaccqoq,
7417 AMFBS_HasVendorXSiFivecdiscarddlone,
7418 AMFBS_HasVendorXSiFivecflushdlone,
7419 AMFBS_HasVendorXTHeadBa,
7420 AMFBS_HasVendorXTHeadBb,
7421 AMFBS_HasVendorXTHeadBs,
7422 AMFBS_HasVendorXTHeadCmo,
7423 AMFBS_HasVendorXTHeadCondMov,
7424 AMFBS_HasVendorXTHeadMac,
7425 AMFBS_HasVendorXTHeadMemIdx,
7426 AMFBS_HasVendorXTHeadMemPair,
7427 AMFBS_HasVendorXTHeadSync,
7428 AMFBS_HasVendorXTHeadVdot,
7429 AMFBS_HasVendorXqccmp,
7430 AMFBS_HasVendorXqccmt,
7431 AMFBS_HasVendorXwchc,
7432 AMFBS_HasXAIFET,
7433 AMFBS_IsRV32,
7434 AMFBS_IsRV64,
7435 AMFBS_HasStdExtD_IsRV64,
7436 AMFBS_HasStdExtF_IsRV64,
7437 AMFBS_HasStdExtM_IsRV64,
7438 AMFBS_HasStdExtP_IsRV32,
7439 AMFBS_HasStdExtP_IsRV64,
7440 AMFBS_HasStdExtQ_IsRV64,
7441 AMFBS_HasStdExtSvinval_HasStdExtH,
7442 AMFBS_HasStdExtZaamo_IsRV64,
7443 AMFBS_HasStdExtZabha_HasStdExtZacas,
7444 AMFBS_HasStdExtZacas_IsRV32,
7445 AMFBS_HasStdExtZacas_IsRV64,
7446 AMFBS_HasStdExtZalasr_IsRV64,
7447 AMFBS_HasStdExtZalrsc_IsRV64,
7448 AMFBS_HasStdExtZba_IsRV64,
7449 AMFBS_HasStdExtZbb_IsRV64,
7450 AMFBS_HasStdExtZbbOrZbkb_IsRV32,
7451 AMFBS_HasStdExtZbbOrZbkb_IsRV64,
7452 AMFBS_HasStdExtZbkb_IsRV32,
7453 AMFBS_HasStdExtZbkb_IsRV64,
7454 AMFBS_HasStdExtZca_IsRV32,
7455 AMFBS_HasStdExtZca_IsRV64,
7456 AMFBS_HasStdExtZcb_HasStdExtZbb,
7457 AMFBS_HasStdExtZcb_HasStdExtZmmul,
7458 AMFBS_HasStdExtZcf_IsRV32,
7459 AMFBS_HasStdExtZclsd_IsRV32,
7460 AMFBS_HasStdExtZdinx_IsRV32,
7461 AMFBS_HasStdExtZdinx_IsRV64,
7462 AMFBS_HasStdExtZfa_HasStdExtD,
7463 AMFBS_HasStdExtZfa_HasStdExtQ,
7464 AMFBS_HasStdExtZfa_HasStdExtZfh,
7465 AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh,
7466 AMFBS_HasStdExtZfh_IsRV64,
7467 AMFBS_HasStdExtZfhmin_HasStdExtD,
7468 AMFBS_HasStdExtZfhmin_HasStdExtQ,
7469 AMFBS_HasStdExtZfinx_IsRV64,
7470 AMFBS_HasStdExtZhinx_IsRV64,
7471 AMFBS_HasStdExtZicfiss_IsRV64,
7472 AMFBS_HasStdExtZilsd_IsRV32,
7473 AMFBS_HasStdExtZilx_IsRV64,
7474 AMFBS_HasStdExtZknd_IsRV32,
7475 AMFBS_HasStdExtZknd_IsRV64,
7476 AMFBS_HasStdExtZkndOrZkne_IsRV64,
7477 AMFBS_HasStdExtZkne_IsRV32,
7478 AMFBS_HasStdExtZkne_IsRV64,
7479 AMFBS_HasStdExtZknh_IsRV32,
7480 AMFBS_HasStdExtZknh_IsRV64,
7481 AMFBS_HasStdExtZmmul_IsRV64,
7482 AMFBS_HasVInstructionsI64_IsRV64,
7483 AMFBS_HasVendorXAndesPerf_IsRV64,
7484 AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF,
7485 AMFBS_HasVendorXCValu_IsRV32,
7486 AMFBS_HasVendorXCVbi_IsRV32,
7487 AMFBS_HasVendorXCVbitmanip_IsRV32,
7488 AMFBS_HasVendorXCVelw_IsRV32,
7489 AMFBS_HasVendorXCVmac_IsRV32,
7490 AMFBS_HasVendorXCVmem_IsRV32,
7491 AMFBS_HasVendorXCVsimd_IsRV32,
7492 AMFBS_HasVendorXMIPSLSP_IsRV64,
7493 AMFBS_HasVendorXSMTVDot_IsRV64,
7494 AMFBS_HasVendorXSMTVDotII_IsRV64,
7495 AMFBS_HasVendorXTHeadBb_IsRV64,
7496 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD,
7497 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF,
7498 AMFBS_HasVendorXTHeadMac_IsRV64,
7499 AMFBS_HasVendorXTHeadMemIdx_IsRV64,
7500 AMFBS_HasVendorXTHeadMemPair_IsRV64,
7501 AMFBS_HasVendorXqccmi_IsRV32,
7502 AMFBS_HasVendorXqcia_IsRV32,
7503 AMFBS_HasVendorXqciac_IsRV32,
7504 AMFBS_HasVendorXqcibi_IsRV32,
7505 AMFBS_HasVendorXqcibm_IsRV32,
7506 AMFBS_HasVendorXqcicli_IsRV32,
7507 AMFBS_HasVendorXqcicm_IsRV32,
7508 AMFBS_HasVendorXqcics_IsRV32,
7509 AMFBS_HasVendorXqcicsr_IsRV32,
7510 AMFBS_HasVendorXqciint_IsRV32,
7511 AMFBS_HasVendorXqciio_IsRV32,
7512 AMFBS_HasVendorXqcilb_IsRV32,
7513 AMFBS_HasVendorXqcili_IsRV32,
7514 AMFBS_HasVendorXqcilia_IsRV32,
7515 AMFBS_HasVendorXqcilo_IsRV32,
7516 AMFBS_HasVendorXqcilsm_IsRV32,
7517 AMFBS_HasVendorXqcisim_IsRV32,
7518 AMFBS_HasVendorXqcisls_IsRV32,
7519 AMFBS_HasVendorXqcisync_IsRV32,
7520 AMFBS_IsRV32_HasStdExtZca,
7521 AMFBS_IsRV32_HasStdExtZcb,
7522 AMFBS_IsRV64_HasStdExtH,
7523 AMFBS_IsRV64_HasVInstructionsI64,
7524 AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64,
7525 AMFBS_HasStdExtZdinx_IsRV64_IsRV64,
7526 AMFBS_HasStdExtZfa_HasStdExtD_IsRV32,
7527 AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64,
7528 AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32,
7529 AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64,
7530 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64,
7531 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64,
7532 AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32,
7533};
7534
7535static constexpr FeatureBitset FeatureBitsets[] = {
7536 {}, // AMFBS_None
7537 {Feature_HasHalfFPLoadStoreMoveBit, }, // AMFBS_HasHalfFPLoadStoreMove
7538 {Feature_HasStdExtDBit, }, // AMFBS_HasStdExtD
7539 {Feature_HasStdExtFBit, }, // AMFBS_HasStdExtF
7540 {Feature_HasStdExtFOrZfinxBit, }, // AMFBS_HasStdExtFOrZfinx
7541 {Feature_HasStdExtHBit, }, // AMFBS_HasStdExtH
7542 {Feature_HasStdExtMBit, }, // AMFBS_HasStdExtM
7543 {Feature_HasStdExtPBit, }, // AMFBS_HasStdExtP
7544 {Feature_HasStdExtQBit, }, // AMFBS_HasStdExtQ
7545 {Feature_HasStdExtSmcspsBit, }, // AMFBS_HasStdExtSmcsps
7546 {Feature_HasStdExtSmctrOrSsctrBit, }, // AMFBS_HasStdExtSmctrOrSsctr
7547 {Feature_HasStdExtSmipBit, }, // AMFBS_HasStdExtSmip
7548 {Feature_HasStdExtSmrnmiBit, }, // AMFBS_HasStdExtSmrnmi
7549 {Feature_HasStdExtSscspsBit, }, // AMFBS_HasStdExtSscsps
7550 {Feature_HasStdExtSsipBit, }, // AMFBS_HasStdExtSsip
7551 {Feature_HasStdExtSvinvalBit, }, // AMFBS_HasStdExtSvinval
7552 {Feature_HasStdExtYBit, }, // AMFBS_HasStdExtY
7553 {Feature_HasStdExtZaamoBit, }, // AMFBS_HasStdExtZaamo
7554 {Feature_HasStdExtZabhaBit, }, // AMFBS_HasStdExtZabha
7555 {Feature_HasStdExtZacasBit, }, // AMFBS_HasStdExtZacas
7556 {Feature_HasStdExtZalasrBit, }, // AMFBS_HasStdExtZalasr
7557 {Feature_HasStdExtZalrscBit, }, // AMFBS_HasStdExtZalrsc
7558 {Feature_HasStdExtZawrsBit, }, // AMFBS_HasStdExtZawrs
7559 {Feature_HasStdExtZbaBit, }, // AMFBS_HasStdExtZba
7560 {Feature_HasStdExtZbbBit, }, // AMFBS_HasStdExtZbb
7561 {Feature_HasStdExtZbbOrZbkbBit, }, // AMFBS_HasStdExtZbbOrZbkb
7562 {Feature_HasStdExtZbcBit, }, // AMFBS_HasStdExtZbc
7563 {Feature_HasStdExtZbkbBit, }, // AMFBS_HasStdExtZbkb
7564 {Feature_HasStdExtZbkbOrPBit, }, // AMFBS_HasStdExtZbkbOrP
7565 {Feature_HasStdExtZbkcBit, }, // AMFBS_HasStdExtZbkc
7566 {Feature_HasStdExtZbkxBit, }, // AMFBS_HasStdExtZbkx
7567 {Feature_HasStdExtZbsBit, }, // AMFBS_HasStdExtZbs
7568 {Feature_HasStdExtZcaBit, }, // AMFBS_HasStdExtZca
7569 {Feature_HasStdExtZcbBit, }, // AMFBS_HasStdExtZcb
7570 {Feature_HasStdExtZcdBit, }, // AMFBS_HasStdExtZcd
7571 {Feature_HasStdExtZcmopBit, }, // AMFBS_HasStdExtZcmop
7572 {Feature_HasStdExtZcmpBit, }, // AMFBS_HasStdExtZcmp
7573 {Feature_HasStdExtZcmtBit, }, // AMFBS_HasStdExtZcmt
7574 {Feature_HasStdExtZfaBit, }, // AMFBS_HasStdExtZfa
7575 {Feature_HasStdExtZfbfminBit, }, // AMFBS_HasStdExtZfbfmin
7576 {Feature_HasStdExtZfhBit, }, // AMFBS_HasStdExtZfh
7577 {Feature_HasStdExtZfhminBit, }, // AMFBS_HasStdExtZfhmin
7578 {Feature_HasStdExtZfinxBit, }, // AMFBS_HasStdExtZfinx
7579 {Feature_HasStdExtZhinxBit, }, // AMFBS_HasStdExtZhinx
7580 {Feature_HasStdExtZhinxminBit, }, // AMFBS_HasStdExtZhinxmin
7581 {Feature_HasStdExtZibiBit, }, // AMFBS_HasStdExtZibi
7582 {Feature_HasStdExtZicbomBit, }, // AMFBS_HasStdExtZicbom
7583 {Feature_HasStdExtZicbozBit, }, // AMFBS_HasStdExtZicboz
7584 {Feature_HasStdExtZicfissBit, }, // AMFBS_HasStdExtZicfiss
7585 {Feature_HasStdExtZicondBit, }, // AMFBS_HasStdExtZicond
7586 {Feature_HasStdExtZilxBit, }, // AMFBS_HasStdExtZilx
7587 {Feature_HasStdExtZimopBit, }, // AMFBS_HasStdExtZimop
7588 {Feature_HasStdExtZknhBit, }, // AMFBS_HasStdExtZknh
7589 {Feature_HasStdExtZksedBit, }, // AMFBS_HasStdExtZksed
7590 {Feature_HasStdExtZkshBit, }, // AMFBS_HasStdExtZksh
7591 {Feature_HasStdExtZmmulBit, }, // AMFBS_HasStdExtZmmul
7592 {Feature_HasStdExtZvabdBit, }, // AMFBS_HasStdExtZvabd
7593 {Feature_HasStdExtZvbbBit, }, // AMFBS_HasStdExtZvbb
7594 {Feature_HasStdExtZvbcOrZvbc32eBit, }, // AMFBS_HasStdExtZvbcOrZvbc32e
7595 {Feature_HasStdExtZvdot4a8iBit, }, // AMFBS_HasStdExtZvdot4a8i
7596 {Feature_HasStdExtZvfbdota32fBit, }, // AMFBS_HasStdExtZvfbdota32f
7597 {Feature_HasStdExtZvfbfminOrZvfofp8minBit, }, // AMFBS_HasStdExtZvfbfminOrZvfofp8min
7598 {Feature_HasStdExtZvfbfwmaBit, }, // AMFBS_HasStdExtZvfbfwma
7599 {Feature_HasStdExtZvfofp8minBit, }, // AMFBS_HasStdExtZvfofp8min
7600 {Feature_HasStdExtZvfqwbdota8fBit, }, // AMFBS_HasStdExtZvfqwbdota8f
7601 {Feature_HasStdExtZvfqwdota8fBit, }, // AMFBS_HasStdExtZvfqwdota8f
7602 {Feature_HasStdExtZvfwbdota16bfBit, }, // AMFBS_HasStdExtZvfwbdota16bf
7603 {Feature_HasStdExtZvfwdota16bfBit, }, // AMFBS_HasStdExtZvfwdota16bf
7604 {Feature_HasStdExtZvkbBit, }, // AMFBS_HasStdExtZvkb
7605 {Feature_HasStdExtZvkgBit, }, // AMFBS_HasStdExtZvkg
7606 {Feature_HasStdExtZvkgsBit, }, // AMFBS_HasStdExtZvkgs
7607 {Feature_HasStdExtZvknedBit, }, // AMFBS_HasStdExtZvkned
7608 {Feature_HasStdExtZvknhaBit, }, // AMFBS_HasStdExtZvknha
7609 {Feature_HasStdExtZvksedBit, }, // AMFBS_HasStdExtZvksed
7610 {Feature_HasStdExtZvkshBit, }, // AMFBS_HasStdExtZvksh
7611 {Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit, }, // AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i
7612 {Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit, }, // AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i
7613 {Feature_HasStdExtZvvfmmBit, }, // AMFBS_HasStdExtZvvfmm
7614 {Feature_HasStdExtZvvmmBit, }, // AMFBS_HasStdExtZvvmm
7615 {Feature_HasStdExtZvvmtlsBit, }, // AMFBS_HasStdExtZvvmtls
7616 {Feature_HasStdExtZvvmttlsBit, }, // AMFBS_HasStdExtZvvmttls
7617 {Feature_HasStdExtZvzipBit, }, // AMFBS_HasStdExtZvzip
7618 {Feature_HasVInstructionsBit, }, // AMFBS_HasVInstructions
7619 {Feature_HasVInstructionsAnyFBit, }, // AMFBS_HasVInstructionsAnyF
7620 {Feature_HasVInstructionsI64Bit, }, // AMFBS_HasVInstructionsI64
7621 {Feature_HasVendorXAndesBFHCvtBit, }, // AMFBS_HasVendorXAndesBFHCvt
7622 {Feature_HasVendorXAndesPerfBit, }, // AMFBS_HasVendorXAndesPerf
7623 {Feature_HasVendorXAndesVBFHCvtBit, }, // AMFBS_HasVendorXAndesVBFHCvt
7624 {Feature_HasVendorXAndesVDotBit, }, // AMFBS_HasVendorXAndesVDot
7625 {Feature_HasVendorXAndesVPackFPHBit, }, // AMFBS_HasVendorXAndesVPackFPH
7626 {Feature_HasVendorXAndesVSIntHBit, }, // AMFBS_HasVendorXAndesVSIntH
7627 {Feature_HasVendorXAndesVSIntLoadBit, }, // AMFBS_HasVendorXAndesVSIntLoad
7628 {Feature_HasVendorXMIPSCBOPBit, }, // AMFBS_HasVendorXMIPSCBOP
7629 {Feature_HasVendorXMIPSCMovBit, }, // AMFBS_HasVendorXMIPSCMov
7630 {Feature_HasVendorXMIPSEXECTLBit, }, // AMFBS_HasVendorXMIPSEXECTL
7631 {Feature_HasVendorXMIPSLSPBit, }, // AMFBS_HasVendorXMIPSLSP
7632 {Feature_HasVendorXSfceaseBit, }, // AMFBS_HasVendorXSfcease
7633 {Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit, }, // AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f
7634 {Feature_HasVendorXSfmm32a8fBit, }, // AMFBS_HasVendorXSfmm32a8f
7635 {Feature_HasVendorXSfmm32a8iBit, }, // AMFBS_HasVendorXSfmm32a8i
7636 {Feature_HasVendorXSfmmbaseBit, }, // AMFBS_HasVendorXSfmmbase
7637 {Feature_HasVendorXSfvcpBit, }, // AMFBS_HasVendorXSfvcp
7638 {Feature_HasVendorXSfvfexpAnyBit, }, // AMFBS_HasVendorXSfvfexpAny
7639 {Feature_HasVendorXSfvfexpaBit, }, // AMFBS_HasVendorXSfvfexpa
7640 {Feature_HasVendorXSfvfnrclipxfqfBit, }, // AMFBS_HasVendorXSfvfnrclipxfqf
7641 {Feature_HasVendorXSfvfwmaccqqqBit, }, // AMFBS_HasVendorXSfvfwmaccqqq
7642 {Feature_HasVendorXSfvqmaccdodBit, }, // AMFBS_HasVendorXSfvqmaccdod
7643 {Feature_HasVendorXSfvqmaccqoqBit, }, // AMFBS_HasVendorXSfvqmaccqoq
7644 {Feature_HasVendorXSiFivecdiscarddloneBit, }, // AMFBS_HasVendorXSiFivecdiscarddlone
7645 {Feature_HasVendorXSiFivecflushdloneBit, }, // AMFBS_HasVendorXSiFivecflushdlone
7646 {Feature_HasVendorXTHeadBaBit, }, // AMFBS_HasVendorXTHeadBa
7647 {Feature_HasVendorXTHeadBbBit, }, // AMFBS_HasVendorXTHeadBb
7648 {Feature_HasVendorXTHeadBsBit, }, // AMFBS_HasVendorXTHeadBs
7649 {Feature_HasVendorXTHeadCmoBit, }, // AMFBS_HasVendorXTHeadCmo
7650 {Feature_HasVendorXTHeadCondMovBit, }, // AMFBS_HasVendorXTHeadCondMov
7651 {Feature_HasVendorXTHeadMacBit, }, // AMFBS_HasVendorXTHeadMac
7652 {Feature_HasVendorXTHeadMemIdxBit, }, // AMFBS_HasVendorXTHeadMemIdx
7653 {Feature_HasVendorXTHeadMemPairBit, }, // AMFBS_HasVendorXTHeadMemPair
7654 {Feature_HasVendorXTHeadSyncBit, }, // AMFBS_HasVendorXTHeadSync
7655 {Feature_HasVendorXTHeadVdotBit, }, // AMFBS_HasVendorXTHeadVdot
7656 {Feature_HasVendorXqccmpBit, }, // AMFBS_HasVendorXqccmp
7657 {Feature_HasVendorXqccmtBit, }, // AMFBS_HasVendorXqccmt
7658 {Feature_HasVendorXwchcBit, }, // AMFBS_HasVendorXwchc
7659 {Feature_HasXAIFETBit, }, // AMFBS_HasXAIFET
7660 {Feature_IsRV32Bit, }, // AMFBS_IsRV32
7661 {Feature_IsRV64Bit, }, // AMFBS_IsRV64
7662 {Feature_HasStdExtDBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtD_IsRV64
7663 {Feature_HasStdExtFBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtF_IsRV64
7664 {Feature_HasStdExtMBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtM_IsRV64
7665 {Feature_HasStdExtPBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtP_IsRV32
7666 {Feature_HasStdExtPBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtP_IsRV64
7667 {Feature_HasStdExtQBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtQ_IsRV64
7668 {Feature_HasStdExtSvinvalBit, Feature_HasStdExtHBit, }, // AMFBS_HasStdExtSvinval_HasStdExtH
7669 {Feature_HasStdExtZaamoBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZaamo_IsRV64
7670 {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, }, // AMFBS_HasStdExtZabha_HasStdExtZacas
7671 {Feature_HasStdExtZacasBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZacas_IsRV32
7672 {Feature_HasStdExtZacasBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZacas_IsRV64
7673 {Feature_HasStdExtZalasrBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZalasr_IsRV64
7674 {Feature_HasStdExtZalrscBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZalrsc_IsRV64
7675 {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZba_IsRV64
7676 {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZbb_IsRV64
7677 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZbbOrZbkb_IsRV32
7678 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZbbOrZbkb_IsRV64
7679 {Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZbkb_IsRV32
7680 {Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZbkb_IsRV64
7681 {Feature_HasStdExtZcaBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZca_IsRV32
7682 {Feature_HasStdExtZcaBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZca_IsRV64
7683 {Feature_HasStdExtZcbBit, Feature_HasStdExtZbbBit, }, // AMFBS_HasStdExtZcb_HasStdExtZbb
7684 {Feature_HasStdExtZcbBit, Feature_HasStdExtZmmulBit, }, // AMFBS_HasStdExtZcb_HasStdExtZmmul
7685 {Feature_HasStdExtZcfBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZcf_IsRV32
7686 {Feature_HasStdExtZclsdBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZclsd_IsRV32
7687 {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZdinx_IsRV32
7688 {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZdinx_IsRV64
7689 {Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, }, // AMFBS_HasStdExtZfa_HasStdExtD
7690 {Feature_HasStdExtZfaBit, Feature_HasStdExtQBit, }, // AMFBS_HasStdExtZfa_HasStdExtQ
7691 {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, }, // AMFBS_HasStdExtZfa_HasStdExtZfh
7692 {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhOrZvfhBit, }, // AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh
7693 {Feature_HasStdExtZfhBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZfh_IsRV64
7694 {Feature_HasStdExtZfhminBit, Feature_HasStdExtDBit, }, // AMFBS_HasStdExtZfhmin_HasStdExtD
7695 {Feature_HasStdExtZfhminBit, Feature_HasStdExtQBit, }, // AMFBS_HasStdExtZfhmin_HasStdExtQ
7696 {Feature_HasStdExtZfinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZfinx_IsRV64
7697 {Feature_HasStdExtZhinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZhinx_IsRV64
7698 {Feature_HasStdExtZicfissBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZicfiss_IsRV64
7699 {Feature_HasStdExtZilsdBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZilsd_IsRV32
7700 {Feature_HasStdExtZilxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZilx_IsRV64
7701 {Feature_HasStdExtZkndBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZknd_IsRV32
7702 {Feature_HasStdExtZkndBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZknd_IsRV64
7703 {Feature_HasStdExtZkndOrZkneBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZkndOrZkne_IsRV64
7704 {Feature_HasStdExtZkneBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZkne_IsRV32
7705 {Feature_HasStdExtZkneBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZkne_IsRV64
7706 {Feature_HasStdExtZknhBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZknh_IsRV32
7707 {Feature_HasStdExtZknhBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZknh_IsRV64
7708 {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZmmul_IsRV64
7709 {Feature_HasVInstructionsI64Bit, Feature_IsRV64Bit, }, // AMFBS_HasVInstructionsI64_IsRV64
7710 {Feature_HasVendorXAndesPerfBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXAndesPerf_IsRV64
7711 {Feature_HasVendorXAndesVSIntHBit, Feature_HasVInstructionsAnyFBit, }, // AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF
7712 {Feature_HasVendorXCValuBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCValu_IsRV32
7713 {Feature_HasVendorXCVbiBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVbi_IsRV32
7714 {Feature_HasVendorXCVbitmanipBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVbitmanip_IsRV32
7715 {Feature_HasVendorXCVelwBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVelw_IsRV32
7716 {Feature_HasVendorXCVmacBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVmac_IsRV32
7717 {Feature_HasVendorXCVmemBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVmem_IsRV32
7718 {Feature_HasVendorXCVsimdBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVsimd_IsRV32
7719 {Feature_HasVendorXMIPSLSPBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXMIPSLSP_IsRV64
7720 {Feature_HasVendorXSMTVDotBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXSMTVDot_IsRV64
7721 {Feature_HasVendorXSMTVDotIIBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXSMTVDotII_IsRV64
7722 {Feature_HasVendorXTHeadBbBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadBb_IsRV64
7723 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD
7724 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF
7725 {Feature_HasVendorXTHeadMacBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadMac_IsRV64
7726 {Feature_HasVendorXTHeadMemIdxBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadMemIdx_IsRV64
7727 {Feature_HasVendorXTHeadMemPairBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadMemPair_IsRV64
7728 {Feature_HasVendorXqccmiBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqccmi_IsRV32
7729 {Feature_HasVendorXqciaBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcia_IsRV32
7730 {Feature_HasVendorXqciacBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqciac_IsRV32
7731 {Feature_HasVendorXqcibiBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcibi_IsRV32
7732 {Feature_HasVendorXqcibmBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcibm_IsRV32
7733 {Feature_HasVendorXqcicliBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcicli_IsRV32
7734 {Feature_HasVendorXqcicmBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcicm_IsRV32
7735 {Feature_HasVendorXqcicsBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcics_IsRV32
7736 {Feature_HasVendorXqcicsrBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcicsr_IsRV32
7737 {Feature_HasVendorXqciintBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqciint_IsRV32
7738 {Feature_HasVendorXqciioBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqciio_IsRV32
7739 {Feature_HasVendorXqcilbBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilb_IsRV32
7740 {Feature_HasVendorXqciliBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcili_IsRV32
7741 {Feature_HasVendorXqciliaBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilia_IsRV32
7742 {Feature_HasVendorXqciloBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilo_IsRV32
7743 {Feature_HasVendorXqcilsmBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilsm_IsRV32
7744 {Feature_HasVendorXqcisimBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcisim_IsRV32
7745 {Feature_HasVendorXqcislsBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcisls_IsRV32
7746 {Feature_HasVendorXqcisyncBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcisync_IsRV32
7747 {Feature_IsRV32Bit, Feature_HasStdExtZcaBit, }, // AMFBS_IsRV32_HasStdExtZca
7748 {Feature_IsRV32Bit, Feature_HasStdExtZcbBit, }, // AMFBS_IsRV32_HasStdExtZcb
7749 {Feature_IsRV64Bit, Feature_HasStdExtHBit, }, // AMFBS_IsRV64_HasStdExtH
7750 {Feature_IsRV64Bit, Feature_HasVInstructionsI64Bit, }, // AMFBS_IsRV64_HasVInstructionsI64
7751 {Feature_HasStdExtZcbBit, Feature_HasStdExtZbaBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64
7752 {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZdinx_IsRV64_IsRV64
7753 {Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZfa_HasStdExtD_IsRV32
7754 {Feature_HasStdExtZfaBit, Feature_HasStdExtQBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64
7755 {Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32
7756 {Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64
7757 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64
7758 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64
7759 {Feature_HasVendorXqciloBit, Feature_HasVendorXqciliBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32
7760};
7761
7762namespace {
7763 struct MatchEntry {
7764 uint16_t Mnemonic;
7765 uint32_t Opcode;
7766 uint16_t ConvertFn;
7767 uint8_t RequiredFeaturesIdx;
7768 uint16_t Classes[8];
7769 StringRef getMnemonic() const {
7770 return StringRef(MnemonicTable + Mnemonic + 1,
7771 MnemonicTable[Mnemonic]);
7772 }
7773 };
7774
7775 // Predicate for searching for an opcode.
7776 struct LessOpcode {
7777 bool operator()(const MatchEntry &LHS, StringRef RHS) {
7778 return LHS.getMnemonic() < RHS;
7779 }
7780 bool operator()(StringRef LHS, const MatchEntry &RHS) {
7781 return LHS < RHS.getMnemonic();
7782 }
7783 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
7784 return LHS.getMnemonic() < RHS.getMnemonic();
7785 }
7786 };
7787} // end anonymous namespace
7788
7789static const MatchEntry MatchTable0[] = {
7790 { 0 /* .insn_b */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_BareSImm13Lsb0 }, },
7791 { 8 /* .insn_ca */, RISCV::InsnCA, Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm6, MCK_UImm2, MCK_AnyRegCOperand, MCK_AnyRegCOperand }, },
7792 { 17 /* .insn_cb */, RISCV::InsnCB, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_BareSImm9Lsb0 }, },
7793 { 26 /* .insn_ci */, RISCV::InsnCI, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm6 }, },
7794 { 35 /* .insn_ciw */, RISCV::InsnCIW, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm8 }, },
7795 { 45 /* .insn_cj */, RISCV::InsnCJ, Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_BareSImm12Lsb0 }, },
7796 { 54 /* .insn_cl */, RISCV::InsnCL, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__OptionalUImm51_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_OptionalUImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7797 { 63 /* .insn_cr */, RISCV::InsnCR, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm4, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7798 { 72 /* .insn_cs */, RISCV::InsnCS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__OptionalUImm51_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_OptionalUImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7799 { 81 /* .insn_css */, RISCV::InsnCSS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_UImm6 }, },
7800 { 91 /* .insn_i */, RISCV::InsnI, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm12LO }, },
7801 { 91 /* .insn_i */, RISCV::InsnI_Mem, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__OptionalSImm12LO1_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_OptionalSImm12LO, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7802 { 99 /* .insn_j */, RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_BareSImm21Lsb0 }, },
7803 { 107 /* .insn_qc.eai */, RISCV::InsnQC_EAI, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm1, MCK_AnyRegOperand, MCK_BareSImm32 }, },
7804 { 120 /* .insn_qc.eb */, RISCV::InsnQC_EB, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm5, MCK_AnyRegOperand, MCK_SImm16, MCK_BareSImm13Lsb0 }, },
7805 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm26 }, },
7806 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI_Mem, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__OptionalSImm261_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_OptionalSImm26, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7807 { 144 /* .insn_qc.ej */, RISCV::InsnQC_EJ, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_UImm5, MCK_BareSImm32Lsb0 }, },
7808 { 156 /* .insn_qc.es */, RISCV::InsnQC_ES, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__OptionalSImm261_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_OptionalSImm26, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7809 { 168 /* .insn_r */, RISCV::InsnR, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm7, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7810 { 168 /* .insn_r */, RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7811 { 176 /* .insn_r4 */, RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7812 { 185 /* .insn_s */, RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__OptionalSImm12LO1_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_OptionalSImm12LO, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7813 { 193 /* .insn_sb */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_BareSImm13Lsb0 }, },
7814 { 202 /* .insn_u */, RISCV::InsnU, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_UImm20LUI }, },
7815 { 210 /* .insn_uj */, RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_BareSImm21Lsb0 }, },
7816 { 219 /* aadd */, RISCV::AADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7817 { 224 /* aaddu */, RISCV::AADDU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7818 { 230 /* abs */, RISCV::ABS, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
7819 { 234 /* absw */, RISCV::ABSW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
7820 { 239 /* add */, RISCV::ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7821 { 239 /* add */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7822 { 239 /* add */, RISCV::PseudoAddTPRel, Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_TPRelAddSymbol }, },
7823 { 243 /* add.uw */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7824 { 250 /* addd */, RISCV::ADDD, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
7825 { 255 /* addi */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7826 { 260 /* addiw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7827 { 266 /* addw */, RISCV::ADDW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7828 { 266 /* addw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7829 { 271 /* aes32dsi */, RISCV::AES32DSI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7830 { 280 /* aes32dsmi */, RISCV::AES32DSMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7831 { 290 /* aes32esi */, RISCV::AES32ESI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7832 { 299 /* aes32esmi */, RISCV::AES32ESMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7833 { 309 /* aes64ds */, RISCV::AES64DS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7834 { 317 /* aes64dsm */, RISCV::AES64DSM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7835 { 326 /* aes64es */, RISCV::AES64ES, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7836 { 334 /* aes64esm */, RISCV::AES64ESM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7837 { 343 /* aes64im */, RISCV::AES64IM, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR }, },
7838 { 351 /* aes64ks1i */, RISCV::AES64KS1I, Convert__Reg1_0__Reg1_1__RnumArg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_RnumArg }, },
7839 { 361 /* aes64ks2 */, RISCV::AES64KS2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7840 { 370 /* aif.amoaddg.d */, RISCV::AIF_AMOADDG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7841 { 384 /* aif.amoaddg.w */, RISCV::AIF_AMOADDG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7842 { 398 /* aif.amoaddl.d */, RISCV::AIF_AMOADDL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7843 { 412 /* aif.amoaddl.w */, RISCV::AIF_AMOADDL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7844 { 426 /* aif.amoandg.d */, RISCV::AIF_AMOANDG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7845 { 440 /* aif.amoandg.w */, RISCV::AIF_AMOANDG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7846 { 454 /* aif.amoandl.d */, RISCV::AIF_AMOANDL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7847 { 468 /* aif.amoandl.w */, RISCV::AIF_AMOANDL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7848 { 482 /* aif.amocmpswapg.d */, RISCV::AIF_AMOCMPSWAPG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7849 { 500 /* aif.amocmpswapg.w */, RISCV::AIF_AMOCMPSWAPG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7850 { 518 /* aif.amocmpswapl.d */, RISCV::AIF_AMOCMPSWAPL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7851 { 536 /* aif.amocmpswapl.w */, RISCV::AIF_AMOCMPSWAPL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7852 { 554 /* aif.amomaxg.d */, RISCV::AIF_AMOMAXG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7853 { 568 /* aif.amomaxg.w */, RISCV::AIF_AMOMAXG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7854 { 582 /* aif.amomaxl.d */, RISCV::AIF_AMOMAXL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7855 { 596 /* aif.amomaxl.w */, RISCV::AIF_AMOMAXL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7856 { 610 /* aif.amomaxug.d */, RISCV::AIF_AMOMAXUG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7857 { 625 /* aif.amomaxug.w */, RISCV::AIF_AMOMAXUG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7858 { 640 /* aif.amomaxul.d */, RISCV::AIF_AMOMAXUL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7859 { 655 /* aif.amomaxul.w */, RISCV::AIF_AMOMAXUL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7860 { 670 /* aif.amoming.d */, RISCV::AIF_AMOMING_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7861 { 684 /* aif.amoming.w */, RISCV::AIF_AMOMING_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7862 { 698 /* aif.amominl.d */, RISCV::AIF_AMOMINL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7863 { 712 /* aif.amominl.w */, RISCV::AIF_AMOMINL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7864 { 726 /* aif.amominug.d */, RISCV::AIF_AMOMINUG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7865 { 741 /* aif.amominug.w */, RISCV::AIF_AMOMINUG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7866 { 756 /* aif.amominul.d */, RISCV::AIF_AMOMINUL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7867 { 771 /* aif.amominul.w */, RISCV::AIF_AMOMINUL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7868 { 786 /* aif.amoorg.d */, RISCV::AIF_AMOORG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7869 { 799 /* aif.amoorg.w */, RISCV::AIF_AMOORG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7870 { 812 /* aif.amoorl.d */, RISCV::AIF_AMOORL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7871 { 825 /* aif.amoorl.w */, RISCV::AIF_AMOORL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7872 { 838 /* aif.amoswapg.d */, RISCV::AIF_AMOSWAPG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7873 { 853 /* aif.amoswapg.w */, RISCV::AIF_AMOSWAPG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7874 { 868 /* aif.amoswapl.d */, RISCV::AIF_AMOSWAPL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7875 { 883 /* aif.amoswapl.w */, RISCV::AIF_AMOSWAPL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7876 { 898 /* aif.amoxorg.d */, RISCV::AIF_AMOXORG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7877 { 912 /* aif.amoxorg.w */, RISCV::AIF_AMOXORG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7878 { 926 /* aif.amoxorl.d */, RISCV::AIF_AMOXORL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7879 { 940 /* aif.amoxorl.w */, RISCV::AIF_AMOXORL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7880 { 954 /* aif.bitmixb */, RISCV::AIF_BITMIXB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7881 { 966 /* aif.cubeface.ps */, RISCV::AIF_CUBEFACE_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7882 { 982 /* aif.cubefaceidx.ps */, RISCV::AIF_CUBEFACEIDX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7883 { 1001 /* aif.cubesgnsc.ps */, RISCV::AIF_CUBESGNSC_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7884 { 1018 /* aif.cubesgntc.ps */, RISCV::AIF_CUBESGNTC_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7885 { 1035 /* aif.fadd.pi */, RISCV::AIF_FADD_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7886 { 1047 /* aif.fadd.ps */, RISCV::AIF_FADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7887 { 1059 /* aif.faddi.pi */, RISCV::AIF_FADDI_PI, Convert__Reg1_0__Reg1_1__SImm101_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_SImm10 }, },
7888 { 1072 /* aif.famoaddg.pi */, RISCV::AIF_FAMOADDG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7889 { 1088 /* aif.famoaddl.pi */, RISCV::AIF_FAMOADDL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7890 { 1104 /* aif.famoandg.pi */, RISCV::AIF_FAMOANDG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7891 { 1120 /* aif.famoandl.pi */, RISCV::AIF_FAMOANDL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7892 { 1136 /* aif.famomaxg.pi */, RISCV::AIF_FAMOMAXG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7893 { 1152 /* aif.famomaxg.ps */, RISCV::AIF_FAMOMAXG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7894 { 1168 /* aif.famomaxl.pi */, RISCV::AIF_FAMOMAXL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7895 { 1184 /* aif.famomaxl.ps */, RISCV::AIF_FAMOMAXL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7896 { 1200 /* aif.famomaxug.pi */, RISCV::AIF_FAMOMAXUG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7897 { 1217 /* aif.famomaxul.pi */, RISCV::AIF_FAMOMAXUL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7898 { 1234 /* aif.famoming.pi */, RISCV::AIF_FAMOMING_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7899 { 1250 /* aif.famoming.ps */, RISCV::AIF_FAMOMING_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7900 { 1266 /* aif.famominl.pi */, RISCV::AIF_FAMOMINL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7901 { 1282 /* aif.famominl.ps */, RISCV::AIF_FAMOMINL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7902 { 1298 /* aif.famominug.pi */, RISCV::AIF_FAMOMINUG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7903 { 1315 /* aif.famominul.pi */, RISCV::AIF_FAMOMINUL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7904 { 1332 /* aif.famoorg.pi */, RISCV::AIF_FAMOORG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7905 { 1347 /* aif.famoorl.pi */, RISCV::AIF_FAMOORL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7906 { 1362 /* aif.famoswapg.pi */, RISCV::AIF_FAMOSWAPG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7907 { 1379 /* aif.famoswapl.pi */, RISCV::AIF_FAMOSWAPL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7908 { 1396 /* aif.famoxorg.pi */, RISCV::AIF_FAMOXORG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7909 { 1412 /* aif.famoxorl.pi */, RISCV::AIF_FAMOXORL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7910 { 1428 /* aif.fand.pi */, RISCV::AIF_FAND_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7911 { 1440 /* aif.fandi.pi */, RISCV::AIF_FANDI_PI, Convert__Reg1_0__Reg1_1__SImm101_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_SImm10 }, },
7912 { 1453 /* aif.fbc.ps */, RISCV::AIF_FBC_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7913 { 1464 /* aif.fbci.pi */, RISCV::AIF_FBCI_PI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_UImm20LUI }, },
7914 { 1476 /* aif.fbci.ps */, RISCV::AIF_FBCI_PS, Convert__Reg1_0__UImm20LUI1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_UImm20LUI }, },
7915 { 1488 /* aif.fbcx.ps */, RISCV::AIF_FBCX_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR }, },
7916 { 1500 /* aif.fclass.ps */, RISCV::AIF_FCLASS_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7917 { 1514 /* aif.fcmov.ps */, RISCV::AIF_FCMOV_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7918 { 1527 /* aif.fcmovm.ps */, RISCV::AIF_FCMOVM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7919 { 1541 /* aif.fcvt.f10.ps */, RISCV::AIF_FCVT_F10_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7920 { 1557 /* aif.fcvt.f11.ps */, RISCV::AIF_FCVT_F11_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7921 { 1573 /* aif.fcvt.f16.ps */, RISCV::AIF_FCVT_F16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7922 { 1589 /* aif.fcvt.ps.f10 */, RISCV::AIF_FCVT_PS_F10, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7923 { 1605 /* aif.fcvt.ps.f11 */, RISCV::AIF_FCVT_PS_F11, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7924 { 1621 /* aif.fcvt.ps.f16 */, RISCV::AIF_FCVT_PS_F16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7925 { 1637 /* aif.fcvt.ps.pw */, RISCV::AIF_FCVT_PS_PW, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7926 { 1652 /* aif.fcvt.ps.pwu */, RISCV::AIF_FCVT_PS_PWU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7927 { 1668 /* aif.fcvt.ps.rast */, RISCV::AIF_FCVT_PS_RAST, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7928 { 1685 /* aif.fcvt.ps.sn16 */, RISCV::AIF_FCVT_PS_SN16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7929 { 1702 /* aif.fcvt.ps.sn8 */, RISCV::AIF_FCVT_PS_SN8, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7930 { 1718 /* aif.fcvt.ps.un10 */, RISCV::AIF_FCVT_PS_UN10, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7931 { 1735 /* aif.fcvt.ps.un16 */, RISCV::AIF_FCVT_PS_UN16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7932 { 1752 /* aif.fcvt.ps.un2 */, RISCV::AIF_FCVT_PS_UN2, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7933 { 1768 /* aif.fcvt.ps.un24 */, RISCV::AIF_FCVT_PS_UN24, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7934 { 1785 /* aif.fcvt.ps.un8 */, RISCV::AIF_FCVT_PS_UN8, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7935 { 1801 /* aif.fcvt.pw.ps */, RISCV::AIF_FCVT_PW_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7936 { 1816 /* aif.fcvt.pwu.ps */, RISCV::AIF_FCVT_PWU_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7937 { 1832 /* aif.fcvt.rast.ps */, RISCV::AIF_FCVT_RAST_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7938 { 1849 /* aif.fcvt.sn16.ps */, RISCV::AIF_FCVT_SN16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7939 { 1866 /* aif.fcvt.sn8.ps */, RISCV::AIF_FCVT_SN8_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7940 { 1882 /* aif.fcvt.un10.ps */, RISCV::AIF_FCVT_UN10_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7941 { 1899 /* aif.fcvt.un16.ps */, RISCV::AIF_FCVT_UN16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7942 { 1916 /* aif.fcvt.un2.ps */, RISCV::AIF_FCVT_UN2_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7943 { 1932 /* aif.fcvt.un24.ps */, RISCV::AIF_FCVT_UN24_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7944 { 1949 /* aif.fcvt.un8.ps */, RISCV::AIF_FCVT_UN8_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7945 { 1965 /* aif.fdiv.pi */, RISCV::AIF_FDIV_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7946 { 1977 /* aif.fdiv.ps */, RISCV::AIF_FDIV_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7947 { 1989 /* aif.fdivu.pi */, RISCV::AIF_FDIVU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7948 { 2002 /* aif.feq.pi */, RISCV::AIF_FEQ_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7949 { 2013 /* aif.feq.ps */, RISCV::AIF_FEQ_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7950 { 2024 /* aif.feqm.ps */, RISCV::AIF_FEQM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7951 { 2036 /* aif.fexp.ps */, RISCV::AIF_FEXP_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7952 { 2048 /* aif.ffrc.ps */, RISCV::AIF_FFRC_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7953 { 2060 /* aif.fg32b.ps */, RISCV::AIF_FG32B_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7954 { 2073 /* aif.fg32h.ps */, RISCV::AIF_FG32H_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7955 { 2086 /* aif.fg32w.ps */, RISCV::AIF_FG32W_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7956 { 2099 /* aif.fgb.ps */, RISCV::AIF_FGB_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7957 { 2110 /* aif.fgbg.ps */, RISCV::AIF_FGBG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7958 { 2122 /* aif.fgbl.ps */, RISCV::AIF_FGBL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7959 { 2134 /* aif.fgh.ps */, RISCV::AIF_FGH_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7960 { 2145 /* aif.fghg.ps */, RISCV::AIF_FGHG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7961 { 2157 /* aif.fghl.ps */, RISCV::AIF_FGHL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7962 { 2169 /* aif.fgw.ps */, RISCV::AIF_FGW_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7963 { 2180 /* aif.fgwg.ps */, RISCV::AIF_FGWG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7964 { 2192 /* aif.fgwl.ps */, RISCV::AIF_FGWL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7965 { 2204 /* aif.fle.pi */, RISCV::AIF_FLE_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7966 { 2215 /* aif.fle.ps */, RISCV::AIF_FLE_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7967 { 2226 /* aif.flem.ps */, RISCV::AIF_FLEM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7968 { 2238 /* aif.flog.ps */, RISCV::AIF_FLOG_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7969 { 2250 /* aif.flq2 */, RISCV::AIF_FLQ2, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7970 { 2259 /* aif.flt.pi */, RISCV::AIF_FLT_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7971 { 2270 /* aif.flt.ps */, RISCV::AIF_FLT_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7972 { 2281 /* aif.fltm.pi */, RISCV::AIF_FLTM_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7973 { 2293 /* aif.fltm.ps */, RISCV::AIF_FLTM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7974 { 2305 /* aif.fltu.pi */, RISCV::AIF_FLTU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7975 { 2317 /* aif.flw.ps */, RISCV::AIF_FLW_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7976 { 2328 /* aif.flwg.ps */, RISCV::AIF_FLWG_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7977 { 2340 /* aif.flwl.ps */, RISCV::AIF_FLWL_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7978 { 2352 /* aif.fmadd.ps */, RISCV::AIF_FMADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7979 { 2365 /* aif.fmax.pi */, RISCV::AIF_FMAX_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7980 { 2377 /* aif.fmax.ps */, RISCV::AIF_FMAX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7981 { 2389 /* aif.fmaxu.pi */, RISCV::AIF_FMAXU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7982 { 2402 /* aif.fmin.pi */, RISCV::AIF_FMIN_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7983 { 2414 /* aif.fmin.ps */, RISCV::AIF_FMIN_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7984 { 2426 /* aif.fminu.pi */, RISCV::AIF_FMINU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7985 { 2439 /* aif.fmsub.ps */, RISCV::AIF_FMSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7986 { 2452 /* aif.fmul.pi */, RISCV::AIF_FMUL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7987 { 2464 /* aif.fmul.ps */, RISCV::AIF_FMUL_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7988 { 2476 /* aif.fmulh.pi */, RISCV::AIF_FMULH_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7989 { 2489 /* aif.fmulhu.pi */, RISCV::AIF_FMULHU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7990 { 2503 /* aif.fmvs.x.ps */, RISCV::AIF_FMVS_X_PS, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_FPR256, MCK_UImm3 }, },
7991 { 2517 /* aif.fmvz.x.ps */, RISCV::AIF_FMVZ_X_PS, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_FPR256, MCK_UImm3 }, },
7992 { 2531 /* aif.fnmadd.ps */, RISCV::AIF_FNMADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7993 { 2545 /* aif.fnmsub.ps */, RISCV::AIF_FNMSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7994 { 2559 /* aif.fnot.pi */, RISCV::AIF_FNOT_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7995 { 2571 /* aif.for.pi */, RISCV::AIF_FOR_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7996 { 2582 /* aif.fpackrepb.pi */, RISCV::AIF_FPACKREPB_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7997 { 2599 /* aif.fpackreph.pi */, RISCV::AIF_FPACKREPH_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7998 { 2616 /* aif.frcp.ps */, RISCV::AIF_FRCP_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7999 { 2628 /* aif.frcp_fix.rast */, RISCV::AIF_FRCP_FIX_RAST, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8000 { 2646 /* aif.frem.pi */, RISCV::AIF_FREM_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8001 { 2658 /* aif.fremu.pi */, RISCV::AIF_FREMU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8002 { 2671 /* aif.fround.ps */, RISCV::AIF_FROUND_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
8003 { 2685 /* aif.frsq.ps */, RISCV::AIF_FRSQ_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
8004 { 2697 /* aif.fsat8.pi */, RISCV::AIF_FSAT8_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
8005 { 2710 /* aif.fsatu8.pi */, RISCV::AIF_FSATU8_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
8006 { 2724 /* aif.fsc32b.ps */, RISCV::AIF_FSC32B_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8007 { 2738 /* aif.fsc32h.ps */, RISCV::AIF_FSC32H_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8008 { 2752 /* aif.fsc32w.ps */, RISCV::AIF_FSC32W_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8009 { 2766 /* aif.fscb.ps */, RISCV::AIF_FSCB_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
8010 { 2778 /* aif.fscbg.ps */, RISCV::AIF_FSCBG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
8011 { 2791 /* aif.fscbl.ps */, RISCV::AIF_FSCBL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
8012 { 2804 /* aif.fsch.ps */, RISCV::AIF_FSCH_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
8013 { 2816 /* aif.fschg.ps */, RISCV::AIF_FSCHG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
8014 { 2829 /* aif.fschl.ps */, RISCV::AIF_FSCHL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
8015 { 2842 /* aif.fscw.ps */, RISCV::AIF_FSCW_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
8016 { 2854 /* aif.fscwg.ps */, RISCV::AIF_FSCWG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
8017 { 2867 /* aif.fscwl.ps */, RISCV::AIF_FSCWL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
8018 { 2880 /* aif.fsetm.pi */, RISCV::AIF_FSETM_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256 }, },
8019 { 2893 /* aif.fsgnj.ps */, RISCV::AIF_FSGNJ_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8020 { 2906 /* aif.fsgnjn.ps */, RISCV::AIF_FSGNJN_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8021 { 2920 /* aif.fsgnjx.ps */, RISCV::AIF_FSGNJX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8022 { 2934 /* aif.fsin.ps */, RISCV::AIF_FSIN_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
8023 { 2946 /* aif.fsll.pi */, RISCV::AIF_FSLL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8024 { 2958 /* aif.fslli.pi */, RISCV::AIF_FSLLI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
8025 { 2971 /* aif.fsq2 */, RISCV::AIF_FSQ2, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8026 { 2980 /* aif.fsqrt.ps */, RISCV::AIF_FSQRT_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
8027 { 2993 /* aif.fsra.pi */, RISCV::AIF_FSRA_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8028 { 3005 /* aif.fsrai.pi */, RISCV::AIF_FSRAI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
8029 { 3018 /* aif.fsrl.pi */, RISCV::AIF_FSRL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8030 { 3030 /* aif.fsrli.pi */, RISCV::AIF_FSRLI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
8031 { 3043 /* aif.fsub.pi */, RISCV::AIF_FSUB_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8032 { 3055 /* aif.fsub.ps */, RISCV::AIF_FSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
8033 { 3067 /* aif.fsw.ps */, RISCV::AIF_FSW_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8034 { 3078 /* aif.fswg.ps */, RISCV::AIF_FSWG_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
8035 { 3090 /* aif.fswizz.ps */, RISCV::AIF_FSWIZZ_PS, Convert__Reg1_0__Reg1_1__UImm81_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm8 }, },
8036 { 3104 /* aif.fswl.ps */, RISCV::AIF_FSWL_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
8037 { 3116 /* aif.fxor.pi */, RISCV::AIF_FXOR_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
8038 { 3128 /* aif.maskand */, RISCV::AIF_MASKAND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
8039 { 3140 /* aif.masknot */, RISCV::AIF_MASKNOT, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_MR, MCK_MR }, },
8040 { 3152 /* aif.maskor */, RISCV::AIF_MASKOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
8041 { 3163 /* aif.maskpopc */, RISCV::AIF_MASKPOPC, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_MR }, },
8042 { 3176 /* aif.maskpopc.rast */, RISCV::AIF_MASKPOPC_ET_RAST, Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR, MCK_UImm4 }, },
8043 { 3194 /* aif.maskpopcz */, RISCV::AIF_MASKPOPCZ, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_MR }, },
8044 { 3208 /* aif.maskxor */, RISCV::AIF_MASKXOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
8045 { 3220 /* aif.mov.m.x */, RISCV::AIF_MOV_M_X, Convert__Reg1_0__Reg1_1__UImm81_2, AMFBS_HasXAIFET, { MCK_MR, MCK_GPR, MCK_UImm8 }, },
8046 { 3232 /* aif.mova.m.x */, RISCV::AIF_MOVA_M_X, Convert__Reg1_0, AMFBS_HasXAIFET, { MCK_GPR }, },
8047 { 3245 /* aif.mova.x.m */, RISCV::AIF_MOVA_X_M, Convert__Reg1_0, AMFBS_HasXAIFET, { MCK_GPR }, },
8048 { 3258 /* aif.packb */, RISCV::AIF_PACKB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8049 { 3268 /* aif.sbg */, RISCV::AIF_SBG, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8050 { 3276 /* aif.sbl */, RISCV::AIF_SBL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8051 { 3284 /* aif.shg */, RISCV::AIF_SHG, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8052 { 3292 /* aif.shl */, RISCV::AIF_SHL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8053 { 3300 /* amoadd.b */, RISCV::AMOADD_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8054 { 3309 /* amoadd.b.aq */, RISCV::AMOADD_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8055 { 3321 /* amoadd.b.aqrl */, RISCV::AMOADD_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8056 { 3335 /* amoadd.b.rl */, RISCV::AMOADD_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8057 { 3347 /* amoadd.d */, RISCV::AMOADD_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8058 { 3356 /* amoadd.d.aq */, RISCV::AMOADD_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8059 { 3368 /* amoadd.d.aqrl */, RISCV::AMOADD_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8060 { 3382 /* amoadd.d.rl */, RISCV::AMOADD_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8061 { 3394 /* amoadd.h */, RISCV::AMOADD_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8062 { 3403 /* amoadd.h.aq */, RISCV::AMOADD_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8063 { 3415 /* amoadd.h.aqrl */, RISCV::AMOADD_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8064 { 3429 /* amoadd.h.rl */, RISCV::AMOADD_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8065 { 3441 /* amoadd.w */, RISCV::AMOADD_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8066 { 3450 /* amoadd.w.aq */, RISCV::AMOADD_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8067 { 3462 /* amoadd.w.aqrl */, RISCV::AMOADD_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8068 { 3476 /* amoadd.w.rl */, RISCV::AMOADD_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8069 { 3488 /* amoand.b */, RISCV::AMOAND_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8070 { 3497 /* amoand.b.aq */, RISCV::AMOAND_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8071 { 3509 /* amoand.b.aqrl */, RISCV::AMOAND_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8072 { 3523 /* amoand.b.rl */, RISCV::AMOAND_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8073 { 3535 /* amoand.d */, RISCV::AMOAND_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8074 { 3544 /* amoand.d.aq */, RISCV::AMOAND_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8075 { 3556 /* amoand.d.aqrl */, RISCV::AMOAND_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8076 { 3570 /* amoand.d.rl */, RISCV::AMOAND_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8077 { 3582 /* amoand.h */, RISCV::AMOAND_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8078 { 3591 /* amoand.h.aq */, RISCV::AMOAND_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8079 { 3603 /* amoand.h.aqrl */, RISCV::AMOAND_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8080 { 3617 /* amoand.h.rl */, RISCV::AMOAND_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8081 { 3629 /* amoand.w */, RISCV::AMOAND_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8082 { 3638 /* amoand.w.aq */, RISCV::AMOAND_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8083 { 3650 /* amoand.w.aqrl */, RISCV::AMOAND_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8084 { 3664 /* amoand.w.rl */, RISCV::AMOAND_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8085 { 3676 /* amocas.b */, RISCV::AMOCAS_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8086 { 3685 /* amocas.b.aq */, RISCV::AMOCAS_B_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8087 { 3697 /* amocas.b.aqrl */, RISCV::AMOCAS_B_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8088 { 3711 /* amocas.b.rl */, RISCV::AMOCAS_B_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8089 { 3723 /* amocas.d */, RISCV::AMOCAS_D_RV64, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8090 { 3723 /* amocas.d */, RISCV::AMOCAS_D_RV32, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
8091 { 3732 /* amocas.d.aq */, RISCV::AMOCAS_D_RV64_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8092 { 3732 /* amocas.d.aq */, RISCV::AMOCAS_D_RV32_AQ, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
8093 { 3744 /* amocas.d.aqrl */, RISCV::AMOCAS_D_RV64_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8094 { 3744 /* amocas.d.aqrl */, RISCV::AMOCAS_D_RV32_AQRL, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
8095 { 3758 /* amocas.d.rl */, RISCV::AMOCAS_D_RV64_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8096 { 3758 /* amocas.d.rl */, RISCV::AMOCAS_D_RV32_RL, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
8097 { 3770 /* amocas.h */, RISCV::AMOCAS_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8098 { 3779 /* amocas.h.aq */, RISCV::AMOCAS_H_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8099 { 3791 /* amocas.h.aqrl */, RISCV::AMOCAS_H_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8100 { 3805 /* amocas.h.rl */, RISCV::AMOCAS_H_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8101 { 3817 /* amocas.q */, RISCV::AMOCAS_Q, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
8102 { 3826 /* amocas.q.aq */, RISCV::AMOCAS_Q_AQ, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
8103 { 3838 /* amocas.q.aqrl */, RISCV::AMOCAS_Q_AQRL, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
8104 { 3852 /* amocas.q.rl */, RISCV::AMOCAS_Q_RL, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
8105 { 3864 /* amocas.w */, RISCV::AMOCAS_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8106 { 3873 /* amocas.w.aq */, RISCV::AMOCAS_W_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8107 { 3885 /* amocas.w.aqrl */, RISCV::AMOCAS_W_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8108 { 3899 /* amocas.w.rl */, RISCV::AMOCAS_W_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8109 { 3911 /* amomax.b */, RISCV::AMOMAX_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8110 { 3920 /* amomax.b.aq */, RISCV::AMOMAX_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8111 { 3932 /* amomax.b.aqrl */, RISCV::AMOMAX_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8112 { 3946 /* amomax.b.rl */, RISCV::AMOMAX_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8113 { 3958 /* amomax.d */, RISCV::AMOMAX_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8114 { 3967 /* amomax.d.aq */, RISCV::AMOMAX_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8115 { 3979 /* amomax.d.aqrl */, RISCV::AMOMAX_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8116 { 3993 /* amomax.d.rl */, RISCV::AMOMAX_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8117 { 4005 /* amomax.h */, RISCV::AMOMAX_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8118 { 4014 /* amomax.h.aq */, RISCV::AMOMAX_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8119 { 4026 /* amomax.h.aqrl */, RISCV::AMOMAX_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8120 { 4040 /* amomax.h.rl */, RISCV::AMOMAX_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8121 { 4052 /* amomax.w */, RISCV::AMOMAX_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8122 { 4061 /* amomax.w.aq */, RISCV::AMOMAX_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8123 { 4073 /* amomax.w.aqrl */, RISCV::AMOMAX_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8124 { 4087 /* amomax.w.rl */, RISCV::AMOMAX_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8125 { 4099 /* amomaxu.b */, RISCV::AMOMAXU_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8126 { 4109 /* amomaxu.b.aq */, RISCV::AMOMAXU_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8127 { 4122 /* amomaxu.b.aqrl */, RISCV::AMOMAXU_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8128 { 4137 /* amomaxu.b.rl */, RISCV::AMOMAXU_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8129 { 4150 /* amomaxu.d */, RISCV::AMOMAXU_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8130 { 4160 /* amomaxu.d.aq */, RISCV::AMOMAXU_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8131 { 4173 /* amomaxu.d.aqrl */, RISCV::AMOMAXU_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8132 { 4188 /* amomaxu.d.rl */, RISCV::AMOMAXU_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8133 { 4201 /* amomaxu.h */, RISCV::AMOMAXU_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8134 { 4211 /* amomaxu.h.aq */, RISCV::AMOMAXU_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8135 { 4224 /* amomaxu.h.aqrl */, RISCV::AMOMAXU_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8136 { 4239 /* amomaxu.h.rl */, RISCV::AMOMAXU_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8137 { 4252 /* amomaxu.w */, RISCV::AMOMAXU_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8138 { 4262 /* amomaxu.w.aq */, RISCV::AMOMAXU_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8139 { 4275 /* amomaxu.w.aqrl */, RISCV::AMOMAXU_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8140 { 4290 /* amomaxu.w.rl */, RISCV::AMOMAXU_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8141 { 4303 /* amomin.b */, RISCV::AMOMIN_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8142 { 4312 /* amomin.b.aq */, RISCV::AMOMIN_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8143 { 4324 /* amomin.b.aqrl */, RISCV::AMOMIN_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8144 { 4338 /* amomin.b.rl */, RISCV::AMOMIN_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8145 { 4350 /* amomin.d */, RISCV::AMOMIN_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8146 { 4359 /* amomin.d.aq */, RISCV::AMOMIN_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8147 { 4371 /* amomin.d.aqrl */, RISCV::AMOMIN_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8148 { 4385 /* amomin.d.rl */, RISCV::AMOMIN_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8149 { 4397 /* amomin.h */, RISCV::AMOMIN_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8150 { 4406 /* amomin.h.aq */, RISCV::AMOMIN_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8151 { 4418 /* amomin.h.aqrl */, RISCV::AMOMIN_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8152 { 4432 /* amomin.h.rl */, RISCV::AMOMIN_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8153 { 4444 /* amomin.w */, RISCV::AMOMIN_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8154 { 4453 /* amomin.w.aq */, RISCV::AMOMIN_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8155 { 4465 /* amomin.w.aqrl */, RISCV::AMOMIN_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8156 { 4479 /* amomin.w.rl */, RISCV::AMOMIN_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8157 { 4491 /* amominu.b */, RISCV::AMOMINU_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8158 { 4501 /* amominu.b.aq */, RISCV::AMOMINU_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8159 { 4514 /* amominu.b.aqrl */, RISCV::AMOMINU_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8160 { 4529 /* amominu.b.rl */, RISCV::AMOMINU_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8161 { 4542 /* amominu.d */, RISCV::AMOMINU_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8162 { 4552 /* amominu.d.aq */, RISCV::AMOMINU_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8163 { 4565 /* amominu.d.aqrl */, RISCV::AMOMINU_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8164 { 4580 /* amominu.d.rl */, RISCV::AMOMINU_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8165 { 4593 /* amominu.h */, RISCV::AMOMINU_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8166 { 4603 /* amominu.h.aq */, RISCV::AMOMINU_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8167 { 4616 /* amominu.h.aqrl */, RISCV::AMOMINU_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8168 { 4631 /* amominu.h.rl */, RISCV::AMOMINU_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8169 { 4644 /* amominu.w */, RISCV::AMOMINU_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8170 { 4654 /* amominu.w.aq */, RISCV::AMOMINU_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8171 { 4667 /* amominu.w.aqrl */, RISCV::AMOMINU_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8172 { 4682 /* amominu.w.rl */, RISCV::AMOMINU_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8173 { 4695 /* amoor.b */, RISCV::AMOOR_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8174 { 4703 /* amoor.b.aq */, RISCV::AMOOR_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8175 { 4714 /* amoor.b.aqrl */, RISCV::AMOOR_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8176 { 4727 /* amoor.b.rl */, RISCV::AMOOR_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8177 { 4738 /* amoor.d */, RISCV::AMOOR_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8178 { 4746 /* amoor.d.aq */, RISCV::AMOOR_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8179 { 4757 /* amoor.d.aqrl */, RISCV::AMOOR_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8180 { 4770 /* amoor.d.rl */, RISCV::AMOOR_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8181 { 4781 /* amoor.h */, RISCV::AMOOR_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8182 { 4789 /* amoor.h.aq */, RISCV::AMOOR_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8183 { 4800 /* amoor.h.aqrl */, RISCV::AMOOR_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8184 { 4813 /* amoor.h.rl */, RISCV::AMOOR_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8185 { 4824 /* amoor.w */, RISCV::AMOOR_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8186 { 4832 /* amoor.w.aq */, RISCV::AMOOR_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8187 { 4843 /* amoor.w.aqrl */, RISCV::AMOOR_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8188 { 4856 /* amoor.w.rl */, RISCV::AMOOR_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8189 { 4867 /* amoswap.b */, RISCV::AMOSWAP_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8190 { 4877 /* amoswap.b.aq */, RISCV::AMOSWAP_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8191 { 4890 /* amoswap.b.aqrl */, RISCV::AMOSWAP_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8192 { 4905 /* amoswap.b.rl */, RISCV::AMOSWAP_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8193 { 4918 /* amoswap.d */, RISCV::AMOSWAP_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8194 { 4928 /* amoswap.d.aq */, RISCV::AMOSWAP_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8195 { 4941 /* amoswap.d.aqrl */, RISCV::AMOSWAP_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8196 { 4956 /* amoswap.d.rl */, RISCV::AMOSWAP_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8197 { 4969 /* amoswap.h */, RISCV::AMOSWAP_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8198 { 4979 /* amoswap.h.aq */, RISCV::AMOSWAP_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8199 { 4992 /* amoswap.h.aqrl */, RISCV::AMOSWAP_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8200 { 5007 /* amoswap.h.rl */, RISCV::AMOSWAP_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8201 { 5020 /* amoswap.w */, RISCV::AMOSWAP_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8202 { 5030 /* amoswap.w.aq */, RISCV::AMOSWAP_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8203 { 5043 /* amoswap.w.aqrl */, RISCV::AMOSWAP_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8204 { 5058 /* amoswap.w.rl */, RISCV::AMOSWAP_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8205 { 5071 /* amoxor.b */, RISCV::AMOXOR_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8206 { 5080 /* amoxor.b.aq */, RISCV::AMOXOR_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8207 { 5092 /* amoxor.b.aqrl */, RISCV::AMOXOR_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8208 { 5106 /* amoxor.b.rl */, RISCV::AMOXOR_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8209 { 5118 /* amoxor.d */, RISCV::AMOXOR_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8210 { 5127 /* amoxor.d.aq */, RISCV::AMOXOR_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8211 { 5139 /* amoxor.d.aqrl */, RISCV::AMOXOR_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8212 { 5153 /* amoxor.d.rl */, RISCV::AMOXOR_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8213 { 5165 /* amoxor.h */, RISCV::AMOXOR_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8214 { 5174 /* amoxor.h.aq */, RISCV::AMOXOR_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8215 { 5186 /* amoxor.h.aqrl */, RISCV::AMOXOR_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8216 { 5200 /* amoxor.h.rl */, RISCV::AMOXOR_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8217 { 5212 /* amoxor.w */, RISCV::AMOXOR_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8218 { 5221 /* amoxor.w.aq */, RISCV::AMOXOR_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8219 { 5233 /* amoxor.w.aqrl */, RISCV::AMOXOR_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8220 { 5247 /* amoxor.w.rl */, RISCV::AMOXOR_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8221 { 5259 /* and */, RISCV::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8222 { 5259 /* and */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
8223 { 5263 /* andi */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
8224 { 5268 /* andn */, RISCV::ANDN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8225 { 5273 /* asub */, RISCV::ASUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8226 { 5278 /* asubu */, RISCV::ASUBU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8227 { 5284 /* auipc */, RISCV::AUIPC, Convert__Reg1_0__UImm20AUIPC1_1, AMFBS_None, { MCK_GPR, MCK_UImm20AUIPC }, },
8228 { 5290 /* bclr */, RISCV::BCLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8229 { 5290 /* bclr */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
8230 { 5295 /* bclri */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
8231 { 5301 /* beq */, RISCV::BEQ, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8232 { 5305 /* beqi */, RISCV::BEQI, Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2, AMFBS_HasStdExtZibi, { MCK_GPR, MCK_Imm5Zibi, MCK_BareSImm13Lsb0 }, },
8233 { 5310 /* beqz */, RISCV::BEQ, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
8234 { 5315 /* bext */, RISCV::BEXT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8235 { 5315 /* bext */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
8236 { 5320 /* bexti */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
8237 { 5326 /* bge */, RISCV::BGE, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8238 { 5330 /* bgeu */, RISCV::BGEU, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8239 { 5335 /* bgez */, RISCV::BGE, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
8240 { 5340 /* bgt */, RISCV::BLT, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8241 { 5344 /* bgtu */, RISCV::BLTU, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8242 { 5349 /* bgtz */, RISCV::BLT, Convert__regX0__Reg1_0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
8243 { 5354 /* binv */, RISCV::BINV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8244 { 5354 /* binv */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
8245 { 5359 /* binvi */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
8246 { 5365 /* ble */, RISCV::BGE, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8247 { 5369 /* bleu */, RISCV::BGEU, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8248 { 5374 /* blez */, RISCV::BGE, Convert__regX0__Reg1_0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
8249 { 5379 /* blt */, RISCV::BLT, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8250 { 5383 /* bltu */, RISCV::BLTU, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8251 { 5388 /* bltz */, RISCV::BLT, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
8252 { 5393 /* bne */, RISCV::BNE, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
8253 { 5397 /* bnei */, RISCV::BNEI, Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2, AMFBS_HasStdExtZibi, { MCK_GPR, MCK_Imm5Zibi, MCK_BareSImm13Lsb0 }, },
8254 { 5402 /* bnez */, RISCV::BNE, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
8255 { 5407 /* brev8 */, RISCV::BREV8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR }, },
8256 { 5413 /* bset */, RISCV::BSET, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8257 { 5413 /* bset */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
8258 { 5418 /* bseti */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
8259 { 5424 /* c.add */, RISCV::C_ADD, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_GPRNoX0 }, },
8260 { 5430 /* c.addi */, RISCV::PseudoC_ADDI_NOP, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRX0, MCK_SImm6 }, },
8261 { 5430 /* c.addi */, RISCV::C_ADDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK_SImm6 }, },
8262 { 5437 /* c.addi16sp */, RISCV::C_ADDI16SP, Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, AMFBS_HasStdExtZca, { MCK_SP, MCK_SImm10Lsb0000NonZero }, },
8263 { 5448 /* c.addi4spn */, RISCV::C_ADDI4SPN, Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_SP, MCK_UImm10Lsb00NonZero }, },
8264 { 5459 /* c.addiw */, RISCV::C_ADDIW, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK_SImm6 }, },
8265 { 5467 /* c.addw */, RISCV::C_ADDW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
8266 { 5474 /* c.and */, RISCV::C_AND, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
8267 { 5480 /* c.andi */, RISCV::C_ANDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_SImm6 }, },
8268 { 5487 /* c.beqz */, RISCV::C_BEQZ, Convert__Reg1_0__BareSImm9Lsb01_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_BareSImm9Lsb0 }, },
8269 { 5494 /* c.bnez */, RISCV::C_BNEZ, Convert__Reg1_0__BareSImm9Lsb01_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_BareSImm9Lsb0 }, },
8270 { 5501 /* c.ebreak */, RISCV::C_EBREAK, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
8271 { 5510 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK_OptionalUImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
8272 { 5516 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_3__OptionalUImm9Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK_OptionalUImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
8273 { 5524 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
8274 { 5530 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK_OptionalUImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
8275 { 5538 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK_OptionalUImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
8276 { 5544 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_3__OptionalUImm9Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK_OptionalUImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
8277 { 5552 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
8278 { 5558 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK_OptionalUImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
8279 { 5566 /* c.j */, RISCV::C_J, Convert__BareSImm12Lsb01_0, AMFBS_HasStdExtZca, { MCK_BareSImm12Lsb0 }, },
8280 { 5570 /* c.jal */, RISCV::C_JAL, Convert__BareSImm12Lsb01_0, AMFBS_HasStdExtZca_IsRV32, { MCK_BareSImm12Lsb0 }, },
8281 { 5576 /* c.jalr */, RISCV::C_JALR, Convert__Reg1_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0 }, },
8282 { 5583 /* c.jr */, RISCV::C_JR, Convert__Reg1_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0 }, },
8283 { 5588 /* c.lbu */, RISCV::C_LBU, Convert__Reg1_0__Reg1_3__OptionalUImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
8284 { 5588 /* c.lbu */, RISCV::PseudoQCAccessC_LBU, Convert__Reg1_0__Reg1_3__OptionalUImm21_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
8285 { 5594 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_OptionalUImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
8286 { 5594 /* c.ld */, RISCV::C_LD_RV32, Convert__GPRPairCRV321_0__Reg1_3__OptionalUImm8Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK_OptionalUImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
8287 { 5599 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_3__OptionalUImm9Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK_OptionalUImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
8288 { 5599 /* c.ldsp */, RISCV::C_LDSP_RV32, Convert__GPRPairNoX0RV321_0__Reg1_3__OptionalUImm9Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairNoX0RV32, MCK_OptionalUImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
8289 { 5606 /* c.lh */, RISCV::C_LH, Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
8290 { 5606 /* c.lh */, RISCV::PseudoQCAccessC_LH, Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
8291 { 5611 /* c.lhu */, RISCV::C_LHU, Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
8292 { 5611 /* c.lhu */, RISCV::PseudoQCAccessC_LHU, Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
8293 { 5617 /* c.li */, RISCV::C_LI, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_SImm6 }, },
8294 { 5622 /* c.lui */, RISCV::C_LUI, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtZca, { MCK_GPRNoX2, MCK_CLUIImm }, },
8295 { 5628 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
8296 { 5628 /* c.lw */, RISCV::PseudoQCAccessC_LW, Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
8297 { 5633 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK_OptionalUImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
8298 { 5640 /* c.mop.1 */, RISCV::C_SSPUSH, Convert__regX1, AMFBS_HasStdExtZcmop, { }, },
8299 { 5648 /* c.mop.11 */, RISCV::C_MOP_11, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
8300 { 5657 /* c.mop.13 */, RISCV::C_MOP_13, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
8301 { 5666 /* c.mop.15 */, RISCV::C_MOP_15, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
8302 { 5675 /* c.mop.3 */, RISCV::C_MOP_3, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
8303 { 5683 /* c.mop.5 */, RISCV::C_SSPOPCHK, Convert__regX5, AMFBS_HasStdExtZcmop, { }, },
8304 { 5691 /* c.mop.7 */, RISCV::C_MOP_7, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
8305 { 5699 /* c.mop.9 */, RISCV::C_MOP_9, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
8306 { 5707 /* c.mul */, RISCV::C_MUL, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZcb_HasStdExtZmmul, { MCK_GPRC, MCK_GPRC }, },
8307 { 5713 /* c.mv */, RISCV::C_MV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_GPRNoX0 }, },
8308 { 5718 /* c.nop */, RISCV::C_NOP, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
8309 { 5718 /* c.nop */, RISCV::C_NOP_HINT, Convert__SImm6NonZero1_0, AMFBS_HasStdExtZca, { MCK_SImm6NonZero }, },
8310 { 5724 /* c.not */, RISCV::C_NOT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
8311 { 5730 /* c.ntl.all */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX5, AMFBS_HasStdExtZca, { }, },
8312 { 5740 /* c.ntl.p1 */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX2, AMFBS_HasStdExtZca, { }, },
8313 { 5749 /* c.ntl.pall */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX3, AMFBS_HasStdExtZca, { }, },
8314 { 5760 /* c.ntl.s1 */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX4, AMFBS_HasStdExtZca, { }, },
8315 { 5769 /* c.or */, RISCV::C_OR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
8316 { 5774 /* c.sb */, RISCV::C_SB, Convert__Reg1_0__Reg1_3__OptionalUImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
8317 { 5774 /* c.sb */, RISCV::PseudoQCAccessC_SB, Convert__Reg1_0__Reg1_3__OptionalUImm21_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
8318 { 5779 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_OptionalUImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
8319 { 5779 /* c.sd */, RISCV::C_SD_RV32, Convert__GPRPairCRV321_0__Reg1_3__OptionalUImm8Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK_OptionalUImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
8320 { 5784 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_3__OptionalUImm9Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPR, MCK_OptionalUImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
8321 { 5784 /* c.sdsp */, RISCV::C_SDSP_RV32, Convert__GPRPairRV321_0__Reg1_3__OptionalUImm9Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairRV32, MCK_OptionalUImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
8322 { 5791 /* c.sext.b */, RISCV::C_SEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
8323 { 5800 /* c.sext.h */, RISCV::C_SEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
8324 { 5809 /* c.sh */, RISCV::C_SH, Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
8325 { 5809 /* c.sh */, RISCV::PseudoQCAccessC_SH, Convert__Reg1_0__Reg1_3__OptionalUImm2Lsb01_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_OptionalUImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
8326 { 5814 /* c.slli */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_UImmLog2XLen }, },
8327 { 5821 /* c.slli64 */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPR }, },
8328 { 5830 /* c.srai */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImmLog2XLen }, },
8329 { 5837 /* c.srai64 */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC }, },
8330 { 5846 /* c.srli */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImmLog2XLen }, },
8331 { 5853 /* c.srli64 */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC }, },
8332 { 5862 /* c.sspopchk */, RISCV::C_SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZcmop, { MCK_GPRX5 }, },
8333 { 5873 /* c.sspush */, RISCV::C_SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZcmop, { MCK_GPRX1 }, },
8334 { 5882 /* c.sub */, RISCV::C_SUB, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
8335 { 5888 /* c.subw */, RISCV::C_SUBW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
8336 { 5895 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
8337 { 5895 /* c.sw */, RISCV::PseudoQCAccessC_SW, Convert__Reg1_0__Reg1_3__OptionalUImm7Lsb001_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
8338 { 5900 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_3__OptionalUImm8Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_OptionalUImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
8339 { 5907 /* c.unimp */, RISCV::C_UNIMP, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
8340 { 5915 /* c.xor */, RISCV::C_XOR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
8341 { 5921 /* c.zext.b */, RISCV::C_ZEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
8342 { 5930 /* c.zext.h */, RISCV::C_ZEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
8343 { 5939 /* c.zext.w */, RISCV::C_ZEXT_W, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64, { MCK_GPRC }, },
8344 { 5948 /* call */, RISCV::PseudoCALL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
8345 { 5948 /* call */, RISCV::PseudoCALLReg, Convert__Reg1_0__CallSymbol1_1, AMFBS_None, { MCK_GPR, MCK_CallSymbol }, },
8346 { 5953 /* cbo.clean */, RISCV::CBO_CLEAN, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
8347 { 5963 /* cbo.flush */, RISCV::CBO_FLUSH, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
8348 { 5973 /* cbo.inval */, RISCV::CBO_INVAL, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
8349 { 5983 /* cbo.zero */, RISCV::CBO_ZERO, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicboz, { MCK_ZeroOffsetMemOpOperand }, },
8350 { 5992 /* clmul */, RISCV::CLMUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8351 { 5998 /* clmulh */, RISCV::CLMULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8352 { 6005 /* clmulr */, RISCV::CLMULR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8353 { 6012 /* cls */, RISCV::CLS, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
8354 { 6016 /* clsw */, RISCV::CLSW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
8355 { 6021 /* clz */, RISCV::CLZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
8356 { 6025 /* clzw */, RISCV::CLZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
8357 { 6030 /* cm.jalt */, RISCV::CM_JALT, Convert__UImm8GE321_0, AMFBS_HasStdExtZcmt, { MCK_UImm8GE32 }, },
8358 { 6038 /* cm.jt */, RISCV::CM_JT, Convert__UImm51_0, AMFBS_HasStdExtZcmt, { MCK_UImm5 }, },
8359 { 6044 /* cm.mva01s */, RISCV::CM_MVA01S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_GPRS07, MCK_GPRS07 }, },
8360 { 6054 /* cm.mvsa01 */, RISCV::CM_MVSA01, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_GPRS07, MCK_GPRS07 }, },
8361 { 6064 /* cm.pop */, RISCV::CM_POP, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
8362 { 6071 /* cm.popret */, RISCV::CM_POPRET, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
8363 { 6081 /* cm.popretz */, RISCV::CM_POPRETZ, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
8364 { 6092 /* cm.push */, RISCV::CM_PUSH, Convert__RegList1_0__NegStackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_NegStackAdj }, },
8365 { 6100 /* cpop */, RISCV::CPOP, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
8366 { 6105 /* cpopw */, RISCV::CPOPW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
8367 { 6111 /* csrc */, RISCV::CSRRC, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
8368 { 6111 /* csrc */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8369 { 6116 /* csrci */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8370 { 6122 /* csrr */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, },
8371 { 6127 /* csrrc */, RISCV::CSRRC, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
8372 { 6127 /* csrrc */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8373 { 6133 /* csrrci */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8374 { 6140 /* csrrs */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
8375 { 6140 /* csrrs */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8376 { 6146 /* csrrsi */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8377 { 6153 /* csrrw */, RISCV::CSRRW, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
8378 { 6153 /* csrrw */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8379 { 6159 /* csrrwi */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
8380 { 6166 /* csrs */, RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
8381 { 6166 /* csrs */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8382 { 6171 /* csrsi */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8383 { 6177 /* csrw */, RISCV::CSRRW, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
8384 { 6177 /* csrw */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8385 { 6182 /* csrwi */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
8386 { 6188 /* ctz */, RISCV::CTZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
8387 { 6192 /* ctzw */, RISCV::CTZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
8388 { 6197 /* cv.abs */, RISCV::CV_ABS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8389 { 6204 /* cv.abs.b */, RISCV::CV_ABS_B, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
8390 { 6213 /* cv.abs.h */, RISCV::CV_ABS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
8391 { 6222 /* cv.add.b */, RISCV::CV_ADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8392 { 6231 /* cv.add.div2 */, RISCV::CV_ADD_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8393 { 6243 /* cv.add.div4 */, RISCV::CV_ADD_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8394 { 6255 /* cv.add.div8 */, RISCV::CV_ADD_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8395 { 6267 /* cv.add.h */, RISCV::CV_ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8396 { 6276 /* cv.add.sc.b */, RISCV::CV_ADD_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8397 { 6288 /* cv.add.sc.h */, RISCV::CV_ADD_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8398 { 6300 /* cv.add.sci.b */, RISCV::CV_ADD_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8399 { 6313 /* cv.add.sci.h */, RISCV::CV_ADD_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8400 { 6326 /* cv.addn */, RISCV::CV_ADDN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8401 { 6334 /* cv.addnr */, RISCV::CV_ADDNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8402 { 6343 /* cv.addrn */, RISCV::CV_ADDRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8403 { 6352 /* cv.addrnr */, RISCV::CV_ADDRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8404 { 6362 /* cv.addun */, RISCV::CV_ADDUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8405 { 6371 /* cv.addunr */, RISCV::CV_ADDUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8406 { 6381 /* cv.addurn */, RISCV::CV_ADDURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8407 { 6391 /* cv.addurnr */, RISCV::CV_ADDURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8408 { 6402 /* cv.and.b */, RISCV::CV_AND_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8409 { 6411 /* cv.and.h */, RISCV::CV_AND_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8410 { 6420 /* cv.and.sc.b */, RISCV::CV_AND_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8411 { 6432 /* cv.and.sc.h */, RISCV::CV_AND_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8412 { 6444 /* cv.and.sci.b */, RISCV::CV_AND_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8413 { 6457 /* cv.and.sci.h */, RISCV::CV_AND_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8414 { 6470 /* cv.avg.b */, RISCV::CV_AVG_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8415 { 6479 /* cv.avg.h */, RISCV::CV_AVG_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8416 { 6488 /* cv.avg.sc.b */, RISCV::CV_AVG_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8417 { 6500 /* cv.avg.sc.h */, RISCV::CV_AVG_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8418 { 6512 /* cv.avg.sci.b */, RISCV::CV_AVG_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8419 { 6525 /* cv.avg.sci.h */, RISCV::CV_AVG_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8420 { 6538 /* cv.avgu.b */, RISCV::CV_AVGU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8421 { 6548 /* cv.avgu.h */, RISCV::CV_AVGU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8422 { 6558 /* cv.avgu.sc.b */, RISCV::CV_AVGU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8423 { 6571 /* cv.avgu.sc.h */, RISCV::CV_AVGU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8424 { 6584 /* cv.avgu.sci.b */, RISCV::CV_AVGU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8425 { 6598 /* cv.avgu.sci.h */, RISCV::CV_AVGU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8426 { 6612 /* cv.bclr */, RISCV::CV_BCLR, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8427 { 6620 /* cv.bclrr */, RISCV::CV_BCLRR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8428 { 6629 /* cv.beqimm */, RISCV::CV_BEQIMM, Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_BareSImm13Lsb0 }, },
8429 { 6639 /* cv.bitrev */, RISCV::CV_BITREV, Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm2, MCK_UImm5 }, },
8430 { 6649 /* cv.bneimm */, RISCV::CV_BNEIMM, Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_BareSImm13Lsb0 }, },
8431 { 6659 /* cv.bset */, RISCV::CV_BSET, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8432 { 6667 /* cv.bsetr */, RISCV::CV_BSETR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8433 { 6676 /* cv.clb */, RISCV::CV_CLB, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8434 { 6683 /* cv.clip */, RISCV::CV_CLIP, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8435 { 6691 /* cv.clipr */, RISCV::CV_CLIPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8436 { 6700 /* cv.clipu */, RISCV::CV_CLIPU, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8437 { 6709 /* cv.clipur */, RISCV::CV_CLIPUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8438 { 6719 /* cv.cmpeq.b */, RISCV::CV_CMPEQ_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8439 { 6730 /* cv.cmpeq.h */, RISCV::CV_CMPEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8440 { 6741 /* cv.cmpeq.sc.b */, RISCV::CV_CMPEQ_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8441 { 6755 /* cv.cmpeq.sc.h */, RISCV::CV_CMPEQ_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8442 { 6769 /* cv.cmpeq.sci.b */, RISCV::CV_CMPEQ_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8443 { 6784 /* cv.cmpeq.sci.h */, RISCV::CV_CMPEQ_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8444 { 6799 /* cv.cmpge.b */, RISCV::CV_CMPGE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8445 { 6810 /* cv.cmpge.h */, RISCV::CV_CMPGE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8446 { 6821 /* cv.cmpge.sc.b */, RISCV::CV_CMPGE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8447 { 6835 /* cv.cmpge.sc.h */, RISCV::CV_CMPGE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8448 { 6849 /* cv.cmpge.sci.b */, RISCV::CV_CMPGE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8449 { 6864 /* cv.cmpge.sci.h */, RISCV::CV_CMPGE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8450 { 6879 /* cv.cmpgeu.b */, RISCV::CV_CMPGEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8451 { 6891 /* cv.cmpgeu.h */, RISCV::CV_CMPGEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8452 { 6903 /* cv.cmpgeu.sc.b */, RISCV::CV_CMPGEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8453 { 6918 /* cv.cmpgeu.sc.h */, RISCV::CV_CMPGEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8454 { 6933 /* cv.cmpgeu.sci.b */, RISCV::CV_CMPGEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8455 { 6949 /* cv.cmpgeu.sci.h */, RISCV::CV_CMPGEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8456 { 6965 /* cv.cmpgt.b */, RISCV::CV_CMPGT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8457 { 6976 /* cv.cmpgt.h */, RISCV::CV_CMPGT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8458 { 6987 /* cv.cmpgt.sc.b */, RISCV::CV_CMPGT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8459 { 7001 /* cv.cmpgt.sc.h */, RISCV::CV_CMPGT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8460 { 7015 /* cv.cmpgt.sci.b */, RISCV::CV_CMPGT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8461 { 7030 /* cv.cmpgt.sci.h */, RISCV::CV_CMPGT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8462 { 7045 /* cv.cmpgtu.b */, RISCV::CV_CMPGTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8463 { 7057 /* cv.cmpgtu.h */, RISCV::CV_CMPGTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8464 { 7069 /* cv.cmpgtu.sc.b */, RISCV::CV_CMPGTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8465 { 7084 /* cv.cmpgtu.sc.h */, RISCV::CV_CMPGTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8466 { 7099 /* cv.cmpgtu.sci.b */, RISCV::CV_CMPGTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8467 { 7115 /* cv.cmpgtu.sci.h */, RISCV::CV_CMPGTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8468 { 7131 /* cv.cmple.b */, RISCV::CV_CMPLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8469 { 7142 /* cv.cmple.h */, RISCV::CV_CMPLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8470 { 7153 /* cv.cmple.sc.b */, RISCV::CV_CMPLE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8471 { 7167 /* cv.cmple.sc.h */, RISCV::CV_CMPLE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8472 { 7181 /* cv.cmple.sci.b */, RISCV::CV_CMPLE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8473 { 7196 /* cv.cmple.sci.h */, RISCV::CV_CMPLE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8474 { 7211 /* cv.cmpleu.b */, RISCV::CV_CMPLEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8475 { 7223 /* cv.cmpleu.h */, RISCV::CV_CMPLEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8476 { 7235 /* cv.cmpleu.sc.b */, RISCV::CV_CMPLEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8477 { 7250 /* cv.cmpleu.sc.h */, RISCV::CV_CMPLEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8478 { 7265 /* cv.cmpleu.sci.b */, RISCV::CV_CMPLEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8479 { 7281 /* cv.cmpleu.sci.h */, RISCV::CV_CMPLEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8480 { 7297 /* cv.cmplt.b */, RISCV::CV_CMPLT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8481 { 7308 /* cv.cmplt.h */, RISCV::CV_CMPLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8482 { 7319 /* cv.cmplt.sc.b */, RISCV::CV_CMPLT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8483 { 7333 /* cv.cmplt.sc.h */, RISCV::CV_CMPLT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8484 { 7347 /* cv.cmplt.sci.b */, RISCV::CV_CMPLT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8485 { 7362 /* cv.cmplt.sci.h */, RISCV::CV_CMPLT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8486 { 7377 /* cv.cmpltu.b */, RISCV::CV_CMPLTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8487 { 7389 /* cv.cmpltu.h */, RISCV::CV_CMPLTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8488 { 7401 /* cv.cmpltu.sc.b */, RISCV::CV_CMPLTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8489 { 7416 /* cv.cmpltu.sc.h */, RISCV::CV_CMPLTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8490 { 7431 /* cv.cmpltu.sci.b */, RISCV::CV_CMPLTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8491 { 7447 /* cv.cmpltu.sci.h */, RISCV::CV_CMPLTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8492 { 7463 /* cv.cmpne.b */, RISCV::CV_CMPNE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8493 { 7474 /* cv.cmpne.h */, RISCV::CV_CMPNE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8494 { 7485 /* cv.cmpne.sc.b */, RISCV::CV_CMPNE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8495 { 7499 /* cv.cmpne.sc.h */, RISCV::CV_CMPNE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8496 { 7513 /* cv.cmpne.sci.b */, RISCV::CV_CMPNE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8497 { 7528 /* cv.cmpne.sci.h */, RISCV::CV_CMPNE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8498 { 7543 /* cv.cnt */, RISCV::CV_CNT, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8499 { 7550 /* cv.cplxconj */, RISCV::CV_CPLXCONJ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
8500 { 7562 /* cv.cplxmul.i */, RISCV::CV_CPLXMUL_I, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8501 { 7575 /* cv.cplxmul.i.div2 */, RISCV::CV_CPLXMUL_I_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8502 { 7593 /* cv.cplxmul.i.div4 */, RISCV::CV_CPLXMUL_I_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8503 { 7611 /* cv.cplxmul.i.div8 */, RISCV::CV_CPLXMUL_I_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8504 { 7629 /* cv.cplxmul.r */, RISCV::CV_CPLXMUL_R, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8505 { 7642 /* cv.cplxmul.r.div2 */, RISCV::CV_CPLXMUL_R_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8506 { 7660 /* cv.cplxmul.r.div4 */, RISCV::CV_CPLXMUL_R_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8507 { 7678 /* cv.cplxmul.r.div8 */, RISCV::CV_CPLXMUL_R_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8508 { 7696 /* cv.dotsp.b */, RISCV::CV_DOTSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8509 { 7707 /* cv.dotsp.h */, RISCV::CV_DOTSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8510 { 7718 /* cv.dotsp.sc.b */, RISCV::CV_DOTSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8511 { 7732 /* cv.dotsp.sc.h */, RISCV::CV_DOTSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8512 { 7746 /* cv.dotsp.sci.b */, RISCV::CV_DOTSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8513 { 7761 /* cv.dotsp.sci.h */, RISCV::CV_DOTSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8514 { 7776 /* cv.dotup.b */, RISCV::CV_DOTUP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8515 { 7787 /* cv.dotup.h */, RISCV::CV_DOTUP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8516 { 7798 /* cv.dotup.sc.b */, RISCV::CV_DOTUP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8517 { 7812 /* cv.dotup.sc.h */, RISCV::CV_DOTUP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8518 { 7826 /* cv.dotup.sci.b */, RISCV::CV_DOTUP_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8519 { 7841 /* cv.dotup.sci.h */, RISCV::CV_DOTUP_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8520 { 7856 /* cv.dotusp.b */, RISCV::CV_DOTUSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8521 { 7868 /* cv.dotusp.h */, RISCV::CV_DOTUSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8522 { 7880 /* cv.dotusp.sc.b */, RISCV::CV_DOTUSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8523 { 7895 /* cv.dotusp.sc.h */, RISCV::CV_DOTUSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8524 { 7910 /* cv.dotusp.sci.b */, RISCV::CV_DOTUSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8525 { 7926 /* cv.dotusp.sci.h */, RISCV::CV_DOTUSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8526 { 7942 /* cv.elw */, RISCV::PseudoCV_ELW, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXCVelw_IsRV32, { MCK_GPRNoX0, MCK_BareSymbol }, },
8527 { 7942 /* cv.elw */, RISCV::CV_ELW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasVendorXCVelw_IsRV32, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8528 { 7949 /* cv.extbs */, RISCV::CV_EXTBS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8529 { 7958 /* cv.extbz */, RISCV::CV_EXTBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8530 { 7967 /* cv.exths */, RISCV::CV_EXTHS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8531 { 7976 /* cv.exthz */, RISCV::CV_EXTHZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8532 { 7985 /* cv.extract */, RISCV::CV_EXTRACT, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8533 { 7996 /* cv.extract.b */, RISCV::CV_EXTRACT_B, Convert__Reg1_0__Reg1_1__UImm21_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm2 }, },
8534 { 8009 /* cv.extract.h */, RISCV::CV_EXTRACT_H, Convert__Reg1_0__Reg1_1__UImm11_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm1 }, },
8535 { 8022 /* cv.extractr */, RISCV::CV_EXTRACTR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8536 { 8034 /* cv.extractu */, RISCV::CV_EXTRACTU, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8537 { 8046 /* cv.extractu.b */, RISCV::CV_EXTRACTU_B, Convert__Reg1_0__Reg1_1__UImm21_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm2 }, },
8538 { 8060 /* cv.extractu.h */, RISCV::CV_EXTRACTU_H, Convert__Reg1_0__Reg1_1__UImm11_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm1 }, },
8539 { 8074 /* cv.extractur */, RISCV::CV_EXTRACTUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8540 { 8087 /* cv.ff1 */, RISCV::CV_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8541 { 8094 /* cv.fl1 */, RISCV::CV_FL1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8542 { 8101 /* cv.insert */, RISCV::CV_INSERT, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8543 { 8111 /* cv.insert.b */, RISCV::CV_INSERT_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm21_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm2 }, },
8544 { 8123 /* cv.insert.h */, RISCV::CV_INSERT_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm11_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm1 }, },
8545 { 8135 /* cv.insertr */, RISCV::CV_INSERTR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8546 { 8146 /* cv.lb */, RISCV::CV_LB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8547 { 8146 /* cv.lb */, RISCV::CV_LB_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8548 { 8146 /* cv.lb */, RISCV::CV_LB_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8549 { 8152 /* cv.lbu */, RISCV::CV_LBU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8550 { 8152 /* cv.lbu */, RISCV::CV_LBU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8551 { 8152 /* cv.lbu */, RISCV::CV_LBU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8552 { 8159 /* cv.lh */, RISCV::CV_LH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8553 { 8159 /* cv.lh */, RISCV::CV_LH_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8554 { 8159 /* cv.lh */, RISCV::CV_LH_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8555 { 8165 /* cv.lhu */, RISCV::CV_LHU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8556 { 8165 /* cv.lhu */, RISCV::CV_LHU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8557 { 8165 /* cv.lhu */, RISCV::CV_LHU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8558 { 8172 /* cv.lw */, RISCV::CV_LW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8559 { 8172 /* cv.lw */, RISCV::CV_LW_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8560 { 8172 /* cv.lw */, RISCV::CV_LW_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8561 { 8178 /* cv.mac */, RISCV::CV_MAC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8562 { 8185 /* cv.machhsn */, RISCV::CV_MACHHSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8563 { 8196 /* cv.machhsrn */, RISCV::CV_MACHHSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8564 { 8208 /* cv.machhun */, RISCV::CV_MACHHUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8565 { 8219 /* cv.machhurn */, RISCV::CV_MACHHURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8566 { 8231 /* cv.macsn */, RISCV::CV_MACSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8567 { 8240 /* cv.macsrn */, RISCV::CV_MACSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8568 { 8250 /* cv.macun */, RISCV::CV_MACUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8569 { 8259 /* cv.macurn */, RISCV::CV_MACURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8570 { 8269 /* cv.max */, RISCV::CV_MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8571 { 8276 /* cv.max.b */, RISCV::CV_MAX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8572 { 8285 /* cv.max.h */, RISCV::CV_MAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8573 { 8294 /* cv.max.sc.b */, RISCV::CV_MAX_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8574 { 8306 /* cv.max.sc.h */, RISCV::CV_MAX_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8575 { 8318 /* cv.max.sci.b */, RISCV::CV_MAX_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8576 { 8331 /* cv.max.sci.h */, RISCV::CV_MAX_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8577 { 8344 /* cv.maxu */, RISCV::CV_MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8578 { 8352 /* cv.maxu.b */, RISCV::CV_MAXU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8579 { 8362 /* cv.maxu.h */, RISCV::CV_MAXU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8580 { 8372 /* cv.maxu.sc.b */, RISCV::CV_MAXU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8581 { 8385 /* cv.maxu.sc.h */, RISCV::CV_MAXU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8582 { 8398 /* cv.maxu.sci.b */, RISCV::CV_MAXU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8583 { 8412 /* cv.maxu.sci.h */, RISCV::CV_MAXU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8584 { 8426 /* cv.min */, RISCV::CV_MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8585 { 8433 /* cv.min.b */, RISCV::CV_MIN_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8586 { 8442 /* cv.min.h */, RISCV::CV_MIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8587 { 8451 /* cv.min.sc.b */, RISCV::CV_MIN_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8588 { 8463 /* cv.min.sc.h */, RISCV::CV_MIN_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8589 { 8475 /* cv.min.sci.b */, RISCV::CV_MIN_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8590 { 8488 /* cv.min.sci.h */, RISCV::CV_MIN_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8591 { 8501 /* cv.minu */, RISCV::CV_MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8592 { 8509 /* cv.minu.b */, RISCV::CV_MINU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8593 { 8519 /* cv.minu.h */, RISCV::CV_MINU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8594 { 8529 /* cv.minu.sc.b */, RISCV::CV_MINU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8595 { 8542 /* cv.minu.sc.h */, RISCV::CV_MINU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8596 { 8555 /* cv.minu.sci.b */, RISCV::CV_MINU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8597 { 8569 /* cv.minu.sci.h */, RISCV::CV_MINU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8598 { 8583 /* cv.msu */, RISCV::CV_MSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8599 { 8590 /* cv.mulhhs */, RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8600 { 8600 /* cv.mulhhsn */, RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8601 { 8611 /* cv.mulhhsrn */, RISCV::CV_MULHHSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8602 { 8623 /* cv.mulhhu */, RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8603 { 8633 /* cv.mulhhun */, RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8604 { 8644 /* cv.mulhhurn */, RISCV::CV_MULHHURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8605 { 8656 /* cv.muls */, RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8606 { 8664 /* cv.mulsn */, RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8607 { 8673 /* cv.mulsrn */, RISCV::CV_MULSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8608 { 8683 /* cv.mulu */, RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8609 { 8691 /* cv.mulun */, RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8610 { 8700 /* cv.mulurn */, RISCV::CV_MULURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8611 { 8710 /* cv.or.b */, RISCV::CV_OR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8612 { 8718 /* cv.or.h */, RISCV::CV_OR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8613 { 8726 /* cv.or.sc.b */, RISCV::CV_OR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8614 { 8737 /* cv.or.sc.h */, RISCV::CV_OR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8615 { 8748 /* cv.or.sci.b */, RISCV::CV_OR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8616 { 8760 /* cv.or.sci.h */, RISCV::CV_OR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8617 { 8772 /* cv.pack */, RISCV::CV_PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8618 { 8780 /* cv.pack.h */, RISCV::CV_PACK_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8619 { 8790 /* cv.packhi.b */, RISCV::CV_PACKHI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8620 { 8802 /* cv.packlo.b */, RISCV::CV_PACKLO_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8621 { 8814 /* cv.ror */, RISCV::CV_ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8622 { 8821 /* cv.sb */, RISCV::CV_SB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8623 { 8821 /* cv.sb */, RISCV::CV_SB_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8624 { 8821 /* cv.sb */, RISCV::CV_SB_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8625 { 8827 /* cv.sdotsp.b */, RISCV::CV_SDOTSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8626 { 8839 /* cv.sdotsp.h */, RISCV::CV_SDOTSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8627 { 8851 /* cv.sdotsp.sc.b */, RISCV::CV_SDOTSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8628 { 8866 /* cv.sdotsp.sc.h */, RISCV::CV_SDOTSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8629 { 8881 /* cv.sdotsp.sci.b */, RISCV::CV_SDOTSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8630 { 8897 /* cv.sdotsp.sci.h */, RISCV::CV_SDOTSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8631 { 8913 /* cv.sdotup.b */, RISCV::CV_SDOTUP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8632 { 8925 /* cv.sdotup.h */, RISCV::CV_SDOTUP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8633 { 8937 /* cv.sdotup.sc.b */, RISCV::CV_SDOTUP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8634 { 8952 /* cv.sdotup.sc.h */, RISCV::CV_SDOTUP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8635 { 8967 /* cv.sdotup.sci.b */, RISCV::CV_SDOTUP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8636 { 8983 /* cv.sdotup.sci.h */, RISCV::CV_SDOTUP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8637 { 8999 /* cv.sdotusp.b */, RISCV::CV_SDOTUSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8638 { 9012 /* cv.sdotusp.h */, RISCV::CV_SDOTUSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8639 { 9025 /* cv.sdotusp.sc.b */, RISCV::CV_SDOTUSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8640 { 9041 /* cv.sdotusp.sc.h */, RISCV::CV_SDOTUSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8641 { 9057 /* cv.sdotusp.sci.b */, RISCV::CV_SDOTUSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8642 { 9074 /* cv.sdotusp.sci.h */, RISCV::CV_SDOTUSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8643 { 9091 /* cv.sh */, RISCV::CV_SH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8644 { 9091 /* cv.sh */, RISCV::CV_SH_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8645 { 9091 /* cv.sh */, RISCV::CV_SH_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8646 { 9097 /* cv.shuffle.b */, RISCV::CV_SHUFFLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8647 { 9110 /* cv.shuffle.h */, RISCV::CV_SHUFFLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8648 { 9123 /* cv.shuffle.sci.h */, RISCV::CV_SHUFFLE_SCI_H, Convert__Reg1_0__Reg1_1__UImm21_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm2 }, },
8649 { 9140 /* cv.shuffle2.b */, RISCV::CV_SHUFFLE2_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8650 { 9154 /* cv.shuffle2.h */, RISCV::CV_SHUFFLE2_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8651 { 9168 /* cv.shufflei0.sci.b */, RISCV::CV_SHUFFLEI0_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8652 { 9187 /* cv.shufflei1.sci.b */, RISCV::CV_SHUFFLEI1_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8653 { 9206 /* cv.shufflei2.sci.b */, RISCV::CV_SHUFFLEI2_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8654 { 9225 /* cv.shufflei3.sci.b */, RISCV::CV_SHUFFLEI3_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8655 { 9244 /* cv.sle */, RISCV::CV_SLE, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8656 { 9251 /* cv.sleu */, RISCV::CV_SLEU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8657 { 9259 /* cv.sll.b */, RISCV::CV_SLL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8658 { 9268 /* cv.sll.h */, RISCV::CV_SLL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8659 { 9277 /* cv.sll.sc.b */, RISCV::CV_SLL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8660 { 9289 /* cv.sll.sc.h */, RISCV::CV_SLL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8661 { 9301 /* cv.sll.sci.b */, RISCV::CV_SLL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8662 { 9314 /* cv.sll.sci.h */, RISCV::CV_SLL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8663 { 9327 /* cv.sra.b */, RISCV::CV_SRA_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8664 { 9336 /* cv.sra.h */, RISCV::CV_SRA_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8665 { 9345 /* cv.sra.sc.b */, RISCV::CV_SRA_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8666 { 9357 /* cv.sra.sc.h */, RISCV::CV_SRA_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8667 { 9369 /* cv.sra.sci.b */, RISCV::CV_SRA_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8668 { 9382 /* cv.sra.sci.h */, RISCV::CV_SRA_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8669 { 9395 /* cv.srl.b */, RISCV::CV_SRL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8670 { 9404 /* cv.srl.h */, RISCV::CV_SRL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8671 { 9413 /* cv.srl.sc.b */, RISCV::CV_SRL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8672 { 9425 /* cv.srl.sc.h */, RISCV::CV_SRL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8673 { 9437 /* cv.srl.sci.b */, RISCV::CV_SRL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8674 { 9450 /* cv.srl.sci.h */, RISCV::CV_SRL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8675 { 9463 /* cv.sub.b */, RISCV::CV_SUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8676 { 9472 /* cv.sub.div2 */, RISCV::CV_SUB_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8677 { 9484 /* cv.sub.div4 */, RISCV::CV_SUB_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8678 { 9496 /* cv.sub.div8 */, RISCV::CV_SUB_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8679 { 9508 /* cv.sub.h */, RISCV::CV_SUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8680 { 9517 /* cv.sub.sc.b */, RISCV::CV_SUB_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8681 { 9529 /* cv.sub.sc.h */, RISCV::CV_SUB_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8682 { 9541 /* cv.sub.sci.b */, RISCV::CV_SUB_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8683 { 9554 /* cv.sub.sci.h */, RISCV::CV_SUB_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8684 { 9567 /* cv.subn */, RISCV::CV_SUBN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8685 { 9575 /* cv.subnr */, RISCV::CV_SUBNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8686 { 9584 /* cv.subrn */, RISCV::CV_SUBRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8687 { 9593 /* cv.subrnr */, RISCV::CV_SUBRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8688 { 9603 /* cv.subrotmj */, RISCV::CV_SUBROTMJ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8689 { 9615 /* cv.subrotmj.div2 */, RISCV::CV_SUBROTMJ_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8690 { 9632 /* cv.subrotmj.div4 */, RISCV::CV_SUBROTMJ_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8691 { 9649 /* cv.subrotmj.div8 */, RISCV::CV_SUBROTMJ_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8692 { 9666 /* cv.subun */, RISCV::CV_SUBUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8693 { 9675 /* cv.subunr */, RISCV::CV_SUBUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8694 { 9685 /* cv.suburn */, RISCV::CV_SUBURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8695 { 9695 /* cv.suburnr */, RISCV::CV_SUBURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8696 { 9706 /* cv.sw */, RISCV::CV_SW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8697 { 9706 /* cv.sw */, RISCV::CV_SW_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8698 { 9706 /* cv.sw */, RISCV::CV_SW_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
8699 { 9712 /* cv.xor.b */, RISCV::CV_XOR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8700 { 9721 /* cv.xor.h */, RISCV::CV_XOR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8701 { 9730 /* cv.xor.sc.b */, RISCV::CV_XOR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8702 { 9742 /* cv.xor.sc.h */, RISCV::CV_XOR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8703 { 9754 /* cv.xor.sci.b */, RISCV::CV_XOR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8704 { 9767 /* cv.xor.sci.h */, RISCV::CV_XOR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8705 { 9780 /* czero.eqz */, RISCV::CZERO_EQZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8706 { 9790 /* czero.nez */, RISCV::CZERO_NEZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8707 { 9800 /* div */, RISCV::DIV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8708 { 9804 /* divu */, RISCV::DIVU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8709 { 9809 /* divuw */, RISCV::DIVUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8710 { 9815 /* divw */, RISCV::DIVW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8711 { 9820 /* dret */, RISCV::DRET, Convert_NoOperands, AMFBS_None, { }, },
8712 { 9825 /* ebreak */, RISCV::EBREAK, Convert_NoOperands, AMFBS_None, { }, },
8713 { 9832 /* ecall */, RISCV::ECALL, Convert_NoOperands, AMFBS_None, { }, },
8714 { 9838 /* fabs.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8715 { 9838 /* fabs.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8716 { 9838 /* fabs.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8717 { 9845 /* fabs.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8718 { 9845 /* fabs.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8719 { 9852 /* fabs.q */, RISCV::FSGNJX_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8720 { 9859 /* fabs.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8721 { 9859 /* fabs.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8722 { 9866 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8723 { 9866 /* fadd.d */, RISCV::FADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8724 { 9866 /* fadd.d */, RISCV::FADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8725 { 9873 /* fadd.h */, RISCV::FADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8726 { 9873 /* fadd.h */, RISCV::FADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8727 { 9880 /* fadd.q */, RISCV::FADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8728 { 9887 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8729 { 9887 /* fadd.s */, RISCV::FADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8730 { 9894 /* fclass.d */, RISCV::FCLASS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, },
8731 { 9894 /* fclass.d */, RISCV::FCLASS_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, },
8732 { 9894 /* fclass.d */, RISCV::FCLASS_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR }, },
8733 { 9903 /* fclass.h */, RISCV::FCLASS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16 }, },
8734 { 9903 /* fclass.h */, RISCV::FCLASS_H_INX, Convert__Reg1_0__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16 }, },
8735 { 9912 /* fclass.q */, RISCV::FCLASS_Q, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128 }, },
8736 { 9921 /* fclass.s */, RISCV::FCLASS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
8737 { 9921 /* fclass.s */, RISCV::FCLASS_S_INX, Convert__Reg1_0__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32 }, },
8738 { 9930 /* fcvt.bf16.s */, RISCV::FCVT_BF16_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
8739 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR64, MCK_FPR16, MCK_FRMArgLegacy }, },
8740 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8741 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8742 { 9951 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
8743 { 9951 /* fcvt.d.l */, RISCV::FCVT_D_L_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
8744 { 9960 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
8745 { 9960 /* fcvt.d.lu */, RISCV::FCVT_D_LU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
8746 { 9970 /* fcvt.d.q */, RISCV::FCVT_D_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR64, MCK_FPR128, MCK_FRMArg }, },
8747 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR32, MCK_FRMArgLegacy }, },
8748 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
8749 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
8750 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
8751 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8752 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8753 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
8754 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8755 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8756 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR16, MCK_FPR64, MCK_FRMArg }, },
8757 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D_INX, Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8758 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D_IN32X, Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR16, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8759 { 10016 /* fcvt.h.l */, RISCV::FCVT_H_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8760 { 10016 /* fcvt.h.l */, RISCV::FCVT_H_L_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8761 { 10025 /* fcvt.h.lu */, RISCV::FCVT_H_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8762 { 10025 /* fcvt.h.lu */, RISCV::FCVT_H_LU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8763 { 10035 /* fcvt.h.q */, RISCV::FCVT_H_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin_HasStdExtQ, { MCK_FPR16, MCK_FPR128, MCK_FRMArg }, },
8764 { 10044 /* fcvt.h.s */, RISCV::FCVT_H_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
8765 { 10044 /* fcvt.h.s */, RISCV::FCVT_H_S_INX, Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR16, MCK_GPRAsFPR32, MCK_FRMArg }, },
8766 { 10053 /* fcvt.h.w */, RISCV::FCVT_H_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8767 { 10053 /* fcvt.h.w */, RISCV::FCVT_H_W_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8768 { 10062 /* fcvt.h.wu */, RISCV::FCVT_H_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8769 { 10062 /* fcvt.h.wu */, RISCV::FCVT_H_WU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8770 { 10072 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8771 { 10072 /* fcvt.l.d */, RISCV::FCVT_L_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8772 { 10081 /* fcvt.l.h */, RISCV::FCVT_L_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8773 { 10081 /* fcvt.l.h */, RISCV::FCVT_L_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8774 { 10090 /* fcvt.l.q */, RISCV::FCVT_L_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8775 { 10099 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8776 { 10099 /* fcvt.l.s */, RISCV::FCVT_L_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8777 { 10108 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8778 { 10108 /* fcvt.lu.d */, RISCV::FCVT_LU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8779 { 10118 /* fcvt.lu.h */, RISCV::FCVT_LU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8780 { 10118 /* fcvt.lu.h */, RISCV::FCVT_LU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8781 { 10128 /* fcvt.lu.q */, RISCV::FCVT_LU_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8782 { 10138 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8783 { 10138 /* fcvt.lu.s */, RISCV::FCVT_LU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8784 { 10148 /* fcvt.q.d */, RISCV::FCVT_Q_D, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR64, MCK_FRMArgLegacy }, },
8785 { 10157 /* fcvt.q.h */, RISCV::FCVT_Q_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin_HasStdExtQ, { MCK_FPR128, MCK_FPR16, MCK_FRMArgLegacy }, },
8786 { 10166 /* fcvt.q.l */, RISCV::FCVT_Q_L, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8787 { 10175 /* fcvt.q.lu */, RISCV::FCVT_Q_LU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8788 { 10185 /* fcvt.q.s */, RISCV::FCVT_Q_S, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR32, MCK_FRMArgLegacy }, },
8789 { 10194 /* fcvt.q.w */, RISCV::FCVT_Q_W, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8790 { 10203 /* fcvt.q.wu */, RISCV::FCVT_Q_WU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8791 { 10213 /* fcvt.s.bf16 */, RISCV::FCVT_S_BF16, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
8792 { 10225 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64, MCK_FRMArg }, },
8793 { 10225 /* fcvt.s.d */, RISCV::FCVT_S_D_INX, Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8794 { 10225 /* fcvt.s.d */, RISCV::FCVT_S_D_IN32X, Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR32, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8795 { 10234 /* fcvt.s.h */, RISCV::FCVT_S_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
8796 { 10234 /* fcvt.s.h */, RISCV::FCVT_S_H_INX, Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR32, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8797 { 10243 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8798 { 10243 /* fcvt.s.l */, RISCV::FCVT_S_L_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8799 { 10252 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8800 { 10252 /* fcvt.s.lu */, RISCV::FCVT_S_LU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8801 { 10262 /* fcvt.s.q */, RISCV::FCVT_S_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR32, MCK_FPR128, MCK_FRMArg }, },
8802 { 10271 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8803 { 10271 /* fcvt.s.w */, RISCV::FCVT_S_W_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8804 { 10280 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8805 { 10280 /* fcvt.s.wu */, RISCV::FCVT_S_WU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8806 { 10290 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8807 { 10290 /* fcvt.w.d */, RISCV::FCVT_W_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8808 { 10290 /* fcvt.w.d */, RISCV::FCVT_W_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8809 { 10299 /* fcvt.w.h */, RISCV::FCVT_W_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8810 { 10299 /* fcvt.w.h */, RISCV::FCVT_W_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8811 { 10308 /* fcvt.w.q */, RISCV::FCVT_W_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8812 { 10317 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8813 { 10317 /* fcvt.w.s */, RISCV::FCVT_W_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8814 { 10326 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8815 { 10326 /* fcvt.wu.d */, RISCV::FCVT_WU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8816 { 10326 /* fcvt.wu.d */, RISCV::FCVT_WU_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8817 { 10336 /* fcvt.wu.h */, RISCV::FCVT_WU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8818 { 10336 /* fcvt.wu.h */, RISCV::FCVT_WU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8819 { 10346 /* fcvt.wu.q */, RISCV::FCVT_WU_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8820 { 10356 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8821 { 10356 /* fcvt.wu.s */, RISCV::FCVT_WU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8822 { 10366 /* fcvtmod.w.d */, RISCV::FCVTMOD_W_D, Convert__Reg1_0__Reg1_1__RTZArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_RTZArg }, },
8823 { 10378 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8824 { 10378 /* fdiv.d */, RISCV::FDIV_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8825 { 10378 /* fdiv.d */, RISCV::FDIV_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8826 { 10385 /* fdiv.h */, RISCV::FDIV_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8827 { 10385 /* fdiv.h */, RISCV::FDIV_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8828 { 10392 /* fdiv.q */, RISCV::FDIV_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8829 { 10399 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8830 { 10399 /* fdiv.s */, RISCV::FDIV_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8831 { 10406 /* fence */, RISCV::FENCE, Convert__imm_95_15__imm_95_15, AMFBS_None, { }, },
8832 { 10406 /* fence */, RISCV::FENCE, Convert__FenceArg1_0__FenceArg1_1, AMFBS_None, { MCK_FenceArg, MCK_FenceArg }, },
8833 { 10412 /* fence.i */, RISCV::FENCE_I, Convert_NoOperands, AMFBS_None, { }, },
8834 { 10420 /* fence.tso */, RISCV::FENCE_TSO, Convert_NoOperands, AMFBS_None, { }, },
8835 { 10430 /* feq.d */, RISCV::FEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8836 { 10430 /* feq.d */, RISCV::FEQ_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8837 { 10430 /* feq.d */, RISCV::FEQ_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8838 { 10436 /* feq.h */, RISCV::FEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8839 { 10436 /* feq.h */, RISCV::FEQ_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8840 { 10442 /* feq.q */, RISCV::FEQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8841 { 10448 /* feq.s */, RISCV::FEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8842 { 10448 /* feq.s */, RISCV::FEQ_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8843 { 10454 /* fge.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8844 { 10454 /* fge.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8845 { 10454 /* fge.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8846 { 10460 /* fge.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8847 { 10460 /* fge.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8848 { 10466 /* fge.q */, RISCV::FLE_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8849 { 10472 /* fge.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8850 { 10472 /* fge.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8851 { 10478 /* fgeq.d */, RISCV::FLEQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8852 { 10485 /* fgeq.h */, RISCV::FLEQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8853 { 10492 /* fgeq.q */, RISCV::FLEQ_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8854 { 10499 /* fgeq.s */, RISCV::FLEQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8855 { 10506 /* fgt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8856 { 10506 /* fgt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8857 { 10506 /* fgt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8858 { 10512 /* fgt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8859 { 10512 /* fgt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8860 { 10518 /* fgt.q */, RISCV::FLT_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8861 { 10524 /* fgt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8862 { 10524 /* fgt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8863 { 10530 /* fgtq.d */, RISCV::FLTQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8864 { 10537 /* fgtq.h */, RISCV::FLTQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8865 { 10544 /* fgtq.q */, RISCV::FLTQ_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8866 { 10551 /* fgtq.s */, RISCV::FLTQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8867 { 10558 /* fld */, RISCV::PseudoFLD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPRNoX0 }, },
8868 { 10558 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8869 { 10562 /* fle.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8870 { 10562 /* fle.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8871 { 10562 /* fle.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8872 { 10568 /* fle.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8873 { 10568 /* fle.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8874 { 10574 /* fle.q */, RISCV::FLE_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8875 { 10580 /* fle.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8876 { 10580 /* fle.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8877 { 10586 /* fleq.d */, RISCV::FLEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8878 { 10593 /* fleq.h */, RISCV::FLEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8879 { 10600 /* fleq.q */, RISCV::FLEQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8880 { 10607 /* fleq.s */, RISCV::FLEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8881 { 10614 /* flh */, RISCV::PseudoFLH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_BareSymbol, MCK_GPRNoX0 }, },
8882 { 10614 /* flh */, RISCV::FLH, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8883 { 10618 /* fli.d */, RISCV::FLI_D, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_LoadFPImm }, },
8884 { 10624 /* fli.h */, RISCV::FLI_H, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh, { MCK_FPR16, MCK_LoadFPImm }, },
8885 { 10630 /* fli.q */, RISCV::FLI_Q, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_LoadFPImm }, },
8886 { 10636 /* fli.s */, RISCV::FLI_S, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_LoadFPImm }, },
8887 { 10642 /* flq */, RISCV::PseudoFLQ, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_BareSymbol, MCK_GPRNoX0 }, },
8888 { 10642 /* flq */, RISCV::FLQ, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8889 { 10646 /* flt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8890 { 10646 /* flt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8891 { 10646 /* flt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8892 { 10652 /* flt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8893 { 10652 /* flt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8894 { 10658 /* flt.q */, RISCV::FLT_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8895 { 10664 /* flt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8896 { 10664 /* flt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8897 { 10670 /* fltq.d */, RISCV::FLTQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8898 { 10677 /* fltq.h */, RISCV::FLTQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8899 { 10684 /* fltq.q */, RISCV::FLTQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8900 { 10691 /* fltq.s */, RISCV::FLTQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8901 { 10698 /* flw */, RISCV::PseudoFLW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPRNoX0 }, },
8902 { 10698 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8903 { 10702 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8904 { 10702 /* fmadd.d */, RISCV::FMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8905 { 10702 /* fmadd.d */, RISCV::FMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8906 { 10710 /* fmadd.h */, RISCV::FMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8907 { 10710 /* fmadd.h */, RISCV::FMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8908 { 10718 /* fmadd.q */, RISCV::FMADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8909 { 10726 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8910 { 10726 /* fmadd.s */, RISCV::FMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8911 { 10734 /* fmax.d */, RISCV::FMAX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8912 { 10734 /* fmax.d */, RISCV::FMAX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8913 { 10734 /* fmax.d */, RISCV::FMAX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8914 { 10741 /* fmax.h */, RISCV::FMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8915 { 10741 /* fmax.h */, RISCV::FMAX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8916 { 10748 /* fmax.q */, RISCV::FMAX_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8917 { 10755 /* fmax.s */, RISCV::FMAX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8918 { 10755 /* fmax.s */, RISCV::FMAX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8919 { 10762 /* fmaxm.d */, RISCV::FMAXM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8920 { 10770 /* fmaxm.h */, RISCV::FMAXM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8921 { 10778 /* fmaxm.q */, RISCV::FMAXM_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8922 { 10786 /* fmaxm.s */, RISCV::FMAXM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8923 { 10794 /* fmin.d */, RISCV::FMIN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8924 { 10794 /* fmin.d */, RISCV::FMIN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8925 { 10794 /* fmin.d */, RISCV::FMIN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8926 { 10801 /* fmin.h */, RISCV::FMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8927 { 10801 /* fmin.h */, RISCV::FMIN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8928 { 10808 /* fmin.q */, RISCV::FMIN_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8929 { 10815 /* fmin.s */, RISCV::FMIN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8930 { 10815 /* fmin.s */, RISCV::FMIN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8931 { 10822 /* fminm.d */, RISCV::FMINM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8932 { 10830 /* fminm.h */, RISCV::FMINM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8933 { 10838 /* fminm.q */, RISCV::FMINM_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8934 { 10846 /* fminm.s */, RISCV::FMINM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8935 { 10854 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8936 { 10854 /* fmsub.d */, RISCV::FMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8937 { 10854 /* fmsub.d */, RISCV::FMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8938 { 10862 /* fmsub.h */, RISCV::FMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8939 { 10862 /* fmsub.h */, RISCV::FMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8940 { 10870 /* fmsub.q */, RISCV::FMSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8941 { 10878 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8942 { 10878 /* fmsub.s */, RISCV::FMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8943 { 10886 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8944 { 10886 /* fmul.d */, RISCV::FMUL_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8945 { 10886 /* fmul.d */, RISCV::FMUL_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8946 { 10893 /* fmul.h */, RISCV::FMUL_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8947 { 10893 /* fmul.h */, RISCV::FMUL_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8948 { 10900 /* fmul.q */, RISCV::FMUL_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8949 { 10907 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8950 { 10907 /* fmul.s */, RISCV::FMUL_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8951 { 10914 /* fmv.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8952 { 10914 /* fmv.d */, RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8953 { 10914 /* fmv.d */, RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8954 { 10920 /* fmv.d.x */, RISCV::FMV_D_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, },
8955 { 10928 /* fmv.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8956 { 10928 /* fmv.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8957 { 10934 /* fmv.h.x */, RISCV::FMV_H_X, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_GPR }, },
8958 { 10942 /* fmv.q */, RISCV::FSGNJ_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8959 { 10948 /* fmv.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8960 { 10948 /* fmv.s */, RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8961 { 10954 /* fmv.w.x */, RISCV::FMV_W_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, },
8962 { 10962 /* fmv.x.d */, RISCV::FMV_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, },
8963 { 10970 /* fmv.x.h */, RISCV::FMV_X_H, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_GPR, MCK_FPR16 }, },
8964 { 10978 /* fmv.x.w */, RISCV::FMV_X_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
8965 { 10986 /* fmvh.x.d */, RISCV::FMVH_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_GPR, MCK_FPR64 }, },
8966 { 10995 /* fmvh.x.q */, RISCV::FMVH_X_Q, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128 }, },
8967 { 11004 /* fmvp.d.x */, RISCV::FMVP_D_X, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
8968 { 11013 /* fmvp.q.x */, RISCV::FMVP_Q_X, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_GPR }, },
8969 { 11022 /* fneg.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8970 { 11022 /* fneg.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8971 { 11022 /* fneg.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8972 { 11029 /* fneg.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8973 { 11029 /* fneg.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8974 { 11036 /* fneg.q */, RISCV::FSGNJN_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8975 { 11043 /* fneg.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8976 { 11043 /* fneg.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8977 { 11050 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8978 { 11050 /* fnmadd.d */, RISCV::FNMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8979 { 11050 /* fnmadd.d */, RISCV::FNMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8980 { 11059 /* fnmadd.h */, RISCV::FNMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8981 { 11059 /* fnmadd.h */, RISCV::FNMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8982 { 11068 /* fnmadd.q */, RISCV::FNMADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8983 { 11077 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8984 { 11077 /* fnmadd.s */, RISCV::FNMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8985 { 11086 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8986 { 11086 /* fnmsub.d */, RISCV::FNMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8987 { 11086 /* fnmsub.d */, RISCV::FNMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8988 { 11095 /* fnmsub.h */, RISCV::FNMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8989 { 11095 /* fnmsub.h */, RISCV::FNMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8990 { 11104 /* fnmsub.q */, RISCV::FNMSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8991 { 11113 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8992 { 11113 /* fnmsub.s */, RISCV::FNMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8993 { 11122 /* frcsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8994 { 11128 /* frflags */, RISCV::CSRRS, Convert__Reg1_0__imm_95_1__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8995 { 11136 /* fround.d */, RISCV::FROUND_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8996 { 11145 /* fround.h */, RISCV::FROUND_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8997 { 11154 /* fround.q */, RISCV::FROUND_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8998 { 11163 /* fround.s */, RISCV::FROUND_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8999 { 11172 /* froundnx.d */, RISCV::FROUNDNX_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
9000 { 11183 /* froundnx.h */, RISCV::FROUNDNX_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
9001 { 11194 /* froundnx.q */, RISCV::FROUNDNX_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
9002 { 11205 /* froundnx.s */, RISCV::FROUNDNX_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
9003 { 11216 /* frrm */, RISCV::CSRRS, Convert__Reg1_0__imm_95_2__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
9004 { 11221 /* fscsr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
9005 { 11221 /* fscsr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
9006 { 11227 /* fsd */, RISCV::PseudoFSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPRNoX0 }, },
9007 { 11227 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9008 { 11231 /* fsflags */, RISCV::CSRRW, Convert__regX0__imm_95_1__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
9009 { 11231 /* fsflags */, RISCV::CSRRW, Convert__Reg1_0__imm_95_1__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
9010 { 11239 /* fsflagsi */, RISCV::CSRRWI, Convert__regX0__imm_95_1__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
9011 { 11239 /* fsflagsi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_1__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
9012 { 11248 /* fsgnj.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
9013 { 11248 /* fsgnj.d */, RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
9014 { 11248 /* fsgnj.d */, RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
9015 { 11256 /* fsgnj.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
9016 { 11256 /* fsgnj.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
9017 { 11264 /* fsgnj.q */, RISCV::FSGNJ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
9018 { 11272 /* fsgnj.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
9019 { 11272 /* fsgnj.s */, RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
9020 { 11280 /* fsgnjn.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
9021 { 11280 /* fsgnjn.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
9022 { 11280 /* fsgnjn.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
9023 { 11289 /* fsgnjn.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
9024 { 11289 /* fsgnjn.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
9025 { 11298 /* fsgnjn.q */, RISCV::FSGNJN_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
9026 { 11307 /* fsgnjn.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
9027 { 11307 /* fsgnjn.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
9028 { 11316 /* fsgnjx.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
9029 { 11316 /* fsgnjx.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
9030 { 11316 /* fsgnjx.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
9031 { 11325 /* fsgnjx.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
9032 { 11325 /* fsgnjx.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
9033 { 11334 /* fsgnjx.q */, RISCV::FSGNJX_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
9034 { 11343 /* fsgnjx.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
9035 { 11343 /* fsgnjx.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
9036 { 11352 /* fsh */, RISCV::PseudoFSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_BareSymbol, MCK_GPRNoX0 }, },
9037 { 11352 /* fsh */, RISCV::FSH, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9038 { 11356 /* fsq */, RISCV::PseudoFSQ, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_BareSymbol, MCK_GPRNoX0 }, },
9039 { 11356 /* fsq */, RISCV::FSQ, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9040 { 11360 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
9041 { 11360 /* fsqrt.d */, RISCV::FSQRT_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
9042 { 11360 /* fsqrt.d */, RISCV::FSQRT_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
9043 { 11368 /* fsqrt.h */, RISCV::FSQRT_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
9044 { 11368 /* fsqrt.h */, RISCV::FSQRT_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
9045 { 11376 /* fsqrt.q */, RISCV::FSQRT_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
9046 { 11384 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
9047 { 11384 /* fsqrt.s */, RISCV::FSQRT_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
9048 { 11392 /* fsrm */, RISCV::CSRRW, Convert__regX0__imm_95_2__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
9049 { 11392 /* fsrm */, RISCV::CSRRW, Convert__Reg1_0__imm_95_2__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
9050 { 11397 /* fsrmi */, RISCV::CSRRWI, Convert__regX0__imm_95_2__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
9051 { 11397 /* fsrmi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_2__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
9052 { 11403 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
9053 { 11403 /* fsub.d */, RISCV::FSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
9054 { 11403 /* fsub.d */, RISCV::FSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
9055 { 11410 /* fsub.h */, RISCV::FSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
9056 { 11410 /* fsub.h */, RISCV::FSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
9057 { 11417 /* fsub.q */, RISCV::FSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
9058 { 11424 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
9059 { 11424 /* fsub.s */, RISCV::FSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
9060 { 11431 /* fsw */, RISCV::PseudoFSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPRNoX0 }, },
9061 { 11431 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9062 { 11435 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__regX0__regX0, AMFBS_HasStdExtH, { }, },
9063 { 11435 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__regX0, AMFBS_HasStdExtH, { MCK_GPR }, },
9064 { 11435 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
9065 { 11447 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__regX0__regX0, AMFBS_HasStdExtH, { }, },
9066 { 11447 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__regX0, AMFBS_HasStdExtH, { MCK_GPR }, },
9067 { 11447 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
9068 { 11459 /* hinval.gvma */, RISCV::HINVAL_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval_HasStdExtH, { MCK_GPR, MCK_GPR }, },
9069 { 11471 /* hinval.vvma */, RISCV::HINVAL_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval_HasStdExtH, { MCK_GPR, MCK_GPR }, },
9070 { 11483 /* hlv.b */, RISCV::HLV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9071 { 11489 /* hlv.bu */, RISCV::HLV_BU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9072 { 11496 /* hlv.d */, RISCV::HLV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9073 { 11502 /* hlv.h */, RISCV::HLV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9074 { 11508 /* hlv.hu */, RISCV::HLV_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9075 { 11515 /* hlv.w */, RISCV::HLV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9076 { 11521 /* hlv.wu */, RISCV::HLV_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9077 { 11528 /* hlvx.hu */, RISCV::HLVX_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9078 { 11536 /* hlvx.wu */, RISCV::HLVX_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9079 { 11544 /* hsv.b */, RISCV::HSV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9080 { 11550 /* hsv.d */, RISCV::HSV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9081 { 11556 /* hsv.h */, RISCV::HSV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9082 { 11562 /* hsv.w */, RISCV::HSV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9083 { 11568 /* j */, RISCV::JAL, Convert__regX0__BareSImm21Lsb01_0, AMFBS_None, { MCK_BareSImm21Lsb0 }, },
9084 { 11570 /* jal */, RISCV::JAL, Convert__regX1__BareSImm21Lsb01_0, AMFBS_None, { MCK_BareSImm21Lsb0 }, },
9085 { 11570 /* jal */, RISCV::JAL, Convert__Reg1_0__BareSImm21Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm21Lsb0 }, },
9086 { 11574 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
9087 { 11574 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9088 { 11574 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
9089 { 11574 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9090 { 11574 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_2__OptionalSImm12LO1_0, AMFBS_None, { MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9091 { 11574 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9092 { 11574 /* jalr */, RISCV::PseudoTLSDESCCall, Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_, MCK_TLSDESCCallSymbol }, },
9093 { 11579 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
9094 { 11579 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
9095 { 11579 /* jr */, RISCV::JALR, Convert__regX0__Reg1_2__OptionalSImm12LO1_0, AMFBS_None, { MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9096 { 11582 /* jump */, RISCV::PseudoJump, Convert__Reg1_1__PseudoJumpSymbol1_0, AMFBS_None, { MCK_PseudoJumpSymbol, MCK_GPR }, },
9097 { 11587 /* la */, RISCV::PseudoLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
9098 { 11587 /* la */, RISCV::PseudoLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
9099 { 11590 /* la.tls.gd */, RISCV::PseudoLA_TLS_GD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
9100 { 11600 /* la.tls.ie */, RISCV::PseudoLA_TLS_IE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
9101 { 11610 /* lb */, RISCV::PseudoLB, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPRNoX0, MCK_BareSymbol }, },
9102 { 11610 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9103 { 11610 /* lb */, RISCV::PseudoQCAccessLB, Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_OptionalSImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9104 { 11613 /* lb.aq */, RISCV::LB_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9105 { 11619 /* lb.aqrl */, RISCV::LB_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9106 { 11627 /* lbu */, RISCV::PseudoLBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPRNoX0, MCK_BareSymbol }, },
9107 { 11627 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9108 { 11627 /* lbu */, RISCV::PseudoQCAccessLBU, Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_OptionalSImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9109 { 11631 /* ld */, RISCV::PseudoLD, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPRNoX0, MCK_BareSymbol }, },
9110 { 11631 /* ld */, RISCV::PseudoLD_RV32, Convert__GPRPairNoX0RV321_0__BareSymbol1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairNoX0RV32, MCK_BareSymbol }, },
9111 { 11631 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9112 { 11631 /* ld */, RISCV::LD_RV32, Convert__GPRPairRV321_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9113 { 11634 /* ld.aq */, RISCV::LD_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9114 { 11640 /* ld.aqrl */, RISCV::LD_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9115 { 11648 /* lga */, RISCV::PseudoLGA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
9116 { 11652 /* lh */, RISCV::PseudoLH, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPRNoX0, MCK_BareSymbol }, },
9117 { 11652 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9118 { 11652 /* lh */, RISCV::PseudoQCAccessLH, Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_OptionalSImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9119 { 11655 /* lh.aq */, RISCV::LH_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9120 { 11661 /* lh.aqrl */, RISCV::LH_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9121 { 11669 /* lhu */, RISCV::PseudoLHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPRNoX0, MCK_BareSymbol }, },
9122 { 11669 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9123 { 11669 /* lhu */, RISCV::PseudoQCAccessLHU, Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_OptionalSImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9124 { 11673 /* li */, RISCV::ADDI, Convert__Reg1_0__regX0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
9125 { 11673 /* li */, RISCV::PseudoLI, Convert__Reg1_0__ImmXLenLI1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI }, },
9126 { 11676 /* lla */, RISCV::PseudoLLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
9127 { 11676 /* lla */, RISCV::PseudoLLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
9128 { 11680 /* lpad */, RISCV::AUIPC, Convert__regX0__UImm201_0, AMFBS_None, { MCK_UImm20 }, },
9129 { 11685 /* lr.d */, RISCV::LR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9130 { 11690 /* lr.d.aq */, RISCV::LR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9131 { 11698 /* lr.d.aqrl */, RISCV::LR_D_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9132 { 11708 /* lr.d.rl */, RISCV::LR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9133 { 11716 /* lr.w */, RISCV::LR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9134 { 11721 /* lr.w.aq */, RISCV::LR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9135 { 11729 /* lr.w.aqrl */, RISCV::LR_W_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9136 { 11739 /* lr.w.rl */, RISCV::LR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9137 { 11747 /* lui */, RISCV::LUI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_None, { MCK_GPR, MCK_UImm20LUI }, },
9138 { 11751 /* lw */, RISCV::PseudoLW, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPRNoX0, MCK_BareSymbol }, },
9139 { 11751 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9140 { 11751 /* lw */, RISCV::PseudoQCAccessLW, Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_OptionalSImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9141 { 11754 /* lw.aq */, RISCV::LW_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9142 { 11760 /* lw.aqrl */, RISCV::LW_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9143 { 11768 /* lwu */, RISCV::PseudoLWU, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPRNoX0, MCK_BareSymbol }, },
9144 { 11768 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9145 { 11772 /* lxb */, RISCV::LXSB, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9146 { 11776 /* lxbu */, RISCV::LXSBU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9147 { 11781 /* lxd */, RISCV::LXD, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9148 { 11785 /* lxh */, RISCV::LXH, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9149 { 11789 /* lxhu */, RISCV::LXHU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9150 { 11794 /* lxsb */, RISCV::LXSB, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9151 { 11799 /* lxsbu */, RISCV::LXSBU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9152 { 11805 /* lxsd */, RISCV::LXSD, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9153 { 11810 /* lxsh */, RISCV::LXSH, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9154 { 11815 /* lxshu */, RISCV::LXSHU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9155 { 11821 /* lxsuwb */, RISCV::LXSUWB, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9156 { 11828 /* lxsuwbu */, RISCV::LXSUWBU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9157 { 11836 /* lxsuwd */, RISCV::LXSUWD, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9158 { 11843 /* lxsuwh */, RISCV::LXSUWH, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9159 { 11850 /* lxsuwhu */, RISCV::LXSUWHU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9160 { 11858 /* lxsuww */, RISCV::LXSUWW, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9161 { 11865 /* lxsuwwu */, RISCV::LXSUWWU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9162 { 11873 /* lxsw */, RISCV::LXSW, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9163 { 11878 /* lxswu */, RISCV::LXSWU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9164 { 11884 /* lxw */, RISCV::LXW, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9165 { 11888 /* lxwu */, RISCV::LXWU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2, AMFBS_HasStdExtZilx_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand, MCK_GPR }, },
9166 { 11893 /* macc.h00 */, RISCV::MACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9167 { 11902 /* macc.h01 */, RISCV::MACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9168 { 11911 /* macc.h11 */, RISCV::MACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9169 { 11920 /* macc.w00 */, RISCV::MACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9170 { 11929 /* macc.w01 */, RISCV::MACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9171 { 11938 /* macc.w11 */, RISCV::MACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9172 { 11947 /* maccsu.h00 */, RISCV::MACCSU_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9173 { 11958 /* maccsu.h11 */, RISCV::MACCSU_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9174 { 11969 /* maccsu.w00 */, RISCV::MACCSU_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9175 { 11980 /* maccsu.w11 */, RISCV::MACCSU_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9176 { 11991 /* maccu.h00 */, RISCV::MACCU_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9177 { 12001 /* maccu.h01 */, RISCV::MACCU_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9178 { 12011 /* maccu.h11 */, RISCV::MACCU_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9179 { 12021 /* maccu.w00 */, RISCV::MACCU_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9180 { 12031 /* maccu.w01 */, RISCV::MACCU_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9181 { 12041 /* maccu.w11 */, RISCV::MACCU_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9182 { 12051 /* max */, RISCV::MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9183 { 12055 /* maxu */, RISCV::MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9184 { 12060 /* mcspspop */, RISCV::MCSPSPOP, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSmcsps, { MCK_SP, MCK_SP }, },
9185 { 12069 /* mcspspush */, RISCV::MCSPSPUSH, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSmcsps, { MCK_SP, MCK_SP }, },
9186 { 12079 /* merge */, RISCV::MERGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9187 { 12085 /* mhacc */, RISCV::MHACC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9188 { 12091 /* mhacc.h0 */, RISCV::MHACC_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9189 { 12100 /* mhacc.h1 */, RISCV::MHACC_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9190 { 12109 /* mhaccsu */, RISCV::MHACCSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9191 { 12117 /* mhaccsu.h0 */, RISCV::MHACCSU_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9192 { 12128 /* mhaccsu.h1 */, RISCV::MHACCSU_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9193 { 12139 /* mhaccu */, RISCV::MHACCU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9194 { 12146 /* mhracc */, RISCV::MHRACC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9195 { 12153 /* mhraccsu */, RISCV::MHRACCSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9196 { 12162 /* mhraccu */, RISCV::MHRACCU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9197 { 12170 /* min */, RISCV::MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9198 { 12174 /* minu */, RISCV::MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9199 { 12179 /* mipopret */, RISCV::MIPOPRET, Convert_NoOperands, AMFBS_HasStdExtSmip, { }, },
9200 { 12188 /* mips.ccmov */, RISCV::MIPS_CCMOV, Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3, AMFBS_HasVendorXMIPSCMov, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
9201 { 12199 /* mips.ehb */, RISCV::MIPS_EHB, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
9202 { 12208 /* mips.ihb */, RISCV::MIPS_IHB, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
9203 { 12217 /* mips.ldp */, RISCV::MIPS_LDP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2, AMFBS_HasVendorXMIPSLSP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb000, MCK__40_, MCK_GPR, MCK__41_ }, },
9204 { 12226 /* mips.lwp */, RISCV::MIPS_LWP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9205 { 12235 /* mips.pause */, RISCV::MIPS_PAUSE, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
9206 { 12246 /* mips.pref */, RISCV::MIPS_PREF, Convert__Reg1_3__UImm91_1__UImm51_0, AMFBS_HasVendorXMIPSCBOP, { MCK_UImm5, MCK_UImm9, MCK__40_, MCK_GPR, MCK__41_ }, },
9207 { 12256 /* mips.sdp */, RISCV::MIPS_SDP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2, AMFBS_HasVendorXMIPSLSP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb000, MCK__40_, MCK_GPR, MCK__41_ }, },
9208 { 12265 /* mips.swp */, RISCV::MIPS_SWP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9209 { 12274 /* mnret */, RISCV::MNRET, Convert_NoOperands, AMFBS_HasStdExtSmrnmi, { }, },
9210 { 12280 /* mop.r.0 */, RISCV::MOP_R_0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9211 { 12288 /* mop.r.1 */, RISCV::MOP_R_1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9212 { 12296 /* mop.r.10 */, RISCV::MOP_R_10, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9213 { 12305 /* mop.r.11 */, RISCV::MOP_R_11, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9214 { 12314 /* mop.r.12 */, RISCV::MOP_R_12, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9215 { 12323 /* mop.r.13 */, RISCV::MOP_R_13, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9216 { 12332 /* mop.r.14 */, RISCV::MOP_R_14, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9217 { 12341 /* mop.r.15 */, RISCV::MOP_R_15, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9218 { 12350 /* mop.r.16 */, RISCV::MOP_R_16, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9219 { 12359 /* mop.r.17 */, RISCV::MOP_R_17, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9220 { 12368 /* mop.r.18 */, RISCV::MOP_R_18, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9221 { 12377 /* mop.r.19 */, RISCV::MOP_R_19, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9222 { 12386 /* mop.r.2 */, RISCV::MOP_R_2, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9223 { 12394 /* mop.r.20 */, RISCV::MOP_R_20, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9224 { 12403 /* mop.r.21 */, RISCV::MOP_R_21, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9225 { 12412 /* mop.r.22 */, RISCV::MOP_R_22, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9226 { 12421 /* mop.r.23 */, RISCV::MOP_R_23, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9227 { 12430 /* mop.r.24 */, RISCV::MOP_R_24, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9228 { 12439 /* mop.r.25 */, RISCV::MOP_R_25, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9229 { 12448 /* mop.r.26 */, RISCV::MOP_R_26, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9230 { 12457 /* mop.r.27 */, RISCV::MOP_R_27, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9231 { 12466 /* mop.r.28 */, RISCV::MOP_R_28, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9232 { 12475 /* mop.r.29 */, RISCV::MOP_R_29, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9233 { 12484 /* mop.r.3 */, RISCV::MOP_R_3, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9234 { 12492 /* mop.r.30 */, RISCV::MOP_R_30, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9235 { 12501 /* mop.r.31 */, RISCV::MOP_R_31, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9236 { 12510 /* mop.r.4 */, RISCV::MOP_R_4, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9237 { 12518 /* mop.r.5 */, RISCV::MOP_R_5, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9238 { 12526 /* mop.r.6 */, RISCV::MOP_R_6, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9239 { 12534 /* mop.r.7 */, RISCV::MOP_R_7, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9240 { 12542 /* mop.r.8 */, RISCV::MOP_R_8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9241 { 12550 /* mop.r.9 */, RISCV::MOP_R_9, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
9242 { 12558 /* mop.rr.0 */, RISCV::MOP_RR_0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9243 { 12567 /* mop.rr.1 */, RISCV::MOP_RR_1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9244 { 12576 /* mop.rr.2 */, RISCV::MOP_RR_2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9245 { 12585 /* mop.rr.3 */, RISCV::MOP_RR_3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9246 { 12594 /* mop.rr.4 */, RISCV::MOP_RR_4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9247 { 12603 /* mop.rr.5 */, RISCV::MOP_RR_5, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9248 { 12612 /* mop.rr.6 */, RISCV::MOP_RR_6, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9249 { 12621 /* mop.rr.7 */, RISCV::MOP_RR_7, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9250 { 12630 /* mqacc.h00 */, RISCV::MQACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9251 { 12640 /* mqacc.h01 */, RISCV::MQACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9252 { 12650 /* mqacc.h11 */, RISCV::MQACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9253 { 12660 /* mqacc.w00 */, RISCV::MQACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9254 { 12670 /* mqacc.w01 */, RISCV::MQACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9255 { 12680 /* mqacc.w11 */, RISCV::MQACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9256 { 12690 /* mqracc.h00 */, RISCV::MQRACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9257 { 12701 /* mqracc.h01 */, RISCV::MQRACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9258 { 12712 /* mqracc.h11 */, RISCV::MQRACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9259 { 12723 /* mqracc.w00 */, RISCV::MQRACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9260 { 12734 /* mqracc.w01 */, RISCV::MQRACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9261 { 12745 /* mqracc.w11 */, RISCV::MQRACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9262 { 12756 /* mqrwacc */, RISCV::MQRWACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9263 { 12764 /* mqwacc */, RISCV::MQWACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9264 { 12771 /* mret */, RISCV::MRET, Convert_NoOperands, AMFBS_None, { }, },
9265 { 12776 /* mseq */, RISCV::MSEQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9266 { 12781 /* mseqz */, RISCV::MSEQ, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
9267 { 12787 /* msgt */, RISCV::MSLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9268 { 12792 /* msgtu */, RISCV::MSLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9269 { 12798 /* msgtz */, RISCV::MSLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
9270 { 12804 /* mslt */, RISCV::MSLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9271 { 12809 /* msltu */, RISCV::MSLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9272 { 12815 /* msltz */, RISCV::MSLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
9273 { 12821 /* msnez */, RISCV::MSLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
9274 { 12827 /* mul */, RISCV::MUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9275 { 12831 /* mul.h00 */, RISCV::MUL_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9276 { 12839 /* mul.h01 */, RISCV::MUL_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9277 { 12847 /* mul.h11 */, RISCV::MUL_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9278 { 12855 /* mul.w00 */, RISCV::MUL_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9279 { 12863 /* mul.w01 */, RISCV::MUL_W01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9280 { 12871 /* mul.w11 */, RISCV::MUL_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9281 { 12879 /* mulh */, RISCV::MULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9282 { 12884 /* mulh.h0 */, RISCV::MULH_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9283 { 12892 /* mulh.h1 */, RISCV::MULH_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9284 { 12900 /* mulhr */, RISCV::MULHR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9285 { 12906 /* mulhrsu */, RISCV::MULHRSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9286 { 12914 /* mulhru */, RISCV::MULHRU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9287 { 12921 /* mulhsu */, RISCV::MULHSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9288 { 12928 /* mulhsu.h0 */, RISCV::MULHSU_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9289 { 12938 /* mulhsu.h1 */, RISCV::MULHSU_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9290 { 12948 /* mulhu */, RISCV::MULHU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9291 { 12954 /* mulq */, RISCV::MULQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9292 { 12959 /* mulqr */, RISCV::MULQR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9293 { 12965 /* mulsu.h00 */, RISCV::MULSU_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9294 { 12975 /* mulsu.h11 */, RISCV::MULSU_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9295 { 12985 /* mulsu.w00 */, RISCV::MULSU_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9296 { 12995 /* mulsu.w11 */, RISCV::MULSU_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9297 { 13005 /* mulu.h00 */, RISCV::MULU_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9298 { 13014 /* mulu.h01 */, RISCV::MULU_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9299 { 13023 /* mulu.h11 */, RISCV::MULU_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9300 { 13032 /* mulu.w00 */, RISCV::MULU_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9301 { 13041 /* mulu.w01 */, RISCV::MULU_W01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9302 { 13050 /* mulu.w11 */, RISCV::MULU_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9303 { 13059 /* mulw */, RISCV::MULW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9304 { 13064 /* mv */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9305 { 13067 /* mvd */, RISCV::PADD_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9306 { 13071 /* mvm */, RISCV::MVM, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9307 { 13075 /* mvmn */, RISCV::MVMN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9308 { 13080 /* nclip */, RISCV::NCLIP, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9309 { 13086 /* nclipi */, RISCV::NCLIPI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
9310 { 13093 /* nclipiu */, RISCV::NCLIPIU, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
9311 { 13101 /* nclipr */, RISCV::NCLIPR, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9312 { 13108 /* nclipri */, RISCV::NCLIPRI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
9313 { 13116 /* nclipriu */, RISCV::NCLIPRIU, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
9314 { 13125 /* nclipru */, RISCV::NCLIPRU, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9315 { 13133 /* nclipu */, RISCV::NCLIPU, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9316 { 13140 /* nds.addigp */, RISCV::NDS_ADDIGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
9317 { 13151 /* nds.bbc */, RISCV::NDS_BBC, Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImmLog2XLen, MCK_BareSImm11Lsb0 }, },
9318 { 13159 /* nds.bbs */, RISCV::NDS_BBS, Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImmLog2XLen, MCK_BareSImm11Lsb0 }, },
9319 { 13167 /* nds.beqc */, RISCV::NDS_BEQC, Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImm7, MCK_BareSImm11Lsb0 }, },
9320 { 13176 /* nds.bfos */, RISCV::NDS_BFOS, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
9321 { 13185 /* nds.bfoz */, RISCV::NDS_BFOZ, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
9322 { 13194 /* nds.bnec */, RISCV::NDS_BNEC, Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImm7, MCK_BareSImm11Lsb0 }, },
9323 { 13203 /* nds.fcvt.bf16.s */, RISCV::NDS_FCVT_BF16_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesBFHCvt, { MCK_FPR16, MCK_FPR32 }, },
9324 { 13219 /* nds.fcvt.s.bf16 */, RISCV::NDS_FCVT_S_BF16, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesBFHCvt, { MCK_FPR32, MCK_FPR16 }, },
9325 { 13235 /* nds.ffb */, RISCV::NDS_FFB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9326 { 13243 /* nds.ffmism */, RISCV::NDS_FFMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9327 { 13254 /* nds.ffzmism */, RISCV::NDS_FFZMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9328 { 13266 /* nds.flmism */, RISCV::NDS_FLMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9329 { 13277 /* nds.lbgp */, RISCV::NDS_LBGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
9330 { 13286 /* nds.lbugp */, RISCV::NDS_LBUGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
9331 { 13296 /* nds.ldgp */, RISCV::NDS_LDGP, Convert__Reg1_0__SImm20Lsb0001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm20Lsb000 }, },
9332 { 13305 /* nds.lea.b.ze */, RISCV::NDS_LEA_B_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9333 { 13318 /* nds.lea.d */, RISCV::NDS_LEA_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9334 { 13328 /* nds.lea.d.ze */, RISCV::NDS_LEA_D_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9335 { 13341 /* nds.lea.h */, RISCV::NDS_LEA_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9336 { 13351 /* nds.lea.h.ze */, RISCV::NDS_LEA_H_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9337 { 13364 /* nds.lea.w */, RISCV::NDS_LEA_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9338 { 13374 /* nds.lea.w.ze */, RISCV::NDS_LEA_W_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9339 { 13387 /* nds.lhgp */, RISCV::NDS_LHGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
9340 { 13396 /* nds.lhugp */, RISCV::NDS_LHUGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
9341 { 13406 /* nds.lwgp */, RISCV::NDS_LWGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm19Lsb00 }, },
9342 { 13415 /* nds.lwugp */, RISCV::NDS_LWUGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm19Lsb00 }, },
9343 { 13425 /* nds.sbgp */, RISCV::NDS_SBGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
9344 { 13434 /* nds.sdgp */, RISCV::NDS_SDGP, Convert__Reg1_0__SImm20Lsb0001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm20Lsb000 }, },
9345 { 13443 /* nds.shgp */, RISCV::NDS_SHGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
9346 { 13452 /* nds.swgp */, RISCV::NDS_SWGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm19Lsb00 }, },
9347 { 13461 /* nds.vd4dots.vv */, RISCV::NDS_VD4DOTS_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9348 { 13476 /* nds.vd4dotsu.vv */, RISCV::NDS_VD4DOTSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9349 { 13492 /* nds.vd4dotu.vv */, RISCV::NDS_VD4DOTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9350 { 13507 /* nds.vfncvt.bf16.s */, RISCV::NDS_VFNCVT_BF16_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesVBFHCvt, { MCK_VR, MCK_VR }, },
9351 { 13525 /* nds.vfpmadb.vf */, RISCV::NDS_VFPMADB_VF, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVPackFPH, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9352 { 13540 /* nds.vfpmadt.vf */, RISCV::NDS_VFPMADT_VF, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVPackFPH, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9353 { 13555 /* nds.vfwcvt.f.b.v */, RISCV::NDS_VFWCVT_F_B, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9354 { 13572 /* nds.vfwcvt.f.bu.v */, RISCV::NDS_VFWCVT_F_BU, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9355 { 13590 /* nds.vfwcvt.f.n.v */, RISCV::NDS_VFWCVT_F_N, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9356 { 13607 /* nds.vfwcvt.f.nu.v */, RISCV::NDS_VFWCVT_F_NU, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9357 { 13625 /* nds.vfwcvt.s.bf16 */, RISCV::NDS_VFWCVT_S_BF16, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesVBFHCvt, { MCK_VR, MCK_VR }, },
9358 { 13643 /* nds.vle4.v */, RISCV::NDS_VLE4_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
9359 { 13654 /* nds.vln8.v */, RISCV::NDS_VLN8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntLoad, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9360 { 13665 /* nds.vlnu8.v */, RISCV::NDS_VLNU8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntLoad, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
9361 { 13677 /* neg */, RISCV::SUB, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9362 { 13681 /* negd */, RISCV::SUBD, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9363 { 13686 /* negw */, RISCV::SUBW, Convert__Reg1_0__regX0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
9364 { 13691 /* nop */, RISCV::ADDI, Convert__regX0__regX0__imm_95_0, AMFBS_None, { }, },
9365 { 13695 /* not */, RISCV::XORI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9366 { 13699 /* nsra */, RISCV::NSRA, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9367 { 13704 /* nsrai */, RISCV::NSRAI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
9368 { 13710 /* nsrar */, RISCV::NSRAR, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9369 { 13716 /* nsrari */, RISCV::NSRARI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
9370 { 13723 /* nsrl */, RISCV::NSRL, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9371 { 13728 /* nsrli */, RISCV::NSRLI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
9372 { 13734 /* ntl.all */, RISCV::ADD, Convert__regX0__regX0__regX5, AMFBS_None, { }, },
9373 { 13742 /* ntl.p1 */, RISCV::ADD, Convert__regX0__regX0__regX2, AMFBS_None, { }, },
9374 { 13749 /* ntl.pall */, RISCV::ADD, Convert__regX0__regX0__regX3, AMFBS_None, { }, },
9375 { 13758 /* ntl.s1 */, RISCV::ADD, Convert__regX0__regX0__regX4, AMFBS_None, { }, },
9376 { 13765 /* or */, RISCV::OR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9377 { 13765 /* or */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9378 { 13768 /* orc.b */, RISCV::ORC_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
9379 { 13774 /* ori */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9380 { 13778 /* orn */, RISCV::ORN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9381 { 13782 /* paadd.b */, RISCV::PAADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9382 { 13790 /* paadd.db */, RISCV::PAADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9383 { 13799 /* paadd.dh */, RISCV::PAADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9384 { 13808 /* paadd.dw */, RISCV::PAADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9385 { 13817 /* paadd.h */, RISCV::PAADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9386 { 13825 /* paadd.w */, RISCV::PAADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9387 { 13833 /* paaddu.b */, RISCV::PAADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9388 { 13842 /* paaddu.db */, RISCV::PAADDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9389 { 13852 /* paaddu.dh */, RISCV::PAADDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9390 { 13862 /* paaddu.dw */, RISCV::PAADDU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9391 { 13872 /* paaddu.h */, RISCV::PAADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9392 { 13881 /* paaddu.w */, RISCV::PAADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9393 { 13890 /* paas.dhx */, RISCV::PAAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9394 { 13899 /* paas.hx */, RISCV::PAAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9395 { 13907 /* paas.wx */, RISCV::PAAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9396 { 13915 /* pabd.b */, RISCV::PABD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9397 { 13922 /* pabd.db */, RISCV::PABD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9398 { 13930 /* pabd.dh */, RISCV::PABD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9399 { 13938 /* pabd.h */, RISCV::PABD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9400 { 13945 /* pabdsumau.b */, RISCV::PABDSUMAU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9401 { 13957 /* pabdsumu.b */, RISCV::PABDSUMU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9402 { 13968 /* pabdu.b */, RISCV::PABDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9403 { 13976 /* pabdu.db */, RISCV::PABDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9404 { 13985 /* pabdu.dh */, RISCV::PABDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9405 { 13994 /* pabdu.h */, RISCV::PABDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9406 { 14002 /* pabs.b */, RISCV::PABD_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9407 { 14009 /* pabs.db */, RISCV::PABD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9408 { 14017 /* pabs.dh */, RISCV::PABD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9409 { 14025 /* pabs.h */, RISCV::PABD_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9410 { 14032 /* pack */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkbOrP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9411 { 14037 /* packh */, RISCV::PACKH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9412 { 14043 /* packw */, RISCV::PACKW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9413 { 14049 /* padd.b */, RISCV::PADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9414 { 14056 /* padd.bs */, RISCV::PADD_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9415 { 14064 /* padd.db */, RISCV::PADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9416 { 14072 /* padd.dbs */, RISCV::PADD_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9417 { 14081 /* padd.dh */, RISCV::PADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9418 { 14089 /* padd.dhs */, RISCV::PADD_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9419 { 14098 /* padd.dw */, RISCV::PADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9420 { 14106 /* padd.dws */, RISCV::PADD_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9421 { 14115 /* padd.h */, RISCV::PADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9422 { 14122 /* padd.hs */, RISCV::PADD_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9423 { 14130 /* padd.w */, RISCV::PADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9424 { 14137 /* padd.ws */, RISCV::PADD_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9425 { 14145 /* pas.dhx */, RISCV::PAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9426 { 14153 /* pas.hx */, RISCV::PAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9427 { 14160 /* pas.wx */, RISCV::PAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9428 { 14167 /* pasa.dhx */, RISCV::PASA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9429 { 14176 /* pasa.hx */, RISCV::PASA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9430 { 14184 /* pasa.wx */, RISCV::PASA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9431 { 14192 /* pasub.b */, RISCV::PASUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9432 { 14200 /* pasub.db */, RISCV::PASUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9433 { 14209 /* pasub.dh */, RISCV::PASUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9434 { 14218 /* pasub.dw */, RISCV::PASUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9435 { 14227 /* pasub.h */, RISCV::PASUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9436 { 14235 /* pasub.w */, RISCV::PASUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9437 { 14243 /* pasubu.b */, RISCV::PASUBU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9438 { 14252 /* pasubu.db */, RISCV::PASUBU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9439 { 14262 /* pasubu.dh */, RISCV::PASUBU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9440 { 14272 /* pasubu.dw */, RISCV::PASUBU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9441 { 14282 /* pasubu.h */, RISCV::PASUBU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9442 { 14291 /* pasubu.w */, RISCV::PASUBU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9443 { 14300 /* pause */, RISCV::FENCE, Convert__imm_95_1__imm_95_0, AMFBS_None, { }, },
9444 { 14306 /* pli.b */, RISCV::PLI_B, Convert__Reg1_0__SImm8PLI_B1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm8PLI_B }, },
9445 { 14312 /* pli.db */, RISCV::PLI_DB, Convert__GPRPairRV321_0__SImm8PLI_B1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm8PLI_B }, },
9446 { 14319 /* pli.dh */, RISCV::PLI_DH, Convert__GPRPairRV321_0__SImm10PLI_H1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm10PLI_H }, },
9447 { 14326 /* pli.h */, RISCV::PLI_H, Convert__Reg1_0__SImm10PLI_H1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm10PLI_H }, },
9448 { 14332 /* pli.w */, RISCV::PLI_W, Convert__Reg1_0__SImm10PLI_W1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_SImm10PLI_W }, },
9449 { 14338 /* plui.dh */, RISCV::PLUI_DH, Convert__GPRPairRV321_0__SImm10PLUI1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm10PLUI }, },
9450 { 14346 /* plui.h */, RISCV::PLUI_H, Convert__Reg1_0__SImm10PLUI1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm10PLUI }, },
9451 { 14353 /* plui.w */, RISCV::PLUI_W, Convert__Reg1_0__SImm10PLUI1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_SImm10PLUI }, },
9452 { 14360 /* pm2add.h */, RISCV::PM2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9453 { 14369 /* pm2add.hx */, RISCV::PM2ADD_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9454 { 14379 /* pm2add.w */, RISCV::PM2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9455 { 14388 /* pm2add.wx */, RISCV::PM2ADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9456 { 14398 /* pm2adda.h */, RISCV::PM2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9457 { 14408 /* pm2adda.hx */, RISCV::PM2ADDA_HX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9458 { 14419 /* pm2adda.w */, RISCV::PM2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9459 { 14429 /* pm2adda.wx */, RISCV::PM2ADDA_WX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9460 { 14440 /* pm2addasu.h */, RISCV::PM2ADDASU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9461 { 14452 /* pm2addasu.w */, RISCV::PM2ADDASU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9462 { 14464 /* pm2addau.h */, RISCV::PM2ADDAU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9463 { 14475 /* pm2addau.w */, RISCV::PM2ADDAU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9464 { 14486 /* pm2addsu.h */, RISCV::PM2ADDSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9465 { 14497 /* pm2addsu.w */, RISCV::PM2ADDSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9466 { 14508 /* pm2addu.h */, RISCV::PM2ADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9467 { 14518 /* pm2addu.w */, RISCV::PM2ADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9468 { 14528 /* pm2sadd.h */, RISCV::PM2SADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9469 { 14538 /* pm2sadd.hx */, RISCV::PM2SADD_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9470 { 14549 /* pm2sub.h */, RISCV::PM2SUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9471 { 14558 /* pm2sub.hx */, RISCV::PM2SUB_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9472 { 14568 /* pm2sub.w */, RISCV::PM2SUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9473 { 14577 /* pm2sub.wx */, RISCV::PM2SUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9474 { 14587 /* pm2suba.h */, RISCV::PM2SUBA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9475 { 14597 /* pm2suba.hx */, RISCV::PM2SUBA_HX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9476 { 14608 /* pm2suba.w */, RISCV::PM2SUBA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9477 { 14618 /* pm2suba.wx */, RISCV::PM2SUBA_WX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9478 { 14629 /* pm2wadd.h */, RISCV::PM2WADD_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9479 { 14639 /* pm2wadd.hx */, RISCV::PM2WADD_HX, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9480 { 14650 /* pm2wadda.h */, RISCV::PM2WADDA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9481 { 14661 /* pm2wadda.hx */, RISCV::PM2WADDA_HX, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9482 { 14673 /* pm2waddasu.h */, RISCV::PM2WADDASU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9483 { 14686 /* pm2waddau.h */, RISCV::PM2WADDAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9484 { 14698 /* pm2waddsu.h */, RISCV::PM2WADDSU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9485 { 14710 /* pm2waddu.h */, RISCV::PM2WADDU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9486 { 14721 /* pm2wsub.h */, RISCV::PM2WSUB_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9487 { 14731 /* pm2wsub.hx */, RISCV::PM2WSUB_HX, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9488 { 14742 /* pm2wsuba.h */, RISCV::PM2WSUBA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9489 { 14753 /* pm2wsuba.hx */, RISCV::PM2WSUBA_HX, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9490 { 14765 /* pm4add.b */, RISCV::PM4ADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9491 { 14774 /* pm4add.h */, RISCV::PM4ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9492 { 14783 /* pm4adda.b */, RISCV::PM4ADDA_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9493 { 14793 /* pm4adda.h */, RISCV::PM4ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9494 { 14803 /* pm4addasu.b */, RISCV::PM4ADDASU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9495 { 14815 /* pm4addasu.h */, RISCV::PM4ADDASU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9496 { 14827 /* pm4addau.b */, RISCV::PM4ADDAU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9497 { 14838 /* pm4addau.h */, RISCV::PM4ADDAU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9498 { 14849 /* pm4addsu.b */, RISCV::PM4ADDSU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9499 { 14860 /* pm4addsu.h */, RISCV::PM4ADDSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9500 { 14871 /* pm4addu.b */, RISCV::PM4ADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9501 { 14881 /* pm4addu.h */, RISCV::PM4ADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9502 { 14891 /* pmacc.w.h00 */, RISCV::PMACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9503 { 14903 /* pmacc.w.h01 */, RISCV::PMACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9504 { 14915 /* pmacc.w.h11 */, RISCV::PMACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9505 { 14927 /* pmaccsu.w.h00 */, RISCV::PMACCSU_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9506 { 14941 /* pmaccsu.w.h11 */, RISCV::PMACCSU_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9507 { 14955 /* pmaccu.w.h00 */, RISCV::PMACCU_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9508 { 14968 /* pmaccu.w.h01 */, RISCV::PMACCU_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9509 { 14981 /* pmaccu.w.h11 */, RISCV::PMACCU_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9510 { 14994 /* pmax.b */, RISCV::PMAX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9511 { 15001 /* pmax.db */, RISCV::PMAX_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9512 { 15009 /* pmax.dh */, RISCV::PMAX_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9513 { 15017 /* pmax.dw */, RISCV::PMAX_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9514 { 15025 /* pmax.h */, RISCV::PMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9515 { 15032 /* pmax.w */, RISCV::PMAX_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9516 { 15039 /* pmaxu.b */, RISCV::PMAXU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9517 { 15047 /* pmaxu.db */, RISCV::PMAXU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9518 { 15056 /* pmaxu.dh */, RISCV::PMAXU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9519 { 15065 /* pmaxu.dw */, RISCV::PMAXU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9520 { 15074 /* pmaxu.h */, RISCV::PMAXU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9521 { 15082 /* pmaxu.w */, RISCV::PMAXU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9522 { 15090 /* pmhacc.h */, RISCV::PMHACC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9523 { 15099 /* pmhacc.h.b0 */, RISCV::PMHACC_H_B0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9524 { 15111 /* pmhacc.h.b1 */, RISCV::PMHACC_H_B1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9525 { 15123 /* pmhacc.w */, RISCV::PMHACC_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9526 { 15132 /* pmhacc.w.h0 */, RISCV::PMHACC_W_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9527 { 15144 /* pmhacc.w.h1 */, RISCV::PMHACC_W_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9528 { 15156 /* pmhaccsu.h */, RISCV::PMHACCSU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9529 { 15167 /* pmhaccsu.h.b0 */, RISCV::PMHACCSU_H_B0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9530 { 15181 /* pmhaccsu.h.b1 */, RISCV::PMHACCSU_H_B1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9531 { 15195 /* pmhaccsu.w */, RISCV::PMHACCSU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9532 { 15206 /* pmhaccsu.w.h0 */, RISCV::PMHACCSU_W_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9533 { 15220 /* pmhaccsu.w.h1 */, RISCV::PMHACCSU_W_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9534 { 15234 /* pmhaccu.h */, RISCV::PMHACCU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9535 { 15244 /* pmhaccu.w */, RISCV::PMHACCU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9536 { 15254 /* pmhracc.h */, RISCV::PMHRACC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9537 { 15264 /* pmhracc.w */, RISCV::PMHRACC_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9538 { 15274 /* pmhraccsu.h */, RISCV::PMHRACCSU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9539 { 15286 /* pmhraccsu.w */, RISCV::PMHRACCSU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9540 { 15298 /* pmhraccu.h */, RISCV::PMHRACCU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9541 { 15309 /* pmhraccu.w */, RISCV::PMHRACCU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9542 { 15320 /* pmin.b */, RISCV::PMIN_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9543 { 15327 /* pmin.db */, RISCV::PMIN_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9544 { 15335 /* pmin.dh */, RISCV::PMIN_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9545 { 15343 /* pmin.dw */, RISCV::PMIN_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9546 { 15351 /* pmin.h */, RISCV::PMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9547 { 15358 /* pmin.w */, RISCV::PMIN_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9548 { 15365 /* pminu.b */, RISCV::PMINU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9549 { 15373 /* pminu.db */, RISCV::PMINU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9550 { 15382 /* pminu.dh */, RISCV::PMINU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9551 { 15391 /* pminu.dw */, RISCV::PMINU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9552 { 15400 /* pminu.h */, RISCV::PMINU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9553 { 15408 /* pminu.w */, RISCV::PMINU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9554 { 15416 /* pmq2add.h */, RISCV::PMQ2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9555 { 15426 /* pmq2add.w */, RISCV::PMQ2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9556 { 15436 /* pmq2adda.h */, RISCV::PMQ2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9557 { 15447 /* pmq2adda.w */, RISCV::PMQ2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9558 { 15458 /* pmqacc.w.h00 */, RISCV::PMQACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9559 { 15471 /* pmqacc.w.h01 */, RISCV::PMQACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9560 { 15484 /* pmqacc.w.h11 */, RISCV::PMQACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9561 { 15497 /* pmqr2add.h */, RISCV::PMQR2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9562 { 15508 /* pmqr2add.w */, RISCV::PMQR2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9563 { 15519 /* pmqr2adda.h */, RISCV::PMQR2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9564 { 15531 /* pmqr2adda.w */, RISCV::PMQR2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9565 { 15543 /* pmqracc.w.h00 */, RISCV::PMQRACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9566 { 15557 /* pmqracc.w.h01 */, RISCV::PMQRACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9567 { 15571 /* pmqracc.w.h11 */, RISCV::PMQRACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9568 { 15585 /* pmqrwacc.h */, RISCV::PMQRWACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9569 { 15596 /* pmqwacc.h */, RISCV::PMQWACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9570 { 15606 /* pmseq.b */, RISCV::PMSEQ_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9571 { 15614 /* pmseq.db */, RISCV::PMSEQ_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9572 { 15623 /* pmseq.dh */, RISCV::PMSEQ_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9573 { 15632 /* pmseq.dw */, RISCV::PMSEQ_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9574 { 15641 /* pmseq.h */, RISCV::PMSEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9575 { 15649 /* pmseq.w */, RISCV::PMSEQ_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9576 { 15657 /* pmseqz.b */, RISCV::PMSEQ_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9577 { 15666 /* pmseqz.db */, RISCV::PMSEQ_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9578 { 15676 /* pmseqz.dh */, RISCV::PMSEQ_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9579 { 15686 /* pmseqz.dw */, RISCV::PMSEQ_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9580 { 15696 /* pmseqz.h */, RISCV::PMSEQ_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9581 { 15705 /* pmseqz.w */, RISCV::PMSEQ_W, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9582 { 15714 /* pmsgt.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9583 { 15722 /* pmsgt.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9584 { 15731 /* pmsgt.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9585 { 15740 /* pmsgt.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9586 { 15749 /* pmsgt.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9587 { 15757 /* pmsgt.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9588 { 15765 /* pmsgtu.b */, RISCV::PMSLTU_B, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9589 { 15774 /* pmsgtu.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9590 { 15784 /* pmsgtu.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9591 { 15794 /* pmsgtu.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9592 { 15804 /* pmsgtu.h */, RISCV::PMSLTU_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9593 { 15813 /* pmsgtu.w */, RISCV::PMSLTU_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9594 { 15822 /* pmsgtz.b */, RISCV::PMSLT_B, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9595 { 15831 /* pmsgtz.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9596 { 15841 /* pmsgtz.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9597 { 15851 /* pmsgtz.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9598 { 15861 /* pmsgtz.h */, RISCV::PMSLT_H, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9599 { 15870 /* pmsgtz.w */, RISCV::PMSLT_W, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9600 { 15879 /* pmslt.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9601 { 15887 /* pmslt.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9602 { 15896 /* pmslt.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9603 { 15905 /* pmslt.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9604 { 15914 /* pmslt.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9605 { 15922 /* pmslt.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9606 { 15930 /* pmsltu.b */, RISCV::PMSLTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9607 { 15939 /* pmsltu.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9608 { 15949 /* pmsltu.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9609 { 15959 /* pmsltu.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9610 { 15969 /* pmsltu.h */, RISCV::PMSLTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9611 { 15978 /* pmsltu.w */, RISCV::PMSLTU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9612 { 15987 /* pmsltz.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9613 { 15996 /* pmsltz.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9614 { 16006 /* pmsltz.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9615 { 16016 /* pmsltz.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9616 { 16026 /* pmsltz.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9617 { 16035 /* pmsltz.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9618 { 16044 /* pmsnez.b */, RISCV::PMSLTU_B, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9619 { 16053 /* pmsnez.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9620 { 16063 /* pmsnez.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9621 { 16073 /* pmsnez.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9622 { 16083 /* pmsnez.h */, RISCV::PMSLTU_H, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9623 { 16092 /* pmsnez.w */, RISCV::PMSLTU_W, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9624 { 16101 /* pmul.h.b00 */, RISCV::PMUL_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9625 { 16112 /* pmul.h.b01 */, RISCV::PMUL_H_B01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9626 { 16123 /* pmul.h.b11 */, RISCV::PMUL_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9627 { 16134 /* pmul.w.h00 */, RISCV::PMUL_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9628 { 16145 /* pmul.w.h01 */, RISCV::PMUL_W_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9629 { 16156 /* pmul.w.h11 */, RISCV::PMUL_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9630 { 16167 /* pmulh.h */, RISCV::PMULH_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9631 { 16175 /* pmulh.h.b0 */, RISCV::PMULH_H_B0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9632 { 16186 /* pmulh.h.b1 */, RISCV::PMULH_H_B1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9633 { 16197 /* pmulh.w */, RISCV::PMULH_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9634 { 16205 /* pmulh.w.h0 */, RISCV::PMULH_W_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9635 { 16216 /* pmulh.w.h1 */, RISCV::PMULH_W_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9636 { 16227 /* pmulhr.h */, RISCV::PMULHR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9637 { 16236 /* pmulhr.w */, RISCV::PMULHR_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9638 { 16245 /* pmulhrsu.h */, RISCV::PMULHRSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9639 { 16256 /* pmulhrsu.w */, RISCV::PMULHRSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9640 { 16267 /* pmulhru.h */, RISCV::PMULHRU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9641 { 16277 /* pmulhru.w */, RISCV::PMULHRU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9642 { 16287 /* pmulhsu.h */, RISCV::PMULHSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9643 { 16297 /* pmulhsu.h.b0 */, RISCV::PMULHSU_H_B0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9644 { 16310 /* pmulhsu.h.b1 */, RISCV::PMULHSU_H_B1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9645 { 16323 /* pmulhsu.w */, RISCV::PMULHSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9646 { 16333 /* pmulhsu.w.h0 */, RISCV::PMULHSU_W_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9647 { 16346 /* pmulhsu.w.h1 */, RISCV::PMULHSU_W_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9648 { 16359 /* pmulhu.h */, RISCV::PMULHU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9649 { 16368 /* pmulhu.w */, RISCV::PMULHU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9650 { 16377 /* pmulq.h */, RISCV::PMULQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9651 { 16385 /* pmulq.w */, RISCV::PMULQ_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9652 { 16393 /* pmulqr.h */, RISCV::PMULQR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9653 { 16402 /* pmulqr.w */, RISCV::PMULQR_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9654 { 16411 /* pmulsu.h.b00 */, RISCV::PMULSU_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9655 { 16424 /* pmulsu.h.b11 */, RISCV::PMULSU_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9656 { 16437 /* pmulsu.w.h00 */, RISCV::PMULSU_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9657 { 16450 /* pmulsu.w.h11 */, RISCV::PMULSU_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9658 { 16463 /* pmulu.h.b00 */, RISCV::PMULU_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9659 { 16475 /* pmulu.h.b01 */, RISCV::PMULU_H_B01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9660 { 16487 /* pmulu.h.b11 */, RISCV::PMULU_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9661 { 16499 /* pmulu.w.h00 */, RISCV::PMULU_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9662 { 16511 /* pmulu.w.h01 */, RISCV::PMULU_W_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9663 { 16523 /* pmulu.w.h11 */, RISCV::PMULU_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9664 { 16535 /* pmv.bs */, RISCV::PADD_BS, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9665 { 16542 /* pmv.dbs */, RISCV::PADD_DBS, Convert__GPRPairRV321_0__regX0_Pair__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9666 { 16550 /* pmv.dhs */, RISCV::PADD_DHS, Convert__GPRPairRV321_0__regX0_Pair__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9667 { 16558 /* pmv.dws */, RISCV::PADD_DWS, Convert__GPRPairRV321_0__regX0_Pair__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9668 { 16566 /* pmv.hs */, RISCV::PADD_HS, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9669 { 16573 /* pmv.ws */, RISCV::PADD_WS, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9670 { 16580 /* pnclip.bs */, RISCV::PNCLIP_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9671 { 16590 /* pnclip.hs */, RISCV::PNCLIP_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9672 { 16600 /* pnclipi.b */, RISCV::PNCLIPI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9673 { 16610 /* pnclipi.h */, RISCV::PNCLIPI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9674 { 16620 /* pnclipiu.b */, RISCV::PNCLIPIU_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9675 { 16631 /* pnclipiu.h */, RISCV::PNCLIPIU_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9676 { 16642 /* pnclipp.b */, RISCV::PNCLIPP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9677 { 16652 /* pnclipp.h */, RISCV::PNCLIPP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9678 { 16662 /* pnclipp.w */, RISCV::PNCLIPP_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9679 { 16672 /* pnclipr.bs */, RISCV::PNCLIPR_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9680 { 16683 /* pnclipr.hs */, RISCV::PNCLIPR_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9681 { 16694 /* pnclipri.b */, RISCV::PNCLIPRI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9682 { 16705 /* pnclipri.h */, RISCV::PNCLIPRI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9683 { 16716 /* pnclipriu.b */, RISCV::PNCLIPRIU_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9684 { 16728 /* pnclipriu.h */, RISCV::PNCLIPRIU_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9685 { 16740 /* pnclipru.bs */, RISCV::PNCLIPRU_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9686 { 16752 /* pnclipru.hs */, RISCV::PNCLIPRU_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9687 { 16764 /* pnclipu.bs */, RISCV::PNCLIPU_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9688 { 16775 /* pnclipu.hs */, RISCV::PNCLIPU_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9689 { 16786 /* pnclipup.b */, RISCV::PNCLIPUP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9690 { 16797 /* pnclipup.h */, RISCV::PNCLIPUP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9691 { 16808 /* pnclipup.w */, RISCV::PNCLIPUP_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9692 { 16819 /* pncvt.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__imm_95_0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9693 { 16827 /* pncvt.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__imm_95_0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9694 { 16835 /* pncvt.wb */, RISCV::UNZIP8P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9695 { 16844 /* pncvt.wh */, RISCV::UNZIP16P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9696 { 16853 /* pncvth.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__imm_95_8, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9697 { 16862 /* pncvth.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__imm_95_16, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9698 { 16871 /* pncvth.wb */, RISCV::UNZIP8HP, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9699 { 16881 /* pncvth.wh */, RISCV::UNZIP16HP, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9700 { 16891 /* pneg.b */, RISCV::PSUB_B, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9701 { 16898 /* pneg.db */, RISCV::PSUB_DB, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9702 { 16906 /* pneg.dh */, RISCV::PSUB_DH, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9703 { 16914 /* pneg.dw */, RISCV::PSUB_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9704 { 16922 /* pneg.h */, RISCV::PSUB_H, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9705 { 16929 /* pneg.w */, RISCV::PSUB_W, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9706 { 16936 /* pnsra.bs */, RISCV::PNSRA_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9707 { 16945 /* pnsra.hs */, RISCV::PNSRA_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9708 { 16954 /* pnsrai.b */, RISCV::PNSRAI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9709 { 16963 /* pnsrai.h */, RISCV::PNSRAI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9710 { 16972 /* pnsrar.bs */, RISCV::PNSRAR_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9711 { 16982 /* pnsrar.hs */, RISCV::PNSRAR_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9712 { 16992 /* pnsrari.b */, RISCV::PNSRARI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9713 { 17002 /* pnsrari.h */, RISCV::PNSRARI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9714 { 17012 /* pnsrl.bs */, RISCV::PNSRL_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9715 { 17021 /* pnsrl.hs */, RISCV::PNSRL_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9716 { 17030 /* pnsrli.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9717 { 17039 /* pnsrli.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9718 { 17048 /* ppaire.b */, RISCV::PPAIRE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9719 { 17057 /* ppaire.db */, RISCV::PPAIRE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9720 { 17067 /* ppaire.dh */, RISCV::PPAIRE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9721 { 17077 /* ppaire.h */, RISCV::PPAIRE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9722 { 17077 /* ppaire.h */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9723 { 17086 /* ppaire.w */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9724 { 17095 /* ppaireo.b */, RISCV::PPAIREO_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9725 { 17105 /* ppaireo.db */, RISCV::PPAIREO_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9726 { 17116 /* ppaireo.dh */, RISCV::PPAIREO_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9727 { 17127 /* ppaireo.h */, RISCV::PPAIREO_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9728 { 17137 /* ppaireo.w */, RISCV::PPAIREO_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9729 { 17147 /* ppairo.b */, RISCV::PPAIRO_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9730 { 17156 /* ppairo.db */, RISCV::PPAIRO_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9731 { 17166 /* ppairo.dh */, RISCV::PPAIRO_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9732 { 17176 /* ppairo.h */, RISCV::PPAIRO_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9733 { 17185 /* ppairo.w */, RISCV::PPAIRO_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9734 { 17194 /* ppairoe.b */, RISCV::PPAIROE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9735 { 17204 /* ppairoe.db */, RISCV::PPAIROE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9736 { 17215 /* ppairoe.dh */, RISCV::PPAIROE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9737 { 17226 /* ppairoe.h */, RISCV::PPAIROE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9738 { 17236 /* ppairoe.w */, RISCV::PPAIROE_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9739 { 17246 /* predsum.bs */, RISCV::PREDSUM_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9740 { 17257 /* predsum.dbs */, RISCV::PREDSUM_DBS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9741 { 17269 /* predsum.dhs */, RISCV::PREDSUM_DHS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9742 { 17281 /* predsum.hs */, RISCV::PREDSUM_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9743 { 17292 /* predsum.ws */, RISCV::PREDSUM_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9744 { 17303 /* predsumu.bs */, RISCV::PREDSUMU_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9745 { 17315 /* predsumu.dbs */, RISCV::PREDSUMU_DBS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9746 { 17328 /* predsumu.dhs */, RISCV::PREDSUMU_DHS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9747 { 17341 /* predsumu.hs */, RISCV::PREDSUMU_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9748 { 17353 /* predsumu.ws */, RISCV::PREDSUMU_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9749 { 17365 /* prefetch.i */, RISCV::PREFETCH_I, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_None, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
9750 { 17376 /* prefetch.r */, RISCV::PREFETCH_R, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_None, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
9751 { 17387 /* prefetch.w */, RISCV::PREFETCH_W, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_None, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
9752 { 17398 /* psa.dhx */, RISCV::PSA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9753 { 17406 /* psa.hx */, RISCV::PSA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9754 { 17413 /* psa.wx */, RISCV::PSA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9755 { 17420 /* psabs.b */, RISCV::PSABS_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9756 { 17428 /* psabs.db */, RISCV::PSABS_DB, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9757 { 17437 /* psabs.dh */, RISCV::PSABS_DH, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9758 { 17446 /* psabs.h */, RISCV::PSABS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9759 { 17454 /* psadd.b */, RISCV::PSADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9760 { 17462 /* psadd.db */, RISCV::PSADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9761 { 17471 /* psadd.dh */, RISCV::PSADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9762 { 17480 /* psadd.dw */, RISCV::PSADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9763 { 17489 /* psadd.h */, RISCV::PSADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9764 { 17497 /* psadd.w */, RISCV::PSADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9765 { 17505 /* psaddu.b */, RISCV::PSADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9766 { 17514 /* psaddu.db */, RISCV::PSADDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9767 { 17524 /* psaddu.dh */, RISCV::PSADDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9768 { 17534 /* psaddu.dw */, RISCV::PSADDU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9769 { 17544 /* psaddu.h */, RISCV::PSADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9770 { 17553 /* psaddu.w */, RISCV::PSADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9771 { 17562 /* psas.dhx */, RISCV::PSAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9772 { 17571 /* psas.hx */, RISCV::PSAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9773 { 17579 /* psas.wx */, RISCV::PSAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9774 { 17587 /* psati.dh */, RISCV::PSATI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm4Plus11_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4Plus1 }, },
9775 { 17596 /* psati.dw */, RISCV::PSATI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm5Plus11_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5Plus1 }, },
9776 { 17605 /* psati.h */, RISCV::PSATI_H, Convert__Reg1_0__Reg1_1__UImm4Plus11_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4Plus1 }, },
9777 { 17613 /* psati.w */, RISCV::PSATI_W, Convert__Reg1_0__Reg1_1__UImm5Plus11_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5Plus1 }, },
9778 { 17621 /* psext.dh.b */, RISCV::PSEXT_DH_B, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9779 { 17632 /* psext.dw.b */, RISCV::PSEXT_DW_B, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9780 { 17643 /* psext.dw.h */, RISCV::PSEXT_DW_H, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9781 { 17654 /* psext.h.b */, RISCV::PSEXT_H_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9782 { 17664 /* psext.w.b */, RISCV::PSEXT_W_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9783 { 17674 /* psext.w.h */, RISCV::PSEXT_W_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9784 { 17684 /* psh1add.dh */, RISCV::PSH1ADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9785 { 17695 /* psh1add.dw */, RISCV::PSH1ADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9786 { 17706 /* psh1add.h */, RISCV::PSH1ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9787 { 17716 /* psh1add.w */, RISCV::PSH1ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9788 { 17726 /* psll.bs */, RISCV::PSLL_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9789 { 17734 /* psll.dbs */, RISCV::PSLL_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9790 { 17743 /* psll.dhs */, RISCV::PSLL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9791 { 17752 /* psll.dws */, RISCV::PSLL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9792 { 17761 /* psll.hs */, RISCV::PSLL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9793 { 17769 /* psll.ws */, RISCV::PSLL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9794 { 17777 /* pslli.b */, RISCV::PSLLI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
9795 { 17785 /* pslli.db */, RISCV::PSLLI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
9796 { 17794 /* pslli.dh */, RISCV::PSLLI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9797 { 17803 /* pslli.dw */, RISCV::PSLLI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9798 { 17812 /* pslli.h */, RISCV::PSLLI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9799 { 17820 /* pslli.w */, RISCV::PSLLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9800 { 17828 /* psra.bs */, RISCV::PSRA_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9801 { 17836 /* psra.dbs */, RISCV::PSRA_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9802 { 17845 /* psra.dhs */, RISCV::PSRA_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9803 { 17854 /* psra.dws */, RISCV::PSRA_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9804 { 17863 /* psra.hs */, RISCV::PSRA_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9805 { 17871 /* psra.ws */, RISCV::PSRA_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9806 { 17879 /* psrai.b */, RISCV::PSRAI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
9807 { 17887 /* psrai.db */, RISCV::PSRAI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
9808 { 17896 /* psrai.dh */, RISCV::PSRAI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9809 { 17905 /* psrai.dw */, RISCV::PSRAI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9810 { 17914 /* psrai.h */, RISCV::PSRAI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9811 { 17922 /* psrai.w */, RISCV::PSRAI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9812 { 17930 /* psrari.dh */, RISCV::PSRARI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9813 { 17940 /* psrari.dw */, RISCV::PSRARI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9814 { 17950 /* psrari.h */, RISCV::PSRARI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9815 { 17959 /* psrari.w */, RISCV::PSRARI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9816 { 17968 /* psrl.bs */, RISCV::PSRL_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9817 { 17976 /* psrl.dbs */, RISCV::PSRL_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9818 { 17985 /* psrl.dhs */, RISCV::PSRL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9819 { 17994 /* psrl.dws */, RISCV::PSRL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9820 { 18003 /* psrl.hs */, RISCV::PSRL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9821 { 18011 /* psrl.ws */, RISCV::PSRL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9822 { 18019 /* psrli.b */, RISCV::PSRLI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
9823 { 18027 /* psrli.db */, RISCV::PSRLI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
9824 { 18036 /* psrli.dh */, RISCV::PSRLI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9825 { 18045 /* psrli.dw */, RISCV::PSRLI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9826 { 18054 /* psrli.h */, RISCV::PSRLI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9827 { 18062 /* psrli.w */, RISCV::PSRLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9828 { 18070 /* pssa.dhx */, RISCV::PSSA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9829 { 18079 /* pssa.hx */, RISCV::PSSA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9830 { 18087 /* pssa.wx */, RISCV::PSSA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9831 { 18095 /* pssh1sadd.dh */, RISCV::PSSH1SADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9832 { 18108 /* pssh1sadd.dw */, RISCV::PSSH1SADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9833 { 18121 /* pssh1sadd.h */, RISCV::PSSH1SADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9834 { 18133 /* pssh1sadd.w */, RISCV::PSSH1SADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9835 { 18145 /* pssha.dhs */, RISCV::PSSHA_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9836 { 18155 /* pssha.dws */, RISCV::PSSHA_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9837 { 18165 /* pssha.hs */, RISCV::PSSHA_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9838 { 18174 /* pssha.ws */, RISCV::PSSHA_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9839 { 18183 /* psshar.dhs */, RISCV::PSSHAR_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9840 { 18194 /* psshar.dws */, RISCV::PSSHAR_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9841 { 18205 /* psshar.hs */, RISCV::PSSHAR_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9842 { 18215 /* psshar.ws */, RISCV::PSSHAR_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9843 { 18225 /* psshl.dhs */, RISCV::PSSHL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9844 { 18235 /* psshl.dws */, RISCV::PSSHL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9845 { 18245 /* psshl.hs */, RISCV::PSSHL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9846 { 18254 /* psshl.ws */, RISCV::PSSHL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9847 { 18263 /* psshlr.dhs */, RISCV::PSSHLR_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9848 { 18274 /* psshlr.dws */, RISCV::PSSHLR_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9849 { 18285 /* psshlr.hs */, RISCV::PSSHLR_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9850 { 18295 /* psshlr.ws */, RISCV::PSSHLR_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9851 { 18305 /* psslai.dh */, RISCV::PSSLAI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9852 { 18315 /* psslai.dw */, RISCV::PSSLAI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9853 { 18325 /* psslai.h */, RISCV::PSSLAI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9854 { 18334 /* psslai.w */, RISCV::PSSLAI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9855 { 18343 /* pssub.b */, RISCV::PSSUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9856 { 18351 /* pssub.db */, RISCV::PSSUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9857 { 18360 /* pssub.dh */, RISCV::PSSUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9858 { 18369 /* pssub.dw */, RISCV::PSSUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9859 { 18378 /* pssub.h */, RISCV::PSSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9860 { 18386 /* pssub.w */, RISCV::PSSUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9861 { 18394 /* pssubu.b */, RISCV::PSSUBU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9862 { 18403 /* pssubu.db */, RISCV::PSSUBU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9863 { 18413 /* pssubu.dh */, RISCV::PSSUBU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9864 { 18423 /* pssubu.dw */, RISCV::PSSUBU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9865 { 18433 /* pssubu.h */, RISCV::PSSUBU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9866 { 18442 /* pssubu.w */, RISCV::PSSUBU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9867 { 18451 /* psub.b */, RISCV::PSUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9868 { 18458 /* psub.db */, RISCV::PSUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9869 { 18466 /* psub.dh */, RISCV::PSUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9870 { 18474 /* psub.dw */, RISCV::PSUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9871 { 18482 /* psub.h */, RISCV::PSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9872 { 18489 /* psub.w */, RISCV::PSUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9873 { 18496 /* pusati.dh */, RISCV::PUSATI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9874 { 18506 /* pusati.dw */, RISCV::PUSATI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9875 { 18516 /* pusati.h */, RISCV::PUSATI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9876 { 18525 /* pusati.w */, RISCV::PUSATI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9877 { 18534 /* pwadd.b */, RISCV::PWADD_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9878 { 18542 /* pwadd.h */, RISCV::PWADD_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9879 { 18550 /* pwadda.b */, RISCV::PWADDA_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9880 { 18559 /* pwadda.h */, RISCV::PWADDA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9881 { 18568 /* pwaddau.b */, RISCV::PWADDAU_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9882 { 18578 /* pwaddau.h */, RISCV::PWADDAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9883 { 18588 /* pwaddu.b */, RISCV::PWADDU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9884 { 18597 /* pwaddu.h */, RISCV::PWADDU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9885 { 18606 /* pwcvt.b */, RISCV::PWADD_B, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9886 { 18614 /* pwcvt.h */, RISCV::PWADD_H, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9887 { 18622 /* pwcvth.b */, RISCV::WZIP8P, Convert__GPRPairRV321_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9888 { 18631 /* pwcvth.h */, RISCV::WZIP16P, Convert__GPRPairRV321_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9889 { 18640 /* pwcvth.wb */, RISCV::ZIP8P, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9890 { 18650 /* pwcvth.wh */, RISCV::ZIP16P, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9891 { 18660 /* pwcvtu.b */, RISCV::WZIP8P, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9892 { 18669 /* pwcvtu.h */, RISCV::WZIP16P, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9893 { 18678 /* pwcvtu.wb */, RISCV::ZIP8P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9894 { 18688 /* pwcvtu.wh */, RISCV::ZIP16P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9895 { 18698 /* pwmacc.h */, RISCV::PWMACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9896 { 18707 /* pwmaccsu.h */, RISCV::PWMACCSU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9897 { 18718 /* pwmaccu.h */, RISCV::PWMACCU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9898 { 18728 /* pwmul.b */, RISCV::PWMUL_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9899 { 18736 /* pwmul.h */, RISCV::PWMUL_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9900 { 18744 /* pwmulsu.b */, RISCV::PWMULSU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9901 { 18754 /* pwmulsu.h */, RISCV::PWMULSU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9902 { 18764 /* pwmulu.b */, RISCV::PWMULU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9903 { 18773 /* pwmulu.h */, RISCV::PWMULU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9904 { 18782 /* pwsla.bs */, RISCV::PWSLA_BS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9905 { 18791 /* pwsla.hs */, RISCV::PWSLA_HS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9906 { 18800 /* pwslai.b */, RISCV::PWSLAI_B, Convert__GPRPairRV321_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm4 }, },
9907 { 18809 /* pwslai.h */, RISCV::PWSLAI_H, Convert__GPRPairRV321_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm5 }, },
9908 { 18818 /* pwsll.bs */, RISCV::PWSLL_BS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9909 { 18827 /* pwsll.hs */, RISCV::PWSLL_HS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9910 { 18836 /* pwslli.b */, RISCV::PWSLLI_B, Convert__GPRPairRV321_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm4 }, },
9911 { 18845 /* pwslli.h */, RISCV::PWSLLI_H, Convert__GPRPairRV321_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm5 }, },
9912 { 18854 /* pwsub.b */, RISCV::PWSUB_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9913 { 18862 /* pwsub.h */, RISCV::PWSUB_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9914 { 18870 /* pwsuba.b */, RISCV::PWSUBA_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9915 { 18879 /* pwsuba.h */, RISCV::PWSUBA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9916 { 18888 /* pwsubau.b */, RISCV::PWSUBAU_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9917 { 18898 /* pwsubau.h */, RISCV::PWSUBAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9918 { 18908 /* pwsubu.b */, RISCV::PWSUBU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9919 { 18917 /* pwsubu.h */, RISCV::PWSUBU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9920 { 18926 /* pzext.dh.b */, RISCV::PPAIRE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9921 { 18937 /* pzext.dw.h */, RISCV::PPAIRE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9922 { 18948 /* pzext.h.b */, RISCV::PPAIRE_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9923 { 18958 /* pzext.w.h */, RISCV::PPAIRE_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9924 { 18968 /* qc.addsat */, RISCV::QC_ADDSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9925 { 18978 /* qc.addusat */, RISCV::QC_ADDUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9926 { 18989 /* qc.beqi */, RISCV::QC_BEQI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9927 { 18997 /* qc.bgei */, RISCV::QC_BGEI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9928 { 19005 /* qc.bgeui */, RISCV::QC_BGEUI, Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_BareSImm13Lsb0 }, },
9929 { 19014 /* qc.blti */, RISCV::QC_BLTI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9930 { 19022 /* qc.bltui */, RISCV::QC_BLTUI, Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_BareSImm13Lsb0 }, },
9931 { 19031 /* qc.bnei */, RISCV::QC_BNEI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9932 { 19039 /* qc.brev32 */, RISCV::QC_BREV32, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9933 { 19049 /* qc.c.bexti */, RISCV::QC_C_BEXTI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
9934 { 19060 /* qc.c.bseti */, RISCV::QC_C_BSETI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
9935 { 19071 /* qc.c.clrint */, RISCV::QC_C_CLRINT, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9936 { 19083 /* qc.c.delay */, RISCV::C_SLLI, Convert__regX0__Tie0_1_1__UImm5NonZero1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5NonZero }, },
9937 { 19094 /* qc.c.di */, RISCV::QC_C_DI, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9938 { 19102 /* qc.c.dir */, RISCV::QC_C_DIR, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9939 { 19111 /* qc.c.ei */, RISCV::QC_C_EI, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9940 { 19119 /* qc.c.eir */, RISCV::QC_C_EIR, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9941 { 19128 /* qc.c.extu */, RISCV::QC_C_EXTU, Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_UImm5GE6Plus1 }, },
9942 { 19138 /* qc.c.mienter */, RISCV::QC_C_MIENTER, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9943 { 19151 /* qc.c.mienter.nest */, RISCV::QC_C_MIENTER_NEST, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9944 { 19169 /* qc.c.mileaveret */, RISCV::QC_C_MILEAVERET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9945 { 19185 /* qc.c.mnret */, RISCV::QC_C_MNRET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9946 { 19196 /* qc.c.mret */, RISCV::QC_C_MRET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9947 { 19206 /* qc.c.muliadd */, RISCV::QC_C_MULIADD, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRC, MCK_GPRC, MCK_UImm5 }, },
9948 { 19219 /* qc.c.mveqz */, RISCV::QC_C_MVEQZ, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRC, MCK_GPRC }, },
9949 { 19230 /* qc.c.ptrace */, RISCV::C_SLLI, Convert__regX0__Tie0_1_1__imm_95_0, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9950 { 19242 /* qc.c.setint */, RISCV::QC_C_SETINT, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9951 { 19254 /* qc.c.sync */, RISCV::QC_C_SYNC, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9952 { 19264 /* qc.c.syncr */, RISCV::QC_C_SYNCR, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9953 { 19275 /* qc.c.syncwf */, RISCV::QC_C_SYNCWF, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9954 { 19287 /* qc.c.syncwl */, RISCV::QC_C_SYNCWL, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9955 { 19299 /* qc.clo */, RISCV::QC_CLO, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9956 { 19306 /* qc.clrinti */, RISCV::QC_CLRINTI, Convert__UImm101_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_UImm10 }, },
9957 { 19317 /* qc.cm.ilut */, RISCV::QC_CM_ILUT, Convert__UImm111_0, AMFBS_HasVendorXqccmi_IsRV32, { MCK_UImm11 }, },
9958 { 19328 /* qc.cm.jalt */, RISCV::QC_CM_JALT, Convert__UImm8GE321_0, AMFBS_HasVendorXqccmt, { MCK_UImm8GE32 }, },
9959 { 19339 /* qc.cm.jt */, RISCV::QC_CM_JT, Convert__UImm51_0, AMFBS_HasVendorXqccmt, { MCK_UImm5 }, },
9960 { 19348 /* qc.cm.mva01s */, RISCV::QC_CM_MVA01S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqccmp, { MCK_GPRS07, MCK_GPRS07 }, },
9961 { 19361 /* qc.cm.mvsa01 */, RISCV::QC_CM_MVSA01, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqccmp, { MCK_GPRS07, MCK_GPRS07 }, },
9962 { 19374 /* qc.cm.pop */, RISCV::QC_CM_POP, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9963 { 19384 /* qc.cm.popret */, RISCV::QC_CM_POPRET, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9964 { 19397 /* qc.cm.popretz */, RISCV::QC_CM_POPRETZ, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9965 { 19411 /* qc.cm.push */, RISCV::QC_CM_PUSH, Convert__RegList1_0__NegStackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_NegStackAdj }, },
9966 { 19422 /* qc.cm.pushfp */, RISCV::QC_CM_PUSHFP, Convert__RegListS01_0__NegStackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegListS0, MCK_NegStackAdj }, },
9967 { 19435 /* qc.compress2 */, RISCV::QC_COMPRESS2, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9968 { 19448 /* qc.compress3 */, RISCV::QC_COMPRESS3, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9969 { 19461 /* qc.csrrwr */, RISCV::QC_CSRRWR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcicsr_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0 }, },
9970 { 19471 /* qc.csrrwri */, RISCV::QC_CSRRWRI, Convert__Reg1_0__UImm51_1__Reg1_2, AMFBS_HasVendorXqcicsr_IsRV32, { MCK_GPR, MCK_UImm5, MCK_GPRNoX0 }, },
9971 { 19482 /* qc.cto */, RISCV::QC_CTO, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9972 { 19489 /* qc.e.addai */, RISCV::QC_E_ADDAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9973 { 19500 /* qc.e.addi */, RISCV::QC_E_ADDI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9974 { 19510 /* qc.e.andai */, RISCV::QC_E_ANDAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9975 { 19521 /* qc.e.andi */, RISCV::QC_E_ANDI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9976 { 19531 /* qc.e.beqi */, RISCV::QC_E_BEQI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9977 { 19541 /* qc.e.bgei */, RISCV::QC_E_BGEI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9978 { 19551 /* qc.e.bgeui */, RISCV::QC_E_BGEUI, Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm16NonZero, MCK_BareSImm13Lsb0 }, },
9979 { 19562 /* qc.e.blti */, RISCV::QC_E_BLTI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9980 { 19572 /* qc.e.bltui */, RISCV::QC_E_BLTUI, Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm16NonZero, MCK_BareSImm13Lsb0 }, },
9981 { 19583 /* qc.e.bnei */, RISCV::QC_E_BNEI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9982 { 19593 /* qc.e.j */, RISCV::QC_E_J, Convert__BareSImm32Lsb01_0, AMFBS_HasVendorXqcilb_IsRV32, { MCK_BareSImm32Lsb0 }, },
9983 { 19600 /* qc.e.jal */, RISCV::QC_E_JAL, Convert__BareSImm32Lsb01_0, AMFBS_HasVendorXqcilb_IsRV32, { MCK_BareSImm32Lsb0 }, },
9984 { 19609 /* qc.e.lb */, RISCV::PseudoQC_E_LB, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_BareSymbol }, },
9985 { 19609 /* qc.e.lb */, RISCV::QC_E_LB, Convert__Reg1_0__Reg1_3__OptionalSImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_OptionalSImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9986 { 19617 /* qc.e.lbu */, RISCV::PseudoQC_E_LBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_BareSymbol }, },
9987 { 19617 /* qc.e.lbu */, RISCV::QC_E_LBU, Convert__Reg1_0__Reg1_3__OptionalSImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_OptionalSImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9988 { 19626 /* qc.e.lh */, RISCV::PseudoQC_E_LH, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_BareSymbol }, },
9989 { 19626 /* qc.e.lh */, RISCV::QC_E_LH, Convert__Reg1_0__Reg1_3__OptionalSImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_OptionalSImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9990 { 19634 /* qc.e.lhu */, RISCV::PseudoQC_E_LHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_BareSymbol }, },
9991 { 19634 /* qc.e.lhu */, RISCV::QC_E_LHU, Convert__Reg1_0__Reg1_3__OptionalSImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_OptionalSImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9992 { 19643 /* qc.e.li */, RISCV::QC_E_LI, Convert__Reg1_0__BareSImm321_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9993 { 19643 /* qc.e.li */, RISCV::ADDI, Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbolQC_E_LI }, },
9994 { 19651 /* qc.e.lw */, RISCV::PseudoQC_E_LW, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_BareSymbol }, },
9995 { 19651 /* qc.e.lw */, RISCV::QC_E_LW, Convert__Reg1_0__Reg1_3__OptionalSImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_OptionalSImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9996 { 19659 /* qc.e.orai */, RISCV::QC_E_ORAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9997 { 19669 /* qc.e.ori */, RISCV::QC_E_ORI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9998 { 19678 /* qc.e.sb */, RISCV::PseudoQC_E_SB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPRNoX0 }, },
9999 { 19678 /* qc.e.sb */, RISCV::QC_E_SB, Convert__Reg1_0__Reg1_3__OptionalSImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_OptionalSImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
10000 { 19686 /* qc.e.sh */, RISCV::PseudoQC_E_SH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPRNoX0 }, },
10001 { 19686 /* qc.e.sh */, RISCV::QC_E_SH, Convert__Reg1_0__Reg1_3__OptionalSImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_OptionalSImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
10002 { 19694 /* qc.e.sw */, RISCV::PseudoQC_E_SW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPRNoX0 }, },
10003 { 19694 /* qc.e.sw */, RISCV::QC_E_SW, Convert__Reg1_0__Reg1_3__OptionalSImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_OptionalSImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
10004 { 19702 /* qc.e.xorai */, RISCV::QC_E_XORAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
10005 { 19713 /* qc.e.xori */, RISCV::QC_E_XORI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
10006 { 19723 /* qc.expand2 */, RISCV::QC_EXPAND2, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
10007 { 19734 /* qc.expand3 */, RISCV::QC_EXPAND3, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
10008 { 19745 /* qc.ext */, RISCV::QC_EXT, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5Plus1, MCK_UImm5 }, },
10009 { 19752 /* qc.extd */, RISCV::QC_EXTD, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_UImm5Plus1, MCK_UImm5 }, },
10010 { 19760 /* qc.extdpr */, RISCV::QC_EXTDPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
10011 { 19770 /* qc.extdprh */, RISCV::QC_EXTDPRH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
10012 { 19781 /* qc.extdr */, RISCV::QC_EXTDR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
10013 { 19790 /* qc.extdu */, RISCV::QC_EXTDU, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_UImm5Plus1, MCK_UImm5 }, },
10014 { 19799 /* qc.extdupr */, RISCV::QC_EXTDUPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
10015 { 19810 /* qc.extduprh */, RISCV::QC_EXTDUPRH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
10016 { 19822 /* qc.extdur */, RISCV::QC_EXTDUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
10017 { 19832 /* qc.extu */, RISCV::QC_EXTU, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5Plus1, MCK_UImm5 }, },
10018 { 19840 /* qc.insb */, RISCV::QC_INSB, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_UImm5Plus1, MCK_UImm5 }, },
10019 { 19848 /* qc.insbh */, RISCV::QC_INSBH, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_UImm5Plus1, MCK_UImm5 }, },
10020 { 19857 /* qc.insbhr */, RISCV::QC_INSBHR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
10021 { 19867 /* qc.insbi */, RISCV::QC_INSBI, Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_UImm5Plus1, MCK_UImm5 }, },
10022 { 19876 /* qc.insbpr */, RISCV::QC_INSBPR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
10023 { 19886 /* qc.insbprh */, RISCV::QC_INSBPRH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
10024 { 19897 /* qc.insbr */, RISCV::QC_INSBR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
10025 { 19906 /* qc.insbri */, RISCV::QC_INSBRI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm11 }, },
10026 { 19916 /* qc.inw */, RISCV::QC_INW, Convert__Reg1_0__Reg1_3__OptionalUImm14Lsb001_1, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPR, MCK_OptionalUImm14Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
10027 { 19923 /* qc.li */, RISCV::QC_LI, Convert__Reg1_0__SImm20LI1_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_SImm20LI }, },
10028 { 19929 /* qc.lieq */, RISCV::QC_LIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
10029 { 19937 /* qc.lieqi */, RISCV::QC_LIEQI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
10030 { 19946 /* qc.lige */, RISCV::QC_LIGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
10031 { 19954 /* qc.ligei */, RISCV::QC_LIGEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
10032 { 19963 /* qc.ligeu */, RISCV::QC_LIGEU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
10033 { 19972 /* qc.ligeui */, RISCV::QC_LIGEUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_SImm5 }, },
10034 { 19982 /* qc.lilt */, RISCV::QC_LILT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
10035 { 19990 /* qc.lilti */, RISCV::QC_LILTI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
10036 { 19999 /* qc.liltu */, RISCV::QC_LILTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
10037 { 20008 /* qc.liltui */, RISCV::QC_LILTUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_SImm5 }, },
10038 { 20018 /* qc.line */, RISCV::QC_LINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
10039 { 20026 /* qc.linei */, RISCV::QC_LINEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
10040 { 20035 /* qc.lrb */, RISCV::QC_LRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
10041 { 20042 /* qc.lrbu */, RISCV::QC_LRBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
10042 { 20050 /* qc.lrh */, RISCV::QC_LRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
10043 { 20057 /* qc.lrhu */, RISCV::QC_LRHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
10044 { 20065 /* qc.lrw */, RISCV::QC_LRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
10045 { 20072 /* qc.lwm */, RISCV::QC_LWM, Convert__Reg1_0__Reg1_4__Reg1_1__OptionalUImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
10046 { 20079 /* qc.lwmi */, RISCV::QC_LWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__OptionalUImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
10047 { 20087 /* qc.muliadd */, RISCV::QC_MULIADD, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm12LO }, },
10048 { 20098 /* qc.mveq */, RISCV::QC_MVEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10049 { 20106 /* qc.mveqi */, RISCV::QC_MVEQI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
10050 { 20115 /* qc.mvge */, RISCV::QC_MVGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10051 { 20123 /* qc.mvgei */, RISCV::QC_MVGEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
10052 { 20132 /* qc.mvgeu */, RISCV::QC_MVGEU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10053 { 20141 /* qc.mvgeui */, RISCV::QC_MVGEUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_GPRNoX0 }, },
10054 { 20151 /* qc.mvlt */, RISCV::QC_MVLT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10055 { 20159 /* qc.mvlti */, RISCV::QC_MVLTI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
10056 { 20168 /* qc.mvltu */, RISCV::QC_MVLTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10057 { 20177 /* qc.mvltui */, RISCV::QC_MVLTUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_GPRNoX0 }, },
10058 { 20187 /* qc.mvne */, RISCV::QC_MVNE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10059 { 20195 /* qc.mvnei */, RISCV::QC_MVNEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
10060 { 20204 /* qc.norm */, RISCV::QC_NORM, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
10061 { 20212 /* qc.normeu */, RISCV::QC_NORMEU, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
10062 { 20222 /* qc.normu */, RISCV::QC_NORMU, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
10063 { 20231 /* qc.outw */, RISCV::QC_OUTW, Convert__Reg1_0__Reg1_3__OptionalUImm14Lsb001_1, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPR, MCK_OptionalUImm14Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
10064 { 20239 /* qc.pcoredump */, RISCV::SLTI, Convert__regX0__regX0__imm_95_1536, AMFBS_HasVendorXqcisim_IsRV32, { }, },
10065 { 20252 /* qc.pexit */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1280, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
10066 { 20261 /* qc.ppreg */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_2048, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
10067 { 20270 /* qc.ppregs */, RISCV::SLTI, Convert__regX0__regX0__imm_95_1792, AMFBS_HasVendorXqcisim_IsRV32, { }, },
10068 { 20280 /* qc.pputc */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1792, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
10069 { 20289 /* qc.pputci */, RISCV::QC_PPUTCI, Convert__UImm81_0, AMFBS_HasVendorXqcisim_IsRV32, { MCK_UImm8 }, },
10070 { 20299 /* qc.pputs */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1536, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
10071 { 20308 /* qc.psyscall */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1024, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
10072 { 20320 /* qc.psyscalli */, RISCV::SLTI, Convert__regX0__regX0__UImm101_0, AMFBS_HasVendorXqcisim_IsRV32, { MCK_UImm10 }, },
10073 { 20333 /* qc.selecteqi */, RISCV::QC_SELECTEQI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10074 { 20346 /* qc.selectieq */, RISCV::QC_SELECTIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
10075 { 20359 /* qc.selectieqi */, RISCV::QC_SELECTIEQI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_SImm5 }, },
10076 { 20373 /* qc.selectiieq */, RISCV::QC_SELECTIIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
10077 { 20387 /* qc.selectiine */, RISCV::QC_SELECTIINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
10078 { 20401 /* qc.selectine */, RISCV::QC_SELECTINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
10079 { 20414 /* qc.selectinei */, RISCV::QC_SELECTINEI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_SImm5 }, },
10080 { 20428 /* qc.selectnei */, RISCV::QC_SELECTNEI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10081 { 20441 /* qc.setinti */, RISCV::QC_SETINTI, Convert__UImm101_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_UImm10 }, },
10082 { 20452 /* qc.setwm */, RISCV::QC_SETWM, Convert__Reg1_0__Reg1_4__Reg1_1__OptionalUImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_GPRNoX0, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
10083 { 20461 /* qc.setwmi */, RISCV::QC_SETWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__OptionalUImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_UImm5NonZero, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
10084 { 20471 /* qc.shladd */, RISCV::QC_SHLADD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5GT3 }, },
10085 { 20481 /* qc.shlsat */, RISCV::QC_SHLSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10086 { 20491 /* qc.shlusat */, RISCV::QC_SHLUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10087 { 20502 /* qc.srb */, RISCV::QC_SRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
10088 { 20509 /* qc.srh */, RISCV::QC_SRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
10089 { 20516 /* qc.srw */, RISCV::QC_SRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
10090 { 20523 /* qc.subsat */, RISCV::QC_SUBSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10091 { 20533 /* qc.subusat */, RISCV::QC_SUBUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
10092 { 20544 /* qc.swm */, RISCV::QC_SWM, Convert__Reg1_0__Reg1_4__Reg1_1__OptionalUImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
10093 { 20551 /* qc.swmi */, RISCV::QC_SWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__OptionalUImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_OptionalUImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
10094 { 20559 /* qc.sync */, RISCV::QC_SYNC, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
10095 { 20567 /* qc.syncr */, RISCV::QC_SYNCR, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
10096 { 20576 /* qc.syncwf */, RISCV::QC_SYNCWF, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
10097 { 20586 /* qc.syncwl */, RISCV::QC_SYNCWL, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
10098 { 20596 /* qc.wrap */, RISCV::QC_WRAP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
10099 { 20604 /* qc.wrapi */, RISCV::QC_WRAPI, Convert__Reg1_0__Reg1_1__UImm111_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm11 }, },
10100 { 20613 /* qk.c.lbu */, RISCV::QK_C_LBU, Convert__Reg1_0__Reg1_3__OptionalUImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_OptionalUImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
10101 { 20622 /* qk.c.lbusp */, RISCV::QK_C_LBUSP, Convert__Reg1_0__Reg1_3__OptionalUImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_OptionalUImm4, MCK__40_, MCK_SP, MCK__41_ }, },
10102 { 20633 /* qk.c.lhu */, RISCV::QK_C_LHU, Convert__Reg1_0__Reg1_3__OptionalUImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_OptionalUImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
10103 { 20642 /* qk.c.lhusp */, RISCV::QK_C_LHUSP, Convert__Reg1_0__Reg1_3__OptionalUImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_OptionalUImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
10104 { 20653 /* qk.c.sb */, RISCV::QK_C_SB, Convert__Reg1_0__Reg1_3__OptionalUImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_OptionalUImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
10105 { 20661 /* qk.c.sbsp */, RISCV::QK_C_SBSP, Convert__Reg1_0__Reg1_3__OptionalUImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_OptionalUImm4, MCK__40_, MCK_SP, MCK__41_ }, },
10106 { 20671 /* qk.c.sh */, RISCV::QK_C_SH, Convert__Reg1_0__Reg1_3__OptionalUImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_OptionalUImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
10107 { 20679 /* qk.c.shsp */, RISCV::QK_C_SHSP, Convert__Reg1_0__Reg1_3__OptionalUImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_OptionalUImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
10108 { 20689 /* rdcycle */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3072__regX0, AMFBS_None, { MCK_GPR }, },
10109 { 20697 /* rdcycleh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3200__regX0, AMFBS_IsRV32, { MCK_GPR }, },
10110 { 20706 /* rdinstret */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3074__regX0, AMFBS_None, { MCK_GPR }, },
10111 { 20716 /* rdinstreth */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3202__regX0, AMFBS_IsRV32, { MCK_GPR }, },
10112 { 20727 /* rdtime */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3073__regX0, AMFBS_None, { MCK_GPR }, },
10113 { 20734 /* rdtimeh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3201__regX0, AMFBS_IsRV32, { MCK_GPR }, },
10114 { 20742 /* rem */, RISCV::REM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10115 { 20746 /* remu */, RISCV::REMU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10116 { 20751 /* remuw */, RISCV::REMUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10117 { 20757 /* remw */, RISCV::REMW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10118 { 20762 /* ret */, RISCV::JALR, Convert__regX0__regX1__imm_95_0, AMFBS_None, { }, },
10119 { 20766 /* rev */, RISCV::REV_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
10120 { 20766 /* rev */, RISCV::REV_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
10121 { 20770 /* rev16 */, RISCV::REV16_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
10122 { 20776 /* rev8 */, RISCV::REV8_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
10123 { 20776 /* rev8 */, RISCV::REV8_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR }, },
10124 { 20781 /* rol */, RISCV::ROL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10125 { 20785 /* rolw */, RISCV::ROLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10126 { 20790 /* ror */, RISCV::ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10127 { 20790 /* ror */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10128 { 20794 /* rori */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10129 { 20799 /* roriw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10130 { 20805 /* rorw */, RISCV::RORW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10131 { 20805 /* rorw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10132 { 20810 /* sadd */, RISCV::SADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10133 { 20815 /* saddu */, RISCV::SADDU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10134 { 20821 /* sati */, RISCV::SATI_RV32, Convert__Reg1_0__Reg1_1__UImm5Plus11_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5Plus1 }, },
10135 { 20821 /* sati */, RISCV::SATI_RV64, Convert__Reg1_0__Reg1_1__UImm6Plus11_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6Plus1 }, },
10136 { 20826 /* sb */, RISCV::PseudoSB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPRNoX0 }, },
10137 { 20826 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
10138 { 20826 /* sb */, RISCV::PseudoQCAccessSB, Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_OptionalSImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
10139 { 20829 /* sb.aqrl */, RISCV::SB_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10140 { 20837 /* sb.rl */, RISCV::SB_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10141 { 20843 /* sc.d */, RISCV::SC_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10142 { 20848 /* sc.d.aq */, RISCV::SC_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10143 { 20856 /* sc.d.aqrl */, RISCV::SC_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10144 { 20866 /* sc.d.rl */, RISCV::SC_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10145 { 20874 /* sc.w */, RISCV::SC_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10146 { 20879 /* sc.w.aq */, RISCV::SC_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10147 { 20887 /* sc.w.aqrl */, RISCV::SC_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10148 { 20897 /* sc.w.rl */, RISCV::SC_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10149 { 20905 /* scspspop */, RISCV::SCSPSPOP, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSscsps, { MCK_SP, MCK_SP }, },
10150 { 20914 /* scspspush */, RISCV::SCSPSPUSH, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSscsps, { MCK_SP, MCK_SP }, },
10151 { 20924 /* sctrclr */, RISCV::SCTRCLR, Convert_NoOperands, AMFBS_HasStdExtSmctrOrSsctr, { }, },
10152 { 20932 /* sd */, RISCV::PseudoSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol, MCK_GPRNoX0 }, },
10153 { 20932 /* sd */, RISCV::PseudoSD_RV32, Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_BareSymbol, MCK_GPRNoX0 }, },
10154 { 20932 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
10155 { 20932 /* sd */, RISCV::SD_RV32, Convert__GPRPairRV321_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
10156 { 20935 /* sd.aqrl */, RISCV::SD_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10157 { 20943 /* sd.rl */, RISCV::SD_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10158 { 20949 /* seqz */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__imm_95_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10159 { 20954 /* sext.b */, RISCV::SEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
10160 { 20954 /* sext.b */, RISCV::PseudoSEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10161 { 20961 /* sext.h */, RISCV::SEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
10162 { 20961 /* sext.h */, RISCV::PseudoSEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10163 { 20968 /* sext.w */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
10164 { 20975 /* sf.cdiscard.d.l1 */, RISCV::SF_CDISCARD_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecdiscarddlone, { }, },
10165 { 20975 /* sf.cdiscard.d.l1 */, RISCV::SF_CDISCARD_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecdiscarddlone, { MCK_GPR }, },
10166 { 20992 /* sf.cease */, RISCV::SF_CEASE, Convert_NoOperands, AMFBS_HasVendorXSfcease, { }, },
10167 { 21001 /* sf.cflush.d.l1 */, RISCV::SF_CFLUSH_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecflushdlone, { }, },
10168 { 21001 /* sf.cflush.d.l1 */, RISCV::SF_CFLUSH_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecflushdlone, { MCK_GPR }, },
10169 { 21016 /* sf.mm.e4m3.e4m3 */, RISCV::SF_MM_E4M3_E4M3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
10170 { 21032 /* sf.mm.e4m3.e5m2 */, RISCV::SF_MM_E4M3_E5M2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
10171 { 21048 /* sf.mm.e5m2.e4m3 */, RISCV::SF_MM_E5M2_E4M3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
10172 { 21064 /* sf.mm.e5m2.e5m2 */, RISCV::SF_MM_E5M2_E5M2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
10173 { 21080 /* sf.mm.f.f */, RISCV::SF_MM_F_F, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f, { MCK_TRM2, MCK_VR, MCK_VR }, },
10174 { 21090 /* sf.mm.s.s */, RISCV::SF_MM_S_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
10175 { 21100 /* sf.mm.s.u */, RISCV::SF_MM_S_U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
10176 { 21110 /* sf.mm.u.s */, RISCV::SF_MM_U_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
10177 { 21120 /* sf.mm.u.u */, RISCV::SF_MM_U_U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
10178 { 21130 /* sf.vc.fv */, RISCV::SF_VC_FV, Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_UImm5, MCK_VR, MCK_FPR32 }, },
10179 { 21139 /* sf.vc.fvv */, RISCV::SF_VC_FVV, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
10180 { 21149 /* sf.vc.fvw */, RISCV::SF_VC_FVW, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
10181 { 21159 /* sf.vc.i */, RISCV::SF_VC_I, Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_SImm5 }, },
10182 { 21167 /* sf.vc.iv */, RISCV::SF_VC_IV, Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_SImm5 }, },
10183 { 21176 /* sf.vc.ivv */, RISCV::SF_VC_IVV, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
10184 { 21186 /* sf.vc.ivw */, RISCV::SF_VC_IVW, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
10185 { 21196 /* sf.vc.v.fv */, RISCV::SF_VC_V_FV, Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
10186 { 21207 /* sf.vc.v.fvv */, RISCV::SF_VC_V_FVV, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
10187 { 21219 /* sf.vc.v.fvw */, RISCV::SF_VC_V_FVW, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
10188 { 21231 /* sf.vc.v.i */, RISCV::SF_VC_V_I, Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_SImm5 }, },
10189 { 21241 /* sf.vc.v.iv */, RISCV::SF_VC_V_IV, Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
10190 { 21252 /* sf.vc.v.ivv */, RISCV::SF_VC_V_IVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
10191 { 21264 /* sf.vc.v.ivw */, RISCV::SF_VC_V_IVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
10192 { 21276 /* sf.vc.v.vv */, RISCV::SF_VC_V_VV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
10193 { 21287 /* sf.vc.v.vvv */, RISCV::SF_VC_V_VVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
10194 { 21299 /* sf.vc.v.vvw */, RISCV::SF_VC_V_VVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
10195 { 21311 /* sf.vc.v.x */, RISCV::SF_VC_V_X, Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_GPR }, },
10196 { 21321 /* sf.vc.v.xv */, RISCV::SF_VC_V_XV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
10197 { 21332 /* sf.vc.v.xvv */, RISCV::SF_VC_V_XVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
10198 { 21344 /* sf.vc.v.xvw */, RISCV::SF_VC_V_XVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
10199 { 21356 /* sf.vc.vv */, RISCV::SF_VC_VV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_VR }, },
10200 { 21365 /* sf.vc.vvv */, RISCV::SF_VC_VVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
10201 { 21375 /* sf.vc.vvw */, RISCV::SF_VC_VVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
10202 { 21385 /* sf.vc.x */, RISCV::SF_VC_X, Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_GPR }, },
10203 { 21393 /* sf.vc.xv */, RISCV::SF_VC_XV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_GPR }, },
10204 { 21402 /* sf.vc.xvv */, RISCV::SF_VC_XVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
10205 { 21412 /* sf.vc.xvw */, RISCV::SF_VC_XVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
10206 { 21422 /* sf.vfexp.v */, RISCV::SF_VFEXP_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXSfvfexpAny, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10207 { 21433 /* sf.vfexpa.v */, RISCV::SF_VFEXPA_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXSfvfexpa, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10208 { 21445 /* sf.vfnrclip.x.f.qf */, RISCV::SF_VFNRCLIP_X_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10209 { 21464 /* sf.vfnrclip.xu.f.qf */, RISCV::SF_VFNRCLIP_XU_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10210 { 21484 /* sf.vfwmacc.4x4x4 */, RISCV::SF_VFWMACC_4x4x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvfwmaccqqq, { MCK_VR, MCK_VR, MCK_VR }, },
10211 { 21501 /* sf.vlte16 */, RISCV::SF_VLTE16, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10212 { 21511 /* sf.vlte32 */, RISCV::SF_VLTE32, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10213 { 21521 /* sf.vlte64 */, RISCV::SF_VLTE64, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10214 { 21531 /* sf.vlte8 */, RISCV::SF_VLTE8, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10215 { 21540 /* sf.vqmacc.2x8x2 */, RISCV::SF_VQMACC_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
10216 { 21556 /* sf.vqmacc.4x8x4 */, RISCV::SF_VQMACC_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
10217 { 21572 /* sf.vqmaccsu.2x8x2 */, RISCV::SF_VQMACCSU_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
10218 { 21590 /* sf.vqmaccsu.4x8x4 */, RISCV::SF_VQMACCSU_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
10219 { 21608 /* sf.vqmaccu.2x8x2 */, RISCV::SF_VQMACCU_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
10220 { 21625 /* sf.vqmaccu.4x8x4 */, RISCV::SF_VQMACCU_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
10221 { 21642 /* sf.vqmaccus.2x8x2 */, RISCV::SF_VQMACCUS_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
10222 { 21660 /* sf.vqmaccus.4x8x4 */, RISCV::SF_VQMACCUS_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
10223 { 21678 /* sf.vsettk */, RISCV::SF_VSETTK, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
10224 { 21688 /* sf.vsettm */, RISCV::SF_VSETTM, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
10225 { 21698 /* sf.vsettn */, RISCV::SF_VSETTN, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
10226 { 21708 /* sf.vsettnt */, RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__XSfmmVType1_2, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR, MCK_XSfmmVType }, },
10227 { 21719 /* sf.vste16 */, RISCV::SF_VSTE16, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10228 { 21729 /* sf.vste32 */, RISCV::SF_VSTE32, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10229 { 21739 /* sf.vste64 */, RISCV::SF_VSTE64, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10230 { 21749 /* sf.vste8 */, RISCV::SF_VSTE8, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10231 { 21758 /* sf.vtdiscard */, RISCV::SF_VTDISCARD, Convert_NoOperands, AMFBS_HasVendorXSfmmbase, { }, },
10232 { 21771 /* sf.vtmv.t.v */, RISCV::SF_VTMV_T_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_VR }, },
10233 { 21783 /* sf.vtmv.v.t */, RISCV::SF_VTMV_V_T, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_VR, MCK_GPR }, },
10234 { 21795 /* sf.vtzero.t */, RISCV::SF_VTZERO_T, Convert__Reg1_0, AMFBS_HasVendorXSfmmbase, { MCK_TR }, },
10235 { 21807 /* sfence.inval.ir */, RISCV::SFENCE_INVAL_IR, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
10236 { 21823 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__regX0__regX0, AMFBS_None, { }, },
10237 { 21823 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
10238 { 21823 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10239 { 21834 /* sfence.w.inval */, RISCV::SFENCE_W_INVAL, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
10240 { 21849 /* sgt */, RISCV::SLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10241 { 21853 /* sgtu */, RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10242 { 21858 /* sgtz */, RISCV::SLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10243 { 21863 /* sh */, RISCV::PseudoSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPRNoX0 }, },
10244 { 21863 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
10245 { 21863 /* sh */, RISCV::PseudoQCAccessSH, Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_OptionalSImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
10246 { 21866 /* sh.aqrl */, RISCV::SH_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10247 { 21874 /* sh.rl */, RISCV::SH_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10248 { 21880 /* sh1add */, RISCV::SH1ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10249 { 21887 /* sh1add.uw */, RISCV::SH1ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10250 { 21897 /* sh2add */, RISCV::SH2ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10251 { 21904 /* sh2add.uw */, RISCV::SH2ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10252 { 21914 /* sh3add */, RISCV::SH3ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10253 { 21921 /* sh3add.uw */, RISCV::SH3ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10254 { 21931 /* sha */, RISCV::SHA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10255 { 21935 /* sha256sig0 */, RISCV::SHA256SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
10256 { 21946 /* sha256sig1 */, RISCV::SHA256SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
10257 { 21957 /* sha256sum0 */, RISCV::SHA256SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
10258 { 21968 /* sha256sum1 */, RISCV::SHA256SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
10259 { 21979 /* sha512sig0 */, RISCV::SHA512SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
10260 { 21990 /* sha512sig0h */, RISCV::SHA512SIG0H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10261 { 22002 /* sha512sig0l */, RISCV::SHA512SIG0L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10262 { 22014 /* sha512sig1 */, RISCV::SHA512SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
10263 { 22025 /* sha512sig1h */, RISCV::SHA512SIG1H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10264 { 22037 /* sha512sig1l */, RISCV::SHA512SIG1L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10265 { 22049 /* sha512sum0 */, RISCV::SHA512SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
10266 { 22060 /* sha512sum0r */, RISCV::SHA512SUM0R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10267 { 22072 /* sha512sum1 */, RISCV::SHA512SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
10268 { 22083 /* sha512sum1r */, RISCV::SHA512SUM1R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10269 { 22095 /* shar */, RISCV::SHAR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10270 { 22100 /* shl */, RISCV::SHL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10271 { 22104 /* shlr */, RISCV::SHLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10272 { 22109 /* sinval.vma */, RISCV::SINVAL_VMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
10273 { 22120 /* sipopret */, RISCV::SIPOPRET, Convert_NoOperands, AMFBS_HasStdExtSsip, { }, },
10274 { 22129 /* sll */, RISCV::SLL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10275 { 22129 /* sll */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10276 { 22133 /* slli */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10277 { 22138 /* slli.uw */, RISCV::SLLI_UW, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10278 { 22146 /* slliw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10279 { 22152 /* sllw */, RISCV::SLLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10280 { 22152 /* sllw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10281 { 22157 /* slt */, RISCV::SLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10282 { 22157 /* slt */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10283 { 22161 /* slti */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10284 { 22166 /* sltiu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10285 { 22172 /* sltu */, RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10286 { 22172 /* sltu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10287 { 22177 /* sltz */, RISCV::SLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10288 { 22182 /* slx */, RISCV::SLX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10289 { 22186 /* sm3p0 */, RISCV::SM3P0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
10290 { 22192 /* sm3p1 */, RISCV::SM3P1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
10291 { 22198 /* sm4ed */, RISCV::SM4ED, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10292 { 22204 /* sm4ks */, RISCV::SM4KS, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10293 { 22210 /* smt.vfwmadot */, RISCV::VFWMADOT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
10294 { 22223 /* smt.vfwmadot1 */, RISCV::VFWMADOT1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10295 { 22237 /* smt.vfwmadot2 */, RISCV::VFWMADOT2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10296 { 22251 /* smt.vfwmadot3 */, RISCV::VFWMADOT3, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10297 { 22265 /* smt.vmadot */, RISCV::SMT_VMADOT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
10298 { 22265 /* smt.vmadot */, RISCV::VMADOT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_SMTVType }, },
10299 { 22276 /* smt.vmadot.hp */, RISCV::VMADOT_HP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_VR, MCK_UImm3, MCK_SMTVType }, },
10300 { 22290 /* smt.vmadot.sp */, RISCV::VMADOT_SP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2, MCK_SMTVType }, },
10301 { 22304 /* smt.vmadot1 */, RISCV::SMT_VMADOT1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10302 { 22304 /* smt.vmadot1 */, RISCV::VMADOT1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10303 { 22316 /* smt.vmadot1su */, RISCV::SMT_VMADOT1SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10304 { 22316 /* smt.vmadot1su */, RISCV::VMADOT1SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10305 { 22330 /* smt.vmadot1u */, RISCV::SMT_VMADOT1U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10306 { 22330 /* smt.vmadot1u */, RISCV::VMADOT1U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10307 { 22343 /* smt.vmadot1us */, RISCV::SMT_VMADOT1US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10308 { 22343 /* smt.vmadot1us */, RISCV::VMADOT1US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10309 { 22357 /* smt.vmadot2 */, RISCV::SMT_VMADOT2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10310 { 22357 /* smt.vmadot2 */, RISCV::VMADOT2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10311 { 22369 /* smt.vmadot2su */, RISCV::SMT_VMADOT2SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10312 { 22369 /* smt.vmadot2su */, RISCV::VMADOT2SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10313 { 22383 /* smt.vmadot2u */, RISCV::SMT_VMADOT2U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10314 { 22383 /* smt.vmadot2u */, RISCV::VMADOT2U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10315 { 22396 /* smt.vmadot2us */, RISCV::SMT_VMADOT2US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10316 { 22396 /* smt.vmadot2us */, RISCV::VMADOT2US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10317 { 22410 /* smt.vmadot3 */, RISCV::SMT_VMADOT3, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10318 { 22410 /* smt.vmadot3 */, RISCV::VMADOT3, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10319 { 22422 /* smt.vmadot3su */, RISCV::SMT_VMADOT3SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10320 { 22422 /* smt.vmadot3su */, RISCV::VMADOT3SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10321 { 22436 /* smt.vmadot3u */, RISCV::SMT_VMADOT3U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10322 { 22436 /* smt.vmadot3u */, RISCV::VMADOT3U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10323 { 22449 /* smt.vmadot3us */, RISCV::SMT_VMADOT3US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
10324 { 22449 /* smt.vmadot3us */, RISCV::VMADOT3US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTI81_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_SMTI8 }, },
10325 { 22463 /* smt.vmadotsu */, RISCV::SMT_VMADOTSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
10326 { 22463 /* smt.vmadotsu */, RISCV::VMADOTSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_SMTVType }, },
10327 { 22476 /* smt.vmadotsu.hp */, RISCV::VMADOTSU_HP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_VR, MCK_UImm3, MCK_SMTVType }, },
10328 { 22492 /* smt.vmadotsu.sp */, RISCV::VMADOTSU_SP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2, MCK_SMTVType }, },
10329 { 22508 /* smt.vmadotu */, RISCV::SMT_VMADOTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
10330 { 22508 /* smt.vmadotu */, RISCV::VMADOTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_SMTVType }, },
10331 { 22520 /* smt.vmadotu.hp */, RISCV::VMADOTU_HP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_VR, MCK_UImm3, MCK_SMTVType }, },
10332 { 22535 /* smt.vmadotu.sp */, RISCV::VMADOTU_SP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2, MCK_SMTVType }, },
10333 { 22550 /* smt.vmadotus */, RISCV::SMT_VMADOTUS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
10334 { 22550 /* smt.vmadotus */, RISCV::VMADOTUS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SMTVType1_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_SMTVType }, },
10335 { 22563 /* smt.vmadotus.hp */, RISCV::VMADOTUS_HP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm31_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_VR, MCK_UImm3, MCK_SMTVType }, },
10336 { 22579 /* smt.vmadotus.sp */, RISCV::VMADOTUS_SP, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3__UImm21_4__SMTVType1_5, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2, MCK_SMTVType }, },
10337 { 22595 /* smt.vnpack.vv */, RISCV::VNPACK_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_UImm2 }, },
10338 { 22609 /* smt.vnpack4.vv */, RISCV::VNPACK4_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_UImm2 }, },
10339 { 22624 /* smt.vnspack.vv */, RISCV::VNSPACK_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_UImm2 }, },
10340 { 22639 /* smt.vnspack4.vv */, RISCV::VNSPACK4_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VR, MCK_VR, MCK_VR, MCK_UImm2 }, },
10341 { 22655 /* smt.vpack.vv */, RISCV::VPACK_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2 }, },
10342 { 22668 /* smt.vupack.vv */, RISCV::VUPACK_VV, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXSMTVDotII_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR, MCK_UImm2 }, },
10343 { 22682 /* snez */, RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10344 { 22687 /* sra */, RISCV::SRA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10345 { 22687 /* sra */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10346 { 22691 /* srai */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10347 { 22696 /* sraiw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10348 { 22702 /* srari */, RISCV::SRARI_RV32, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10349 { 22702 /* srari */, RISCV::SRARI_RV64, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
10350 { 22708 /* sraw */, RISCV::SRAW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10351 { 22708 /* sraw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10352 { 22713 /* sret */, RISCV::SRET, Convert_NoOperands, AMFBS_None, { }, },
10353 { 22718 /* srl */, RISCV::SRL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10354 { 22718 /* srl */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10355 { 22722 /* srli */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10356 { 22727 /* srliw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10357 { 22733 /* srlw */, RISCV::SRLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10358 { 22733 /* srlw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10359 { 22738 /* srx */, RISCV::SRX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10360 { 22742 /* ssamoswap.d */, RISCV::SSAMOSWAP_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10361 { 22754 /* ssamoswap.d.aq */, RISCV::SSAMOSWAP_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10362 { 22769 /* ssamoswap.d.aqrl */, RISCV::SSAMOSWAP_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10363 { 22786 /* ssamoswap.d.rl */, RISCV::SSAMOSWAP_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10364 { 22801 /* ssamoswap.w */, RISCV::SSAMOSWAP_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10365 { 22813 /* ssamoswap.w.aq */, RISCV::SSAMOSWAP_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10366 { 22828 /* ssamoswap.w.aqrl */, RISCV::SSAMOSWAP_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10367 { 22845 /* ssamoswap.w.rl */, RISCV::SSAMOSWAP_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10368 { 22860 /* ssh1sadd */, RISCV::SSH1SADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10369 { 22869 /* ssha */, RISCV::SSHA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10370 { 22874 /* sshar */, RISCV::SSHAR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10371 { 22880 /* sshl */, RISCV::SSHL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10372 { 22885 /* sshlr */, RISCV::SSHLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10373 { 22891 /* sslai */, RISCV::SSLAI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10374 { 22897 /* sspopchk */, RISCV::SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRX1X5 }, },
10375 { 22906 /* sspush */, RISCV::SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRX1X5 }, },
10376 { 22913 /* ssrdp */, RISCV::SSRDP, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRNoX0 }, },
10377 { 22919 /* ssub */, RISCV::SSUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10378 { 22924 /* ssubu */, RISCV::SSUBU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10379 { 22930 /* sub */, RISCV::SUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10380 { 22934 /* subd */, RISCV::SUBD, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
10381 { 22939 /* subw */, RISCV::SUBW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10382 { 22944 /* sw */, RISCV::PseudoSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPRNoX0 }, },
10383 { 22944 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_3__OptionalSImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_OptionalSImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
10384 { 22944 /* sw */, RISCV::PseudoQCAccessSW, Convert__Reg1_0__Reg1_3__OptionalSImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_OptionalSImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
10385 { 22947 /* sw.aqrl */, RISCV::SW_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10386 { 22955 /* sw.rl */, RISCV::SW_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
10387 { 22961 /* tail */, RISCV::PseudoTAIL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
10388 { 22961 /* tail */, RISCV::PseudoTAILReg, Convert__TailCallSymbol1_0__Reg1_1, AMFBS_None, { MCK_TailCallSymbol, MCK_GPR }, },
10389 { 22966 /* th.addsl */, RISCV::TH_ADDSL, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadBa, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10390 { 22975 /* th.dcache.call */, RISCV::TH_DCACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10391 { 22990 /* th.dcache.ciall */, RISCV::TH_DCACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10392 { 23006 /* th.dcache.cipa */, RISCV::TH_DCACHE_CIPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10393 { 23021 /* th.dcache.cisw */, RISCV::TH_DCACHE_CISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10394 { 23036 /* th.dcache.civa */, RISCV::TH_DCACHE_CIVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10395 { 23051 /* th.dcache.cpa */, RISCV::TH_DCACHE_CPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10396 { 23065 /* th.dcache.cpal1 */, RISCV::TH_DCACHE_CPAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10397 { 23081 /* th.dcache.csw */, RISCV::TH_DCACHE_CSW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10398 { 23095 /* th.dcache.cva */, RISCV::TH_DCACHE_CVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10399 { 23109 /* th.dcache.cval1 */, RISCV::TH_DCACHE_CVAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10400 { 23125 /* th.dcache.iall */, RISCV::TH_DCACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10401 { 23140 /* th.dcache.ipa */, RISCV::TH_DCACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10402 { 23154 /* th.dcache.isw */, RISCV::TH_DCACHE_ISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10403 { 23168 /* th.dcache.iva */, RISCV::TH_DCACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10404 { 23182 /* th.ext */, RISCV::TH_EXT, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
10405 { 23189 /* th.extu */, RISCV::TH_EXTU, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
10406 { 23197 /* th.ff0 */, RISCV::TH_FF0, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10407 { 23204 /* th.ff1 */, RISCV::TH_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10408 { 23211 /* th.flrd */, RISCV::TH_FLRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10409 { 23219 /* th.flrw */, RISCV::TH_FLRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10410 { 23227 /* th.flurd */, RISCV::TH_FLURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10411 { 23236 /* th.flurw */, RISCV::TH_FLURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10412 { 23245 /* th.fsrd */, RISCV::TH_FSRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10413 { 23253 /* th.fsrw */, RISCV::TH_FSRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10414 { 23261 /* th.fsurd */, RISCV::TH_FSURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10415 { 23270 /* th.fsurw */, RISCV::TH_FSURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10416 { 23279 /* th.icache.iall */, RISCV::TH_ICACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10417 { 23294 /* th.icache.ialls */, RISCV::TH_ICACHE_IALLS, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10418 { 23310 /* th.icache.ipa */, RISCV::TH_ICACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10419 { 23324 /* th.icache.iva */, RISCV::TH_ICACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
10420 { 23338 /* th.l2cache.call */, RISCV::TH_L2CACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10421 { 23354 /* th.l2cache.ciall */, RISCV::TH_L2CACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10422 { 23371 /* th.l2cache.iall */, RISCV::TH_L2CACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
10423 { 23387 /* th.lbia */, RISCV::TH_LBIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10424 { 23395 /* th.lbib */, RISCV::TH_LBIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10425 { 23403 /* th.lbuia */, RISCV::TH_LBUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10426 { 23412 /* th.lbuib */, RISCV::TH_LBUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10427 { 23421 /* th.ldd */, RISCV::TH_LDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmFour }, },
10428 { 23428 /* th.ldia */, RISCV::TH_LDIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10429 { 23436 /* th.ldib */, RISCV::TH_LDIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10430 { 23444 /* th.lhia */, RISCV::TH_LHIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10431 { 23452 /* th.lhib */, RISCV::TH_LHIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10432 { 23460 /* th.lhuia */, RISCV::TH_LHUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10433 { 23469 /* th.lhuib */, RISCV::TH_LHUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10434 { 23478 /* th.lrb */, RISCV::TH_LRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10435 { 23485 /* th.lrbu */, RISCV::TH_LRBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10436 { 23493 /* th.lrd */, RISCV::TH_LRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10437 { 23500 /* th.lrh */, RISCV::TH_LRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10438 { 23507 /* th.lrhu */, RISCV::TH_LRHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10439 { 23515 /* th.lrw */, RISCV::TH_LRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10440 { 23522 /* th.lrwu */, RISCV::TH_LRWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10441 { 23530 /* th.lurb */, RISCV::TH_LURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10442 { 23538 /* th.lurbu */, RISCV::TH_LURBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10443 { 23547 /* th.lurd */, RISCV::TH_LURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10444 { 23555 /* th.lurh */, RISCV::TH_LURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10445 { 23563 /* th.lurhu */, RISCV::TH_LURHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10446 { 23572 /* th.lurw */, RISCV::TH_LURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10447 { 23580 /* th.lurwu */, RISCV::TH_LURWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10448 { 23589 /* th.lwd */, RISCV::TH_LWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
10449 { 23596 /* th.lwia */, RISCV::TH_LWIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10450 { 23604 /* th.lwib */, RISCV::TH_LWIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10451 { 23612 /* th.lwud */, RISCV::TH_LWUD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
10452 { 23620 /* th.lwuia */, RISCV::TH_LWUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10453 { 23629 /* th.lwuib */, RISCV::TH_LWUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10454 { 23638 /* th.mula */, RISCV::TH_MULA, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10455 { 23646 /* th.mulah */, RISCV::TH_MULAH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10456 { 23655 /* th.mulaw */, RISCV::TH_MULAW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10457 { 23664 /* th.muls */, RISCV::TH_MULS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10458 { 23672 /* th.mulsh */, RISCV::TH_MULSH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10459 { 23681 /* th.mulsw */, RISCV::TH_MULSW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10460 { 23690 /* th.mveqz */, RISCV::TH_MVEQZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10461 { 23699 /* th.mvnez */, RISCV::TH_MVNEZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10462 { 23708 /* th.rev */, RISCV::TH_REV, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10463 { 23715 /* th.revw */, RISCV::TH_REVW, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR }, },
10464 { 23723 /* th.sbia */, RISCV::TH_SBIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10465 { 23731 /* th.sbib */, RISCV::TH_SBIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10466 { 23739 /* th.sdd */, RISCV::TH_SDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmFour }, },
10467 { 23746 /* th.sdia */, RISCV::TH_SDIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10468 { 23754 /* th.sdib */, RISCV::TH_SDIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10469 { 23762 /* th.sfence.vmas */, RISCV::TH_SFENCE_VMAS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadSync, { MCK_GPR, MCK_GPR }, },
10470 { 23777 /* th.shia */, RISCV::TH_SHIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10471 { 23785 /* th.shib */, RISCV::TH_SHIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10472 { 23793 /* th.srb */, RISCV::TH_SRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10473 { 23800 /* th.srd */, RISCV::TH_SRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10474 { 23807 /* th.srh */, RISCV::TH_SRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10475 { 23814 /* th.srri */, RISCV::TH_SRRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10476 { 23822 /* th.srriw */, RISCV::TH_SRRIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10477 { 23831 /* th.srw */, RISCV::TH_SRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10478 { 23838 /* th.surb */, RISCV::TH_SURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10479 { 23846 /* th.surd */, RISCV::TH_SURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10480 { 23854 /* th.surh */, RISCV::TH_SURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10481 { 23862 /* th.surw */, RISCV::TH_SURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10482 { 23870 /* th.swd */, RISCV::TH_SWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
10483 { 23877 /* th.swia */, RISCV::TH_SWIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10484 { 23885 /* th.swib */, RISCV::TH_SWIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10485 { 23893 /* th.sync */, RISCV::TH_SYNC, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10486 { 23901 /* th.sync.i */, RISCV::TH_SYNC_I, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10487 { 23911 /* th.sync.is */, RISCV::TH_SYNC_IS, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10488 { 23922 /* th.sync.s */, RISCV::TH_SYNC_S, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10489 { 23932 /* th.tst */, RISCV::TH_TST, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10490 { 23939 /* th.tstnbz */, RISCV::TH_TSTNBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10491 { 23949 /* th.vmaqa.vv */, RISCV::TH_VMAQA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10492 { 23961 /* th.vmaqa.vx */, RISCV::TH_VMAQA_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10493 { 23973 /* th.vmaqasu.vv */, RISCV::TH_VMAQASU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10494 { 23987 /* th.vmaqasu.vx */, RISCV::TH_VMAQASU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10495 { 24001 /* th.vmaqau.vv */, RISCV::TH_VMAQAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10496 { 24014 /* th.vmaqau.vx */, RISCV::TH_VMAQAU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10497 { 24027 /* th.vmaqaus.vx */, RISCV::TH_VMAQAUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10498 { 24041 /* unimp */, RISCV::UNIMP, Convert_NoOperands, AMFBS_None, { }, },
10499 { 24047 /* unzip */, RISCV::UNZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
10500 { 24053 /* unzip16hp */, RISCV::UNZIP16HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10501 { 24063 /* unzip16p */, RISCV::UNZIP16P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10502 { 24072 /* unzip8hp */, RISCV::UNZIP8HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10503 { 24081 /* unzip8p */, RISCV::UNZIP8P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10504 { 24089 /* usati */, RISCV::USATI_RV32, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10505 { 24089 /* usati */, RISCV::USATI_RV64, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
10506 { 24095 /* v8wmmacc.vv */, RISCV::V8WMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10507 { 24107 /* vaadd.vv */, RISCV::VAADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10508 { 24116 /* vaadd.vx */, RISCV::VAADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10509 { 24125 /* vaaddu.vv */, RISCV::VAADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10510 { 24135 /* vaaddu.vx */, RISCV::VAADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10511 { 24145 /* vabd.vv */, RISCV::VABD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10512 { 24153 /* vabd.vx */, RISCV::VABD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10513 { 24161 /* vabdu.vv */, RISCV::VABDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10514 { 24170 /* vabdu.vx */, RISCV::VABDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10515 { 24179 /* vabs.v */, RISCV::VABD_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR }, },
10516 { 24179 /* vabs.v */, RISCV::VABD_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10517 { 24186 /* vadc.vim */, RISCV::VADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
10518 { 24195 /* vadc.vvm */, RISCV::VADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10519 { 24204 /* vadc.vxm */, RISCV::VADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10520 { 24213 /* vadd.vi */, RISCV::VADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10521 { 24221 /* vadd.vv */, RISCV::VADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10522 { 24229 /* vadd.vx */, RISCV::VADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10523 { 24237 /* vaesdf.vs */, RISCV::VAESDF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10524 { 24247 /* vaesdf.vv */, RISCV::VAESDF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10525 { 24257 /* vaesdm.vs */, RISCV::VAESDM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10526 { 24267 /* vaesdm.vv */, RISCV::VAESDM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10527 { 24277 /* vaesef.vs */, RISCV::VAESEF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10528 { 24287 /* vaesef.vv */, RISCV::VAESEF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10529 { 24297 /* vaesem.vs */, RISCV::VAESEM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10530 { 24307 /* vaesem.vv */, RISCV::VAESEM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10531 { 24317 /* vaeskf1.vi */, RISCV::VAESKF1_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10532 { 24328 /* vaeskf2.vi */, RISCV::VAESKF2_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10533 { 24339 /* vaesz.vs */, RISCV::VAESZ_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10534 { 24348 /* vand.vi */, RISCV::VAND_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10535 { 24356 /* vand.vv */, RISCV::VAND_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10536 { 24364 /* vand.vx */, RISCV::VAND_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10537 { 24372 /* vandn.vv */, RISCV::VANDN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10538 { 24381 /* vandn.vx */, RISCV::VANDN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10539 { 24390 /* vasub.vv */, RISCV::VASUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10540 { 24399 /* vasub.vx */, RISCV::VASUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10541 { 24408 /* vasubu.vv */, RISCV::VASUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10542 { 24418 /* vasubu.vx */, RISCV::VASUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10543 { 24428 /* vbrev.v */, RISCV::VBREV_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10544 { 24436 /* vbrev8.v */, RISCV::VBREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10545 { 24445 /* vclmul.vv */, RISCV::VCLMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10546 { 24455 /* vclmul.vx */, RISCV::VCLMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10547 { 24465 /* vclmulh.vv */, RISCV::VCLMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10548 { 24476 /* vclmulh.vx */, RISCV::VCLMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10549 { 24487 /* vclz.v */, RISCV::VCLZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10550 { 24494 /* vcompress.vm */, RISCV::VCOMPRESS_VM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10551 { 24507 /* vcpop.m */, RISCV::VCPOP_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10552 { 24515 /* vcpop.v */, RISCV::VCPOP_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10553 { 24523 /* vctz.v */, RISCV::VCTZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10554 { 24530 /* vdiv.vv */, RISCV::VDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10555 { 24538 /* vdiv.vx */, RISCV::VDIV_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10556 { 24546 /* vdivu.vv */, RISCV::VDIVU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10557 { 24555 /* vdivu.vx */, RISCV::VDIVU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10558 { 24564 /* vdot4a.vv */, RISCV::VDOT4A_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10559 { 24574 /* vdot4a.vx */, RISCV::VDOT4A_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10560 { 24584 /* vdot4asu.vv */, RISCV::VDOT4ASU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10561 { 24596 /* vdot4asu.vx */, RISCV::VDOT4ASU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10562 { 24608 /* vdot4au.vv */, RISCV::VDOT4AU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10563 { 24619 /* vdot4au.vx */, RISCV::VDOT4AU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10564 { 24630 /* vdot4aus.vx */, RISCV::VDOT4AUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10565 { 24642 /* vf8wimmacc.vv */, RISCV::VF8WIMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10566 { 24656 /* vf8wmmacc.vv */, RISCV::VF8WMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10567 { 24656 /* vf8wmmacc.vv */, RISCV::VF8WMMACC_VV_SCALE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10568 { 24669 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR }, },
10569 { 24669 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10570 { 24677 /* vfadd.vf */, RISCV::VFADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10571 { 24686 /* vfadd.vv */, RISCV::VFADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10572 { 24695 /* vfbdota.vv */, RISCV::VFBDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm6Lsb0001_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfbdota32f, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm6Lsb000, MCK_RVVMaskRegOpOperand }, },
10573 { 24706 /* vfclass.v */, RISCV::VFCLASS_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10574 { 24716 /* vfcvt.f.x.v */, RISCV::VFCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10575 { 24728 /* vfcvt.f.xu.v */, RISCV::VFCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10576 { 24741 /* vfcvt.rtz.x.f.v */, RISCV::VFCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10577 { 24757 /* vfcvt.rtz.xu.f.v */, RISCV::VFCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10578 { 24774 /* vfcvt.x.f.v */, RISCV::VFCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10579 { 24786 /* vfcvt.xu.f.v */, RISCV::VFCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10580 { 24799 /* vfdiv.vf */, RISCV::VFDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10581 { 24808 /* vfdiv.vv */, RISCV::VFDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10582 { 24817 /* vfirst.m */, RISCV::VFIRST_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10583 { 24826 /* vfmacc.vf */, RISCV::VFMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10584 { 24836 /* vfmacc.vv */, RISCV::VFMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10585 { 24846 /* vfmadd.vf */, RISCV::VFMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10586 { 24856 /* vfmadd.vv */, RISCV::VFMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10587 { 24866 /* vfmax.vf */, RISCV::VFMAX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10588 { 24875 /* vfmax.vv */, RISCV::VFMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10589 { 24884 /* vfmerge.vfm */, RISCV::VFMERGE_VFM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskCarryInRegOpOperand }, },
10590 { 24896 /* vfmin.vf */, RISCV::VFMIN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10591 { 24905 /* vfmin.vv */, RISCV::VFMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10592 { 24914 /* vfmmacc.vv */, RISCV::VFMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10593 { 24925 /* vfmsac.vf */, RISCV::VFMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10594 { 24935 /* vfmsac.vv */, RISCV::VFMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10595 { 24945 /* vfmsub.vf */, RISCV::VFMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10596 { 24955 /* vfmsub.vv */, RISCV::VFMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10597 { 24965 /* vfmul.vf */, RISCV::VFMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10598 { 24974 /* vfmul.vv */, RISCV::VFMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10599 { 24983 /* vfmv.f.s */, RISCV::VFMV_F_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_FPR32, MCK_VR }, },
10600 { 24992 /* vfmv.s.f */, RISCV::VFMV_S_F, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32 }, },
10601 { 25001 /* vfmv.v.f */, RISCV::VFMV_V_F, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32 }, },
10602 { 25010 /* vfncvt.f.f.q */, RISCV::VFNCVT_F_F_Q, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10603 { 25023 /* vfncvt.f.f.w */, RISCV::VFNCVT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10604 { 25036 /* vfncvt.f.x.w */, RISCV::VFNCVT_F_X_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10605 { 25049 /* vfncvt.f.xu.w */, RISCV::VFNCVT_F_XU_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10606 { 25063 /* vfncvt.rod.f.f.w */, RISCV::VFNCVT_ROD_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10607 { 25080 /* vfncvt.rtz.x.f.w */, RISCV::VFNCVT_RTZ_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10608 { 25097 /* vfncvt.rtz.xu.f.w */, RISCV::VFNCVT_RTZ_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10609 { 25115 /* vfncvt.sat.f.f.q */, RISCV::VFNCVT_SAT_F_F_Q, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10610 { 25132 /* vfncvt.x.f.w */, RISCV::VFNCVT_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10611 { 25145 /* vfncvt.xu.f.w */, RISCV::VFNCVT_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10612 { 25159 /* vfncvtbf16.f.f.w */, RISCV::VFNCVTBF16_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfminOrZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10613 { 25176 /* vfncvtbf16.sat.f.f.w */, RISCV::VFNCVTBF16_SAT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10614 { 25197 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR }, },
10615 { 25197 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10616 { 25205 /* vfnmacc.vf */, RISCV::VFNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10617 { 25216 /* vfnmacc.vv */, RISCV::VFNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10618 { 25227 /* vfnmadd.vf */, RISCV::VFNMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10619 { 25238 /* vfnmadd.vv */, RISCV::VFNMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10620 { 25249 /* vfnmsac.vf */, RISCV::VFNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10621 { 25260 /* vfnmsac.vv */, RISCV::VFNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10622 { 25271 /* vfnmsub.vf */, RISCV::VFNMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10623 { 25282 /* vfnmsub.vv */, RISCV::VFNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10624 { 25293 /* vfqimmacc.vv */, RISCV::VFQIMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10625 { 25306 /* vfqmmacc.vv */, RISCV::VFQMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10626 { 25306 /* vfqmmacc.vv */, RISCV::VFQMMACC_VV_SCALE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10627 { 25318 /* vfqwbdota.alt.vv */, RISCV::VFQWBDOTA_ALT_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm6Lsb0001_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfqwbdota8f, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm6Lsb000, MCK_RVVMaskRegOpOperand }, },
10628 { 25335 /* vfqwbdota.vv */, RISCV::VFQWBDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm6Lsb0001_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfqwbdota8f, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm6Lsb000, MCK_RVVMaskRegOpOperand }, },
10629 { 25348 /* vfqwdota.alt.vv */, RISCV::VFQWDOTA_ALT_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfqwdota8f, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10630 { 25364 /* vfqwdota.vv */, RISCV::VFQWDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfqwdota8f, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10631 { 25376 /* vfrdiv.vf */, RISCV::VFRDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10632 { 25386 /* vfrec7.v */, RISCV::VFREC7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10633 { 25395 /* vfredmax.vs */, RISCV::VFREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10634 { 25407 /* vfredmin.vs */, RISCV::VFREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10635 { 25419 /* vfredosum.vs */, RISCV::VFREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10636 { 25432 /* vfredusum.vs */, RISCV::VFREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10637 { 25445 /* vfrsqrt7.v */, RISCV::VFRSQRT7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10638 { 25456 /* vfrsub.vf */, RISCV::VFRSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10639 { 25466 /* vfsgnj.vf */, RISCV::VFSGNJ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10640 { 25476 /* vfsgnj.vv */, RISCV::VFSGNJ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10641 { 25486 /* vfsgnjn.vf */, RISCV::VFSGNJN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10642 { 25497 /* vfsgnjn.vv */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10643 { 25508 /* vfsgnjx.vf */, RISCV::VFSGNJX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10644 { 25519 /* vfsgnjx.vv */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10645 { 25530 /* vfslide1down.vf */, RISCV::VFSLIDE1DOWN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10646 { 25546 /* vfslide1up.vf */, RISCV::VFSLIDE1UP_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10647 { 25560 /* vfsqrt.v */, RISCV::VFSQRT_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10648 { 25569 /* vfsub.vf */, RISCV::VFSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10649 { 25578 /* vfsub.vv */, RISCV::VFSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10650 { 25587 /* vfwadd.vf */, RISCV::VFWADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10651 { 25597 /* vfwadd.vv */, RISCV::VFWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10652 { 25607 /* vfwadd.wf */, RISCV::VFWADD_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10653 { 25617 /* vfwadd.wv */, RISCV::VFWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10654 { 25627 /* vfwbdota.vv */, RISCV::VFWBDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm6Lsb0001_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfwbdota16bf, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm6Lsb000, MCK_RVVMaskRegOpOperand }, },
10655 { 25639 /* vfwcvt.f.f.v */, RISCV::VFWCVT_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10656 { 25652 /* vfwcvt.f.x.v */, RISCV::VFWCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10657 { 25665 /* vfwcvt.f.xu.v */, RISCV::VFWCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10658 { 25679 /* vfwcvt.rtz.x.f.v */, RISCV::VFWCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10659 { 25696 /* vfwcvt.rtz.xu.f.v */, RISCV::VFWCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10660 { 25714 /* vfwcvt.x.f.v */, RISCV::VFWCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10661 { 25727 /* vfwcvt.xu.f.v */, RISCV::VFWCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10662 { 25741 /* vfwcvtbf16.f.f.v */, RISCV::VFWCVTBF16_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfminOrZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10663 { 25758 /* vfwdota.vv */, RISCV::VFWDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfwdota16bf, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10664 { 25769 /* vfwimmacc.vv */, RISCV::VFWIMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10665 { 25782 /* vfwmacc.vf */, RISCV::VFWMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10666 { 25793 /* vfwmacc.vv */, RISCV::VFWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10667 { 25804 /* vfwmaccbf16.vf */, RISCV::VFWMACCBF16_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10668 { 25819 /* vfwmaccbf16.vv */, RISCV::VFWMACCBF16_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10669 { 25834 /* vfwmmacc.vv */, RISCV::VFWMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10670 { 25834 /* vfwmmacc.vv */, RISCV::VFWMMACC_VV_SCALE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10671 { 25846 /* vfwmsac.vf */, RISCV::VFWMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10672 { 25857 /* vfwmsac.vv */, RISCV::VFWMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10673 { 25868 /* vfwmul.vf */, RISCV::VFWMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10674 { 25878 /* vfwmul.vv */, RISCV::VFWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10675 { 25888 /* vfwnmacc.vf */, RISCV::VFWNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10676 { 25900 /* vfwnmacc.vv */, RISCV::VFWNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10677 { 25912 /* vfwnmsac.vf */, RISCV::VFWNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10678 { 25924 /* vfwnmsac.vv */, RISCV::VFWNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10679 { 25936 /* vfwredosum.vs */, RISCV::VFWREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10680 { 25950 /* vfwredusum.vs */, RISCV::VFWREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10681 { 25964 /* vfwsub.vf */, RISCV::VFWSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10682 { 25974 /* vfwsub.vv */, RISCV::VFWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10683 { 25984 /* vfwsub.wf */, RISCV::VFWSUB_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10684 { 25994 /* vfwsub.wv */, RISCV::VFWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10685 { 26004 /* vghsh.vs */, RISCV::VGHSH_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkgs, { MCK_VR, MCK_VR, MCK_VR }, },
10686 { 26013 /* vghsh.vv */, RISCV::VGHSH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkg, { MCK_VR, MCK_VR, MCK_VR }, },
10687 { 26022 /* vgmul.vs */, RISCV::VGMUL_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkgs, { MCK_VR, MCK_VR }, },
10688 { 26031 /* vgmul.vv */, RISCV::VGMUL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkg, { MCK_VR, MCK_VR }, },
10689 { 26040 /* vid.v */, RISCV::VID_V, Convert__Reg1_0__RVVMaskRegOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_RVVMaskRegOpOperand }, },
10690 { 26046 /* viota.m */, RISCV::VIOTA_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10691 { 26054 /* vl1r.v */, RISCV::VL1RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10692 { 26061 /* vl1re16.v */, RISCV::VL1RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10693 { 26071 /* vl1re32.v */, RISCV::VL1RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10694 { 26081 /* vl1re64.v */, RISCV::VL1RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10695 { 26091 /* vl1re8.v */, RISCV::VL1RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10696 { 26100 /* vl2r.v */, RISCV::VL2RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10697 { 26107 /* vl2re16.v */, RISCV::VL2RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10698 { 26117 /* vl2re32.v */, RISCV::VL2RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10699 { 26127 /* vl2re64.v */, RISCV::VL2RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10700 { 26137 /* vl2re8.v */, RISCV::VL2RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10701 { 26146 /* vl4r.v */, RISCV::VL4RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10702 { 26153 /* vl4re16.v */, RISCV::VL4RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10703 { 26163 /* vl4re32.v */, RISCV::VL4RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10704 { 26173 /* vl4re64.v */, RISCV::VL4RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10705 { 26183 /* vl4re8.v */, RISCV::VL4RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10706 { 26192 /* vl8r.v */, RISCV::VL8RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10707 { 26199 /* vl8re16.v */, RISCV::VL8RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10708 { 26209 /* vl8re32.v */, RISCV::VL8RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10709 { 26219 /* vl8re64.v */, RISCV::VL8RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10710 { 26229 /* vl8re8.v */, RISCV::VL8RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10711 { 26238 /* vle16.v */, RISCV::VLE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10712 { 26246 /* vle16ff.v */, RISCV::VLE16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10713 { 26256 /* vle32.v */, RISCV::VLE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10714 { 26264 /* vle32ff.v */, RISCV::VLE32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10715 { 26274 /* vle64.v */, RISCV::VLE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10716 { 26282 /* vle64ff.v */, RISCV::VLE64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10717 { 26292 /* vle8.v */, RISCV::VLE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10718 { 26299 /* vle8ff.v */, RISCV::VLE8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10719 { 26308 /* vlm.v */, RISCV::VLM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10720 { 26314 /* vloxei16.v */, RISCV::VLOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10721 { 26325 /* vloxei32.v */, RISCV::VLOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10722 { 26336 /* vloxei64.v */, RISCV::VLOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10723 { 26347 /* vloxei8.v */, RISCV::VLOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10724 { 26357 /* vloxseg2ei16.v */, RISCV::VLOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10725 { 26372 /* vloxseg2ei32.v */, RISCV::VLOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10726 { 26387 /* vloxseg2ei64.v */, RISCV::VLOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10727 { 26402 /* vloxseg2ei8.v */, RISCV::VLOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10728 { 26416 /* vloxseg3ei16.v */, RISCV::VLOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10729 { 26431 /* vloxseg3ei32.v */, RISCV::VLOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10730 { 26446 /* vloxseg3ei64.v */, RISCV::VLOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10731 { 26461 /* vloxseg3ei8.v */, RISCV::VLOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10732 { 26475 /* vloxseg4ei16.v */, RISCV::VLOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10733 { 26490 /* vloxseg4ei32.v */, RISCV::VLOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10734 { 26505 /* vloxseg4ei64.v */, RISCV::VLOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10735 { 26520 /* vloxseg4ei8.v */, RISCV::VLOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10736 { 26534 /* vloxseg5ei16.v */, RISCV::VLOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10737 { 26549 /* vloxseg5ei32.v */, RISCV::VLOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10738 { 26564 /* vloxseg5ei64.v */, RISCV::VLOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10739 { 26579 /* vloxseg5ei8.v */, RISCV::VLOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10740 { 26593 /* vloxseg6ei16.v */, RISCV::VLOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10741 { 26608 /* vloxseg6ei32.v */, RISCV::VLOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10742 { 26623 /* vloxseg6ei64.v */, RISCV::VLOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10743 { 26638 /* vloxseg6ei8.v */, RISCV::VLOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10744 { 26652 /* vloxseg7ei16.v */, RISCV::VLOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10745 { 26667 /* vloxseg7ei32.v */, RISCV::VLOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10746 { 26682 /* vloxseg7ei64.v */, RISCV::VLOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10747 { 26697 /* vloxseg7ei8.v */, RISCV::VLOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10748 { 26711 /* vloxseg8ei16.v */, RISCV::VLOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10749 { 26726 /* vloxseg8ei32.v */, RISCV::VLOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10750 { 26741 /* vloxseg8ei64.v */, RISCV::VLOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10751 { 26756 /* vloxseg8ei8.v */, RISCV::VLOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10752 { 26770 /* vlse16.v */, RISCV::VLSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10753 { 26779 /* vlse32.v */, RISCV::VLSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10754 { 26788 /* vlse64.v */, RISCV::VLSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10755 { 26797 /* vlse8.v */, RISCV::VLSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10756 { 26805 /* vlseg2e16.v */, RISCV::VLSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10757 { 26817 /* vlseg2e16ff.v */, RISCV::VLSEG2E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10758 { 26831 /* vlseg2e32.v */, RISCV::VLSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10759 { 26843 /* vlseg2e32ff.v */, RISCV::VLSEG2E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10760 { 26857 /* vlseg2e64.v */, RISCV::VLSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10761 { 26869 /* vlseg2e64ff.v */, RISCV::VLSEG2E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10762 { 26883 /* vlseg2e8.v */, RISCV::VLSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10763 { 26894 /* vlseg2e8ff.v */, RISCV::VLSEG2E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10764 { 26907 /* vlseg3e16.v */, RISCV::VLSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10765 { 26919 /* vlseg3e16ff.v */, RISCV::VLSEG3E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10766 { 26933 /* vlseg3e32.v */, RISCV::VLSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10767 { 26945 /* vlseg3e32ff.v */, RISCV::VLSEG3E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10768 { 26959 /* vlseg3e64.v */, RISCV::VLSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10769 { 26971 /* vlseg3e64ff.v */, RISCV::VLSEG3E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10770 { 26985 /* vlseg3e8.v */, RISCV::VLSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10771 { 26996 /* vlseg3e8ff.v */, RISCV::VLSEG3E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10772 { 27009 /* vlseg4e16.v */, RISCV::VLSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10773 { 27021 /* vlseg4e16ff.v */, RISCV::VLSEG4E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10774 { 27035 /* vlseg4e32.v */, RISCV::VLSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10775 { 27047 /* vlseg4e32ff.v */, RISCV::VLSEG4E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10776 { 27061 /* vlseg4e64.v */, RISCV::VLSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10777 { 27073 /* vlseg4e64ff.v */, RISCV::VLSEG4E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10778 { 27087 /* vlseg4e8.v */, RISCV::VLSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10779 { 27098 /* vlseg4e8ff.v */, RISCV::VLSEG4E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10780 { 27111 /* vlseg5e16.v */, RISCV::VLSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10781 { 27123 /* vlseg5e16ff.v */, RISCV::VLSEG5E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10782 { 27137 /* vlseg5e32.v */, RISCV::VLSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10783 { 27149 /* vlseg5e32ff.v */, RISCV::VLSEG5E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10784 { 27163 /* vlseg5e64.v */, RISCV::VLSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10785 { 27175 /* vlseg5e64ff.v */, RISCV::VLSEG5E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10786 { 27189 /* vlseg5e8.v */, RISCV::VLSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10787 { 27200 /* vlseg5e8ff.v */, RISCV::VLSEG5E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10788 { 27213 /* vlseg6e16.v */, RISCV::VLSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10789 { 27225 /* vlseg6e16ff.v */, RISCV::VLSEG6E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10790 { 27239 /* vlseg6e32.v */, RISCV::VLSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10791 { 27251 /* vlseg6e32ff.v */, RISCV::VLSEG6E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10792 { 27265 /* vlseg6e64.v */, RISCV::VLSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10793 { 27277 /* vlseg6e64ff.v */, RISCV::VLSEG6E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10794 { 27291 /* vlseg6e8.v */, RISCV::VLSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10795 { 27302 /* vlseg6e8ff.v */, RISCV::VLSEG6E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10796 { 27315 /* vlseg7e16.v */, RISCV::VLSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10797 { 27327 /* vlseg7e16ff.v */, RISCV::VLSEG7E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10798 { 27341 /* vlseg7e32.v */, RISCV::VLSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10799 { 27353 /* vlseg7e32ff.v */, RISCV::VLSEG7E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10800 { 27367 /* vlseg7e64.v */, RISCV::VLSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10801 { 27379 /* vlseg7e64ff.v */, RISCV::VLSEG7E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10802 { 27393 /* vlseg7e8.v */, RISCV::VLSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10803 { 27404 /* vlseg7e8ff.v */, RISCV::VLSEG7E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10804 { 27417 /* vlseg8e16.v */, RISCV::VLSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10805 { 27429 /* vlseg8e16ff.v */, RISCV::VLSEG8E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10806 { 27443 /* vlseg8e32.v */, RISCV::VLSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10807 { 27455 /* vlseg8e32ff.v */, RISCV::VLSEG8E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10808 { 27469 /* vlseg8e64.v */, RISCV::VLSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10809 { 27481 /* vlseg8e64ff.v */, RISCV::VLSEG8E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10810 { 27495 /* vlseg8e8.v */, RISCV::VLSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10811 { 27506 /* vlseg8e8ff.v */, RISCV::VLSEG8E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10812 { 27519 /* vlsseg2e16.v */, RISCV::VLSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10813 { 27532 /* vlsseg2e32.v */, RISCV::VLSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10814 { 27545 /* vlsseg2e64.v */, RISCV::VLSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10815 { 27558 /* vlsseg2e8.v */, RISCV::VLSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10816 { 27570 /* vlsseg3e16.v */, RISCV::VLSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10817 { 27583 /* vlsseg3e32.v */, RISCV::VLSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10818 { 27596 /* vlsseg3e64.v */, RISCV::VLSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10819 { 27609 /* vlsseg3e8.v */, RISCV::VLSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10820 { 27621 /* vlsseg4e16.v */, RISCV::VLSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10821 { 27634 /* vlsseg4e32.v */, RISCV::VLSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10822 { 27647 /* vlsseg4e64.v */, RISCV::VLSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10823 { 27660 /* vlsseg4e8.v */, RISCV::VLSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10824 { 27672 /* vlsseg5e16.v */, RISCV::VLSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10825 { 27685 /* vlsseg5e32.v */, RISCV::VLSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10826 { 27698 /* vlsseg5e64.v */, RISCV::VLSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10827 { 27711 /* vlsseg5e8.v */, RISCV::VLSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10828 { 27723 /* vlsseg6e16.v */, RISCV::VLSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10829 { 27736 /* vlsseg6e32.v */, RISCV::VLSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10830 { 27749 /* vlsseg6e64.v */, RISCV::VLSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10831 { 27762 /* vlsseg6e8.v */, RISCV::VLSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10832 { 27774 /* vlsseg7e16.v */, RISCV::VLSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10833 { 27787 /* vlsseg7e32.v */, RISCV::VLSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10834 { 27800 /* vlsseg7e64.v */, RISCV::VLSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10835 { 27813 /* vlsseg7e8.v */, RISCV::VLSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10836 { 27825 /* vlsseg8e16.v */, RISCV::VLSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10837 { 27838 /* vlsseg8e32.v */, RISCV::VLSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10838 { 27851 /* vlsseg8e64.v */, RISCV::VLSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10839 { 27864 /* vlsseg8e8.v */, RISCV::VLSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10840 { 27876 /* vluxei16.v */, RISCV::VLUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10841 { 27887 /* vluxei32.v */, RISCV::VLUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10842 { 27898 /* vluxei64.v */, RISCV::VLUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10843 { 27909 /* vluxei8.v */, RISCV::VLUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10844 { 27919 /* vluxseg2ei16.v */, RISCV::VLUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10845 { 27934 /* vluxseg2ei32.v */, RISCV::VLUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10846 { 27949 /* vluxseg2ei64.v */, RISCV::VLUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10847 { 27964 /* vluxseg2ei8.v */, RISCV::VLUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10848 { 27978 /* vluxseg3ei16.v */, RISCV::VLUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10849 { 27993 /* vluxseg3ei32.v */, RISCV::VLUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10850 { 28008 /* vluxseg3ei64.v */, RISCV::VLUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10851 { 28023 /* vluxseg3ei8.v */, RISCV::VLUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10852 { 28037 /* vluxseg4ei16.v */, RISCV::VLUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10853 { 28052 /* vluxseg4ei32.v */, RISCV::VLUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10854 { 28067 /* vluxseg4ei64.v */, RISCV::VLUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10855 { 28082 /* vluxseg4ei8.v */, RISCV::VLUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10856 { 28096 /* vluxseg5ei16.v */, RISCV::VLUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10857 { 28111 /* vluxseg5ei32.v */, RISCV::VLUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10858 { 28126 /* vluxseg5ei64.v */, RISCV::VLUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10859 { 28141 /* vluxseg5ei8.v */, RISCV::VLUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10860 { 28155 /* vluxseg6ei16.v */, RISCV::VLUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10861 { 28170 /* vluxseg6ei32.v */, RISCV::VLUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10862 { 28185 /* vluxseg6ei64.v */, RISCV::VLUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10863 { 28200 /* vluxseg6ei8.v */, RISCV::VLUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10864 { 28214 /* vluxseg7ei16.v */, RISCV::VLUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10865 { 28229 /* vluxseg7ei32.v */, RISCV::VLUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10866 { 28244 /* vluxseg7ei64.v */, RISCV::VLUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10867 { 28259 /* vluxseg7ei8.v */, RISCV::VLUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10868 { 28273 /* vluxseg8ei16.v */, RISCV::VLUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10869 { 28288 /* vluxseg8ei32.v */, RISCV::VLUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10870 { 28303 /* vluxseg8ei64.v */, RISCV::VLUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10871 { 28318 /* vluxseg8ei8.v */, RISCV::VLUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10872 { 28332 /* vmacc.vv */, RISCV::VMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10873 { 28341 /* vmacc.vx */, RISCV::VMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10874 { 28350 /* vmadc.vi */, RISCV::VMADC_VI, Convert__Reg1_0__Reg1_1__SImm51_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5 }, },
10875 { 28359 /* vmadc.vim */, RISCV::VMADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
10876 { 28369 /* vmadc.vv */, RISCV::VMADC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10877 { 28378 /* vmadc.vvm */, RISCV::VMADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10878 { 28388 /* vmadc.vx */, RISCV::VMADC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10879 { 28397 /* vmadc.vxm */, RISCV::VMADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10880 { 28407 /* vmadd.vv */, RISCV::VMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10881 { 28416 /* vmadd.vx */, RISCV::VMADD_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10882 { 28425 /* vmand.mm */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10883 { 28434 /* vmandn.mm */, RISCV::VMANDN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10884 { 28444 /* vmax.vv */, RISCV::VMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10885 { 28452 /* vmax.vx */, RISCV::VMAX_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10886 { 28460 /* vmaxu.vv */, RISCV::VMAXU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10887 { 28469 /* vmaxu.vx */, RISCV::VMAXU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10888 { 28478 /* vmclr.m */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VR }, },
10889 { 28486 /* vmerge.vim */, RISCV::VMERGE_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
10890 { 28497 /* vmerge.vvm */, RISCV::VMERGE_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10891 { 28508 /* vmerge.vxm */, RISCV::VMERGE_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10892 { 28519 /* vmfeq.vf */, RISCV::VMFEQ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10893 { 28528 /* vmfeq.vv */, RISCV::VMFEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10894 { 28537 /* vmfge.vf */, RISCV::VMFGE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10895 { 28546 /* vmfge.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10896 { 28555 /* vmfgt.vf */, RISCV::VMFGT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10897 { 28564 /* vmfgt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10898 { 28573 /* vmfle.vf */, RISCV::VMFLE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10899 { 28582 /* vmfle.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10900 { 28591 /* vmflt.vf */, RISCV::VMFLT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10901 { 28600 /* vmflt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10902 { 28609 /* vmfne.vf */, RISCV::VMFNE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10903 { 28618 /* vmfne.vv */, RISCV::VMFNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10904 { 28627 /* vmin.vv */, RISCV::VMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10905 { 28635 /* vmin.vx */, RISCV::VMIN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10906 { 28643 /* vminu.vv */, RISCV::VMINU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10907 { 28652 /* vminu.vx */, RISCV::VMINU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10908 { 28661 /* vmmacc.vv */, RISCV::VMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10909 { 28671 /* vmmv.m */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10910 { 28678 /* vmnand.mm */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10911 { 28688 /* vmnor.mm */, RISCV::VMNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10912 { 28697 /* vmnot.m */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10913 { 28705 /* vmor.mm */, RISCV::VMOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10914 { 28713 /* vmorn.mm */, RISCV::VMORN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10915 { 28722 /* vmsbc.vv */, RISCV::VMSBC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10916 { 28731 /* vmsbc.vvm */, RISCV::VMSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10917 { 28741 /* vmsbc.vx */, RISCV::VMSBC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10918 { 28750 /* vmsbc.vxm */, RISCV::VMSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10919 { 28760 /* vmsbf.m */, RISCV::VMSBF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10920 { 28768 /* vmseq.vi */, RISCV::VMSEQ_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10921 { 28777 /* vmseq.vv */, RISCV::VMSEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10922 { 28786 /* vmseq.vx */, RISCV::VMSEQ_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10923 { 28795 /* vmset.m */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VR }, },
10924 { 28803 /* vmsge.vi */, RISCV::PseudoVMSGE_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10925 { 28812 /* vmsge.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10926 { 28821 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10927 { 28821 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
10928 { 28830 /* vmsgeu.vi */, RISCV::PseudoVMSGEU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10929 { 28840 /* vmsgeu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10930 { 28850 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10931 { 28850 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
10932 { 28860 /* vmsgt.vi */, RISCV::VMSGT_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10933 { 28869 /* vmsgt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10934 { 28878 /* vmsgt.vx */, RISCV::VMSGT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10935 { 28887 /* vmsgtu.vi */, RISCV::VMSGTU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10936 { 28897 /* vmsgtu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10937 { 28907 /* vmsgtu.vx */, RISCV::VMSGTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10938 { 28917 /* vmsif.m */, RISCV::VMSIF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10939 { 28925 /* vmsle.vi */, RISCV::VMSLE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10940 { 28934 /* vmsle.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10941 { 28943 /* vmsle.vx */, RISCV::VMSLE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10942 { 28952 /* vmsleu.vi */, RISCV::VMSLEU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10943 { 28962 /* vmsleu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10944 { 28972 /* vmsleu.vx */, RISCV::VMSLEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10945 { 28982 /* vmslt.vi */, RISCV::PseudoVMSLT_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10946 { 28991 /* vmslt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10947 { 29000 /* vmslt.vx */, RISCV::VMSLT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10948 { 29009 /* vmsltu.vi */, RISCV::PseudoVMSLTU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10949 { 29019 /* vmsltu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10950 { 29029 /* vmsltu.vx */, RISCV::VMSLTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10951 { 29039 /* vmsne.vi */, RISCV::VMSNE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10952 { 29048 /* vmsne.vv */, RISCV::VMSNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10953 { 29057 /* vmsne.vx */, RISCV::VMSNE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10954 { 29066 /* vmsof.m */, RISCV::VMSOF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10955 { 29074 /* vmtl.v */, RISCV::VMTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10956 { 29074 /* vmtl.v */, RISCV::VMTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10957 { 29081 /* vmts.v */, RISCV::VMTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10958 { 29081 /* vmts.v */, RISCV::VMTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10959 { 29088 /* vmttl.v */, RISCV::VMTTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10960 { 29088 /* vmttl.v */, RISCV::VMTTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10961 { 29096 /* vmtts.v */, RISCV::VMTTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10962 { 29096 /* vmtts.v */, RISCV::VMTTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10963 { 29104 /* vmul.vv */, RISCV::VMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10964 { 29112 /* vmul.vx */, RISCV::VMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10965 { 29120 /* vmulh.vv */, RISCV::VMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10966 { 29129 /* vmulh.vx */, RISCV::VMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10967 { 29138 /* vmulhsu.vv */, RISCV::VMULHSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10968 { 29149 /* vmulhsu.vx */, RISCV::VMULHSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10969 { 29160 /* vmulhu.vv */, RISCV::VMULHU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10970 { 29170 /* vmulhu.vx */, RISCV::VMULHU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10971 { 29180 /* vmv.s.x */, RISCV::VMV_S_X, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR }, },
10972 { 29188 /* vmv.v.i */, RISCV::VMV_V_I, Convert__Reg1_0__SImm51_1, AMFBS_HasVInstructions, { MCK_VR, MCK_SImm5 }, },
10973 { 29196 /* vmv.v.v */, RISCV::VMV_V_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10974 { 29204 /* vmv.v.x */, RISCV::VMV_V_X, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR }, },
10975 { 29212 /* vmv.x.s */, RISCV::VMV_X_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR }, },
10976 { 29220 /* vmv1r.v */, RISCV::VMV1R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10977 { 29228 /* vmv2r.v */, RISCV::VMV2R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_VRM2 }, },
10978 { 29236 /* vmv4r.v */, RISCV::VMV4R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_VRM4 }, },
10979 { 29244 /* vmv8r.v */, RISCV::VMV8R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_VRM8 }, },
10980 { 29252 /* vmxnor.mm */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10981 { 29262 /* vmxor.mm */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10982 { 29271 /* vnclip.wi */, RISCV::VNCLIP_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10983 { 29281 /* vnclip.wv */, RISCV::VNCLIP_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10984 { 29291 /* vnclip.wx */, RISCV::VNCLIP_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10985 { 29301 /* vnclipu.wi */, RISCV::VNCLIPU_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10986 { 29312 /* vnclipu.wv */, RISCV::VNCLIPU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10987 { 29323 /* vnclipu.wx */, RISCV::VNCLIPU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10988 { 29334 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10989 { 29334 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10990 { 29346 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10991 { 29346 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10992 { 29353 /* vnmsac.vv */, RISCV::VNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10993 { 29363 /* vnmsac.vx */, RISCV::VNMSAC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10994 { 29373 /* vnmsub.vv */, RISCV::VNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10995 { 29383 /* vnmsub.vx */, RISCV::VNMSUB_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10996 { 29393 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10997 { 29393 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10998 { 29400 /* vnsra.wi */, RISCV::VNSRA_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10999 { 29409 /* vnsra.wv */, RISCV::VNSRA_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11000 { 29418 /* vnsra.wx */, RISCV::VNSRA_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11001 { 29427 /* vnsrl.wi */, RISCV::VNSRL_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11002 { 29436 /* vnsrl.wv */, RISCV::VNSRL_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11003 { 29445 /* vnsrl.wx */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11004 { 29454 /* vor.vi */, RISCV::VOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
11005 { 29461 /* vor.vv */, RISCV::VOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11006 { 29468 /* vor.vx */, RISCV::VOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11007 { 29475 /* vpaire.vv */, RISCV::VPAIRE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11008 { 29485 /* vpairo.vv */, RISCV::VPAIRO_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11009 { 29495 /* vqmmacc.vv */, RISCV::VQMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
11010 { 29506 /* vqwbdotas.vv */, RISCV::VQWBDOTAS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm6Lsb0001_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm6Lsb000, MCK_RVVMaskRegOpOperand }, },
11011 { 29519 /* vqwbdotau.vv */, RISCV::VQWBDOTAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm6Lsb0001_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm6Lsb000, MCK_RVVMaskRegOpOperand }, },
11012 { 29532 /* vqwdotas.vv */, RISCV::VQWDOTAS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11013 { 29544 /* vqwdotau.vv */, RISCV::VQWDOTAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11014 { 29556 /* vredand.vs */, RISCV::VREDAND_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11015 { 29567 /* vredmax.vs */, RISCV::VREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11016 { 29578 /* vredmaxu.vs */, RISCV::VREDMAXU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11017 { 29590 /* vredmin.vs */, RISCV::VREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11018 { 29601 /* vredminu.vs */, RISCV::VREDMINU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11019 { 29613 /* vredor.vs */, RISCV::VREDOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11020 { 29623 /* vredsum.vs */, RISCV::VREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11021 { 29634 /* vredxor.vs */, RISCV::VREDXOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11022 { 29645 /* vrem.vv */, RISCV::VREM_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11023 { 29653 /* vrem.vx */, RISCV::VREM_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11024 { 29661 /* vremu.vv */, RISCV::VREMU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11025 { 29670 /* vremu.vx */, RISCV::VREMU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11026 { 29679 /* vrev8.v */, RISCV::VREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11027 { 29687 /* vrgather.vi */, RISCV::VRGATHER_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11028 { 29699 /* vrgather.vv */, RISCV::VRGATHER_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11029 { 29711 /* vrgather.vx */, RISCV::VRGATHER_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11030 { 29723 /* vrgatherei16.vv */, RISCV::VRGATHEREI16_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11031 { 29739 /* vrol.vv */, RISCV::VROL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11032 { 29747 /* vrol.vx */, RISCV::VROL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11033 { 29755 /* vror.vi */, RISCV::VROR_VI, Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_UImm6, MCK_RVVMaskRegOpOperand }, },
11034 { 29763 /* vror.vv */, RISCV::VROR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11035 { 29771 /* vror.vx */, RISCV::VROR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11036 { 29779 /* vrsub.vi */, RISCV::VRSUB_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
11037 { 29788 /* vrsub.vx */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11038 { 29797 /* vs1r.v */, RISCV::VS1R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
11039 { 29804 /* vs2r.v */, RISCV::VS2R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
11040 { 29811 /* vs4r.v */, RISCV::VS4R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
11041 { 29818 /* vs8r.v */, RISCV::VS8R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
11042 { 29825 /* vsadd.vi */, RISCV::VSADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
11043 { 29834 /* vsadd.vv */, RISCV::VSADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11044 { 29843 /* vsadd.vx */, RISCV::VSADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11045 { 29852 /* vsaddu.vi */, RISCV::VSADDU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
11046 { 29862 /* vsaddu.vv */, RISCV::VSADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11047 { 29872 /* vsaddu.vx */, RISCV::VSADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11048 { 29882 /* vsbc.vvm */, RISCV::VSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
11049 { 29891 /* vsbc.vxm */, RISCV::VSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
11050 { 29900 /* vse16.v */, RISCV::VSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11051 { 29908 /* vse32.v */, RISCV::VSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11052 { 29916 /* vse64.v */, RISCV::VSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11053 { 29924 /* vse8.v */, RISCV::VSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11054 { 29931 /* vsetivli */, RISCV::VSETIVLI, Convert__Reg1_0__UImm51_1__VTypeI101_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_UImm5, MCK_VTypeI10 }, },
11055 { 29940 /* vsetvl */, RISCV::VSETVL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_GPR }, },
11056 { 29947 /* vsetvli */, RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__VTypeI111_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_VTypeI11 }, },
11057 { 29955 /* vsext.vf2 */, RISCV::VSEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11058 { 29965 /* vsext.vf4 */, RISCV::VSEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11059 { 29975 /* vsext.vf8 */, RISCV::VSEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11060 { 29985 /* vsha2ch.vv */, RISCV::VSHA2CH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknha, { MCK_VR, MCK_VR, MCK_VR }, },
11061 { 29996 /* vsha2cl.vv */, RISCV::VSHA2CL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknha, { MCK_VR, MCK_VR, MCK_VR }, },
11062 { 30007 /* vsha2ms.vv */, RISCV::VSHA2MS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknha, { MCK_VR, MCK_VR, MCK_VR }, },
11063 { 30018 /* vslide1down.vx */, RISCV::VSLIDE1DOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11064 { 30033 /* vslide1up.vx */, RISCV::VSLIDE1UP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11065 { 30046 /* vslidedown.vi */, RISCV::VSLIDEDOWN_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11066 { 30060 /* vslidedown.vx */, RISCV::VSLIDEDOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11067 { 30074 /* vslideup.vi */, RISCV::VSLIDEUP_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11068 { 30086 /* vslideup.vx */, RISCV::VSLIDEUP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11069 { 30098 /* vsll.vi */, RISCV::VSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11070 { 30106 /* vsll.vv */, RISCV::VSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11071 { 30114 /* vsll.vx */, RISCV::VSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11072 { 30122 /* vsm.v */, RISCV::VSM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
11073 { 30128 /* vsm3c.vi */, RISCV::VSM3C_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksh, { MCK_VR, MCK_VR, MCK_UImm5 }, },
11074 { 30137 /* vsm3me.vv */, RISCV::VSM3ME_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZvksh, { MCK_VR, MCK_VR, MCK_VR }, },
11075 { 30147 /* vsm4k.vi */, RISCV::VSM4K_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR, MCK_UImm5 }, },
11076 { 30156 /* vsm4r.vs */, RISCV::VSM4R_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR }, },
11077 { 30165 /* vsm4r.vv */, RISCV::VSM4R_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR }, },
11078 { 30174 /* vsmul.vv */, RISCV::VSMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11079 { 30183 /* vsmul.vx */, RISCV::VSMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11080 { 30192 /* vsoxei16.v */, RISCV::VSOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11081 { 30203 /* vsoxei32.v */, RISCV::VSOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11082 { 30214 /* vsoxei64.v */, RISCV::VSOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11083 { 30225 /* vsoxei8.v */, RISCV::VSOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11084 { 30235 /* vsoxseg2ei16.v */, RISCV::VSOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11085 { 30250 /* vsoxseg2ei32.v */, RISCV::VSOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11086 { 30265 /* vsoxseg2ei64.v */, RISCV::VSOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11087 { 30280 /* vsoxseg2ei8.v */, RISCV::VSOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11088 { 30294 /* vsoxseg3ei16.v */, RISCV::VSOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11089 { 30309 /* vsoxseg3ei32.v */, RISCV::VSOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11090 { 30324 /* vsoxseg3ei64.v */, RISCV::VSOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11091 { 30339 /* vsoxseg3ei8.v */, RISCV::VSOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11092 { 30353 /* vsoxseg4ei16.v */, RISCV::VSOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11093 { 30368 /* vsoxseg4ei32.v */, RISCV::VSOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11094 { 30383 /* vsoxseg4ei64.v */, RISCV::VSOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11095 { 30398 /* vsoxseg4ei8.v */, RISCV::VSOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11096 { 30412 /* vsoxseg5ei16.v */, RISCV::VSOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11097 { 30427 /* vsoxseg5ei32.v */, RISCV::VSOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11098 { 30442 /* vsoxseg5ei64.v */, RISCV::VSOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11099 { 30457 /* vsoxseg5ei8.v */, RISCV::VSOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11100 { 30471 /* vsoxseg6ei16.v */, RISCV::VSOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11101 { 30486 /* vsoxseg6ei32.v */, RISCV::VSOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11102 { 30501 /* vsoxseg6ei64.v */, RISCV::VSOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11103 { 30516 /* vsoxseg6ei8.v */, RISCV::VSOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11104 { 30530 /* vsoxseg7ei16.v */, RISCV::VSOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11105 { 30545 /* vsoxseg7ei32.v */, RISCV::VSOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11106 { 30560 /* vsoxseg7ei64.v */, RISCV::VSOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11107 { 30575 /* vsoxseg7ei8.v */, RISCV::VSOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11108 { 30589 /* vsoxseg8ei16.v */, RISCV::VSOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11109 { 30604 /* vsoxseg8ei32.v */, RISCV::VSOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11110 { 30619 /* vsoxseg8ei64.v */, RISCV::VSOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11111 { 30634 /* vsoxseg8ei8.v */, RISCV::VSOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11112 { 30648 /* vsra.vi */, RISCV::VSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11113 { 30656 /* vsra.vv */, RISCV::VSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11114 { 30664 /* vsra.vx */, RISCV::VSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11115 { 30672 /* vsrl.vi */, RISCV::VSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11116 { 30680 /* vsrl.vv */, RISCV::VSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11117 { 30688 /* vsrl.vx */, RISCV::VSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11118 { 30696 /* vsse16.v */, RISCV::VSSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11119 { 30705 /* vsse32.v */, RISCV::VSSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11120 { 30714 /* vsse64.v */, RISCV::VSSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11121 { 30723 /* vsse8.v */, RISCV::VSSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11122 { 30731 /* vsseg2e16.v */, RISCV::VSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11123 { 30743 /* vsseg2e32.v */, RISCV::VSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11124 { 30755 /* vsseg2e64.v */, RISCV::VSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11125 { 30767 /* vsseg2e8.v */, RISCV::VSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11126 { 30778 /* vsseg3e16.v */, RISCV::VSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11127 { 30790 /* vsseg3e32.v */, RISCV::VSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11128 { 30802 /* vsseg3e64.v */, RISCV::VSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11129 { 30814 /* vsseg3e8.v */, RISCV::VSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11130 { 30825 /* vsseg4e16.v */, RISCV::VSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11131 { 30837 /* vsseg4e32.v */, RISCV::VSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11132 { 30849 /* vsseg4e64.v */, RISCV::VSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11133 { 30861 /* vsseg4e8.v */, RISCV::VSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11134 { 30872 /* vsseg5e16.v */, RISCV::VSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11135 { 30884 /* vsseg5e32.v */, RISCV::VSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11136 { 30896 /* vsseg5e64.v */, RISCV::VSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11137 { 30908 /* vsseg5e8.v */, RISCV::VSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11138 { 30919 /* vsseg6e16.v */, RISCV::VSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11139 { 30931 /* vsseg6e32.v */, RISCV::VSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11140 { 30943 /* vsseg6e64.v */, RISCV::VSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11141 { 30955 /* vsseg6e8.v */, RISCV::VSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11142 { 30966 /* vsseg7e16.v */, RISCV::VSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11143 { 30978 /* vsseg7e32.v */, RISCV::VSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11144 { 30990 /* vsseg7e64.v */, RISCV::VSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11145 { 31002 /* vsseg7e8.v */, RISCV::VSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11146 { 31013 /* vsseg8e16.v */, RISCV::VSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11147 { 31025 /* vsseg8e32.v */, RISCV::VSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11148 { 31037 /* vsseg8e64.v */, RISCV::VSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11149 { 31049 /* vsseg8e8.v */, RISCV::VSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
11150 { 31060 /* vssra.vi */, RISCV::VSSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11151 { 31069 /* vssra.vv */, RISCV::VSSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11152 { 31078 /* vssra.vx */, RISCV::VSSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11153 { 31087 /* vssrl.vi */, RISCV::VSSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11154 { 31096 /* vssrl.vv */, RISCV::VSSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11155 { 31105 /* vssrl.vx */, RISCV::VSSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11156 { 31114 /* vssseg2e16.v */, RISCV::VSSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11157 { 31127 /* vssseg2e32.v */, RISCV::VSSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11158 { 31140 /* vssseg2e64.v */, RISCV::VSSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11159 { 31153 /* vssseg2e8.v */, RISCV::VSSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11160 { 31165 /* vssseg3e16.v */, RISCV::VSSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11161 { 31178 /* vssseg3e32.v */, RISCV::VSSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11162 { 31191 /* vssseg3e64.v */, RISCV::VSSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11163 { 31204 /* vssseg3e8.v */, RISCV::VSSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11164 { 31216 /* vssseg4e16.v */, RISCV::VSSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11165 { 31229 /* vssseg4e32.v */, RISCV::VSSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11166 { 31242 /* vssseg4e64.v */, RISCV::VSSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11167 { 31255 /* vssseg4e8.v */, RISCV::VSSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11168 { 31267 /* vssseg5e16.v */, RISCV::VSSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11169 { 31280 /* vssseg5e32.v */, RISCV::VSSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11170 { 31293 /* vssseg5e64.v */, RISCV::VSSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11171 { 31306 /* vssseg5e8.v */, RISCV::VSSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11172 { 31318 /* vssseg6e16.v */, RISCV::VSSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11173 { 31331 /* vssseg6e32.v */, RISCV::VSSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11174 { 31344 /* vssseg6e64.v */, RISCV::VSSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11175 { 31357 /* vssseg6e8.v */, RISCV::VSSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11176 { 31369 /* vssseg7e16.v */, RISCV::VSSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11177 { 31382 /* vssseg7e32.v */, RISCV::VSSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11178 { 31395 /* vssseg7e64.v */, RISCV::VSSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11179 { 31408 /* vssseg7e8.v */, RISCV::VSSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11180 { 31420 /* vssseg8e16.v */, RISCV::VSSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11181 { 31433 /* vssseg8e32.v */, RISCV::VSSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11182 { 31446 /* vssseg8e64.v */, RISCV::VSSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11183 { 31459 /* vssseg8e8.v */, RISCV::VSSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11184 { 31471 /* vssub.vv */, RISCV::VSSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11185 { 31480 /* vssub.vx */, RISCV::VSSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11186 { 31489 /* vssubu.vv */, RISCV::VSSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11187 { 31499 /* vssubu.vx */, RISCV::VSSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11188 { 31509 /* vsub.vv */, RISCV::VSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11189 { 31517 /* vsub.vx */, RISCV::VSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11190 { 31525 /* vsuxei16.v */, RISCV::VSUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11191 { 31536 /* vsuxei32.v */, RISCV::VSUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11192 { 31547 /* vsuxei64.v */, RISCV::VSUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11193 { 31558 /* vsuxei8.v */, RISCV::VSUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11194 { 31568 /* vsuxseg2ei16.v */, RISCV::VSUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11195 { 31583 /* vsuxseg2ei32.v */, RISCV::VSUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11196 { 31598 /* vsuxseg2ei64.v */, RISCV::VSUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11197 { 31613 /* vsuxseg2ei8.v */, RISCV::VSUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11198 { 31627 /* vsuxseg3ei16.v */, RISCV::VSUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11199 { 31642 /* vsuxseg3ei32.v */, RISCV::VSUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11200 { 31657 /* vsuxseg3ei64.v */, RISCV::VSUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11201 { 31672 /* vsuxseg3ei8.v */, RISCV::VSUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11202 { 31686 /* vsuxseg4ei16.v */, RISCV::VSUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11203 { 31701 /* vsuxseg4ei32.v */, RISCV::VSUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11204 { 31716 /* vsuxseg4ei64.v */, RISCV::VSUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11205 { 31731 /* vsuxseg4ei8.v */, RISCV::VSUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11206 { 31745 /* vsuxseg5ei16.v */, RISCV::VSUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11207 { 31760 /* vsuxseg5ei32.v */, RISCV::VSUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11208 { 31775 /* vsuxseg5ei64.v */, RISCV::VSUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11209 { 31790 /* vsuxseg5ei8.v */, RISCV::VSUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11210 { 31804 /* vsuxseg6ei16.v */, RISCV::VSUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11211 { 31819 /* vsuxseg6ei32.v */, RISCV::VSUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11212 { 31834 /* vsuxseg6ei64.v */, RISCV::VSUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11213 { 31849 /* vsuxseg6ei8.v */, RISCV::VSUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11214 { 31863 /* vsuxseg7ei16.v */, RISCV::VSUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11215 { 31878 /* vsuxseg7ei32.v */, RISCV::VSUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11216 { 31893 /* vsuxseg7ei64.v */, RISCV::VSUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11217 { 31908 /* vsuxseg7ei8.v */, RISCV::VSUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11218 { 31922 /* vsuxseg8ei16.v */, RISCV::VSUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11219 { 31937 /* vsuxseg8ei32.v */, RISCV::VSUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11220 { 31952 /* vsuxseg8ei64.v */, RISCV::VSUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11221 { 31967 /* vsuxseg8ei8.v */, RISCV::VSUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11222 { 31981 /* vunzipe.v */, RISCV::VUNZIPE_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11223 { 31991 /* vunzipo.v */, RISCV::VUNZIPO_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11224 { 32001 /* vwabda.vv */, RISCV::VWABDA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11225 { 32011 /* vwabda.vx */, RISCV::VWABDA_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11226 { 32021 /* vwabdau.vv */, RISCV::VWABDAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11227 { 32032 /* vwabdau.vx */, RISCV::VWABDAU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11228 { 32043 /* vwadd.vv */, RISCV::VWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11229 { 32052 /* vwadd.vx */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11230 { 32061 /* vwadd.wv */, RISCV::VWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11231 { 32070 /* vwadd.wx */, RISCV::VWADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11232 { 32079 /* vwaddu.vv */, RISCV::VWADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11233 { 32089 /* vwaddu.vx */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11234 { 32099 /* vwaddu.wv */, RISCV::VWADDU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11235 { 32109 /* vwaddu.wx */, RISCV::VWADDU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11236 { 32119 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
11237 { 32119 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11238 { 32131 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
11239 { 32131 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11240 { 32144 /* vwmacc.vv */, RISCV::VWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11241 { 32154 /* vwmacc.vx */, RISCV::VWMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11242 { 32164 /* vwmaccsu.vv */, RISCV::VWMACCSU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11243 { 32176 /* vwmaccsu.vx */, RISCV::VWMACCSU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11244 { 32188 /* vwmaccu.vv */, RISCV::VWMACCU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11245 { 32199 /* vwmaccu.vx */, RISCV::VWMACCU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11246 { 32210 /* vwmaccus.vx */, RISCV::VWMACCUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11247 { 32222 /* vwmmacc.vv */, RISCV::VWMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
11248 { 32233 /* vwmul.vv */, RISCV::VWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11249 { 32242 /* vwmul.vx */, RISCV::VWMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11250 { 32251 /* vwmulsu.vv */, RISCV::VWMULSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11251 { 32262 /* vwmulsu.vx */, RISCV::VWMULSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11252 { 32273 /* vwmulu.vv */, RISCV::VWMULU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11253 { 32283 /* vwmulu.vx */, RISCV::VWMULU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11254 { 32293 /* vwredsum.vs */, RISCV::VWREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11255 { 32305 /* vwredsumu.vs */, RISCV::VWREDSUMU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11256 { 32318 /* vwsll.vi */, RISCV::VWSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
11257 { 32327 /* vwsll.vv */, RISCV::VWSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11258 { 32336 /* vwsll.vx */, RISCV::VWSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11259 { 32345 /* vwsub.vv */, RISCV::VWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11260 { 32354 /* vwsub.vx */, RISCV::VWSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11261 { 32363 /* vwsub.wv */, RISCV::VWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11262 { 32372 /* vwsub.wx */, RISCV::VWSUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11263 { 32381 /* vwsubu.vv */, RISCV::VWSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11264 { 32391 /* vwsubu.vx */, RISCV::VWSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11265 { 32401 /* vwsubu.wv */, RISCV::VWSUBU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11266 { 32411 /* vwsubu.wx */, RISCV::VWSUBU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11267 { 32421 /* vxor.vi */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
11268 { 32429 /* vxor.vv */, RISCV::VXOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11269 { 32437 /* vxor.vx */, RISCV::VXOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
11270 { 32445 /* vzext.vf2 */, RISCV::VZEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11271 { 32455 /* vzext.vf4 */, RISCV::VZEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11272 { 32465 /* vzext.vf8 */, RISCV::VZEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11273 { 32475 /* vzip.vv */, RISCV::VZIP_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
11274 { 32483 /* wadd */, RISCV::WADD, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11275 { 32488 /* wadda */, RISCV::WADDA, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11276 { 32494 /* waddau */, RISCV::WADDAU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11277 { 32501 /* waddu */, RISCV::WADDU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11278 { 32507 /* wfi */, RISCV::WFI, Convert_NoOperands, AMFBS_None, { }, },
11279 { 32511 /* wmacc */, RISCV::WMACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11280 { 32517 /* wmaccsu */, RISCV::WMACCSU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11281 { 32525 /* wmaccu */, RISCV::WMACCU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11282 { 32532 /* wmul */, RISCV::WMUL, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11283 { 32537 /* wmulsu */, RISCV::WMULSU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11284 { 32544 /* wmulu */, RISCV::WMULU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11285 { 32550 /* wrs.nto */, RISCV::WRS_NTO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
11286 { 32558 /* wrs.sto */, RISCV::WRS_STO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
11287 { 32566 /* wsla */, RISCV::WSLA, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11288 { 32571 /* wslai */, RISCV::WSLAI, Convert__GPRPairRV321_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm6 }, },
11289 { 32577 /* wsll */, RISCV::WSLL, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11290 { 32582 /* wslli */, RISCV::WSLLI, Convert__GPRPairRV321_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm6 }, },
11291 { 32588 /* wsub */, RISCV::WSUB, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11292 { 32593 /* wsuba */, RISCV::WSUBA, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11293 { 32599 /* wsubau */, RISCV::WSUBAU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11294 { 32606 /* wsubu */, RISCV::WSUBU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11295 { 32612 /* wzip16p */, RISCV::WZIP16P, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11296 { 32620 /* wzip8p */, RISCV::WZIP8P, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
11297 { 32627 /* xnor */, RISCV::XNOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
11298 { 32632 /* xor */, RISCV::XOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
11299 { 32632 /* xor */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
11300 { 32636 /* xori */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
11301 { 32641 /* xperm4 */, RISCV::XPERM4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
11302 { 32648 /* xperm8 */, RISCV::XPERM8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
11303 { 32655 /* yadd */, RISCV::YADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPRNoX0 }, },
11304 { 32655 /* yadd */, RISCV::YADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_SImm12LO }, },
11305 { 32660 /* yaddi */, RISCV::YADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_SImm12LO }, },
11306 { 32666 /* yaddrw */, RISCV::YADDRW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
11307 { 32673 /* yamask */, RISCV::YAMASK, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_GPR }, },
11308 { 32680 /* ybaser */, RISCV::YBASER, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
11309 { 32687 /* ybld */, RISCV::YBLD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YGPR }, },
11310 { 32692 /* ybndsrw */, RISCV::YBNDSRW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
11311 { 32700 /* ybndsw */, RISCV::YBNDSW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
11312 { 32700 /* ybndsw */, RISCV::YBNDSWI, Convert__Reg1_0__Reg1_1__YBNDSWImm1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YBNDSWImm }, },
11313 { 32707 /* ybndswi */, RISCV::YBNDSWI, Convert__Reg1_0__Reg1_1__YBNDSWImm1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YBNDSWImm }, },
11314 { 32715 /* yeq */, RISCV::YEQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR, MCK_YGPR }, },
11315 { 32719 /* yhir */, RISCV::YHIR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
11316 { 32724 /* yhiw */, RISCV::YHIW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_GPR, MCK_GPR }, },
11317 { 32729 /* ylenr */, RISCV::YLENR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
11318 { 32735 /* ymv */, RISCV::YMV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR }, },
11319 { 32739 /* ypermc */, RISCV::YPERMC, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
11320 { 32746 /* ypermr */, RISCV::YPERMR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
11321 { 32753 /* yseale */, RISCV::YSEALE, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR }, },
11322 { 32760 /* yss */, RISCV::YSS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR, MCK_YGPR }, },
11323 { 32764 /* ytagr */, RISCV::YTAGR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
11324 { 32770 /* ytopr */, RISCV::YTOPR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
11325 { 32776 /* ytyper */, RISCV::YTYPER, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
11326 { 32783 /* yunseals */, RISCV::YUNSEALS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YGPR }, },
11327 { 32792 /* zext.b */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__imm_95_255, AMFBS_None, { MCK_GPR, MCK_GPR }, },
11328 { 32799 /* zext.h */, RISCV::ZEXT_H_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
11329 { 32799 /* zext.h */, RISCV::ZEXT_H_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR }, },
11330 { 32799 /* zext.h */, RISCV::PseudoZEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
11331 { 32806 /* zext.w */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR }, },
11332 { 32806 /* zext.w */, RISCV::PseudoZEXT_W, Convert__Reg1_0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
11333 { 32813 /* zip */, RISCV::ZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
11334 { 32817 /* zip16hp */, RISCV::ZIP16HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
11335 { 32825 /* zip16p */, RISCV::ZIP16P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
11336 { 32832 /* zip8hp */, RISCV::ZIP8HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
11337 { 32839 /* zip8p */, RISCV::ZIP8P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
11338};
11339
11340#include "llvm/Support/Debug.h"
11341#include "llvm/Support/Format.h"
11342
11343unsigned RISCVAsmParser::
11344MatchInstructionImpl(const OperandVector &Operands,
11345 MCInst &Inst,
11346 SmallVectorImpl<NearMissInfo> *NearMisses,
11347 bool matchingInlineAsm, unsigned VariantID) {
11348 // Get the current feature set.
11349 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
11350
11351 // Get the instruction mnemonic, which is the first token.
11352 StringRef Mnemonic = ((RISCVOperand &)*Operands[0]).getToken();
11353
11354 // Process all MnemonicAliases to remap the mnemonic.
11355 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
11356
11357 SmallBitVector OptionalOperandsMask(9);
11358 // Find the appropriate table for this asm variant.
11359 const MatchEntry *Start, *End;
11360 switch (VariantID) {
11361 default: llvm_unreachable("invalid variant!");
11362 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
11363 }
11364 // Search the table.
11365 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
11366
11367 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
11368 std::distance(MnemonicRange.first, MnemonicRange.second) <<
11369 " encodings with mnemonic '" << Mnemonic << "'\n");
11370
11371 // Return a more specific error code if no mnemonics match.
11372 if (MnemonicRange.first == MnemonicRange.second)
11373 return Match_MnemonicFail;
11374
11375 // First operand near-miss of each opcode that mismatched in
11376 // more than one operand. Used only if no opcode yields a
11377 // near-miss of its own (see below).
11378 SmallVector<NearMissInfo, 4> MultiMismatchFallback;
11379
11380 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
11381 it != ie; ++it) {
11382 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
11383 bool HasRequiredFeatures =
11384 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
11385 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
11386 << MII.getName(it->Opcode) << "\n");
11387 // Some state to record ways in which this instruction did not match.
11388 NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();
11389 NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();
11390 NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();
11391 NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();
11392 bool MultipleInvalidOperands = false;
11393 // equal_range guarantees that instruction mnemonic matches.
11394 assert(Mnemonic == it->getMnemonic());
11395 OptionalOperandsMask.reset(0, 9);
11396 unsigned ActualIdx = 1;
11397 for (unsigned FormalIdx = 0; FormalIdx != 8; ++FormalIdx) {
11398 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
11399 DEBUG_WITH_TYPE("asm-matcher",
11400 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
11401 << " against actual operand at index " << ActualIdx);
11402 if (ActualIdx < Operands.size())
11403 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
11404 Operands[ActualIdx]->print(dbgs(), getContext().getAsmInfo()); dbgs() << "): ");
11405 else
11406 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
11407 if (ActualIdx >= Operands.size()) {
11408 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
11409 bool ThisOperandValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
11410 if (!ThisOperandValid) {
11411 if (!OperandNearMiss) {
11412 // Record info about match failure for later use.
11413 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "recording too-few-operands near miss\n");
11414 OperandNearMiss =
11415 NearMissInfo::getTooFewOperands(Formal, it->Opcode);
11416 } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {
11417 // If more than one operand is invalid, give up on this match entry.
11418 DEBUG_WITH_TYPE(
11419 "asm-matcher",
11420 dbgs() << "second invalid operand, giving up on this opcode\n");
11421 MultipleInvalidOperands = true;
11422 break;
11423 }
11424 } else {
11425 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "but formal operand not required\n");
11426 if (isSubclass(Formal, OptionalMatchClass)) {
11427 OptionalOperandsMask.set(FormalIdx + 1);
11428 }
11429 }
11430 continue;
11431 }
11432 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
11433 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
11434 if (Diag == Match_Success) {
11435 DEBUG_WITH_TYPE("asm-matcher",
11436 dbgs() << "match success using generic matcher\n");
11437 ++ActualIdx;
11438 continue;
11439 }
11440 // If the generic handler indicates an invalid operand
11441 // failure, check for a special case.
11442 if (Diag != Match_Success) {
11443 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
11444 if (TargetDiag == Match_Success) {
11445 DEBUG_WITH_TYPE("asm-matcher",
11446 dbgs() << "match success using target matcher\n");
11447 ++ActualIdx;
11448 continue;
11449 }
11450 // If the target matcher returned a specific error code use
11451 // that, else use the one from the generic matcher.
11452 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
11453 Diag = TargetDiag;
11454 }
11455 // If current formal operand wasn't matched and it is optional
11456 // then try to match next formal operand
11457 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
11458 OptionalOperandsMask.set(FormalIdx + 1);
11459 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
11460 continue;
11461 }
11462 if (!OperandNearMiss) {
11463 // If this is the first invalid operand we have seen, record some
11464 // information about it.
11465 DEBUG_WITH_TYPE(
11466 "asm-matcher",
11467 dbgs()
11468 << "operand match failed, recording near-miss with diag code "
11469 << Diag << "\n");
11470 OperandNearMiss =
11471 NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);
11472 ++ActualIdx;
11473 } else {
11474 // If more than one operand is invalid, give up on this match entry.
11475 DEBUG_WITH_TYPE(
11476 "asm-matcher",
11477 dbgs() << "second operand mismatch, skipping this opcode\n");
11478 MultipleInvalidOperands = true;
11479 break;
11480 }
11481 }
11482
11483 // Reject surplus operands as one more operand mismatch.
11484 if (!MultipleInvalidOperands && ActualIdx < Operands.size()) {
11485 if (!OperandNearMiss) {
11486 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "too many operands, recording near-miss at index "
11487 << ActualIdx << "\n");
11488 OperandNearMiss = NearMissInfo::getMissedOperand(
11489 Match_InvalidOperand, InvalidMatchClass, it->Opcode, ActualIdx);
11490 } else {
11491 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "too many operands after an earlier mismatch, skipping this opcode\n");
11492 MultipleInvalidOperands = true;
11493 }
11494 }
11495
11496 if (!HasRequiredFeatures) {
11497 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
11498 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
11499 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
11500 if (NewMissingFeatures[I])
11501 dbgs() << ' ' << I;
11502 dbgs() << "\n");
11503 FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);
11504 }
11505 if (MultipleInvalidOperands) {
11506 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11507 "operand mismatches, ignoring "
11508 "this opcode\n");
11509 // Too many invalid operands to report a single near-miss;
11510 // keep the first one as a fallback in case no opcode
11511 // matches more closely.
11512 // If the opcode also has missing features, promote the
11513 // feature near-miss instead of the operand near-miss so
11514 // that the diagnostic points to the missing extension.
11515 if (FeaturesNearMiss)
11516 MultiMismatchFallback.push_back(FeaturesNearMiss);
11517 else if (OperandNearMiss)
11518 MultiMismatchFallback.push_back(OperandNearMiss);
11519 continue;
11520 }
11521
11522 Inst.clear();
11523
11524 Inst.setOpcode(it->Opcode);
11525 // We have a potential match but have not rendered the operands.
11526 // Check the target predicate to handle any context sensitive
11527 // constraints.
11528 // For example, Ties that are referenced multiple times must be
11529 // checked here to ensure the input is the same for each match
11530 // constraints. If we leave it any later the ties will have been
11531 // canonicalized
11532 unsigned MatchResult;
11533 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
11534 Inst.clear();
11535 DEBUG_WITH_TYPE(
11536 "asm-matcher",
11537 dbgs() << "Early target match predicate failed with diag code "
11538 << MatchResult << "\n");
11539 EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
11540 }
11541
11542 // If we did not successfully match the operands, then we can't convert to
11543 // an MCInst, so bail out on this instruction variant now.
11544 if (OperandNearMiss) {
11545 // If the operand mismatch was the only problem, report it as a near-miss.
11546 if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) {
11547 DEBUG_WITH_TYPE(
11548 "asm-matcher",
11549 dbgs()
11550 << "Opcode result: one mismatched operand, adding near-miss\n");
11551 NearMisses->push_back(OperandNearMiss);
11552 } else {
11553 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11554 "types of mismatch, so not "
11555 "reporting near-miss\n");
11556 }
11557 continue;
11558 }
11559
11560 unsigned DefaultsOffset[9] = { 0 };
11561 assert(OptionalOperandsMask.size() == 9);
11562 for (unsigned i = 0, NumDefaults = 0; i < 8; ++i) {
11563 NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
11564 DefaultsOffset[i + 1] = NumDefaults;
11565 }
11566
11567 if (matchingInlineAsm) {
11568 convertToMapAndConstraints(it->ConvertFn, Operands);
11569 return Match_Success;
11570 }
11571
11572 // We have selected a definite instruction, convert the parsed
11573 // operands into the appropriate MCInst.
11574 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,
11575 OptionalOperandsMask, DefaultsOffset);
11576
11577 // We have a potential match. Check the target predicate to
11578 // handle any context sensitive constraints.
11579 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
11580 DEBUG_WITH_TYPE("asm-matcher",
11581 dbgs() << "Target match predicate failed with diag code "
11582 << MatchResult << "\n");
11583 Inst.clear();
11584 LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
11585 }
11586
11587 int NumNearMisses = ((int)(bool)OperandNearMiss +
11588 (int)(bool)FeaturesNearMiss +
11589 (int)(bool)EarlyPredicateNearMiss +
11590 (int)(bool)LatePredicateNearMiss);
11591 if (NumNearMisses == 1) {
11592 // We had exactly one type of near-miss, so add that to the list.
11593 assert(!OperandNearMiss && "OperandNearMiss was handled earlier");
11594 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: found one type of "
11595 "mismatch, so reporting a "
11596 "near-miss\n");
11597 if (NearMisses && FeaturesNearMiss)
11598 NearMisses->push_back(FeaturesNearMiss);
11599 else if (NearMisses && EarlyPredicateNearMiss)
11600 NearMisses->push_back(EarlyPredicateNearMiss);
11601 else if (NearMisses && LatePredicateNearMiss)
11602 NearMisses->push_back(LatePredicateNearMiss);
11603
11604 continue;
11605 } else if (NumNearMisses > 1) {
11606 // This instruction missed in more than one way, so ignore it.
11607 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11608 "types of mismatch, so not "
11609 "reporting near-miss\n");
11610 continue;
11611 }
11612 DEBUG_WITH_TYPE(
11613 "asm-matcher",
11614 dbgs() << "Opcode result: complete match, selecting this opcode\n");
11615 return Match_Success;
11616 }
11617
11618 // No instruction variants matched exactly. If nothing produced
11619 // a near-miss, fall back to the multi-mismatch list so we can
11620 // still give a specific diagnostic rather than a generic
11621 // "invalid instruction".
11622 if (NearMisses && NearMisses->empty())
11623 NearMisses->append(MultiMismatchFallback.begin(),
11624 MultiMismatchFallback.end());
11625 return Match_NearMisses;
11626}
11627
11628namespace {
11629 struct OperandMatchEntry {
11630 uint16_t Mnemonic;
11631 uint8_t OperandMask;
11632 uint16_t Class;
11633 uint8_t RequiredFeaturesIdx;
11634
11635 StringRef getMnemonic() const {
11636 return StringRef(MnemonicTable + Mnemonic + 1,
11637 MnemonicTable[Mnemonic]);
11638 }
11639 };
11640
11641 // Predicate for searching for an opcode.
11642 struct LessOpcodeOperand {
11643 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
11644 return LHS.getMnemonic() < RHS;
11645 }
11646 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
11647 return LHS < RHS.getMnemonic();
11648 }
11649 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
11650 return LHS.getMnemonic() < RHS.getMnemonic();
11651 }
11652 };
11653} // end anonymous namespace
11654
11655static const OperandMatchEntry OperandMatchTable[2126] = {
11656 /* Operand List Mnemonic, Mask, Operand Class, Features */
11657 { 0 /* .insn_b */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11658 { 8 /* .insn_ca */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11659 { 17 /* .insn_cb */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11660 { 26 /* .insn_ci */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11661 { 35 /* .insn_ciw */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11662 { 45 /* .insn_cj */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11663 { 54 /* .insn_cl */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11664 { 63 /* .insn_cr */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11665 { 72 /* .insn_cs */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11666 { 81 /* .insn_css */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11667 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11668 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11669 { 99 /* .insn_j */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11670 { 99 /* .insn_j */, 4 /* 2 */, MCK_BareSImm21Lsb0, AMFBS_None },
11671 { 107 /* .insn_qc.eai */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11672 { 120 /* .insn_qc.eb */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11673 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11674 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11675 { 144 /* .insn_qc.ej */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11676 { 156 /* .insn_qc.es */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11677 { 168 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11678 { 168 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11679 { 176 /* .insn_r4 */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11680 { 185 /* .insn_s */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11681 { 193 /* .insn_sb */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11682 { 202 /* .insn_u */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11683 { 210 /* .insn_uj */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11684 { 210 /* .insn_uj */, 4 /* 2 */, MCK_BareSImm21Lsb0, AMFBS_None },
11685 { 239 /* add */, 8 /* 3 */, MCK_TPRelAddSymbol, AMFBS_None },
11686 { 250 /* addd */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11687 { 370 /* aif.amoaddg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11688 { 384 /* aif.amoaddg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11689 { 398 /* aif.amoaddl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11690 { 412 /* aif.amoaddl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11691 { 426 /* aif.amoandg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11692 { 440 /* aif.amoandg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11693 { 454 /* aif.amoandl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11694 { 468 /* aif.amoandl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11695 { 482 /* aif.amocmpswapg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11696 { 500 /* aif.amocmpswapg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11697 { 518 /* aif.amocmpswapl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11698 { 536 /* aif.amocmpswapl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11699 { 554 /* aif.amomaxg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11700 { 568 /* aif.amomaxg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11701 { 582 /* aif.amomaxl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11702 { 596 /* aif.amomaxl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11703 { 610 /* aif.amomaxug.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11704 { 625 /* aif.amomaxug.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11705 { 640 /* aif.amomaxul.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11706 { 655 /* aif.amomaxul.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11707 { 670 /* aif.amoming.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11708 { 684 /* aif.amoming.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11709 { 698 /* aif.amominl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11710 { 712 /* aif.amominl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11711 { 726 /* aif.amominug.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11712 { 741 /* aif.amominug.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11713 { 756 /* aif.amominul.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11714 { 771 /* aif.amominul.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11715 { 786 /* aif.amoorg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11716 { 799 /* aif.amoorg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11717 { 812 /* aif.amoorl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11718 { 825 /* aif.amoorl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11719 { 838 /* aif.amoswapg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11720 { 853 /* aif.amoswapg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11721 { 868 /* aif.amoswapl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11722 { 883 /* aif.amoswapl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11723 { 898 /* aif.amoxorg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11724 { 912 /* aif.amoxorg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11725 { 926 /* aif.amoxorl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11726 { 940 /* aif.amoxorl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11727 { 1047 /* aif.fadd.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11728 { 1072 /* aif.famoaddg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11729 { 1088 /* aif.famoaddl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11730 { 1104 /* aif.famoandg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11731 { 1120 /* aif.famoandl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11732 { 1136 /* aif.famomaxg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11733 { 1152 /* aif.famomaxg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11734 { 1168 /* aif.famomaxl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11735 { 1184 /* aif.famomaxl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11736 { 1200 /* aif.famomaxug.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11737 { 1217 /* aif.famomaxul.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11738 { 1234 /* aif.famoming.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11739 { 1250 /* aif.famoming.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11740 { 1266 /* aif.famominl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11741 { 1282 /* aif.famominl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11742 { 1298 /* aif.famominug.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11743 { 1315 /* aif.famominul.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11744 { 1332 /* aif.famoorg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11745 { 1347 /* aif.famoorl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11746 { 1362 /* aif.famoswapg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11747 { 1379 /* aif.famoswapl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11748 { 1396 /* aif.famoxorg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11749 { 1412 /* aif.famoxorl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11750 { 1637 /* aif.fcvt.ps.pw */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11751 { 1652 /* aif.fcvt.ps.pwu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11752 { 1801 /* aif.fcvt.pw.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11753 { 1816 /* aif.fcvt.pwu.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11754 { 1977 /* aif.fdiv.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11755 { 2060 /* aif.fg32b.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11756 { 2073 /* aif.fg32h.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11757 { 2086 /* aif.fg32w.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11758 { 2099 /* aif.fgb.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11759 { 2110 /* aif.fgbg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11760 { 2122 /* aif.fgbl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11761 { 2134 /* aif.fgh.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11762 { 2145 /* aif.fghg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11763 { 2157 /* aif.fghl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11764 { 2169 /* aif.fgw.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11765 { 2180 /* aif.fgwg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11766 { 2192 /* aif.fgwl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11767 { 2352 /* aif.fmadd.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11768 { 2439 /* aif.fmsub.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11769 { 2464 /* aif.fmul.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11770 { 2531 /* aif.fnmadd.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11771 { 2545 /* aif.fnmsub.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11772 { 2671 /* aif.fround.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11773 { 2724 /* aif.fsc32b.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11774 { 2738 /* aif.fsc32h.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11775 { 2752 /* aif.fsc32w.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11776 { 2766 /* aif.fscb.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11777 { 2778 /* aif.fscbg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11778 { 2791 /* aif.fscbl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11779 { 2804 /* aif.fsch.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11780 { 2816 /* aif.fschg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11781 { 2829 /* aif.fschl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11782 { 2842 /* aif.fscw.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11783 { 2854 /* aif.fscwg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11784 { 2867 /* aif.fscwl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11785 { 3055 /* aif.fsub.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11786 { 3268 /* aif.sbg */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11787 { 3276 /* aif.sbl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11788 { 3284 /* aif.shg */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11789 { 3292 /* aif.shl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11790 { 3300 /* amoadd.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11791 { 3309 /* amoadd.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11792 { 3321 /* amoadd.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11793 { 3335 /* amoadd.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11794 { 3347 /* amoadd.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11795 { 3356 /* amoadd.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11796 { 3368 /* amoadd.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11797 { 3382 /* amoadd.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11798 { 3394 /* amoadd.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11799 { 3403 /* amoadd.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11800 { 3415 /* amoadd.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11801 { 3429 /* amoadd.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11802 { 3441 /* amoadd.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11803 { 3450 /* amoadd.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11804 { 3462 /* amoadd.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11805 { 3476 /* amoadd.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11806 { 3488 /* amoand.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11807 { 3497 /* amoand.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11808 { 3509 /* amoand.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11809 { 3523 /* amoand.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11810 { 3535 /* amoand.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11811 { 3544 /* amoand.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11812 { 3556 /* amoand.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11813 { 3570 /* amoand.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11814 { 3582 /* amoand.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11815 { 3591 /* amoand.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11816 { 3603 /* amoand.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11817 { 3617 /* amoand.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11818 { 3629 /* amoand.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11819 { 3638 /* amoand.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11820 { 3650 /* amoand.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11821 { 3664 /* amoand.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11822 { 3676 /* amocas.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11823 { 3685 /* amocas.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11824 { 3697 /* amocas.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11825 { 3711 /* amocas.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11826 { 3723 /* amocas.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11827 { 3723 /* amocas.d */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11828 { 3723 /* amocas.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11829 { 3732 /* amocas.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11830 { 3732 /* amocas.d.aq */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11831 { 3732 /* amocas.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11832 { 3744 /* amocas.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11833 { 3744 /* amocas.d.aqrl */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11834 { 3744 /* amocas.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11835 { 3758 /* amocas.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11836 { 3758 /* amocas.d.rl */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11837 { 3758 /* amocas.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11838 { 3770 /* amocas.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11839 { 3779 /* amocas.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11840 { 3791 /* amocas.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11841 { 3805 /* amocas.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11842 { 3817 /* amocas.q */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11843 { 3817 /* amocas.q */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11844 { 3826 /* amocas.q.aq */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11845 { 3826 /* amocas.q.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11846 { 3838 /* amocas.q.aqrl */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11847 { 3838 /* amocas.q.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11848 { 3852 /* amocas.q.rl */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11849 { 3852 /* amocas.q.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11850 { 3864 /* amocas.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11851 { 3873 /* amocas.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11852 { 3885 /* amocas.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11853 { 3899 /* amocas.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11854 { 3911 /* amomax.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11855 { 3920 /* amomax.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11856 { 3932 /* amomax.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11857 { 3946 /* amomax.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11858 { 3958 /* amomax.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11859 { 3967 /* amomax.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11860 { 3979 /* amomax.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11861 { 3993 /* amomax.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11862 { 4005 /* amomax.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11863 { 4014 /* amomax.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11864 { 4026 /* amomax.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11865 { 4040 /* amomax.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11866 { 4052 /* amomax.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11867 { 4061 /* amomax.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11868 { 4073 /* amomax.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11869 { 4087 /* amomax.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11870 { 4099 /* amomaxu.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11871 { 4109 /* amomaxu.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11872 { 4122 /* amomaxu.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11873 { 4137 /* amomaxu.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11874 { 4150 /* amomaxu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11875 { 4160 /* amomaxu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11876 { 4173 /* amomaxu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11877 { 4188 /* amomaxu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11878 { 4201 /* amomaxu.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11879 { 4211 /* amomaxu.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11880 { 4224 /* amomaxu.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11881 { 4239 /* amomaxu.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11882 { 4252 /* amomaxu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11883 { 4262 /* amomaxu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11884 { 4275 /* amomaxu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11885 { 4290 /* amomaxu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11886 { 4303 /* amomin.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11887 { 4312 /* amomin.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11888 { 4324 /* amomin.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11889 { 4338 /* amomin.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11890 { 4350 /* amomin.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11891 { 4359 /* amomin.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11892 { 4371 /* amomin.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11893 { 4385 /* amomin.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11894 { 4397 /* amomin.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11895 { 4406 /* amomin.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11896 { 4418 /* amomin.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11897 { 4432 /* amomin.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11898 { 4444 /* amomin.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11899 { 4453 /* amomin.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11900 { 4465 /* amomin.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11901 { 4479 /* amomin.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11902 { 4491 /* amominu.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11903 { 4501 /* amominu.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11904 { 4514 /* amominu.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11905 { 4529 /* amominu.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11906 { 4542 /* amominu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11907 { 4552 /* amominu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11908 { 4565 /* amominu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11909 { 4580 /* amominu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11910 { 4593 /* amominu.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11911 { 4603 /* amominu.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11912 { 4616 /* amominu.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11913 { 4631 /* amominu.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11914 { 4644 /* amominu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11915 { 4654 /* amominu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11916 { 4667 /* amominu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11917 { 4682 /* amominu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11918 { 4695 /* amoor.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11919 { 4703 /* amoor.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11920 { 4714 /* amoor.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11921 { 4727 /* amoor.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11922 { 4738 /* amoor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11923 { 4746 /* amoor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11924 { 4757 /* amoor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11925 { 4770 /* amoor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11926 { 4781 /* amoor.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11927 { 4789 /* amoor.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11928 { 4800 /* amoor.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11929 { 4813 /* amoor.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11930 { 4824 /* amoor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11931 { 4832 /* amoor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11932 { 4843 /* amoor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11933 { 4856 /* amoor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11934 { 4867 /* amoswap.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11935 { 4877 /* amoswap.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11936 { 4890 /* amoswap.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11937 { 4905 /* amoswap.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11938 { 4918 /* amoswap.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11939 { 4928 /* amoswap.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11940 { 4941 /* amoswap.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11941 { 4956 /* amoswap.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11942 { 4969 /* amoswap.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11943 { 4979 /* amoswap.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11944 { 4992 /* amoswap.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11945 { 5007 /* amoswap.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11946 { 5020 /* amoswap.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11947 { 5030 /* amoswap.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11948 { 5043 /* amoswap.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11949 { 5058 /* amoswap.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11950 { 5071 /* amoxor.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11951 { 5080 /* amoxor.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11952 { 5092 /* amoxor.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11953 { 5106 /* amoxor.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11954 { 5118 /* amoxor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11955 { 5127 /* amoxor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11956 { 5139 /* amoxor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11957 { 5153 /* amoxor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11958 { 5165 /* amoxor.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11959 { 5174 /* amoxor.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11960 { 5186 /* amoxor.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11961 { 5200 /* amoxor.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11962 { 5212 /* amoxor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11963 { 5221 /* amoxor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11964 { 5233 /* amoxor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11965 { 5247 /* amoxor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11966 { 5588 /* c.lbu */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11967 { 5594 /* c.ld */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11968 { 5599 /* c.ldsp */, 1 /* 0 */, MCK_GPRPairNoX0RV32, AMFBS_HasStdExtZclsd_IsRV32 },
11969 { 5606 /* c.lh */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11970 { 5611 /* c.lhu */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11971 { 5628 /* c.lw */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11972 { 5774 /* c.sb */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11973 { 5779 /* c.sd */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11974 { 5784 /* c.sdsp */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11975 { 5809 /* c.sh */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11976 { 5895 /* c.sw */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11977 { 5948 /* call */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
11978 { 5948 /* call */, 2 /* 1 */, MCK_CallSymbol, AMFBS_None },
11979 { 5953 /* cbo.clean */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
11980 { 5963 /* cbo.flush */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
11981 { 5973 /* cbo.inval */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
11982 { 5983 /* cbo.zero */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicboz },
11983 { 6064 /* cm.pop */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11984 { 6064 /* cm.pop */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
11985 { 6071 /* cm.popret */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11986 { 6071 /* cm.popret */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
11987 { 6081 /* cm.popretz */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11988 { 6081 /* cm.popretz */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
11989 { 6092 /* cm.push */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasStdExtZcmp },
11990 { 6092 /* cm.push */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11991 { 6111 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11992 { 6111 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11993 { 6116 /* csrci */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11994 { 6122 /* csrr */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11995 { 6127 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11996 { 6127 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11997 { 6133 /* csrrci */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11998 { 6140 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11999 { 6140 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
12000 { 6146 /* csrrsi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
12001 { 6153 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
12002 { 6153 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
12003 { 6159 /* csrrwi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
12004 { 6166 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
12005 { 6166 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
12006 { 6171 /* csrsi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
12007 { 6177 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
12008 { 6177 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
12009 { 6182 /* csrwi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
12010 { 7942 /* cv.elw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXCVelw_IsRV32 },
12011 { 8146 /* cv.lb */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
12012 { 8152 /* cv.lbu */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
12013 { 8159 /* cv.lh */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
12014 { 8165 /* cv.lhu */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
12015 { 8172 /* cv.lw */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
12016 { 8821 /* cv.sb */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
12017 { 9091 /* cv.sh */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
12018 { 9706 /* cv.sw */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
12019 { 9838 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12020 { 9838 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12021 { 9845 /* fabs.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12022 { 9859 /* fabs.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12023 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
12024 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12025 { 9866 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12026 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12027 { 9866 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12028 { 9873 /* fadd.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12029 { 9873 /* fadd.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12030 { 9873 /* fadd.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12031 { 9880 /* fadd.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12032 { 9887 /* fadd.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
12033 { 9887 /* fadd.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12034 { 9887 /* fadd.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12035 { 9894 /* fclass.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12036 { 9894 /* fclass.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12037 { 9903 /* fclass.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12038 { 9921 /* fclass.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12039 { 9930 /* fcvt.bf16.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfbfmin },
12040 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin_HasStdExtD },
12041 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
12042 { 9942 /* fcvt.d.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
12043 { 9942 /* fcvt.d.h */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
12044 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
12045 { 9942 /* fcvt.d.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
12046 { 9942 /* fcvt.d.h */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
12047 { 9951 /* fcvt.d.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
12048 { 9951 /* fcvt.d.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
12049 { 9951 /* fcvt.d.l */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
12050 { 9960 /* fcvt.d.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
12051 { 9960 /* fcvt.d.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
12052 { 9960 /* fcvt.d.lu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
12053 { 9970 /* fcvt.d.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12054 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
12055 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
12056 { 9979 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
12057 { 9979 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12058 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
12059 { 9979 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
12060 { 9979 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12061 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
12062 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
12063 { 9988 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12064 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
12065 { 9988 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12066 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
12067 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
12068 { 9997 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12069 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
12070 { 9997 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12071 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfhmin_HasStdExtD },
12072 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
12073 { 10007 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
12074 { 10007 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
12075 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
12076 { 10007 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
12077 { 10007 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
12078 { 10016 /* fcvt.h.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
12079 { 10016 /* fcvt.h.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
12080 { 10016 /* fcvt.h.l */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
12081 { 10025 /* fcvt.h.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
12082 { 10025 /* fcvt.h.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
12083 { 10025 /* fcvt.h.lu */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
12084 { 10035 /* fcvt.h.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfhmin_HasStdExtQ },
12085 { 10044 /* fcvt.h.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfhmin },
12086 { 10044 /* fcvt.h.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin },
12087 { 10044 /* fcvt.h.s */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
12088 { 10044 /* fcvt.h.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
12089 { 10053 /* fcvt.h.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12090 { 10053 /* fcvt.h.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12091 { 10053 /* fcvt.h.w */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12092 { 10062 /* fcvt.h.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12093 { 10062 /* fcvt.h.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12094 { 10062 /* fcvt.h.wu */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12095 { 10072 /* fcvt.l.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
12096 { 10072 /* fcvt.l.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
12097 { 10072 /* fcvt.l.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
12098 { 10081 /* fcvt.l.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
12099 { 10081 /* fcvt.l.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
12100 { 10081 /* fcvt.l.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
12101 { 10090 /* fcvt.l.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ_IsRV64 },
12102 { 10099 /* fcvt.l.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
12103 { 10099 /* fcvt.l.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
12104 { 10099 /* fcvt.l.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
12105 { 10108 /* fcvt.lu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
12106 { 10108 /* fcvt.lu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
12107 { 10108 /* fcvt.lu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
12108 { 10118 /* fcvt.lu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
12109 { 10118 /* fcvt.lu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
12110 { 10118 /* fcvt.lu.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
12111 { 10128 /* fcvt.lu.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ_IsRV64 },
12112 { 10138 /* fcvt.lu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
12113 { 10138 /* fcvt.lu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
12114 { 10138 /* fcvt.lu.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
12115 { 10148 /* fcvt.q.d */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
12116 { 10157 /* fcvt.q.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin_HasStdExtQ },
12117 { 10166 /* fcvt.q.l */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ_IsRV64 },
12118 { 10175 /* fcvt.q.lu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ_IsRV64 },
12119 { 10185 /* fcvt.q.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
12120 { 10194 /* fcvt.q.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
12121 { 10203 /* fcvt.q.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
12122 { 10213 /* fcvt.s.bf16 */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfbfmin },
12123 { 10225 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
12124 { 10225 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12125 { 10225 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
12126 { 10225 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12127 { 10225 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12128 { 10225 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
12129 { 10225 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12130 { 10234 /* fcvt.s.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin },
12131 { 10234 /* fcvt.s.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin },
12132 { 10234 /* fcvt.s.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
12133 { 10234 /* fcvt.s.h */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
12134 { 10243 /* fcvt.s.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
12135 { 10243 /* fcvt.s.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
12136 { 10243 /* fcvt.s.l */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
12137 { 10252 /* fcvt.s.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
12138 { 10252 /* fcvt.s.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
12139 { 10252 /* fcvt.s.lu */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
12140 { 10262 /* fcvt.s.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12141 { 10271 /* fcvt.s.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
12142 { 10271 /* fcvt.s.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12143 { 10271 /* fcvt.s.w */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12144 { 10280 /* fcvt.s.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
12145 { 10280 /* fcvt.s.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12146 { 10280 /* fcvt.s.wu */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12147 { 10290 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
12148 { 10290 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12149 { 10290 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12150 { 10290 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12151 { 10290 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12152 { 10299 /* fcvt.w.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12153 { 10299 /* fcvt.w.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12154 { 10299 /* fcvt.w.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12155 { 10308 /* fcvt.w.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12156 { 10317 /* fcvt.w.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
12157 { 10317 /* fcvt.w.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12158 { 10317 /* fcvt.w.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12159 { 10326 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
12160 { 10326 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12161 { 10326 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12162 { 10326 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12163 { 10326 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12164 { 10336 /* fcvt.wu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12165 { 10336 /* fcvt.wu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12166 { 10336 /* fcvt.wu.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12167 { 10346 /* fcvt.wu.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12168 { 10356 /* fcvt.wu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
12169 { 10356 /* fcvt.wu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12170 { 10356 /* fcvt.wu.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12171 { 10366 /* fcvtmod.w.d */, 4 /* 2 */, MCK_RTZArg, AMFBS_HasStdExtZfa_HasStdExtD },
12172 { 10378 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
12173 { 10378 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12174 { 10378 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12175 { 10378 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12176 { 10378 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12177 { 10385 /* fdiv.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12178 { 10385 /* fdiv.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12179 { 10385 /* fdiv.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12180 { 10392 /* fdiv.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12181 { 10399 /* fdiv.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
12182 { 10399 /* fdiv.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12183 { 10399 /* fdiv.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12184 { 10406 /* fence */, 3 /* 0, 1 */, MCK_FenceArg, AMFBS_None },
12185 { 10430 /* feq.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12186 { 10430 /* feq.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12187 { 10436 /* feq.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12188 { 10448 /* feq.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12189 { 10454 /* fge.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12190 { 10454 /* fge.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12191 { 10460 /* fge.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12192 { 10472 /* fge.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12193 { 10506 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12194 { 10506 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12195 { 10512 /* fgt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12196 { 10524 /* fgt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12197 { 10558 /* fld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
12198 { 10562 /* fle.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12199 { 10562 /* fle.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12200 { 10568 /* fle.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12201 { 10580 /* fle.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12202 { 10614 /* flh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasHalfFPLoadStoreMove },
12203 { 10618 /* fli.d */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtD },
12204 { 10624 /* fli.h */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh },
12205 { 10630 /* fli.q */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtQ },
12206 { 10636 /* fli.s */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa },
12207 { 10642 /* flq */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtQ },
12208 { 10646 /* flt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12209 { 10646 /* flt.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12210 { 10652 /* flt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12211 { 10664 /* flt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12212 { 10698 /* flw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
12213 { 10702 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
12214 { 10702 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12215 { 10702 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12216 { 10702 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12217 { 10702 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12218 { 10710 /* fmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12219 { 10710 /* fmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12220 { 10710 /* fmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12221 { 10718 /* fmadd.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12222 { 10726 /* fmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
12223 { 10726 /* fmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12224 { 10726 /* fmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12225 { 10734 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12226 { 10734 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12227 { 10741 /* fmax.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12228 { 10755 /* fmax.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12229 { 10794 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12230 { 10794 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12231 { 10801 /* fmin.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12232 { 10815 /* fmin.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12233 { 10854 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
12234 { 10854 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12235 { 10854 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12236 { 10854 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12237 { 10854 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12238 { 10862 /* fmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12239 { 10862 /* fmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12240 { 10862 /* fmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12241 { 10870 /* fmsub.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12242 { 10878 /* fmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
12243 { 10878 /* fmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12244 { 10878 /* fmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12245 { 10886 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
12246 { 10886 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12247 { 10886 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12248 { 10886 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12249 { 10886 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12250 { 10893 /* fmul.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12251 { 10893 /* fmul.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12252 { 10893 /* fmul.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12253 { 10900 /* fmul.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12254 { 10907 /* fmul.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
12255 { 10907 /* fmul.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12256 { 10907 /* fmul.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12257 { 10914 /* fmv.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12258 { 10914 /* fmv.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12259 { 10928 /* fmv.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12260 { 10948 /* fmv.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12261 { 11022 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12262 { 11022 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12263 { 11029 /* fneg.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12264 { 11043 /* fneg.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12265 { 11050 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
12266 { 11050 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12267 { 11050 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12268 { 11050 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12269 { 11050 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12270 { 11059 /* fnmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12271 { 11059 /* fnmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12272 { 11059 /* fnmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12273 { 11068 /* fnmadd.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12274 { 11077 /* fnmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
12275 { 11077 /* fnmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12276 { 11077 /* fnmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12277 { 11086 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
12278 { 11086 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12279 { 11086 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12280 { 11086 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12281 { 11086 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12282 { 11095 /* fnmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12283 { 11095 /* fnmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12284 { 11095 /* fnmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12285 { 11104 /* fnmsub.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12286 { 11113 /* fnmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
12287 { 11113 /* fnmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12288 { 11113 /* fnmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12289 { 11136 /* fround.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
12290 { 11145 /* fround.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
12291 { 11154 /* fround.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtQ },
12292 { 11163 /* fround.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa },
12293 { 11172 /* froundnx.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
12294 { 11183 /* froundnx.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
12295 { 11194 /* froundnx.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtQ },
12296 { 11205 /* froundnx.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa },
12297 { 11227 /* fsd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
12298 { 11248 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12299 { 11248 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12300 { 11256 /* fsgnj.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12301 { 11272 /* fsgnj.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12302 { 11280 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12303 { 11280 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12304 { 11289 /* fsgnjn.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12305 { 11307 /* fsgnjn.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12306 { 11316 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12307 { 11316 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12308 { 11325 /* fsgnjx.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12309 { 11343 /* fsgnjx.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12310 { 11352 /* fsh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasHalfFPLoadStoreMove },
12311 { 11356 /* fsq */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtQ },
12312 { 11360 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
12313 { 11360 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12314 { 11360 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12315 { 11360 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12316 { 11360 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12317 { 11368 /* fsqrt.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12318 { 11368 /* fsqrt.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12319 { 11368 /* fsqrt.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12320 { 11376 /* fsqrt.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12321 { 11384 /* fsqrt.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
12322 { 11384 /* fsqrt.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12323 { 11384 /* fsqrt.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12324 { 11403 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
12325 { 11403 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
12326 { 11403 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
12327 { 11403 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
12328 { 11403 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
12329 { 11410 /* fsub.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
12330 { 11410 /* fsub.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
12331 { 11410 /* fsub.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
12332 { 11417 /* fsub.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
12333 { 11424 /* fsub.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
12334 { 11424 /* fsub.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
12335 { 11424 /* fsub.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
12336 { 11431 /* fsw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
12337 { 11483 /* hlv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12338 { 11489 /* hlv.bu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12339 { 11496 /* hlv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
12340 { 11502 /* hlv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12341 { 11508 /* hlv.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12342 { 11515 /* hlv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12343 { 11521 /* hlv.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
12344 { 11528 /* hlvx.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12345 { 11536 /* hlvx.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12346 { 11544 /* hsv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12347 { 11550 /* hsv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
12348 { 11556 /* hsv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12349 { 11562 /* hsv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
12350 { 11568 /* j */, 1 /* 0 */, MCK_BareSImm21Lsb0, AMFBS_None },
12351 { 11570 /* jal */, 1 /* 0 */, MCK_BareSImm21Lsb0, AMFBS_None },
12352 { 11570 /* jal */, 2 /* 1 */, MCK_BareSImm21Lsb0, AMFBS_None },
12353 { 11574 /* jalr */, 32 /* 5 */, MCK_TLSDESCCallSymbol, AMFBS_None },
12354 { 11582 /* jump */, 1 /* 0 */, MCK_PseudoJumpSymbol, AMFBS_None },
12355 { 11587 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12356 { 11590 /* la.tls.gd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12357 { 11600 /* la.tls.ie */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12358 { 11610 /* lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12359 { 11610 /* lb */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12360 { 11613 /* lb.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12361 { 11619 /* lb.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12362 { 11627 /* lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12363 { 11627 /* lbu */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12364 { 11631 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
12365 { 11631 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZilsd_IsRV32 },
12366 { 11631 /* ld */, 1 /* 0 */, MCK_GPRPairNoX0RV32, AMFBS_HasStdExtZilsd_IsRV32 },
12367 { 11631 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12368 { 11634 /* ld.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12369 { 11640 /* ld.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12370 { 11648 /* lga */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12371 { 11652 /* lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12372 { 11652 /* lh */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12373 { 11655 /* lh.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12374 { 11661 /* lh.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12375 { 11669 /* lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12376 { 11669 /* lhu */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12377 { 11676 /* lla */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12378 { 11685 /* lr.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12379 { 11690 /* lr.d.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12380 { 11698 /* lr.d.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12381 { 11708 /* lr.d.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12382 { 11716 /* lr.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12383 { 11721 /* lr.w.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12384 { 11729 /* lr.w.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12385 { 11739 /* lr.w.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12386 { 11751 /* lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12387 { 11751 /* lw */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12388 { 11754 /* lw.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12389 { 11760 /* lw.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12390 { 11768 /* lwu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
12391 { 11772 /* lxb */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12392 { 11776 /* lxbu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12393 { 11781 /* lxd */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12394 { 11785 /* lxh */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12395 { 11789 /* lxhu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12396 { 11794 /* lxsb */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12397 { 11799 /* lxsbu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12398 { 11805 /* lxsd */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12399 { 11810 /* lxsh */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12400 { 11815 /* lxshu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12401 { 11821 /* lxsuwb */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12402 { 11828 /* lxsuwbu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12403 { 11836 /* lxsuwd */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12404 { 11843 /* lxsuwh */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12405 { 11850 /* lxsuwhu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12406 { 11858 /* lxsuww */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12407 { 11865 /* lxsuwwu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12408 { 11873 /* lxsw */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12409 { 11878 /* lxswu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12410 { 11884 /* lxw */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx },
12411 { 11888 /* lxwu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZilx_IsRV64 },
12412 { 12756 /* mqrwacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12413 { 12764 /* mqwacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12414 { 13067 /* mvd */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12415 { 13080 /* nclip */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12416 { 13086 /* nclipi */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12417 { 13093 /* nclipiu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12418 { 13101 /* nclipr */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12419 { 13108 /* nclipri */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12420 { 13116 /* nclipriu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12421 { 13125 /* nclipru */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12422 { 13133 /* nclipu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12423 { 13461 /* nds.vd4dots.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
12424 { 13476 /* nds.vd4dotsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
12425 { 13492 /* nds.vd4dotu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
12426 { 13525 /* nds.vfpmadb.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVPackFPH },
12427 { 13540 /* nds.vfpmadt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVPackFPH },
12428 { 13555 /* nds.vfwcvt.f.b.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF },
12429 { 13572 /* nds.vfwcvt.f.bu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF },
12430 { 13590 /* nds.vfwcvt.f.n.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF },
12431 { 13607 /* nds.vfwcvt.f.nu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH_HasVInstructionsAnyF },
12432 { 13643 /* nds.vle4.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntH },
12433 { 13654 /* nds.vln8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
12434 { 13654 /* nds.vln8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
12435 { 13665 /* nds.vlnu8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
12436 { 13665 /* nds.vlnu8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
12437 { 13681 /* negd */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12438 { 13699 /* nsra */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12439 { 13704 /* nsrai */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12440 { 13710 /* nsrar */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12441 { 13716 /* nsrari */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12442 { 13723 /* nsrl */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12443 { 13728 /* nsrli */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12444 { 13790 /* paadd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12445 { 13799 /* paadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12446 { 13808 /* paadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12447 { 13842 /* paaddu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12448 { 13852 /* paaddu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12449 { 13862 /* paaddu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12450 { 13890 /* paas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12451 { 13922 /* pabd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12452 { 13930 /* pabd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12453 { 13976 /* pabdu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12454 { 13985 /* pabdu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12455 { 14009 /* pabs.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12456 { 14017 /* pabs.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12457 { 14064 /* padd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12458 { 14072 /* padd.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12459 { 14081 /* padd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12460 { 14089 /* padd.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12461 { 14098 /* padd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12462 { 14106 /* padd.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12463 { 14145 /* pas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12464 { 14167 /* pasa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12465 { 14200 /* pasub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12466 { 14209 /* pasub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12467 { 14218 /* pasub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12468 { 14252 /* pasubu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12469 { 14262 /* pasubu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12470 { 14272 /* pasubu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12471 { 14312 /* pli.db */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12472 { 14319 /* pli.dh */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12473 { 14338 /* plui.dh */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12474 { 14629 /* pm2wadd.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12475 { 14639 /* pm2wadd.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12476 { 14650 /* pm2wadda.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12477 { 14661 /* pm2wadda.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12478 { 14673 /* pm2waddasu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12479 { 14686 /* pm2waddau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12480 { 14698 /* pm2waddsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12481 { 14710 /* pm2waddu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12482 { 14721 /* pm2wsub.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12483 { 14731 /* pm2wsub.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12484 { 14742 /* pm2wsuba.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12485 { 14753 /* pm2wsuba.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12486 { 15001 /* pmax.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12487 { 15009 /* pmax.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12488 { 15017 /* pmax.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12489 { 15047 /* pmaxu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12490 { 15056 /* pmaxu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12491 { 15065 /* pmaxu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12492 { 15327 /* pmin.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12493 { 15335 /* pmin.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12494 { 15343 /* pmin.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12495 { 15373 /* pminu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12496 { 15382 /* pminu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12497 { 15391 /* pminu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12498 { 15585 /* pmqrwacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12499 { 15596 /* pmqwacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12500 { 15614 /* pmseq.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12501 { 15623 /* pmseq.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12502 { 15632 /* pmseq.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12503 { 15666 /* pmseqz.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12504 { 15676 /* pmseqz.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12505 { 15686 /* pmseqz.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12506 { 15722 /* pmsgt.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12507 { 15731 /* pmsgt.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12508 { 15740 /* pmsgt.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12509 { 15774 /* pmsgtu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12510 { 15784 /* pmsgtu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12511 { 15794 /* pmsgtu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12512 { 15831 /* pmsgtz.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12513 { 15841 /* pmsgtz.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12514 { 15851 /* pmsgtz.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12515 { 15887 /* pmslt.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12516 { 15896 /* pmslt.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12517 { 15905 /* pmslt.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12518 { 15939 /* pmsltu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12519 { 15949 /* pmsltu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12520 { 15959 /* pmsltu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12521 { 15996 /* pmsltz.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12522 { 16006 /* pmsltz.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12523 { 16016 /* pmsltz.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12524 { 16053 /* pmsnez.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12525 { 16063 /* pmsnez.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12526 { 16073 /* pmsnez.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12527 { 16542 /* pmv.dbs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12528 { 16550 /* pmv.dhs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12529 { 16558 /* pmv.dws */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12530 { 16580 /* pnclip.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12531 { 16590 /* pnclip.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12532 { 16600 /* pnclipi.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12533 { 16610 /* pnclipi.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12534 { 16620 /* pnclipiu.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12535 { 16631 /* pnclipiu.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12536 { 16672 /* pnclipr.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12537 { 16683 /* pnclipr.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12538 { 16694 /* pnclipri.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12539 { 16705 /* pnclipri.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12540 { 16716 /* pnclipriu.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12541 { 16728 /* pnclipriu.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12542 { 16740 /* pnclipru.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12543 { 16752 /* pnclipru.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12544 { 16764 /* pnclipu.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12545 { 16775 /* pnclipu.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12546 { 16819 /* pncvt.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12547 { 16827 /* pncvt.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12548 { 16853 /* pncvth.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12549 { 16862 /* pncvth.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12550 { 16898 /* pneg.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12551 { 16906 /* pneg.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12552 { 16914 /* pneg.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12553 { 16936 /* pnsra.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12554 { 16945 /* pnsra.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12555 { 16954 /* pnsrai.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12556 { 16963 /* pnsrai.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12557 { 16972 /* pnsrar.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12558 { 16982 /* pnsrar.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12559 { 16992 /* pnsrari.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12560 { 17002 /* pnsrari.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12561 { 17012 /* pnsrl.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12562 { 17021 /* pnsrl.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12563 { 17030 /* pnsrli.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12564 { 17039 /* pnsrli.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12565 { 17057 /* ppaire.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12566 { 17067 /* ppaire.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12567 { 17105 /* ppaireo.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12568 { 17116 /* ppaireo.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12569 { 17156 /* ppairo.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12570 { 17166 /* ppairo.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12571 { 17204 /* ppairoe.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12572 { 17215 /* ppairoe.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12573 { 17257 /* predsum.dbs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12574 { 17269 /* predsum.dhs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12575 { 17315 /* predsumu.dbs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12576 { 17328 /* predsumu.dhs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12577 { 17398 /* psa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12578 { 17428 /* psabs.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12579 { 17437 /* psabs.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12580 { 17462 /* psadd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12581 { 17471 /* psadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12582 { 17480 /* psadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12583 { 17514 /* psaddu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12584 { 17524 /* psaddu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12585 { 17534 /* psaddu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12586 { 17562 /* psas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12587 { 17587 /* psati.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12588 { 17596 /* psati.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12589 { 17621 /* psext.dh.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12590 { 17632 /* psext.dw.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12591 { 17643 /* psext.dw.h */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12592 { 17684 /* psh1add.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12593 { 17695 /* psh1add.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12594 { 17734 /* psll.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12595 { 17743 /* psll.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12596 { 17752 /* psll.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12597 { 17785 /* pslli.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12598 { 17794 /* pslli.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12599 { 17803 /* pslli.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12600 { 17836 /* psra.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12601 { 17845 /* psra.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12602 { 17854 /* psra.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12603 { 17887 /* psrai.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12604 { 17896 /* psrai.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12605 { 17905 /* psrai.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12606 { 17930 /* psrari.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12607 { 17940 /* psrari.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12608 { 17976 /* psrl.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12609 { 17985 /* psrl.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12610 { 17994 /* psrl.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12611 { 18027 /* psrli.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12612 { 18036 /* psrli.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12613 { 18045 /* psrli.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12614 { 18070 /* pssa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12615 { 18095 /* pssh1sadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12616 { 18108 /* pssh1sadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12617 { 18145 /* pssha.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12618 { 18155 /* pssha.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12619 { 18183 /* psshar.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12620 { 18194 /* psshar.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12621 { 18225 /* psshl.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12622 { 18235 /* psshl.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12623 { 18263 /* psshlr.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12624 { 18274 /* psshlr.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12625 { 18305 /* psslai.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12626 { 18315 /* psslai.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12627 { 18351 /* pssub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12628 { 18360 /* pssub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12629 { 18369 /* pssub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12630 { 18403 /* pssubu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12631 { 18413 /* pssubu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12632 { 18423 /* pssubu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12633 { 18458 /* psub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12634 { 18466 /* psub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12635 { 18474 /* psub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12636 { 18496 /* pusati.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12637 { 18506 /* pusati.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12638 { 18534 /* pwadd.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12639 { 18542 /* pwadd.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12640 { 18550 /* pwadda.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12641 { 18559 /* pwadda.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12642 { 18568 /* pwaddau.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12643 { 18578 /* pwaddau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12644 { 18588 /* pwaddu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12645 { 18597 /* pwaddu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12646 { 18606 /* pwcvt.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12647 { 18614 /* pwcvt.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12648 { 18622 /* pwcvth.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12649 { 18631 /* pwcvth.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12650 { 18660 /* pwcvtu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12651 { 18669 /* pwcvtu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12652 { 18698 /* pwmacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12653 { 18707 /* pwmaccsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12654 { 18718 /* pwmaccu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12655 { 18728 /* pwmul.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12656 { 18736 /* pwmul.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12657 { 18744 /* pwmulsu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12658 { 18754 /* pwmulsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12659 { 18764 /* pwmulu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12660 { 18773 /* pwmulu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12661 { 18782 /* pwsla.bs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12662 { 18791 /* pwsla.hs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12663 { 18800 /* pwslai.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12664 { 18809 /* pwslai.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12665 { 18818 /* pwsll.bs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12666 { 18827 /* pwsll.hs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12667 { 18836 /* pwslli.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12668 { 18845 /* pwslli.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12669 { 18854 /* pwsub.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12670 { 18862 /* pwsub.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12671 { 18870 /* pwsuba.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12672 { 18879 /* pwsuba.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12673 { 18888 /* pwsubau.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12674 { 18898 /* pwsubau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12675 { 18908 /* pwsubu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12676 { 18917 /* pwsubu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12677 { 18926 /* pzext.dh.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12678 { 18937 /* pzext.dw.h */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12679 { 19374 /* qc.cm.pop */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12680 { 19374 /* qc.cm.pop */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
12681 { 19384 /* qc.cm.popret */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12682 { 19384 /* qc.cm.popret */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
12683 { 19397 /* qc.cm.popretz */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12684 { 19397 /* qc.cm.popretz */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
12685 { 19411 /* qc.cm.push */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasVendorXqccmp },
12686 { 19411 /* qc.cm.push */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12687 { 19422 /* qc.cm.pushfp */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasVendorXqccmp },
12688 { 19422 /* qc.cm.pushfp */, 1 /* 0 */, MCK_RegListS0, AMFBS_HasVendorXqccmp },
12689 { 19609 /* qc.e.lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12690 { 19617 /* qc.e.lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12691 { 19626 /* qc.e.lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12692 { 19634 /* qc.e.lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12693 { 19643 /* qc.e.li */, 2 /* 1 */, MCK_BareSymbolQC_E_LI, AMFBS_HasVendorXqcili_IsRV32 },
12694 { 19651 /* qc.e.lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12695 { 19678 /* qc.e.sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12696 { 19686 /* qc.e.sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12697 { 19694 /* qc.e.sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12698 { 20826 /* sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12699 { 20826 /* sb */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12700 { 20829 /* sb.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12701 { 20837 /* sb.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12702 { 20843 /* sc.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12703 { 20848 /* sc.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12704 { 20856 /* sc.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12705 { 20866 /* sc.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12706 { 20874 /* sc.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12707 { 20879 /* sc.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12708 { 20887 /* sc.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12709 { 20897 /* sc.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12710 { 20932 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
12711 { 20932 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZilsd_IsRV32 },
12712 { 20932 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12713 { 20932 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12714 { 20935 /* sd.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12715 { 20943 /* sd.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12716 { 21422 /* sf.vfexp.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfexpAny },
12717 { 21433 /* sf.vfexpa.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfexpa },
12718 { 21445 /* sf.vfnrclip.x.f.qf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
12719 { 21464 /* sf.vfnrclip.xu.f.qf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
12720 { 21501 /* sf.vlte16 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12721 { 21511 /* sf.vlte32 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12722 { 21521 /* sf.vlte64 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12723 { 21531 /* sf.vlte8 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12724 { 21708 /* sf.vsettnt */, 4 /* 2 */, MCK_XSfmmVType, AMFBS_HasVendorXSfmmbase },
12725 { 21719 /* sf.vste16 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12726 { 21729 /* sf.vste32 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12727 { 21739 /* sf.vste64 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12728 { 21749 /* sf.vste8 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12729 { 21863 /* sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12730 { 21863 /* sh */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12731 { 21866 /* sh.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12732 { 21874 /* sh.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12733 { 22265 /* smt.vmadot */, 8 /* 3 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12734 { 22276 /* smt.vmadot.hp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12735 { 22290 /* smt.vmadot.sp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12736 { 22304 /* smt.vmadot1 */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12737 { 22316 /* smt.vmadot1su */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12738 { 22330 /* smt.vmadot1u */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12739 { 22343 /* smt.vmadot1us */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12740 { 22357 /* smt.vmadot2 */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12741 { 22369 /* smt.vmadot2su */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12742 { 22383 /* smt.vmadot2u */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12743 { 22396 /* smt.vmadot2us */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12744 { 22410 /* smt.vmadot3 */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12745 { 22422 /* smt.vmadot3su */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12746 { 22436 /* smt.vmadot3u */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12747 { 22449 /* smt.vmadot3us */, 8 /* 3 */, MCK_SMTI8, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12748 { 22463 /* smt.vmadotsu */, 8 /* 3 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12749 { 22476 /* smt.vmadotsu.hp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12750 { 22492 /* smt.vmadotsu.sp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12751 { 22508 /* smt.vmadotu */, 8 /* 3 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12752 { 22520 /* smt.vmadotu.hp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12753 { 22535 /* smt.vmadotu.sp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12754 { 22550 /* smt.vmadotus */, 8 /* 3 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12755 { 22563 /* smt.vmadotus.hp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12756 { 22579 /* smt.vmadotus.sp */, 32 /* 5 */, MCK_SMTVType, AMFBS_HasVendorXSMTVDotII_IsRV64 },
12757 { 22742 /* ssamoswap.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12758 { 22754 /* ssamoswap.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12759 { 22769 /* ssamoswap.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12760 { 22786 /* ssamoswap.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12761 { 22801 /* ssamoswap.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12762 { 22813 /* ssamoswap.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12763 { 22828 /* ssamoswap.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12764 { 22845 /* ssamoswap.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12765 { 22934 /* subd */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12766 { 22944 /* sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12767 { 22944 /* sw */, 48 /* 4, 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12768 { 22947 /* sw.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12769 { 22955 /* sw.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12770 { 22961 /* tail */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
12771 { 22961 /* tail */, 1 /* 0 */, MCK_TailCallSymbol, AMFBS_None },
12772 { 23949 /* th.vmaqa.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12773 { 23961 /* th.vmaqa.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12774 { 23973 /* th.vmaqasu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12775 { 23987 /* th.vmaqasu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12776 { 24001 /* th.vmaqau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12777 { 24014 /* th.vmaqau.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12778 { 24027 /* th.vmaqaus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12779 { 24107 /* vaadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12780 { 24116 /* vaadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12781 { 24125 /* vaaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12782 { 24135 /* vaaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12783 { 24145 /* vabd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12784 { 24153 /* vabd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12785 { 24161 /* vabdu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12786 { 24170 /* vabdu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12787 { 24179 /* vabs.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12788 { 24213 /* vadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12789 { 24221 /* vadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12790 { 24229 /* vadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12791 { 24348 /* vand.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12792 { 24356 /* vand.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12793 { 24364 /* vand.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12794 { 24372 /* vandn.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12795 { 24381 /* vandn.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12796 { 24390 /* vasub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12797 { 24399 /* vasub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12798 { 24408 /* vasubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12799 { 24418 /* vasubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12800 { 24428 /* vbrev.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12801 { 24436 /* vbrev8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12802 { 24445 /* vclmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12803 { 24455 /* vclmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12804 { 24465 /* vclmulh.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12805 { 24476 /* vclmulh.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12806 { 24487 /* vclz.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12807 { 24507 /* vcpop.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12808 { 24515 /* vcpop.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12809 { 24523 /* vctz.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12810 { 24530 /* vdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12811 { 24538 /* vdiv.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12812 { 24546 /* vdivu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12813 { 24555 /* vdivu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12814 { 24564 /* vdot4a.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12815 { 24574 /* vdot4a.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12816 { 24584 /* vdot4asu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12817 { 24596 /* vdot4asu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12818 { 24608 /* vdot4au.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12819 { 24619 /* vdot4au.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12820 { 24630 /* vdot4aus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12821 { 24642 /* vf8wimmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12822 { 24656 /* vf8wmmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12823 { 24669 /* vfabs.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12824 { 24677 /* vfadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12825 { 24686 /* vfadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12826 { 24695 /* vfbdota.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbdota32f },
12827 { 24706 /* vfclass.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12828 { 24716 /* vfcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12829 { 24728 /* vfcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12830 { 24741 /* vfcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12831 { 24757 /* vfcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12832 { 24774 /* vfcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12833 { 24786 /* vfcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12834 { 24799 /* vfdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12835 { 24808 /* vfdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12836 { 24817 /* vfirst.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12837 { 24826 /* vfmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12838 { 24836 /* vfmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12839 { 24846 /* vfmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12840 { 24856 /* vfmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12841 { 24866 /* vfmax.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12842 { 24875 /* vfmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12843 { 24896 /* vfmin.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12844 { 24905 /* vfmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12845 { 24925 /* vfmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12846 { 24935 /* vfmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12847 { 24945 /* vfmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12848 { 24955 /* vfmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12849 { 24965 /* vfmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12850 { 24974 /* vfmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12851 { 25010 /* vfncvt.f.f.q */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
12852 { 25023 /* vfncvt.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12853 { 25036 /* vfncvt.f.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12854 { 25049 /* vfncvt.f.xu.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12855 { 25063 /* vfncvt.rod.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12856 { 25080 /* vfncvt.rtz.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12857 { 25097 /* vfncvt.rtz.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12858 { 25115 /* vfncvt.sat.f.f.q */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
12859 { 25132 /* vfncvt.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12860 { 25145 /* vfncvt.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12861 { 25159 /* vfncvtbf16.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfminOrZvfofp8min },
12862 { 25176 /* vfncvtbf16.sat.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
12863 { 25197 /* vfneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12864 { 25205 /* vfnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12865 { 25216 /* vfnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12866 { 25227 /* vfnmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12867 { 25238 /* vfnmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12868 { 25249 /* vfnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12869 { 25260 /* vfnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12870 { 25271 /* vfnmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12871 { 25282 /* vfnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12872 { 25293 /* vfqimmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12873 { 25306 /* vfqmmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12874 { 25318 /* vfqwbdota.alt.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwbdota8f },
12875 { 25335 /* vfqwbdota.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwbdota8f },
12876 { 25348 /* vfqwdota.alt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwdota8f },
12877 { 25364 /* vfqwdota.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwdota8f },
12878 { 25376 /* vfrdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12879 { 25386 /* vfrec7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12880 { 25395 /* vfredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12881 { 25407 /* vfredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12882 { 25419 /* vfredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12883 { 25432 /* vfredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12884 { 25445 /* vfrsqrt7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12885 { 25456 /* vfrsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12886 { 25466 /* vfsgnj.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12887 { 25476 /* vfsgnj.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12888 { 25486 /* vfsgnjn.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12889 { 25497 /* vfsgnjn.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12890 { 25508 /* vfsgnjx.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12891 { 25519 /* vfsgnjx.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12892 { 25530 /* vfslide1down.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12893 { 25546 /* vfslide1up.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12894 { 25560 /* vfsqrt.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12895 { 25569 /* vfsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12896 { 25578 /* vfsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12897 { 25587 /* vfwadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12898 { 25597 /* vfwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12899 { 25607 /* vfwadd.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12900 { 25617 /* vfwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12901 { 25627 /* vfwbdota.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfwbdota16bf },
12902 { 25639 /* vfwcvt.f.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12903 { 25652 /* vfwcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12904 { 25665 /* vfwcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12905 { 25679 /* vfwcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12906 { 25696 /* vfwcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12907 { 25714 /* vfwcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12908 { 25727 /* vfwcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12909 { 25741 /* vfwcvtbf16.f.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfminOrZvfofp8min },
12910 { 25758 /* vfwdota.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfwdota16bf },
12911 { 25769 /* vfwimmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12912 { 25782 /* vfwmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12913 { 25793 /* vfwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12914 { 25804 /* vfwmaccbf16.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
12915 { 25819 /* vfwmaccbf16.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
12916 { 25834 /* vfwmmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12917 { 25846 /* vfwmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12918 { 25857 /* vfwmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12919 { 25868 /* vfwmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12920 { 25878 /* vfwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12921 { 25888 /* vfwnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12922 { 25900 /* vfwnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12923 { 25912 /* vfwnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12924 { 25924 /* vfwnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12925 { 25936 /* vfwredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12926 { 25950 /* vfwredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12927 { 25964 /* vfwsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12928 { 25974 /* vfwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12929 { 25984 /* vfwsub.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12930 { 25994 /* vfwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12931 { 26040 /* vid.v */, 2 /* 1 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12932 { 26046 /* viota.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12933 { 26054 /* vl1r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12934 { 26061 /* vl1re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12935 { 26071 /* vl1re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12936 { 26081 /* vl1re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12937 { 26091 /* vl1re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12938 { 26100 /* vl2r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12939 { 26107 /* vl2re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12940 { 26117 /* vl2re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12941 { 26127 /* vl2re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12942 { 26137 /* vl2re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12943 { 26146 /* vl4r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12944 { 26153 /* vl4re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12945 { 26163 /* vl4re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12946 { 26173 /* vl4re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12947 { 26183 /* vl4re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12948 { 26192 /* vl8r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12949 { 26199 /* vl8re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12950 { 26209 /* vl8re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12951 { 26219 /* vl8re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12952 { 26229 /* vl8re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12953 { 26238 /* vle16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12954 { 26238 /* vle16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12955 { 26246 /* vle16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12956 { 26246 /* vle16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12957 { 26256 /* vle32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12958 { 26256 /* vle32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12959 { 26264 /* vle32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12960 { 26264 /* vle32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12961 { 26274 /* vle64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12962 { 26274 /* vle64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12963 { 26282 /* vle64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12964 { 26282 /* vle64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12965 { 26292 /* vle8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12966 { 26292 /* vle8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12967 { 26299 /* vle8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12968 { 26299 /* vle8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12969 { 26308 /* vlm.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12970 { 26314 /* vloxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12971 { 26314 /* vloxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12972 { 26325 /* vloxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12973 { 26325 /* vloxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12974 { 26336 /* vloxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12975 { 26336 /* vloxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12976 { 26347 /* vloxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12977 { 26347 /* vloxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12978 { 26357 /* vloxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12979 { 26357 /* vloxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12980 { 26372 /* vloxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12981 { 26372 /* vloxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12982 { 26387 /* vloxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12983 { 26387 /* vloxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12984 { 26402 /* vloxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12985 { 26402 /* vloxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12986 { 26416 /* vloxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12987 { 26416 /* vloxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12988 { 26431 /* vloxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12989 { 26431 /* vloxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12990 { 26446 /* vloxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12991 { 26446 /* vloxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12992 { 26461 /* vloxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12993 { 26461 /* vloxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12994 { 26475 /* vloxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12995 { 26475 /* vloxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12996 { 26490 /* vloxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12997 { 26490 /* vloxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12998 { 26505 /* vloxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12999 { 26505 /* vloxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13000 { 26520 /* vloxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13001 { 26520 /* vloxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13002 { 26534 /* vloxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13003 { 26534 /* vloxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13004 { 26549 /* vloxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13005 { 26549 /* vloxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13006 { 26564 /* vloxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13007 { 26564 /* vloxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13008 { 26579 /* vloxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13009 { 26579 /* vloxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13010 { 26593 /* vloxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13011 { 26593 /* vloxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13012 { 26608 /* vloxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13013 { 26608 /* vloxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13014 { 26623 /* vloxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13015 { 26623 /* vloxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13016 { 26638 /* vloxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13017 { 26638 /* vloxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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13019 { 26652 /* vloxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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13021 { 26667 /* vloxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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13023 { 26682 /* vloxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13024 { 26697 /* vloxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13025 { 26697 /* vloxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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13031 { 26741 /* vloxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
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13033 { 26756 /* vloxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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13035 { 26770 /* vlse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13036 { 26779 /* vlse32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
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13038 { 26788 /* vlse64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13039 { 26788 /* vlse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13040 { 26797 /* vlse8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13041 { 26797 /* vlse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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13205 { 27838 /* vlsseg8e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13206 { 27851 /* vlsseg8e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13207 { 27851 /* vlsseg8e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13208 { 27864 /* vlsseg8e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13209 { 27864 /* vlsseg8e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13210 { 27876 /* vluxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13211 { 27876 /* vluxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13212 { 27887 /* vluxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13213 { 27887 /* vluxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13214 { 27898 /* vluxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13215 { 27898 /* vluxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13216 { 27909 /* vluxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13217 { 27909 /* vluxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13218 { 27919 /* vluxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13219 { 27919 /* vluxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13220 { 27934 /* vluxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13221 { 27934 /* vluxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13222 { 27949 /* vluxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13223 { 27949 /* vluxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13224 { 27964 /* vluxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13225 { 27964 /* vluxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13226 { 27978 /* vluxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13227 { 27978 /* vluxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13228 { 27993 /* vluxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13229 { 27993 /* vluxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13230 { 28008 /* vluxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13231 { 28008 /* vluxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13232 { 28023 /* vluxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13233 { 28023 /* vluxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13234 { 28037 /* vluxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13235 { 28037 /* vluxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13236 { 28052 /* vluxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13237 { 28052 /* vluxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13238 { 28067 /* vluxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13239 { 28067 /* vluxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13240 { 28082 /* vluxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13241 { 28082 /* vluxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13242 { 28096 /* vluxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13243 { 28096 /* vluxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13244 { 28111 /* vluxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13245 { 28111 /* vluxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13246 { 28126 /* vluxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13247 { 28126 /* vluxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13248 { 28141 /* vluxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13249 { 28141 /* vluxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13250 { 28155 /* vluxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13251 { 28155 /* vluxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13252 { 28170 /* vluxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13253 { 28170 /* vluxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13254 { 28185 /* vluxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13255 { 28185 /* vluxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13256 { 28200 /* vluxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13257 { 28200 /* vluxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13258 { 28214 /* vluxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13259 { 28214 /* vluxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13260 { 28229 /* vluxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13261 { 28229 /* vluxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13262 { 28244 /* vluxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13263 { 28244 /* vluxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13264 { 28259 /* vluxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13265 { 28259 /* vluxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13266 { 28273 /* vluxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13267 { 28273 /* vluxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13268 { 28288 /* vluxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13269 { 28288 /* vluxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13270 { 28303 /* vluxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13271 { 28303 /* vluxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13272 { 28318 /* vluxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13273 { 28318 /* vluxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13274 { 28332 /* vmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13275 { 28341 /* vmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13276 { 28407 /* vmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13277 { 28416 /* vmadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13278 { 28444 /* vmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13279 { 28452 /* vmax.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13280 { 28460 /* vmaxu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13281 { 28469 /* vmaxu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13282 { 28519 /* vmfeq.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13283 { 28528 /* vmfeq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13284 { 28537 /* vmfge.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13285 { 28546 /* vmfge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13286 { 28555 /* vmfgt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13287 { 28564 /* vmfgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13288 { 28573 /* vmfle.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13289 { 28582 /* vmfle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13290 { 28591 /* vmflt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13291 { 28600 /* vmflt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13292 { 28609 /* vmfne.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13293 { 28618 /* vmfne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
13294 { 28627 /* vmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13295 { 28635 /* vmin.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13296 { 28643 /* vminu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13297 { 28652 /* vminu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13298 { 28760 /* vmsbf.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13299 { 28768 /* vmseq.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13300 { 28777 /* vmseq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13301 { 28786 /* vmseq.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13302 { 28803 /* vmsge.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13303 { 28812 /* vmsge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13304 { 28821 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13305 { 28821 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13306 { 28830 /* vmsgeu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13307 { 28840 /* vmsgeu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13308 { 28850 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13309 { 28850 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13310 { 28860 /* vmsgt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13311 { 28869 /* vmsgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13312 { 28878 /* vmsgt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13313 { 28887 /* vmsgtu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13314 { 28897 /* vmsgtu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13315 { 28907 /* vmsgtu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13316 { 28917 /* vmsif.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13317 { 28925 /* vmsle.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13318 { 28934 /* vmsle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13319 { 28943 /* vmsle.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13320 { 28952 /* vmsleu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13321 { 28962 /* vmsleu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13322 { 28972 /* vmsleu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13323 { 28982 /* vmslt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13324 { 28991 /* vmslt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13325 { 29000 /* vmslt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13326 { 29009 /* vmsltu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13327 { 29019 /* vmsltu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13328 { 29029 /* vmsltu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13329 { 29039 /* vmsne.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13330 { 29048 /* vmsne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13331 { 29057 /* vmsne.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13332 { 29066 /* vmsof.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13333 { 29074 /* vmtl.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
13334 { 29074 /* vmtl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
13335 { 29074 /* vmtl.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmtls },
13336 { 29074 /* vmtl.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
13337 { 29074 /* vmtl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
13338 { 29081 /* vmts.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
13339 { 29081 /* vmts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
13340 { 29081 /* vmts.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmtls },
13341 { 29081 /* vmts.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
13342 { 29081 /* vmts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
13343 { 29088 /* vmttl.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
13344 { 29088 /* vmttl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
13345 { 29088 /* vmttl.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmttls },
13346 { 29088 /* vmttl.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
13347 { 29088 /* vmttl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
13348 { 29096 /* vmtts.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
13349 { 29096 /* vmtts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
13350 { 29096 /* vmtts.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmttls },
13351 { 29096 /* vmtts.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
13352 { 29096 /* vmtts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
13353 { 29104 /* vmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13354 { 29112 /* vmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13355 { 29120 /* vmulh.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13356 { 29129 /* vmulh.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13357 { 29138 /* vmulhsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13358 { 29149 /* vmulhsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13359 { 29160 /* vmulhu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13360 { 29170 /* vmulhu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13361 { 29271 /* vnclip.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13362 { 29281 /* vnclip.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13363 { 29291 /* vnclip.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13364 { 29301 /* vnclipu.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13365 { 29312 /* vnclipu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13366 { 29323 /* vnclipu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13367 { 29334 /* vncvt.x.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13368 { 29346 /* vneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13369 { 29353 /* vnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13370 { 29363 /* vnmsac.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13371 { 29373 /* vnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13372 { 29383 /* vnmsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13373 { 29393 /* vnot.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13374 { 29400 /* vnsra.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13375 { 29409 /* vnsra.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13376 { 29418 /* vnsra.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13377 { 29427 /* vnsrl.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13378 { 29436 /* vnsrl.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13379 { 29445 /* vnsrl.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13380 { 29454 /* vor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13381 { 29461 /* vor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13382 { 29468 /* vor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13383 { 29475 /* vpaire.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13384 { 29485 /* vpairo.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13385 { 29506 /* vqwbdotas.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i },
13386 { 29519 /* vqwbdotau.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i },
13387 { 29532 /* vqwdotas.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i },
13388 { 29544 /* vqwdotau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i },
13389 { 29556 /* vredand.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13390 { 29567 /* vredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13391 { 29578 /* vredmaxu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13392 { 29590 /* vredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13393 { 29601 /* vredminu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13394 { 29613 /* vredor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13395 { 29623 /* vredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13396 { 29634 /* vredxor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13397 { 29645 /* vrem.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13398 { 29653 /* vrem.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13399 { 29661 /* vremu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13400 { 29670 /* vremu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13401 { 29679 /* vrev8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13402 { 29687 /* vrgather.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13403 { 29699 /* vrgather.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13404 { 29711 /* vrgather.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13405 { 29723 /* vrgatherei16.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13406 { 29739 /* vrol.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13407 { 29747 /* vrol.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13408 { 29755 /* vror.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13409 { 29763 /* vror.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13410 { 29771 /* vror.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
13411 { 29779 /* vrsub.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13412 { 29788 /* vrsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13413 { 29797 /* vs1r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13414 { 29804 /* vs2r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13415 { 29811 /* vs4r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13416 { 29818 /* vs8r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13417 { 29825 /* vsadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13418 { 29834 /* vsadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13419 { 29843 /* vsadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13420 { 29852 /* vsaddu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13421 { 29862 /* vsaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13422 { 29872 /* vsaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13423 { 29900 /* vse16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13424 { 29900 /* vse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13425 { 29908 /* vse32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13426 { 29908 /* vse32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13427 { 29916 /* vse64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13428 { 29916 /* vse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13429 { 29924 /* vse8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13430 { 29924 /* vse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13431 { 29931 /* vsetivli */, 4 /* 2 */, MCK_VTypeI10, AMFBS_HasVInstructions },
13432 { 29947 /* vsetvli */, 4 /* 2 */, MCK_VTypeI11, AMFBS_HasVInstructions },
13433 { 29955 /* vsext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13434 { 29965 /* vsext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13435 { 29975 /* vsext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13436 { 30018 /* vslide1down.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13437 { 30033 /* vslide1up.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13438 { 30046 /* vslidedown.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13439 { 30060 /* vslidedown.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13440 { 30074 /* vslideup.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13441 { 30086 /* vslideup.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13442 { 30098 /* vsll.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13443 { 30106 /* vsll.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13444 { 30114 /* vsll.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13445 { 30122 /* vsm.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13446 { 30174 /* vsmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13447 { 30183 /* vsmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13448 { 30192 /* vsoxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13449 { 30192 /* vsoxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13450 { 30203 /* vsoxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13451 { 30203 /* vsoxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13452 { 30214 /* vsoxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13453 { 30214 /* vsoxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13454 { 30225 /* vsoxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13455 { 30225 /* vsoxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13456 { 30235 /* vsoxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13457 { 30235 /* vsoxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13458 { 30250 /* vsoxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13459 { 30250 /* vsoxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13460 { 30265 /* vsoxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13461 { 30265 /* vsoxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13462 { 30280 /* vsoxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13463 { 30280 /* vsoxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13464 { 30294 /* vsoxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13465 { 30294 /* vsoxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13466 { 30309 /* vsoxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13467 { 30309 /* vsoxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13468 { 30324 /* vsoxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13469 { 30324 /* vsoxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13470 { 30339 /* vsoxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13471 { 30339 /* vsoxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13472 { 30353 /* vsoxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13473 { 30353 /* vsoxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13474 { 30368 /* vsoxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13475 { 30368 /* vsoxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13476 { 30383 /* vsoxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13477 { 30383 /* vsoxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13478 { 30398 /* vsoxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13479 { 30398 /* vsoxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13480 { 30412 /* vsoxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13481 { 30412 /* vsoxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13482 { 30427 /* vsoxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13483 { 30427 /* vsoxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13484 { 30442 /* vsoxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13485 { 30442 /* vsoxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13486 { 30457 /* vsoxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13487 { 30457 /* vsoxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13488 { 30471 /* vsoxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13489 { 30471 /* vsoxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13490 { 30486 /* vsoxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13491 { 30486 /* vsoxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13492 { 30501 /* vsoxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13493 { 30501 /* vsoxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13494 { 30516 /* vsoxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13495 { 30516 /* vsoxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13496 { 30530 /* vsoxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13497 { 30530 /* vsoxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13498 { 30545 /* vsoxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13499 { 30545 /* vsoxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13500 { 30560 /* vsoxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13501 { 30560 /* vsoxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13502 { 30575 /* vsoxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13503 { 30575 /* vsoxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13504 { 30589 /* vsoxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13505 { 30589 /* vsoxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13506 { 30604 /* vsoxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13507 { 30604 /* vsoxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13508 { 30619 /* vsoxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13509 { 30619 /* vsoxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13510 { 30634 /* vsoxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13511 { 30634 /* vsoxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13512 { 30648 /* vsra.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13513 { 30656 /* vsra.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13514 { 30664 /* vsra.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13515 { 30672 /* vsrl.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13516 { 30680 /* vsrl.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13517 { 30688 /* vsrl.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13518 { 30696 /* vsse16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13519 { 30696 /* vsse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13520 { 30705 /* vsse32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13521 { 30705 /* vsse32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13522 { 30714 /* vsse64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13523 { 30714 /* vsse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13524 { 30723 /* vsse8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13525 { 30723 /* vsse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13526 { 30731 /* vsseg2e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13527 { 30731 /* vsseg2e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13528 { 30743 /* vsseg2e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13529 { 30743 /* vsseg2e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13530 { 30755 /* vsseg2e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13531 { 30755 /* vsseg2e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13532 { 30767 /* vsseg2e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13533 { 30767 /* vsseg2e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13534 { 30778 /* vsseg3e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13535 { 30778 /* vsseg3e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13536 { 30790 /* vsseg3e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13537 { 30790 /* vsseg3e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13538 { 30802 /* vsseg3e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13539 { 30802 /* vsseg3e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13540 { 30814 /* vsseg3e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13541 { 30814 /* vsseg3e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13542 { 30825 /* vsseg4e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13543 { 30825 /* vsseg4e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13544 { 30837 /* vsseg4e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13545 { 30837 /* vsseg4e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13546 { 30849 /* vsseg4e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13547 { 30849 /* vsseg4e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13548 { 30861 /* vsseg4e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13549 { 30861 /* vsseg4e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13550 { 30872 /* vsseg5e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13551 { 30872 /* vsseg5e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13552 { 30884 /* vsseg5e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13553 { 30884 /* vsseg5e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13554 { 30896 /* vsseg5e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13555 { 30896 /* vsseg5e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13556 { 30908 /* vsseg5e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13557 { 30908 /* vsseg5e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13558 { 30919 /* vsseg6e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13559 { 30919 /* vsseg6e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13560 { 30931 /* vsseg6e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13561 { 30931 /* vsseg6e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13562 { 30943 /* vsseg6e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13563 { 30943 /* vsseg6e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13564 { 30955 /* vsseg6e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13565 { 30955 /* vsseg6e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13566 { 30966 /* vsseg7e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13567 { 30966 /* vsseg7e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13568 { 30978 /* vsseg7e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13569 { 30978 /* vsseg7e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13570 { 30990 /* vsseg7e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13571 { 30990 /* vsseg7e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13572 { 31002 /* vsseg7e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13573 { 31002 /* vsseg7e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13574 { 31013 /* vsseg8e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13575 { 31013 /* vsseg8e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13576 { 31025 /* vsseg8e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13577 { 31025 /* vsseg8e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13578 { 31037 /* vsseg8e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13579 { 31037 /* vsseg8e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13580 { 31049 /* vsseg8e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13581 { 31049 /* vsseg8e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13582 { 31060 /* vssra.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13583 { 31069 /* vssra.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13584 { 31078 /* vssra.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13585 { 31087 /* vssrl.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13586 { 31096 /* vssrl.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13587 { 31105 /* vssrl.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13588 { 31114 /* vssseg2e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13589 { 31114 /* vssseg2e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13590 { 31127 /* vssseg2e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13591 { 31127 /* vssseg2e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13592 { 31140 /* vssseg2e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13593 { 31140 /* vssseg2e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13594 { 31153 /* vssseg2e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13595 { 31153 /* vssseg2e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13596 { 31165 /* vssseg3e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13597 { 31165 /* vssseg3e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13598 { 31178 /* vssseg3e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13599 { 31178 /* vssseg3e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13600 { 31191 /* vssseg3e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13601 { 31191 /* vssseg3e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13602 { 31204 /* vssseg3e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13603 { 31204 /* vssseg3e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13604 { 31216 /* vssseg4e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13605 { 31216 /* vssseg4e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13606 { 31229 /* vssseg4e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13607 { 31229 /* vssseg4e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13608 { 31242 /* vssseg4e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13609 { 31242 /* vssseg4e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13610 { 31255 /* vssseg4e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13611 { 31255 /* vssseg4e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13612 { 31267 /* vssseg5e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13613 { 31267 /* vssseg5e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13614 { 31280 /* vssseg5e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13615 { 31280 /* vssseg5e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13616 { 31293 /* vssseg5e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13617 { 31293 /* vssseg5e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13618 { 31306 /* vssseg5e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13619 { 31306 /* vssseg5e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13620 { 31318 /* vssseg6e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13621 { 31318 /* vssseg6e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13622 { 31331 /* vssseg6e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13623 { 31331 /* vssseg6e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13624 { 31344 /* vssseg6e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13625 { 31344 /* vssseg6e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13626 { 31357 /* vssseg6e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13627 { 31357 /* vssseg6e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13628 { 31369 /* vssseg7e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13629 { 31369 /* vssseg7e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13630 { 31382 /* vssseg7e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13631 { 31382 /* vssseg7e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13632 { 31395 /* vssseg7e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13633 { 31395 /* vssseg7e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13634 { 31408 /* vssseg7e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13635 { 31408 /* vssseg7e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13636 { 31420 /* vssseg8e16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13637 { 31420 /* vssseg8e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13638 { 31433 /* vssseg8e32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13639 { 31433 /* vssseg8e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13640 { 31446 /* vssseg8e64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
13641 { 31446 /* vssseg8e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
13642 { 31459 /* vssseg8e8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13643 { 31459 /* vssseg8e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13644 { 31471 /* vssub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13645 { 31480 /* vssub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13646 { 31489 /* vssubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13647 { 31499 /* vssubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13648 { 31509 /* vsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13649 { 31517 /* vsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13650 { 31525 /* vsuxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13651 { 31525 /* vsuxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13652 { 31536 /* vsuxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13653 { 31536 /* vsuxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13654 { 31547 /* vsuxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13655 { 31547 /* vsuxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
13656 { 31558 /* vsuxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13657 { 31558 /* vsuxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13658 { 31568 /* vsuxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13659 { 31568 /* vsuxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13660 { 31583 /* vsuxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13661 { 31583 /* vsuxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13662 { 31598 /* vsuxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13663 { 31598 /* vsuxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13664 { 31613 /* vsuxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13665 { 31613 /* vsuxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13666 { 31627 /* vsuxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13667 { 31627 /* vsuxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13668 { 31642 /* vsuxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13669 { 31642 /* vsuxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13670 { 31657 /* vsuxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13671 { 31657 /* vsuxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13672 { 31672 /* vsuxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13673 { 31672 /* vsuxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13674 { 31686 /* vsuxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13675 { 31686 /* vsuxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13676 { 31701 /* vsuxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13677 { 31701 /* vsuxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13678 { 31716 /* vsuxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13679 { 31716 /* vsuxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13680 { 31731 /* vsuxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13681 { 31731 /* vsuxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13682 { 31745 /* vsuxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13683 { 31745 /* vsuxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13684 { 31760 /* vsuxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13685 { 31760 /* vsuxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13686 { 31775 /* vsuxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13687 { 31775 /* vsuxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13688 { 31790 /* vsuxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13689 { 31790 /* vsuxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13690 { 31804 /* vsuxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13691 { 31804 /* vsuxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13692 { 31819 /* vsuxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13693 { 31819 /* vsuxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13694 { 31834 /* vsuxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13695 { 31834 /* vsuxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13696 { 31849 /* vsuxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13697 { 31849 /* vsuxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13698 { 31863 /* vsuxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13699 { 31863 /* vsuxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13700 { 31878 /* vsuxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13701 { 31878 /* vsuxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13702 { 31893 /* vsuxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13703 { 31893 /* vsuxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13704 { 31908 /* vsuxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13705 { 31908 /* vsuxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13706 { 31922 /* vsuxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13707 { 31922 /* vsuxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13708 { 31937 /* vsuxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13709 { 31937 /* vsuxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13710 { 31952 /* vsuxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13711 { 31952 /* vsuxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13712 { 31967 /* vsuxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13713 { 31967 /* vsuxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13714 { 31981 /* vunzipe.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13715 { 31991 /* vunzipo.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13716 { 32001 /* vwabda.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
13717 { 32011 /* vwabda.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
13718 { 32021 /* vwabdau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
13719 { 32032 /* vwabdau.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
13720 { 32043 /* vwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13721 { 32052 /* vwadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13722 { 32061 /* vwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13723 { 32070 /* vwadd.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13724 { 32079 /* vwaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13725 { 32089 /* vwaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13726 { 32099 /* vwaddu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13727 { 32109 /* vwaddu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13728 { 32119 /* vwcvt.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13729 { 32131 /* vwcvtu.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13730 { 32144 /* vwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13731 { 32154 /* vwmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13732 { 32164 /* vwmaccsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13733 { 32176 /* vwmaccsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13734 { 32188 /* vwmaccu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13735 { 32199 /* vwmaccu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13736 { 32210 /* vwmaccus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13737 { 32233 /* vwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13738 { 32242 /* vwmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13739 { 32251 /* vwmulsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13740 { 32262 /* vwmulsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13741 { 32273 /* vwmulu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13742 { 32283 /* vwmulu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13743 { 32293 /* vwredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13744 { 32305 /* vwredsumu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13745 { 32318 /* vwsll.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
13746 { 32327 /* vwsll.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
13747 { 32336 /* vwsll.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
13748 { 32345 /* vwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13749 { 32354 /* vwsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13750 { 32363 /* vwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13751 { 32372 /* vwsub.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13752 { 32381 /* vwsubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13753 { 32391 /* vwsubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13754 { 32401 /* vwsubu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13755 { 32411 /* vwsubu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13756 { 32421 /* vxor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13757 { 32429 /* vxor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13758 { 32437 /* vxor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13759 { 32445 /* vzext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13760 { 32455 /* vzext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13761 { 32465 /* vzext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13762 { 32475 /* vzip.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13763 { 32483 /* wadd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13764 { 32488 /* wadda */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13765 { 32494 /* waddau */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13766 { 32501 /* waddu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13767 { 32511 /* wmacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13768 { 32517 /* wmaccsu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13769 { 32525 /* wmaccu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13770 { 32532 /* wmul */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13771 { 32537 /* wmulsu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13772 { 32544 /* wmulu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13773 { 32566 /* wsla */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13774 { 32571 /* wslai */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13775 { 32577 /* wsll */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13776 { 32582 /* wslli */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13777 { 32588 /* wsub */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13778 { 32593 /* wsuba */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13779 { 32599 /* wsubau */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13780 { 32606 /* wsubu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13781 { 32612 /* wzip16p */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13782 { 32620 /* wzip8p */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13783};
13784
13785ParseStatus RISCVAsmParser::
13786tryCustomParseOperand(OperandVector &Operands,
13787 unsigned MCK) {
13788
13789 switch(MCK) {
13790 case MCK_BareSymbol:
13791 return parseBareSymbol(Operands);
13792 case MCK_BareSymbolQC_E_LI:
13793 return parseBareSymbol(Operands);
13794 case MCK_CSRSystemRegister:
13795 return parseCSRSystemRegister(Operands);
13796 case MCK_RegReg:
13797 return parseRegReg(Operands);
13798 case MCK_TailCallSymbol:
13799 return parseTailCallSymbol(Operands);
13800 case MCK_CallSymbol:
13801 return parseCallSymbol(Operands);
13802 case MCK_FRMArg:
13803 return parseFRMArg(Operands);
13804 case MCK_FRMArgLegacy:
13805 return parseFRMArg(Operands);
13806 case MCK_FenceArg:
13807 return parseFenceArg(Operands);
13808 case MCK_GPRAsFPR16:
13809 return parseGPRAsFPR(Operands);
13810 case MCK_GPRAsFPR32:
13811 return parseGPRAsFPR(Operands);
13812 case MCK_GPRF64AsFPR:
13813 return parseGPRAsFPR64(Operands);
13814 case MCK_GPRPairAsFPR:
13815 return parseGPRPairAsFPR64(Operands);
13816 case MCK_GPRPairCRV32:
13817 return parseGPRPair<false>(Operands);
13818 case MCK_GPRPairNoX0RV32:
13819 return parseGPRPair<false>(Operands);
13820 case MCK_GPRPairRV32:
13821 return parseGPRPair<false>(Operands);
13822 case MCK_GPRPairRV64:
13823 return parseGPRPair<true>(Operands);
13824 case MCK_InsnCDirectiveOpcode:
13825 return parseInsnCDirectiveOpcode(Operands);
13826 case MCK_InsnDirectiveOpcode:
13827 return parseInsnDirectiveOpcode(Operands);
13828 case MCK_LoadFPImm:
13829 return parseFPImm(Operands);
13830 case MCK_NegStackAdj:
13831 return parseZcmpNegStackAdj(Operands);
13832 case MCK_PseudoJumpSymbol:
13833 return parsePseudoJumpSymbol(Operands);
13834 case MCK_QCAccessSymbol:
13835 return parseOperandWithSpecifier(Operands);
13836 case MCK_RTZArg:
13837 return parseFRMArg(Operands);
13838 case MCK_RegList:
13839 return parseRegList(Operands);
13840 case MCK_RegListS0:
13841 return parseRegListS0(Operands);
13842 case MCK_SMTI8:
13843 return parseSMTVType(Operands);
13844 case MCK_SMTVType:
13845 return parseSMTVType(Operands);
13846 case MCK_BareSImm21Lsb0:
13847 return parseJALOffset(Operands);
13848 case MCK_StackAdj:
13849 return parseZcmpStackAdj(Operands);
13850 case MCK_TLSDESCCallSymbol:
13851 return parseOperandWithSpecifier(Operands);
13852 case MCK_TPRelAddSymbol:
13853 return parseOperandWithSpecifier(Operands);
13854 case MCK_TileLambda:
13855 return parseTileLambda(Operands);
13856 case MCK_RVVMaskRegOpOperand:
13857 return parseMaskReg(Operands);
13858 case MCK_RVVScaleRegOpOperand:
13859 return parseVScaleReg(Operands);
13860 case MCK_XSfmmVType:
13861 return parseXSfmmVType(Operands);
13862 case MCK_ZeroOffsetMemOpOperand:
13863 return parseZeroOffsetMemOp(Operands);
13864 case MCK_VTypeI10:
13865 return parseVTypeI(Operands);
13866 case MCK_VTypeI11:
13867 return parseVTypeI(Operands);
13868 default:
13869 return ParseStatus::NoMatch;
13870 }
13871 return ParseStatus::NoMatch;
13872}
13873
13874ParseStatus RISCVAsmParser::
13875MatchOperandParserImpl(OperandVector &Operands,
13876 StringRef Mnemonic,
13877 bool ParseForAllFeatures) {
13878 // Get the current feature set.
13879 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
13880
13881 // Get the next operand index.
13882 unsigned NextOpNum = Operands.size() - 1;
13883 // Search the table.
13884 auto MnemonicRange =
13885 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
13886 Mnemonic, LessOpcodeOperand());
13887
13888 if (MnemonicRange.first == MnemonicRange.second)
13889 return ParseStatus::NoMatch;
13890
13891 for (const OperandMatchEntry *it = MnemonicRange.first,
13892 *ie = MnemonicRange.second; it != ie; ++it) {
13893 // equal_range guarantees that instruction mnemonic matches.
13894 assert(Mnemonic == it->getMnemonic());
13895
13896 // check if the available features match
13897 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
13898 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
13899 continue;
13900
13901 // check if the operand in question has a custom parser.
13902 if (!(it->OperandMask & (1 << NextOpNum)))
13903 continue;
13904
13905 // call custom parse method to handle the operand
13906 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
13907 if (!Result.isNoMatch())
13908 return Result;
13909 }
13910
13911 // Okay, we had no match.
13912 return ParseStatus::NoMatch;
13913}
13914
13915#endif // GET_MATCHER_IMPLEMENTATION
13916
13917
13918#ifdef GET_MNEMONIC_SPELL_CHECKER
13919#undef GET_MNEMONIC_SPELL_CHECKER
13920
13921static std::string RISCVMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
13922 const unsigned MaxEditDist = 2;
13923 std::vector<StringRef> Candidates;
13924 StringRef Prev = "";
13925
13926 // Find the appropriate table for this asm variant.
13927 const MatchEntry *Start, *End;
13928 switch (VariantID) {
13929 default: llvm_unreachable("invalid variant!");
13930 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
13931 }
13932
13933 for (auto I = Start; I < End; I++) {
13934 // Ignore unsupported instructions.
13935 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
13936 if ((FBS & RequiredFeatures) != RequiredFeatures)
13937 continue;
13938
13939 StringRef T = I->getMnemonic();
13940 // Avoid recomputing the edit distance for the same string.
13941 if (T == Prev)
13942 continue;
13943
13944 Prev = T;
13945 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
13946 if (Dist <= MaxEditDist)
13947 Candidates.push_back(T);
13948 }
13949
13950 if (Candidates.empty())
13951 return "";
13952
13953 std::string Res = ", did you mean: ";
13954 unsigned i = 0;
13955 for (; i < Candidates.size() - 1; i++)
13956 Res += Candidates[i].str() + ", ";
13957 return Res + Candidates[i].str() + "?";
13958}
13959
13960#endif // GET_MNEMONIC_SPELL_CHECKER
13961
13962
13963#ifdef GET_MNEMONIC_CHECKER
13964#undef GET_MNEMONIC_CHECKER
13965
13966static bool RISCVCheckMnemonic(StringRef Mnemonic,
13967 const FeatureBitset &AvailableFeatures,
13968 unsigned VariantID) {
13969 // Process all MnemonicAliases to remap the mnemonic.
13970 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
13971
13972 // Find the appropriate table for this asm variant.
13973 const MatchEntry *Start, *End;
13974 switch (VariantID) {
13975 default: llvm_unreachable("invalid variant!");
13976 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
13977 }
13978
13979 // Search the table.
13980 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
13981
13982 if (MnemonicRange.first == MnemonicRange.second)
13983 return false;
13984
13985 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
13986 it != ie; ++it) {
13987 const FeatureBitset &RequiredFeatures =
13988 FeatureBitsets[it->RequiredFeaturesIdx];
13989 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
13990 return true;
13991 }
13992 return false;
13993}
13994
13995#endif // GET_MNEMONIC_CHECKER
13996
13997