1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: RISCV.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands,
18 const SmallBitVector &OptionalOperandsMask,
19 ArrayRef<unsigned> DefaultsOffset);
20 void convertToMapAndConstraints(unsigned Kind,
21 const OperandVector &Operands) override;
22 unsigned MatchInstructionImpl(const OperandVector &Operands,
23 MCInst &Inst,
24 uint64_t &ErrorInfo,
25 FeatureBitset &MissingFeatures,
26 bool matchingInlineAsm,
27 unsigned VariantID = 0);
28 unsigned MatchInstructionImpl(const OperandVector &Operands,
29 MCInst &Inst,
30 uint64_t &ErrorInfo,
31 bool matchingInlineAsm,
32 unsigned VariantID = 0) {
33 FeatureBitset MissingFeatures;
34 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
35 matchingInlineAsm, VariantID);
36 }
37
38 ParseStatus MatchOperandParserImpl(
39 OperandVector &Operands,
40 StringRef Mnemonic,
41 bool ParseForAllFeatures = false);
42 ParseStatus tryCustomParseOperand(
43 OperandVector &Operands,
44 unsigned MCK);
45
46#endif // GET_ASSEMBLER_HEADER
47
48
49#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
50#undef GET_OPERAND_DIAGNOSTIC_TYPES
51
52 Match_GPRC,
53 Match_InvalidBareSImm11Lsb0,
54 Match_InvalidBareSImm12Lsb0,
55 Match_InvalidBareSImm13Lsb0,
56 Match_InvalidBareSImm21Lsb0,
57 Match_InvalidBareSImm32,
58 Match_InvalidBareSImm32Lsb0,
59 Match_InvalidBareSImm9Lsb0,
60 Match_InvalidBareSymbol,
61 Match_InvalidBareSymbolQC_E_LI,
62 Match_InvalidCLUIImm,
63 Match_InvalidCSRSystemRegister,
64 Match_InvalidCallSymbol,
65 Match_InvalidImm5Zibi,
66 Match_InvalidImmFour,
67 Match_InvalidImmThree,
68 Match_InvalidImmXLenLI,
69 Match_InvalidImmXLenLI_Restricted,
70 Match_InvalidImmZero,
71 Match_InvalidLoadFPImm,
72 Match_InvalidPseudoJumpSymbol,
73 Match_InvalidQCAccessSymbol,
74 Match_InvalidRTZArg,
75 Match_InvalidRegClassGPRNoX0,
76 Match_InvalidRegClassGPRNoX0X2,
77 Match_InvalidRegClassGPRNoX2,
78 Match_InvalidRegClassGPRX1,
79 Match_InvalidRegClassGPRX1X5,
80 Match_InvalidRegClassGPRX31,
81 Match_InvalidRegClassGPRX5,
82 Match_InvalidRegClassSP,
83 Match_InvalidRegList,
84 Match_InvalidRegListS0,
85 Match_InvalidRnumArg,
86 Match_InvalidSImm10,
87 Match_InvalidSImm10Lsb0000NonZero,
88 Match_InvalidSImm10PLI_H,
89 Match_InvalidSImm10PLI_W,
90 Match_InvalidSImm10PLUI,
91 Match_InvalidSImm11,
92 Match_InvalidSImm12,
93 Match_InvalidSImm12LO,
94 Match_InvalidSImm12Lsb00000,
95 Match_InvalidSImm16,
96 Match_InvalidSImm16NonZero,
97 Match_InvalidSImm18,
98 Match_InvalidSImm18Lsb0,
99 Match_InvalidSImm19Lsb00,
100 Match_InvalidSImm20LI,
101 Match_InvalidSImm20Lsb000,
102 Match_InvalidSImm26,
103 Match_InvalidSImm5,
104 Match_InvalidSImm5NonZero,
105 Match_InvalidSImm5Plus1,
106 Match_InvalidSImm6,
107 Match_InvalidSImm6NonZero,
108 Match_InvalidSImm8PLI_B,
109 Match_InvalidStackAdj,
110 Match_InvalidTLSDESCCallSymbol,
111 Match_InvalidTPRelAddSymbol,
112 Match_InvalidTileLambda,
113 Match_InvalidUImm1,
114 Match_InvalidUImm10,
115 Match_InvalidUImm10Lsb00NonZero,
116 Match_InvalidUImm11,
117 Match_InvalidUImm14Lsb00,
118 Match_InvalidUImm16,
119 Match_InvalidUImm16NonZero,
120 Match_InvalidUImm2,
121 Match_InvalidUImm20,
122 Match_InvalidUImm20AUIPC,
123 Match_InvalidUImm20LUI,
124 Match_InvalidUImm2Lsb0,
125 Match_InvalidUImm3,
126 Match_InvalidUImm32,
127 Match_InvalidUImm4,
128 Match_InvalidUImm48,
129 Match_InvalidUImm4Plus1,
130 Match_InvalidUImm5,
131 Match_InvalidUImm5GE6Plus1,
132 Match_InvalidUImm5GT3,
133 Match_InvalidUImm5Lsb0,
134 Match_InvalidUImm5NonZero,
135 Match_InvalidUImm5Plus1,
136 Match_InvalidUImm5Slist,
137 Match_InvalidUImm6,
138 Match_InvalidUImm64,
139 Match_InvalidUImm6Lsb0,
140 Match_InvalidUImm6Plus1,
141 Match_InvalidUImm7,
142 Match_InvalidUImm7EqXLen,
143 Match_InvalidUImm7Lsb00,
144 Match_InvalidUImm7Lsb000,
145 Match_InvalidUImm8,
146 Match_InvalidUImm8GE32,
147 Match_InvalidUImm8Lsb00,
148 Match_InvalidUImm8Lsb000,
149 Match_InvalidUImm9,
150 Match_InvalidUImm9Lsb000,
151 Match_InvalidUImmLog2XLen,
152 Match_InvalidUImmLog2XLenNonZero,
153 Match_InvalidVMaskCarryInRegister,
154 Match_InvalidVMaskRegister,
155 Match_InvalidVScaleRegister,
156 Match_InvalidVTypeI,
157 Match_InvalidYBNDSWImm,
158 END_OPERAND_DIAGNOSTIC_TYPES
159#endif // GET_OPERAND_DIAGNOSTIC_TYPES
160
161
162#ifdef GET_REGISTER_MATCHER
163#undef GET_REGISTER_MATCHER
164
165// Bits for subtarget features that participate in instruction matching.
166enum SubtargetFeatureBits : uint8_t {
167 Feature_HasStdExtZibiBit = 46,
168 Feature_HasStdExtZicbomBit = 47,
169 Feature_HasStdExtZicbopBit = 48,
170 Feature_HasStdExtZicbozBit = 49,
171 Feature_HasStdExtZicsrBit = 52,
172 Feature_HasStdExtZicondBit = 51,
173 Feature_HasStdExtZifenceiBit = 53,
174 Feature_HasStdExtZihintpauseBit = 55,
175 Feature_HasStdExtZihintntlBit = 54,
176 Feature_HasStdExtZimopBit = 57,
177 Feature_HasStdExtZicfissBit = 50,
178 Feature_HasStdExtZilsdBit = 56,
179 Feature_HasStdExtZmmulBit = 65,
180 Feature_HasStdExtMBit = 7,
181 Feature_HasStdExtZaamoBit = 14,
182 Feature_HasStdExtZalrscBit = 18,
183 Feature_HasStdExtABit = 2,
184 Feature_HasStdExtZtsoBit = 66,
185 Feature_HasStdExtZabhaBit = 15,
186 Feature_HasStdExtZacasBit = 16,
187 Feature_HasStdExtZalasrBit = 17,
188 Feature_HasStdExtZawrsBit = 19,
189 Feature_HasStdExtFBit = 4,
190 Feature_HasStdExtDBit = 3,
191 Feature_HasStdExtQBit = 9,
192 Feature_HasStdExtZfhminBit = 42,
193 Feature_HasStdExtZfhBit = 40,
194 Feature_HasStdExtZfbfminBit = 39,
195 Feature_HasHalfFPLoadStoreMoveBit = 1,
196 Feature_HasStdExtZfaBit = 38,
197 Feature_HasStdExtZfinxBit = 43,
198 Feature_HasStdExtFOrZfinxBit = 5,
199 Feature_HasStdExtZdinxBit = 37,
200 Feature_HasStdExtZhinxminBit = 45,
201 Feature_HasStdExtZhinxBit = 44,
202 Feature_HasStdExtZcaBit = 29,
203 Feature_HasStdExtZcbBit = 30,
204 Feature_HasStdExtZcfBit = 32,
205 Feature_HasStdExtZcdBit = 31,
206 Feature_HasStdExtZclsdBit = 33,
207 Feature_HasStdExtZcmpBit = 35,
208 Feature_HasStdExtZcmtBit = 36,
209 Feature_HasStdExtZcmopBit = 34,
210 Feature_HasStdExtZbaBit = 20,
211 Feature_HasStdExtZbbBit = 21,
212 Feature_NoStdExtZbbBit = 169,
213 Feature_HasStdExtZbsBit = 28,
214 Feature_HasStdExtZbkbBit = 24,
215 Feature_NoStdExtZbkbBit = 170,
216 Feature_HasStdExtZbkxBit = 27,
217 Feature_HasStdExtZbbOrZbkbBit = 22,
218 Feature_HasStdExtZbkcBit = 26,
219 Feature_HasStdExtZbcBit = 23,
220 Feature_HasStdExtZkndBit = 58,
221 Feature_HasStdExtZkneBit = 60,
222 Feature_HasStdExtZkndOrZkneBit = 59,
223 Feature_HasStdExtZknhBit = 61,
224 Feature_HasStdExtZksedBit = 63,
225 Feature_HasStdExtZkshBit = 64,
226 Feature_HasStdExtZkrBit = 62,
227 Feature_HasStdExtZvabdBit = 67,
228 Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit = 90,
229 Feature_HasStdExtZvfwdota16bfBit = 80,
230 Feature_HasStdExtZvfqwdota8fBit = 78,
231 Feature_HasStdExtZvfbfminBit = 73,
232 Feature_HasStdExtZvfbfwmaBit = 75,
233 Feature_HasStdExtZfhOrZvfhBit = 41,
234 Feature_HasStdExtZvfofp8minBit = 76,
235 Feature_HasStdExtZvfbfminOrZvfofp8minBit = 74,
236 Feature_HasStdExtZvkbBit = 81,
237 Feature_HasStdExtZvbbBit = 68,
238 Feature_HasStdExtZvbcBit = 69,
239 Feature_HasStdExtZvbcOrZvbc32eBit = 70,
240 Feature_HasStdExtZvkgBit = 82,
241 Feature_HasStdExtZvkgsBit = 83,
242 Feature_HasStdExtZvknedBit = 84,
243 Feature_HasStdExtZvknhaBit = 85,
244 Feature_HasStdExtZvknhbBit = 86,
245 Feature_HasStdExtZvksedBit = 87,
246 Feature_HasStdExtZvkshBit = 88,
247 Feature_HasStdExtZvdot4a8iBit = 71,
248 Feature_HasStdExtZvzipBit = 95,
249 Feature_HasStdExtZvvmmBit = 92,
250 Feature_HasStdExtZvvfmmBit = 91,
251 Feature_HasStdExtZvvmtlsBit = 93,
252 Feature_HasStdExtZvvmttlsBit = 94,
253 Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit = 89,
254 Feature_HasStdExtZvfwbdota16bfBit = 79,
255 Feature_HasStdExtZvfqwbdota8fBit = 77,
256 Feature_HasStdExtZvfbdota32fBit = 72,
257 Feature_HasVInstructionsBit = 96,
258 Feature_HasVInstructionsI64Bit = 99,
259 Feature_HasVInstructionsAnyFBit = 97,
260 Feature_HasVInstructionsF16MinimalBit = 98,
261 Feature_HasStdExtHBit = 6,
262 Feature_HasStdExtSmrnmiBit = 11,
263 Feature_HasStdExtSvinvalBit = 12,
264 Feature_HasStdExtSmctrOrSsctrBit = 10,
265 Feature_HasStdExtPBit = 8,
266 Feature_HasStdExtZbkbOrPBit = 25,
267 Feature_HasStdExtYBit = 13,
268 Feature_HasVendorXVentanaCondOpsBit = 144,
269 Feature_HasVendorXTHeadBaBit = 133,
270 Feature_HasVendorXTHeadBbBit = 134,
271 Feature_HasVendorXTHeadBsBit = 135,
272 Feature_HasVendorXTHeadCondMovBit = 137,
273 Feature_HasVendorXTHeadCmoBit = 136,
274 Feature_HasVendorXTHeadFMemIdxBit = 138,
275 Feature_HasVendorXTHeadMacBit = 139,
276 Feature_HasVendorXTHeadMemIdxBit = 140,
277 Feature_HasVendorXTHeadMemPairBit = 141,
278 Feature_HasVendorXTHeadSyncBit = 142,
279 Feature_HasVendorXTHeadVdotBit = 143,
280 Feature_HasVendorXSfvcpBit = 124,
281 Feature_HasVendorXSfmmbaseBit = 123,
282 Feature_HasVendorXSfmm32a8fBit = 120,
283 Feature_HasVendorXSfmm32a8iBit = 121,
284 Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit = 122,
285 Feature_HasVendorXSfvqmaccdodBit = 129,
286 Feature_HasVendorXSfvqmaccqoqBit = 130,
287 Feature_HasVendorXSfvfwmaccqqqBit = 128,
288 Feature_HasVendorXSfvfnrclipxfqfBit = 127,
289 Feature_HasVendorXSfvfexpAnyBit = 125,
290 Feature_HasVendorXSfvfexpaBit = 126,
291 Feature_HasVendorXSiFivecdiscarddloneBit = 131,
292 Feature_HasVendorXSiFivecflushdloneBit = 132,
293 Feature_HasVendorXSfceaseBit = 119,
294 Feature_HasVendorXCVelwBit = 110,
295 Feature_HasVendorXCVbitmanipBit = 109,
296 Feature_HasVendorXCVmacBit = 111,
297 Feature_HasVendorXCVmemBit = 112,
298 Feature_HasVendorXCValuBit = 107,
299 Feature_HasVendorXCVsimdBit = 113,
300 Feature_HasVendorXCVbiBit = 108,
301 Feature_HasVendorXMIPSCMovBit = 115,
302 Feature_HasVendorXMIPSLSPBit = 117,
303 Feature_HasVendorXMIPSCBOPBit = 114,
304 Feature_HasVendorXMIPSEXECTLBit = 116,
305 Feature_HasVendorXwchcBit = 165,
306 Feature_HasVendorXqccmpBit = 145,
307 Feature_HasVendorXqccmtBit = 146,
308 Feature_HasVendorXqciaBit = 147,
309 Feature_HasVendorXqciacBit = 148,
310 Feature_HasVendorXqcibiBit = 149,
311 Feature_HasVendorXqcibmBit = 150,
312 Feature_HasVendorXqcicliBit = 151,
313 Feature_HasVendorXqcicmBit = 152,
314 Feature_HasVendorXqcicsBit = 153,
315 Feature_HasVendorXqcicsrBit = 154,
316 Feature_HasVendorXqciintBit = 155,
317 Feature_HasVendorXqciioBit = 156,
318 Feature_HasVendorXqcilbBit = 157,
319 Feature_HasVendorXqciliBit = 158,
320 Feature_HasVendorXqciliaBit = 159,
321 Feature_HasVendorXqciloBit = 160,
322 Feature_HasVendorXqcilsmBit = 161,
323 Feature_HasVendorXqcisimBit = 162,
324 Feature_HasVendorXqcislsBit = 163,
325 Feature_HasVendorXqcisyncBit = 164,
326 Feature_HasVendorXAndesPerfBit = 101,
327 Feature_HasVendorXAndesBFHCvtBit = 100,
328 Feature_HasVendorXAndesVBFHCvtBit = 102,
329 Feature_HasVendorXAndesVSIntHBit = 105,
330 Feature_HasVendorXAndesVSIntLoadBit = 106,
331 Feature_HasVendorXAndesVPackFPHBit = 104,
332 Feature_HasVendorXAndesVDotBit = 103,
333 Feature_HasVendorXSMTVDotBit = 118,
334 Feature_HasXAIFETBit = 166,
335 Feature_HasCheriotBit = 0,
336 Feature_IsRV64Bit = 168,
337 Feature_IsRV32Bit = 167,
338};
339
340static MCRegister MatchRegisterName(StringRef Name) {
341 switch (Name.size()) {
342 default: break;
343 case 1: // 1 string to match.
344 if (Name[0] != '0')
345 break;
346 return RISCV::DUMMY_REG_PAIR_WITH_X0; // "0"
347 case 2: // 212 strings to match.
348 switch (Name[0]) {
349 default: break;
350 case 'f': // 50 strings to match.
351 switch (Name[1]) {
352 default: break;
353 case '0': // 5 strings to match.
354 return RISCV::F0_D; // "f0"
355 case '1': // 5 strings to match.
356 return RISCV::F1_D; // "f1"
357 case '2': // 5 strings to match.
358 return RISCV::F2_D; // "f2"
359 case '3': // 5 strings to match.
360 return RISCV::F3_D; // "f3"
361 case '4': // 5 strings to match.
362 return RISCV::F4_D; // "f4"
363 case '5': // 5 strings to match.
364 return RISCV::F5_D; // "f5"
365 case '6': // 5 strings to match.
366 return RISCV::F6_D; // "f6"
367 case '7': // 5 strings to match.
368 return RISCV::F7_D; // "f7"
369 case '8': // 5 strings to match.
370 return RISCV::F8_D; // "f8"
371 case '9': // 5 strings to match.
372 return RISCV::F9_D; // "f9"
373 }
374 break;
375 case 'm': // 8 strings to match.
376 switch (Name[1]) {
377 default: break;
378 case '0': // 1 string to match.
379 return RISCV::M0; // "m0"
380 case '1': // 1 string to match.
381 return RISCV::M1; // "m1"
382 case '2': // 1 string to match.
383 return RISCV::M2; // "m2"
384 case '3': // 1 string to match.
385 return RISCV::M3; // "m3"
386 case '4': // 1 string to match.
387 return RISCV::M4; // "m4"
388 case '5': // 1 string to match.
389 return RISCV::M5; // "m5"
390 case '6': // 1 string to match.
391 return RISCV::M6; // "m6"
392 case '7': // 1 string to match.
393 return RISCV::M7; // "m7"
394 }
395 break;
396 case 'v': // 109 strings to match.
397 switch (Name[1]) {
398 default: break;
399 case '0': // 15 strings to match.
400 return RISCV::V0; // "v0"
401 case '1': // 8 strings to match.
402 return RISCV::V1; // "v1"
403 case '2': // 12 strings to match.
404 return RISCV::V2; // "v2"
405 case '3': // 8 strings to match.
406 return RISCV::V3; // "v3"
407 case '4': // 14 strings to match.
408 return RISCV::V4; // "v4"
409 case '5': // 8 strings to match.
410 return RISCV::V5; // "v5"
411 case '6': // 12 strings to match.
412 return RISCV::V6; // "v6"
413 case '7': // 8 strings to match.
414 return RISCV::V7; // "v7"
415 case '8': // 15 strings to match.
416 return RISCV::V8; // "v8"
417 case '9': // 8 strings to match.
418 return RISCV::V9; // "v9"
419 case 'l': // 1 string to match.
420 return RISCV::VL; // "vl"
421 }
422 break;
423 case 'x': // 45 strings to match.
424 switch (Name[1]) {
425 default: break;
426 case '0': // 5 strings to match.
427 return RISCV::X0; // "x0"
428 case '1': // 4 strings to match.
429 return RISCV::X1; // "x1"
430 case '2': // 5 strings to match.
431 return RISCV::X2; // "x2"
432 case '3': // 4 strings to match.
433 return RISCV::X3; // "x3"
434 case '4': // 5 strings to match.
435 return RISCV::X4; // "x4"
436 case '5': // 4 strings to match.
437 return RISCV::X5; // "x5"
438 case '6': // 5 strings to match.
439 return RISCV::X6; // "x6"
440 case '7': // 4 strings to match.
441 return RISCV::X7; // "x7"
442 case '8': // 5 strings to match.
443 return RISCV::X8; // "x8"
444 case '9': // 4 strings to match.
445 return RISCV::X9; // "x9"
446 }
447 break;
448 }
449 break;
450 case 3: // 418 strings to match.
451 switch (Name[0]) {
452 default: break;
453 case 'f': // 111 strings to match.
454 switch (Name[1]) {
455 default: break;
456 case '1': // 50 strings to match.
457 switch (Name[2]) {
458 default: break;
459 case '0': // 5 strings to match.
460 return RISCV::F10_D; // "f10"
461 case '1': // 5 strings to match.
462 return RISCV::F11_D; // "f11"
463 case '2': // 5 strings to match.
464 return RISCV::F12_D; // "f12"
465 case '3': // 5 strings to match.
466 return RISCV::F13_D; // "f13"
467 case '4': // 5 strings to match.
468 return RISCV::F14_D; // "f14"
469 case '5': // 5 strings to match.
470 return RISCV::F15_D; // "f15"
471 case '6': // 5 strings to match.
472 return RISCV::F16_D; // "f16"
473 case '7': // 5 strings to match.
474 return RISCV::F17_D; // "f17"
475 case '8': // 5 strings to match.
476 return RISCV::F18_D; // "f18"
477 case '9': // 5 strings to match.
478 return RISCV::F19_D; // "f19"
479 }
480 break;
481 case '2': // 50 strings to match.
482 switch (Name[2]) {
483 default: break;
484 case '0': // 5 strings to match.
485 return RISCV::F20_D; // "f20"
486 case '1': // 5 strings to match.
487 return RISCV::F21_D; // "f21"
488 case '2': // 5 strings to match.
489 return RISCV::F22_D; // "f22"
490 case '3': // 5 strings to match.
491 return RISCV::F23_D; // "f23"
492 case '4': // 5 strings to match.
493 return RISCV::F24_D; // "f24"
494 case '5': // 5 strings to match.
495 return RISCV::F25_D; // "f25"
496 case '6': // 5 strings to match.
497 return RISCV::F26_D; // "f26"
498 case '7': // 5 strings to match.
499 return RISCV::F27_D; // "f27"
500 case '8': // 5 strings to match.
501 return RISCV::F28_D; // "f28"
502 case '9': // 5 strings to match.
503 return RISCV::F29_D; // "f29"
504 }
505 break;
506 case '3': // 10 strings to match.
507 switch (Name[2]) {
508 default: break;
509 case '0': // 5 strings to match.
510 return RISCV::F30_D; // "f30"
511 case '1': // 5 strings to match.
512 return RISCV::F31_D; // "f31"
513 }
514 break;
515 case 'r': // 1 string to match.
516 if (Name[2] != 'm')
517 break;
518 return RISCV::FRM; // "frm"
519 }
520 break;
521 case 'm': // 10 strings to match.
522 if (Name[1] != 't')
523 break;
524 switch (Name[2]) {
525 default: break;
526 case '0': // 1 string to match.
527 return RISCV::T0; // "mt0"
528 case '1': // 1 string to match.
529 return RISCV::T1; // "mt1"
530 case '2': // 1 string to match.
531 return RISCV::T2; // "mt2"
532 case '3': // 1 string to match.
533 return RISCV::T3; // "mt3"
534 case '4': // 1 string to match.
535 return RISCV::T4; // "mt4"
536 case '5': // 1 string to match.
537 return RISCV::T5; // "mt5"
538 case '6': // 1 string to match.
539 return RISCV::T6; // "mt6"
540 case '7': // 1 string to match.
541 return RISCV::T7; // "mt7"
542 case '8': // 1 string to match.
543 return RISCV::T8; // "mt8"
544 case '9': // 1 string to match.
545 return RISCV::T9; // "mt9"
546 }
547 break;
548 case 's': // 1 string to match.
549 if (memcmp(Name.data()+1, "sp", 2) != 0)
550 break;
551 return RISCV::SSP; // "ssp"
552 case 'v': // 197 strings to match.
553 switch (Name[1]) {
554 default: break;
555 case '1': // 105 strings to match.
556 switch (Name[2]) {
557 default: break;
558 case '0': // 12 strings to match.
559 return RISCV::V10; // "v10"
560 case '1': // 8 strings to match.
561 return RISCV::V11; // "v11"
562 case '2': // 14 strings to match.
563 return RISCV::V12; // "v12"
564 case '3': // 8 strings to match.
565 return RISCV::V13; // "v13"
566 case '4': // 12 strings to match.
567 return RISCV::V14; // "v14"
568 case '5': // 8 strings to match.
569 return RISCV::V15; // "v15"
570 case '6': // 15 strings to match.
571 return RISCV::V16; // "v16"
572 case '7': // 8 strings to match.
573 return RISCV::V17; // "v17"
574 case '8': // 12 strings to match.
575 return RISCV::V18; // "v18"
576 case '9': // 8 strings to match.
577 return RISCV::V19; // "v19"
578 }
579 break;
580 case '2': // 88 strings to match.
581 switch (Name[2]) {
582 default: break;
583 case '0': // 14 strings to match.
584 return RISCV::V20; // "v20"
585 case '1': // 8 strings to match.
586 return RISCV::V21; // "v21"
587 case '2': // 12 strings to match.
588 return RISCV::V22; // "v22"
589 case '3': // 8 strings to match.
590 return RISCV::V23; // "v23"
591 case '4': // 15 strings to match.
592 return RISCV::V24; // "v24"
593 case '5': // 7 strings to match.
594 return RISCV::V25; // "v25"
595 case '6': // 9 strings to match.
596 return RISCV::V26; // "v26"
597 case '7': // 5 strings to match.
598 return RISCV::V27; // "v27"
599 case '8': // 7 strings to match.
600 return RISCV::V28; // "v28"
601 case '9': // 3 strings to match.
602 return RISCV::V29; // "v29"
603 }
604 break;
605 case '3': // 4 strings to match.
606 switch (Name[2]) {
607 default: break;
608 case '0': // 3 strings to match.
609 return RISCV::V30; // "v30"
610 case '1': // 1 string to match.
611 return RISCV::V31; // "v31"
612 }
613 break;
614 }
615 break;
616 case 'x': // 99 strings to match.
617 switch (Name[1]) {
618 default: break;
619 case '1': // 45 strings to match.
620 switch (Name[2]) {
621 default: break;
622 case '0': // 5 strings to match.
623 return RISCV::X10; // "x10"
624 case '1': // 4 strings to match.
625 return RISCV::X11; // "x11"
626 case '2': // 5 strings to match.
627 return RISCV::X12; // "x12"
628 case '3': // 4 strings to match.
629 return RISCV::X13; // "x13"
630 case '4': // 5 strings to match.
631 return RISCV::X14; // "x14"
632 case '5': // 4 strings to match.
633 return RISCV::X15; // "x15"
634 case '6': // 5 strings to match.
635 return RISCV::X16; // "x16"
636 case '7': // 4 strings to match.
637 return RISCV::X17; // "x17"
638 case '8': // 5 strings to match.
639 return RISCV::X18; // "x18"
640 case '9': // 4 strings to match.
641 return RISCV::X19; // "x19"
642 }
643 break;
644 case '2': // 45 strings to match.
645 switch (Name[2]) {
646 default: break;
647 case '0': // 5 strings to match.
648 return RISCV::X20; // "x20"
649 case '1': // 4 strings to match.
650 return RISCV::X21; // "x21"
651 case '2': // 5 strings to match.
652 return RISCV::X22; // "x22"
653 case '3': // 4 strings to match.
654 return RISCV::X23; // "x23"
655 case '4': // 5 strings to match.
656 return RISCV::X24; // "x24"
657 case '5': // 4 strings to match.
658 return RISCV::X25; // "x25"
659 case '6': // 5 strings to match.
660 return RISCV::X26; // "x26"
661 case '7': // 4 strings to match.
662 return RISCV::X27; // "x27"
663 case '8': // 5 strings to match.
664 return RISCV::X28; // "x28"
665 case '9': // 4 strings to match.
666 return RISCV::X29; // "x29"
667 }
668 break;
669 case '3': // 9 strings to match.
670 switch (Name[2]) {
671 default: break;
672 case '0': // 5 strings to match.
673 return RISCV::X30; // "x30"
674 case '1': // 4 strings to match.
675 return RISCV::X31; // "x31"
676 }
677 break;
678 }
679 break;
680 }
681 break;
682 case 4: // 8 strings to match.
683 switch (Name[0]) {
684 default: break;
685 case 'f': // 1 string to match.
686 if (memcmp(Name.data()+1, "csr", 3) != 0)
687 break;
688 return RISCV::FCSR; // "fcsr"
689 case 'm': // 6 strings to match.
690 if (memcmp(Name.data()+1, "t1", 2) != 0)
691 break;
692 switch (Name[3]) {
693 default: break;
694 case '0': // 1 string to match.
695 return RISCV::T10; // "mt10"
696 case '1': // 1 string to match.
697 return RISCV::T11; // "mt11"
698 case '2': // 1 string to match.
699 return RISCV::T12; // "mt12"
700 case '3': // 1 string to match.
701 return RISCV::T13; // "mt13"
702 case '4': // 1 string to match.
703 return RISCV::T14; // "mt14"
704 case '5': // 1 string to match.
705 return RISCV::T15; // "mt15"
706 }
707 break;
708 case 'v': // 1 string to match.
709 if (memcmp(Name.data()+1, "xrm", 3) != 0)
710 break;
711 return RISCV::VXRM; // "vxrm"
712 }
713 break;
714 case 5: // 3 strings to match.
715 if (Name[0] != 'v')
716 break;
717 switch (Name[1]) {
718 default: break;
719 case 'l': // 1 string to match.
720 if (memcmp(Name.data()+2, "enb", 3) != 0)
721 break;
722 return RISCV::VLENB; // "vlenb"
723 case 't': // 1 string to match.
724 if (memcmp(Name.data()+2, "ype", 3) != 0)
725 break;
726 return RISCV::VTYPE; // "vtype"
727 case 'x': // 1 string to match.
728 if (memcmp(Name.data()+2, "sat", 3) != 0)
729 break;
730 return RISCV::VXSAT; // "vxsat"
731 }
732 break;
733 case 6: // 1 string to match.
734 if (memcmp(Name.data()+0, "fflags", 6) != 0)
735 break;
736 return RISCV::FFLAGS; // "fflags"
737 case 13: // 1 string to match.
738 if (memcmp(Name.data()+0, "sf.vcix_state", 13) != 0)
739 break;
740 return RISCV::SF_VCIX_STATE; // "sf.vcix_state"
741 }
742 return RISCV::NoRegister;
743}
744
745static MCRegister MatchRegisterAltName(StringRef Name) {
746 switch (Name.size()) {
747 default: break;
748 case 2: // 143 strings to match.
749 switch (Name[0]) {
750 default: break;
751 case 'a': // 36 strings to match.
752 switch (Name[1]) {
753 default: break;
754 case '0': // 5 strings to match.
755 return RISCV::X10; // "a0"
756 case '1': // 4 strings to match.
757 return RISCV::X11; // "a1"
758 case '2': // 5 strings to match.
759 return RISCV::X12; // "a2"
760 case '3': // 4 strings to match.
761 return RISCV::X13; // "a3"
762 case '4': // 5 strings to match.
763 return RISCV::X14; // "a4"
764 case '5': // 4 strings to match.
765 return RISCV::X15; // "a5"
766 case '6': // 5 strings to match.
767 return RISCV::X16; // "a6"
768 case '7': // 4 strings to match.
769 return RISCV::X17; // "a7"
770 }
771 break;
772 case 'f': // 5 strings to match.
773 if (Name[1] != 'p')
774 break;
775 return RISCV::X8; // "fp"
776 case 'g': // 4 strings to match.
777 if (Name[1] != 'p')
778 break;
779 return RISCV::X3; // "gp"
780 case 'm': // 8 strings to match.
781 switch (Name[1]) {
782 default: break;
783 case '0': // 1 string to match.
784 return RISCV::M0; // "m0"
785 case '1': // 1 string to match.
786 return RISCV::M1; // "m1"
787 case '2': // 1 string to match.
788 return RISCV::M2; // "m2"
789 case '3': // 1 string to match.
790 return RISCV::M3; // "m3"
791 case '4': // 1 string to match.
792 return RISCV::M4; // "m4"
793 case '5': // 1 string to match.
794 return RISCV::M5; // "m5"
795 case '6': // 1 string to match.
796 return RISCV::M6; // "m6"
797 case '7': // 1 string to match.
798 return RISCV::M7; // "m7"
799 }
800 break;
801 case 'r': // 4 strings to match.
802 if (Name[1] != 'a')
803 break;
804 return RISCV::X1; // "ra"
805 case 's': // 50 strings to match.
806 switch (Name[1]) {
807 default: break;
808 case '0': // 5 strings to match.
809 return RISCV::X8; // "s0"
810 case '1': // 4 strings to match.
811 return RISCV::X9; // "s1"
812 case '2': // 5 strings to match.
813 return RISCV::X18; // "s2"
814 case '3': // 4 strings to match.
815 return RISCV::X19; // "s3"
816 case '4': // 5 strings to match.
817 return RISCV::X20; // "s4"
818 case '5': // 4 strings to match.
819 return RISCV::X21; // "s5"
820 case '6': // 5 strings to match.
821 return RISCV::X22; // "s6"
822 case '7': // 4 strings to match.
823 return RISCV::X23; // "s7"
824 case '8': // 5 strings to match.
825 return RISCV::X24; // "s8"
826 case '9': // 4 strings to match.
827 return RISCV::X25; // "s9"
828 case 'p': // 5 strings to match.
829 return RISCV::X2; // "sp"
830 }
831 break;
832 case 't': // 36 strings to match.
833 switch (Name[1]) {
834 default: break;
835 case '0': // 4 strings to match.
836 return RISCV::X5; // "t0"
837 case '1': // 5 strings to match.
838 return RISCV::X6; // "t1"
839 case '2': // 4 strings to match.
840 return RISCV::X7; // "t2"
841 case '3': // 5 strings to match.
842 return RISCV::X28; // "t3"
843 case '4': // 4 strings to match.
844 return RISCV::X29; // "t4"
845 case '5': // 5 strings to match.
846 return RISCV::X30; // "t5"
847 case '6': // 4 strings to match.
848 return RISCV::X31; // "t6"
849 case 'p': // 5 strings to match.
850 return RISCV::X4; // "tp"
851 }
852 break;
853 }
854 break;
855 case 3: // 149 strings to match.
856 switch (Name[0]) {
857 default: break;
858 case 'f': // 140 strings to match.
859 switch (Name[1]) {
860 default: break;
861 case 'a': // 40 strings to match.
862 switch (Name[2]) {
863 default: break;
864 case '0': // 5 strings to match.
865 return RISCV::F10_D; // "fa0"
866 case '1': // 5 strings to match.
867 return RISCV::F11_D; // "fa1"
868 case '2': // 5 strings to match.
869 return RISCV::F12_D; // "fa2"
870 case '3': // 5 strings to match.
871 return RISCV::F13_D; // "fa3"
872 case '4': // 5 strings to match.
873 return RISCV::F14_D; // "fa4"
874 case '5': // 5 strings to match.
875 return RISCV::F15_D; // "fa5"
876 case '6': // 5 strings to match.
877 return RISCV::F16_D; // "fa6"
878 case '7': // 5 strings to match.
879 return RISCV::F17_D; // "fa7"
880 }
881 break;
882 case 's': // 50 strings to match.
883 switch (Name[2]) {
884 default: break;
885 case '0': // 5 strings to match.
886 return RISCV::F8_D; // "fs0"
887 case '1': // 5 strings to match.
888 return RISCV::F9_D; // "fs1"
889 case '2': // 5 strings to match.
890 return RISCV::F18_D; // "fs2"
891 case '3': // 5 strings to match.
892 return RISCV::F19_D; // "fs3"
893 case '4': // 5 strings to match.
894 return RISCV::F20_D; // "fs4"
895 case '5': // 5 strings to match.
896 return RISCV::F21_D; // "fs5"
897 case '6': // 5 strings to match.
898 return RISCV::F22_D; // "fs6"
899 case '7': // 5 strings to match.
900 return RISCV::F23_D; // "fs7"
901 case '8': // 5 strings to match.
902 return RISCV::F24_D; // "fs8"
903 case '9': // 5 strings to match.
904 return RISCV::F25_D; // "fs9"
905 }
906 break;
907 case 't': // 50 strings to match.
908 switch (Name[2]) {
909 default: break;
910 case '0': // 5 strings to match.
911 return RISCV::F0_D; // "ft0"
912 case '1': // 5 strings to match.
913 return RISCV::F1_D; // "ft1"
914 case '2': // 5 strings to match.
915 return RISCV::F2_D; // "ft2"
916 case '3': // 5 strings to match.
917 return RISCV::F3_D; // "ft3"
918 case '4': // 5 strings to match.
919 return RISCV::F4_D; // "ft4"
920 case '5': // 5 strings to match.
921 return RISCV::F5_D; // "ft5"
922 case '6': // 5 strings to match.
923 return RISCV::F6_D; // "ft6"
924 case '7': // 5 strings to match.
925 return RISCV::F7_D; // "ft7"
926 case '8': // 5 strings to match.
927 return RISCV::F28_D; // "ft8"
928 case '9': // 5 strings to match.
929 return RISCV::F29_D; // "ft9"
930 }
931 break;
932 }
933 break;
934 case 's': // 9 strings to match.
935 if (Name[1] != '1')
936 break;
937 switch (Name[2]) {
938 default: break;
939 case '0': // 5 strings to match.
940 return RISCV::X26; // "s10"
941 case '1': // 4 strings to match.
942 return RISCV::X27; // "s11"
943 }
944 break;
945 }
946 break;
947 case 4: // 26 strings to match.
948 switch (Name[0]) {
949 default: break;
950 case 'f': // 20 strings to match.
951 switch (Name[1]) {
952 default: break;
953 case 's': // 10 strings to match.
954 if (Name[2] != '1')
955 break;
956 switch (Name[3]) {
957 default: break;
958 case '0': // 5 strings to match.
959 return RISCV::F26_D; // "fs10"
960 case '1': // 5 strings to match.
961 return RISCV::F27_D; // "fs11"
962 }
963 break;
964 case 't': // 10 strings to match.
965 if (Name[2] != '1')
966 break;
967 switch (Name[3]) {
968 default: break;
969 case '0': // 5 strings to match.
970 return RISCV::F30_D; // "ft10"
971 case '1': // 5 strings to match.
972 return RISCV::F31_D; // "ft11"
973 }
974 break;
975 }
976 break;
977 case 'n': // 1 string to match.
978 if (memcmp(Name.data()+1, "ull", 3) != 0)
979 break;
980 return RISCV::X0_Y; // "null"
981 case 'z': // 5 strings to match.
982 if (memcmp(Name.data()+1, "ero", 3) != 0)
983 break;
984 return RISCV::X0; // "zero"
985 }
986 break;
987 }
988 return RISCV::NoRegister;
989}
990
991#endif // GET_REGISTER_MATCHER
992
993
994#ifdef GET_SUBTARGET_FEATURE_NAME
995#undef GET_SUBTARGET_FEATURE_NAME
996
997// User-level names for subtarget features that participate in
998// instruction matching.
999static const char *getSubtargetFeatureName(uint64_t Val) {
1000 switch(Val) {
1001 case Feature_HasStdExtZibiBit: return "'Zibi' (Branch with Immediate)";
1002 case Feature_HasStdExtZicbomBit: return "'Zicbom' (Cache-Block Management Instructions)";
1003 case Feature_HasStdExtZicbopBit: return "'Zicbop' (Cache-Block Prefetch Instructions)";
1004 case Feature_HasStdExtZicbozBit: return "'Zicboz' (Cache-Block Zero Instructions)";
1005 case Feature_HasStdExtZicsrBit: return "'Zicsr' (CSRs)";
1006 case Feature_HasStdExtZicondBit: return "(Integer Conditional Operations)";
1007 case Feature_HasStdExtZifenceiBit: return "'Zifencei' (fence.i)";
1008 case Feature_HasStdExtZihintpauseBit: return "'Zihintpause' (Pause Hint)";
1009 case Feature_HasStdExtZihintntlBit: return "'Zihintntl' (Non-Temporal Locality Hints)";
1010 case Feature_HasStdExtZimopBit: return "'Zimop' (May-Be-Operations)";
1011 case Feature_HasStdExtZicfissBit: return "'Zicfiss' (Shadow stack)";
1012 case Feature_HasStdExtZilsdBit: return "'Zilsd' (Load/Store pair instructions)";
1013 case Feature_HasStdExtZmmulBit: return "'Zmmul' (Integer Multiplication)";
1014 case Feature_HasStdExtMBit: return "'M' (Integer Multiplication and Division)";
1015 case Feature_HasStdExtZaamoBit: return "'Zaamo' (Atomic Memory Operations)";
1016 case Feature_HasStdExtZalrscBit: return "'Zalrsc' (Load-Reserved/Store-Conditional)";
1017 case Feature_HasStdExtABit: return "'A' (Atomic Instructions)";
1018 case Feature_HasStdExtZtsoBit: return "'Ztso' (Memory Model - Total Store Order)";
1019 case Feature_HasStdExtZabhaBit: return "'Zabha' (Byte and Halfword Atomic Memory Operations)";
1020 case Feature_HasStdExtZacasBit: return "'Zacas' (Atomic Compare-And-Swap Instructions)";
1021 case Feature_HasStdExtZalasrBit: return "'Zalasr' (Load-Acquire and Store-Release Instructions)";
1022 case Feature_HasStdExtZawrsBit: return "'Zawrs' (Wait on Reservation Set)";
1023 case Feature_HasStdExtFBit: return "'F' (Single-Precision Floating-Point)";
1024 case Feature_HasStdExtDBit: return "'D' (Double-Precision Floating-Point)";
1025 case Feature_HasStdExtQBit: return "'Q' (Quad-Precision Floating-Point)";
1026 case Feature_HasStdExtZfhminBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)";
1027 case Feature_HasStdExtZfhBit: return "'Zfh' (Half-Precision Floating-Point)";
1028 case Feature_HasStdExtZfbfminBit: return "'Zfbfmin' (Scalar BF16 Converts)";
1029 case Feature_HasHalfFPLoadStoreMoveBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts)";
1030 case Feature_HasStdExtZfaBit: return "'Zfa' (Additional Floating-Point)";
1031 case Feature_HasStdExtZfinxBit: return "'Zfinx' (Float in Integer)";
1032 case Feature_HasStdExtFOrZfinxBit: return "'F' (Single-Precision Floating-Point) or 'Zfinx' (Float in Integer)";
1033 case Feature_HasStdExtZdinxBit: return "'Zdinx' (Double in Integer)";
1034 case Feature_HasStdExtZhinxminBit: return "'Zhinx' (Half Float in Integer) or 'Zhinxmin' (Half Float in Integer Minimal)";
1035 case Feature_HasStdExtZhinxBit: return "'Zhinx' (Half Float in Integer)";
1036 case Feature_HasStdExtZcaBit: return "'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores)";
1037 case Feature_HasStdExtZcbBit: return "'Zcb' (Compressed basic bit manipulation instructions)";
1038 case Feature_HasStdExtZcfBit: return "'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions)";
1039 case Feature_HasStdExtZcdBit: return "'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions)";
1040 case Feature_HasStdExtZclsdBit: return "'Zclsd' (Compressed Load/Store pair instructions)";
1041 case Feature_HasStdExtZcmpBit: return "'Zcmp' (sequenced instructions for code-size reduction)";
1042 case Feature_HasStdExtZcmtBit: return "'Zcmt' (table jump instructions for code-size reduction)";
1043 case Feature_HasStdExtZcmopBit: return "'Zcmop' (Compressed May-Be-Operations)";
1044 case Feature_HasStdExtZbaBit: return "'Zba' (Address Generation Instructions)";
1045 case Feature_HasStdExtZbbBit: return "'Zbb' (Basic Bit-Manipulation)";
1046 case Feature_NoStdExtZbbBit: return "";
1047 case Feature_HasStdExtZbsBit: return "'Zbs' (Single-Bit Instructions)";
1048 case Feature_HasStdExtZbkbBit: return "'Zbkb' (Bitmanip instructions for Cryptography)";
1049 case Feature_NoStdExtZbkbBit: return "";
1050 case Feature_HasStdExtZbkxBit: return "'Zbkx' (Crossbar permutation instructions)";
1051 case Feature_HasStdExtZbbOrZbkbBit: return "'Zbb' (Basic Bit-Manipulation) or 'Zbkb' (Bitmanip instructions for Cryptography)";
1052 case Feature_HasStdExtZbkcBit: return "'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography)";
1053 case Feature_HasStdExtZbcBit: return "'Zbc' (Carry-Less Multiplication)";
1054 case Feature_HasStdExtZkndBit: return "'Zknd' (NIST Suite: AES Decryption)";
1055 case Feature_HasStdExtZkneBit: return "'Zkne' (NIST Suite: AES Encryption)";
1056 case Feature_HasStdExtZkndOrZkneBit: return "'Zknd' (NIST Suite: AES Decryption) or 'Zkne' (NIST Suite: AES Encryption)";
1057 case Feature_HasStdExtZknhBit: return "'Zknh' (NIST Suite: Hash Function Instructions)";
1058 case Feature_HasStdExtZksedBit: return "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)";
1059 case Feature_HasStdExtZkshBit: return "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)";
1060 case Feature_HasStdExtZkrBit: return "'Zkr' (Entropy Source Extension)";
1061 case Feature_HasStdExtZvabdBit: return "'Zvabd' (Vector Absolute Difference)";
1062 case Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit: return "'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Product)";
1063 case Feature_HasStdExtZvfwdota16bfBit: return "'Zvfwdota16bf' (BF16 Dot-Product)";
1064 case Feature_HasStdExtZvfqwdota8fBit: return "'Zvfqwdota8f' (OCP FP8 Dot-Product)";
1065 case Feature_HasStdExtZvfbfminBit: return "'Zvfbfmin' (Vector BF16 Converts)";
1066 case Feature_HasStdExtZvfbfwmaBit: return "'Zvfbfwma' (Vector BF16 widening mul-add)";
1067 case Feature_HasStdExtZfhOrZvfhBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zvfh' (Vector Half-Precision Floating-Point)";
1068 case Feature_HasStdExtZvfofp8minBit: return "'Zvfofp8min' (Vector OFP8 Converts)";
1069 case Feature_HasStdExtZvfbfminOrZvfofp8minBit: return "'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts)";
1070 case Feature_HasStdExtZvkbBit: return "'Zvkb' (Vector Bit-manipulation used in Cryptography)";
1071 case Feature_HasStdExtZvbbBit: return "'Zvbb' (Vector basic bit-manipulation instructions)";
1072 case Feature_HasStdExtZvbcBit: return "'Zvbc' (Vector Carryless Multiplication)";
1073 case Feature_HasStdExtZvbcOrZvbc32eBit: return "'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)";
1074 case Feature_HasStdExtZvkgBit: return "'Zvkg' (Vector GCM instructions for Cryptography)";
1075 case Feature_HasStdExtZvkgsBit: return "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)";
1076 case Feature_HasStdExtZvknedBit: return "'Zvkned' (Vector AES Encryption & Decryption (Single Round))";
1077 case Feature_HasStdExtZvknhaBit: return "'Zvknha' (Vector SHA-2 (SHA-256 only))";
1078 case Feature_HasStdExtZvknhbBit: return "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))";
1079 case Feature_HasStdExtZvksedBit: return "'Zvksed' (SM4 Block Cipher Instructions)";
1080 case Feature_HasStdExtZvkshBit: return "'Zvksh' (SM3 Hash Function Instructions)";
1081 case Feature_HasStdExtZvdot4a8iBit: return "'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers)";
1082 case Feature_HasStdExtZvzipBit: return "'Zvzip' (Vector Reordering Structured Data)";
1083 case Feature_HasStdExtZvvmmBit: return "'Zvvmm' (Integer Matrix Multiply-Accumulate)";
1084 case Feature_HasStdExtZvvfmmBit: return "'Zvvfmm' (Floating-Point Matrix Multiply-Accumulate)";
1085 case Feature_HasStdExtZvvmtlsBit: return "'Zvvmtls' (Matrix Tile Load/Store)";
1086 case Feature_HasStdExtZvvmttlsBit: return "'Zvvmttls' (Transposing Matrix Tile Load/Store)";
1087 case Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit: return "'Zvqwbdota8i' or 'Zvqwbdota16i' (8-bit or 16-bit integer batched dot-product extension)";
1088 case Feature_HasStdExtZvfwbdota16bfBit: return "'Zvfwbdota16bf' (BF16 batched dot-product extension)";
1089 case Feature_HasStdExtZvfqwbdota8fBit: return "'Zvfqwbdota8f' (OCP FP8 batched dot-product extension)";
1090 case Feature_HasStdExtZvfbdota32fBit: return "'Zvfbdota32f' (FP32 batched dot-product extension)";
1091 case Feature_HasVInstructionsBit: return "'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors)";
1092 case Feature_HasVInstructionsI64Bit: return "'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors)";
1093 case Feature_HasVInstructionsAnyFBit: return "'V' (Vector Extension for Application Processors), 'Zve32f' (Vector Extensions for Embedded Processors)";
1094 case Feature_HasVInstructionsF16MinimalBit: return "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or 'Zvfh' (Vector Half-Precision Floating-Point)";
1095 case Feature_HasStdExtHBit: return "'H' (Hypervisor)";
1096 case Feature_HasStdExtSmrnmiBit: return "'Smrnmi' (Resumable Non-Maskable Interrupts)";
1097 case Feature_HasStdExtSvinvalBit: return "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)";
1098 case Feature_HasStdExtSmctrOrSsctrBit: return "'Smctr' (Control Transfer Records Machine Level) or 'Ssctr' (Control Transfer Records Supervisor Level)";
1099 case Feature_HasStdExtPBit: return "'Base P' (Packed SIMD)";
1100 case Feature_HasStdExtZbkbOrPBit: return "'Zbkb' (Bitmanip instructions for Cryptography) or 'Base P' (Packed-SIMD)";
1101 case Feature_HasStdExtYBit: return "'Base Y' (CHERI)";
1102 case Feature_HasVendorXVentanaCondOpsBit: return "'XVentanaCondOps' (Ventana Conditional Ops)";
1103 case Feature_HasVendorXTHeadBaBit: return "'XTHeadBa' (T-Head address calculation instructions)";
1104 case Feature_HasVendorXTHeadBbBit: return "'XTHeadBb' (T-Head basic bit-manipulation instructions)";
1105 case Feature_HasVendorXTHeadBsBit: return "'XTHeadBs' (T-Head single-bit instructions)";
1106 case Feature_HasVendorXTHeadCondMovBit: return "'XTHeadCondMov' (T-Head conditional move instructions)";
1107 case Feature_HasVendorXTHeadCmoBit: return "'XTHeadCmo' (T-Head cache management instructions)";
1108 case Feature_HasVendorXTHeadFMemIdxBit: return "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)";
1109 case Feature_HasVendorXTHeadMacBit: return "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)";
1110 case Feature_HasVendorXTHeadMemIdxBit: return "'XTHeadMemIdx' (T-Head Indexed Memory Operations)";
1111 case Feature_HasVendorXTHeadMemPairBit: return "'XTHeadMemPair' (T-Head two-GPR Memory Operations)";
1112 case Feature_HasVendorXTHeadSyncBit: return "'XTHeadSync' (T-Head multicore synchronization instructions)";
1113 case Feature_HasVendorXTHeadVdotBit: return "'XTHeadVdot' (T-Head Vector Extensions for Dot)";
1114 case Feature_HasVendorXSfvcpBit: return "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)";
1115 case Feature_HasVendorXSfmmbaseBit: return "'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)";
1116 case Feature_HasVendorXSfmm32a8fBit: return "'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)";
1117 case Feature_HasVendorXSfmm32a8iBit: return "'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)";
1118 case Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit: return "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF)), or 'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b), or 'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)";
1119 case Feature_HasVendorXSfvqmaccdodBit: return "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))";
1120 case Feature_HasVendorXSfvqmaccqoqBit: return "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))";
1121 case Feature_HasVendorXSfvfwmaccqqqBit: return "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))";
1122 case Feature_HasVendorXSfvfnrclipxfqfBit: return "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)";
1123 case Feature_HasVendorXSfvfexpAnyBit: return "'Xsfvfbfexp16e', 'Xsfvfexp16e', or 'Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction)";
1124 case Feature_HasVendorXSfvfexpaBit: return "'Xsfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)";
1125 case Feature_HasVendorXSiFivecdiscarddloneBit: return "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)";
1126 case Feature_HasVendorXSiFivecflushdloneBit: return "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)";
1127 case Feature_HasVendorXSfceaseBit: return "'XSfcease' (SiFive sf.cease Instruction)";
1128 case Feature_HasVendorXCVelwBit: return "'XCVelw' (CORE-V Event Load Word)";
1129 case Feature_HasVendorXCVbitmanipBit: return "'XCVbitmanip' (CORE-V Bit Manipulation)";
1130 case Feature_HasVendorXCVmacBit: return "'XCVmac' (CORE-V Multiply-Accumulate)";
1131 case Feature_HasVendorXCVmemBit: return "'XCVmem' (CORE-V Post-incrementing Load & Store)";
1132 case Feature_HasVendorXCValuBit: return "'XCValu' (CORE-V ALU Operations)";
1133 case Feature_HasVendorXCVsimdBit: return "'XCVsimd' (CORE-V SIMD ALU)";
1134 case Feature_HasVendorXCVbiBit: return "'XCVbi' (CORE-V Immediate Branching)";
1135 case Feature_HasVendorXMIPSCMovBit: return "'Xmipscmov' ('mips.ccmov' instruction)";
1136 case Feature_HasVendorXMIPSLSPBit: return "'Xmipslsp' (load and store pair instructions)";
1137 case Feature_HasVendorXMIPSCBOPBit: return "'Xmipscbop' (MIPS hardware prefetch)";
1138 case Feature_HasVendorXMIPSEXECTLBit: return "'Xmipsexectl' (MIPS execution control)";
1139 case Feature_HasVendorXwchcBit: return "'Xwchc' (WCH/QingKe additional compressed opcodes)";
1140 case Feature_HasVendorXqccmpBit: return "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)";
1141 case Feature_HasVendorXqccmtBit: return "'Xqccmt' (Qualcomm 16-bit Table Jump)";
1142 case Feature_HasVendorXqciaBit: return "'Xqcia' (Qualcomm uC Arithmetic Extension)";
1143 case Feature_HasVendorXqciacBit: return "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)";
1144 case Feature_HasVendorXqcibiBit: return "'Xqcibi' (Qualcomm uC Branch Immediate Extension)";
1145 case Feature_HasVendorXqcibmBit: return "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)";
1146 case Feature_HasVendorXqcicliBit: return "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)";
1147 case Feature_HasVendorXqcicmBit: return "'Xqcicm' (Qualcomm uC Conditional Move Extension)";
1148 case Feature_HasVendorXqcicsBit: return "'Xqcics' (Qualcomm uC Conditional Select Extension)";
1149 case Feature_HasVendorXqcicsrBit: return "'Xqcicsr' (Qualcomm uC CSR Extension)";
1150 case Feature_HasVendorXqciintBit: return "'Xqciint' (Qualcomm uC Interrupts Extension)";
1151 case Feature_HasVendorXqciioBit: return "'Xqciio' (Qualcomm uC External Input Output Extension)";
1152 case Feature_HasVendorXqcilbBit: return "'Xqcilb' (Qualcomm uC Long Branch Extension)";
1153 case Feature_HasVendorXqciliBit: return "'Xqcili' (Qualcomm uC Load Large Immediate Extension)";
1154 case Feature_HasVendorXqciliaBit: return "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)";
1155 case Feature_HasVendorXqciloBit: return "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)";
1156 case Feature_HasVendorXqcilsmBit: return "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)";
1157 case Feature_HasVendorXqcisimBit: return "'Xqcisim' (Qualcomm uC Simulation Hint Extension)";
1158 case Feature_HasVendorXqcislsBit: return "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)";
1159 case Feature_HasVendorXqcisyncBit: return "'Xqcisync' (Qualcomm uC Sync Delay Extension)";
1160 case Feature_HasVendorXAndesPerfBit: return "'XAndesPerf' (Andes Performance Extension)";
1161 case Feature_HasVendorXAndesBFHCvtBit: return "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)";
1162 case Feature_HasVendorXAndesVBFHCvtBit: return "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)";
1163 case Feature_HasVendorXAndesVSIntHBit: return "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)";
1164 case Feature_HasVendorXAndesVSIntLoadBit: return "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)";
1165 case Feature_HasVendorXAndesVPackFPHBit: return "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)";
1166 case Feature_HasVendorXAndesVDotBit: return "'XAndesVDot' (Andes Vector Dot Product Extension)";
1167 case Feature_HasVendorXSMTVDotBit: return "'XSMTVDot' (SpacemiT Vector Dot Product Extension)";
1168 case Feature_HasXAIFETBit: return "'XAIFET' (AI Foundry ET Extension)";
1169 case Feature_HasCheriotBit: return "'XCheriot' (CHERIoT Extension)";
1170 case Feature_IsRV64Bit: return "RV64I Base Instruction Set";
1171 case Feature_IsRV32Bit: return "RV32I Base Instruction Set";
1172 default: return "(unknown)";
1173 }
1174}
1175
1176#endif // GET_SUBTARGET_FEATURE_NAME
1177
1178
1179#ifdef GET_MATCHER_IMPLEMENTATION
1180#undef GET_MATCHER_IMPLEMENTATION
1181
1182static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
1183 switch (Mnemonic.size()) {
1184 default: break;
1185 case 4: // 4 strings to match.
1186 switch (Mnemonic[0]) {
1187 default: break;
1188 case 'f': // 2 strings to match.
1189 switch (Mnemonic[1]) {
1190 default: break;
1191 case 'r': // 1 string to match.
1192 if (memcmp(Mnemonic.data()+2, "sr", 2) != 0)
1193 break;
1194 if (Features.test(Feature_HasStdExtFOrZfinxBit)) // "frsr"
1195 Mnemonic = "frcsr";
1196 return;
1197 case 's': // 1 string to match.
1198 if (memcmp(Mnemonic.data()+2, "sr", 2) != 0)
1199 break;
1200 if (Features.test(Feature_HasStdExtFOrZfinxBit)) // "fssr"
1201 Mnemonic = "fscsr";
1202 return;
1203 }
1204 break;
1205 case 'm': // 1 string to match.
1206 if (memcmp(Mnemonic.data()+1, "ove", 3) != 0)
1207 break;
1208 Mnemonic = "mv"; // "move"
1209 return;
1210 case 'y': // 1 string to match.
1211 if (memcmp(Mnemonic.data()+1, "hiw", 3) != 0)
1212 break;
1213 if (Features.test(Feature_HasStdExtYBit)) // "yhiw"
1214 Mnemonic = "packy";
1215 return;
1216 }
1217 break;
1218 case 5: // 1 string to match.
1219 if (memcmp(Mnemonic.data()+0, "scall", 5) != 0)
1220 break;
1221 Mnemonic = "ecall"; // "scall"
1222 return;
1223 case 6: // 3 strings to match.
1224 switch (Mnemonic[0]) {
1225 default: break;
1226 case 's': // 1 string to match.
1227 if (memcmp(Mnemonic.data()+1, "break", 5) != 0)
1228 break;
1229 Mnemonic = "ebreak"; // "sbreak"
1230 return;
1231 case 'v': // 2 strings to match.
1232 switch (Mnemonic[1]) {
1233 default: break;
1234 case 'l': // 1 string to match.
1235 if (memcmp(Mnemonic.data()+2, "e1.v", 4) != 0)
1236 break;
1237 if (Features.test(Feature_HasVInstructionsBit)) // "vle1.v"
1238 Mnemonic = "vlm.v";
1239 return;
1240 case 's': // 1 string to match.
1241 if (memcmp(Mnemonic.data()+2, "e1.v", 4) != 0)
1242 break;
1243 if (Features.test(Feature_HasVInstructionsBit)) // "vse1.v"
1244 Mnemonic = "vsm.v";
1245 return;
1246 }
1247 break;
1248 }
1249 break;
1250 case 7: // 4 strings to match.
1251 switch (Mnemonic[0]) {
1252 default: break;
1253 case 'c': // 1 string to match.
1254 if (memcmp(Mnemonic.data()+1, "v.slet", 6) != 0)
1255 break;
1256 if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit)) // "cv.slet"
1257 Mnemonic = "cv.sle";
1258 return;
1259 case 'f': // 2 strings to match.
1260 if (memcmp(Mnemonic.data()+1, "mv.", 3) != 0)
1261 break;
1262 switch (Mnemonic[4]) {
1263 default: break;
1264 case 's': // 1 string to match.
1265 if (memcmp(Mnemonic.data()+5, ".x", 2) != 0)
1266 break;
1267 if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x"
1268 Mnemonic = "fmv.w.x";
1269 return;
1270 case 'x': // 1 string to match.
1271 if (memcmp(Mnemonic.data()+5, ".s", 2) != 0)
1272 break;
1273 if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s"
1274 Mnemonic = "fmv.x.w";
1275 return;
1276 }
1277 break;
1278 case 'v': // 1 string to match.
1279 if (memcmp(Mnemonic.data()+1, "popc.m", 6) != 0)
1280 break;
1281 if (Features.test(Feature_HasVInstructionsBit)) // "vpopc.m"
1282 Mnemonic = "vcpop.m";
1283 return;
1284 }
1285 break;
1286 case 8: // 1 string to match.
1287 if (memcmp(Mnemonic.data()+0, "cv.sletu", 8) != 0)
1288 break;
1289 if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit)) // "cv.sletu"
1290 Mnemonic = "cv.sleu";
1291 return;
1292 case 10: // 1 string to match.
1293 if (memcmp(Mnemonic.data()+0, "vmornot.mm", 10) != 0)
1294 break;
1295 if (Features.test(Feature_HasVInstructionsBit)) // "vmornot.mm"
1296 Mnemonic = "vmorn.mm";
1297 return;
1298 case 11: // 2 strings to match.
1299 if (Mnemonic[0] != 'v')
1300 break;
1301 switch (Mnemonic[1]) {
1302 default: break;
1303 case 'f': // 1 string to match.
1304 if (memcmp(Mnemonic.data()+2, "redsum.vs", 9) != 0)
1305 break;
1306 if (Features.test(Feature_HasVInstructionsAnyFBit)) // "vfredsum.vs"
1307 Mnemonic = "vfredusum.vs";
1308 return;
1309 case 'm': // 1 string to match.
1310 if (memcmp(Mnemonic.data()+2, "andnot.mm", 9) != 0)
1311 break;
1312 if (Features.test(Feature_HasVInstructionsBit)) // "vmandnot.mm"
1313 Mnemonic = "vmandn.mm";
1314 return;
1315 }
1316 break;
1317 case 12: // 1 string to match.
1318 if (memcmp(Mnemonic.data()+0, "vfwredsum.vs", 12) != 0)
1319 break;
1320 if (Features.test(Feature_HasVInstructionsAnyFBit)) // "vfwredsum.vs"
1321 Mnemonic = "vfwredusum.vs";
1322 return;
1323 }
1324}
1325
1326enum {
1327 Tie0_1_1,
1328 Tie0_2_2,
1329 Tie0_3_3,
1330 Tie1_3_3,
1331};
1332
1333static const uint8_t TiedAsmOperandTable[][3] = {
1334 /* Tie0_1_1 */ { 0, 1, 1 },
1335 /* Tie0_2_2 */ { 0, 2, 2 },
1336 /* Tie0_3_3 */ { 0, 3, 3 },
1337 /* Tie1_3_3 */ { 1, 3, 3 },
1338};
1339
1340namespace {
1341enum OperatorConversionKind {
1342 CVT_Done,
1343 CVT_Reg,
1344 CVT_Tied,
1345 CVT_95_addImmOperands,
1346 CVT_95_addRegOperands,
1347 CVT_imm_95_0,
1348 CVT_95_Reg,
1349 CVT_95_addFRMArgOperands_95_defaultFRMArgOp,
1350 CVT_regX0,
1351 CVT_regX1,
1352 CVT_regX5,
1353 CVT_regX2,
1354 CVT_regX3,
1355 CVT_regX4,
1356 CVT_95_addRegListOperands,
1357 CVT_95_addStackAdjOperands,
1358 CVT_95_addCSRSystemRegisterOperands,
1359 CVT_95_addRegRegOperands,
1360 CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp,
1361 CVT_95_addFRMArgOperands,
1362 CVT_imm_95_15,
1363 CVT_95_addFenceArgOperands,
1364 CVT_95_addFPImmOperands,
1365 CVT_imm_95_3,
1366 CVT_imm_95_1,
1367 CVT_imm_95_2,
1368 CVT_regX0_Pair,
1369 CVT_95_addRegOperands_95_defaultMaskRegOp,
1370 CVT_imm_95__MINUS_1,
1371 CVT_95_addSExtImmOperands_LT_8_GT_,
1372 CVT_95_addSExtImmOperands_LT_10_GT_,
1373 CVT_imm_95_8,
1374 CVT_imm_95_16,
1375 CVT_imm_95_1536,
1376 CVT_imm_95__MINUS_1280,
1377 CVT_imm_95__MINUS_2048,
1378 CVT_imm_95_1792,
1379 CVT_imm_95__MINUS_1792,
1380 CVT_imm_95__MINUS_1536,
1381 CVT_imm_95__MINUS_1024,
1382 CVT_imm_95_3072,
1383 CVT_imm_95_3200,
1384 CVT_imm_95_3074,
1385 CVT_imm_95_3202,
1386 CVT_imm_95_3073,
1387 CVT_imm_95_3201,
1388 CVT_95_addVTypeIOperands,
1389 CVT_reg0,
1390 CVT_imm_95_64,
1391 CVT_imm_95_32,
1392 CVT_imm_95_255,
1393 CVT_NUM_CONVERTERS
1394};
1395
1396enum InstructionConversionKind {
1397 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4,
1398 Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4,
1399 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3,
1400 Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3,
1401 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3,
1402 Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2,
1403 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0,
1404 Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3,
1405 Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3,
1406 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0,
1407 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3,
1408 Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3,
1409 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4,
1410 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0,
1411 Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm12LO1_3,
1412 Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2,
1413 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4,
1414 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5,
1415 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5,
1416 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_5__imm_95_0,
1417 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__SImm261_4,
1418 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4,
1419 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_5__imm_95_0,
1420 Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__SImm261_4,
1421 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5,
1422 Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6,
1423 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0,
1424 Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm12LO1_3,
1425 Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2,
1426 Convert__Reg1_0__Reg1_1__Reg1_2,
1427 Convert__Reg1_0__Reg1_1,
1428 Convert__Reg1_0__Reg1_1__SImm12LO1_2,
1429 Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3,
1430 Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2,
1431 Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3,
1432 Convert__Reg1_0__Reg1_1__RnumArg1_2,
1433 Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2,
1434 Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3,
1435 Convert__Reg1_0__Reg1_1__SImm101_2,
1436 Convert__Reg1_0__SImm12LO1_1__Reg1_3,
1437 Convert__Reg1_0__UImm20LUI1_1,
1438 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
1439 Convert__Reg1_0__Reg1_1__FRMArg1_2,
1440 Convert__Reg1_0__Reg1_2,
1441 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4,
1442 Convert__Reg1_0__Reg1_1__UImm31_2,
1443 Convert__Reg1_0__Reg1_1__UImm51_2,
1444 Convert__Reg1_0__Reg1_1__UImm81_2,
1445 Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3,
1446 Convert__Reg1_0,
1447 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1,
1448 Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2,
1449 Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2,
1450 Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2,
1451 Convert__Reg1_0__UImm20AUIPC1_1,
1452 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2,
1453 Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2,
1454 Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2,
1455 Convert__Reg1_0__regX0__BareSImm13Lsb01_1,
1456 Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2,
1457 Convert__regX0__Reg1_0__BareSImm13Lsb01_1,
1458 Convert__Reg1_0__Tie0_1_1__Reg1_1,
1459 Convert__Reg1_0__Tie0_1_1__SImm61_1,
1460 Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1,
1461 Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2,
1462 Convert__Reg1_0__BareSImm9Lsb01_1,
1463 Convert_NoOperands,
1464 Convert__Reg1_0__Reg1_2__imm_95_0,
1465 Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1,
1466 Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1,
1467 Convert__Reg1_0__Reg1_3__UImm7Lsb001_1,
1468 Convert__Reg1_0__Reg1_3__UImm8Lsb001_1,
1469 Convert__BareSImm12Lsb01_0,
1470 Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4,
1471 Convert__Reg1_0__Reg1_3__UImm21_1,
1472 Convert__Reg1_0__Reg1_3__UImm21_1__QCAccessSymbol1_5,
1473 Convert__GPRPairCRV321_0__Reg1_2__imm_95_0,
1474 Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1,
1475 Convert__GPRPairNoX0RV321_0__Reg1_2__imm_95_0,
1476 Convert__GPRPairNoX0RV321_0__Reg1_3__UImm9Lsb0001_1,
1477 Convert__Reg1_0__Reg1_3__UImm2Lsb01_1,
1478 Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5,
1479 Convert__Reg1_0__SImm61_1,
1480 Convert__Reg1_0__CLUIImm1_1,
1481 Convert__Reg1_0__Reg1_3__UImm7Lsb001_1__QCAccessSymbol1_5,
1482 Convert__regX1,
1483 Convert__regX5,
1484 Convert__SImm6NonZero1_0,
1485 Convert__Reg1_0__Tie0_1_1,
1486 Convert__regX0__Tie0_1_1__regX5,
1487 Convert__regX0__Tie0_1_1__regX2,
1488 Convert__regX0__Tie0_1_1__regX3,
1489 Convert__regX0__Tie0_1_1__regX4,
1490 Convert__GPRPairRV321_0__Reg1_2__imm_95_0,
1491 Convert__GPRPairRV321_0__Reg1_3__UImm9Lsb0001_1,
1492 Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1,
1493 Convert__Reg1_0__Tie0_1_1__imm_95_0,
1494 Convert__CallSymbol1_0,
1495 Convert__Reg1_0__CallSymbol1_1,
1496 Convert__ZeroOffsetMemOpOperand1_0,
1497 Convert__UImm8GE321_0,
1498 Convert__UImm51_0,
1499 Convert__RegList1_0__StackAdj1_1,
1500 Convert__RegList1_0__NegStackAdj1_1,
1501 Convert__regX0__CSRSystemRegister1_0__Reg1_1,
1502 Convert__regX0__CSRSystemRegister1_0__UImm51_1,
1503 Convert__Reg1_0__CSRSystemRegister1_1__regX0,
1504 Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2,
1505 Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2,
1506 Convert__Reg1_0__Reg1_1__SImm61_2,
1507 Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3,
1508 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
1509 Convert__Reg1_0__Reg1_1__UImm61_2,
1510 Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3,
1511 Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2,
1512 Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3,
1513 Convert__Reg1_0__BareSymbol1_1,
1514 Convert__Reg1_0__Reg1_3__SImm12LO1_1,
1515 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3,
1516 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2,
1517 Convert__Reg1_0__RegReg2_1,
1518 Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4,
1519 Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4,
1520 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3,
1521 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
1522 Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4,
1523 Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4,
1524 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2,
1525 Convert__Reg1_0__Reg1_1__UImm41_2,
1526 Convert__Reg1_0__Reg1_1__Reg1_1,
1527 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1,
1528 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1,
1529 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1,
1530 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1,
1531 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3,
1532 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3,
1533 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3,
1534 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3,
1535 Convert__Reg1_0__GPRF64AsFPR1_1,
1536 Convert__Reg1_0__GPRPairAsFPR1_1,
1537 Convert__Reg1_0__GPRAsFPR161_1,
1538 Convert__Reg1_0__GPRAsFPR321_1,
1539 Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2,
1540 Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1541 Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1542 Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2,
1543 Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
1544 Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
1545 Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2,
1546 Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2,
1547 Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2,
1548 Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2,
1549 Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2,
1550 Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2,
1551 Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2,
1552 Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2,
1553 Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2,
1554 Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2,
1555 Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2,
1556 Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2,
1557 Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2,
1558 Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2,
1559 Convert__Reg1_0__Reg1_1__RTZArg1_2,
1560 Convert__imm_95_15__imm_95_15,
1561 Convert__FenceArg1_0__FenceArg1_1,
1562 Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
1563 Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
1564 Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2,
1565 Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2,
1566 Convert__Reg1_0__Reg1_2__Reg1_1,
1567 Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1,
1568 Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1,
1569 Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1,
1570 Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1,
1571 Convert__Reg1_2__Reg1_0__BareSymbol1_1,
1572 Convert__Reg1_0__LoadFPImm1_1,
1573 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4,
1574 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4,
1575 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4,
1576 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4,
1577 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
1578 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
1579 Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2,
1580 Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2,
1581 Convert__Reg1_0__imm_95_3__regX0,
1582 Convert__Reg1_0__imm_95_1__regX0,
1583 Convert__Reg1_0__imm_95_2__regX0,
1584 Convert__regX0__imm_95_3__Reg1_0,
1585 Convert__Reg1_0__imm_95_3__Reg1_1,
1586 Convert__regX0__imm_95_1__Reg1_0,
1587 Convert__Reg1_0__imm_95_1__Reg1_1,
1588 Convert__regX0__imm_95_1__UImm51_0,
1589 Convert__Reg1_0__imm_95_1__UImm51_1,
1590 Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2,
1591 Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2,
1592 Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2,
1593 Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2,
1594 Convert__regX0__imm_95_2__Reg1_0,
1595 Convert__Reg1_0__imm_95_2__Reg1_1,
1596 Convert__regX0__imm_95_2__UImm51_0,
1597 Convert__Reg1_0__imm_95_2__UImm51_1,
1598 Convert__regX0__regX0,
1599 Convert__Reg1_0__regX0,
1600 Convert__regX0__BareSImm21Lsb01_0,
1601 Convert__regX1__BareSImm21Lsb01_0,
1602 Convert__Reg1_0__BareSImm21Lsb01_1,
1603 Convert__regX1__Reg1_0__imm_95_0,
1604 Convert__Reg1_0__Reg1_1__imm_95_0,
1605 Convert__regX1__Reg1_0__SImm12LO1_1,
1606 Convert__regX1__Reg1_1__imm_95_0,
1607 Convert__regX1__Reg1_2__SImm12LO1_0,
1608 Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5,
1609 Convert__regX0__Reg1_0__imm_95_0,
1610 Convert__regX0__Reg1_0__SImm12LO1_1,
1611 Convert__regX0__Reg1_1__imm_95_0,
1612 Convert__regX0__Reg1_2__SImm12LO1_0,
1613 Convert__Reg1_1__PseudoJumpSymbol1_0,
1614 Convert__Reg1_0__ImmXLenLI_Restricted1_1,
1615 Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5,
1616 Convert__GPRPairRV321_0__BareSymbol1_1,
1617 Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1,
1618 Convert__Reg1_0__regX0__SImm12LO1_1,
1619 Convert__Reg1_0__ImmXLenLI1_1,
1620 Convert__regX0__UImm201_0,
1621 Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3,
1622 Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2,
1623 Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2,
1624 Convert__Reg1_3__UImm91_1__UImm51_0,
1625 Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2,
1626 Convert__Reg1_0__Reg1_1__regX0,
1627 Convert__Reg1_0__regX0__Reg1_1,
1628 Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1,
1629 Convert__Reg1_0__GPRPairRV321_1__Reg1_2,
1630 Convert__Reg1_0__GPRPairRV321_1__UImm61_2,
1631 Convert__Reg1_0__SImm181_1,
1632 Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2,
1633 Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2,
1634 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3,
1635 Convert__Reg1_0__SImm20Lsb0001_1,
1636 Convert__Reg1_0__SImm18Lsb01_1,
1637 Convert__Reg1_0__SImm19Lsb001_1,
1638 Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1639 Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3,
1640 Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2,
1641 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2,
1642 Convert__regX0__regX0__imm_95_0,
1643 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1,
1644 Convert__regX0__regX0__regX5,
1645 Convert__regX0__regX0__regX2,
1646 Convert__regX0__regX0__regX3,
1647 Convert__regX0__regX0__regX4,
1648 Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair,
1649 Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2,
1650 Convert__imm_95_1__imm_95_0,
1651 Convert__Reg1_0__SImm8PLI_B1_1,
1652 Convert__GPRPairRV321_0__SImm8PLI_B1_1,
1653 Convert__GPRPairRV321_0__SImm10PLI_H1_1,
1654 Convert__Reg1_0__SImm10PLI_H1_1,
1655 Convert__Reg1_0__SImm10PLI_W1_1,
1656 Convert__GPRPairRV321_0__SImm10PLUI1_1,
1657 Convert__Reg1_0__SImm10PLUI1_1,
1658 Convert__GPRPairRV321_0__Reg1_1__Reg1_2,
1659 Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1,
1660 Convert__GPRPairRV321_0__regX0_Pair__Reg1_1,
1661 Convert__Reg1_0__GPRPairRV321_1__UImm41_2,
1662 Convert__Reg1_0__GPRPairRV321_1__UImm51_2,
1663 Convert__Reg1_0__GPRPairRV321_1__imm_95_0,
1664 Convert__Reg1_0__GPRPairRV321_1__imm_95_8,
1665 Convert__Reg1_0__GPRPairRV321_1__imm_95_16,
1666 Convert__Reg1_2__SImm12Lsb000001_0,
1667 Convert__GPRPairRV321_0__GPRPairRV321_1,
1668 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2,
1669 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2,
1670 Convert__Reg1_0__Reg1_1__UImm4Plus11_2,
1671 Convert__Reg1_0__Reg1_1__UImm5Plus11_2,
1672 Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2,
1673 Convert__GPRPairRV321_0__Reg1_1__regX0,
1674 Convert__GPRPairRV321_0__regX0__Reg1_1,
1675 Convert__GPRPairRV321_0__Reg1_1__UImm41_2,
1676 Convert__GPRPairRV321_0__Reg1_1__UImm51_2,
1677 Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2,
1678 Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2,
1679 Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1,
1680 Convert__regX0__Tie0_1_1__UImm5NonZero1_0,
1681 Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1,
1682 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2,
1683 Convert__regX0__Tie0_1_1__imm_95_0,
1684 Convert__UImm5Slist1_0,
1685 Convert__UImm101_0,
1686 Convert__RegListS01_0__NegStackAdj1_1,
1687 Convert__Reg1_0__UImm51_1__Reg1_2,
1688 Convert__Reg1_0__Tie0_1_1__BareSImm321_1,
1689 Convert__Reg1_0__Reg1_1__SImm261_2,
1690 Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2,
1691 Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2,
1692 Convert__BareSImm32Lsb01_0,
1693 Convert__Reg1_0__Reg1_3__SImm261_1,
1694 Convert__Reg1_0__BareSImm321_1,
1695 Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1,
1696 Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3,
1697 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3,
1698 Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3,
1699 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2,
1700 Convert__Reg1_0__Reg1_3__UImm14Lsb001_1,
1701 Convert__Reg1_0__SImm20LI1_1,
1702 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3,
1703 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3,
1704 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3,
1705 Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3,
1706 Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0,
1707 Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2,
1708 Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0,
1709 Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2,
1710 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2,
1711 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3,
1712 Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3,
1713 Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3,
1714 Convert__regX0__regX0__imm_95_1536,
1715 Convert__regX0__Reg1_0__imm_95__MINUS_1280,
1716 Convert__regX0__Reg1_0__imm_95__MINUS_2048,
1717 Convert__regX0__regX0__imm_95_1792,
1718 Convert__regX0__Reg1_0__imm_95__MINUS_1792,
1719 Convert__UImm81_0,
1720 Convert__regX0__Reg1_0__imm_95__MINUS_1536,
1721 Convert__regX0__Reg1_0__imm_95__MINUS_1024,
1722 Convert__regX0__regX0__UImm101_0,
1723 Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3,
1724 Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3,
1725 Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3,
1726 Convert__Reg1_0__Reg1_1__UImm111_2,
1727 Convert__Reg1_0__Reg1_3__UImm51_1,
1728 Convert__Reg1_0__Reg1_3__UImm41_1,
1729 Convert__Reg1_0__Reg1_3__UImm6Lsb01_1,
1730 Convert__Reg1_0__Reg1_3__UImm5Lsb01_1,
1731 Convert__Reg1_0__imm_95_3072__regX0,
1732 Convert__Reg1_0__imm_95_3200__regX0,
1733 Convert__Reg1_0__imm_95_3074__regX0,
1734 Convert__Reg1_0__imm_95_3202__regX0,
1735 Convert__Reg1_0__imm_95_3073__regX0,
1736 Convert__Reg1_0__imm_95_3201__regX0,
1737 Convert__regX0__regX1__imm_95_0,
1738 Convert__Reg1_0__Reg1_1__UImm6Plus11_2,
1739 Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1,
1740 Convert__Reg1_0__Reg1_1__imm_95_1,
1741 Convert__regX0,
1742 Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3,
1743 Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3,
1744 Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3,
1745 Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3,
1746 Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3,
1747 Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3,
1748 Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3,
1749 Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3,
1750 Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3,
1751 Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3,
1752 Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3,
1753 Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3,
1754 Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3,
1755 Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3,
1756 Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3,
1757 Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3,
1758 Convert__Reg1_0__Reg1_1__XSfmmVType1_2,
1759 Convert__Reg1_0__Reg1_1__UImm7EqXLen1_2,
1760 Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5,
1761 Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6,
1762 Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6,
1763 Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5,
1764 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1765 Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3,
1766 Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3,
1767 Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3,
1768 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3,
1769 Convert__Reg1_0__Reg1_1__Reg1_1__reg0,
1770 Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2,
1771 Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4,
1772 Convert__Reg1_0__RVVMaskRegOpOperand1_1,
1773 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1774 Convert__Reg1_0__Reg1_1__SImm51_2,
1775 Convert__Reg1_0__Reg1_0__Reg1_0,
1776 Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3,
1777 Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
1778 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3,
1779 Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4,
1780 Convert__Reg1_0__SImm51_1,
1781 Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3,
1782 Convert__Reg1_0__Reg1_1__regX0__reg0,
1783 Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2,
1784 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0,
1785 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2,
1786 Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3,
1787 Convert__Reg1_0__UImm51_1__VTypeI101_2,
1788 Convert__Reg1_0__Reg1_1__VTypeI111_2,
1789 Convert__GPRPairRV321_0__Reg1_1__UImm61_2,
1790 Convert__Reg1_0__Reg1_1__YBNDSWImm1_2,
1791 Convert__Reg1_0__Reg1_1__imm_95_64,
1792 Convert__Reg1_0__Reg1_1__imm_95_32,
1793 Convert__Reg1_0__Reg1_1__imm_95_255,
1794 CVT_NUM_SIGNATURES
1795};
1796
1797} // end anonymous namespace
1798
1799static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][15] = {
1800 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4
1801 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1802 // Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4
1803 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_Done },
1804 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3
1805 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1806 // Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3
1807 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
1808 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3
1809 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
1810 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2
1811 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1812 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0
1813 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1814 // Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3
1815 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1816 // Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3
1817 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_Done },
1818 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0
1819 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1820 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3
1821 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1822 // Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3
1823 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1824 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4
1825 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1826 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0
1827 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1828 // Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm12LO1_3
1829 { CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1830 // Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2
1831 { CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
1832 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4
1833 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
1834 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5
1835 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1836 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5
1837 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1838 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_5__imm_95_0
1839 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
1840 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__SImm261_4
1841 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 7, CVT_95_addImmOperands, 5, CVT_Done },
1842 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4
1843 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1844 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_5__imm_95_0
1845 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
1846 // Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__SImm261_4
1847 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addRegOperands, 7, CVT_95_addImmOperands, 5, CVT_Done },
1848 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5
1849 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
1850 // Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6
1851 { CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_95_addRegOperands, 7, CVT_Done },
1852 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0
1853 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
1854 // Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm12LO1_3
1855 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
1856 // Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2
1857 { CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
1858 // Convert__Reg1_0__Reg1_1__Reg1_2
1859 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1860 // Convert__Reg1_0__Reg1_1
1861 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1862 // Convert__Reg1_0__Reg1_1__SImm12LO1_2
1863 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1864 // Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3
1865 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1866 // Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2
1867 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1868 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3
1869 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1870 // Convert__Reg1_0__Reg1_1__RnumArg1_2
1871 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1872 // Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2
1873 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands, 3, CVT_Done },
1874 // Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3
1875 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
1876 // Convert__Reg1_0__Reg1_1__SImm101_2
1877 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1878 // Convert__Reg1_0__SImm12LO1_1__Reg1_3
1879 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_Done },
1880 // Convert__Reg1_0__UImm20LUI1_1
1881 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1882 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
1883 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
1884 // Convert__Reg1_0__Reg1_1__FRMArg1_2
1885 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
1886 // Convert__Reg1_0__Reg1_2
1887 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
1888 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4
1889 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
1890 // Convert__Reg1_0__Reg1_1__UImm31_2
1891 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1892 // Convert__Reg1_0__Reg1_1__UImm51_2
1893 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1894 // Convert__Reg1_0__Reg1_1__UImm81_2
1895 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1896 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3
1897 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
1898 // Convert__Reg1_0
1899 { CVT_95_Reg, 1, CVT_Done },
1900 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1
1901 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
1902 // Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2
1903 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addRegOperands, 3, CVT_Done },
1904 // Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2
1905 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1906 // Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2
1907 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
1908 // Convert__Reg1_0__UImm20AUIPC1_1
1909 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1910 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2
1911 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1912 // Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2
1913 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1914 // Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2
1915 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1916 // Convert__Reg1_0__regX0__BareSImm13Lsb01_1
1917 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
1918 // Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2
1919 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },
1920 // Convert__regX0__Reg1_0__BareSImm13Lsb01_1
1921 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1922 // Convert__Reg1_0__Tie0_1_1__Reg1_1
1923 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
1924 // Convert__Reg1_0__Tie0_1_1__SImm61_1
1925 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1926 // Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1
1927 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1928 // Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2
1929 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1930 // Convert__Reg1_0__BareSImm9Lsb01_1
1931 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1932 // Convert_NoOperands
1933 { CVT_Done },
1934 // Convert__Reg1_0__Reg1_2__imm_95_0
1935 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1936 // Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1
1937 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1938 // Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1
1939 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1940 // Convert__Reg1_0__Reg1_3__UImm7Lsb001_1
1941 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1942 // Convert__Reg1_0__Reg1_3__UImm8Lsb001_1
1943 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1944 // Convert__BareSImm12Lsb01_0
1945 { CVT_95_addImmOperands, 1, CVT_Done },
1946 // Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4
1947 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 5, CVT_Done },
1948 // Convert__Reg1_0__Reg1_3__UImm21_1
1949 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1950 // Convert__Reg1_0__Reg1_3__UImm21_1__QCAccessSymbol1_5
1951 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
1952 // Convert__GPRPairCRV321_0__Reg1_2__imm_95_0
1953 { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1954 // Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1
1955 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1956 // Convert__GPRPairNoX0RV321_0__Reg1_2__imm_95_0
1957 { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1958 // Convert__GPRPairNoX0RV321_0__Reg1_3__UImm9Lsb0001_1
1959 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1960 // Convert__Reg1_0__Reg1_3__UImm2Lsb01_1
1961 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1962 // Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5
1963 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
1964 // Convert__Reg1_0__SImm61_1
1965 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1966 // Convert__Reg1_0__CLUIImm1_1
1967 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1968 // Convert__Reg1_0__Reg1_3__UImm7Lsb001_1__QCAccessSymbol1_5
1969 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
1970 // Convert__regX1
1971 { CVT_regX1, 0, CVT_Done },
1972 // Convert__regX5
1973 { CVT_regX5, 0, CVT_Done },
1974 // Convert__SImm6NonZero1_0
1975 { CVT_95_addImmOperands, 1, CVT_Done },
1976 // Convert__Reg1_0__Tie0_1_1
1977 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1978 // Convert__regX0__Tie0_1_1__regX5
1979 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX5, 0, CVT_Done },
1980 // Convert__regX0__Tie0_1_1__regX2
1981 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX2, 0, CVT_Done },
1982 // Convert__regX0__Tie0_1_1__regX3
1983 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX3, 0, CVT_Done },
1984 // Convert__regX0__Tie0_1_1__regX4
1985 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX4, 0, CVT_Done },
1986 // Convert__GPRPairRV321_0__Reg1_2__imm_95_0
1987 { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1988 // Convert__GPRPairRV321_0__Reg1_3__UImm9Lsb0001_1
1989 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
1990 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1
1991 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
1992 // Convert__Reg1_0__Tie0_1_1__imm_95_0
1993 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
1994 // Convert__CallSymbol1_0
1995 { CVT_95_addImmOperands, 1, CVT_Done },
1996 // Convert__Reg1_0__CallSymbol1_1
1997 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1998 // Convert__ZeroOffsetMemOpOperand1_0
1999 { CVT_95_addRegOperands, 1, CVT_Done },
2000 // Convert__UImm8GE321_0
2001 { CVT_95_addImmOperands, 1, CVT_Done },
2002 // Convert__UImm51_0
2003 { CVT_95_addImmOperands, 1, CVT_Done },
2004 // Convert__RegList1_0__StackAdj1_1
2005 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
2006 // Convert__RegList1_0__NegStackAdj1_1
2007 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
2008 // Convert__regX0__CSRSystemRegister1_0__Reg1_1
2009 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
2010 // Convert__regX0__CSRSystemRegister1_0__UImm51_1
2011 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2012 // Convert__Reg1_0__CSRSystemRegister1_1__regX0
2013 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_regX0, 0, CVT_Done },
2014 // Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2
2015 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_Reg, 3, CVT_Done },
2016 // Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2
2017 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2018 // Convert__Reg1_0__Reg1_1__SImm61_2
2019 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2020 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3
2021 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2022 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
2023 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2024 // Convert__Reg1_0__Reg1_1__UImm61_2
2025 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2026 // Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3
2027 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2028 // Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2
2029 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2030 // Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3
2031 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2032 // Convert__Reg1_0__BareSymbol1_1
2033 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2034 // Convert__Reg1_0__Reg1_3__SImm12LO1_1
2035 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2036 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3
2037 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2038 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2
2039 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2040 // Convert__Reg1_0__RegReg2_1
2041 { CVT_95_Reg, 1, CVT_95_addRegRegOperands, 2, CVT_Done },
2042 // Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4
2043 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_Reg, 5, CVT_Done },
2044 // Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4
2045 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_Done },
2046 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3
2047 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2048 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
2049 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
2050 // Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4
2051 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
2052 // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4
2053 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
2054 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2
2055 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2056 // Convert__Reg1_0__Reg1_1__UImm41_2
2057 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2058 // Convert__Reg1_0__Reg1_1__Reg1_1
2059 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_Done },
2060 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1
2061 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2062 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1
2063 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2064 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1
2065 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2066 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1
2067 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
2068 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3
2069 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2070 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3
2071 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2072 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3
2073 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2074 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3
2075 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
2076 // Convert__Reg1_0__GPRF64AsFPR1_1
2077 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2078 // Convert__Reg1_0__GPRPairAsFPR1_1
2079 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2080 // Convert__Reg1_0__GPRAsFPR161_1
2081 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2082 // Convert__Reg1_0__GPRAsFPR321_1
2083 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
2084 // Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2
2085 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2086 // Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2
2087 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2088 // Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2
2089 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2090 // Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2
2091 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2092 // Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2
2093 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2094 // Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2
2095 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2096 // Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2
2097 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2098 // Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2
2099 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2100 // Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2
2101 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2102 // Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2
2103 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2104 // Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2
2105 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2106 // Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2
2107 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2108 // Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2
2109 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2110 // Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2
2111 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2112 // Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2
2113 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2114 // Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2
2115 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2116 // Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2
2117 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2118 // Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2
2119 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
2120 // Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2
2121 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2122 // Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2
2123 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2124 // Convert__Reg1_0__Reg1_1__RTZArg1_2
2125 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
2126 // Convert__imm_95_15__imm_95_15
2127 { CVT_imm_95_15, 0, CVT_imm_95_15, 0, CVT_Done },
2128 // Convert__FenceArg1_0__FenceArg1_1
2129 { CVT_95_addFenceArgOperands, 1, CVT_95_addFenceArgOperands, 2, CVT_Done },
2130 // Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
2131 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2132 // Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2
2133 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2134 // Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2
2135 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2136 // Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2
2137 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2138 // Convert__Reg1_0__Reg1_2__Reg1_1
2139 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
2140 // Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1
2141 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2142 // Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1
2143 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2144 // Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1
2145 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2146 // Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1
2147 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2148 // Convert__Reg1_2__Reg1_0__BareSymbol1_1
2149 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2150 // Convert__Reg1_0__LoadFPImm1_1
2151 { CVT_95_Reg, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
2152 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4
2153 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2154 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4
2155 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2156 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4
2157 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2158 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4
2159 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
2160 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
2161 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2162 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2
2163 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2164 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2
2165 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2166 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2
2167 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2168 // Convert__Reg1_0__imm_95_3__regX0
2169 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_regX0, 0, CVT_Done },
2170 // Convert__Reg1_0__imm_95_1__regX0
2171 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_regX0, 0, CVT_Done },
2172 // Convert__Reg1_0__imm_95_2__regX0
2173 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_regX0, 0, CVT_Done },
2174 // Convert__regX0__imm_95_3__Reg1_0
2175 { CVT_regX0, 0, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
2176 // Convert__Reg1_0__imm_95_3__Reg1_1
2177 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
2178 // Convert__regX0__imm_95_1__Reg1_0
2179 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
2180 // Convert__Reg1_0__imm_95_1__Reg1_1
2181 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
2182 // Convert__regX0__imm_95_1__UImm51_0
2183 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_addImmOperands, 1, CVT_Done },
2184 // Convert__Reg1_0__imm_95_1__UImm51_1
2185 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_addImmOperands, 2, CVT_Done },
2186 // Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2
2187 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2188 // Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2
2189 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2190 // Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2
2191 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2192 // Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2
2193 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
2194 // Convert__regX0__imm_95_2__Reg1_0
2195 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
2196 // Convert__Reg1_0__imm_95_2__Reg1_1
2197 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
2198 // Convert__regX0__imm_95_2__UImm51_0
2199 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_addImmOperands, 1, CVT_Done },
2200 // Convert__Reg1_0__imm_95_2__UImm51_1
2201 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_addImmOperands, 2, CVT_Done },
2202 // Convert__regX0__regX0
2203 { CVT_regX0, 0, CVT_regX0, 0, CVT_Done },
2204 // Convert__Reg1_0__regX0
2205 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_Done },
2206 // Convert__regX0__BareSImm21Lsb01_0
2207 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2208 // Convert__regX1__BareSImm21Lsb01_0
2209 { CVT_regX1, 0, CVT_95_addImmOperands, 1, CVT_Done },
2210 // Convert__Reg1_0__BareSImm21Lsb01_1
2211 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2212 // Convert__regX1__Reg1_0__imm_95_0
2213 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2214 // Convert__Reg1_0__Reg1_1__imm_95_0
2215 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2216 // Convert__regX1__Reg1_0__SImm12LO1_1
2217 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2218 // Convert__regX1__Reg1_1__imm_95_0
2219 { CVT_regX1, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2220 // Convert__regX1__Reg1_2__SImm12LO1_0
2221 { CVT_regX1, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2222 // Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5
2223 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
2224 // Convert__regX0__Reg1_0__imm_95_0
2225 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2226 // Convert__regX0__Reg1_0__SImm12LO1_1
2227 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2228 // Convert__regX0__Reg1_1__imm_95_0
2229 { CVT_regX0, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2230 // Convert__regX0__Reg1_2__SImm12LO1_0
2231 { CVT_regX0, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2232 // Convert__Reg1_1__PseudoJumpSymbol1_0
2233 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
2234 // Convert__Reg1_0__ImmXLenLI_Restricted1_1
2235 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2236 // Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5
2237 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
2238 // Convert__GPRPairRV321_0__BareSymbol1_1
2239 { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2240 // Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1
2241 { CVT_95_addRegOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2242 // Convert__Reg1_0__regX0__SImm12LO1_1
2243 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
2244 // Convert__Reg1_0__ImmXLenLI1_1
2245 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2246 // Convert__regX0__UImm201_0
2247 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2248 // Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3
2249 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Done },
2250 // Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2
2251 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_95_addImmOperands, 3, CVT_Done },
2252 // Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2
2253 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_95_addImmOperands, 3, CVT_Done },
2254 // Convert__Reg1_3__UImm91_1__UImm51_0
2255 { CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2256 // Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2
2257 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2258 // Convert__Reg1_0__Reg1_1__regX0
2259 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
2260 // Convert__Reg1_0__regX0__Reg1_1
2261 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
2262 // Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1
2263 { CVT_95_addRegOperands, 1, CVT_regX0_Pair, 0, CVT_95_addRegOperands, 2, CVT_Done },
2264 // Convert__Reg1_0__GPRPairRV321_1__Reg1_2
2265 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_Done },
2266 // Convert__Reg1_0__GPRPairRV321_1__UImm61_2
2267 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2268 // Convert__Reg1_0__SImm181_1
2269 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2270 // Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2
2271 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2272 // Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2
2273 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2274 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3
2275 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2276 // Convert__Reg1_0__SImm20Lsb0001_1
2277 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2278 // Convert__Reg1_0__SImm18Lsb01_1
2279 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2280 // Convert__Reg1_0__SImm19Lsb001_1
2281 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2282 // Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2283 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2284 // Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3
2285 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2286 // Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2
2287 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2288 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2
2289 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2290 // Convert__regX0__regX0__imm_95_0
2291 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done },
2292 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1
2293 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_Done },
2294 // Convert__regX0__regX0__regX5
2295 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX5, 0, CVT_Done },
2296 // Convert__regX0__regX0__regX2
2297 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX2, 0, CVT_Done },
2298 // Convert__regX0__regX0__regX3
2299 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX3, 0, CVT_Done },
2300 // Convert__regX0__regX0__regX4
2301 { CVT_regX0, 0, CVT_regX0, 0, CVT_regX4, 0, CVT_Done },
2302 // Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair
2303 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_regX0_Pair, 0, CVT_Done },
2304 // Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2
2305 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_Done },
2306 // Convert__imm_95_1__imm_95_0
2307 { CVT_imm_95_1, 0, CVT_imm_95_0, 0, CVT_Done },
2308 // Convert__Reg1_0__SImm8PLI_B1_1
2309 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_8_GT_, 2, CVT_Done },
2310 // Convert__GPRPairRV321_0__SImm8PLI_B1_1
2311 { CVT_95_addRegOperands, 1, CVT_95_addSExtImmOperands_LT_8_GT_, 2, CVT_Done },
2312 // Convert__GPRPairRV321_0__SImm10PLI_H1_1
2313 { CVT_95_addRegOperands, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2314 // Convert__Reg1_0__SImm10PLI_H1_1
2315 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2316 // Convert__Reg1_0__SImm10PLI_W1_1
2317 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2318 // Convert__GPRPairRV321_0__SImm10PLUI1_1
2319 { CVT_95_addRegOperands, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2320 // Convert__Reg1_0__SImm10PLUI1_1
2321 { CVT_95_Reg, 1, CVT_95_addSExtImmOperands_LT_10_GT_, 2, CVT_Done },
2322 // Convert__GPRPairRV321_0__Reg1_1__Reg1_2
2323 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2324 // Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1
2325 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
2326 // Convert__GPRPairRV321_0__regX0_Pair__Reg1_1
2327 { CVT_95_addRegOperands, 1, CVT_regX0_Pair, 0, CVT_95_Reg, 2, CVT_Done },
2328 // Convert__Reg1_0__GPRPairRV321_1__UImm41_2
2329 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2330 // Convert__Reg1_0__GPRPairRV321_1__UImm51_2
2331 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2332 // Convert__Reg1_0__GPRPairRV321_1__imm_95_0
2333 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2334 // Convert__Reg1_0__GPRPairRV321_1__imm_95_8
2335 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_8, 0, CVT_Done },
2336 // Convert__Reg1_0__GPRPairRV321_1__imm_95_16
2337 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_16, 0, CVT_Done },
2338 // Convert__Reg1_2__SImm12Lsb000001_0
2339 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
2340 // Convert__GPRPairRV321_0__GPRPairRV321_1
2341 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
2342 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2
2343 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2344 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2
2345 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2346 // Convert__Reg1_0__Reg1_1__UImm4Plus11_2
2347 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2348 // Convert__Reg1_0__Reg1_1__UImm5Plus11_2
2349 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2350 // Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2
2351 { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2352 // Convert__GPRPairRV321_0__Reg1_1__regX0
2353 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
2354 // Convert__GPRPairRV321_0__regX0__Reg1_1
2355 { CVT_95_addRegOperands, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
2356 // Convert__GPRPairRV321_0__Reg1_1__UImm41_2
2357 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2358 // Convert__GPRPairRV321_0__Reg1_1__UImm51_2
2359 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2360 // Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2
2361 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2362 // Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2
2363 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2364 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1
2365 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2366 // Convert__regX0__Tie0_1_1__UImm5NonZero1_0
2367 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2368 // Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1
2369 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2370 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2
2371 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2372 // Convert__regX0__Tie0_1_1__imm_95_0
2373 { CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
2374 // Convert__UImm5Slist1_0
2375 { CVT_95_addImmOperands, 1, CVT_Done },
2376 // Convert__UImm101_0
2377 { CVT_95_addImmOperands, 1, CVT_Done },
2378 // Convert__RegListS01_0__NegStackAdj1_1
2379 { CVT_95_addRegListOperands, 1, CVT_95_addStackAdjOperands, 2, CVT_Done },
2380 // Convert__Reg1_0__UImm51_1__Reg1_2
2381 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
2382 // Convert__Reg1_0__Tie0_1_1__BareSImm321_1
2383 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2384 // Convert__Reg1_0__Reg1_1__SImm261_2
2385 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2386 // Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2
2387 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2388 // Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2
2389 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2390 // Convert__BareSImm32Lsb01_0
2391 { CVT_95_addImmOperands, 1, CVT_Done },
2392 // Convert__Reg1_0__Reg1_3__SImm261_1
2393 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2394 // Convert__Reg1_0__BareSImm321_1
2395 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2396 // Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1
2397 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
2398 // Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3
2399 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2400 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3
2401 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2402 // Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3
2403 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2404 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2
2405 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2406 // Convert__Reg1_0__Reg1_3__UImm14Lsb001_1
2407 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2408 // Convert__Reg1_0__SImm20LI1_1
2409 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2410 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3
2411 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2412 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3
2413 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2414 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3
2415 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2416 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3
2417 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2418 // Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0
2419 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2420 // Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2
2421 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2422 // Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0
2423 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2424 // Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2
2425 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2426 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2
2427 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2428 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3
2429 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2430 // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3
2431 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2432 // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3
2433 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2434 // Convert__regX0__regX0__imm_95_1536
2435 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_1536, 0, CVT_Done },
2436 // Convert__regX0__Reg1_0__imm_95__MINUS_1280
2437 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1280, 0, CVT_Done },
2438 // Convert__regX0__Reg1_0__imm_95__MINUS_2048
2439 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_2048, 0, CVT_Done },
2440 // Convert__regX0__regX0__imm_95_1792
2441 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_1792, 0, CVT_Done },
2442 // Convert__regX0__Reg1_0__imm_95__MINUS_1792
2443 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1792, 0, CVT_Done },
2444 // Convert__UImm81_0
2445 { CVT_95_addImmOperands, 1, CVT_Done },
2446 // Convert__regX0__Reg1_0__imm_95__MINUS_1536
2447 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1536, 0, CVT_Done },
2448 // Convert__regX0__Reg1_0__imm_95__MINUS_1024
2449 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95__MINUS_1024, 0, CVT_Done },
2450 // Convert__regX0__regX0__UImm101_0
2451 { CVT_regX0, 0, CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2452 // Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3
2453 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2454 // Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3
2455 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2456 // Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3
2457 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2458 // Convert__Reg1_0__Reg1_1__UImm111_2
2459 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2460 // Convert__Reg1_0__Reg1_3__UImm51_1
2461 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2462 // Convert__Reg1_0__Reg1_3__UImm41_1
2463 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2464 // Convert__Reg1_0__Reg1_3__UImm6Lsb01_1
2465 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2466 // Convert__Reg1_0__Reg1_3__UImm5Lsb01_1
2467 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
2468 // Convert__Reg1_0__imm_95_3072__regX0
2469 { CVT_95_Reg, 1, CVT_imm_95_3072, 0, CVT_regX0, 0, CVT_Done },
2470 // Convert__Reg1_0__imm_95_3200__regX0
2471 { CVT_95_Reg, 1, CVT_imm_95_3200, 0, CVT_regX0, 0, CVT_Done },
2472 // Convert__Reg1_0__imm_95_3074__regX0
2473 { CVT_95_Reg, 1, CVT_imm_95_3074, 0, CVT_regX0, 0, CVT_Done },
2474 // Convert__Reg1_0__imm_95_3202__regX0
2475 { CVT_95_Reg, 1, CVT_imm_95_3202, 0, CVT_regX0, 0, CVT_Done },
2476 // Convert__Reg1_0__imm_95_3073__regX0
2477 { CVT_95_Reg, 1, CVT_imm_95_3073, 0, CVT_regX0, 0, CVT_Done },
2478 // Convert__Reg1_0__imm_95_3201__regX0
2479 { CVT_95_Reg, 1, CVT_imm_95_3201, 0, CVT_regX0, 0, CVT_Done },
2480 // Convert__regX0__regX1__imm_95_0
2481 { CVT_regX0, 0, CVT_regX1, 0, CVT_imm_95_0, 0, CVT_Done },
2482 // Convert__Reg1_0__Reg1_1__UImm6Plus11_2
2483 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2484 // Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1
2485 { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2486 // Convert__Reg1_0__Reg1_1__imm_95_1
2487 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
2488 // Convert__regX0
2489 { CVT_regX0, 0, CVT_Done },
2490 // Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3
2491 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2492 // Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3
2493 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2494 // Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3
2495 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2496 // Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3
2497 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2498 // Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3
2499 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2500 // Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3
2501 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2502 // Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3
2503 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2504 // Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3
2505 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
2506 // Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3
2507 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2508 // Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3
2509 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
2510 // Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3
2511 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2512 // Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3
2513 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2514 // Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3
2515 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_Done },
2516 // Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3
2517 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2518 // Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3
2519 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2520 // Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3
2521 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
2522 // Convert__Reg1_0__Reg1_1__XSfmmVType1_2
2523 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2524 // Convert__Reg1_0__Reg1_1__UImm7EqXLen1_2
2525 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2526 // Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5
2527 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2528 // Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6
2529 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
2530 // Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6
2531 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
2532 // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5
2533 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2534 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2535 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2536 // Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3
2537 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
2538 // Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3
2539 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 4, CVT_Done },
2540 // Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3
2541 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2542 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3
2543 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 4, CVT_Done },
2544 // Convert__Reg1_0__Reg1_1__Reg1_1__reg0
2545 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_reg0, 0, CVT_Done },
2546 // Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2
2547 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2548 // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4
2549 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addRegOperands_95_defaultMaskRegOp, 5, CVT_Done },
2550 // Convert__Reg1_0__RVVMaskRegOpOperand1_1
2551 { CVT_95_Reg, 1, CVT_95_addRegOperands_95_defaultMaskRegOp, 2, CVT_Done },
2552 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3
2553 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2554 // Convert__Reg1_0__Reg1_1__SImm51_2
2555 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2556 // Convert__Reg1_0__Reg1_0__Reg1_0
2557 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_Done },
2558 // Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3
2559 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2560 // Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
2561 { CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2562 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3
2563 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2564 // Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4
2565 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addRegOperands_95_defaultMaskRegOp, 5, CVT_Done },
2566 // Convert__Reg1_0__SImm51_1
2567 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2568 // Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3
2569 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2570 // Convert__Reg1_0__Reg1_1__regX0__reg0
2571 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_reg0, 0, CVT_Done },
2572 // Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2
2573 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2574 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0
2575 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_reg0, 0, CVT_Done },
2576 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2
2577 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
2578 // Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3
2579 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
2580 // Convert__Reg1_0__UImm51_1__VTypeI101_2
2581 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2582 // Convert__Reg1_0__Reg1_1__VTypeI111_2
2583 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
2584 // Convert__GPRPairRV321_0__Reg1_1__UImm61_2
2585 { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2586 // Convert__Reg1_0__Reg1_1__YBNDSWImm1_2
2587 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
2588 // Convert__Reg1_0__Reg1_1__imm_95_64
2589 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_64, 0, CVT_Done },
2590 // Convert__Reg1_0__Reg1_1__imm_95_32
2591 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_32, 0, CVT_Done },
2592 // Convert__Reg1_0__Reg1_1__imm_95_255
2593 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_255, 0, CVT_Done },
2594};
2595
2596void RISCVAsmParser::
2597convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2598 const OperandVector &Operands,
2599 const SmallBitVector &OptionalOperandsMask,
2600 ArrayRef<unsigned> DefaultsOffset) {
2601 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2602 const uint8_t *Converter = ConversionTable[Kind];
2603 Inst.setOpcode(Opcode);
2604 for (const uint8_t *p = Converter; *p; p += 2) {
2605 unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
2606 switch (*p) {
2607 default: llvm_unreachable("invalid conversion entry!");
2608 case CVT_Reg:
2609 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2610 break;
2611 case CVT_Tied: {
2612 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
2613 std::begin(TiedAsmOperandTable)) &&
2614 "Tied operand not found");
2615 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
2616 if (TiedResOpnd != (uint8_t)-1)
2617 Inst.addOperand(Inst.getOperand(TiedResOpnd));
2618 break;
2619 }
2620 case CVT_95_addImmOperands:
2621 static_cast<RISCVOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2622 break;
2623 case CVT_95_addRegOperands:
2624 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2625 break;
2626 case CVT_imm_95_0:
2627 Inst.addOperand(MCOperand::createImm(0));
2628 break;
2629 case CVT_95_Reg:
2630 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2631 break;
2632 case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
2633 if (OptionalOperandsMask[*(p + 1)]) {
2634 defaultFRMArgOp()->addFRMArgOperands(Inst, 1);
2635 } else {
2636 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2637 }
2638 break;
2639 case CVT_regX0:
2640 Inst.addOperand(MCOperand::createReg(RISCV::X0));
2641 break;
2642 case CVT_regX1:
2643 Inst.addOperand(MCOperand::createReg(RISCV::X1));
2644 break;
2645 case CVT_regX5:
2646 Inst.addOperand(MCOperand::createReg(RISCV::X5));
2647 break;
2648 case CVT_regX2:
2649 Inst.addOperand(MCOperand::createReg(RISCV::X2));
2650 break;
2651 case CVT_regX3:
2652 Inst.addOperand(MCOperand::createReg(RISCV::X3));
2653 break;
2654 case CVT_regX4:
2655 Inst.addOperand(MCOperand::createReg(RISCV::X4));
2656 break;
2657 case CVT_95_addRegListOperands:
2658 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
2659 break;
2660 case CVT_95_addStackAdjOperands:
2661 static_cast<RISCVOperand &>(*Operands[OpIdx]).addStackAdjOperands(Inst, 1);
2662 break;
2663 case CVT_95_addCSRSystemRegisterOperands:
2664 static_cast<RISCVOperand &>(*Operands[OpIdx]).addCSRSystemRegisterOperands(Inst, 1);
2665 break;
2666 case CVT_95_addRegRegOperands:
2667 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegRegOperands(Inst, 2);
2668 break;
2669 case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
2670 if (OptionalOperandsMask[*(p + 1)]) {
2671 defaultFRMArgLegacyOp()->addFRMArgOperands(Inst, 1);
2672 } else {
2673 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2674 }
2675 break;
2676 case CVT_95_addFRMArgOperands:
2677 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
2678 break;
2679 case CVT_imm_95_15:
2680 Inst.addOperand(MCOperand::createImm(15));
2681 break;
2682 case CVT_95_addFenceArgOperands:
2683 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFenceArgOperands(Inst, 1);
2684 break;
2685 case CVT_95_addFPImmOperands:
2686 static_cast<RISCVOperand &>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
2687 break;
2688 case CVT_imm_95_3:
2689 Inst.addOperand(MCOperand::createImm(3));
2690 break;
2691 case CVT_imm_95_1:
2692 Inst.addOperand(MCOperand::createImm(1));
2693 break;
2694 case CVT_imm_95_2:
2695 Inst.addOperand(MCOperand::createImm(2));
2696 break;
2697 case CVT_regX0_Pair:
2698 Inst.addOperand(MCOperand::createReg(RISCV::X0_Pair));
2699 break;
2700 case CVT_95_addRegOperands_95_defaultMaskRegOp:
2701 if (OptionalOperandsMask[*(p + 1)]) {
2702 defaultMaskRegOp()->addRegOperands(Inst, 1);
2703 } else {
2704 static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2705 }
2706 break;
2707 case CVT_imm_95__MINUS_1:
2708 Inst.addOperand(MCOperand::createImm(-1));
2709 break;
2710 case CVT_95_addSExtImmOperands_LT_8_GT_:
2711 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSExtImmOperands<8>(Inst, 1);
2712 break;
2713 case CVT_95_addSExtImmOperands_LT_10_GT_:
2714 static_cast<RISCVOperand &>(*Operands[OpIdx]).addSExtImmOperands<10>(Inst, 1);
2715 break;
2716 case CVT_imm_95_8:
2717 Inst.addOperand(MCOperand::createImm(8));
2718 break;
2719 case CVT_imm_95_16:
2720 Inst.addOperand(MCOperand::createImm(16));
2721 break;
2722 case CVT_imm_95_1536:
2723 Inst.addOperand(MCOperand::createImm(1536));
2724 break;
2725 case CVT_imm_95__MINUS_1280:
2726 Inst.addOperand(MCOperand::createImm(-1280));
2727 break;
2728 case CVT_imm_95__MINUS_2048:
2729 Inst.addOperand(MCOperand::createImm(-2048));
2730 break;
2731 case CVT_imm_95_1792:
2732 Inst.addOperand(MCOperand::createImm(1792));
2733 break;
2734 case CVT_imm_95__MINUS_1792:
2735 Inst.addOperand(MCOperand::createImm(-1792));
2736 break;
2737 case CVT_imm_95__MINUS_1536:
2738 Inst.addOperand(MCOperand::createImm(-1536));
2739 break;
2740 case CVT_imm_95__MINUS_1024:
2741 Inst.addOperand(MCOperand::createImm(-1024));
2742 break;
2743 case CVT_imm_95_3072:
2744 Inst.addOperand(MCOperand::createImm(3072));
2745 break;
2746 case CVT_imm_95_3200:
2747 Inst.addOperand(MCOperand::createImm(3200));
2748 break;
2749 case CVT_imm_95_3074:
2750 Inst.addOperand(MCOperand::createImm(3074));
2751 break;
2752 case CVT_imm_95_3202:
2753 Inst.addOperand(MCOperand::createImm(3202));
2754 break;
2755 case CVT_imm_95_3073:
2756 Inst.addOperand(MCOperand::createImm(3073));
2757 break;
2758 case CVT_imm_95_3201:
2759 Inst.addOperand(MCOperand::createImm(3201));
2760 break;
2761 case CVT_95_addVTypeIOperands:
2762 static_cast<RISCVOperand &>(*Operands[OpIdx]).addVTypeIOperands(Inst, 1);
2763 break;
2764 case CVT_reg0:
2765 Inst.addOperand(MCOperand::createReg(0));
2766 break;
2767 case CVT_imm_95_64:
2768 Inst.addOperand(MCOperand::createImm(64));
2769 break;
2770 case CVT_imm_95_32:
2771 Inst.addOperand(MCOperand::createImm(32));
2772 break;
2773 case CVT_imm_95_255:
2774 Inst.addOperand(MCOperand::createImm(255));
2775 break;
2776 }
2777 }
2778}
2779
2780void RISCVAsmParser::
2781convertToMapAndConstraints(unsigned Kind,
2782 const OperandVector &Operands) {
2783 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2784 unsigned NumMCOperands = 0;
2785 const uint8_t *Converter = ConversionTable[Kind];
2786 for (const uint8_t *p = Converter; *p; p += 2) {
2787 switch (*p) {
2788 default: llvm_unreachable("invalid conversion entry!");
2789 case CVT_Reg:
2790 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2791 Operands[*(p + 1)]->setConstraint("r");
2792 ++NumMCOperands;
2793 break;
2794 case CVT_Tied:
2795 ++NumMCOperands;
2796 break;
2797 case CVT_95_addImmOperands:
2798 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2799 Operands[*(p + 1)]->setConstraint("m");
2800 NumMCOperands += 1;
2801 break;
2802 case CVT_95_addRegOperands:
2803 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2804 Operands[*(p + 1)]->setConstraint("m");
2805 NumMCOperands += 1;
2806 break;
2807 case CVT_imm_95_0:
2808 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2809 Operands[*(p + 1)]->setConstraint("");
2810 ++NumMCOperands;
2811 break;
2812 case CVT_95_Reg:
2813 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2814 Operands[*(p + 1)]->setConstraint("r");
2815 NumMCOperands += 1;
2816 break;
2817 case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
2818 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2819 Operands[*(p + 1)]->setConstraint("m");
2820 NumMCOperands += 1;
2821 break;
2822 case CVT_regX0:
2823 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2824 Operands[*(p + 1)]->setConstraint("m");
2825 ++NumMCOperands;
2826 break;
2827 case CVT_regX1:
2828 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2829 Operands[*(p + 1)]->setConstraint("m");
2830 ++NumMCOperands;
2831 break;
2832 case CVT_regX5:
2833 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2834 Operands[*(p + 1)]->setConstraint("m");
2835 ++NumMCOperands;
2836 break;
2837 case CVT_regX2:
2838 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2839 Operands[*(p + 1)]->setConstraint("m");
2840 ++NumMCOperands;
2841 break;
2842 case CVT_regX3:
2843 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2844 Operands[*(p + 1)]->setConstraint("m");
2845 ++NumMCOperands;
2846 break;
2847 case CVT_regX4:
2848 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2849 Operands[*(p + 1)]->setConstraint("m");
2850 ++NumMCOperands;
2851 break;
2852 case CVT_95_addRegListOperands:
2853 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2854 Operands[*(p + 1)]->setConstraint("m");
2855 NumMCOperands += 1;
2856 break;
2857 case CVT_95_addStackAdjOperands:
2858 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2859 Operands[*(p + 1)]->setConstraint("m");
2860 NumMCOperands += 1;
2861 break;
2862 case CVT_95_addCSRSystemRegisterOperands:
2863 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2864 Operands[*(p + 1)]->setConstraint("m");
2865 NumMCOperands += 1;
2866 break;
2867 case CVT_95_addRegRegOperands:
2868 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2869 Operands[*(p + 1)]->setConstraint("m");
2870 NumMCOperands += 2;
2871 break;
2872 case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
2873 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2874 Operands[*(p + 1)]->setConstraint("m");
2875 NumMCOperands += 1;
2876 break;
2877 case CVT_95_addFRMArgOperands:
2878 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2879 Operands[*(p + 1)]->setConstraint("m");
2880 NumMCOperands += 1;
2881 break;
2882 case CVT_imm_95_15:
2883 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2884 Operands[*(p + 1)]->setConstraint("");
2885 ++NumMCOperands;
2886 break;
2887 case CVT_95_addFenceArgOperands:
2888 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2889 Operands[*(p + 1)]->setConstraint("m");
2890 NumMCOperands += 1;
2891 break;
2892 case CVT_95_addFPImmOperands:
2893 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2894 Operands[*(p + 1)]->setConstraint("m");
2895 NumMCOperands += 1;
2896 break;
2897 case CVT_imm_95_3:
2898 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2899 Operands[*(p + 1)]->setConstraint("");
2900 ++NumMCOperands;
2901 break;
2902 case CVT_imm_95_1:
2903 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2904 Operands[*(p + 1)]->setConstraint("");
2905 ++NumMCOperands;
2906 break;
2907 case CVT_imm_95_2:
2908 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2909 Operands[*(p + 1)]->setConstraint("");
2910 ++NumMCOperands;
2911 break;
2912 case CVT_regX0_Pair:
2913 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2914 Operands[*(p + 1)]->setConstraint("m");
2915 ++NumMCOperands;
2916 break;
2917 case CVT_95_addRegOperands_95_defaultMaskRegOp:
2918 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2919 Operands[*(p + 1)]->setConstraint("m");
2920 NumMCOperands += 1;
2921 break;
2922 case CVT_imm_95__MINUS_1:
2923 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2924 Operands[*(p + 1)]->setConstraint("");
2925 ++NumMCOperands;
2926 break;
2927 case CVT_95_addSExtImmOperands_LT_8_GT_:
2928 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2929 Operands[*(p + 1)]->setConstraint("m");
2930 NumMCOperands += 1;
2931 break;
2932 case CVT_95_addSExtImmOperands_LT_10_GT_:
2933 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2934 Operands[*(p + 1)]->setConstraint("m");
2935 NumMCOperands += 1;
2936 break;
2937 case CVT_imm_95_8:
2938 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2939 Operands[*(p + 1)]->setConstraint("");
2940 ++NumMCOperands;
2941 break;
2942 case CVT_imm_95_16:
2943 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2944 Operands[*(p + 1)]->setConstraint("");
2945 ++NumMCOperands;
2946 break;
2947 case CVT_imm_95_1536:
2948 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2949 Operands[*(p + 1)]->setConstraint("");
2950 ++NumMCOperands;
2951 break;
2952 case CVT_imm_95__MINUS_1280:
2953 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2954 Operands[*(p + 1)]->setConstraint("");
2955 ++NumMCOperands;
2956 break;
2957 case CVT_imm_95__MINUS_2048:
2958 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2959 Operands[*(p + 1)]->setConstraint("");
2960 ++NumMCOperands;
2961 break;
2962 case CVT_imm_95_1792:
2963 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2964 Operands[*(p + 1)]->setConstraint("");
2965 ++NumMCOperands;
2966 break;
2967 case CVT_imm_95__MINUS_1792:
2968 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2969 Operands[*(p + 1)]->setConstraint("");
2970 ++NumMCOperands;
2971 break;
2972 case CVT_imm_95__MINUS_1536:
2973 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2974 Operands[*(p + 1)]->setConstraint("");
2975 ++NumMCOperands;
2976 break;
2977 case CVT_imm_95__MINUS_1024:
2978 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2979 Operands[*(p + 1)]->setConstraint("");
2980 ++NumMCOperands;
2981 break;
2982 case CVT_imm_95_3072:
2983 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2984 Operands[*(p + 1)]->setConstraint("");
2985 ++NumMCOperands;
2986 break;
2987 case CVT_imm_95_3200:
2988 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2989 Operands[*(p + 1)]->setConstraint("");
2990 ++NumMCOperands;
2991 break;
2992 case CVT_imm_95_3074:
2993 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2994 Operands[*(p + 1)]->setConstraint("");
2995 ++NumMCOperands;
2996 break;
2997 case CVT_imm_95_3202:
2998 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2999 Operands[*(p + 1)]->setConstraint("");
3000 ++NumMCOperands;
3001 break;
3002 case CVT_imm_95_3073:
3003 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3004 Operands[*(p + 1)]->setConstraint("");
3005 ++NumMCOperands;
3006 break;
3007 case CVT_imm_95_3201:
3008 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3009 Operands[*(p + 1)]->setConstraint("");
3010 ++NumMCOperands;
3011 break;
3012 case CVT_95_addVTypeIOperands:
3013 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3014 Operands[*(p + 1)]->setConstraint("m");
3015 NumMCOperands += 1;
3016 break;
3017 case CVT_reg0:
3018 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3019 Operands[*(p + 1)]->setConstraint("m");
3020 ++NumMCOperands;
3021 break;
3022 case CVT_imm_95_64:
3023 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3024 Operands[*(p + 1)]->setConstraint("");
3025 ++NumMCOperands;
3026 break;
3027 case CVT_imm_95_32:
3028 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3029 Operands[*(p + 1)]->setConstraint("");
3030 ++NumMCOperands;
3031 break;
3032 case CVT_imm_95_255:
3033 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3034 Operands[*(p + 1)]->setConstraint("");
3035 ++NumMCOperands;
3036 break;
3037 }
3038 }
3039}
3040
3041namespace {
3042
3043/// MatchClassKind - The kinds of classes which participate in
3044/// instruction matching.
3045enum MatchClassKind {
3046 InvalidMatchClass = 0,
3047 OptionalMatchClass = 1,
3048 MCK__40_, // '('
3049 MCK__41_, // ')'
3050 MCK_LAST_TOKEN = MCK__41_,
3051 MCK_Reg142, // derived register class
3052 MCK_Reg139, // derived register class
3053 MCK_Reg136, // derived register class
3054 MCK_Reg133, // derived register class
3055 MCK_Reg130, // derived register class
3056 MCK_Reg127, // derived register class
3057 MCK_Reg124, // derived register class
3058 MCK_Reg121, // derived register class
3059 MCK_Reg118, // derived register class
3060 MCK_Reg115, // derived register class
3061 MCK_Reg112, // derived register class
3062 MCK_Reg98, // derived register class
3063 MCK_Reg95, // derived register class
3064 MCK_Reg92, // derived register class
3065 MCK_Reg73, // derived register class
3066 MCK_Reg68, // derived register class
3067 MCK_Reg65, // derived register class
3068 MCK_Reg62, // derived register class
3069 MCK_Reg59, // derived register class
3070 MCK_Reg54, // derived register class
3071 MCK_Reg45, // derived register class
3072 MCK_Reg44, // derived register class
3073 MCK_Reg38, // derived register class
3074 MCK_Reg33, // derived register class
3075 MCK_GPRX0, // register class 'GPRX0'
3076 MCK_GPRX1, // register class 'GPRX1'
3077 MCK_GPRX5, // register class 'GPRX5'
3078 MCK_GPRX7, // register class 'GPRX7'
3079 MCK_MR0, // register class 'MR0'
3080 MCK_SP, // register class 'SP'
3081 MCK_VMV0, // register class 'VMV0'
3082 MCK_anonymous_14630, // register class 'anonymous_14630'
3083 MCK_Reg55, // derived register class
3084 MCK_Reg43, // derived register class
3085 MCK_Reg29, // derived register class
3086 MCK_GPRX1X5, // register class 'GPRX1X5'
3087 MCK_Reg78, // derived register class
3088 MCK_VCSR, // register class 'VCSR'
3089 MCK_VRM8NoV0, // register class 'VRM8NoV0'
3090 MCK_Reg77, // derived register class
3091 MCK_GPRPairC, // register class 'GPRPairC'
3092 MCK_TRM4, // register class 'TRM4'
3093 MCK_VRM8, // register class 'VRM8'
3094 MCK_Reg79, // derived register class
3095 MCK_Reg80, // derived register class
3096 MCK_Reg71, // derived register class
3097 MCK_Reg58, // derived register class
3098 MCK_Reg32, // derived register class
3099 MCK_VRN2M4NoV0, // register class 'VRN2M4NoV0'
3100 MCK_Reg72, // derived register class
3101 MCK_VRM4NoV0, // register class 'VRM4NoV0'
3102 MCK_VRN2M4, // register class 'VRN2M4'
3103 MCK_Reg107, // derived register class
3104 MCK_Reg88, // derived register class
3105 MCK_Reg57, // derived register class
3106 MCK_Reg56, // derived register class
3107 MCK_FPR16C, // register class 'FPR16C'
3108 MCK_FPR32C, // register class 'FPR32C'
3109 MCK_FPR64C, // register class 'FPR64C'
3110 MCK_GPRC, // register class 'GPRC'
3111 MCK_GPRF16C, // register class 'GPRF16C'
3112 MCK_GPRF32C, // register class 'GPRF32C'
3113 MCK_MR, // register class 'MR'
3114 MCK_SR07, // register class 'SR07'
3115 MCK_TRM2, // register class 'TRM2'
3116 MCK_VRM4, // register class 'VRM4'
3117 MCK_Reg75, // derived register class
3118 MCK_Reg76, // derived register class
3119 MCK_Reg69, // derived register class
3120 MCK_Reg52, // derived register class
3121 MCK_Reg26, // derived register class
3122 MCK_VRN4M2NoV0, // register class 'VRN4M2NoV0'
3123 MCK_Reg70, // derived register class
3124 MCK_Reg66, // derived register class
3125 MCK_Reg53, // derived register class
3126 MCK_Reg48, // derived register class
3127 MCK_Reg22, // derived register class
3128 MCK_GPRTCNonX7, // register class 'GPRTCNonX7'
3129 MCK_VRN3M2NoV0, // register class 'VRN3M2NoV0'
3130 MCK_VRN4M2, // register class 'VRN4M2'
3131 MCK_Reg67, // derived register class
3132 MCK_Reg63, // derived register class
3133 MCK_Reg49, // derived register class
3134 MCK_GPRTC, // register class 'GPRTC'
3135 MCK_VRN2M2NoV0, // register class 'VRN2M2NoV0'
3136 MCK_VRN3M2, // register class 'VRN3M2'
3137 MCK_Reg61, // derived register class
3138 MCK_GPRPairNoX0, // register class 'GPRPairNoX0'
3139 MCK_VRM2NoV0, // register class 'VRM2NoV0'
3140 MCK_VRN2M2, // register class 'VRN2M2'
3141 MCK_GPRPair, // register class 'GPRPair'
3142 MCK_TR, // register class 'TR'
3143 MCK_VRM2, // register class 'VRM2'
3144 MCK_Reg50, // derived register class
3145 MCK_Reg24, // derived register class
3146 MCK_VRN8M1NoV0, // register class 'VRN8M1NoV0'
3147 MCK_Reg51, // derived register class
3148 MCK_Reg46, // derived register class
3149 MCK_Reg20, // derived register class
3150 MCK_GPRJALRNonX7, // register class 'GPRJALRNonX7'
3151 MCK_VRN7M1NoV0, // register class 'VRN7M1NoV0'
3152 MCK_VRN8M1, // register class 'VRN8M1'
3153 MCK_Reg47, // derived register class
3154 MCK_GPRJALR, // register class 'GPRJALR'
3155 MCK_VRN6M1NoV0, // register class 'VRN6M1NoV0'
3156 MCK_VRN7M1, // register class 'VRN7M1'
3157 MCK_VRN5M1NoV0, // register class 'VRN5M1NoV0'
3158 MCK_VRN6M1, // register class 'VRN6M1'
3159 MCK_VRN4M1NoV0, // register class 'VRN4M1NoV0'
3160 MCK_VRN5M1, // register class 'VRN5M1'
3161 MCK_Reg41, // derived register class
3162 MCK_Reg15, // derived register class
3163 MCK_VRN3M1NoV0, // register class 'VRN3M1NoV0'
3164 MCK_VRN4M1, // register class 'VRN4M1'
3165 MCK_Reg42, // derived register class
3166 MCK_Reg39, // derived register class
3167 MCK_Reg36, // derived register class
3168 MCK_Reg13, // derived register class
3169 MCK_Reg10, // derived register class
3170 MCK_GPRNoX0X2, // register class 'GPRNoX0X2'
3171 MCK_VRN2M1NoV0, // register class 'VRN2M1NoV0'
3172 MCK_VRN3M1, // register class 'VRN3M1'
3173 MCK_Reg40, // derived register class
3174 MCK_Reg37, // derived register class
3175 MCK_Reg34, // derived register class
3176 MCK_GPRF16NoX0, // register class 'GPRF16NoX0'
3177 MCK_GPRF32NoX0, // register class 'GPRF32NoX0'
3178 MCK_GPRNoX0, // register class 'GPRNoX0'
3179 MCK_GPRNoX2, // register class 'GPRNoX2'
3180 MCK_GPRNoX31, // register class 'GPRNoX31'
3181 MCK_VRN2M1, // register class 'VRN2M1'
3182 MCK_VRNoV0, // register class 'VRNoV0,ZZZ_VMNoV0,ZZZ_VRMF2NoV0,ZZZ_VRMF4NoV0,ZZZ_VRMF8NoV0'
3183 MCK_FPR128, // register class 'FPR128'
3184 MCK_FPR16, // register class 'FPR16'
3185 MCK_FPR256, // register class 'FPR256'
3186 MCK_FPR32, // register class 'FPR32'
3187 MCK_FPR64, // register class 'FPR64'
3188 MCK_GPR, // register class 'GPR'
3189 MCK_GPRF16, // register class 'GPRF16'
3190 MCK_GPRF32, // register class 'GPRF32'
3191 MCK_VR, // register class 'VR,ZZZ_VM,ZZZ_VRMF2,ZZZ_VRMF4,ZZZ_VRMF8'
3192 MCK_YGPR, // register class 'YGPR'
3193 MCK_GPRAll, // register class 'GPRAll'
3194 MCK_LAST_REGISTER = MCK_GPRAll,
3195 MCK_AnyRegCOperand, // user defined class 'AnyRegCOperand'
3196 MCK_AnyRegOperand, // user defined class 'AnyRegOperand'
3197 MCK_BareSymbol, // user defined class 'BareSymbol'
3198 MCK_BareSymbolQC_E_LI, // user defined class 'BareSymbolQC_E_LI'
3199 MCK_CLUIImm, // user defined class 'CLUIImmAsmOperand'
3200 MCK_CSRSystemRegister, // user defined class 'CSRSystemRegister'
3201 MCK_RegReg, // user defined class 'CVrrAsmOperand'
3202 MCK_CallSymbol, // user defined class 'CallSymbol'
3203 MCK_FRMArg, // user defined class 'FRMArg'
3204 MCK_FRMArgLegacy, // user defined class 'FRMArgLegacy'
3205 MCK_FenceArg, // user defined class 'FenceArg'
3206 MCK_GPRAsFPR16, // user defined class 'GPRAsFPR16'
3207 MCK_GPRAsFPR32, // user defined class 'GPRAsFPR32'
3208 MCK_GPRF64AsFPR, // user defined class 'GPRF64AsFPR'
3209 MCK_GPRPairAsFPR, // user defined class 'GPRPairAsFPR'
3210 MCK_GPRPairCRV32, // user defined class 'GPRPairCRV32Operand'
3211 MCK_GPRPairNoX0RV32, // user defined class 'GPRPairNoX0RV32Operand'
3212 MCK_GPRPairRV32, // user defined class 'GPRPairRV32Operand'
3213 MCK_GPRPairRV64, // user defined class 'GPRPairRV64Operand'
3214 MCK_Imm, // user defined class 'ImmAsmOperand'
3215 MCK_ImmFour, // user defined class 'ImmFourAsmOperand'
3216 MCK_ImmThree, // user defined class 'ImmThreeAsmOperand'
3217 MCK_ImmZero, // user defined class 'ImmZeroAsmOperand'
3218 MCK_InsnCDirectiveOpcode, // user defined class 'InsnCDirectiveOpcode'
3219 MCK_InsnDirectiveOpcode, // user defined class 'InsnDirectiveOpcode'
3220 MCK_LoadFPImm, // user defined class 'LoadFPImmOperand'
3221 MCK_NegStackAdj, // user defined class 'NegStackAdjAsmOperand'
3222 MCK_PseudoJumpSymbol, // user defined class 'PseudoJumpSymbol'
3223 MCK_QCAccessSymbol, // user defined class 'QCAccessSymbol'
3224 MCK_RTZArg, // user defined class 'RTZArg'
3225 MCK_RegList, // user defined class 'RegListAsmOperand'
3226 MCK_RegListS0, // user defined class 'RegListS0AsmOperand'
3227 MCK_RnumArg, // user defined class 'RnumArg'
3228 MCK_SImm10PLI_H, // user defined class 'SImm10PLI_HAsmOperand'
3229 MCK_SImm10PLI_W, // user defined class 'SImm10PLI_WAsmOperand'
3230 MCK_SImm10PLUI, // user defined class 'SImm10PLUIAsmOperand'
3231 MCK_SImm8PLI_B, // user defined class 'SImm8PLI_BAsmOperand'
3232 MCK_BareSImm21Lsb0, // user defined class 'Simm21Lsb0JALAsmOperand'
3233 MCK_StackAdj, // user defined class 'StackAdjAsmOperand'
3234 MCK_TLSDESCCallSymbol, // user defined class 'TLSDESCCallSymbol'
3235 MCK_TPRelAddSymbol, // user defined class 'TPRelAddSymbol'
3236 MCK_TileLambda, // user defined class 'TileLambdaAsmOperand'
3237 MCK_UImmLog2XLen, // user defined class 'UImmLog2XLenAsmOperand'
3238 MCK_UImmLog2XLenNonZero, // user defined class 'UImmLog2XLenNonZeroAsmOperand'
3239 MCK_RVVMaskRegOpOperand, // user defined class 'VMaskAsmOperand'
3240 MCK_RVVMaskCarryInRegOpOperand, // user defined class 'VMaskCarryInAsmOperand'
3241 MCK_RVVScaleRegOpOperand, // user defined class 'VScaleAsmOperand'
3242 MCK_XSfmmVType, // user defined class 'XSfmmVTypeAsmOperand'
3243 MCK_YBNDSWImm, // user defined class 'YBNDSWImmOperand'
3244 MCK_ZeroOffsetMemOpOperand, // user defined class 'ZeroOffsetMemOpOperand'
3245 MCK_UImm1, // user defined class 'anonymous_15021'
3246 MCK_UImm2, // user defined class 'anonymous_15022'
3247 MCK_UImm3, // user defined class 'anonymous_15023'
3248 MCK_UImm4, // user defined class 'anonymous_15024'
3249 MCK_UImm5, // user defined class 'anonymous_15025'
3250 MCK_UImm6, // user defined class 'anonymous_15026'
3251 MCK_UImm7, // user defined class 'anonymous_15027'
3252 MCK_UImm8, // user defined class 'anonymous_15028'
3253 MCK_UImm16, // user defined class 'anonymous_15029'
3254 MCK_UImm32, // user defined class 'anonymous_15030'
3255 MCK_UImm48, // user defined class 'anonymous_15031'
3256 MCK_UImm64, // user defined class 'anonymous_15032'
3257 MCK_SImm12, // user defined class 'anonymous_15033'
3258 MCK_SImm12LO, // user defined class 'anonymous_15034'
3259 MCK_BareSImm13Lsb0, // user defined class 'anonymous_15035'
3260 MCK_UImm20, // user defined class 'anonymous_15036'
3261 MCK_UImm20LUI, // user defined class 'anonymous_15037'
3262 MCK_UImm20AUIPC, // user defined class 'anonymous_15038'
3263 MCK_ImmXLenLI, // user defined class 'anonymous_15039'
3264 MCK_ImmXLenLI_Restricted, // user defined class 'anonymous_15040'
3265 MCK_SImm12Lsb00000, // user defined class 'anonymous_16014'
3266 MCK_Imm5Zibi, // user defined class 'anonymous_16026'
3267 MCK_VTypeI10, // user defined class 'anonymous_16717'
3268 MCK_VTypeI11, // user defined class 'anonymous_16718'
3269 MCK_SImm5, // user defined class 'anonymous_16719'
3270 MCK_SImm5Plus1, // user defined class 'anonymous_16720'
3271 MCK_UImm4Plus1, // user defined class 'anonymous_61279'
3272 MCK_UImm5Plus1, // user defined class 'anonymous_61280'
3273 MCK_UImm6Plus1, // user defined class 'anonymous_61281'
3274 MCK_SImm6, // user defined class 'anonymous_61732'
3275 MCK_SImm6NonZero, // user defined class 'anonymous_61733'
3276 MCK_UImm7Lsb00, // user defined class 'anonymous_61734'
3277 MCK_UImm8Lsb00, // user defined class 'anonymous_61735'
3278 MCK_UImm8Lsb000, // user defined class 'anonymous_61736'
3279 MCK_BareSImm9Lsb0, // user defined class 'anonymous_61737'
3280 MCK_UImm9Lsb000, // user defined class 'anonymous_61738'
3281 MCK_UImm10Lsb00NonZero, // user defined class 'anonymous_61739'
3282 MCK_SImm10Lsb0000NonZero, // user defined class 'anonymous_61740'
3283 MCK_BareSImm12Lsb0, // user defined class 'anonymous_61741'
3284 MCK_UImm2Lsb0, // user defined class 'anonymous_61833'
3285 MCK_UImm8GE32, // user defined class 'anonymous_61834'
3286 MCK_UImm7EqXLen, // user defined class 'anonymous_61872'
3287 MCK_UImm5Lsb0, // user defined class 'anonymous_63745'
3288 MCK_UImm6Lsb0, // user defined class 'anonymous_63746'
3289 MCK_UImm5NonZero, // user defined class 'anonymous_63764'
3290 MCK_UImm5GT3, // user defined class 'anonymous_63765'
3291 MCK_UImm5GE6Plus1, // user defined class 'anonymous_63766'
3292 MCK_UImm5Slist, // user defined class 'anonymous_63767'
3293 MCK_UImm10, // user defined class 'anonymous_63768'
3294 MCK_UImm11, // user defined class 'anonymous_63769'
3295 MCK_UImm14Lsb00, // user defined class 'anonymous_63770'
3296 MCK_UImm16NonZero, // user defined class 'anonymous_63771'
3297 MCK_SImm5NonZero, // user defined class 'anonymous_63772'
3298 MCK_SImm11, // user defined class 'anonymous_63773'
3299 MCK_SImm16, // user defined class 'anonymous_63774'
3300 MCK_SImm16NonZero, // user defined class 'anonymous_63775'
3301 MCK_SImm20LI, // user defined class 'anonymous_63776'
3302 MCK_SImm26, // user defined class 'anonymous_63777'
3303 MCK_BareSImm32, // user defined class 'anonymous_63778'
3304 MCK_BareSImm32Lsb0, // user defined class 'anonymous_63779'
3305 MCK_UImm7Lsb000, // user defined class 'anonymous_64038'
3306 MCK_UImm9, // user defined class 'anonymous_64039'
3307 MCK_BareSImm11Lsb0, // user defined class 'anonymous_64050'
3308 MCK_SImm18, // user defined class 'anonymous_64051'
3309 MCK_SImm18Lsb0, // user defined class 'anonymous_64052'
3310 MCK_SImm19Lsb00, // user defined class 'anonymous_64053'
3311 MCK_SImm20Lsb000, // user defined class 'anonymous_64054'
3312 MCK_SImm10, // user defined class 'anonymous_64323'
3313 NumMatchClassKinds
3314};
3315
3316} // end anonymous namespace
3317
3318static const char *getMatchKindDiag(RISCVAsmParser::RISCVMatchResultTy MatchResult) {
3319 switch (MatchResult) {
3320 case RISCVAsmParser::Match_InvalidRegClassGPRX1:
3321 return "register must be ra (x1)";
3322 case RISCVAsmParser::Match_InvalidRegClassGPRX5:
3323 return "register must be t0 (x5)";
3324 case RISCVAsmParser::Match_InvalidRegClassSP:
3325 return "register must be sp (x2)";
3326 case RISCVAsmParser::Match_InvalidRegClassGPRX1X5:
3327 return "register must be ra or t0 (x1 or x5)";
3328 case RISCVAsmParser::Match_GPRC:
3329 return "register must be a GPR from x8 to x15";
3330 case RISCVAsmParser::Match_InvalidRegClassGPRNoX0X2:
3331 return "register must be a GPR excluding zero (x0) and sp (x2)";
3332 case RISCVAsmParser::Match_InvalidRegClassGPRNoX0:
3333 return "register must be a GPR excluding zero (x0)";
3334 case RISCVAsmParser::Match_InvalidRegClassGPRNoX2:
3335 return "register must be a GPR excluding sp (x2)";
3336 case RISCVAsmParser::Match_InvalidRegClassGPRX31:
3337 return "register must be a GPR excluding t6 (x31)";
3338 case RISCVAsmParser::Match_InvalidBareSymbol:
3339 return "operand must be a bare symbol name";
3340 case RISCVAsmParser::Match_InvalidCallSymbol:
3341 return "operand must be a bare symbol name";
3342 case RISCVAsmParser::Match_InvalidImmFour:
3343 return "operand must be constant 4";
3344 case RISCVAsmParser::Match_InvalidImmThree:
3345 return "operand must be constant 3";
3346 case RISCVAsmParser::Match_InvalidImmZero:
3347 return "immediate must be zero";
3348 case RISCVAsmParser::Match_InvalidLoadFPImm:
3349 return "operand must be a valid floating-point constant";
3350 case RISCVAsmParser::Match_InvalidPseudoJumpSymbol:
3351 return "operand must be a valid jump target";
3352 case RISCVAsmParser::Match_InvalidQCAccessSymbol:
3353 return "operand must be a symbol with a %qc.access specifier";
3354 case RISCVAsmParser::Match_InvalidRTZArg:
3355 return "operand must be 'rtz' floating-point rounding mode";
3356 case RISCVAsmParser::Match_InvalidRegList:
3357 return "operand must be {ra [, s0[-sN]]} or {x1 [, x8[-x9][, x18[-xN]]]}";
3358 case RISCVAsmParser::Match_InvalidRegListS0:
3359 return "operand must be {ra, s0[-sN]} or {x1, x8[-x9][, x18[-xN]]}";
3360 case RISCVAsmParser::Match_InvalidTLSDESCCallSymbol:
3361 return "operand must be a symbol with %tlsdesc_call specifier";
3362 case RISCVAsmParser::Match_InvalidTPRelAddSymbol:
3363 return "operand must be a symbol with %tprel_add specifier";
3364 case RISCVAsmParser::Match_InvalidTileLambda:
3365 return "operand must be L1, L2, L4, L8, L16, L32, or L64";
3366 case RISCVAsmParser::Match_InvalidVMaskRegister:
3367 return "operand must be v0.t";
3368 case RISCVAsmParser::Match_InvalidVMaskCarryInRegister:
3369 return "operand must be v0";
3370 case RISCVAsmParser::Match_InvalidVScaleRegister:
3371 return "operand must be v0.scale";
3372 default:
3373 return nullptr;
3374 }
3375}
3376
3377static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
3378 switch (RegisterClass) {
3379 case MCK_GPRX1:
3380 return RISCVAsmParser::Match_InvalidRegClassGPRX1;
3381 case MCK_GPRX5:
3382 return RISCVAsmParser::Match_InvalidRegClassGPRX5;
3383 case MCK_SP:
3384 return RISCVAsmParser::Match_InvalidRegClassSP;
3385 case MCK_GPRX1X5:
3386 return RISCVAsmParser::Match_InvalidRegClassGPRX1X5;
3387 case MCK_GPRC:
3388 return RISCVAsmParser::Match_GPRC;
3389 case MCK_GPRNoX0X2:
3390 return RISCVAsmParser::Match_InvalidRegClassGPRNoX0X2;
3391 case MCK_GPRNoX0:
3392 return RISCVAsmParser::Match_InvalidRegClassGPRNoX0;
3393 case MCK_GPRNoX2:
3394 return RISCVAsmParser::Match_InvalidRegClassGPRNoX2;
3395 case MCK_GPRNoX31:
3396 return RISCVAsmParser::Match_InvalidRegClassGPRX31;
3397 default:
3398 return MCTargetAsmParser::Match_InvalidOperand;
3399 }
3400}
3401
3402static MatchClassKind matchTokenString(StringRef Name) {
3403 switch (Name.size()) {
3404 default: break;
3405 case 1: // 2 strings to match.
3406 switch (Name[0]) {
3407 default: break;
3408 case '(': // 1 string to match.
3409 return MCK__40_; // "("
3410 case ')': // 1 string to match.
3411 return MCK__41_; // ")"
3412 }
3413 break;
3414 }
3415 return InvalidMatchClass;
3416}
3417
3418/// isSubclass - Compute whether \p A is a subclass of \p B.
3419static bool isSubclass(MatchClassKind A, MatchClassKind B) {
3420 if (A == B)
3421 return true;
3422
3423 [[maybe_unused]] static constexpr struct {
3424 uint32_t Offset;
3425 uint16_t Start;
3426 uint16_t Length;
3427 } Table[] = {
3428 {0, 0, 0},
3429 {0, 0, 0},
3430 {0, 0, 0},
3431 {0, 0, 0},
3432 {0, 105, 1},
3433 {1, 109, 1},
3434 {2, 111, 1},
3435 {3, 113, 1},
3436 {4, 83, 1},
3437 {5, 117, 1},
3438 {6, 89, 1},
3439 {7, 125, 1},
3440 {8, 55, 1},
3441 {9, 93, 1},
3442 {10, 134, 1},
3443 {11, 46, 1},
3444 {12, 69, 1},
3445 {13, 96, 1},
3446 {14, 43, 52},
3447 {66, 49, 46},
3448 {112, 77, 18},
3449 {130, 85, 10},
3450 {140, 90, 5},
3451 {145, 79, 67},
3452 {212, 37, 109},
3453 {321, 119, 27},
3454 {348, 37, 109},
3455 {457, 120, 26},
3456 {483, 122, 25},
3457 {508, 39, 108},
3458 {616, 39, 108},
3459 {724, 80, 67},
3460 {791, 66, 1},
3461 {792, 121, 26},
3462 {818, 144, 1},
3463 {819, 0, 0},
3464 {819, 58, 88},
3465 {907, 114, 32},
3466 {939, 63, 84},
3467 {1023, 115, 32},
3468 {1055, 44, 51},
3469 {1106, 0, 0},
3470 {1106, 46, 1},
3471 {1107, 70, 25},
3472 {1132, 70, 25},
3473 {1157, 68, 28},
3474 {1185, 0, 0},
3475 {1185, 48, 47},
3476 {1232, 53, 42},
3477 {1274, 53, 42},
3478 {1316, 59, 87},
3479 {1403, 63, 84},
3480 {1487, 55, 1},
3481 {1488, 76, 19},
3482 {1507, 69, 1},
3483 {1508, 0, 0},
3484 {1508, 138, 1},
3485 {1509, 136, 1},
3486 {1510, 97, 49},
3487 {1559, 97, 49},
3488 {1608, 137, 1},
3489 {1609, 139, 1},
3490 {1610, 140, 1},
3491 {1611, 98, 49},
3492 {1660, 129, 14},
3493 {1674, 130, 14},
3494 {1688, 0, 0},
3495 {1688, 98, 49},
3496 {1737, 95, 1},
3497 {1738, 0, 0},
3498 {1738, 71, 24},
3499 {1762, 76, 19},
3500 {1781, 76, 19},
3501 {1800, 78, 68},
3502 {1868, 80, 67},
3503 {1935, 83, 1},
3504 {1936, 84, 11},
3505 {1947, 84, 11},
3506 {1958, 86, 60},
3507 {2018, 86, 60},
3508 {2078, 87, 60},
3509 {2138, 87, 60},
3510 {2198, 89, 1},
3511 {2199, 0, 0},
3512 {2199, 90, 5},
3513 {2204, 91, 4},
3514 {2208, 106, 40},
3515 {2248, 107, 40},
3516 {2288, 93, 1},
3517 {2289, 0, 0},
3518 {2289, 94, 1},
3519 {2290, 94, 1},
3520 {2291, 96, 1},
3521 {2292, 0, 0},
3522 {2292, 0, 0},
3523 {2292, 0, 0},
3524 {2292, 0, 0},
3525 {2292, 100, 46},
3526 {2338, 102, 45},
3527 {2383, 105, 1},
3528 {2384, 106, 40},
3529 {2424, 106, 40},
3530 {2464, 107, 40},
3531 {2504, 107, 40},
3532 {2544, 109, 1},
3533 {2545, 0, 0},
3534 {2545, 118, 28},
3535 {2573, 123, 24},
3536 {2597, 111, 1},
3537 {2598, 0, 0},
3538 {2598, 113, 1},
3539 {2599, 0, 0},
3540 {2599, 117, 1},
3541 {2600, 0, 0},
3542 {2600, 118, 28},
3543 {2628, 121, 26},
3544 {2654, 125, 1},
3545 {2655, 0, 0},
3546 {2655, 126, 20},
3547 {2675, 126, 20},
3548 {2695, 127, 19},
3549 {2714, 131, 16},
3550 {2730, 132, 15},
3551 {2745, 131, 16},
3552 {2761, 134, 1},
3553 {2762, 0, 0},
3554 {2762, 145, 1},
3555 {2763, 145, 1},
3556 {2764, 145, 1},
3557 {2765, 142, 1},
3558 {2766, 143, 1},
3559 {2767, 141, 6},
3560 {2773, 141, 6},
3561 {2779, 141, 6},
3562 {2785, 0, 0},
3563 {2785, 144, 1},
3564 {2786, 0, 0},
3565 {2786, 0, 0},
3566 {2786, 0, 0},
3567 {2786, 0, 0},
3568 {2786, 0, 0},
3569 {2786, 146, 1},
3570 {2787, 0, 0},
3571 {2787, 0, 0},
3572 {2787, 0, 0},
3573 {2787, 0, 0},
3574 {2787, 0, 0},
3575 {2787, 0, 0},
3576 {2787, 0, 0},
3577 {2787, 0, 0},
3578 {2787, 0, 0},
3579 {2787, 0, 0},
3580 {2787, 0, 0},
3581 {2787, 0, 0},
3582 {2787, 0, 0},
3583 {2787, 1, 1},
3584 {2788, 1, 1},
3585 {2789, 0, 0},
3586 {2789, 0, 0},
3587 {2789, 0, 0},
3588 {2789, 0, 0},
3589 {2789, 0, 0},
3590 {2789, 0, 0},
3591 {2789, 0, 0},
3592 {2789, 0, 0},
3593 {2789, 0, 0},
3594 {2789, 0, 0},
3595 {2789, 0, 0},
3596 {2789, 0, 0},
3597 {2789, 0, 0},
3598 {2789, 0, 0},
3599 {2789, 0, 0},
3600 {2789, 0, 0},
3601 {2789, 0, 0},
3602 {2789, 0, 0},
3603 {2789, 0, 0},
3604 {2789, 0, 0},
3605 {2789, 0, 0},
3606 {2789, 0, 0},
3607 {2789, 0, 0},
3608 {2789, 0, 0},
3609 {2789, 0, 0},
3610 {2789, 0, 0},
3611 {2789, 0, 0},
3612 {2789, 0, 0},
3613 {2789, 0, 0},
3614 {2789, 0, 0},
3615 {2789, 0, 0},
3616 {2789, 0, 0},
3617 {2789, 0, 0},
3618 {2789, 0, 0},
3619 {2789, 1, 1},
3620 {2790, 0, 0},
3621 {2790, 0, 0},
3622 {2790, 0, 0},
3623 {2790, 0, 0},
3624 {2790, 0, 0},
3625 {2790, 0, 0},
3626 {2790, 0, 0},
3627 {2790, 0, 0},
3628 {2790, 0, 0},
3629 {2790, 0, 0},
3630 {2790, 0, 0},
3631 {2790, 0, 0},
3632 {2790, 0, 0},
3633 {2790, 0, 0},
3634 {2790, 0, 0},
3635 {2790, 0, 0},
3636 {2790, 0, 0},
3637 {2790, 0, 0},
3638 {2790, 0, 0},
3639 {2790, 0, 0},
3640 {2790, 0, 0},
3641 {2790, 0, 0},
3642 {2790, 0, 0},
3643 {2790, 0, 0},
3644 {2790, 0, 0},
3645 {2790, 0, 0},
3646 {2790, 0, 0},
3647 {2790, 0, 0},
3648 {2790, 0, 0},
3649 {2790, 0, 0},
3650 {2790, 0, 0},
3651 {2790, 0, 0},
3652 {2790, 0, 0},
3653 {2790, 0, 0},
3654 {2790, 0, 0},
3655 {2790, 0, 0},
3656 {2790, 0, 0},
3657 {2790, 0, 0},
3658 {2790, 0, 0},
3659 {2790, 0, 0},
3660 {2790, 0, 0},
3661 {2790, 0, 0},
3662 {2790, 0, 0},
3663 {2790, 0, 0},
3664 {2790, 0, 0},
3665 {2790, 0, 0},
3666 {2790, 0, 0},
3667 {2790, 0, 0},
3668 {2790, 0, 0},
3669 {2790, 0, 0},
3670 {2790, 0, 0},
3671 {2790, 0, 0},
3672 {2790, 0, 0},
3673 {2790, 0, 0},
3674 {2790, 0, 0},
3675 {2790, 0, 0},
3676 {2790, 0, 0},
3677 {2790, 0, 0},
3678 {2790, 0, 0},
3679 {2790, 0, 0},
3680 {2790, 0, 0},
3681 {2790, 0, 0},
3682 {2790, 0, 0},
3683 {2790, 0, 0},
3684 {2790, 0, 0},
3685 {2790, 0, 0},
3686 {2790, 0, 0},
3687 {2790, 0, 0},
3688 {2790, 0, 0},
3689 {2790, 0, 0},
3690 {2790, 0, 0},
3691 {2790, 0, 0},
3692 {2790, 0, 0},
3693 };
3694
3695 static constexpr uint8_t Data[] = {
3696 0xFF,
3697 0xFF,
3698 0x00,
3699 0x00,
3700 0x00,
3701 0x8E,
3702 0x81,
3703 0x61,
3704 0x46,
3705 0x00,
3706 0x00,
3707 0x62,
3708 0x60,
3709 0x98,
3710 0x81,
3711 0x61,
3712 0x06,
3713 0x19,
3714 0x03,
3715 0x01,
3716 0x80,
3717 0x10,
3718 0x10,
3719 0x07,
3720 0x07,
3721 0x00,
3722 0x18,
3723 0x00,
3724 0x00,
3725 0x00,
3726 0x00,
3727 0x00,
3728 0x00,
3729 0x00,
3730 0x00,
3731 0x00,
3732 0xE2,
3733 0xE0,
3734 0x00,
3735 0x00,
3736 0x03,
3737 0x05,
3738 0x00,
3739 0x18,
3740 0x00,
3741 0x00,
3742 0x00,
3743 0x00,
3744 0x00,
3745 0x00,
3746 0x00,
3747 0x00,
3748 0x00,
3749 0xE2,
3750 0xE0,
3751 0x00,
3752 0x00,
3753 0x03,
3754 0x03,
3755 0x00,
3756 0x0C,
3757 0x60,
3758 0x40,
3759 0x18,
3760 0x00,
3761 0x00,
3762 0x00,
3763 0x00,
3764 0x00,
3765 0x00,
3766 0x00,
3767 0x00,
3768 0x00,
3769 0xC1,
3770 0x01,
3771 0x07,
3772 0x84,
3773 0x01,
3774 0x00,
3775 0x00,
3776 0x00,
3777 0x00,
3778 0x00,
3779 0x00,
3780 0x00,
3781 0x00,
3782 0x10,
3783 0x1C,
3784 0x70,
3785 0x40,
3786 0x18,
3787 0x08,
3788 0x00,
3789 0x84,
3790 0x80,
3791 0xE0,
3792 0x80,
3793 0x03,
3794 0xC2,
3795 0x01,
3796 0x14,
3797 0x10,
3798 0x1E,
3799 0x00,
3800 0x00,
3801 0x00,
3802 0x00,
3803 0x64,
3804 0x08,
3805 0x88,
3806 0x83,
3807 0x03,
3808 0x00,
3809 0x8C,
3810 0x83,
3811 0x03,
3812 0x00,
3813 0x8C,
3814 0x00,
3815 0x00,
3816 0x00,
3817 0x40,
3818 0x8C,
3819 0x80,
3820 0xE0,
3821 0x80,
3822 0x03,
3823 0xC2,
3824 0xE0,
3825 0x80,
3826 0x03,
3827 0xC2,
3828 0x1C,
3829 0x01,
3830 0x00,
3831 0x8E,
3832 0x81,
3833 0x61,
3834 0x3E,
3835 0x06,
3836 0x86,
3837 0x79,
3838 0x0C,
3839 0x0C,
3840 0x33,
3841 0x00,
3842 0x00,
3843 0x00,
3844 0x47,
3845 0x00,
3846 0x80,
3847 0x63,
3848 0x60,
3849 0x98,
3850 0x01,
3851 0x00,
3852 0x84,
3853 0x80,
3854 0x60,
3855 0x06,
3856 0x00,
3857 0x20,
3858 0x06,
3859 0x86,
3860 0x19,
3861 0x00,
3862 0x84,
3863 0x81,
3864 0x00,
3865 0x64,
3866 0x08,
3867 0x88,
3868 0x83,
3869 0x03,
3870 0x00,
3871 0x0C,
3872 0x40,
3873 0x30,
3874 0x08,
3875 0x40,
3876 0x8C,
3877 0x80,
3878 0xE0,
3879 0x80,
3880 0x03,
3881 0xC2,
3882 0x01,
3883 0xC1,
3884 0x7C,
3885 0x86,
3886 0x80,
3887 0x38,
3888 0x38,
3889 0x00,
3890 0xC0,
3891 0x0C,
3892 0x01,
3893 0x71,
3894 0x70,
3895 0x00,
3896 0x80,
3897 0x8F,
3898 0x11,
3899 0x10,
3900 0x1C,
3901 0x70,
3902 0x40,
3903 0x18,
3904 0x00,
3905 0x06,
3906 0x80,
3907 0x31,
3908 0x02,
3909 0x82,
3910 0x03,
3911 0x0E,
3912 0x08,
3913 0x8F,
3914 0x81,
3915 0x61,
3916 0x06,
3917 0x04,
3918 0x73,
3919 0x60,
3920 0x98,
3921 0x03,
3922 0x01,
3923 0xC8,
3924 0x10,
3925 0x10,
3926 0x07,
3927 0x07,
3928 0x00,
3929 0x38,
3930 0x08,
3931 0x40,
3932 0x8C,
3933 0x80,
3934 0xE0,
3935 0x80,
3936 0x03,
3937 0xC2,
3938 0xC1,
3939 0x1C,
3940 0x66,
3941 0x00,
3942 0x10,
3943 0x04,
3944 0x40,
3945 0xC0,
3946 0x00,
3947 0x00,
3948 0x06,
3949 0x00,
3950 0x42,
3951 0x40,
3952 0x1C,
3953 0x1C,
3954 0x00,
3955 0x60,
3956 0x00,
3957 0x20,
3958 0x04,
3959 0x04,
3960 0x07,
3961 0x1C,
3962 0x10,
3963 0x06,
3964 0x00,
3965 0x44,
3966 0x00,
3967 0x40,
3968 0xC0,
3969 0x00,
3970 0xE1,
3971 0x99,
3972 0x01,
3973 0x10,
3974 0x30,
3975 0x00,
3976 0x80,
3977 0x01,
3978 0x00,
3979 0x01,
3980 0x03,
3981 0x84,
3982 0x3F,
3983 0x04,
3984 0xC4,
3985 0xC1,
3986 0x01,
3987 0x00,
3988 0x8E,
3989 0x80,
3990 0xE0,
3991 0x80,
3992 0x03,
3993 0xC2,
3994 0x01,
3995 0x10,
3996 0x30,
3997 0x00,
3998 0x80,
3999 0x01,
4000 0x71,
4001 0x70,
4002 0x00,
4003 0x80,
4004 0x01,
4005 0xC1,
4006 0x01,
4007 0x07,
4008 0x84,
4009 0x01,
4010 0x00,
4011 0x01,
4012 0x03,
4013 0x84,
4014 0x03,
4015 0x06,
4016 0x00,
4017 0x30,
4018 0x60,
4019 0x80,
4020 0xF0,
4021 0x07,
4022 0x07,
4023 0x00,
4024 0x78,
4025 0xC0,
4026 0x01,
4027 0xE1,
4028 0x01,
4029 0x00,
4030 0x2C,
4031 0x00,
4032 0xC0,
4033 0x01,
4034 0x00,
4035 0x16,
4036 0x10,
4037 0x0E,
4038 0x08,
4039 0x07,
4040 0x08,
4041 0xFF,
4042 0x30,
4043 0x0C,
4044 0x3F,
4045 };
4046
4047 auto &Entry = Table[A];
4048 unsigned Idx = B - Entry.Start;
4049 if (Idx >= Entry.Length)
4050 return false;
4051 Idx += Entry.Offset;
4052 return (Data[Idx / 8] >> (Idx % 8)) & 1;
4053}
4054
4055static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
4056 RISCVOperand &Operand = (RISCVOperand &)GOp;
4057 if (Kind == InvalidMatchClass)
4058 return MCTargetAsmParser::Match_InvalidOperand;
4059
4060 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
4061 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
4062 MCTargetAsmParser::Match_Success :
4063 MCTargetAsmParser::Match_InvalidOperand;
4064
4065 switch (Kind) {
4066 default: break;
4067 case MCK_AnyRegCOperand: {
4068 DiagnosticPredicate DP(Operand.isAnyRegC());
4069 if (DP.isMatch())
4070 return MCTargetAsmParser::Match_Success;
4071 break;
4072 }
4073 case MCK_AnyRegOperand: {
4074 DiagnosticPredicate DP(Operand.isAnyReg());
4075 if (DP.isMatch())
4076 return MCTargetAsmParser::Match_Success;
4077 break;
4078 }
4079 case MCK_BareSymbol: {
4080 DiagnosticPredicate DP(Operand.isBareSymbol());
4081 if (DP.isMatch())
4082 return MCTargetAsmParser::Match_Success;
4083 if (DP.isNearMatch())
4084 return RISCVAsmParser::Match_InvalidBareSymbol;
4085 break;
4086 }
4087 case MCK_BareSymbolQC_E_LI: {
4088 DiagnosticPredicate DP(Operand.isBareSymbol());
4089 if (DP.isMatch())
4090 return MCTargetAsmParser::Match_Success;
4091 if (DP.isNearMatch())
4092 return RISCVAsmParser::Match_InvalidBareSymbolQC_E_LI;
4093 break;
4094 }
4095 case MCK_CLUIImm: {
4096 DiagnosticPredicate DP(Operand.isCLUIImm());
4097 if (DP.isMatch())
4098 return MCTargetAsmParser::Match_Success;
4099 if (DP.isNearMatch())
4100 return RISCVAsmParser::Match_InvalidCLUIImm;
4101 break;
4102 }
4103 case MCK_CSRSystemRegister: {
4104 DiagnosticPredicate DP(Operand.isCSRSystemRegister());
4105 if (DP.isMatch())
4106 return MCTargetAsmParser::Match_Success;
4107 if (DP.isNearMatch())
4108 return RISCVAsmParser::Match_InvalidCSRSystemRegister;
4109 break;
4110 }
4111 case MCK_RegReg: {
4112 DiagnosticPredicate DP(Operand.isRegReg());
4113 if (DP.isMatch())
4114 return MCTargetAsmParser::Match_Success;
4115 break;
4116 }
4117 case MCK_CallSymbol: {
4118 DiagnosticPredicate DP(Operand.isCallSymbol());
4119 if (DP.isMatch())
4120 return MCTargetAsmParser::Match_Success;
4121 if (DP.isNearMatch())
4122 return RISCVAsmParser::Match_InvalidCallSymbol;
4123 break;
4124 }
4125 case MCK_FRMArg: {
4126 DiagnosticPredicate DP(Operand.isFRMArg());
4127 if (DP.isMatch())
4128 return MCTargetAsmParser::Match_Success;
4129 break;
4130 }
4131 case MCK_FRMArgLegacy: {
4132 DiagnosticPredicate DP(Operand.isFRMArgLegacy());
4133 if (DP.isMatch())
4134 return MCTargetAsmParser::Match_Success;
4135 break;
4136 }
4137 case MCK_FenceArg: {
4138 DiagnosticPredicate DP(Operand.isFenceArg());
4139 if (DP.isMatch())
4140 return MCTargetAsmParser::Match_Success;
4141 break;
4142 }
4143 case MCK_GPRAsFPR16: {
4144 DiagnosticPredicate DP(Operand.isGPRAsFPR16());
4145 if (DP.isMatch())
4146 return MCTargetAsmParser::Match_Success;
4147 break;
4148 }
4149 case MCK_GPRAsFPR32: {
4150 DiagnosticPredicate DP(Operand.isGPRAsFPR32());
4151 if (DP.isMatch())
4152 return MCTargetAsmParser::Match_Success;
4153 break;
4154 }
4155 case MCK_GPRF64AsFPR: {
4156 DiagnosticPredicate DP(Operand.isGPRAsFPR());
4157 if (DP.isMatch())
4158 return MCTargetAsmParser::Match_Success;
4159 break;
4160 }
4161 case MCK_GPRPairAsFPR: {
4162 DiagnosticPredicate DP(Operand.isGPRPairAsFPR64());
4163 if (DP.isMatch())
4164 return MCTargetAsmParser::Match_Success;
4165 break;
4166 }
4167 case MCK_GPRPairCRV32: {
4168 DiagnosticPredicate DP(Operand.isGPRPairC());
4169 if (DP.isMatch())
4170 return MCTargetAsmParser::Match_Success;
4171 break;
4172 }
4173 case MCK_GPRPairNoX0RV32: {
4174 DiagnosticPredicate DP(Operand.isGPRPairNoX0());
4175 if (DP.isMatch())
4176 return MCTargetAsmParser::Match_Success;
4177 break;
4178 }
4179 case MCK_GPRPairRV32: {
4180 DiagnosticPredicate DP(Operand.isGPRPair());
4181 if (DP.isMatch())
4182 return MCTargetAsmParser::Match_Success;
4183 break;
4184 }
4185 case MCK_GPRPairRV64: {
4186 DiagnosticPredicate DP(Operand.isGPRPair());
4187 if (DP.isMatch())
4188 return MCTargetAsmParser::Match_Success;
4189 break;
4190 }
4191 case MCK_Imm: {
4192 DiagnosticPredicate DP(Operand.isImm());
4193 if (DP.isMatch())
4194 return MCTargetAsmParser::Match_Success;
4195 break;
4196 }
4197 case MCK_ImmFour: {
4198 DiagnosticPredicate DP(Operand.isImmFour());
4199 if (DP.isMatch())
4200 return MCTargetAsmParser::Match_Success;
4201 if (DP.isNearMatch())
4202 return RISCVAsmParser::Match_InvalidImmFour;
4203 break;
4204 }
4205 case MCK_ImmThree: {
4206 DiagnosticPredicate DP(Operand.isImmThree());
4207 if (DP.isMatch())
4208 return MCTargetAsmParser::Match_Success;
4209 if (DP.isNearMatch())
4210 return RISCVAsmParser::Match_InvalidImmThree;
4211 break;
4212 }
4213 case MCK_ImmZero: {
4214 DiagnosticPredicate DP(Operand.isImmZero());
4215 if (DP.isMatch())
4216 return MCTargetAsmParser::Match_Success;
4217 if (DP.isNearMatch())
4218 return RISCVAsmParser::Match_InvalidImmZero;
4219 break;
4220 }
4221 case MCK_InsnCDirectiveOpcode: {
4222 DiagnosticPredicate DP(Operand.isImm());
4223 if (DP.isMatch())
4224 return MCTargetAsmParser::Match_Success;
4225 break;
4226 }
4227 case MCK_InsnDirectiveOpcode: {
4228 DiagnosticPredicate DP(Operand.isImm());
4229 if (DP.isMatch())
4230 return MCTargetAsmParser::Match_Success;
4231 break;
4232 }
4233 case MCK_LoadFPImm: {
4234 DiagnosticPredicate DP(Operand.isLoadFPImm());
4235 if (DP.isMatch())
4236 return MCTargetAsmParser::Match_Success;
4237 if (DP.isNearMatch())
4238 return RISCVAsmParser::Match_InvalidLoadFPImm;
4239 break;
4240 }
4241 case MCK_NegStackAdj: {
4242 DiagnosticPredicate DP(Operand.isStackAdj());
4243 if (DP.isMatch())
4244 return MCTargetAsmParser::Match_Success;
4245 if (DP.isNearMatch())
4246 return RISCVAsmParser::Match_InvalidStackAdj;
4247 break;
4248 }
4249 case MCK_PseudoJumpSymbol: {
4250 DiagnosticPredicate DP(Operand.isPseudoJumpSymbol());
4251 if (DP.isMatch())
4252 return MCTargetAsmParser::Match_Success;
4253 if (DP.isNearMatch())
4254 return RISCVAsmParser::Match_InvalidPseudoJumpSymbol;
4255 break;
4256 }
4257 case MCK_QCAccessSymbol: {
4258 DiagnosticPredicate DP(Operand.isQCAccessSymbol());
4259 if (DP.isMatch())
4260 return MCTargetAsmParser::Match_Success;
4261 if (DP.isNearMatch())
4262 return RISCVAsmParser::Match_InvalidQCAccessSymbol;
4263 break;
4264 }
4265 case MCK_RTZArg: {
4266 DiagnosticPredicate DP(Operand.isRTZArg());
4267 if (DP.isMatch())
4268 return MCTargetAsmParser::Match_Success;
4269 if (DP.isNearMatch())
4270 return RISCVAsmParser::Match_InvalidRTZArg;
4271 break;
4272 }
4273 case MCK_RegList: {
4274 DiagnosticPredicate DP(Operand.isRegList());
4275 if (DP.isMatch())
4276 return MCTargetAsmParser::Match_Success;
4277 if (DP.isNearMatch())
4278 return RISCVAsmParser::Match_InvalidRegList;
4279 break;
4280 }
4281 case MCK_RegListS0: {
4282 DiagnosticPredicate DP(Operand.isRegListS0());
4283 if (DP.isMatch())
4284 return MCTargetAsmParser::Match_Success;
4285 if (DP.isNearMatch())
4286 return RISCVAsmParser::Match_InvalidRegListS0;
4287 break;
4288 }
4289 case MCK_RnumArg: {
4290 DiagnosticPredicate DP(Operand.isRnumArg());
4291 if (DP.isMatch())
4292 return MCTargetAsmParser::Match_Success;
4293 if (DP.isNearMatch())
4294 return RISCVAsmParser::Match_InvalidRnumArg;
4295 break;
4296 }
4297 case MCK_SImm10PLI_H: {
4298 DiagnosticPredicate DP(Operand.isSImm10PLI_H());
4299 if (DP.isMatch())
4300 return MCTargetAsmParser::Match_Success;
4301 if (DP.isNearMatch())
4302 return RISCVAsmParser::Match_InvalidSImm10PLI_H;
4303 break;
4304 }
4305 case MCK_SImm10PLI_W: {
4306 DiagnosticPredicate DP(Operand.isSImm10PLI_W());
4307 if (DP.isMatch())
4308 return MCTargetAsmParser::Match_Success;
4309 if (DP.isNearMatch())
4310 return RISCVAsmParser::Match_InvalidSImm10PLI_W;
4311 break;
4312 }
4313 case MCK_SImm10PLUI: {
4314 DiagnosticPredicate DP(Operand.isSImm10PLUI());
4315 if (DP.isMatch())
4316 return MCTargetAsmParser::Match_Success;
4317 if (DP.isNearMatch())
4318 return RISCVAsmParser::Match_InvalidSImm10PLUI;
4319 break;
4320 }
4321 case MCK_SImm8PLI_B: {
4322 DiagnosticPredicate DP(Operand.isSImm8PLI_B());
4323 if (DP.isMatch())
4324 return MCTargetAsmParser::Match_Success;
4325 if (DP.isNearMatch())
4326 return RISCVAsmParser::Match_InvalidSImm8PLI_B;
4327 break;
4328 }
4329 case MCK_BareSImm21Lsb0: {
4330 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<21>());
4331 if (DP.isMatch())
4332 return MCTargetAsmParser::Match_Success;
4333 if (DP.isNearMatch())
4334 return RISCVAsmParser::Match_InvalidBareSImm21Lsb0;
4335 break;
4336 }
4337 case MCK_StackAdj: {
4338 DiagnosticPredicate DP(Operand.isStackAdj());
4339 if (DP.isMatch())
4340 return MCTargetAsmParser::Match_Success;
4341 if (DP.isNearMatch())
4342 return RISCVAsmParser::Match_InvalidStackAdj;
4343 break;
4344 }
4345 case MCK_TLSDESCCallSymbol: {
4346 DiagnosticPredicate DP(Operand.isTLSDESCCallSymbol());
4347 if (DP.isMatch())
4348 return MCTargetAsmParser::Match_Success;
4349 if (DP.isNearMatch())
4350 return RISCVAsmParser::Match_InvalidTLSDESCCallSymbol;
4351 break;
4352 }
4353 case MCK_TPRelAddSymbol: {
4354 DiagnosticPredicate DP(Operand.isTPRelAddSymbol());
4355 if (DP.isMatch())
4356 return MCTargetAsmParser::Match_Success;
4357 if (DP.isNearMatch())
4358 return RISCVAsmParser::Match_InvalidTPRelAddSymbol;
4359 break;
4360 }
4361 case MCK_TileLambda: {
4362 DiagnosticPredicate DP(Operand.isTileLambda());
4363 if (DP.isMatch())
4364 return MCTargetAsmParser::Match_Success;
4365 if (DP.isNearMatch())
4366 return RISCVAsmParser::Match_InvalidTileLambda;
4367 break;
4368 }
4369 case MCK_UImmLog2XLen: {
4370 DiagnosticPredicate DP(Operand.isUImmLog2XLen());
4371 if (DP.isMatch())
4372 return MCTargetAsmParser::Match_Success;
4373 if (DP.isNearMatch())
4374 return RISCVAsmParser::Match_InvalidUImmLog2XLen;
4375 break;
4376 }
4377 case MCK_UImmLog2XLenNonZero: {
4378 DiagnosticPredicate DP(Operand.isUImmLog2XLenNonZero());
4379 if (DP.isMatch())
4380 return MCTargetAsmParser::Match_Success;
4381 if (DP.isNearMatch())
4382 return RISCVAsmParser::Match_InvalidUImmLog2XLenNonZero;
4383 break;
4384 }
4385 case MCK_RVVMaskRegOpOperand: {
4386 DiagnosticPredicate DP(Operand.isV0Reg());
4387 if (DP.isMatch())
4388 return MCTargetAsmParser::Match_Success;
4389 if (DP.isNearMatch())
4390 return RISCVAsmParser::Match_InvalidVMaskRegister;
4391 break;
4392 }
4393 case MCK_RVVMaskCarryInRegOpOperand: {
4394 DiagnosticPredicate DP(Operand.isV0Reg());
4395 if (DP.isMatch())
4396 return MCTargetAsmParser::Match_Success;
4397 if (DP.isNearMatch())
4398 return RISCVAsmParser::Match_InvalidVMaskCarryInRegister;
4399 break;
4400 }
4401 case MCK_RVVScaleRegOpOperand: {
4402 DiagnosticPredicate DP(Operand.isV0Reg());
4403 if (DP.isMatch())
4404 return MCTargetAsmParser::Match_Success;
4405 if (DP.isNearMatch())
4406 return RISCVAsmParser::Match_InvalidVScaleRegister;
4407 break;
4408 }
4409 case MCK_XSfmmVType: {
4410 DiagnosticPredicate DP(Operand.isXSfmmVType());
4411 if (DP.isMatch())
4412 return MCTargetAsmParser::Match_Success;
4413 break;
4414 }
4415 case MCK_YBNDSWImm: {
4416 DiagnosticPredicate DP(Operand.isYBNDSWImm());
4417 if (DP.isMatch())
4418 return MCTargetAsmParser::Match_Success;
4419 if (DP.isNearMatch())
4420 return RISCVAsmParser::Match_InvalidYBNDSWImm;
4421 break;
4422 }
4423 case MCK_ZeroOffsetMemOpOperand: {
4424 DiagnosticPredicate DP(Operand.isGPR());
4425 if (DP.isMatch())
4426 return MCTargetAsmParser::Match_Success;
4427 break;
4428 }
4429 case MCK_UImm1: {
4430 DiagnosticPredicate DP(Operand.isUImm1());
4431 if (DP.isMatch())
4432 return MCTargetAsmParser::Match_Success;
4433 if (DP.isNearMatch())
4434 return RISCVAsmParser::Match_InvalidUImm1;
4435 break;
4436 }
4437 case MCK_UImm2: {
4438 DiagnosticPredicate DP(Operand.isUImm2());
4439 if (DP.isMatch())
4440 return MCTargetAsmParser::Match_Success;
4441 if (DP.isNearMatch())
4442 return RISCVAsmParser::Match_InvalidUImm2;
4443 break;
4444 }
4445 case MCK_UImm3: {
4446 DiagnosticPredicate DP(Operand.isUImm3());
4447 if (DP.isMatch())
4448 return MCTargetAsmParser::Match_Success;
4449 if (DP.isNearMatch())
4450 return RISCVAsmParser::Match_InvalidUImm3;
4451 break;
4452 }
4453 case MCK_UImm4: {
4454 DiagnosticPredicate DP(Operand.isUImm4());
4455 if (DP.isMatch())
4456 return MCTargetAsmParser::Match_Success;
4457 if (DP.isNearMatch())
4458 return RISCVAsmParser::Match_InvalidUImm4;
4459 break;
4460 }
4461 case MCK_UImm5: {
4462 DiagnosticPredicate DP(Operand.isUImm5());
4463 if (DP.isMatch())
4464 return MCTargetAsmParser::Match_Success;
4465 if (DP.isNearMatch())
4466 return RISCVAsmParser::Match_InvalidUImm5;
4467 break;
4468 }
4469 case MCK_UImm6: {
4470 DiagnosticPredicate DP(Operand.isUImm6());
4471 if (DP.isMatch())
4472 return MCTargetAsmParser::Match_Success;
4473 if (DP.isNearMatch())
4474 return RISCVAsmParser::Match_InvalidUImm6;
4475 break;
4476 }
4477 case MCK_UImm7: {
4478 DiagnosticPredicate DP(Operand.isUImm7());
4479 if (DP.isMatch())
4480 return MCTargetAsmParser::Match_Success;
4481 if (DP.isNearMatch())
4482 return RISCVAsmParser::Match_InvalidUImm7;
4483 break;
4484 }
4485 case MCK_UImm8: {
4486 DiagnosticPredicate DP(Operand.isUImm8());
4487 if (DP.isMatch())
4488 return MCTargetAsmParser::Match_Success;
4489 if (DP.isNearMatch())
4490 return RISCVAsmParser::Match_InvalidUImm8;
4491 break;
4492 }
4493 case MCK_UImm16: {
4494 DiagnosticPredicate DP(Operand.isUImm16());
4495 if (DP.isMatch())
4496 return MCTargetAsmParser::Match_Success;
4497 if (DP.isNearMatch())
4498 return RISCVAsmParser::Match_InvalidUImm16;
4499 break;
4500 }
4501 case MCK_UImm32: {
4502 DiagnosticPredicate DP(Operand.isUImm32());
4503 if (DP.isMatch())
4504 return MCTargetAsmParser::Match_Success;
4505 if (DP.isNearMatch())
4506 return RISCVAsmParser::Match_InvalidUImm32;
4507 break;
4508 }
4509 case MCK_UImm48: {
4510 DiagnosticPredicate DP(Operand.isUImm48());
4511 if (DP.isMatch())
4512 return MCTargetAsmParser::Match_Success;
4513 if (DP.isNearMatch())
4514 return RISCVAsmParser::Match_InvalidUImm48;
4515 break;
4516 }
4517 case MCK_UImm64: {
4518 DiagnosticPredicate DP(Operand.isUImm64());
4519 if (DP.isMatch())
4520 return MCTargetAsmParser::Match_Success;
4521 if (DP.isNearMatch())
4522 return RISCVAsmParser::Match_InvalidUImm64;
4523 break;
4524 }
4525 case MCK_SImm12: {
4526 DiagnosticPredicate DP(Operand.isSImm12());
4527 if (DP.isMatch())
4528 return MCTargetAsmParser::Match_Success;
4529 if (DP.isNearMatch())
4530 return RISCVAsmParser::Match_InvalidSImm12;
4531 break;
4532 }
4533 case MCK_SImm12LO: {
4534 DiagnosticPredicate DP(Operand.isSImm12LO());
4535 if (DP.isMatch())
4536 return MCTargetAsmParser::Match_Success;
4537 if (DP.isNearMatch())
4538 return RISCVAsmParser::Match_InvalidSImm12LO;
4539 break;
4540 }
4541 case MCK_BareSImm13Lsb0: {
4542 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<13>());
4543 if (DP.isMatch())
4544 return MCTargetAsmParser::Match_Success;
4545 if (DP.isNearMatch())
4546 return RISCVAsmParser::Match_InvalidBareSImm13Lsb0;
4547 break;
4548 }
4549 case MCK_UImm20: {
4550 DiagnosticPredicate DP(Operand.isUImm20());
4551 if (DP.isMatch())
4552 return MCTargetAsmParser::Match_Success;
4553 if (DP.isNearMatch())
4554 return RISCVAsmParser::Match_InvalidUImm20;
4555 break;
4556 }
4557 case MCK_UImm20LUI: {
4558 DiagnosticPredicate DP(Operand.isUImm20LUI());
4559 if (DP.isMatch())
4560 return MCTargetAsmParser::Match_Success;
4561 if (DP.isNearMatch())
4562 return RISCVAsmParser::Match_InvalidUImm20LUI;
4563 break;
4564 }
4565 case MCK_UImm20AUIPC: {
4566 DiagnosticPredicate DP(Operand.isUImm20AUIPC());
4567 if (DP.isMatch())
4568 return MCTargetAsmParser::Match_Success;
4569 if (DP.isNearMatch())
4570 return RISCVAsmParser::Match_InvalidUImm20AUIPC;
4571 break;
4572 }
4573 case MCK_ImmXLenLI: {
4574 DiagnosticPredicate DP(Operand.isImmXLenLI());
4575 if (DP.isMatch())
4576 return MCTargetAsmParser::Match_Success;
4577 if (DP.isNearMatch())
4578 return RISCVAsmParser::Match_InvalidImmXLenLI;
4579 break;
4580 }
4581 case MCK_ImmXLenLI_Restricted: {
4582 DiagnosticPredicate DP(Operand.isImmXLenLI_Restricted());
4583 if (DP.isMatch())
4584 return MCTargetAsmParser::Match_Success;
4585 if (DP.isNearMatch())
4586 return RISCVAsmParser::Match_InvalidImmXLenLI_Restricted;
4587 break;
4588 }
4589 case MCK_SImm12Lsb00000: {
4590 DiagnosticPredicate DP(Operand.isSImm12Lsb00000());
4591 if (DP.isMatch())
4592 return MCTargetAsmParser::Match_Success;
4593 if (DP.isNearMatch())
4594 return RISCVAsmParser::Match_InvalidSImm12Lsb00000;
4595 break;
4596 }
4597 case MCK_Imm5Zibi: {
4598 DiagnosticPredicate DP(Operand.isImm5Zibi());
4599 if (DP.isMatch())
4600 return MCTargetAsmParser::Match_Success;
4601 if (DP.isNearMatch())
4602 return RISCVAsmParser::Match_InvalidImm5Zibi;
4603 break;
4604 }
4605 case MCK_VTypeI10: {
4606 DiagnosticPredicate DP(Operand.isVTypeI10());
4607 if (DP.isMatch())
4608 return MCTargetAsmParser::Match_Success;
4609 if (DP.isNearMatch())
4610 return RISCVAsmParser::Match_InvalidVTypeI;
4611 break;
4612 }
4613 case MCK_VTypeI11: {
4614 DiagnosticPredicate DP(Operand.isVTypeI11());
4615 if (DP.isMatch())
4616 return MCTargetAsmParser::Match_Success;
4617 if (DP.isNearMatch())
4618 return RISCVAsmParser::Match_InvalidVTypeI;
4619 break;
4620 }
4621 case MCK_SImm5: {
4622 DiagnosticPredicate DP(Operand.isSImm5());
4623 if (DP.isMatch())
4624 return MCTargetAsmParser::Match_Success;
4625 if (DP.isNearMatch())
4626 return RISCVAsmParser::Match_InvalidSImm5;
4627 break;
4628 }
4629 case MCK_SImm5Plus1: {
4630 DiagnosticPredicate DP(Operand.isSImm5Plus1());
4631 if (DP.isMatch())
4632 return MCTargetAsmParser::Match_Success;
4633 if (DP.isNearMatch())
4634 return RISCVAsmParser::Match_InvalidSImm5Plus1;
4635 break;
4636 }
4637 case MCK_UImm4Plus1: {
4638 DiagnosticPredicate DP(Operand.isUImm4Plus1());
4639 if (DP.isMatch())
4640 return MCTargetAsmParser::Match_Success;
4641 if (DP.isNearMatch())
4642 return RISCVAsmParser::Match_InvalidUImm4Plus1;
4643 break;
4644 }
4645 case MCK_UImm5Plus1: {
4646 DiagnosticPredicate DP(Operand.isUImm5Plus1());
4647 if (DP.isMatch())
4648 return MCTargetAsmParser::Match_Success;
4649 if (DP.isNearMatch())
4650 return RISCVAsmParser::Match_InvalidUImm5Plus1;
4651 break;
4652 }
4653 case MCK_UImm6Plus1: {
4654 DiagnosticPredicate DP(Operand.isUImm6Plus1());
4655 if (DP.isMatch())
4656 return MCTargetAsmParser::Match_Success;
4657 if (DP.isNearMatch())
4658 return RISCVAsmParser::Match_InvalidUImm6Plus1;
4659 break;
4660 }
4661 case MCK_SImm6: {
4662 DiagnosticPredicate DP(Operand.isSImm6());
4663 if (DP.isMatch())
4664 return MCTargetAsmParser::Match_Success;
4665 if (DP.isNearMatch())
4666 return RISCVAsmParser::Match_InvalidSImm6;
4667 break;
4668 }
4669 case MCK_SImm6NonZero: {
4670 DiagnosticPredicate DP(Operand.isSImm6NonZero());
4671 if (DP.isMatch())
4672 return MCTargetAsmParser::Match_Success;
4673 if (DP.isNearMatch())
4674 return RISCVAsmParser::Match_InvalidSImm6NonZero;
4675 break;
4676 }
4677 case MCK_UImm7Lsb00: {
4678 DiagnosticPredicate DP(Operand.isUImm7Lsb00());
4679 if (DP.isMatch())
4680 return MCTargetAsmParser::Match_Success;
4681 if (DP.isNearMatch())
4682 return RISCVAsmParser::Match_InvalidUImm7Lsb00;
4683 break;
4684 }
4685 case MCK_UImm8Lsb00: {
4686 DiagnosticPredicate DP(Operand.isUImm8Lsb00());
4687 if (DP.isMatch())
4688 return MCTargetAsmParser::Match_Success;
4689 if (DP.isNearMatch())
4690 return RISCVAsmParser::Match_InvalidUImm8Lsb00;
4691 break;
4692 }
4693 case MCK_UImm8Lsb000: {
4694 DiagnosticPredicate DP(Operand.isUImm8Lsb000());
4695 if (DP.isMatch())
4696 return MCTargetAsmParser::Match_Success;
4697 if (DP.isNearMatch())
4698 return RISCVAsmParser::Match_InvalidUImm8Lsb000;
4699 break;
4700 }
4701 case MCK_BareSImm9Lsb0: {
4702 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<9>());
4703 if (DP.isMatch())
4704 return MCTargetAsmParser::Match_Success;
4705 if (DP.isNearMatch())
4706 return RISCVAsmParser::Match_InvalidBareSImm9Lsb0;
4707 break;
4708 }
4709 case MCK_UImm9Lsb000: {
4710 DiagnosticPredicate DP(Operand.isUImm9Lsb000());
4711 if (DP.isMatch())
4712 return MCTargetAsmParser::Match_Success;
4713 if (DP.isNearMatch())
4714 return RISCVAsmParser::Match_InvalidUImm9Lsb000;
4715 break;
4716 }
4717 case MCK_UImm10Lsb00NonZero: {
4718 DiagnosticPredicate DP(Operand.isUImm10Lsb00NonZero());
4719 if (DP.isMatch())
4720 return MCTargetAsmParser::Match_Success;
4721 if (DP.isNearMatch())
4722 return RISCVAsmParser::Match_InvalidUImm10Lsb00NonZero;
4723 break;
4724 }
4725 case MCK_SImm10Lsb0000NonZero: {
4726 DiagnosticPredicate DP(Operand.isSImm10Lsb0000NonZero());
4727 if (DP.isMatch())
4728 return MCTargetAsmParser::Match_Success;
4729 if (DP.isNearMatch())
4730 return RISCVAsmParser::Match_InvalidSImm10Lsb0000NonZero;
4731 break;
4732 }
4733 case MCK_BareSImm12Lsb0: {
4734 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<12>());
4735 if (DP.isMatch())
4736 return MCTargetAsmParser::Match_Success;
4737 if (DP.isNearMatch())
4738 return RISCVAsmParser::Match_InvalidBareSImm12Lsb0;
4739 break;
4740 }
4741 case MCK_UImm2Lsb0: {
4742 DiagnosticPredicate DP(Operand.isUImm2Lsb0());
4743 if (DP.isMatch())
4744 return MCTargetAsmParser::Match_Success;
4745 if (DP.isNearMatch())
4746 return RISCVAsmParser::Match_InvalidUImm2Lsb0;
4747 break;
4748 }
4749 case MCK_UImm8GE32: {
4750 DiagnosticPredicate DP(Operand.isUImm8GE32());
4751 if (DP.isMatch())
4752 return MCTargetAsmParser::Match_Success;
4753 if (DP.isNearMatch())
4754 return RISCVAsmParser::Match_InvalidUImm8GE32;
4755 break;
4756 }
4757 case MCK_UImm7EqXLen: {
4758 DiagnosticPredicate DP(Operand.isUImm7EqXLen());
4759 if (DP.isMatch())
4760 return MCTargetAsmParser::Match_Success;
4761 if (DP.isNearMatch())
4762 return RISCVAsmParser::Match_InvalidUImm7EqXLen;
4763 break;
4764 }
4765 case MCK_UImm5Lsb0: {
4766 DiagnosticPredicate DP(Operand.isUImm5Lsb0());
4767 if (DP.isMatch())
4768 return MCTargetAsmParser::Match_Success;
4769 if (DP.isNearMatch())
4770 return RISCVAsmParser::Match_InvalidUImm5Lsb0;
4771 break;
4772 }
4773 case MCK_UImm6Lsb0: {
4774 DiagnosticPredicate DP(Operand.isUImm6Lsb0());
4775 if (DP.isMatch())
4776 return MCTargetAsmParser::Match_Success;
4777 if (DP.isNearMatch())
4778 return RISCVAsmParser::Match_InvalidUImm6Lsb0;
4779 break;
4780 }
4781 case MCK_UImm5NonZero: {
4782 DiagnosticPredicate DP(Operand.isUImm5NonZero());
4783 if (DP.isMatch())
4784 return MCTargetAsmParser::Match_Success;
4785 if (DP.isNearMatch())
4786 return RISCVAsmParser::Match_InvalidUImm5NonZero;
4787 break;
4788 }
4789 case MCK_UImm5GT3: {
4790 DiagnosticPredicate DP(Operand.isUImm5GT3());
4791 if (DP.isMatch())
4792 return MCTargetAsmParser::Match_Success;
4793 if (DP.isNearMatch())
4794 return RISCVAsmParser::Match_InvalidUImm5GT3;
4795 break;
4796 }
4797 case MCK_UImm5GE6Plus1: {
4798 DiagnosticPredicate DP(Operand.isUImm5GE6Plus1());
4799 if (DP.isMatch())
4800 return MCTargetAsmParser::Match_Success;
4801 if (DP.isNearMatch())
4802 return RISCVAsmParser::Match_InvalidUImm5GE6Plus1;
4803 break;
4804 }
4805 case MCK_UImm5Slist: {
4806 DiagnosticPredicate DP(Operand.isUImm5Slist());
4807 if (DP.isMatch())
4808 return MCTargetAsmParser::Match_Success;
4809 if (DP.isNearMatch())
4810 return RISCVAsmParser::Match_InvalidUImm5Slist;
4811 break;
4812 }
4813 case MCK_UImm10: {
4814 DiagnosticPredicate DP(Operand.isUImm10());
4815 if (DP.isMatch())
4816 return MCTargetAsmParser::Match_Success;
4817 if (DP.isNearMatch())
4818 return RISCVAsmParser::Match_InvalidUImm10;
4819 break;
4820 }
4821 case MCK_UImm11: {
4822 DiagnosticPredicate DP(Operand.isUImm11());
4823 if (DP.isMatch())
4824 return MCTargetAsmParser::Match_Success;
4825 if (DP.isNearMatch())
4826 return RISCVAsmParser::Match_InvalidUImm11;
4827 break;
4828 }
4829 case MCK_UImm14Lsb00: {
4830 DiagnosticPredicate DP(Operand.isUImm14Lsb00());
4831 if (DP.isMatch())
4832 return MCTargetAsmParser::Match_Success;
4833 if (DP.isNearMatch())
4834 return RISCVAsmParser::Match_InvalidUImm14Lsb00;
4835 break;
4836 }
4837 case MCK_UImm16NonZero: {
4838 DiagnosticPredicate DP(Operand.isUImm16NonZero());
4839 if (DP.isMatch())
4840 return MCTargetAsmParser::Match_Success;
4841 if (DP.isNearMatch())
4842 return RISCVAsmParser::Match_InvalidUImm16NonZero;
4843 break;
4844 }
4845 case MCK_SImm5NonZero: {
4846 DiagnosticPredicate DP(Operand.isSImm5NonZero());
4847 if (DP.isMatch())
4848 return MCTargetAsmParser::Match_Success;
4849 if (DP.isNearMatch())
4850 return RISCVAsmParser::Match_InvalidSImm5NonZero;
4851 break;
4852 }
4853 case MCK_SImm11: {
4854 DiagnosticPredicate DP(Operand.isSImm11());
4855 if (DP.isMatch())
4856 return MCTargetAsmParser::Match_Success;
4857 if (DP.isNearMatch())
4858 return RISCVAsmParser::Match_InvalidSImm11;
4859 break;
4860 }
4861 case MCK_SImm16: {
4862 DiagnosticPredicate DP(Operand.isSImm16());
4863 if (DP.isMatch())
4864 return MCTargetAsmParser::Match_Success;
4865 if (DP.isNearMatch())
4866 return RISCVAsmParser::Match_InvalidSImm16;
4867 break;
4868 }
4869 case MCK_SImm16NonZero: {
4870 DiagnosticPredicate DP(Operand.isSImm16NonZero());
4871 if (DP.isMatch())
4872 return MCTargetAsmParser::Match_Success;
4873 if (DP.isNearMatch())
4874 return RISCVAsmParser::Match_InvalidSImm16NonZero;
4875 break;
4876 }
4877 case MCK_SImm20LI: {
4878 DiagnosticPredicate DP(Operand.isSImm20LI());
4879 if (DP.isMatch())
4880 return MCTargetAsmParser::Match_Success;
4881 if (DP.isNearMatch())
4882 return RISCVAsmParser::Match_InvalidSImm20LI;
4883 break;
4884 }
4885 case MCK_SImm26: {
4886 DiagnosticPredicate DP(Operand.isSImm26());
4887 if (DP.isMatch())
4888 return MCTargetAsmParser::Match_Success;
4889 if (DP.isNearMatch())
4890 return RISCVAsmParser::Match_InvalidSImm26;
4891 break;
4892 }
4893 case MCK_BareSImm32: {
4894 DiagnosticPredicate DP(Operand.isBareSimmN<32>());
4895 if (DP.isMatch())
4896 return MCTargetAsmParser::Match_Success;
4897 if (DP.isNearMatch())
4898 return RISCVAsmParser::Match_InvalidBareSImm32;
4899 break;
4900 }
4901 case MCK_BareSImm32Lsb0: {
4902 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<32>());
4903 if (DP.isMatch())
4904 return MCTargetAsmParser::Match_Success;
4905 if (DP.isNearMatch())
4906 return RISCVAsmParser::Match_InvalidBareSImm32Lsb0;
4907 break;
4908 }
4909 case MCK_UImm7Lsb000: {
4910 DiagnosticPredicate DP(Operand.isUImm7Lsb000());
4911 if (DP.isMatch())
4912 return MCTargetAsmParser::Match_Success;
4913 if (DP.isNearMatch())
4914 return RISCVAsmParser::Match_InvalidUImm7Lsb000;
4915 break;
4916 }
4917 case MCK_UImm9: {
4918 DiagnosticPredicate DP(Operand.isUImm9());
4919 if (DP.isMatch())
4920 return MCTargetAsmParser::Match_Success;
4921 if (DP.isNearMatch())
4922 return RISCVAsmParser::Match_InvalidUImm9;
4923 break;
4924 }
4925 case MCK_BareSImm11Lsb0: {
4926 DiagnosticPredicate DP(Operand.isBareSimmNLsb0<11>());
4927 if (DP.isMatch())
4928 return MCTargetAsmParser::Match_Success;
4929 if (DP.isNearMatch())
4930 return RISCVAsmParser::Match_InvalidBareSImm11Lsb0;
4931 break;
4932 }
4933 case MCK_SImm18: {
4934 DiagnosticPredicate DP(Operand.isSImm18());
4935 if (DP.isMatch())
4936 return MCTargetAsmParser::Match_Success;
4937 if (DP.isNearMatch())
4938 return RISCVAsmParser::Match_InvalidSImm18;
4939 break;
4940 }
4941 case MCK_SImm18Lsb0: {
4942 DiagnosticPredicate DP(Operand.isSImm18Lsb0());
4943 if (DP.isMatch())
4944 return MCTargetAsmParser::Match_Success;
4945 if (DP.isNearMatch())
4946 return RISCVAsmParser::Match_InvalidSImm18Lsb0;
4947 break;
4948 }
4949 case MCK_SImm19Lsb00: {
4950 DiagnosticPredicate DP(Operand.isSImm19Lsb00());
4951 if (DP.isMatch())
4952 return MCTargetAsmParser::Match_Success;
4953 if (DP.isNearMatch())
4954 return RISCVAsmParser::Match_InvalidSImm19Lsb00;
4955 break;
4956 }
4957 case MCK_SImm20Lsb000: {
4958 DiagnosticPredicate DP(Operand.isSImm20Lsb000());
4959 if (DP.isMatch())
4960 return MCTargetAsmParser::Match_Success;
4961 if (DP.isNearMatch())
4962 return RISCVAsmParser::Match_InvalidSImm20Lsb000;
4963 break;
4964 }
4965 case MCK_SImm10: {
4966 DiagnosticPredicate DP(Operand.isSImm10());
4967 if (DP.isMatch())
4968 return MCTargetAsmParser::Match_Success;
4969 if (DP.isNearMatch())
4970 return RISCVAsmParser::Match_InvalidSImm10;
4971 break;
4972 }
4973 } // end switch (Kind)
4974
4975 if (Operand.isReg()) {
4976 static constexpr uint16_t Table[RISCV::NUM_TARGET_REGS] = {
4977 InvalidMatchClass,
4978 InvalidMatchClass,
4979 InvalidMatchClass,
4980 InvalidMatchClass,
4981 MCK_anonymous_14630,
4982 InvalidMatchClass,
4983 MCK_VCSR,
4984 MCK_VCSR,
4985 MCK_VCSR,
4986 InvalidMatchClass,
4987 InvalidMatchClass,
4988 MCK_GPRAll,
4989 MCK_MR0,
4990 MCK_MR,
4991 MCK_MR,
4992 MCK_MR,
4993 MCK_MR,
4994 MCK_MR,
4995 MCK_MR,
4996 MCK_MR,
4997 MCK_TRM4,
4998 MCK_TR,
4999 MCK_TRM2,
5000 MCK_TR,
5001 MCK_TRM4,
5002 MCK_TR,
5003 MCK_TRM2,
5004 MCK_TR,
5005 MCK_TRM4,
5006 MCK_TR,
5007 MCK_TRM2,
5008 MCK_TR,
5009 MCK_TRM4,
5010 MCK_TR,
5011 MCK_TRM2,
5012 MCK_TR,
5013 MCK_VMV0,
5014 MCK_VRNoV0,
5015 MCK_VRNoV0,
5016 MCK_VRNoV0,
5017 MCK_VRNoV0,
5018 MCK_VRNoV0,
5019 MCK_VRNoV0,
5020 MCK_VRNoV0,
5021 MCK_VRNoV0,
5022 MCK_VRNoV0,
5023 MCK_VRNoV0,
5024 MCK_VRNoV0,
5025 MCK_VRNoV0,
5026 MCK_VRNoV0,
5027 MCK_VRNoV0,
5028 MCK_VRNoV0,
5029 MCK_VRNoV0,
5030 MCK_VRNoV0,
5031 MCK_VRNoV0,
5032 MCK_VRNoV0,
5033 MCK_VRNoV0,
5034 MCK_VRNoV0,
5035 MCK_VRNoV0,
5036 MCK_VRNoV0,
5037 MCK_VRNoV0,
5038 MCK_VRNoV0,
5039 MCK_VRNoV0,
5040 MCK_VRNoV0,
5041 MCK_VRNoV0,
5042 MCK_VRNoV0,
5043 MCK_VRNoV0,
5044 MCK_VRNoV0,
5045 MCK_GPRX0,
5046 MCK_GPRX1,
5047 MCK_SP,
5048 MCK_Reg15,
5049 MCK_Reg15,
5050 MCK_GPRX5,
5051 MCK_Reg26,
5052 MCK_GPRX7,
5053 MCK_Reg29,
5054 MCK_Reg29,
5055 MCK_Reg32,
5056 MCK_Reg32,
5057 MCK_Reg32,
5058 MCK_Reg32,
5059 MCK_Reg32,
5060 MCK_Reg32,
5061 MCK_Reg26,
5062 MCK_Reg26,
5063 MCK_SR07,
5064 MCK_SR07,
5065 MCK_SR07,
5066 MCK_SR07,
5067 MCK_SR07,
5068 MCK_SR07,
5069 MCK_Reg24,
5070 MCK_Reg24,
5071 MCK_Reg24,
5072 MCK_Reg24,
5073 MCK_Reg26,
5074 MCK_Reg26,
5075 MCK_Reg26,
5076 MCK_GPRTCNonX7,
5077 MCK_FPR64,
5078 MCK_FPR64,
5079 MCK_FPR64,
5080 MCK_FPR64,
5081 MCK_FPR64,
5082 MCK_FPR64,
5083 MCK_FPR64,
5084 MCK_FPR64,
5085 MCK_FPR64C,
5086 MCK_FPR64C,
5087 MCK_FPR64C,
5088 MCK_FPR64C,
5089 MCK_FPR64C,
5090 MCK_FPR64C,
5091 MCK_FPR64C,
5092 MCK_FPR64C,
5093 MCK_FPR64,
5094 MCK_FPR64,
5095 MCK_FPR64,
5096 MCK_FPR64,
5097 MCK_FPR64,
5098 MCK_FPR64,
5099 MCK_FPR64,
5100 MCK_FPR64,
5101 MCK_FPR64,
5102 MCK_FPR64,
5103 MCK_FPR64,
5104 MCK_FPR64,
5105 MCK_FPR64,
5106 MCK_FPR64,
5107 MCK_FPR64,
5108 MCK_FPR64,
5109 MCK_FPR32,
5110 MCK_FPR32,
5111 MCK_FPR32,
5112 MCK_FPR32,
5113 MCK_FPR32,
5114 MCK_FPR32,
5115 MCK_FPR32,
5116 MCK_FPR32,
5117 MCK_FPR32C,
5118 MCK_FPR32C,
5119 MCK_FPR32C,
5120 MCK_FPR32C,
5121 MCK_FPR32C,
5122 MCK_FPR32C,
5123 MCK_FPR32C,
5124 MCK_FPR32C,
5125 MCK_FPR32,
5126 MCK_FPR32,
5127 MCK_FPR32,
5128 MCK_FPR32,
5129 MCK_FPR32,
5130 MCK_FPR32,
5131 MCK_FPR32,
5132 MCK_FPR32,
5133 MCK_FPR32,
5134 MCK_FPR32,
5135 MCK_FPR32,
5136 MCK_FPR32,
5137 MCK_FPR32,
5138 MCK_FPR32,
5139 MCK_FPR32,
5140 MCK_FPR32,
5141 MCK_FPR16,
5142 MCK_FPR16,
5143 MCK_FPR16,
5144 MCK_FPR16,
5145 MCK_FPR16,
5146 MCK_FPR16,
5147 MCK_FPR16,
5148 MCK_FPR16,
5149 MCK_FPR16C,
5150 MCK_FPR16C,
5151 MCK_FPR16C,
5152 MCK_FPR16C,
5153 MCK_FPR16C,
5154 MCK_FPR16C,
5155 MCK_FPR16C,
5156 MCK_FPR16C,
5157 MCK_FPR16,
5158 MCK_FPR16,
5159 MCK_FPR16,
5160 MCK_FPR16,
5161 MCK_FPR16,
5162 MCK_FPR16,
5163 MCK_FPR16,
5164 MCK_FPR16,
5165 MCK_FPR16,
5166 MCK_FPR16,
5167 MCK_FPR16,
5168 MCK_FPR16,
5169 MCK_FPR16,
5170 MCK_FPR16,
5171 MCK_FPR16,
5172 MCK_FPR16,
5173 MCK_FPR128,
5174 MCK_FPR128,
5175 MCK_FPR128,
5176 MCK_FPR128,
5177 MCK_FPR128,
5178 MCK_FPR128,
5179 MCK_FPR128,
5180 MCK_FPR128,
5181 MCK_Reg88,
5182 MCK_Reg88,
5183 MCK_Reg88,
5184 MCK_Reg88,
5185 MCK_Reg88,
5186 MCK_Reg88,
5187 MCK_Reg88,
5188 MCK_Reg88,
5189 MCK_FPR128,
5190 MCK_FPR128,
5191 MCK_FPR128,
5192 MCK_FPR128,
5193 MCK_FPR128,
5194 MCK_FPR128,
5195 MCK_FPR128,
5196 MCK_FPR128,
5197 MCK_FPR128,
5198 MCK_FPR128,
5199 MCK_FPR128,
5200 MCK_FPR128,
5201 MCK_FPR128,
5202 MCK_FPR128,
5203 MCK_FPR128,
5204 MCK_FPR128,
5205 MCK_GPRF16,
5206 MCK_GPRF16NoX0,
5207 MCK_GPRF16NoX0,
5208 MCK_GPRF16NoX0,
5209 MCK_GPRF16NoX0,
5210 MCK_GPRF16NoX0,
5211 MCK_GPRF16NoX0,
5212 MCK_GPRF16NoX0,
5213 MCK_GPRF16C,
5214 MCK_GPRF16C,
5215 MCK_GPRF16C,
5216 MCK_GPRF16C,
5217 MCK_GPRF16C,
5218 MCK_GPRF16C,
5219 MCK_GPRF16C,
5220 MCK_GPRF16C,
5221 MCK_GPRF16NoX0,
5222 MCK_GPRF16NoX0,
5223 MCK_GPRF16NoX0,
5224 MCK_GPRF16NoX0,
5225 MCK_GPRF16NoX0,
5226 MCK_GPRF16NoX0,
5227 MCK_GPRF16NoX0,
5228 MCK_GPRF16NoX0,
5229 MCK_GPRF16NoX0,
5230 MCK_GPRF16NoX0,
5231 MCK_GPRF16NoX0,
5232 MCK_GPRF16NoX0,
5233 MCK_GPRF16NoX0,
5234 MCK_GPRF16NoX0,
5235 MCK_GPRF16NoX0,
5236 MCK_GPRF16NoX0,
5237 MCK_Reg59,
5238 MCK_GPRF32,
5239 MCK_GPRF32NoX0,
5240 MCK_GPRF32NoX0,
5241 MCK_GPRF32NoX0,
5242 MCK_GPRF32NoX0,
5243 MCK_GPRF32NoX0,
5244 MCK_GPRF32NoX0,
5245 MCK_GPRF32NoX0,
5246 MCK_GPRF32C,
5247 MCK_GPRF32C,
5248 MCK_GPRF32C,
5249 MCK_GPRF32C,
5250 MCK_GPRF32C,
5251 MCK_GPRF32C,
5252 MCK_GPRF32C,
5253 MCK_GPRF32C,
5254 MCK_GPRF32NoX0,
5255 MCK_GPRF32NoX0,
5256 MCK_GPRF32NoX0,
5257 MCK_GPRF32NoX0,
5258 MCK_GPRF32NoX0,
5259 MCK_GPRF32NoX0,
5260 MCK_GPRF32NoX0,
5261 MCK_GPRF32NoX0,
5262 MCK_GPRF32NoX0,
5263 MCK_GPRF32NoX0,
5264 MCK_GPRF32NoX0,
5265 MCK_GPRF32NoX0,
5266 MCK_GPRF32NoX0,
5267 MCK_GPRF32NoX0,
5268 MCK_GPRF32NoX0,
5269 MCK_GPRF32NoX0,
5270 MCK_Reg33,
5271 MCK_Reg38,
5272 MCK_Reg44,
5273 MCK_Reg41,
5274 MCK_Reg41,
5275 MCK_Reg45,
5276 MCK_Reg52,
5277 MCK_Reg54,
5278 MCK_Reg55,
5279 MCK_Reg55,
5280 MCK_Reg58,
5281 MCK_Reg58,
5282 MCK_Reg58,
5283 MCK_Reg58,
5284 MCK_Reg58,
5285 MCK_Reg58,
5286 MCK_Reg52,
5287 MCK_Reg52,
5288 MCK_Reg57,
5289 MCK_Reg57,
5290 MCK_Reg57,
5291 MCK_Reg57,
5292 MCK_Reg57,
5293 MCK_Reg57,
5294 MCK_Reg50,
5295 MCK_Reg50,
5296 MCK_Reg50,
5297 MCK_Reg50,
5298 MCK_Reg52,
5299 MCK_Reg52,
5300 MCK_Reg52,
5301 MCK_Reg53,
5302 MCK_FPR256,
5303 MCK_FPR256,
5304 MCK_FPR256,
5305 MCK_FPR256,
5306 MCK_FPR256,
5307 MCK_FPR256,
5308 MCK_FPR256,
5309 MCK_FPR256,
5310 MCK_Reg107,
5311 MCK_Reg107,
5312 MCK_Reg107,
5313 MCK_Reg107,
5314 MCK_Reg107,
5315 MCK_Reg107,
5316 MCK_Reg107,
5317 MCK_Reg107,
5318 MCK_FPR256,
5319 MCK_FPR256,
5320 MCK_FPR256,
5321 MCK_FPR256,
5322 MCK_FPR256,
5323 MCK_FPR256,
5324 MCK_FPR256,
5325 MCK_FPR256,
5326 MCK_FPR256,
5327 MCK_FPR256,
5328 MCK_FPR256,
5329 MCK_FPR256,
5330 MCK_FPR256,
5331 MCK_FPR256,
5332 MCK_FPR256,
5333 MCK_FPR256,
5334 MCK_Reg92,
5335 MCK_Reg95,
5336 MCK_Reg98,
5337 MCK_VRM2NoV0,
5338 MCK_VRM2NoV0,
5339 MCK_VRM4NoV0,
5340 MCK_VRM2NoV0,
5341 MCK_VRM2NoV0,
5342 MCK_VRM4NoV0,
5343 MCK_VRM8NoV0,
5344 MCK_VRM2NoV0,
5345 MCK_VRM2NoV0,
5346 MCK_VRM4NoV0,
5347 MCK_VRM2NoV0,
5348 MCK_VRM2NoV0,
5349 MCK_VRM4NoV0,
5350 MCK_VRM8NoV0,
5351 MCK_VRM2NoV0,
5352 MCK_VRM2NoV0,
5353 MCK_VRM4NoV0,
5354 MCK_VRM2NoV0,
5355 MCK_VRM2NoV0,
5356 MCK_VRM4NoV0,
5357 MCK_VRM8NoV0,
5358 MCK_VRM2NoV0,
5359 MCK_VRM2NoV0,
5360 MCK_VRM4NoV0,
5361 MCK_VRM2NoV0,
5362 MCK_Reg62,
5363 MCK_Reg65,
5364 MCK_Reg68,
5365 MCK_Reg73,
5366 MCK_Reg78,
5367 MCK_Reg78,
5368 MCK_Reg78,
5369 MCK_Reg79,
5370 MCK_Reg77,
5371 MCK_Reg77,
5372 MCK_Reg77,
5373 MCK_Reg75,
5374 MCK_Reg75,
5375 MCK_Reg79,
5376 MCK_Reg80,
5377 MCK_VRN2M1NoV0,
5378 MCK_VRN2M1NoV0,
5379 MCK_VRN2M1NoV0,
5380 MCK_VRN2M1NoV0,
5381 MCK_VRN2M1NoV0,
5382 MCK_VRN2M1NoV0,
5383 MCK_VRN2M1NoV0,
5384 MCK_VRN2M1NoV0,
5385 MCK_VRN2M1NoV0,
5386 MCK_VRN2M1NoV0,
5387 MCK_VRN2M1NoV0,
5388 MCK_VRN2M1NoV0,
5389 MCK_VRN2M1NoV0,
5390 MCK_VRN2M1NoV0,
5391 MCK_VRN2M1NoV0,
5392 MCK_VRN2M1NoV0,
5393 MCK_VRN2M1NoV0,
5394 MCK_VRN2M1NoV0,
5395 MCK_VRN2M1NoV0,
5396 MCK_VRN2M1NoV0,
5397 MCK_VRN2M1NoV0,
5398 MCK_VRN2M1NoV0,
5399 MCK_VRN2M1NoV0,
5400 MCK_VRN2M1NoV0,
5401 MCK_VRN2M1NoV0,
5402 MCK_VRN2M1NoV0,
5403 MCK_VRN2M1NoV0,
5404 MCK_VRN2M1NoV0,
5405 MCK_VRN2M1NoV0,
5406 MCK_VRN2M1NoV0,
5407 MCK_Reg112,
5408 MCK_VRN2M2NoV0,
5409 MCK_VRN2M2NoV0,
5410 MCK_VRN2M2NoV0,
5411 MCK_VRN2M2NoV0,
5412 MCK_VRN2M2NoV0,
5413 MCK_VRN2M2NoV0,
5414 MCK_VRN2M2NoV0,
5415 MCK_VRN2M2NoV0,
5416 MCK_VRN2M2NoV0,
5417 MCK_VRN2M2NoV0,
5418 MCK_VRN2M2NoV0,
5419 MCK_VRN2M2NoV0,
5420 MCK_VRN2M2NoV0,
5421 MCK_VRN2M2NoV0,
5422 MCK_Reg115,
5423 MCK_VRN2M4NoV0,
5424 MCK_VRN2M4NoV0,
5425 MCK_VRN2M4NoV0,
5426 MCK_VRN2M4NoV0,
5427 MCK_VRN2M4NoV0,
5428 MCK_VRN2M4NoV0,
5429 MCK_Reg118,
5430 MCK_VRN3M1NoV0,
5431 MCK_VRN3M1NoV0,
5432 MCK_VRN3M1NoV0,
5433 MCK_VRN3M1NoV0,
5434 MCK_VRN3M1NoV0,
5435 MCK_VRN3M1NoV0,
5436 MCK_VRN3M1NoV0,
5437 MCK_VRN3M1NoV0,
5438 MCK_VRN3M1NoV0,
5439 MCK_VRN3M1NoV0,
5440 MCK_VRN3M1NoV0,
5441 MCK_VRN3M1NoV0,
5442 MCK_VRN3M1NoV0,
5443 MCK_VRN3M1NoV0,
5444 MCK_VRN3M1NoV0,
5445 MCK_VRN3M1NoV0,
5446 MCK_VRN3M1NoV0,
5447 MCK_VRN3M1NoV0,
5448 MCK_VRN3M1NoV0,
5449 MCK_VRN3M1NoV0,
5450 MCK_VRN3M1NoV0,
5451 MCK_VRN3M1NoV0,
5452 MCK_VRN3M1NoV0,
5453 MCK_VRN3M1NoV0,
5454 MCK_VRN3M1NoV0,
5455 MCK_VRN3M1NoV0,
5456 MCK_VRN3M1NoV0,
5457 MCK_VRN3M1NoV0,
5458 MCK_VRN3M1NoV0,
5459 MCK_Reg121,
5460 MCK_VRN3M2NoV0,
5461 MCK_VRN3M2NoV0,
5462 MCK_VRN3M2NoV0,
5463 MCK_VRN3M2NoV0,
5464 MCK_VRN3M2NoV0,
5465 MCK_VRN3M2NoV0,
5466 MCK_VRN3M2NoV0,
5467 MCK_VRN3M2NoV0,
5468 MCK_VRN3M2NoV0,
5469 MCK_VRN3M2NoV0,
5470 MCK_VRN3M2NoV0,
5471 MCK_VRN3M2NoV0,
5472 MCK_VRN3M2NoV0,
5473 MCK_Reg124,
5474 MCK_VRN4M1NoV0,
5475 MCK_VRN4M1NoV0,
5476 MCK_VRN4M1NoV0,
5477 MCK_VRN4M1NoV0,
5478 MCK_VRN4M1NoV0,
5479 MCK_VRN4M1NoV0,
5480 MCK_VRN4M1NoV0,
5481 MCK_VRN4M1NoV0,
5482 MCK_VRN4M1NoV0,
5483 MCK_VRN4M1NoV0,
5484 MCK_VRN4M1NoV0,
5485 MCK_VRN4M1NoV0,
5486 MCK_VRN4M1NoV0,
5487 MCK_VRN4M1NoV0,
5488 MCK_VRN4M1NoV0,
5489 MCK_VRN4M1NoV0,
5490 MCK_VRN4M1NoV0,
5491 MCK_VRN4M1NoV0,
5492 MCK_VRN4M1NoV0,
5493 MCK_VRN4M1NoV0,
5494 MCK_VRN4M1NoV0,
5495 MCK_VRN4M1NoV0,
5496 MCK_VRN4M1NoV0,
5497 MCK_VRN4M1NoV0,
5498 MCK_VRN4M1NoV0,
5499 MCK_VRN4M1NoV0,
5500 MCK_VRN4M1NoV0,
5501 MCK_VRN4M1NoV0,
5502 MCK_Reg127,
5503 MCK_VRN4M2NoV0,
5504 MCK_VRN4M2NoV0,
5505 MCK_VRN4M2NoV0,
5506 MCK_VRN4M2NoV0,
5507 MCK_VRN4M2NoV0,
5508 MCK_VRN4M2NoV0,
5509 MCK_VRN4M2NoV0,
5510 MCK_VRN4M2NoV0,
5511 MCK_VRN4M2NoV0,
5512 MCK_VRN4M2NoV0,
5513 MCK_VRN4M2NoV0,
5514 MCK_VRN4M2NoV0,
5515 MCK_Reg130,
5516 MCK_VRN5M1NoV0,
5517 MCK_VRN5M1NoV0,
5518 MCK_VRN5M1NoV0,
5519 MCK_VRN5M1NoV0,
5520 MCK_VRN5M1NoV0,
5521 MCK_VRN5M1NoV0,
5522 MCK_VRN5M1NoV0,
5523 MCK_VRN5M1NoV0,
5524 MCK_VRN5M1NoV0,
5525 MCK_VRN5M1NoV0,
5526 MCK_VRN5M1NoV0,
5527 MCK_VRN5M1NoV0,
5528 MCK_VRN5M1NoV0,
5529 MCK_VRN5M1NoV0,
5530 MCK_VRN5M1NoV0,
5531 MCK_VRN5M1NoV0,
5532 MCK_VRN5M1NoV0,
5533 MCK_VRN5M1NoV0,
5534 MCK_VRN5M1NoV0,
5535 MCK_VRN5M1NoV0,
5536 MCK_VRN5M1NoV0,
5537 MCK_VRN5M1NoV0,
5538 MCK_VRN5M1NoV0,
5539 MCK_VRN5M1NoV0,
5540 MCK_VRN5M1NoV0,
5541 MCK_VRN5M1NoV0,
5542 MCK_VRN5M1NoV0,
5543 MCK_Reg133,
5544 MCK_VRN6M1NoV0,
5545 MCK_VRN6M1NoV0,
5546 MCK_VRN6M1NoV0,
5547 MCK_VRN6M1NoV0,
5548 MCK_VRN6M1NoV0,
5549 MCK_VRN6M1NoV0,
5550 MCK_VRN6M1NoV0,
5551 MCK_VRN6M1NoV0,
5552 MCK_VRN6M1NoV0,
5553 MCK_VRN6M1NoV0,
5554 MCK_VRN6M1NoV0,
5555 MCK_VRN6M1NoV0,
5556 MCK_VRN6M1NoV0,
5557 MCK_VRN6M1NoV0,
5558 MCK_VRN6M1NoV0,
5559 MCK_VRN6M1NoV0,
5560 MCK_VRN6M1NoV0,
5561 MCK_VRN6M1NoV0,
5562 MCK_VRN6M1NoV0,
5563 MCK_VRN6M1NoV0,
5564 MCK_VRN6M1NoV0,
5565 MCK_VRN6M1NoV0,
5566 MCK_VRN6M1NoV0,
5567 MCK_VRN6M1NoV0,
5568 MCK_VRN6M1NoV0,
5569 MCK_VRN6M1NoV0,
5570 MCK_Reg136,
5571 MCK_VRN7M1NoV0,
5572 MCK_VRN7M1NoV0,
5573 MCK_VRN7M1NoV0,
5574 MCK_VRN7M1NoV0,
5575 MCK_VRN7M1NoV0,
5576 MCK_VRN7M1NoV0,
5577 MCK_VRN7M1NoV0,
5578 MCK_VRN7M1NoV0,
5579 MCK_VRN7M1NoV0,
5580 MCK_VRN7M1NoV0,
5581 MCK_VRN7M1NoV0,
5582 MCK_VRN7M1NoV0,
5583 MCK_VRN7M1NoV0,
5584 MCK_VRN7M1NoV0,
5585 MCK_VRN7M1NoV0,
5586 MCK_VRN7M1NoV0,
5587 MCK_VRN7M1NoV0,
5588 MCK_VRN7M1NoV0,
5589 MCK_VRN7M1NoV0,
5590 MCK_VRN7M1NoV0,
5591 MCK_VRN7M1NoV0,
5592 MCK_VRN7M1NoV0,
5593 MCK_VRN7M1NoV0,
5594 MCK_VRN7M1NoV0,
5595 MCK_VRN7M1NoV0,
5596 MCK_Reg139,
5597 MCK_VRN8M1NoV0,
5598 MCK_VRN8M1NoV0,
5599 MCK_VRN8M1NoV0,
5600 MCK_VRN8M1NoV0,
5601 MCK_VRN8M1NoV0,
5602 MCK_VRN8M1NoV0,
5603 MCK_VRN8M1NoV0,
5604 MCK_VRN8M1NoV0,
5605 MCK_VRN8M1NoV0,
5606 MCK_VRN8M1NoV0,
5607 MCK_VRN8M1NoV0,
5608 MCK_VRN8M1NoV0,
5609 MCK_VRN8M1NoV0,
5610 MCK_VRN8M1NoV0,
5611 MCK_VRN8M1NoV0,
5612 MCK_VRN8M1NoV0,
5613 MCK_VRN8M1NoV0,
5614 MCK_VRN8M1NoV0,
5615 MCK_VRN8M1NoV0,
5616 MCK_VRN8M1NoV0,
5617 MCK_VRN8M1NoV0,
5618 MCK_VRN8M1NoV0,
5619 MCK_VRN8M1NoV0,
5620 MCK_VRN8M1NoV0,
5621 MCK_Reg142,
5622 };
5623
5624 MCRegister Reg = Operand.getReg();
5625 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
5626 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
5627 getDiagKindFromRegisterClass(Kind);
5628 }
5629
5630 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
5631 return getDiagKindFromRegisterClass(Kind);
5632
5633 return MCTargetAsmParser::Match_InvalidOperand;
5634}
5635
5636#ifndef NDEBUG
5637const char *getMatchClassName(MatchClassKind Kind) {
5638 switch (Kind) {
5639 case InvalidMatchClass: return "InvalidMatchClass";
5640 case OptionalMatchClass: return "OptionalMatchClass";
5641 case MCK__40_: return "MCK__40_";
5642 case MCK__41_: return "MCK__41_";
5643 case MCK_Reg142: return "MCK_Reg142";
5644 case MCK_Reg139: return "MCK_Reg139";
5645 case MCK_Reg136: return "MCK_Reg136";
5646 case MCK_Reg133: return "MCK_Reg133";
5647 case MCK_Reg130: return "MCK_Reg130";
5648 case MCK_Reg127: return "MCK_Reg127";
5649 case MCK_Reg124: return "MCK_Reg124";
5650 case MCK_Reg121: return "MCK_Reg121";
5651 case MCK_Reg118: return "MCK_Reg118";
5652 case MCK_Reg115: return "MCK_Reg115";
5653 case MCK_Reg112: return "MCK_Reg112";
5654 case MCK_Reg98: return "MCK_Reg98";
5655 case MCK_Reg95: return "MCK_Reg95";
5656 case MCK_Reg92: return "MCK_Reg92";
5657 case MCK_Reg73: return "MCK_Reg73";
5658 case MCK_Reg68: return "MCK_Reg68";
5659 case MCK_Reg65: return "MCK_Reg65";
5660 case MCK_Reg62: return "MCK_Reg62";
5661 case MCK_Reg59: return "MCK_Reg59";
5662 case MCK_Reg54: return "MCK_Reg54";
5663 case MCK_Reg45: return "MCK_Reg45";
5664 case MCK_Reg44: return "MCK_Reg44";
5665 case MCK_Reg38: return "MCK_Reg38";
5666 case MCK_Reg33: return "MCK_Reg33";
5667 case MCK_GPRX0: return "MCK_GPRX0";
5668 case MCK_GPRX1: return "MCK_GPRX1";
5669 case MCK_GPRX5: return "MCK_GPRX5";
5670 case MCK_GPRX7: return "MCK_GPRX7";
5671 case MCK_MR0: return "MCK_MR0";
5672 case MCK_SP: return "MCK_SP";
5673 case MCK_VMV0: return "MCK_VMV0";
5674 case MCK_anonymous_14630: return "MCK_anonymous_14630";
5675 case MCK_Reg55: return "MCK_Reg55";
5676 case MCK_Reg43: return "MCK_Reg43";
5677 case MCK_Reg29: return "MCK_Reg29";
5678 case MCK_GPRX1X5: return "MCK_GPRX1X5";
5679 case MCK_Reg78: return "MCK_Reg78";
5680 case MCK_VCSR: return "MCK_VCSR";
5681 case MCK_VRM8NoV0: return "MCK_VRM8NoV0";
5682 case MCK_Reg77: return "MCK_Reg77";
5683 case MCK_GPRPairC: return "MCK_GPRPairC";
5684 case MCK_TRM4: return "MCK_TRM4";
5685 case MCK_VRM8: return "MCK_VRM8";
5686 case MCK_Reg79: return "MCK_Reg79";
5687 case MCK_Reg80: return "MCK_Reg80";
5688 case MCK_Reg71: return "MCK_Reg71";
5689 case MCK_Reg58: return "MCK_Reg58";
5690 case MCK_Reg32: return "MCK_Reg32";
5691 case MCK_VRN2M4NoV0: return "MCK_VRN2M4NoV0";
5692 case MCK_Reg72: return "MCK_Reg72";
5693 case MCK_VRM4NoV0: return "MCK_VRM4NoV0";
5694 case MCK_VRN2M4: return "MCK_VRN2M4";
5695 case MCK_Reg107: return "MCK_Reg107";
5696 case MCK_Reg88: return "MCK_Reg88";
5697 case MCK_Reg57: return "MCK_Reg57";
5698 case MCK_Reg56: return "MCK_Reg56";
5699 case MCK_FPR16C: return "MCK_FPR16C";
5700 case MCK_FPR32C: return "MCK_FPR32C";
5701 case MCK_FPR64C: return "MCK_FPR64C";
5702 case MCK_GPRC: return "MCK_GPRC";
5703 case MCK_GPRF16C: return "MCK_GPRF16C";
5704 case MCK_GPRF32C: return "MCK_GPRF32C";
5705 case MCK_MR: return "MCK_MR";
5706 case MCK_SR07: return "MCK_SR07";
5707 case MCK_TRM2: return "MCK_TRM2";
5708 case MCK_VRM4: return "MCK_VRM4";
5709 case MCK_Reg75: return "MCK_Reg75";
5710 case MCK_Reg76: return "MCK_Reg76";
5711 case MCK_Reg69: return "MCK_Reg69";
5712 case MCK_Reg52: return "MCK_Reg52";
5713 case MCK_Reg26: return "MCK_Reg26";
5714 case MCK_VRN4M2NoV0: return "MCK_VRN4M2NoV0";
5715 case MCK_Reg70: return "MCK_Reg70";
5716 case MCK_Reg66: return "MCK_Reg66";
5717 case MCK_Reg53: return "MCK_Reg53";
5718 case MCK_Reg48: return "MCK_Reg48";
5719 case MCK_Reg22: return "MCK_Reg22";
5720 case MCK_GPRTCNonX7: return "MCK_GPRTCNonX7";
5721 case MCK_VRN3M2NoV0: return "MCK_VRN3M2NoV0";
5722 case MCK_VRN4M2: return "MCK_VRN4M2";
5723 case MCK_Reg67: return "MCK_Reg67";
5724 case MCK_Reg63: return "MCK_Reg63";
5725 case MCK_Reg49: return "MCK_Reg49";
5726 case MCK_GPRTC: return "MCK_GPRTC";
5727 case MCK_VRN2M2NoV0: return "MCK_VRN2M2NoV0";
5728 case MCK_VRN3M2: return "MCK_VRN3M2";
5729 case MCK_Reg61: return "MCK_Reg61";
5730 case MCK_GPRPairNoX0: return "MCK_GPRPairNoX0";
5731 case MCK_VRM2NoV0: return "MCK_VRM2NoV0";
5732 case MCK_VRN2M2: return "MCK_VRN2M2";
5733 case MCK_GPRPair: return "MCK_GPRPair";
5734 case MCK_TR: return "MCK_TR";
5735 case MCK_VRM2: return "MCK_VRM2";
5736 case MCK_Reg50: return "MCK_Reg50";
5737 case MCK_Reg24: return "MCK_Reg24";
5738 case MCK_VRN8M1NoV0: return "MCK_VRN8M1NoV0";
5739 case MCK_Reg51: return "MCK_Reg51";
5740 case MCK_Reg46: return "MCK_Reg46";
5741 case MCK_Reg20: return "MCK_Reg20";
5742 case MCK_GPRJALRNonX7: return "MCK_GPRJALRNonX7";
5743 case MCK_VRN7M1NoV0: return "MCK_VRN7M1NoV0";
5744 case MCK_VRN8M1: return "MCK_VRN8M1";
5745 case MCK_Reg47: return "MCK_Reg47";
5746 case MCK_GPRJALR: return "MCK_GPRJALR";
5747 case MCK_VRN6M1NoV0: return "MCK_VRN6M1NoV0";
5748 case MCK_VRN7M1: return "MCK_VRN7M1";
5749 case MCK_VRN5M1NoV0: return "MCK_VRN5M1NoV0";
5750 case MCK_VRN6M1: return "MCK_VRN6M1";
5751 case MCK_VRN4M1NoV0: return "MCK_VRN4M1NoV0";
5752 case MCK_VRN5M1: return "MCK_VRN5M1";
5753 case MCK_Reg41: return "MCK_Reg41";
5754 case MCK_Reg15: return "MCK_Reg15";
5755 case MCK_VRN3M1NoV0: return "MCK_VRN3M1NoV0";
5756 case MCK_VRN4M1: return "MCK_VRN4M1";
5757 case MCK_Reg42: return "MCK_Reg42";
5758 case MCK_Reg39: return "MCK_Reg39";
5759 case MCK_Reg36: return "MCK_Reg36";
5760 case MCK_Reg13: return "MCK_Reg13";
5761 case MCK_Reg10: return "MCK_Reg10";
5762 case MCK_GPRNoX0X2: return "MCK_GPRNoX0X2";
5763 case MCK_VRN2M1NoV0: return "MCK_VRN2M1NoV0";
5764 case MCK_VRN3M1: return "MCK_VRN3M1";
5765 case MCK_Reg40: return "MCK_Reg40";
5766 case MCK_Reg37: return "MCK_Reg37";
5767 case MCK_Reg34: return "MCK_Reg34";
5768 case MCK_GPRF16NoX0: return "MCK_GPRF16NoX0";
5769 case MCK_GPRF32NoX0: return "MCK_GPRF32NoX0";
5770 case MCK_GPRNoX0: return "MCK_GPRNoX0";
5771 case MCK_GPRNoX2: return "MCK_GPRNoX2";
5772 case MCK_GPRNoX31: return "MCK_GPRNoX31";
5773 case MCK_VRN2M1: return "MCK_VRN2M1";
5774 case MCK_VRNoV0: return "MCK_VRNoV0";
5775 case MCK_FPR128: return "MCK_FPR128";
5776 case MCK_FPR16: return "MCK_FPR16";
5777 case MCK_FPR256: return "MCK_FPR256";
5778 case MCK_FPR32: return "MCK_FPR32";
5779 case MCK_FPR64: return "MCK_FPR64";
5780 case MCK_GPR: return "MCK_GPR";
5781 case MCK_GPRF16: return "MCK_GPRF16";
5782 case MCK_GPRF32: return "MCK_GPRF32";
5783 case MCK_VR: return "MCK_VR";
5784 case MCK_YGPR: return "MCK_YGPR";
5785 case MCK_GPRAll: return "MCK_GPRAll";
5786 case MCK_AnyRegCOperand: return "MCK_AnyRegCOperand";
5787 case MCK_AnyRegOperand: return "MCK_AnyRegOperand";
5788 case MCK_BareSymbol: return "MCK_BareSymbol";
5789 case MCK_BareSymbolQC_E_LI: return "MCK_BareSymbolQC_E_LI";
5790 case MCK_CLUIImm: return "MCK_CLUIImm";
5791 case MCK_CSRSystemRegister: return "MCK_CSRSystemRegister";
5792 case MCK_RegReg: return "MCK_RegReg";
5793 case MCK_CallSymbol: return "MCK_CallSymbol";
5794 case MCK_FRMArg: return "MCK_FRMArg";
5795 case MCK_FRMArgLegacy: return "MCK_FRMArgLegacy";
5796 case MCK_FenceArg: return "MCK_FenceArg";
5797 case MCK_GPRAsFPR16: return "MCK_GPRAsFPR16";
5798 case MCK_GPRAsFPR32: return "MCK_GPRAsFPR32";
5799 case MCK_GPRF64AsFPR: return "MCK_GPRF64AsFPR";
5800 case MCK_GPRPairAsFPR: return "MCK_GPRPairAsFPR";
5801 case MCK_GPRPairCRV32: return "MCK_GPRPairCRV32";
5802 case MCK_GPRPairNoX0RV32: return "MCK_GPRPairNoX0RV32";
5803 case MCK_GPRPairRV32: return "MCK_GPRPairRV32";
5804 case MCK_GPRPairRV64: return "MCK_GPRPairRV64";
5805 case MCK_Imm: return "MCK_Imm";
5806 case MCK_ImmFour: return "MCK_ImmFour";
5807 case MCK_ImmThree: return "MCK_ImmThree";
5808 case MCK_ImmZero: return "MCK_ImmZero";
5809 case MCK_InsnCDirectiveOpcode: return "MCK_InsnCDirectiveOpcode";
5810 case MCK_InsnDirectiveOpcode: return "MCK_InsnDirectiveOpcode";
5811 case MCK_LoadFPImm: return "MCK_LoadFPImm";
5812 case MCK_NegStackAdj: return "MCK_NegStackAdj";
5813 case MCK_PseudoJumpSymbol: return "MCK_PseudoJumpSymbol";
5814 case MCK_QCAccessSymbol: return "MCK_QCAccessSymbol";
5815 case MCK_RTZArg: return "MCK_RTZArg";
5816 case MCK_RegList: return "MCK_RegList";
5817 case MCK_RegListS0: return "MCK_RegListS0";
5818 case MCK_RnumArg: return "MCK_RnumArg";
5819 case MCK_SImm10PLI_H: return "MCK_SImm10PLI_H";
5820 case MCK_SImm10PLI_W: return "MCK_SImm10PLI_W";
5821 case MCK_SImm10PLUI: return "MCK_SImm10PLUI";
5822 case MCK_SImm8PLI_B: return "MCK_SImm8PLI_B";
5823 case MCK_BareSImm21Lsb0: return "MCK_BareSImm21Lsb0";
5824 case MCK_StackAdj: return "MCK_StackAdj";
5825 case MCK_TLSDESCCallSymbol: return "MCK_TLSDESCCallSymbol";
5826 case MCK_TPRelAddSymbol: return "MCK_TPRelAddSymbol";
5827 case MCK_TileLambda: return "MCK_TileLambda";
5828 case MCK_UImmLog2XLen: return "MCK_UImmLog2XLen";
5829 case MCK_UImmLog2XLenNonZero: return "MCK_UImmLog2XLenNonZero";
5830 case MCK_RVVMaskRegOpOperand: return "MCK_RVVMaskRegOpOperand";
5831 case MCK_RVVMaskCarryInRegOpOperand: return "MCK_RVVMaskCarryInRegOpOperand";
5832 case MCK_RVVScaleRegOpOperand: return "MCK_RVVScaleRegOpOperand";
5833 case MCK_XSfmmVType: return "MCK_XSfmmVType";
5834 case MCK_YBNDSWImm: return "MCK_YBNDSWImm";
5835 case MCK_ZeroOffsetMemOpOperand: return "MCK_ZeroOffsetMemOpOperand";
5836 case MCK_UImm1: return "MCK_UImm1";
5837 case MCK_UImm2: return "MCK_UImm2";
5838 case MCK_UImm3: return "MCK_UImm3";
5839 case MCK_UImm4: return "MCK_UImm4";
5840 case MCK_UImm5: return "MCK_UImm5";
5841 case MCK_UImm6: return "MCK_UImm6";
5842 case MCK_UImm7: return "MCK_UImm7";
5843 case MCK_UImm8: return "MCK_UImm8";
5844 case MCK_UImm16: return "MCK_UImm16";
5845 case MCK_UImm32: return "MCK_UImm32";
5846 case MCK_UImm48: return "MCK_UImm48";
5847 case MCK_UImm64: return "MCK_UImm64";
5848 case MCK_SImm12: return "MCK_SImm12";
5849 case MCK_SImm12LO: return "MCK_SImm12LO";
5850 case MCK_BareSImm13Lsb0: return "MCK_BareSImm13Lsb0";
5851 case MCK_UImm20: return "MCK_UImm20";
5852 case MCK_UImm20LUI: return "MCK_UImm20LUI";
5853 case MCK_UImm20AUIPC: return "MCK_UImm20AUIPC";
5854 case MCK_ImmXLenLI: return "MCK_ImmXLenLI";
5855 case MCK_ImmXLenLI_Restricted: return "MCK_ImmXLenLI_Restricted";
5856 case MCK_SImm12Lsb00000: return "MCK_SImm12Lsb00000";
5857 case MCK_Imm5Zibi: return "MCK_Imm5Zibi";
5858 case MCK_VTypeI10: return "MCK_VTypeI10";
5859 case MCK_VTypeI11: return "MCK_VTypeI11";
5860 case MCK_SImm5: return "MCK_SImm5";
5861 case MCK_SImm5Plus1: return "MCK_SImm5Plus1";
5862 case MCK_UImm4Plus1: return "MCK_UImm4Plus1";
5863 case MCK_UImm5Plus1: return "MCK_UImm5Plus1";
5864 case MCK_UImm6Plus1: return "MCK_UImm6Plus1";
5865 case MCK_SImm6: return "MCK_SImm6";
5866 case MCK_SImm6NonZero: return "MCK_SImm6NonZero";
5867 case MCK_UImm7Lsb00: return "MCK_UImm7Lsb00";
5868 case MCK_UImm8Lsb00: return "MCK_UImm8Lsb00";
5869 case MCK_UImm8Lsb000: return "MCK_UImm8Lsb000";
5870 case MCK_BareSImm9Lsb0: return "MCK_BareSImm9Lsb0";
5871 case MCK_UImm9Lsb000: return "MCK_UImm9Lsb000";
5872 case MCK_UImm10Lsb00NonZero: return "MCK_UImm10Lsb00NonZero";
5873 case MCK_SImm10Lsb0000NonZero: return "MCK_SImm10Lsb0000NonZero";
5874 case MCK_BareSImm12Lsb0: return "MCK_BareSImm12Lsb0";
5875 case MCK_UImm2Lsb0: return "MCK_UImm2Lsb0";
5876 case MCK_UImm8GE32: return "MCK_UImm8GE32";
5877 case MCK_UImm7EqXLen: return "MCK_UImm7EqXLen";
5878 case MCK_UImm5Lsb0: return "MCK_UImm5Lsb0";
5879 case MCK_UImm6Lsb0: return "MCK_UImm6Lsb0";
5880 case MCK_UImm5NonZero: return "MCK_UImm5NonZero";
5881 case MCK_UImm5GT3: return "MCK_UImm5GT3";
5882 case MCK_UImm5GE6Plus1: return "MCK_UImm5GE6Plus1";
5883 case MCK_UImm5Slist: return "MCK_UImm5Slist";
5884 case MCK_UImm10: return "MCK_UImm10";
5885 case MCK_UImm11: return "MCK_UImm11";
5886 case MCK_UImm14Lsb00: return "MCK_UImm14Lsb00";
5887 case MCK_UImm16NonZero: return "MCK_UImm16NonZero";
5888 case MCK_SImm5NonZero: return "MCK_SImm5NonZero";
5889 case MCK_SImm11: return "MCK_SImm11";
5890 case MCK_SImm16: return "MCK_SImm16";
5891 case MCK_SImm16NonZero: return "MCK_SImm16NonZero";
5892 case MCK_SImm20LI: return "MCK_SImm20LI";
5893 case MCK_SImm26: return "MCK_SImm26";
5894 case MCK_BareSImm32: return "MCK_BareSImm32";
5895 case MCK_BareSImm32Lsb0: return "MCK_BareSImm32Lsb0";
5896 case MCK_UImm7Lsb000: return "MCK_UImm7Lsb000";
5897 case MCK_UImm9: return "MCK_UImm9";
5898 case MCK_BareSImm11Lsb0: return "MCK_BareSImm11Lsb0";
5899 case MCK_SImm18: return "MCK_SImm18";
5900 case MCK_SImm18Lsb0: return "MCK_SImm18Lsb0";
5901 case MCK_SImm19Lsb00: return "MCK_SImm19Lsb00";
5902 case MCK_SImm20Lsb000: return "MCK_SImm20Lsb000";
5903 case MCK_SImm10: return "MCK_SImm10";
5904 case NumMatchClassKinds: return "NumMatchClassKinds";
5905 }
5906 llvm_unreachable("unhandled MatchClassKind!");
5907}
5908
5909#endif // NDEBUG
5910FeatureBitset RISCVAsmParser::
5911ComputeAvailableFeatures(const FeatureBitset &FB) const {
5912 FeatureBitset Features;
5913 if (FB[RISCV::FeatureStdExtZibi])
5914 Features.set(Feature_HasStdExtZibiBit);
5915 if (FB[RISCV::FeatureStdExtZicbom])
5916 Features.set(Feature_HasStdExtZicbomBit);
5917 if (FB[RISCV::FeatureStdExtZicbop])
5918 Features.set(Feature_HasStdExtZicbopBit);
5919 if (FB[RISCV::FeatureStdExtZicboz])
5920 Features.set(Feature_HasStdExtZicbozBit);
5921 if (FB[RISCV::FeatureStdExtZicsr])
5922 Features.set(Feature_HasStdExtZicsrBit);
5923 if (FB[RISCV::FeatureStdExtZicond])
5924 Features.set(Feature_HasStdExtZicondBit);
5925 if (FB[RISCV::FeatureStdExtZifencei])
5926 Features.set(Feature_HasStdExtZifenceiBit);
5927 if (FB[RISCV::FeatureStdExtZihintpause])
5928 Features.set(Feature_HasStdExtZihintpauseBit);
5929 if (FB[RISCV::FeatureStdExtZihintntl])
5930 Features.set(Feature_HasStdExtZihintntlBit);
5931 if (FB[RISCV::FeatureStdExtZimop])
5932 Features.set(Feature_HasStdExtZimopBit);
5933 if (FB[RISCV::FeatureStdExtZicfiss])
5934 Features.set(Feature_HasStdExtZicfissBit);
5935 if (FB[RISCV::FeatureStdExtZilsd])
5936 Features.set(Feature_HasStdExtZilsdBit);
5937 if (FB[RISCV::FeatureStdExtZmmul])
5938 Features.set(Feature_HasStdExtZmmulBit);
5939 if (FB[RISCV::FeatureStdExtM])
5940 Features.set(Feature_HasStdExtMBit);
5941 if (FB[RISCV::FeatureStdExtZaamo])
5942 Features.set(Feature_HasStdExtZaamoBit);
5943 if (FB[RISCV::FeatureStdExtZalrsc])
5944 Features.set(Feature_HasStdExtZalrscBit);
5945 if (FB[RISCV::FeatureStdExtA])
5946 Features.set(Feature_HasStdExtABit);
5947 if (FB[RISCV::FeatureStdExtZtso])
5948 Features.set(Feature_HasStdExtZtsoBit);
5949 if (FB[RISCV::FeatureStdExtZabha])
5950 Features.set(Feature_HasStdExtZabhaBit);
5951 if (FB[RISCV::FeatureStdExtZacas])
5952 Features.set(Feature_HasStdExtZacasBit);
5953 if (FB[RISCV::FeatureStdExtZalasr])
5954 Features.set(Feature_HasStdExtZalasrBit);
5955 if (FB[RISCV::FeatureStdExtZawrs])
5956 Features.set(Feature_HasStdExtZawrsBit);
5957 if (FB[RISCV::FeatureStdExtF])
5958 Features.set(Feature_HasStdExtFBit);
5959 if (FB[RISCV::FeatureStdExtD])
5960 Features.set(Feature_HasStdExtDBit);
5961 if (FB[RISCV::FeatureStdExtQ])
5962 Features.set(Feature_HasStdExtQBit);
5963 if (FB[RISCV::FeatureStdExtZfhmin])
5964 Features.set(Feature_HasStdExtZfhminBit);
5965 if (FB[RISCV::FeatureStdExtZfh])
5966 Features.set(Feature_HasStdExtZfhBit);
5967 if (FB[RISCV::FeatureStdExtZfbfmin])
5968 Features.set(Feature_HasStdExtZfbfminBit);
5969 if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZfhmin] || FB[RISCV::FeatureStdExtZfbfmin])
5970 Features.set(Feature_HasHalfFPLoadStoreMoveBit);
5971 if (FB[RISCV::FeatureStdExtZfa])
5972 Features.set(Feature_HasStdExtZfaBit);
5973 if (FB[RISCV::FeatureStdExtZfinx])
5974 Features.set(Feature_HasStdExtZfinxBit);
5975 if (FB[RISCV::FeatureStdExtF] || FB[RISCV::FeatureStdExtZfinx])
5976 Features.set(Feature_HasStdExtFOrZfinxBit);
5977 if (FB[RISCV::FeatureStdExtZdinx])
5978 Features.set(Feature_HasStdExtZdinxBit);
5979 if (FB[RISCV::FeatureStdExtZhinxmin])
5980 Features.set(Feature_HasStdExtZhinxminBit);
5981 if (FB[RISCV::FeatureStdExtZhinx])
5982 Features.set(Feature_HasStdExtZhinxBit);
5983 if (FB[RISCV::FeatureStdExtZca])
5984 Features.set(Feature_HasStdExtZcaBit);
5985 if (FB[RISCV::FeatureStdExtZcb])
5986 Features.set(Feature_HasStdExtZcbBit);
5987 if (FB[RISCV::FeatureStdExtZcf])
5988 Features.set(Feature_HasStdExtZcfBit);
5989 if (FB[RISCV::FeatureStdExtZcd])
5990 Features.set(Feature_HasStdExtZcdBit);
5991 if (FB[RISCV::FeatureStdExtZclsd])
5992 Features.set(Feature_HasStdExtZclsdBit);
5993 if (FB[RISCV::FeatureStdExtZcmp])
5994 Features.set(Feature_HasStdExtZcmpBit);
5995 if (FB[RISCV::FeatureStdExtZcmt])
5996 Features.set(Feature_HasStdExtZcmtBit);
5997 if (FB[RISCV::FeatureStdExtZcmop])
5998 Features.set(Feature_HasStdExtZcmopBit);
5999 if (FB[RISCV::FeatureStdExtZba])
6000 Features.set(Feature_HasStdExtZbaBit);
6001 if (FB[RISCV::FeatureStdExtZbb])
6002 Features.set(Feature_HasStdExtZbbBit);
6003 if (!FB[RISCV::FeatureStdExtZbb])
6004 Features.set(Feature_NoStdExtZbbBit);
6005 if (FB[RISCV::FeatureStdExtZbs])
6006 Features.set(Feature_HasStdExtZbsBit);
6007 if (FB[RISCV::FeatureStdExtZbkb])
6008 Features.set(Feature_HasStdExtZbkbBit);
6009 if (!FB[RISCV::FeatureStdExtZbkb])
6010 Features.set(Feature_NoStdExtZbkbBit);
6011 if (FB[RISCV::FeatureStdExtZbkx])
6012 Features.set(Feature_HasStdExtZbkxBit);
6013 if (FB[RISCV::FeatureStdExtZbb] || FB[RISCV::FeatureStdExtZbkb])
6014 Features.set(Feature_HasStdExtZbbOrZbkbBit);
6015 if (FB[RISCV::FeatureStdExtZbkc])
6016 Features.set(Feature_HasStdExtZbkcBit);
6017 if (FB[RISCV::FeatureStdExtZbc])
6018 Features.set(Feature_HasStdExtZbcBit);
6019 if (FB[RISCV::FeatureStdExtZknd])
6020 Features.set(Feature_HasStdExtZkndBit);
6021 if (FB[RISCV::FeatureStdExtZkne])
6022 Features.set(Feature_HasStdExtZkneBit);
6023 if (FB[RISCV::FeatureStdExtZknd] || FB[RISCV::FeatureStdExtZkne])
6024 Features.set(Feature_HasStdExtZkndOrZkneBit);
6025 if (FB[RISCV::FeatureStdExtZknh])
6026 Features.set(Feature_HasStdExtZknhBit);
6027 if (FB[RISCV::FeatureStdExtZksed])
6028 Features.set(Feature_HasStdExtZksedBit);
6029 if (FB[RISCV::FeatureStdExtZksh])
6030 Features.set(Feature_HasStdExtZkshBit);
6031 if (FB[RISCV::FeatureStdExtZkr])
6032 Features.set(Feature_HasStdExtZkrBit);
6033 if (FB[RISCV::FeatureStdExtZvabd])
6034 Features.set(Feature_HasStdExtZvabdBit);
6035 if (FB[RISCV::FeatureStdExtZvqwdota8i] || FB[RISCV::FeatureStdExtZvqwdota16i])
6036 Features.set(Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit);
6037 if (FB[RISCV::FeatureStdExtZvfwdota16bf])
6038 Features.set(Feature_HasStdExtZvfwdota16bfBit);
6039 if (FB[RISCV::FeatureStdExtZvfqwdota8f])
6040 Features.set(Feature_HasStdExtZvfqwdota8fBit);
6041 if (FB[RISCV::FeatureStdExtZvfbfmin])
6042 Features.set(Feature_HasStdExtZvfbfminBit);
6043 if (FB[RISCV::FeatureStdExtZvfbfwma])
6044 Features.set(Feature_HasStdExtZvfbfwmaBit);
6045 if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZvfh])
6046 Features.set(Feature_HasStdExtZfhOrZvfhBit);
6047 if (FB[RISCV::FeatureStdExtZvfofp8min])
6048 Features.set(Feature_HasStdExtZvfofp8minBit);
6049 if (FB[RISCV::FeatureStdExtZvfbfmin] || FB[RISCV::FeatureStdExtZvfofp8min])
6050 Features.set(Feature_HasStdExtZvfbfminOrZvfofp8minBit);
6051 if (FB[RISCV::FeatureStdExtZvkb])
6052 Features.set(Feature_HasStdExtZvkbBit);
6053 if (FB[RISCV::FeatureStdExtZvbb])
6054 Features.set(Feature_HasStdExtZvbbBit);
6055 if (FB[RISCV::FeatureStdExtZvbc])
6056 Features.set(Feature_HasStdExtZvbcBit);
6057 if (FB[RISCV::FeatureStdExtZvbc] || FB[RISCV::FeatureStdExtZvbc32e])
6058 Features.set(Feature_HasStdExtZvbcOrZvbc32eBit);
6059 if (FB[RISCV::FeatureStdExtZvkg])
6060 Features.set(Feature_HasStdExtZvkgBit);
6061 if (FB[RISCV::FeatureStdExtZvkgs])
6062 Features.set(Feature_HasStdExtZvkgsBit);
6063 if (FB[RISCV::FeatureStdExtZvkned])
6064 Features.set(Feature_HasStdExtZvknedBit);
6065 if (FB[RISCV::FeatureStdExtZvknha])
6066 Features.set(Feature_HasStdExtZvknhaBit);
6067 if (FB[RISCV::FeatureStdExtZvknhb])
6068 Features.set(Feature_HasStdExtZvknhbBit);
6069 if (FB[RISCV::FeatureStdExtZvksed])
6070 Features.set(Feature_HasStdExtZvksedBit);
6071 if (FB[RISCV::FeatureStdExtZvksh])
6072 Features.set(Feature_HasStdExtZvkshBit);
6073 if (FB[RISCV::FeatureStdExtZvdot4a8i])
6074 Features.set(Feature_HasStdExtZvdot4a8iBit);
6075 if (FB[RISCV::FeatureStdExtZvzip])
6076 Features.set(Feature_HasStdExtZvzipBit);
6077 if (FB[RISCV::FeatureStdExtZvvmm])
6078 Features.set(Feature_HasStdExtZvvmmBit);
6079 if (FB[RISCV::FeatureStdExtZvvfmm])
6080 Features.set(Feature_HasStdExtZvvfmmBit);
6081 if (FB[RISCV::FeatureStdExtZvvmtls])
6082 Features.set(Feature_HasStdExtZvvmtlsBit);
6083 if (FB[RISCV::FeatureStdExtZvvmttls])
6084 Features.set(Feature_HasStdExtZvvmttlsBit);
6085 if (FB[RISCV::FeatureStdExtZvqwbdota8i] || FB[RISCV::FeatureStdExtZvqwbdota16i])
6086 Features.set(Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit);
6087 if (FB[RISCV::FeatureStdExtZvfwbdota16bf])
6088 Features.set(Feature_HasStdExtZvfwbdota16bfBit);
6089 if (FB[RISCV::FeatureStdExtZvfqwbdota8f])
6090 Features.set(Feature_HasStdExtZvfqwbdota8fBit);
6091 if (FB[RISCV::FeatureStdExtZvfbdota32f])
6092 Features.set(Feature_HasStdExtZvfbdota32fBit);
6093 if (FB[RISCV::FeatureStdExtZve32x])
6094 Features.set(Feature_HasVInstructionsBit);
6095 if (FB[RISCV::FeatureStdExtZve64x])
6096 Features.set(Feature_HasVInstructionsI64Bit);
6097 if (FB[RISCV::FeatureStdExtZve32f])
6098 Features.set(Feature_HasVInstructionsAnyFBit);
6099 if (FB[RISCV::FeatureStdExtZvfhmin] || FB[RISCV::FeatureStdExtZvfh])
6100 Features.set(Feature_HasVInstructionsF16MinimalBit);
6101 if (FB[RISCV::FeatureStdExtH])
6102 Features.set(Feature_HasStdExtHBit);
6103 if (FB[RISCV::FeatureStdExtSmrnmi])
6104 Features.set(Feature_HasStdExtSmrnmiBit);
6105 if (FB[RISCV::FeatureStdExtSvinval])
6106 Features.set(Feature_HasStdExtSvinvalBit);
6107 if (FB[RISCV::FeatureStdExtSmctr] || FB[RISCV::FeatureStdExtSsctr])
6108 Features.set(Feature_HasStdExtSmctrOrSsctrBit);
6109 if (FB[RISCV::FeatureStdExtP])
6110 Features.set(Feature_HasStdExtPBit);
6111 if (FB[RISCV::FeatureStdExtZbkb] || FB[RISCV::FeatureStdExtP])
6112 Features.set(Feature_HasStdExtZbkbOrPBit);
6113 if (FB[RISCV::FeatureStdExtY])
6114 Features.set(Feature_HasStdExtYBit);
6115 if (FB[RISCV::FeatureVendorXVentanaCondOps])
6116 Features.set(Feature_HasVendorXVentanaCondOpsBit);
6117 if (FB[RISCV::FeatureVendorXTHeadBa])
6118 Features.set(Feature_HasVendorXTHeadBaBit);
6119 if (FB[RISCV::FeatureVendorXTHeadBb])
6120 Features.set(Feature_HasVendorXTHeadBbBit);
6121 if (FB[RISCV::FeatureVendorXTHeadBs])
6122 Features.set(Feature_HasVendorXTHeadBsBit);
6123 if (FB[RISCV::FeatureVendorXTHeadCondMov])
6124 Features.set(Feature_HasVendorXTHeadCondMovBit);
6125 if (FB[RISCV::FeatureVendorXTHeadCmo])
6126 Features.set(Feature_HasVendorXTHeadCmoBit);
6127 if (FB[RISCV::FeatureVendorXTHeadFMemIdx])
6128 Features.set(Feature_HasVendorXTHeadFMemIdxBit);
6129 if (FB[RISCV::FeatureVendorXTHeadMac])
6130 Features.set(Feature_HasVendorXTHeadMacBit);
6131 if (FB[RISCV::FeatureVendorXTHeadMemIdx])
6132 Features.set(Feature_HasVendorXTHeadMemIdxBit);
6133 if (FB[RISCV::FeatureVendorXTHeadMemPair])
6134 Features.set(Feature_HasVendorXTHeadMemPairBit);
6135 if (FB[RISCV::FeatureVendorXTHeadSync])
6136 Features.set(Feature_HasVendorXTHeadSyncBit);
6137 if (FB[RISCV::FeatureVendorXTHeadVdot])
6138 Features.set(Feature_HasVendorXTHeadVdotBit);
6139 if (FB[RISCV::FeatureVendorXSfvcp])
6140 Features.set(Feature_HasVendorXSfvcpBit);
6141 if (FB[RISCV::FeatureVendorXSfmmbase])
6142 Features.set(Feature_HasVendorXSfmmbaseBit);
6143 if (FB[RISCV::FeatureVendorXSfmm32a8f])
6144 Features.set(Feature_HasVendorXSfmm32a8fBit);
6145 if (FB[RISCV::FeatureVendorXSfmm32a8i])
6146 Features.set(Feature_HasVendorXSfmm32a8iBit);
6147 if (FB[RISCV::FeatureVendorXSfmm32a16f] || FB[RISCV::FeatureVendorXSfmm32a32f] || FB[RISCV::FeatureVendorXSfmm64a64f])
6148 Features.set(Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit);
6149 if (FB[RISCV::FeatureVendorXSfvqmaccdod])
6150 Features.set(Feature_HasVendorXSfvqmaccdodBit);
6151 if (FB[RISCV::FeatureVendorXSfvqmaccqoq])
6152 Features.set(Feature_HasVendorXSfvqmaccqoqBit);
6153 if (FB[RISCV::FeatureVendorXSfvfwmaccqqq])
6154 Features.set(Feature_HasVendorXSfvfwmaccqqqBit);
6155 if (FB[RISCV::FeatureVendorXSfvfnrclipxfqf])
6156 Features.set(Feature_HasVendorXSfvfnrclipxfqfBit);
6157 if (FB[RISCV::FeatureVendorXSfvfbfexp16e] || FB[RISCV::FeatureVendorXSfvfexp16e] || FB[RISCV::FeatureVendorXSfvfexp32e])
6158 Features.set(Feature_HasVendorXSfvfexpAnyBit);
6159 if (FB[RISCV::FeatureVendorXSfvfexpa])
6160 Features.set(Feature_HasVendorXSfvfexpaBit);
6161 if (FB[RISCV::FeatureVendorXSiFivecdiscarddlone])
6162 Features.set(Feature_HasVendorXSiFivecdiscarddloneBit);
6163 if (FB[RISCV::FeatureVendorXSiFivecflushdlone])
6164 Features.set(Feature_HasVendorXSiFivecflushdloneBit);
6165 if (FB[RISCV::FeatureVendorXSfcease])
6166 Features.set(Feature_HasVendorXSfceaseBit);
6167 if (FB[RISCV::FeatureVendorXCVelw])
6168 Features.set(Feature_HasVendorXCVelwBit);
6169 if (FB[RISCV::FeatureVendorXCVbitmanip])
6170 Features.set(Feature_HasVendorXCVbitmanipBit);
6171 if (FB[RISCV::FeatureVendorXCVmac])
6172 Features.set(Feature_HasVendorXCVmacBit);
6173 if (FB[RISCV::FeatureVendorXCVmem])
6174 Features.set(Feature_HasVendorXCVmemBit);
6175 if (FB[RISCV::FeatureVendorXCValu])
6176 Features.set(Feature_HasVendorXCValuBit);
6177 if (FB[RISCV::FeatureVendorXCVsimd])
6178 Features.set(Feature_HasVendorXCVsimdBit);
6179 if (FB[RISCV::FeatureVendorXCVbi])
6180 Features.set(Feature_HasVendorXCVbiBit);
6181 if (FB[RISCV::FeatureVendorXMIPSCMov])
6182 Features.set(Feature_HasVendorXMIPSCMovBit);
6183 if (FB[RISCV::FeatureVendorXMIPSLSP])
6184 Features.set(Feature_HasVendorXMIPSLSPBit);
6185 if (FB[RISCV::FeatureVendorXMIPSCBOP])
6186 Features.set(Feature_HasVendorXMIPSCBOPBit);
6187 if (FB[RISCV::FeatureVendorXMIPSEXECTL])
6188 Features.set(Feature_HasVendorXMIPSEXECTLBit);
6189 if (FB[RISCV::FeatureVendorXwchc])
6190 Features.set(Feature_HasVendorXwchcBit);
6191 if (FB[RISCV::FeatureVendorXqccmp])
6192 Features.set(Feature_HasVendorXqccmpBit);
6193 if (FB[RISCV::FeatureVendorXqccmt])
6194 Features.set(Feature_HasVendorXqccmtBit);
6195 if (FB[RISCV::FeatureVendorXqcia])
6196 Features.set(Feature_HasVendorXqciaBit);
6197 if (FB[RISCV::FeatureVendorXqciac])
6198 Features.set(Feature_HasVendorXqciacBit);
6199 if (FB[RISCV::FeatureVendorXqcibi])
6200 Features.set(Feature_HasVendorXqcibiBit);
6201 if (FB[RISCV::FeatureVendorXqcibm])
6202 Features.set(Feature_HasVendorXqcibmBit);
6203 if (FB[RISCV::FeatureVendorXqcicli])
6204 Features.set(Feature_HasVendorXqcicliBit);
6205 if (FB[RISCV::FeatureVendorXqcicm])
6206 Features.set(Feature_HasVendorXqcicmBit);
6207 if (FB[RISCV::FeatureVendorXqcics])
6208 Features.set(Feature_HasVendorXqcicsBit);
6209 if (FB[RISCV::FeatureVendorXqcicsr])
6210 Features.set(Feature_HasVendorXqcicsrBit);
6211 if (FB[RISCV::FeatureVendorXqciint])
6212 Features.set(Feature_HasVendorXqciintBit);
6213 if (FB[RISCV::FeatureVendorXqciio])
6214 Features.set(Feature_HasVendorXqciioBit);
6215 if (FB[RISCV::FeatureVendorXqcilb])
6216 Features.set(Feature_HasVendorXqcilbBit);
6217 if (FB[RISCV::FeatureVendorXqcili])
6218 Features.set(Feature_HasVendorXqciliBit);
6219 if (FB[RISCV::FeatureVendorXqcilia])
6220 Features.set(Feature_HasVendorXqciliaBit);
6221 if (FB[RISCV::FeatureVendorXqcilo])
6222 Features.set(Feature_HasVendorXqciloBit);
6223 if (FB[RISCV::FeatureVendorXqcilsm])
6224 Features.set(Feature_HasVendorXqcilsmBit);
6225 if (FB[RISCV::FeatureVendorXqcisim])
6226 Features.set(Feature_HasVendorXqcisimBit);
6227 if (FB[RISCV::FeatureVendorXqcisls])
6228 Features.set(Feature_HasVendorXqcislsBit);
6229 if (FB[RISCV::FeatureVendorXqcisync])
6230 Features.set(Feature_HasVendorXqcisyncBit);
6231 if (FB[RISCV::FeatureVendorXAndesPerf])
6232 Features.set(Feature_HasVendorXAndesPerfBit);
6233 if (FB[RISCV::FeatureVendorXAndesBFHCvt])
6234 Features.set(Feature_HasVendorXAndesBFHCvtBit);
6235 if (FB[RISCV::FeatureVendorXAndesVBFHCvt])
6236 Features.set(Feature_HasVendorXAndesVBFHCvtBit);
6237 if (FB[RISCV::FeatureVendorXAndesVSIntH])
6238 Features.set(Feature_HasVendorXAndesVSIntHBit);
6239 if (FB[RISCV::FeatureVendorXAndesVSIntLoad])
6240 Features.set(Feature_HasVendorXAndesVSIntLoadBit);
6241 if (FB[RISCV::FeatureVendorXAndesVPackFPH])
6242 Features.set(Feature_HasVendorXAndesVPackFPHBit);
6243 if (FB[RISCV::FeatureVendorXAndesVDot])
6244 Features.set(Feature_HasVendorXAndesVDotBit);
6245 if (FB[RISCV::FeatureVendorXSMTVDot])
6246 Features.set(Feature_HasVendorXSMTVDotBit);
6247 if (FB[RISCV::FeatureVendorXAIFET])
6248 Features.set(Feature_HasXAIFETBit);
6249 if (FB[RISCV::FeatureVendorXCheriot])
6250 Features.set(Feature_HasCheriotBit);
6251 if (FB[RISCV::Feature64Bit])
6252 Features.set(Feature_IsRV64Bit);
6253 if (!FB[RISCV::Feature64Bit])
6254 Features.set(Feature_IsRV32Bit);
6255 return Features;
6256}
6257
6258static bool checkAsmTiedOperandConstraints(const RISCVAsmParser&AsmParser,
6259 unsigned Kind, const OperandVector &Operands,
6260 ArrayRef<unsigned> DefaultsOffset,
6261 uint64_t &ErrorInfo) {
6262 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
6263 const uint8_t *Converter = ConversionTable[Kind];
6264 for (const uint8_t *p = Converter; *p; p += 2) {
6265 switch (*p) {
6266 case CVT_Tied: {
6267 unsigned OpIdx = *(p + 1);
6268 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
6269 std::begin(TiedAsmOperandTable)) &&
6270 "Tied operand not found");
6271 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
6272 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
6273 OpndNum1 = OpndNum1 - DefaultsOffset[OpndNum1];
6274 OpndNum2 = OpndNum2 - DefaultsOffset[OpndNum2];
6275 if (OpndNum1 != OpndNum2) {
6276 auto &SrcOp1 = Operands[OpndNum1];
6277 auto &SrcOp2 = Operands[OpndNum2];
6278 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
6279 ErrorInfo = OpndNum2;
6280 return false;
6281 }
6282 }
6283 break;
6284 }
6285 default:
6286 break;
6287 }
6288 }
6289 return true;
6290}
6291
6292static const char MnemonicTable[] =
6293 "\007.insn_b\010.insn_ca\010.insn_cb\010.insn_ci\t.insn_ciw\010.insn_cj\010"
6294 ".insn_cl\010.insn_cr\010.insn_cs\t.insn_css\007.insn_i\007.insn_j\014.i"
6295 "nsn_qc.eai\013.insn_qc.eb\013.insn_qc.ei\013.insn_qc.ej\013.insn_qc.es\007"
6296 ".insn_r\010.insn_r4\007.insn_s\010.insn_sb\007.insn_u\010.insn_uj\004aa"
6297 "dd\005aaddu\003abs\004absw\003add\006add.uw\004addd\004addi\005addiw\004"
6298 "addw\010aes32dsi\taes32dsmi\010aes32esi\taes32esmi\007aes64ds\010aes64d"
6299 "sm\007aes64es\010aes64esm\007aes64im\taes64ks1i\010aes64ks2\015aif.amoa"
6300 "ddg.d\015aif.amoaddg.w\015aif.amoaddl.d\015aif.amoaddl.w\015aif.amoandg"
6301 ".d\015aif.amoandg.w\015aif.amoandl.d\015aif.amoandl.w\021aif.amocmpswap"
6302 "g.d\021aif.amocmpswapg.w\021aif.amocmpswapl.d\021aif.amocmpswapl.w\015a"
6303 "if.amomaxg.d\015aif.amomaxg.w\015aif.amomaxl.d\015aif.amomaxl.w\016aif."
6304 "amomaxug.d\016aif.amomaxug.w\016aif.amomaxul.d\016aif.amomaxul.w\015aif"
6305 ".amoming.d\015aif.amoming.w\015aif.amominl.d\015aif.amominl.w\016aif.am"
6306 "ominug.d\016aif.amominug.w\016aif.amominul.d\016aif.amominul.w\014aif.a"
6307 "moorg.d\014aif.amoorg.w\014aif.amoorl.d\014aif.amoorl.w\016aif.amoswapg"
6308 ".d\016aif.amoswapg.w\016aif.amoswapl.d\016aif.amoswapl.w\015aif.amoxorg"
6309 ".d\015aif.amoxorg.w\015aif.amoxorl.d\015aif.amoxorl.w\013aif.bitmixb\017"
6310 "aif.cubeface.ps\022aif.cubefaceidx.ps\020aif.cubesgnsc.ps\020aif.cubesg"
6311 "ntc.ps\013aif.fadd.pi\013aif.fadd.ps\014aif.faddi.pi\017aif.famoaddg.pi"
6312 "\017aif.famoaddl.pi\017aif.famoandg.pi\017aif.famoandl.pi\017aif.famoma"
6313 "xg.pi\017aif.famomaxg.ps\017aif.famomaxl.pi\017aif.famomaxl.ps\020aif.f"
6314 "amomaxug.pi\020aif.famomaxul.pi\017aif.famoming.pi\017aif.famoming.ps\017"
6315 "aif.famominl.pi\017aif.famominl.ps\020aif.famominug.pi\020aif.famominul"
6316 ".pi\016aif.famoorg.pi\016aif.famoorl.pi\020aif.famoswapg.pi\020aif.famo"
6317 "swapl.pi\017aif.famoxorg.pi\017aif.famoxorl.pi\013aif.fand.pi\014aif.fa"
6318 "ndi.pi\naif.fbc.ps\013aif.fbci.pi\013aif.fbci.ps\013aif.fbcx.ps\015aif."
6319 "fclass.ps\014aif.fcmov.ps\015aif.fcmovm.ps\017aif.fcvt.f10.ps\017aif.fc"
6320 "vt.f11.ps\017aif.fcvt.f16.ps\017aif.fcvt.ps.f10\017aif.fcvt.ps.f11\017a"
6321 "if.fcvt.ps.f16\016aif.fcvt.ps.pw\017aif.fcvt.ps.pwu\020aif.fcvt.ps.rast"
6322 "\020aif.fcvt.ps.sn16\017aif.fcvt.ps.sn8\020aif.fcvt.ps.un10\020aif.fcvt"
6323 ".ps.un16\017aif.fcvt.ps.un2\020aif.fcvt.ps.un24\017aif.fcvt.ps.un8\016a"
6324 "if.fcvt.pw.ps\017aif.fcvt.pwu.ps\020aif.fcvt.rast.ps\020aif.fcvt.sn16.p"
6325 "s\017aif.fcvt.sn8.ps\020aif.fcvt.un10.ps\020aif.fcvt.un16.ps\017aif.fcv"
6326 "t.un2.ps\020aif.fcvt.un24.ps\017aif.fcvt.un8.ps\013aif.fdiv.pi\013aif.f"
6327 "div.ps\014aif.fdivu.pi\naif.feq.pi\naif.feq.ps\013aif.feqm.ps\013aif.fe"
6328 "xp.ps\013aif.ffrc.ps\014aif.fg32b.ps\014aif.fg32h.ps\014aif.fg32w.ps\na"
6329 "if.fgb.ps\013aif.fgbg.ps\013aif.fgbl.ps\naif.fgh.ps\013aif.fghg.ps\013a"
6330 "if.fghl.ps\naif.fgw.ps\013aif.fgwg.ps\013aif.fgwl.ps\naif.fle.pi\naif.f"
6331 "le.ps\013aif.flem.ps\013aif.flog.ps\010aif.flq2\naif.flt.pi\naif.flt.ps"
6332 "\013aif.fltm.pi\013aif.fltm.ps\013aif.fltu.pi\naif.flw.ps\013aif.flwg.p"
6333 "s\013aif.flwl.ps\014aif.fmadd.ps\013aif.fmax.pi\013aif.fmax.ps\014aif.f"
6334 "maxu.pi\013aif.fmin.pi\013aif.fmin.ps\014aif.fminu.pi\014aif.fmsub.ps\013"
6335 "aif.fmul.pi\013aif.fmul.ps\014aif.fmulh.pi\015aif.fmulhu.pi\015aif.fmvs"
6336 ".x.ps\015aif.fmvz.x.ps\015aif.fnmadd.ps\015aif.fnmsub.ps\013aif.fnot.pi"
6337 "\naif.for.pi\020aif.fpackrepb.pi\020aif.fpackreph.pi\013aif.frcp.ps\021"
6338 "aif.frcp_fix.rast\013aif.frem.pi\014aif.fremu.pi\015aif.fround.ps\013ai"
6339 "f.frsq.ps\014aif.fsat8.pi\015aif.fsatu8.pi\015aif.fsc32b.ps\015aif.fsc3"
6340 "2h.ps\015aif.fsc32w.ps\013aif.fscb.ps\014aif.fscbg.ps\014aif.fscbl.ps\013"
6341 "aif.fsch.ps\014aif.fschg.ps\014aif.fschl.ps\013aif.fscw.ps\014aif.fscwg"
6342 ".ps\014aif.fscwl.ps\014aif.fsetm.pi\014aif.fsgnj.ps\015aif.fsgnjn.ps\015"
6343 "aif.fsgnjx.ps\013aif.fsin.ps\013aif.fsll.pi\014aif.fslli.pi\010aif.fsq2"
6344 "\014aif.fsqrt.ps\013aif.fsra.pi\014aif.fsrai.pi\013aif.fsrl.pi\014aif.f"
6345 "srli.pi\013aif.fsub.pi\013aif.fsub.ps\naif.fsw.ps\013aif.fswg.ps\015aif"
6346 ".fswizz.ps\013aif.fswl.ps\013aif.fxor.pi\013aif.maskand\013aif.masknot\n"
6347 "aif.maskor\014aif.maskpopc\021aif.maskpopc.rast\015aif.maskpopcz\013aif"
6348 ".maskxor\013aif.mov.m.x\014aif.mova.m.x\014aif.mova.x.m\taif.packb\007a"
6349 "if.sbg\007aif.sbl\007aif.shg\007aif.shl\010amoadd.b\013amoadd.b.aq\015a"
6350 "moadd.b.aqrl\013amoadd.b.rl\010amoadd.d\013amoadd.d.aq\015amoadd.d.aqrl"
6351 "\013amoadd.d.rl\010amoadd.h\013amoadd.h.aq\015amoadd.h.aqrl\013amoadd.h"
6352 ".rl\010amoadd.w\013amoadd.w.aq\015amoadd.w.aqrl\013amoadd.w.rl\010amoan"
6353 "d.b\013amoand.b.aq\015amoand.b.aqrl\013amoand.b.rl\010amoand.d\013amoan"
6354 "d.d.aq\015amoand.d.aqrl\013amoand.d.rl\010amoand.h\013amoand.h.aq\015am"
6355 "oand.h.aqrl\013amoand.h.rl\010amoand.w\013amoand.w.aq\015amoand.w.aqrl\013"
6356 "amoand.w.rl\010amocas.b\013amocas.b.aq\015amocas.b.aqrl\013amocas.b.rl\010"
6357 "amocas.d\013amocas.d.aq\015amocas.d.aqrl\013amocas.d.rl\010amocas.h\013"
6358 "amocas.h.aq\015amocas.h.aqrl\013amocas.h.rl\010amocas.q\013amocas.q.aq\015"
6359 "amocas.q.aqrl\013amocas.q.rl\010amocas.w\013amocas.w.aq\015amocas.w.aqr"
6360 "l\013amocas.w.rl\010amomax.b\013amomax.b.aq\015amomax.b.aqrl\013amomax."
6361 "b.rl\010amomax.d\013amomax.d.aq\015amomax.d.aqrl\013amomax.d.rl\010amom"
6362 "ax.h\013amomax.h.aq\015amomax.h.aqrl\013amomax.h.rl\010amomax.w\013amom"
6363 "ax.w.aq\015amomax.w.aqrl\013amomax.w.rl\tamomaxu.b\014amomaxu.b.aq\016a"
6364 "momaxu.b.aqrl\014amomaxu.b.rl\tamomaxu.d\014amomaxu.d.aq\016amomaxu.d.a"
6365 "qrl\014amomaxu.d.rl\tamomaxu.h\014amomaxu.h.aq\016amomaxu.h.aqrl\014amo"
6366 "maxu.h.rl\tamomaxu.w\014amomaxu.w.aq\016amomaxu.w.aqrl\014amomaxu.w.rl\010"
6367 "amomin.b\013amomin.b.aq\015amomin.b.aqrl\013amomin.b.rl\010amomin.d\013"
6368 "amomin.d.aq\015amomin.d.aqrl\013amomin.d.rl\010amomin.h\013amomin.h.aq\015"
6369 "amomin.h.aqrl\013amomin.h.rl\010amomin.w\013amomin.w.aq\015amomin.w.aqr"
6370 "l\013amomin.w.rl\tamominu.b\014amominu.b.aq\016amominu.b.aqrl\014amomin"
6371 "u.b.rl\tamominu.d\014amominu.d.aq\016amominu.d.aqrl\014amominu.d.rl\tam"
6372 "ominu.h\014amominu.h.aq\016amominu.h.aqrl\014amominu.h.rl\tamominu.w\014"
6373 "amominu.w.aq\016amominu.w.aqrl\014amominu.w.rl\007amoor.b\namoor.b.aq\014"
6374 "amoor.b.aqrl\namoor.b.rl\007amoor.d\namoor.d.aq\014amoor.d.aqrl\namoor."
6375 "d.rl\007amoor.h\namoor.h.aq\014amoor.h.aqrl\namoor.h.rl\007amoor.w\namo"
6376 "or.w.aq\014amoor.w.aqrl\namoor.w.rl\tamoswap.b\014amoswap.b.aq\016amosw"
6377 "ap.b.aqrl\014amoswap.b.rl\tamoswap.d\014amoswap.d.aq\016amoswap.d.aqrl\014"
6378 "amoswap.d.rl\tamoswap.h\014amoswap.h.aq\016amoswap.h.aqrl\014amoswap.h."
6379 "rl\tamoswap.w\014amoswap.w.aq\016amoswap.w.aqrl\014amoswap.w.rl\010amox"
6380 "or.b\013amoxor.b.aq\015amoxor.b.aqrl\013amoxor.b.rl\010amoxor.d\013amox"
6381 "or.d.aq\015amoxor.d.aqrl\013amoxor.d.rl\010amoxor.h\013amoxor.h.aq\015a"
6382 "moxor.h.aqrl\013amoxor.h.rl\010amoxor.w\013amoxor.w.aq\015amoxor.w.aqrl"
6383 "\013amoxor.w.rl\003and\004andi\004andn\004asub\005asubu\005auipc\004bcl"
6384 "r\005bclri\003beq\004beqi\004beqz\004bext\005bexti\003bge\004bgeu\004bg"
6385 "ez\003bgt\004bgtu\004bgtz\004binv\005binvi\003ble\004bleu\004blez\003bl"
6386 "t\004bltu\004bltz\003bne\004bnei\004bnez\005brev8\004bset\005bseti\005c"
6387 ".add\006c.addi\nc.addi16sp\nc.addi4spn\007c.addiw\006c.addw\005c.and\006"
6388 "c.andi\006c.beqz\006c.bnez\010c.ebreak\005c.fld\007c.fldsp\005c.flw\007"
6389 "c.flwsp\005c.fsd\007c.fsdsp\005c.fsw\007c.fswsp\003c.j\005c.jal\006c.ja"
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6717 ".vv\nvclmulh.vx\006vclz.v\014vcompress.vm\007vcpop.m\007vcpop.v\006vctz"
6718 ".v\007vdiv.vv\007vdiv.vx\010vdivu.vv\010vdivu.vx\tvdot4a.vv\tvdot4a.vx\013"
6719 "vdot4asu.vv\013vdot4asu.vx\nvdot4au.vv\nvdot4au.vx\013vdot4aus.vx\015vf"
6720 "8wimmacc.vv\014vf8wmmacc.vv\007vfabs.v\010vfadd.vf\010vfadd.vv\nvfbdota"
6721 ".vv\tvfclass.v\013vfcvt.f.x.v\014vfcvt.f.xu.v\017vfcvt.rtz.x.f.v\020vfc"
6722 "vt.rtz.xu.f.v\013vfcvt.x.f.v\014vfcvt.xu.f.v\010vfdiv.vf\010vfdiv.vv\010"
6723 "vfirst.m\tvfmacc.vf\tvfmacc.vv\tvfmadd.vf\tvfmadd.vv\010vfmax.vf\010vfm"
6724 "ax.vv\013vfmerge.vfm\010vfmin.vf\010vfmin.vv\nvfmmacc.vv\tvfmsac.vf\tvf"
6725 "msac.vv\tvfmsub.vf\tvfmsub.vv\010vfmul.vf\010vfmul.vv\010vfmv.f.s\010vf"
6726 "mv.s.f\010vfmv.v.f\014vfncvt.f.f.q\014vfncvt.f.f.w\014vfncvt.f.x.w\015v"
6727 "fncvt.f.xu.w\020vfncvt.rod.f.f.w\020vfncvt.rtz.x.f.w\021vfncvt.rtz.xu.f"
6728 ".w\020vfncvt.sat.f.f.q\014vfncvt.x.f.w\015vfncvt.xu.f.w\020vfncvtbf16.f"
6729 ".f.w\024vfncvtbf16.sat.f.f.w\007vfneg.v\nvfnmacc.vf\nvfnmacc.vv\nvfnmad"
6730 "d.vf\nvfnmadd.vv\nvfnmsac.vf\nvfnmsac.vv\nvfnmsub.vf\nvfnmsub.vv\014vfq"
6731 "immacc.vv\013vfqmmacc.vv\020vfqwbdota.alt.vv\014vfqwbdota.vv\017vfqwdot"
6732 "a.alt.vv\013vfqwdota.vv\tvfrdiv.vf\010vfrec7.v\013vfredmax.vs\013vfredm"
6733 "in.vs\014vfredosum.vs\014vfredusum.vs\nvfrsqrt7.v\tvfrsub.vf\tvfsgnj.vf"
6734 "\tvfsgnj.vv\nvfsgnjn.vf\nvfsgnjn.vv\nvfsgnjx.vf\nvfsgnjx.vv\017vfslide1"
6735 "down.vf\015vfslide1up.vf\010vfsqrt.v\010vfsub.vf\010vfsub.vv\tvfwadd.vf"
6736 "\tvfwadd.vv\tvfwadd.wf\tvfwadd.wv\013vfwbdota.vv\014vfwcvt.f.f.v\014vfw"
6737 "cvt.f.x.v\015vfwcvt.f.xu.v\020vfwcvt.rtz.x.f.v\021vfwcvt.rtz.xu.f.v\014"
6738 "vfwcvt.x.f.v\015vfwcvt.xu.f.v\020vfwcvtbf16.f.f.v\nvfwdota.vv\014vfwimm"
6739 "acc.vv\nvfwmacc.vf\nvfwmacc.vv\016vfwmaccbf16.vf\016vfwmaccbf16.vv\013v"
6740 "fwmmacc.vv\nvfwmsac.vf\nvfwmsac.vv\tvfwmul.vf\tvfwmul.vv\013vfwnmacc.vf"
6741 "\013vfwnmacc.vv\013vfwnmsac.vf\013vfwnmsac.vv\015vfwredosum.vs\015vfwre"
6742 "dusum.vs\tvfwsub.vf\tvfwsub.vv\tvfwsub.wf\tvfwsub.wv\010vghsh.vs\010vgh"
6743 "sh.vv\010vgmul.vs\010vgmul.vv\005vid.v\007viota.m\006vl1r.v\tvl1re16.v\t"
6744 "vl1re32.v\tvl1re64.v\010vl1re8.v\006vl2r.v\tvl2re16.v\tvl2re32.v\tvl2re"
6745 "64.v\010vl2re8.v\006vl4r.v\tvl4re16.v\tvl4re32.v\tvl4re64.v\010vl4re8.v"
6746 "\006vl8r.v\tvl8re16.v\tvl8re32.v\tvl8re64.v\010vl8re8.v\007vle16.v\tvle"
6747 "16ff.v\007vle32.v\tvle32ff.v\007vle64.v\tvle64ff.v\006vle8.v\010vle8ff."
6748 "v\005vlm.v\nvloxei16.v\nvloxei32.v\nvloxei64.v\tvloxei8.v\016vloxseg2ei"
6749 "16.v\016vloxseg2ei32.v\016vloxseg2ei64.v\015vloxseg2ei8.v\016vloxseg3ei"
6750 "16.v\016vloxseg3ei32.v\016vloxseg3ei64.v\015vloxseg3ei8.v\016vloxseg4ei"
6751 "16.v\016vloxseg4ei32.v\016vloxseg4ei64.v\015vloxseg4ei8.v\016vloxseg5ei"
6752 "16.v\016vloxseg5ei32.v\016vloxseg5ei64.v\015vloxseg5ei8.v\016vloxseg6ei"
6753 "16.v\016vloxseg6ei32.v\016vloxseg6ei64.v\015vloxseg6ei8.v\016vloxseg7ei"
6754 "16.v\016vloxseg7ei32.v\016vloxseg7ei64.v\015vloxseg7ei8.v\016vloxseg8ei"
6755 "16.v\016vloxseg8ei32.v\016vloxseg8ei64.v\015vloxseg8ei8.v\010vlse16.v\010"
6756 "vlse32.v\010vlse64.v\007vlse8.v\013vlseg2e16.v\015vlseg2e16ff.v\013vlse"
6757 "g2e32.v\015vlseg2e32ff.v\013vlseg2e64.v\015vlseg2e64ff.v\nvlseg2e8.v\014"
6758 "vlseg2e8ff.v\013vlseg3e16.v\015vlseg3e16ff.v\013vlseg3e32.v\015vlseg3e3"
6759 "2ff.v\013vlseg3e64.v\015vlseg3e64ff.v\nvlseg3e8.v\014vlseg3e8ff.v\013vl"
6760 "seg4e16.v\015vlseg4e16ff.v\013vlseg4e32.v\015vlseg4e32ff.v\013vlseg4e64"
6761 ".v\015vlseg4e64ff.v\nvlseg4e8.v\014vlseg4e8ff.v\013vlseg5e16.v\015vlseg"
6762 "5e16ff.v\013vlseg5e32.v\015vlseg5e32ff.v\013vlseg5e64.v\015vlseg5e64ff."
6763 "v\nvlseg5e8.v\014vlseg5e8ff.v\013vlseg6e16.v\015vlseg6e16ff.v\013vlseg6"
6764 "e32.v\015vlseg6e32ff.v\013vlseg6e64.v\015vlseg6e64ff.v\nvlseg6e8.v\014v"
6765 "lseg6e8ff.v\013vlseg7e16.v\015vlseg7e16ff.v\013vlseg7e32.v\015vlseg7e32"
6766 "ff.v\013vlseg7e64.v\015vlseg7e64ff.v\nvlseg7e8.v\014vlseg7e8ff.v\013vls"
6767 "eg8e16.v\015vlseg8e16ff.v\013vlseg8e32.v\015vlseg8e32ff.v\013vlseg8e64."
6768 "v\015vlseg8e64ff.v\nvlseg8e8.v\014vlseg8e8ff.v\014vlsseg2e16.v\014vlsse"
6769 "g2e32.v\014vlsseg2e64.v\013vlsseg2e8.v\014vlsseg3e16.v\014vlsseg3e32.v\014"
6770 "vlsseg3e64.v\013vlsseg3e8.v\014vlsseg4e16.v\014vlsseg4e32.v\014vlsseg4e"
6771 "64.v\013vlsseg4e8.v\014vlsseg5e16.v\014vlsseg5e32.v\014vlsseg5e64.v\013"
6772 "vlsseg5e8.v\014vlsseg6e16.v\014vlsseg6e32.v\014vlsseg6e64.v\013vlsseg6e"
6773 "8.v\014vlsseg7e16.v\014vlsseg7e32.v\014vlsseg7e64.v\013vlsseg7e8.v\014v"
6774 "lsseg8e16.v\014vlsseg8e32.v\014vlsseg8e64.v\013vlsseg8e8.v\nvluxei16.v\n"
6775 "vluxei32.v\nvluxei64.v\tvluxei8.v\016vluxseg2ei16.v\016vluxseg2ei32.v\016"
6776 "vluxseg2ei64.v\015vluxseg2ei8.v\016vluxseg3ei16.v\016vluxseg3ei32.v\016"
6777 "vluxseg3ei64.v\015vluxseg3ei8.v\016vluxseg4ei16.v\016vluxseg4ei32.v\016"
6778 "vluxseg4ei64.v\015vluxseg4ei8.v\016vluxseg5ei16.v\016vluxseg5ei32.v\016"
6779 "vluxseg5ei64.v\015vluxseg5ei8.v\016vluxseg6ei16.v\016vluxseg6ei32.v\016"
6780 "vluxseg6ei64.v\015vluxseg6ei8.v\016vluxseg7ei16.v\016vluxseg7ei32.v\016"
6781 "vluxseg7ei64.v\015vluxseg7ei8.v\016vluxseg8ei16.v\016vluxseg8ei32.v\016"
6782 "vluxseg8ei64.v\015vluxseg8ei8.v\010vmacc.vv\010vmacc.vx\010vmadc.vi\tvm"
6783 "adc.vim\010vmadc.vv\tvmadc.vvm\010vmadc.vx\tvmadc.vxm\010vmadd.vv\010vm"
6784 "add.vx\010vmand.mm\tvmandn.mm\007vmax.vv\007vmax.vx\010vmaxu.vv\010vmax"
6785 "u.vx\007vmclr.m\nvmerge.vim\nvmerge.vvm\nvmerge.vxm\010vmfeq.vf\010vmfe"
6786 "q.vv\010vmfge.vf\010vmfge.vv\010vmfgt.vf\010vmfgt.vv\010vmfle.vf\010vmf"
6787 "le.vv\010vmflt.vf\010vmflt.vv\010vmfne.vf\010vmfne.vv\007vmin.vv\007vmi"
6788 "n.vx\010vminu.vv\010vminu.vx\tvmmacc.vv\006vmmv.m\tvmnand.mm\010vmnor.m"
6789 "m\007vmnot.m\007vmor.mm\010vmorn.mm\010vmsbc.vv\tvmsbc.vvm\010vmsbc.vx\t"
6790 "vmsbc.vxm\007vmsbf.m\010vmseq.vi\010vmseq.vv\010vmseq.vx\007vmset.m\010"
6791 "vmsge.vi\010vmsge.vv\010vmsge.vx\tvmsgeu.vi\tvmsgeu.vv\tvmsgeu.vx\010vm"
6792 "sgt.vi\010vmsgt.vv\010vmsgt.vx\tvmsgtu.vi\tvmsgtu.vv\tvmsgtu.vx\007vmsi"
6793 "f.m\010vmsle.vi\010vmsle.vv\010vmsle.vx\tvmsleu.vi\tvmsleu.vv\tvmsleu.v"
6794 "x\010vmslt.vi\010vmslt.vv\010vmslt.vx\tvmsltu.vi\tvmsltu.vv\tvmsltu.vx\010"
6795 "vmsne.vi\010vmsne.vv\010vmsne.vx\007vmsof.m\006vmtl.v\006vmts.v\007vmtt"
6796 "l.v\007vmtts.v\007vmul.vv\007vmul.vx\010vmulh.vv\010vmulh.vx\nvmulhsu.v"
6797 "v\nvmulhsu.vx\tvmulhu.vv\tvmulhu.vx\007vmv.s.x\007vmv.v.i\007vmv.v.v\007"
6798 "vmv.v.x\007vmv.x.s\007vmv1r.v\007vmv2r.v\007vmv4r.v\007vmv8r.v\tvmxnor."
6799 "mm\010vmxor.mm\tvnclip.wi\tvnclip.wv\tvnclip.wx\nvnclipu.wi\nvnclipu.wv"
6800 "\nvnclipu.wx\013vncvt.x.x.w\006vneg.v\tvnmsac.vv\tvnmsac.vx\tvnmsub.vv\t"
6801 "vnmsub.vx\006vnot.v\010vnsra.wi\010vnsra.wv\010vnsra.wx\010vnsrl.wi\010"
6802 "vnsrl.wv\010vnsrl.wx\006vor.vi\006vor.vv\006vor.vx\tvpaire.vv\tvpairo.v"
6803 "v\nvqmmacc.vv\014vqwbdotas.vv\014vqwbdotau.vv\013vqwdotas.vv\013vqwdota"
6804 "u.vv\nvredand.vs\nvredmax.vs\013vredmaxu.vs\nvredmin.vs\013vredminu.vs\t"
6805 "vredor.vs\nvredsum.vs\nvredxor.vs\007vrem.vv\007vrem.vx\010vremu.vv\010"
6806 "vremu.vx\007vrev8.v\013vrgather.vi\013vrgather.vv\013vrgather.vx\017vrg"
6807 "atherei16.vv\007vrol.vv\007vrol.vx\007vror.vi\007vror.vv\007vror.vx\010"
6808 "vrsub.vi\010vrsub.vx\006vs1r.v\006vs2r.v\006vs4r.v\006vs8r.v\010vsadd.v"
6809 "i\010vsadd.vv\010vsadd.vx\tvsaddu.vi\tvsaddu.vv\tvsaddu.vx\010vsbc.vvm\010"
6810 "vsbc.vxm\007vse16.v\007vse32.v\007vse64.v\006vse8.v\010vsetivli\006vset"
6811 "vl\007vsetvli\tvsext.vf2\tvsext.vf4\tvsext.vf8\nvsha2ch.vv\nvsha2cl.vv\n"
6812 "vsha2ms.vv\016vslide1down.vx\014vslide1up.vx\015vslidedown.vi\015vslide"
6813 "down.vx\013vslideup.vi\013vslideup.vx\007vsll.vi\007vsll.vv\007vsll.vx\005"
6814 "vsm.v\010vsm3c.vi\tvsm3me.vv\010vsm4k.vi\010vsm4r.vs\010vsm4r.vv\010vsm"
6815 "ul.vv\010vsmul.vx\nvsoxei16.v\nvsoxei32.v\nvsoxei64.v\tvsoxei8.v\016vso"
6816 "xseg2ei16.v\016vsoxseg2ei32.v\016vsoxseg2ei64.v\015vsoxseg2ei8.v\016vso"
6817 "xseg3ei16.v\016vsoxseg3ei32.v\016vsoxseg3ei64.v\015vsoxseg3ei8.v\016vso"
6818 "xseg4ei16.v\016vsoxseg4ei32.v\016vsoxseg4ei64.v\015vsoxseg4ei8.v\016vso"
6819 "xseg5ei16.v\016vsoxseg5ei32.v\016vsoxseg5ei64.v\015vsoxseg5ei8.v\016vso"
6820 "xseg6ei16.v\016vsoxseg6ei32.v\016vsoxseg6ei64.v\015vsoxseg6ei8.v\016vso"
6821 "xseg7ei16.v\016vsoxseg7ei32.v\016vsoxseg7ei64.v\015vsoxseg7ei8.v\016vso"
6822 "xseg8ei16.v\016vsoxseg8ei32.v\016vsoxseg8ei64.v\015vsoxseg8ei8.v\007vsr"
6823 "a.vi\007vsra.vv\007vsra.vx\007vsrl.vi\007vsrl.vv\007vsrl.vx\010vsse16.v"
6824 "\010vsse32.v\010vsse64.v\007vsse8.v\013vsseg2e16.v\013vsseg2e32.v\013vs"
6825 "seg2e64.v\nvsseg2e8.v\013vsseg3e16.v\013vsseg3e32.v\013vsseg3e64.v\nvss"
6826 "eg3e8.v\013vsseg4e16.v\013vsseg4e32.v\013vsseg4e64.v\nvsseg4e8.v\013vss"
6827 "eg5e16.v\013vsseg5e32.v\013vsseg5e64.v\nvsseg5e8.v\013vsseg6e16.v\013vs"
6828 "seg6e32.v\013vsseg6e64.v\nvsseg6e8.v\013vsseg7e16.v\013vsseg7e32.v\013v"
6829 "sseg7e64.v\nvsseg7e8.v\013vsseg8e16.v\013vsseg8e32.v\013vsseg8e64.v\nvs"
6830 "seg8e8.v\010vssra.vi\010vssra.vv\010vssra.vx\010vssrl.vi\010vssrl.vv\010"
6831 "vssrl.vx\014vssseg2e16.v\014vssseg2e32.v\014vssseg2e64.v\013vssseg2e8.v"
6832 "\014vssseg3e16.v\014vssseg3e32.v\014vssseg3e64.v\013vssseg3e8.v\014vsss"
6833 "eg4e16.v\014vssseg4e32.v\014vssseg4e64.v\013vssseg4e8.v\014vssseg5e16.v"
6834 "\014vssseg5e32.v\014vssseg5e64.v\013vssseg5e8.v\014vssseg6e16.v\014vsss"
6835 "eg6e32.v\014vssseg6e64.v\013vssseg6e8.v\014vssseg7e16.v\014vssseg7e32.v"
6836 "\014vssseg7e64.v\013vssseg7e8.v\014vssseg8e16.v\014vssseg8e32.v\014vsss"
6837 "eg8e64.v\013vssseg8e8.v\010vssub.vv\010vssub.vx\tvssubu.vv\tvssubu.vx\007"
6838 "vsub.vv\007vsub.vx\nvsuxei16.v\nvsuxei32.v\nvsuxei64.v\tvsuxei8.v\016vs"
6839 "uxseg2ei16.v\016vsuxseg2ei32.v\016vsuxseg2ei64.v\015vsuxseg2ei8.v\016vs"
6840 "uxseg3ei16.v\016vsuxseg3ei32.v\016vsuxseg3ei64.v\015vsuxseg3ei8.v\016vs"
6841 "uxseg4ei16.v\016vsuxseg4ei32.v\016vsuxseg4ei64.v\015vsuxseg4ei8.v\016vs"
6842 "uxseg5ei16.v\016vsuxseg5ei32.v\016vsuxseg5ei64.v\015vsuxseg5ei8.v\016vs"
6843 "uxseg6ei16.v\016vsuxseg6ei32.v\016vsuxseg6ei64.v\015vsuxseg6ei8.v\016vs"
6844 "uxseg7ei16.v\016vsuxseg7ei32.v\016vsuxseg7ei64.v\015vsuxseg7ei8.v\016vs"
6845 "uxseg8ei16.v\016vsuxseg8ei32.v\016vsuxseg8ei64.v\015vsuxseg8ei8.v\010vt"
6846 ".maskc\tvt.maskcn\tvunzipe.v\tvunzipo.v\tvwabda.vv\nvwabdau.vv\010vwadd"
6847 ".vv\010vwadd.vx\010vwadd.wv\010vwadd.wx\tvwaddu.vv\tvwaddu.vx\tvwaddu.w"
6848 "v\tvwaddu.wx\013vwcvt.x.x.v\014vwcvtu.x.x.v\tvwmacc.vv\tvwmacc.vx\013vw"
6849 "maccsu.vv\013vwmaccsu.vx\nvwmaccu.vv\nvwmaccu.vx\013vwmaccus.vx\nvwmmac"
6850 "c.vv\010vwmul.vv\010vwmul.vx\nvwmulsu.vv\nvwmulsu.vx\tvwmulu.vv\tvwmulu"
6851 ".vx\013vwredsum.vs\014vwredsumu.vs\010vwsll.vi\010vwsll.vv\010vwsll.vx\010"
6852 "vwsub.vv\010vwsub.vx\010vwsub.wv\010vwsub.wx\tvwsubu.vv\tvwsubu.vx\tvws"
6853 "ubu.wv\tvwsubu.wx\007vxor.vi\007vxor.vv\007vxor.vx\tvzext.vf2\tvzext.vf"
6854 "4\tvzext.vf8\007vzip.vv\004wadd\005wadda\006waddau\005waddu\003wfi\005w"
6855 "macc\007wmaccsu\006wmaccu\004wmul\006wmulsu\005wmulu\007wrs.nto\007wrs."
6856 "sto\004wsla\005wslai\004wsll\005wslli\004wsub\005wsuba\006wsubau\005wsu"
6857 "bu\007wzip16p\006wzip8p\004xnor\003xor\004xori\006xperm4\006xperm8\004y"
6858 "add\005yaddi\006yaddrw\006yamask\006ybaser\004ybld\007ybndsrw\006ybndsw"
6859 "\007ybndswi\003yeq\004yhir\005ylenr\003ymv\006ypermc\006ypermr\003yss\010"
6860 "ysunseal\005ytagr\005ytopr\006ytyper\006zext.b\006zext.h\006zext.w\003z"
6861 "ip\007zip16hp\006zip16p\006zip8hp\005zip8p";
6862
6863// Feature bitsets.
6864enum : uint8_t {
6865 AMFBS_None,
6866 AMFBS_HasHalfFPLoadStoreMove,
6867 AMFBS_HasStdExtD,
6868 AMFBS_HasStdExtF,
6869 AMFBS_HasStdExtFOrZfinx,
6870 AMFBS_HasStdExtH,
6871 AMFBS_HasStdExtM,
6872 AMFBS_HasStdExtP,
6873 AMFBS_HasStdExtQ,
6874 AMFBS_HasStdExtSmctrOrSsctr,
6875 AMFBS_HasStdExtSmrnmi,
6876 AMFBS_HasStdExtSvinval,
6877 AMFBS_HasStdExtY,
6878 AMFBS_HasStdExtZaamo,
6879 AMFBS_HasStdExtZabha,
6880 AMFBS_HasStdExtZacas,
6881 AMFBS_HasStdExtZalasr,
6882 AMFBS_HasStdExtZalrsc,
6883 AMFBS_HasStdExtZawrs,
6884 AMFBS_HasStdExtZba,
6885 AMFBS_HasStdExtZbb,
6886 AMFBS_HasStdExtZbbOrZbkb,
6887 AMFBS_HasStdExtZbc,
6888 AMFBS_HasStdExtZbkb,
6889 AMFBS_HasStdExtZbkbOrP,
6890 AMFBS_HasStdExtZbkc,
6891 AMFBS_HasStdExtZbkx,
6892 AMFBS_HasStdExtZbs,
6893 AMFBS_HasStdExtZca,
6894 AMFBS_HasStdExtZcb,
6895 AMFBS_HasStdExtZcd,
6896 AMFBS_HasStdExtZcmop,
6897 AMFBS_HasStdExtZcmp,
6898 AMFBS_HasStdExtZcmt,
6899 AMFBS_HasStdExtZfa,
6900 AMFBS_HasStdExtZfbfmin,
6901 AMFBS_HasStdExtZfh,
6902 AMFBS_HasStdExtZfhmin,
6903 AMFBS_HasStdExtZfinx,
6904 AMFBS_HasStdExtZhinx,
6905 AMFBS_HasStdExtZhinxmin,
6906 AMFBS_HasStdExtZibi,
6907 AMFBS_HasStdExtZicbom,
6908 AMFBS_HasStdExtZicboz,
6909 AMFBS_HasStdExtZicfiss,
6910 AMFBS_HasStdExtZicond,
6911 AMFBS_HasStdExtZimop,
6912 AMFBS_HasStdExtZknh,
6913 AMFBS_HasStdExtZksed,
6914 AMFBS_HasStdExtZksh,
6915 AMFBS_HasStdExtZmmul,
6916 AMFBS_HasStdExtZvabd,
6917 AMFBS_HasStdExtZvbb,
6918 AMFBS_HasStdExtZvbcOrZvbc32e,
6919 AMFBS_HasStdExtZvdot4a8i,
6920 AMFBS_HasStdExtZvfbdota32f,
6921 AMFBS_HasStdExtZvfbfminOrZvfofp8min,
6922 AMFBS_HasStdExtZvfbfwma,
6923 AMFBS_HasStdExtZvfofp8min,
6924 AMFBS_HasStdExtZvfqwbdota8f,
6925 AMFBS_HasStdExtZvfqwdota8f,
6926 AMFBS_HasStdExtZvfwbdota16bf,
6927 AMFBS_HasStdExtZvfwdota16bf,
6928 AMFBS_HasStdExtZvkb,
6929 AMFBS_HasStdExtZvkg,
6930 AMFBS_HasStdExtZvkgs,
6931 AMFBS_HasStdExtZvkned,
6932 AMFBS_HasStdExtZvknha,
6933 AMFBS_HasStdExtZvksed,
6934 AMFBS_HasStdExtZvksh,
6935 AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i,
6936 AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i,
6937 AMFBS_HasStdExtZvvfmm,
6938 AMFBS_HasStdExtZvvmm,
6939 AMFBS_HasStdExtZvvmtls,
6940 AMFBS_HasStdExtZvvmttls,
6941 AMFBS_HasStdExtZvzip,
6942 AMFBS_HasVInstructions,
6943 AMFBS_HasVInstructionsAnyF,
6944 AMFBS_HasVInstructionsI64,
6945 AMFBS_HasVendorXAndesBFHCvt,
6946 AMFBS_HasVendorXAndesPerf,
6947 AMFBS_HasVendorXAndesVBFHCvt,
6948 AMFBS_HasVendorXAndesVDot,
6949 AMFBS_HasVendorXAndesVPackFPH,
6950 AMFBS_HasVendorXAndesVSIntH,
6951 AMFBS_HasVendorXAndesVSIntLoad,
6952 AMFBS_HasVendorXMIPSCBOP,
6953 AMFBS_HasVendorXMIPSCMov,
6954 AMFBS_HasVendorXMIPSEXECTL,
6955 AMFBS_HasVendorXMIPSLSP,
6956 AMFBS_HasVendorXSfcease,
6957 AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f,
6958 AMFBS_HasVendorXSfmm32a8f,
6959 AMFBS_HasVendorXSfmm32a8i,
6960 AMFBS_HasVendorXSfmmbase,
6961 AMFBS_HasVendorXSfvcp,
6962 AMFBS_HasVendorXSfvfexpAny,
6963 AMFBS_HasVendorXSfvfexpa,
6964 AMFBS_HasVendorXSfvfnrclipxfqf,
6965 AMFBS_HasVendorXSfvfwmaccqqq,
6966 AMFBS_HasVendorXSfvqmaccdod,
6967 AMFBS_HasVendorXSfvqmaccqoq,
6968 AMFBS_HasVendorXSiFivecdiscarddlone,
6969 AMFBS_HasVendorXSiFivecflushdlone,
6970 AMFBS_HasVendorXTHeadBa,
6971 AMFBS_HasVendorXTHeadBb,
6972 AMFBS_HasVendorXTHeadBs,
6973 AMFBS_HasVendorXTHeadCmo,
6974 AMFBS_HasVendorXTHeadCondMov,
6975 AMFBS_HasVendorXTHeadMac,
6976 AMFBS_HasVendorXTHeadMemIdx,
6977 AMFBS_HasVendorXTHeadMemPair,
6978 AMFBS_HasVendorXTHeadSync,
6979 AMFBS_HasVendorXTHeadVdot,
6980 AMFBS_HasVendorXVentanaCondOps,
6981 AMFBS_HasVendorXqccmp,
6982 AMFBS_HasVendorXqccmt,
6983 AMFBS_HasVendorXwchc,
6984 AMFBS_HasXAIFET,
6985 AMFBS_IsRV32,
6986 AMFBS_IsRV64,
6987 AMFBS_HasStdExtD_IsRV64,
6988 AMFBS_HasStdExtF_IsRV64,
6989 AMFBS_HasStdExtM_IsRV64,
6990 AMFBS_HasStdExtP_IsRV32,
6991 AMFBS_HasStdExtP_IsRV64,
6992 AMFBS_HasStdExtQ_IsRV64,
6993 AMFBS_HasStdExtY_IsRV32,
6994 AMFBS_HasStdExtY_IsRV64,
6995 AMFBS_HasStdExtZaamo_IsRV64,
6996 AMFBS_HasStdExtZabha_HasStdExtZacas,
6997 AMFBS_HasStdExtZacas_IsRV32,
6998 AMFBS_HasStdExtZacas_IsRV64,
6999 AMFBS_HasStdExtZalasr_IsRV64,
7000 AMFBS_HasStdExtZalrsc_IsRV64,
7001 AMFBS_HasStdExtZba_IsRV64,
7002 AMFBS_HasStdExtZbb_IsRV64,
7003 AMFBS_HasStdExtZbbOrZbkb_IsRV32,
7004 AMFBS_HasStdExtZbbOrZbkb_IsRV64,
7005 AMFBS_HasStdExtZbkb_IsRV32,
7006 AMFBS_HasStdExtZbkb_IsRV64,
7007 AMFBS_HasStdExtZca_IsRV32,
7008 AMFBS_HasStdExtZca_IsRV64,
7009 AMFBS_HasStdExtZcb_HasStdExtZbb,
7010 AMFBS_HasStdExtZcb_HasStdExtZmmul,
7011 AMFBS_HasStdExtZcf_IsRV32,
7012 AMFBS_HasStdExtZclsd_IsRV32,
7013 AMFBS_HasStdExtZdinx_IsRV32,
7014 AMFBS_HasStdExtZdinx_IsRV64,
7015 AMFBS_HasStdExtZfa_HasStdExtD,
7016 AMFBS_HasStdExtZfa_HasStdExtQ,
7017 AMFBS_HasStdExtZfa_HasStdExtZfh,
7018 AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh,
7019 AMFBS_HasStdExtZfh_IsRV64,
7020 AMFBS_HasStdExtZfhmin_HasStdExtD,
7021 AMFBS_HasStdExtZfinx_IsRV64,
7022 AMFBS_HasStdExtZhinx_IsRV64,
7023 AMFBS_HasStdExtZicfiss_IsRV64,
7024 AMFBS_HasStdExtZilsd_IsRV32,
7025 AMFBS_HasStdExtZknd_IsRV32,
7026 AMFBS_HasStdExtZknd_IsRV64,
7027 AMFBS_HasStdExtZkndOrZkne_IsRV64,
7028 AMFBS_HasStdExtZkne_IsRV32,
7029 AMFBS_HasStdExtZkne_IsRV64,
7030 AMFBS_HasStdExtZknh_IsRV32,
7031 AMFBS_HasStdExtZknh_IsRV64,
7032 AMFBS_HasStdExtZmmul_IsRV64,
7033 AMFBS_HasVInstructionsI64_IsRV64,
7034 AMFBS_HasVendorXAndesPerf_IsRV64,
7035 AMFBS_HasVendorXCValu_IsRV32,
7036 AMFBS_HasVendorXCVbi_IsRV32,
7037 AMFBS_HasVendorXCVbitmanip_IsRV32,
7038 AMFBS_HasVendorXCVelw_IsRV32,
7039 AMFBS_HasVendorXCVmac_IsRV32,
7040 AMFBS_HasVendorXCVmem_IsRV32,
7041 AMFBS_HasVendorXCVsimd_IsRV32,
7042 AMFBS_HasVendorXSMTVDot_IsRV64,
7043 AMFBS_HasVendorXTHeadBb_IsRV64,
7044 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD,
7045 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF,
7046 AMFBS_HasVendorXTHeadMac_IsRV64,
7047 AMFBS_HasVendorXTHeadMemIdx_IsRV64,
7048 AMFBS_HasVendorXTHeadMemPair_IsRV64,
7049 AMFBS_HasVendorXqcia_IsRV32,
7050 AMFBS_HasVendorXqciac_IsRV32,
7051 AMFBS_HasVendorXqcibi_IsRV32,
7052 AMFBS_HasVendorXqcibm_IsRV32,
7053 AMFBS_HasVendorXqcicli_IsRV32,
7054 AMFBS_HasVendorXqcicm_IsRV32,
7055 AMFBS_HasVendorXqcics_IsRV32,
7056 AMFBS_HasVendorXqcicsr_IsRV32,
7057 AMFBS_HasVendorXqciint_IsRV32,
7058 AMFBS_HasVendorXqciio_IsRV32,
7059 AMFBS_HasVendorXqcilb_IsRV32,
7060 AMFBS_HasVendorXqcili_IsRV32,
7061 AMFBS_HasVendorXqcilia_IsRV32,
7062 AMFBS_HasVendorXqcilo_IsRV32,
7063 AMFBS_HasVendorXqcilsm_IsRV32,
7064 AMFBS_HasVendorXqcisim_IsRV32,
7065 AMFBS_HasVendorXqcisls_IsRV32,
7066 AMFBS_HasVendorXqcisync_IsRV32,
7067 AMFBS_IsRV32_HasStdExtZca,
7068 AMFBS_IsRV32_HasStdExtZcb,
7069 AMFBS_IsRV64_HasStdExtH,
7070 AMFBS_IsRV64_HasVInstructionsI64,
7071 AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64,
7072 AMFBS_HasStdExtZdinx_IsRV64_IsRV64,
7073 AMFBS_HasStdExtZfa_HasStdExtD_IsRV32,
7074 AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64,
7075 AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32,
7076 AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64,
7077 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64,
7078 AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64,
7079 AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32,
7080};
7081
7082static constexpr FeatureBitset FeatureBitsets[] = {
7083 {}, // AMFBS_None
7084 {Feature_HasHalfFPLoadStoreMoveBit, }, // AMFBS_HasHalfFPLoadStoreMove
7085 {Feature_HasStdExtDBit, }, // AMFBS_HasStdExtD
7086 {Feature_HasStdExtFBit, }, // AMFBS_HasStdExtF
7087 {Feature_HasStdExtFOrZfinxBit, }, // AMFBS_HasStdExtFOrZfinx
7088 {Feature_HasStdExtHBit, }, // AMFBS_HasStdExtH
7089 {Feature_HasStdExtMBit, }, // AMFBS_HasStdExtM
7090 {Feature_HasStdExtPBit, }, // AMFBS_HasStdExtP
7091 {Feature_HasStdExtQBit, }, // AMFBS_HasStdExtQ
7092 {Feature_HasStdExtSmctrOrSsctrBit, }, // AMFBS_HasStdExtSmctrOrSsctr
7093 {Feature_HasStdExtSmrnmiBit, }, // AMFBS_HasStdExtSmrnmi
7094 {Feature_HasStdExtSvinvalBit, }, // AMFBS_HasStdExtSvinval
7095 {Feature_HasStdExtYBit, }, // AMFBS_HasStdExtY
7096 {Feature_HasStdExtZaamoBit, }, // AMFBS_HasStdExtZaamo
7097 {Feature_HasStdExtZabhaBit, }, // AMFBS_HasStdExtZabha
7098 {Feature_HasStdExtZacasBit, }, // AMFBS_HasStdExtZacas
7099 {Feature_HasStdExtZalasrBit, }, // AMFBS_HasStdExtZalasr
7100 {Feature_HasStdExtZalrscBit, }, // AMFBS_HasStdExtZalrsc
7101 {Feature_HasStdExtZawrsBit, }, // AMFBS_HasStdExtZawrs
7102 {Feature_HasStdExtZbaBit, }, // AMFBS_HasStdExtZba
7103 {Feature_HasStdExtZbbBit, }, // AMFBS_HasStdExtZbb
7104 {Feature_HasStdExtZbbOrZbkbBit, }, // AMFBS_HasStdExtZbbOrZbkb
7105 {Feature_HasStdExtZbcBit, }, // AMFBS_HasStdExtZbc
7106 {Feature_HasStdExtZbkbBit, }, // AMFBS_HasStdExtZbkb
7107 {Feature_HasStdExtZbkbOrPBit, }, // AMFBS_HasStdExtZbkbOrP
7108 {Feature_HasStdExtZbkcBit, }, // AMFBS_HasStdExtZbkc
7109 {Feature_HasStdExtZbkxBit, }, // AMFBS_HasStdExtZbkx
7110 {Feature_HasStdExtZbsBit, }, // AMFBS_HasStdExtZbs
7111 {Feature_HasStdExtZcaBit, }, // AMFBS_HasStdExtZca
7112 {Feature_HasStdExtZcbBit, }, // AMFBS_HasStdExtZcb
7113 {Feature_HasStdExtZcdBit, }, // AMFBS_HasStdExtZcd
7114 {Feature_HasStdExtZcmopBit, }, // AMFBS_HasStdExtZcmop
7115 {Feature_HasStdExtZcmpBit, }, // AMFBS_HasStdExtZcmp
7116 {Feature_HasStdExtZcmtBit, }, // AMFBS_HasStdExtZcmt
7117 {Feature_HasStdExtZfaBit, }, // AMFBS_HasStdExtZfa
7118 {Feature_HasStdExtZfbfminBit, }, // AMFBS_HasStdExtZfbfmin
7119 {Feature_HasStdExtZfhBit, }, // AMFBS_HasStdExtZfh
7120 {Feature_HasStdExtZfhminBit, }, // AMFBS_HasStdExtZfhmin
7121 {Feature_HasStdExtZfinxBit, }, // AMFBS_HasStdExtZfinx
7122 {Feature_HasStdExtZhinxBit, }, // AMFBS_HasStdExtZhinx
7123 {Feature_HasStdExtZhinxminBit, }, // AMFBS_HasStdExtZhinxmin
7124 {Feature_HasStdExtZibiBit, }, // AMFBS_HasStdExtZibi
7125 {Feature_HasStdExtZicbomBit, }, // AMFBS_HasStdExtZicbom
7126 {Feature_HasStdExtZicbozBit, }, // AMFBS_HasStdExtZicboz
7127 {Feature_HasStdExtZicfissBit, }, // AMFBS_HasStdExtZicfiss
7128 {Feature_HasStdExtZicondBit, }, // AMFBS_HasStdExtZicond
7129 {Feature_HasStdExtZimopBit, }, // AMFBS_HasStdExtZimop
7130 {Feature_HasStdExtZknhBit, }, // AMFBS_HasStdExtZknh
7131 {Feature_HasStdExtZksedBit, }, // AMFBS_HasStdExtZksed
7132 {Feature_HasStdExtZkshBit, }, // AMFBS_HasStdExtZksh
7133 {Feature_HasStdExtZmmulBit, }, // AMFBS_HasStdExtZmmul
7134 {Feature_HasStdExtZvabdBit, }, // AMFBS_HasStdExtZvabd
7135 {Feature_HasStdExtZvbbBit, }, // AMFBS_HasStdExtZvbb
7136 {Feature_HasStdExtZvbcOrZvbc32eBit, }, // AMFBS_HasStdExtZvbcOrZvbc32e
7137 {Feature_HasStdExtZvdot4a8iBit, }, // AMFBS_HasStdExtZvdot4a8i
7138 {Feature_HasStdExtZvfbdota32fBit, }, // AMFBS_HasStdExtZvfbdota32f
7139 {Feature_HasStdExtZvfbfminOrZvfofp8minBit, }, // AMFBS_HasStdExtZvfbfminOrZvfofp8min
7140 {Feature_HasStdExtZvfbfwmaBit, }, // AMFBS_HasStdExtZvfbfwma
7141 {Feature_HasStdExtZvfofp8minBit, }, // AMFBS_HasStdExtZvfofp8min
7142 {Feature_HasStdExtZvfqwbdota8fBit, }, // AMFBS_HasStdExtZvfqwbdota8f
7143 {Feature_HasStdExtZvfqwdota8fBit, }, // AMFBS_HasStdExtZvfqwdota8f
7144 {Feature_HasStdExtZvfwbdota16bfBit, }, // AMFBS_HasStdExtZvfwbdota16bf
7145 {Feature_HasStdExtZvfwdota16bfBit, }, // AMFBS_HasStdExtZvfwdota16bf
7146 {Feature_HasStdExtZvkbBit, }, // AMFBS_HasStdExtZvkb
7147 {Feature_HasStdExtZvkgBit, }, // AMFBS_HasStdExtZvkg
7148 {Feature_HasStdExtZvkgsBit, }, // AMFBS_HasStdExtZvkgs
7149 {Feature_HasStdExtZvknedBit, }, // AMFBS_HasStdExtZvkned
7150 {Feature_HasStdExtZvknhaBit, }, // AMFBS_HasStdExtZvknha
7151 {Feature_HasStdExtZvksedBit, }, // AMFBS_HasStdExtZvksed
7152 {Feature_HasStdExtZvkshBit, }, // AMFBS_HasStdExtZvksh
7153 {Feature_HasStdExtZvqwbdota8iOrZvqwbdota16iBit, }, // AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i
7154 {Feature_HasStdExtZvqwdota8iOrZvqwdota16iBit, }, // AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i
7155 {Feature_HasStdExtZvvfmmBit, }, // AMFBS_HasStdExtZvvfmm
7156 {Feature_HasStdExtZvvmmBit, }, // AMFBS_HasStdExtZvvmm
7157 {Feature_HasStdExtZvvmtlsBit, }, // AMFBS_HasStdExtZvvmtls
7158 {Feature_HasStdExtZvvmttlsBit, }, // AMFBS_HasStdExtZvvmttls
7159 {Feature_HasStdExtZvzipBit, }, // AMFBS_HasStdExtZvzip
7160 {Feature_HasVInstructionsBit, }, // AMFBS_HasVInstructions
7161 {Feature_HasVInstructionsAnyFBit, }, // AMFBS_HasVInstructionsAnyF
7162 {Feature_HasVInstructionsI64Bit, }, // AMFBS_HasVInstructionsI64
7163 {Feature_HasVendorXAndesBFHCvtBit, }, // AMFBS_HasVendorXAndesBFHCvt
7164 {Feature_HasVendorXAndesPerfBit, }, // AMFBS_HasVendorXAndesPerf
7165 {Feature_HasVendorXAndesVBFHCvtBit, }, // AMFBS_HasVendorXAndesVBFHCvt
7166 {Feature_HasVendorXAndesVDotBit, }, // AMFBS_HasVendorXAndesVDot
7167 {Feature_HasVendorXAndesVPackFPHBit, }, // AMFBS_HasVendorXAndesVPackFPH
7168 {Feature_HasVendorXAndesVSIntHBit, }, // AMFBS_HasVendorXAndesVSIntH
7169 {Feature_HasVendorXAndesVSIntLoadBit, }, // AMFBS_HasVendorXAndesVSIntLoad
7170 {Feature_HasVendorXMIPSCBOPBit, }, // AMFBS_HasVendorXMIPSCBOP
7171 {Feature_HasVendorXMIPSCMovBit, }, // AMFBS_HasVendorXMIPSCMov
7172 {Feature_HasVendorXMIPSEXECTLBit, }, // AMFBS_HasVendorXMIPSEXECTL
7173 {Feature_HasVendorXMIPSLSPBit, }, // AMFBS_HasVendorXMIPSLSP
7174 {Feature_HasVendorXSfceaseBit, }, // AMFBS_HasVendorXSfcease
7175 {Feature_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64fBit, }, // AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f
7176 {Feature_HasVendorXSfmm32a8fBit, }, // AMFBS_HasVendorXSfmm32a8f
7177 {Feature_HasVendorXSfmm32a8iBit, }, // AMFBS_HasVendorXSfmm32a8i
7178 {Feature_HasVendorXSfmmbaseBit, }, // AMFBS_HasVendorXSfmmbase
7179 {Feature_HasVendorXSfvcpBit, }, // AMFBS_HasVendorXSfvcp
7180 {Feature_HasVendorXSfvfexpAnyBit, }, // AMFBS_HasVendorXSfvfexpAny
7181 {Feature_HasVendorXSfvfexpaBit, }, // AMFBS_HasVendorXSfvfexpa
7182 {Feature_HasVendorXSfvfnrclipxfqfBit, }, // AMFBS_HasVendorXSfvfnrclipxfqf
7183 {Feature_HasVendorXSfvfwmaccqqqBit, }, // AMFBS_HasVendorXSfvfwmaccqqq
7184 {Feature_HasVendorXSfvqmaccdodBit, }, // AMFBS_HasVendorXSfvqmaccdod
7185 {Feature_HasVendorXSfvqmaccqoqBit, }, // AMFBS_HasVendorXSfvqmaccqoq
7186 {Feature_HasVendorXSiFivecdiscarddloneBit, }, // AMFBS_HasVendorXSiFivecdiscarddlone
7187 {Feature_HasVendorXSiFivecflushdloneBit, }, // AMFBS_HasVendorXSiFivecflushdlone
7188 {Feature_HasVendorXTHeadBaBit, }, // AMFBS_HasVendorXTHeadBa
7189 {Feature_HasVendorXTHeadBbBit, }, // AMFBS_HasVendorXTHeadBb
7190 {Feature_HasVendorXTHeadBsBit, }, // AMFBS_HasVendorXTHeadBs
7191 {Feature_HasVendorXTHeadCmoBit, }, // AMFBS_HasVendorXTHeadCmo
7192 {Feature_HasVendorXTHeadCondMovBit, }, // AMFBS_HasVendorXTHeadCondMov
7193 {Feature_HasVendorXTHeadMacBit, }, // AMFBS_HasVendorXTHeadMac
7194 {Feature_HasVendorXTHeadMemIdxBit, }, // AMFBS_HasVendorXTHeadMemIdx
7195 {Feature_HasVendorXTHeadMemPairBit, }, // AMFBS_HasVendorXTHeadMemPair
7196 {Feature_HasVendorXTHeadSyncBit, }, // AMFBS_HasVendorXTHeadSync
7197 {Feature_HasVendorXTHeadVdotBit, }, // AMFBS_HasVendorXTHeadVdot
7198 {Feature_HasVendorXVentanaCondOpsBit, }, // AMFBS_HasVendorXVentanaCondOps
7199 {Feature_HasVendorXqccmpBit, }, // AMFBS_HasVendorXqccmp
7200 {Feature_HasVendorXqccmtBit, }, // AMFBS_HasVendorXqccmt
7201 {Feature_HasVendorXwchcBit, }, // AMFBS_HasVendorXwchc
7202 {Feature_HasXAIFETBit, }, // AMFBS_HasXAIFET
7203 {Feature_IsRV32Bit, }, // AMFBS_IsRV32
7204 {Feature_IsRV64Bit, }, // AMFBS_IsRV64
7205 {Feature_HasStdExtDBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtD_IsRV64
7206 {Feature_HasStdExtFBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtF_IsRV64
7207 {Feature_HasStdExtMBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtM_IsRV64
7208 {Feature_HasStdExtPBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtP_IsRV32
7209 {Feature_HasStdExtPBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtP_IsRV64
7210 {Feature_HasStdExtQBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtQ_IsRV64
7211 {Feature_HasStdExtYBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtY_IsRV32
7212 {Feature_HasStdExtYBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtY_IsRV64
7213 {Feature_HasStdExtZaamoBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZaamo_IsRV64
7214 {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, }, // AMFBS_HasStdExtZabha_HasStdExtZacas
7215 {Feature_HasStdExtZacasBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZacas_IsRV32
7216 {Feature_HasStdExtZacasBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZacas_IsRV64
7217 {Feature_HasStdExtZalasrBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZalasr_IsRV64
7218 {Feature_HasStdExtZalrscBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZalrsc_IsRV64
7219 {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZba_IsRV64
7220 {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZbb_IsRV64
7221 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZbbOrZbkb_IsRV32
7222 {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZbbOrZbkb_IsRV64
7223 {Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZbkb_IsRV32
7224 {Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZbkb_IsRV64
7225 {Feature_HasStdExtZcaBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZca_IsRV32
7226 {Feature_HasStdExtZcaBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZca_IsRV64
7227 {Feature_HasStdExtZcbBit, Feature_HasStdExtZbbBit, }, // AMFBS_HasStdExtZcb_HasStdExtZbb
7228 {Feature_HasStdExtZcbBit, Feature_HasStdExtZmmulBit, }, // AMFBS_HasStdExtZcb_HasStdExtZmmul
7229 {Feature_HasStdExtZcfBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZcf_IsRV32
7230 {Feature_HasStdExtZclsdBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZclsd_IsRV32
7231 {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZdinx_IsRV32
7232 {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZdinx_IsRV64
7233 {Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, }, // AMFBS_HasStdExtZfa_HasStdExtD
7234 {Feature_HasStdExtZfaBit, Feature_HasStdExtQBit, }, // AMFBS_HasStdExtZfa_HasStdExtQ
7235 {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, }, // AMFBS_HasStdExtZfa_HasStdExtZfh
7236 {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhOrZvfhBit, }, // AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh
7237 {Feature_HasStdExtZfhBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZfh_IsRV64
7238 {Feature_HasStdExtZfhminBit, Feature_HasStdExtDBit, }, // AMFBS_HasStdExtZfhmin_HasStdExtD
7239 {Feature_HasStdExtZfinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZfinx_IsRV64
7240 {Feature_HasStdExtZhinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZhinx_IsRV64
7241 {Feature_HasStdExtZicfissBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZicfiss_IsRV64
7242 {Feature_HasStdExtZilsdBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZilsd_IsRV32
7243 {Feature_HasStdExtZkndBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZknd_IsRV32
7244 {Feature_HasStdExtZkndBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZknd_IsRV64
7245 {Feature_HasStdExtZkndOrZkneBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZkndOrZkne_IsRV64
7246 {Feature_HasStdExtZkneBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZkne_IsRV32
7247 {Feature_HasStdExtZkneBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZkne_IsRV64
7248 {Feature_HasStdExtZknhBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZknh_IsRV32
7249 {Feature_HasStdExtZknhBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZknh_IsRV64
7250 {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZmmul_IsRV64
7251 {Feature_HasVInstructionsI64Bit, Feature_IsRV64Bit, }, // AMFBS_HasVInstructionsI64_IsRV64
7252 {Feature_HasVendorXAndesPerfBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXAndesPerf_IsRV64
7253 {Feature_HasVendorXCValuBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCValu_IsRV32
7254 {Feature_HasVendorXCVbiBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVbi_IsRV32
7255 {Feature_HasVendorXCVbitmanipBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVbitmanip_IsRV32
7256 {Feature_HasVendorXCVelwBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVelw_IsRV32
7257 {Feature_HasVendorXCVmacBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVmac_IsRV32
7258 {Feature_HasVendorXCVmemBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVmem_IsRV32
7259 {Feature_HasVendorXCVsimdBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXCVsimd_IsRV32
7260 {Feature_HasVendorXSMTVDotBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXSMTVDot_IsRV64
7261 {Feature_HasVendorXTHeadBbBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadBb_IsRV64
7262 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD
7263 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF
7264 {Feature_HasVendorXTHeadMacBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadMac_IsRV64
7265 {Feature_HasVendorXTHeadMemIdxBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadMemIdx_IsRV64
7266 {Feature_HasVendorXTHeadMemPairBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadMemPair_IsRV64
7267 {Feature_HasVendorXqciaBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcia_IsRV32
7268 {Feature_HasVendorXqciacBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqciac_IsRV32
7269 {Feature_HasVendorXqcibiBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcibi_IsRV32
7270 {Feature_HasVendorXqcibmBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcibm_IsRV32
7271 {Feature_HasVendorXqcicliBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcicli_IsRV32
7272 {Feature_HasVendorXqcicmBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcicm_IsRV32
7273 {Feature_HasVendorXqcicsBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcics_IsRV32
7274 {Feature_HasVendorXqcicsrBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcicsr_IsRV32
7275 {Feature_HasVendorXqciintBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqciint_IsRV32
7276 {Feature_HasVendorXqciioBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqciio_IsRV32
7277 {Feature_HasVendorXqcilbBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilb_IsRV32
7278 {Feature_HasVendorXqciliBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcili_IsRV32
7279 {Feature_HasVendorXqciliaBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilia_IsRV32
7280 {Feature_HasVendorXqciloBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilo_IsRV32
7281 {Feature_HasVendorXqcilsmBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilsm_IsRV32
7282 {Feature_HasVendorXqcisimBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcisim_IsRV32
7283 {Feature_HasVendorXqcislsBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcisls_IsRV32
7284 {Feature_HasVendorXqcisyncBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcisync_IsRV32
7285 {Feature_IsRV32Bit, Feature_HasStdExtZcaBit, }, // AMFBS_IsRV32_HasStdExtZca
7286 {Feature_IsRV32Bit, Feature_HasStdExtZcbBit, }, // AMFBS_IsRV32_HasStdExtZcb
7287 {Feature_IsRV64Bit, Feature_HasStdExtHBit, }, // AMFBS_IsRV64_HasStdExtH
7288 {Feature_IsRV64Bit, Feature_HasVInstructionsI64Bit, }, // AMFBS_IsRV64_HasVInstructionsI64
7289 {Feature_HasStdExtZcbBit, Feature_HasStdExtZbaBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64
7290 {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZdinx_IsRV64_IsRV64
7291 {Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZfa_HasStdExtD_IsRV32
7292 {Feature_HasStdExtZfaBit, Feature_HasStdExtQBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64
7293 {Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, }, // AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32
7294 {Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, }, // AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64
7295 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64
7296 {Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, Feature_IsRV64Bit, }, // AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64
7297 {Feature_HasVendorXqciloBit, Feature_HasVendorXqciliBit, Feature_IsRV32Bit, }, // AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32
7298};
7299
7300namespace {
7301 struct MatchEntry {
7302 uint16_t Mnemonic;
7303 uint32_t Opcode;
7304 uint16_t ConvertFn;
7305 uint8_t RequiredFeaturesIdx;
7306 uint16_t Classes[8];
7307 StringRef getMnemonic() const {
7308 return StringRef(MnemonicTable + Mnemonic + 1,
7309 MnemonicTable[Mnemonic]);
7310 }
7311 };
7312
7313 // Predicate for searching for an opcode.
7314 struct LessOpcode {
7315 bool operator()(const MatchEntry &LHS, StringRef RHS) {
7316 return LHS.getMnemonic() < RHS;
7317 }
7318 bool operator()(StringRef LHS, const MatchEntry &RHS) {
7319 return LHS < RHS.getMnemonic();
7320 }
7321 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
7322 return LHS.getMnemonic() < RHS.getMnemonic();
7323 }
7324 };
7325} // end anonymous namespace
7326
7327static const MatchEntry MatchTable0[] = {
7328 { 0 /* .insn_b */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_BareSImm13Lsb0 }, },
7329 { 8 /* .insn_ca */, RISCV::InsnCA, Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm6, MCK_UImm2, MCK_AnyRegCOperand, MCK_AnyRegCOperand }, },
7330 { 17 /* .insn_cb */, RISCV::InsnCB, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__BareSImm9Lsb01_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_BareSImm9Lsb0 }, },
7331 { 26 /* .insn_ci */, RISCV::InsnCI, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm6 }, },
7332 { 35 /* .insn_ciw */, RISCV::InsnCIW, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm8 }, },
7333 { 45 /* .insn_cj */, RISCV::InsnCJ, Convert__InsnCDirectiveOpcode1_0__UImm31_1__BareSImm12Lsb01_2, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_BareSImm12Lsb0 }, },
7334 { 54 /* .insn_cl */, RISCV::InsnCL, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7335 { 54 /* .insn_cl */, RISCV::InsnCL, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7336 { 63 /* .insn_cr */, RISCV::InsnCR, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm4, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7337 { 72 /* .insn_cs */, RISCV::InsnCS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7338 { 72 /* .insn_cs */, RISCV::InsnCS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
7339 { 81 /* .insn_css */, RISCV::InsnCSS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3, AMFBS_HasStdExtZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_UImm6 }, },
7340 { 91 /* .insn_i */, RISCV::InsnI, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm12LO1_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm12LO }, },
7341 { 91 /* .insn_i */, RISCV::InsnI_Mem, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7342 { 91 /* .insn_i */, RISCV::InsnI_Mem, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm12LO1_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm12LO, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7343 { 99 /* .insn_j */, RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_BareSImm21Lsb0 }, },
7344 { 107 /* .insn_qc.eai */, RISCV::InsnQC_EAI, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm11_2__BareSImm321_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm1, MCK_AnyRegOperand, MCK_BareSImm32 }, },
7345 { 120 /* .insn_qc.eb */, RISCV::InsnQC_EB, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm51_2__AnyRegOperand1_3__SImm161_4__BareSImm13Lsb01_5, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm5, MCK_AnyRegOperand, MCK_SImm16, MCK_BareSImm13Lsb0 }, },
7346 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__SImm261_5, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm26 }, },
7347 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI_Mem, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_5__imm_95_0, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7348 { 132 /* .insn_qc.ei */, RISCV::InsnQC_EI_Mem, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_6__SImm261_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_SImm26, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7349 { 144 /* .insn_qc.ej */, RISCV::InsnQC_EJ, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__UImm51_3__BareSImm32Lsb01_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_UImm5, MCK_BareSImm32Lsb0 }, },
7350 { 156 /* .insn_qc.es */, RISCV::InsnQC_ES, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_5__imm_95_0, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7351 { 156 /* .insn_qc.es */, RISCV::InsnQC_ES, Convert__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_3__AnyRegOperand1_6__SImm261_4, AMFBS_IsRV32, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_SImm26, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7352 { 168 /* .insn_r */, RISCV::InsnR, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm7, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7353 { 168 /* .insn_r */, RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7354 { 176 /* .insn_r4 */, RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
7355 { 185 /* .insn_s */, RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7356 { 185 /* .insn_s */, RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm12LO1_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm12LO, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
7357 { 193 /* .insn_sb */, RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__BareSImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_BareSImm13Lsb0 }, },
7358 { 202 /* .insn_u */, RISCV::InsnU, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_UImm20LUI }, },
7359 { 210 /* .insn_uj */, RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__BareSImm21Lsb01_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_BareSImm21Lsb0 }, },
7360 { 219 /* aadd */, RISCV::AADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7361 { 224 /* aaddu */, RISCV::AADDU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7362 { 230 /* abs */, RISCV::ABS, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
7363 { 234 /* absw */, RISCV::ABSW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
7364 { 239 /* add */, RISCV::ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7365 { 239 /* add */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7366 { 239 /* add */, RISCV::PseudoAddTPRel, Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_TPRelAddSymbol }, },
7367 { 243 /* add.uw */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7368 { 250 /* addd */, RISCV::ADDD, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
7369 { 255 /* addi */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7370 { 260 /* addiw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7371 { 266 /* addw */, RISCV::ADDW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7372 { 266 /* addw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7373 { 271 /* aes32dsi */, RISCV::AES32DSI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7374 { 280 /* aes32dsmi */, RISCV::AES32DSMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7375 { 290 /* aes32esi */, RISCV::AES32ESI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7376 { 299 /* aes32esmi */, RISCV::AES32ESMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
7377 { 309 /* aes64ds */, RISCV::AES64DS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7378 { 317 /* aes64dsm */, RISCV::AES64DSM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7379 { 326 /* aes64es */, RISCV::AES64ES, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7380 { 334 /* aes64esm */, RISCV::AES64ESM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7381 { 343 /* aes64im */, RISCV::AES64IM, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR }, },
7382 { 351 /* aes64ks1i */, RISCV::AES64KS1I, Convert__Reg1_0__Reg1_1__RnumArg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_RnumArg }, },
7383 { 361 /* aes64ks2 */, RISCV::AES64KS2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7384 { 370 /* aif.amoaddg.d */, RISCV::AIF_AMOADDG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7385 { 384 /* aif.amoaddg.w */, RISCV::AIF_AMOADDG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7386 { 398 /* aif.amoaddl.d */, RISCV::AIF_AMOADDL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7387 { 412 /* aif.amoaddl.w */, RISCV::AIF_AMOADDL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7388 { 426 /* aif.amoandg.d */, RISCV::AIF_AMOANDG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7389 { 440 /* aif.amoandg.w */, RISCV::AIF_AMOANDG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7390 { 454 /* aif.amoandl.d */, RISCV::AIF_AMOANDL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7391 { 468 /* aif.amoandl.w */, RISCV::AIF_AMOANDL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7392 { 482 /* aif.amocmpswapg.d */, RISCV::AIF_AMOCMPSWAPG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7393 { 500 /* aif.amocmpswapg.w */, RISCV::AIF_AMOCMPSWAPG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7394 { 518 /* aif.amocmpswapl.d */, RISCV::AIF_AMOCMPSWAPL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7395 { 536 /* aif.amocmpswapl.w */, RISCV::AIF_AMOCMPSWAPL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7396 { 554 /* aif.amomaxg.d */, RISCV::AIF_AMOMAXG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7397 { 568 /* aif.amomaxg.w */, RISCV::AIF_AMOMAXG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7398 { 582 /* aif.amomaxl.d */, RISCV::AIF_AMOMAXL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7399 { 596 /* aif.amomaxl.w */, RISCV::AIF_AMOMAXL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7400 { 610 /* aif.amomaxug.d */, RISCV::AIF_AMOMAXUG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7401 { 625 /* aif.amomaxug.w */, RISCV::AIF_AMOMAXUG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7402 { 640 /* aif.amomaxul.d */, RISCV::AIF_AMOMAXUL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7403 { 655 /* aif.amomaxul.w */, RISCV::AIF_AMOMAXUL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7404 { 670 /* aif.amoming.d */, RISCV::AIF_AMOMING_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7405 { 684 /* aif.amoming.w */, RISCV::AIF_AMOMING_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7406 { 698 /* aif.amominl.d */, RISCV::AIF_AMOMINL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7407 { 712 /* aif.amominl.w */, RISCV::AIF_AMOMINL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7408 { 726 /* aif.amominug.d */, RISCV::AIF_AMOMINUG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7409 { 741 /* aif.amominug.w */, RISCV::AIF_AMOMINUG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7410 { 756 /* aif.amominul.d */, RISCV::AIF_AMOMINUL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7411 { 771 /* aif.amominul.w */, RISCV::AIF_AMOMINUL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7412 { 786 /* aif.amoorg.d */, RISCV::AIF_AMOORG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7413 { 799 /* aif.amoorg.w */, RISCV::AIF_AMOORG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7414 { 812 /* aif.amoorl.d */, RISCV::AIF_AMOORL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7415 { 825 /* aif.amoorl.w */, RISCV::AIF_AMOORL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7416 { 838 /* aif.amoswapg.d */, RISCV::AIF_AMOSWAPG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7417 { 853 /* aif.amoswapg.w */, RISCV::AIF_AMOSWAPG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7418 { 868 /* aif.amoswapl.d */, RISCV::AIF_AMOSWAPL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7419 { 883 /* aif.amoswapl.w */, RISCV::AIF_AMOSWAPL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7420 { 898 /* aif.amoxorg.d */, RISCV::AIF_AMOXORG_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7421 { 912 /* aif.amoxorg.w */, RISCV::AIF_AMOXORG_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7422 { 926 /* aif.amoxorl.d */, RISCV::AIF_AMOXORL_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7423 { 940 /* aif.amoxorl.w */, RISCV::AIF_AMOXORL_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7424 { 954 /* aif.bitmixb */, RISCV::AIF_BITMIXB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7425 { 966 /* aif.cubeface.ps */, RISCV::AIF_CUBEFACE_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7426 { 982 /* aif.cubefaceidx.ps */, RISCV::AIF_CUBEFACEIDX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7427 { 1001 /* aif.cubesgnsc.ps */, RISCV::AIF_CUBESGNSC_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7428 { 1018 /* aif.cubesgntc.ps */, RISCV::AIF_CUBESGNTC_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7429 { 1035 /* aif.fadd.pi */, RISCV::AIF_FADD_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7430 { 1047 /* aif.fadd.ps */, RISCV::AIF_FADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7431 { 1059 /* aif.faddi.pi */, RISCV::AIF_FADDI_PI, Convert__Reg1_0__Reg1_1__SImm101_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_SImm10 }, },
7432 { 1072 /* aif.famoaddg.pi */, RISCV::AIF_FAMOADDG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7433 { 1088 /* aif.famoaddl.pi */, RISCV::AIF_FAMOADDL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7434 { 1104 /* aif.famoandg.pi */, RISCV::AIF_FAMOANDG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7435 { 1120 /* aif.famoandl.pi */, RISCV::AIF_FAMOANDL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7436 { 1136 /* aif.famomaxg.pi */, RISCV::AIF_FAMOMAXG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7437 { 1152 /* aif.famomaxg.ps */, RISCV::AIF_FAMOMAXG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7438 { 1168 /* aif.famomaxl.pi */, RISCV::AIF_FAMOMAXL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7439 { 1184 /* aif.famomaxl.ps */, RISCV::AIF_FAMOMAXL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7440 { 1200 /* aif.famomaxug.pi */, RISCV::AIF_FAMOMAXUG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7441 { 1217 /* aif.famomaxul.pi */, RISCV::AIF_FAMOMAXUL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7442 { 1234 /* aif.famoming.pi */, RISCV::AIF_FAMOMING_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7443 { 1250 /* aif.famoming.ps */, RISCV::AIF_FAMOMING_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7444 { 1266 /* aif.famominl.pi */, RISCV::AIF_FAMOMINL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7445 { 1282 /* aif.famominl.ps */, RISCV::AIF_FAMOMINL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7446 { 1298 /* aif.famominug.pi */, RISCV::AIF_FAMOMINUG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7447 { 1315 /* aif.famominul.pi */, RISCV::AIF_FAMOMINUL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7448 { 1332 /* aif.famoorg.pi */, RISCV::AIF_FAMOORG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7449 { 1347 /* aif.famoorl.pi */, RISCV::AIF_FAMOORL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7450 { 1362 /* aif.famoswapg.pi */, RISCV::AIF_FAMOSWAPG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7451 { 1379 /* aif.famoswapl.pi */, RISCV::AIF_FAMOSWAPL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7452 { 1396 /* aif.famoxorg.pi */, RISCV::AIF_FAMOXORG_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7453 { 1412 /* aif.famoxorl.pi */, RISCV::AIF_FAMOXORL_PI, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7454 { 1428 /* aif.fand.pi */, RISCV::AIF_FAND_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7455 { 1440 /* aif.fandi.pi */, RISCV::AIF_FANDI_PI, Convert__Reg1_0__Reg1_1__SImm101_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_SImm10 }, },
7456 { 1453 /* aif.fbc.ps */, RISCV::AIF_FBC_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7457 { 1464 /* aif.fbci.pi */, RISCV::AIF_FBCI_PI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_UImm20LUI }, },
7458 { 1476 /* aif.fbci.ps */, RISCV::AIF_FBCI_PS, Convert__Reg1_0__UImm20LUI1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_UImm20LUI }, },
7459 { 1488 /* aif.fbcx.ps */, RISCV::AIF_FBCX_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR }, },
7460 { 1500 /* aif.fclass.ps */, RISCV::AIF_FCLASS_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7461 { 1514 /* aif.fcmov.ps */, RISCV::AIF_FCMOV_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7462 { 1527 /* aif.fcmovm.ps */, RISCV::AIF_FCMOVM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7463 { 1541 /* aif.fcvt.f10.ps */, RISCV::AIF_FCVT_F10_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7464 { 1557 /* aif.fcvt.f11.ps */, RISCV::AIF_FCVT_F11_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7465 { 1573 /* aif.fcvt.f16.ps */, RISCV::AIF_FCVT_F16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7466 { 1589 /* aif.fcvt.ps.f10 */, RISCV::AIF_FCVT_PS_F10, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7467 { 1605 /* aif.fcvt.ps.f11 */, RISCV::AIF_FCVT_PS_F11, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7468 { 1621 /* aif.fcvt.ps.f16 */, RISCV::AIF_FCVT_PS_F16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7469 { 1637 /* aif.fcvt.ps.pw */, RISCV::AIF_FCVT_PS_PW, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7470 { 1652 /* aif.fcvt.ps.pwu */, RISCV::AIF_FCVT_PS_PWU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7471 { 1668 /* aif.fcvt.ps.rast */, RISCV::AIF_FCVT_PS_RAST, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7472 { 1685 /* aif.fcvt.ps.sn16 */, RISCV::AIF_FCVT_PS_SN16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7473 { 1702 /* aif.fcvt.ps.sn8 */, RISCV::AIF_FCVT_PS_SN8, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7474 { 1718 /* aif.fcvt.ps.un10 */, RISCV::AIF_FCVT_PS_UN10, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7475 { 1735 /* aif.fcvt.ps.un16 */, RISCV::AIF_FCVT_PS_UN16, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7476 { 1752 /* aif.fcvt.ps.un2 */, RISCV::AIF_FCVT_PS_UN2, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7477 { 1768 /* aif.fcvt.ps.un24 */, RISCV::AIF_FCVT_PS_UN24, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7478 { 1785 /* aif.fcvt.ps.un8 */, RISCV::AIF_FCVT_PS_UN8, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7479 { 1801 /* aif.fcvt.pw.ps */, RISCV::AIF_FCVT_PW_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7480 { 1816 /* aif.fcvt.pwu.ps */, RISCV::AIF_FCVT_PWU_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7481 { 1832 /* aif.fcvt.rast.ps */, RISCV::AIF_FCVT_RAST_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7482 { 1849 /* aif.fcvt.sn16.ps */, RISCV::AIF_FCVT_SN16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7483 { 1866 /* aif.fcvt.sn8.ps */, RISCV::AIF_FCVT_SN8_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7484 { 1882 /* aif.fcvt.un10.ps */, RISCV::AIF_FCVT_UN10_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7485 { 1899 /* aif.fcvt.un16.ps */, RISCV::AIF_FCVT_UN16_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7486 { 1916 /* aif.fcvt.un2.ps */, RISCV::AIF_FCVT_UN2_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7487 { 1932 /* aif.fcvt.un24.ps */, RISCV::AIF_FCVT_UN24_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7488 { 1949 /* aif.fcvt.un8.ps */, RISCV::AIF_FCVT_UN8_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7489 { 1965 /* aif.fdiv.pi */, RISCV::AIF_FDIV_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7490 { 1977 /* aif.fdiv.ps */, RISCV::AIF_FDIV_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7491 { 1989 /* aif.fdivu.pi */, RISCV::AIF_FDIVU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7492 { 2002 /* aif.feq.pi */, RISCV::AIF_FEQ_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7493 { 2013 /* aif.feq.ps */, RISCV::AIF_FEQ_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7494 { 2024 /* aif.feqm.ps */, RISCV::AIF_FEQM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7495 { 2036 /* aif.fexp.ps */, RISCV::AIF_FEXP_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7496 { 2048 /* aif.ffrc.ps */, RISCV::AIF_FFRC_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7497 { 2060 /* aif.fg32b.ps */, RISCV::AIF_FG32B_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7498 { 2073 /* aif.fg32h.ps */, RISCV::AIF_FG32H_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7499 { 2086 /* aif.fg32w.ps */, RISCV::AIF_FG32W_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7500 { 2099 /* aif.fgb.ps */, RISCV::AIF_FGB_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7501 { 2110 /* aif.fgbg.ps */, RISCV::AIF_FGBG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7502 { 2122 /* aif.fgbl.ps */, RISCV::AIF_FGBL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7503 { 2134 /* aif.fgh.ps */, RISCV::AIF_FGH_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7504 { 2145 /* aif.fghg.ps */, RISCV::AIF_FGHG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7505 { 2157 /* aif.fghl.ps */, RISCV::AIF_FGHL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7506 { 2169 /* aif.fgw.ps */, RISCV::AIF_FGW_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7507 { 2180 /* aif.fgwg.ps */, RISCV::AIF_FGWG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7508 { 2192 /* aif.fgwl.ps */, RISCV::AIF_FGWL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7509 { 2204 /* aif.fle.pi */, RISCV::AIF_FLE_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7510 { 2215 /* aif.fle.ps */, RISCV::AIF_FLE_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7511 { 2226 /* aif.flem.ps */, RISCV::AIF_FLEM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7512 { 2238 /* aif.flog.ps */, RISCV::AIF_FLOG_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7513 { 2250 /* aif.flq2 */, RISCV::AIF_FLQ2, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7514 { 2259 /* aif.flt.pi */, RISCV::AIF_FLT_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7515 { 2270 /* aif.flt.ps */, RISCV::AIF_FLT_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7516 { 2281 /* aif.fltm.pi */, RISCV::AIF_FLTM_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7517 { 2293 /* aif.fltm.ps */, RISCV::AIF_FLTM_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256, MCK_FPR256 }, },
7518 { 2305 /* aif.fltu.pi */, RISCV::AIF_FLTU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7519 { 2317 /* aif.flw.ps */, RISCV::AIF_FLW_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7520 { 2328 /* aif.flwg.ps */, RISCV::AIF_FLWG_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7521 { 2340 /* aif.flwl.ps */, RISCV::AIF_FLWL_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7522 { 2352 /* aif.fmadd.ps */, RISCV::AIF_FMADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7523 { 2365 /* aif.fmax.pi */, RISCV::AIF_FMAX_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7524 { 2377 /* aif.fmax.ps */, RISCV::AIF_FMAX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7525 { 2389 /* aif.fmaxu.pi */, RISCV::AIF_FMAXU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7526 { 2402 /* aif.fmin.pi */, RISCV::AIF_FMIN_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7527 { 2414 /* aif.fmin.ps */, RISCV::AIF_FMIN_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7528 { 2426 /* aif.fminu.pi */, RISCV::AIF_FMINU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7529 { 2439 /* aif.fmsub.ps */, RISCV::AIF_FMSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7530 { 2452 /* aif.fmul.pi */, RISCV::AIF_FMUL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7531 { 2464 /* aif.fmul.ps */, RISCV::AIF_FMUL_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7532 { 2476 /* aif.fmulh.pi */, RISCV::AIF_FMULH_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7533 { 2489 /* aif.fmulhu.pi */, RISCV::AIF_FMULHU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7534 { 2503 /* aif.fmvs.x.ps */, RISCV::AIF_FMVS_X_PS, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_FPR256, MCK_UImm3 }, },
7535 { 2517 /* aif.fmvz.x.ps */, RISCV::AIF_FMVZ_X_PS, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_FPR256, MCK_UImm3 }, },
7536 { 2531 /* aif.fnmadd.ps */, RISCV::AIF_FNMADD_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7537 { 2545 /* aif.fnmsub.ps */, RISCV::AIF_FNMSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7538 { 2559 /* aif.fnot.pi */, RISCV::AIF_FNOT_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7539 { 2571 /* aif.for.pi */, RISCV::AIF_FOR_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7540 { 2582 /* aif.fpackrepb.pi */, RISCV::AIF_FPACKREPB_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7541 { 2599 /* aif.fpackreph.pi */, RISCV::AIF_FPACKREPH_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7542 { 2616 /* aif.frcp.ps */, RISCV::AIF_FRCP_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7543 { 2628 /* aif.frcp_fix.rast */, RISCV::AIF_FRCP_FIX_RAST, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7544 { 2646 /* aif.frem.pi */, RISCV::AIF_FREM_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7545 { 2658 /* aif.fremu.pi */, RISCV::AIF_FREMU_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7546 { 2671 /* aif.fround.ps */, RISCV::AIF_FROUND_PS, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7547 { 2685 /* aif.frsq.ps */, RISCV::AIF_FRSQ_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7548 { 2697 /* aif.fsat8.pi */, RISCV::AIF_FSAT8_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7549 { 2710 /* aif.fsatu8.pi */, RISCV::AIF_FSATU8_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7550 { 2724 /* aif.fsc32b.ps */, RISCV::AIF_FSC32B_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7551 { 2738 /* aif.fsc32h.ps */, RISCV::AIF_FSC32H_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7552 { 2752 /* aif.fsc32w.ps */, RISCV::AIF_FSC32W_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7553 { 2766 /* aif.fscb.ps */, RISCV::AIF_FSCB_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7554 { 2778 /* aif.fscbg.ps */, RISCV::AIF_FSCBG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7555 { 2791 /* aif.fscbl.ps */, RISCV::AIF_FSCBL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7556 { 2804 /* aif.fsch.ps */, RISCV::AIF_FSCH_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7557 { 2816 /* aif.fschg.ps */, RISCV::AIF_FSCHG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7558 { 2829 /* aif.fschl.ps */, RISCV::AIF_FSCHL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7559 { 2842 /* aif.fscw.ps */, RISCV::AIF_FSCW_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7560 { 2854 /* aif.fscwg.ps */, RISCV::AIF_FSCWG_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7561 { 2867 /* aif.fscwl.ps */, RISCV::AIF_FSCWL_PS, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_ZeroOffsetMemOpOperand }, },
7562 { 2880 /* aif.fsetm.pi */, RISCV::AIF_FSETM_PI, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_MR, MCK_FPR256 }, },
7563 { 2893 /* aif.fsgnj.ps */, RISCV::AIF_FSGNJ_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7564 { 2906 /* aif.fsgnjn.ps */, RISCV::AIF_FSGNJN_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7565 { 2920 /* aif.fsgnjx.ps */, RISCV::AIF_FSGNJX_PS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7566 { 2934 /* aif.fsin.ps */, RISCV::AIF_FSIN_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7567 { 2946 /* aif.fsll.pi */, RISCV::AIF_FSLL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7568 { 2958 /* aif.fslli.pi */, RISCV::AIF_FSLLI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
7569 { 2971 /* aif.fsq2 */, RISCV::AIF_FSQ2, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7570 { 2980 /* aif.fsqrt.ps */, RISCV::AIF_FSQRT_PS, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256 }, },
7571 { 2993 /* aif.fsra.pi */, RISCV::AIF_FSRA_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7572 { 3005 /* aif.fsrai.pi */, RISCV::AIF_FSRAI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
7573 { 3018 /* aif.fsrl.pi */, RISCV::AIF_FSRL_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7574 { 3030 /* aif.fsrli.pi */, RISCV::AIF_FSRLI_PI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm5 }, },
7575 { 3043 /* aif.fsub.pi */, RISCV::AIF_FSUB_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7576 { 3055 /* aif.fsub.ps */, RISCV::AIF_FSUB_PS, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256, MCK_FRMArg }, },
7577 { 3067 /* aif.fsw.ps */, RISCV::AIF_FSW_PS, Convert__Reg1_0__SImm12LO1_1__Reg1_3, AMFBS_HasXAIFET, { MCK_FPR256, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
7578 { 3078 /* aif.fswg.ps */, RISCV::AIF_FSWG_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7579 { 3090 /* aif.fswizz.ps */, RISCV::AIF_FSWIZZ_PS, Convert__Reg1_0__Reg1_1__UImm81_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_UImm8 }, },
7580 { 3104 /* aif.fswl.ps */, RISCV::AIF_FSWL_PS, Convert__Reg1_0__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK__40_, MCK_GPR, MCK__41_ }, },
7581 { 3116 /* aif.fxor.pi */, RISCV::AIF_FXOR_PI, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_FPR256, MCK_FPR256, MCK_FPR256 }, },
7582 { 3128 /* aif.maskand */, RISCV::AIF_MASKAND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
7583 { 3140 /* aif.masknot */, RISCV::AIF_MASKNOT, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_MR, MCK_MR }, },
7584 { 3152 /* aif.maskor */, RISCV::AIF_MASKOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
7585 { 3163 /* aif.maskpopc */, RISCV::AIF_MASKPOPC, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_MR }, },
7586 { 3176 /* aif.maskpopc.rast */, RISCV::AIF_MASKPOPC_ET_RAST, Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR, MCK_UImm4 }, },
7587 { 3194 /* aif.maskpopcz */, RISCV::AIF_MASKPOPCZ, Convert__Reg1_0__Reg1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_MR }, },
7588 { 3208 /* aif.maskxor */, RISCV::AIF_MASKXOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_MR, MCK_MR, MCK_MR }, },
7589 { 3220 /* aif.mov.m.x */, RISCV::AIF_MOV_M_X, Convert__Reg1_0__Reg1_1__UImm81_2, AMFBS_HasXAIFET, { MCK_MR, MCK_GPR, MCK_UImm8 }, },
7590 { 3232 /* aif.mova.m.x */, RISCV::AIF_MOVA_M_X, Convert__Reg1_0, AMFBS_HasXAIFET, { MCK_GPR }, },
7591 { 3245 /* aif.mova.x.m */, RISCV::AIF_MOVA_X_M, Convert__Reg1_0, AMFBS_HasXAIFET, { MCK_GPR }, },
7592 { 3258 /* aif.packb */, RISCV::AIF_PACKB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasXAIFET, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7593 { 3268 /* aif.sbg */, RISCV::AIF_SBG, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7594 { 3276 /* aif.sbl */, RISCV::AIF_SBL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7595 { 3284 /* aif.shg */, RISCV::AIF_SHG, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7596 { 3292 /* aif.shl */, RISCV::AIF_SHL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasXAIFET, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7597 { 3300 /* amoadd.b */, RISCV::AMOADD_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7598 { 3309 /* amoadd.b.aq */, RISCV::AMOADD_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7599 { 3321 /* amoadd.b.aqrl */, RISCV::AMOADD_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7600 { 3335 /* amoadd.b.rl */, RISCV::AMOADD_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7601 { 3347 /* amoadd.d */, RISCV::AMOADD_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7602 { 3356 /* amoadd.d.aq */, RISCV::AMOADD_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7603 { 3368 /* amoadd.d.aqrl */, RISCV::AMOADD_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7604 { 3382 /* amoadd.d.rl */, RISCV::AMOADD_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7605 { 3394 /* amoadd.h */, RISCV::AMOADD_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7606 { 3403 /* amoadd.h.aq */, RISCV::AMOADD_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7607 { 3415 /* amoadd.h.aqrl */, RISCV::AMOADD_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7608 { 3429 /* amoadd.h.rl */, RISCV::AMOADD_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7609 { 3441 /* amoadd.w */, RISCV::AMOADD_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7610 { 3450 /* amoadd.w.aq */, RISCV::AMOADD_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7611 { 3462 /* amoadd.w.aqrl */, RISCV::AMOADD_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7612 { 3476 /* amoadd.w.rl */, RISCV::AMOADD_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7613 { 3488 /* amoand.b */, RISCV::AMOAND_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7614 { 3497 /* amoand.b.aq */, RISCV::AMOAND_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7615 { 3509 /* amoand.b.aqrl */, RISCV::AMOAND_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7616 { 3523 /* amoand.b.rl */, RISCV::AMOAND_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7617 { 3535 /* amoand.d */, RISCV::AMOAND_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7618 { 3544 /* amoand.d.aq */, RISCV::AMOAND_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7619 { 3556 /* amoand.d.aqrl */, RISCV::AMOAND_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7620 { 3570 /* amoand.d.rl */, RISCV::AMOAND_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7621 { 3582 /* amoand.h */, RISCV::AMOAND_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7622 { 3591 /* amoand.h.aq */, RISCV::AMOAND_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7623 { 3603 /* amoand.h.aqrl */, RISCV::AMOAND_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7624 { 3617 /* amoand.h.rl */, RISCV::AMOAND_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7625 { 3629 /* amoand.w */, RISCV::AMOAND_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7626 { 3638 /* amoand.w.aq */, RISCV::AMOAND_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7627 { 3650 /* amoand.w.aqrl */, RISCV::AMOAND_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7628 { 3664 /* amoand.w.rl */, RISCV::AMOAND_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7629 { 3676 /* amocas.b */, RISCV::AMOCAS_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7630 { 3685 /* amocas.b.aq */, RISCV::AMOCAS_B_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7631 { 3697 /* amocas.b.aqrl */, RISCV::AMOCAS_B_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7632 { 3711 /* amocas.b.rl */, RISCV::AMOCAS_B_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7633 { 3723 /* amocas.d */, RISCV::AMOCAS_D_RV64, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7634 { 3723 /* amocas.d */, RISCV::AMOCAS_D_RV32, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7635 { 3732 /* amocas.d.aq */, RISCV::AMOCAS_D_RV64_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7636 { 3732 /* amocas.d.aq */, RISCV::AMOCAS_D_RV32_AQ, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7637 { 3744 /* amocas.d.aqrl */, RISCV::AMOCAS_D_RV64_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7638 { 3744 /* amocas.d.aqrl */, RISCV::AMOCAS_D_RV32_AQRL, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7639 { 3758 /* amocas.d.rl */, RISCV::AMOCAS_D_RV64_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7640 { 3758 /* amocas.d.rl */, RISCV::AMOCAS_D_RV32_RL, Convert__GPRPairRV321_0__Tie0_1_1__GPRPairRV321_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
7641 { 3770 /* amocas.h */, RISCV::AMOCAS_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7642 { 3779 /* amocas.h.aq */, RISCV::AMOCAS_H_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7643 { 3791 /* amocas.h.aqrl */, RISCV::AMOCAS_H_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7644 { 3805 /* amocas.h.rl */, RISCV::AMOCAS_H_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7645 { 3817 /* amocas.q */, RISCV::AMOCAS_Q, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7646 { 3826 /* amocas.q.aq */, RISCV::AMOCAS_Q_AQ, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7647 { 3838 /* amocas.q.aqrl */, RISCV::AMOCAS_Q_AQRL, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7648 { 3852 /* amocas.q.rl */, RISCV::AMOCAS_Q_RL, Convert__GPRPairRV641_0__Tie0_1_1__GPRPairRV641_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
7649 { 3864 /* amocas.w */, RISCV::AMOCAS_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7650 { 3873 /* amocas.w.aq */, RISCV::AMOCAS_W_AQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7651 { 3885 /* amocas.w.aqrl */, RISCV::AMOCAS_W_AQRL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7652 { 3899 /* amocas.w.rl */, RISCV::AMOCAS_W_RL, Convert__Reg1_0__Tie0_1_1__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7653 { 3911 /* amomax.b */, RISCV::AMOMAX_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7654 { 3920 /* amomax.b.aq */, RISCV::AMOMAX_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7655 { 3932 /* amomax.b.aqrl */, RISCV::AMOMAX_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7656 { 3946 /* amomax.b.rl */, RISCV::AMOMAX_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7657 { 3958 /* amomax.d */, RISCV::AMOMAX_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7658 { 3967 /* amomax.d.aq */, RISCV::AMOMAX_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7659 { 3979 /* amomax.d.aqrl */, RISCV::AMOMAX_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7660 { 3993 /* amomax.d.rl */, RISCV::AMOMAX_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7661 { 4005 /* amomax.h */, RISCV::AMOMAX_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7662 { 4014 /* amomax.h.aq */, RISCV::AMOMAX_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7663 { 4026 /* amomax.h.aqrl */, RISCV::AMOMAX_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7664 { 4040 /* amomax.h.rl */, RISCV::AMOMAX_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7665 { 4052 /* amomax.w */, RISCV::AMOMAX_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7666 { 4061 /* amomax.w.aq */, RISCV::AMOMAX_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7667 { 4073 /* amomax.w.aqrl */, RISCV::AMOMAX_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7668 { 4087 /* amomax.w.rl */, RISCV::AMOMAX_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7669 { 4099 /* amomaxu.b */, RISCV::AMOMAXU_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7670 { 4109 /* amomaxu.b.aq */, RISCV::AMOMAXU_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7671 { 4122 /* amomaxu.b.aqrl */, RISCV::AMOMAXU_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7672 { 4137 /* amomaxu.b.rl */, RISCV::AMOMAXU_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7673 { 4150 /* amomaxu.d */, RISCV::AMOMAXU_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7674 { 4160 /* amomaxu.d.aq */, RISCV::AMOMAXU_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7675 { 4173 /* amomaxu.d.aqrl */, RISCV::AMOMAXU_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7676 { 4188 /* amomaxu.d.rl */, RISCV::AMOMAXU_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7677 { 4201 /* amomaxu.h */, RISCV::AMOMAXU_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7678 { 4211 /* amomaxu.h.aq */, RISCV::AMOMAXU_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7679 { 4224 /* amomaxu.h.aqrl */, RISCV::AMOMAXU_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7680 { 4239 /* amomaxu.h.rl */, RISCV::AMOMAXU_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7681 { 4252 /* amomaxu.w */, RISCV::AMOMAXU_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7682 { 4262 /* amomaxu.w.aq */, RISCV::AMOMAXU_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7683 { 4275 /* amomaxu.w.aqrl */, RISCV::AMOMAXU_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7684 { 4290 /* amomaxu.w.rl */, RISCV::AMOMAXU_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7685 { 4303 /* amomin.b */, RISCV::AMOMIN_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7686 { 4312 /* amomin.b.aq */, RISCV::AMOMIN_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7687 { 4324 /* amomin.b.aqrl */, RISCV::AMOMIN_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7688 { 4338 /* amomin.b.rl */, RISCV::AMOMIN_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7689 { 4350 /* amomin.d */, RISCV::AMOMIN_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7690 { 4359 /* amomin.d.aq */, RISCV::AMOMIN_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7691 { 4371 /* amomin.d.aqrl */, RISCV::AMOMIN_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7692 { 4385 /* amomin.d.rl */, RISCV::AMOMIN_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7693 { 4397 /* amomin.h */, RISCV::AMOMIN_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7694 { 4406 /* amomin.h.aq */, RISCV::AMOMIN_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7695 { 4418 /* amomin.h.aqrl */, RISCV::AMOMIN_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7696 { 4432 /* amomin.h.rl */, RISCV::AMOMIN_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7697 { 4444 /* amomin.w */, RISCV::AMOMIN_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7698 { 4453 /* amomin.w.aq */, RISCV::AMOMIN_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7699 { 4465 /* amomin.w.aqrl */, RISCV::AMOMIN_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7700 { 4479 /* amomin.w.rl */, RISCV::AMOMIN_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7701 { 4491 /* amominu.b */, RISCV::AMOMINU_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7702 { 4501 /* amominu.b.aq */, RISCV::AMOMINU_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7703 { 4514 /* amominu.b.aqrl */, RISCV::AMOMINU_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7704 { 4529 /* amominu.b.rl */, RISCV::AMOMINU_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7705 { 4542 /* amominu.d */, RISCV::AMOMINU_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7706 { 4552 /* amominu.d.aq */, RISCV::AMOMINU_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7707 { 4565 /* amominu.d.aqrl */, RISCV::AMOMINU_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7708 { 4580 /* amominu.d.rl */, RISCV::AMOMINU_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7709 { 4593 /* amominu.h */, RISCV::AMOMINU_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7710 { 4603 /* amominu.h.aq */, RISCV::AMOMINU_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7711 { 4616 /* amominu.h.aqrl */, RISCV::AMOMINU_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7712 { 4631 /* amominu.h.rl */, RISCV::AMOMINU_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7713 { 4644 /* amominu.w */, RISCV::AMOMINU_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7714 { 4654 /* amominu.w.aq */, RISCV::AMOMINU_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7715 { 4667 /* amominu.w.aqrl */, RISCV::AMOMINU_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7716 { 4682 /* amominu.w.rl */, RISCV::AMOMINU_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7717 { 4695 /* amoor.b */, RISCV::AMOOR_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7718 { 4703 /* amoor.b.aq */, RISCV::AMOOR_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7719 { 4714 /* amoor.b.aqrl */, RISCV::AMOOR_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7720 { 4727 /* amoor.b.rl */, RISCV::AMOOR_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7721 { 4738 /* amoor.d */, RISCV::AMOOR_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7722 { 4746 /* amoor.d.aq */, RISCV::AMOOR_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7723 { 4757 /* amoor.d.aqrl */, RISCV::AMOOR_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7724 { 4770 /* amoor.d.rl */, RISCV::AMOOR_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7725 { 4781 /* amoor.h */, RISCV::AMOOR_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7726 { 4789 /* amoor.h.aq */, RISCV::AMOOR_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7727 { 4800 /* amoor.h.aqrl */, RISCV::AMOOR_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7728 { 4813 /* amoor.h.rl */, RISCV::AMOOR_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7729 { 4824 /* amoor.w */, RISCV::AMOOR_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7730 { 4832 /* amoor.w.aq */, RISCV::AMOOR_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7731 { 4843 /* amoor.w.aqrl */, RISCV::AMOOR_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7732 { 4856 /* amoor.w.rl */, RISCV::AMOOR_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7733 { 4867 /* amoswap.b */, RISCV::AMOSWAP_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7734 { 4877 /* amoswap.b.aq */, RISCV::AMOSWAP_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7735 { 4890 /* amoswap.b.aqrl */, RISCV::AMOSWAP_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7736 { 4905 /* amoswap.b.rl */, RISCV::AMOSWAP_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7737 { 4918 /* amoswap.d */, RISCV::AMOSWAP_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7738 { 4928 /* amoswap.d.aq */, RISCV::AMOSWAP_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7739 { 4941 /* amoswap.d.aqrl */, RISCV::AMOSWAP_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7740 { 4956 /* amoswap.d.rl */, RISCV::AMOSWAP_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7741 { 4969 /* amoswap.h */, RISCV::AMOSWAP_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7742 { 4979 /* amoswap.h.aq */, RISCV::AMOSWAP_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7743 { 4992 /* amoswap.h.aqrl */, RISCV::AMOSWAP_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7744 { 5007 /* amoswap.h.rl */, RISCV::AMOSWAP_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7745 { 5020 /* amoswap.w */, RISCV::AMOSWAP_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7746 { 5030 /* amoswap.w.aq */, RISCV::AMOSWAP_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7747 { 5043 /* amoswap.w.aqrl */, RISCV::AMOSWAP_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7748 { 5058 /* amoswap.w.rl */, RISCV::AMOSWAP_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7749 { 5071 /* amoxor.b */, RISCV::AMOXOR_B, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7750 { 5080 /* amoxor.b.aq */, RISCV::AMOXOR_B_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7751 { 5092 /* amoxor.b.aqrl */, RISCV::AMOXOR_B_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7752 { 5106 /* amoxor.b.rl */, RISCV::AMOXOR_B_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7753 { 5118 /* amoxor.d */, RISCV::AMOXOR_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7754 { 5127 /* amoxor.d.aq */, RISCV::AMOXOR_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7755 { 5139 /* amoxor.d.aqrl */, RISCV::AMOXOR_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7756 { 5153 /* amoxor.d.rl */, RISCV::AMOXOR_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7757 { 5165 /* amoxor.h */, RISCV::AMOXOR_H, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7758 { 5174 /* amoxor.h.aq */, RISCV::AMOXOR_H_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7759 { 5186 /* amoxor.h.aqrl */, RISCV::AMOXOR_H_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7760 { 5200 /* amoxor.h.rl */, RISCV::AMOXOR_H_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7761 { 5212 /* amoxor.w */, RISCV::AMOXOR_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7762 { 5221 /* amoxor.w.aq */, RISCV::AMOXOR_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7763 { 5233 /* amoxor.w.aqrl */, RISCV::AMOXOR_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7764 { 5247 /* amoxor.w.rl */, RISCV::AMOXOR_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
7765 { 5259 /* and */, RISCV::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7766 { 5259 /* and */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7767 { 5263 /* andi */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
7768 { 5268 /* andn */, RISCV::ANDN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7769 { 5273 /* asub */, RISCV::ASUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7770 { 5278 /* asubu */, RISCV::ASUBU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7771 { 5284 /* auipc */, RISCV::AUIPC, Convert__Reg1_0__UImm20AUIPC1_1, AMFBS_None, { MCK_GPR, MCK_UImm20AUIPC }, },
7772 { 5290 /* bclr */, RISCV::BCLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7773 { 5290 /* bclr */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7774 { 5295 /* bclri */, RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7775 { 5301 /* beq */, RISCV::BEQ, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7776 { 5305 /* beqi */, RISCV::BEQI, Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2, AMFBS_HasStdExtZibi, { MCK_GPR, MCK_Imm5Zibi, MCK_BareSImm13Lsb0 }, },
7777 { 5310 /* beqz */, RISCV::BEQ, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7778 { 5315 /* bext */, RISCV::BEXT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7779 { 5315 /* bext */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7780 { 5320 /* bexti */, RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7781 { 5326 /* bge */, RISCV::BGE, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7782 { 5330 /* bgeu */, RISCV::BGEU, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7783 { 5335 /* bgez */, RISCV::BGE, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7784 { 5340 /* bgt */, RISCV::BLT, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7785 { 5344 /* bgtu */, RISCV::BLTU, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7786 { 5349 /* bgtz */, RISCV::BLT, Convert__regX0__Reg1_0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7787 { 5354 /* binv */, RISCV::BINV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7788 { 5354 /* binv */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7789 { 5359 /* binvi */, RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7790 { 5365 /* ble */, RISCV::BGE, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7791 { 5369 /* bleu */, RISCV::BGEU, Convert__Reg1_1__Reg1_0__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7792 { 5374 /* blez */, RISCV::BGE, Convert__regX0__Reg1_0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7793 { 5379 /* blt */, RISCV::BLT, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7794 { 5383 /* bltu */, RISCV::BLTU, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7795 { 5388 /* bltz */, RISCV::BLT, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7796 { 5393 /* bne */, RISCV::BNE, Convert__Reg1_0__Reg1_1__BareSImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSImm13Lsb0 }, },
7797 { 5397 /* bnei */, RISCV::BNEI, Convert__Reg1_0__Imm5Zibi1_1__BareSImm13Lsb01_2, AMFBS_HasStdExtZibi, { MCK_GPR, MCK_Imm5Zibi, MCK_BareSImm13Lsb0 }, },
7798 { 5402 /* bnez */, RISCV::BNE, Convert__Reg1_0__regX0__BareSImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm13Lsb0 }, },
7799 { 5407 /* brev8 */, RISCV::BREV8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR }, },
7800 { 5413 /* bset */, RISCV::BSET, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7801 { 5413 /* bset */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7802 { 5418 /* bseti */, RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
7803 { 5424 /* c.add */, RISCV::C_ADD, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_GPRNoX0 }, },
7804 { 5430 /* c.addi */, RISCV::PseudoC_ADDI_NOP, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRX0, MCK_SImm6 }, },
7805 { 5430 /* c.addi */, RISCV::C_ADDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK_SImm6 }, },
7806 { 5437 /* c.addi16sp */, RISCV::C_ADDI16SP, Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, AMFBS_HasStdExtZca, { MCK_SP, MCK_SImm10Lsb0000NonZero }, },
7807 { 5448 /* c.addi4spn */, RISCV::C_ADDI4SPN, Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_SP, MCK_UImm10Lsb00NonZero }, },
7808 { 5459 /* c.addiw */, RISCV::C_ADDIW, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK_SImm6 }, },
7809 { 5467 /* c.addw */, RISCV::C_ADDW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
7810 { 5474 /* c.and */, RISCV::C_AND, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7811 { 5480 /* c.andi */, RISCV::C_ANDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_SImm6 }, },
7812 { 5487 /* c.beqz */, RISCV::C_BEQZ, Convert__Reg1_0__BareSImm9Lsb01_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_BareSImm9Lsb0 }, },
7813 { 5494 /* c.bnez */, RISCV::C_BNEZ, Convert__Reg1_0__BareSImm9Lsb01_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_BareSImm9Lsb0 }, },
7814 { 5501 /* c.ebreak */, RISCV::C_EBREAK, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
7815 { 5510 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7816 { 5510 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7817 { 5516 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK__40_, MCK_SP, MCK__41_ }, },
7818 { 5516 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7819 { 5524 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7820 { 5524 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7821 { 5530 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK__40_, MCK_SP, MCK__41_ }, },
7822 { 5530 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7823 { 5538 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7824 { 5538 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7825 { 5544 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK__40_, MCK_SP, MCK__41_ }, },
7826 { 5544 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZcd, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7827 { 5552 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
7828 { 5552 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7829 { 5558 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK__40_, MCK_SP, MCK__41_ }, },
7830 { 5558 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZcf_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7831 { 5566 /* c.j */, RISCV::C_J, Convert__BareSImm12Lsb01_0, AMFBS_HasStdExtZca, { MCK_BareSImm12Lsb0 }, },
7832 { 5570 /* c.jal */, RISCV::C_JAL, Convert__BareSImm12Lsb01_0, AMFBS_HasStdExtZca_IsRV32, { MCK_BareSImm12Lsb0 }, },
7833 { 5576 /* c.jalr */, RISCV::C_JALR, Convert__Reg1_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0 }, },
7834 { 5583 /* c.jr */, RISCV::C_JR, Convert__Reg1_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0 }, },
7835 { 5588 /* c.lbu */, RISCV::C_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7836 { 5588 /* c.lbu */, RISCV::PseudoQCAccessC_LBU, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7837 { 5588 /* c.lbu */, RISCV::C_LBU, Convert__Reg1_0__Reg1_3__UImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
7838 { 5588 /* c.lbu */, RISCV::PseudoQCAccessC_LBU, Convert__Reg1_0__Reg1_3__UImm21_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7839 { 5594 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7840 { 5594 /* c.ld */, RISCV::C_LD_RV32, Convert__GPRPairCRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK__40_, MCK_GPRC, MCK__41_ }, },
7841 { 5594 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7842 { 5594 /* c.ld */, RISCV::C_LD_RV32, Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7843 { 5599 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
7844 { 5599 /* c.ldsp */, RISCV::C_LDSP_RV32, Convert__GPRPairNoX0RV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairNoX0RV32, MCK__40_, MCK_SP, MCK__41_ }, },
7845 { 5599 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRNoX0, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7846 { 5599 /* c.ldsp */, RISCV::C_LDSP_RV32, Convert__GPRPairNoX0RV321_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairNoX0RV32, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7847 { 5606 /* c.lh */, RISCV::C_LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7848 { 5606 /* c.lh */, RISCV::PseudoQCAccessC_LH, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7849 { 5606 /* c.lh */, RISCV::C_LH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
7850 { 5606 /* c.lh */, RISCV::PseudoQCAccessC_LH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7851 { 5611 /* c.lhu */, RISCV::C_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7852 { 5611 /* c.lhu */, RISCV::PseudoQCAccessC_LHU, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7853 { 5611 /* c.lhu */, RISCV::C_LHU, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
7854 { 5611 /* c.lhu */, RISCV::PseudoQCAccessC_LHU, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7855 { 5617 /* c.li */, RISCV::C_LI, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_SImm6 }, },
7856 { 5622 /* c.lui */, RISCV::C_LUI, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtZca, { MCK_GPRNoX2, MCK_CLUIImm }, },
7857 { 5628 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7858 { 5628 /* c.lw */, RISCV::PseudoQCAccessC_LW, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7859 { 5628 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7860 { 5628 /* c.lw */, RISCV::PseudoQCAccessC_LW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7861 { 5633 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
7862 { 5633 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRNoX0, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7863 { 5640 /* c.mop.1 */, RISCV::C_SSPUSH, Convert__regX1, AMFBS_HasStdExtZcmop, { }, },
7864 { 5648 /* c.mop.11 */, RISCV::C_MOP_11, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7865 { 5657 /* c.mop.13 */, RISCV::C_MOP_13, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7866 { 5666 /* c.mop.15 */, RISCV::C_MOP_15, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7867 { 5675 /* c.mop.3 */, RISCV::C_MOP_3, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7868 { 5683 /* c.mop.5 */, RISCV::C_SSPOPCHK, Convert__regX5, AMFBS_HasStdExtZcmop, { }, },
7869 { 5691 /* c.mop.7 */, RISCV::C_MOP_7, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7870 { 5699 /* c.mop.9 */, RISCV::C_MOP_9, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
7871 { 5707 /* c.mul */, RISCV::C_MUL, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZcb_HasStdExtZmmul, { MCK_GPRC, MCK_GPRC }, },
7872 { 5713 /* c.mv */, RISCV::C_MV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_GPRNoX0 }, },
7873 { 5718 /* c.nop */, RISCV::C_NOP, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
7874 { 5718 /* c.nop */, RISCV::C_NOP_HINT, Convert__SImm6NonZero1_0, AMFBS_HasStdExtZca, { MCK_SImm6NonZero }, },
7875 { 5724 /* c.not */, RISCV::C_NOT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
7876 { 5730 /* c.ntl.all */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX5, AMFBS_HasStdExtZca, { }, },
7877 { 5740 /* c.ntl.p1 */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX2, AMFBS_HasStdExtZca, { }, },
7878 { 5749 /* c.ntl.pall */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX3, AMFBS_HasStdExtZca, { }, },
7879 { 5760 /* c.ntl.s1 */, RISCV::C_ADD, Convert__regX0__Tie0_1_1__regX4, AMFBS_HasStdExtZca, { }, },
7880 { 5769 /* c.or */, RISCV::C_OR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7881 { 5774 /* c.sb */, RISCV::C_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7882 { 5774 /* c.sb */, RISCV::PseudoQCAccessC_SB, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7883 { 5774 /* c.sb */, RISCV::C_SB, Convert__Reg1_0__Reg1_3__UImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
7884 { 5774 /* c.sb */, RISCV::PseudoQCAccessC_SB, Convert__Reg1_0__Reg1_3__UImm21_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7885 { 5779 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7886 { 5779 /* c.sd */, RISCV::C_SD_RV32, Convert__GPRPairCRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK__40_, MCK_GPRC, MCK__41_ }, },
7887 { 5779 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7888 { 5779 /* c.sd */, RISCV::C_SD_RV32, Convert__GPRPairCRV321_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairCRV32, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
7889 { 5784 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca_IsRV64, { MCK_GPR, MCK__40_, MCK_SP, MCK__41_ }, },
7890 { 5784 /* c.sdsp */, RISCV::C_SDSP_RV32, Convert__GPRPairRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairRV32, MCK__40_, MCK_SP, MCK__41_ }, },
7891 { 5784 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPR, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7892 { 5784 /* c.sdsp */, RISCV::C_SDSP_RV32, Convert__GPRPairRV321_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtZclsd_IsRV32, { MCK_GPRPairRV32, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
7893 { 5791 /* c.sext.b */, RISCV::C_SEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
7894 { 5800 /* c.sext.h */, RISCV::C_SEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
7895 { 5809 /* c.sh */, RISCV::C_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7896 { 5809 /* c.sh */, RISCV::PseudoQCAccessC_SH, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7897 { 5809 /* c.sh */, RISCV::C_SH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
7898 { 5809 /* c.sh */, RISCV::PseudoQCAccessC_SH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7899 { 5814 /* c.slli */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_UImmLog2XLen }, },
7900 { 5821 /* c.slli64 */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPR }, },
7901 { 5830 /* c.srai */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImmLog2XLen }, },
7902 { 5837 /* c.srai64 */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC }, },
7903 { 5846 /* c.srli */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLen1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImmLog2XLen }, },
7904 { 5853 /* c.srli64 */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC }, },
7905 { 5862 /* c.sspopchk */, RISCV::C_SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZcmop, { MCK_GPRX5 }, },
7906 { 5873 /* c.sspush */, RISCV::C_SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZcmop, { MCK_GPRX1 }, },
7907 { 5882 /* c.sub */, RISCV::C_SUB, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7908 { 5888 /* c.subw */, RISCV::C_SUBW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
7909 { 5895 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
7910 { 5895 /* c.sw */, RISCV::PseudoQCAccessC_SW, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7911 { 5895 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
7912 { 5895 /* c.sw */, RISCV::PseudoQCAccessC_SW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1__QCAccessSymbol1_5, AMFBS_IsRV32_HasStdExtZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_, MCK_QCAccessSymbol }, },
7913 { 5900 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZca, { MCK_GPR, MCK__40_, MCK_SP, MCK__41_ }, },
7914 { 5900 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtZca, { MCK_GPR, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
7915 { 5907 /* c.unimp */, RISCV::C_UNIMP, Convert_NoOperands, AMFBS_HasStdExtZca, { }, },
7916 { 5915 /* c.xor */, RISCV::C_XOR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZca, { MCK_GPRC, MCK_GPRC }, },
7917 { 5921 /* c.zext.b */, RISCV::C_ZEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
7918 { 5930 /* c.zext.h */, RISCV::C_ZEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
7919 { 5939 /* c.zext.w */, RISCV::C_ZEXT_W, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64, { MCK_GPRC }, },
7920 { 5948 /* call */, RISCV::PseudoCALL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
7921 { 5948 /* call */, RISCV::PseudoCALLReg, Convert__Reg1_0__CallSymbol1_1, AMFBS_None, { MCK_GPR, MCK_CallSymbol }, },
7922 { 5953 /* cbo.clean */, RISCV::CBO_CLEAN, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
7923 { 5963 /* cbo.flush */, RISCV::CBO_FLUSH, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
7924 { 5973 /* cbo.inval */, RISCV::CBO_INVAL, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
7925 { 5983 /* cbo.zero */, RISCV::CBO_ZERO, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicboz, { MCK_ZeroOffsetMemOpOperand }, },
7926 { 5992 /* clmul */, RISCV::CLMUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7927 { 5998 /* clmulh */, RISCV::CLMULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7928 { 6005 /* clmulr */, RISCV::CLMULR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7929 { 6012 /* cls */, RISCV::CLS, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
7930 { 6016 /* clsw */, RISCV::CLSW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
7931 { 6021 /* clz */, RISCV::CLZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
7932 { 6025 /* clzw */, RISCV::CLZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
7933 { 6030 /* cm.jalt */, RISCV::CM_JALT, Convert__UImm8GE321_0, AMFBS_HasStdExtZcmt, { MCK_UImm8GE32 }, },
7934 { 6038 /* cm.jt */, RISCV::CM_JT, Convert__UImm51_0, AMFBS_HasStdExtZcmt, { MCK_UImm5 }, },
7935 { 6044 /* cm.mva01s */, RISCV::CM_MVA01S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_SR07, MCK_SR07 }, },
7936 { 6054 /* cm.mvsa01 */, RISCV::CM_MVSA01, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_SR07, MCK_SR07 }, },
7937 { 6064 /* cm.pop */, RISCV::CM_POP, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
7938 { 6071 /* cm.popret */, RISCV::CM_POPRET, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
7939 { 6081 /* cm.popretz */, RISCV::CM_POPRETZ, Convert__RegList1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_StackAdj }, },
7940 { 6092 /* cm.push */, RISCV::CM_PUSH, Convert__RegList1_0__NegStackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_RegList, MCK_NegStackAdj }, },
7941 { 6100 /* cpop */, RISCV::CPOP, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
7942 { 6105 /* cpopw */, RISCV::CPOPW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
7943 { 6111 /* csrc */, RISCV::CSRRC, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
7944 { 6111 /* csrc */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7945 { 6116 /* csrci */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7946 { 6122 /* csrr */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, },
7947 { 6127 /* csrrc */, RISCV::CSRRC, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
7948 { 6127 /* csrrc */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7949 { 6133 /* csrrci */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7950 { 6140 /* csrrs */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
7951 { 6140 /* csrrs */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7952 { 6146 /* csrrsi */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7953 { 6153 /* csrrw */, RISCV::CSRRW, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
7954 { 6153 /* csrrw */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7955 { 6159 /* csrrwi */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
7956 { 6166 /* csrs */, RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
7957 { 6166 /* csrs */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7958 { 6171 /* csrsi */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7959 { 6177 /* csrw */, RISCV::CSRRW, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
7960 { 6177 /* csrw */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7961 { 6182 /* csrwi */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
7962 { 6188 /* ctz */, RISCV::CTZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
7963 { 6192 /* ctzw */, RISCV::CTZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
7964 { 6197 /* cv.abs */, RISCV::CV_ABS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
7965 { 6204 /* cv.abs.b */, RISCV::CV_ABS_B, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
7966 { 6213 /* cv.abs.h */, RISCV::CV_ABS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
7967 { 6222 /* cv.add.b */, RISCV::CV_ADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7968 { 6231 /* cv.add.div2 */, RISCV::CV_ADD_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7969 { 6243 /* cv.add.div4 */, RISCV::CV_ADD_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7970 { 6255 /* cv.add.div8 */, RISCV::CV_ADD_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7971 { 6267 /* cv.add.h */, RISCV::CV_ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7972 { 6276 /* cv.add.sc.b */, RISCV::CV_ADD_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7973 { 6288 /* cv.add.sc.h */, RISCV::CV_ADD_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7974 { 6300 /* cv.add.sci.b */, RISCV::CV_ADD_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7975 { 6313 /* cv.add.sci.h */, RISCV::CV_ADD_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7976 { 6326 /* cv.addn */, RISCV::CV_ADDN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7977 { 6334 /* cv.addnr */, RISCV::CV_ADDNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7978 { 6343 /* cv.addrn */, RISCV::CV_ADDRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7979 { 6352 /* cv.addrnr */, RISCV::CV_ADDRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7980 { 6362 /* cv.addun */, RISCV::CV_ADDUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7981 { 6371 /* cv.addunr */, RISCV::CV_ADDUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7982 { 6381 /* cv.addurn */, RISCV::CV_ADDURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
7983 { 6391 /* cv.addurnr */, RISCV::CV_ADDURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7984 { 6402 /* cv.and.b */, RISCV::CV_AND_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7985 { 6411 /* cv.and.h */, RISCV::CV_AND_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7986 { 6420 /* cv.and.sc.b */, RISCV::CV_AND_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7987 { 6432 /* cv.and.sc.h */, RISCV::CV_AND_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7988 { 6444 /* cv.and.sci.b */, RISCV::CV_AND_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7989 { 6457 /* cv.and.sci.h */, RISCV::CV_AND_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7990 { 6470 /* cv.avg.b */, RISCV::CV_AVG_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7991 { 6479 /* cv.avg.h */, RISCV::CV_AVG_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7992 { 6488 /* cv.avg.sc.b */, RISCV::CV_AVG_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7993 { 6500 /* cv.avg.sc.h */, RISCV::CV_AVG_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7994 { 6512 /* cv.avg.sci.b */, RISCV::CV_AVG_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7995 { 6525 /* cv.avg.sci.h */, RISCV::CV_AVG_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
7996 { 6538 /* cv.avgu.b */, RISCV::CV_AVGU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7997 { 6548 /* cv.avgu.h */, RISCV::CV_AVGU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7998 { 6558 /* cv.avgu.sc.b */, RISCV::CV_AVGU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
7999 { 6571 /* cv.avgu.sc.h */, RISCV::CV_AVGU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8000 { 6584 /* cv.avgu.sci.b */, RISCV::CV_AVGU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8001 { 6598 /* cv.avgu.sci.h */, RISCV::CV_AVGU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8002 { 6612 /* cv.bclr */, RISCV::CV_BCLR, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8003 { 6620 /* cv.bclrr */, RISCV::CV_BCLRR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8004 { 6629 /* cv.beqimm */, RISCV::CV_BEQIMM, Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_BareSImm13Lsb0 }, },
8005 { 6639 /* cv.bitrev */, RISCV::CV_BITREV, Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm2, MCK_UImm5 }, },
8006 { 6649 /* cv.bneimm */, RISCV::CV_BNEIMM, Convert__Reg1_0__SImm51_1__BareSImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_BareSImm13Lsb0 }, },
8007 { 6659 /* cv.bset */, RISCV::CV_BSET, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8008 { 6667 /* cv.bsetr */, RISCV::CV_BSETR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8009 { 6676 /* cv.clb */, RISCV::CV_CLB, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8010 { 6683 /* cv.clip */, RISCV::CV_CLIP, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8011 { 6691 /* cv.clipr */, RISCV::CV_CLIPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8012 { 6700 /* cv.clipu */, RISCV::CV_CLIPU, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8013 { 6709 /* cv.clipur */, RISCV::CV_CLIPUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8014 { 6719 /* cv.cmpeq.b */, RISCV::CV_CMPEQ_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8015 { 6730 /* cv.cmpeq.h */, RISCV::CV_CMPEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8016 { 6741 /* cv.cmpeq.sc.b */, RISCV::CV_CMPEQ_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8017 { 6755 /* cv.cmpeq.sc.h */, RISCV::CV_CMPEQ_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8018 { 6769 /* cv.cmpeq.sci.b */, RISCV::CV_CMPEQ_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8019 { 6784 /* cv.cmpeq.sci.h */, RISCV::CV_CMPEQ_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8020 { 6799 /* cv.cmpge.b */, RISCV::CV_CMPGE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8021 { 6810 /* cv.cmpge.h */, RISCV::CV_CMPGE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8022 { 6821 /* cv.cmpge.sc.b */, RISCV::CV_CMPGE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8023 { 6835 /* cv.cmpge.sc.h */, RISCV::CV_CMPGE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8024 { 6849 /* cv.cmpge.sci.b */, RISCV::CV_CMPGE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8025 { 6864 /* cv.cmpge.sci.h */, RISCV::CV_CMPGE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8026 { 6879 /* cv.cmpgeu.b */, RISCV::CV_CMPGEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8027 { 6891 /* cv.cmpgeu.h */, RISCV::CV_CMPGEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8028 { 6903 /* cv.cmpgeu.sc.b */, RISCV::CV_CMPGEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8029 { 6918 /* cv.cmpgeu.sc.h */, RISCV::CV_CMPGEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8030 { 6933 /* cv.cmpgeu.sci.b */, RISCV::CV_CMPGEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8031 { 6949 /* cv.cmpgeu.sci.h */, RISCV::CV_CMPGEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8032 { 6965 /* cv.cmpgt.b */, RISCV::CV_CMPGT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8033 { 6976 /* cv.cmpgt.h */, RISCV::CV_CMPGT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8034 { 6987 /* cv.cmpgt.sc.b */, RISCV::CV_CMPGT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8035 { 7001 /* cv.cmpgt.sc.h */, RISCV::CV_CMPGT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8036 { 7015 /* cv.cmpgt.sci.b */, RISCV::CV_CMPGT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8037 { 7030 /* cv.cmpgt.sci.h */, RISCV::CV_CMPGT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8038 { 7045 /* cv.cmpgtu.b */, RISCV::CV_CMPGTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8039 { 7057 /* cv.cmpgtu.h */, RISCV::CV_CMPGTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8040 { 7069 /* cv.cmpgtu.sc.b */, RISCV::CV_CMPGTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8041 { 7084 /* cv.cmpgtu.sc.h */, RISCV::CV_CMPGTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8042 { 7099 /* cv.cmpgtu.sci.b */, RISCV::CV_CMPGTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8043 { 7115 /* cv.cmpgtu.sci.h */, RISCV::CV_CMPGTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8044 { 7131 /* cv.cmple.b */, RISCV::CV_CMPLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8045 { 7142 /* cv.cmple.h */, RISCV::CV_CMPLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8046 { 7153 /* cv.cmple.sc.b */, RISCV::CV_CMPLE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8047 { 7167 /* cv.cmple.sc.h */, RISCV::CV_CMPLE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8048 { 7181 /* cv.cmple.sci.b */, RISCV::CV_CMPLE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8049 { 7196 /* cv.cmple.sci.h */, RISCV::CV_CMPLE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8050 { 7211 /* cv.cmpleu.b */, RISCV::CV_CMPLEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8051 { 7223 /* cv.cmpleu.h */, RISCV::CV_CMPLEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8052 { 7235 /* cv.cmpleu.sc.b */, RISCV::CV_CMPLEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8053 { 7250 /* cv.cmpleu.sc.h */, RISCV::CV_CMPLEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8054 { 7265 /* cv.cmpleu.sci.b */, RISCV::CV_CMPLEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8055 { 7281 /* cv.cmpleu.sci.h */, RISCV::CV_CMPLEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8056 { 7297 /* cv.cmplt.b */, RISCV::CV_CMPLT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8057 { 7308 /* cv.cmplt.h */, RISCV::CV_CMPLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8058 { 7319 /* cv.cmplt.sc.b */, RISCV::CV_CMPLT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8059 { 7333 /* cv.cmplt.sc.h */, RISCV::CV_CMPLT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8060 { 7347 /* cv.cmplt.sci.b */, RISCV::CV_CMPLT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8061 { 7362 /* cv.cmplt.sci.h */, RISCV::CV_CMPLT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8062 { 7377 /* cv.cmpltu.b */, RISCV::CV_CMPLTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8063 { 7389 /* cv.cmpltu.h */, RISCV::CV_CMPLTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8064 { 7401 /* cv.cmpltu.sc.b */, RISCV::CV_CMPLTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8065 { 7416 /* cv.cmpltu.sc.h */, RISCV::CV_CMPLTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8066 { 7431 /* cv.cmpltu.sci.b */, RISCV::CV_CMPLTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8067 { 7447 /* cv.cmpltu.sci.h */, RISCV::CV_CMPLTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8068 { 7463 /* cv.cmpne.b */, RISCV::CV_CMPNE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8069 { 7474 /* cv.cmpne.h */, RISCV::CV_CMPNE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8070 { 7485 /* cv.cmpne.sc.b */, RISCV::CV_CMPNE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8071 { 7499 /* cv.cmpne.sc.h */, RISCV::CV_CMPNE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8072 { 7513 /* cv.cmpne.sci.b */, RISCV::CV_CMPNE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8073 { 7528 /* cv.cmpne.sci.h */, RISCV::CV_CMPNE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8074 { 7543 /* cv.cnt */, RISCV::CV_CNT, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8075 { 7550 /* cv.cplxconj */, RISCV::CV_CPLXCONJ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
8076 { 7562 /* cv.cplxmul.i */, RISCV::CV_CPLXMUL_I, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8077 { 7575 /* cv.cplxmul.i.div2 */, RISCV::CV_CPLXMUL_I_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8078 { 7593 /* cv.cplxmul.i.div4 */, RISCV::CV_CPLXMUL_I_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8079 { 7611 /* cv.cplxmul.i.div8 */, RISCV::CV_CPLXMUL_I_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8080 { 7629 /* cv.cplxmul.r */, RISCV::CV_CPLXMUL_R, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8081 { 7642 /* cv.cplxmul.r.div2 */, RISCV::CV_CPLXMUL_R_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8082 { 7660 /* cv.cplxmul.r.div4 */, RISCV::CV_CPLXMUL_R_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8083 { 7678 /* cv.cplxmul.r.div8 */, RISCV::CV_CPLXMUL_R_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8084 { 7696 /* cv.dotsp.b */, RISCV::CV_DOTSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8085 { 7707 /* cv.dotsp.h */, RISCV::CV_DOTSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8086 { 7718 /* cv.dotsp.sc.b */, RISCV::CV_DOTSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8087 { 7732 /* cv.dotsp.sc.h */, RISCV::CV_DOTSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8088 { 7746 /* cv.dotsp.sci.b */, RISCV::CV_DOTSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8089 { 7761 /* cv.dotsp.sci.h */, RISCV::CV_DOTSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8090 { 7776 /* cv.dotup.b */, RISCV::CV_DOTUP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8091 { 7787 /* cv.dotup.h */, RISCV::CV_DOTUP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8092 { 7798 /* cv.dotup.sc.b */, RISCV::CV_DOTUP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8093 { 7812 /* cv.dotup.sc.h */, RISCV::CV_DOTUP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8094 { 7826 /* cv.dotup.sci.b */, RISCV::CV_DOTUP_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8095 { 7841 /* cv.dotup.sci.h */, RISCV::CV_DOTUP_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8096 { 7856 /* cv.dotusp.b */, RISCV::CV_DOTUSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8097 { 7868 /* cv.dotusp.h */, RISCV::CV_DOTUSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8098 { 7880 /* cv.dotusp.sc.b */, RISCV::CV_DOTUSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8099 { 7895 /* cv.dotusp.sc.h */, RISCV::CV_DOTUSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8100 { 7910 /* cv.dotusp.sci.b */, RISCV::CV_DOTUSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8101 { 7926 /* cv.dotusp.sci.h */, RISCV::CV_DOTUSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8102 { 7942 /* cv.elw */, RISCV::PseudoCV_ELW, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXCVelw_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
8103 { 7942 /* cv.elw */, RISCV::CV_ELW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasVendorXCVelw_IsRV32, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8104 { 7949 /* cv.extbs */, RISCV::CV_EXTBS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8105 { 7958 /* cv.extbz */, RISCV::CV_EXTBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8106 { 7967 /* cv.exths */, RISCV::CV_EXTHS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8107 { 7976 /* cv.exthz */, RISCV::CV_EXTHZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
8108 { 7985 /* cv.extract */, RISCV::CV_EXTRACT, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8109 { 7996 /* cv.extract.b */, RISCV::CV_EXTRACT_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8110 { 8009 /* cv.extract.h */, RISCV::CV_EXTRACT_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8111 { 8022 /* cv.extractr */, RISCV::CV_EXTRACTR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8112 { 8034 /* cv.extractu */, RISCV::CV_EXTRACTU, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8113 { 8046 /* cv.extractu.b */, RISCV::CV_EXTRACTU_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8114 { 8060 /* cv.extractu.h */, RISCV::CV_EXTRACTU_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8115 { 8074 /* cv.extractur */, RISCV::CV_EXTRACTUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8116 { 8087 /* cv.ff1 */, RISCV::CV_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8117 { 8094 /* cv.fl1 */, RISCV::CV_FL1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
8118 { 8101 /* cv.insert */, RISCV::CV_INSERT, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
8119 { 8111 /* cv.insert.b */, RISCV::CV_INSERT_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8120 { 8123 /* cv.insert.h */, RISCV::CV_INSERT_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8121 { 8135 /* cv.insertr */, RISCV::CV_INSERTR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8122 { 8146 /* cv.lb */, RISCV::CV_LB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8123 { 8146 /* cv.lb */, RISCV::CV_LB_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8124 { 8146 /* cv.lb */, RISCV::CV_LB_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
8125 { 8152 /* cv.lbu */, RISCV::CV_LBU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8126 { 8152 /* cv.lbu */, RISCV::CV_LBU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8127 { 8152 /* cv.lbu */, RISCV::CV_LBU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
8128 { 8159 /* cv.lh */, RISCV::CV_LH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8129 { 8159 /* cv.lh */, RISCV::CV_LH_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8130 { 8159 /* cv.lh */, RISCV::CV_LH_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
8131 { 8165 /* cv.lhu */, RISCV::CV_LHU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8132 { 8165 /* cv.lhu */, RISCV::CV_LHU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8133 { 8165 /* cv.lhu */, RISCV::CV_LHU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
8134 { 8172 /* cv.lw */, RISCV::CV_LW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8135 { 8172 /* cv.lw */, RISCV::CV_LW_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8136 { 8172 /* cv.lw */, RISCV::CV_LW_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
8137 { 8178 /* cv.mac */, RISCV::CV_MAC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8138 { 8185 /* cv.machhsn */, RISCV::CV_MACHHSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8139 { 8196 /* cv.machhsrn */, RISCV::CV_MACHHSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8140 { 8208 /* cv.machhun */, RISCV::CV_MACHHUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8141 { 8219 /* cv.machhurn */, RISCV::CV_MACHHURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8142 { 8231 /* cv.macsn */, RISCV::CV_MACSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8143 { 8240 /* cv.macsrn */, RISCV::CV_MACSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8144 { 8250 /* cv.macun */, RISCV::CV_MACUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8145 { 8259 /* cv.macurn */, RISCV::CV_MACURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8146 { 8269 /* cv.max */, RISCV::CV_MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8147 { 8276 /* cv.max.b */, RISCV::CV_MAX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8148 { 8285 /* cv.max.h */, RISCV::CV_MAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8149 { 8294 /* cv.max.sc.b */, RISCV::CV_MAX_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8150 { 8306 /* cv.max.sc.h */, RISCV::CV_MAX_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8151 { 8318 /* cv.max.sci.b */, RISCV::CV_MAX_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8152 { 8331 /* cv.max.sci.h */, RISCV::CV_MAX_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8153 { 8344 /* cv.maxu */, RISCV::CV_MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8154 { 8352 /* cv.maxu.b */, RISCV::CV_MAXU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8155 { 8362 /* cv.maxu.h */, RISCV::CV_MAXU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8156 { 8372 /* cv.maxu.sc.b */, RISCV::CV_MAXU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8157 { 8385 /* cv.maxu.sc.h */, RISCV::CV_MAXU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8158 { 8398 /* cv.maxu.sci.b */, RISCV::CV_MAXU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8159 { 8412 /* cv.maxu.sci.h */, RISCV::CV_MAXU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8160 { 8426 /* cv.min */, RISCV::CV_MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8161 { 8433 /* cv.min.b */, RISCV::CV_MIN_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8162 { 8442 /* cv.min.h */, RISCV::CV_MIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8163 { 8451 /* cv.min.sc.b */, RISCV::CV_MIN_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8164 { 8463 /* cv.min.sc.h */, RISCV::CV_MIN_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8165 { 8475 /* cv.min.sci.b */, RISCV::CV_MIN_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8166 { 8488 /* cv.min.sci.h */, RISCV::CV_MIN_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8167 { 8501 /* cv.minu */, RISCV::CV_MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8168 { 8509 /* cv.minu.b */, RISCV::CV_MINU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8169 { 8519 /* cv.minu.h */, RISCV::CV_MINU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8170 { 8529 /* cv.minu.sc.b */, RISCV::CV_MINU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8171 { 8542 /* cv.minu.sc.h */, RISCV::CV_MINU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8172 { 8555 /* cv.minu.sci.b */, RISCV::CV_MINU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8173 { 8569 /* cv.minu.sci.h */, RISCV::CV_MINU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8174 { 8583 /* cv.msu */, RISCV::CV_MSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8175 { 8590 /* cv.mulhhs */, RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8176 { 8600 /* cv.mulhhsn */, RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8177 { 8611 /* cv.mulhhsrn */, RISCV::CV_MULHHSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8178 { 8623 /* cv.mulhhu */, RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8179 { 8633 /* cv.mulhhun */, RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8180 { 8644 /* cv.mulhhurn */, RISCV::CV_MULHHURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8181 { 8656 /* cv.muls */, RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8182 { 8664 /* cv.mulsn */, RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8183 { 8673 /* cv.mulsrn */, RISCV::CV_MULSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8184 { 8683 /* cv.mulu */, RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8185 { 8691 /* cv.mulun */, RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8186 { 8700 /* cv.mulurn */, RISCV::CV_MULURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8187 { 8710 /* cv.or.b */, RISCV::CV_OR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8188 { 8718 /* cv.or.h */, RISCV::CV_OR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8189 { 8726 /* cv.or.sc.b */, RISCV::CV_OR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8190 { 8737 /* cv.or.sc.h */, RISCV::CV_OR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8191 { 8748 /* cv.or.sci.b */, RISCV::CV_OR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8192 { 8760 /* cv.or.sci.h */, RISCV::CV_OR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8193 { 8772 /* cv.pack */, RISCV::CV_PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8194 { 8780 /* cv.pack.h */, RISCV::CV_PACK_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8195 { 8790 /* cv.packhi.b */, RISCV::CV_PACKHI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8196 { 8802 /* cv.packlo.b */, RISCV::CV_PACKLO_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8197 { 8814 /* cv.ror */, RISCV::CV_ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8198 { 8821 /* cv.sb */, RISCV::CV_SB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8199 { 8821 /* cv.sb */, RISCV::CV_SB_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8200 { 8821 /* cv.sb */, RISCV::CV_SB_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
8201 { 8827 /* cv.sdotsp.b */, RISCV::CV_SDOTSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8202 { 8839 /* cv.sdotsp.h */, RISCV::CV_SDOTSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8203 { 8851 /* cv.sdotsp.sc.b */, RISCV::CV_SDOTSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8204 { 8866 /* cv.sdotsp.sc.h */, RISCV::CV_SDOTSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8205 { 8881 /* cv.sdotsp.sci.b */, RISCV::CV_SDOTSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8206 { 8897 /* cv.sdotsp.sci.h */, RISCV::CV_SDOTSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8207 { 8913 /* cv.sdotup.b */, RISCV::CV_SDOTUP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8208 { 8925 /* cv.sdotup.h */, RISCV::CV_SDOTUP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8209 { 8937 /* cv.sdotup.sc.b */, RISCV::CV_SDOTUP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8210 { 8952 /* cv.sdotup.sc.h */, RISCV::CV_SDOTUP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8211 { 8967 /* cv.sdotup.sci.b */, RISCV::CV_SDOTUP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8212 { 8983 /* cv.sdotup.sci.h */, RISCV::CV_SDOTUP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8213 { 8999 /* cv.sdotusp.b */, RISCV::CV_SDOTUSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8214 { 9012 /* cv.sdotusp.h */, RISCV::CV_SDOTUSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8215 { 9025 /* cv.sdotusp.sc.b */, RISCV::CV_SDOTUSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8216 { 9041 /* cv.sdotusp.sc.h */, RISCV::CV_SDOTUSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8217 { 9057 /* cv.sdotusp.sci.b */, RISCV::CV_SDOTUSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8218 { 9074 /* cv.sdotusp.sci.h */, RISCV::CV_SDOTUSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8219 { 9091 /* cv.sh */, RISCV::CV_SH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8220 { 9091 /* cv.sh */, RISCV::CV_SH_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8221 { 9091 /* cv.sh */, RISCV::CV_SH_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
8222 { 9097 /* cv.shuffle.b */, RISCV::CV_SHUFFLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8223 { 9110 /* cv.shuffle.h */, RISCV::CV_SHUFFLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8224 { 9123 /* cv.shuffle.sci.h */, RISCV::CV_SHUFFLE_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8225 { 9140 /* cv.shuffle2.b */, RISCV::CV_SHUFFLE2_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8226 { 9154 /* cv.shuffle2.h */, RISCV::CV_SHUFFLE2_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8227 { 9168 /* cv.shufflei0.sci.b */, RISCV::CV_SHUFFLEI0_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8228 { 9187 /* cv.shufflei1.sci.b */, RISCV::CV_SHUFFLEI1_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8229 { 9206 /* cv.shufflei2.sci.b */, RISCV::CV_SHUFFLEI2_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8230 { 9225 /* cv.shufflei3.sci.b */, RISCV::CV_SHUFFLEI3_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
8231 { 9244 /* cv.sle */, RISCV::CV_SLE, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8232 { 9251 /* cv.sleu */, RISCV::CV_SLEU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8233 { 9259 /* cv.sll.b */, RISCV::CV_SLL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8234 { 9268 /* cv.sll.h */, RISCV::CV_SLL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8235 { 9277 /* cv.sll.sc.b */, RISCV::CV_SLL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8236 { 9289 /* cv.sll.sc.h */, RISCV::CV_SLL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8237 { 9301 /* cv.sll.sci.b */, RISCV::CV_SLL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8238 { 9314 /* cv.sll.sci.h */, RISCV::CV_SLL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8239 { 9327 /* cv.sra.b */, RISCV::CV_SRA_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8240 { 9336 /* cv.sra.h */, RISCV::CV_SRA_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8241 { 9345 /* cv.sra.sc.b */, RISCV::CV_SRA_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8242 { 9357 /* cv.sra.sc.h */, RISCV::CV_SRA_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8243 { 9369 /* cv.sra.sci.b */, RISCV::CV_SRA_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8244 { 9382 /* cv.sra.sci.h */, RISCV::CV_SRA_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8245 { 9395 /* cv.srl.b */, RISCV::CV_SRL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8246 { 9404 /* cv.srl.h */, RISCV::CV_SRL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8247 { 9413 /* cv.srl.sc.b */, RISCV::CV_SRL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8248 { 9425 /* cv.srl.sc.h */, RISCV::CV_SRL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8249 { 9437 /* cv.srl.sci.b */, RISCV::CV_SRL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
8250 { 9450 /* cv.srl.sci.h */, RISCV::CV_SRL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
8251 { 9463 /* cv.sub.b */, RISCV::CV_SUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8252 { 9472 /* cv.sub.div2 */, RISCV::CV_SUB_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8253 { 9484 /* cv.sub.div4 */, RISCV::CV_SUB_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8254 { 9496 /* cv.sub.div8 */, RISCV::CV_SUB_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8255 { 9508 /* cv.sub.h */, RISCV::CV_SUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8256 { 9517 /* cv.sub.sc.b */, RISCV::CV_SUB_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8257 { 9529 /* cv.sub.sc.h */, RISCV::CV_SUB_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8258 { 9541 /* cv.sub.sci.b */, RISCV::CV_SUB_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8259 { 9554 /* cv.sub.sci.h */, RISCV::CV_SUB_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8260 { 9567 /* cv.subn */, RISCV::CV_SUBN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8261 { 9575 /* cv.subnr */, RISCV::CV_SUBNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8262 { 9584 /* cv.subrn */, RISCV::CV_SUBRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8263 { 9593 /* cv.subrnr */, RISCV::CV_SUBRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8264 { 9603 /* cv.subrotmj */, RISCV::CV_SUBROTMJ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8265 { 9615 /* cv.subrotmj.div2 */, RISCV::CV_SUBROTMJ_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8266 { 9632 /* cv.subrotmj.div4 */, RISCV::CV_SUBROTMJ_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8267 { 9649 /* cv.subrotmj.div8 */, RISCV::CV_SUBROTMJ_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8268 { 9666 /* cv.subun */, RISCV::CV_SUBUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8269 { 9675 /* cv.subunr */, RISCV::CV_SUBUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8270 { 9685 /* cv.suburn */, RISCV::CV_SUBURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
8271 { 9695 /* cv.suburnr */, RISCV::CV_SUBURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8272 { 9706 /* cv.sw */, RISCV::CV_SW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
8273 { 9706 /* cv.sw */, RISCV::CV_SW_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
8274 { 9706 /* cv.sw */, RISCV::CV_SW_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm12LO1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12LO }, },
8275 { 9712 /* cv.xor.b */, RISCV::CV_XOR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8276 { 9721 /* cv.xor.h */, RISCV::CV_XOR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8277 { 9730 /* cv.xor.sc.b */, RISCV::CV_XOR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8278 { 9742 /* cv.xor.sc.h */, RISCV::CV_XOR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8279 { 9754 /* cv.xor.sci.b */, RISCV::CV_XOR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8280 { 9767 /* cv.xor.sci.h */, RISCV::CV_XOR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
8281 { 9780 /* czero.eqz */, RISCV::CZERO_EQZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8282 { 9790 /* czero.nez */, RISCV::CZERO_NEZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8283 { 9800 /* div */, RISCV::DIV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8284 { 9804 /* divu */, RISCV::DIVU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8285 { 9809 /* divuw */, RISCV::DIVUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8286 { 9815 /* divw */, RISCV::DIVW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8287 { 9820 /* dret */, RISCV::DRET, Convert_NoOperands, AMFBS_None, { }, },
8288 { 9825 /* ebreak */, RISCV::EBREAK, Convert_NoOperands, AMFBS_None, { }, },
8289 { 9832 /* ecall */, RISCV::ECALL, Convert_NoOperands, AMFBS_None, { }, },
8290 { 9838 /* fabs.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8291 { 9838 /* fabs.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8292 { 9838 /* fabs.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8293 { 9845 /* fabs.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8294 { 9845 /* fabs.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8295 { 9852 /* fabs.q */, RISCV::FSGNJX_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8296 { 9859 /* fabs.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8297 { 9859 /* fabs.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8298 { 9866 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8299 { 9866 /* fadd.d */, RISCV::FADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8300 { 9866 /* fadd.d */, RISCV::FADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8301 { 9873 /* fadd.h */, RISCV::FADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8302 { 9873 /* fadd.h */, RISCV::FADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8303 { 9880 /* fadd.q */, RISCV::FADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8304 { 9887 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8305 { 9887 /* fadd.s */, RISCV::FADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8306 { 9894 /* fclass.d */, RISCV::FCLASS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, },
8307 { 9894 /* fclass.d */, RISCV::FCLASS_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, },
8308 { 9894 /* fclass.d */, RISCV::FCLASS_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR }, },
8309 { 9903 /* fclass.h */, RISCV::FCLASS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16 }, },
8310 { 9903 /* fclass.h */, RISCV::FCLASS_H_INX, Convert__Reg1_0__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16 }, },
8311 { 9912 /* fclass.q */, RISCV::FCLASS_Q, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128 }, },
8312 { 9921 /* fclass.s */, RISCV::FCLASS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
8313 { 9921 /* fclass.s */, RISCV::FCLASS_S_INX, Convert__Reg1_0__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32 }, },
8314 { 9930 /* fcvt.bf16.s */, RISCV::FCVT_BF16_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
8315 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR64, MCK_FPR16, MCK_FRMArgLegacy }, },
8316 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8317 { 9942 /* fcvt.d.h */, RISCV::FCVT_D_H_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8318 { 9951 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
8319 { 9951 /* fcvt.d.l */, RISCV::FCVT_D_L_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
8320 { 9960 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
8321 { 9960 /* fcvt.d.lu */, RISCV::FCVT_D_LU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
8322 { 9970 /* fcvt.d.q */, RISCV::FCVT_D_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR64, MCK_FPR128, MCK_FRMArg }, },
8323 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR32, MCK_FRMArgLegacy }, },
8324 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
8325 { 9979 /* fcvt.d.s */, RISCV::FCVT_D_S_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
8326 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
8327 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8328 { 9988 /* fcvt.d.w */, RISCV::FCVT_D_W_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8329 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
8330 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8331 { 9997 /* fcvt.d.wu */, RISCV::FCVT_D_WU_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
8332 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR16, MCK_FPR64, MCK_FRMArg }, },
8333 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D_INX, Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8334 { 10007 /* fcvt.h.d */, RISCV::FCVT_H_D_IN32X, Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR16, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8335 { 10016 /* fcvt.h.l */, RISCV::FCVT_H_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8336 { 10016 /* fcvt.h.l */, RISCV::FCVT_H_L_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8337 { 10025 /* fcvt.h.lu */, RISCV::FCVT_H_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8338 { 10025 /* fcvt.h.lu */, RISCV::FCVT_H_LU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8339 { 10035 /* fcvt.h.s */, RISCV::FCVT_H_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
8340 { 10035 /* fcvt.h.s */, RISCV::FCVT_H_S_INX, Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR16, MCK_GPRAsFPR32, MCK_FRMArg }, },
8341 { 10044 /* fcvt.h.w */, RISCV::FCVT_H_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8342 { 10044 /* fcvt.h.w */, RISCV::FCVT_H_W_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8343 { 10053 /* fcvt.h.wu */, RISCV::FCVT_H_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
8344 { 10053 /* fcvt.h.wu */, RISCV::FCVT_H_WU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
8345 { 10063 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8346 { 10063 /* fcvt.l.d */, RISCV::FCVT_L_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8347 { 10072 /* fcvt.l.h */, RISCV::FCVT_L_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8348 { 10072 /* fcvt.l.h */, RISCV::FCVT_L_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8349 { 10081 /* fcvt.l.q */, RISCV::FCVT_L_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8350 { 10090 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8351 { 10090 /* fcvt.l.s */, RISCV::FCVT_L_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8352 { 10099 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8353 { 10099 /* fcvt.lu.d */, RISCV::FCVT_LU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8354 { 10109 /* fcvt.lu.h */, RISCV::FCVT_LU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8355 { 10109 /* fcvt.lu.h */, RISCV::FCVT_LU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8356 { 10119 /* fcvt.lu.q */, RISCV::FCVT_LU_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8357 { 10129 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8358 { 10129 /* fcvt.lu.s */, RISCV::FCVT_LU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8359 { 10139 /* fcvt.q.d */, RISCV::FCVT_Q_D, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR64, MCK_FRMArgLegacy }, },
8360 { 10148 /* fcvt.q.l */, RISCV::FCVT_Q_L, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8361 { 10157 /* fcvt.q.lu */, RISCV::FCVT_Q_LU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8362 { 10167 /* fcvt.q.s */, RISCV::FCVT_Q_S, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR32, MCK_FRMArgLegacy }, },
8363 { 10176 /* fcvt.q.w */, RISCV::FCVT_Q_W, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8364 { 10185 /* fcvt.q.wu */, RISCV::FCVT_Q_WU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_GPR, MCK_FRMArgLegacy }, },
8365 { 10195 /* fcvt.s.bf16 */, RISCV::FCVT_S_BF16, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
8366 { 10207 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64, MCK_FRMArg }, },
8367 { 10207 /* fcvt.s.d */, RISCV::FCVT_S_D_INX, Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8368 { 10207 /* fcvt.s.d */, RISCV::FCVT_S_D_IN32X, Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR32, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8369 { 10216 /* fcvt.s.h */, RISCV::FCVT_S_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
8370 { 10216 /* fcvt.s.h */, RISCV::FCVT_S_H_INX, Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR32, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
8371 { 10225 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8372 { 10225 /* fcvt.s.l */, RISCV::FCVT_S_L_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8373 { 10234 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8374 { 10234 /* fcvt.s.lu */, RISCV::FCVT_S_LU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8375 { 10244 /* fcvt.s.q */, RISCV::FCVT_S_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR32, MCK_FPR128, MCK_FRMArg }, },
8376 { 10253 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8377 { 10253 /* fcvt.s.w */, RISCV::FCVT_S_W_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8378 { 10262 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
8379 { 10262 /* fcvt.s.wu */, RISCV::FCVT_S_WU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
8380 { 10272 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8381 { 10272 /* fcvt.w.d */, RISCV::FCVT_W_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8382 { 10272 /* fcvt.w.d */, RISCV::FCVT_W_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8383 { 10281 /* fcvt.w.h */, RISCV::FCVT_W_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8384 { 10281 /* fcvt.w.h */, RISCV::FCVT_W_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8385 { 10290 /* fcvt.w.q */, RISCV::FCVT_W_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8386 { 10299 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8387 { 10299 /* fcvt.w.s */, RISCV::FCVT_W_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8388 { 10308 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
8389 { 10308 /* fcvt.wu.d */, RISCV::FCVT_WU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8390 { 10308 /* fcvt.wu.d */, RISCV::FCVT_WU_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8391 { 10318 /* fcvt.wu.h */, RISCV::FCVT_WU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
8392 { 10318 /* fcvt.wu.h */, RISCV::FCVT_WU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
8393 { 10328 /* fcvt.wu.q */, RISCV::FCVT_WU_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FRMArg }, },
8394 { 10338 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
8395 { 10338 /* fcvt.wu.s */, RISCV::FCVT_WU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
8396 { 10348 /* fcvtmod.w.d */, RISCV::FCVTMOD_W_D, Convert__Reg1_0__Reg1_1__RTZArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_RTZArg }, },
8397 { 10360 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8398 { 10360 /* fdiv.d */, RISCV::FDIV_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8399 { 10360 /* fdiv.d */, RISCV::FDIV_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8400 { 10367 /* fdiv.h */, RISCV::FDIV_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8401 { 10367 /* fdiv.h */, RISCV::FDIV_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8402 { 10374 /* fdiv.q */, RISCV::FDIV_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8403 { 10381 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8404 { 10381 /* fdiv.s */, RISCV::FDIV_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8405 { 10388 /* fence */, RISCV::FENCE, Convert__imm_95_15__imm_95_15, AMFBS_None, { }, },
8406 { 10388 /* fence */, RISCV::FENCE, Convert__FenceArg1_0__FenceArg1_1, AMFBS_None, { MCK_FenceArg, MCK_FenceArg }, },
8407 { 10394 /* fence.i */, RISCV::FENCE_I, Convert_NoOperands, AMFBS_None, { }, },
8408 { 10402 /* fence.tso */, RISCV::FENCE_TSO, Convert_NoOperands, AMFBS_None, { }, },
8409 { 10412 /* feq.d */, RISCV::FEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8410 { 10412 /* feq.d */, RISCV::FEQ_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8411 { 10412 /* feq.d */, RISCV::FEQ_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8412 { 10418 /* feq.h */, RISCV::FEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8413 { 10418 /* feq.h */, RISCV::FEQ_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8414 { 10424 /* feq.q */, RISCV::FEQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8415 { 10430 /* feq.s */, RISCV::FEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8416 { 10430 /* feq.s */, RISCV::FEQ_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8417 { 10436 /* fge.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8418 { 10436 /* fge.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8419 { 10436 /* fge.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8420 { 10442 /* fge.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8421 { 10442 /* fge.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8422 { 10448 /* fge.q */, RISCV::FLE_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8423 { 10454 /* fge.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8424 { 10454 /* fge.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8425 { 10460 /* fgeq.d */, RISCV::FLEQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8426 { 10467 /* fgeq.h */, RISCV::FLEQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8427 { 10474 /* fgeq.q */, RISCV::FLEQ_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8428 { 10481 /* fgeq.s */, RISCV::FLEQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8429 { 10488 /* fgt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8430 { 10488 /* fgt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8431 { 10488 /* fgt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8432 { 10494 /* fgt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8433 { 10494 /* fgt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8434 { 10500 /* fgt.q */, RISCV::FLT_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8435 { 10506 /* fgt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8436 { 10506 /* fgt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8437 { 10512 /* fgtq.d */, RISCV::FLTQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8438 { 10519 /* fgtq.h */, RISCV::FLTQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8439 { 10526 /* fgtq.q */, RISCV::FLTQ_Q, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8440 { 10533 /* fgtq.s */, RISCV::FLTQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8441 { 10540 /* fld */, RISCV::PseudoFLD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
8442 { 10540 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
8443 { 10540 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8444 { 10544 /* fle.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8445 { 10544 /* fle.d */, RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8446 { 10544 /* fle.d */, RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8447 { 10550 /* fle.h */, RISCV::FLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8448 { 10550 /* fle.h */, RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8449 { 10556 /* fle.q */, RISCV::FLE_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8450 { 10562 /* fle.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8451 { 10562 /* fle.s */, RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8452 { 10568 /* fleq.d */, RISCV::FLEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8453 { 10575 /* fleq.h */, RISCV::FLEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8454 { 10582 /* fleq.q */, RISCV::FLEQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8455 { 10589 /* fleq.s */, RISCV::FLEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8456 { 10596 /* flh */, RISCV::PseudoFLH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, },
8457 { 10596 /* flh */, RISCV::FLH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, },
8458 { 10596 /* flh */, RISCV::FLH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8459 { 10600 /* fli.d */, RISCV::FLI_D, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_LoadFPImm }, },
8460 { 10606 /* fli.h */, RISCV::FLI_H, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh, { MCK_FPR16, MCK_LoadFPImm }, },
8461 { 10612 /* fli.q */, RISCV::FLI_Q, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_LoadFPImm }, },
8462 { 10618 /* fli.s */, RISCV::FLI_S, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_LoadFPImm }, },
8463 { 10624 /* flq */, RISCV::PseudoFLQ, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_BareSymbol, MCK_GPR }, },
8464 { 10624 /* flq */, RISCV::FLQ, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtQ, { MCK_FPR128, MCK__40_, MCK_GPR, MCK__41_ }, },
8465 { 10624 /* flq */, RISCV::FLQ, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8466 { 10628 /* flt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8467 { 10628 /* flt.d */, RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8468 { 10628 /* flt.d */, RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8469 { 10634 /* flt.h */, RISCV::FLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8470 { 10634 /* flt.h */, RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8471 { 10640 /* flt.q */, RISCV::FLT_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8472 { 10646 /* flt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8473 { 10646 /* flt.s */, RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8474 { 10652 /* fltq.d */, RISCV::FLTQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
8475 { 10659 /* fltq.h */, RISCV::FLTQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
8476 { 10666 /* fltq.q */, RISCV::FLTQ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_GPR, MCK_FPR128, MCK_FPR128 }, },
8477 { 10673 /* fltq.s */, RISCV::FLTQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
8478 { 10680 /* flw */, RISCV::PseudoFLW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
8479 { 10680 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
8480 { 10680 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8481 { 10684 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8482 { 10684 /* fmadd.d */, RISCV::FMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8483 { 10684 /* fmadd.d */, RISCV::FMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8484 { 10692 /* fmadd.h */, RISCV::FMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8485 { 10692 /* fmadd.h */, RISCV::FMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8486 { 10700 /* fmadd.q */, RISCV::FMADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8487 { 10708 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8488 { 10708 /* fmadd.s */, RISCV::FMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8489 { 10716 /* fmax.d */, RISCV::FMAX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8490 { 10716 /* fmax.d */, RISCV::FMAX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8491 { 10716 /* fmax.d */, RISCV::FMAX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8492 { 10723 /* fmax.h */, RISCV::FMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8493 { 10723 /* fmax.h */, RISCV::FMAX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8494 { 10730 /* fmax.q */, RISCV::FMAX_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8495 { 10737 /* fmax.s */, RISCV::FMAX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8496 { 10737 /* fmax.s */, RISCV::FMAX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8497 { 10744 /* fmaxm.d */, RISCV::FMAXM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8498 { 10752 /* fmaxm.h */, RISCV::FMAXM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8499 { 10760 /* fmaxm.q */, RISCV::FMAXM_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8500 { 10768 /* fmaxm.s */, RISCV::FMAXM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8501 { 10776 /* fmin.d */, RISCV::FMIN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8502 { 10776 /* fmin.d */, RISCV::FMIN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8503 { 10776 /* fmin.d */, RISCV::FMIN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8504 { 10783 /* fmin.h */, RISCV::FMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8505 { 10783 /* fmin.h */, RISCV::FMIN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8506 { 10790 /* fmin.q */, RISCV::FMIN_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8507 { 10797 /* fmin.s */, RISCV::FMIN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8508 { 10797 /* fmin.s */, RISCV::FMIN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8509 { 10804 /* fminm.d */, RISCV::FMINM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8510 { 10812 /* fminm.h */, RISCV::FMINM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8511 { 10820 /* fminm.q */, RISCV::FMINM_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8512 { 10828 /* fminm.s */, RISCV::FMINM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8513 { 10836 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8514 { 10836 /* fmsub.d */, RISCV::FMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8515 { 10836 /* fmsub.d */, RISCV::FMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8516 { 10844 /* fmsub.h */, RISCV::FMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8517 { 10844 /* fmsub.h */, RISCV::FMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8518 { 10852 /* fmsub.q */, RISCV::FMSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8519 { 10860 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8520 { 10860 /* fmsub.s */, RISCV::FMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8521 { 10868 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8522 { 10868 /* fmul.d */, RISCV::FMUL_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8523 { 10868 /* fmul.d */, RISCV::FMUL_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8524 { 10875 /* fmul.h */, RISCV::FMUL_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8525 { 10875 /* fmul.h */, RISCV::FMUL_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8526 { 10882 /* fmul.q */, RISCV::FMUL_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8527 { 10889 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8528 { 10889 /* fmul.s */, RISCV::FMUL_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8529 { 10896 /* fmv.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8530 { 10896 /* fmv.d */, RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8531 { 10896 /* fmv.d */, RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8532 { 10902 /* fmv.d.x */, RISCV::FMV_D_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, },
8533 { 10910 /* fmv.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8534 { 10910 /* fmv.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8535 { 10916 /* fmv.h.x */, RISCV::FMV_H_X, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_GPR }, },
8536 { 10924 /* fmv.q */, RISCV::FSGNJ_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8537 { 10930 /* fmv.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8538 { 10930 /* fmv.s */, RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8539 { 10936 /* fmv.w.x */, RISCV::FMV_W_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, },
8540 { 10944 /* fmv.x.d */, RISCV::FMV_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, },
8541 { 10952 /* fmv.x.h */, RISCV::FMV_X_H, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_GPR, MCK_FPR16 }, },
8542 { 10960 /* fmv.x.w */, RISCV::FMV_X_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
8543 { 10968 /* fmvh.x.d */, RISCV::FMVH_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_GPR, MCK_FPR64 }, },
8544 { 10977 /* fmvh.x.q */, RISCV::FMVH_X_Q, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64, { MCK_GPR, MCK_FPR128 }, },
8545 { 10986 /* fmvp.d.x */, RISCV::FMVP_D_X, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
8546 { 10995 /* fmvp.q.x */, RISCV::FMVP_Q_X, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtQ_IsRV64, { MCK_FPR128, MCK_GPR, MCK_GPR }, },
8547 { 11004 /* fneg.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
8548 { 11004 /* fneg.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8549 { 11004 /* fneg.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8550 { 11011 /* fneg.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
8551 { 11011 /* fneg.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8552 { 11018 /* fneg.q */, RISCV::FSGNJN_Q, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128 }, },
8553 { 11025 /* fneg.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
8554 { 11025 /* fneg.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8555 { 11032 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8556 { 11032 /* fnmadd.d */, RISCV::FNMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8557 { 11032 /* fnmadd.d */, RISCV::FNMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8558 { 11041 /* fnmadd.h */, RISCV::FNMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8559 { 11041 /* fnmadd.h */, RISCV::FNMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8560 { 11050 /* fnmadd.q */, RISCV::FNMADD_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8561 { 11059 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8562 { 11059 /* fnmadd.s */, RISCV::FNMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8563 { 11068 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8564 { 11068 /* fnmsub.d */, RISCV::FNMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8565 { 11068 /* fnmsub.d */, RISCV::FNMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8566 { 11077 /* fnmsub.h */, RISCV::FNMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8567 { 11077 /* fnmsub.h */, RISCV::FNMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8568 { 11086 /* fnmsub.q */, RISCV::FNMSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8569 { 11095 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8570 { 11095 /* fnmsub.s */, RISCV::FNMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8571 { 11104 /* frcsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8572 { 11110 /* frflags */, RISCV::CSRRS, Convert__Reg1_0__imm_95_1__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8573 { 11118 /* fround.d */, RISCV::FROUND_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8574 { 11127 /* fround.h */, RISCV::FROUND_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8575 { 11136 /* fround.q */, RISCV::FROUND_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8576 { 11145 /* fround.s */, RISCV::FROUND_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8577 { 11154 /* froundnx.d */, RISCV::FROUNDNX_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8578 { 11165 /* froundnx.h */, RISCV::FROUNDNX_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8579 { 11176 /* froundnx.q */, RISCV::FROUNDNX_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8580 { 11187 /* froundnx.s */, RISCV::FROUNDNX_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8581 { 11198 /* frrm */, RISCV::CSRRS, Convert__Reg1_0__imm_95_2__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8582 { 11203 /* fscsr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8583 { 11203 /* fscsr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
8584 { 11209 /* fsd */, RISCV::PseudoFSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
8585 { 11209 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
8586 { 11209 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8587 { 11213 /* fsflags */, RISCV::CSRRW, Convert__regX0__imm_95_1__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8588 { 11213 /* fsflags */, RISCV::CSRRW, Convert__Reg1_0__imm_95_1__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
8589 { 11221 /* fsflagsi */, RISCV::CSRRWI, Convert__regX0__imm_95_1__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
8590 { 11221 /* fsflagsi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_1__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
8591 { 11230 /* fsgnj.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8592 { 11230 /* fsgnj.d */, RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8593 { 11230 /* fsgnj.d */, RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8594 { 11238 /* fsgnj.h */, RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8595 { 11238 /* fsgnj.h */, RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8596 { 11246 /* fsgnj.q */, RISCV::FSGNJ_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8597 { 11254 /* fsgnj.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8598 { 11254 /* fsgnj.s */, RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8599 { 11262 /* fsgnjn.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8600 { 11262 /* fsgnjn.d */, RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8601 { 11262 /* fsgnjn.d */, RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8602 { 11271 /* fsgnjn.h */, RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8603 { 11271 /* fsgnjn.h */, RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8604 { 11280 /* fsgnjn.q */, RISCV::FSGNJN_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8605 { 11289 /* fsgnjn.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8606 { 11289 /* fsgnjn.s */, RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8607 { 11298 /* fsgnjx.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
8608 { 11298 /* fsgnjx.d */, RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
8609 { 11298 /* fsgnjx.d */, RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
8610 { 11307 /* fsgnjx.h */, RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
8611 { 11307 /* fsgnjx.h */, RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
8612 { 11316 /* fsgnjx.q */, RISCV::FSGNJX_Q, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128 }, },
8613 { 11325 /* fsgnjx.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
8614 { 11325 /* fsgnjx.s */, RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
8615 { 11334 /* fsh */, RISCV::PseudoFSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, },
8616 { 11334 /* fsh */, RISCV::FSH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, },
8617 { 11334 /* fsh */, RISCV::FSH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8618 { 11338 /* fsq */, RISCV::PseudoFSQ, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_BareSymbol, MCK_GPR }, },
8619 { 11338 /* fsq */, RISCV::FSQ, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtQ, { MCK_FPR128, MCK__40_, MCK_GPR, MCK__41_ }, },
8620 { 11338 /* fsq */, RISCV::FSQ, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8621 { 11342 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8622 { 11342 /* fsqrt.d */, RISCV::FSQRT_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8623 { 11342 /* fsqrt.d */, RISCV::FSQRT_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8624 { 11350 /* fsqrt.h */, RISCV::FSQRT_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8625 { 11350 /* fsqrt.h */, RISCV::FSQRT_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8626 { 11358 /* fsqrt.q */, RISCV::FSQRT_Q, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8627 { 11366 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8628 { 11366 /* fsqrt.s */, RISCV::FSQRT_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8629 { 11374 /* fsrm */, RISCV::CSRRW, Convert__regX0__imm_95_2__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
8630 { 11374 /* fsrm */, RISCV::CSRRW, Convert__Reg1_0__imm_95_2__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
8631 { 11379 /* fsrmi */, RISCV::CSRRWI, Convert__regX0__imm_95_2__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
8632 { 11379 /* fsrmi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_2__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
8633 { 11385 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
8634 { 11385 /* fsub.d */, RISCV::FSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
8635 { 11385 /* fsub.d */, RISCV::FSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
8636 { 11392 /* fsub.h */, RISCV::FSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
8637 { 11392 /* fsub.h */, RISCV::FSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
8638 { 11399 /* fsub.q */, RISCV::FSUB_Q, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtQ, { MCK_FPR128, MCK_FPR128, MCK_FPR128, MCK_FRMArg }, },
8639 { 11406 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
8640 { 11406 /* fsub.s */, RISCV::FSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
8641 { 11413 /* fsw */, RISCV::PseudoFSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
8642 { 11413 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
8643 { 11413 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8644 { 11417 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__regX0__regX0, AMFBS_None, { }, },
8645 { 11417 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
8646 { 11417 /* hfence.gvma */, RISCV::HFENCE_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
8647 { 11429 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__regX0__regX0, AMFBS_None, { }, },
8648 { 11429 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
8649 { 11429 /* hfence.vvma */, RISCV::HFENCE_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
8650 { 11441 /* hinval.gvma */, RISCV::HINVAL_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
8651 { 11453 /* hinval.vvma */, RISCV::HINVAL_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
8652 { 11465 /* hlv.b */, RISCV::HLV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8653 { 11471 /* hlv.bu */, RISCV::HLV_BU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8654 { 11478 /* hlv.d */, RISCV::HLV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8655 { 11484 /* hlv.h */, RISCV::HLV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8656 { 11490 /* hlv.hu */, RISCV::HLV_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8657 { 11497 /* hlv.w */, RISCV::HLV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8658 { 11503 /* hlv.wu */, RISCV::HLV_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8659 { 11510 /* hlvx.hu */, RISCV::HLVX_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8660 { 11518 /* hlvx.wu */, RISCV::HLVX_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8661 { 11526 /* hsv.b */, RISCV::HSV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8662 { 11532 /* hsv.d */, RISCV::HSV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8663 { 11538 /* hsv.h */, RISCV::HSV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8664 { 11544 /* hsv.w */, RISCV::HSV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8665 { 11550 /* j */, RISCV::JAL, Convert__regX0__BareSImm21Lsb01_0, AMFBS_None, { MCK_BareSImm21Lsb0 }, },
8666 { 11552 /* jal */, RISCV::JAL, Convert__regX1__BareSImm21Lsb01_0, AMFBS_None, { MCK_BareSImm21Lsb0 }, },
8667 { 11552 /* jal */, RISCV::JAL, Convert__Reg1_0__BareSImm21Lsb01_1, AMFBS_None, { MCK_GPR, MCK_BareSImm21Lsb0 }, },
8668 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
8669 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8670 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
8671 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_1__imm_95_0, AMFBS_None, { MCK__40_, MCK_GPR, MCK__41_ }, },
8672 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
8673 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8674 { 11556 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_2__SImm12LO1_0, AMFBS_None, { MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8675 { 11556 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8676 { 11556 /* jalr */, RISCV::PseudoTLSDESCCall, Convert__Reg1_0__Reg1_3__SImm12LO1_1__TLSDESCCallSymbol1_5, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_, MCK_TLSDESCCallSymbol }, },
8677 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
8678 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
8679 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_1__imm_95_0, AMFBS_None, { MCK__40_, MCK_GPR, MCK__41_ }, },
8680 { 11561 /* jr */, RISCV::JALR, Convert__regX0__Reg1_2__SImm12LO1_0, AMFBS_None, { MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8681 { 11564 /* jump */, RISCV::PseudoJump, Convert__Reg1_1__PseudoJumpSymbol1_0, AMFBS_None, { MCK_PseudoJumpSymbol, MCK_GPR }, },
8682 { 11569 /* la */, RISCV::PseudoLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8683 { 11569 /* la */, RISCV::PseudoLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
8684 { 11572 /* la.tls.gd */, RISCV::PseudoLA_TLS_GD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8685 { 11582 /* la.tls.ie */, RISCV::PseudoLA_TLS_IE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8686 { 11592 /* lb */, RISCV::PseudoLB, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8687 { 11592 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8688 { 11592 /* lb */, RISCV::PseudoQCAccessLB, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8689 { 11592 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8690 { 11592 /* lb */, RISCV::PseudoQCAccessLB, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8691 { 11595 /* lb.aq */, RISCV::LB_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8692 { 11601 /* lb.aqrl */, RISCV::LB_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8693 { 11609 /* lbu */, RISCV::PseudoLBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8694 { 11609 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8695 { 11609 /* lbu */, RISCV::PseudoQCAccessLB, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8696 { 11609 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8697 { 11609 /* lbu */, RISCV::PseudoQCAccessLBU, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8698 { 11613 /* ld */, RISCV::PseudoLD, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
8699 { 11613 /* ld */, RISCV::PseudoLD_RV32, Convert__GPRPairRV321_0__BareSymbol1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_BareSymbol }, },
8700 { 11613 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8701 { 11613 /* ld */, RISCV::LD_RV32, Convert__GPRPairRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK__40_, MCK_GPR, MCK__41_ }, },
8702 { 11613 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8703 { 11613 /* ld */, RISCV::LD_RV32, Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8704 { 11616 /* ld.aq */, RISCV::LD_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8705 { 11622 /* ld.aqrl */, RISCV::LD_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8706 { 11630 /* lga */, RISCV::PseudoLGA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8707 { 11634 /* lh */, RISCV::PseudoLH, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8708 { 11634 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8709 { 11634 /* lh */, RISCV::PseudoQCAccessLH, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8710 { 11634 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8711 { 11634 /* lh */, RISCV::PseudoQCAccessLH, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8712 { 11637 /* lh.aq */, RISCV::LH_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8713 { 11643 /* lh.aqrl */, RISCV::LH_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8714 { 11651 /* lhu */, RISCV::PseudoLHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8715 { 11651 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8716 { 11651 /* lhu */, RISCV::PseudoQCAccessLHU, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8717 { 11651 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8718 { 11651 /* lhu */, RISCV::PseudoQCAccessLHU, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8719 { 11655 /* li */, RISCV::ADDI, Convert__Reg1_0__regX0__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO }, },
8720 { 11655 /* li */, RISCV::PseudoLI, Convert__Reg1_0__ImmXLenLI1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI }, },
8721 { 11658 /* lla */, RISCV::PseudoLLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8722 { 11658 /* lla */, RISCV::PseudoLLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
8723 { 11662 /* lpad */, RISCV::AUIPC, Convert__regX0__UImm201_0, AMFBS_None, { MCK_UImm20 }, },
8724 { 11667 /* lr.d */, RISCV::LR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8725 { 11672 /* lr.d.aq */, RISCV::LR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8726 { 11680 /* lr.d.aqrl */, RISCV::LR_D_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8727 { 11690 /* lr.d.rl */, RISCV::LR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8728 { 11698 /* lr.w */, RISCV::LR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8729 { 11703 /* lr.w.aq */, RISCV::LR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8730 { 11711 /* lr.w.aqrl */, RISCV::LR_W_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8731 { 11721 /* lr.w.rl */, RISCV::LR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8732 { 11729 /* lui */, RISCV::LUI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_None, { MCK_GPR, MCK_UImm20LUI }, },
8733 { 11733 /* lw */, RISCV::PseudoLW, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
8734 { 11733 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8735 { 11733 /* lw */, RISCV::PseudoQCAccessLW, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8736 { 11733 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8737 { 11733 /* lw */, RISCV::PseudoQCAccessLW, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
8738 { 11736 /* lw.aq */, RISCV::LW_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8739 { 11742 /* lw.aqrl */, RISCV::LW_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
8740 { 11750 /* lwu */, RISCV::PseudoLWU, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
8741 { 11750 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
8742 { 11750 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
8743 { 11754 /* macc.h00 */, RISCV::MACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8744 { 11763 /* macc.h01 */, RISCV::MACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8745 { 11772 /* macc.h11 */, RISCV::MACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8746 { 11781 /* macc.w00 */, RISCV::MACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8747 { 11790 /* macc.w01 */, RISCV::MACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8748 { 11799 /* macc.w11 */, RISCV::MACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8749 { 11808 /* maccsu.h00 */, RISCV::MACCSU_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8750 { 11819 /* maccsu.h11 */, RISCV::MACCSU_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8751 { 11830 /* maccsu.w00 */, RISCV::MACCSU_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8752 { 11841 /* maccsu.w11 */, RISCV::MACCSU_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8753 { 11852 /* maccu.h00 */, RISCV::MACCU_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8754 { 11862 /* maccu.h01 */, RISCV::MACCU_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8755 { 11872 /* maccu.h11 */, RISCV::MACCU_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8756 { 11882 /* maccu.w00 */, RISCV::MACCU_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8757 { 11892 /* maccu.w01 */, RISCV::MACCU_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8758 { 11902 /* maccu.w11 */, RISCV::MACCU_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8759 { 11912 /* max */, RISCV::MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8760 { 11916 /* maxu */, RISCV::MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8761 { 11921 /* merge */, RISCV::MERGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8762 { 11927 /* mhacc */, RISCV::MHACC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8763 { 11933 /* mhacc.h0 */, RISCV::MHACC_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8764 { 11942 /* mhacc.h1 */, RISCV::MHACC_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8765 { 11951 /* mhaccsu */, RISCV::MHACCSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8766 { 11959 /* mhaccsu.h0 */, RISCV::MHACCSU_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8767 { 11970 /* mhaccsu.h1 */, RISCV::MHACCSU_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8768 { 11981 /* mhaccu */, RISCV::MHACCU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8769 { 11988 /* mhracc */, RISCV::MHRACC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8770 { 11995 /* mhraccsu */, RISCV::MHRACCSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8771 { 12004 /* mhraccu */, RISCV::MHRACCU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8772 { 12012 /* min */, RISCV::MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8773 { 12016 /* minu */, RISCV::MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8774 { 12021 /* mips.ccmov */, RISCV::MIPS_CCMOV, Convert__Reg1_0__Reg1_2__Reg1_1__Reg1_3, AMFBS_HasVendorXMIPSCMov, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8775 { 12032 /* mips.ehb */, RISCV::MIPS_EHB, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
8776 { 12041 /* mips.ihb */, RISCV::MIPS_IHB, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
8777 { 12050 /* mips.ldp */, RISCV::MIPS_LDP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb000, MCK__40_, MCK_GPR, MCK__41_ }, },
8778 { 12059 /* mips.lwp */, RISCV::MIPS_LWP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
8779 { 12068 /* mips.pause */, RISCV::MIPS_PAUSE, Convert_NoOperands, AMFBS_HasVendorXMIPSEXECTL, { }, },
8780 { 12079 /* mips.pref */, RISCV::MIPS_PREF, Convert__Reg1_3__UImm91_1__UImm51_0, AMFBS_HasVendorXMIPSCBOP, { MCK_UImm5, MCK_UImm9, MCK__40_, MCK_GPR, MCK__41_ }, },
8781 { 12089 /* mips.sdp */, RISCV::MIPS_SDP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb0001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb000, MCK__40_, MCK_GPR, MCK__41_ }, },
8782 { 12098 /* mips.swp */, RISCV::MIPS_SWP, Convert__Reg1_0__Reg1_1__Reg1_4__UImm7Lsb001_2, AMFBS_HasVendorXMIPSLSP, { MCK_GPR, MCK_GPR, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
8783 { 12107 /* mnret */, RISCV::MNRET, Convert_NoOperands, AMFBS_HasStdExtSmrnmi, { }, },
8784 { 12113 /* mop.r.0 */, RISCV::MOP_R_0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8785 { 12121 /* mop.r.1 */, RISCV::MOP_R_1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8786 { 12129 /* mop.r.10 */, RISCV::MOP_R_10, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8787 { 12138 /* mop.r.11 */, RISCV::MOP_R_11, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8788 { 12147 /* mop.r.12 */, RISCV::MOP_R_12, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8789 { 12156 /* mop.r.13 */, RISCV::MOP_R_13, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8790 { 12165 /* mop.r.14 */, RISCV::MOP_R_14, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8791 { 12174 /* mop.r.15 */, RISCV::MOP_R_15, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8792 { 12183 /* mop.r.16 */, RISCV::MOP_R_16, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8793 { 12192 /* mop.r.17 */, RISCV::MOP_R_17, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8794 { 12201 /* mop.r.18 */, RISCV::MOP_R_18, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8795 { 12210 /* mop.r.19 */, RISCV::MOP_R_19, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8796 { 12219 /* mop.r.2 */, RISCV::MOP_R_2, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8797 { 12227 /* mop.r.20 */, RISCV::MOP_R_20, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8798 { 12236 /* mop.r.21 */, RISCV::MOP_R_21, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8799 { 12245 /* mop.r.22 */, RISCV::MOP_R_22, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8800 { 12254 /* mop.r.23 */, RISCV::MOP_R_23, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8801 { 12263 /* mop.r.24 */, RISCV::MOP_R_24, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8802 { 12272 /* mop.r.25 */, RISCV::MOP_R_25, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8803 { 12281 /* mop.r.26 */, RISCV::MOP_R_26, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8804 { 12290 /* mop.r.27 */, RISCV::MOP_R_27, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8805 { 12299 /* mop.r.28 */, RISCV::MOP_R_28, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8806 { 12308 /* mop.r.29 */, RISCV::MOP_R_29, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8807 { 12317 /* mop.r.3 */, RISCV::MOP_R_3, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8808 { 12325 /* mop.r.30 */, RISCV::MOP_R_30, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8809 { 12334 /* mop.r.31 */, RISCV::MOP_R_31, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8810 { 12343 /* mop.r.4 */, RISCV::MOP_R_4, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8811 { 12351 /* mop.r.5 */, RISCV::MOP_R_5, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8812 { 12359 /* mop.r.6 */, RISCV::MOP_R_6, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8813 { 12367 /* mop.r.7 */, RISCV::MOP_R_7, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8814 { 12375 /* mop.r.8 */, RISCV::MOP_R_8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8815 { 12383 /* mop.r.9 */, RISCV::MOP_R_9, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
8816 { 12391 /* mop.rr.0 */, RISCV::MOP_RR_0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8817 { 12400 /* mop.rr.1 */, RISCV::MOP_RR_1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8818 { 12409 /* mop.rr.2 */, RISCV::MOP_RR_2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8819 { 12418 /* mop.rr.3 */, RISCV::MOP_RR_3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8820 { 12427 /* mop.rr.4 */, RISCV::MOP_RR_4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8821 { 12436 /* mop.rr.5 */, RISCV::MOP_RR_5, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8822 { 12445 /* mop.rr.6 */, RISCV::MOP_RR_6, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8823 { 12454 /* mop.rr.7 */, RISCV::MOP_RR_7, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8824 { 12463 /* mqacc.h00 */, RISCV::MQACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8825 { 12473 /* mqacc.h01 */, RISCV::MQACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8826 { 12483 /* mqacc.h11 */, RISCV::MQACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8827 { 12493 /* mqacc.w00 */, RISCV::MQACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8828 { 12503 /* mqacc.w01 */, RISCV::MQACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8829 { 12513 /* mqacc.w11 */, RISCV::MQACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8830 { 12523 /* mqracc.h00 */, RISCV::MQRACC_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8831 { 12534 /* mqracc.h01 */, RISCV::MQRACC_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8832 { 12545 /* mqracc.h11 */, RISCV::MQRACC_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8833 { 12556 /* mqracc.w00 */, RISCV::MQRACC_W00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8834 { 12567 /* mqracc.w01 */, RISCV::MQRACC_W01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8835 { 12578 /* mqracc.w11 */, RISCV::MQRACC_W11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8836 { 12589 /* mqrwacc */, RISCV::MQRWACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8837 { 12597 /* mqwacc */, RISCV::MQWACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
8838 { 12604 /* mret */, RISCV::MRET, Convert_NoOperands, AMFBS_None, { }, },
8839 { 12609 /* mseq */, RISCV::MSEQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8840 { 12614 /* mseqz */, RISCV::MSEQ, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
8841 { 12620 /* msgt */, RISCV::MSLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8842 { 12625 /* msgtu */, RISCV::MSLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8843 { 12631 /* msgtz */, RISCV::MSLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
8844 { 12637 /* mslt */, RISCV::MSLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8845 { 12642 /* msltu */, RISCV::MSLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8846 { 12648 /* msltz */, RISCV::MSLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
8847 { 12654 /* msnez */, RISCV::MSLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
8848 { 12660 /* mul */, RISCV::MUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8849 { 12664 /* mul.h00 */, RISCV::MUL_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8850 { 12672 /* mul.h01 */, RISCV::MUL_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8851 { 12680 /* mul.h11 */, RISCV::MUL_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8852 { 12688 /* mul.w00 */, RISCV::MUL_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8853 { 12696 /* mul.w01 */, RISCV::MUL_W01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8854 { 12704 /* mul.w11 */, RISCV::MUL_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8855 { 12712 /* mulh */, RISCV::MULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8856 { 12717 /* mulh.h0 */, RISCV::MULH_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8857 { 12725 /* mulh.h1 */, RISCV::MULH_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8858 { 12733 /* mulhr */, RISCV::MULHR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8859 { 12739 /* mulhrsu */, RISCV::MULHRSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8860 { 12747 /* mulhru */, RISCV::MULHRU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8861 { 12754 /* mulhsu */, RISCV::MULHSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8862 { 12761 /* mulhsu.h0 */, RISCV::MULHSU_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8863 { 12771 /* mulhsu.h1 */, RISCV::MULHSU_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8864 { 12781 /* mulhu */, RISCV::MULHU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8865 { 12787 /* mulq */, RISCV::MULQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8866 { 12792 /* mulqr */, RISCV::MULQR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8867 { 12798 /* mulsu.h00 */, RISCV::MULSU_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8868 { 12808 /* mulsu.h11 */, RISCV::MULSU_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8869 { 12818 /* mulsu.w00 */, RISCV::MULSU_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8870 { 12828 /* mulsu.w11 */, RISCV::MULSU_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8871 { 12838 /* mulu.h00 */, RISCV::MULU_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8872 { 12847 /* mulu.h01 */, RISCV::MULU_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8873 { 12856 /* mulu.h11 */, RISCV::MULU_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8874 { 12865 /* mulu.w00 */, RISCV::MULU_W00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8875 { 12874 /* mulu.w01 */, RISCV::MULU_W01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8876 { 12883 /* mulu.w11 */, RISCV::MULU_W11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8877 { 12892 /* mulw */, RISCV::MULW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8878 { 12897 /* mv */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8879 { 12900 /* mvd */, RISCV::PADD_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8880 { 12904 /* mvm */, RISCV::MVM, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8881 { 12908 /* mvmn */, RISCV::MVMN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8882 { 12913 /* nclip */, RISCV::NCLIP, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8883 { 12919 /* nclipi */, RISCV::NCLIPI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8884 { 12926 /* nclipiu */, RISCV::NCLIPIU, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8885 { 12934 /* nclipr */, RISCV::NCLIPR, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8886 { 12941 /* nclipri */, RISCV::NCLIPRI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8887 { 12949 /* nclipriu */, RISCV::NCLIPRIU, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8888 { 12958 /* nclipru */, RISCV::NCLIPRU, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8889 { 12966 /* nclipu */, RISCV::NCLIPU, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8890 { 12973 /* nds.addigp */, RISCV::NDS_ADDIGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8891 { 12984 /* nds.bbc */, RISCV::NDS_BBC, Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImmLog2XLen, MCK_BareSImm11Lsb0 }, },
8892 { 12992 /* nds.bbs */, RISCV::NDS_BBS, Convert__Reg1_0__UImmLog2XLen1_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImmLog2XLen, MCK_BareSImm11Lsb0 }, },
8893 { 13000 /* nds.beqc */, RISCV::NDS_BEQC, Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImm7, MCK_BareSImm11Lsb0 }, },
8894 { 13009 /* nds.bfos */, RISCV::NDS_BFOS, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
8895 { 13018 /* nds.bfoz */, RISCV::NDS_BFOZ, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
8896 { 13027 /* nds.bnec */, RISCV::NDS_BNEC, Convert__Reg1_0__UImm71_1__BareSImm11Lsb01_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_UImm7, MCK_BareSImm11Lsb0 }, },
8897 { 13036 /* nds.fcvt.bf16.s */, RISCV::NDS_FCVT_BF16_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesBFHCvt, { MCK_FPR16, MCK_FPR32 }, },
8898 { 13052 /* nds.fcvt.s.bf16 */, RISCV::NDS_FCVT_S_BF16, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesBFHCvt, { MCK_FPR32, MCK_FPR16 }, },
8899 { 13068 /* nds.ffb */, RISCV::NDS_FFB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8900 { 13076 /* nds.ffmism */, RISCV::NDS_FFMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8901 { 13087 /* nds.ffzmism */, RISCV::NDS_FFZMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8902 { 13099 /* nds.flmism */, RISCV::NDS_FLMISM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8903 { 13110 /* nds.lbgp */, RISCV::NDS_LBGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8904 { 13119 /* nds.lbugp */, RISCV::NDS_LBUGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8905 { 13129 /* nds.ldgp */, RISCV::NDS_LDGP, Convert__Reg1_0__SImm20Lsb0001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm20Lsb000 }, },
8906 { 13138 /* nds.lea.b.ze */, RISCV::NDS_LEA_B_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8907 { 13151 /* nds.lea.d */, RISCV::NDS_LEA_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8908 { 13161 /* nds.lea.d.ze */, RISCV::NDS_LEA_D_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8909 { 13174 /* nds.lea.h */, RISCV::NDS_LEA_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8910 { 13184 /* nds.lea.h.ze */, RISCV::NDS_LEA_H_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8911 { 13197 /* nds.lea.w */, RISCV::NDS_LEA_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8912 { 13207 /* nds.lea.w.ze */, RISCV::NDS_LEA_W_ZE, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8913 { 13220 /* nds.lhgp */, RISCV::NDS_LHGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
8914 { 13229 /* nds.lhugp */, RISCV::NDS_LHUGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
8915 { 13239 /* nds.lwgp */, RISCV::NDS_LWGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm19Lsb00 }, },
8916 { 13248 /* nds.lwugp */, RISCV::NDS_LWUGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm19Lsb00 }, },
8917 { 13258 /* nds.sbgp */, RISCV::NDS_SBGP, Convert__Reg1_0__SImm181_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18 }, },
8918 { 13267 /* nds.sdgp */, RISCV::NDS_SDGP, Convert__Reg1_0__SImm20Lsb0001_1, AMFBS_HasVendorXAndesPerf_IsRV64, { MCK_GPR, MCK_SImm20Lsb000 }, },
8919 { 13276 /* nds.shgp */, RISCV::NDS_SHGP, Convert__Reg1_0__SImm18Lsb01_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm18Lsb0 }, },
8920 { 13285 /* nds.swgp */, RISCV::NDS_SWGP, Convert__Reg1_0__SImm19Lsb001_1, AMFBS_HasVendorXAndesPerf, { MCK_GPR, MCK_SImm19Lsb00 }, },
8921 { 13294 /* nds.vd4dots.vv */, RISCV::NDS_VD4DOTS_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8922 { 13309 /* nds.vd4dotsu.vv */, RISCV::NDS_VD4DOTSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8923 { 13325 /* nds.vd4dotu.vv */, RISCV::NDS_VD4DOTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVDot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8924 { 13340 /* nds.vfncvt.bf16.s */, RISCV::NDS_VFNCVT_BF16_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesVBFHCvt, { MCK_VR, MCK_VR }, },
8925 { 13358 /* nds.vfpmadb.vf */, RISCV::NDS_VFPMADB_VF, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVPackFPH, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8926 { 13373 /* nds.vfpmadt.vf */, RISCV::NDS_VFPMADT_VF, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXAndesVPackFPH, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8927 { 13388 /* nds.vfwcvt.f.b.v */, RISCV::NDS_VFWCVT_F_B, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8928 { 13405 /* nds.vfwcvt.f.bu.v */, RISCV::NDS_VFWCVT_F_BU, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8929 { 13423 /* nds.vfwcvt.f.n.v */, RISCV::NDS_VFWCVT_F_N, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8930 { 13440 /* nds.vfwcvt.f.nu.v */, RISCV::NDS_VFWCVT_F_NU, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
8931 { 13458 /* nds.vfwcvt.s.bf16 */, RISCV::NDS_VFWCVT_S_BF16, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXAndesVBFHCvt, { MCK_VR, MCK_VR }, },
8932 { 13476 /* nds.vle4.v */, RISCV::NDS_VLE4_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXAndesVSIntH, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
8933 { 13487 /* nds.vln8.v */, RISCV::NDS_VLN8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntLoad, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
8934 { 13498 /* nds.vlnu8.v */, RISCV::NDS_VLNU8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXAndesVSIntLoad, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
8935 { 13510 /* neg */, RISCV::SUB, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8936 { 13514 /* negd */, RISCV::SUBD, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8937 { 13519 /* negw */, RISCV::SUBW, Convert__Reg1_0__regX0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
8938 { 13524 /* nop */, RISCV::ADDI, Convert__regX0__regX0__imm_95_0, AMFBS_None, { }, },
8939 { 13528 /* not */, RISCV::XORI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
8940 { 13532 /* nsra */, RISCV::NSRA, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8941 { 13537 /* nsrai */, RISCV::NSRAI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8942 { 13543 /* nsrar */, RISCV::NSRAR, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8943 { 13549 /* nsrari */, RISCV::NSRARI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8944 { 13556 /* nsrl */, RISCV::NSRL, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
8945 { 13561 /* nsrli */, RISCV::NSRLI, Convert__Reg1_0__GPRPairRV321_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm6 }, },
8946 { 13567 /* ntl.all */, RISCV::ADD, Convert__regX0__regX0__regX5, AMFBS_None, { }, },
8947 { 13575 /* ntl.p1 */, RISCV::ADD, Convert__regX0__regX0__regX2, AMFBS_None, { }, },
8948 { 13582 /* ntl.pall */, RISCV::ADD, Convert__regX0__regX0__regX3, AMFBS_None, { }, },
8949 { 13591 /* ntl.s1 */, RISCV::ADD, Convert__regX0__regX0__regX4, AMFBS_None, { }, },
8950 { 13598 /* or */, RISCV::OR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8951 { 13598 /* or */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
8952 { 13601 /* orc.b */, RISCV::ORC_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
8953 { 13607 /* ori */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
8954 { 13611 /* orn */, RISCV::ORN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8955 { 13615 /* paadd.b */, RISCV::PAADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8956 { 13623 /* paadd.db */, RISCV::PAADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8957 { 13632 /* paadd.dh */, RISCV::PAADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8958 { 13641 /* paadd.dw */, RISCV::PAADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8959 { 13650 /* paadd.h */, RISCV::PAADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8960 { 13658 /* paadd.w */, RISCV::PAADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8961 { 13666 /* paaddu.b */, RISCV::PAADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8962 { 13675 /* paaddu.db */, RISCV::PAADDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8963 { 13685 /* paaddu.dh */, RISCV::PAADDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8964 { 13695 /* paaddu.dw */, RISCV::PAADDU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8965 { 13705 /* paaddu.h */, RISCV::PAADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8966 { 13714 /* paaddu.w */, RISCV::PAADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8967 { 13723 /* paas.dhx */, RISCV::PAAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8968 { 13732 /* paas.hx */, RISCV::PAAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8969 { 13740 /* paas.wx */, RISCV::PAAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8970 { 13748 /* pabd.b */, RISCV::PABD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8971 { 13755 /* pabd.db */, RISCV::PABD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8972 { 13763 /* pabd.dh */, RISCV::PABD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8973 { 13771 /* pabd.h */, RISCV::PABD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8974 { 13778 /* pabdsumau.b */, RISCV::PABDSUMAU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8975 { 13790 /* pabdsumu.b */, RISCV::PABDSUMU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8976 { 13801 /* pabdu.b */, RISCV::PABDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8977 { 13809 /* pabdu.db */, RISCV::PABDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8978 { 13818 /* pabdu.dh */, RISCV::PABDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8979 { 13827 /* pabdu.h */, RISCV::PABDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8980 { 13835 /* pabs.b */, RISCV::PABD_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
8981 { 13842 /* pabs.db */, RISCV::PABD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8982 { 13850 /* pabs.dh */, RISCV::PABD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8983 { 13858 /* pabs.h */, RISCV::PABD_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
8984 { 13865 /* pack */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkbOrP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8985 { 13870 /* packh */, RISCV::PACKH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8986 { 13876 /* packw */, RISCV::PACKW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8987 { 13882 /* packy */, RISCV::PACKY, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
8988 { 13888 /* padd.b */, RISCV::PADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8989 { 13895 /* padd.bs */, RISCV::PADD_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8990 { 13903 /* padd.db */, RISCV::PADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8991 { 13911 /* padd.dbs */, RISCV::PADD_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8992 { 13920 /* padd.dh */, RISCV::PADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8993 { 13928 /* padd.dhs */, RISCV::PADD_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8994 { 13937 /* padd.dw */, RISCV::PADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
8995 { 13945 /* padd.dws */, RISCV::PADD_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
8996 { 13954 /* padd.h */, RISCV::PADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8997 { 13961 /* padd.hs */, RISCV::PADD_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8998 { 13969 /* padd.w */, RISCV::PADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
8999 { 13976 /* padd.ws */, RISCV::PADD_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9000 { 13984 /* pas.dhx */, RISCV::PAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9001 { 13992 /* pas.hx */, RISCV::PAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9002 { 13999 /* pas.wx */, RISCV::PAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9003 { 14006 /* pasa.dhx */, RISCV::PASA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9004 { 14015 /* pasa.hx */, RISCV::PASA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9005 { 14023 /* pasa.wx */, RISCV::PASA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9006 { 14031 /* pasub.b */, RISCV::PASUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9007 { 14039 /* pasub.db */, RISCV::PASUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9008 { 14048 /* pasub.dh */, RISCV::PASUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9009 { 14057 /* pasub.dw */, RISCV::PASUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9010 { 14066 /* pasub.h */, RISCV::PASUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9011 { 14074 /* pasub.w */, RISCV::PASUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9012 { 14082 /* pasubu.b */, RISCV::PASUBU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9013 { 14091 /* pasubu.db */, RISCV::PASUBU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9014 { 14101 /* pasubu.dh */, RISCV::PASUBU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9015 { 14111 /* pasubu.dw */, RISCV::PASUBU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9016 { 14121 /* pasubu.h */, RISCV::PASUBU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9017 { 14130 /* pasubu.w */, RISCV::PASUBU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9018 { 14139 /* pause */, RISCV::FENCE, Convert__imm_95_1__imm_95_0, AMFBS_None, { }, },
9019 { 14145 /* pli.b */, RISCV::PLI_B, Convert__Reg1_0__SImm8PLI_B1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm8PLI_B }, },
9020 { 14151 /* pli.db */, RISCV::PLI_DB, Convert__GPRPairRV321_0__SImm8PLI_B1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm8PLI_B }, },
9021 { 14158 /* pli.dh */, RISCV::PLI_DH, Convert__GPRPairRV321_0__SImm10PLI_H1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm10PLI_H }, },
9022 { 14165 /* pli.h */, RISCV::PLI_H, Convert__Reg1_0__SImm10PLI_H1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm10PLI_H }, },
9023 { 14171 /* pli.w */, RISCV::PLI_W, Convert__Reg1_0__SImm10PLI_W1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_SImm10PLI_W }, },
9024 { 14177 /* plui.dh */, RISCV::PLUI_DH, Convert__GPRPairRV321_0__SImm10PLUI1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_SImm10PLUI }, },
9025 { 14185 /* plui.h */, RISCV::PLUI_H, Convert__Reg1_0__SImm10PLUI1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_SImm10PLUI }, },
9026 { 14192 /* plui.w */, RISCV::PLUI_W, Convert__Reg1_0__SImm10PLUI1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_SImm10PLUI }, },
9027 { 14199 /* pm2add.h */, RISCV::PM2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9028 { 14208 /* pm2add.hx */, RISCV::PM2ADD_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9029 { 14218 /* pm2add.w */, RISCV::PM2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9030 { 14227 /* pm2add.wx */, RISCV::PM2ADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9031 { 14237 /* pm2adda.h */, RISCV::PM2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9032 { 14247 /* pm2adda.hx */, RISCV::PM2ADDA_HX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9033 { 14258 /* pm2adda.w */, RISCV::PM2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9034 { 14268 /* pm2adda.wx */, RISCV::PM2ADDA_WX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9035 { 14279 /* pm2addasu.h */, RISCV::PM2ADDASU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9036 { 14291 /* pm2addasu.w */, RISCV::PM2ADDASU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9037 { 14303 /* pm2addau.h */, RISCV::PM2ADDAU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9038 { 14314 /* pm2addau.w */, RISCV::PM2ADDAU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9039 { 14325 /* pm2addsu.h */, RISCV::PM2ADDSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9040 { 14336 /* pm2addsu.w */, RISCV::PM2ADDSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9041 { 14347 /* pm2addu.h */, RISCV::PM2ADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9042 { 14357 /* pm2addu.w */, RISCV::PM2ADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9043 { 14367 /* pm2sadd.h */, RISCV::PM2SADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9044 { 14377 /* pm2sadd.hx */, RISCV::PM2SADD_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9045 { 14388 /* pm2sub.h */, RISCV::PM2SUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9046 { 14397 /* pm2sub.hx */, RISCV::PM2SUB_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9047 { 14407 /* pm2sub.w */, RISCV::PM2SUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9048 { 14416 /* pm2sub.wx */, RISCV::PM2SUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9049 { 14426 /* pm2suba.h */, RISCV::PM2SUBA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9050 { 14436 /* pm2suba.hx */, RISCV::PM2SUBA_HX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9051 { 14447 /* pm2suba.w */, RISCV::PM2SUBA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9052 { 14457 /* pm2suba.wx */, RISCV::PM2SUBA_WX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9053 { 14468 /* pm2wadd.h */, RISCV::PM2WADD_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9054 { 14478 /* pm2wadd.hx */, RISCV::PM2WADD_HX, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9055 { 14489 /* pm2wadda.h */, RISCV::PM2WADDA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9056 { 14500 /* pm2wadda.hx */, RISCV::PM2WADDA_HX, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9057 { 14512 /* pm2waddasu.h */, RISCV::PM2WADDASU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9058 { 14525 /* pm2waddau.h */, RISCV::PM2WADDAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9059 { 14537 /* pm2waddsu.h */, RISCV::PM2WADDSU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9060 { 14549 /* pm2waddu.h */, RISCV::PM2WADDU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9061 { 14560 /* pm2wsub.h */, RISCV::PM2WSUB_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9062 { 14570 /* pm2wsub.hx */, RISCV::PM2WSUB_HX, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9063 { 14581 /* pm2wsuba.h */, RISCV::PM2WSUBA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9064 { 14592 /* pm2wsuba.hx */, RISCV::PM2WSUBA_HX, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9065 { 14604 /* pm4add.b */, RISCV::PM4ADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9066 { 14613 /* pm4add.h */, RISCV::PM4ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9067 { 14622 /* pm4adda.b */, RISCV::PM4ADDA_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9068 { 14632 /* pm4adda.h */, RISCV::PM4ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9069 { 14642 /* pm4addasu.b */, RISCV::PM4ADDASU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9070 { 14654 /* pm4addasu.h */, RISCV::PM4ADDASU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9071 { 14666 /* pm4addau.b */, RISCV::PM4ADDAU_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9072 { 14677 /* pm4addau.h */, RISCV::PM4ADDAU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9073 { 14688 /* pm4addsu.b */, RISCV::PM4ADDSU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9074 { 14699 /* pm4addsu.h */, RISCV::PM4ADDSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9075 { 14710 /* pm4addu.b */, RISCV::PM4ADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9076 { 14720 /* pm4addu.h */, RISCV::PM4ADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9077 { 14730 /* pmacc.w.h00 */, RISCV::PMACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9078 { 14742 /* pmacc.w.h01 */, RISCV::PMACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9079 { 14754 /* pmacc.w.h11 */, RISCV::PMACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9080 { 14766 /* pmaccsu.w.h00 */, RISCV::PMACCSU_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9081 { 14780 /* pmaccsu.w.h11 */, RISCV::PMACCSU_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9082 { 14794 /* pmaccu.w.h00 */, RISCV::PMACCU_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9083 { 14807 /* pmaccu.w.h01 */, RISCV::PMACCU_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9084 { 14820 /* pmaccu.w.h11 */, RISCV::PMACCU_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9085 { 14833 /* pmax.b */, RISCV::PMAX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9086 { 14840 /* pmax.db */, RISCV::PMAX_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9087 { 14848 /* pmax.dh */, RISCV::PMAX_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9088 { 14856 /* pmax.dw */, RISCV::PMAX_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9089 { 14864 /* pmax.h */, RISCV::PMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9090 { 14871 /* pmax.w */, RISCV::PMAX_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9091 { 14878 /* pmaxu.b */, RISCV::PMAXU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9092 { 14886 /* pmaxu.db */, RISCV::PMAXU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9093 { 14895 /* pmaxu.dh */, RISCV::PMAXU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9094 { 14904 /* pmaxu.dw */, RISCV::PMAXU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9095 { 14913 /* pmaxu.h */, RISCV::PMAXU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9096 { 14921 /* pmaxu.w */, RISCV::PMAXU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9097 { 14929 /* pmhacc.h */, RISCV::PMHACC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9098 { 14938 /* pmhacc.h.b0 */, RISCV::PMHACC_H_B0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9099 { 14950 /* pmhacc.h.b1 */, RISCV::PMHACC_H_B1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9100 { 14962 /* pmhacc.w */, RISCV::PMHACC_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9101 { 14971 /* pmhacc.w.h0 */, RISCV::PMHACC_W_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9102 { 14983 /* pmhacc.w.h1 */, RISCV::PMHACC_W_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9103 { 14995 /* pmhaccsu.h */, RISCV::PMHACCSU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9104 { 15006 /* pmhaccsu.h.b0 */, RISCV::PMHACCSU_H_B0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9105 { 15020 /* pmhaccsu.h.b1 */, RISCV::PMHACCSU_H_B1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9106 { 15034 /* pmhaccsu.w */, RISCV::PMHACCSU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9107 { 15045 /* pmhaccsu.w.h0 */, RISCV::PMHACCSU_W_H0, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9108 { 15059 /* pmhaccsu.w.h1 */, RISCV::PMHACCSU_W_H1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9109 { 15073 /* pmhaccu.h */, RISCV::PMHACCU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9110 { 15083 /* pmhaccu.w */, RISCV::PMHACCU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9111 { 15093 /* pmhracc.h */, RISCV::PMHRACC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9112 { 15103 /* pmhracc.w */, RISCV::PMHRACC_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9113 { 15113 /* pmhraccsu.h */, RISCV::PMHRACCSU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9114 { 15125 /* pmhraccsu.w */, RISCV::PMHRACCSU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9115 { 15137 /* pmhraccu.h */, RISCV::PMHRACCU_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9116 { 15148 /* pmhraccu.w */, RISCV::PMHRACCU_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9117 { 15159 /* pmin.b */, RISCV::PMIN_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9118 { 15166 /* pmin.db */, RISCV::PMIN_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9119 { 15174 /* pmin.dh */, RISCV::PMIN_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9120 { 15182 /* pmin.dw */, RISCV::PMIN_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9121 { 15190 /* pmin.h */, RISCV::PMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9122 { 15197 /* pmin.w */, RISCV::PMIN_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9123 { 15204 /* pminu.b */, RISCV::PMINU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9124 { 15212 /* pminu.db */, RISCV::PMINU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9125 { 15221 /* pminu.dh */, RISCV::PMINU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9126 { 15230 /* pminu.dw */, RISCV::PMINU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9127 { 15239 /* pminu.h */, RISCV::PMINU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9128 { 15247 /* pminu.w */, RISCV::PMINU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9129 { 15255 /* pmq2add.h */, RISCV::PMQ2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9130 { 15265 /* pmq2add.w */, RISCV::PMQ2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9131 { 15275 /* pmq2adda.h */, RISCV::PMQ2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9132 { 15286 /* pmq2adda.w */, RISCV::PMQ2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9133 { 15297 /* pmqacc.w.h00 */, RISCV::PMQACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9134 { 15310 /* pmqacc.w.h01 */, RISCV::PMQACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9135 { 15323 /* pmqacc.w.h11 */, RISCV::PMQACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9136 { 15336 /* pmqr2add.h */, RISCV::PMQR2ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9137 { 15347 /* pmqr2add.w */, RISCV::PMQR2ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9138 { 15358 /* pmqr2adda.h */, RISCV::PMQR2ADDA_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9139 { 15370 /* pmqr2adda.w */, RISCV::PMQR2ADDA_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9140 { 15382 /* pmqracc.w.h00 */, RISCV::PMQRACC_W_H00, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9141 { 15396 /* pmqracc.w.h01 */, RISCV::PMQRACC_W_H01, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9142 { 15410 /* pmqracc.w.h11 */, RISCV::PMQRACC_W_H11, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9143 { 15424 /* pmqrwacc.h */, RISCV::PMQRWACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9144 { 15435 /* pmqwacc.h */, RISCV::PMQWACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9145 { 15445 /* pmseq.b */, RISCV::PMSEQ_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9146 { 15453 /* pmseq.db */, RISCV::PMSEQ_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9147 { 15462 /* pmseq.dh */, RISCV::PMSEQ_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9148 { 15471 /* pmseq.dw */, RISCV::PMSEQ_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9149 { 15480 /* pmseq.h */, RISCV::PMSEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9150 { 15488 /* pmseq.w */, RISCV::PMSEQ_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9151 { 15496 /* pmseqz.b */, RISCV::PMSEQ_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9152 { 15505 /* pmseqz.db */, RISCV::PMSEQ_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9153 { 15515 /* pmseqz.dh */, RISCV::PMSEQ_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9154 { 15525 /* pmseqz.dw */, RISCV::PMSEQ_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9155 { 15535 /* pmseqz.h */, RISCV::PMSEQ_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9156 { 15544 /* pmseqz.w */, RISCV::PMSEQ_W, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9157 { 15553 /* pmsgt.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9158 { 15561 /* pmsgt.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9159 { 15570 /* pmsgt.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9160 { 15579 /* pmsgt.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9161 { 15588 /* pmsgt.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9162 { 15596 /* pmsgt.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9163 { 15604 /* pmsgtu.b */, RISCV::PMSLTU_B, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9164 { 15613 /* pmsgtu.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9165 { 15623 /* pmsgtu.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9166 { 15633 /* pmsgtu.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__GPRPairRV321_2__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9167 { 15643 /* pmsgtu.h */, RISCV::PMSLTU_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9168 { 15652 /* pmsgtu.w */, RISCV::PMSLTU_W, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9169 { 15661 /* pmsgtz.b */, RISCV::PMSLT_B, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9170 { 15670 /* pmsgtz.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9171 { 15680 /* pmsgtz.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9172 { 15690 /* pmsgtz.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9173 { 15700 /* pmsgtz.h */, RISCV::PMSLT_H, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9174 { 15709 /* pmsgtz.w */, RISCV::PMSLT_W, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9175 { 15718 /* pmslt.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9176 { 15726 /* pmslt.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9177 { 15735 /* pmslt.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9178 { 15744 /* pmslt.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9179 { 15753 /* pmslt.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9180 { 15761 /* pmslt.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9181 { 15769 /* pmsltu.b */, RISCV::PMSLTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9182 { 15778 /* pmsltu.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9183 { 15788 /* pmsltu.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9184 { 15798 /* pmsltu.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9185 { 15808 /* pmsltu.h */, RISCV::PMSLTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9186 { 15817 /* pmsltu.w */, RISCV::PMSLTU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9187 { 15826 /* pmsltz.b */, RISCV::PMSLT_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9188 { 15835 /* pmsltz.db */, RISCV::PMSLT_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9189 { 15845 /* pmsltz.dh */, RISCV::PMSLT_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9190 { 15855 /* pmsltz.dw */, RISCV::PMSLT_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9191 { 15865 /* pmsltz.h */, RISCV::PMSLT_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9192 { 15874 /* pmsltz.w */, RISCV::PMSLT_W, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9193 { 15883 /* pmsnez.b */, RISCV::PMSLTU_B, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9194 { 15892 /* pmsnez.db */, RISCV::PMSLTU_DB, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9195 { 15902 /* pmsnez.dh */, RISCV::PMSLTU_DH, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9196 { 15912 /* pmsnez.dw */, RISCV::PMSLTU_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9197 { 15922 /* pmsnez.h */, RISCV::PMSLTU_H, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9198 { 15931 /* pmsnez.w */, RISCV::PMSLTU_W, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9199 { 15940 /* pmul.h.b00 */, RISCV::PMUL_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9200 { 15951 /* pmul.h.b01 */, RISCV::PMUL_H_B01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9201 { 15962 /* pmul.h.b11 */, RISCV::PMUL_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9202 { 15973 /* pmul.w.h00 */, RISCV::PMUL_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9203 { 15984 /* pmul.w.h01 */, RISCV::PMUL_W_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9204 { 15995 /* pmul.w.h11 */, RISCV::PMUL_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9205 { 16006 /* pmulh.h */, RISCV::PMULH_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9206 { 16014 /* pmulh.h.b0 */, RISCV::PMULH_H_B0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9207 { 16025 /* pmulh.h.b1 */, RISCV::PMULH_H_B1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9208 { 16036 /* pmulh.w */, RISCV::PMULH_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9209 { 16044 /* pmulh.w.h0 */, RISCV::PMULH_W_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9210 { 16055 /* pmulh.w.h1 */, RISCV::PMULH_W_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9211 { 16066 /* pmulhr.h */, RISCV::PMULHR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9212 { 16075 /* pmulhr.w */, RISCV::PMULHR_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9213 { 16084 /* pmulhrsu.h */, RISCV::PMULHRSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9214 { 16095 /* pmulhrsu.w */, RISCV::PMULHRSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9215 { 16106 /* pmulhru.h */, RISCV::PMULHRU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9216 { 16116 /* pmulhru.w */, RISCV::PMULHRU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9217 { 16126 /* pmulhsu.h */, RISCV::PMULHSU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9218 { 16136 /* pmulhsu.h.b0 */, RISCV::PMULHSU_H_B0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9219 { 16149 /* pmulhsu.h.b1 */, RISCV::PMULHSU_H_B1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9220 { 16162 /* pmulhsu.w */, RISCV::PMULHSU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9221 { 16172 /* pmulhsu.w.h0 */, RISCV::PMULHSU_W_H0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9222 { 16185 /* pmulhsu.w.h1 */, RISCV::PMULHSU_W_H1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9223 { 16198 /* pmulhu.h */, RISCV::PMULHU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9224 { 16207 /* pmulhu.w */, RISCV::PMULHU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9225 { 16216 /* pmulq.h */, RISCV::PMULQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9226 { 16224 /* pmulq.w */, RISCV::PMULQ_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9227 { 16232 /* pmulqr.h */, RISCV::PMULQR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9228 { 16241 /* pmulqr.w */, RISCV::PMULQR_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9229 { 16250 /* pmulsu.h.b00 */, RISCV::PMULSU_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9230 { 16263 /* pmulsu.h.b11 */, RISCV::PMULSU_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9231 { 16276 /* pmulsu.w.h00 */, RISCV::PMULSU_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9232 { 16289 /* pmulsu.w.h11 */, RISCV::PMULSU_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9233 { 16302 /* pmulu.h.b00 */, RISCV::PMULU_H_B00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9234 { 16314 /* pmulu.h.b01 */, RISCV::PMULU_H_B01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9235 { 16326 /* pmulu.h.b11 */, RISCV::PMULU_H_B11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9236 { 16338 /* pmulu.w.h00 */, RISCV::PMULU_W_H00, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9237 { 16350 /* pmulu.w.h01 */, RISCV::PMULU_W_H01, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9238 { 16362 /* pmulu.w.h11 */, RISCV::PMULU_W_H11, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9239 { 16374 /* pmv.bs */, RISCV::PADD_BS, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9240 { 16381 /* pmv.dbs */, RISCV::PADD_DBS, Convert__GPRPairRV321_0__regX0_Pair__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9241 { 16389 /* pmv.dhs */, RISCV::PADD_DHS, Convert__GPRPairRV321_0__regX0_Pair__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9242 { 16397 /* pmv.dws */, RISCV::PADD_DWS, Convert__GPRPairRV321_0__regX0_Pair__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9243 { 16405 /* pmv.hs */, RISCV::PADD_HS, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9244 { 16412 /* pmv.ws */, RISCV::PADD_WS, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9245 { 16419 /* pnclip.bs */, RISCV::PNCLIP_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9246 { 16429 /* pnclip.hs */, RISCV::PNCLIP_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9247 { 16439 /* pnclipi.b */, RISCV::PNCLIPI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9248 { 16449 /* pnclipi.h */, RISCV::PNCLIPI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9249 { 16459 /* pnclipiu.b */, RISCV::PNCLIPIU_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9250 { 16470 /* pnclipiu.h */, RISCV::PNCLIPIU_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9251 { 16481 /* pnclipp.b */, RISCV::PNCLIPP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9252 { 16491 /* pnclipp.h */, RISCV::PNCLIPP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9253 { 16501 /* pnclipp.w */, RISCV::PNCLIPP_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9254 { 16511 /* pnclipr.bs */, RISCV::PNCLIPR_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9255 { 16522 /* pnclipr.hs */, RISCV::PNCLIPR_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9256 { 16533 /* pnclipri.b */, RISCV::PNCLIPRI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9257 { 16544 /* pnclipri.h */, RISCV::PNCLIPRI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9258 { 16555 /* pnclipriu.b */, RISCV::PNCLIPRIU_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9259 { 16567 /* pnclipriu.h */, RISCV::PNCLIPRIU_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9260 { 16579 /* pnclipru.bs */, RISCV::PNCLIPRU_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9261 { 16591 /* pnclipru.hs */, RISCV::PNCLIPRU_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9262 { 16603 /* pnclipu.bs */, RISCV::PNCLIPU_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9263 { 16614 /* pnclipu.hs */, RISCV::PNCLIPU_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9264 { 16625 /* pnclipup.b */, RISCV::PNCLIPUP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9265 { 16636 /* pnclipup.h */, RISCV::PNCLIPUP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9266 { 16647 /* pnclipup.w */, RISCV::PNCLIPUP_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9267 { 16658 /* pncvt.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__imm_95_0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9268 { 16666 /* pncvt.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__imm_95_0, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9269 { 16674 /* pncvt.wb */, RISCV::UNZIP8P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9270 { 16683 /* pncvt.wh */, RISCV::UNZIP16P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9271 { 16692 /* pncvth.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__imm_95_8, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9272 { 16701 /* pncvth.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__imm_95_16, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32 }, },
9273 { 16710 /* pncvth.wb */, RISCV::UNZIP8HP, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9274 { 16720 /* pncvth.wh */, RISCV::UNZIP16HP, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9275 { 16730 /* pneg.b */, RISCV::PSUB_B, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9276 { 16737 /* pneg.db */, RISCV::PSUB_DB, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9277 { 16745 /* pneg.dh */, RISCV::PSUB_DH, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9278 { 16753 /* pneg.dw */, RISCV::PSUB_DW, Convert__GPRPairRV321_0__regX0_Pair__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9279 { 16761 /* pneg.h */, RISCV::PSUB_H, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9280 { 16768 /* pneg.w */, RISCV::PSUB_W, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9281 { 16775 /* pnsra.bs */, RISCV::PNSRA_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9282 { 16784 /* pnsra.hs */, RISCV::PNSRA_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9283 { 16793 /* pnsrai.b */, RISCV::PNSRAI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9284 { 16802 /* pnsrai.h */, RISCV::PNSRAI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9285 { 16811 /* pnsrar.bs */, RISCV::PNSRAR_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9286 { 16821 /* pnsrar.hs */, RISCV::PNSRAR_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9287 { 16831 /* pnsrari.b */, RISCV::PNSRARI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9288 { 16841 /* pnsrari.h */, RISCV::PNSRARI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9289 { 16851 /* pnsrl.bs */, RISCV::PNSRL_BS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9290 { 16860 /* pnsrl.hs */, RISCV::PNSRL_HS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9291 { 16869 /* pnsrli.b */, RISCV::PNSRLI_B, Convert__Reg1_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm4 }, },
9292 { 16878 /* pnsrli.h */, RISCV::PNSRLI_H, Convert__Reg1_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_UImm5 }, },
9293 { 16887 /* ppaire.b */, RISCV::PPAIRE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9294 { 16896 /* ppaire.db */, RISCV::PPAIRE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9295 { 16906 /* ppaire.dh */, RISCV::PPAIRE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9296 { 16916 /* ppaire.h */, RISCV::PPAIRE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9297 { 16916 /* ppaire.h */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9298 { 16925 /* ppaire.w */, RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9299 { 16934 /* ppaireo.b */, RISCV::PPAIREO_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9300 { 16944 /* ppaireo.db */, RISCV::PPAIREO_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9301 { 16955 /* ppaireo.dh */, RISCV::PPAIREO_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9302 { 16966 /* ppaireo.h */, RISCV::PPAIREO_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9303 { 16976 /* ppaireo.w */, RISCV::PPAIREO_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9304 { 16986 /* ppairo.b */, RISCV::PPAIRO_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9305 { 16995 /* ppairo.db */, RISCV::PPAIRO_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9306 { 17005 /* ppairo.dh */, RISCV::PPAIRO_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9307 { 17015 /* ppairo.h */, RISCV::PPAIRO_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9308 { 17024 /* ppairo.w */, RISCV::PPAIRO_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9309 { 17033 /* ppairoe.b */, RISCV::PPAIROE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9310 { 17043 /* ppairoe.db */, RISCV::PPAIROE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9311 { 17054 /* ppairoe.dh */, RISCV::PPAIROE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9312 { 17065 /* ppairoe.h */, RISCV::PPAIROE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9313 { 17075 /* ppairoe.w */, RISCV::PPAIROE_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9314 { 17085 /* predsum.bs */, RISCV::PREDSUM_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9315 { 17096 /* predsum.dbs */, RISCV::PREDSUM_DBS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9316 { 17108 /* predsum.dhs */, RISCV::PREDSUM_DHS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9317 { 17120 /* predsum.hs */, RISCV::PREDSUM_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9318 { 17131 /* predsum.ws */, RISCV::PREDSUM_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9319 { 17142 /* predsumu.bs */, RISCV::PREDSUMU_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9320 { 17154 /* predsumu.dbs */, RISCV::PREDSUMU_DBS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9321 { 17167 /* predsumu.dhs */, RISCV::PREDSUMU_DHS, Convert__Reg1_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPRPairRV32, MCK_GPR }, },
9322 { 17180 /* predsumu.hs */, RISCV::PREDSUMU_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9323 { 17192 /* predsumu.ws */, RISCV::PREDSUMU_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9324 { 17204 /* prefetch.i */, RISCV::PREFETCH_I, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_None, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
9325 { 17215 /* prefetch.r */, RISCV::PREFETCH_R, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_None, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
9326 { 17226 /* prefetch.w */, RISCV::PREFETCH_W, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_None, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
9327 { 17237 /* psa.dhx */, RISCV::PSA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9328 { 17245 /* psa.hx */, RISCV::PSA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9329 { 17252 /* psa.wx */, RISCV::PSA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9330 { 17259 /* psabs.b */, RISCV::PSABS_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9331 { 17267 /* psabs.db */, RISCV::PSABS_DB, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9332 { 17276 /* psabs.dh */, RISCV::PSABS_DH, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9333 { 17285 /* psabs.h */, RISCV::PSABS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9334 { 17293 /* psadd.b */, RISCV::PSADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9335 { 17301 /* psadd.db */, RISCV::PSADD_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9336 { 17310 /* psadd.dh */, RISCV::PSADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9337 { 17319 /* psadd.dw */, RISCV::PSADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9338 { 17328 /* psadd.h */, RISCV::PSADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9339 { 17336 /* psadd.w */, RISCV::PSADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9340 { 17344 /* psaddu.b */, RISCV::PSADDU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9341 { 17353 /* psaddu.db */, RISCV::PSADDU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9342 { 17363 /* psaddu.dh */, RISCV::PSADDU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9343 { 17373 /* psaddu.dw */, RISCV::PSADDU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9344 { 17383 /* psaddu.h */, RISCV::PSADDU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9345 { 17392 /* psaddu.w */, RISCV::PSADDU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9346 { 17401 /* psas.dhx */, RISCV::PSAS_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9347 { 17410 /* psas.hx */, RISCV::PSAS_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9348 { 17418 /* psas.wx */, RISCV::PSAS_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9349 { 17426 /* psati.dh */, RISCV::PSATI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9350 { 17435 /* psati.dw */, RISCV::PSATI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9351 { 17444 /* psati.h */, RISCV::PSATI_H, Convert__Reg1_0__Reg1_1__UImm4Plus11_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4Plus1 }, },
9352 { 17452 /* psati.w */, RISCV::PSATI_W, Convert__Reg1_0__Reg1_1__UImm5Plus11_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5Plus1 }, },
9353 { 17460 /* psext.dh.b */, RISCV::PSEXT_DH_B, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9354 { 17471 /* psext.dw.b */, RISCV::PSEXT_DW_B, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9355 { 17482 /* psext.dw.h */, RISCV::PSEXT_DW_H, Convert__GPRPairRV321_0__GPRPairRV321_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9356 { 17493 /* psext.h.b */, RISCV::PSEXT_H_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9357 { 17503 /* psext.w.b */, RISCV::PSEXT_W_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9358 { 17513 /* psext.w.h */, RISCV::PSEXT_W_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9359 { 17523 /* psh1add.dh */, RISCV::PSH1ADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9360 { 17534 /* psh1add.dw */, RISCV::PSH1ADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9361 { 17545 /* psh1add.h */, RISCV::PSH1ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9362 { 17555 /* psh1add.w */, RISCV::PSH1ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9363 { 17565 /* psll.bs */, RISCV::PSLL_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9364 { 17573 /* psll.dbs */, RISCV::PSLL_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9365 { 17582 /* psll.dhs */, RISCV::PSLL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9366 { 17591 /* psll.dws */, RISCV::PSLL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9367 { 17600 /* psll.hs */, RISCV::PSLL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9368 { 17608 /* psll.ws */, RISCV::PSLL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9369 { 17616 /* pslli.b */, RISCV::PSLLI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
9370 { 17624 /* pslli.db */, RISCV::PSLLI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
9371 { 17633 /* pslli.dh */, RISCV::PSLLI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9372 { 17642 /* pslli.dw */, RISCV::PSLLI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9373 { 17651 /* pslli.h */, RISCV::PSLLI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9374 { 17659 /* pslli.w */, RISCV::PSLLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9375 { 17667 /* psra.bs */, RISCV::PSRA_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9376 { 17675 /* psra.dbs */, RISCV::PSRA_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9377 { 17684 /* psra.dhs */, RISCV::PSRA_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9378 { 17693 /* psra.dws */, RISCV::PSRA_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9379 { 17702 /* psra.hs */, RISCV::PSRA_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9380 { 17710 /* psra.ws */, RISCV::PSRA_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9381 { 17718 /* psrai.b */, RISCV::PSRAI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
9382 { 17726 /* psrai.db */, RISCV::PSRAI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
9383 { 17735 /* psrai.dh */, RISCV::PSRAI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9384 { 17744 /* psrai.dw */, RISCV::PSRAI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9385 { 17753 /* psrai.h */, RISCV::PSRAI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9386 { 17761 /* psrai.w */, RISCV::PSRAI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9387 { 17769 /* psrari.dh */, RISCV::PSRARI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9388 { 17779 /* psrari.dw */, RISCV::PSRARI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9389 { 17789 /* psrari.h */, RISCV::PSRARI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9390 { 17798 /* psrari.w */, RISCV::PSRARI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9391 { 17807 /* psrl.bs */, RISCV::PSRL_BS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9392 { 17815 /* psrl.dbs */, RISCV::PSRL_DBS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9393 { 17824 /* psrl.dhs */, RISCV::PSRL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9394 { 17833 /* psrl.dws */, RISCV::PSRL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9395 { 17842 /* psrl.hs */, RISCV::PSRL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9396 { 17850 /* psrl.ws */, RISCV::PSRL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9397 { 17858 /* psrli.b */, RISCV::PSRLI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
9398 { 17866 /* psrli.db */, RISCV::PSRLI_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm31_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm3 }, },
9399 { 17875 /* psrli.dh */, RISCV::PSRLI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9400 { 17884 /* psrli.dw */, RISCV::PSRLI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9401 { 17893 /* psrli.h */, RISCV::PSRLI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9402 { 17901 /* psrli.w */, RISCV::PSRLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9403 { 17909 /* pssa.dhx */, RISCV::PSSA_DHX, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9404 { 17918 /* pssa.hx */, RISCV::PSSA_HX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9405 { 17926 /* pssa.wx */, RISCV::PSSA_WX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9406 { 17934 /* pssh1sadd.dh */, RISCV::PSSH1SADD_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9407 { 17947 /* pssh1sadd.dw */, RISCV::PSSH1SADD_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9408 { 17960 /* pssh1sadd.h */, RISCV::PSSH1SADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9409 { 17972 /* pssh1sadd.w */, RISCV::PSSH1SADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9410 { 17984 /* pssha.dhs */, RISCV::PSSHA_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9411 { 17994 /* pssha.dws */, RISCV::PSSHA_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9412 { 18004 /* pssha.hs */, RISCV::PSSHA_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9413 { 18013 /* pssha.ws */, RISCV::PSSHA_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9414 { 18022 /* psshar.dhs */, RISCV::PSSHAR_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9415 { 18033 /* psshar.dws */, RISCV::PSSHAR_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9416 { 18044 /* psshar.hs */, RISCV::PSSHAR_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9417 { 18054 /* psshar.ws */, RISCV::PSSHAR_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9418 { 18064 /* psshl.dhs */, RISCV::PSSHL_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9419 { 18074 /* psshl.dws */, RISCV::PSSHL_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9420 { 18084 /* psshl.hs */, RISCV::PSSHL_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9421 { 18093 /* psshl.ws */, RISCV::PSSHL_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9422 { 18102 /* psshlr.dhs */, RISCV::PSSHLR_DHS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9423 { 18113 /* psshlr.dws */, RISCV::PSSHLR_DWS, Convert__GPRPairRV321_0__GPRPairRV321_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPR }, },
9424 { 18124 /* psshlr.hs */, RISCV::PSSHLR_HS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9425 { 18134 /* psshlr.ws */, RISCV::PSSHLR_WS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9426 { 18144 /* psslai.dh */, RISCV::PSSLAI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9427 { 18154 /* psslai.dw */, RISCV::PSSLAI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9428 { 18164 /* psslai.h */, RISCV::PSSLAI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9429 { 18173 /* psslai.w */, RISCV::PSSLAI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9430 { 18182 /* pssub.b */, RISCV::PSSUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9431 { 18190 /* pssub.db */, RISCV::PSSUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9432 { 18199 /* pssub.dh */, RISCV::PSSUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9433 { 18208 /* pssub.dw */, RISCV::PSSUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9434 { 18217 /* pssub.h */, RISCV::PSSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9435 { 18225 /* pssub.w */, RISCV::PSSUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9436 { 18233 /* pssubu.b */, RISCV::PSSUBU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9437 { 18242 /* pssubu.db */, RISCV::PSSUBU_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9438 { 18252 /* pssubu.dh */, RISCV::PSSUBU_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9439 { 18262 /* pssubu.dw */, RISCV::PSSUBU_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9440 { 18272 /* pssubu.h */, RISCV::PSSUBU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9441 { 18281 /* pssubu.w */, RISCV::PSSUBU_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9442 { 18290 /* psub.b */, RISCV::PSUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9443 { 18297 /* psub.db */, RISCV::PSUB_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9444 { 18305 /* psub.dh */, RISCV::PSUB_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9445 { 18313 /* psub.dw */, RISCV::PSUB_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9446 { 18321 /* psub.h */, RISCV::PSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9447 { 18328 /* psub.w */, RISCV::PSUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9448 { 18335 /* pusati.dh */, RISCV::PUSATI_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm4 }, },
9449 { 18345 /* pusati.dw */, RISCV::PUSATI_DW, Convert__GPRPairRV321_0__GPRPairRV321_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_UImm5 }, },
9450 { 18355 /* pusati.h */, RISCV::PUSATI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
9451 { 18364 /* pusati.w */, RISCV::PUSATI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9452 { 18373 /* pwadd.b */, RISCV::PWADD_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9453 { 18381 /* pwadd.h */, RISCV::PWADD_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9454 { 18389 /* pwadda.b */, RISCV::PWADDA_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9455 { 18398 /* pwadda.h */, RISCV::PWADDA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9456 { 18407 /* pwaddau.b */, RISCV::PWADDAU_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9457 { 18417 /* pwaddau.h */, RISCV::PWADDAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9458 { 18427 /* pwaddu.b */, RISCV::PWADDU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9459 { 18436 /* pwaddu.h */, RISCV::PWADDU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9460 { 18445 /* pwcvt.b */, RISCV::PWADD_B, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9461 { 18453 /* pwcvt.h */, RISCV::PWADD_H, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9462 { 18461 /* pwcvth.b */, RISCV::WZIP8P, Convert__GPRPairRV321_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9463 { 18470 /* pwcvth.h */, RISCV::WZIP16P, Convert__GPRPairRV321_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9464 { 18479 /* pwcvth.wb */, RISCV::ZIP8P, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9465 { 18489 /* pwcvth.wh */, RISCV::ZIP16P, Convert__Reg1_0__regX0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9466 { 18499 /* pwcvtu.b */, RISCV::WZIP8P, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9467 { 18508 /* pwcvtu.h */, RISCV::WZIP16P, Convert__GPRPairRV321_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR }, },
9468 { 18517 /* pwcvtu.wb */, RISCV::ZIP8P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9469 { 18527 /* pwcvtu.wh */, RISCV::ZIP16P, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9470 { 18537 /* pwmacc.h */, RISCV::PWMACC_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9471 { 18546 /* pwmaccsu.h */, RISCV::PWMACCSU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9472 { 18557 /* pwmaccu.h */, RISCV::PWMACCU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9473 { 18567 /* pwmul.b */, RISCV::PWMUL_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9474 { 18575 /* pwmul.h */, RISCV::PWMUL_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9475 { 18583 /* pwmulsu.b */, RISCV::PWMULSU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9476 { 18593 /* pwmulsu.h */, RISCV::PWMULSU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9477 { 18603 /* pwmulu.b */, RISCV::PWMULU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9478 { 18612 /* pwmulu.h */, RISCV::PWMULU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9479 { 18621 /* pwsla.bs */, RISCV::PWSLA_BS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9480 { 18630 /* pwsla.hs */, RISCV::PWSLA_HS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9481 { 18639 /* pwslai.b */, RISCV::PWSLAI_B, Convert__GPRPairRV321_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm4 }, },
9482 { 18648 /* pwslai.h */, RISCV::PWSLAI_H, Convert__GPRPairRV321_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm5 }, },
9483 { 18657 /* pwsll.bs */, RISCV::PWSLL_BS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9484 { 18666 /* pwsll.hs */, RISCV::PWSLL_HS, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9485 { 18675 /* pwslli.b */, RISCV::PWSLLI_B, Convert__GPRPairRV321_0__Reg1_1__UImm41_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm4 }, },
9486 { 18684 /* pwslli.h */, RISCV::PWSLLI_H, Convert__GPRPairRV321_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm5 }, },
9487 { 18693 /* pwsub.b */, RISCV::PWSUB_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9488 { 18701 /* pwsub.h */, RISCV::PWSUB_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9489 { 18709 /* pwsuba.b */, RISCV::PWSUBA_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9490 { 18718 /* pwsuba.h */, RISCV::PWSUBA_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9491 { 18727 /* pwsubau.b */, RISCV::PWSUBAU_B, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9492 { 18737 /* pwsubau.h */, RISCV::PWSUBAU_H, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9493 { 18747 /* pwsubu.b */, RISCV::PWSUBU_B, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9494 { 18756 /* pwsubu.h */, RISCV::PWSUBU_H, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
9495 { 18765 /* pzext.dh.b */, RISCV::PPAIRE_DB, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9496 { 18776 /* pzext.dw.h */, RISCV::PPAIRE_DH, Convert__GPRPairRV321_0__GPRPairRV321_1__regX0_Pair, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9497 { 18787 /* pzext.h.b */, RISCV::PPAIRE_B, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR }, },
9498 { 18797 /* pzext.w.h */, RISCV::PPAIRE_H, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9499 { 18807 /* qc.addsat */, RISCV::QC_ADDSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9500 { 18817 /* qc.addusat */, RISCV::QC_ADDUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9501 { 18828 /* qc.beqi */, RISCV::QC_BEQI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9502 { 18836 /* qc.bgei */, RISCV::QC_BGEI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9503 { 18844 /* qc.bgeui */, RISCV::QC_BGEUI, Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_BareSImm13Lsb0 }, },
9504 { 18853 /* qc.blti */, RISCV::QC_BLTI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9505 { 18861 /* qc.bltui */, RISCV::QC_BLTUI, Convert__Reg1_0__UImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_BareSImm13Lsb0 }, },
9506 { 18870 /* qc.bnei */, RISCV::QC_BNEI, Convert__Reg1_0__SImm5NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm5NonZero, MCK_BareSImm13Lsb0 }, },
9507 { 18878 /* qc.brev32 */, RISCV::QC_BREV32, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9508 { 18888 /* qc.c.bexti */, RISCV::QC_C_BEXTI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
9509 { 18899 /* qc.c.bseti */, RISCV::QC_C_BSETI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
9510 { 18910 /* qc.c.clrint */, RISCV::QC_C_CLRINT, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9511 { 18922 /* qc.c.delay */, RISCV::C_SLLI, Convert__regX0__Tie0_1_1__UImm5NonZero1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5NonZero }, },
9512 { 18933 /* qc.c.di */, RISCV::QC_C_DI, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9513 { 18941 /* qc.c.dir */, RISCV::QC_C_DIR, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9514 { 18950 /* qc.c.ei */, RISCV::QC_C_EI, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9515 { 18958 /* qc.c.eir */, RISCV::QC_C_EIR, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9516 { 18967 /* qc.c.extu */, RISCV::QC_C_EXTU, Convert__Reg1_0__Tie0_1_1__UImm5GE6Plus11_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_UImm5GE6Plus1 }, },
9517 { 18977 /* qc.c.mienter */, RISCV::QC_C_MIENTER, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9518 { 18990 /* qc.c.mienter.nest */, RISCV::QC_C_MIENTER_NEST, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9519 { 19008 /* qc.c.mileaveret */, RISCV::QC_C_MILEAVERET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9520 { 19024 /* qc.c.mnret */, RISCV::QC_C_MNRET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9521 { 19035 /* qc.c.mret */, RISCV::QC_C_MRET, Convert_NoOperands, AMFBS_HasVendorXqciint_IsRV32, { }, },
9522 { 19045 /* qc.c.muliadd */, RISCV::QC_C_MULIADD, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRC, MCK_GPRC, MCK_UImm5 }, },
9523 { 19058 /* qc.c.mveqz */, RISCV::QC_C_MVEQZ, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRC, MCK_GPRC }, },
9524 { 19069 /* qc.c.ptrace */, RISCV::C_SLLI, Convert__regX0__Tie0_1_1__imm_95_0, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9525 { 19081 /* qc.c.setint */, RISCV::QC_C_SETINT, Convert__Reg1_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_GPRNoX0 }, },
9526 { 19093 /* qc.c.sync */, RISCV::QC_C_SYNC, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9527 { 19103 /* qc.c.syncr */, RISCV::QC_C_SYNCR, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9528 { 19114 /* qc.c.syncwf */, RISCV::QC_C_SYNCWF, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9529 { 19126 /* qc.c.syncwl */, RISCV::QC_C_SYNCWL, Convert__UImm5Slist1_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5Slist }, },
9530 { 19138 /* qc.clo */, RISCV::QC_CLO, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9531 { 19145 /* qc.clrinti */, RISCV::QC_CLRINTI, Convert__UImm101_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_UImm10 }, },
9532 { 19156 /* qc.cm.jalt */, RISCV::QC_CM_JALT, Convert__UImm8GE321_0, AMFBS_HasVendorXqccmt, { MCK_UImm8GE32 }, },
9533 { 19167 /* qc.cm.jt */, RISCV::QC_CM_JT, Convert__UImm51_0, AMFBS_HasVendorXqccmt, { MCK_UImm5 }, },
9534 { 19176 /* qc.cm.mva01s */, RISCV::QC_CM_MVA01S, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqccmp, { MCK_SR07, MCK_SR07 }, },
9535 { 19189 /* qc.cm.mvsa01 */, RISCV::QC_CM_MVSA01, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqccmp, { MCK_SR07, MCK_SR07 }, },
9536 { 19202 /* qc.cm.pop */, RISCV::QC_CM_POP, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9537 { 19212 /* qc.cm.popret */, RISCV::QC_CM_POPRET, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9538 { 19225 /* qc.cm.popretz */, RISCV::QC_CM_POPRETZ, Convert__RegList1_0__StackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_StackAdj }, },
9539 { 19239 /* qc.cm.push */, RISCV::QC_CM_PUSH, Convert__RegList1_0__NegStackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegList, MCK_NegStackAdj }, },
9540 { 19250 /* qc.cm.pushfp */, RISCV::QC_CM_PUSHFP, Convert__RegListS01_0__NegStackAdj1_1, AMFBS_HasVendorXqccmp, { MCK_RegListS0, MCK_NegStackAdj }, },
9541 { 19263 /* qc.compress2 */, RISCV::QC_COMPRESS2, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9542 { 19276 /* qc.compress3 */, RISCV::QC_COMPRESS3, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9543 { 19289 /* qc.csrrwr */, RISCV::QC_CSRRWR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcicsr_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0 }, },
9544 { 19299 /* qc.csrrwri */, RISCV::QC_CSRRWRI, Convert__Reg1_0__UImm51_1__Reg1_2, AMFBS_HasVendorXqcicsr_IsRV32, { MCK_GPR, MCK_UImm5, MCK_GPRNoX0 }, },
9545 { 19310 /* qc.cto */, RISCV::QC_CTO, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9546 { 19317 /* qc.e.addai */, RISCV::QC_E_ADDAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9547 { 19328 /* qc.e.addi */, RISCV::QC_E_ADDI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9548 { 19338 /* qc.e.andai */, RISCV::QC_E_ANDAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9549 { 19349 /* qc.e.andi */, RISCV::QC_E_ANDI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9550 { 19359 /* qc.e.beqi */, RISCV::QC_E_BEQI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9551 { 19369 /* qc.e.bgei */, RISCV::QC_E_BGEI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9552 { 19379 /* qc.e.bgeui */, RISCV::QC_E_BGEUI, Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm16NonZero, MCK_BareSImm13Lsb0 }, },
9553 { 19390 /* qc.e.blti */, RISCV::QC_E_BLTI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9554 { 19400 /* qc.e.bltui */, RISCV::QC_E_BLTUI, Convert__Reg1_0__UImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_UImm16NonZero, MCK_BareSImm13Lsb0 }, },
9555 { 19411 /* qc.e.bnei */, RISCV::QC_E_BNEI, Convert__Reg1_0__SImm16NonZero1_1__BareSImm13Lsb01_2, AMFBS_HasVendorXqcibi_IsRV32, { MCK_GPRNoX0, MCK_SImm16NonZero, MCK_BareSImm13Lsb0 }, },
9556 { 19421 /* qc.e.j */, RISCV::QC_E_J, Convert__BareSImm32Lsb01_0, AMFBS_HasVendorXqcilb_IsRV32, { MCK_BareSImm32Lsb0 }, },
9557 { 19428 /* qc.e.jal */, RISCV::QC_E_JAL, Convert__BareSImm32Lsb01_0, AMFBS_HasVendorXqcilb_IsRV32, { MCK_BareSImm32Lsb0 }, },
9558 { 19437 /* qc.e.lb */, RISCV::PseudoQC_E_LB, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9559 { 19437 /* qc.e.lb */, RISCV::QC_E_LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9560 { 19437 /* qc.e.lb */, RISCV::QC_E_LB, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9561 { 19445 /* qc.e.lbu */, RISCV::PseudoQC_E_LBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9562 { 19445 /* qc.e.lbu */, RISCV::QC_E_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9563 { 19445 /* qc.e.lbu */, RISCV::QC_E_LBU, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9564 { 19454 /* qc.e.lh */, RISCV::PseudoQC_E_LH, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9565 { 19454 /* qc.e.lh */, RISCV::QC_E_LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9566 { 19454 /* qc.e.lh */, RISCV::QC_E_LH, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9567 { 19462 /* qc.e.lhu */, RISCV::PseudoQC_E_LHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9568 { 19462 /* qc.e.lhu */, RISCV::QC_E_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9569 { 19462 /* qc.e.lhu */, RISCV::QC_E_LHU, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9570 { 19471 /* qc.e.li */, RISCV::QC_E_LI, Convert__Reg1_0__BareSImm321_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9571 { 19471 /* qc.e.li */, RISCV::ADDI, Convert__Reg1_0__regX0__BareSymbolQC_E_LI1_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbolQC_E_LI }, },
9572 { 19479 /* qc.e.lw */, RISCV::PseudoQC_E_LW, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol }, },
9573 { 19479 /* qc.e.lw */, RISCV::QC_E_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9574 { 19479 /* qc.e.lw */, RISCV::QC_E_LW, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9575 { 19487 /* qc.e.orai */, RISCV::QC_E_ORAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9576 { 19497 /* qc.e.ori */, RISCV::QC_E_ORI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9577 { 19506 /* qc.e.sb */, RISCV::PseudoQC_E_SB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9578 { 19506 /* qc.e.sb */, RISCV::QC_E_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9579 { 19506 /* qc.e.sb */, RISCV::QC_E_SB, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9580 { 19514 /* qc.e.sh */, RISCV::PseudoQC_E_SH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9581 { 19514 /* qc.e.sh */, RISCV::QC_E_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9582 { 19514 /* qc.e.sh */, RISCV::QC_E_SH, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9583 { 19522 /* qc.e.sw */, RISCV::PseudoQC_E_SW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9584 { 19522 /* qc.e.sw */, RISCV::QC_E_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9585 { 19522 /* qc.e.sw */, RISCV::QC_E_SW, Convert__Reg1_0__Reg1_3__SImm261_1, AMFBS_HasVendorXqcilo_IsRV32, { MCK_GPR, MCK_SImm26, MCK__40_, MCK_GPR, MCK__41_ }, },
9586 { 19530 /* qc.e.xorai */, RISCV::QC_E_XORAI, Convert__Reg1_0__Tie0_1_1__BareSImm321_1, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_BareSImm32 }, },
9587 { 19541 /* qc.e.xori */, RISCV::QC_E_XORI, Convert__Reg1_0__Reg1_1__SImm261_2, AMFBS_HasVendorXqcilia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm26 }, },
9588 { 19551 /* qc.expand2 */, RISCV::QC_EXPAND2, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9589 { 19562 /* qc.expand3 */, RISCV::QC_EXPAND3, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9590 { 19573 /* qc.ext */, RISCV::QC_EXT, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5Plus1, MCK_UImm5 }, },
9591 { 19580 /* qc.extd */, RISCV::QC_EXTD, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_UImm5Plus1, MCK_UImm5 }, },
9592 { 19588 /* qc.extdpr */, RISCV::QC_EXTDPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9593 { 19598 /* qc.extdprh */, RISCV::QC_EXTDPRH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9594 { 19609 /* qc.extdr */, RISCV::QC_EXTDR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9595 { 19618 /* qc.extdu */, RISCV::QC_EXTDU, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_UImm5Plus1, MCK_UImm5 }, },
9596 { 19627 /* qc.extdupr */, RISCV::QC_EXTDUPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9597 { 19638 /* qc.extduprh */, RISCV::QC_EXTDUPRH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9598 { 19650 /* qc.extdur */, RISCV::QC_EXTDUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX31, MCK_GPRNoX0 }, },
9599 { 19660 /* qc.extu */, RISCV::QC_EXTU, Convert__Reg1_0__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5Plus1, MCK_UImm5 }, },
9600 { 19668 /* qc.insb */, RISCV::QC_INSB, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_UImm5Plus1, MCK_UImm5 }, },
9601 { 19676 /* qc.insbh */, RISCV::QC_INSBH, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_UImm5Plus1, MCK_UImm5 }, },
9602 { 19685 /* qc.insbhr */, RISCV::QC_INSBHR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9603 { 19695 /* qc.insbi */, RISCV::QC_INSBI, Convert__Reg1_0__Tie0_1_1__SImm51_1__UImm5Plus11_2__UImm51_3, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_UImm5Plus1, MCK_UImm5 }, },
9604 { 19704 /* qc.insbpr */, RISCV::QC_INSBPR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9605 { 19714 /* qc.insbprh */, RISCV::QC_INSBPRH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9606 { 19725 /* qc.insbr */, RISCV::QC_INSBR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9607 { 19734 /* qc.insbri */, RISCV::QC_INSBRI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm111_2, AMFBS_HasVendorXqcibm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm11 }, },
9608 { 19744 /* qc.inw */, RISCV::QC_INW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9609 { 19744 /* qc.inw */, RISCV::QC_INW, Convert__Reg1_0__Reg1_3__UImm14Lsb001_1, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPRNoX0, MCK_UImm14Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9610 { 19751 /* qc.li */, RISCV::QC_LI, Convert__Reg1_0__SImm20LI1_1, AMFBS_HasVendorXqcili_IsRV32, { MCK_GPRNoX0, MCK_SImm20LI }, },
9611 { 19757 /* qc.lieq */, RISCV::QC_LIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9612 { 19765 /* qc.lieqi */, RISCV::QC_LIEQI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9613 { 19774 /* qc.lige */, RISCV::QC_LIGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9614 { 19782 /* qc.ligei */, RISCV::QC_LIGEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9615 { 19791 /* qc.ligeu */, RISCV::QC_LIGEU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9616 { 19800 /* qc.ligeui */, RISCV::QC_LIGEUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_SImm5 }, },
9617 { 19810 /* qc.lilt */, RISCV::QC_LILT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9618 { 19818 /* qc.lilti */, RISCV::QC_LILTI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9619 { 19827 /* qc.liltu */, RISCV::QC_LILTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9620 { 19836 /* qc.liltui */, RISCV::QC_LILTUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_SImm5 }, },
9621 { 19846 /* qc.line */, RISCV::QC_LINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9622 { 19854 /* qc.linei */, RISCV::QC_LINEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcicli_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9623 { 19863 /* qc.lrb */, RISCV::QC_LRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9624 { 19870 /* qc.lrbu */, RISCV::QC_LRBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9625 { 19878 /* qc.lrh */, RISCV::QC_LRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9626 { 19885 /* qc.lrhu */, RISCV::QC_LRHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9627 { 19893 /* qc.lrw */, RISCV::QC_LRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9628 { 19900 /* qc.lwm */, RISCV::QC_LWM, Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9629 { 19900 /* qc.lwm */, RISCV::QC_LWM, Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9630 { 19907 /* qc.lwmi */, RISCV::QC_LWMI, Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK__40_, MCK_GPR, MCK__41_ }, },
9631 { 19907 /* qc.lwmi */, RISCV::QC_LWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9632 { 19915 /* qc.muliadd */, RISCV::QC_MULIADD, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm12LO1_2, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm12LO }, },
9633 { 19926 /* qc.mveq */, RISCV::QC_MVEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9634 { 19934 /* qc.mveqi */, RISCV::QC_MVEQI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9635 { 19943 /* qc.mvge */, RISCV::QC_MVGE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9636 { 19951 /* qc.mvgei */, RISCV::QC_MVGEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9637 { 19960 /* qc.mvgeu */, RISCV::QC_MVGEU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9638 { 19969 /* qc.mvgeui */, RISCV::QC_MVGEUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_GPRNoX0 }, },
9639 { 19979 /* qc.mvlt */, RISCV::QC_MVLT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9640 { 19987 /* qc.mvlti */, RISCV::QC_MVLTI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9641 { 19996 /* qc.mvltu */, RISCV::QC_MVLTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9642 { 20005 /* qc.mvltui */, RISCV::QC_MVLTUI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5, MCK_GPRNoX0 }, },
9643 { 20015 /* qc.mvne */, RISCV::QC_MVNE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9644 { 20023 /* qc.mvnei */, RISCV::QC_MVNEI, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__Reg1_3, AMFBS_HasVendorXqcicm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0 }, },
9645 { 20032 /* qc.norm */, RISCV::QC_NORM, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9646 { 20040 /* qc.normeu */, RISCV::QC_NORMEU, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9647 { 20050 /* qc.normu */, RISCV::QC_NORMU, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
9648 { 20059 /* qc.outw */, RISCV::QC_OUTW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9649 { 20059 /* qc.outw */, RISCV::QC_OUTW, Convert__Reg1_0__Reg1_3__UImm14Lsb001_1, AMFBS_HasVendorXqciio_IsRV32, { MCK_GPR, MCK_UImm14Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9650 { 20067 /* qc.pcoredump */, RISCV::SLTI, Convert__regX0__regX0__imm_95_1536, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9651 { 20080 /* qc.pexit */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1280, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9652 { 20089 /* qc.ppreg */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_2048, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9653 { 20098 /* qc.ppregs */, RISCV::SLTI, Convert__regX0__regX0__imm_95_1792, AMFBS_HasVendorXqcisim_IsRV32, { }, },
9654 { 20108 /* qc.pputc */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1792, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9655 { 20117 /* qc.pputci */, RISCV::QC_PPUTCI, Convert__UImm81_0, AMFBS_HasVendorXqcisim_IsRV32, { MCK_UImm8 }, },
9656 { 20127 /* qc.pputs */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1536, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9657 { 20136 /* qc.psyscall */, RISCV::SLTI, Convert__regX0__Reg1_0__imm_95__MINUS_1024, AMFBS_HasVendorXqcisim_IsRV32, { MCK_GPR }, },
9658 { 20148 /* qc.psyscalli */, RISCV::SLTI, Convert__regX0__regX0__UImm101_0, AMFBS_HasVendorXqcisim_IsRV32, { MCK_UImm10 }, },
9659 { 20161 /* qc.selecteqi */, RISCV::QC_SELECTEQI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9660 { 20174 /* qc.selectieq */, RISCV::QC_SELECTIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9661 { 20187 /* qc.selectieqi */, RISCV::QC_SELECTIEQI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_SImm5 }, },
9662 { 20201 /* qc.selectiieq */, RISCV::QC_SELECTIIEQ, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9663 { 20215 /* qc.selectiine */, RISCV::QC_SELECTIINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm51_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5, MCK_SImm5 }, },
9664 { 20229 /* qc.selectine */, RISCV::QC_SELECTINE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_SImm5 }, },
9665 { 20242 /* qc.selectinei */, RISCV::QC_SELECTINEI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_SImm5 }, },
9666 { 20256 /* qc.selectnei */, RISCV::QC_SELECTNEI, Convert__Reg1_0__Tie0_1_1__SImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXqcics_IsRV32, { MCK_GPRNoX0, MCK_SImm5, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9667 { 20269 /* qc.setinti */, RISCV::QC_SETINTI, Convert__UImm101_0, AMFBS_HasVendorXqciint_IsRV32, { MCK_UImm10 }, },
9668 { 20280 /* qc.setwm */, RISCV::QC_SETWM, Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9669 { 20280 /* qc.setwm */, RISCV::QC_SETWM, Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_GPRNoX0, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9670 { 20289 /* qc.setwmi */, RISCV::QC_SETWMI, Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_UImm5NonZero, MCK__40_, MCK_GPR, MCK__41_ }, },
9671 { 20289 /* qc.setwmi */, RISCV::QC_SETWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPR, MCK_UImm5NonZero, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9672 { 20299 /* qc.shladd */, RISCV::QC_SHLADD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm5GT31_3, AMFBS_HasVendorXqciac_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm5GT3 }, },
9673 { 20309 /* qc.shlsat */, RISCV::QC_SHLSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9674 { 20319 /* qc.shlusat */, RISCV::QC_SHLUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9675 { 20330 /* qc.srb */, RISCV::QC_SRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9676 { 20337 /* qc.srh */, RISCV::QC_SRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9677 { 20344 /* qc.srw */, RISCV::QC_SRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_HasVendorXqcisls_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPRNoX0, MCK_UImm3 }, },
9678 { 20351 /* qc.subsat */, RISCV::QC_SUBSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9679 { 20361 /* qc.subusat */, RISCV::QC_SUBUSAT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_GPRNoX0 }, },
9680 { 20372 /* qc.swm */, RISCV::QC_SWM, Convert__Reg1_0__Reg1_3__Reg1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK__40_, MCK_GPR, MCK__41_ }, },
9681 { 20372 /* qc.swm */, RISCV::QC_SWM, Convert__Reg1_0__Reg1_4__Reg1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9682 { 20379 /* qc.swmi */, RISCV::QC_SWMI, Convert__Reg1_0__Reg1_3__UImm5NonZero1_1__imm_95_0, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK__40_, MCK_GPR, MCK__41_ }, },
9683 { 20379 /* qc.swmi */, RISCV::QC_SWMI, Convert__Reg1_0__Reg1_4__UImm5NonZero1_1__UImm7Lsb001_2, AMFBS_HasVendorXqcilsm_IsRV32, { MCK_GPRNoX0, MCK_UImm5NonZero, MCK_UImm7Lsb00, MCK__40_, MCK_GPR, MCK__41_ }, },
9684 { 20387 /* qc.sync */, RISCV::QC_SYNC, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9685 { 20395 /* qc.syncr */, RISCV::QC_SYNCR, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9686 { 20404 /* qc.syncwf */, RISCV::QC_SYNCWF, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9687 { 20414 /* qc.syncwl */, RISCV::QC_SYNCWL, Convert__UImm51_0, AMFBS_HasVendorXqcisync_IsRV32, { MCK_UImm5 }, },
9688 { 20424 /* qc.wrap */, RISCV::QC_WRAP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPR, MCK_GPRNoX0 }, },
9689 { 20432 /* qc.wrapi */, RISCV::QC_WRAPI, Convert__Reg1_0__Reg1_1__UImm111_2, AMFBS_HasVendorXqcia_IsRV32, { MCK_GPRNoX0, MCK_GPRNoX0, MCK_UImm11 }, },
9690 { 20441 /* qk.c.lbu */, RISCV::QK_C_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9691 { 20441 /* qk.c.lbu */, RISCV::QK_C_LBU, Convert__Reg1_0__Reg1_3__UImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
9692 { 20450 /* qk.c.lbusp */, RISCV::QK_C_LBUSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9693 { 20450 /* qk.c.lbusp */, RISCV::QK_C_LBUSP, Convert__Reg1_0__Reg1_3__UImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm4, MCK__40_, MCK_SP, MCK__41_ }, },
9694 { 20461 /* qk.c.lhu */, RISCV::QK_C_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9695 { 20461 /* qk.c.lhu */, RISCV::QK_C_LHU, Convert__Reg1_0__Reg1_3__UImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
9696 { 20470 /* qk.c.lhusp */, RISCV::QK_C_LHUSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9697 { 20470 /* qk.c.lhusp */, RISCV::QK_C_LHUSP, Convert__Reg1_0__Reg1_3__UImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
9698 { 20481 /* qk.c.sb */, RISCV::QK_C_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9699 { 20481 /* qk.c.sb */, RISCV::QK_C_SB, Convert__Reg1_0__Reg1_3__UImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
9700 { 20489 /* qk.c.sbsp */, RISCV::QK_C_SBSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9701 { 20489 /* qk.c.sbsp */, RISCV::QK_C_SBSP, Convert__Reg1_0__Reg1_3__UImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm4, MCK__40_, MCK_SP, MCK__41_ }, },
9702 { 20499 /* qk.c.sh */, RISCV::QK_C_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
9703 { 20499 /* qk.c.sh */, RISCV::QK_C_SH, Convert__Reg1_0__Reg1_3__UImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
9704 { 20507 /* qk.c.shsp */, RISCV::QK_C_SHSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
9705 { 20507 /* qk.c.shsp */, RISCV::QK_C_SHSP, Convert__Reg1_0__Reg1_3__UImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
9706 { 20517 /* rdcycle */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3072__regX0, AMFBS_None, { MCK_GPR }, },
9707 { 20525 /* rdcycleh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3200__regX0, AMFBS_IsRV32, { MCK_GPR }, },
9708 { 20534 /* rdinstret */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3074__regX0, AMFBS_None, { MCK_GPR }, },
9709 { 20544 /* rdinstreth */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3202__regX0, AMFBS_IsRV32, { MCK_GPR }, },
9710 { 20555 /* rdtime */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3073__regX0, AMFBS_None, { MCK_GPR }, },
9711 { 20562 /* rdtimeh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3201__regX0, AMFBS_IsRV32, { MCK_GPR }, },
9712 { 20570 /* rem */, RISCV::REM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9713 { 20574 /* remu */, RISCV::REMU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9714 { 20579 /* remuw */, RISCV::REMUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9715 { 20585 /* remw */, RISCV::REMW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9716 { 20590 /* ret */, RISCV::JALR, Convert__regX0__regX1__imm_95_0, AMFBS_None, { }, },
9717 { 20594 /* rev */, RISCV::REV_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR }, },
9718 { 20594 /* rev */, RISCV::REV_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9719 { 20598 /* rev16 */, RISCV::REV16_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR }, },
9720 { 20604 /* rev8 */, RISCV::REV8_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
9721 { 20604 /* rev8 */, RISCV::REV8_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR }, },
9722 { 20609 /* rol */, RISCV::ROL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9723 { 20613 /* rolw */, RISCV::ROLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9724 { 20618 /* ror */, RISCV::ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9725 { 20618 /* ror */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9726 { 20622 /* rori */, RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9727 { 20627 /* roriw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9728 { 20633 /* rorw */, RISCV::RORW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9729 { 20633 /* rorw */, RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9730 { 20638 /* sadd */, RISCV::SADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9731 { 20643 /* saddu */, RISCV::SADDU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9732 { 20649 /* sati */, RISCV::SATI_RV32, Convert__Reg1_0__Reg1_1__UImm5Plus11_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5Plus1 }, },
9733 { 20649 /* sati */, RISCV::SATI_RV64, Convert__Reg1_0__Reg1_1__UImm6Plus11_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6Plus1 }, },
9734 { 20654 /* sb */, RISCV::PseudoSB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9735 { 20654 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9736 { 20654 /* sb */, RISCV::PseudoQCAccessSB, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9737 { 20654 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9738 { 20654 /* sb */, RISCV::PseudoQCAccessSB, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9739 { 20657 /* sb.aqrl */, RISCV::SB_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9740 { 20665 /* sb.rl */, RISCV::SB_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9741 { 20671 /* sc.d */, RISCV::SC_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9742 { 20676 /* sc.d.aq */, RISCV::SC_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9743 { 20684 /* sc.d.aqrl */, RISCV::SC_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9744 { 20694 /* sc.d.rl */, RISCV::SC_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9745 { 20702 /* sc.w */, RISCV::SC_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9746 { 20707 /* sc.w.aq */, RISCV::SC_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9747 { 20715 /* sc.w.aqrl */, RISCV::SC_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9748 { 20725 /* sc.w.rl */, RISCV::SC_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9749 { 20733 /* sctrclr */, RISCV::SCTRCLR, Convert_NoOperands, AMFBS_HasStdExtSmctrOrSsctr, { }, },
9750 { 20741 /* sd */, RISCV::PseudoSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9751 { 20741 /* sd */, RISCV::PseudoSD_RV32, Convert__Reg1_2__GPRPairRV321_0__BareSymbol1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_BareSymbol, MCK_GPR }, },
9752 { 20741 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9753 { 20741 /* sd */, RISCV::SD_RV32, Convert__GPRPairRV321_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK__40_, MCK_GPR, MCK__41_ }, },
9754 { 20741 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9755 { 20741 /* sd */, RISCV::SD_RV32, Convert__GPRPairRV321_0__Reg1_3__SImm12LO1_1, AMFBS_HasStdExtZilsd_IsRV32, { MCK_GPRPairRV32, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9756 { 20744 /* sd.aqrl */, RISCV::SD_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9757 { 20752 /* sd.rl */, RISCV::SD_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9758 { 20758 /* seqz */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__imm_95_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9759 { 20763 /* sext.b */, RISCV::SEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
9760 { 20763 /* sext.b */, RISCV::PseudoSEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9761 { 20770 /* sext.h */, RISCV::SEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
9762 { 20770 /* sext.h */, RISCV::PseudoSEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9763 { 20777 /* sext.w */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
9764 { 20784 /* sf.cdiscard.d.l1 */, RISCV::SF_CDISCARD_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecdiscarddlone, { }, },
9765 { 20784 /* sf.cdiscard.d.l1 */, RISCV::SF_CDISCARD_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecdiscarddlone, { MCK_GPR }, },
9766 { 20801 /* sf.cease */, RISCV::SF_CEASE, Convert_NoOperands, AMFBS_HasVendorXSfcease, { }, },
9767 { 20810 /* sf.cflush.d.l1 */, RISCV::SF_CFLUSH_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecflushdlone, { }, },
9768 { 20810 /* sf.cflush.d.l1 */, RISCV::SF_CFLUSH_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecflushdlone, { MCK_GPR }, },
9769 { 20825 /* sf.mm.e4m3.e4m3 */, RISCV::SF_MM_E4M3_E4M3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9770 { 20841 /* sf.mm.e4m3.e5m2 */, RISCV::SF_MM_E4M3_E5M2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9771 { 20857 /* sf.mm.e5m2.e4m3 */, RISCV::SF_MM_E5M2_E4M3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9772 { 20873 /* sf.mm.e5m2.e5m2 */, RISCV::SF_MM_E5M2_E5M2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8f, { MCK_TRM4, MCK_VR, MCK_VR }, },
9773 { 20889 /* sf.mm.f.f */, RISCV::SF_MM_F_F, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f, { MCK_TRM2, MCK_VR, MCK_VR }, },
9774 { 20899 /* sf.mm.s.s */, RISCV::SF_MM_S_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9775 { 20909 /* sf.mm.s.u */, RISCV::SF_MM_S_U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9776 { 20919 /* sf.mm.u.s */, RISCV::SF_MM_U_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9777 { 20929 /* sf.mm.u.u */, RISCV::SF_MM_U_U, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfmm32a8i, { MCK_TRM4, MCK_VR, MCK_VR }, },
9778 { 20939 /* sf.vc.fv */, RISCV::SF_VC_FV, Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_UImm5, MCK_VR, MCK_FPR32 }, },
9779 { 20948 /* sf.vc.fvv */, RISCV::SF_VC_FVV, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9780 { 20958 /* sf.vc.fvw */, RISCV::SF_VC_FVW, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9781 { 20968 /* sf.vc.i */, RISCV::SF_VC_I, Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_SImm5 }, },
9782 { 20976 /* sf.vc.iv */, RISCV::SF_VC_IV, Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_SImm5 }, },
9783 { 20985 /* sf.vc.ivv */, RISCV::SF_VC_IVV, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9784 { 20995 /* sf.vc.ivw */, RISCV::SF_VC_IVW, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9785 { 21005 /* sf.vc.v.fv */, RISCV::SF_VC_V_FV, Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9786 { 21016 /* sf.vc.v.fvv */, RISCV::SF_VC_V_FVV, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9787 { 21028 /* sf.vc.v.fvw */, RISCV::SF_VC_V_FVW, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VR, MCK_VR, MCK_FPR32 }, },
9788 { 21040 /* sf.vc.v.i */, RISCV::SF_VC_V_I, Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_SImm5 }, },
9789 { 21050 /* sf.vc.v.iv */, RISCV::SF_VC_V_IV, Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9790 { 21061 /* sf.vc.v.ivv */, RISCV::SF_VC_V_IVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9791 { 21073 /* sf.vc.v.ivw */, RISCV::SF_VC_V_IVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_SImm5 }, },
9792 { 21085 /* sf.vc.v.vv */, RISCV::SF_VC_V_VV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9793 { 21096 /* sf.vc.v.vvv */, RISCV::SF_VC_V_VVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9794 { 21108 /* sf.vc.v.vvw */, RISCV::SF_VC_V_VVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9795 { 21120 /* sf.vc.v.x */, RISCV::SF_VC_V_X, Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_GPR }, },
9796 { 21130 /* sf.vc.v.xv */, RISCV::SF_VC_V_XV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9797 { 21141 /* sf.vc.v.xvv */, RISCV::SF_VC_V_XVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9798 { 21153 /* sf.vc.v.xvw */, RISCV::SF_VC_V_XVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9799 { 21165 /* sf.vc.vv */, RISCV::SF_VC_VV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_VR }, },
9800 { 21174 /* sf.vc.vvv */, RISCV::SF_VC_VVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9801 { 21184 /* sf.vc.vvw */, RISCV::SF_VC_VVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_VR }, },
9802 { 21194 /* sf.vc.x */, RISCV::SF_VC_X, Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_GPR }, },
9803 { 21202 /* sf.vc.xv */, RISCV::SF_VC_XV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VR, MCK_GPR }, },
9804 { 21211 /* sf.vc.xvv */, RISCV::SF_VC_XVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9805 { 21221 /* sf.vc.xvw */, RISCV::SF_VC_XVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VR, MCK_VR, MCK_GPR }, },
9806 { 21231 /* sf.vfexp.v */, RISCV::SF_VFEXP_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXSfvfexpAny, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9807 { 21242 /* sf.vfexpa.v */, RISCV::SF_VFEXPA_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVendorXSfvfexpa, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
9808 { 21254 /* sf.vfnrclip.x.f.qf */, RISCV::SF_VFNRCLIP_X_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9809 { 21273 /* sf.vfnrclip.xu.f.qf */, RISCV::SF_VFNRCLIP_XU_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
9810 { 21293 /* sf.vfwmacc.4x4x4 */, RISCV::SF_VFWMACC_4x4x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvfwmaccqqq, { MCK_VR, MCK_VR, MCK_VR }, },
9811 { 21310 /* sf.vlte16 */, RISCV::SF_VLTE16, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9812 { 21320 /* sf.vlte32 */, RISCV::SF_VLTE32, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9813 { 21330 /* sf.vlte64 */, RISCV::SF_VLTE64, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9814 { 21340 /* sf.vlte8 */, RISCV::SF_VLTE8, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9815 { 21349 /* sf.vqmacc.2x8x2 */, RISCV::SF_VQMACC_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9816 { 21365 /* sf.vqmacc.4x8x4 */, RISCV::SF_VQMACC_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9817 { 21381 /* sf.vqmaccsu.2x8x2 */, RISCV::SF_VQMACCSU_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9818 { 21399 /* sf.vqmaccsu.4x8x4 */, RISCV::SF_VQMACCSU_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9819 { 21417 /* sf.vqmaccu.2x8x2 */, RISCV::SF_VQMACCU_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9820 { 21434 /* sf.vqmaccu.4x8x4 */, RISCV::SF_VQMACCU_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9821 { 21451 /* sf.vqmaccus.2x8x2 */, RISCV::SF_VQMACCUS_2x8x2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VR, MCK_VR, MCK_VR }, },
9822 { 21469 /* sf.vqmaccus.4x8x4 */, RISCV::SF_VQMACCUS_4x8x4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VR, MCK_VR, MCK_VR }, },
9823 { 21487 /* sf.vsettk */, RISCV::SF_VSETTK, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
9824 { 21497 /* sf.vsettm */, RISCV::SF_VSETTM, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
9825 { 21507 /* sf.vsettn */, RISCV::SF_VSETTN, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR }, },
9826 { 21517 /* sf.vsettnt */, RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__XSfmmVType1_2, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_GPR, MCK_XSfmmVType }, },
9827 { 21528 /* sf.vste16 */, RISCV::SF_VSTE16, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9828 { 21538 /* sf.vste32 */, RISCV::SF_VSTE32, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9829 { 21548 /* sf.vste64 */, RISCV::SF_VSTE64, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9830 { 21558 /* sf.vste8 */, RISCV::SF_VSTE8, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9831 { 21567 /* sf.vtdiscard */, RISCV::SF_VTDISCARD, Convert_NoOperands, AMFBS_HasVendorXSfmmbase, { }, },
9832 { 21580 /* sf.vtmv.t.v */, RISCV::SF_VTMV_T_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_GPR, MCK_VR }, },
9833 { 21592 /* sf.vtmv.v.t */, RISCV::SF_VTMV_V_T, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXSfmmbase, { MCK_VR, MCK_GPR }, },
9834 { 21604 /* sf.vtzero.t */, RISCV::SF_VTZERO_T, Convert__Reg1_0, AMFBS_HasVendorXSfmmbase, { MCK_TR }, },
9835 { 21616 /* sfence.inval.ir */, RISCV::SFENCE_INVAL_IR, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
9836 { 21632 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__regX0__regX0, AMFBS_None, { }, },
9837 { 21632 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
9838 { 21632 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9839 { 21643 /* sfence.w.inval */, RISCV::SFENCE_W_INVAL, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
9840 { 21658 /* sgt */, RISCV::SLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9841 { 21662 /* sgtu */, RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9842 { 21667 /* sgtz */, RISCV::SLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9843 { 21672 /* sh */, RISCV::PseudoSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9844 { 21672 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9845 { 21672 /* sh */, RISCV::PseudoQCAccessSH, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9846 { 21672 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9847 { 21672 /* sh */, RISCV::PseudoQCAccessSH, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9848 { 21675 /* sh.aqrl */, RISCV::SH_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9849 { 21683 /* sh.rl */, RISCV::SH_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9850 { 21689 /* sh1add */, RISCV::SH1ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9851 { 21696 /* sh1add.uw */, RISCV::SH1ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9852 { 21706 /* sh2add */, RISCV::SH2ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9853 { 21713 /* sh2add.uw */, RISCV::SH2ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9854 { 21723 /* sh3add */, RISCV::SH3ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9855 { 21730 /* sh3add.uw */, RISCV::SH3ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9856 { 21740 /* sha */, RISCV::SHA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9857 { 21744 /* sha256sig0 */, RISCV::SHA256SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9858 { 21755 /* sha256sig1 */, RISCV::SHA256SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9859 { 21766 /* sha256sum0 */, RISCV::SHA256SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9860 { 21777 /* sha256sum1 */, RISCV::SHA256SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
9861 { 21788 /* sha512sig0 */, RISCV::SHA512SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9862 { 21799 /* sha512sig0h */, RISCV::SHA512SIG0H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9863 { 21811 /* sha512sig0l */, RISCV::SHA512SIG0L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9864 { 21823 /* sha512sig1 */, RISCV::SHA512SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9865 { 21834 /* sha512sig1h */, RISCV::SHA512SIG1H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9866 { 21846 /* sha512sig1l */, RISCV::SHA512SIG1L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9867 { 21858 /* sha512sum0 */, RISCV::SHA512SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9868 { 21869 /* sha512sum0r */, RISCV::SHA512SUM0R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9869 { 21881 /* sha512sum1 */, RISCV::SHA512SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
9870 { 21892 /* sha512sum1r */, RISCV::SHA512SUM1R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9871 { 21904 /* shar */, RISCV::SHAR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9872 { 21909 /* shl */, RISCV::SHL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9873 { 21913 /* shlr */, RISCV::SHLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9874 { 21918 /* sinval.vma */, RISCV::SINVAL_VMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
9875 { 21929 /* sll */, RISCV::SLL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9876 { 21929 /* sll */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9877 { 21933 /* slli */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9878 { 21938 /* slli.uw */, RISCV::SLLI_UW, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9879 { 21946 /* slliw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9880 { 21952 /* sllw */, RISCV::SLLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9881 { 21952 /* sllw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9882 { 21957 /* slt */, RISCV::SLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9883 { 21957 /* slt */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9884 { 21961 /* slti */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9885 { 21966 /* sltiu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9886 { 21972 /* sltu */, RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9887 { 21972 /* sltu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
9888 { 21977 /* sltz */, RISCV::SLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9889 { 21982 /* slx */, RISCV::SLX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9890 { 21986 /* sm3p0 */, RISCV::SM3P0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
9891 { 21992 /* sm3p1 */, RISCV::SM3P1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
9892 { 21998 /* sm4ed */, RISCV::SM4ED, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9893 { 22004 /* sm4ks */, RISCV::SM4KS, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9894 { 22010 /* smt.vmadot */, RISCV::SMT_VMADOT, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
9895 { 22021 /* smt.vmadot1 */, RISCV::SMT_VMADOT1, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9896 { 22033 /* smt.vmadot1su */, RISCV::SMT_VMADOT1SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9897 { 22047 /* smt.vmadot1u */, RISCV::SMT_VMADOT1U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9898 { 22060 /* smt.vmadot1us */, RISCV::SMT_VMADOT1US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9899 { 22074 /* smt.vmadot2 */, RISCV::SMT_VMADOT2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9900 { 22086 /* smt.vmadot2su */, RISCV::SMT_VMADOT2SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9901 { 22100 /* smt.vmadot2u */, RISCV::SMT_VMADOT2U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9902 { 22113 /* smt.vmadot2us */, RISCV::SMT_VMADOT2US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9903 { 22127 /* smt.vmadot3 */, RISCV::SMT_VMADOT3, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9904 { 22139 /* smt.vmadot3su */, RISCV::SMT_VMADOT3SU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9905 { 22153 /* smt.vmadot3u */, RISCV::SMT_VMADOT3U, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9906 { 22166 /* smt.vmadot3us */, RISCV::SMT_VMADOT3US, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VRM2, MCK_VR }, },
9907 { 22180 /* smt.vmadotsu */, RISCV::SMT_VMADOTSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
9908 { 22193 /* smt.vmadotu */, RISCV::SMT_VMADOTU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
9909 { 22205 /* smt.vmadotus */, RISCV::SMT_VMADOTUS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXSMTVDot_IsRV64, { MCK_VRM2, MCK_VR, MCK_VR }, },
9910 { 22218 /* snez */, RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
9911 { 22223 /* sra */, RISCV::SRA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9912 { 22223 /* sra */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9913 { 22227 /* srai */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9914 { 22232 /* sraiw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9915 { 22238 /* srari */, RISCV::SRARI_RV32, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9916 { 22238 /* srari */, RISCV::SRARI_RV64, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
9917 { 22244 /* sraw */, RISCV::SRAW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9918 { 22244 /* sraw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9919 { 22249 /* sret */, RISCV::SRET, Convert_NoOperands, AMFBS_None, { }, },
9920 { 22254 /* srl */, RISCV::SRL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9921 { 22254 /* srl */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9922 { 22258 /* srli */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
9923 { 22263 /* srliw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9924 { 22269 /* srliy */, RISCV::SRLIY, Convert__Reg1_0__Reg1_1__UImm7EqXLen1_2, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR, MCK_UImm7EqXLen }, },
9925 { 22275 /* srlw */, RISCV::SRLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9926 { 22275 /* srlw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9927 { 22280 /* srx */, RISCV::SRX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9928 { 22284 /* ssamoswap.d */, RISCV::SSAMOSWAP_D, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9929 { 22296 /* ssamoswap.d.aq */, RISCV::SSAMOSWAP_D_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9930 { 22311 /* ssamoswap.d.aqrl */, RISCV::SSAMOSWAP_D_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9931 { 22328 /* ssamoswap.d.rl */, RISCV::SSAMOSWAP_D_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9932 { 22343 /* ssamoswap.w */, RISCV::SSAMOSWAP_W, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9933 { 22355 /* ssamoswap.w.aq */, RISCV::SSAMOSWAP_W_AQ, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9934 { 22370 /* ssamoswap.w.aqrl */, RISCV::SSAMOSWAP_W_AQRL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9935 { 22387 /* ssamoswap.w.rl */, RISCV::SSAMOSWAP_W_RL, Convert__Reg1_0__Reg1_1__ZeroOffsetMemOpOperand1_2, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9936 { 22402 /* ssh1sadd */, RISCV::SSH1SADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9937 { 22411 /* ssha */, RISCV::SSHA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9938 { 22416 /* sshar */, RISCV::SSHAR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9939 { 22422 /* sshl */, RISCV::SSHL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9940 { 22427 /* sshlr */, RISCV::SSHLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9941 { 22433 /* sslai */, RISCV::SSLAI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
9942 { 22439 /* sspopchk */, RISCV::SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRX1X5 }, },
9943 { 22448 /* sspush */, RISCV::SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRX1X5 }, },
9944 { 22455 /* ssrdp */, RISCV::SSRDP, Convert__Reg1_0, AMFBS_HasStdExtZimop, { MCK_GPRNoX0 }, },
9945 { 22461 /* ssub */, RISCV::SSUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9946 { 22466 /* ssubu */, RISCV::SSUBU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9947 { 22472 /* sub */, RISCV::SUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9948 { 22476 /* subd */, RISCV::SUBD, Convert__GPRPairRV321_0__GPRPairRV321_1__GPRPairRV321_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_GPRPairRV32 }, },
9949 { 22481 /* subw */, RISCV::SUBW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
9950 { 22486 /* sw */, RISCV::PseudoSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
9951 { 22486 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
9952 { 22486 /* sw */, RISCV::PseudoQCAccessSW, Convert__Reg1_0__Reg1_2__imm_95_0__QCAccessSymbol1_4, AMFBS_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9953 { 22486 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_3__SImm12LO1_1, AMFBS_None, { MCK_GPR, MCK_SImm12LO, MCK__40_, MCK_GPR, MCK__41_ }, },
9954 { 22486 /* sw */, RISCV::PseudoQCAccessSW, Convert__Reg1_0__Reg1_3__SImm121_1__QCAccessSymbol1_5, AMFBS_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_QCAccessSymbol }, },
9955 { 22489 /* sw.aqrl */, RISCV::SW_AQRL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9956 { 22497 /* sw.rl */, RISCV::SW_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
9957 { 22503 /* tail */, RISCV::PseudoTAIL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
9958 { 22508 /* th.addsl */, RISCV::TH_ADDSL, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadBa, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9959 { 22517 /* th.dcache.call */, RISCV::TH_DCACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9960 { 22532 /* th.dcache.ciall */, RISCV::TH_DCACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9961 { 22548 /* th.dcache.cipa */, RISCV::TH_DCACHE_CIPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9962 { 22563 /* th.dcache.cisw */, RISCV::TH_DCACHE_CISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9963 { 22578 /* th.dcache.civa */, RISCV::TH_DCACHE_CIVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9964 { 22593 /* th.dcache.cpa */, RISCV::TH_DCACHE_CPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9965 { 22607 /* th.dcache.cpal1 */, RISCV::TH_DCACHE_CPAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9966 { 22623 /* th.dcache.csw */, RISCV::TH_DCACHE_CSW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9967 { 22637 /* th.dcache.cva */, RISCV::TH_DCACHE_CVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9968 { 22651 /* th.dcache.cval1 */, RISCV::TH_DCACHE_CVAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9969 { 22667 /* th.dcache.iall */, RISCV::TH_DCACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9970 { 22682 /* th.dcache.ipa */, RISCV::TH_DCACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9971 { 22696 /* th.dcache.isw */, RISCV::TH_DCACHE_ISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9972 { 22710 /* th.dcache.iva */, RISCV::TH_DCACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9973 { 22724 /* th.ext */, RISCV::TH_EXT, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
9974 { 22731 /* th.extu */, RISCV::TH_EXTU, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
9975 { 22739 /* th.ff0 */, RISCV::TH_FF0, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
9976 { 22746 /* th.ff1 */, RISCV::TH_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
9977 { 22753 /* th.flrd */, RISCV::TH_FLRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9978 { 22761 /* th.flrw */, RISCV::TH_FLRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9979 { 22769 /* th.flurd */, RISCV::TH_FLURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9980 { 22778 /* th.flurw */, RISCV::TH_FLURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9981 { 22787 /* th.fsrd */, RISCV::TH_FSRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9982 { 22795 /* th.fsrw */, RISCV::TH_FSRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9983 { 22803 /* th.fsurd */, RISCV::TH_FSURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9984 { 22812 /* th.fsurw */, RISCV::TH_FSURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
9985 { 22821 /* th.icache.iall */, RISCV::TH_ICACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9986 { 22836 /* th.icache.ialls */, RISCV::TH_ICACHE_IALLS, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9987 { 22852 /* th.icache.ipa */, RISCV::TH_ICACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9988 { 22866 /* th.icache.iva */, RISCV::TH_ICACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
9989 { 22880 /* th.l2cache.call */, RISCV::TH_L2CACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9990 { 22896 /* th.l2cache.ciall */, RISCV::TH_L2CACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9991 { 22913 /* th.l2cache.iall */, RISCV::TH_L2CACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
9992 { 22929 /* th.lbia */, RISCV::TH_LBIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9993 { 22937 /* th.lbib */, RISCV::TH_LBIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9994 { 22945 /* th.lbuia */, RISCV::TH_LBUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9995 { 22954 /* th.lbuib */, RISCV::TH_LBUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9996 { 22963 /* th.ldd */, RISCV::TH_LDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmFour }, },
9997 { 22970 /* th.ldia */, RISCV::TH_LDIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9998 { 22978 /* th.ldib */, RISCV::TH_LDIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
9999 { 22986 /* th.lhia */, RISCV::TH_LHIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10000 { 22994 /* th.lhib */, RISCV::TH_LHIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10001 { 23002 /* th.lhuia */, RISCV::TH_LHUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10002 { 23011 /* th.lhuib */, RISCV::TH_LHUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10003 { 23020 /* th.lrb */, RISCV::TH_LRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10004 { 23027 /* th.lrbu */, RISCV::TH_LRBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10005 { 23035 /* th.lrd */, RISCV::TH_LRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10006 { 23042 /* th.lrh */, RISCV::TH_LRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10007 { 23049 /* th.lrhu */, RISCV::TH_LRHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10008 { 23057 /* th.lrw */, RISCV::TH_LRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10009 { 23064 /* th.lrwu */, RISCV::TH_LRWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10010 { 23072 /* th.lurb */, RISCV::TH_LURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10011 { 23080 /* th.lurbu */, RISCV::TH_LURBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10012 { 23089 /* th.lurd */, RISCV::TH_LURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10013 { 23097 /* th.lurh */, RISCV::TH_LURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10014 { 23105 /* th.lurhu */, RISCV::TH_LURHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10015 { 23114 /* th.lurw */, RISCV::TH_LURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10016 { 23122 /* th.lurwu */, RISCV::TH_LURWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10017 { 23131 /* th.lwd */, RISCV::TH_LWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
10018 { 23138 /* th.lwia */, RISCV::TH_LWIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10019 { 23146 /* th.lwib */, RISCV::TH_LWIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10020 { 23154 /* th.lwud */, RISCV::TH_LWUD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
10021 { 23162 /* th.lwuia */, RISCV::TH_LWUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10022 { 23171 /* th.lwuib */, RISCV::TH_LWUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10023 { 23180 /* th.mula */, RISCV::TH_MULA, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10024 { 23188 /* th.mulah */, RISCV::TH_MULAH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10025 { 23197 /* th.mulaw */, RISCV::TH_MULAW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10026 { 23206 /* th.muls */, RISCV::TH_MULS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10027 { 23214 /* th.mulsh */, RISCV::TH_MULSH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10028 { 23223 /* th.mulsw */, RISCV::TH_MULSW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10029 { 23232 /* th.mveqz */, RISCV::TH_MVEQZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10030 { 23241 /* th.mvnez */, RISCV::TH_MVNEZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10031 { 23250 /* th.rev */, RISCV::TH_REV, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10032 { 23257 /* th.revw */, RISCV::TH_REVW, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR }, },
10033 { 23265 /* th.sbia */, RISCV::TH_SBIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10034 { 23273 /* th.sbib */, RISCV::TH_SBIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10035 { 23281 /* th.sdd */, RISCV::TH_SDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmFour1_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmFour }, },
10036 { 23288 /* th.sdia */, RISCV::TH_SDIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10037 { 23296 /* th.sdib */, RISCV::TH_SDIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10038 { 23304 /* th.sfence.vmas */, RISCV::TH_SFENCE_VMAS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadSync, { MCK_GPR, MCK_GPR }, },
10039 { 23319 /* th.shia */, RISCV::TH_SHIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10040 { 23327 /* th.shib */, RISCV::TH_SHIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10041 { 23335 /* th.srb */, RISCV::TH_SRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10042 { 23342 /* th.srd */, RISCV::TH_SRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10043 { 23349 /* th.srh */, RISCV::TH_SRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10044 { 23356 /* th.srri */, RISCV::TH_SRRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10045 { 23364 /* th.srriw */, RISCV::TH_SRRIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10046 { 23373 /* th.srw */, RISCV::TH_SRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10047 { 23380 /* th.surb */, RISCV::TH_SURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10048 { 23388 /* th.surd */, RISCV::TH_SURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10049 { 23396 /* th.surh */, RISCV::TH_SURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10050 { 23404 /* th.surw */, RISCV::TH_SURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
10051 { 23412 /* th.swd */, RISCV::TH_SWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__ImmThree1_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_ImmThree }, },
10052 { 23419 /* th.swia */, RISCV::TH_SWIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10053 { 23427 /* th.swib */, RISCV::TH_SWIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
10054 { 23435 /* th.sync */, RISCV::TH_SYNC, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10055 { 23443 /* th.sync.i */, RISCV::TH_SYNC_I, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10056 { 23453 /* th.sync.is */, RISCV::TH_SYNC_IS, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10057 { 23464 /* th.sync.s */, RISCV::TH_SYNC_S, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
10058 { 23474 /* th.tst */, RISCV::TH_TST, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
10059 { 23481 /* th.tstnbz */, RISCV::TH_TSTNBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
10060 { 23491 /* th.vmaqa.vv */, RISCV::TH_VMAQA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10061 { 23503 /* th.vmaqa.vx */, RISCV::TH_VMAQA_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10062 { 23515 /* th.vmaqasu.vv */, RISCV::TH_VMAQASU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10063 { 23529 /* th.vmaqasu.vx */, RISCV::TH_VMAQASU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10064 { 23543 /* th.vmaqau.vv */, RISCV::TH_VMAQAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10065 { 23556 /* th.vmaqau.vx */, RISCV::TH_VMAQAU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10066 { 23569 /* th.vmaqaus.vx */, RISCV::TH_VMAQAUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10067 { 23583 /* unimp */, RISCV::UNIMP, Convert_NoOperands, AMFBS_None, { }, },
10068 { 23589 /* unzip */, RISCV::UNZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
10069 { 23595 /* unzip16hp */, RISCV::UNZIP16HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10070 { 23605 /* unzip16p */, RISCV::UNZIP16P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10071 { 23614 /* unzip8hp */, RISCV::UNZIP8HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10072 { 23623 /* unzip8p */, RISCV::UNZIP8P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10073 { 23631 /* usati */, RISCV::USATI_RV32, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
10074 { 23631 /* usati */, RISCV::USATI_RV64, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
10075 { 23637 /* v8wmmacc.vv */, RISCV::V8WMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10076 { 23649 /* vaadd.vv */, RISCV::VAADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10077 { 23658 /* vaadd.vx */, RISCV::VAADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10078 { 23667 /* vaaddu.vv */, RISCV::VAADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10079 { 23677 /* vaaddu.vx */, RISCV::VAADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10080 { 23687 /* vabd.vv */, RISCV::VABD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10081 { 23695 /* vabdu.vv */, RISCV::VABDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10082 { 23704 /* vabs.v */, RISCV::VABS_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10083 { 23711 /* vadc.vim */, RISCV::VADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
10084 { 23720 /* vadc.vvm */, RISCV::VADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10085 { 23729 /* vadc.vxm */, RISCV::VADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10086 { 23738 /* vadd.vi */, RISCV::VADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10087 { 23746 /* vadd.vv */, RISCV::VADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10088 { 23754 /* vadd.vx */, RISCV::VADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10089 { 23762 /* vaesdf.vs */, RISCV::VAESDF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10090 { 23772 /* vaesdf.vv */, RISCV::VAESDF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10091 { 23782 /* vaesdm.vs */, RISCV::VAESDM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10092 { 23792 /* vaesdm.vv */, RISCV::VAESDM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10093 { 23802 /* vaesef.vs */, RISCV::VAESEF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10094 { 23812 /* vaesef.vv */, RISCV::VAESEF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10095 { 23822 /* vaesem.vs */, RISCV::VAESEM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10096 { 23832 /* vaesem.vv */, RISCV::VAESEM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10097 { 23842 /* vaeskf1.vi */, RISCV::VAESKF1_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10098 { 23853 /* vaeskf2.vi */, RISCV::VAESKF2_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10099 { 23864 /* vaesz.vs */, RISCV::VAESZ_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VR, MCK_VR }, },
10100 { 23873 /* vand.vi */, RISCV::VAND_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10101 { 23881 /* vand.vv */, RISCV::VAND_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10102 { 23889 /* vand.vx */, RISCV::VAND_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10103 { 23897 /* vandn.vv */, RISCV::VANDN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10104 { 23906 /* vandn.vx */, RISCV::VANDN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10105 { 23915 /* vasub.vv */, RISCV::VASUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10106 { 23924 /* vasub.vx */, RISCV::VASUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10107 { 23933 /* vasubu.vv */, RISCV::VASUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10108 { 23943 /* vasubu.vx */, RISCV::VASUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10109 { 23953 /* vbrev.v */, RISCV::VBREV_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10110 { 23961 /* vbrev8.v */, RISCV::VBREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10111 { 23970 /* vclmul.vv */, RISCV::VCLMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10112 { 23980 /* vclmul.vx */, RISCV::VCLMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10113 { 23990 /* vclmulh.vv */, RISCV::VCLMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10114 { 24001 /* vclmulh.vx */, RISCV::VCLMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10115 { 24012 /* vclz.v */, RISCV::VCLZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10116 { 24019 /* vcompress.vm */, RISCV::VCOMPRESS_VM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10117 { 24032 /* vcpop.m */, RISCV::VCPOP_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10118 { 24040 /* vcpop.v */, RISCV::VCPOP_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10119 { 24048 /* vctz.v */, RISCV::VCTZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10120 { 24055 /* vdiv.vv */, RISCV::VDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10121 { 24063 /* vdiv.vx */, RISCV::VDIV_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10122 { 24071 /* vdivu.vv */, RISCV::VDIVU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10123 { 24080 /* vdivu.vx */, RISCV::VDIVU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10124 { 24089 /* vdot4a.vv */, RISCV::VDOT4A_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10125 { 24099 /* vdot4a.vx */, RISCV::VDOT4A_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10126 { 24109 /* vdot4asu.vv */, RISCV::VDOT4ASU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10127 { 24121 /* vdot4asu.vx */, RISCV::VDOT4ASU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10128 { 24133 /* vdot4au.vv */, RISCV::VDOT4AU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10129 { 24144 /* vdot4au.vx */, RISCV::VDOT4AU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10130 { 24155 /* vdot4aus.vx */, RISCV::VDOT4AUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvdot4a8i, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10131 { 24167 /* vf8wimmacc.vv */, RISCV::VF8WIMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10132 { 24181 /* vf8wmmacc.vv */, RISCV::VF8WMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10133 { 24181 /* vf8wmmacc.vv */, RISCV::VF8WMMACC_VV_SCALE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10134 { 24194 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR }, },
10135 { 24194 /* vfabs.v */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10136 { 24202 /* vfadd.vf */, RISCV::VFADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10137 { 24211 /* vfadd.vv */, RISCV::VFADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10138 { 24220 /* vfbdota.vv */, RISCV::VFBDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfbdota32f, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10139 { 24231 /* vfclass.v */, RISCV::VFCLASS_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10140 { 24241 /* vfcvt.f.x.v */, RISCV::VFCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10141 { 24253 /* vfcvt.f.xu.v */, RISCV::VFCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10142 { 24266 /* vfcvt.rtz.x.f.v */, RISCV::VFCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10143 { 24282 /* vfcvt.rtz.xu.f.v */, RISCV::VFCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10144 { 24299 /* vfcvt.x.f.v */, RISCV::VFCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10145 { 24311 /* vfcvt.xu.f.v */, RISCV::VFCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10146 { 24324 /* vfdiv.vf */, RISCV::VFDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10147 { 24333 /* vfdiv.vv */, RISCV::VFDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10148 { 24342 /* vfirst.m */, RISCV::VFIRST_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10149 { 24351 /* vfmacc.vf */, RISCV::VFMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10150 { 24361 /* vfmacc.vv */, RISCV::VFMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10151 { 24371 /* vfmadd.vf */, RISCV::VFMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10152 { 24381 /* vfmadd.vv */, RISCV::VFMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10153 { 24391 /* vfmax.vf */, RISCV::VFMAX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10154 { 24400 /* vfmax.vv */, RISCV::VFMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10155 { 24409 /* vfmerge.vfm */, RISCV::VFMERGE_VFM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskCarryInRegOpOperand }, },
10156 { 24421 /* vfmin.vf */, RISCV::VFMIN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10157 { 24430 /* vfmin.vv */, RISCV::VFMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10158 { 24439 /* vfmmacc.vv */, RISCV::VFMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10159 { 24450 /* vfmsac.vf */, RISCV::VFMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10160 { 24460 /* vfmsac.vv */, RISCV::VFMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10161 { 24470 /* vfmsub.vf */, RISCV::VFMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10162 { 24480 /* vfmsub.vv */, RISCV::VFMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10163 { 24490 /* vfmul.vf */, RISCV::VFMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10164 { 24499 /* vfmul.vv */, RISCV::VFMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10165 { 24508 /* vfmv.f.s */, RISCV::VFMV_F_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_FPR32, MCK_VR }, },
10166 { 24517 /* vfmv.s.f */, RISCV::VFMV_S_F, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32 }, },
10167 { 24526 /* vfmv.v.f */, RISCV::VFMV_V_F, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32 }, },
10168 { 24535 /* vfncvt.f.f.q */, RISCV::VFNCVT_F_F_Q, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10169 { 24548 /* vfncvt.f.f.w */, RISCV::VFNCVT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10170 { 24561 /* vfncvt.f.x.w */, RISCV::VFNCVT_F_X_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10171 { 24574 /* vfncvt.f.xu.w */, RISCV::VFNCVT_F_XU_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10172 { 24588 /* vfncvt.rod.f.f.w */, RISCV::VFNCVT_ROD_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10173 { 24605 /* vfncvt.rtz.x.f.w */, RISCV::VFNCVT_RTZ_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10174 { 24622 /* vfncvt.rtz.xu.f.w */, RISCV::VFNCVT_RTZ_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10175 { 24640 /* vfncvt.sat.f.f.q */, RISCV::VFNCVT_SAT_F_F_Q, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10176 { 24657 /* vfncvt.x.f.w */, RISCV::VFNCVT_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10177 { 24670 /* vfncvt.xu.f.w */, RISCV::VFNCVT_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10178 { 24684 /* vfncvtbf16.f.f.w */, RISCV::VFNCVTBF16_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfminOrZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10179 { 24701 /* vfncvtbf16.sat.f.f.w */, RISCV::VFNCVTBF16_SAT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10180 { 24722 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR }, },
10181 { 24722 /* vfneg.v */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10182 { 24730 /* vfnmacc.vf */, RISCV::VFNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10183 { 24741 /* vfnmacc.vv */, RISCV::VFNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10184 { 24752 /* vfnmadd.vf */, RISCV::VFNMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10185 { 24763 /* vfnmadd.vv */, RISCV::VFNMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10186 { 24774 /* vfnmsac.vf */, RISCV::VFNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10187 { 24785 /* vfnmsac.vv */, RISCV::VFNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10188 { 24796 /* vfnmsub.vf */, RISCV::VFNMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10189 { 24807 /* vfnmsub.vv */, RISCV::VFNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10190 { 24818 /* vfqimmacc.vv */, RISCV::VFQIMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10191 { 24831 /* vfqmmacc.vv */, RISCV::VFQMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10192 { 24831 /* vfqmmacc.vv */, RISCV::VFQMMACC_VV_SCALE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10193 { 24843 /* vfqwbdota.alt.vv */, RISCV::VFQWBDOTA_ALT_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfqwbdota8f, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10194 { 24860 /* vfqwbdota.vv */, RISCV::VFQWBDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfqwbdota8f, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10195 { 24873 /* vfqwdota.alt.vv */, RISCV::VFQWDOTA_ALT_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfqwdota8f, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10196 { 24889 /* vfqwdota.vv */, RISCV::VFQWDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfqwdota8f, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10197 { 24901 /* vfrdiv.vf */, RISCV::VFRDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10198 { 24911 /* vfrec7.v */, RISCV::VFREC7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10199 { 24920 /* vfredmax.vs */, RISCV::VFREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10200 { 24932 /* vfredmin.vs */, RISCV::VFREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10201 { 24944 /* vfredosum.vs */, RISCV::VFREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10202 { 24957 /* vfredusum.vs */, RISCV::VFREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10203 { 24970 /* vfrsqrt7.v */, RISCV::VFRSQRT7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10204 { 24981 /* vfrsub.vf */, RISCV::VFRSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10205 { 24991 /* vfsgnj.vf */, RISCV::VFSGNJ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10206 { 25001 /* vfsgnj.vv */, RISCV::VFSGNJ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10207 { 25011 /* vfsgnjn.vf */, RISCV::VFSGNJN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10208 { 25022 /* vfsgnjn.vv */, RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10209 { 25033 /* vfsgnjx.vf */, RISCV::VFSGNJX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10210 { 25044 /* vfsgnjx.vv */, RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10211 { 25055 /* vfslide1down.vf */, RISCV::VFSLIDE1DOWN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10212 { 25071 /* vfslide1up.vf */, RISCV::VFSLIDE1UP_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10213 { 25085 /* vfsqrt.v */, RISCV::VFSQRT_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10214 { 25094 /* vfsub.vf */, RISCV::VFSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10215 { 25103 /* vfsub.vv */, RISCV::VFSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10216 { 25112 /* vfwadd.vf */, RISCV::VFWADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10217 { 25122 /* vfwadd.vv */, RISCV::VFWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10218 { 25132 /* vfwadd.wf */, RISCV::VFWADD_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10219 { 25142 /* vfwadd.wv */, RISCV::VFWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10220 { 25152 /* vfwbdota.vv */, RISCV::VFWBDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvfwbdota16bf, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10221 { 25164 /* vfwcvt.f.f.v */, RISCV::VFWCVT_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10222 { 25177 /* vfwcvt.f.x.v */, RISCV::VFWCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10223 { 25190 /* vfwcvt.f.xu.v */, RISCV::VFWCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10224 { 25204 /* vfwcvt.rtz.x.f.v */, RISCV::VFWCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10225 { 25221 /* vfwcvt.rtz.xu.f.v */, RISCV::VFWCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10226 { 25239 /* vfwcvt.x.f.v */, RISCV::VFWCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10227 { 25252 /* vfwcvt.xu.f.v */, RISCV::VFWCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10228 { 25266 /* vfwcvtbf16.f.f.v */, RISCV::VFWCVTBF16_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfminOrZvfofp8min, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10229 { 25283 /* vfwdota.vv */, RISCV::VFWDOTA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfwdota16bf, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10230 { 25294 /* vfwimmacc.vv */, RISCV::VFWIMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10231 { 25307 /* vfwmacc.vf */, RISCV::VFWMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10232 { 25318 /* vfwmacc.vv */, RISCV::VFWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10233 { 25329 /* vfwmaccbf16.vf */, RISCV::VFWMACCBF16_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10234 { 25344 /* vfwmaccbf16.vv */, RISCV::VFWMACCBF16_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10235 { 25359 /* vfwmmacc.vv */, RISCV::VFWMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR }, },
10236 { 25359 /* vfwmmacc.vv */, RISCV::VFWMMACC_VV_SCALE, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVScaleRegOpOperand1_3, AMFBS_HasStdExtZvvfmm, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVScaleRegOpOperand }, },
10237 { 25371 /* vfwmsac.vf */, RISCV::VFWMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10238 { 25382 /* vfwmsac.vv */, RISCV::VFWMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10239 { 25393 /* vfwmul.vf */, RISCV::VFWMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10240 { 25403 /* vfwmul.vv */, RISCV::VFWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10241 { 25413 /* vfwnmacc.vf */, RISCV::VFWNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10242 { 25425 /* vfwnmacc.vv */, RISCV::VFWNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10243 { 25437 /* vfwnmsac.vf */, RISCV::VFWNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_FPR32, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10244 { 25449 /* vfwnmsac.vv */, RISCV::VFWNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10245 { 25461 /* vfwredosum.vs */, RISCV::VFWREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10246 { 25475 /* vfwredusum.vs */, RISCV::VFWREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10247 { 25489 /* vfwsub.vf */, RISCV::VFWSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10248 { 25499 /* vfwsub.vv */, RISCV::VFWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10249 { 25509 /* vfwsub.wf */, RISCV::VFWSUB_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10250 { 25519 /* vfwsub.wv */, RISCV::VFWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10251 { 25529 /* vghsh.vs */, RISCV::VGHSH_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkgs, { MCK_VR, MCK_VR, MCK_VR }, },
10252 { 25538 /* vghsh.vv */, RISCV::VGHSH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkg, { MCK_VR, MCK_VR, MCK_VR }, },
10253 { 25547 /* vgmul.vs */, RISCV::VGMUL_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkgs, { MCK_VR, MCK_VR }, },
10254 { 25556 /* vgmul.vv */, RISCV::VGMUL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkg, { MCK_VR, MCK_VR }, },
10255 { 25565 /* vid.v */, RISCV::VID_V, Convert__Reg1_0__RVVMaskRegOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_RVVMaskRegOpOperand }, },
10256 { 25571 /* viota.m */, RISCV::VIOTA_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10257 { 25579 /* vl1r.v */, RISCV::VL1RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10258 { 25586 /* vl1re16.v */, RISCV::VL1RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10259 { 25596 /* vl1re32.v */, RISCV::VL1RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10260 { 25606 /* vl1re64.v */, RISCV::VL1RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10261 { 25616 /* vl1re8.v */, RISCV::VL1RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10262 { 25625 /* vl2r.v */, RISCV::VL2RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10263 { 25632 /* vl2re16.v */, RISCV::VL2RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10264 { 25642 /* vl2re32.v */, RISCV::VL2RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10265 { 25652 /* vl2re64.v */, RISCV::VL2RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10266 { 25662 /* vl2re8.v */, RISCV::VL2RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10267 { 25671 /* vl4r.v */, RISCV::VL4RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10268 { 25678 /* vl4re16.v */, RISCV::VL4RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10269 { 25688 /* vl4re32.v */, RISCV::VL4RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10270 { 25698 /* vl4re64.v */, RISCV::VL4RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10271 { 25708 /* vl4re8.v */, RISCV::VL4RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10272 { 25717 /* vl8r.v */, RISCV::VL8RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10273 { 25724 /* vl8re16.v */, RISCV::VL8RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10274 { 25734 /* vl8re32.v */, RISCV::VL8RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10275 { 25744 /* vl8re64.v */, RISCV::VL8RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10276 { 25754 /* vl8re8.v */, RISCV::VL8RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10277 { 25763 /* vle16.v */, RISCV::VLE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10278 { 25771 /* vle16ff.v */, RISCV::VLE16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10279 { 25781 /* vle32.v */, RISCV::VLE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10280 { 25789 /* vle32ff.v */, RISCV::VLE32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10281 { 25799 /* vle64.v */, RISCV::VLE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10282 { 25807 /* vle64ff.v */, RISCV::VLE64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10283 { 25817 /* vle8.v */, RISCV::VLE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10284 { 25824 /* vle8ff.v */, RISCV::VLE8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10285 { 25833 /* vlm.v */, RISCV::VLM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10286 { 25839 /* vloxei16.v */, RISCV::VLOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10287 { 25850 /* vloxei32.v */, RISCV::VLOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10288 { 25861 /* vloxei64.v */, RISCV::VLOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10289 { 25872 /* vloxei8.v */, RISCV::VLOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10290 { 25882 /* vloxseg2ei16.v */, RISCV::VLOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10291 { 25897 /* vloxseg2ei32.v */, RISCV::VLOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10292 { 25912 /* vloxseg2ei64.v */, RISCV::VLOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10293 { 25927 /* vloxseg2ei8.v */, RISCV::VLOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10294 { 25941 /* vloxseg3ei16.v */, RISCV::VLOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10295 { 25956 /* vloxseg3ei32.v */, RISCV::VLOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10296 { 25971 /* vloxseg3ei64.v */, RISCV::VLOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10297 { 25986 /* vloxseg3ei8.v */, RISCV::VLOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10298 { 26000 /* vloxseg4ei16.v */, RISCV::VLOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10299 { 26015 /* vloxseg4ei32.v */, RISCV::VLOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10300 { 26030 /* vloxseg4ei64.v */, RISCV::VLOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10301 { 26045 /* vloxseg4ei8.v */, RISCV::VLOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10302 { 26059 /* vloxseg5ei16.v */, RISCV::VLOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10303 { 26074 /* vloxseg5ei32.v */, RISCV::VLOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10304 { 26089 /* vloxseg5ei64.v */, RISCV::VLOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10305 { 26104 /* vloxseg5ei8.v */, RISCV::VLOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10306 { 26118 /* vloxseg6ei16.v */, RISCV::VLOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10307 { 26133 /* vloxseg6ei32.v */, RISCV::VLOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10308 { 26148 /* vloxseg6ei64.v */, RISCV::VLOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10309 { 26163 /* vloxseg6ei8.v */, RISCV::VLOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10310 { 26177 /* vloxseg7ei16.v */, RISCV::VLOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10311 { 26192 /* vloxseg7ei32.v */, RISCV::VLOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10312 { 26207 /* vloxseg7ei64.v */, RISCV::VLOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10313 { 26222 /* vloxseg7ei8.v */, RISCV::VLOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10314 { 26236 /* vloxseg8ei16.v */, RISCV::VLOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10315 { 26251 /* vloxseg8ei32.v */, RISCV::VLOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10316 { 26266 /* vloxseg8ei64.v */, RISCV::VLOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10317 { 26281 /* vloxseg8ei8.v */, RISCV::VLOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10318 { 26295 /* vlse16.v */, RISCV::VLSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10319 { 26304 /* vlse32.v */, RISCV::VLSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10320 { 26313 /* vlse64.v */, RISCV::VLSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10321 { 26322 /* vlse8.v */, RISCV::VLSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10322 { 26330 /* vlseg2e16.v */, RISCV::VLSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10323 { 26342 /* vlseg2e16ff.v */, RISCV::VLSEG2E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10324 { 26356 /* vlseg2e32.v */, RISCV::VLSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10325 { 26368 /* vlseg2e32ff.v */, RISCV::VLSEG2E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10326 { 26382 /* vlseg2e64.v */, RISCV::VLSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10327 { 26394 /* vlseg2e64ff.v */, RISCV::VLSEG2E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10328 { 26408 /* vlseg2e8.v */, RISCV::VLSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10329 { 26419 /* vlseg2e8ff.v */, RISCV::VLSEG2E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10330 { 26432 /* vlseg3e16.v */, RISCV::VLSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10331 { 26444 /* vlseg3e16ff.v */, RISCV::VLSEG3E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10332 { 26458 /* vlseg3e32.v */, RISCV::VLSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10333 { 26470 /* vlseg3e32ff.v */, RISCV::VLSEG3E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10334 { 26484 /* vlseg3e64.v */, RISCV::VLSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10335 { 26496 /* vlseg3e64ff.v */, RISCV::VLSEG3E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10336 { 26510 /* vlseg3e8.v */, RISCV::VLSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10337 { 26521 /* vlseg3e8ff.v */, RISCV::VLSEG3E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10338 { 26534 /* vlseg4e16.v */, RISCV::VLSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10339 { 26546 /* vlseg4e16ff.v */, RISCV::VLSEG4E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10340 { 26560 /* vlseg4e32.v */, RISCV::VLSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10341 { 26572 /* vlseg4e32ff.v */, RISCV::VLSEG4E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10342 { 26586 /* vlseg4e64.v */, RISCV::VLSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10343 { 26598 /* vlseg4e64ff.v */, RISCV::VLSEG4E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10344 { 26612 /* vlseg4e8.v */, RISCV::VLSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10345 { 26623 /* vlseg4e8ff.v */, RISCV::VLSEG4E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10346 { 26636 /* vlseg5e16.v */, RISCV::VLSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10347 { 26648 /* vlseg5e16ff.v */, RISCV::VLSEG5E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10348 { 26662 /* vlseg5e32.v */, RISCV::VLSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10349 { 26674 /* vlseg5e32ff.v */, RISCV::VLSEG5E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10350 { 26688 /* vlseg5e64.v */, RISCV::VLSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10351 { 26700 /* vlseg5e64ff.v */, RISCV::VLSEG5E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10352 { 26714 /* vlseg5e8.v */, RISCV::VLSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10353 { 26725 /* vlseg5e8ff.v */, RISCV::VLSEG5E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10354 { 26738 /* vlseg6e16.v */, RISCV::VLSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10355 { 26750 /* vlseg6e16ff.v */, RISCV::VLSEG6E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10356 { 26764 /* vlseg6e32.v */, RISCV::VLSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10357 { 26776 /* vlseg6e32ff.v */, RISCV::VLSEG6E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10358 { 26790 /* vlseg6e64.v */, RISCV::VLSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10359 { 26802 /* vlseg6e64ff.v */, RISCV::VLSEG6E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10360 { 26816 /* vlseg6e8.v */, RISCV::VLSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10361 { 26827 /* vlseg6e8ff.v */, RISCV::VLSEG6E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10362 { 26840 /* vlseg7e16.v */, RISCV::VLSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10363 { 26852 /* vlseg7e16ff.v */, RISCV::VLSEG7E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10364 { 26866 /* vlseg7e32.v */, RISCV::VLSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10365 { 26878 /* vlseg7e32ff.v */, RISCV::VLSEG7E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10366 { 26892 /* vlseg7e64.v */, RISCV::VLSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10367 { 26904 /* vlseg7e64ff.v */, RISCV::VLSEG7E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10368 { 26918 /* vlseg7e8.v */, RISCV::VLSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10369 { 26929 /* vlseg7e8ff.v */, RISCV::VLSEG7E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10370 { 26942 /* vlseg8e16.v */, RISCV::VLSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10371 { 26954 /* vlseg8e16ff.v */, RISCV::VLSEG8E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10372 { 26968 /* vlseg8e32.v */, RISCV::VLSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10373 { 26980 /* vlseg8e32ff.v */, RISCV::VLSEG8E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10374 { 26994 /* vlseg8e64.v */, RISCV::VLSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10375 { 27006 /* vlseg8e64ff.v */, RISCV::VLSEG8E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10376 { 27020 /* vlseg8e8.v */, RISCV::VLSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10377 { 27031 /* vlseg8e8ff.v */, RISCV::VLSEG8E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10378 { 27044 /* vlsseg2e16.v */, RISCV::VLSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10379 { 27057 /* vlsseg2e32.v */, RISCV::VLSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10380 { 27070 /* vlsseg2e64.v */, RISCV::VLSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10381 { 27083 /* vlsseg2e8.v */, RISCV::VLSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10382 { 27095 /* vlsseg3e16.v */, RISCV::VLSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10383 { 27108 /* vlsseg3e32.v */, RISCV::VLSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10384 { 27121 /* vlsseg3e64.v */, RISCV::VLSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10385 { 27134 /* vlsseg3e8.v */, RISCV::VLSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10386 { 27146 /* vlsseg4e16.v */, RISCV::VLSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10387 { 27159 /* vlsseg4e32.v */, RISCV::VLSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10388 { 27172 /* vlsseg4e64.v */, RISCV::VLSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10389 { 27185 /* vlsseg4e8.v */, RISCV::VLSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10390 { 27197 /* vlsseg5e16.v */, RISCV::VLSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10391 { 27210 /* vlsseg5e32.v */, RISCV::VLSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10392 { 27223 /* vlsseg5e64.v */, RISCV::VLSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10393 { 27236 /* vlsseg5e8.v */, RISCV::VLSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10394 { 27248 /* vlsseg6e16.v */, RISCV::VLSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10395 { 27261 /* vlsseg6e32.v */, RISCV::VLSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10396 { 27274 /* vlsseg6e64.v */, RISCV::VLSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10397 { 27287 /* vlsseg6e8.v */, RISCV::VLSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10398 { 27299 /* vlsseg7e16.v */, RISCV::VLSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10399 { 27312 /* vlsseg7e32.v */, RISCV::VLSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10400 { 27325 /* vlsseg7e64.v */, RISCV::VLSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10401 { 27338 /* vlsseg7e8.v */, RISCV::VLSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10402 { 27350 /* vlsseg8e16.v */, RISCV::VLSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10403 { 27363 /* vlsseg8e32.v */, RISCV::VLSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10404 { 27376 /* vlsseg8e64.v */, RISCV::VLSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10405 { 27389 /* vlsseg8e8.v */, RISCV::VLSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10406 { 27401 /* vluxei16.v */, RISCV::VLUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10407 { 27412 /* vluxei32.v */, RISCV::VLUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10408 { 27423 /* vluxei64.v */, RISCV::VLUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10409 { 27434 /* vluxei8.v */, RISCV::VLUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10410 { 27444 /* vluxseg2ei16.v */, RISCV::VLUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10411 { 27459 /* vluxseg2ei32.v */, RISCV::VLUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10412 { 27474 /* vluxseg2ei64.v */, RISCV::VLUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10413 { 27489 /* vluxseg2ei8.v */, RISCV::VLUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10414 { 27503 /* vluxseg3ei16.v */, RISCV::VLUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10415 { 27518 /* vluxseg3ei32.v */, RISCV::VLUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10416 { 27533 /* vluxseg3ei64.v */, RISCV::VLUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10417 { 27548 /* vluxseg3ei8.v */, RISCV::VLUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10418 { 27562 /* vluxseg4ei16.v */, RISCV::VLUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10419 { 27577 /* vluxseg4ei32.v */, RISCV::VLUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10420 { 27592 /* vluxseg4ei64.v */, RISCV::VLUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10421 { 27607 /* vluxseg4ei8.v */, RISCV::VLUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10422 { 27621 /* vluxseg5ei16.v */, RISCV::VLUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10423 { 27636 /* vluxseg5ei32.v */, RISCV::VLUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10424 { 27651 /* vluxseg5ei64.v */, RISCV::VLUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10425 { 27666 /* vluxseg5ei8.v */, RISCV::VLUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10426 { 27680 /* vluxseg6ei16.v */, RISCV::VLUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10427 { 27695 /* vluxseg6ei32.v */, RISCV::VLUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10428 { 27710 /* vluxseg6ei64.v */, RISCV::VLUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10429 { 27725 /* vluxseg6ei8.v */, RISCV::VLUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10430 { 27739 /* vluxseg7ei16.v */, RISCV::VLUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10431 { 27754 /* vluxseg7ei32.v */, RISCV::VLUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10432 { 27769 /* vluxseg7ei64.v */, RISCV::VLUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10433 { 27784 /* vluxseg7ei8.v */, RISCV::VLUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10434 { 27798 /* vluxseg8ei16.v */, RISCV::VLUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10435 { 27813 /* vluxseg8ei32.v */, RISCV::VLUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10436 { 27828 /* vluxseg8ei64.v */, RISCV::VLUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10437 { 27843 /* vluxseg8ei8.v */, RISCV::VLUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10438 { 27857 /* vmacc.vv */, RISCV::VMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10439 { 27866 /* vmacc.vx */, RISCV::VMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10440 { 27875 /* vmadc.vi */, RISCV::VMADC_VI, Convert__Reg1_0__Reg1_1__SImm51_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5 }, },
10441 { 27884 /* vmadc.vim */, RISCV::VMADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
10442 { 27894 /* vmadc.vv */, RISCV::VMADC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10443 { 27903 /* vmadc.vvm */, RISCV::VMADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10444 { 27913 /* vmadc.vx */, RISCV::VMADC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10445 { 27922 /* vmadc.vxm */, RISCV::VMADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10446 { 27932 /* vmadd.vv */, RISCV::VMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10447 { 27941 /* vmadd.vx */, RISCV::VMADD_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10448 { 27950 /* vmand.mm */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10449 { 27959 /* vmandn.mm */, RISCV::VMANDN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10450 { 27969 /* vmax.vv */, RISCV::VMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10451 { 27977 /* vmax.vx */, RISCV::VMAX_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10452 { 27985 /* vmaxu.vv */, RISCV::VMAXU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10453 { 27994 /* vmaxu.vx */, RISCV::VMAXU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10454 { 28003 /* vmclr.m */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VR }, },
10455 { 28011 /* vmerge.vim */, RISCV::VMERGE_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskCarryInRegOpOperand }, },
10456 { 28022 /* vmerge.vvm */, RISCV::VMERGE_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10457 { 28033 /* vmerge.vxm */, RISCV::VMERGE_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10458 { 28044 /* vmfeq.vf */, RISCV::VMFEQ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10459 { 28053 /* vmfeq.vv */, RISCV::VMFEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10460 { 28062 /* vmfge.vf */, RISCV::VMFGE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10461 { 28071 /* vmfge.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10462 { 28080 /* vmfgt.vf */, RISCV::VMFGT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10463 { 28089 /* vmfgt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10464 { 28098 /* vmfle.vf */, RISCV::VMFLE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10465 { 28107 /* vmfle.vv */, RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10466 { 28116 /* vmflt.vf */, RISCV::VMFLT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10467 { 28125 /* vmflt.vv */, RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10468 { 28134 /* vmfne.vf */, RISCV::VMFNE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
10469 { 28143 /* vmfne.vv */, RISCV::VMFNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10470 { 28152 /* vmin.vv */, RISCV::VMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10471 { 28160 /* vmin.vx */, RISCV::VMIN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10472 { 28168 /* vminu.vv */, RISCV::VMINU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10473 { 28177 /* vminu.vx */, RISCV::VMINU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10474 { 28186 /* vmmacc.vv */, RISCV::VMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10475 { 28196 /* vmmv.m */, RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10476 { 28203 /* vmnand.mm */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10477 { 28213 /* vmnor.mm */, RISCV::VMNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10478 { 28222 /* vmnot.m */, RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10479 { 28230 /* vmor.mm */, RISCV::VMOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10480 { 28238 /* vmorn.mm */, RISCV::VMORN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10481 { 28247 /* vmsbc.vv */, RISCV::VMSBC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10482 { 28256 /* vmsbc.vvm */, RISCV::VMSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10483 { 28266 /* vmsbc.vx */, RISCV::VMSBC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10484 { 28275 /* vmsbc.vxm */, RISCV::VMSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10485 { 28285 /* vmsbf.m */, RISCV::VMSBF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10486 { 28293 /* vmseq.vi */, RISCV::VMSEQ_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10487 { 28302 /* vmseq.vv */, RISCV::VMSEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10488 { 28311 /* vmseq.vx */, RISCV::VMSEQ_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10489 { 28320 /* vmset.m */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VR }, },
10490 { 28328 /* vmsge.vi */, RISCV::PseudoVMSGE_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10491 { 28337 /* vmsge.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10492 { 28346 /* vmsge.vx */, RISCV::PseudoVMSGE_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10493 { 28346 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VRNoV0, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10494 { 28346 /* vmsge.vx */, RISCV::PseudoVMSGE_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
10495 { 28355 /* vmsgeu.vi */, RISCV::PseudoVMSGEU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10496 { 28365 /* vmsgeu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10497 { 28375 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR }, },
10498 { 28375 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VRNoV0, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10499 { 28375 /* vmsgeu.vx */, RISCV::PseudoVMSGEU_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
10500 { 28385 /* vmsgt.vi */, RISCV::VMSGT_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10501 { 28394 /* vmsgt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10502 { 28403 /* vmsgt.vx */, RISCV::VMSGT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10503 { 28412 /* vmsgtu.vi */, RISCV::VMSGTU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10504 { 28422 /* vmsgtu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10505 { 28432 /* vmsgtu.vx */, RISCV::VMSGTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10506 { 28442 /* vmsif.m */, RISCV::VMSIF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10507 { 28450 /* vmsle.vi */, RISCV::VMSLE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10508 { 28459 /* vmsle.vv */, RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10509 { 28468 /* vmsle.vx */, RISCV::VMSLE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10510 { 28477 /* vmsleu.vi */, RISCV::VMSLEU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10511 { 28487 /* vmsleu.vv */, RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10512 { 28497 /* vmsleu.vx */, RISCV::VMSLEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10513 { 28507 /* vmslt.vi */, RISCV::PseudoVMSLT_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10514 { 28516 /* vmslt.vv */, RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10515 { 28525 /* vmslt.vx */, RISCV::VMSLT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10516 { 28534 /* vmsltu.vi */, RISCV::PseudoVMSLTU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
10517 { 28544 /* vmsltu.vv */, RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10518 { 28554 /* vmsltu.vx */, RISCV::VMSLTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10519 { 28564 /* vmsne.vi */, RISCV::VMSNE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10520 { 28573 /* vmsne.vv */, RISCV::VMSNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10521 { 28582 /* vmsne.vx */, RISCV::VMSNE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10522 { 28591 /* vmsof.m */, RISCV::VMSOF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10523 { 28599 /* vmtl.v */, RISCV::VMTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10524 { 28599 /* vmtl.v */, RISCV::VMTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10525 { 28606 /* vmts.v */, RISCV::VMTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10526 { 28606 /* vmts.v */, RISCV::VMTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmtls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10527 { 28613 /* vmttl.v */, RISCV::VMTTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10528 { 28613 /* vmttl.v */, RISCV::VMTTL_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10529 { 28621 /* vmtts.v */, RISCV::VMTTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__imm_95_0__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10530 { 28621 /* vmtts.v */, RISCV::VMTTS_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__TileLambda1_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvvmttls, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_TileLambda, MCK_RVVMaskRegOpOperand }, },
10531 { 28629 /* vmul.vv */, RISCV::VMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10532 { 28637 /* vmul.vx */, RISCV::VMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10533 { 28645 /* vmulh.vv */, RISCV::VMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10534 { 28654 /* vmulh.vx */, RISCV::VMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10535 { 28663 /* vmulhsu.vv */, RISCV::VMULHSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10536 { 28674 /* vmulhsu.vx */, RISCV::VMULHSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10537 { 28685 /* vmulhu.vv */, RISCV::VMULHU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10538 { 28695 /* vmulhu.vx */, RISCV::VMULHU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10539 { 28705 /* vmv.s.x */, RISCV::VMV_S_X, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR }, },
10540 { 28713 /* vmv.v.i */, RISCV::VMV_V_I, Convert__Reg1_0__SImm51_1, AMFBS_HasVInstructions, { MCK_VR, MCK_SImm5 }, },
10541 { 28721 /* vmv.v.v */, RISCV::VMV_V_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10542 { 28729 /* vmv.v.x */, RISCV::VMV_V_X, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR }, },
10543 { 28737 /* vmv.x.s */, RISCV::VMV_X_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_GPR, MCK_VR }, },
10544 { 28745 /* vmv1r.v */, RISCV::VMV1R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10545 { 28753 /* vmv2r.v */, RISCV::VMV2R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_VRM2 }, },
10546 { 28761 /* vmv4r.v */, RISCV::VMV4R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_VRM4 }, },
10547 { 28769 /* vmv8r.v */, RISCV::VMV8R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_VRM8 }, },
10548 { 28777 /* vmxnor.mm */, RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10549 { 28787 /* vmxor.mm */, RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR }, },
10550 { 28796 /* vnclip.wi */, RISCV::VNCLIP_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10551 { 28806 /* vnclip.wv */, RISCV::VNCLIP_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10552 { 28816 /* vnclip.wx */, RISCV::VNCLIP_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10553 { 28826 /* vnclipu.wi */, RISCV::VNCLIPU_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10554 { 28837 /* vnclipu.wv */, RISCV::VNCLIPU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10555 { 28848 /* vnclipu.wx */, RISCV::VNCLIPU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10556 { 28859 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10557 { 28859 /* vncvt.x.x.w */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10558 { 28871 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10559 { 28871 /* vneg.v */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10560 { 28878 /* vnmsac.vv */, RISCV::VNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10561 { 28888 /* vnmsac.vx */, RISCV::VNMSAC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10562 { 28898 /* vnmsub.vv */, RISCV::VNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10563 { 28908 /* vnmsub.vx */, RISCV::VNMSUB_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10564 { 28918 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10565 { 28918 /* vnot.v */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10566 { 28925 /* vnsra.wi */, RISCV::VNSRA_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10567 { 28934 /* vnsra.wv */, RISCV::VNSRA_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10568 { 28943 /* vnsra.wx */, RISCV::VNSRA_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10569 { 28952 /* vnsrl.wi */, RISCV::VNSRL_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10570 { 28961 /* vnsrl.wv */, RISCV::VNSRL_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10571 { 28970 /* vnsrl.wx */, RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10572 { 28979 /* vor.vi */, RISCV::VOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10573 { 28986 /* vor.vv */, RISCV::VOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10574 { 28993 /* vor.vx */, RISCV::VOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10575 { 29000 /* vpaire.vv */, RISCV::VPAIRE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10576 { 29010 /* vpairo.vv */, RISCV::VPAIRO_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10577 { 29020 /* vqmmacc.vv */, RISCV::VQMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10578 { 29031 /* vqwbdotas.vv */, RISCV::VQWBDOTAS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10579 { 29044 /* vqwbdotau.vv */, RISCV::VQWBDOTAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm31_3__RVVMaskRegOpOperand1_4, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i, { MCK_VR, MCK_VRM8, MCK_VR, MCK_UImm3, MCK_RVVMaskRegOpOperand }, },
10580 { 29057 /* vqwdotas.vv */, RISCV::VQWDOTAS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10581 { 29069 /* vqwdotau.vv */, RISCV::VQWDOTAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10582 { 29081 /* vredand.vs */, RISCV::VREDAND_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10583 { 29092 /* vredmax.vs */, RISCV::VREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10584 { 29103 /* vredmaxu.vs */, RISCV::VREDMAXU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10585 { 29115 /* vredmin.vs */, RISCV::VREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10586 { 29126 /* vredminu.vs */, RISCV::VREDMINU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10587 { 29138 /* vredor.vs */, RISCV::VREDOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10588 { 29148 /* vredsum.vs */, RISCV::VREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10589 { 29159 /* vredxor.vs */, RISCV::VREDXOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10590 { 29170 /* vrem.vv */, RISCV::VREM_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10591 { 29178 /* vrem.vx */, RISCV::VREM_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10592 { 29186 /* vremu.vv */, RISCV::VREMU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10593 { 29195 /* vremu.vx */, RISCV::VREMU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10594 { 29204 /* vrev8.v */, RISCV::VREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10595 { 29212 /* vrgather.vi */, RISCV::VRGATHER_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10596 { 29224 /* vrgather.vv */, RISCV::VRGATHER_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10597 { 29236 /* vrgather.vx */, RISCV::VRGATHER_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10598 { 29248 /* vrgatherei16.vv */, RISCV::VRGATHEREI16_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10599 { 29264 /* vrol.vv */, RISCV::VROL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10600 { 29272 /* vrol.vx */, RISCV::VROL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10601 { 29280 /* vror.vi */, RISCV::VROR_VI, Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_UImm6, MCK_RVVMaskRegOpOperand }, },
10602 { 29288 /* vror.vv */, RISCV::VROR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10603 { 29296 /* vror.vx */, RISCV::VROR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10604 { 29304 /* vrsub.vi */, RISCV::VRSUB_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10605 { 29313 /* vrsub.vx */, RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10606 { 29322 /* vs1r.v */, RISCV::VS1R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10607 { 29329 /* vs2r.v */, RISCV::VS2R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
10608 { 29336 /* vs4r.v */, RISCV::VS4R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
10609 { 29343 /* vs8r.v */, RISCV::VS8R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
10610 { 29350 /* vsadd.vi */, RISCV::VSADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10611 { 29359 /* vsadd.vv */, RISCV::VSADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10612 { 29368 /* vsadd.vx */, RISCV::VSADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10613 { 29377 /* vsaddu.vi */, RISCV::VSADDU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10614 { 29387 /* vsaddu.vv */, RISCV::VSADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10615 { 29397 /* vsaddu.vx */, RISCV::VSADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10616 { 29407 /* vsbc.vvm */, RISCV::VSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskCarryInRegOpOperand }, },
10617 { 29416 /* vsbc.vxm */, RISCV::VSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskCarryInRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskCarryInRegOpOperand }, },
10618 { 29425 /* vse16.v */, RISCV::VSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10619 { 29433 /* vse32.v */, RISCV::VSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10620 { 29441 /* vse64.v */, RISCV::VSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10621 { 29449 /* vse8.v */, RISCV::VSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10622 { 29456 /* vsetivli */, RISCV::VSETIVLI, Convert__Reg1_0__UImm51_1__VTypeI101_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_UImm5, MCK_VTypeI10 }, },
10623 { 29465 /* vsetvl */, RISCV::VSETVL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10624 { 29472 /* vsetvli */, RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__VTypeI111_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_VTypeI11 }, },
10625 { 29480 /* vsext.vf2 */, RISCV::VSEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10626 { 29490 /* vsext.vf4 */, RISCV::VSEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10627 { 29500 /* vsext.vf8 */, RISCV::VSEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10628 { 29510 /* vsha2ch.vv */, RISCV::VSHA2CH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknha, { MCK_VR, MCK_VR, MCK_VR }, },
10629 { 29521 /* vsha2cl.vv */, RISCV::VSHA2CL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknha, { MCK_VR, MCK_VR, MCK_VR }, },
10630 { 29532 /* vsha2ms.vv */, RISCV::VSHA2MS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknha, { MCK_VR, MCK_VR, MCK_VR }, },
10631 { 29543 /* vslide1down.vx */, RISCV::VSLIDE1DOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10632 { 29558 /* vslide1up.vx */, RISCV::VSLIDE1UP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10633 { 29571 /* vslidedown.vi */, RISCV::VSLIDEDOWN_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10634 { 29585 /* vslidedown.vx */, RISCV::VSLIDEDOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10635 { 29599 /* vslideup.vi */, RISCV::VSLIDEUP_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10636 { 29611 /* vslideup.vx */, RISCV::VSLIDEUP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10637 { 29623 /* vsll.vi */, RISCV::VSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10638 { 29631 /* vsll.vv */, RISCV::VSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10639 { 29639 /* vsll.vx */, RISCV::VSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10640 { 29647 /* vsm.v */, RISCV::VSM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand }, },
10641 { 29653 /* vsm3c.vi */, RISCV::VSM3C_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksh, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10642 { 29662 /* vsm3me.vv */, RISCV::VSM3ME_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZvksh, { MCK_VR, MCK_VR, MCK_VR }, },
10643 { 29672 /* vsm4k.vi */, RISCV::VSM4K_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR, MCK_UImm5 }, },
10644 { 29681 /* vsm4r.vs */, RISCV::VSM4R_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR }, },
10645 { 29690 /* vsm4r.vv */, RISCV::VSM4R_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VR, MCK_VR }, },
10646 { 29699 /* vsmul.vv */, RISCV::VSMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10647 { 29708 /* vsmul.vx */, RISCV::VSMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10648 { 29717 /* vsoxei16.v */, RISCV::VSOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10649 { 29728 /* vsoxei32.v */, RISCV::VSOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10650 { 29739 /* vsoxei64.v */, RISCV::VSOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10651 { 29750 /* vsoxei8.v */, RISCV::VSOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10652 { 29760 /* vsoxseg2ei16.v */, RISCV::VSOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10653 { 29775 /* vsoxseg2ei32.v */, RISCV::VSOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10654 { 29790 /* vsoxseg2ei64.v */, RISCV::VSOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10655 { 29805 /* vsoxseg2ei8.v */, RISCV::VSOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10656 { 29819 /* vsoxseg3ei16.v */, RISCV::VSOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10657 { 29834 /* vsoxseg3ei32.v */, RISCV::VSOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10658 { 29849 /* vsoxseg3ei64.v */, RISCV::VSOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10659 { 29864 /* vsoxseg3ei8.v */, RISCV::VSOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10660 { 29878 /* vsoxseg4ei16.v */, RISCV::VSOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10661 { 29893 /* vsoxseg4ei32.v */, RISCV::VSOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10662 { 29908 /* vsoxseg4ei64.v */, RISCV::VSOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10663 { 29923 /* vsoxseg4ei8.v */, RISCV::VSOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10664 { 29937 /* vsoxseg5ei16.v */, RISCV::VSOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10665 { 29952 /* vsoxseg5ei32.v */, RISCV::VSOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10666 { 29967 /* vsoxseg5ei64.v */, RISCV::VSOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10667 { 29982 /* vsoxseg5ei8.v */, RISCV::VSOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10668 { 29996 /* vsoxseg6ei16.v */, RISCV::VSOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10669 { 30011 /* vsoxseg6ei32.v */, RISCV::VSOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10670 { 30026 /* vsoxseg6ei64.v */, RISCV::VSOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10671 { 30041 /* vsoxseg6ei8.v */, RISCV::VSOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10672 { 30055 /* vsoxseg7ei16.v */, RISCV::VSOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10673 { 30070 /* vsoxseg7ei32.v */, RISCV::VSOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10674 { 30085 /* vsoxseg7ei64.v */, RISCV::VSOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10675 { 30100 /* vsoxseg7ei8.v */, RISCV::VSOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10676 { 30114 /* vsoxseg8ei16.v */, RISCV::VSOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10677 { 30129 /* vsoxseg8ei32.v */, RISCV::VSOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10678 { 30144 /* vsoxseg8ei64.v */, RISCV::VSOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10679 { 30159 /* vsoxseg8ei8.v */, RISCV::VSOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10680 { 30173 /* vsra.vi */, RISCV::VSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10681 { 30181 /* vsra.vv */, RISCV::VSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10682 { 30189 /* vsra.vx */, RISCV::VSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10683 { 30197 /* vsrl.vi */, RISCV::VSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10684 { 30205 /* vsrl.vv */, RISCV::VSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10685 { 30213 /* vsrl.vx */, RISCV::VSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10686 { 30221 /* vsse16.v */, RISCV::VSSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10687 { 30230 /* vsse32.v */, RISCV::VSSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10688 { 30239 /* vsse64.v */, RISCV::VSSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10689 { 30248 /* vsse8.v */, RISCV::VSSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10690 { 30256 /* vsseg2e16.v */, RISCV::VSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10691 { 30268 /* vsseg2e32.v */, RISCV::VSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10692 { 30280 /* vsseg2e64.v */, RISCV::VSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10693 { 30292 /* vsseg2e8.v */, RISCV::VSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10694 { 30303 /* vsseg3e16.v */, RISCV::VSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10695 { 30315 /* vsseg3e32.v */, RISCV::VSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10696 { 30327 /* vsseg3e64.v */, RISCV::VSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10697 { 30339 /* vsseg3e8.v */, RISCV::VSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10698 { 30350 /* vsseg4e16.v */, RISCV::VSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10699 { 30362 /* vsseg4e32.v */, RISCV::VSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10700 { 30374 /* vsseg4e64.v */, RISCV::VSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10701 { 30386 /* vsseg4e8.v */, RISCV::VSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10702 { 30397 /* vsseg5e16.v */, RISCV::VSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10703 { 30409 /* vsseg5e32.v */, RISCV::VSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10704 { 30421 /* vsseg5e64.v */, RISCV::VSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10705 { 30433 /* vsseg5e8.v */, RISCV::VSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10706 { 30444 /* vsseg6e16.v */, RISCV::VSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10707 { 30456 /* vsseg6e32.v */, RISCV::VSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10708 { 30468 /* vsseg6e64.v */, RISCV::VSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10709 { 30480 /* vsseg6e8.v */, RISCV::VSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10710 { 30491 /* vsseg7e16.v */, RISCV::VSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10711 { 30503 /* vsseg7e32.v */, RISCV::VSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10712 { 30515 /* vsseg7e64.v */, RISCV::VSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10713 { 30527 /* vsseg7e8.v */, RISCV::VSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10714 { 30538 /* vsseg8e16.v */, RISCV::VSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10715 { 30550 /* vsseg8e32.v */, RISCV::VSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10716 { 30562 /* vsseg8e64.v */, RISCV::VSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10717 { 30574 /* vsseg8e8.v */, RISCV::VSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
10718 { 30585 /* vssra.vi */, RISCV::VSSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10719 { 30594 /* vssra.vv */, RISCV::VSSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10720 { 30603 /* vssra.vx */, RISCV::VSSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10721 { 30612 /* vssrl.vi */, RISCV::VSSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10722 { 30621 /* vssrl.vv */, RISCV::VSSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10723 { 30630 /* vssrl.vx */, RISCV::VSSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10724 { 30639 /* vssseg2e16.v */, RISCV::VSSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10725 { 30652 /* vssseg2e32.v */, RISCV::VSSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10726 { 30665 /* vssseg2e64.v */, RISCV::VSSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10727 { 30678 /* vssseg2e8.v */, RISCV::VSSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10728 { 30690 /* vssseg3e16.v */, RISCV::VSSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10729 { 30703 /* vssseg3e32.v */, RISCV::VSSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10730 { 30716 /* vssseg3e64.v */, RISCV::VSSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10731 { 30729 /* vssseg3e8.v */, RISCV::VSSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10732 { 30741 /* vssseg4e16.v */, RISCV::VSSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10733 { 30754 /* vssseg4e32.v */, RISCV::VSSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10734 { 30767 /* vssseg4e64.v */, RISCV::VSSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10735 { 30780 /* vssseg4e8.v */, RISCV::VSSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10736 { 30792 /* vssseg5e16.v */, RISCV::VSSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10737 { 30805 /* vssseg5e32.v */, RISCV::VSSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10738 { 30818 /* vssseg5e64.v */, RISCV::VSSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10739 { 30831 /* vssseg5e8.v */, RISCV::VSSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10740 { 30843 /* vssseg6e16.v */, RISCV::VSSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10741 { 30856 /* vssseg6e32.v */, RISCV::VSSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10742 { 30869 /* vssseg6e64.v */, RISCV::VSSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10743 { 30882 /* vssseg6e8.v */, RISCV::VSSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10744 { 30894 /* vssseg7e16.v */, RISCV::VSSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10745 { 30907 /* vssseg7e32.v */, RISCV::VSSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10746 { 30920 /* vssseg7e64.v */, RISCV::VSSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10747 { 30933 /* vssseg7e8.v */, RISCV::VSSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10748 { 30945 /* vssseg8e16.v */, RISCV::VSSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10749 { 30958 /* vssseg8e32.v */, RISCV::VSSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10750 { 30971 /* vssseg8e64.v */, RISCV::VSSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10751 { 30984 /* vssseg8e8.v */, RISCV::VSSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10752 { 30996 /* vssub.vv */, RISCV::VSSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10753 { 31005 /* vssub.vx */, RISCV::VSSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10754 { 31014 /* vssubu.vv */, RISCV::VSSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10755 { 31024 /* vssubu.vx */, RISCV::VSSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10756 { 31034 /* vsub.vv */, RISCV::VSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10757 { 31042 /* vsub.vx */, RISCV::VSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10758 { 31050 /* vsuxei16.v */, RISCV::VSUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10759 { 31061 /* vsuxei32.v */, RISCV::VSUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10760 { 31072 /* vsuxei64.v */, RISCV::VSUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10761 { 31083 /* vsuxei8.v */, RISCV::VSUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10762 { 31093 /* vsuxseg2ei16.v */, RISCV::VSUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10763 { 31108 /* vsuxseg2ei32.v */, RISCV::VSUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10764 { 31123 /* vsuxseg2ei64.v */, RISCV::VSUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10765 { 31138 /* vsuxseg2ei8.v */, RISCV::VSUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10766 { 31152 /* vsuxseg3ei16.v */, RISCV::VSUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10767 { 31167 /* vsuxseg3ei32.v */, RISCV::VSUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10768 { 31182 /* vsuxseg3ei64.v */, RISCV::VSUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10769 { 31197 /* vsuxseg3ei8.v */, RISCV::VSUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10770 { 31211 /* vsuxseg4ei16.v */, RISCV::VSUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10771 { 31226 /* vsuxseg4ei32.v */, RISCV::VSUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10772 { 31241 /* vsuxseg4ei64.v */, RISCV::VSUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10773 { 31256 /* vsuxseg4ei8.v */, RISCV::VSUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10774 { 31270 /* vsuxseg5ei16.v */, RISCV::VSUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10775 { 31285 /* vsuxseg5ei32.v */, RISCV::VSUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10776 { 31300 /* vsuxseg5ei64.v */, RISCV::VSUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10777 { 31315 /* vsuxseg5ei8.v */, RISCV::VSUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10778 { 31329 /* vsuxseg6ei16.v */, RISCV::VSUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10779 { 31344 /* vsuxseg6ei32.v */, RISCV::VSUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10780 { 31359 /* vsuxseg6ei64.v */, RISCV::VSUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10781 { 31374 /* vsuxseg6ei8.v */, RISCV::VSUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10782 { 31388 /* vsuxseg7ei16.v */, RISCV::VSUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10783 { 31403 /* vsuxseg7ei32.v */, RISCV::VSUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10784 { 31418 /* vsuxseg7ei64.v */, RISCV::VSUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10785 { 31433 /* vsuxseg7ei8.v */, RISCV::VSUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10786 { 31447 /* vsuxseg8ei16.v */, RISCV::VSUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10787 { 31462 /* vsuxseg8ei32.v */, RISCV::VSUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10788 { 31477 /* vsuxseg8ei64.v */, RISCV::VSUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10789 { 31492 /* vsuxseg8ei8.v */, RISCV::VSUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_ZeroOffsetMemOpOperand, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10790 { 31506 /* vt.maskc */, RISCV::VT_MASKC, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10791 { 31515 /* vt.maskcn */, RISCV::VT_MASKCN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10792 { 31525 /* vunzipe.v */, RISCV::VUNZIPE_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10793 { 31535 /* vunzipo.v */, RISCV::VUNZIPO_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10794 { 31545 /* vwabda.vv */, RISCV::VWABDA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10795 { 31555 /* vwabdau.vv */, RISCV::VWABDAU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvabd, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10796 { 31566 /* vwadd.vv */, RISCV::VWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10797 { 31575 /* vwadd.vx */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10798 { 31584 /* vwadd.wv */, RISCV::VWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10799 { 31593 /* vwadd.wx */, RISCV::VWADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10800 { 31602 /* vwaddu.vv */, RISCV::VWADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10801 { 31612 /* vwaddu.vx */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10802 { 31622 /* vwaddu.wv */, RISCV::VWADDU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10803 { 31632 /* vwaddu.wx */, RISCV::VWADDU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10804 { 31642 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10805 { 31642 /* vwcvt.x.x.v */, RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10806 { 31654 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VR, MCK_VR }, },
10807 { 31654 /* vwcvtu.x.x.v */, RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10808 { 31667 /* vwmacc.vv */, RISCV::VWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10809 { 31677 /* vwmacc.vx */, RISCV::VWMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10810 { 31687 /* vwmaccsu.vv */, RISCV::VWMACCSU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10811 { 31699 /* vwmaccsu.vx */, RISCV::VWMACCSU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10812 { 31711 /* vwmaccu.vv */, RISCV::VWMACCU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10813 { 31722 /* vwmaccu.vx */, RISCV::VWMACCU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10814 { 31733 /* vwmaccus.vx */, RISCV::VWMACCUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_GPR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10815 { 31745 /* vwmmacc.vv */, RISCV::VWMMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvvmm, { MCK_VR, MCK_VR, MCK_VR }, },
10816 { 31756 /* vwmul.vv */, RISCV::VWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10817 { 31765 /* vwmul.vx */, RISCV::VWMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10818 { 31774 /* vwmulsu.vv */, RISCV::VWMULSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10819 { 31785 /* vwmulsu.vx */, RISCV::VWMULSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10820 { 31796 /* vwmulu.vv */, RISCV::VWMULU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10821 { 31806 /* vwmulu.vx */, RISCV::VWMULU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10822 { 31816 /* vwredsum.vs */, RISCV::VWREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10823 { 31828 /* vwredsumu.vs */, RISCV::VWREDSUMU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10824 { 31841 /* vwsll.vi */, RISCV::VWSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
10825 { 31850 /* vwsll.vv */, RISCV::VWSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10826 { 31859 /* vwsll.vx */, RISCV::VWSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10827 { 31868 /* vwsub.vv */, RISCV::VWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10828 { 31877 /* vwsub.vx */, RISCV::VWSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10829 { 31886 /* vwsub.wv */, RISCV::VWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10830 { 31895 /* vwsub.wx */, RISCV::VWSUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10831 { 31904 /* vwsubu.vv */, RISCV::VWSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10832 { 31914 /* vwsubu.vx */, RISCV::VWSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10833 { 31924 /* vwsubu.wv */, RISCV::VWSUBU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10834 { 31934 /* vwsubu.wx */, RISCV::VWSUBU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10835 { 31944 /* vxor.vi */, RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
10836 { 31952 /* vxor.vv */, RISCV::VXOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10837 { 31960 /* vxor.vx */, RISCV::VXOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
10838 { 31968 /* vzext.vf2 */, RISCV::VZEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10839 { 31978 /* vzext.vf4 */, RISCV::VZEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10840 { 31988 /* vzext.vf8 */, RISCV::VZEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10841 { 31998 /* vzip.vv */, RISCV::VZIP_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvzip, { MCK_VR, MCK_VR, MCK_VR, MCK_RVVMaskRegOpOperand }, },
10842 { 32006 /* wadd */, RISCV::WADD, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10843 { 32011 /* wadda */, RISCV::WADDA, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10844 { 32017 /* waddau */, RISCV::WADDAU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10845 { 32024 /* waddu */, RISCV::WADDU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10846 { 32030 /* wfi */, RISCV::WFI, Convert_NoOperands, AMFBS_None, { }, },
10847 { 32034 /* wmacc */, RISCV::WMACC, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10848 { 32040 /* wmaccsu */, RISCV::WMACCSU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10849 { 32048 /* wmaccu */, RISCV::WMACCU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10850 { 32055 /* wmul */, RISCV::WMUL, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10851 { 32060 /* wmulsu */, RISCV::WMULSU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10852 { 32067 /* wmulu */, RISCV::WMULU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10853 { 32073 /* wrs.nto */, RISCV::WRS_NTO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
10854 { 32081 /* wrs.sto */, RISCV::WRS_STO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
10855 { 32089 /* wsla */, RISCV::WSLA, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10856 { 32094 /* wslai */, RISCV::WSLAI, Convert__GPRPairRV321_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm6 }, },
10857 { 32100 /* wsll */, RISCV::WSLL, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10858 { 32105 /* wslli */, RISCV::WSLLI, Convert__GPRPairRV321_0__Reg1_1__UImm61_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_UImm6 }, },
10859 { 32111 /* wsub */, RISCV::WSUB, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10860 { 32116 /* wsuba */, RISCV::WSUBA, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10861 { 32122 /* wsubau */, RISCV::WSUBAU, Convert__GPRPairRV321_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10862 { 32129 /* wsubu */, RISCV::WSUBU, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10863 { 32135 /* wzip16p */, RISCV::WZIP16P, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10864 { 32143 /* wzip8p */, RISCV::WZIP8P, Convert__GPRPairRV321_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV32, { MCK_GPRPairRV32, MCK_GPR, MCK_GPR }, },
10865 { 32150 /* xnor */, RISCV::XNOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10866 { 32155 /* xor */, RISCV::XOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10867 { 32155 /* xor */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10868 { 32159 /* xori */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12LO }, },
10869 { 32164 /* xperm4 */, RISCV::XPERM4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10870 { 32171 /* xperm8 */, RISCV::XPERM8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10871 { 32178 /* yadd */, RISCV::YADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPRNoX0 }, },
10872 { 32178 /* yadd */, RISCV::YADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_SImm12LO }, },
10873 { 32183 /* yaddi */, RISCV::YADDI, Convert__Reg1_0__Reg1_1__SImm12LO1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_SImm12LO }, },
10874 { 32189 /* yaddrw */, RISCV::YADDRW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
10875 { 32196 /* yamask */, RISCV::YAMASK, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_GPR }, },
10876 { 32203 /* ybaser */, RISCV::YBASER, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10877 { 32210 /* ybld */, RISCV::YBLD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YGPR }, },
10878 { 32215 /* ybndsrw */, RISCV::YBNDSRW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
10879 { 32223 /* ybndsw */, RISCV::YBNDSW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
10880 { 32223 /* ybndsw */, RISCV::YBNDSWI, Convert__Reg1_0__Reg1_1__YBNDSWImm1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YBNDSWImm }, },
10881 { 32230 /* ybndswi */, RISCV::YBNDSWI, Convert__Reg1_0__Reg1_1__YBNDSWImm1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YBNDSWImm }, },
10882 { 32238 /* yeq */, RISCV::YEQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR, MCK_YGPR }, },
10883 { 32242 /* yhir */, RISCV::SRLIY, Convert__Reg1_0__Reg1_1__imm_95_64, AMFBS_HasStdExtY_IsRV64, { MCK_GPR, MCK_YGPR }, },
10884 { 32242 /* yhir */, RISCV::SRLIY, Convert__Reg1_0__Reg1_1__imm_95_32, AMFBS_HasStdExtY_IsRV32, { MCK_GPR, MCK_YGPR }, },
10885 { 32247 /* ylenr */, RISCV::YLENR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10886 { 32253 /* ymv */, RISCV::YMV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR }, },
10887 { 32257 /* ypermc */, RISCV::YPERMC, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_GPR }, },
10888 { 32264 /* ypermr */, RISCV::YPERMR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10889 { 32271 /* yss */, RISCV::YSS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR, MCK_YGPR }, },
10890 { 32275 /* ysunseal */, RISCV::YSUNSEAL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtY, { MCK_YGPR, MCK_YGPR, MCK_YGPR }, },
10891 { 32284 /* ytagr */, RISCV::YTAGR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10892 { 32290 /* ytopr */, RISCV::YTOPR, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10893 { 32296 /* ytyper */, RISCV::YTYPER, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtY, { MCK_GPR, MCK_YGPR }, },
10894 { 32303 /* zext.b */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__imm_95_255, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10895 { 32310 /* zext.h */, RISCV::ZEXT_H_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
10896 { 32310 /* zext.h */, RISCV::ZEXT_H_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR }, },
10897 { 32310 /* zext.h */, RISCV::PseudoZEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
10898 { 32317 /* zext.w */, RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR }, },
10899 { 32317 /* zext.w */, RISCV::PseudoZEXT_W, Convert__Reg1_0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
10900 { 32324 /* zip */, RISCV::ZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
10901 { 32328 /* zip16hp */, RISCV::ZIP16HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10902 { 32336 /* zip16p */, RISCV::ZIP16P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10903 { 32343 /* zip8hp */, RISCV::ZIP8HP, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10904 { 32350 /* zip8p */, RISCV::ZIP8P, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtP_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
10905};
10906
10907#include "llvm/Support/Debug.h"
10908#include "llvm/Support/Format.h"
10909
10910unsigned RISCVAsmParser::
10911MatchInstructionImpl(const OperandVector &Operands,
10912 MCInst &Inst,
10913 uint64_t &ErrorInfo,
10914 FeatureBitset &MissingFeatures,
10915 bool matchingInlineAsm, unsigned VariantID) {
10916 // Eliminate obvious mismatches.
10917 if (Operands.size() > 9) {
10918 ErrorInfo = 9;
10919 return Match_InvalidOperand;
10920 }
10921
10922 // Get the current feature set.
10923 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
10924
10925 // Get the instruction mnemonic, which is the first token.
10926 StringRef Mnemonic = ((RISCVOperand &)*Operands[0]).getToken();
10927
10928 // Process all MnemonicAliases to remap the mnemonic.
10929 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
10930
10931 // Some state to try to produce better error messages.
10932 bool HadMatchOtherThanFeatures = false;
10933 bool HadMatchOtherThanPredicate = false;
10934 unsigned RetCode = Match_InvalidOperand;
10935 MissingFeatures.set();
10936 // Set ErrorInfo to the operand that mismatches if it is
10937 // wrong for all instances of the instruction.
10938 ErrorInfo = ~0ULL;
10939 SmallBitVector OptionalOperandsMask(9);
10940 // Find the appropriate table for this asm variant.
10941 const MatchEntry *Start, *End;
10942 switch (VariantID) {
10943 default: llvm_unreachable("invalid variant!");
10944 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
10945 }
10946 // Search the table.
10947 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
10948
10949 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
10950 std::distance(MnemonicRange.first, MnemonicRange.second) <<
10951 " encodings with mnemonic '" << Mnemonic << "'\n");
10952
10953 // Return a more specific error code if no mnemonics match.
10954 if (MnemonicRange.first == MnemonicRange.second)
10955 return Match_MnemonicFail;
10956
10957 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
10958 it != ie; ++it) {
10959 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
10960 bool HasRequiredFeatures =
10961 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
10962 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
10963 << MII.getName(it->Opcode) << "\n");
10964 // equal_range guarantees that instruction mnemonic matches.
10965 assert(Mnemonic == it->getMnemonic());
10966 bool OperandsValid = true;
10967 OptionalOperandsMask.reset(0, 9);
10968 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx) {
10969 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
10970 DEBUG_WITH_TYPE("asm-matcher",
10971 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
10972 << " against actual operand at index " << ActualIdx);
10973 if (ActualIdx < Operands.size())
10974 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
10975 Operands[ActualIdx]->print(dbgs(), getContext().getAsmInfo()); dbgs() << "): ");
10976 else
10977 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
10978 if (ActualIdx >= Operands.size()) {
10979 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
10980 if (Formal == InvalidMatchClass) {
10981 OptionalOperandsMask.set(FormalIdx + 1, 9);
10982 break;
10983 }
10984 if (isSubclass(Formal, OptionalMatchClass)) {
10985 OptionalOperandsMask.set(FormalIdx + 1);
10986 continue;
10987 }
10988 OperandsValid = false;
10989 ErrorInfo = ActualIdx;
10990 break;
10991 }
10992 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
10993 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
10994 if (Diag == Match_Success) {
10995 DEBUG_WITH_TYPE("asm-matcher",
10996 dbgs() << "match success using generic matcher\n");
10997 ++ActualIdx;
10998 continue;
10999 }
11000 // If the generic handler indicates an invalid operand
11001 // failure, check for a special case.
11002 if (Diag != Match_Success) {
11003 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
11004 if (TargetDiag == Match_Success) {
11005 DEBUG_WITH_TYPE("asm-matcher",
11006 dbgs() << "match success using target matcher\n");
11007 ++ActualIdx;
11008 continue;
11009 }
11010 // If the target matcher returned a specific error code use
11011 // that, else use the one from the generic matcher.
11012 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
11013 Diag = TargetDiag;
11014 }
11015 // If current formal operand wasn't matched and it is optional
11016 // then try to match next formal operand
11017 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
11018 OptionalOperandsMask.set(FormalIdx + 1);
11019 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
11020 continue;
11021 }
11022 // If this operand is broken for all of the instances of this
11023 // mnemonic, keep track of it so we can report loc info.
11024 // If we already had a match that only failed due to a
11025 // target predicate, that diagnostic is preferred.
11026 if (!HadMatchOtherThanPredicate &&
11027 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
11028 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
11029 RetCode = Diag;
11030 ErrorInfo = ActualIdx;
11031 }
11032 // Otherwise, just reject this instance of the mnemonic.
11033 OperandsValid = false;
11034 break;
11035 }
11036
11037 if (!OperandsValid) {
11038 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11039 "operand mismatches, ignoring "
11040 "this opcode\n");
11041 continue;
11042 }
11043 if (!HasRequiredFeatures) {
11044 HadMatchOtherThanFeatures = true;
11045 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
11046 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
11047 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
11048 if (NewMissingFeatures[I])
11049 dbgs() << ' ' << I;
11050 dbgs() << "\n");
11051 if (NewMissingFeatures.count() <=
11052 MissingFeatures.count())
11053 MissingFeatures = NewMissingFeatures;
11054 continue;
11055 }
11056
11057 Inst.clear();
11058
11059 Inst.setOpcode(it->Opcode);
11060 // We have a potential match but have not rendered the operands.
11061 // Check the target predicate to handle any context sensitive
11062 // constraints.
11063 // For example, Ties that are referenced multiple times must be
11064 // checked here to ensure the input is the same for each match
11065 // constraints. If we leave it any later the ties will have been
11066 // canonicalized
11067 unsigned MatchResult;
11068 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
11069 Inst.clear();
11070 DEBUG_WITH_TYPE(
11071 "asm-matcher",
11072 dbgs() << "Early target match predicate failed with diag code "
11073 << MatchResult << "\n");
11074 RetCode = MatchResult;
11075 HadMatchOtherThanPredicate = true;
11076 continue;
11077 }
11078
11079 unsigned DefaultsOffset[9] = { 0 };
11080 assert(OptionalOperandsMask.size() == 9);
11081 for (unsigned i = 0, NumDefaults = 0; i < 8; ++i) {
11082 NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
11083 DefaultsOffset[i + 1] = NumDefaults;
11084 }
11085
11086 if (matchingInlineAsm) {
11087 convertToMapAndConstraints(it->ConvertFn, Operands);
11088 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
11089 DefaultsOffset, ErrorInfo))
11090 return Match_InvalidTiedOperand;
11091
11092 return Match_Success;
11093 }
11094
11095 // We have selected a definite instruction, convert the parsed
11096 // operands into the appropriate MCInst.
11097 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,
11098 OptionalOperandsMask, DefaultsOffset);
11099
11100 // We have a potential match. Check the target predicate to
11101 // handle any context sensitive constraints.
11102 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
11103 DEBUG_WITH_TYPE("asm-matcher",
11104 dbgs() << "Target match predicate failed with diag code "
11105 << MatchResult << "\n");
11106 Inst.clear();
11107 RetCode = MatchResult;
11108 HadMatchOtherThanPredicate = true;
11109 continue;
11110 }
11111
11112 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
11113 DefaultsOffset, ErrorInfo))
11114 return Match_InvalidTiedOperand;
11115
11116 DEBUG_WITH_TYPE(
11117 "asm-matcher",
11118 dbgs() << "Opcode result: complete match, selecting this opcode\n");
11119 return Match_Success;
11120 }
11121
11122 // Okay, we had no match. Try to return a useful error code.
11123 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
11124 return RetCode;
11125
11126 ErrorInfo = 0;
11127 return Match_MissingFeature;
11128}
11129
11130namespace {
11131 struct OperandMatchEntry {
11132 uint16_t Mnemonic;
11133 uint8_t OperandMask;
11134 uint16_t Class;
11135 uint8_t RequiredFeaturesIdx;
11136
11137 StringRef getMnemonic() const {
11138 return StringRef(MnemonicTable + Mnemonic + 1,
11139 MnemonicTable[Mnemonic]);
11140 }
11141 };
11142
11143 // Predicate for searching for an opcode.
11144 struct LessOpcodeOperand {
11145 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
11146 return LHS.getMnemonic() < RHS;
11147 }
11148 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
11149 return LHS < RHS.getMnemonic();
11150 }
11151 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
11152 return LHS.getMnemonic() < RHS.getMnemonic();
11153 }
11154 };
11155} // end anonymous namespace
11156
11157static const OperandMatchEntry OperandMatchTable[2101] = {
11158 /* Operand List Mnemonic, Mask, Operand Class, Features */
11159 { 0 /* .insn_b */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11160 { 8 /* .insn_ca */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11161 { 17 /* .insn_cb */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11162 { 26 /* .insn_ci */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11163 { 35 /* .insn_ciw */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11164 { 45 /* .insn_cj */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11165 { 54 /* .insn_cl */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11166 { 54 /* .insn_cl */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11167 { 63 /* .insn_cr */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11168 { 72 /* .insn_cs */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11169 { 72 /* .insn_cs */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11170 { 81 /* .insn_css */, 1 /* 0 */, MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtZca },
11171 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11172 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11173 { 91 /* .insn_i */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11174 { 99 /* .insn_j */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11175 { 99 /* .insn_j */, 4 /* 2 */, MCK_BareSImm21Lsb0, AMFBS_None },
11176 { 107 /* .insn_qc.eai */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11177 { 120 /* .insn_qc.eb */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11178 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11179 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11180 { 132 /* .insn_qc.ei */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11181 { 144 /* .insn_qc.ej */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11182 { 156 /* .insn_qc.es */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11183 { 156 /* .insn_qc.es */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_IsRV32 },
11184 { 168 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11185 { 168 /* .insn_r */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11186 { 176 /* .insn_r4 */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11187 { 185 /* .insn_s */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11188 { 185 /* .insn_s */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11189 { 193 /* .insn_sb */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11190 { 202 /* .insn_u */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11191 { 210 /* .insn_uj */, 1 /* 0 */, MCK_InsnDirectiveOpcode, AMFBS_None },
11192 { 210 /* .insn_uj */, 4 /* 2 */, MCK_BareSImm21Lsb0, AMFBS_None },
11193 { 239 /* add */, 8 /* 3 */, MCK_TPRelAddSymbol, AMFBS_None },
11194 { 250 /* addd */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11195 { 370 /* aif.amoaddg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11196 { 384 /* aif.amoaddg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11197 { 398 /* aif.amoaddl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11198 { 412 /* aif.amoaddl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11199 { 426 /* aif.amoandg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11200 { 440 /* aif.amoandg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11201 { 454 /* aif.amoandl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11202 { 468 /* aif.amoandl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11203 { 482 /* aif.amocmpswapg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11204 { 500 /* aif.amocmpswapg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11205 { 518 /* aif.amocmpswapl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11206 { 536 /* aif.amocmpswapl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11207 { 554 /* aif.amomaxg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11208 { 568 /* aif.amomaxg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11209 { 582 /* aif.amomaxl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11210 { 596 /* aif.amomaxl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11211 { 610 /* aif.amomaxug.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11212 { 625 /* aif.amomaxug.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11213 { 640 /* aif.amomaxul.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11214 { 655 /* aif.amomaxul.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11215 { 670 /* aif.amoming.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11216 { 684 /* aif.amoming.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11217 { 698 /* aif.amominl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11218 { 712 /* aif.amominl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11219 { 726 /* aif.amominug.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11220 { 741 /* aif.amominug.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11221 { 756 /* aif.amominul.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11222 { 771 /* aif.amominul.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11223 { 786 /* aif.amoorg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11224 { 799 /* aif.amoorg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11225 { 812 /* aif.amoorl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11226 { 825 /* aif.amoorl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11227 { 838 /* aif.amoswapg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11228 { 853 /* aif.amoswapg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11229 { 868 /* aif.amoswapl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11230 { 883 /* aif.amoswapl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11231 { 898 /* aif.amoxorg.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11232 { 912 /* aif.amoxorg.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11233 { 926 /* aif.amoxorl.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11234 { 940 /* aif.amoxorl.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11235 { 1047 /* aif.fadd.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11236 { 1072 /* aif.famoaddg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11237 { 1088 /* aif.famoaddl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11238 { 1104 /* aif.famoandg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11239 { 1120 /* aif.famoandl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11240 { 1136 /* aif.famomaxg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11241 { 1152 /* aif.famomaxg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11242 { 1168 /* aif.famomaxl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11243 { 1184 /* aif.famomaxl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11244 { 1200 /* aif.famomaxug.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11245 { 1217 /* aif.famomaxul.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11246 { 1234 /* aif.famoming.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11247 { 1250 /* aif.famoming.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11248 { 1266 /* aif.famominl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11249 { 1282 /* aif.famominl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11250 { 1298 /* aif.famominug.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11251 { 1315 /* aif.famominul.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11252 { 1332 /* aif.famoorg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11253 { 1347 /* aif.famoorl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11254 { 1362 /* aif.famoswapg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11255 { 1379 /* aif.famoswapl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11256 { 1396 /* aif.famoxorg.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11257 { 1412 /* aif.famoxorl.pi */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11258 { 1637 /* aif.fcvt.ps.pw */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11259 { 1652 /* aif.fcvt.ps.pwu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11260 { 1801 /* aif.fcvt.pw.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11261 { 1816 /* aif.fcvt.pwu.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11262 { 1977 /* aif.fdiv.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11263 { 2060 /* aif.fg32b.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11264 { 2073 /* aif.fg32h.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11265 { 2086 /* aif.fg32w.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11266 { 2099 /* aif.fgb.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11267 { 2110 /* aif.fgbg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11268 { 2122 /* aif.fgbl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11269 { 2134 /* aif.fgh.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11270 { 2145 /* aif.fghg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11271 { 2157 /* aif.fghl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11272 { 2169 /* aif.fgw.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11273 { 2180 /* aif.fgwg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11274 { 2192 /* aif.fgwl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11275 { 2352 /* aif.fmadd.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11276 { 2439 /* aif.fmsub.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11277 { 2464 /* aif.fmul.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11278 { 2531 /* aif.fnmadd.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11279 { 2545 /* aif.fnmsub.ps */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasXAIFET },
11280 { 2671 /* aif.fround.ps */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasXAIFET },
11281 { 2724 /* aif.fsc32b.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11282 { 2738 /* aif.fsc32h.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11283 { 2752 /* aif.fsc32w.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11284 { 2766 /* aif.fscb.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11285 { 2778 /* aif.fscbg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11286 { 2791 /* aif.fscbl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11287 { 2804 /* aif.fsch.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11288 { 2816 /* aif.fschg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11289 { 2829 /* aif.fschl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11290 { 2842 /* aif.fscw.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11291 { 2854 /* aif.fscwg.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11292 { 2867 /* aif.fscwl.ps */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11293 { 3055 /* aif.fsub.ps */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasXAIFET },
11294 { 3268 /* aif.sbg */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11295 { 3276 /* aif.sbl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11296 { 3284 /* aif.shg */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11297 { 3292 /* aif.shl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasXAIFET },
11298 { 3300 /* amoadd.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11299 { 3309 /* amoadd.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11300 { 3321 /* amoadd.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11301 { 3335 /* amoadd.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11302 { 3347 /* amoadd.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11303 { 3356 /* amoadd.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11304 { 3368 /* amoadd.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11305 { 3382 /* amoadd.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11306 { 3394 /* amoadd.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11307 { 3403 /* amoadd.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11308 { 3415 /* amoadd.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11309 { 3429 /* amoadd.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11310 { 3441 /* amoadd.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11311 { 3450 /* amoadd.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11312 { 3462 /* amoadd.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11313 { 3476 /* amoadd.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11314 { 3488 /* amoand.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11315 { 3497 /* amoand.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11316 { 3509 /* amoand.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11317 { 3523 /* amoand.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11318 { 3535 /* amoand.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11319 { 3544 /* amoand.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11320 { 3556 /* amoand.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11321 { 3570 /* amoand.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11322 { 3582 /* amoand.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11323 { 3591 /* amoand.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11324 { 3603 /* amoand.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11325 { 3617 /* amoand.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11326 { 3629 /* amoand.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11327 { 3638 /* amoand.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11328 { 3650 /* amoand.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11329 { 3664 /* amoand.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11330 { 3676 /* amocas.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11331 { 3685 /* amocas.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11332 { 3697 /* amocas.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11333 { 3711 /* amocas.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11334 { 3723 /* amocas.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11335 { 3723 /* amocas.d */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11336 { 3723 /* amocas.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11337 { 3732 /* amocas.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11338 { 3732 /* amocas.d.aq */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11339 { 3732 /* amocas.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11340 { 3744 /* amocas.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11341 { 3744 /* amocas.d.aqrl */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11342 { 3744 /* amocas.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11343 { 3758 /* amocas.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11344 { 3758 /* amocas.d.rl */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
11345 { 3758 /* amocas.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
11346 { 3770 /* amocas.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11347 { 3779 /* amocas.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11348 { 3791 /* amocas.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11349 { 3805 /* amocas.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
11350 { 3817 /* amocas.q */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11351 { 3817 /* amocas.q */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11352 { 3826 /* amocas.q.aq */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11353 { 3826 /* amocas.q.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11354 { 3838 /* amocas.q.aqrl */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11355 { 3838 /* amocas.q.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11356 { 3852 /* amocas.q.rl */, 3 /* 0, 1 */, MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
11357 { 3852 /* amocas.q.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
11358 { 3864 /* amocas.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11359 { 3873 /* amocas.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11360 { 3885 /* amocas.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11361 { 3899 /* amocas.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
11362 { 3911 /* amomax.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11363 { 3920 /* amomax.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11364 { 3932 /* amomax.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11365 { 3946 /* amomax.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11366 { 3958 /* amomax.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11367 { 3967 /* amomax.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11368 { 3979 /* amomax.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11369 { 3993 /* amomax.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11370 { 4005 /* amomax.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11371 { 4014 /* amomax.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11372 { 4026 /* amomax.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11373 { 4040 /* amomax.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11374 { 4052 /* amomax.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11375 { 4061 /* amomax.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11376 { 4073 /* amomax.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11377 { 4087 /* amomax.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11378 { 4099 /* amomaxu.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11379 { 4109 /* amomaxu.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11380 { 4122 /* amomaxu.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11381 { 4137 /* amomaxu.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11382 { 4150 /* amomaxu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11383 { 4160 /* amomaxu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11384 { 4173 /* amomaxu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11385 { 4188 /* amomaxu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11386 { 4201 /* amomaxu.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11387 { 4211 /* amomaxu.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11388 { 4224 /* amomaxu.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11389 { 4239 /* amomaxu.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11390 { 4252 /* amomaxu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11391 { 4262 /* amomaxu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11392 { 4275 /* amomaxu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11393 { 4290 /* amomaxu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11394 { 4303 /* amomin.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11395 { 4312 /* amomin.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11396 { 4324 /* amomin.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11397 { 4338 /* amomin.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11398 { 4350 /* amomin.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11399 { 4359 /* amomin.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11400 { 4371 /* amomin.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11401 { 4385 /* amomin.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11402 { 4397 /* amomin.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11403 { 4406 /* amomin.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11404 { 4418 /* amomin.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11405 { 4432 /* amomin.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11406 { 4444 /* amomin.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11407 { 4453 /* amomin.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11408 { 4465 /* amomin.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11409 { 4479 /* amomin.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11410 { 4491 /* amominu.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11411 { 4501 /* amominu.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11412 { 4514 /* amominu.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11413 { 4529 /* amominu.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11414 { 4542 /* amominu.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11415 { 4552 /* amominu.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11416 { 4565 /* amominu.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11417 { 4580 /* amominu.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11418 { 4593 /* amominu.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11419 { 4603 /* amominu.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11420 { 4616 /* amominu.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11421 { 4631 /* amominu.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11422 { 4644 /* amominu.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11423 { 4654 /* amominu.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11424 { 4667 /* amominu.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11425 { 4682 /* amominu.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11426 { 4695 /* amoor.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11427 { 4703 /* amoor.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11428 { 4714 /* amoor.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11429 { 4727 /* amoor.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11430 { 4738 /* amoor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11431 { 4746 /* amoor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11432 { 4757 /* amoor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11433 { 4770 /* amoor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11434 { 4781 /* amoor.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11435 { 4789 /* amoor.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11436 { 4800 /* amoor.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11437 { 4813 /* amoor.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11438 { 4824 /* amoor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11439 { 4832 /* amoor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11440 { 4843 /* amoor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11441 { 4856 /* amoor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11442 { 4867 /* amoswap.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11443 { 4877 /* amoswap.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11444 { 4890 /* amoswap.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11445 { 4905 /* amoswap.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11446 { 4918 /* amoswap.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11447 { 4928 /* amoswap.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11448 { 4941 /* amoswap.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11449 { 4956 /* amoswap.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11450 { 4969 /* amoswap.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11451 { 4979 /* amoswap.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11452 { 4992 /* amoswap.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11453 { 5007 /* amoswap.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11454 { 5020 /* amoswap.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11455 { 5030 /* amoswap.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11456 { 5043 /* amoswap.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11457 { 5058 /* amoswap.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11458 { 5071 /* amoxor.b */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11459 { 5080 /* amoxor.b.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11460 { 5092 /* amoxor.b.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11461 { 5106 /* amoxor.b.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11462 { 5118 /* amoxor.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11463 { 5127 /* amoxor.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11464 { 5139 /* amoxor.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11465 { 5153 /* amoxor.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo_IsRV64 },
11466 { 5165 /* amoxor.h */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11467 { 5174 /* amoxor.h.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11468 { 5186 /* amoxor.h.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11469 { 5200 /* amoxor.h.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
11470 { 5212 /* amoxor.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11471 { 5221 /* amoxor.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11472 { 5233 /* amoxor.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11473 { 5247 /* amoxor.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZaamo },
11474 { 5588 /* c.lbu */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11475 { 5588 /* c.lbu */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11476 { 5594 /* c.ld */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11477 { 5594 /* c.ld */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11478 { 5599 /* c.ldsp */, 1 /* 0 */, MCK_GPRPairNoX0RV32, AMFBS_HasStdExtZclsd_IsRV32 },
11479 { 5599 /* c.ldsp */, 1 /* 0 */, MCK_GPRPairNoX0RV32, AMFBS_HasStdExtZclsd_IsRV32 },
11480 { 5606 /* c.lh */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11481 { 5606 /* c.lh */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11482 { 5611 /* c.lhu */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11483 { 5611 /* c.lhu */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11484 { 5628 /* c.lw */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11485 { 5628 /* c.lw */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11486 { 5774 /* c.sb */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11487 { 5774 /* c.sb */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11488 { 5779 /* c.sd */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11489 { 5779 /* c.sd */, 1 /* 0 */, MCK_GPRPairCRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11490 { 5784 /* c.sdsp */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11491 { 5784 /* c.sdsp */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZclsd_IsRV32 },
11492 { 5809 /* c.sh */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11493 { 5809 /* c.sh */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZcb },
11494 { 5895 /* c.sw */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11495 { 5895 /* c.sw */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32_HasStdExtZca },
11496 { 5948 /* call */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
11497 { 5948 /* call */, 2 /* 1 */, MCK_CallSymbol, AMFBS_None },
11498 { 5953 /* cbo.clean */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
11499 { 5963 /* cbo.flush */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
11500 { 5973 /* cbo.inval */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
11501 { 5983 /* cbo.zero */, 1 /* 0 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicboz },
11502 { 6064 /* cm.pop */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11503 { 6064 /* cm.pop */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
11504 { 6071 /* cm.popret */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11505 { 6071 /* cm.popret */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
11506 { 6081 /* cm.popretz */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11507 { 6081 /* cm.popretz */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasStdExtZcmp },
11508 { 6092 /* cm.push */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasStdExtZcmp },
11509 { 6092 /* cm.push */, 1 /* 0 */, MCK_RegList, AMFBS_HasStdExtZcmp },
11510 { 6111 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11511 { 6111 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11512 { 6116 /* csrci */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11513 { 6122 /* csrr */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11514 { 6127 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11515 { 6127 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11516 { 6133 /* csrrci */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11517 { 6140 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11518 { 6140 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11519 { 6146 /* csrrsi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11520 { 6153 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11521 { 6153 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11522 { 6159 /* csrrwi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
11523 { 6166 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11524 { 6166 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11525 { 6171 /* csrsi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11526 { 6177 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11527 { 6177 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11528 { 6182 /* csrwi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
11529 { 7942 /* cv.elw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXCVelw_IsRV32 },
11530 { 8146 /* cv.lb */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11531 { 8152 /* cv.lbu */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11532 { 8159 /* cv.lh */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11533 { 8165 /* cv.lhu */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11534 { 8172 /* cv.lw */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11535 { 8821 /* cv.sb */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11536 { 9091 /* cv.sh */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11537 { 9706 /* cv.sw */, 2 /* 1 */, MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
11538 { 9838 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11539 { 9838 /* fabs.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11540 { 9845 /* fabs.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11541 { 9859 /* fabs.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11542 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11543 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11544 { 9866 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11545 { 9866 /* fadd.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11546 { 9866 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11547 { 9873 /* fadd.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11548 { 9873 /* fadd.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11549 { 9873 /* fadd.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11550 { 9880 /* fadd.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11551 { 9887 /* fadd.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11552 { 9887 /* fadd.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11553 { 9887 /* fadd.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11554 { 9894 /* fclass.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11555 { 9894 /* fclass.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11556 { 9903 /* fclass.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11557 { 9921 /* fclass.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11558 { 9930 /* fcvt.bf16.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfbfmin },
11559 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin_HasStdExtD },
11560 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11561 { 9942 /* fcvt.d.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11562 { 9942 /* fcvt.d.h */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11563 { 9942 /* fcvt.d.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11564 { 9942 /* fcvt.d.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11565 { 9942 /* fcvt.d.h */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11566 { 9951 /* fcvt.d.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11567 { 9951 /* fcvt.d.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11568 { 9951 /* fcvt.d.l */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11569 { 9960 /* fcvt.d.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11570 { 9960 /* fcvt.d.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11571 { 9960 /* fcvt.d.lu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11572 { 9970 /* fcvt.d.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11573 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
11574 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
11575 { 9979 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
11576 { 9979 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11577 { 9979 /* fcvt.d.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
11578 { 9979 /* fcvt.d.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
11579 { 9979 /* fcvt.d.s */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11580 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
11581 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
11582 { 9988 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11583 { 9988 /* fcvt.d.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
11584 { 9988 /* fcvt.d.w */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11585 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtD },
11586 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
11587 { 9997 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11588 { 9997 /* fcvt.d.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
11589 { 9997 /* fcvt.d.wu */, 1 /* 0 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11590 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfhmin_HasStdExtD },
11591 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11592 { 10007 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11593 { 10007 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
11594 { 10007 /* fcvt.h.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11595 { 10007 /* fcvt.h.d */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11596 { 10007 /* fcvt.h.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
11597 { 10016 /* fcvt.h.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11598 { 10016 /* fcvt.h.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11599 { 10016 /* fcvt.h.l */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11600 { 10025 /* fcvt.h.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11601 { 10025 /* fcvt.h.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11602 { 10025 /* fcvt.h.lu */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11603 { 10035 /* fcvt.h.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfhmin },
11604 { 10035 /* fcvt.h.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinxmin },
11605 { 10035 /* fcvt.h.s */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
11606 { 10035 /* fcvt.h.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
11607 { 10044 /* fcvt.h.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11608 { 10044 /* fcvt.h.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11609 { 10044 /* fcvt.h.w */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11610 { 10053 /* fcvt.h.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11611 { 10053 /* fcvt.h.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11612 { 10053 /* fcvt.h.wu */, 1 /* 0 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11613 { 10063 /* fcvt.l.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11614 { 10063 /* fcvt.l.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11615 { 10063 /* fcvt.l.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11616 { 10072 /* fcvt.l.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11617 { 10072 /* fcvt.l.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11618 { 10072 /* fcvt.l.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11619 { 10081 /* fcvt.l.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ_IsRV64 },
11620 { 10090 /* fcvt.l.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11621 { 10090 /* fcvt.l.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11622 { 10090 /* fcvt.l.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11623 { 10099 /* fcvt.lu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
11624 { 10099 /* fcvt.lu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11625 { 10099 /* fcvt.lu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
11626 { 10109 /* fcvt.lu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
11627 { 10109 /* fcvt.lu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
11628 { 10109 /* fcvt.lu.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
11629 { 10119 /* fcvt.lu.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ_IsRV64 },
11630 { 10129 /* fcvt.lu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11631 { 10129 /* fcvt.lu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11632 { 10129 /* fcvt.lu.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11633 { 10139 /* fcvt.q.d */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11634 { 10148 /* fcvt.q.l */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ_IsRV64 },
11635 { 10157 /* fcvt.q.lu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ_IsRV64 },
11636 { 10167 /* fcvt.q.s */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11637 { 10176 /* fcvt.q.w */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11638 { 10185 /* fcvt.q.wu */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtQ },
11639 { 10195 /* fcvt.s.bf16 */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfbfmin },
11640 { 10207 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11641 { 10207 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11642 { 10207 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
11643 { 10207 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11644 { 10207 /* fcvt.s.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11645 { 10207 /* fcvt.s.d */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
11646 { 10207 /* fcvt.s.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11647 { 10216 /* fcvt.s.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin },
11648 { 10216 /* fcvt.s.h */, 4 /* 2 */, MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin },
11649 { 10216 /* fcvt.s.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
11650 { 10216 /* fcvt.s.h */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
11651 { 10225 /* fcvt.s.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11652 { 10225 /* fcvt.s.l */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11653 { 10225 /* fcvt.s.l */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11654 { 10234 /* fcvt.s.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
11655 { 10234 /* fcvt.s.lu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
11656 { 10234 /* fcvt.s.lu */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
11657 { 10244 /* fcvt.s.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11658 { 10253 /* fcvt.s.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11659 { 10253 /* fcvt.s.w */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11660 { 10253 /* fcvt.s.w */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11661 { 10262 /* fcvt.s.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11662 { 10262 /* fcvt.s.wu */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11663 { 10262 /* fcvt.s.wu */, 1 /* 0 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11664 { 10272 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11665 { 10272 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11666 { 10272 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11667 { 10272 /* fcvt.w.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11668 { 10272 /* fcvt.w.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11669 { 10281 /* fcvt.w.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11670 { 10281 /* fcvt.w.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11671 { 10281 /* fcvt.w.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11672 { 10290 /* fcvt.w.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11673 { 10299 /* fcvt.w.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11674 { 10299 /* fcvt.w.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11675 { 10299 /* fcvt.w.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11676 { 10308 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11677 { 10308 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11678 { 10308 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11679 { 10308 /* fcvt.wu.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11680 { 10308 /* fcvt.wu.d */, 2 /* 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11681 { 10318 /* fcvt.wu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11682 { 10318 /* fcvt.wu.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11683 { 10318 /* fcvt.wu.h */, 2 /* 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11684 { 10328 /* fcvt.wu.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11685 { 10338 /* fcvt.wu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11686 { 10338 /* fcvt.wu.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11687 { 10338 /* fcvt.wu.s */, 2 /* 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11688 { 10348 /* fcvtmod.w.d */, 4 /* 2 */, MCK_RTZArg, AMFBS_HasStdExtZfa_HasStdExtD },
11689 { 10360 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11690 { 10360 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11691 { 10360 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11692 { 10360 /* fdiv.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11693 { 10360 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11694 { 10367 /* fdiv.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11695 { 10367 /* fdiv.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11696 { 10367 /* fdiv.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11697 { 10374 /* fdiv.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11698 { 10381 /* fdiv.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11699 { 10381 /* fdiv.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11700 { 10381 /* fdiv.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11701 { 10388 /* fence */, 3 /* 0, 1 */, MCK_FenceArg, AMFBS_None },
11702 { 10412 /* feq.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11703 { 10412 /* feq.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11704 { 10418 /* feq.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11705 { 10430 /* feq.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11706 { 10436 /* fge.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11707 { 10436 /* fge.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11708 { 10442 /* fge.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11709 { 10454 /* fge.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11710 { 10488 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11711 { 10488 /* fgt.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11712 { 10494 /* fgt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11713 { 10506 /* fgt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11714 { 10540 /* fld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
11715 { 10544 /* fle.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11716 { 10544 /* fle.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11717 { 10550 /* fle.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11718 { 10562 /* fle.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11719 { 10596 /* flh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasHalfFPLoadStoreMove },
11720 { 10600 /* fli.d */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtD },
11721 { 10606 /* fli.h */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh },
11722 { 10612 /* fli.q */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtQ },
11723 { 10618 /* fli.s */, 2 /* 1 */, MCK_LoadFPImm, AMFBS_HasStdExtZfa },
11724 { 10624 /* flq */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtQ },
11725 { 10628 /* flt.d */, 6 /* 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11726 { 10628 /* flt.d */, 6 /* 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11727 { 10634 /* flt.h */, 6 /* 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11728 { 10646 /* flt.s */, 6 /* 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11729 { 10680 /* flw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
11730 { 10684 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11731 { 10684 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11732 { 10684 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11733 { 10684 /* fmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11734 { 10684 /* fmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11735 { 10692 /* fmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11736 { 10692 /* fmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11737 { 10692 /* fmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11738 { 10700 /* fmadd.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11739 { 10708 /* fmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11740 { 10708 /* fmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11741 { 10708 /* fmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11742 { 10716 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11743 { 10716 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11744 { 10723 /* fmax.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11745 { 10737 /* fmax.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11746 { 10776 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11747 { 10776 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11748 { 10783 /* fmin.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11749 { 10797 /* fmin.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11750 { 10836 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11751 { 10836 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11752 { 10836 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11753 { 10836 /* fmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11754 { 10836 /* fmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11755 { 10844 /* fmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11756 { 10844 /* fmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11757 { 10844 /* fmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11758 { 10852 /* fmsub.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11759 { 10860 /* fmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11760 { 10860 /* fmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11761 { 10860 /* fmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11762 { 10868 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11763 { 10868 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11764 { 10868 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11765 { 10868 /* fmul.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11766 { 10868 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11767 { 10875 /* fmul.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11768 { 10875 /* fmul.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11769 { 10875 /* fmul.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11770 { 10882 /* fmul.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11771 { 10889 /* fmul.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11772 { 10889 /* fmul.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11773 { 10889 /* fmul.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11774 { 10896 /* fmv.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11775 { 10896 /* fmv.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11776 { 10910 /* fmv.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11777 { 10930 /* fmv.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11778 { 11004 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11779 { 11004 /* fneg.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11780 { 11011 /* fneg.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11781 { 11025 /* fneg.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11782 { 11032 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11783 { 11032 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11784 { 11032 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11785 { 11032 /* fnmadd.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11786 { 11032 /* fnmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11787 { 11041 /* fnmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11788 { 11041 /* fnmadd.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11789 { 11041 /* fnmadd.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11790 { 11050 /* fnmadd.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11791 { 11059 /* fnmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11792 { 11059 /* fnmadd.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11793 { 11059 /* fnmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11794 { 11068 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtD },
11795 { 11068 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11796 { 11068 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11797 { 11068 /* fnmsub.d */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11798 { 11068 /* fnmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11799 { 11077 /* fnmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11800 { 11077 /* fnmsub.h */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11801 { 11077 /* fnmsub.h */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11802 { 11086 /* fnmsub.q */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11803 { 11095 /* fnmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtF },
11804 { 11095 /* fnmsub.s */, 16 /* 4 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11805 { 11095 /* fnmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11806 { 11118 /* fround.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
11807 { 11127 /* fround.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
11808 { 11136 /* fround.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtQ },
11809 { 11145 /* fround.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa },
11810 { 11154 /* froundnx.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
11811 { 11165 /* froundnx.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
11812 { 11176 /* froundnx.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtQ },
11813 { 11187 /* froundnx.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfa },
11814 { 11209 /* fsd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
11815 { 11230 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11816 { 11230 /* fsgnj.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11817 { 11238 /* fsgnj.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11818 { 11254 /* fsgnj.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11819 { 11262 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11820 { 11262 /* fsgnjn.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11821 { 11271 /* fsgnjn.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11822 { 11289 /* fsgnjn.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11823 { 11298 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11824 { 11298 /* fsgnjx.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11825 { 11307 /* fsgnjx.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11826 { 11325 /* fsgnjx.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11827 { 11334 /* fsh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasHalfFPLoadStoreMove },
11828 { 11338 /* fsq */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtQ },
11829 { 11342 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtD },
11830 { 11342 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11831 { 11342 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11832 { 11342 /* fsqrt.d */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11833 { 11342 /* fsqrt.d */, 3 /* 0, 1 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11834 { 11350 /* fsqrt.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11835 { 11350 /* fsqrt.h */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11836 { 11350 /* fsqrt.h */, 3 /* 0, 1 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11837 { 11358 /* fsqrt.q */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11838 { 11366 /* fsqrt.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtF },
11839 { 11366 /* fsqrt.s */, 4 /* 2 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11840 { 11366 /* fsqrt.s */, 3 /* 0, 1 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11841 { 11385 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtD },
11842 { 11385 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
11843 { 11385 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
11844 { 11385 /* fsub.d */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
11845 { 11385 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
11846 { 11392 /* fsub.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfh },
11847 { 11392 /* fsub.h */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZhinx },
11848 { 11392 /* fsub.h */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
11849 { 11399 /* fsub.q */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtQ },
11850 { 11406 /* fsub.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtF },
11851 { 11406 /* fsub.s */, 8 /* 3 */, MCK_FRMArg, AMFBS_HasStdExtZfinx },
11852 { 11406 /* fsub.s */, 7 /* 0, 1, 2 */, MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
11853 { 11413 /* fsw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
11854 { 11465 /* hlv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11855 { 11471 /* hlv.bu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11856 { 11478 /* hlv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
11857 { 11484 /* hlv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11858 { 11490 /* hlv.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11859 { 11497 /* hlv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11860 { 11503 /* hlv.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
11861 { 11510 /* hlvx.hu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11862 { 11518 /* hlvx.wu */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11863 { 11526 /* hsv.b */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11864 { 11532 /* hsv.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
11865 { 11538 /* hsv.h */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11866 { 11544 /* hsv.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
11867 { 11550 /* j */, 1 /* 0 */, MCK_BareSImm21Lsb0, AMFBS_None },
11868 { 11552 /* jal */, 1 /* 0 */, MCK_BareSImm21Lsb0, AMFBS_None },
11869 { 11552 /* jal */, 2 /* 1 */, MCK_BareSImm21Lsb0, AMFBS_None },
11870 { 11556 /* jalr */, 32 /* 5 */, MCK_TLSDESCCallSymbol, AMFBS_None },
11871 { 11564 /* jump */, 1 /* 0 */, MCK_PseudoJumpSymbol, AMFBS_None },
11872 { 11569 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11873 { 11572 /* la.tls.gd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11874 { 11582 /* la.tls.ie */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11875 { 11592 /* lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11876 { 11592 /* lb */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11877 { 11592 /* lb */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11878 { 11595 /* lb.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11879 { 11601 /* lb.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11880 { 11609 /* lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11881 { 11609 /* lbu */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11882 { 11609 /* lbu */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11883 { 11613 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
11884 { 11613 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZilsd_IsRV32 },
11885 { 11613 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
11886 { 11613 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
11887 { 11613 /* ld */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
11888 { 11616 /* ld.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
11889 { 11622 /* ld.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
11890 { 11630 /* lga */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11891 { 11634 /* lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11892 { 11634 /* lh */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11893 { 11634 /* lh */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11894 { 11637 /* lh.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11895 { 11643 /* lh.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11896 { 11651 /* lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11897 { 11651 /* lhu */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11898 { 11651 /* lhu */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11899 { 11658 /* lla */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11900 { 11667 /* lr.d */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11901 { 11672 /* lr.d.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11902 { 11680 /* lr.d.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11903 { 11690 /* lr.d.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
11904 { 11698 /* lr.w */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11905 { 11703 /* lr.w.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11906 { 11711 /* lr.w.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11907 { 11721 /* lr.w.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
11908 { 11733 /* lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
11909 { 11733 /* lw */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11910 { 11733 /* lw */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
11911 { 11736 /* lw.aq */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11912 { 11742 /* lw.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
11913 { 11750 /* lwu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
11914 { 12589 /* mqrwacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11915 { 12597 /* mqwacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11916 { 12900 /* mvd */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11917 { 12913 /* nclip */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11918 { 12919 /* nclipi */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11919 { 12926 /* nclipiu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11920 { 12934 /* nclipr */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11921 { 12941 /* nclipri */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11922 { 12949 /* nclipriu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11923 { 12958 /* nclipru */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11924 { 12966 /* nclipu */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11925 { 13294 /* nds.vd4dots.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
11926 { 13309 /* nds.vd4dotsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
11927 { 13325 /* nds.vd4dotu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVDot },
11928 { 13358 /* nds.vfpmadb.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVPackFPH },
11929 { 13373 /* nds.vfpmadt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVPackFPH },
11930 { 13388 /* nds.vfwcvt.f.b.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
11931 { 13405 /* nds.vfwcvt.f.bu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
11932 { 13423 /* nds.vfwcvt.f.n.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
11933 { 13440 /* nds.vfwcvt.f.nu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntH },
11934 { 13476 /* nds.vle4.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntH },
11935 { 13487 /* nds.vln8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
11936 { 13487 /* nds.vln8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
11937 { 13498 /* nds.vlnu8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
11938 { 13498 /* nds.vlnu8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXAndesVSIntLoad },
11939 { 13514 /* negd */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11940 { 13532 /* nsra */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11941 { 13537 /* nsrai */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11942 { 13543 /* nsrar */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11943 { 13549 /* nsrari */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11944 { 13556 /* nsrl */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11945 { 13561 /* nsrli */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11946 { 13623 /* paadd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11947 { 13632 /* paadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11948 { 13641 /* paadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11949 { 13675 /* paaddu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11950 { 13685 /* paaddu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11951 { 13695 /* paaddu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11952 { 13723 /* paas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11953 { 13755 /* pabd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11954 { 13763 /* pabd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11955 { 13809 /* pabdu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11956 { 13818 /* pabdu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11957 { 13842 /* pabs.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11958 { 13850 /* pabs.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11959 { 13903 /* padd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11960 { 13911 /* padd.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11961 { 13920 /* padd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11962 { 13928 /* padd.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11963 { 13937 /* padd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11964 { 13945 /* padd.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11965 { 13984 /* pas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11966 { 14006 /* pasa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11967 { 14039 /* pasub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11968 { 14048 /* pasub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11969 { 14057 /* pasub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11970 { 14091 /* pasubu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11971 { 14101 /* pasubu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11972 { 14111 /* pasubu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11973 { 14151 /* pli.db */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11974 { 14158 /* pli.dh */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11975 { 14177 /* plui.dh */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11976 { 14468 /* pm2wadd.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11977 { 14478 /* pm2wadd.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11978 { 14489 /* pm2wadda.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11979 { 14500 /* pm2wadda.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11980 { 14512 /* pm2waddasu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11981 { 14525 /* pm2waddau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11982 { 14537 /* pm2waddsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11983 { 14549 /* pm2waddu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11984 { 14560 /* pm2wsub.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11985 { 14570 /* pm2wsub.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11986 { 14581 /* pm2wsuba.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11987 { 14592 /* pm2wsuba.hx */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11988 { 14840 /* pmax.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11989 { 14848 /* pmax.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11990 { 14856 /* pmax.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11991 { 14886 /* pmaxu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11992 { 14895 /* pmaxu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11993 { 14904 /* pmaxu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11994 { 15166 /* pmin.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11995 { 15174 /* pmin.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11996 { 15182 /* pmin.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11997 { 15212 /* pminu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11998 { 15221 /* pminu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
11999 { 15230 /* pminu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12000 { 15424 /* pmqrwacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12001 { 15435 /* pmqwacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12002 { 15453 /* pmseq.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12003 { 15462 /* pmseq.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12004 { 15471 /* pmseq.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12005 { 15505 /* pmseqz.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12006 { 15515 /* pmseqz.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12007 { 15525 /* pmseqz.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12008 { 15561 /* pmsgt.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12009 { 15570 /* pmsgt.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12010 { 15579 /* pmsgt.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12011 { 15613 /* pmsgtu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12012 { 15623 /* pmsgtu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12013 { 15633 /* pmsgtu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12014 { 15670 /* pmsgtz.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12015 { 15680 /* pmsgtz.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12016 { 15690 /* pmsgtz.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12017 { 15726 /* pmslt.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12018 { 15735 /* pmslt.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12019 { 15744 /* pmslt.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12020 { 15778 /* pmsltu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12021 { 15788 /* pmsltu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12022 { 15798 /* pmsltu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12023 { 15835 /* pmsltz.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12024 { 15845 /* pmsltz.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12025 { 15855 /* pmsltz.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12026 { 15892 /* pmsnez.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12027 { 15902 /* pmsnez.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12028 { 15912 /* pmsnez.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12029 { 16381 /* pmv.dbs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12030 { 16389 /* pmv.dhs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12031 { 16397 /* pmv.dws */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12032 { 16419 /* pnclip.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12033 { 16429 /* pnclip.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12034 { 16439 /* pnclipi.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12035 { 16449 /* pnclipi.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12036 { 16459 /* pnclipiu.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12037 { 16470 /* pnclipiu.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12038 { 16511 /* pnclipr.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12039 { 16522 /* pnclipr.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12040 { 16533 /* pnclipri.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12041 { 16544 /* pnclipri.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12042 { 16555 /* pnclipriu.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12043 { 16567 /* pnclipriu.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12044 { 16579 /* pnclipru.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12045 { 16591 /* pnclipru.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12046 { 16603 /* pnclipu.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12047 { 16614 /* pnclipu.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12048 { 16658 /* pncvt.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12049 { 16666 /* pncvt.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12050 { 16692 /* pncvth.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12051 { 16701 /* pncvth.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12052 { 16737 /* pneg.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12053 { 16745 /* pneg.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12054 { 16753 /* pneg.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12055 { 16775 /* pnsra.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12056 { 16784 /* pnsra.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12057 { 16793 /* pnsrai.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12058 { 16802 /* pnsrai.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12059 { 16811 /* pnsrar.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12060 { 16821 /* pnsrar.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12061 { 16831 /* pnsrari.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12062 { 16841 /* pnsrari.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12063 { 16851 /* pnsrl.bs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12064 { 16860 /* pnsrl.hs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12065 { 16869 /* pnsrli.b */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12066 { 16878 /* pnsrli.h */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12067 { 16896 /* ppaire.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12068 { 16906 /* ppaire.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12069 { 16944 /* ppaireo.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12070 { 16955 /* ppaireo.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12071 { 16995 /* ppairo.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12072 { 17005 /* ppairo.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12073 { 17043 /* ppairoe.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12074 { 17054 /* ppairoe.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12075 { 17096 /* predsum.dbs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12076 { 17108 /* predsum.dhs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12077 { 17154 /* predsumu.dbs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12078 { 17167 /* predsumu.dhs */, 2 /* 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12079 { 17237 /* psa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12080 { 17267 /* psabs.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12081 { 17276 /* psabs.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12082 { 17301 /* psadd.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12083 { 17310 /* psadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12084 { 17319 /* psadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12085 { 17353 /* psaddu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12086 { 17363 /* psaddu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12087 { 17373 /* psaddu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12088 { 17401 /* psas.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12089 { 17426 /* psati.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12090 { 17435 /* psati.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12091 { 17460 /* psext.dh.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12092 { 17471 /* psext.dw.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12093 { 17482 /* psext.dw.h */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12094 { 17523 /* psh1add.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12095 { 17534 /* psh1add.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12096 { 17573 /* psll.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12097 { 17582 /* psll.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12098 { 17591 /* psll.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12099 { 17624 /* pslli.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12100 { 17633 /* pslli.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12101 { 17642 /* pslli.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12102 { 17675 /* psra.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12103 { 17684 /* psra.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12104 { 17693 /* psra.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12105 { 17726 /* psrai.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12106 { 17735 /* psrai.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12107 { 17744 /* psrai.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12108 { 17769 /* psrari.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12109 { 17779 /* psrari.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12110 { 17815 /* psrl.dbs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12111 { 17824 /* psrl.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12112 { 17833 /* psrl.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12113 { 17866 /* psrli.db */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12114 { 17875 /* psrli.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12115 { 17884 /* psrli.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12116 { 17909 /* pssa.dhx */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12117 { 17934 /* pssh1sadd.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12118 { 17947 /* pssh1sadd.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12119 { 17984 /* pssha.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12120 { 17994 /* pssha.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12121 { 18022 /* psshar.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12122 { 18033 /* psshar.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12123 { 18064 /* psshl.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12124 { 18074 /* psshl.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12125 { 18102 /* psshlr.dhs */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12126 { 18113 /* psshlr.dws */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12127 { 18144 /* psslai.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12128 { 18154 /* psslai.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12129 { 18190 /* pssub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12130 { 18199 /* pssub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12131 { 18208 /* pssub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12132 { 18242 /* pssubu.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12133 { 18252 /* pssubu.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12134 { 18262 /* pssubu.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12135 { 18297 /* psub.db */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12136 { 18305 /* psub.dh */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12137 { 18313 /* psub.dw */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12138 { 18335 /* pusati.dh */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12139 { 18345 /* pusati.dw */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12140 { 18373 /* pwadd.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12141 { 18381 /* pwadd.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12142 { 18389 /* pwadda.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12143 { 18398 /* pwadda.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12144 { 18407 /* pwaddau.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12145 { 18417 /* pwaddau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12146 { 18427 /* pwaddu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12147 { 18436 /* pwaddu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12148 { 18445 /* pwcvt.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12149 { 18453 /* pwcvt.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12150 { 18461 /* pwcvth.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12151 { 18470 /* pwcvth.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12152 { 18499 /* pwcvtu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12153 { 18508 /* pwcvtu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12154 { 18537 /* pwmacc.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12155 { 18546 /* pwmaccsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12156 { 18557 /* pwmaccu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12157 { 18567 /* pwmul.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12158 { 18575 /* pwmul.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12159 { 18583 /* pwmulsu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12160 { 18593 /* pwmulsu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12161 { 18603 /* pwmulu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12162 { 18612 /* pwmulu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12163 { 18621 /* pwsla.bs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12164 { 18630 /* pwsla.hs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12165 { 18639 /* pwslai.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12166 { 18648 /* pwslai.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12167 { 18657 /* pwsll.bs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12168 { 18666 /* pwsll.hs */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12169 { 18675 /* pwslli.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12170 { 18684 /* pwslli.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12171 { 18693 /* pwsub.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12172 { 18701 /* pwsub.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12173 { 18709 /* pwsuba.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12174 { 18718 /* pwsuba.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12175 { 18727 /* pwsubau.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12176 { 18737 /* pwsubau.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12177 { 18747 /* pwsubu.b */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12178 { 18756 /* pwsubu.h */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12179 { 18765 /* pzext.dh.b */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12180 { 18776 /* pzext.dw.h */, 3 /* 0, 1 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12181 { 19202 /* qc.cm.pop */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12182 { 19202 /* qc.cm.pop */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
12183 { 19212 /* qc.cm.popret */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12184 { 19212 /* qc.cm.popret */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
12185 { 19225 /* qc.cm.popretz */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12186 { 19225 /* qc.cm.popretz */, 2 /* 1 */, MCK_StackAdj, AMFBS_HasVendorXqccmp },
12187 { 19239 /* qc.cm.push */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasVendorXqccmp },
12188 { 19239 /* qc.cm.push */, 1 /* 0 */, MCK_RegList, AMFBS_HasVendorXqccmp },
12189 { 19250 /* qc.cm.pushfp */, 2 /* 1 */, MCK_NegStackAdj, AMFBS_HasVendorXqccmp },
12190 { 19250 /* qc.cm.pushfp */, 1 /* 0 */, MCK_RegListS0, AMFBS_HasVendorXqccmp },
12191 { 19437 /* qc.e.lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12192 { 19445 /* qc.e.lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12193 { 19454 /* qc.e.lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12194 { 19462 /* qc.e.lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12195 { 19471 /* qc.e.li */, 2 /* 1 */, MCK_BareSymbolQC_E_LI, AMFBS_HasVendorXqcili_IsRV32 },
12196 { 19479 /* qc.e.lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12197 { 19506 /* qc.e.sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12198 { 19514 /* qc.e.sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12199 { 19522 /* qc.e.sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasVendorXqcilo_HasVendorXqcili_IsRV32 },
12200 { 20654 /* sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12201 { 20654 /* sb */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12202 { 20654 /* sb */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12203 { 20657 /* sb.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12204 { 20665 /* sb.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12205 { 20671 /* sc.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12206 { 20676 /* sc.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12207 { 20684 /* sc.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12208 { 20694 /* sc.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc_IsRV64 },
12209 { 20702 /* sc.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12210 { 20707 /* sc.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12211 { 20715 /* sc.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12212 { 20725 /* sc.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalrsc },
12213 { 20741 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
12214 { 20741 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtZilsd_IsRV32 },
12215 { 20741 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12216 { 20741 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12217 { 20741 /* sd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtZilsd_IsRV32 },
12218 { 20744 /* sd.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12219 { 20752 /* sd.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
12220 { 21231 /* sf.vfexp.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfexpAny },
12221 { 21242 /* sf.vfexpa.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfexpa },
12222 { 21254 /* sf.vfnrclip.x.f.qf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
12223 { 21273 /* sf.vfnrclip.xu.f.qf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
12224 { 21310 /* sf.vlte16 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12225 { 21320 /* sf.vlte32 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12226 { 21330 /* sf.vlte64 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12227 { 21340 /* sf.vlte8 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12228 { 21517 /* sf.vsettnt */, 4 /* 2 */, MCK_XSfmmVType, AMFBS_HasVendorXSfmmbase },
12229 { 21528 /* sf.vste16 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12230 { 21538 /* sf.vste32 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12231 { 21548 /* sf.vste64 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12232 { 21558 /* sf.vste8 */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVendorXSfmmbase },
12233 { 21672 /* sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12234 { 21672 /* sh */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12235 { 21672 /* sh */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12236 { 21675 /* sh.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12237 { 21683 /* sh.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12238 { 22284 /* ssamoswap.d */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12239 { 22296 /* ssamoswap.d.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12240 { 22311 /* ssamoswap.d.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12241 { 22328 /* ssamoswap.d.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
12242 { 22343 /* ssamoswap.w */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12243 { 22355 /* ssamoswap.w.aq */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12244 { 22370 /* ssamoswap.w.aqrl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12245 { 22387 /* ssamoswap.w.rl */, 4 /* 2 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
12246 { 22476 /* subd */, 7 /* 0, 1, 2 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
12247 { 22486 /* sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
12248 { 22486 /* sw */, 16 /* 4 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12249 { 22486 /* sw */, 32 /* 5 */, MCK_QCAccessSymbol, AMFBS_IsRV32 },
12250 { 22489 /* sw.aqrl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12251 { 22497 /* sw.rl */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
12252 { 22503 /* tail */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
12253 { 23491 /* th.vmaqa.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12254 { 23503 /* th.vmaqa.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12255 { 23515 /* th.vmaqasu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12256 { 23529 /* th.vmaqasu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12257 { 23543 /* th.vmaqau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12258 { 23556 /* th.vmaqau.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12259 { 23569 /* th.vmaqaus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
12260 { 23649 /* vaadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12261 { 23658 /* vaadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12262 { 23667 /* vaaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12263 { 23677 /* vaaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12264 { 23687 /* vabd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12265 { 23695 /* vabdu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12266 { 23704 /* vabs.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
12267 { 23738 /* vadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12268 { 23746 /* vadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12269 { 23754 /* vadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12270 { 23873 /* vand.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12271 { 23881 /* vand.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12272 { 23889 /* vand.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12273 { 23897 /* vandn.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12274 { 23906 /* vandn.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12275 { 23915 /* vasub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12276 { 23924 /* vasub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12277 { 23933 /* vasubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12278 { 23943 /* vasubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12279 { 23953 /* vbrev.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12280 { 23961 /* vbrev8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12281 { 23970 /* vclmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12282 { 23980 /* vclmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12283 { 23990 /* vclmulh.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12284 { 24001 /* vclmulh.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
12285 { 24012 /* vclz.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12286 { 24032 /* vcpop.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12287 { 24040 /* vcpop.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12288 { 24048 /* vctz.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
12289 { 24055 /* vdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12290 { 24063 /* vdiv.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12291 { 24071 /* vdivu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12292 { 24080 /* vdivu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12293 { 24089 /* vdot4a.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12294 { 24099 /* vdot4a.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12295 { 24109 /* vdot4asu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12296 { 24121 /* vdot4asu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12297 { 24133 /* vdot4au.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12298 { 24144 /* vdot4au.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12299 { 24155 /* vdot4aus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvdot4a8i },
12300 { 24167 /* vf8wimmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12301 { 24181 /* vf8wmmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12302 { 24194 /* vfabs.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12303 { 24202 /* vfadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12304 { 24211 /* vfadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12305 { 24220 /* vfbdota.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbdota32f },
12306 { 24231 /* vfclass.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12307 { 24241 /* vfcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12308 { 24253 /* vfcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12309 { 24266 /* vfcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12310 { 24282 /* vfcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12311 { 24299 /* vfcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12312 { 24311 /* vfcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12313 { 24324 /* vfdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12314 { 24333 /* vfdiv.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12315 { 24342 /* vfirst.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12316 { 24351 /* vfmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12317 { 24361 /* vfmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12318 { 24371 /* vfmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12319 { 24381 /* vfmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12320 { 24391 /* vfmax.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12321 { 24400 /* vfmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12322 { 24421 /* vfmin.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12323 { 24430 /* vfmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12324 { 24450 /* vfmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12325 { 24460 /* vfmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12326 { 24470 /* vfmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12327 { 24480 /* vfmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12328 { 24490 /* vfmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12329 { 24499 /* vfmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12330 { 24535 /* vfncvt.f.f.q */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
12331 { 24548 /* vfncvt.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12332 { 24561 /* vfncvt.f.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12333 { 24574 /* vfncvt.f.xu.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12334 { 24588 /* vfncvt.rod.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12335 { 24605 /* vfncvt.rtz.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12336 { 24622 /* vfncvt.rtz.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12337 { 24640 /* vfncvt.sat.f.f.q */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
12338 { 24657 /* vfncvt.x.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12339 { 24670 /* vfncvt.xu.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12340 { 24684 /* vfncvtbf16.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfminOrZvfofp8min },
12341 { 24701 /* vfncvtbf16.sat.f.f.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfofp8min },
12342 { 24722 /* vfneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12343 { 24730 /* vfnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12344 { 24741 /* vfnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12345 { 24752 /* vfnmadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12346 { 24763 /* vfnmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12347 { 24774 /* vfnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12348 { 24785 /* vfnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12349 { 24796 /* vfnmsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12350 { 24807 /* vfnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12351 { 24818 /* vfqimmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12352 { 24831 /* vfqmmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12353 { 24843 /* vfqwbdota.alt.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwbdota8f },
12354 { 24860 /* vfqwbdota.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwbdota8f },
12355 { 24873 /* vfqwdota.alt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwdota8f },
12356 { 24889 /* vfqwdota.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfqwdota8f },
12357 { 24901 /* vfrdiv.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12358 { 24911 /* vfrec7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12359 { 24920 /* vfredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12360 { 24932 /* vfredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12361 { 24944 /* vfredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12362 { 24957 /* vfredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12363 { 24970 /* vfrsqrt7.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12364 { 24981 /* vfrsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12365 { 24991 /* vfsgnj.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12366 { 25001 /* vfsgnj.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12367 { 25011 /* vfsgnjn.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12368 { 25022 /* vfsgnjn.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12369 { 25033 /* vfsgnjx.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12370 { 25044 /* vfsgnjx.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12371 { 25055 /* vfslide1down.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12372 { 25071 /* vfslide1up.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12373 { 25085 /* vfsqrt.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12374 { 25094 /* vfsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12375 { 25103 /* vfsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12376 { 25112 /* vfwadd.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12377 { 25122 /* vfwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12378 { 25132 /* vfwadd.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12379 { 25142 /* vfwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12380 { 25152 /* vfwbdota.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfwbdota16bf },
12381 { 25164 /* vfwcvt.f.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12382 { 25177 /* vfwcvt.f.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12383 { 25190 /* vfwcvt.f.xu.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12384 { 25204 /* vfwcvt.rtz.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12385 { 25221 /* vfwcvt.rtz.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12386 { 25239 /* vfwcvt.x.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12387 { 25252 /* vfwcvt.xu.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12388 { 25266 /* vfwcvtbf16.f.f.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfminOrZvfofp8min },
12389 { 25283 /* vfwdota.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfwdota16bf },
12390 { 25294 /* vfwimmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12391 { 25307 /* vfwmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12392 { 25318 /* vfwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12393 { 25329 /* vfwmaccbf16.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
12394 { 25344 /* vfwmaccbf16.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
12395 { 25359 /* vfwmmacc.vv */, 8 /* 3 */, MCK_RVVScaleRegOpOperand, AMFBS_HasStdExtZvvfmm },
12396 { 25371 /* vfwmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12397 { 25382 /* vfwmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12398 { 25393 /* vfwmul.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12399 { 25403 /* vfwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12400 { 25413 /* vfwnmacc.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12401 { 25425 /* vfwnmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12402 { 25437 /* vfwnmsac.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12403 { 25449 /* vfwnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12404 { 25461 /* vfwredosum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12405 { 25475 /* vfwredusum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12406 { 25489 /* vfwsub.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12407 { 25499 /* vfwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12408 { 25509 /* vfwsub.wf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12409 { 25519 /* vfwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12410 { 25565 /* vid.v */, 2 /* 1 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12411 { 25571 /* viota.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12412 { 25579 /* vl1r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12413 { 25586 /* vl1re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12414 { 25596 /* vl1re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12415 { 25606 /* vl1re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12416 { 25616 /* vl1re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12417 { 25625 /* vl2r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12418 { 25632 /* vl2re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12419 { 25642 /* vl2re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12420 { 25652 /* vl2re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12421 { 25662 /* vl2re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12422 { 25671 /* vl4r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12423 { 25678 /* vl4re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12424 { 25688 /* vl4re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12425 { 25698 /* vl4re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12426 { 25708 /* vl4re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12427 { 25717 /* vl8r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12428 { 25724 /* vl8re16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12429 { 25734 /* vl8re32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12430 { 25744 /* vl8re64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12431 { 25754 /* vl8re8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12432 { 25763 /* vle16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12433 { 25763 /* vle16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12434 { 25771 /* vle16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12435 { 25771 /* vle16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12436 { 25781 /* vle32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12437 { 25781 /* vle32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12438 { 25789 /* vle32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12439 { 25789 /* vle32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12440 { 25799 /* vle64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12441 { 25799 /* vle64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12442 { 25807 /* vle64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12443 { 25807 /* vle64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12444 { 25817 /* vle8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12445 { 25817 /* vle8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12446 { 25824 /* vle8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12447 { 25824 /* vle8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12448 { 25833 /* vlm.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12449 { 25839 /* vloxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12450 { 25839 /* vloxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12451 { 25850 /* vloxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12452 { 25850 /* vloxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12453 { 25861 /* vloxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12454 { 25861 /* vloxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12455 { 25872 /* vloxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12456 { 25872 /* vloxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12457 { 25882 /* vloxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12458 { 25882 /* vloxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12459 { 25897 /* vloxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12460 { 25897 /* vloxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12461 { 25912 /* vloxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12462 { 25912 /* vloxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12463 { 25927 /* vloxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12464 { 25927 /* vloxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12465 { 25941 /* vloxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12466 { 25941 /* vloxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12467 { 25956 /* vloxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12468 { 25956 /* vloxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12469 { 25971 /* vloxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12470 { 25971 /* vloxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12471 { 25986 /* vloxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12472 { 25986 /* vloxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12473 { 26000 /* vloxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12474 { 26000 /* vloxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12475 { 26015 /* vloxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12476 { 26015 /* vloxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12477 { 26030 /* vloxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12478 { 26030 /* vloxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12479 { 26045 /* vloxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12480 { 26045 /* vloxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12481 { 26059 /* vloxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12482 { 26059 /* vloxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12483 { 26074 /* vloxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12484 { 26074 /* vloxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12485 { 26089 /* vloxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12486 { 26089 /* vloxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12487 { 26104 /* vloxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12488 { 26104 /* vloxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12489 { 26118 /* vloxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12490 { 26118 /* vloxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12491 { 26133 /* vloxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12492 { 26133 /* vloxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12493 { 26148 /* vloxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12494 { 26148 /* vloxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12495 { 26163 /* vloxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12496 { 26163 /* vloxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12497 { 26177 /* vloxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12498 { 26177 /* vloxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12499 { 26192 /* vloxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12500 { 26192 /* vloxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12501 { 26207 /* vloxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12502 { 26207 /* vloxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12503 { 26222 /* vloxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12504 { 26222 /* vloxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12505 { 26236 /* vloxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12506 { 26236 /* vloxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12507 { 26251 /* vloxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12508 { 26251 /* vloxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12509 { 26266 /* vloxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12510 { 26266 /* vloxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12511 { 26281 /* vloxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12512 { 26281 /* vloxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12513 { 26295 /* vlse16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12514 { 26295 /* vlse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12515 { 26304 /* vlse32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12516 { 26304 /* vlse32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12517 { 26313 /* vlse64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12518 { 26313 /* vlse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12519 { 26322 /* vlse8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12520 { 26322 /* vlse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12521 { 26330 /* vlseg2e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12522 { 26330 /* vlseg2e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12523 { 26342 /* vlseg2e16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12524 { 26342 /* vlseg2e16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12525 { 26356 /* vlseg2e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12526 { 26356 /* vlseg2e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12527 { 26368 /* vlseg2e32ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12528 { 26368 /* vlseg2e32ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12529 { 26382 /* vlseg2e64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12530 { 26382 /* vlseg2e64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12531 { 26394 /* vlseg2e64ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12532 { 26394 /* vlseg2e64ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12533 { 26408 /* vlseg2e8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12534 { 26408 /* vlseg2e8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12535 { 26419 /* vlseg2e8ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12536 { 26419 /* vlseg2e8ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12537 { 26432 /* vlseg3e16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12538 { 26432 /* vlseg3e16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12539 { 26444 /* vlseg3e16ff.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12540 { 26444 /* vlseg3e16ff.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12541 { 26458 /* vlseg3e32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12542 { 26458 /* vlseg3e32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
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12736 { 27725 /* vluxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12737 { 27739 /* vluxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12738 { 27739 /* vluxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12739 { 27754 /* vluxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12740 { 27754 /* vluxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12741 { 27769 /* vluxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12742 { 27769 /* vluxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12743 { 27784 /* vluxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12744 { 27784 /* vluxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12745 { 27798 /* vluxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12746 { 27798 /* vluxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12747 { 27813 /* vluxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12748 { 27813 /* vluxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12749 { 27828 /* vluxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12750 { 27828 /* vluxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12751 { 27843 /* vluxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12752 { 27843 /* vluxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12753 { 27857 /* vmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12754 { 27866 /* vmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12755 { 27932 /* vmadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12756 { 27941 /* vmadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12757 { 27969 /* vmax.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12758 { 27977 /* vmax.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12759 { 27985 /* vmaxu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12760 { 27994 /* vmaxu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12761 { 28044 /* vmfeq.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12762 { 28053 /* vmfeq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12763 { 28062 /* vmfge.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12764 { 28071 /* vmfge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12765 { 28080 /* vmfgt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12766 { 28089 /* vmfgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12767 { 28098 /* vmfle.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12768 { 28107 /* vmfle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12769 { 28116 /* vmflt.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12770 { 28125 /* vmflt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12771 { 28134 /* vmfne.vf */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12772 { 28143 /* vmfne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
12773 { 28152 /* vmin.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12774 { 28160 /* vmin.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12775 { 28168 /* vminu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12776 { 28177 /* vminu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12777 { 28285 /* vmsbf.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12778 { 28293 /* vmseq.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12779 { 28302 /* vmseq.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12780 { 28311 /* vmseq.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12781 { 28328 /* vmsge.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12782 { 28337 /* vmsge.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12783 { 28346 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12784 { 28346 /* vmsge.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12785 { 28355 /* vmsgeu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12786 { 28365 /* vmsgeu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12787 { 28375 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12788 { 28375 /* vmsgeu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12789 { 28385 /* vmsgt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12790 { 28394 /* vmsgt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12791 { 28403 /* vmsgt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12792 { 28412 /* vmsgtu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12793 { 28422 /* vmsgtu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12794 { 28432 /* vmsgtu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12795 { 28442 /* vmsif.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12796 { 28450 /* vmsle.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12797 { 28459 /* vmsle.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12798 { 28468 /* vmsle.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12799 { 28477 /* vmsleu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12800 { 28487 /* vmsleu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12801 { 28497 /* vmsleu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12802 { 28507 /* vmslt.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12803 { 28516 /* vmslt.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12804 { 28525 /* vmslt.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12805 { 28534 /* vmsltu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12806 { 28544 /* vmsltu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12807 { 28554 /* vmsltu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12808 { 28564 /* vmsne.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12809 { 28573 /* vmsne.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12810 { 28582 /* vmsne.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12811 { 28591 /* vmsof.m */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12812 { 28599 /* vmtl.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
12813 { 28599 /* vmtl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
12814 { 28599 /* vmtl.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmtls },
12815 { 28599 /* vmtl.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
12816 { 28599 /* vmtl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
12817 { 28606 /* vmts.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
12818 { 28606 /* vmts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
12819 { 28606 /* vmts.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmtls },
12820 { 28606 /* vmts.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmtls },
12821 { 28606 /* vmts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmtls },
12822 { 28613 /* vmttl.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
12823 { 28613 /* vmttl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
12824 { 28613 /* vmttl.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmttls },
12825 { 28613 /* vmttl.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
12826 { 28613 /* vmttl.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
12827 { 28621 /* vmtts.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
12828 { 28621 /* vmtts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
12829 { 28621 /* vmtts.v */, 8 /* 3 */, MCK_TileLambda, AMFBS_HasStdExtZvvmttls },
12830 { 28621 /* vmtts.v */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvvmttls },
12831 { 28621 /* vmtts.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZvvmttls },
12832 { 28629 /* vmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12833 { 28637 /* vmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12834 { 28645 /* vmulh.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12835 { 28654 /* vmulh.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12836 { 28663 /* vmulhsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12837 { 28674 /* vmulhsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12838 { 28685 /* vmulhu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12839 { 28695 /* vmulhu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12840 { 28796 /* vnclip.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12841 { 28806 /* vnclip.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12842 { 28816 /* vnclip.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12843 { 28826 /* vnclipu.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12844 { 28837 /* vnclipu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12845 { 28848 /* vnclipu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12846 { 28859 /* vncvt.x.x.w */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12847 { 28871 /* vneg.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12848 { 28878 /* vnmsac.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12849 { 28888 /* vnmsac.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12850 { 28898 /* vnmsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12851 { 28908 /* vnmsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12852 { 28918 /* vnot.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12853 { 28925 /* vnsra.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12854 { 28934 /* vnsra.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12855 { 28943 /* vnsra.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12856 { 28952 /* vnsrl.wi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12857 { 28961 /* vnsrl.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12858 { 28970 /* vnsrl.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12859 { 28979 /* vor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12860 { 28986 /* vor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12861 { 28993 /* vor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12862 { 29000 /* vpaire.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
12863 { 29010 /* vpairo.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
12864 { 29031 /* vqwbdotas.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i },
12865 { 29044 /* vqwbdotau.vv */, 16 /* 4 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwbdota8iOrZvqwbdota16i },
12866 { 29057 /* vqwdotas.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i },
12867 { 29069 /* vqwdotau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvqwdota8iOrZvqwdota16i },
12868 { 29081 /* vredand.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12869 { 29092 /* vredmax.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12870 { 29103 /* vredmaxu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12871 { 29115 /* vredmin.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12872 { 29126 /* vredminu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12873 { 29138 /* vredor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12874 { 29148 /* vredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12875 { 29159 /* vredxor.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12876 { 29170 /* vrem.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12877 { 29178 /* vrem.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12878 { 29186 /* vremu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12879 { 29195 /* vremu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12880 { 29204 /* vrev8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12881 { 29212 /* vrgather.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12882 { 29224 /* vrgather.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12883 { 29236 /* vrgather.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12884 { 29248 /* vrgatherei16.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12885 { 29264 /* vrol.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12886 { 29272 /* vrol.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12887 { 29280 /* vror.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12888 { 29288 /* vror.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12889 { 29296 /* vror.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
12890 { 29304 /* vrsub.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12891 { 29313 /* vrsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12892 { 29322 /* vs1r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12893 { 29329 /* vs2r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12894 { 29336 /* vs4r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12895 { 29343 /* vs8r.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12896 { 29350 /* vsadd.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12897 { 29359 /* vsadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12898 { 29368 /* vsadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12899 { 29377 /* vsaddu.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12900 { 29387 /* vsaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12901 { 29397 /* vsaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12902 { 29425 /* vse16.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12903 { 29425 /* vse16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12904 { 29433 /* vse32.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12905 { 29433 /* vse32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12906 { 29441 /* vse64.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
12907 { 29441 /* vse64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
12908 { 29449 /* vse8.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12909 { 29449 /* vse8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12910 { 29456 /* vsetivli */, 4 /* 2 */, MCK_VTypeI10, AMFBS_HasVInstructions },
12911 { 29472 /* vsetvli */, 4 /* 2 */, MCK_VTypeI11, AMFBS_HasVInstructions },
12912 { 29480 /* vsext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12913 { 29490 /* vsext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12914 { 29500 /* vsext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12915 { 29543 /* vslide1down.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12916 { 29558 /* vslide1up.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12917 { 29571 /* vslidedown.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12918 { 29585 /* vslidedown.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12919 { 29599 /* vslideup.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12920 { 29611 /* vslideup.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12921 { 29623 /* vsll.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12922 { 29631 /* vsll.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12923 { 29639 /* vsll.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12924 { 29647 /* vsm.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12925 { 29699 /* vsmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12926 { 29708 /* vsmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12927 { 29717 /* vsoxei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12928 { 29717 /* vsoxei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12929 { 29728 /* vsoxei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12930 { 29728 /* vsoxei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12931 { 29739 /* vsoxei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12932 { 29739 /* vsoxei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
12933 { 29750 /* vsoxei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12934 { 29750 /* vsoxei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12935 { 29760 /* vsoxseg2ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12936 { 29760 /* vsoxseg2ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12937 { 29775 /* vsoxseg2ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12938 { 29775 /* vsoxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12939 { 29790 /* vsoxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12940 { 29790 /* vsoxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
12941 { 29805 /* vsoxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
12942 { 29805 /* vsoxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
12943 { 29819 /* vsoxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
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13140 { 31108 /* vsuxseg2ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13141 { 31123 /* vsuxseg2ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13142 { 31123 /* vsuxseg2ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13143 { 31138 /* vsuxseg2ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13144 { 31138 /* vsuxseg2ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13145 { 31152 /* vsuxseg3ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13146 { 31152 /* vsuxseg3ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13147 { 31167 /* vsuxseg3ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13148 { 31167 /* vsuxseg3ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13149 { 31182 /* vsuxseg3ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13150 { 31182 /* vsuxseg3ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13151 { 31197 /* vsuxseg3ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13152 { 31197 /* vsuxseg3ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13153 { 31211 /* vsuxseg4ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13154 { 31211 /* vsuxseg4ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13155 { 31226 /* vsuxseg4ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13156 { 31226 /* vsuxseg4ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13157 { 31241 /* vsuxseg4ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13158 { 31241 /* vsuxseg4ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13159 { 31256 /* vsuxseg4ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13160 { 31256 /* vsuxseg4ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13161 { 31270 /* vsuxseg5ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13162 { 31270 /* vsuxseg5ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13163 { 31285 /* vsuxseg5ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13164 { 31285 /* vsuxseg5ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13165 { 31300 /* vsuxseg5ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13166 { 31300 /* vsuxseg5ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13167 { 31315 /* vsuxseg5ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13168 { 31315 /* vsuxseg5ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13169 { 31329 /* vsuxseg6ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13170 { 31329 /* vsuxseg6ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13171 { 31344 /* vsuxseg6ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13172 { 31344 /* vsuxseg6ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13173 { 31359 /* vsuxseg6ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13174 { 31359 /* vsuxseg6ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13175 { 31374 /* vsuxseg6ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13176 { 31374 /* vsuxseg6ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13177 { 31388 /* vsuxseg7ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13178 { 31388 /* vsuxseg7ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13179 { 31403 /* vsuxseg7ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13180 { 31403 /* vsuxseg7ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13181 { 31418 /* vsuxseg7ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13182 { 31418 /* vsuxseg7ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13183 { 31433 /* vsuxseg7ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13184 { 31433 /* vsuxseg7ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13185 { 31447 /* vsuxseg8ei16.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13186 { 31447 /* vsuxseg8ei16.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13187 { 31462 /* vsuxseg8ei32.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13188 { 31462 /* vsuxseg8ei32.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13189 { 31477 /* vsuxseg8ei64.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13190 { 31477 /* vsuxseg8ei64.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
13191 { 31492 /* vsuxseg8ei8.v */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13192 { 31492 /* vsuxseg8ei8.v */, 2 /* 1 */, MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
13193 { 31525 /* vunzipe.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13194 { 31535 /* vunzipo.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13195 { 31545 /* vwabda.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
13196 { 31555 /* vwabdau.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvabd },
13197 { 31566 /* vwadd.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13198 { 31575 /* vwadd.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13199 { 31584 /* vwadd.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13200 { 31593 /* vwadd.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13201 { 31602 /* vwaddu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13202 { 31612 /* vwaddu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13203 { 31622 /* vwaddu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13204 { 31632 /* vwaddu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13205 { 31642 /* vwcvt.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13206 { 31654 /* vwcvtu.x.x.v */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13207 { 31667 /* vwmacc.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13208 { 31677 /* vwmacc.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13209 { 31687 /* vwmaccsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13210 { 31699 /* vwmaccsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13211 { 31711 /* vwmaccu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13212 { 31722 /* vwmaccu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13213 { 31733 /* vwmaccus.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13214 { 31756 /* vwmul.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13215 { 31765 /* vwmul.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13216 { 31774 /* vwmulsu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13217 { 31785 /* vwmulsu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13218 { 31796 /* vwmulu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13219 { 31806 /* vwmulu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13220 { 31816 /* vwredsum.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13221 { 31828 /* vwredsumu.vs */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13222 { 31841 /* vwsll.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
13223 { 31850 /* vwsll.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
13224 { 31859 /* vwsll.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
13225 { 31868 /* vwsub.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13226 { 31877 /* vwsub.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13227 { 31886 /* vwsub.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13228 { 31895 /* vwsub.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13229 { 31904 /* vwsubu.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13230 { 31914 /* vwsubu.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13231 { 31924 /* vwsubu.wv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13232 { 31934 /* vwsubu.wx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13233 { 31944 /* vxor.vi */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13234 { 31952 /* vxor.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13235 { 31960 /* vxor.vx */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13236 { 31968 /* vzext.vf2 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13237 { 31978 /* vzext.vf4 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13238 { 31988 /* vzext.vf8 */, 4 /* 2 */, MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
13239 { 31998 /* vzip.vv */, 8 /* 3 */, MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvzip },
13240 { 32006 /* wadd */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13241 { 32011 /* wadda */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13242 { 32017 /* waddau */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13243 { 32024 /* waddu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13244 { 32034 /* wmacc */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13245 { 32040 /* wmaccsu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13246 { 32048 /* wmaccu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13247 { 32055 /* wmul */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13248 { 32060 /* wmulsu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13249 { 32067 /* wmulu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13250 { 32089 /* wsla */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13251 { 32094 /* wslai */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13252 { 32100 /* wsll */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13253 { 32105 /* wslli */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13254 { 32111 /* wsub */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13255 { 32116 /* wsuba */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13256 { 32122 /* wsubau */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13257 { 32129 /* wsubu */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13258 { 32135 /* wzip16p */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13259 { 32143 /* wzip8p */, 1 /* 0 */, MCK_GPRPairRV32, AMFBS_HasStdExtP_IsRV32 },
13260};
13261
13262ParseStatus RISCVAsmParser::
13263tryCustomParseOperand(OperandVector &Operands,
13264 unsigned MCK) {
13265
13266 switch(MCK) {
13267 case MCK_BareSymbol:
13268 return parseBareSymbol(Operands);
13269 case MCK_BareSymbolQC_E_LI:
13270 return parseBareSymbol(Operands);
13271 case MCK_CSRSystemRegister:
13272 return parseCSRSystemRegister(Operands);
13273 case MCK_RegReg:
13274 return parseRegReg(Operands);
13275 case MCK_CallSymbol:
13276 return parseCallSymbol(Operands);
13277 case MCK_FRMArg:
13278 return parseFRMArg(Operands);
13279 case MCK_FRMArgLegacy:
13280 return parseFRMArg(Operands);
13281 case MCK_FenceArg:
13282 return parseFenceArg(Operands);
13283 case MCK_GPRAsFPR16:
13284 return parseGPRAsFPR(Operands);
13285 case MCK_GPRAsFPR32:
13286 return parseGPRAsFPR(Operands);
13287 case MCK_GPRF64AsFPR:
13288 return parseGPRAsFPR64(Operands);
13289 case MCK_GPRPairAsFPR:
13290 return parseGPRPairAsFPR64(Operands);
13291 case MCK_GPRPairCRV32:
13292 return parseGPRPair<false>(Operands);
13293 case MCK_GPRPairNoX0RV32:
13294 return parseGPRPair<false>(Operands);
13295 case MCK_GPRPairRV32:
13296 return parseGPRPair<false>(Operands);
13297 case MCK_GPRPairRV64:
13298 return parseGPRPair<true>(Operands);
13299 case MCK_InsnCDirectiveOpcode:
13300 return parseInsnCDirectiveOpcode(Operands);
13301 case MCK_InsnDirectiveOpcode:
13302 return parseInsnDirectiveOpcode(Operands);
13303 case MCK_LoadFPImm:
13304 return parseFPImm(Operands);
13305 case MCK_NegStackAdj:
13306 return parseZcmpNegStackAdj(Operands);
13307 case MCK_PseudoJumpSymbol:
13308 return parsePseudoJumpSymbol(Operands);
13309 case MCK_QCAccessSymbol:
13310 return parseOperandWithSpecifier(Operands);
13311 case MCK_RTZArg:
13312 return parseFRMArg(Operands);
13313 case MCK_RegList:
13314 return parseRegList(Operands);
13315 case MCK_RegListS0:
13316 return parseRegListS0(Operands);
13317 case MCK_BareSImm21Lsb0:
13318 return parseJALOffset(Operands);
13319 case MCK_StackAdj:
13320 return parseZcmpStackAdj(Operands);
13321 case MCK_TLSDESCCallSymbol:
13322 return parseOperandWithSpecifier(Operands);
13323 case MCK_TPRelAddSymbol:
13324 return parseOperandWithSpecifier(Operands);
13325 case MCK_TileLambda:
13326 return parseTileLambda(Operands);
13327 case MCK_RVVMaskRegOpOperand:
13328 return parseMaskReg(Operands);
13329 case MCK_RVVScaleRegOpOperand:
13330 return parseVScaleReg(Operands);
13331 case MCK_XSfmmVType:
13332 return parseXSfmmVType(Operands);
13333 case MCK_ZeroOffsetMemOpOperand:
13334 return parseZeroOffsetMemOp(Operands);
13335 case MCK_VTypeI10:
13336 return parseVTypeI(Operands);
13337 case MCK_VTypeI11:
13338 return parseVTypeI(Operands);
13339 default:
13340 return ParseStatus::NoMatch;
13341 }
13342 return ParseStatus::NoMatch;
13343}
13344
13345ParseStatus RISCVAsmParser::
13346MatchOperandParserImpl(OperandVector &Operands,
13347 StringRef Mnemonic,
13348 bool ParseForAllFeatures) {
13349 // Get the current feature set.
13350 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
13351
13352 // Get the next operand index.
13353 unsigned NextOpNum = Operands.size() - 1;
13354 // Search the table.
13355 auto MnemonicRange =
13356 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
13357 Mnemonic, LessOpcodeOperand());
13358
13359 if (MnemonicRange.first == MnemonicRange.second)
13360 return ParseStatus::NoMatch;
13361
13362 for (const OperandMatchEntry *it = MnemonicRange.first,
13363 *ie = MnemonicRange.second; it != ie; ++it) {
13364 // equal_range guarantees that instruction mnemonic matches.
13365 assert(Mnemonic == it->getMnemonic());
13366
13367 // check if the available features match
13368 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
13369 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
13370 continue;
13371
13372 // check if the operand in question has a custom parser.
13373 if (!(it->OperandMask & (1 << NextOpNum)))
13374 continue;
13375
13376 // call custom parse method to handle the operand
13377 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
13378 if (!Result.isNoMatch())
13379 return Result;
13380 }
13381
13382 // Okay, we had no match.
13383 return ParseStatus::NoMatch;
13384}
13385
13386#endif // GET_MATCHER_IMPLEMENTATION
13387
13388
13389#ifdef GET_MNEMONIC_SPELL_CHECKER
13390#undef GET_MNEMONIC_SPELL_CHECKER
13391
13392static std::string RISCVMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
13393 const unsigned MaxEditDist = 2;
13394 std::vector<StringRef> Candidates;
13395 StringRef Prev = "";
13396
13397 // Find the appropriate table for this asm variant.
13398 const MatchEntry *Start, *End;
13399 switch (VariantID) {
13400 default: llvm_unreachable("invalid variant!");
13401 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
13402 }
13403
13404 for (auto I = Start; I < End; I++) {
13405 // Ignore unsupported instructions.
13406 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
13407 if ((FBS & RequiredFeatures) != RequiredFeatures)
13408 continue;
13409
13410 StringRef T = I->getMnemonic();
13411 // Avoid recomputing the edit distance for the same string.
13412 if (T == Prev)
13413 continue;
13414
13415 Prev = T;
13416 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
13417 if (Dist <= MaxEditDist)
13418 Candidates.push_back(T);
13419 }
13420
13421 if (Candidates.empty())
13422 return "";
13423
13424 std::string Res = ", did you mean: ";
13425 unsigned i = 0;
13426 for (; i < Candidates.size() - 1; i++)
13427 Res += Candidates[i].str() + ", ";
13428 return Res + Candidates[i].str() + "?";
13429}
13430
13431#endif // GET_MNEMONIC_SPELL_CHECKER
13432
13433
13434#ifdef GET_MNEMONIC_CHECKER
13435#undef GET_MNEMONIC_CHECKER
13436
13437static bool RISCVCheckMnemonic(StringRef Mnemonic,
13438 const FeatureBitset &AvailableFeatures,
13439 unsigned VariantID) {
13440 // Process all MnemonicAliases to remap the mnemonic.
13441 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
13442
13443 // Find the appropriate table for this asm variant.
13444 const MatchEntry *Start, *End;
13445 switch (VariantID) {
13446 default: llvm_unreachable("invalid variant!");
13447 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
13448 }
13449
13450 // Search the table.
13451 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
13452
13453 if (MnemonicRange.first == MnemonicRange.second)
13454 return false;
13455
13456 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
13457 it != ie; ++it) {
13458 const FeatureBitset &RequiredFeatures =
13459 FeatureBitsets[it->RequiredFeaturesIdx];
13460 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
13461 return true;
13462 }
13463 return false;
13464}
13465
13466#endif // GET_MNEMONIC_CHECKER
13467
13468