1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SPIRV {
13
14 enum {
15 PHI = 0, // Target.td:1301
16 INLINEASM = 1, // Target.td:1307
17 INLINEASM_BR = 2, // Target.td:1313
18 CFI_INSTRUCTION = 3, // Target.td:1322
19 EH_LABEL = 4, // Target.td:1331
20 GC_LABEL = 5, // Target.td:1340
21 ANNOTATION_LABEL = 6, // Target.td:1349
22 KILL = 7, // Target.td:1357
23 EXTRACT_SUBREG = 8, // Target.td:1364
24 INSERT_SUBREG = 9, // Target.td:1370
25 IMPLICIT_DEF = 10, // Target.td:1377
26 INIT_UNDEF = 11, // Target.td:1386
27 SUBREG_TO_REG = 12, // Target.td:1393
28 COPY_TO_REGCLASS = 13, // Target.td:1399
29 DBG_VALUE = 14, // Target.td:1406
30 DBG_VALUE_LIST = 15, // Target.td:1413
31 DBG_INSTR_REF = 16, // Target.td:1420
32 DBG_PHI = 17, // Target.td:1427
33 DBG_LABEL = 18, // Target.td:1434
34 REG_SEQUENCE = 19, // Target.td:1441
35 COPY = 20, // Target.td:1448
36 COPY_LANEMASK = 21, // Target.td:1456
37 BUNDLE = 22, // Target.td:1463
38 LIFETIME_START = 23, // Target.td:1469
39 LIFETIME_END = 24, // Target.td:1476
40 PSEUDO_PROBE = 25, // Target.td:1483
41 ARITH_FENCE = 26, // Target.td:1490
42 STACKMAP = 27, // Target.td:1499
43 FENTRY_CALL = 28, // Target.td:1634
44 PATCHPOINT = 29, // Target.td:1507
45 LOAD_STACK_GUARD = 30, // Target.td:1525
46 PREALLOCATED_SETUP = 31, // Target.td:1533
47 PREALLOCATED_ARG = 32, // Target.td:1539
48 STATEPOINT = 33, // Target.td:1516
49 LOCAL_ESCAPE = 34, // Target.td:1545
50 FAULTING_OP = 35, // Target.td:1554
51 PATCHABLE_OP = 36, // Target.td:1574
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1582
53 PATCHABLE_RET = 38, // Target.td:1589
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1598
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1606
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1614
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1624
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1644
59 FAKE_USE = 44, // Target.td:1564
60 MEMBARRIER = 45, // Target.td:1650
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1658
62 RELOC_NONE = 47, // Target.td:1666
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1678
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1674
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1682
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1686
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1867
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1859
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1874
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1474
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1486
96 G_INSERT = 81, // GenericOpcodes.td:1494
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1504
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1523
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1532
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1539
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1881
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_FMAXIMUMNUM = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_FMINIMUMNUM = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_UINC_WRAP = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_UDEC_WRAP = 129, // GenericOpcodes.td:1448
145 G_ATOMICRMW_USUB_COND = 130, // GenericOpcodes.td:1449
146 G_ATOMICRMW_USUB_SAT = 131, // GenericOpcodes.td:1450
147 G_FENCE = 132, // GenericOpcodes.td:1452
148 G_PREFETCH = 133, // GenericOpcodes.td:1459
149 G_BRCOND = 134, // GenericOpcodes.td:1594
150 G_BRINDIRECT = 135, // GenericOpcodes.td:1603
151 G_INVOKE_REGION_START = 136, // GenericOpcodes.td:1626
152 G_INTRINSIC = 137, // GenericOpcodes.td:1546
153 G_INTRINSIC_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1553
154 G_INTRINSIC_CONVERGENT = 139, // GenericOpcodes.td:1562
155 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1570
156 G_ANYEXT = 141, // GenericOpcodes.td:44
157 G_TRUNC = 142, // GenericOpcodes.td:83
158 G_TRUNC_SSAT_S = 143, // GenericOpcodes.td:90
159 G_TRUNC_SSAT_U = 144, // GenericOpcodes.td:97
160 G_TRUNC_USAT_U = 145, // GenericOpcodes.td:104
161 G_CONSTANT = 146, // GenericOpcodes.td:165
162 G_FCONSTANT = 147, // GenericOpcodes.td:172
163 G_VASTART = 148, // GenericOpcodes.td:178
164 G_VAARG = 149, // GenericOpcodes.td:185
165 G_SEXT = 150, // GenericOpcodes.td:52
166 G_SEXT_INREG = 151, // GenericOpcodes.td:66
167 G_ZEXT = 152, // GenericOpcodes.td:74
168 G_SHL = 153, // GenericOpcodes.td:396
169 G_LSHR = 154, // GenericOpcodes.td:403
170 G_ASHR = 155, // GenericOpcodes.td:410
171 G_FSHL = 156, // GenericOpcodes.td:462
172 G_FSHR = 157, // GenericOpcodes.td:470
173 G_ROTR = 158, // GenericOpcodes.td:477
174 G_ROTL = 159, // GenericOpcodes.td:484
175 G_ICMP = 160, // GenericOpcodes.td:491
176 G_FCMP = 161, // GenericOpcodes.td:498
177 G_SCMP = 162, // GenericOpcodes.td:505
178 G_UCMP = 163, // GenericOpcodes.td:512
179 G_SELECT = 164, // GenericOpcodes.td:519
180 G_UADDO = 165, // GenericOpcodes.td:584
181 G_UADDE = 166, // GenericOpcodes.td:592
182 G_USUBO = 167, // GenericOpcodes.td:614
183 G_USUBE = 168, // GenericOpcodes.td:620
184 G_SADDO = 169, // GenericOpcodes.td:599
185 G_SADDE = 170, // GenericOpcodes.td:607
186 G_SSUBO = 171, // GenericOpcodes.td:627
187 G_SSUBE = 172, // GenericOpcodes.td:634
188 G_UMULO = 173, // GenericOpcodes.td:641
189 G_SMULO = 174, // GenericOpcodes.td:649
190 G_UMULH = 175, // GenericOpcodes.td:658
191 G_SMULH = 176, // GenericOpcodes.td:667
192 G_UADDSAT = 177, // GenericOpcodes.td:679
193 G_SADDSAT = 178, // GenericOpcodes.td:687
194 G_USUBSAT = 179, // GenericOpcodes.td:695
195 G_SSUBSAT = 180, // GenericOpcodes.td:703
196 G_USHLSAT = 181, // GenericOpcodes.td:711
197 G_SSHLSAT = 182, // GenericOpcodes.td:719
198 G_SMULFIX = 183, // GenericOpcodes.td:731
199 G_UMULFIX = 184, // GenericOpcodes.td:738
200 G_SMULFIXSAT = 185, // GenericOpcodes.td:748
201 G_UMULFIXSAT = 186, // GenericOpcodes.td:755
202 G_SDIVFIX = 187, // GenericOpcodes.td:766
203 G_UDIVFIX = 188, // GenericOpcodes.td:773
204 G_SDIVFIXSAT = 189, // GenericOpcodes.td:783
205 G_UDIVFIXSAT = 190, // GenericOpcodes.td:790
206 G_FADD = 191, // GenericOpcodes.td:963
207 G_FSUB = 192, // GenericOpcodes.td:971
208 G_FMUL = 193, // GenericOpcodes.td:979
209 G_FMA = 194, // GenericOpcodes.td:988
210 G_FMAD = 195, // GenericOpcodes.td:997
211 G_FDIV = 196, // GenericOpcodes.td:1005
212 G_FREM = 197, // GenericOpcodes.td:1012
213 G_FMODF = 198, // GenericOpcodes.td:1019
214 G_FPOW = 199, // GenericOpcodes.td:1026
215 G_FPOWI = 200, // GenericOpcodes.td:1033
216 G_FEXP = 201, // GenericOpcodes.td:1040
217 G_FEXP2 = 202, // GenericOpcodes.td:1047
218 G_FEXP10 = 203, // GenericOpcodes.td:1054
219 G_FLOG = 204, // GenericOpcodes.td:1061
220 G_FLOG2 = 205, // GenericOpcodes.td:1068
221 G_FLOG10 = 206, // GenericOpcodes.td:1075
222 G_FLDEXP = 207, // GenericOpcodes.td:1082
223 G_FFREXP = 208, // GenericOpcodes.td:1089
224 G_FNEG = 209, // GenericOpcodes.td:801
225 G_FPEXT = 210, // GenericOpcodes.td:807
226 G_FPTRUNC = 211, // GenericOpcodes.td:813
227 G_FPTOSI = 212, // GenericOpcodes.td:819
228 G_FPTOUI = 213, // GenericOpcodes.td:825
229 G_SITOFP = 214, // GenericOpcodes.td:831
230 G_UITOFP = 215, // GenericOpcodes.td:837
231 G_FPTOSI_SAT = 216, // GenericOpcodes.td:843
232 G_FPTOUI_SAT = 217, // GenericOpcodes.td:849
233 G_FABS = 218, // GenericOpcodes.td:855
234 G_FCOPYSIGN = 219, // GenericOpcodes.td:861
235 G_IS_FPCLASS = 220, // GenericOpcodes.td:874
236 G_FCANONICALIZE = 221, // GenericOpcodes.td:867
237 G_FMINNUM = 222, // GenericOpcodes.td:887
238 G_FMAXNUM = 223, // GenericOpcodes.td:894
239 G_FMINNUM_IEEE = 224, // GenericOpcodes.td:912
240 G_FMAXNUM_IEEE = 225, // GenericOpcodes.td:919
241 G_FMINIMUM = 226, // GenericOpcodes.td:929
242 G_FMAXIMUM = 227, // GenericOpcodes.td:936
243 G_FMINIMUMNUM = 228, // GenericOpcodes.td:944
244 G_FMAXIMUMNUM = 229, // GenericOpcodes.td:951
245 G_GET_FPENV = 230, // GenericOpcodes.td:1219
246 G_SET_FPENV = 231, // GenericOpcodes.td:1226
247 G_RESET_FPENV = 232, // GenericOpcodes.td:1233
248 G_GET_FPMODE = 233, // GenericOpcodes.td:1240
249 G_SET_FPMODE = 234, // GenericOpcodes.td:1247
250 G_RESET_FPMODE = 235, // GenericOpcodes.td:1254
251 G_GET_ROUNDING = 236, // GenericOpcodes.td:1311
252 G_SET_ROUNDING = 237, // GenericOpcodes.td:1317
253 G_PTR_ADD = 238, // GenericOpcodes.td:526
254 G_PTRMASK = 239, // GenericOpcodes.td:534
255 G_SMIN = 240, // GenericOpcodes.td:541
256 G_SMAX = 241, // GenericOpcodes.td:549
257 G_UMIN = 242, // GenericOpcodes.td:557
258 G_UMAX = 243, // GenericOpcodes.td:565
259 G_ABS = 244, // GenericOpcodes.td:573
260 G_LROUND = 245, // GenericOpcodes.td:283
261 G_LLROUND = 246, // GenericOpcodes.td:289
262 G_BR = 247, // GenericOpcodes.td:1584
263 G_BRJT = 248, // GenericOpcodes.td:1614
264 G_VSCALE = 249, // GenericOpcodes.td:1514
265 G_INSERT_SUBVECTOR = 250, // GenericOpcodes.td:1658
266 G_EXTRACT_SUBVECTOR = 251, // GenericOpcodes.td:1665
267 G_INSERT_VECTOR_ELT = 252, // GenericOpcodes.td:1672
268 G_EXTRACT_VECTOR_ELT = 253, // GenericOpcodes.td:1679
269 G_SHUFFLE_VECTOR = 254, // GenericOpcodes.td:1689
270 G_SPLAT_VECTOR = 255, // GenericOpcodes.td:1696
271 G_STEP_VECTOR = 256, // GenericOpcodes.td:1703
272 G_VECTOR_COMPRESS = 257, // GenericOpcodes.td:1710
273 G_CTTZ = 258, // GenericOpcodes.td:205
274 G_CTTZ_ZERO_UNDEF = 259, // GenericOpcodes.td:211
275 G_CTLZ = 260, // GenericOpcodes.td:193
276 G_CTLZ_ZERO_UNDEF = 261, // GenericOpcodes.td:199
277 G_CTLS = 262, // GenericOpcodes.td:217
278 G_CTPOP = 263, // GenericOpcodes.td:223
279 G_BSWAP = 264, // GenericOpcodes.td:229
280 G_BITREVERSE = 265, // GenericOpcodes.td:235
281 G_FCEIL = 266, // GenericOpcodes.td:1096
282 G_FCOS = 267, // GenericOpcodes.td:1103
283 G_FSIN = 268, // GenericOpcodes.td:1110
284 G_FSINCOS = 269, // GenericOpcodes.td:1117
285 G_FTAN = 270, // GenericOpcodes.td:1124
286 G_FACOS = 271, // GenericOpcodes.td:1131
287 G_FASIN = 272, // GenericOpcodes.td:1138
288 G_FATAN = 273, // GenericOpcodes.td:1145
289 G_FATAN2 = 274, // GenericOpcodes.td:1152
290 G_FCOSH = 275, // GenericOpcodes.td:1159
291 G_FSINH = 276, // GenericOpcodes.td:1166
292 G_FTANH = 277, // GenericOpcodes.td:1173
293 G_FSQRT = 278, // GenericOpcodes.td:1183
294 G_FFLOOR = 279, // GenericOpcodes.td:1190
295 G_FRINT = 280, // GenericOpcodes.td:1197
296 G_FNEARBYINT = 281, // GenericOpcodes.td:1204
297 G_ADDRSPACE_CAST = 282, // GenericOpcodes.td:241
298 G_BLOCK_ADDR = 283, // GenericOpcodes.td:247
299 G_JUMP_TABLE = 284, // GenericOpcodes.td:253
300 G_DYN_STACKALLOC = 285, // GenericOpcodes.td:259
301 G_STACKSAVE = 286, // GenericOpcodes.td:265
302 G_STACKRESTORE = 287, // GenericOpcodes.td:271
303 G_STRICT_FADD = 288, // GenericOpcodes.td:1760
304 G_STRICT_FSUB = 289, // GenericOpcodes.td:1761
305 G_STRICT_FMUL = 290, // GenericOpcodes.td:1762
306 G_STRICT_FDIV = 291, // GenericOpcodes.td:1763
307 G_STRICT_FREM = 292, // GenericOpcodes.td:1764
308 G_STRICT_FMA = 293, // GenericOpcodes.td:1765
309 G_STRICT_FSQRT = 294, // GenericOpcodes.td:1766
310 G_STRICT_FLDEXP = 295, // GenericOpcodes.td:1767
311 G_READ_REGISTER = 296, // GenericOpcodes.td:1633
312 G_WRITE_REGISTER = 297, // GenericOpcodes.td:1643
313 G_MEMCPY = 298, // GenericOpcodes.td:1773
314 G_MEMCPY_INLINE = 299, // GenericOpcodes.td:1781
315 G_MEMMOVE = 300, // GenericOpcodes.td:1789
316 G_MEMSET = 301, // GenericOpcodes.td:1797
317 G_BZERO = 302, // GenericOpcodes.td:1804
318 G_TRAP = 303, // GenericOpcodes.td:1814
319 G_DEBUGTRAP = 304, // GenericOpcodes.td:1821
320 G_UBSANTRAP = 305, // GenericOpcodes.td:1827
321 G_VECREDUCE_SEQ_FADD = 306, // GenericOpcodes.td:1726
322 G_VECREDUCE_SEQ_FMUL = 307, // GenericOpcodes.td:1732
323 G_VECREDUCE_FADD = 308, // GenericOpcodes.td:1738
324 G_VECREDUCE_FMUL = 309, // GenericOpcodes.td:1739
325 G_VECREDUCE_FMAX = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMIN = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_FMAXIMUM = 312, // GenericOpcodes.td:1743
328 G_VECREDUCE_FMINIMUM = 313, // GenericOpcodes.td:1744
329 G_VECREDUCE_ADD = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_MUL = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_AND = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_OR = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_XOR = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_SMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_SMIN = 320, // GenericOpcodes.td:1752
336 G_VECREDUCE_UMAX = 321, // GenericOpcodes.td:1753
337 G_VECREDUCE_UMIN = 322, // GenericOpcodes.td:1754
338 G_SBFX = 323, // GenericOpcodes.td:1839
339 G_UBFX = 324, // GenericOpcodes.td:1847
340 ASSIGN_TYPE = 325, // SPIRVInstrInfo.td:18
341 UNKNOWN_type = 326, // SPIRVInstrInfo.td:21
342 OpAccessChain = 327, // SPIRVInstrInfo.td:266
343 OpAliasDomainDeclINTEL = 328, // SPIRVInstrInfo.td:969
344 OpAliasScopeDeclINTEL = 329, // SPIRVInstrInfo.td:971
345 OpAliasScopeListDeclINTEL = 330, // SPIRVInstrInfo.td:973
346 OpAll = 331, // SPIRVInstrInfo.td:560
347 OpAny = 332, // SPIRVInstrInfo.td:558
348 OpArbitraryFloatACosALTERA = 333, // SPIRVInstrInfo.td:1060
349 OpArbitraryFloatACosPiALTERA = 334, // SPIRVInstrInfo.td:1062
350 OpArbitraryFloatASinALTERA = 335, // SPIRVInstrInfo.td:1056
351 OpArbitraryFloatASinPiALTERA = 336, // SPIRVInstrInfo.td:1058
352 OpArbitraryFloatATan2ALTERA = 337, // SPIRVInstrInfo.td:1068
353 OpArbitraryFloatATanALTERA = 338, // SPIRVInstrInfo.td:1064
354 OpArbitraryFloatATanPiALTERA = 339, // SPIRVInstrInfo.td:1066
355 OpArbitraryFloatAddALTERA = 340, // SPIRVInstrInfo.td:1045
356 OpArbitraryFloatCastALTERA = 341, // SPIRVInstrInfo.td:1076
357 OpArbitraryFloatCastFromIntALTERA = 342, // SPIRVInstrInfo.td:1078
358 OpArbitraryFloatCastToIntALTERA = 343, // SPIRVInstrInfo.td:1080
359 OpArbitraryFloatCbrtALTERA = 344, // SPIRVInstrInfo.td:994
360 OpArbitraryFloatCosALTERA = 345, // SPIRVInstrInfo.td:1030
361 OpArbitraryFloatCosPiALTERA = 346, // SPIRVInstrInfo.td:1039
362 OpArbitraryFloatDivALTERA = 347, // SPIRVInstrInfo.td:1052
363 OpArbitraryFloatEQALTERA = 348, // SPIRVInstrInfo.td:989
364 OpArbitraryFloatExp10ALTERA = 349, // SPIRVInstrInfo.td:1021
365 OpArbitraryFloatExp2ALTERA = 350, // SPIRVInstrInfo.td:1018
366 OpArbitraryFloatExpALTERA = 351, // SPIRVInstrInfo.td:1015
367 OpArbitraryFloatExpm1ALTERA = 352, // SPIRVInstrInfo.td:1024
368 OpArbitraryFloatGEALTERA = 353, // SPIRVInstrInfo.td:983
369 OpArbitraryFloatGTALTERA = 354, // SPIRVInstrInfo.td:981
370 OpArbitraryFloatHypotALTERA = 355, // SPIRVInstrInfo.td:997
371 OpArbitraryFloatLEALTERA = 356, // SPIRVInstrInfo.td:987
372 OpArbitraryFloatLTALTERA = 357, // SPIRVInstrInfo.td:985
373 OpArbitraryFloatLog10ALTERA = 358, // SPIRVInstrInfo.td:1009
374 OpArbitraryFloatLog1pALTERA = 359, // SPIRVInstrInfo.td:1012
375 OpArbitraryFloatLog2ALTERA = 360, // SPIRVInstrInfo.td:1006
376 OpArbitraryFloatLogALTERA = 361, // SPIRVInstrInfo.td:1003
377 OpArbitraryFloatMulALTERA = 362, // SPIRVInstrInfo.td:1050
378 OpArbitraryFloatPowALTERA = 363, // SPIRVInstrInfo.td:1070
379 OpArbitraryFloatPowNALTERA = 364, // SPIRVInstrInfo.td:1074
380 OpArbitraryFloatPowRALTERA = 365, // SPIRVInstrInfo.td:1072
381 OpArbitraryFloatRSqrtALTERA = 366, // SPIRVInstrInfo.td:1054
382 OpArbitraryFloatRecipALTERA = 367, // SPIRVInstrInfo.td:991
383 OpArbitraryFloatSinALTERA = 368, // SPIRVInstrInfo.td:1027
384 OpArbitraryFloatSinCosALTERA = 369, // SPIRVInstrInfo.td:1033
385 OpArbitraryFloatSinCosPiALTERA = 370, // SPIRVInstrInfo.td:1042
386 OpArbitraryFloatSinPiALTERA = 371, // SPIRVInstrInfo.td:1036
387 OpArbitraryFloatSqrtALTERA = 372, // SPIRVInstrInfo.td:1000
388 OpArbitraryFloatSubALTERA = 373, // SPIRVInstrInfo.td:1048
389 OpArithmeticFenceEXT = 374, // SPIRVInstrInfo.td:957
390 OpArrayLength = 375, // SPIRVInstrInfo.td:274
391 OpAsmCallINTEL = 376, // SPIRVInstrInfo.td:923
392 OpAsmINTEL = 377, // SPIRVInstrInfo.td:920
393 OpAsmTargetINTEL = 378, // SPIRVInstrInfo.td:919
394 OpAssumeTrueKHR = 379, // SPIRVInstrInfo.td:102
395 OpAtomicAnd = 380, // SPIRVInstrInfo.td:686
396 OpAtomicCompareExchange = 381, // SPIRVInstrInfo.td:666
397 OpAtomicCompareExchangeWeak = 382, // SPIRVInstrInfo.td:670
398 OpAtomicExchange = 383, // SPIRVInstrInfo.td:663
399 OpAtomicFAddEXT = 384, // SPIRVInstrInfo.td:690
400 OpAtomicFMaxEXT = 385, // SPIRVInstrInfo.td:692
401 OpAtomicFMinEXT = 386, // SPIRVInstrInfo.td:691
402 OpAtomicFlagClear = 387, // SPIRVInstrInfo.td:695
403 OpAtomicFlagTestAndSet = 388, // SPIRVInstrInfo.td:694
404 OpAtomicIAdd = 389, // SPIRVInstrInfo.td:678
405 OpAtomicIDecrement = 390, // SPIRVInstrInfo.td:676
406 OpAtomicIIncrement = 391, // SPIRVInstrInfo.td:675
407 OpAtomicISub = 392, // SPIRVInstrInfo.td:679
408 OpAtomicLoad = 393, // SPIRVInstrInfo.td:659
409 OpAtomicOr = 394, // SPIRVInstrInfo.td:687
410 OpAtomicSMax = 395, // SPIRVInstrInfo.td:683
411 OpAtomicSMin = 396, // SPIRVInstrInfo.td:681
412 OpAtomicStore = 397, // SPIRVInstrInfo.td:661
413 OpAtomicUMax = 398, // SPIRVInstrInfo.td:684
414 OpAtomicUMin = 399, // SPIRVInstrInfo.td:682
415 OpAtomicXor = 400, // SPIRVInstrInfo.td:688
416 OpBitCount = 401, // SPIRVInstrInfo.td:554
417 OpBitFieldInsert = 402, // SPIRVInstrInfo.td:544
418 OpBitFieldSExtract = 403, // SPIRVInstrInfo.td:547
419 OpBitFieldUExtract = 404, // SPIRVInstrInfo.td:550
420 OpBitReverse = 405, // SPIRVInstrInfo.td:553
421 OpBitcast = 406, // SPIRVInstrInfo.td:438
422 OpBitwiseAndS = 407, // SPIRVInstrInfo.td:48
423 OpBitwiseAndV = 408, // SPIRVInstrInfo.td:53
424 OpBitwiseFunctionINTEL = 409, // SPIRVInstrInfo.td:977
425 OpBitwiseOrS = 410, // SPIRVInstrInfo.td:48
426 OpBitwiseOrV = 411, // SPIRVInstrInfo.td:53
427 OpBitwiseXorS = 412, // SPIRVInstrInfo.td:48
428 OpBitwiseXorV = 413, // SPIRVInstrInfo.td:53
429 OpBranch = 414, // SPIRVInstrInfo.td:634
430 OpBranchConditional = 415, // SPIRVInstrInfo.td:635
431 OpBuildNDRange = 416, // SPIRVInstrInfo.td:768
432 OpCapability = 417, // SPIRVInstrInfo.td:160
433 OpCaptureEventProfilingInfo = 418, // SPIRVInstrInfo.td:763
434 OpCommitReadPipe = 419, // SPIRVInstrInfo.td:785
435 OpCommitWritePipe = 420, // SPIRVInstrInfo.td:787
436 OpCompositeConstruct = 421, // SPIRVInstrInfo.td:459
437 OpCompositeConstructContinuedINTEL = 422, // SPIRVInstrInfo.td:461
438 OpCompositeExtract = 423, // SPIRVInstrInfo.td:463
439 OpCompositeInsert = 424, // SPIRVInstrInfo.td:465
440 OpConstantComposite = 425, // SPIRVInstrInfo.td:230
441 OpConstantCompositeContinuedINTEL = 426, // SPIRVInstrInfo.td:232
442 OpConstantF = 427, // SPIRVInstrInfo.td:218
443 OpConstantFalse = 428, // SPIRVInstrInfo.td:227
444 OpConstantFunctionPointerINTEL = 429, // SPIRVInstrInfo.td:867
445 OpConstantI = 430, // SPIRVInstrInfo.td:216
446 OpConstantNull = 431, // SPIRVInstrInfo.td:238
447 OpConstantSampler = 432, // SPIRVInstrInfo.td:235
448 OpConstantTrue = 433, // SPIRVInstrInfo.td:225
449 OpControlBarrier = 434, // SPIRVInstrInfo.td:707
450 OpControlBarrierArriveINTEL = 435, // SPIRVInstrInfo.td:716
451 OpControlBarrierWaitINTEL = 436, // SPIRVInstrInfo.td:718
452 OpConvertBF16ToFINTEL = 437, // SPIRVInstrInfo.td:446
453 OpConvertFToBF16INTEL = 438, // SPIRVInstrInfo.td:445
454 OpConvertFToS = 439, // SPIRVInstrInfo.td:418
455 OpConvertFToU = 440, // SPIRVInstrInfo.td:417
456 OpConvertHandleToImageINTEL = 441, // SPIRVInstrInfo.td:961
457 OpConvertHandleToSampledImageINTEL = 442, // SPIRVInstrInfo.td:965
458 OpConvertHandleToSamplerINTEL = 443, // SPIRVInstrInfo.td:963
459 OpConvertPtrToU = 444, // SPIRVInstrInfo.td:428
460 OpConvertSToF = 445, // SPIRVInstrInfo.td:419
461 OpConvertUToF = 446, // SPIRVInstrInfo.td:420
462 OpConvertUToPtr = 447, // SPIRVInstrInfo.td:433
463 OpCooperativeMatrixConstructCheckedINTEL = 448, // SPIRVInstrInfo.td:946
464 OpCooperativeMatrixGetElementCoordINTEL = 449, // SPIRVInstrInfo.td:949
465 OpCooperativeMatrixLengthKHR = 450, // SPIRVInstrInfo.td:936
466 OpCooperativeMatrixLoadCheckedINTEL = 451, // SPIRVInstrInfo.td:940
467 OpCooperativeMatrixLoadKHR = 452, // SPIRVInstrInfo.td:927
468 OpCooperativeMatrixMulAddKHR = 453, // SPIRVInstrInfo.td:933
469 OpCooperativeMatrixPrefetchINTEL = 454, // SPIRVInstrInfo.td:952
470 OpCooperativeMatrixStoreCheckedINTEL = 455, // SPIRVInstrInfo.td:943
471 OpCooperativeMatrixStoreKHR = 456, // SPIRVInstrInfo.td:930
472 OpCopyLogical = 457, // SPIRVInstrInfo.td:469
473 OpCopyMemory = 458, // SPIRVInstrInfo.td:262
474 OpCopyMemorySized = 459, // SPIRVInstrInfo.td:264
475 OpCopyObject = 460, // SPIRVInstrInfo.td:467
476 OpCreateUserEvent = 461, // SPIRVInstrInfo.td:757
477 OpCrossWorkgroupCastToPtrINTEL = 462, // SPIRVInstrInfo.td:442
478 OpDPdx = 463, // SPIRVInstrInfo.td:610
479 OpDPdxCoarse = 464, // SPIRVInstrInfo.td:618
480 OpDPdxFine = 465, // SPIRVInstrInfo.td:614
481 OpDPdy = 466, // SPIRVInstrInfo.td:611
482 OpDPdyCoarse = 467, // SPIRVInstrInfo.td:619
483 OpDPdyFine = 468, // SPIRVInstrInfo.td:615
484 OpDecorate = 469, // SPIRVInstrInfo.td:124
485 OpDecorateId = 470, // SPIRVInstrInfo.td:132
486 OpDecorateString = 471, // SPIRVInstrInfo.td:134
487 OpDemoteToHelperInvocation = 472, // SPIRVInstrInfo.td:647
488 OpDot = 473, // SPIRVInstrInfo.td:510
489 OpEmitStreamVertex = 474, // SPIRVInstrInfo.td:702
490 OpEmitVertex = 475, // SPIRVInstrInfo.td:700
491 OpEndPrimitive = 476, // SPIRVInstrInfo.td:701
492 OpEndStreamPrimitive = 477, // SPIRVInstrInfo.td:703
493 OpEnqueueKernel = 478, // SPIRVInstrInfo.td:752
494 OpEntryPoint = 479, // SPIRVInstrInfo.td:155
495 OpExecutionMode = 480, // SPIRVInstrInfo.td:158
496 OpExecutionModeId = 481, // SPIRVInstrInfo.td:161
497 OpExpectKHR = 482, // SPIRVInstrInfo.td:103
498 OpExtInst = 483, // SPIRVInstrInfo.td:149
499 OpExtInstImport = 484, // SPIRVInstrInfo.td:143
500 OpExtension = 485, // SPIRVInstrInfo.td:142
501 OpFAddS = 486, // SPIRVInstrInfo.td:46
502 OpFAddV = 487, // SPIRVInstrInfo.td:51
503 OpFConvert = 488, // SPIRVInstrInfo.td:424
504 OpFDivS = 489, // SPIRVInstrInfo.td:46
505 OpFDivV = 490, // SPIRVInstrInfo.td:51
506 OpFMod = 491, // SPIRVInstrInfo.td:501
507 OpFMulS = 492, // SPIRVInstrInfo.td:46
508 OpFMulV = 493, // SPIRVInstrInfo.td:51
509 OpFNegate = 494, // SPIRVInstrInfo.td:474
510 OpFNegateV = 495, // SPIRVInstrInfo.td:475
511 OpFOrdEqual = 496, // SPIRVInstrInfo.td:593
512 OpFOrdGreaterThan = 497, // SPIRVInstrInfo.td:600
513 OpFOrdGreaterThanEqual = 498, // SPIRVInstrInfo.td:605
514 OpFOrdLessThan = 499, // SPIRVInstrInfo.td:598
515 OpFOrdLessThanEqual = 500, // SPIRVInstrInfo.td:603
516 OpFOrdNotEqual = 501, // SPIRVInstrInfo.td:595
517 OpFRemS = 502, // SPIRVInstrInfo.td:46
518 OpFRemV = 503, // SPIRVInstrInfo.td:51
519 OpFSubS = 504, // SPIRVInstrInfo.td:46
520 OpFSubV = 505, // SPIRVInstrInfo.td:51
521 OpFUnordEqual = 506, // SPIRVInstrInfo.td:594
522 OpFUnordGreaterThan = 507, // SPIRVInstrInfo.td:601
523 OpFUnordGreaterThanEqual = 508, // SPIRVInstrInfo.td:606
524 OpFUnordLessThan = 509, // SPIRVInstrInfo.td:599
525 OpFUnordLessThanEqual = 510, // SPIRVInstrInfo.td:604
526 OpFUnordNotEqual = 511, // SPIRVInstrInfo.td:596
527 OpFixedCosALTERA = 512, // SPIRVInstrInfo.td:1121
528 OpFixedCosPiALTERA = 513, // SPIRVInstrInfo.td:1127
529 OpFixedExpALTERA = 514, // SPIRVInstrInfo.td:1133
530 OpFixedLogALTERA = 515, // SPIRVInstrInfo.td:1131
531 OpFixedRecipALTERA = 516, // SPIRVInstrInfo.td:1115
532 OpFixedRsqrtALTERA = 517, // SPIRVInstrInfo.td:1117
533 OpFixedSinALTERA = 518, // SPIRVInstrInfo.td:1119
534 OpFixedSinCosALTERA = 519, // SPIRVInstrInfo.td:1123
535 OpFixedSinCosPiALTERA = 520, // SPIRVInstrInfo.td:1129
536 OpFixedSinPiALTERA = 521, // SPIRVInstrInfo.td:1125
537 OpFixedSqrtALTERA = 522, // SPIRVInstrInfo.td:1113
538 OpFmaKHR = 523, // SPIRVInstrInfo.td:530
539 OpFunction = 524, // SPIRVInstrInfo.td:299
540 OpFunctionCall = 525, // SPIRVInstrInfo.td:307
541 OpFunctionEnd = 526, // SPIRVInstrInfo.td:304
542 OpFunctionParameter = 527, // SPIRVInstrInfo.td:302
543 OpFunctionPointerCallINTEL = 528, // SPIRVInstrInfo.td:872
544 OpFwidth = 529, // SPIRVInstrInfo.td:612
545 OpFwidthCoarse = 530, // SPIRVInstrInfo.td:620
546 OpFwidthFine = 531, // SPIRVInstrInfo.td:616
547 OpGenericCastToPtr = 532, // SPIRVInstrInfo.td:435
548 OpGenericCastToPtrExplicit = 533, // SPIRVInstrInfo.td:436
549 OpGenericPtrMemSemantics = 534, // SPIRVInstrInfo.td:276
550 OpGetDefaultQueue = 535, // SPIRVInstrInfo.td:766
551 OpGetMaxPipePackets = 536, // SPIRVInstrInfo.td:793
552 OpGetNumPipePackets = 537, // SPIRVInstrInfo.td:791
553 OpGroupAll = 538, // SPIRVInstrInfo.td:728
554 OpGroupAny = 539, // SPIRVInstrInfo.td:730
555 OpGroupAsyncCopy = 540, // SPIRVInstrInfo.td:723
556 OpGroupBitwiseAndKHR = 541, // SPIRVInstrInfo.td:905
557 OpGroupBitwiseOrKHR = 542, // SPIRVInstrInfo.td:907
558 OpGroupBitwiseXorKHR = 543, // SPIRVInstrInfo.td:909
559 OpGroupBroadcast = 544, // SPIRVInstrInfo.td:732
560 OpGroupCommitReadPipe = 545, // SPIRVInstrInfo.td:799
561 OpGroupCommitWritePipe = 546, // SPIRVInstrInfo.td:801
562 OpGroupFAdd = 547, // SPIRVInstrInfo.td:739
563 OpGroupFMax = 548, // SPIRVInstrInfo.td:743
564 OpGroupFMin = 549, // SPIRVInstrInfo.td:740
565 OpGroupFMulKHR = 550, // SPIRVInstrInfo.td:903
566 OpGroupIAdd = 551, // SPIRVInstrInfo.td:738
567 OpGroupIMulKHR = 552, // SPIRVInstrInfo.td:901
568 OpGroupLogicalAndKHR = 553, // SPIRVInstrInfo.td:911
569 OpGroupLogicalOrKHR = 554, // SPIRVInstrInfo.td:913
570 OpGroupLogicalXorKHR = 555, // SPIRVInstrInfo.td:915
571 OpGroupNonUniformAll = 556, // SPIRVInstrInfo.td:814
572 OpGroupNonUniformAllEqual = 557, // SPIRVInstrInfo.td:816
573 OpGroupNonUniformAny = 558, // SPIRVInstrInfo.td:815
574 OpGroupNonUniformBallot = 559, // SPIRVInstrInfo.td:819
575 OpGroupNonUniformBallotBitCount = 560, // SPIRVInstrInfo.td:822
576 OpGroupNonUniformBallotBitExtract = 561, // SPIRVInstrInfo.td:821
577 OpGroupNonUniformBallotFindLSB = 562, // SPIRVInstrInfo.td:826
578 OpGroupNonUniformBallotFindMSB = 563, // SPIRVInstrInfo.td:827
579 OpGroupNonUniformBitwiseAnd = 564, // SPIRVInstrInfo.td:846
580 OpGroupNonUniformBitwiseOr = 565, // SPIRVInstrInfo.td:847
581 OpGroupNonUniformBitwiseXor = 566, // SPIRVInstrInfo.td:848
582 OpGroupNonUniformBroadcast = 567, // SPIRVInstrInfo.td:817
583 OpGroupNonUniformBroadcastFirst = 568, // SPIRVInstrInfo.td:818
584 OpGroupNonUniformElect = 569, // SPIRVInstrInfo.td:806
585 OpGroupNonUniformFAdd = 570, // SPIRVInstrInfo.td:837
586 OpGroupNonUniformFMax = 571, // SPIRVInstrInfo.td:845
587 OpGroupNonUniformFMin = 572, // SPIRVInstrInfo.td:842
588 OpGroupNonUniformFMul = 573, // SPIRVInstrInfo.td:839
589 OpGroupNonUniformIAdd = 574, // SPIRVInstrInfo.td:836
590 OpGroupNonUniformIMul = 575, // SPIRVInstrInfo.td:838
591 OpGroupNonUniformInverseBallot = 576, // SPIRVInstrInfo.td:820
592 OpGroupNonUniformLogicalAnd = 577, // SPIRVInstrInfo.td:849
593 OpGroupNonUniformLogicalOr = 578, // SPIRVInstrInfo.td:850
594 OpGroupNonUniformLogicalXor = 579, // SPIRVInstrInfo.td:851
595 OpGroupNonUniformQuadSwap = 580, // SPIRVInstrInfo.td:852
596 OpGroupNonUniformRotateKHR = 581, // SPIRVInstrInfo.td:855
597 OpGroupNonUniformSMax = 582, // SPIRVInstrInfo.td:843
598 OpGroupNonUniformSMin = 583, // SPIRVInstrInfo.td:840
599 OpGroupNonUniformShuffle = 584, // SPIRVInstrInfo.td:828
600 OpGroupNonUniformShuffleDown = 585, // SPIRVInstrInfo.td:831
601 OpGroupNonUniformShuffleUp = 586, // SPIRVInstrInfo.td:830
602 OpGroupNonUniformShuffleXor = 587, // SPIRVInstrInfo.td:829
603 OpGroupNonUniformUMax = 588, // SPIRVInstrInfo.td:844
604 OpGroupNonUniformUMin = 589, // SPIRVInstrInfo.td:841
605 OpGroupReserveReadPipePackets = 590, // SPIRVInstrInfo.td:795
606 OpGroupReserveWritePipePackets = 591, // SPIRVInstrInfo.td:797
607 OpGroupSMax = 592, // SPIRVInstrInfo.td:745
608 OpGroupSMin = 593, // SPIRVInstrInfo.td:742
609 OpGroupUMax = 594, // SPIRVInstrInfo.td:744
610 OpGroupUMin = 595, // SPIRVInstrInfo.td:741
611 OpGroupWaitEvents = 596, // SPIRVInstrInfo.td:726
612 OpIAddCarryS = 597, // SPIRVInstrInfo.td:48
613 OpIAddCarryV = 598, // SPIRVInstrInfo.td:53
614 OpIAddS = 599, // SPIRVInstrInfo.td:48
615 OpIAddV = 600, // SPIRVInstrInfo.td:53
616 OpIEqual = 601, // SPIRVInstrInfo.td:581
617 OpIMulS = 602, // SPIRVInstrInfo.td:48
618 OpIMulV = 603, // SPIRVInstrInfo.td:53
619 OpINotEqual = 604, // SPIRVInstrInfo.td:582
620 OpISubBorrowS = 605, // SPIRVInstrInfo.td:48
621 OpISubBorrowV = 606, // SPIRVInstrInfo.td:53
622 OpISubS = 607, // SPIRVInstrInfo.td:48
623 OpISubV = 608, // SPIRVInstrInfo.td:53
624 OpImage = 609, // SPIRVInstrInfo.td:358
625 OpImageDrefGather = 610, // SPIRVInstrInfo.td:348
626 OpImageFetch = 611, // SPIRVInstrInfo.td:342
627 OpImageGather = 612, // SPIRVInstrInfo.td:345
628 OpImageQueryFormat = 613, // SPIRVInstrInfo.td:359
629 OpImageQueryLevels = 614, // SPIRVInstrInfo.td:364
630 OpImageQueryLod = 615, // SPIRVInstrInfo.td:363
631 OpImageQueryOrder = 616, // SPIRVInstrInfo.td:360
632 OpImageQuerySamples = 617, // SPIRVInstrInfo.td:365
633 OpImageQuerySize = 618, // SPIRVInstrInfo.td:362
634 OpImageQuerySizeLod = 619, // SPIRVInstrInfo.td:361
635 OpImageRead = 620, // SPIRVInstrInfo.td:352
636 OpImageSampleDrefExplicitLod = 621, // SPIRVInstrInfo.td:324
637 OpImageSampleDrefImplicitLod = 622, // SPIRVInstrInfo.td:321
638 OpImageSampleExplicitLod = 623, // SPIRVInstrInfo.td:317
639 OpImageSampleFootprintNV = 624, // SPIRVInstrInfo.td:411
640 OpImageSampleImplicitLod = 625, // SPIRVInstrInfo.td:314
641 OpImageSampleProjDrefExplicitLod = 626, // SPIRVInstrInfo.td:338
642 OpImageSampleProjDrefImplicitLod = 627, // SPIRVInstrInfo.td:335
643 OpImageSampleProjExplicitLod = 628, // SPIRVInstrInfo.td:331
644 OpImageSampleProjImplicitLod = 629, // SPIRVInstrInfo.td:328
645 OpImageSparseDrefGather = 630, // SPIRVInstrInfo.td:401
646 OpImageSparseFetch = 631, // SPIRVInstrInfo.td:395
647 OpImageSparseGather = 632, // SPIRVInstrInfo.td:398
648 OpImageSparseRead = 633, // SPIRVInstrInfo.td:407
649 OpImageSparseSampleDrefExplicitLod = 634, // SPIRVInstrInfo.td:377
650 OpImageSparseSampleDrefImplicitLod = 635, // SPIRVInstrInfo.td:374
651 OpImageSparseSampleExplicitLod = 636, // SPIRVInstrInfo.td:370
652 OpImageSparseSampleImplicitLod = 637, // SPIRVInstrInfo.td:367
653 OpImageSparseSampleProjDrefExplicitLod = 638, // SPIRVInstrInfo.td:391
654 OpImageSparseSampleProjDrefImplicitLod = 639, // SPIRVInstrInfo.td:388
655 OpImageSparseSampleProjExplicitLod = 640, // SPIRVInstrInfo.td:384
656 OpImageSparseSampleProjImplicitLod = 641, // SPIRVInstrInfo.td:381
657 OpImageSparseTexelsResident = 642, // SPIRVInstrInfo.td:405
658 OpImageTexelPointer = 643, // SPIRVInstrInfo.td:255
659 OpImageWrite = 644, // SPIRVInstrInfo.td:355
660 OpInBoundsAccessChain = 645, // SPIRVInstrInfo.td:268
661 OpInBoundsPtrAccessChain = 646, // SPIRVInstrInfo.td:278
662 OpIsFinite = 647, // SPIRVInstrInfo.td:565
663 OpIsInf = 648, // SPIRVInstrInfo.td:564
664 OpIsNan = 649, // SPIRVInstrInfo.td:563
665 OpIsNormal = 650, // SPIRVInstrInfo.td:566
666 OpIsValidEvent = 651, // SPIRVInstrInfo.td:759
667 OpIsValidReserveId = 652, // SPIRVInstrInfo.td:789
668 OpKill = 653, // SPIRVInstrInfo.td:640
669 OpLabel = 654, // SPIRVInstrInfo.td:632
670 OpLessOrGreater = 655, // SPIRVInstrInfo.td:569
671 OpLifetimeStart = 656, // SPIRVInstrInfo.td:645
672 OpLifetimeStop = 657, // SPIRVInstrInfo.td:646
673 OpLine = 658, // SPIRVInstrInfo.td:117
674 OpLoad = 659, // SPIRVInstrInfo.td:258
675 OpLogicalAnd = 660, // SPIRVInstrInfo.td:576
676 OpLogicalEqual = 661, // SPIRVInstrInfo.td:573
677 OpLogicalNot = 662, // SPIRVInstrInfo.td:577
678 OpLogicalNotEqual = 663, // SPIRVInstrInfo.td:574
679 OpLogicalOr = 664, // SPIRVInstrInfo.td:575
680 OpLoopControlINTEL = 665, // SPIRVInstrInfo.td:628
681 OpLoopMerge = 666, // SPIRVInstrInfo.td:626
682 OpMaskedGatherINTEL = 667, // SPIRVInstrInfo.td:1137
683 OpMaskedScatterINTEL = 668, // SPIRVInstrInfo.td:1139
684 OpMatrixTimesMatrix = 669, // SPIRVInstrInfo.td:507
685 OpMatrixTimesScalar = 670, // SPIRVInstrInfo.td:504
686 OpMatrixTimesVector = 671, // SPIRVInstrInfo.td:506
687 OpMemberDecorate = 672, // SPIRVInstrInfo.td:126
688 OpMemberDecorateString = 673, // SPIRVInstrInfo.td:136
689 OpMemberName = 674, // SPIRVInstrInfo.td:114
690 OpMemoryBarrier = 675, // SPIRVInstrInfo.td:709
691 OpMemoryModel = 676, // SPIRVInstrInfo.td:153
692 OpMemoryNamedBarrier = 677, // SPIRVInstrInfo.td:712
693 OpModuleProcessed = 678, // SPIRVInstrInfo.td:119
694 OpName = 679, // SPIRVInstrInfo.td:113
695 OpNamedBarrierInitialize = 680, // SPIRVInstrInfo.td:711
696 OpNoLine = 681, // SPIRVInstrInfo.td:118
697 OpNop = 682, // SPIRVInstrInfo.td:97
698 OpNot = 683, // SPIRVInstrInfo.td:542
699 OpOrdered = 684, // SPIRVInstrInfo.td:570
700 OpOuterProduct = 685, // SPIRVInstrInfo.td:509
701 OpPhi = 686, // SPIRVInstrInfo.td:624
702 OpPredicatedLoadINTEL = 687, // SPIRVInstrInfo.td:1101
703 OpPredicatedStoreINTEL = 688, // SPIRVInstrInfo.td:1103
704 OpPtrAccessChain = 689, // SPIRVInstrInfo.td:271
705 OpPtrCastToCrossWorkgroupINTEL = 690, // SPIRVInstrInfo.td:441
706 OpPtrCastToGeneric = 691, // SPIRVInstrInfo.td:434
707 OpPtrDiff = 692, // SPIRVInstrInfo.td:285
708 OpPtrEqual = 693, // SPIRVInstrInfo.td:281
709 OpPtrNotEqual = 694, // SPIRVInstrInfo.td:283
710 OpQuantizeToF16 = 695, // SPIRVInstrInfo.td:426
711 OpReadClockKHR = 696, // SPIRVInstrInfo.td:860
712 OpReadPipe = 697, // SPIRVInstrInfo.td:773
713 OpReadPipeBlockingALTERA = 698, // SPIRVInstrInfo.td:1107
714 OpReleaseEvent = 699, // SPIRVInstrInfo.td:756
715 OpReserveReadPipePackets = 700, // SPIRVInstrInfo.td:781
716 OpReserveWritePipePackets = 701, // SPIRVInstrInfo.td:783
717 OpReservedReadPipe = 702, // SPIRVInstrInfo.td:777
718 OpReservedWritePipe = 703, // SPIRVInstrInfo.td:779
719 OpRestoreMemoryINTEL = 704, // SPIRVInstrInfo.td:294
720 OpRetainEvent = 705, // SPIRVInstrInfo.td:755
721 OpReturn = 706, // SPIRVInstrInfo.td:641
722 OpReturnValue = 707, // SPIRVInstrInfo.td:642
723 OpRoundFToTF32INTEL = 708, // SPIRVInstrInfo.td:449
724 OpSConvert = 709, // SPIRVInstrInfo.td:423
725 OpSDivS = 710, // SPIRVInstrInfo.td:48
726 OpSDivV = 711, // SPIRVInstrInfo.td:53
727 OpSDot = 712, // SPIRVInstrInfo.td:517
728 OpSDotAccSat = 713, // SPIRVInstrInfo.td:523
729 OpSGreaterThan = 714, // SPIRVInstrInfo.td:585
730 OpSGreaterThanEqual = 715, // SPIRVInstrInfo.td:587
731 OpSLessThan = 716, // SPIRVInstrInfo.td:589
732 OpSLessThanEqual = 717, // SPIRVInstrInfo.td:591
733 OpSMod = 718, // SPIRVInstrInfo.td:496
734 OpSMulExtended = 719, // SPIRVInstrInfo.td:515
735 OpSNegate = 720, // SPIRVInstrInfo.td:473
736 OpSRemS = 721, // SPIRVInstrInfo.td:48
737 OpSRemV = 722, // SPIRVInstrInfo.td:53
738 OpSUDot = 723, // SPIRVInstrInfo.td:521
739 OpSUDotAccSat = 724, // SPIRVInstrInfo.td:527
740 OpSampledImage = 725, // SPIRVInstrInfo.td:312
741 OpSatConvertSToU = 726, // SPIRVInstrInfo.td:430
742 OpSatConvertUToS = 727, // SPIRVInstrInfo.td:431
743 OpSaveMemoryINTEL = 728, // SPIRVInstrInfo.td:292
744 OpSelectSFSCond = 729, // SPIRVInstrInfo.td:67
745 OpSelectSFVCond = 730, // SPIRVInstrInfo.td:68
746 OpSelectSISCond = 731, // SPIRVInstrInfo.td:63
747 OpSelectSIVCond = 732, // SPIRVInstrInfo.td:64
748 OpSelectSPSCond = 733, // SPIRVInstrInfo.td:59
749 OpSelectSPVCond = 734, // SPIRVInstrInfo.td:60
750 OpSelectVFSCond = 735, // SPIRVInstrInfo.td:80
751 OpSelectVFVCond = 736, // SPIRVInstrInfo.td:81
752 OpSelectVISCond = 737, // SPIRVInstrInfo.td:76
753 OpSelectVIVCond = 738, // SPIRVInstrInfo.td:77
754 OpSelectVPSCond = 739, // SPIRVInstrInfo.td:72
755 OpSelectVPVCond = 740, // SPIRVInstrInfo.td:73
756 OpSelectionMerge = 741, // SPIRVInstrInfo.td:630
757 OpSetUserEventStatus = 742, // SPIRVInstrInfo.td:761
758 OpShiftLeftLogicalS = 743, // SPIRVInstrInfo.td:48
759 OpShiftLeftLogicalV = 744, // SPIRVInstrInfo.td:53
760 OpShiftRightArithmeticS = 745, // SPIRVInstrInfo.td:48
761 OpShiftRightArithmeticV = 746, // SPIRVInstrInfo.td:53
762 OpShiftRightLogicalS = 747, // SPIRVInstrInfo.td:48
763 OpShiftRightLogicalV = 748, // SPIRVInstrInfo.td:53
764 OpSignBitSet = 749, // SPIRVInstrInfo.td:567
765 OpSizeOf = 750, // SPIRVInstrInfo.td:99
766 OpSource = 751, // SPIRVInstrInfo.td:109
767 OpSourceContinued = 752, // SPIRVInstrInfo.td:107
768 OpSourceExtension = 753, // SPIRVInstrInfo.td:111
769 OpSpecConstant = 754, // SPIRVInstrInfo.td:242
770 OpSpecConstantComposite = 755, // SPIRVInstrInfo.td:244
771 OpSpecConstantCompositeContinuedINTEL = 756, // SPIRVInstrInfo.td:246
772 OpSpecConstantFalse = 757, // SPIRVInstrInfo.td:241
773 OpSpecConstantOp = 758, // SPIRVInstrInfo.td:248
774 OpSpecConstantTrue = 759, // SPIRVInstrInfo.td:240
775 OpStore = 760, // SPIRVInstrInfo.td:260
776 OpStrictFAddS = 761, // SPIRVInstrInfo.td:46
777 OpStrictFAddV = 762, // SPIRVInstrInfo.td:51
778 OpStrictFDivS = 763, // SPIRVInstrInfo.td:46
779 OpStrictFDivV = 764, // SPIRVInstrInfo.td:51
780 OpStrictFMulS = 765, // SPIRVInstrInfo.td:46
781 OpStrictFMulV = 766, // SPIRVInstrInfo.td:51
782 OpStrictFRemS = 767, // SPIRVInstrInfo.td:46
783 OpStrictFRemV = 768, // SPIRVInstrInfo.td:51
784 OpStrictFSubS = 769, // SPIRVInstrInfo.td:46
785 OpStrictFSubV = 770, // SPIRVInstrInfo.td:51
786 OpString = 771, // SPIRVInstrInfo.td:116
787 OpSubgroup2DBlockLoadINTEL = 772, // SPIRVInstrInfo.td:1084
788 OpSubgroup2DBlockLoadTransformINTEL = 773, // SPIRVInstrInfo.td:1090
789 OpSubgroup2DBlockLoadTransposeINTEL = 774, // SPIRVInstrInfo.td:1087
790 OpSubgroup2DBlockPrefetchINTEL = 775, // SPIRVInstrInfo.td:1093
791 OpSubgroup2DBlockStoreINTEL = 776, // SPIRVInstrInfo.td:1096
792 OpSubgroupBlockReadINTEL = 777, // SPIRVInstrInfo.td:885
793 OpSubgroupBlockWriteINTEL = 778, // SPIRVInstrInfo.td:887
794 OpSubgroupImageBlockReadINTEL = 779, // SPIRVInstrInfo.td:889
795 OpSubgroupImageBlockWriteINTEL = 780, // SPIRVInstrInfo.td:891
796 OpSubgroupImageMediaBlockReadINTEL = 781, // SPIRVInstrInfo.td:895
797 OpSubgroupImageMediaBlockWriteINTEL = 782, // SPIRVInstrInfo.td:897
798 OpSubgroupMatrixMultiplyAccumulateINTEL = 783, // SPIRVInstrInfo.td:747
799 OpSubgroupShuffleDownINTEL = 784, // SPIRVInstrInfo.td:879
800 OpSubgroupShuffleINTEL = 785, // SPIRVInstrInfo.td:877
801 OpSubgroupShuffleUpINTEL = 786, // SPIRVInstrInfo.td:881
802 OpSubgroupShuffleXorINTEL = 787, // SPIRVInstrInfo.td:883
803 OpSwitch = 788, // SPIRVInstrInfo.td:637
804 OpTranspose = 789, // SPIRVInstrInfo.td:468
805 OpTypeAccelerationStructureNV = 790, // SPIRVInstrInfo.td:204
806 OpTypeArray = 791, // SPIRVInstrInfo.td:182
807 OpTypeBool = 792, // SPIRVInstrInfo.td:167
808 OpTypeCooperativeMatrixKHR = 793, // SPIRVInstrInfo.td:209
809 OpTypeCooperativeMatrixNV = 794, // SPIRVInstrInfo.td:206
810 OpTypeDeviceEvent = 795, // SPIRVInstrInfo.td:196
811 OpTypeEvent = 796, // SPIRVInstrInfo.td:195
812 OpTypeFloat = 797, // SPIRVInstrInfo.td:170
813 OpTypeForwardPointer = 798, // SPIRVInstrInfo.td:200
814 OpTypeFunction = 799, // SPIRVInstrInfo.td:193
815 OpTypeImage = 800, // SPIRVInstrInfo.td:176
816 OpTypeInt = 801, // SPIRVInstrInfo.td:168
817 OpTypeMatrix = 802, // SPIRVInstrInfo.td:174
818 OpTypeNamedBarrier = 803, // SPIRVInstrInfo.td:203
819 OpTypeOpaque = 804, // SPIRVInstrInfo.td:189
820 OpTypePipe = 805, // SPIRVInstrInfo.td:199
821 OpTypePipeStorage = 806, // SPIRVInstrInfo.td:202
822 OpTypePointer = 807, // SPIRVInstrInfo.td:191
823 OpTypeQueue = 808, // SPIRVInstrInfo.td:198
824 OpTypeReserveId = 809, // SPIRVInstrInfo.td:197
825 OpTypeRuntimeArray = 810, // SPIRVInstrInfo.td:184
826 OpTypeSampledImage = 811, // SPIRVInstrInfo.td:180
827 OpTypeSampler = 812, // SPIRVInstrInfo.td:179
828 OpTypeStruct = 813, // SPIRVInstrInfo.td:186
829 OpTypeStructContinuedINTEL = 814, // SPIRVInstrInfo.td:187
830 OpTypeVector = 815, // SPIRVInstrInfo.td:172
831 OpTypeVoid = 816, // SPIRVInstrInfo.td:166
832 OpUConvert = 817, // SPIRVInstrInfo.td:422
833 OpUDivS = 818, // SPIRVInstrInfo.td:48
834 OpUDivV = 819, // SPIRVInstrInfo.td:53
835 OpUDot = 820, // SPIRVInstrInfo.td:519
836 OpUDotAccSat = 821, // SPIRVInstrInfo.td:525
837 OpUGreaterThan = 822, // SPIRVInstrInfo.td:584
838 OpUGreaterThanEqual = 823, // SPIRVInstrInfo.td:586
839 OpULessThan = 824, // SPIRVInstrInfo.td:588
840 OpULessThanEqual = 825, // SPIRVInstrInfo.td:590
841 OpUModS = 826, // SPIRVInstrInfo.td:48
842 OpUModV = 827, // SPIRVInstrInfo.td:53
843 OpUMulExtended = 828, // SPIRVInstrInfo.td:514
844 OpUndef = 829, // SPIRVInstrInfo.td:98
845 OpUnordered = 830, // SPIRVInstrInfo.td:571
846 OpUnreachable = 831, // SPIRVInstrInfo.td:643
847 OpVariable = 832, // SPIRVInstrInfo.td:253
848 OpVariableLengthArrayINTEL = 833, // SPIRVInstrInfo.td:290
849 OpVectorExtractDynamic = 834, // SPIRVInstrInfo.td:453
850 OpVectorInsertDynamic = 835, // SPIRVInstrInfo.td:455
851 OpVectorShuffle = 836, // SPIRVInstrInfo.td:457
852 OpVectorTimesMatrix = 837, // SPIRVInstrInfo.td:505
853 OpVectorTimesScalar = 838, // SPIRVInstrInfo.td:503
854 OpWritePipe = 839, // SPIRVInstrInfo.td:775
855 OpWritePipeBlockingALTERA = 840, // SPIRVInstrInfo.td:1109
856 INSTRUCTION_LIST_END = 841
857 };
858
859} // namespace llvm::SPIRV
860
861#endif // GET_INSTRINFO_ENUM
862
863#ifdef GET_INSTRINFO_SCHED_ENUM
864#undef GET_INSTRINFO_SCHED_ENUM
865
866namespace llvm::SPIRV::Sched {
867
868 enum {
869 NoInstrModel = 0,
870 SCHED_LIST_END = 1
871 };
872
873} // namespace llvm::SPIRV::Sched
874
875#endif // GET_INSTRINFO_SCHED_ENUM
876
877#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
878
879namespace llvm {
880
881struct SPIRVInstrTable {
882 MCInstrDesc Insts[841];
883 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
884 MCPhysReg ImplicitOps[1];
885 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
886 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
887 MCOperandInfo OperandInfo[484];
888};
889} // namespace llvm
890
891#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
892
893#ifdef GET_INSTRINFO_MC_DESC
894#undef GET_INSTRINFO_MC_DESC
895
896namespace llvm {
897
898static_assert((sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
899static constexpr unsigned SPIRVOpInfoBase = (sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) / sizeof(MCOperandInfo);
900
901extern const SPIRVInstrTable SPIRVDescs = {
902 {
903 { 840, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipeBlockingALTERA
904 { 839, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipe
905 { 838, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesScalar
906 { 837, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesMatrix
907 { 836, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorShuffle
908 { 835, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorInsertDynamic
909 { 834, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorExtractDynamic
910 { 833, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariableLengthArrayINTEL
911 { 832, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 481, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariable
912 { 831, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnreachable
913 { 830, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnordered
914 { 829, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUndef
915 { 828, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUMulExtended
916 { 827, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModV
917 { 826, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModS
918 { 825, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThanEqual
919 { 824, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThan
920 { 823, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThanEqual
921 { 822, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThan
922 { 821, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDotAccSat
923 { 820, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDot
924 { 819, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivV
925 { 818, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivS
926 { 817, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUConvert
927 { 816, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVoid
928 { 815, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 475, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVector
929 { 814, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStructContinuedINTEL
930 { 813, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStruct
931 { 812, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampler
932 { 811, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampledImage
933 { 810, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeRuntimeArray
934 { 809, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeReserveId
935 { 808, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeQueue
936 { 807, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePointer
937 { 806, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipeStorage
938 { 805, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 460, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipe
939 { 804, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 460, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeOpaque
940 { 803, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeNamedBarrier
941 { 802, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 475, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeMatrix
942 { 801, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 472, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeInt
943 { 800, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 464, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeImage
944 { 799, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFunction
945 { 798, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 460, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeForwardPointer
946 { 797, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFloat
947 { 796, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeEvent
948 { 795, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeDeviceEvent
949 { 794, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 455, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixNV
950 { 793, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 449, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixKHR
951 { 792, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeBool
952 { 791, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeArray
953 { 790, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeAccelerationStructureNV
954 { 789, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTranspose
955 { 788, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSwitch
956 { 787, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleXorINTEL
957 { 786, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleUpINTEL
958 { 785, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleINTEL
959 { 784, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleDownINTEL
960 { 783, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupMatrixMultiplyAccumulateINTEL
961 { 782, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 324, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockWriteINTEL
962 { 781, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockReadINTEL
963 { 780, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockWriteINTEL
964 { 779, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockReadINTEL
965 { 778, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockWriteINTEL
966 { 777, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockReadINTEL
967 { 776, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 426, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockStoreINTEL
968 { 775, 9, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 436, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockPrefetchINTEL
969 { 774, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 426, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransposeINTEL
970 { 773, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 426, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransformINTEL
971 { 772, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 426, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadINTEL
972 { 771, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpString
973 { 770, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubV
974 { 769, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubS
975 { 768, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemV
976 { 767, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemS
977 { 766, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulV
978 { 765, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulS
979 { 764, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivV
980 { 763, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivS
981 { 762, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddV
982 { 761, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddS
983 { 760, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStore
984 { 759, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantTrue
985 { 758, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 422, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantOp
986 { 757, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantFalse
987 { 756, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantCompositeContinuedINTEL
988 { 755, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantComposite
989 { 754, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 419, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstant
990 { 753, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceExtension
991 { 752, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceContinued
992 { 751, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSource
993 { 750, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSizeOf
994 { 749, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSignBitSet
995 { 748, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalV
996 { 747, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalS
997 { 746, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticV
998 { 745, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticS
999 { 744, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalV
1000 { 743, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalS
1001 { 742, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSetUserEventStatus
1002 { 741, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectionMerge
1003 { 740, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 414, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPVCond
1004 { 739, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 409, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPSCond
1005 { 738, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 404, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVIVCond
1006 { 737, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 399, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVISCond
1007 { 736, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 394, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFVCond
1008 { 735, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 389, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFSCond
1009 { 734, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 384, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPVCond
1010 { 733, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 379, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPSCond
1011 { 732, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 374, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSIVCond
1012 { 731, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 369, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSISCond
1013 { 730, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 364, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFVCond
1014 { 729, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 359, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFSCond
1015 { 728, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSaveMemoryINTEL
1016 { 727, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertUToS
1017 { 726, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertSToU
1018 { 725, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSampledImage
1019 { 724, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDotAccSat
1020 { 723, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDot
1021 { 722, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemV
1022 { 721, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemS
1023 { 720, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSNegate
1024 { 719, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMulExtended
1025 { 718, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMod
1026 { 717, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThanEqual
1027 { 716, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThan
1028 { 715, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThanEqual
1029 { 714, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThan
1030 { 713, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDotAccSat
1031 { 712, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDot
1032 { 711, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivV
1033 { 710, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivS
1034 { 709, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSConvert
1035 { 708, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRoundFToTF32INTEL
1036 { 707, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturnValue
1037 { 706, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturn
1038 { 705, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRetainEvent
1039 { 704, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRestoreMemoryINTEL
1040 { 703, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedWritePipe
1041 { 702, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedReadPipe
1042 { 701, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveWritePipePackets
1043 { 700, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveReadPipePackets
1044 { 699, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReleaseEvent
1045 { 698, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipeBlockingALTERA
1046 { 697, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipe
1047 { 696, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadClockKHR
1048 { 695, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpQuantizeToF16
1049 { 694, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrNotEqual
1050 { 693, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrEqual
1051 { 692, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrDiff
1052 { 691, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToGeneric
1053 { 690, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToCrossWorkgroupINTEL
1054 { 689, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrAccessChain
1055 { 688, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedStoreINTEL
1056 { 687, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedLoadINTEL
1057 { 686, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPhi
1058 { 685, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOuterProduct
1059 { 684, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOrdered
1060 { 683, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNot
1061 { 682, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNop
1062 { 681, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNoLine
1063 { 680, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNamedBarrierInitialize
1064 { 679, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 276, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpName
1065 { 678, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpModuleProcessed
1066 { 677, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryNamedBarrier
1067 { 676, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryModel
1068 { 675, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryBarrier
1069 { 674, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 352, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberName
1070 { 673, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 355, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorateString
1071 { 672, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 352, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorate
1072 { 671, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesVector
1073 { 670, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesScalar
1074 { 669, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesMatrix
1075 { 668, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedScatterINTEL
1076 { 667, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedGatherINTEL
1077 { 666, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopMerge
1078 { 665, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopControlINTEL
1079 { 664, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalOr
1080 { 663, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNotEqual
1081 { 662, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNot
1082 { 661, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalEqual
1083 { 660, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalAnd
1084 { 659, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoad
1085 { 658, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLine
1086 { 657, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 347, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStop
1087 { 656, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 347, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStart
1088 { 655, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLessOrGreater
1089 { 654, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLabel
1090 { 653, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpKill
1091 { 652, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidReserveId
1092 { 651, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidEvent
1093 { 650, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNormal
1094 { 649, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNan
1095 { 648, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsInf
1096 { 647, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsFinite
1097 { 646, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsPtrAccessChain
1098 { 645, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsAccessChain
1099 { 644, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageWrite
1100 { 643, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageTexelPointer
1101 { 642, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseTexelsResident
1102 { 641, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjImplicitLod
1103 { 640, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 334, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjExplicitLod
1104 { 639, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefImplicitLod
1105 { 638, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 334, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefExplicitLod
1106 { 637, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleImplicitLod
1107 { 636, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 341, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleExplicitLod
1108 { 635, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefImplicitLod
1109 { 634, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 334, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefExplicitLod
1110 { 633, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseRead
1111 { 632, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseGather
1112 { 631, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseFetch
1113 { 630, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseDrefGather
1114 { 629, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjImplicitLod
1115 { 628, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 334, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjExplicitLod
1116 { 627, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefImplicitLod
1117 { 626, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 334, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefExplicitLod
1118 { 625, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleImplicitLod
1119 { 624, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleFootprintNV
1120 { 623, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 341, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleExplicitLod
1121 { 622, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefImplicitLod
1122 { 621, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 334, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefExplicitLod
1123 { 620, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageRead
1124 { 619, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySizeLod
1125 { 618, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySize
1126 { 617, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySamples
1127 { 616, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryOrder
1128 { 615, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLod
1129 { 614, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLevels
1130 { 613, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryFormat
1131 { 612, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageGather
1132 { 611, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageFetch
1133 { 610, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageDrefGather
1134 { 609, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImage
1135 { 608, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubV
1136 { 607, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubS
1137 { 606, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowV
1138 { 605, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowS
1139 { 604, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpINotEqual
1140 { 603, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulV
1141 { 602, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulS
1142 { 601, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIEqual
1143 { 600, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddV
1144 { 599, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddS
1145 { 598, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryV
1146 { 597, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryS
1147 { 596, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupWaitEvents
1148 { 595, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMin
1149 { 594, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMax
1150 { 593, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMin
1151 { 592, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMax
1152 { 591, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 254, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveWritePipePackets
1153 { 590, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 254, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveReadPipePackets
1154 { 589, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMin
1155 { 588, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMax
1156 { 587, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleXor
1157 { 586, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleUp
1158 { 585, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleDown
1159 { 584, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffle
1160 { 583, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMin
1161 { 582, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMax
1162 { 581, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformRotateKHR
1163 { 580, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformQuadSwap
1164 { 579, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalXor
1165 { 578, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalOr
1166 { 577, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalAnd
1167 { 576, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformInverseBallot
1168 { 575, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIMul
1169 { 574, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIAdd
1170 { 573, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMul
1171 { 572, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMin
1172 { 571, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMax
1173 { 570, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFAdd
1174 { 569, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformElect
1175 { 568, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcastFirst
1176 { 567, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcast
1177 { 566, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseXor
1178 { 565, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseOr
1179 { 564, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseAnd
1180 { 563, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindMSB
1181 { 562, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindLSB
1182 { 561, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitExtract
1183 { 560, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitCount
1184 { 559, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallot
1185 { 558, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAny
1186 { 557, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAllEqual
1187 { 556, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAll
1188 { 555, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 319, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalXorKHR
1189 { 554, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 319, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalOrKHR
1190 { 553, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 319, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalAndKHR
1191 { 552, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 319, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIMulKHR
1192 { 551, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIAdd
1193 { 550, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 319, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMulKHR
1194 { 549, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMin
1195 { 548, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMax
1196 { 547, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFAdd
1197 { 546, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 324, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitWritePipe
1198 { 545, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 324, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitReadPipe
1199 { 544, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBroadcast
1200 { 543, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 319, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseXorKHR
1201 { 542, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 319, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseOrKHR
1202 { 541, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 319, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseAndKHR
1203 { 540, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAsyncCopy
1204 { 539, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAny
1205 { 538, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAll
1206 { 537, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetNumPipePackets
1207 { 536, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetMaxPipePackets
1208 { 535, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetDefaultQueue
1209 { 534, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericPtrMemSemantics
1210 { 533, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 315, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtrExplicit
1211 { 532, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtr
1212 { 531, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthFine
1213 { 530, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthCoarse
1214 { 529, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidth
1215 { 528, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionPointerCallINTEL
1216 { 527, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionParameter
1217 { 526, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionEnd
1218 { 525, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionCall
1219 { 524, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 311, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunction
1220 { 523, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFmaKHR
1221 { 522, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSqrtALTERA
1222 { 521, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinPiALTERA
1223 { 520, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosPiALTERA
1224 { 519, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosALTERA
1225 { 518, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinALTERA
1226 { 517, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRsqrtALTERA
1227 { 516, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRecipALTERA
1228 { 515, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedLogALTERA
1229 { 514, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedExpALTERA
1230 { 513, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosPiALTERA
1231 { 512, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosALTERA
1232 { 511, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordNotEqual
1233 { 510, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThanEqual
1234 { 509, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThan
1235 { 508, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThanEqual
1236 { 507, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThan
1237 { 506, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordEqual
1238 { 505, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubV
1239 { 504, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubS
1240 { 503, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemV
1241 { 502, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemS
1242 { 501, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdNotEqual
1243 { 500, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThanEqual
1244 { 499, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThan
1245 { 498, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThanEqual
1246 { 497, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThan
1247 { 496, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdEqual
1248 { 495, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 308, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegateV
1249 { 494, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegate
1250 { 493, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulV
1251 { 492, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulS
1252 { 491, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMod
1253 { 490, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivV
1254 { 489, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivS
1255 { 488, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFConvert
1256 { 487, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 304, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddV
1257 { 486, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 300, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddS
1258 { 485, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtension
1259 { 484, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInstImport
1260 { 483, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 296, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInst
1261 { 482, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExpectKHR
1262 { 481, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionModeId
1263 { 480, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionMode
1264 { 479, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 293, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEntryPoint
1265 { 478, 12, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 281, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEnqueueKernel
1266 { 477, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndStreamPrimitive
1267 { 476, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndPrimitive
1268 { 475, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitVertex
1269 { 474, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitStreamVertex
1270 { 473, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDot
1271 { 472, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDemoteToHelperInvocation
1272 { 471, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateString
1273 { 470, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 276, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateId
1274 { 469, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 276, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorate
1275 { 468, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyFine
1276 { 467, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyCoarse
1277 { 466, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdy
1278 { 465, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxFine
1279 { 464, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxCoarse
1280 { 463, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdx
1281 { 462, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCrossWorkgroupCastToPtrINTEL
1282 { 461, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCreateUserEvent
1283 { 460, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyObject
1284 { 459, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemorySized
1285 { 458, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemory
1286 { 457, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyLogical
1287 { 456, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreKHR
1288 { 455, 7, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 269, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreCheckedINTEL
1289 { 454, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 264, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixPrefetchINTEL
1290 { 453, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixMulAddKHR
1291 { 452, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadKHR
1292 { 451, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadCheckedINTEL
1293 { 450, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 261, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLengthKHR
1294 { 449, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixGetElementCoordINTEL
1295 { 448, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 254, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixConstructCheckedINTEL
1296 { 447, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToPtr
1297 { 446, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToF
1298 { 445, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertSToF
1299 { 444, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertPtrToU
1300 { 443, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSamplerINTEL
1301 { 442, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSampledImageINTEL
1302 { 441, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToImageINTEL
1303 { 440, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToU
1304 { 439, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToS
1305 { 438, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToBF16INTEL
1306 { 437, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertBF16ToFINTEL
1307 { 436, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierWaitINTEL
1308 { 435, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierArriveINTEL
1309 { 434, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrier
1310 { 433, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 244, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantTrue
1311 { 432, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 249, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantSampler
1312 { 431, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantNull
1313 { 430, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantI
1314 { 429, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFunctionPointerINTEL
1315 { 428, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 244, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFalse
1316 { 427, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantF
1317 { 426, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantCompositeContinuedINTEL
1318 { 425, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantComposite
1319 { 424, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeInsert
1320 { 423, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeExtract
1321 { 422, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstructContinuedINTEL
1322 { 421, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstruct
1323 { 420, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitWritePipe
1324 { 419, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitReadPipe
1325 { 418, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCaptureEventProfilingInfo
1326 { 417, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCapability
1327 { 416, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBuildNDRange
1328 { 415, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranchConditional
1329 { 414, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranch
1330 { 413, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorV
1331 { 412, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorS
1332 { 411, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrV
1333 { 410, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrS
1334 { 409, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseFunctionINTEL
1335 { 408, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndV
1336 { 407, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndS
1337 { 406, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitcast
1338 { 405, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitReverse
1339 { 404, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldUExtract
1340 { 403, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldSExtract
1341 { 402, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldInsert
1342 { 401, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitCount
1343 { 400, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicXor
1344 { 399, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMin
1345 { 398, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMax
1346 { 397, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicStore
1347 { 396, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMin
1348 { 395, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMax
1349 { 394, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicOr
1350 { 393, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicLoad
1351 { 392, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicISub
1352 { 391, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIIncrement
1353 { 390, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIDecrement
1354 { 389, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIAdd
1355 { 388, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagTestAndSet
1356 { 387, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagClear
1357 { 386, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMinEXT
1358 { 385, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMaxEXT
1359 { 384, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFAddEXT
1360 { 383, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicExchange
1361 { 382, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchangeWeak
1362 { 381, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchange
1363 { 380, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicAnd
1364 { 379, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAssumeTrueKHR
1365 { 378, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmTargetINTEL
1366 { 377, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 190, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmINTEL
1367 { 376, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmCallINTEL
1368 { 375, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 186, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArrayLength
1369 { 374, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArithmeticFenceEXT
1370 { 373, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSubALTERA
1371 { 372, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSqrtALTERA
1372 { 371, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinPiALTERA
1373 { 370, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosPiALTERA
1374 { 369, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosALTERA
1375 { 368, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinALTERA
1376 { 367, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRecipALTERA
1377 { 366, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRSqrtALTERA
1378 { 365, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowRALTERA
1379 { 364, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowNALTERA
1380 { 363, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowALTERA
1381 { 362, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatMulALTERA
1382 { 361, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLogALTERA
1383 { 360, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog2ALTERA
1384 { 359, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog1pALTERA
1385 { 358, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog10ALTERA
1386 { 357, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLTALTERA
1387 { 356, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLEALTERA
1388 { 355, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatHypotALTERA
1389 { 354, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGTALTERA
1390 { 353, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGEALTERA
1391 { 352, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpm1ALTERA
1392 { 351, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpALTERA
1393 { 350, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp2ALTERA
1394 { 349, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp10ALTERA
1395 { 348, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatEQALTERA
1396 { 347, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatDivALTERA
1397 { 346, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosPiALTERA
1398 { 345, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosALTERA
1399 { 344, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCbrtALTERA
1400 { 343, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastToIntALTERA
1401 { 342, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastFromIntALTERA
1402 { 341, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastALTERA
1403 { 340, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatAddALTERA
1404 { 339, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanPiALTERA
1405 { 338, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanALTERA
1406 { 337, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATan2ALTERA
1407 { 336, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinPiALTERA
1408 { 335, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinALTERA
1409 { 334, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosPiALTERA
1410 { 333, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosALTERA
1411 { 332, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAny
1412 { 331, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAll
1413 { 330, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeListDeclINTEL
1414 { 329, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeDeclINTEL
1415 { 328, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasDomainDeclINTEL
1416 { 327, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAccessChain
1417 { 326, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNKNOWN_type
1418 { 325, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASSIGN_TYPE
1419 { 324, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1420 { 323, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1421 { 322, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1422 { 321, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1423 { 320, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1424 { 319, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1425 { 318, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1426 { 317, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1427 { 316, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1428 { 315, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1429 { 314, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1430 { 313, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1431 { 312, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1432 { 311, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1433 { 310, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1434 { 309, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1435 { 308, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1436 { 307, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1437 { 306, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1438 { 305, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1439 { 304, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1440 { 303, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1441 { 302, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1442 { 301, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1443 { 300, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1444 { 299, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1445 { 298, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1446 { 297, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1447 { 296, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1448 { 295, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1449 { 294, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1450 { 293, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1451 { 292, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1452 { 291, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1453 { 290, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1454 { 289, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1455 { 288, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1456 { 287, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1457 { 286, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1458 { 285, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1459 { 284, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1460 { 283, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1461 { 282, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1462 { 281, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1463 { 280, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1464 { 279, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1465 { 278, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1466 { 277, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1467 { 276, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1468 { 275, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1469 { 274, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1470 { 273, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1471 { 272, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1472 { 271, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1473 { 270, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1474 { 269, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1475 { 268, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1476 { 267, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1477 { 266, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1478 { 265, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1479 { 264, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1480 { 263, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1481 { 262, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1482 { 261, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
1483 { 260, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1484 { 259, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
1485 { 258, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1486 { 257, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1487 { 256, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1488 { 255, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1489 { 254, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1490 { 253, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1491 { 252, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1492 { 251, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1493 { 250, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1494 { 249, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1495 { 248, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1496 { 247, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1497 { 246, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1498 { 245, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1499 { 244, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1500 { 243, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1501 { 242, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1502 { 241, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1503 { 240, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1504 { 239, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1505 { 238, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1506 { 237, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1507 { 236, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1508 { 235, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1509 { 234, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1510 { 233, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1511 { 232, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1512 { 231, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1513 { 230, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1514 { 229, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1515 { 228, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1516 { 227, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1517 { 226, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1518 { 225, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1519 { 224, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1520 { 223, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1521 { 222, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1522 { 221, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1523 { 220, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1524 { 219, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1525 { 218, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1526 { 217, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1527 { 216, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1528 { 215, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1529 { 214, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1530 { 213, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1531 { 212, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1532 { 211, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1533 { 210, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1534 { 209, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1535 { 208, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1536 { 207, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1537 { 206, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1538 { 205, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1539 { 204, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1540 { 203, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1541 { 202, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1542 { 201, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1543 { 200, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1544 { 199, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1545 { 198, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1546 { 197, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1547 { 196, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1548 { 195, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1549 { 194, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1550 { 193, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1551 { 192, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1552 { 191, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1553 { 190, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1554 { 189, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1555 { 188, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1556 { 187, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1557 { 186, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1558 { 185, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1559 { 184, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1560 { 183, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1561 { 182, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1562 { 181, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1563 { 180, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1564 { 179, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1565 { 178, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1566 { 177, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1567 { 176, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1568 { 175, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1569 { 174, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1570 { 173, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1571 { 172, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1572 { 171, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1573 { 170, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1574 { 169, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1575 { 168, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1576 { 167, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1577 { 166, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1578 { 165, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1579 { 164, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1580 { 163, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1581 { 162, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1582 { 161, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1583 { 160, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1584 { 159, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1585 { 158, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1586 { 157, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1587 { 156, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1588 { 155, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1589 { 154, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1590 { 153, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1591 { 152, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1592 { 151, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1593 { 150, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1594 { 149, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1595 { 148, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1596 { 147, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1597 { 146, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1598 { 145, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1599 { 144, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1600 { 143, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1601 { 142, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1602 { 141, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1603 { 140, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1604 { 139, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1605 { 138, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1606 { 137, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1607 { 136, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1608 { 135, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1609 { 134, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1610 { 133, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1611 { 132, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1612 { 131, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1613 { 130, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1614 { 129, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1615 { 128, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1616 { 127, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1617 { 126, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1618 { 125, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1619 { 124, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1620 { 123, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1621 { 122, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1622 { 121, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1623 { 120, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1624 { 119, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1625 { 118, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1626 { 117, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1627 { 116, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1628 { 115, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1629 { 114, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1630 { 113, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1631 { 112, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1632 { 111, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1633 { 110, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1634 { 109, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1635 { 108, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1636 { 107, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1637 { 106, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1638 { 105, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1639 { 104, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1640 { 103, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1641 { 102, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1642 { 101, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1643 { 100, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1644 { 99, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1645 { 98, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1646 { 97, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1647 { 96, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1648 { 95, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1649 { 94, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1650 { 93, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1651 { 92, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1652 { 91, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1653 { 90, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1654 { 89, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1655 { 88, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1656 { 87, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1657 { 86, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1658 { 85, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1659 { 84, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1660 { 83, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1661 { 82, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1662 { 81, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1663 { 80, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1664 { 79, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1665 { 78, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1666 { 77, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1667 { 76, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1668 { 75, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1669 { 74, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1670 { 73, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1671 { 72, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1672 { 71, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1673 { 70, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1674 { 69, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1675 { 68, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1676 { 67, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1677 { 66, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1678 { 65, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1679 { 64, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1680 { 63, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1681 { 62, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1682 { 61, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1683 { 60, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1684 { 59, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1685 { 58, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1686 { 57, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1687 { 56, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1688 { 55, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1689 { 54, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1690 { 53, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1691 { 52, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1692 { 51, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1693 { 50, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1694 { 49, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1695 { 48, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1696 { 47, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1697 { 46, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1698 { 45, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1699 { 44, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1700 { 43, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1701 { 42, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_20917
1702 { 41, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_20916
1703 { 40, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1704 { 39, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1705 { 38, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1706 { 37, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1707 { 36, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1708 { 35, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1709 { 34, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1710 { 33, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1711 { 32, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_20915
1712 { 31, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1713 { 30, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13542
1714 { 29, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1715 { 28, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1716 { 27, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1717 { 26, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1718 { 25, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1719 { 24, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1720 { 23, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1721 { 22, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1722 { 21, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1723 { 20, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1724 { 19, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1725 { 18, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1726 { 17, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1727 { 16, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1728 { 15, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1729 { 14, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1730 { 13, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1731 { 12, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1732 { 11, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1733 { 10, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1734 { 9, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1735 { 8, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1736 { 7, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1737 { 6, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1738 { 5, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1739 { 4, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1740 { 3, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1741 { 2, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1742 { 1, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1743 { 0, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1744 }, {
1745 /* 0 */
1746 }, {
1747 0
1748 }, {
1749 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1750 /* 1 */
1751 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1752 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1753 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1754 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1755 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1756 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1757 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1758 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1759 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1760 /* 28 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1761 /* 29 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1762 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1763 /* 34 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1764 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1765 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1766 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1767 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1768 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1769 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1770 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1771 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1772 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1773 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1774 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1775 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1776 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1777 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1778 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1779 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1780 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1781 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1782 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1783 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1784 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1785 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1786 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1787 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1788 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1789 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1790 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1791 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1792 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1793 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1794 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1795 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1796 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1797 /* 151 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1798 /* 154 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1799 /* 156 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1800 /* 159 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1801 /* 160 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1802 /* 162 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1803 /* 170 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1804 /* 180 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1805 /* 186 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1806 /* 190 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1807 /* 196 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1808 /* 198 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1809 /* 204 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1810 /* 212 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1811 /* 215 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1812 /* 220 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1813 /* 224 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1814 /* 228 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1815 /* 232 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1816 /* 235 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1817 /* 237 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1818 /* 241 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1819 /* 244 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1820 /* 246 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1821 /* 249 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1822 /* 254 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1823 /* 261 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1824 /* 264 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1825 /* 269 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1826 /* 276 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1827 /* 278 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1828 /* 281 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1829 /* 293 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1830 /* 296 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1831 /* 300 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1832 /* 304 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1833 /* 308 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1834 /* 311 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1835 /* 315 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1836 /* 319 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1837 /* 324 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1838 /* 329 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1839 /* 334 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1840 /* 341 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1841 /* 347 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1842 /* 349 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1843 /* 352 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1844 /* 355 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1845 /* 359 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1846 /* 364 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1847 /* 369 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1848 /* 374 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1849 /* 379 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1850 /* 384 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1851 /* 389 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1852 /* 394 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1853 /* 399 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1854 /* 404 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1855 /* 409 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1856 /* 414 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1857 /* 419 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1858 /* 422 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1859 /* 426 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1860 /* 436 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1861 /* 445 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1862 /* 446 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1863 /* 449 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1864 /* 455 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1865 /* 460 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1866 /* 462 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1867 /* 464 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1868 /* 472 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1869 /* 475 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1870 /* 478 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1871 /* 481 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1872 }
1873};
1874
1875
1876#ifdef __GNUC__
1877#pragma GCC diagnostic push
1878#pragma GCC diagnostic ignored "-Woverlength-strings"
1879#endif
1880extern const char SPIRVInstrNameData[] = {
1881 /* 0 */ "G_FLOG10\000"
1882 /* 9 */ "G_FEXP10\000"
1883 /* 18 */ "G_FLOG2\000"
1884 /* 26 */ "G_FATAN2\000"
1885 /* 35 */ "G_FEXP2\000"
1886 /* 43 */ "OpQuantizeToF16\000"
1887 /* 59 */ "G_FMA\000"
1888 /* 65 */ "G_STRICT_FMA\000"
1889 /* 78 */ "OpArbitraryFloatLog10ALTERA\000"
1890 /* 106 */ "OpArbitraryFloatExp10ALTERA\000"
1891 /* 134 */ "OpArbitraryFloatExpm1ALTERA\000"
1892 /* 162 */ "OpArbitraryFloatLog2ALTERA\000"
1893 /* 189 */ "OpArbitraryFloatATan2ALTERA\000"
1894 /* 217 */ "OpArbitraryFloatExp2ALTERA\000"
1895 /* 244 */ "OpArbitraryFloatGEALTERA\000"
1896 /* 269 */ "OpArbitraryFloatLEALTERA\000"
1897 /* 294 */ "OpArbitraryFloatPowNALTERA\000"
1898 /* 321 */ "OpArbitraryFloatEQALTERA\000"
1899 /* 346 */ "OpArbitraryFloatPowRALTERA\000"
1900 /* 373 */ "OpArbitraryFloatGTALTERA\000"
1901 /* 398 */ "OpArbitraryFloatLTALTERA\000"
1902 /* 423 */ "OpArbitraryFloatSubALTERA\000"
1903 /* 449 */ "OpArbitraryFloatAddALTERA\000"
1904 /* 475 */ "OpReadPipeBlockingALTERA\000"
1905 /* 500 */ "OpWritePipeBlockingALTERA\000"
1906 /* 526 */ "OpFixedLogALTERA\000"
1907 /* 543 */ "OpArbitraryFloatLogALTERA\000"
1908 /* 569 */ "OpArbitraryFloatATanPiALTERA\000"
1909 /* 598 */ "OpArbitraryFloatASinPiALTERA\000"
1910 /* 627 */ "OpFixedSinPiALTERA\000"
1911 /* 646 */ "OpArbitraryFloatSinPiALTERA\000"
1912 /* 674 */ "OpArbitraryFloatACosPiALTERA\000"
1913 /* 703 */ "OpFixedCosPiALTERA\000"
1914 /* 722 */ "OpFixedSinCosPiALTERA\000"
1915 /* 744 */ "OpArbitraryFloatSinCosPiALTERA\000"
1916 /* 775 */ "OpArbitraryFloatCosPiALTERA\000"
1917 /* 803 */ "OpArbitraryFloatMulALTERA\000"
1918 /* 829 */ "OpArbitraryFloatATanALTERA\000"
1919 /* 856 */ "OpArbitraryFloatASinALTERA\000"
1920 /* 883 */ "OpFixedSinALTERA\000"
1921 /* 900 */ "OpArbitraryFloatSinALTERA\000"
1922 /* 926 */ "OpArbitraryFloatLog1pALTERA\000"
1923 /* 954 */ "OpFixedRecipALTERA\000"
1924 /* 973 */ "OpArbitraryFloatRecipALTERA\000"
1925 /* 1001 */ "OpFixedExpALTERA\000"
1926 /* 1018 */ "OpArbitraryFloatExpALTERA\000"
1927 /* 1044 */ "OpArbitraryFloatACosALTERA\000"
1928 /* 1071 */ "OpFixedCosALTERA\000"
1929 /* 1088 */ "OpFixedSinCosALTERA\000"
1930 /* 1108 */ "OpArbitraryFloatSinCosALTERA\000"
1931 /* 1137 */ "OpArbitraryFloatCosALTERA\000"
1932 /* 1163 */ "OpArbitraryFloatCastFromIntALTERA\000"
1933 /* 1197 */ "OpArbitraryFloatCastToIntALTERA\000"
1934 /* 1229 */ "OpArbitraryFloatHypotALTERA\000"
1935 /* 1257 */ "OpArbitraryFloatCbrtALTERA\000"
1936 /* 1284 */ "OpArbitraryFloatRSqrtALTERA\000"
1937 /* 1312 */ "OpFixedSqrtALTERA\000"
1938 /* 1330 */ "OpArbitraryFloatSqrtALTERA\000"
1939 /* 1357 */ "OpFixedRsqrtALTERA\000"
1940 /* 1376 */ "OpArbitraryFloatCastALTERA\000"
1941 /* 1403 */ "OpArbitraryFloatDivALTERA\000"
1942 /* 1429 */ "OpArbitraryFloatPowALTERA\000"
1943 /* 1455 */ "OpGroupNonUniformBallotFindLSB\000"
1944 /* 1486 */ "OpGroupNonUniformBallotFindMSB\000"
1945 /* 1517 */ "G_FSUB\000"
1946 /* 1524 */ "G_STRICT_FSUB\000"
1947 /* 1538 */ "G_ATOMICRMW_FSUB\000"
1948 /* 1555 */ "G_SUB\000"
1949 /* 1561 */ "G_ATOMICRMW_SUB\000"
1950 /* 1577 */ "G_INTRINSIC\000"
1951 /* 1589 */ "G_FPTRUNC\000"
1952 /* 1599 */ "G_INTRINSIC_TRUNC\000"
1953 /* 1617 */ "G_TRUNC\000"
1954 /* 1625 */ "G_BUILD_VECTOR_TRUNC\000"
1955 /* 1646 */ "G_DYN_STACKALLOC\000"
1956 /* 1663 */ "G_FMAD\000"
1957 /* 1670 */ "G_INDEXED_SEXTLOAD\000"
1958 /* 1689 */ "G_SEXTLOAD\000"
1959 /* 1700 */ "G_INDEXED_ZEXTLOAD\000"
1960 /* 1719 */ "G_ZEXTLOAD\000"
1961 /* 1730 */ "G_INDEXED_LOAD\000"
1962 /* 1745 */ "G_LOAD\000"
1963 /* 1752 */ "G_VECREDUCE_FADD\000"
1964 /* 1769 */ "G_FADD\000"
1965 /* 1776 */ "G_VECREDUCE_SEQ_FADD\000"
1966 /* 1797 */ "G_STRICT_FADD\000"
1967 /* 1811 */ "G_ATOMICRMW_FADD\000"
1968 /* 1828 */ "G_VECREDUCE_ADD\000"
1969 /* 1844 */ "G_ADD\000"
1970 /* 1850 */ "G_PTR_ADD\000"
1971 /* 1860 */ "G_ATOMICRMW_ADD\000"
1972 /* 1876 */ "G_ATOMICRMW_NAND\000"
1973 /* 1893 */ "G_VECREDUCE_AND\000"
1974 /* 1909 */ "G_AND\000"
1975 /* 1915 */ "G_ATOMICRMW_AND\000"
1976 /* 1931 */ "LIFETIME_END\000"
1977 /* 1944 */ "G_BRCOND\000"
1978 /* 1953 */ "G_ATOMICRMW_USUB_COND\000"
1979 /* 1975 */ "G_LLROUND\000"
1980 /* 1985 */ "G_LROUND\000"
1981 /* 1994 */ "G_INTRINSIC_ROUND\000"
1982 /* 2012 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1983 /* 2038 */ "LOAD_STACK_GUARD\000"
1984 /* 2055 */ "PSEUDO_PROBE\000"
1985 /* 2068 */ "G_SSUBE\000"
1986 /* 2076 */ "G_USUBE\000"
1987 /* 2084 */ "G_FENCE\000"
1988 /* 2092 */ "ARITH_FENCE\000"
1989 /* 2104 */ "REG_SEQUENCE\000"
1990 /* 2117 */ "G_SADDE\000"
1991 /* 2125 */ "G_UADDE\000"
1992 /* 2133 */ "G_GET_FPMODE\000"
1993 /* 2146 */ "G_RESET_FPMODE\000"
1994 /* 2161 */ "G_SET_FPMODE\000"
1995 /* 2174 */ "G_FMINNUM_IEEE\000"
1996 /* 2189 */ "G_FMAXNUM_IEEE\000"
1997 /* 2204 */ "G_VSCALE\000"
1998 /* 2213 */ "G_JUMP_TABLE\000"
1999 /* 2226 */ "BUNDLE\000"
2000 /* 2233 */ "G_MEMCPY_INLINE\000"
2001 /* 2249 */ "RELOC_NONE\000"
2002 /* 2260 */ "LOCAL_ESCAPE\000"
2003 /* 2273 */ "ASSIGN_TYPE\000"
2004 /* 2285 */ "G_STACKRESTORE\000"
2005 /* 2300 */ "G_INDEXED_STORE\000"
2006 /* 2316 */ "G_STORE\000"
2007 /* 2324 */ "G_BITREVERSE\000"
2008 /* 2337 */ "FAKE_USE\000"
2009 /* 2346 */ "DBG_VALUE\000"
2010 /* 2356 */ "G_GLOBAL_VALUE\000"
2011 /* 2371 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2012 /* 2394 */ "CONVERGENCECTRL_GLUE\000"
2013 /* 2415 */ "G_STACKSAVE\000"
2014 /* 2427 */ "G_MEMMOVE\000"
2015 /* 2437 */ "G_FREEZE\000"
2016 /* 2446 */ "G_FCANONICALIZE\000"
2017 /* 2462 */ "G_FMODF\000"
2018 /* 2470 */ "G_CTLZ_ZERO_UNDEF\000"
2019 /* 2488 */ "G_CTTZ_ZERO_UNDEF\000"
2020 /* 2506 */ "INIT_UNDEF\000"
2021 /* 2517 */ "G_IMPLICIT_DEF\000"
2022 /* 2532 */ "DBG_INSTR_REF\000"
2023 /* 2546 */ "OpConvertSToF\000"
2024 /* 2560 */ "OpConvertUToF\000"
2025 /* 2574 */ "OpConstantF\000"
2026 /* 2586 */ "G_FNEG\000"
2027 /* 2593 */ "EXTRACT_SUBREG\000"
2028 /* 2608 */ "INSERT_SUBREG\000"
2029 /* 2622 */ "G_SEXT_INREG\000"
2030 /* 2635 */ "SUBREG_TO_REG\000"
2031 /* 2649 */ "G_ATOMIC_CMPXCHG\000"
2032 /* 2666 */ "G_ATOMICRMW_XCHG\000"
2033 /* 2683 */ "G_GET_ROUNDING\000"
2034 /* 2698 */ "G_SET_ROUNDING\000"
2035 /* 2713 */ "G_FLOG\000"
2036 /* 2720 */ "G_VAARG\000"
2037 /* 2728 */ "PREALLOCATED_ARG\000"
2038 /* 2745 */ "G_PREFETCH\000"
2039 /* 2756 */ "G_SMULH\000"
2040 /* 2764 */ "G_UMULH\000"
2041 /* 2772 */ "G_FTANH\000"
2042 /* 2780 */ "G_FSINH\000"
2043 /* 2788 */ "G_FCOSH\000"
2044 /* 2796 */ "DBG_PHI\000"
2045 /* 2804 */ "G_FPTOSI\000"
2046 /* 2813 */ "G_FPTOUI\000"
2047 /* 2822 */ "G_FPOWI\000"
2048 /* 2830 */ "OpConstantI\000"
2049 /* 2842 */ "COPY_LANEMASK\000"
2050 /* 2856 */ "G_PTRMASK\000"
2051 /* 2866 */ "GC_LABEL\000"
2052 /* 2875 */ "DBG_LABEL\000"
2053 /* 2885 */ "EH_LABEL\000"
2054 /* 2894 */ "ANNOTATION_LABEL\000"
2055 /* 2911 */ "ICALL_BRANCH_FUNNEL\000"
2056 /* 2931 */ "OpRoundFToTF32INTEL\000"
2057 /* 2951 */ "OpConvertFToBF16INTEL\000"
2058 /* 2973 */ "OpConvertBF16ToFINTEL\000"
2059 /* 2995 */ "OpSubgroupImageMediaBlockReadINTEL\000"
2060 /* 3030 */ "OpSubgroupImageBlockReadINTEL\000"
2061 /* 3060 */ "OpSubgroupBlockReadINTEL\000"
2062 /* 3085 */ "OpPredicatedLoadINTEL\000"
2063 /* 3107 */ "OpSubgroup2DBlockLoadINTEL\000"
2064 /* 3134 */ "OpCooperativeMatrixLoadCheckedINTEL\000"
2065 /* 3170 */ "OpCooperativeMatrixStoreCheckedINTEL\000"
2066 /* 3207 */ "OpCooperativeMatrixConstructCheckedINTEL\000"
2067 /* 3248 */ "OpSpecConstantCompositeContinuedINTEL\000"
2068 /* 3286 */ "OpConstantCompositeContinuedINTEL\000"
2069 /* 3320 */ "OpTypeStructContinuedINTEL\000"
2070 /* 3347 */ "OpCompositeConstructContinuedINTEL\000"
2071 /* 3382 */ "OpCooperativeMatrixGetElementCoordINTEL\000"
2072 /* 3422 */ "OpConvertHandleToSampledImageINTEL\000"
2073 /* 3457 */ "OpConvertHandleToImageINTEL\000"
2074 /* 3485 */ "OpSubgroupShuffleINTEL\000"
2075 /* 3508 */ "OpPredicatedStoreINTEL\000"
2076 /* 3531 */ "OpSubgroup2DBlockStoreINTEL\000"
2077 /* 3559 */ "OpSubgroup2DBlockLoadTransposeINTEL\000"
2078 /* 3595 */ "OpSubgroupMatrixMultiplyAccumulateINTEL\000"
2079 /* 3635 */ "OpSubgroupImageMediaBlockWriteINTEL\000"
2080 /* 3671 */ "OpSubgroupImageBlockWriteINTEL\000"
2081 /* 3702 */ "OpSubgroupBlockWriteINTEL\000"
2082 /* 3728 */ "OpControlBarrierArriveINTEL\000"
2083 /* 3756 */ "OpSubgroup2DBlockPrefetchINTEL\000"
2084 /* 3787 */ "OpCooperativeMatrixPrefetchINTEL\000"
2085 /* 3820 */ "OpAliasScopeDeclINTEL\000"
2086 /* 3842 */ "OpAliasDomainDeclINTEL\000"
2087 /* 3865 */ "OpAliasScopeListDeclINTEL\000"
2088 /* 3891 */ "OpAsmCallINTEL\000"
2089 /* 3906 */ "OpFunctionPointerCallINTEL\000"
2090 /* 3933 */ "OpLoopControlINTEL\000"
2091 /* 3952 */ "OpSubgroup2DBlockLoadTransformINTEL\000"
2092 /* 3988 */ "OpAsmINTEL\000"
2093 /* 3999 */ "OpBitwiseFunctionINTEL\000"
2094 /* 4022 */ "OpSubgroupShuffleDownINTEL\000"
2095 /* 4049 */ "OpSubgroupShuffleUpINTEL\000"
2096 /* 4074 */ "OpPtrCastToCrossWorkgroupINTEL\000"
2097 /* 4105 */ "OpMaskedGatherINTEL\000"
2098 /* 4125 */ "OpConvertHandleToSamplerINTEL\000"
2099 /* 4155 */ "OpConstantFunctionPointerINTEL\000"
2100 /* 4186 */ "OpMaskedScatterINTEL\000"
2101 /* 4207 */ "OpSubgroupShuffleXorINTEL\000"
2102 /* 4233 */ "OpCrossWorkgroupCastToPtrINTEL\000"
2103 /* 4264 */ "OpAsmTargetINTEL\000"
2104 /* 4281 */ "OpControlBarrierWaitINTEL\000"
2105 /* 4307 */ "OpVariableLengthArrayINTEL\000"
2106 /* 4334 */ "OpRestoreMemoryINTEL\000"
2107 /* 4355 */ "OpSaveMemoryINTEL\000"
2108 /* 4373 */ "G_FSHL\000"
2109 /* 4380 */ "G_SHL\000"
2110 /* 4386 */ "G_FCEIL\000"
2111 /* 4394 */ "G_SAVGCEIL\000"
2112 /* 4405 */ "G_UAVGCEIL\000"
2113 /* 4416 */ "PATCHABLE_TAIL_CALL\000"
2114 /* 4436 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2115 /* 4463 */ "PATCHABLE_EVENT_CALL\000"
2116 /* 4484 */ "FENTRY_CALL\000"
2117 /* 4496 */ "KILL\000"
2118 /* 4501 */ "G_CONSTANT_POOL\000"
2119 /* 4517 */ "G_ROTL\000"
2120 /* 4524 */ "G_VECREDUCE_FMUL\000"
2121 /* 4541 */ "G_FMUL\000"
2122 /* 4548 */ "G_VECREDUCE_SEQ_FMUL\000"
2123 /* 4569 */ "G_STRICT_FMUL\000"
2124 /* 4583 */ "G_VECREDUCE_MUL\000"
2125 /* 4599 */ "G_MUL\000"
2126 /* 4605 */ "G_FREM\000"
2127 /* 4612 */ "G_STRICT_FREM\000"
2128 /* 4626 */ "G_SREM\000"
2129 /* 4633 */ "G_UREM\000"
2130 /* 4640 */ "G_SDIVREM\000"
2131 /* 4650 */ "G_UDIVREM\000"
2132 /* 4660 */ "INLINEASM\000"
2133 /* 4670 */ "G_VECREDUCE_FMINIMUM\000"
2134 /* 4691 */ "G_FMINIMUM\000"
2135 /* 4702 */ "G_ATOMICRMW_FMINIMUM\000"
2136 /* 4723 */ "G_VECREDUCE_FMAXIMUM\000"
2137 /* 4744 */ "G_FMAXIMUM\000"
2138 /* 4755 */ "G_ATOMICRMW_FMAXIMUM\000"
2139 /* 4776 */ "G_FMINIMUMNUM\000"
2140 /* 4790 */ "G_ATOMICRMW_FMINIMUMNUM\000"
2141 /* 4814 */ "G_FMAXIMUMNUM\000"
2142 /* 4828 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
2143 /* 4852 */ "G_FMINNUM\000"
2144 /* 4862 */ "G_FMAXNUM\000"
2145 /* 4872 */ "G_FATAN\000"
2146 /* 4880 */ "G_FTAN\000"
2147 /* 4887 */ "G_INTRINSIC_ROUNDEVEN\000"
2148 /* 4909 */ "G_ASSERT_ALIGN\000"
2149 /* 4924 */ "G_FCOPYSIGN\000"
2150 /* 4936 */ "G_VECREDUCE_FMIN\000"
2151 /* 4953 */ "G_ATOMICRMW_FMIN\000"
2152 /* 4970 */ "G_VECREDUCE_SMIN\000"
2153 /* 4987 */ "G_SMIN\000"
2154 /* 4994 */ "G_VECREDUCE_UMIN\000"
2155 /* 5011 */ "G_UMIN\000"
2156 /* 5018 */ "G_ATOMICRMW_UMIN\000"
2157 /* 5035 */ "G_ATOMICRMW_MIN\000"
2158 /* 5051 */ "G_FASIN\000"
2159 /* 5059 */ "G_FSIN\000"
2160 /* 5066 */ "CFI_INSTRUCTION\000"
2161 /* 5082 */ "G_SSUBO\000"
2162 /* 5090 */ "G_USUBO\000"
2163 /* 5098 */ "G_SADDO\000"
2164 /* 5106 */ "G_UADDO\000"
2165 /* 5114 */ "JUMP_TABLE_DEBUG_INFO\000"
2166 /* 5136 */ "G_SMULO\000"
2167 /* 5144 */ "G_UMULO\000"
2168 /* 5152 */ "G_BZERO\000"
2169 /* 5160 */ "STACKMAP\000"
2170 /* 5169 */ "G_DEBUGTRAP\000"
2171 /* 5181 */ "G_UBSANTRAP\000"
2172 /* 5193 */ "G_TRAP\000"
2173 /* 5200 */ "G_ATOMICRMW_UDEC_WRAP\000"
2174 /* 5222 */ "G_ATOMICRMW_UINC_WRAP\000"
2175 /* 5244 */ "G_BSWAP\000"
2176 /* 5252 */ "G_SITOFP\000"
2177 /* 5261 */ "G_UITOFP\000"
2178 /* 5270 */ "G_FCMP\000"
2179 /* 5277 */ "G_ICMP\000"
2180 /* 5284 */ "G_SCMP\000"
2181 /* 5291 */ "G_UCMP\000"
2182 /* 5298 */ "CONVERGENCECTRL_LOOP\000"
2183 /* 5319 */ "G_CTPOP\000"
2184 /* 5327 */ "PATCHABLE_OP\000"
2185 /* 5340 */ "FAULTING_OP\000"
2186 /* 5352 */ "PREALLOCATED_SETUP\000"
2187 /* 5371 */ "G_FLDEXP\000"
2188 /* 5380 */ "G_STRICT_FLDEXP\000"
2189 /* 5396 */ "G_FEXP\000"
2190 /* 5403 */ "G_FFREXP\000"
2191 /* 5412 */ "G_BR\000"
2192 /* 5417 */ "INLINEASM_BR\000"
2193 /* 5430 */ "G_BLOCK_ADDR\000"
2194 /* 5443 */ "MEMBARRIER\000"
2195 /* 5454 */ "G_CONSTANT_FOLD_BARRIER\000"
2196 /* 5478 */ "PATCHABLE_FUNCTION_ENTER\000"
2197 /* 5503 */ "G_READCYCLECOUNTER\000"
2198 /* 5522 */ "G_READSTEADYCOUNTER\000"
2199 /* 5542 */ "G_READ_REGISTER\000"
2200 /* 5558 */ "G_WRITE_REGISTER\000"
2201 /* 5575 */ "OpFmaKHR\000"
2202 /* 5584 */ "OpCooperativeMatrixLoadKHR\000"
2203 /* 5611 */ "OpCooperativeMatrixMulAddKHR\000"
2204 /* 5640 */ "OpGroupBitwiseAndKHR\000"
2205 /* 5661 */ "OpGroupLogicalAndKHR\000"
2206 /* 5682 */ "OpCooperativeMatrixStoreKHR\000"
2207 /* 5710 */ "OpGroupNonUniformRotateKHR\000"
2208 /* 5737 */ "OpAssumeTrueKHR\000"
2209 /* 5753 */ "OpCooperativeMatrixLengthKHR\000"
2210 /* 5782 */ "OpReadClockKHR\000"
2211 /* 5797 */ "OpGroupFMulKHR\000"
2212 /* 5812 */ "OpGroupIMulKHR\000"
2213 /* 5827 */ "OpGroupBitwiseOrKHR\000"
2214 /* 5847 */ "OpGroupLogicalOrKHR\000"
2215 /* 5867 */ "OpGroupBitwiseXorKHR\000"
2216 /* 5888 */ "OpGroupLogicalXorKHR\000"
2217 /* 5909 */ "OpExpectKHR\000"
2218 /* 5921 */ "OpTypeCooperativeMatrixKHR\000"
2219 /* 5948 */ "G_ASHR\000"
2220 /* 5955 */ "G_FSHR\000"
2221 /* 5962 */ "G_LSHR\000"
2222 /* 5969 */ "CONVERGENCECTRL_ANCHOR\000"
2223 /* 5992 */ "G_FFLOOR\000"
2224 /* 6001 */ "G_SAVGFLOOR\000"
2225 /* 6013 */ "G_UAVGFLOOR\000"
2226 /* 6025 */ "G_EXTRACT_SUBVECTOR\000"
2227 /* 6045 */ "G_INSERT_SUBVECTOR\000"
2228 /* 6064 */ "G_BUILD_VECTOR\000"
2229 /* 6079 */ "G_SHUFFLE_VECTOR\000"
2230 /* 6096 */ "G_STEP_VECTOR\000"
2231 /* 6110 */ "G_SPLAT_VECTOR\000"
2232 /* 6125 */ "G_VECREDUCE_XOR\000"
2233 /* 6141 */ "G_XOR\000"
2234 /* 6147 */ "G_ATOMICRMW_XOR\000"
2235 /* 6163 */ "G_VECREDUCE_OR\000"
2236 /* 6178 */ "G_OR\000"
2237 /* 6183 */ "G_ATOMICRMW_OR\000"
2238 /* 6198 */ "G_ROTR\000"
2239 /* 6205 */ "G_INTTOPTR\000"
2240 /* 6216 */ "G_FABS\000"
2241 /* 6223 */ "G_ABS\000"
2242 /* 6229 */ "G_ABDS\000"
2243 /* 6236 */ "G_UNMERGE_VALUES\000"
2244 /* 6253 */ "G_MERGE_VALUES\000"
2245 /* 6268 */ "G_CTLS\000"
2246 /* 6275 */ "G_FACOS\000"
2247 /* 6283 */ "G_FCOS\000"
2248 /* 6290 */ "G_FSINCOS\000"
2249 /* 6300 */ "G_CONCAT_VECTORS\000"
2250 /* 6317 */ "COPY_TO_REGCLASS\000"
2251 /* 6334 */ "G_IS_FPCLASS\000"
2252 /* 6347 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2253 /* 6377 */ "G_VECTOR_COMPRESS\000"
2254 /* 6395 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2255 /* 6422 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2256 /* 6460 */ "G_TRUNC_SSAT_S\000"
2257 /* 6475 */ "OpFSubS\000"
2258 /* 6483 */ "OpStrictFSubS\000"
2259 /* 6497 */ "OpISubS\000"
2260 /* 6505 */ "OpShiftRightArithmeticS\000"
2261 /* 6529 */ "OpFAddS\000"
2262 /* 6537 */ "OpStrictFAddS\000"
2263 /* 6551 */ "OpIAddS\000"
2264 /* 6559 */ "OpBitwiseAndS\000"
2265 /* 6573 */ "OpUModS\000"
2266 /* 6581 */ "OpShiftLeftLogicalS\000"
2267 /* 6601 */ "OpShiftRightLogicalS\000"
2268 /* 6622 */ "OpFMulS\000"
2269 /* 6630 */ "OpStrictFMulS\000"
2270 /* 6644 */ "OpIMulS\000"
2271 /* 6652 */ "OpFRemS\000"
2272 /* 6660 */ "OpStrictFRemS\000"
2273 /* 6674 */ "OpSRemS\000"
2274 /* 6682 */ "OpConvertFToS\000"
2275 /* 6696 */ "OpSatConvertUToS\000"
2276 /* 6713 */ "OpBitwiseOrS\000"
2277 /* 6726 */ "OpBitwiseXorS\000"
2278 /* 6740 */ "OpFDivS\000"
2279 /* 6748 */ "OpStrictFDivS\000"
2280 /* 6762 */ "OpSDivS\000"
2281 /* 6770 */ "OpUDivS\000"
2282 /* 6778 */ "OpISubBorrowS\000"
2283 /* 6792 */ "OpIAddCarryS\000"
2284 /* 6805 */ "G_SSUBSAT\000"
2285 /* 6815 */ "G_USUBSAT\000"
2286 /* 6825 */ "G_SADDSAT\000"
2287 /* 6835 */ "G_UADDSAT\000"
2288 /* 6845 */ "G_SSHLSAT\000"
2289 /* 6855 */ "G_USHLSAT\000"
2290 /* 6865 */ "G_SMULFIXSAT\000"
2291 /* 6878 */ "G_UMULFIXSAT\000"
2292 /* 6891 */ "G_SDIVFIXSAT\000"
2293 /* 6904 */ "G_UDIVFIXSAT\000"
2294 /* 6917 */ "G_ATOMICRMW_USUB_SAT\000"
2295 /* 6938 */ "G_FPTOSI_SAT\000"
2296 /* 6951 */ "G_FPTOUI_SAT\000"
2297 /* 6964 */ "G_EXTRACT\000"
2298 /* 6974 */ "G_SELECT\000"
2299 /* 6983 */ "G_BRINDIRECT\000"
2300 /* 6996 */ "PATCHABLE_RET\000"
2301 /* 7010 */ "G_MEMSET\000"
2302 /* 7019 */ "PATCHABLE_FUNCTION_EXIT\000"
2303 /* 7043 */ "G_BRJT\000"
2304 /* 7050 */ "G_EXTRACT_VECTOR_ELT\000"
2305 /* 7071 */ "G_INSERT_VECTOR_ELT\000"
2306 /* 7091 */ "G_FCONSTANT\000"
2307 /* 7103 */ "G_CONSTANT\000"
2308 /* 7114 */ "G_INTRINSIC_CONVERGENT\000"
2309 /* 7137 */ "STATEPOINT\000"
2310 /* 7148 */ "PATCHPOINT\000"
2311 /* 7159 */ "G_PTRTOINT\000"
2312 /* 7170 */ "G_FRINT\000"
2313 /* 7178 */ "G_INTRINSIC_LLRINT\000"
2314 /* 7197 */ "G_INTRINSIC_LRINT\000"
2315 /* 7215 */ "G_FNEARBYINT\000"
2316 /* 7228 */ "G_VASTART\000"
2317 /* 7238 */ "LIFETIME_START\000"
2318 /* 7253 */ "G_INVOKE_REGION_START\000"
2319 /* 7275 */ "G_INSERT\000"
2320 /* 7284 */ "G_FSQRT\000"
2321 /* 7292 */ "G_STRICT_FSQRT\000"
2322 /* 7307 */ "G_BITCAST\000"
2323 /* 7317 */ "G_ADDRSPACE_CAST\000"
2324 /* 7334 */ "DBG_VALUE_LIST\000"
2325 /* 7349 */ "G_FPEXT\000"
2326 /* 7357 */ "G_SEXT\000"
2327 /* 7364 */ "G_ASSERT_SEXT\000"
2328 /* 7378 */ "G_ANYEXT\000"
2329 /* 7387 */ "G_ZEXT\000"
2330 /* 7394 */ "G_ASSERT_ZEXT\000"
2331 /* 7408 */ "OpAtomicFAddEXT\000"
2332 /* 7424 */ "OpArithmeticFenceEXT\000"
2333 /* 7445 */ "OpAtomicFMinEXT\000"
2334 /* 7461 */ "OpAtomicFMaxEXT\000"
2335 /* 7477 */ "G_ABDU\000"
2336 /* 7484 */ "G_TRUNC_SSAT_U\000"
2337 /* 7499 */ "G_TRUNC_USAT_U\000"
2338 /* 7514 */ "OpConvertFToU\000"
2339 /* 7528 */ "OpSatConvertSToU\000"
2340 /* 7545 */ "OpConvertPtrToU\000"
2341 /* 7561 */ "G_FDIV\000"
2342 /* 7568 */ "G_STRICT_FDIV\000"
2343 /* 7582 */ "G_SDIV\000"
2344 /* 7589 */ "G_UDIV\000"
2345 /* 7596 */ "G_GET_FPENV\000"
2346 /* 7608 */ "G_RESET_FPENV\000"
2347 /* 7622 */ "G_SET_FPENV\000"
2348 /* 7634 */ "OpTypeAccelerationStructureNV\000"
2349 /* 7664 */ "OpImageSampleFootprintNV\000"
2350 /* 7689 */ "OpTypeCooperativeMatrixNV\000"
2351 /* 7715 */ "OpFSubV\000"
2352 /* 7723 */ "OpStrictFSubV\000"
2353 /* 7737 */ "OpISubV\000"
2354 /* 7745 */ "OpShiftRightArithmeticV\000"
2355 /* 7769 */ "OpFAddV\000"
2356 /* 7777 */ "OpStrictFAddV\000"
2357 /* 7791 */ "OpIAddV\000"
2358 /* 7799 */ "OpBitwiseAndV\000"
2359 /* 7813 */ "OpUModV\000"
2360 /* 7821 */ "OpFNegateV\000"
2361 /* 7832 */ "OpShiftLeftLogicalV\000"
2362 /* 7852 */ "OpShiftRightLogicalV\000"
2363 /* 7873 */ "OpFMulV\000"
2364 /* 7881 */ "OpStrictFMulV\000"
2365 /* 7895 */ "OpIMulV\000"
2366 /* 7903 */ "OpFRemV\000"
2367 /* 7911 */ "OpStrictFRemV\000"
2368 /* 7925 */ "OpSRemV\000"
2369 /* 7933 */ "OpBitwiseOrV\000"
2370 /* 7946 */ "OpBitwiseXorV\000"
2371 /* 7960 */ "OpFDivV\000"
2372 /* 7968 */ "OpStrictFDivV\000"
2373 /* 7982 */ "OpSDivV\000"
2374 /* 7990 */ "OpUDivV\000"
2375 /* 7998 */ "OpISubBorrowV\000"
2376 /* 8012 */ "OpIAddCarryV\000"
2377 /* 8025 */ "G_FPOW\000"
2378 /* 8032 */ "G_VECREDUCE_FMAX\000"
2379 /* 8049 */ "G_ATOMICRMW_FMAX\000"
2380 /* 8066 */ "G_VECREDUCE_SMAX\000"
2381 /* 8083 */ "G_SMAX\000"
2382 /* 8090 */ "G_VECREDUCE_UMAX\000"
2383 /* 8107 */ "G_UMAX\000"
2384 /* 8114 */ "G_ATOMICRMW_UMAX\000"
2385 /* 8131 */ "G_ATOMICRMW_MAX\000"
2386 /* 8147 */ "G_FRAME_INDEX\000"
2387 /* 8161 */ "G_SBFX\000"
2388 /* 8168 */ "G_UBFX\000"
2389 /* 8175 */ "G_SMULFIX\000"
2390 /* 8185 */ "G_UMULFIX\000"
2391 /* 8195 */ "G_SDIVFIX\000"
2392 /* 8205 */ "G_UDIVFIX\000"
2393 /* 8215 */ "G_MEMCPY\000"
2394 /* 8224 */ "COPY\000"
2395 /* 8229 */ "CONVERGENCECTRL_ENTRY\000"
2396 /* 8251 */ "G_CTLZ\000"
2397 /* 8258 */ "G_CTTZ\000"
2398 /* 8265 */ "OpAtomicISub\000"
2399 /* 8278 */ "OpVectorExtractDynamic\000"
2400 /* 8301 */ "OpVectorInsertDynamic\000"
2401 /* 8323 */ "OpPtrCastToGeneric\000"
2402 /* 8342 */ "OpExecutionModeId\000"
2403 /* 8360 */ "OpDecorateId\000"
2404 /* 8373 */ "OpIsValidReserveId\000"
2405 /* 8392 */ "OpTypeReserveId\000"
2406 /* 8408 */ "OpImageRead\000"
2407 /* 8420 */ "OpImageSparseRead\000"
2408 /* 8438 */ "OpAtomicLoad\000"
2409 /* 8451 */ "OpLoad\000"
2410 /* 8458 */ "OpGroupNonUniformFAdd\000"
2411 /* 8480 */ "OpGroupFAdd\000"
2412 /* 8492 */ "OpAtomicIAdd\000"
2413 /* 8505 */ "OpGroupNonUniformIAdd\000"
2414 /* 8527 */ "OpGroupIAdd\000"
2415 /* 8539 */ "OpSMulExtended\000"
2416 /* 8554 */ "OpUMulExtended\000"
2417 /* 8569 */ "OpOrdered\000"
2418 /* 8579 */ "OpUnordered\000"
2419 /* 8591 */ "OpModuleProcessed\000"
2420 /* 8609 */ "OpSourceContinued\000"
2421 /* 8627 */ "OpCopyMemorySized\000"
2422 /* 8645 */ "OpTypeVoid\000"
2423 /* 8656 */ "OpAtomicAnd\000"
2424 /* 8668 */ "OpGroupNonUniformBitwiseAnd\000"
2425 /* 8696 */ "OpGroupNonUniformLogicalAnd\000"
2426 /* 8724 */ "OpLogicalAnd\000"
2427 /* 8737 */ "OpFunctionEnd\000"
2428 /* 8751 */ "OpSelectSFSCond\000"
2429 /* 8767 */ "OpSelectVFSCond\000"
2430 /* 8783 */ "OpSelectSISCond\000"
2431 /* 8799 */ "OpSelectVISCond\000"
2432 /* 8815 */ "OpSelectSPSCond\000"
2433 /* 8831 */ "OpSelectVPSCond\000"
2434 /* 8847 */ "OpSelectSFVCond\000"
2435 /* 8863 */ "OpSelectVFVCond\000"
2436 /* 8879 */ "OpSelectSIVCond\000"
2437 /* 8895 */ "OpSelectVIVCond\000"
2438 /* 8911 */ "OpSelectSPVCond\000"
2439 /* 8927 */ "OpSelectVPVCond\000"
2440 /* 8943 */ "OpImageQuerySizeLod\000"
2441 /* 8963 */ "OpImageSampleImplicitLod\000"
2442 /* 8988 */ "OpImageSparseSampleImplicitLod\000"
2443 /* 9019 */ "OpImageSampleDrefImplicitLod\000"
2444 /* 9048 */ "OpImageSparseSampleDrefImplicitLod\000"
2445 /* 9083 */ "OpImageSampleProjDrefImplicitLod\000"
2446 /* 9116 */ "OpImageSparseSampleProjDrefImplicitLod\000"
2447 /* 9155 */ "OpImageSampleProjImplicitLod\000"
2448 /* 9184 */ "OpImageSparseSampleProjImplicitLod\000"
2449 /* 9219 */ "OpImageSampleExplicitLod\000"
2450 /* 9244 */ "OpImageSparseSampleExplicitLod\000"
2451 /* 9275 */ "OpImageSampleDrefExplicitLod\000"
2452 /* 9304 */ "OpImageSparseSampleDrefExplicitLod\000"
2453 /* 9339 */ "OpImageSampleProjDrefExplicitLod\000"
2454 /* 9372 */ "OpImageSparseSampleProjDrefExplicitLod\000"
2455 /* 9411 */ "OpImageSampleProjExplicitLod\000"
2456 /* 9440 */ "OpImageSparseSampleProjExplicitLod\000"
2457 /* 9475 */ "OpImageQueryLod\000"
2458 /* 9491 */ "OpFMod\000"
2459 /* 9498 */ "OpSMod\000"
2460 /* 9505 */ "OpSource\000"
2461 /* 9514 */ "OpExecutionMode\000"
2462 /* 9530 */ "OpTypeSampledImage\000"
2463 /* 9549 */ "OpSampledImage\000"
2464 /* 9564 */ "OpTypeImage\000"
2465 /* 9576 */ "OpImage\000"
2466 /* 9584 */ "OpTypePipeStorage\000"
2467 /* 9602 */ "OpBuildNDRange\000"
2468 /* 9617 */ "OpAtomicExchange\000"
2469 /* 9634 */ "OpAtomicCompareExchange\000"
2470 /* 9658 */ "OpSelectionMerge\000"
2471 /* 9675 */ "OpLoopMerge\000"
2472 /* 9687 */ "OpUnreachable\000"
2473 /* 9701 */ "OpVariable\000"
2474 /* 9712 */ "OpGroupNonUniformShuffle\000"
2475 /* 9737 */ "OpVectorShuffle\000"
2476 /* 9753 */ "OpName\000"
2477 /* 9760 */ "OpMemberName\000"
2478 /* 9773 */ "OpFwidthFine\000"
2479 /* 9786 */ "OpDPdxFine\000"
2480 /* 9797 */ "OpDPdyFine\000"
2481 /* 9808 */ "OpNoLine\000"
2482 /* 9817 */ "OpLine\000"
2483 /* 9824 */ "OpReservedReadPipe\000"
2484 /* 9843 */ "OpReadPipe\000"
2485 /* 9854 */ "OpCommitReadPipe\000"
2486 /* 9871 */ "OpGroupCommitReadPipe\000"
2487 /* 9893 */ "OpTypePipe\000"
2488 /* 9904 */ "OpReservedWritePipe\000"
2489 /* 9924 */ "OpWritePipe\000"
2490 /* 9936 */ "OpCommitWritePipe\000"
2491 /* 9954 */ "OpGroupCommitWritePipe\000"
2492 /* 9977 */ "UNKNOWN_type\000"
2493 /* 9990 */ "OpAtomicStore\000"
2494 /* 10004 */ "OpStore\000"
2495 /* 10012 */ "OpSpecConstantFalse\000"
2496 /* 10032 */ "OpConstantFalse\000"
2497 /* 10048 */ "OpTranspose\000"
2498 /* 10060 */ "OpFwidthCoarse\000"
2499 /* 10075 */ "OpDPdxCoarse\000"
2500 /* 10088 */ "OpDPdyCoarse\000"
2501 /* 10101 */ "OpBitReverse\000"
2502 /* 10114 */ "OpFNegate\000"
2503 /* 10124 */ "OpSNegate\000"
2504 /* 10134 */ "OpDecorate\000"
2505 /* 10145 */ "OpMemberDecorate\000"
2506 /* 10162 */ "OpIsFinite\000"
2507 /* 10173 */ "OpImageWrite\000"
2508 /* 10186 */ "OpSpecConstantComposite\000"
2509 /* 10210 */ "OpConstantComposite\000"
2510 /* 10230 */ "OpTypeQueue\000"
2511 /* 10242 */ "OpGetDefaultQueue\000"
2512 /* 10260 */ "OpReturnValue\000"
2513 /* 10274 */ "OpTypeOpaque\000"
2514 /* 10287 */ "OpSpecConstantTrue\000"
2515 /* 10306 */ "OpConstantTrue\000"
2516 /* 10321 */ "OpEndPrimitive\000"
2517 /* 10336 */ "OpEndStreamPrimitive\000"
2518 /* 10357 */ "OpImageQuerySize\000"
2519 /* 10374 */ "OpNamedBarrierInitialize\000"
2520 /* 10399 */ "OpSizeOf\000"
2521 /* 10408 */ "OpUndef\000"
2522 /* 10416 */ "OpPtrDiff\000"
2523 /* 10426 */ "OpIsInf\000"
2524 /* 10434 */ "OpDecorateString\000"
2525 /* 10451 */ "OpMemberDecorateString\000"
2526 /* 10474 */ "OpString\000"
2527 /* 10483 */ "OpBranch\000"
2528 /* 10492 */ "OpImageFetch\000"
2529 /* 10505 */ "OpImageSparseFetch\000"
2530 /* 10524 */ "OpSwitch\000"
2531 /* 10533 */ "OpFwidth\000"
2532 /* 10542 */ "OpArrayLength\000"
2533 /* 10556 */ "OpPhi\000"
2534 /* 10562 */ "OpAtomicCompareExchangeWeak\000"
2535 /* 10590 */ "OpCopyLogical\000"
2536 /* 10604 */ "OpIsNormal\000"
2537 /* 10615 */ "OpBranchConditional\000"
2538 /* 10635 */ "OpIEqual\000"
2539 /* 10644 */ "OpFOrdEqual\000"
2540 /* 10656 */ "OpFUnordEqual\000"
2541 /* 10670 */ "OpLogicalEqual\000"
2542 /* 10685 */ "OpGroupNonUniformAllEqual\000"
2543 /* 10711 */ "OpSGreaterThanEqual\000"
2544 /* 10731 */ "OpUGreaterThanEqual\000"
2545 /* 10751 */ "OpFOrdGreaterThanEqual\000"
2546 /* 10774 */ "OpFUnordGreaterThanEqual\000"
2547 /* 10799 */ "OpSLessThanEqual\000"
2548 /* 10816 */ "OpULessThanEqual\000"
2549 /* 10833 */ "OpFOrdLessThanEqual\000"
2550 /* 10853 */ "OpFUnordLessThanEqual\000"
2551 /* 10875 */ "OpPtrEqual\000"
2552 /* 10886 */ "OpINotEqual\000"
2553 /* 10898 */ "OpFOrdNotEqual\000"
2554 /* 10913 */ "OpFUnordNotEqual\000"
2555 /* 10930 */ "OpLogicalNotEqual\000"
2556 /* 10948 */ "OpPtrNotEqual\000"
2557 /* 10962 */ "OpLabel\000"
2558 /* 10970 */ "OpMemoryModel\000"
2559 /* 10984 */ "OpEnqueueKernel\000"
2560 /* 11000 */ "OpGroupNonUniformAll\000"
2561 /* 11021 */ "OpAll\000"
2562 /* 11027 */ "OpGroupAll\000"
2563 /* 11038 */ "OpFunctionCall\000"
2564 /* 11053 */ "OpKill\000"
2565 /* 11060 */ "OpConstantNull\000"
2566 /* 11075 */ "OpTypeBool\000"
2567 /* 11086 */ "OpGroupNonUniformFMul\000"
2568 /* 11108 */ "OpGroupNonUniformIMul\000"
2569 /* 11130 */ "OpIsNan\000"
2570 /* 11138 */ "OpSGreaterThan\000"
2571 /* 11153 */ "OpUGreaterThan\000"
2572 /* 11168 */ "OpFOrdGreaterThan\000"
2573 /* 11186 */ "OpFUnordGreaterThan\000"
2574 /* 11206 */ "OpSLessThan\000"
2575 /* 11218 */ "OpULessThan\000"
2576 /* 11230 */ "OpFOrdLessThan\000"
2577 /* 11245 */ "OpFUnordLessThan\000"
2578 /* 11262 */ "OpGroupNonUniformFMin\000"
2579 /* 11284 */ "OpGroupFMin\000"
2580 /* 11296 */ "OpAtomicSMin\000"
2581 /* 11309 */ "OpGroupNonUniformSMin\000"
2582 /* 11331 */ "OpGroupSMin\000"
2583 /* 11343 */ "OpAtomicUMin\000"
2584 /* 11356 */ "OpGroupNonUniformUMin\000"
2585 /* 11378 */ "OpGroupUMin\000"
2586 /* 11390 */ "OpAccessChain\000"
2587 /* 11404 */ "OpPtrAccessChain\000"
2588 /* 11421 */ "OpInBoundsPtrAccessChain\000"
2589 /* 11446 */ "OpInBoundsAccessChain\000"
2590 /* 11468 */ "OpSourceExtension\000"
2591 /* 11486 */ "OpExtension\000"
2592 /* 11498 */ "OpDemoteToHelperInvocation\000"
2593 /* 11525 */ "OpTypeFunction\000"
2594 /* 11540 */ "OpFunction\000"
2595 /* 11551 */ "OpReturn\000"
2596 /* 11560 */ "OpGroupNonUniformShuffleDown\000"
2597 /* 11589 */ "OpCaptureEventProfilingInfo\000"
2598 /* 11617 */ "OpSpecConstantOp\000"
2599 /* 11634 */ "OpGroupNonUniformShuffleUp\000"
2600 /* 11661 */ "OpGroupNonUniformQuadSwap\000"
2601 /* 11687 */ "OpNop\000"
2602 /* 11693 */ "OpLifetimeStop\000"
2603 /* 11708 */ "OpAtomicOr\000"
2604 /* 11719 */ "OpGroupNonUniformBitwiseOr\000"
2605 /* 11746 */ "OpGroupNonUniformLogicalOr\000"
2606 /* 11773 */ "OpLogicalOr\000"
2607 /* 11785 */ "OpAtomicFlagClear\000"
2608 /* 11803 */ "OpVectorTimesScalar\000"
2609 /* 11823 */ "OpMatrixTimesScalar\000"
2610 /* 11843 */ "OpImageQueryOrder\000"
2611 /* 11861 */ "OpImageGather\000"
2612 /* 11875 */ "OpImageSparseGather\000"
2613 /* 11895 */ "OpImageDrefGather\000"
2614 /* 11913 */ "OpImageSparseDrefGather\000"
2615 /* 11937 */ "OpTypeNamedBarrier\000"
2616 /* 11956 */ "OpMemoryNamedBarrier\000"
2617 /* 11977 */ "OpControlBarrier\000"
2618 /* 11994 */ "OpMemoryBarrier\000"
2619 /* 12010 */ "OpTypeSampler\000"
2620 /* 12024 */ "OpConstantSampler\000"
2621 /* 12042 */ "OpLessOrGreater\000"
2622 /* 12058 */ "OpFunctionParameter\000"
2623 /* 12078 */ "OpTypeForwardPointer\000"
2624 /* 12099 */ "OpTypePointer\000"
2625 /* 12113 */ "OpImageTexelPointer\000"
2626 /* 12133 */ "OpAtomicXor\000"
2627 /* 12145 */ "OpGroupNonUniformShuffleXor\000"
2628 /* 12173 */ "OpGroupNonUniformBitwiseXor\000"
2629 /* 12201 */ "OpGroupNonUniformLogicalXor\000"
2630 /* 12229 */ "OpTypeVector\000"
2631 /* 12242 */ "OpMatrixTimesVector\000"
2632 /* 12262 */ "OpConvertUToPtr\000"
2633 /* 12278 */ "OpGenericCastToPtr\000"
2634 /* 12297 */ "OpGenericPtrMemSemantics\000"
2635 /* 12322 */ "OpImageQuerySamples\000"
2636 /* 12342 */ "OpImageQueryLevels\000"
2637 /* 12361 */ "OpReserveReadPipePackets\000"
2638 /* 12386 */ "OpGroupReserveReadPipePackets\000"
2639 /* 12416 */ "OpReserveWritePipePackets\000"
2640 /* 12442 */ "OpGroupReserveWritePipePackets\000"
2641 /* 12473 */ "OpGetNumPipePackets\000"
2642 /* 12493 */ "OpGetMaxPipePackets\000"
2643 /* 12513 */ "OpGroupWaitEvents\000"
2644 /* 12531 */ "OpSetUserEventStatus\000"
2645 /* 12552 */ "OpSDotAccSat\000"
2646 /* 12565 */ "OpSUDotAccSat\000"
2647 /* 12579 */ "OpUDotAccSat\000"
2648 /* 12592 */ "OpImageQueryFormat\000"
2649 /* 12611 */ "OpTypeFloat\000"
2650 /* 12623 */ "OpBitFieldSExtract\000"
2651 /* 12642 */ "OpBitFieldUExtract\000"
2652 /* 12661 */ "OpCompositeExtract\000"
2653 /* 12680 */ "OpGroupNonUniformBallotBitExtract\000"
2654 /* 12714 */ "OpCopyObject\000"
2655 /* 12727 */ "OpGroupNonUniformElect\000"
2656 /* 12750 */ "OpOuterProduct\000"
2657 /* 12765 */ "OpTypeStruct\000"
2658 /* 12778 */ "OpCompositeConstruct\000"
2659 /* 12799 */ "OpAtomicFlagTestAndSet\000"
2660 /* 12822 */ "OpSignBitSet\000"
2661 /* 12835 */ "OpGenericCastToPtrExplicit\000"
2662 /* 12862 */ "OpTypeInt\000"
2663 /* 12872 */ "OpSpecConstant\000"
2664 /* 12887 */ "OpImageSparseTexelsResident\000"
2665 /* 12915 */ "OpAtomicIDecrement\000"
2666 /* 12934 */ "OpAtomicIIncrement\000"
2667 /* 12953 */ "OpIsValidEvent\000"
2668 /* 12968 */ "OpTypeDeviceEvent\000"
2669 /* 12986 */ "OpTypeEvent\000"
2670 /* 12998 */ "OpReleaseEvent\000"
2671 /* 13013 */ "OpRetainEvent\000"
2672 /* 13027 */ "OpCreateUserEvent\000"
2673 /* 13045 */ "OpEntryPoint\000"
2674 /* 13058 */ "OpBitCount\000"
2675 /* 13069 */ "OpGroupNonUniformBallotBitCount\000"
2676 /* 13101 */ "OpSDot\000"
2677 /* 13108 */ "OpSUDot\000"
2678 /* 13116 */ "OpUDot\000"
2679 /* 13123 */ "OpDot\000"
2680 /* 13129 */ "OpLogicalNot\000"
2681 /* 13142 */ "OpNot\000"
2682 /* 13148 */ "OpGroupNonUniformInverseBallot\000"
2683 /* 13179 */ "OpGroupNonUniformBallot\000"
2684 /* 13203 */ "OpLifetimeStart\000"
2685 /* 13219 */ "OpBitFieldInsert\000"
2686 /* 13236 */ "OpCompositeInsert\000"
2687 /* 13254 */ "OpFConvert\000"
2688 /* 13265 */ "OpSConvert\000"
2689 /* 13276 */ "OpUConvert\000"
2690 /* 13287 */ "OpExtInstImport\000"
2691 /* 13303 */ "OpGroupNonUniformBroadcast\000"
2692 /* 13330 */ "OpGroupBroadcast\000"
2693 /* 13347 */ "OpBitcast\000"
2694 /* 13357 */ "OpExtInst\000"
2695 /* 13367 */ "OpGroupNonUniformBroadcastFirst\000"
2696 /* 13399 */ "OpGroupNonUniformFMax\000"
2697 /* 13421 */ "OpGroupFMax\000"
2698 /* 13433 */ "OpAtomicSMax\000"
2699 /* 13446 */ "OpGroupNonUniformSMax\000"
2700 /* 13468 */ "OpGroupSMax\000"
2701 /* 13480 */ "OpAtomicUMax\000"
2702 /* 13493 */ "OpGroupNonUniformUMax\000"
2703 /* 13515 */ "OpGroupUMax\000"
2704 /* 13527 */ "OpDPdx\000"
2705 /* 13534 */ "OpEmitStreamVertex\000"
2706 /* 13553 */ "OpEmitVertex\000"
2707 /* 13566 */ "OpTypeMatrix\000"
2708 /* 13579 */ "OpVectorTimesMatrix\000"
2709 /* 13599 */ "OpMatrixTimesMatrix\000"
2710 /* 13619 */ "OpTypeRuntimeArray\000"
2711 /* 13638 */ "OpTypeArray\000"
2712 /* 13650 */ "OpDPdy\000"
2713 /* 13657 */ "OpGroupNonUniformAny\000"
2714 /* 13678 */ "OpAny\000"
2715 /* 13684 */ "OpGroupAny\000"
2716 /* 13695 */ "OpGroupAsyncCopy\000"
2717 /* 13712 */ "OpCopyMemory\000"
2718 /* 13725 */ "OpCapability\000"
2719};
2720#ifdef __GNUC__
2721#pragma GCC diagnostic pop
2722#endif
2723
2724extern const unsigned SPIRVInstrNameIndices[] = {
2725 2800U, 4660U, 5417U, 5066U, 2885U, 2866U, 2894U, 4496U,
2726 2593U, 2608U, 2519U, 2506U, 2635U, 6317U, 2346U, 7334U,
2727 2532U, 2796U, 2875U, 2104U, 8224U, 2842U, 2226U, 7238U,
2728 1931U, 2055U, 2092U, 5160U, 4484U, 7148U, 2038U, 5352U,
2729 2728U, 7137U, 2260U, 5340U, 5327U, 5478U, 6996U, 7019U,
2730 4416U, 4463U, 4436U, 2911U, 2337U, 5443U, 5114U, 2249U,
2731 8229U, 5969U, 5298U, 2394U, 7364U, 7394U, 4909U, 1844U,
2732 1555U, 4599U, 7582U, 7589U, 4626U, 4633U, 4640U, 4650U,
2733 1909U, 6178U, 6141U, 6229U, 7477U, 6013U, 4405U, 6001U,
2734 4394U, 2517U, 2798U, 8147U, 2356U, 2371U, 4501U, 6964U,
2735 6236U, 7275U, 6253U, 6064U, 1625U, 6300U, 7159U, 6205U,
2736 7307U, 2437U, 5454U, 2012U, 1599U, 1994U, 7197U, 7178U,
2737 4887U, 5503U, 5522U, 1745U, 1689U, 1719U, 1730U, 1670U,
2738 1700U, 2316U, 2300U, 6347U, 2649U, 2666U, 1860U, 1561U,
2739 1915U, 1876U, 6183U, 6147U, 8131U, 5035U, 8114U, 5018U,
2740 1811U, 1538U, 8049U, 4953U, 4755U, 4702U, 4828U, 4790U,
2741 5222U, 5200U, 1953U, 6917U, 2084U, 2745U, 1944U, 6983U,
2742 7253U, 1577U, 6395U, 7114U, 6422U, 7378U, 1617U, 6460U,
2743 7484U, 7499U, 7103U, 7091U, 7228U, 2720U, 7357U, 2622U,
2744 7387U, 4380U, 5962U, 5948U, 4373U, 5955U, 6198U, 4517U,
2745 5277U, 5270U, 5284U, 5291U, 6974U, 5106U, 2125U, 5090U,
2746 2076U, 5098U, 2117U, 5082U, 2068U, 5144U, 5136U, 2764U,
2747 2756U, 6835U, 6825U, 6815U, 6805U, 6855U, 6845U, 8175U,
2748 8185U, 6865U, 6878U, 8195U, 8205U, 6891U, 6904U, 1769U,
2749 1517U, 4541U, 59U, 1663U, 7561U, 4605U, 2462U, 8025U,
2750 2822U, 5396U, 35U, 9U, 2713U, 18U, 0U, 5371U,
2751 5403U, 2586U, 7349U, 1589U, 2804U, 2813U, 5252U, 5261U,
2752 6938U, 6951U, 6216U, 4924U, 6334U, 2446U, 4852U, 4862U,
2753 2174U, 2189U, 4691U, 4744U, 4776U, 4814U, 7596U, 7622U,
2754 7608U, 2133U, 2161U, 2146U, 2683U, 2698U, 1850U, 2856U,
2755 4987U, 8083U, 5011U, 8107U, 6223U, 1985U, 1975U, 5412U,
2756 7043U, 2204U, 6045U, 6025U, 7071U, 7050U, 6079U, 6110U,
2757 6096U, 6377U, 8258U, 2488U, 8251U, 2470U, 6268U, 5319U,
2758 5244U, 2324U, 4386U, 6283U, 5059U, 6290U, 4880U, 6275U,
2759 5051U, 4872U, 26U, 2788U, 2780U, 2772U, 7284U, 5992U,
2760 7170U, 7215U, 7317U, 5430U, 2213U, 1646U, 2415U, 2285U,
2761 1797U, 1524U, 4569U, 7568U, 4612U, 65U, 7292U, 5380U,
2762 5542U, 5558U, 8215U, 2233U, 2427U, 7010U, 5152U, 5193U,
2763 5169U, 5181U, 1776U, 4548U, 1752U, 4524U, 8032U, 4936U,
2764 4723U, 4670U, 1828U, 4583U, 1893U, 6163U, 6125U, 8066U,
2765 4970U, 8090U, 4994U, 8161U, 8168U, 2273U, 9977U, 11390U,
2766 3842U, 3820U, 3865U, 11021U, 13678U, 1044U, 674U, 856U,
2767 598U, 189U, 829U, 569U, 449U, 1376U, 1163U, 1197U,
2768 1257U, 1137U, 775U, 1403U, 321U, 106U, 217U, 1018U,
2769 134U, 244U, 373U, 1229U, 269U, 398U, 78U, 926U,
2770 162U, 543U, 803U, 1429U, 294U, 346U, 1284U, 973U,
2771 900U, 1108U, 744U, 646U, 1330U, 423U, 7424U, 10542U,
2772 3891U, 3988U, 4264U, 5737U, 8656U, 9634U, 10562U, 9617U,
2773 7408U, 7461U, 7445U, 11785U, 12799U, 8492U, 12915U, 12934U,
2774 8265U, 8438U, 11708U, 13433U, 11296U, 9990U, 13480U, 11343U,
2775 12133U, 13058U, 13219U, 12623U, 12642U, 10101U, 13347U, 6559U,
2776 7799U, 3999U, 6713U, 7933U, 6726U, 7946U, 10483U, 10615U,
2777 9602U, 13725U, 11589U, 9854U, 9936U, 12778U, 3347U, 12661U,
2778 13236U, 10210U, 3286U, 2574U, 10032U, 4155U, 2830U, 11060U,
2779 12024U, 10306U, 11977U, 3728U, 4281U, 2973U, 2951U, 6682U,
2780 7514U, 3457U, 3422U, 4125U, 7545U, 2546U, 2560U, 12262U,
2781 3207U, 3382U, 5753U, 3134U, 5584U, 5611U, 3787U, 3170U,
2782 5682U, 10590U, 13712U, 8627U, 12714U, 13027U, 4233U, 13527U,
2783 10075U, 9786U, 13650U, 10088U, 9797U, 10134U, 8360U, 10434U,
2784 11498U, 13123U, 13534U, 13553U, 10321U, 10336U, 10984U, 13045U,
2785 9514U, 8342U, 5909U, 13357U, 13287U, 11486U, 6529U, 7769U,
2786 13254U, 6740U, 7960U, 9491U, 6622U, 7873U, 10114U, 7821U,
2787 10644U, 11168U, 10751U, 11230U, 10833U, 10898U, 6652U, 7903U,
2788 6475U, 7715U, 10656U, 11186U, 10774U, 11245U, 10853U, 10913U,
2789 1071U, 703U, 1001U, 526U, 954U, 1357U, 883U, 1088U,
2790 722U, 627U, 1312U, 5575U, 11540U, 11038U, 8737U, 12058U,
2791 3906U, 10533U, 10060U, 9773U, 12278U, 12835U, 12297U, 10242U,
2792 12493U, 12473U, 11027U, 13684U, 13695U, 5640U, 5827U, 5867U,
2793 13330U, 9871U, 9954U, 8480U, 13421U, 11284U, 5797U, 8527U,
2794 5812U, 5661U, 5847U, 5888U, 11000U, 10685U, 13657U, 13179U,
2795 13069U, 12680U, 1455U, 1486U, 8668U, 11719U, 12173U, 13303U,
2796 13367U, 12727U, 8458U, 13399U, 11262U, 11086U, 8505U, 11108U,
2797 13148U, 8696U, 11746U, 12201U, 11661U, 5710U, 13446U, 11309U,
2798 9712U, 11560U, 11634U, 12145U, 13493U, 11356U, 12386U, 12442U,
2799 13468U, 11331U, 13515U, 11378U, 12513U, 6792U, 8012U, 6551U,
2800 7791U, 10635U, 6644U, 7895U, 10886U, 6778U, 7998U, 6497U,
2801 7737U, 9576U, 11895U, 10492U, 11861U, 12592U, 12342U, 9475U,
2802 11843U, 12322U, 10357U, 8943U, 8408U, 9275U, 9019U, 9219U,
2803 7664U, 8963U, 9339U, 9083U, 9411U, 9155U, 11913U, 10505U,
2804 11875U, 8420U, 9304U, 9048U, 9244U, 8988U, 9372U, 9116U,
2805 9440U, 9184U, 12887U, 12113U, 10173U, 11446U, 11421U, 10162U,
2806 10426U, 11130U, 10604U, 12953U, 8373U, 11053U, 10962U, 12042U,
2807 13203U, 11693U, 9817U, 8451U, 8724U, 10670U, 13129U, 10930U,
2808 11773U, 3933U, 9675U, 4105U, 4186U, 13599U, 11823U, 12242U,
2809 10145U, 10451U, 9760U, 11994U, 10970U, 11956U, 8591U, 9753U,
2810 10374U, 9808U, 11687U, 13142U, 8569U, 12750U, 10556U, 3085U,
2811 3508U, 11404U, 4074U, 8323U, 10416U, 10875U, 10948U, 43U,
2812 5782U, 9843U, 475U, 12998U, 12361U, 12416U, 9824U, 9904U,
2813 4334U, 13013U, 11551U, 10260U, 2931U, 13265U, 6762U, 7982U,
2814 13101U, 12552U, 11138U, 10711U, 11206U, 10799U, 9498U, 8539U,
2815 10124U, 6674U, 7925U, 13108U, 12565U, 9549U, 7528U, 6696U,
2816 4355U, 8751U, 8847U, 8783U, 8879U, 8815U, 8911U, 8767U,
2817 8863U, 8799U, 8895U, 8831U, 8927U, 9658U, 12531U, 6581U,
2818 7832U, 6505U, 7745U, 6601U, 7852U, 12822U, 10399U, 9505U,
2819 8609U, 11468U, 12872U, 10186U, 3248U, 10012U, 11617U, 10287U,
2820 10004U, 6537U, 7777U, 6748U, 7968U, 6630U, 7881U, 6660U,
2821 7911U, 6483U, 7723U, 10474U, 3107U, 3952U, 3559U, 3756U,
2822 3531U, 3060U, 3702U, 3030U, 3671U, 2995U, 3635U, 3595U,
2823 4022U, 3485U, 4049U, 4207U, 10524U, 10048U, 7634U, 13638U,
2824 11075U, 5921U, 7689U, 12968U, 12986U, 12611U, 12078U, 11525U,
2825 9564U, 12862U, 13566U, 11937U, 10274U, 9893U, 9584U, 12099U,
2826 10230U, 8392U, 13619U, 9530U, 12010U, 12765U, 3320U, 12229U,
2827 8645U, 13276U, 6770U, 7990U, 13116U, 12579U, 11153U, 10731U,
2828 11218U, 10816U, 6573U, 7813U, 8554U, 10408U, 8579U, 9687U,
2829 9701U, 4307U, 8278U, 8301U, 9737U, 13579U, 11803U, 9924U,
2830 500U,
2831};
2832
2833static inline void InitSPIRVMCInstrInfo(MCInstrInfo *II) {
2834 II->InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 841, nullptr, 0);
2835}
2836
2837
2838} // namespace llvm
2839
2840#endif // GET_INSTRINFO_MC_DESC
2841
2842#ifdef GET_INSTRINFO_HEADER
2843#undef GET_INSTRINFO_HEADER
2844
2845namespace llvm {
2846
2847struct SPIRVGenInstrInfo : public TargetInstrInfo {
2848 explicit SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2849 ~SPIRVGenInstrInfo() override = default;
2850};
2851
2852} // namespace llvm
2853
2854namespace llvm::SPIRV {
2855
2856
2857} // namespace llvm::SPIRV
2858
2859#endif // GET_INSTRINFO_HEADER
2860
2861#ifdef GET_INSTRINFO_HELPER_DECLS
2862#undef GET_INSTRINFO_HELPER_DECLS
2863
2864
2865#endif // GET_INSTRINFO_HELPER_DECLS
2866
2867#ifdef GET_INSTRINFO_HELPERS
2868#undef GET_INSTRINFO_HELPERS
2869
2870
2871#endif // GET_INSTRINFO_HELPERS
2872
2873#ifdef GET_INSTRINFO_CTOR_DTOR
2874#undef GET_INSTRINFO_CTOR_DTOR
2875
2876namespace llvm {
2877
2878extern const SPIRVInstrTable SPIRVDescs;
2879extern const unsigned SPIRVInstrNameIndices[];
2880extern const char SPIRVInstrNameData[];
2881SPIRVGenInstrInfo::SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2882 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2883 InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 841);
2884}
2885
2886} // namespace llvm
2887
2888#endif // GET_INSTRINFO_CTOR_DTOR
2889
2890#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2891#undef GET_INSTRINFO_MC_HELPER_DECLS
2892
2893namespace llvm {
2894
2895class MCInst;
2896class FeatureBitset;
2897
2898namespace SPIRV_MC {
2899
2900void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2901
2902} // namespace SPIRV_MC
2903
2904} // namespace llvm
2905
2906#endif // GET_INSTRINFO_MC_HELPER_DECLS
2907
2908#ifdef GET_INSTRINFO_MC_HELPERS
2909#undef GET_INSTRINFO_MC_HELPERS
2910
2911namespace llvm::SPIRV_MC {
2912
2913
2914} // namespace llvm::SPIRV_MC
2915
2916#endif // GET_INSTRINFO_MC_HELPERS
2917
2918#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2919 defined(GET_AVAILABLE_OPCODE_CHECKER)
2920#define GET_COMPUTE_FEATURES
2921#endif
2922#ifdef GET_COMPUTE_FEATURES
2923#undef GET_COMPUTE_FEATURES
2924
2925namespace llvm::SPIRV_MC {
2926
2927// Bits for subtarget features that participate in instruction matching.
2928enum SubtargetFeatureBits : uint8_t {
2929};
2930
2931inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2932 FeatureBitset Features;
2933 return Features;
2934}
2935
2936inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2937 enum : uint8_t {
2938 CEFBS_None,
2939 };
2940
2941 static constexpr FeatureBitset FeatureBitsets[] = {
2942 {}, // CEFBS_None
2943 };
2944 static constexpr uint8_t RequiredFeaturesRefs[] = {
2945 CEFBS_None, // PHI
2946 CEFBS_None, // INLINEASM
2947 CEFBS_None, // INLINEASM_BR
2948 CEFBS_None, // CFI_INSTRUCTION
2949 CEFBS_None, // EH_LABEL
2950 CEFBS_None, // GC_LABEL
2951 CEFBS_None, // ANNOTATION_LABEL
2952 CEFBS_None, // KILL
2953 CEFBS_None, // EXTRACT_SUBREG
2954 CEFBS_None, // INSERT_SUBREG
2955 CEFBS_None, // IMPLICIT_DEF
2956 CEFBS_None, // INIT_UNDEF
2957 CEFBS_None, // SUBREG_TO_REG
2958 CEFBS_None, // COPY_TO_REGCLASS
2959 CEFBS_None, // DBG_VALUE
2960 CEFBS_None, // DBG_VALUE_LIST
2961 CEFBS_None, // DBG_INSTR_REF
2962 CEFBS_None, // DBG_PHI
2963 CEFBS_None, // DBG_LABEL
2964 CEFBS_None, // REG_SEQUENCE
2965 CEFBS_None, // COPY
2966 CEFBS_None, // COPY_LANEMASK
2967 CEFBS_None, // BUNDLE
2968 CEFBS_None, // LIFETIME_START
2969 CEFBS_None, // LIFETIME_END
2970 CEFBS_None, // PSEUDO_PROBE
2971 CEFBS_None, // ARITH_FENCE
2972 CEFBS_None, // STACKMAP
2973 CEFBS_None, // FENTRY_CALL
2974 CEFBS_None, // PATCHPOINT
2975 CEFBS_None, // LOAD_STACK_GUARD
2976 CEFBS_None, // PREALLOCATED_SETUP
2977 CEFBS_None, // PREALLOCATED_ARG
2978 CEFBS_None, // STATEPOINT
2979 CEFBS_None, // LOCAL_ESCAPE
2980 CEFBS_None, // FAULTING_OP
2981 CEFBS_None, // PATCHABLE_OP
2982 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2983 CEFBS_None, // PATCHABLE_RET
2984 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2985 CEFBS_None, // PATCHABLE_TAIL_CALL
2986 CEFBS_None, // PATCHABLE_EVENT_CALL
2987 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2988 CEFBS_None, // ICALL_BRANCH_FUNNEL
2989 CEFBS_None, // FAKE_USE
2990 CEFBS_None, // MEMBARRIER
2991 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2992 CEFBS_None, // RELOC_NONE
2993 CEFBS_None, // CONVERGENCECTRL_ENTRY
2994 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2995 CEFBS_None, // CONVERGENCECTRL_LOOP
2996 CEFBS_None, // CONVERGENCECTRL_GLUE
2997 CEFBS_None, // G_ASSERT_SEXT
2998 CEFBS_None, // G_ASSERT_ZEXT
2999 CEFBS_None, // G_ASSERT_ALIGN
3000 CEFBS_None, // G_ADD
3001 CEFBS_None, // G_SUB
3002 CEFBS_None, // G_MUL
3003 CEFBS_None, // G_SDIV
3004 CEFBS_None, // G_UDIV
3005 CEFBS_None, // G_SREM
3006 CEFBS_None, // G_UREM
3007 CEFBS_None, // G_SDIVREM
3008 CEFBS_None, // G_UDIVREM
3009 CEFBS_None, // G_AND
3010 CEFBS_None, // G_OR
3011 CEFBS_None, // G_XOR
3012 CEFBS_None, // G_ABDS
3013 CEFBS_None, // G_ABDU
3014 CEFBS_None, // G_UAVGFLOOR
3015 CEFBS_None, // G_UAVGCEIL
3016 CEFBS_None, // G_SAVGFLOOR
3017 CEFBS_None, // G_SAVGCEIL
3018 CEFBS_None, // G_IMPLICIT_DEF
3019 CEFBS_None, // G_PHI
3020 CEFBS_None, // G_FRAME_INDEX
3021 CEFBS_None, // G_GLOBAL_VALUE
3022 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3023 CEFBS_None, // G_CONSTANT_POOL
3024 CEFBS_None, // G_EXTRACT
3025 CEFBS_None, // G_UNMERGE_VALUES
3026 CEFBS_None, // G_INSERT
3027 CEFBS_None, // G_MERGE_VALUES
3028 CEFBS_None, // G_BUILD_VECTOR
3029 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3030 CEFBS_None, // G_CONCAT_VECTORS
3031 CEFBS_None, // G_PTRTOINT
3032 CEFBS_None, // G_INTTOPTR
3033 CEFBS_None, // G_BITCAST
3034 CEFBS_None, // G_FREEZE
3035 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3036 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3037 CEFBS_None, // G_INTRINSIC_TRUNC
3038 CEFBS_None, // G_INTRINSIC_ROUND
3039 CEFBS_None, // G_INTRINSIC_LRINT
3040 CEFBS_None, // G_INTRINSIC_LLRINT
3041 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3042 CEFBS_None, // G_READCYCLECOUNTER
3043 CEFBS_None, // G_READSTEADYCOUNTER
3044 CEFBS_None, // G_LOAD
3045 CEFBS_None, // G_SEXTLOAD
3046 CEFBS_None, // G_ZEXTLOAD
3047 CEFBS_None, // G_INDEXED_LOAD
3048 CEFBS_None, // G_INDEXED_SEXTLOAD
3049 CEFBS_None, // G_INDEXED_ZEXTLOAD
3050 CEFBS_None, // G_STORE
3051 CEFBS_None, // G_INDEXED_STORE
3052 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3053 CEFBS_None, // G_ATOMIC_CMPXCHG
3054 CEFBS_None, // G_ATOMICRMW_XCHG
3055 CEFBS_None, // G_ATOMICRMW_ADD
3056 CEFBS_None, // G_ATOMICRMW_SUB
3057 CEFBS_None, // G_ATOMICRMW_AND
3058 CEFBS_None, // G_ATOMICRMW_NAND
3059 CEFBS_None, // G_ATOMICRMW_OR
3060 CEFBS_None, // G_ATOMICRMW_XOR
3061 CEFBS_None, // G_ATOMICRMW_MAX
3062 CEFBS_None, // G_ATOMICRMW_MIN
3063 CEFBS_None, // G_ATOMICRMW_UMAX
3064 CEFBS_None, // G_ATOMICRMW_UMIN
3065 CEFBS_None, // G_ATOMICRMW_FADD
3066 CEFBS_None, // G_ATOMICRMW_FSUB
3067 CEFBS_None, // G_ATOMICRMW_FMAX
3068 CEFBS_None, // G_ATOMICRMW_FMIN
3069 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3070 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3071 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
3072 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
3073 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3074 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3075 CEFBS_None, // G_ATOMICRMW_USUB_COND
3076 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3077 CEFBS_None, // G_FENCE
3078 CEFBS_None, // G_PREFETCH
3079 CEFBS_None, // G_BRCOND
3080 CEFBS_None, // G_BRINDIRECT
3081 CEFBS_None, // G_INVOKE_REGION_START
3082 CEFBS_None, // G_INTRINSIC
3083 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3084 CEFBS_None, // G_INTRINSIC_CONVERGENT
3085 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3086 CEFBS_None, // G_ANYEXT
3087 CEFBS_None, // G_TRUNC
3088 CEFBS_None, // G_TRUNC_SSAT_S
3089 CEFBS_None, // G_TRUNC_SSAT_U
3090 CEFBS_None, // G_TRUNC_USAT_U
3091 CEFBS_None, // G_CONSTANT
3092 CEFBS_None, // G_FCONSTANT
3093 CEFBS_None, // G_VASTART
3094 CEFBS_None, // G_VAARG
3095 CEFBS_None, // G_SEXT
3096 CEFBS_None, // G_SEXT_INREG
3097 CEFBS_None, // G_ZEXT
3098 CEFBS_None, // G_SHL
3099 CEFBS_None, // G_LSHR
3100 CEFBS_None, // G_ASHR
3101 CEFBS_None, // G_FSHL
3102 CEFBS_None, // G_FSHR
3103 CEFBS_None, // G_ROTR
3104 CEFBS_None, // G_ROTL
3105 CEFBS_None, // G_ICMP
3106 CEFBS_None, // G_FCMP
3107 CEFBS_None, // G_SCMP
3108 CEFBS_None, // G_UCMP
3109 CEFBS_None, // G_SELECT
3110 CEFBS_None, // G_UADDO
3111 CEFBS_None, // G_UADDE
3112 CEFBS_None, // G_USUBO
3113 CEFBS_None, // G_USUBE
3114 CEFBS_None, // G_SADDO
3115 CEFBS_None, // G_SADDE
3116 CEFBS_None, // G_SSUBO
3117 CEFBS_None, // G_SSUBE
3118 CEFBS_None, // G_UMULO
3119 CEFBS_None, // G_SMULO
3120 CEFBS_None, // G_UMULH
3121 CEFBS_None, // G_SMULH
3122 CEFBS_None, // G_UADDSAT
3123 CEFBS_None, // G_SADDSAT
3124 CEFBS_None, // G_USUBSAT
3125 CEFBS_None, // G_SSUBSAT
3126 CEFBS_None, // G_USHLSAT
3127 CEFBS_None, // G_SSHLSAT
3128 CEFBS_None, // G_SMULFIX
3129 CEFBS_None, // G_UMULFIX
3130 CEFBS_None, // G_SMULFIXSAT
3131 CEFBS_None, // G_UMULFIXSAT
3132 CEFBS_None, // G_SDIVFIX
3133 CEFBS_None, // G_UDIVFIX
3134 CEFBS_None, // G_SDIVFIXSAT
3135 CEFBS_None, // G_UDIVFIXSAT
3136 CEFBS_None, // G_FADD
3137 CEFBS_None, // G_FSUB
3138 CEFBS_None, // G_FMUL
3139 CEFBS_None, // G_FMA
3140 CEFBS_None, // G_FMAD
3141 CEFBS_None, // G_FDIV
3142 CEFBS_None, // G_FREM
3143 CEFBS_None, // G_FMODF
3144 CEFBS_None, // G_FPOW
3145 CEFBS_None, // G_FPOWI
3146 CEFBS_None, // G_FEXP
3147 CEFBS_None, // G_FEXP2
3148 CEFBS_None, // G_FEXP10
3149 CEFBS_None, // G_FLOG
3150 CEFBS_None, // G_FLOG2
3151 CEFBS_None, // G_FLOG10
3152 CEFBS_None, // G_FLDEXP
3153 CEFBS_None, // G_FFREXP
3154 CEFBS_None, // G_FNEG
3155 CEFBS_None, // G_FPEXT
3156 CEFBS_None, // G_FPTRUNC
3157 CEFBS_None, // G_FPTOSI
3158 CEFBS_None, // G_FPTOUI
3159 CEFBS_None, // G_SITOFP
3160 CEFBS_None, // G_UITOFP
3161 CEFBS_None, // G_FPTOSI_SAT
3162 CEFBS_None, // G_FPTOUI_SAT
3163 CEFBS_None, // G_FABS
3164 CEFBS_None, // G_FCOPYSIGN
3165 CEFBS_None, // G_IS_FPCLASS
3166 CEFBS_None, // G_FCANONICALIZE
3167 CEFBS_None, // G_FMINNUM
3168 CEFBS_None, // G_FMAXNUM
3169 CEFBS_None, // G_FMINNUM_IEEE
3170 CEFBS_None, // G_FMAXNUM_IEEE
3171 CEFBS_None, // G_FMINIMUM
3172 CEFBS_None, // G_FMAXIMUM
3173 CEFBS_None, // G_FMINIMUMNUM
3174 CEFBS_None, // G_FMAXIMUMNUM
3175 CEFBS_None, // G_GET_FPENV
3176 CEFBS_None, // G_SET_FPENV
3177 CEFBS_None, // G_RESET_FPENV
3178 CEFBS_None, // G_GET_FPMODE
3179 CEFBS_None, // G_SET_FPMODE
3180 CEFBS_None, // G_RESET_FPMODE
3181 CEFBS_None, // G_GET_ROUNDING
3182 CEFBS_None, // G_SET_ROUNDING
3183 CEFBS_None, // G_PTR_ADD
3184 CEFBS_None, // G_PTRMASK
3185 CEFBS_None, // G_SMIN
3186 CEFBS_None, // G_SMAX
3187 CEFBS_None, // G_UMIN
3188 CEFBS_None, // G_UMAX
3189 CEFBS_None, // G_ABS
3190 CEFBS_None, // G_LROUND
3191 CEFBS_None, // G_LLROUND
3192 CEFBS_None, // G_BR
3193 CEFBS_None, // G_BRJT
3194 CEFBS_None, // G_VSCALE
3195 CEFBS_None, // G_INSERT_SUBVECTOR
3196 CEFBS_None, // G_EXTRACT_SUBVECTOR
3197 CEFBS_None, // G_INSERT_VECTOR_ELT
3198 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3199 CEFBS_None, // G_SHUFFLE_VECTOR
3200 CEFBS_None, // G_SPLAT_VECTOR
3201 CEFBS_None, // G_STEP_VECTOR
3202 CEFBS_None, // G_VECTOR_COMPRESS
3203 CEFBS_None, // G_CTTZ
3204 CEFBS_None, // G_CTTZ_ZERO_UNDEF
3205 CEFBS_None, // G_CTLZ
3206 CEFBS_None, // G_CTLZ_ZERO_UNDEF
3207 CEFBS_None, // G_CTLS
3208 CEFBS_None, // G_CTPOP
3209 CEFBS_None, // G_BSWAP
3210 CEFBS_None, // G_BITREVERSE
3211 CEFBS_None, // G_FCEIL
3212 CEFBS_None, // G_FCOS
3213 CEFBS_None, // G_FSIN
3214 CEFBS_None, // G_FSINCOS
3215 CEFBS_None, // G_FTAN
3216 CEFBS_None, // G_FACOS
3217 CEFBS_None, // G_FASIN
3218 CEFBS_None, // G_FATAN
3219 CEFBS_None, // G_FATAN2
3220 CEFBS_None, // G_FCOSH
3221 CEFBS_None, // G_FSINH
3222 CEFBS_None, // G_FTANH
3223 CEFBS_None, // G_FSQRT
3224 CEFBS_None, // G_FFLOOR
3225 CEFBS_None, // G_FRINT
3226 CEFBS_None, // G_FNEARBYINT
3227 CEFBS_None, // G_ADDRSPACE_CAST
3228 CEFBS_None, // G_BLOCK_ADDR
3229 CEFBS_None, // G_JUMP_TABLE
3230 CEFBS_None, // G_DYN_STACKALLOC
3231 CEFBS_None, // G_STACKSAVE
3232 CEFBS_None, // G_STACKRESTORE
3233 CEFBS_None, // G_STRICT_FADD
3234 CEFBS_None, // G_STRICT_FSUB
3235 CEFBS_None, // G_STRICT_FMUL
3236 CEFBS_None, // G_STRICT_FDIV
3237 CEFBS_None, // G_STRICT_FREM
3238 CEFBS_None, // G_STRICT_FMA
3239 CEFBS_None, // G_STRICT_FSQRT
3240 CEFBS_None, // G_STRICT_FLDEXP
3241 CEFBS_None, // G_READ_REGISTER
3242 CEFBS_None, // G_WRITE_REGISTER
3243 CEFBS_None, // G_MEMCPY
3244 CEFBS_None, // G_MEMCPY_INLINE
3245 CEFBS_None, // G_MEMMOVE
3246 CEFBS_None, // G_MEMSET
3247 CEFBS_None, // G_BZERO
3248 CEFBS_None, // G_TRAP
3249 CEFBS_None, // G_DEBUGTRAP
3250 CEFBS_None, // G_UBSANTRAP
3251 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3252 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3253 CEFBS_None, // G_VECREDUCE_FADD
3254 CEFBS_None, // G_VECREDUCE_FMUL
3255 CEFBS_None, // G_VECREDUCE_FMAX
3256 CEFBS_None, // G_VECREDUCE_FMIN
3257 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3258 CEFBS_None, // G_VECREDUCE_FMINIMUM
3259 CEFBS_None, // G_VECREDUCE_ADD
3260 CEFBS_None, // G_VECREDUCE_MUL
3261 CEFBS_None, // G_VECREDUCE_AND
3262 CEFBS_None, // G_VECREDUCE_OR
3263 CEFBS_None, // G_VECREDUCE_XOR
3264 CEFBS_None, // G_VECREDUCE_SMAX
3265 CEFBS_None, // G_VECREDUCE_SMIN
3266 CEFBS_None, // G_VECREDUCE_UMAX
3267 CEFBS_None, // G_VECREDUCE_UMIN
3268 CEFBS_None, // G_SBFX
3269 CEFBS_None, // G_UBFX
3270 CEFBS_None, // ASSIGN_TYPE
3271 CEFBS_None, // UNKNOWN_type
3272 CEFBS_None, // OpAccessChain
3273 CEFBS_None, // OpAliasDomainDeclINTEL
3274 CEFBS_None, // OpAliasScopeDeclINTEL
3275 CEFBS_None, // OpAliasScopeListDeclINTEL
3276 CEFBS_None, // OpAll
3277 CEFBS_None, // OpAny
3278 CEFBS_None, // OpArbitraryFloatACosALTERA
3279 CEFBS_None, // OpArbitraryFloatACosPiALTERA
3280 CEFBS_None, // OpArbitraryFloatASinALTERA
3281 CEFBS_None, // OpArbitraryFloatASinPiALTERA
3282 CEFBS_None, // OpArbitraryFloatATan2ALTERA
3283 CEFBS_None, // OpArbitraryFloatATanALTERA
3284 CEFBS_None, // OpArbitraryFloatATanPiALTERA
3285 CEFBS_None, // OpArbitraryFloatAddALTERA
3286 CEFBS_None, // OpArbitraryFloatCastALTERA
3287 CEFBS_None, // OpArbitraryFloatCastFromIntALTERA
3288 CEFBS_None, // OpArbitraryFloatCastToIntALTERA
3289 CEFBS_None, // OpArbitraryFloatCbrtALTERA
3290 CEFBS_None, // OpArbitraryFloatCosALTERA
3291 CEFBS_None, // OpArbitraryFloatCosPiALTERA
3292 CEFBS_None, // OpArbitraryFloatDivALTERA
3293 CEFBS_None, // OpArbitraryFloatEQALTERA
3294 CEFBS_None, // OpArbitraryFloatExp10ALTERA
3295 CEFBS_None, // OpArbitraryFloatExp2ALTERA
3296 CEFBS_None, // OpArbitraryFloatExpALTERA
3297 CEFBS_None, // OpArbitraryFloatExpm1ALTERA
3298 CEFBS_None, // OpArbitraryFloatGEALTERA
3299 CEFBS_None, // OpArbitraryFloatGTALTERA
3300 CEFBS_None, // OpArbitraryFloatHypotALTERA
3301 CEFBS_None, // OpArbitraryFloatLEALTERA
3302 CEFBS_None, // OpArbitraryFloatLTALTERA
3303 CEFBS_None, // OpArbitraryFloatLog10ALTERA
3304 CEFBS_None, // OpArbitraryFloatLog1pALTERA
3305 CEFBS_None, // OpArbitraryFloatLog2ALTERA
3306 CEFBS_None, // OpArbitraryFloatLogALTERA
3307 CEFBS_None, // OpArbitraryFloatMulALTERA
3308 CEFBS_None, // OpArbitraryFloatPowALTERA
3309 CEFBS_None, // OpArbitraryFloatPowNALTERA
3310 CEFBS_None, // OpArbitraryFloatPowRALTERA
3311 CEFBS_None, // OpArbitraryFloatRSqrtALTERA
3312 CEFBS_None, // OpArbitraryFloatRecipALTERA
3313 CEFBS_None, // OpArbitraryFloatSinALTERA
3314 CEFBS_None, // OpArbitraryFloatSinCosALTERA
3315 CEFBS_None, // OpArbitraryFloatSinCosPiALTERA
3316 CEFBS_None, // OpArbitraryFloatSinPiALTERA
3317 CEFBS_None, // OpArbitraryFloatSqrtALTERA
3318 CEFBS_None, // OpArbitraryFloatSubALTERA
3319 CEFBS_None, // OpArithmeticFenceEXT
3320 CEFBS_None, // OpArrayLength
3321 CEFBS_None, // OpAsmCallINTEL
3322 CEFBS_None, // OpAsmINTEL
3323 CEFBS_None, // OpAsmTargetINTEL
3324 CEFBS_None, // OpAssumeTrueKHR
3325 CEFBS_None, // OpAtomicAnd
3326 CEFBS_None, // OpAtomicCompareExchange
3327 CEFBS_None, // OpAtomicCompareExchangeWeak
3328 CEFBS_None, // OpAtomicExchange
3329 CEFBS_None, // OpAtomicFAddEXT
3330 CEFBS_None, // OpAtomicFMaxEXT
3331 CEFBS_None, // OpAtomicFMinEXT
3332 CEFBS_None, // OpAtomicFlagClear
3333 CEFBS_None, // OpAtomicFlagTestAndSet
3334 CEFBS_None, // OpAtomicIAdd
3335 CEFBS_None, // OpAtomicIDecrement
3336 CEFBS_None, // OpAtomicIIncrement
3337 CEFBS_None, // OpAtomicISub
3338 CEFBS_None, // OpAtomicLoad
3339 CEFBS_None, // OpAtomicOr
3340 CEFBS_None, // OpAtomicSMax
3341 CEFBS_None, // OpAtomicSMin
3342 CEFBS_None, // OpAtomicStore
3343 CEFBS_None, // OpAtomicUMax
3344 CEFBS_None, // OpAtomicUMin
3345 CEFBS_None, // OpAtomicXor
3346 CEFBS_None, // OpBitCount
3347 CEFBS_None, // OpBitFieldInsert
3348 CEFBS_None, // OpBitFieldSExtract
3349 CEFBS_None, // OpBitFieldUExtract
3350 CEFBS_None, // OpBitReverse
3351 CEFBS_None, // OpBitcast
3352 CEFBS_None, // OpBitwiseAndS
3353 CEFBS_None, // OpBitwiseAndV
3354 CEFBS_None, // OpBitwiseFunctionINTEL
3355 CEFBS_None, // OpBitwiseOrS
3356 CEFBS_None, // OpBitwiseOrV
3357 CEFBS_None, // OpBitwiseXorS
3358 CEFBS_None, // OpBitwiseXorV
3359 CEFBS_None, // OpBranch
3360 CEFBS_None, // OpBranchConditional
3361 CEFBS_None, // OpBuildNDRange
3362 CEFBS_None, // OpCapability
3363 CEFBS_None, // OpCaptureEventProfilingInfo
3364 CEFBS_None, // OpCommitReadPipe
3365 CEFBS_None, // OpCommitWritePipe
3366 CEFBS_None, // OpCompositeConstruct
3367 CEFBS_None, // OpCompositeConstructContinuedINTEL
3368 CEFBS_None, // OpCompositeExtract
3369 CEFBS_None, // OpCompositeInsert
3370 CEFBS_None, // OpConstantComposite
3371 CEFBS_None, // OpConstantCompositeContinuedINTEL
3372 CEFBS_None, // OpConstantF
3373 CEFBS_None, // OpConstantFalse
3374 CEFBS_None, // OpConstantFunctionPointerINTEL
3375 CEFBS_None, // OpConstantI
3376 CEFBS_None, // OpConstantNull
3377 CEFBS_None, // OpConstantSampler
3378 CEFBS_None, // OpConstantTrue
3379 CEFBS_None, // OpControlBarrier
3380 CEFBS_None, // OpControlBarrierArriveINTEL
3381 CEFBS_None, // OpControlBarrierWaitINTEL
3382 CEFBS_None, // OpConvertBF16ToFINTEL
3383 CEFBS_None, // OpConvertFToBF16INTEL
3384 CEFBS_None, // OpConvertFToS
3385 CEFBS_None, // OpConvertFToU
3386 CEFBS_None, // OpConvertHandleToImageINTEL
3387 CEFBS_None, // OpConvertHandleToSampledImageINTEL
3388 CEFBS_None, // OpConvertHandleToSamplerINTEL
3389 CEFBS_None, // OpConvertPtrToU
3390 CEFBS_None, // OpConvertSToF
3391 CEFBS_None, // OpConvertUToF
3392 CEFBS_None, // OpConvertUToPtr
3393 CEFBS_None, // OpCooperativeMatrixConstructCheckedINTEL
3394 CEFBS_None, // OpCooperativeMatrixGetElementCoordINTEL
3395 CEFBS_None, // OpCooperativeMatrixLengthKHR
3396 CEFBS_None, // OpCooperativeMatrixLoadCheckedINTEL
3397 CEFBS_None, // OpCooperativeMatrixLoadKHR
3398 CEFBS_None, // OpCooperativeMatrixMulAddKHR
3399 CEFBS_None, // OpCooperativeMatrixPrefetchINTEL
3400 CEFBS_None, // OpCooperativeMatrixStoreCheckedINTEL
3401 CEFBS_None, // OpCooperativeMatrixStoreKHR
3402 CEFBS_None, // OpCopyLogical
3403 CEFBS_None, // OpCopyMemory
3404 CEFBS_None, // OpCopyMemorySized
3405 CEFBS_None, // OpCopyObject
3406 CEFBS_None, // OpCreateUserEvent
3407 CEFBS_None, // OpCrossWorkgroupCastToPtrINTEL
3408 CEFBS_None, // OpDPdx
3409 CEFBS_None, // OpDPdxCoarse
3410 CEFBS_None, // OpDPdxFine
3411 CEFBS_None, // OpDPdy
3412 CEFBS_None, // OpDPdyCoarse
3413 CEFBS_None, // OpDPdyFine
3414 CEFBS_None, // OpDecorate
3415 CEFBS_None, // OpDecorateId
3416 CEFBS_None, // OpDecorateString
3417 CEFBS_None, // OpDemoteToHelperInvocation
3418 CEFBS_None, // OpDot
3419 CEFBS_None, // OpEmitStreamVertex
3420 CEFBS_None, // OpEmitVertex
3421 CEFBS_None, // OpEndPrimitive
3422 CEFBS_None, // OpEndStreamPrimitive
3423 CEFBS_None, // OpEnqueueKernel
3424 CEFBS_None, // OpEntryPoint
3425 CEFBS_None, // OpExecutionMode
3426 CEFBS_None, // OpExecutionModeId
3427 CEFBS_None, // OpExpectKHR
3428 CEFBS_None, // OpExtInst
3429 CEFBS_None, // OpExtInstImport
3430 CEFBS_None, // OpExtension
3431 CEFBS_None, // OpFAddS
3432 CEFBS_None, // OpFAddV
3433 CEFBS_None, // OpFConvert
3434 CEFBS_None, // OpFDivS
3435 CEFBS_None, // OpFDivV
3436 CEFBS_None, // OpFMod
3437 CEFBS_None, // OpFMulS
3438 CEFBS_None, // OpFMulV
3439 CEFBS_None, // OpFNegate
3440 CEFBS_None, // OpFNegateV
3441 CEFBS_None, // OpFOrdEqual
3442 CEFBS_None, // OpFOrdGreaterThan
3443 CEFBS_None, // OpFOrdGreaterThanEqual
3444 CEFBS_None, // OpFOrdLessThan
3445 CEFBS_None, // OpFOrdLessThanEqual
3446 CEFBS_None, // OpFOrdNotEqual
3447 CEFBS_None, // OpFRemS
3448 CEFBS_None, // OpFRemV
3449 CEFBS_None, // OpFSubS
3450 CEFBS_None, // OpFSubV
3451 CEFBS_None, // OpFUnordEqual
3452 CEFBS_None, // OpFUnordGreaterThan
3453 CEFBS_None, // OpFUnordGreaterThanEqual
3454 CEFBS_None, // OpFUnordLessThan
3455 CEFBS_None, // OpFUnordLessThanEqual
3456 CEFBS_None, // OpFUnordNotEqual
3457 CEFBS_None, // OpFixedCosALTERA
3458 CEFBS_None, // OpFixedCosPiALTERA
3459 CEFBS_None, // OpFixedExpALTERA
3460 CEFBS_None, // OpFixedLogALTERA
3461 CEFBS_None, // OpFixedRecipALTERA
3462 CEFBS_None, // OpFixedRsqrtALTERA
3463 CEFBS_None, // OpFixedSinALTERA
3464 CEFBS_None, // OpFixedSinCosALTERA
3465 CEFBS_None, // OpFixedSinCosPiALTERA
3466 CEFBS_None, // OpFixedSinPiALTERA
3467 CEFBS_None, // OpFixedSqrtALTERA
3468 CEFBS_None, // OpFmaKHR
3469 CEFBS_None, // OpFunction
3470 CEFBS_None, // OpFunctionCall
3471 CEFBS_None, // OpFunctionEnd
3472 CEFBS_None, // OpFunctionParameter
3473 CEFBS_None, // OpFunctionPointerCallINTEL
3474 CEFBS_None, // OpFwidth
3475 CEFBS_None, // OpFwidthCoarse
3476 CEFBS_None, // OpFwidthFine
3477 CEFBS_None, // OpGenericCastToPtr
3478 CEFBS_None, // OpGenericCastToPtrExplicit
3479 CEFBS_None, // OpGenericPtrMemSemantics
3480 CEFBS_None, // OpGetDefaultQueue
3481 CEFBS_None, // OpGetMaxPipePackets
3482 CEFBS_None, // OpGetNumPipePackets
3483 CEFBS_None, // OpGroupAll
3484 CEFBS_None, // OpGroupAny
3485 CEFBS_None, // OpGroupAsyncCopy
3486 CEFBS_None, // OpGroupBitwiseAndKHR
3487 CEFBS_None, // OpGroupBitwiseOrKHR
3488 CEFBS_None, // OpGroupBitwiseXorKHR
3489 CEFBS_None, // OpGroupBroadcast
3490 CEFBS_None, // OpGroupCommitReadPipe
3491 CEFBS_None, // OpGroupCommitWritePipe
3492 CEFBS_None, // OpGroupFAdd
3493 CEFBS_None, // OpGroupFMax
3494 CEFBS_None, // OpGroupFMin
3495 CEFBS_None, // OpGroupFMulKHR
3496 CEFBS_None, // OpGroupIAdd
3497 CEFBS_None, // OpGroupIMulKHR
3498 CEFBS_None, // OpGroupLogicalAndKHR
3499 CEFBS_None, // OpGroupLogicalOrKHR
3500 CEFBS_None, // OpGroupLogicalXorKHR
3501 CEFBS_None, // OpGroupNonUniformAll
3502 CEFBS_None, // OpGroupNonUniformAllEqual
3503 CEFBS_None, // OpGroupNonUniformAny
3504 CEFBS_None, // OpGroupNonUniformBallot
3505 CEFBS_None, // OpGroupNonUniformBallotBitCount
3506 CEFBS_None, // OpGroupNonUniformBallotBitExtract
3507 CEFBS_None, // OpGroupNonUniformBallotFindLSB
3508 CEFBS_None, // OpGroupNonUniformBallotFindMSB
3509 CEFBS_None, // OpGroupNonUniformBitwiseAnd
3510 CEFBS_None, // OpGroupNonUniformBitwiseOr
3511 CEFBS_None, // OpGroupNonUniformBitwiseXor
3512 CEFBS_None, // OpGroupNonUniformBroadcast
3513 CEFBS_None, // OpGroupNonUniformBroadcastFirst
3514 CEFBS_None, // OpGroupNonUniformElect
3515 CEFBS_None, // OpGroupNonUniformFAdd
3516 CEFBS_None, // OpGroupNonUniformFMax
3517 CEFBS_None, // OpGroupNonUniformFMin
3518 CEFBS_None, // OpGroupNonUniformFMul
3519 CEFBS_None, // OpGroupNonUniformIAdd
3520 CEFBS_None, // OpGroupNonUniformIMul
3521 CEFBS_None, // OpGroupNonUniformInverseBallot
3522 CEFBS_None, // OpGroupNonUniformLogicalAnd
3523 CEFBS_None, // OpGroupNonUniformLogicalOr
3524 CEFBS_None, // OpGroupNonUniformLogicalXor
3525 CEFBS_None, // OpGroupNonUniformQuadSwap
3526 CEFBS_None, // OpGroupNonUniformRotateKHR
3527 CEFBS_None, // OpGroupNonUniformSMax
3528 CEFBS_None, // OpGroupNonUniformSMin
3529 CEFBS_None, // OpGroupNonUniformShuffle
3530 CEFBS_None, // OpGroupNonUniformShuffleDown
3531 CEFBS_None, // OpGroupNonUniformShuffleUp
3532 CEFBS_None, // OpGroupNonUniformShuffleXor
3533 CEFBS_None, // OpGroupNonUniformUMax
3534 CEFBS_None, // OpGroupNonUniformUMin
3535 CEFBS_None, // OpGroupReserveReadPipePackets
3536 CEFBS_None, // OpGroupReserveWritePipePackets
3537 CEFBS_None, // OpGroupSMax
3538 CEFBS_None, // OpGroupSMin
3539 CEFBS_None, // OpGroupUMax
3540 CEFBS_None, // OpGroupUMin
3541 CEFBS_None, // OpGroupWaitEvents
3542 CEFBS_None, // OpIAddCarryS
3543 CEFBS_None, // OpIAddCarryV
3544 CEFBS_None, // OpIAddS
3545 CEFBS_None, // OpIAddV
3546 CEFBS_None, // OpIEqual
3547 CEFBS_None, // OpIMulS
3548 CEFBS_None, // OpIMulV
3549 CEFBS_None, // OpINotEqual
3550 CEFBS_None, // OpISubBorrowS
3551 CEFBS_None, // OpISubBorrowV
3552 CEFBS_None, // OpISubS
3553 CEFBS_None, // OpISubV
3554 CEFBS_None, // OpImage
3555 CEFBS_None, // OpImageDrefGather
3556 CEFBS_None, // OpImageFetch
3557 CEFBS_None, // OpImageGather
3558 CEFBS_None, // OpImageQueryFormat
3559 CEFBS_None, // OpImageQueryLevels
3560 CEFBS_None, // OpImageQueryLod
3561 CEFBS_None, // OpImageQueryOrder
3562 CEFBS_None, // OpImageQuerySamples
3563 CEFBS_None, // OpImageQuerySize
3564 CEFBS_None, // OpImageQuerySizeLod
3565 CEFBS_None, // OpImageRead
3566 CEFBS_None, // OpImageSampleDrefExplicitLod
3567 CEFBS_None, // OpImageSampleDrefImplicitLod
3568 CEFBS_None, // OpImageSampleExplicitLod
3569 CEFBS_None, // OpImageSampleFootprintNV
3570 CEFBS_None, // OpImageSampleImplicitLod
3571 CEFBS_None, // OpImageSampleProjDrefExplicitLod
3572 CEFBS_None, // OpImageSampleProjDrefImplicitLod
3573 CEFBS_None, // OpImageSampleProjExplicitLod
3574 CEFBS_None, // OpImageSampleProjImplicitLod
3575 CEFBS_None, // OpImageSparseDrefGather
3576 CEFBS_None, // OpImageSparseFetch
3577 CEFBS_None, // OpImageSparseGather
3578 CEFBS_None, // OpImageSparseRead
3579 CEFBS_None, // OpImageSparseSampleDrefExplicitLod
3580 CEFBS_None, // OpImageSparseSampleDrefImplicitLod
3581 CEFBS_None, // OpImageSparseSampleExplicitLod
3582 CEFBS_None, // OpImageSparseSampleImplicitLod
3583 CEFBS_None, // OpImageSparseSampleProjDrefExplicitLod
3584 CEFBS_None, // OpImageSparseSampleProjDrefImplicitLod
3585 CEFBS_None, // OpImageSparseSampleProjExplicitLod
3586 CEFBS_None, // OpImageSparseSampleProjImplicitLod
3587 CEFBS_None, // OpImageSparseTexelsResident
3588 CEFBS_None, // OpImageTexelPointer
3589 CEFBS_None, // OpImageWrite
3590 CEFBS_None, // OpInBoundsAccessChain
3591 CEFBS_None, // OpInBoundsPtrAccessChain
3592 CEFBS_None, // OpIsFinite
3593 CEFBS_None, // OpIsInf
3594 CEFBS_None, // OpIsNan
3595 CEFBS_None, // OpIsNormal
3596 CEFBS_None, // OpIsValidEvent
3597 CEFBS_None, // OpIsValidReserveId
3598 CEFBS_None, // OpKill
3599 CEFBS_None, // OpLabel
3600 CEFBS_None, // OpLessOrGreater
3601 CEFBS_None, // OpLifetimeStart
3602 CEFBS_None, // OpLifetimeStop
3603 CEFBS_None, // OpLine
3604 CEFBS_None, // OpLoad
3605 CEFBS_None, // OpLogicalAnd
3606 CEFBS_None, // OpLogicalEqual
3607 CEFBS_None, // OpLogicalNot
3608 CEFBS_None, // OpLogicalNotEqual
3609 CEFBS_None, // OpLogicalOr
3610 CEFBS_None, // OpLoopControlINTEL
3611 CEFBS_None, // OpLoopMerge
3612 CEFBS_None, // OpMaskedGatherINTEL
3613 CEFBS_None, // OpMaskedScatterINTEL
3614 CEFBS_None, // OpMatrixTimesMatrix
3615 CEFBS_None, // OpMatrixTimesScalar
3616 CEFBS_None, // OpMatrixTimesVector
3617 CEFBS_None, // OpMemberDecorate
3618 CEFBS_None, // OpMemberDecorateString
3619 CEFBS_None, // OpMemberName
3620 CEFBS_None, // OpMemoryBarrier
3621 CEFBS_None, // OpMemoryModel
3622 CEFBS_None, // OpMemoryNamedBarrier
3623 CEFBS_None, // OpModuleProcessed
3624 CEFBS_None, // OpName
3625 CEFBS_None, // OpNamedBarrierInitialize
3626 CEFBS_None, // OpNoLine
3627 CEFBS_None, // OpNop
3628 CEFBS_None, // OpNot
3629 CEFBS_None, // OpOrdered
3630 CEFBS_None, // OpOuterProduct
3631 CEFBS_None, // OpPhi
3632 CEFBS_None, // OpPredicatedLoadINTEL
3633 CEFBS_None, // OpPredicatedStoreINTEL
3634 CEFBS_None, // OpPtrAccessChain
3635 CEFBS_None, // OpPtrCastToCrossWorkgroupINTEL
3636 CEFBS_None, // OpPtrCastToGeneric
3637 CEFBS_None, // OpPtrDiff
3638 CEFBS_None, // OpPtrEqual
3639 CEFBS_None, // OpPtrNotEqual
3640 CEFBS_None, // OpQuantizeToF16
3641 CEFBS_None, // OpReadClockKHR
3642 CEFBS_None, // OpReadPipe
3643 CEFBS_None, // OpReadPipeBlockingALTERA
3644 CEFBS_None, // OpReleaseEvent
3645 CEFBS_None, // OpReserveReadPipePackets
3646 CEFBS_None, // OpReserveWritePipePackets
3647 CEFBS_None, // OpReservedReadPipe
3648 CEFBS_None, // OpReservedWritePipe
3649 CEFBS_None, // OpRestoreMemoryINTEL
3650 CEFBS_None, // OpRetainEvent
3651 CEFBS_None, // OpReturn
3652 CEFBS_None, // OpReturnValue
3653 CEFBS_None, // OpRoundFToTF32INTEL
3654 CEFBS_None, // OpSConvert
3655 CEFBS_None, // OpSDivS
3656 CEFBS_None, // OpSDivV
3657 CEFBS_None, // OpSDot
3658 CEFBS_None, // OpSDotAccSat
3659 CEFBS_None, // OpSGreaterThan
3660 CEFBS_None, // OpSGreaterThanEqual
3661 CEFBS_None, // OpSLessThan
3662 CEFBS_None, // OpSLessThanEqual
3663 CEFBS_None, // OpSMod
3664 CEFBS_None, // OpSMulExtended
3665 CEFBS_None, // OpSNegate
3666 CEFBS_None, // OpSRemS
3667 CEFBS_None, // OpSRemV
3668 CEFBS_None, // OpSUDot
3669 CEFBS_None, // OpSUDotAccSat
3670 CEFBS_None, // OpSampledImage
3671 CEFBS_None, // OpSatConvertSToU
3672 CEFBS_None, // OpSatConvertUToS
3673 CEFBS_None, // OpSaveMemoryINTEL
3674 CEFBS_None, // OpSelectSFSCond
3675 CEFBS_None, // OpSelectSFVCond
3676 CEFBS_None, // OpSelectSISCond
3677 CEFBS_None, // OpSelectSIVCond
3678 CEFBS_None, // OpSelectSPSCond
3679 CEFBS_None, // OpSelectSPVCond
3680 CEFBS_None, // OpSelectVFSCond
3681 CEFBS_None, // OpSelectVFVCond
3682 CEFBS_None, // OpSelectVISCond
3683 CEFBS_None, // OpSelectVIVCond
3684 CEFBS_None, // OpSelectVPSCond
3685 CEFBS_None, // OpSelectVPVCond
3686 CEFBS_None, // OpSelectionMerge
3687 CEFBS_None, // OpSetUserEventStatus
3688 CEFBS_None, // OpShiftLeftLogicalS
3689 CEFBS_None, // OpShiftLeftLogicalV
3690 CEFBS_None, // OpShiftRightArithmeticS
3691 CEFBS_None, // OpShiftRightArithmeticV
3692 CEFBS_None, // OpShiftRightLogicalS
3693 CEFBS_None, // OpShiftRightLogicalV
3694 CEFBS_None, // OpSignBitSet
3695 CEFBS_None, // OpSizeOf
3696 CEFBS_None, // OpSource
3697 CEFBS_None, // OpSourceContinued
3698 CEFBS_None, // OpSourceExtension
3699 CEFBS_None, // OpSpecConstant
3700 CEFBS_None, // OpSpecConstantComposite
3701 CEFBS_None, // OpSpecConstantCompositeContinuedINTEL
3702 CEFBS_None, // OpSpecConstantFalse
3703 CEFBS_None, // OpSpecConstantOp
3704 CEFBS_None, // OpSpecConstantTrue
3705 CEFBS_None, // OpStore
3706 CEFBS_None, // OpStrictFAddS
3707 CEFBS_None, // OpStrictFAddV
3708 CEFBS_None, // OpStrictFDivS
3709 CEFBS_None, // OpStrictFDivV
3710 CEFBS_None, // OpStrictFMulS
3711 CEFBS_None, // OpStrictFMulV
3712 CEFBS_None, // OpStrictFRemS
3713 CEFBS_None, // OpStrictFRemV
3714 CEFBS_None, // OpStrictFSubS
3715 CEFBS_None, // OpStrictFSubV
3716 CEFBS_None, // OpString
3717 CEFBS_None, // OpSubgroup2DBlockLoadINTEL
3718 CEFBS_None, // OpSubgroup2DBlockLoadTransformINTEL
3719 CEFBS_None, // OpSubgroup2DBlockLoadTransposeINTEL
3720 CEFBS_None, // OpSubgroup2DBlockPrefetchINTEL
3721 CEFBS_None, // OpSubgroup2DBlockStoreINTEL
3722 CEFBS_None, // OpSubgroupBlockReadINTEL
3723 CEFBS_None, // OpSubgroupBlockWriteINTEL
3724 CEFBS_None, // OpSubgroupImageBlockReadINTEL
3725 CEFBS_None, // OpSubgroupImageBlockWriteINTEL
3726 CEFBS_None, // OpSubgroupImageMediaBlockReadINTEL
3727 CEFBS_None, // OpSubgroupImageMediaBlockWriteINTEL
3728 CEFBS_None, // OpSubgroupMatrixMultiplyAccumulateINTEL
3729 CEFBS_None, // OpSubgroupShuffleDownINTEL
3730 CEFBS_None, // OpSubgroupShuffleINTEL
3731 CEFBS_None, // OpSubgroupShuffleUpINTEL
3732 CEFBS_None, // OpSubgroupShuffleXorINTEL
3733 CEFBS_None, // OpSwitch
3734 CEFBS_None, // OpTranspose
3735 CEFBS_None, // OpTypeAccelerationStructureNV
3736 CEFBS_None, // OpTypeArray
3737 CEFBS_None, // OpTypeBool
3738 CEFBS_None, // OpTypeCooperativeMatrixKHR
3739 CEFBS_None, // OpTypeCooperativeMatrixNV
3740 CEFBS_None, // OpTypeDeviceEvent
3741 CEFBS_None, // OpTypeEvent
3742 CEFBS_None, // OpTypeFloat
3743 CEFBS_None, // OpTypeForwardPointer
3744 CEFBS_None, // OpTypeFunction
3745 CEFBS_None, // OpTypeImage
3746 CEFBS_None, // OpTypeInt
3747 CEFBS_None, // OpTypeMatrix
3748 CEFBS_None, // OpTypeNamedBarrier
3749 CEFBS_None, // OpTypeOpaque
3750 CEFBS_None, // OpTypePipe
3751 CEFBS_None, // OpTypePipeStorage
3752 CEFBS_None, // OpTypePointer
3753 CEFBS_None, // OpTypeQueue
3754 CEFBS_None, // OpTypeReserveId
3755 CEFBS_None, // OpTypeRuntimeArray
3756 CEFBS_None, // OpTypeSampledImage
3757 CEFBS_None, // OpTypeSampler
3758 CEFBS_None, // OpTypeStruct
3759 CEFBS_None, // OpTypeStructContinuedINTEL
3760 CEFBS_None, // OpTypeVector
3761 CEFBS_None, // OpTypeVoid
3762 CEFBS_None, // OpUConvert
3763 CEFBS_None, // OpUDivS
3764 CEFBS_None, // OpUDivV
3765 CEFBS_None, // OpUDot
3766 CEFBS_None, // OpUDotAccSat
3767 CEFBS_None, // OpUGreaterThan
3768 CEFBS_None, // OpUGreaterThanEqual
3769 CEFBS_None, // OpULessThan
3770 CEFBS_None, // OpULessThanEqual
3771 CEFBS_None, // OpUModS
3772 CEFBS_None, // OpUModV
3773 CEFBS_None, // OpUMulExtended
3774 CEFBS_None, // OpUndef
3775 CEFBS_None, // OpUnordered
3776 CEFBS_None, // OpUnreachable
3777 CEFBS_None, // OpVariable
3778 CEFBS_None, // OpVariableLengthArrayINTEL
3779 CEFBS_None, // OpVectorExtractDynamic
3780 CEFBS_None, // OpVectorInsertDynamic
3781 CEFBS_None, // OpVectorShuffle
3782 CEFBS_None, // OpVectorTimesMatrix
3783 CEFBS_None, // OpVectorTimesScalar
3784 CEFBS_None, // OpWritePipe
3785 CEFBS_None, // OpWritePipeBlockingALTERA
3786 };
3787
3788 assert(Opcode < 841);
3789 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3790}
3791
3792
3793} // namespace llvm::SPIRV_MC
3794
3795#endif // GET_COMPUTE_FEATURES
3796
3797#ifdef GET_AVAILABLE_OPCODE_CHECKER
3798#undef GET_AVAILABLE_OPCODE_CHECKER
3799
3800namespace llvm::SPIRV_MC {
3801
3802bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3803 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3804 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3805 FeatureBitset MissingFeatures =
3806 (AvailableFeatures & RequiredFeatures) ^
3807 RequiredFeatures;
3808 return !MissingFeatures.any();
3809}
3810
3811} // namespace llvm::SPIRV_MC
3812
3813#endif // GET_AVAILABLE_OPCODE_CHECKER
3814
3815#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3816#undef ENABLE_INSTR_PREDICATE_VERIFIER
3817
3818#include <sstream>
3819
3820namespace llvm::SPIRV_MC {
3821
3822#ifndef NDEBUG
3823static const char *SubtargetFeatureNames[] = {
3824 nullptr
3825};
3826
3827#endif // NDEBUG
3828
3829void verifyInstructionPredicates(
3830 unsigned Opcode, const FeatureBitset &Features) {
3831#ifndef NDEBUG
3832 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3833 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3834 FeatureBitset MissingFeatures =
3835 (AvailableFeatures & RequiredFeatures) ^
3836 RequiredFeatures;
3837 if (MissingFeatures.any()) {
3838 std::ostringstream Msg;
3839 Msg << "Attempting to emit " << &SPIRVInstrNameData[SPIRVInstrNameIndices[Opcode]]
3840 << " instruction but the ";
3841 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3842 if (MissingFeatures.test(i))
3843 Msg << SubtargetFeatureNames[i] << " ";
3844 Msg << "predicate(s) are not met";
3845 report_fatal_error(Msg.str().c_str());
3846 }
3847#endif // NDEBUG
3848}
3849
3850} // namespace llvm::SPIRV_MC
3851
3852#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3853
3854