1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SPIRV {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1530
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543
96 G_INSERT = 81, // GenericOpcodes.td:1552
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1562
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330
114 G_LOAD = 99, // GenericOpcodes.td:1357
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1366
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1374
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1383
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410
121 G_STORE = 106, // GenericOpcodes.td:1418
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1436
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1508
150 G_PREFETCH = 135, // GenericOpcodes.td:1515
151 G_BRCOND = 136, // GenericOpcodes.td:1655
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1664
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687
154 G_INTRINSIC = 139, // GenericOpcodes.td:1607
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:609
183 G_UADDE = 168, // GenericOpcodes.td:617
184 G_USUBO = 169, // GenericOpcodes.td:639
185 G_USUBE = 170, // GenericOpcodes.td:645
186 G_SADDO = 171, // GenericOpcodes.td:624
187 G_SADDE = 172, // GenericOpcodes.td:632
188 G_SSUBO = 173, // GenericOpcodes.td:652
189 G_SSUBE = 174, // GenericOpcodes.td:659
190 G_UMULO = 175, // GenericOpcodes.td:666
191 G_SMULO = 176, // GenericOpcodes.td:674
192 G_UMULH = 177, // GenericOpcodes.td:683
193 G_SMULH = 178, // GenericOpcodes.td:692
194 G_UADDSAT = 179, // GenericOpcodes.td:704
195 G_SADDSAT = 180, // GenericOpcodes.td:712
196 G_USUBSAT = 181, // GenericOpcodes.td:720
197 G_SSUBSAT = 182, // GenericOpcodes.td:728
198 G_USHLSAT = 183, // GenericOpcodes.td:736
199 G_SSHLSAT = 184, // GenericOpcodes.td:744
200 G_SMULFIX = 185, // GenericOpcodes.td:756
201 G_UMULFIX = 186, // GenericOpcodes.td:763
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:773
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:780
204 G_SDIVFIX = 189, // GenericOpcodes.td:791
205 G_UDIVFIX = 190, // GenericOpcodes.td:798
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:808
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:815
208 G_FADD = 193, // GenericOpcodes.td:988
209 G_FSUB = 194, // GenericOpcodes.td:996
210 G_FMUL = 195, // GenericOpcodes.td:1004
211 G_FMA = 196, // GenericOpcodes.td:1013
212 G_FMAD = 197, // GenericOpcodes.td:1022
213 G_FDIV = 198, // GenericOpcodes.td:1030
214 G_FREM = 199, // GenericOpcodes.td:1037
215 G_FMODF = 200, // GenericOpcodes.td:1044
216 G_FPOW = 201, // GenericOpcodes.td:1051
217 G_FPOWI = 202, // GenericOpcodes.td:1058
218 G_FEXP = 203, // GenericOpcodes.td:1065
219 G_FEXP2 = 204, // GenericOpcodes.td:1072
220 G_FEXP10 = 205, // GenericOpcodes.td:1079
221 G_FLOG = 206, // GenericOpcodes.td:1086
222 G_FLOG2 = 207, // GenericOpcodes.td:1093
223 G_FLOG10 = 208, // GenericOpcodes.td:1100
224 G_FLDEXP = 209, // GenericOpcodes.td:1107
225 G_FFREXP = 210, // GenericOpcodes.td:1114
226 G_FNEG = 211, // GenericOpcodes.td:826
227 G_FPEXT = 212, // GenericOpcodes.td:832
228 G_FPTRUNC = 213, // GenericOpcodes.td:838
229 G_FPTOSI = 214, // GenericOpcodes.td:844
230 G_FPTOUI = 215, // GenericOpcodes.td:850
231 G_SITOFP = 216, // GenericOpcodes.td:856
232 G_UITOFP = 217, // GenericOpcodes.td:862
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:868
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:874
235 G_FABS = 220, // GenericOpcodes.td:880
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:886
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:899
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:892
239 G_FMINNUM = 224, // GenericOpcodes.td:912
240 G_FMAXNUM = 225, // GenericOpcodes.td:919
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944
243 G_FMINIMUM = 228, // GenericOpcodes.td:954
244 G_FMAXIMUM = 229, // GenericOpcodes.td:961
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:969
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976
247 G_GET_FPENV = 232, // GenericOpcodes.td:1244
248 G_SET_FPENV = 233, // GenericOpcodes.td:1251
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1258
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1265
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1272
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1279
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1336
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1342
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1645
265 G_BRJT = 250, // GenericOpcodes.td:1675
266 G_VSCALE = 251, // GenericOpcodes.td:1573
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1770
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_FCEIL = 270, // GenericOpcodes.td:1121
286 G_FCOS = 271, // GenericOpcodes.td:1128
287 G_FSIN = 272, // GenericOpcodes.td:1135
288 G_FSINCOS = 273, // GenericOpcodes.td:1142
289 G_FTAN = 274, // GenericOpcodes.td:1149
290 G_FACOS = 275, // GenericOpcodes.td:1156
291 G_FASIN = 276, // GenericOpcodes.td:1163
292 G_FATAN = 277, // GenericOpcodes.td:1170
293 G_FATAN2 = 278, // GenericOpcodes.td:1177
294 G_FCOSH = 279, // GenericOpcodes.td:1184
295 G_FSINH = 280, // GenericOpcodes.td:1191
296 G_FTANH = 281, // GenericOpcodes.td:1198
297 G_FSQRT = 282, // GenericOpcodes.td:1208
298 G_FFLOOR = 283, // GenericOpcodes.td:1215
299 G_FRINT = 284, // GenericOpcodes.td:1222
300 G_FNEARBYINT = 285, // GenericOpcodes.td:1229
301 G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248
302 G_BLOCK_ADDR = 287, // GenericOpcodes.td:254
303 G_JUMP_TABLE = 288, // GenericOpcodes.td:260
304 G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266
305 G_STACKSAVE = 290, // GenericOpcodes.td:272
306 G_STACKRESTORE = 291, // GenericOpcodes.td:278
307 G_STRICT_FADD = 292, // GenericOpcodes.td:1829
308 G_STRICT_FSUB = 293, // GenericOpcodes.td:1830
309 G_STRICT_FMUL = 294, // GenericOpcodes.td:1831
310 G_STRICT_FDIV = 295, // GenericOpcodes.td:1832
311 G_STRICT_FREM = 296, // GenericOpcodes.td:1833
312 G_STRICT_FMA = 297, // GenericOpcodes.td:1834
313 G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835
314 G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836
315 G_STRICT_FCMP = 300, // GenericOpcodes.td:1837
316 G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838
317 G_READ_REGISTER = 302, // GenericOpcodes.td:1694
318 G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704
319 G_MEMCPY = 304, // GenericOpcodes.td:1844
320 G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852
321 G_MEMMOVE = 306, // GenericOpcodes.td:1860
322 G_MEMSET = 307, // GenericOpcodes.td:1868
323 G_BZERO = 308, // GenericOpcodes.td:1875
324 G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882
325 G_TRAP = 310, // GenericOpcodes.td:1892
326 G_DEBUGTRAP = 311, // GenericOpcodes.td:1899
327 G_UBSANTRAP = 312, // GenericOpcodes.td:1905
328 G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793
329 G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799
330 G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805
331 G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806
332 G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808
333 G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809
334 G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810
335 G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811
336 G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812
337 G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813
338 G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815
339 G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816
340 G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817
341 G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818
342 G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819
343 G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820
344 G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821
345 G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822
346 G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823
347 G_SBFX = 332, // GenericOpcodes.td:1917
348 G_UBFX = 333, // GenericOpcodes.td:1925
349 ASSIGN_TYPE = 334, // SPIRVInstrInfo.td:18
350 UNKNOWN_type = 335, // SPIRVInstrInfo.td:21
351 OpAbortKHR = 336, // SPIRVInstrInfo.td:679
352 OpAccessChain = 337, // SPIRVInstrInfo.td:274
353 OpAliasDomainDeclINTEL = 338, // SPIRVInstrInfo.td:998
354 OpAliasScopeDeclINTEL = 339, // SPIRVInstrInfo.td:1000
355 OpAliasScopeListDeclINTEL = 340, // SPIRVInstrInfo.td:1002
356 OpAll = 341, // SPIRVInstrInfo.td:595
357 OpAny = 342, // SPIRVInstrInfo.td:593
358 OpArbitraryFloatACosALTERA = 343, // SPIRVInstrInfo.td:1089
359 OpArbitraryFloatACosPiALTERA = 344, // SPIRVInstrInfo.td:1091
360 OpArbitraryFloatASinALTERA = 345, // SPIRVInstrInfo.td:1085
361 OpArbitraryFloatASinPiALTERA = 346, // SPIRVInstrInfo.td:1087
362 OpArbitraryFloatATan2ALTERA = 347, // SPIRVInstrInfo.td:1097
363 OpArbitraryFloatATanALTERA = 348, // SPIRVInstrInfo.td:1093
364 OpArbitraryFloatATanPiALTERA = 349, // SPIRVInstrInfo.td:1095
365 OpArbitraryFloatAddALTERA = 350, // SPIRVInstrInfo.td:1074
366 OpArbitraryFloatCastALTERA = 351, // SPIRVInstrInfo.td:1105
367 OpArbitraryFloatCastFromIntALTERA = 352, // SPIRVInstrInfo.td:1107
368 OpArbitraryFloatCastToIntALTERA = 353, // SPIRVInstrInfo.td:1109
369 OpArbitraryFloatCbrtALTERA = 354, // SPIRVInstrInfo.td:1023
370 OpArbitraryFloatCosALTERA = 355, // SPIRVInstrInfo.td:1059
371 OpArbitraryFloatCosPiALTERA = 356, // SPIRVInstrInfo.td:1068
372 OpArbitraryFloatDivALTERA = 357, // SPIRVInstrInfo.td:1081
373 OpArbitraryFloatEQALTERA = 358, // SPIRVInstrInfo.td:1018
374 OpArbitraryFloatExp10ALTERA = 359, // SPIRVInstrInfo.td:1050
375 OpArbitraryFloatExp2ALTERA = 360, // SPIRVInstrInfo.td:1047
376 OpArbitraryFloatExpALTERA = 361, // SPIRVInstrInfo.td:1044
377 OpArbitraryFloatExpm1ALTERA = 362, // SPIRVInstrInfo.td:1053
378 OpArbitraryFloatGEALTERA = 363, // SPIRVInstrInfo.td:1012
379 OpArbitraryFloatGTALTERA = 364, // SPIRVInstrInfo.td:1010
380 OpArbitraryFloatHypotALTERA = 365, // SPIRVInstrInfo.td:1026
381 OpArbitraryFloatLEALTERA = 366, // SPIRVInstrInfo.td:1016
382 OpArbitraryFloatLTALTERA = 367, // SPIRVInstrInfo.td:1014
383 OpArbitraryFloatLog10ALTERA = 368, // SPIRVInstrInfo.td:1038
384 OpArbitraryFloatLog1pALTERA = 369, // SPIRVInstrInfo.td:1041
385 OpArbitraryFloatLog2ALTERA = 370, // SPIRVInstrInfo.td:1035
386 OpArbitraryFloatLogALTERA = 371, // SPIRVInstrInfo.td:1032
387 OpArbitraryFloatMulALTERA = 372, // SPIRVInstrInfo.td:1079
388 OpArbitraryFloatPowALTERA = 373, // SPIRVInstrInfo.td:1099
389 OpArbitraryFloatPowNALTERA = 374, // SPIRVInstrInfo.td:1103
390 OpArbitraryFloatPowRALTERA = 375, // SPIRVInstrInfo.td:1101
391 OpArbitraryFloatRSqrtALTERA = 376, // SPIRVInstrInfo.td:1083
392 OpArbitraryFloatRecipALTERA = 377, // SPIRVInstrInfo.td:1020
393 OpArbitraryFloatSinALTERA = 378, // SPIRVInstrInfo.td:1056
394 OpArbitraryFloatSinCosALTERA = 379, // SPIRVInstrInfo.td:1062
395 OpArbitraryFloatSinCosPiALTERA = 380, // SPIRVInstrInfo.td:1071
396 OpArbitraryFloatSinPiALTERA = 381, // SPIRVInstrInfo.td:1065
397 OpArbitraryFloatSqrtALTERA = 382, // SPIRVInstrInfo.td:1029
398 OpArbitraryFloatSubALTERA = 383, // SPIRVInstrInfo.td:1077
399 OpArithmeticFenceEXT = 384, // SPIRVInstrInfo.td:986
400 OpArrayLength = 385, // SPIRVInstrInfo.td:282
401 OpAsmCallINTEL = 386, // SPIRVInstrInfo.td:952
402 OpAsmINTEL = 387, // SPIRVInstrInfo.td:949
403 OpAsmTargetINTEL = 388, // SPIRVInstrInfo.td:948
404 OpAssumeTrueKHR = 389, // SPIRVInstrInfo.td:106
405 OpAtomicAnd = 390, // SPIRVInstrInfo.td:723
406 OpAtomicCompareExchange = 391, // SPIRVInstrInfo.td:703
407 OpAtomicCompareExchangeWeak = 392, // SPIRVInstrInfo.td:707
408 OpAtomicExchange = 393, // SPIRVInstrInfo.td:700
409 OpAtomicFAddEXT = 394, // SPIRVInstrInfo.td:727
410 OpAtomicFMaxEXT = 395, // SPIRVInstrInfo.td:729
411 OpAtomicFMinEXT = 396, // SPIRVInstrInfo.td:728
412 OpAtomicFlagClear = 397, // SPIRVInstrInfo.td:732
413 OpAtomicFlagTestAndSet = 398, // SPIRVInstrInfo.td:731
414 OpAtomicIAdd = 399, // SPIRVInstrInfo.td:715
415 OpAtomicIDecrement = 400, // SPIRVInstrInfo.td:713
416 OpAtomicIIncrement = 401, // SPIRVInstrInfo.td:712
417 OpAtomicISub = 402, // SPIRVInstrInfo.td:716
418 OpAtomicLoad = 403, // SPIRVInstrInfo.td:696
419 OpAtomicOr = 404, // SPIRVInstrInfo.td:724
420 OpAtomicSMax = 405, // SPIRVInstrInfo.td:720
421 OpAtomicSMin = 406, // SPIRVInstrInfo.td:718
422 OpAtomicStore = 407, // SPIRVInstrInfo.td:698
423 OpAtomicUMax = 408, // SPIRVInstrInfo.td:721
424 OpAtomicUMin = 409, // SPIRVInstrInfo.td:719
425 OpAtomicXor = 410, // SPIRVInstrInfo.td:725
426 OpBitCount = 411, // SPIRVInstrInfo.td:589
427 OpBitFieldInsert = 412, // SPIRVInstrInfo.td:579
428 OpBitFieldSExtract = 413, // SPIRVInstrInfo.td:582
429 OpBitFieldUExtract = 414, // SPIRVInstrInfo.td:585
430 OpBitReverse = 415, // SPIRVInstrInfo.td:588
431 OpBitcast = 416, // SPIRVInstrInfo.td:473
432 OpBitwiseAndS = 417, // SPIRVInstrInfo.td:48
433 OpBitwiseAndV = 418, // SPIRVInstrInfo.td:53
434 OpBitwiseFunctionINTEL = 419, // SPIRVInstrInfo.td:1006
435 OpBitwiseOrS = 420, // SPIRVInstrInfo.td:48
436 OpBitwiseOrV = 421, // SPIRVInstrInfo.td:53
437 OpBitwiseXorS = 422, // SPIRVInstrInfo.td:48
438 OpBitwiseXorV = 423, // SPIRVInstrInfo.td:53
439 OpBranch = 424, // SPIRVInstrInfo.td:669
440 OpBranchConditional = 425, // SPIRVInstrInfo.td:670
441 OpBuildNDRange = 426, // SPIRVInstrInfo.td:805
442 OpCapability = 427, // SPIRVInstrInfo.td:164
443 OpCaptureEventProfilingInfo = 428, // SPIRVInstrInfo.td:800
444 OpCommitReadPipe = 429, // SPIRVInstrInfo.td:822
445 OpCommitWritePipe = 430, // SPIRVInstrInfo.td:824
446 OpCompositeConstruct = 431, // SPIRVInstrInfo.td:494
447 OpCompositeConstructContinuedINTEL = 432, // SPIRVInstrInfo.td:496
448 OpCompositeExtract = 433, // SPIRVInstrInfo.td:498
449 OpCompositeInsert = 434, // SPIRVInstrInfo.td:500
450 OpConstantComposite = 435, // SPIRVInstrInfo.td:236
451 OpConstantCompositeContinuedINTEL = 436, // SPIRVInstrInfo.td:238
452 OpConstantF = 437, // SPIRVInstrInfo.td:224
453 OpConstantFalse = 438, // SPIRVInstrInfo.td:233
454 OpConstantFunctionPointerINTEL = 439, // SPIRVInstrInfo.td:904
455 OpConstantI = 440, // SPIRVInstrInfo.td:222
456 OpConstantNull = 441, // SPIRVInstrInfo.td:244
457 OpConstantSampler = 442, // SPIRVInstrInfo.td:241
458 OpConstantTrue = 443, // SPIRVInstrInfo.td:231
459 OpControlBarrier = 444, // SPIRVInstrInfo.td:744
460 OpControlBarrierArriveINTEL = 445, // SPIRVInstrInfo.td:753
461 OpControlBarrierWaitINTEL = 446, // SPIRVInstrInfo.td:755
462 OpConvertBF16ToFINTEL = 447, // SPIRVInstrInfo.td:481
463 OpConvertFToBF16INTEL = 448, // SPIRVInstrInfo.td:480
464 OpConvertFToS = 449, // SPIRVInstrInfo.td:453
465 OpConvertFToU = 450, // SPIRVInstrInfo.td:452
466 OpConvertHandleToImageINTEL = 451, // SPIRVInstrInfo.td:990
467 OpConvertHandleToSampledImageINTEL = 452, // SPIRVInstrInfo.td:994
468 OpConvertHandleToSamplerINTEL = 453, // SPIRVInstrInfo.td:992
469 OpConvertPtrToU = 454, // SPIRVInstrInfo.td:463
470 OpConvertSToF = 455, // SPIRVInstrInfo.td:454
471 OpConvertUToF = 456, // SPIRVInstrInfo.td:455
472 OpConvertUToPtr = 457, // SPIRVInstrInfo.td:468
473 OpCooperativeMatrixConstructCheckedINTEL = 458, // SPIRVInstrInfo.td:975
474 OpCooperativeMatrixGetElementCoordINTEL = 459, // SPIRVInstrInfo.td:978
475 OpCooperativeMatrixLengthKHR = 460, // SPIRVInstrInfo.td:965
476 OpCooperativeMatrixLoadCheckedINTEL = 461, // SPIRVInstrInfo.td:969
477 OpCooperativeMatrixLoadKHR = 462, // SPIRVInstrInfo.td:956
478 OpCooperativeMatrixMulAddKHR = 463, // SPIRVInstrInfo.td:962
479 OpCooperativeMatrixPrefetchINTEL = 464, // SPIRVInstrInfo.td:981
480 OpCooperativeMatrixStoreCheckedINTEL = 465, // SPIRVInstrInfo.td:972
481 OpCooperativeMatrixStoreKHR = 466, // SPIRVInstrInfo.td:959
482 OpCopyLogical = 467, // SPIRVInstrInfo.td:504
483 OpCopyMemory = 468, // SPIRVInstrInfo.td:270
484 OpCopyMemorySized = 469, // SPIRVInstrInfo.td:272
485 OpCopyObject = 470, // SPIRVInstrInfo.td:502
486 OpCreateUserEvent = 471, // SPIRVInstrInfo.td:794
487 OpCrossWorkgroupCastToPtrINTEL = 472, // SPIRVInstrInfo.td:477
488 OpDPdx = 473, // SPIRVInstrInfo.td:645
489 OpDPdxCoarse = 474, // SPIRVInstrInfo.td:653
490 OpDPdxFine = 475, // SPIRVInstrInfo.td:649
491 OpDPdy = 476, // SPIRVInstrInfo.td:646
492 OpDPdyCoarse = 477, // SPIRVInstrInfo.td:654
493 OpDPdyFine = 478, // SPIRVInstrInfo.td:650
494 OpDecorate = 479, // SPIRVInstrInfo.td:128
495 OpDecorateId = 480, // SPIRVInstrInfo.td:136
496 OpDecorateString = 481, // SPIRVInstrInfo.td:138
497 OpDemoteToHelperInvocation = 482, // SPIRVInstrInfo.td:684
498 OpDot = 483, // SPIRVInstrInfo.td:545
499 OpEmitStreamVertex = 484, // SPIRVInstrInfo.td:739
500 OpEmitVertex = 485, // SPIRVInstrInfo.td:737
501 OpEndPrimitive = 486, // SPIRVInstrInfo.td:738
502 OpEndStreamPrimitive = 487, // SPIRVInstrInfo.td:740
503 OpEnqueueKernel = 488, // SPIRVInstrInfo.td:789
504 OpEntryPoint = 489, // SPIRVInstrInfo.td:159
505 OpExecutionMode = 490, // SPIRVInstrInfo.td:162
506 OpExecutionModeId = 491, // SPIRVInstrInfo.td:165
507 OpExpectKHR = 492, // SPIRVInstrInfo.td:107
508 OpExtInst = 493, // SPIRVInstrInfo.td:153
509 OpExtInstImport = 494, // SPIRVInstrInfo.td:147
510 OpExtension = 495, // SPIRVInstrInfo.td:146
511 OpFAddS = 496, // SPIRVInstrInfo.td:46
512 OpFAddV = 497, // SPIRVInstrInfo.td:51
513 OpFConvert = 498, // SPIRVInstrInfo.td:459
514 OpFDivS = 499, // SPIRVInstrInfo.td:46
515 OpFDivV = 500, // SPIRVInstrInfo.td:51
516 OpFMod = 501, // SPIRVInstrInfo.td:536
517 OpFMulS = 502, // SPIRVInstrInfo.td:46
518 OpFMulV = 503, // SPIRVInstrInfo.td:51
519 OpFNegate = 504, // SPIRVInstrInfo.td:509
520 OpFNegateV = 505, // SPIRVInstrInfo.td:510
521 OpFOrdEqual = 506, // SPIRVInstrInfo.td:628
522 OpFOrdGreaterThan = 507, // SPIRVInstrInfo.td:635
523 OpFOrdGreaterThanEqual = 508, // SPIRVInstrInfo.td:640
524 OpFOrdLessThan = 509, // SPIRVInstrInfo.td:633
525 OpFOrdLessThanEqual = 510, // SPIRVInstrInfo.td:638
526 OpFOrdNotEqual = 511, // SPIRVInstrInfo.td:630
527 OpFRemS = 512, // SPIRVInstrInfo.td:46
528 OpFRemV = 513, // SPIRVInstrInfo.td:51
529 OpFSubS = 514, // SPIRVInstrInfo.td:46
530 OpFSubV = 515, // SPIRVInstrInfo.td:51
531 OpFUnordEqual = 516, // SPIRVInstrInfo.td:629
532 OpFUnordGreaterThan = 517, // SPIRVInstrInfo.td:636
533 OpFUnordGreaterThanEqual = 518, // SPIRVInstrInfo.td:641
534 OpFUnordLessThan = 519, // SPIRVInstrInfo.td:634
535 OpFUnordLessThanEqual = 520, // SPIRVInstrInfo.td:639
536 OpFUnordNotEqual = 521, // SPIRVInstrInfo.td:631
537 OpFixedCosALTERA = 522, // SPIRVInstrInfo.td:1150
538 OpFixedCosPiALTERA = 523, // SPIRVInstrInfo.td:1156
539 OpFixedExpALTERA = 524, // SPIRVInstrInfo.td:1162
540 OpFixedLogALTERA = 525, // SPIRVInstrInfo.td:1160
541 OpFixedRecipALTERA = 526, // SPIRVInstrInfo.td:1144
542 OpFixedRsqrtALTERA = 527, // SPIRVInstrInfo.td:1146
543 OpFixedSinALTERA = 528, // SPIRVInstrInfo.td:1148
544 OpFixedSinCosALTERA = 529, // SPIRVInstrInfo.td:1152
545 OpFixedSinCosPiALTERA = 530, // SPIRVInstrInfo.td:1158
546 OpFixedSinPiALTERA = 531, // SPIRVInstrInfo.td:1154
547 OpFixedSqrtALTERA = 532, // SPIRVInstrInfo.td:1142
548 OpFmaKHR = 533, // SPIRVInstrInfo.td:565
549 OpFreezeKHR = 534, // SPIRVInstrInfo.td:103
550 OpFunction = 535, // SPIRVInstrInfo.td:334
551 OpFunctionCall = 536, // SPIRVInstrInfo.td:342
552 OpFunctionEnd = 537, // SPIRVInstrInfo.td:339
553 OpFunctionParameter = 538, // SPIRVInstrInfo.td:337
554 OpFunctionPointerCallINTEL = 539, // SPIRVInstrInfo.td:909
555 OpFwidth = 540, // SPIRVInstrInfo.td:647
556 OpFwidthCoarse = 541, // SPIRVInstrInfo.td:655
557 OpFwidthFine = 542, // SPIRVInstrInfo.td:651
558 OpGenericCastToPtr = 543, // SPIRVInstrInfo.td:470
559 OpGenericCastToPtrExplicit = 544, // SPIRVInstrInfo.td:471
560 OpGenericPtrMemSemantics = 545, // SPIRVInstrInfo.td:284
561 OpGetDefaultQueue = 546, // SPIRVInstrInfo.td:803
562 OpGetMaxPipePackets = 547, // SPIRVInstrInfo.td:830
563 OpGetNumPipePackets = 548, // SPIRVInstrInfo.td:828
564 OpGroupAll = 549, // SPIRVInstrInfo.td:765
565 OpGroupAny = 550, // SPIRVInstrInfo.td:767
566 OpGroupAsyncCopy = 551, // SPIRVInstrInfo.td:760
567 OpGroupBitwiseAndKHR = 552, // SPIRVInstrInfo.td:940
568 OpGroupBitwiseOrKHR = 553, // SPIRVInstrInfo.td:941
569 OpGroupBitwiseXorKHR = 554, // SPIRVInstrInfo.td:942
570 OpGroupBroadcast = 555, // SPIRVInstrInfo.td:769
571 OpGroupCommitReadPipe = 556, // SPIRVInstrInfo.td:836
572 OpGroupCommitWritePipe = 557, // SPIRVInstrInfo.td:838
573 OpGroupFAdd = 558, // SPIRVInstrInfo.td:776
574 OpGroupFMax = 559, // SPIRVInstrInfo.td:780
575 OpGroupFMin = 560, // SPIRVInstrInfo.td:777
576 OpGroupFMulKHR = 561, // SPIRVInstrInfo.td:939
577 OpGroupIAdd = 562, // SPIRVInstrInfo.td:775
578 OpGroupIMulKHR = 563, // SPIRVInstrInfo.td:938
579 OpGroupLogicalAndKHR = 564, // SPIRVInstrInfo.td:943
580 OpGroupLogicalOrKHR = 565, // SPIRVInstrInfo.td:944
581 OpGroupLogicalXorKHR = 566, // SPIRVInstrInfo.td:945
582 OpGroupNonUniformAll = 567, // SPIRVInstrInfo.td:851
583 OpGroupNonUniformAllEqual = 568, // SPIRVInstrInfo.td:853
584 OpGroupNonUniformAny = 569, // SPIRVInstrInfo.td:852
585 OpGroupNonUniformBallot = 570, // SPIRVInstrInfo.td:856
586 OpGroupNonUniformBallotBitCount = 571, // SPIRVInstrInfo.td:859
587 OpGroupNonUniformBallotBitExtract = 572, // SPIRVInstrInfo.td:858
588 OpGroupNonUniformBallotFindLSB = 573, // SPIRVInstrInfo.td:863
589 OpGroupNonUniformBallotFindMSB = 574, // SPIRVInstrInfo.td:864
590 OpGroupNonUniformBitwiseAnd = 575, // SPIRVInstrInfo.td:883
591 OpGroupNonUniformBitwiseOr = 576, // SPIRVInstrInfo.td:884
592 OpGroupNonUniformBitwiseXor = 577, // SPIRVInstrInfo.td:885
593 OpGroupNonUniformBroadcast = 578, // SPIRVInstrInfo.td:854
594 OpGroupNonUniformBroadcastFirst = 579, // SPIRVInstrInfo.td:855
595 OpGroupNonUniformElect = 580, // SPIRVInstrInfo.td:843
596 OpGroupNonUniformFAdd = 581, // SPIRVInstrInfo.td:874
597 OpGroupNonUniformFMax = 582, // SPIRVInstrInfo.td:882
598 OpGroupNonUniformFMin = 583, // SPIRVInstrInfo.td:879
599 OpGroupNonUniformFMul = 584, // SPIRVInstrInfo.td:876
600 OpGroupNonUniformIAdd = 585, // SPIRVInstrInfo.td:873
601 OpGroupNonUniformIMul = 586, // SPIRVInstrInfo.td:875
602 OpGroupNonUniformInverseBallot = 587, // SPIRVInstrInfo.td:857
603 OpGroupNonUniformLogicalAnd = 588, // SPIRVInstrInfo.td:886
604 OpGroupNonUniformLogicalOr = 589, // SPIRVInstrInfo.td:887
605 OpGroupNonUniformLogicalXor = 590, // SPIRVInstrInfo.td:888
606 OpGroupNonUniformQuadSwap = 591, // SPIRVInstrInfo.td:889
607 OpGroupNonUniformRotateKHR = 592, // SPIRVInstrInfo.td:892
608 OpGroupNonUniformSMax = 593, // SPIRVInstrInfo.td:880
609 OpGroupNonUniformSMin = 594, // SPIRVInstrInfo.td:877
610 OpGroupNonUniformShuffle = 595, // SPIRVInstrInfo.td:865
611 OpGroupNonUniformShuffleDown = 596, // SPIRVInstrInfo.td:868
612 OpGroupNonUniformShuffleUp = 597, // SPIRVInstrInfo.td:867
613 OpGroupNonUniformShuffleXor = 598, // SPIRVInstrInfo.td:866
614 OpGroupNonUniformUMax = 599, // SPIRVInstrInfo.td:881
615 OpGroupNonUniformUMin = 600, // SPIRVInstrInfo.td:878
616 OpGroupReserveReadPipePackets = 601, // SPIRVInstrInfo.td:832
617 OpGroupReserveWritePipePackets = 602, // SPIRVInstrInfo.td:834
618 OpGroupSMax = 603, // SPIRVInstrInfo.td:782
619 OpGroupSMin = 604, // SPIRVInstrInfo.td:779
620 OpGroupUMax = 605, // SPIRVInstrInfo.td:781
621 OpGroupUMin = 606, // SPIRVInstrInfo.td:778
622 OpGroupWaitEvents = 607, // SPIRVInstrInfo.td:763
623 OpIAddCarryS = 608, // SPIRVInstrInfo.td:48
624 OpIAddCarryV = 609, // SPIRVInstrInfo.td:53
625 OpIAddS = 610, // SPIRVInstrInfo.td:48
626 OpIAddV = 611, // SPIRVInstrInfo.td:53
627 OpIEqual = 612, // SPIRVInstrInfo.td:616
628 OpIMulS = 613, // SPIRVInstrInfo.td:48
629 OpIMulV = 614, // SPIRVInstrInfo.td:53
630 OpINotEqual = 615, // SPIRVInstrInfo.td:617
631 OpISubBorrowS = 616, // SPIRVInstrInfo.td:48
632 OpISubBorrowV = 617, // SPIRVInstrInfo.td:53
633 OpISubS = 618, // SPIRVInstrInfo.td:48
634 OpISubV = 619, // SPIRVInstrInfo.td:53
635 OpImage = 620, // SPIRVInstrInfo.td:393
636 OpImageDrefGather = 621, // SPIRVInstrInfo.td:383
637 OpImageFetch = 622, // SPIRVInstrInfo.td:377
638 OpImageGather = 623, // SPIRVInstrInfo.td:380
639 OpImageQueryFormat = 624, // SPIRVInstrInfo.td:394
640 OpImageQueryLevels = 625, // SPIRVInstrInfo.td:399
641 OpImageQueryLod = 626, // SPIRVInstrInfo.td:398
642 OpImageQueryOrder = 627, // SPIRVInstrInfo.td:395
643 OpImageQuerySamples = 628, // SPIRVInstrInfo.td:400
644 OpImageQuerySize = 629, // SPIRVInstrInfo.td:397
645 OpImageQuerySizeLod = 630, // SPIRVInstrInfo.td:396
646 OpImageRead = 631, // SPIRVInstrInfo.td:387
647 OpImageSampleDrefExplicitLod = 632, // SPIRVInstrInfo.td:359
648 OpImageSampleDrefImplicitLod = 633, // SPIRVInstrInfo.td:356
649 OpImageSampleExplicitLod = 634, // SPIRVInstrInfo.td:352
650 OpImageSampleFootprintNV = 635, // SPIRVInstrInfo.td:446
651 OpImageSampleImplicitLod = 636, // SPIRVInstrInfo.td:349
652 OpImageSampleProjDrefExplicitLod = 637, // SPIRVInstrInfo.td:373
653 OpImageSampleProjDrefImplicitLod = 638, // SPIRVInstrInfo.td:370
654 OpImageSampleProjExplicitLod = 639, // SPIRVInstrInfo.td:366
655 OpImageSampleProjImplicitLod = 640, // SPIRVInstrInfo.td:363
656 OpImageSparseDrefGather = 641, // SPIRVInstrInfo.td:436
657 OpImageSparseFetch = 642, // SPIRVInstrInfo.td:430
658 OpImageSparseGather = 643, // SPIRVInstrInfo.td:433
659 OpImageSparseRead = 644, // SPIRVInstrInfo.td:442
660 OpImageSparseSampleDrefExplicitLod = 645, // SPIRVInstrInfo.td:412
661 OpImageSparseSampleDrefImplicitLod = 646, // SPIRVInstrInfo.td:409
662 OpImageSparseSampleExplicitLod = 647, // SPIRVInstrInfo.td:405
663 OpImageSparseSampleImplicitLod = 648, // SPIRVInstrInfo.td:402
664 OpImageSparseSampleProjDrefExplicitLod = 649, // SPIRVInstrInfo.td:426
665 OpImageSparseSampleProjDrefImplicitLod = 650, // SPIRVInstrInfo.td:423
666 OpImageSparseSampleProjExplicitLod = 651, // SPIRVInstrInfo.td:419
667 OpImageSparseSampleProjImplicitLod = 652, // SPIRVInstrInfo.td:416
668 OpImageSparseTexelsResident = 653, // SPIRVInstrInfo.td:440
669 OpImageTexelPointer = 654, // SPIRVInstrInfo.td:263
670 OpImageWrite = 655, // SPIRVInstrInfo.td:390
671 OpInBoundsAccessChain = 656, // SPIRVInstrInfo.td:276
672 OpInBoundsPtrAccessChain = 657, // SPIRVInstrInfo.td:286
673 OpIsFinite = 658, // SPIRVInstrInfo.td:600
674 OpIsInf = 659, // SPIRVInstrInfo.td:599
675 OpIsNan = 660, // SPIRVInstrInfo.td:598
676 OpIsNormal = 661, // SPIRVInstrInfo.td:601
677 OpIsValidEvent = 662, // SPIRVInstrInfo.td:796
678 OpIsValidReserveId = 663, // SPIRVInstrInfo.td:826
679 OpKill = 664, // SPIRVInstrInfo.td:675
680 OpLabel = 665, // SPIRVInstrInfo.td:667
681 OpLessOrGreater = 666, // SPIRVInstrInfo.td:604
682 OpLifetimeStart = 667, // SPIRVInstrInfo.td:682
683 OpLifetimeStop = 668, // SPIRVInstrInfo.td:683
684 OpLine = 669, // SPIRVInstrInfo.td:121
685 OpLoad = 670, // SPIRVInstrInfo.td:266
686 OpLogicalAnd = 671, // SPIRVInstrInfo.td:611
687 OpLogicalEqual = 672, // SPIRVInstrInfo.td:608
688 OpLogicalNot = 673, // SPIRVInstrInfo.td:612
689 OpLogicalNotEqual = 674, // SPIRVInstrInfo.td:609
690 OpLogicalOr = 675, // SPIRVInstrInfo.td:610
691 OpLoopControlINTEL = 676, // SPIRVInstrInfo.td:663
692 OpLoopMerge = 677, // SPIRVInstrInfo.td:661
693 OpMaskedGatherINTEL = 678, // SPIRVInstrInfo.td:1166
694 OpMaskedScatterINTEL = 679, // SPIRVInstrInfo.td:1168
695 OpMatrixTimesMatrix = 680, // SPIRVInstrInfo.td:542
696 OpMatrixTimesScalar = 681, // SPIRVInstrInfo.td:539
697 OpMatrixTimesVector = 682, // SPIRVInstrInfo.td:541
698 OpMemberDecorate = 683, // SPIRVInstrInfo.td:130
699 OpMemberDecorateString = 684, // SPIRVInstrInfo.td:140
700 OpMemberName = 685, // SPIRVInstrInfo.td:118
701 OpMemoryBarrier = 686, // SPIRVInstrInfo.td:746
702 OpMemoryModel = 687, // SPIRVInstrInfo.td:157
703 OpMemoryNamedBarrier = 688, // SPIRVInstrInfo.td:749
704 OpModuleProcessed = 689, // SPIRVInstrInfo.td:123
705 OpName = 690, // SPIRVInstrInfo.td:117
706 OpNamedBarrierInitialize = 691, // SPIRVInstrInfo.td:748
707 OpNoLine = 692, // SPIRVInstrInfo.td:122
708 OpNop = 693, // SPIRVInstrInfo.td:97
709 OpNot = 694, // SPIRVInstrInfo.td:577
710 OpOrdered = 695, // SPIRVInstrInfo.td:605
711 OpOuterProduct = 696, // SPIRVInstrInfo.td:544
712 OpPhi = 697, // SPIRVInstrInfo.td:659
713 OpPoisonKHR = 698, // SPIRVInstrInfo.td:102
714 OpPredicatedLoadINTEL = 699, // SPIRVInstrInfo.td:1130
715 OpPredicatedStoreINTEL = 700, // SPIRVInstrInfo.td:1132
716 OpPtrAccessChain = 701, // SPIRVInstrInfo.td:279
717 OpPtrCastToCrossWorkgroupINTEL = 702, // SPIRVInstrInfo.td:476
718 OpPtrCastToGeneric = 703, // SPIRVInstrInfo.td:469
719 OpPtrDiff = 704, // SPIRVInstrInfo.td:293
720 OpPtrEqual = 705, // SPIRVInstrInfo.td:289
721 OpPtrNotEqual = 706, // SPIRVInstrInfo.td:291
722 OpQuantizeToF16 = 707, // SPIRVInstrInfo.td:461
723 OpReadClockKHR = 708, // SPIRVInstrInfo.td:897
724 OpReadPipe = 709, // SPIRVInstrInfo.td:810
725 OpReadPipeBlockingALTERA = 710, // SPIRVInstrInfo.td:1136
726 OpReleaseEvent = 711, // SPIRVInstrInfo.td:793
727 OpReserveReadPipePackets = 712, // SPIRVInstrInfo.td:818
728 OpReserveWritePipePackets = 713, // SPIRVInstrInfo.td:820
729 OpReservedReadPipe = 714, // SPIRVInstrInfo.td:814
730 OpReservedWritePipe = 715, // SPIRVInstrInfo.td:816
731 OpRestoreMemoryINTEL = 716, // SPIRVInstrInfo.td:329
732 OpRetainEvent = 717, // SPIRVInstrInfo.td:792
733 OpReturn = 718, // SPIRVInstrInfo.td:676
734 OpReturnValue = 719, // SPIRVInstrInfo.td:677
735 OpRoundFToTF32INTEL = 720, // SPIRVInstrInfo.td:484
736 OpSConvert = 721, // SPIRVInstrInfo.td:458
737 OpSDivS = 722, // SPIRVInstrInfo.td:48
738 OpSDivV = 723, // SPIRVInstrInfo.td:53
739 OpSDot = 724, // SPIRVInstrInfo.td:552
740 OpSDotAccSat = 725, // SPIRVInstrInfo.td:558
741 OpSGreaterThan = 726, // SPIRVInstrInfo.td:620
742 OpSGreaterThanEqual = 727, // SPIRVInstrInfo.td:622
743 OpSLessThan = 728, // SPIRVInstrInfo.td:624
744 OpSLessThanEqual = 729, // SPIRVInstrInfo.td:626
745 OpSMod = 730, // SPIRVInstrInfo.td:531
746 OpSMulExtended = 731, // SPIRVInstrInfo.td:550
747 OpSNegate = 732, // SPIRVInstrInfo.td:508
748 OpSRemS = 733, // SPIRVInstrInfo.td:48
749 OpSRemV = 734, // SPIRVInstrInfo.td:53
750 OpSUDot = 735, // SPIRVInstrInfo.td:556
751 OpSUDotAccSat = 736, // SPIRVInstrInfo.td:562
752 OpSampledImage = 737, // SPIRVInstrInfo.td:347
753 OpSatConvertSToU = 738, // SPIRVInstrInfo.td:465
754 OpSatConvertUToS = 739, // SPIRVInstrInfo.td:466
755 OpSaveMemoryINTEL = 740, // SPIRVInstrInfo.td:327
756 OpSelectSFSCond = 741, // SPIRVInstrInfo.td:67
757 OpSelectSFVCond = 742, // SPIRVInstrInfo.td:68
758 OpSelectSISCond = 743, // SPIRVInstrInfo.td:63
759 OpSelectSIVCond = 744, // SPIRVInstrInfo.td:64
760 OpSelectSPSCond = 745, // SPIRVInstrInfo.td:59
761 OpSelectSPVCond = 746, // SPIRVInstrInfo.td:60
762 OpSelectVFSCond = 747, // SPIRVInstrInfo.td:80
763 OpSelectVFVCond = 748, // SPIRVInstrInfo.td:81
764 OpSelectVISCond = 749, // SPIRVInstrInfo.td:76
765 OpSelectVIVCond = 750, // SPIRVInstrInfo.td:77
766 OpSelectVPSCond = 751, // SPIRVInstrInfo.td:72
767 OpSelectVPVCond = 752, // SPIRVInstrInfo.td:73
768 OpSelectionMerge = 753, // SPIRVInstrInfo.td:665
769 OpSetUserEventStatus = 754, // SPIRVInstrInfo.td:798
770 OpShiftLeftLogicalS = 755, // SPIRVInstrInfo.td:48
771 OpShiftLeftLogicalV = 756, // SPIRVInstrInfo.td:53
772 OpShiftRightArithmeticS = 757, // SPIRVInstrInfo.td:48
773 OpShiftRightArithmeticV = 758, // SPIRVInstrInfo.td:53
774 OpShiftRightLogicalS = 759, // SPIRVInstrInfo.td:48
775 OpShiftRightLogicalV = 760, // SPIRVInstrInfo.td:53
776 OpSignBitSet = 761, // SPIRVInstrInfo.td:602
777 OpSizeOf = 762, // SPIRVInstrInfo.td:99
778 OpSource = 763, // SPIRVInstrInfo.td:113
779 OpSourceContinued = 764, // SPIRVInstrInfo.td:111
780 OpSourceExtension = 765, // SPIRVInstrInfo.td:115
781 OpSpecConstant = 766, // SPIRVInstrInfo.td:248
782 OpSpecConstantComposite = 767, // SPIRVInstrInfo.td:250
783 OpSpecConstantCompositeContinuedINTEL = 768, // SPIRVInstrInfo.td:252
784 OpSpecConstantFalse = 769, // SPIRVInstrInfo.td:247
785 OpSpecConstantOp = 770, // SPIRVInstrInfo.td:256
786 OpSpecConstantTrue = 771, // SPIRVInstrInfo.td:246
787 OpStore = 772, // SPIRVInstrInfo.td:268
788 OpStrictFAddS = 773, // SPIRVInstrInfo.td:46
789 OpStrictFAddV = 774, // SPIRVInstrInfo.td:51
790 OpStrictFDivS = 775, // SPIRVInstrInfo.td:46
791 OpStrictFDivV = 776, // SPIRVInstrInfo.td:51
792 OpStrictFMulS = 777, // SPIRVInstrInfo.td:46
793 OpStrictFMulV = 778, // SPIRVInstrInfo.td:51
794 OpStrictFRemS = 779, // SPIRVInstrInfo.td:46
795 OpStrictFRemV = 780, // SPIRVInstrInfo.td:51
796 OpStrictFSubS = 781, // SPIRVInstrInfo.td:46
797 OpStrictFSubV = 782, // SPIRVInstrInfo.td:51
798 OpString = 783, // SPIRVInstrInfo.td:120
799 OpSubgroup2DBlockLoadINTEL = 784, // SPIRVInstrInfo.td:1113
800 OpSubgroup2DBlockLoadTransformINTEL = 785, // SPIRVInstrInfo.td:1119
801 OpSubgroup2DBlockLoadTransposeINTEL = 786, // SPIRVInstrInfo.td:1116
802 OpSubgroup2DBlockPrefetchINTEL = 787, // SPIRVInstrInfo.td:1122
803 OpSubgroup2DBlockStoreINTEL = 788, // SPIRVInstrInfo.td:1125
804 OpSubgroupBlockReadINTEL = 789, // SPIRVInstrInfo.td:922
805 OpSubgroupBlockWriteINTEL = 790, // SPIRVInstrInfo.td:924
806 OpSubgroupImageBlockReadINTEL = 791, // SPIRVInstrInfo.td:926
807 OpSubgroupImageBlockWriteINTEL = 792, // SPIRVInstrInfo.td:928
808 OpSubgroupImageMediaBlockReadINTEL = 793, // SPIRVInstrInfo.td:932
809 OpSubgroupImageMediaBlockWriteINTEL = 794, // SPIRVInstrInfo.td:934
810 OpSubgroupMatrixMultiplyAccumulateINTEL = 795, // SPIRVInstrInfo.td:784
811 OpSubgroupShuffleDownINTEL = 796, // SPIRVInstrInfo.td:916
812 OpSubgroupShuffleINTEL = 797, // SPIRVInstrInfo.td:914
813 OpSubgroupShuffleUpINTEL = 798, // SPIRVInstrInfo.td:918
814 OpSubgroupShuffleXorINTEL = 799, // SPIRVInstrInfo.td:920
815 OpSwitch = 800, // SPIRVInstrInfo.td:672
816 OpTranspose = 801, // SPIRVInstrInfo.td:503
817 OpTypeAccelerationStructureNV = 802, // SPIRVInstrInfo.td:208
818 OpTypeArray = 803, // SPIRVInstrInfo.td:186
819 OpTypeBool = 804, // SPIRVInstrInfo.td:171
820 OpTypeCooperativeMatrixKHR = 805, // SPIRVInstrInfo.td:213
821 OpTypeCooperativeMatrixNV = 806, // SPIRVInstrInfo.td:210
822 OpTypeDeviceEvent = 807, // SPIRVInstrInfo.td:200
823 OpTypeEvent = 808, // SPIRVInstrInfo.td:199
824 OpTypeFloat = 809, // SPIRVInstrInfo.td:174
825 OpTypeForwardPointer = 810, // SPIRVInstrInfo.td:204
826 OpTypeFunction = 811, // SPIRVInstrInfo.td:197
827 OpTypeImage = 812, // SPIRVInstrInfo.td:180
828 OpTypeInt = 813, // SPIRVInstrInfo.td:172
829 OpTypeMatrix = 814, // SPIRVInstrInfo.td:178
830 OpTypeNamedBarrier = 815, // SPIRVInstrInfo.td:207
831 OpTypeOpaque = 816, // SPIRVInstrInfo.td:193
832 OpTypePipe = 817, // SPIRVInstrInfo.td:203
833 OpTypePipeStorage = 818, // SPIRVInstrInfo.td:206
834 OpTypePointer = 819, // SPIRVInstrInfo.td:195
835 OpTypeQueue = 820, // SPIRVInstrInfo.td:202
836 OpTypeReserveId = 821, // SPIRVInstrInfo.td:201
837 OpTypeRuntimeArray = 822, // SPIRVInstrInfo.td:188
838 OpTypeSampledImage = 823, // SPIRVInstrInfo.td:184
839 OpTypeSampler = 824, // SPIRVInstrInfo.td:183
840 OpTypeStruct = 825, // SPIRVInstrInfo.td:190
841 OpTypeStructContinuedINTEL = 826, // SPIRVInstrInfo.td:191
842 OpTypeUntypedPointerKHR = 827, // SPIRVInstrInfo.td:298
843 OpTypeVector = 828, // SPIRVInstrInfo.td:176
844 OpTypeVectorIdEXT = 829, // SPIRVInstrInfo.td:216
845 OpTypeVoid = 830, // SPIRVInstrInfo.td:170
846 OpUConvert = 831, // SPIRVInstrInfo.td:457
847 OpUDivS = 832, // SPIRVInstrInfo.td:48
848 OpUDivV = 833, // SPIRVInstrInfo.td:53
849 OpUDot = 834, // SPIRVInstrInfo.td:554
850 OpUDotAccSat = 835, // SPIRVInstrInfo.td:560
851 OpUGreaterThan = 836, // SPIRVInstrInfo.td:619
852 OpUGreaterThanEqual = 837, // SPIRVInstrInfo.td:621
853 OpULessThan = 838, // SPIRVInstrInfo.td:623
854 OpULessThanEqual = 839, // SPIRVInstrInfo.td:625
855 OpUModS = 840, // SPIRVInstrInfo.td:48
856 OpUModV = 841, // SPIRVInstrInfo.td:53
857 OpUMulExtended = 842, // SPIRVInstrInfo.td:549
858 OpUndef = 843, // SPIRVInstrInfo.td:98
859 OpUnordered = 844, // SPIRVInstrInfo.td:606
860 OpUnreachable = 845, // SPIRVInstrInfo.td:678
861 OpUntypedAccessChainKHR = 846, // SPIRVInstrInfo.td:303
862 OpUntypedGroupAsyncCopyKHR = 847, // SPIRVInstrInfo.td:318
863 OpUntypedInBoundsAccessChainKHR = 848, // SPIRVInstrInfo.td:306
864 OpUntypedInBoundsPtrAccessChainKHR = 849, // SPIRVInstrInfo.td:312
865 OpUntypedPrefetchKHR = 850, // SPIRVInstrInfo.td:315
866 OpUntypedPtrAccessChainKHR = 851, // SPIRVInstrInfo.td:309
867 OpUntypedVariableKHR = 852, // SPIRVInstrInfo.td:300
868 OpVariable = 853, // SPIRVInstrInfo.td:261
869 OpVariableLengthArrayINTEL = 854, // SPIRVInstrInfo.td:325
870 OpVectorExtractDynamic = 855, // SPIRVInstrInfo.td:488
871 OpVectorInsertDynamic = 856, // SPIRVInstrInfo.td:490
872 OpVectorShuffle = 857, // SPIRVInstrInfo.td:492
873 OpVectorTimesMatrix = 858, // SPIRVInstrInfo.td:540
874 OpVectorTimesScalar = 859, // SPIRVInstrInfo.td:538
875 OpWritePipe = 860, // SPIRVInstrInfo.td:812
876 OpWritePipeBlockingALTERA = 861, // SPIRVInstrInfo.td:1138
877 INSTRUCTION_LIST_END = 862
878 };
879
880} // namespace llvm::SPIRV
881
882#endif // GET_INSTRINFO_ENUM
883
884#ifdef GET_INSTRINFO_SCHED_ENUM
885#undef GET_INSTRINFO_SCHED_ENUM
886
887namespace llvm::SPIRV::Sched {
888
889 enum {
890 NoInstrModel = 0,
891 SCHED_LIST_END = 1
892 };
893
894} // namespace llvm::SPIRV::Sched
895
896#endif // GET_INSTRINFO_SCHED_ENUM
897
898#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
899
900namespace llvm {
901
902struct SPIRVInstrTable {
903 MCInstrDesc Insts[862];
904 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
905 MCPhysReg ImplicitOps[1];
906 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
907 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
908 MCOperandInfo OperandInfo[499];
909};
910} // namespace llvm
911
912#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
913
914#ifdef GET_INSTRINFO_MC_DESC
915#undef GET_INSTRINFO_MC_DESC
916
917namespace llvm {
918
919static_assert((sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
920static constexpr unsigned SPIRVOpInfoBase = (sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) / sizeof(MCOperandInfo);
921
922extern const SPIRVInstrTable SPIRVDescs = {
923 {
924 { 861, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipeBlockingALTERA
925 { 860, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipe
926 { 859, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesScalar
927 { 858, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesMatrix
928 { 857, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorShuffle
929 { 856, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorInsertDynamic
930 { 855, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorExtractDynamic
931 { 854, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariableLengthArrayINTEL
932 { 853, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 496, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariable
933 { 852, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 313, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedVariableKHR
934 { 851, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 491, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedPtrAccessChainKHR
935 { 850, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedPrefetchKHR
936 { 849, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 491, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedInBoundsPtrAccessChainKHR
937 { 848, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedInBoundsAccessChainKHR
938 { 847, 9, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 482, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedGroupAsyncCopyKHR
939 { 846, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedAccessChainKHR
940 { 845, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnreachable
941 { 844, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnordered
942 { 843, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUndef
943 { 842, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUMulExtended
944 { 841, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModV
945 { 840, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModS
946 { 839, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThanEqual
947 { 838, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThan
948 { 837, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThanEqual
949 { 836, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThan
950 { 835, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDotAccSat
951 { 834, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDot
952 { 833, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivV
953 { 832, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivS
954 { 831, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUConvert
955 { 830, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVoid
956 { 829, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 443, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVectorIdEXT
957 { 828, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 472, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVector
958 { 827, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeUntypedPointerKHR
959 { 826, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStructContinuedINTEL
960 { 825, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStruct
961 { 824, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampler
962 { 823, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampledImage
963 { 822, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeRuntimeArray
964 { 821, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeReserveId
965 { 820, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeQueue
966 { 819, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 475, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePointer
967 { 818, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipeStorage
968 { 817, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipe
969 { 816, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeOpaque
970 { 815, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeNamedBarrier
971 { 814, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 472, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeMatrix
972 { 813, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 469, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeInt
973 { 812, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 461, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeImage
974 { 811, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFunction
975 { 810, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeForwardPointer
976 { 809, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFloat
977 { 808, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeEvent
978 { 807, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeDeviceEvent
979 { 806, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 452, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixNV
980 { 805, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixKHR
981 { 804, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeBool
982 { 803, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 443, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeArray
983 { 802, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeAccelerationStructureNV
984 { 801, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTranspose
985 { 800, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSwitch
986 { 799, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleXorINTEL
987 { 798, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleUpINTEL
988 { 797, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleINTEL
989 { 796, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleDownINTEL
990 { 795, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupMatrixMultiplyAccumulateINTEL
991 { 794, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockWriteINTEL
992 { 793, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockReadINTEL
993 { 792, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockWriteINTEL
994 { 791, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockReadINTEL
995 { 790, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockWriteINTEL
996 { 789, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockReadINTEL
997 { 788, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockStoreINTEL
998 { 787, 9, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 433, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockPrefetchINTEL
999 { 786, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransposeINTEL
1000 { 785, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransformINTEL
1001 { 784, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadINTEL
1002 { 783, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpString
1003 { 782, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubV
1004 { 781, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubS
1005 { 780, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemV
1006 { 779, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemS
1007 { 778, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulV
1008 { 777, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulS
1009 { 776, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivV
1010 { 775, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivS
1011 { 774, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddV
1012 { 773, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddS
1013 { 772, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStore
1014 { 771, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantTrue
1015 { 770, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 419, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantOp
1016 { 769, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantFalse
1017 { 768, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantCompositeContinuedINTEL
1018 { 767, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantComposite
1019 { 766, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 416, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstant
1020 { 765, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceExtension
1021 { 764, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceContinued
1022 { 763, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSource
1023 { 762, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSizeOf
1024 { 761, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSignBitSet
1025 { 760, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalV
1026 { 759, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalS
1027 { 758, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticV
1028 { 757, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticS
1029 { 756, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalV
1030 { 755, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalS
1031 { 754, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSetUserEventStatus
1032 { 753, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectionMerge
1033 { 752, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 411, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPVCond
1034 { 751, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 406, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPSCond
1035 { 750, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 401, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVIVCond
1036 { 749, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 396, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVISCond
1037 { 748, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 391, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFVCond
1038 { 747, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 386, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFSCond
1039 { 746, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 381, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPVCond
1040 { 745, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 376, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPSCond
1041 { 744, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 371, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSIVCond
1042 { 743, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 366, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSISCond
1043 { 742, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 361, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFVCond
1044 { 741, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 356, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFSCond
1045 { 740, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSaveMemoryINTEL
1046 { 739, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertUToS
1047 { 738, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertSToU
1048 { 737, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSampledImage
1049 { 736, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDotAccSat
1050 { 735, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDot
1051 { 734, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemV
1052 { 733, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemS
1053 { 732, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSNegate
1054 { 731, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMulExtended
1055 { 730, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMod
1056 { 729, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThanEqual
1057 { 728, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThan
1058 { 727, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThanEqual
1059 { 726, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThan
1060 { 725, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDotAccSat
1061 { 724, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDot
1062 { 723, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivV
1063 { 722, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivS
1064 { 721, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSConvert
1065 { 720, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRoundFToTF32INTEL
1066 { 719, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturnValue
1067 { 718, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturn
1068 { 717, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRetainEvent
1069 { 716, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRestoreMemoryINTEL
1070 { 715, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedWritePipe
1071 { 714, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedReadPipe
1072 { 713, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveWritePipePackets
1073 { 712, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveReadPipePackets
1074 { 711, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReleaseEvent
1075 { 710, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipeBlockingALTERA
1076 { 709, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipe
1077 { 708, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadClockKHR
1078 { 707, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpQuantizeToF16
1079 { 706, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrNotEqual
1080 { 705, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrEqual
1081 { 704, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrDiff
1082 { 703, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToGeneric
1083 { 702, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToCrossWorkgroupINTEL
1084 { 701, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrAccessChain
1085 { 700, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedStoreINTEL
1086 { 699, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedLoadINTEL
1087 { 698, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPoisonKHR
1088 { 697, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPhi
1089 { 696, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOuterProduct
1090 { 695, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOrdered
1091 { 694, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNot
1092 { 693, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNop
1093 { 692, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNoLine
1094 { 691, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNamedBarrierInitialize
1095 { 690, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpName
1096 { 689, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpModuleProcessed
1097 { 688, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryNamedBarrier
1098 { 687, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryModel
1099 { 686, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryBarrier
1100 { 685, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberName
1101 { 684, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 352, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorateString
1102 { 683, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorate
1103 { 682, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesVector
1104 { 681, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesScalar
1105 { 680, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesMatrix
1106 { 679, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedScatterINTEL
1107 { 678, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedGatherINTEL
1108 { 677, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopMerge
1109 { 676, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopControlINTEL
1110 { 675, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalOr
1111 { 674, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNotEqual
1112 { 673, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNot
1113 { 672, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalEqual
1114 { 671, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalAnd
1115 { 670, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoad
1116 { 669, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 346, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLine
1117 { 668, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 344, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStop
1118 { 667, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 344, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStart
1119 { 666, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLessOrGreater
1120 { 665, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLabel
1121 { 664, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpKill
1122 { 663, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidReserveId
1123 { 662, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidEvent
1124 { 661, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNormal
1125 { 660, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNan
1126 { 659, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsInf
1127 { 658, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsFinite
1128 { 657, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsPtrAccessChain
1129 { 656, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsAccessChain
1130 { 655, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageWrite
1131 { 654, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageTexelPointer
1132 { 653, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseTexelsResident
1133 { 652, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjImplicitLod
1134 { 651, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjExplicitLod
1135 { 650, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefImplicitLod
1136 { 649, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefExplicitLod
1137 { 648, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleImplicitLod
1138 { 647, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 338, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleExplicitLod
1139 { 646, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefImplicitLod
1140 { 645, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefExplicitLod
1141 { 644, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseRead
1142 { 643, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseGather
1143 { 642, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseFetch
1144 { 641, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseDrefGather
1145 { 640, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjImplicitLod
1146 { 639, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjExplicitLod
1147 { 638, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefImplicitLod
1148 { 637, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefExplicitLod
1149 { 636, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleImplicitLod
1150 { 635, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleFootprintNV
1151 { 634, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 338, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleExplicitLod
1152 { 633, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefImplicitLod
1153 { 632, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefExplicitLod
1154 { 631, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageRead
1155 { 630, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySizeLod
1156 { 629, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySize
1157 { 628, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySamples
1158 { 627, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryOrder
1159 { 626, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLod
1160 { 625, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLevels
1161 { 624, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryFormat
1162 { 623, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageGather
1163 { 622, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageFetch
1164 { 621, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageDrefGather
1165 { 620, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImage
1166 { 619, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubV
1167 { 618, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubS
1168 { 617, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowV
1169 { 616, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowS
1170 { 615, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpINotEqual
1171 { 614, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulV
1172 { 613, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulS
1173 { 612, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIEqual
1174 { 611, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddV
1175 { 610, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddS
1176 { 609, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryV
1177 { 608, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryS
1178 { 607, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupWaitEvents
1179 { 606, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMin
1180 { 605, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMax
1181 { 604, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMin
1182 { 603, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMax
1183 { 602, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveWritePipePackets
1184 { 601, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveReadPipePackets
1185 { 600, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMin
1186 { 599, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMax
1187 { 598, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleXor
1188 { 597, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleUp
1189 { 596, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleDown
1190 { 595, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffle
1191 { 594, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMin
1192 { 593, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMax
1193 { 592, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformRotateKHR
1194 { 591, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformQuadSwap
1195 { 590, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalXor
1196 { 589, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalOr
1197 { 588, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalAnd
1198 { 587, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformInverseBallot
1199 { 586, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIMul
1200 { 585, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIAdd
1201 { 584, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMul
1202 { 583, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMin
1203 { 582, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMax
1204 { 581, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFAdd
1205 { 580, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformElect
1206 { 579, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcastFirst
1207 { 578, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcast
1208 { 577, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseXor
1209 { 576, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseOr
1210 { 575, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseAnd
1211 { 574, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindMSB
1212 { 573, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindLSB
1213 { 572, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitExtract
1214 { 571, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitCount
1215 { 570, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallot
1216 { 569, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAny
1217 { 568, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAllEqual
1218 { 567, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAll
1219 { 566, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalXorKHR
1220 { 565, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalOrKHR
1221 { 564, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalAndKHR
1222 { 563, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIMulKHR
1223 { 562, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIAdd
1224 { 561, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMulKHR
1225 { 560, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMin
1226 { 559, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMax
1227 { 558, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFAdd
1228 { 557, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitWritePipe
1229 { 556, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitReadPipe
1230 { 555, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBroadcast
1231 { 554, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseXorKHR
1232 { 553, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseOrKHR
1233 { 552, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseAndKHR
1234 { 551, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAsyncCopy
1235 { 550, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAny
1236 { 549, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAll
1237 { 548, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetNumPipePackets
1238 { 547, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetMaxPipePackets
1239 { 546, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetDefaultQueue
1240 { 545, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericPtrMemSemantics
1241 { 544, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 317, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtrExplicit
1242 { 543, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtr
1243 { 542, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthFine
1244 { 541, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthCoarse
1245 { 540, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidth
1246 { 539, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionPointerCallINTEL
1247 { 538, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionParameter
1248 { 537, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionEnd
1249 { 536, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionCall
1250 { 535, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 313, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunction
1251 { 534, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFreezeKHR
1252 { 533, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFmaKHR
1253 { 532, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSqrtALTERA
1254 { 531, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinPiALTERA
1255 { 530, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosPiALTERA
1256 { 529, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosALTERA
1257 { 528, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinALTERA
1258 { 527, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRsqrtALTERA
1259 { 526, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRecipALTERA
1260 { 525, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedLogALTERA
1261 { 524, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedExpALTERA
1262 { 523, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosPiALTERA
1263 { 522, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosALTERA
1264 { 521, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordNotEqual
1265 { 520, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThanEqual
1266 { 519, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThan
1267 { 518, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThanEqual
1268 { 517, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThan
1269 { 516, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordEqual
1270 { 515, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubV
1271 { 514, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubS
1272 { 513, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemV
1273 { 512, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemS
1274 { 511, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdNotEqual
1275 { 510, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThanEqual
1276 { 509, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThan
1277 { 508, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThanEqual
1278 { 507, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThan
1279 { 506, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdEqual
1280 { 505, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 310, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegateV
1281 { 504, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegate
1282 { 503, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulV
1283 { 502, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulS
1284 { 501, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMod
1285 { 500, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivV
1286 { 499, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivS
1287 { 498, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFConvert
1288 { 497, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddV
1289 { 496, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddS
1290 { 495, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtension
1291 { 494, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInstImport
1292 { 493, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 298, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInst
1293 { 492, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExpectKHR
1294 { 491, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionModeId
1295 { 490, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionMode
1296 { 489, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 295, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEntryPoint
1297 { 488, 12, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 283, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEnqueueKernel
1298 { 487, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndStreamPrimitive
1299 { 486, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndPrimitive
1300 { 485, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitVertex
1301 { 484, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitStreamVertex
1302 { 483, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDot
1303 { 482, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDemoteToHelperInvocation
1304 { 481, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 280, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateString
1305 { 480, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateId
1306 { 479, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorate
1307 { 478, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyFine
1308 { 477, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyCoarse
1309 { 476, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdy
1310 { 475, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxFine
1311 { 474, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxCoarse
1312 { 473, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdx
1313 { 472, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCrossWorkgroupCastToPtrINTEL
1314 { 471, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCreateUserEvent
1315 { 470, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyObject
1316 { 469, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemorySized
1317 { 468, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemory
1318 { 467, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyLogical
1319 { 466, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreKHR
1320 { 465, 7, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 271, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreCheckedINTEL
1321 { 464, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 266, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixPrefetchINTEL
1322 { 463, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixMulAddKHR
1323 { 462, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadKHR
1324 { 461, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadCheckedINTEL
1325 { 460, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 263, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLengthKHR
1326 { 459, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixGetElementCoordINTEL
1327 { 458, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixConstructCheckedINTEL
1328 { 457, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToPtr
1329 { 456, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToF
1330 { 455, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertSToF
1331 { 454, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertPtrToU
1332 { 453, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSamplerINTEL
1333 { 452, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSampledImageINTEL
1334 { 451, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToImageINTEL
1335 { 450, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToU
1336 { 449, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToS
1337 { 448, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToBF16INTEL
1338 { 447, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertBF16ToFINTEL
1339 { 446, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierWaitINTEL
1340 { 445, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierArriveINTEL
1341 { 444, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrier
1342 { 443, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantTrue
1343 { 442, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantSampler
1344 { 441, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantNull
1345 { 440, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 248, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantI
1346 { 439, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFunctionPointerINTEL
1347 { 438, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFalse
1348 { 437, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantF
1349 { 436, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantCompositeContinuedINTEL
1350 { 435, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantComposite
1351 { 434, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeInsert
1352 { 433, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeExtract
1353 { 432, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstructContinuedINTEL
1354 { 431, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstruct
1355 { 430, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitWritePipe
1356 { 429, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitReadPipe
1357 { 428, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCaptureEventProfilingInfo
1358 { 427, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCapability
1359 { 426, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBuildNDRange
1360 { 425, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 234, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranchConditional
1361 { 424, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranch
1362 { 423, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorV
1363 { 422, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorS
1364 { 421, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrV
1365 { 420, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrS
1366 { 419, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseFunctionINTEL
1367 { 418, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndV
1368 { 417, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndS
1369 { 416, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitcast
1370 { 415, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitReverse
1371 { 414, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldUExtract
1372 { 413, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldSExtract
1373 { 412, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldInsert
1374 { 411, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitCount
1375 { 410, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicXor
1376 { 409, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMin
1377 { 408, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMax
1378 { 407, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicStore
1379 { 406, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMin
1380 { 405, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMax
1381 { 404, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicOr
1382 { 403, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicLoad
1383 { 402, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicISub
1384 { 401, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIIncrement
1385 { 400, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIDecrement
1386 { 399, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIAdd
1387 { 398, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagTestAndSet
1388 { 397, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagClear
1389 { 396, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMinEXT
1390 { 395, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMaxEXT
1391 { 394, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFAddEXT
1392 { 393, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicExchange
1393 { 392, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchangeWeak
1394 { 391, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchange
1395 { 390, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicAnd
1396 { 389, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAssumeTrueKHR
1397 { 388, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmTargetINTEL
1398 { 387, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 192, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmINTEL
1399 { 386, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmCallINTEL
1400 { 385, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 188, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArrayLength
1401 { 384, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArithmeticFenceEXT
1402 { 383, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSubALTERA
1403 { 382, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSqrtALTERA
1404 { 381, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinPiALTERA
1405 { 380, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosPiALTERA
1406 { 379, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosALTERA
1407 { 378, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinALTERA
1408 { 377, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRecipALTERA
1409 { 376, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRSqrtALTERA
1410 { 375, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowRALTERA
1411 { 374, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowNALTERA
1412 { 373, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowALTERA
1413 { 372, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatMulALTERA
1414 { 371, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLogALTERA
1415 { 370, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog2ALTERA
1416 { 369, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog1pALTERA
1417 { 368, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog10ALTERA
1418 { 367, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLTALTERA
1419 { 366, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLEALTERA
1420 { 365, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatHypotALTERA
1421 { 364, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGTALTERA
1422 { 363, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGEALTERA
1423 { 362, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpm1ALTERA
1424 { 361, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpALTERA
1425 { 360, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp2ALTERA
1426 { 359, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp10ALTERA
1427 { 358, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatEQALTERA
1428 { 357, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatDivALTERA
1429 { 356, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosPiALTERA
1430 { 355, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosALTERA
1431 { 354, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCbrtALTERA
1432 { 353, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastToIntALTERA
1433 { 352, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastFromIntALTERA
1434 { 351, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastALTERA
1435 { 350, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatAddALTERA
1436 { 349, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanPiALTERA
1437 { 348, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanALTERA
1438 { 347, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATan2ALTERA
1439 { 346, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinPiALTERA
1440 { 345, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinALTERA
1441 { 344, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosPiALTERA
1442 { 343, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosALTERA
1443 { 342, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAny
1444 { 341, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAll
1445 { 340, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeListDeclINTEL
1446 { 339, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeDeclINTEL
1447 { 338, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasDomainDeclINTEL
1448 { 337, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAccessChain
1449 { 336, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAbortKHR
1450 { 335, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNKNOWN_type
1451 { 334, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASSIGN_TYPE
1452 { 333, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1453 { 332, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1454 { 331, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1455 { 330, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1456 { 329, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1457 { 328, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1458 { 327, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1459 { 326, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1460 { 325, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1461 { 324, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1462 { 323, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1463 { 322, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1464 { 321, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1465 { 320, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1466 { 319, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1467 { 318, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1468 { 317, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1469 { 316, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1470 { 315, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1471 { 314, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1472 { 313, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1473 { 312, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1474 { 311, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1475 { 310, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1476 { 309, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
1477 { 308, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1478 { 307, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1479 { 306, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1480 { 305, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1481 { 304, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1482 { 303, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1483 { 302, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1484 { 301, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
1485 { 300, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
1486 { 299, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1487 { 298, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1488 { 297, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1489 { 296, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1490 { 295, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1491 { 294, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1492 { 293, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1493 { 292, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1494 { 291, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1495 { 290, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1496 { 289, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1497 { 288, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1498 { 287, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1499 { 286, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1500 { 285, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1501 { 284, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1502 { 283, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1503 { 282, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1504 { 281, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1505 { 280, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1506 { 279, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1507 { 278, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1508 { 277, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1509 { 276, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1510 { 275, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1511 { 274, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1512 { 273, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1513 { 272, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1514 { 271, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1515 { 270, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1516 { 269, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
1517 { 268, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
1518 { 267, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1519 { 266, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1520 { 265, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1521 { 264, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1522 { 263, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
1523 { 262, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1524 { 261, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
1525 { 260, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1526 { 259, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1527 { 258, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1528 { 257, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1529 { 256, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1530 { 255, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1531 { 254, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1532 { 253, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1533 { 252, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1534 { 251, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1535 { 250, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1536 { 249, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1537 { 248, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1538 { 247, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1539 { 246, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1540 { 245, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1541 { 244, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1542 { 243, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1543 { 242, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1544 { 241, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1545 { 240, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1546 { 239, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1547 { 238, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1548 { 237, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1549 { 236, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1550 { 235, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1551 { 234, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1552 { 233, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1553 { 232, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1554 { 231, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1555 { 230, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1556 { 229, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1557 { 228, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1558 { 227, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1559 { 226, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1560 { 225, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1561 { 224, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1562 { 223, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1563 { 222, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1564 { 221, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1565 { 220, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1566 { 219, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1567 { 218, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1568 { 217, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1569 { 216, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1570 { 215, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1571 { 214, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1572 { 213, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1573 { 212, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1574 { 211, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1575 { 210, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1576 { 209, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1577 { 208, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1578 { 207, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1579 { 206, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1580 { 205, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1581 { 204, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1582 { 203, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1583 { 202, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1584 { 201, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1585 { 200, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1586 { 199, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1587 { 198, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1588 { 197, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1589 { 196, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1590 { 195, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1591 { 194, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1592 { 193, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1593 { 192, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1594 { 191, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1595 { 190, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1596 { 189, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1597 { 188, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1598 { 187, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1599 { 186, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1600 { 185, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1601 { 184, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1602 { 183, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1603 { 182, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1604 { 181, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1605 { 180, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1606 { 179, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1607 { 178, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1608 { 177, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1609 { 176, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1610 { 175, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1611 { 174, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1612 { 173, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1613 { 172, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1614 { 171, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1615 { 170, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1616 { 169, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1617 { 168, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1618 { 167, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1619 { 166, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1620 { 165, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1621 { 164, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1622 { 163, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1623 { 162, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1624 { 161, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1625 { 160, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1626 { 159, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1627 { 158, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1628 { 157, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1629 { 156, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1630 { 155, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1631 { 154, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1632 { 153, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1633 { 152, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1634 { 151, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1635 { 150, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1636 { 149, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1637 { 148, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1638 { 147, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1639 { 146, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1640 { 145, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1641 { 144, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1642 { 143, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1643 { 142, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1644 { 141, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1645 { 140, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1646 { 139, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1647 { 138, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1648 { 137, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1649 { 136, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1650 { 135, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1651 { 134, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1652 { 133, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1653 { 132, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1654 { 131, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1655 { 130, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1656 { 129, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1657 { 128, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1658 { 127, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1659 { 126, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1660 { 125, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1661 { 124, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1662 { 123, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1663 { 122, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1664 { 121, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1665 { 120, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1666 { 119, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1667 { 118, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1668 { 117, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1669 { 116, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1670 { 115, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1671 { 114, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1672 { 113, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1673 { 112, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1674 { 111, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1675 { 110, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1676 { 109, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1677 { 108, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1678 { 107, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1679 { 106, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1680 { 105, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1681 { 104, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1682 { 103, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1683 { 102, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1684 { 101, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1685 { 100, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1686 { 99, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1687 { 98, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1688 { 97, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1689 { 96, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1690 { 95, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1691 { 94, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1692 { 93, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1693 { 92, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1694 { 91, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1695 { 90, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1696 { 89, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1697 { 88, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1698 { 87, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1699 { 86, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1700 { 85, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1701 { 84, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1702 { 83, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1703 { 82, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1704 { 81, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1705 { 80, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1706 { 79, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1707 { 78, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1708 { 77, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1709 { 76, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1710 { 75, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1711 { 74, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1712 { 73, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1713 { 72, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1714 { 71, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1715 { 70, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1716 { 69, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1717 { 68, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1718 { 67, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1719 { 66, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1720 { 65, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1721 { 64, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1722 { 63, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1723 { 62, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1724 { 61, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1725 { 60, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1726 { 59, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1727 { 58, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1728 { 57, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1729 { 56, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1730 { 55, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1731 { 54, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1732 { 53, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1733 { 52, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1734 { 51, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1735 { 50, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1736 { 49, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1737 { 48, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1738 { 47, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1739 { 46, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1740 { 45, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1741 { 44, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1742 { 43, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1743 { 42, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21860
1744 { 41, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21859
1745 { 40, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1746 { 39, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1747 { 38, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1748 { 37, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1749 { 36, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1750 { 35, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1751 { 34, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1752 { 33, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1753 { 32, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21858
1754 { 31, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1755 { 30, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14348
1756 { 29, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1757 { 28, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1758 { 27, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1759 { 26, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1760 { 25, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1761 { 24, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1762 { 23, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1763 { 22, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1764 { 21, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1765 { 20, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1766 { 19, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1767 { 18, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1768 { 17, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1769 { 16, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1770 { 15, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1771 { 14, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1772 { 13, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1773 { 12, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1774 { 11, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1775 { 10, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1776 { 9, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1777 { 8, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1778 { 7, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1779 { 6, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1780 { 5, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1781 { 4, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1782 { 3, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1783 { 2, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1784 { 1, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1785 { 0, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1786 }, {
1787 /* 0 */
1788 }, {
1789 0
1790 }, {
1791 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1792 /* 1 */
1793 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1794 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1795 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1796 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1797 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1798 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1799 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1800 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1801 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1802 /* 28 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1803 /* 29 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1804 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1805 /* 34 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1806 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1807 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1808 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1809 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1810 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1811 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1812 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1813 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1814 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1815 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1816 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1817 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1818 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1819 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1820 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1821 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1822 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1823 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1824 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1825 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1826 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1827 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1828 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1829 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1830 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1831 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1832 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1833 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1834 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1835 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1836 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1837 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1838 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1839 /* 151 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1840 /* 154 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1841 /* 156 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1842 /* 158 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1843 /* 161 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1844 /* 162 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1845 /* 164 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1846 /* 172 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1847 /* 182 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1848 /* 188 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1849 /* 192 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1850 /* 198 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1851 /* 200 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1852 /* 206 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1853 /* 214 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1854 /* 217 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1855 /* 222 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1856 /* 226 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1857 /* 230 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1858 /* 234 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1859 /* 237 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1860 /* 239 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1861 /* 243 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1862 /* 246 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1863 /* 248 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1864 /* 251 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1865 /* 256 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1866 /* 263 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1867 /* 266 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1868 /* 271 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1869 /* 278 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1870 /* 280 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1871 /* 283 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1872 /* 295 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1873 /* 298 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1874 /* 302 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1875 /* 306 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1876 /* 310 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1877 /* 313 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1878 /* 317 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1879 /* 321 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1880 /* 326 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1881 /* 331 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1882 /* 338 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1883 /* 344 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1884 /* 346 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1885 /* 349 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1886 /* 352 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1887 /* 356 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1888 /* 361 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1889 /* 366 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1890 /* 371 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1891 /* 376 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1892 /* 381 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1893 /* 386 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1894 /* 391 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1895 /* 396 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1896 /* 401 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1897 /* 406 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1898 /* 411 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1899 /* 416 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1900 /* 419 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1901 /* 423 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1902 /* 433 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1903 /* 442 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1904 /* 443 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1905 /* 446 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1906 /* 452 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1907 /* 457 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1908 /* 459 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1909 /* 461 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1910 /* 469 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1911 /* 472 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1912 /* 475 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1913 /* 478 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1914 /* 482 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1915 /* 491 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1916 /* 496 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1917 }
1918};
1919
1920
1921#ifdef __GNUC__
1922#pragma GCC diagnostic push
1923#pragma GCC diagnostic ignored "-Woverlength-strings"
1924#endif
1925extern const char SPIRVInstrNameData[] = {
1926 /* 0 */ "G_FLOG10\000"
1927 /* 9 */ "G_FEXP10\000"
1928 /* 18 */ "G_FLOG2\000"
1929 /* 26 */ "G_FATAN2\000"
1930 /* 35 */ "G_FEXP2\000"
1931 /* 43 */ "OpQuantizeToF16\000"
1932 /* 59 */ "G_FMA\000"
1933 /* 65 */ "G_STRICT_FMA\000"
1934 /* 78 */ "OpArbitraryFloatLog10ALTERA\000"
1935 /* 106 */ "OpArbitraryFloatExp10ALTERA\000"
1936 /* 134 */ "OpArbitraryFloatExpm1ALTERA\000"
1937 /* 162 */ "OpArbitraryFloatLog2ALTERA\000"
1938 /* 189 */ "OpArbitraryFloatATan2ALTERA\000"
1939 /* 217 */ "OpArbitraryFloatExp2ALTERA\000"
1940 /* 244 */ "OpArbitraryFloatGEALTERA\000"
1941 /* 269 */ "OpArbitraryFloatLEALTERA\000"
1942 /* 294 */ "OpArbitraryFloatPowNALTERA\000"
1943 /* 321 */ "OpArbitraryFloatEQALTERA\000"
1944 /* 346 */ "OpArbitraryFloatPowRALTERA\000"
1945 /* 373 */ "OpArbitraryFloatGTALTERA\000"
1946 /* 398 */ "OpArbitraryFloatLTALTERA\000"
1947 /* 423 */ "OpArbitraryFloatSubALTERA\000"
1948 /* 449 */ "OpArbitraryFloatAddALTERA\000"
1949 /* 475 */ "OpReadPipeBlockingALTERA\000"
1950 /* 500 */ "OpWritePipeBlockingALTERA\000"
1951 /* 526 */ "OpFixedLogALTERA\000"
1952 /* 543 */ "OpArbitraryFloatLogALTERA\000"
1953 /* 569 */ "OpArbitraryFloatATanPiALTERA\000"
1954 /* 598 */ "OpArbitraryFloatASinPiALTERA\000"
1955 /* 627 */ "OpFixedSinPiALTERA\000"
1956 /* 646 */ "OpArbitraryFloatSinPiALTERA\000"
1957 /* 674 */ "OpArbitraryFloatACosPiALTERA\000"
1958 /* 703 */ "OpFixedCosPiALTERA\000"
1959 /* 722 */ "OpFixedSinCosPiALTERA\000"
1960 /* 744 */ "OpArbitraryFloatSinCosPiALTERA\000"
1961 /* 775 */ "OpArbitraryFloatCosPiALTERA\000"
1962 /* 803 */ "OpArbitraryFloatMulALTERA\000"
1963 /* 829 */ "OpArbitraryFloatATanALTERA\000"
1964 /* 856 */ "OpArbitraryFloatASinALTERA\000"
1965 /* 883 */ "OpFixedSinALTERA\000"
1966 /* 900 */ "OpArbitraryFloatSinALTERA\000"
1967 /* 926 */ "OpArbitraryFloatLog1pALTERA\000"
1968 /* 954 */ "OpFixedRecipALTERA\000"
1969 /* 973 */ "OpArbitraryFloatRecipALTERA\000"
1970 /* 1001 */ "OpFixedExpALTERA\000"
1971 /* 1018 */ "OpArbitraryFloatExpALTERA\000"
1972 /* 1044 */ "OpArbitraryFloatACosALTERA\000"
1973 /* 1071 */ "OpFixedCosALTERA\000"
1974 /* 1088 */ "OpFixedSinCosALTERA\000"
1975 /* 1108 */ "OpArbitraryFloatSinCosALTERA\000"
1976 /* 1137 */ "OpArbitraryFloatCosALTERA\000"
1977 /* 1163 */ "OpArbitraryFloatCastFromIntALTERA\000"
1978 /* 1197 */ "OpArbitraryFloatCastToIntALTERA\000"
1979 /* 1229 */ "OpArbitraryFloatHypotALTERA\000"
1980 /* 1257 */ "OpArbitraryFloatCbrtALTERA\000"
1981 /* 1284 */ "OpArbitraryFloatRSqrtALTERA\000"
1982 /* 1312 */ "OpFixedSqrtALTERA\000"
1983 /* 1330 */ "OpArbitraryFloatSqrtALTERA\000"
1984 /* 1357 */ "OpFixedRsqrtALTERA\000"
1985 /* 1376 */ "OpArbitraryFloatCastALTERA\000"
1986 /* 1403 */ "OpArbitraryFloatDivALTERA\000"
1987 /* 1429 */ "OpArbitraryFloatPowALTERA\000"
1988 /* 1455 */ "OpGroupNonUniformBallotFindLSB\000"
1989 /* 1486 */ "OpGroupNonUniformBallotFindMSB\000"
1990 /* 1517 */ "G_FSUB\000"
1991 /* 1524 */ "G_STRICT_FSUB\000"
1992 /* 1538 */ "G_ATOMICRMW_FSUB\000"
1993 /* 1555 */ "G_SUB\000"
1994 /* 1561 */ "G_ATOMICRMW_SUB\000"
1995 /* 1577 */ "G_INTRINSIC\000"
1996 /* 1589 */ "G_FPTRUNC\000"
1997 /* 1599 */ "G_INTRINSIC_TRUNC\000"
1998 /* 1617 */ "G_TRUNC\000"
1999 /* 1625 */ "G_BUILD_VECTOR_TRUNC\000"
2000 /* 1646 */ "G_DYN_STACKALLOC\000"
2001 /* 1663 */ "G_FMAD\000"
2002 /* 1670 */ "G_FPEXTLOAD\000"
2003 /* 1682 */ "G_INDEXED_SEXTLOAD\000"
2004 /* 1701 */ "G_SEXTLOAD\000"
2005 /* 1712 */ "G_INDEXED_ZEXTLOAD\000"
2006 /* 1731 */ "G_ZEXTLOAD\000"
2007 /* 1742 */ "G_INDEXED_LOAD\000"
2008 /* 1757 */ "G_LOAD\000"
2009 /* 1764 */ "G_VECREDUCE_FADD\000"
2010 /* 1781 */ "G_FADD\000"
2011 /* 1788 */ "G_VECREDUCE_SEQ_FADD\000"
2012 /* 1809 */ "G_STRICT_FADD\000"
2013 /* 1823 */ "G_ATOMICRMW_FADD\000"
2014 /* 1840 */ "G_VECREDUCE_ADD\000"
2015 /* 1856 */ "G_ADD\000"
2016 /* 1862 */ "G_PTR_ADD\000"
2017 /* 1872 */ "G_ATOMICRMW_ADD\000"
2018 /* 1888 */ "G_ATOMICRMW_NAND\000"
2019 /* 1905 */ "G_VECREDUCE_AND\000"
2020 /* 1921 */ "G_AND\000"
2021 /* 1927 */ "G_ATOMICRMW_AND\000"
2022 /* 1943 */ "LIFETIME_END\000"
2023 /* 1956 */ "G_BRCOND\000"
2024 /* 1965 */ "G_ATOMICRMW_USUB_COND\000"
2025 /* 1987 */ "G_LLROUND\000"
2026 /* 1997 */ "G_LROUND\000"
2027 /* 2006 */ "G_INTRINSIC_ROUND\000"
2028 /* 2024 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
2029 /* 2050 */ "LOAD_STACK_GUARD\000"
2030 /* 2067 */ "PSEUDO_PROBE\000"
2031 /* 2080 */ "G_SSUBE\000"
2032 /* 2088 */ "G_USUBE\000"
2033 /* 2096 */ "G_FENCE\000"
2034 /* 2104 */ "ARITH_FENCE\000"
2035 /* 2116 */ "REG_SEQUENCE\000"
2036 /* 2129 */ "G_SADDE\000"
2037 /* 2137 */ "G_UADDE\000"
2038 /* 2145 */ "G_GET_FPMODE\000"
2039 /* 2158 */ "G_RESET_FPMODE\000"
2040 /* 2173 */ "G_SET_FPMODE\000"
2041 /* 2186 */ "G_FMINNUM_IEEE\000"
2042 /* 2201 */ "G_FMAXNUM_IEEE\000"
2043 /* 2216 */ "G_VSCALE\000"
2044 /* 2225 */ "G_JUMP_TABLE\000"
2045 /* 2238 */ "BUNDLE\000"
2046 /* 2245 */ "G_MEMSET_INLINE\000"
2047 /* 2261 */ "G_MEMCPY_INLINE\000"
2048 /* 2277 */ "RELOC_NONE\000"
2049 /* 2288 */ "LOCAL_ESCAPE\000"
2050 /* 2301 */ "ASSIGN_TYPE\000"
2051 /* 2313 */ "G_FPTRUNCSTORE\000"
2052 /* 2328 */ "G_STACKRESTORE\000"
2053 /* 2343 */ "G_INDEXED_STORE\000"
2054 /* 2359 */ "G_STORE\000"
2055 /* 2367 */ "G_BITREVERSE\000"
2056 /* 2380 */ "FAKE_USE\000"
2057 /* 2389 */ "DBG_VALUE\000"
2058 /* 2399 */ "G_GLOBAL_VALUE\000"
2059 /* 2414 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2060 /* 2437 */ "CONVERGENCECTRL_GLUE\000"
2061 /* 2458 */ "G_STACKSAVE\000"
2062 /* 2470 */ "G_MEMMOVE\000"
2063 /* 2480 */ "G_FREEZE\000"
2064 /* 2489 */ "G_FCANONICALIZE\000"
2065 /* 2505 */ "G_FMODF\000"
2066 /* 2513 */ "INIT_UNDEF\000"
2067 /* 2524 */ "G_IMPLICIT_DEF\000"
2068 /* 2539 */ "DBG_INSTR_REF\000"
2069 /* 2553 */ "OpConvertSToF\000"
2070 /* 2567 */ "OpConvertUToF\000"
2071 /* 2581 */ "OpConstantF\000"
2072 /* 2593 */ "G_FNEG\000"
2073 /* 2600 */ "EXTRACT_SUBREG\000"
2074 /* 2615 */ "INSERT_SUBREG\000"
2075 /* 2629 */ "G_SEXT_INREG\000"
2076 /* 2642 */ "SUBREG_TO_REG\000"
2077 /* 2656 */ "G_ATOMIC_CMPXCHG\000"
2078 /* 2673 */ "G_ATOMICRMW_XCHG\000"
2079 /* 2690 */ "G_GET_ROUNDING\000"
2080 /* 2705 */ "G_SET_ROUNDING\000"
2081 /* 2720 */ "G_FLOG\000"
2082 /* 2727 */ "G_VAARG\000"
2083 /* 2735 */ "PREALLOCATED_ARG\000"
2084 /* 2752 */ "G_PREFETCH\000"
2085 /* 2763 */ "G_CLMULH\000"
2086 /* 2772 */ "G_SMULH\000"
2087 /* 2780 */ "G_UMULH\000"
2088 /* 2788 */ "G_FTANH\000"
2089 /* 2796 */ "G_FSINH\000"
2090 /* 2804 */ "G_FCOSH\000"
2091 /* 2812 */ "DBG_PHI\000"
2092 /* 2820 */ "G_FPTOSI\000"
2093 /* 2829 */ "G_FPTOUI\000"
2094 /* 2838 */ "G_FPOWI\000"
2095 /* 2846 */ "OpConstantI\000"
2096 /* 2858 */ "COPY_LANEMASK\000"
2097 /* 2872 */ "G_PTRMASK\000"
2098 /* 2882 */ "GC_LABEL\000"
2099 /* 2891 */ "DBG_LABEL\000"
2100 /* 2901 */ "EH_LABEL\000"
2101 /* 2910 */ "ANNOTATION_LABEL\000"
2102 /* 2927 */ "ICALL_BRANCH_FUNNEL\000"
2103 /* 2947 */ "OpRoundFToTF32INTEL\000"
2104 /* 2967 */ "OpConvertFToBF16INTEL\000"
2105 /* 2989 */ "OpConvertBF16ToFINTEL\000"
2106 /* 3011 */ "OpSubgroupImageMediaBlockReadINTEL\000"
2107 /* 3046 */ "OpSubgroupImageBlockReadINTEL\000"
2108 /* 3076 */ "OpSubgroupBlockReadINTEL\000"
2109 /* 3101 */ "OpPredicatedLoadINTEL\000"
2110 /* 3123 */ "OpSubgroup2DBlockLoadINTEL\000"
2111 /* 3150 */ "OpCooperativeMatrixLoadCheckedINTEL\000"
2112 /* 3186 */ "OpCooperativeMatrixStoreCheckedINTEL\000"
2113 /* 3223 */ "OpCooperativeMatrixConstructCheckedINTEL\000"
2114 /* 3264 */ "OpSpecConstantCompositeContinuedINTEL\000"
2115 /* 3302 */ "OpConstantCompositeContinuedINTEL\000"
2116 /* 3336 */ "OpTypeStructContinuedINTEL\000"
2117 /* 3363 */ "OpCompositeConstructContinuedINTEL\000"
2118 /* 3398 */ "OpCooperativeMatrixGetElementCoordINTEL\000"
2119 /* 3438 */ "OpConvertHandleToSampledImageINTEL\000"
2120 /* 3473 */ "OpConvertHandleToImageINTEL\000"
2121 /* 3501 */ "OpSubgroupShuffleINTEL\000"
2122 /* 3524 */ "OpPredicatedStoreINTEL\000"
2123 /* 3547 */ "OpSubgroup2DBlockStoreINTEL\000"
2124 /* 3575 */ "OpSubgroup2DBlockLoadTransposeINTEL\000"
2125 /* 3611 */ "OpSubgroupMatrixMultiplyAccumulateINTEL\000"
2126 /* 3651 */ "OpSubgroupImageMediaBlockWriteINTEL\000"
2127 /* 3687 */ "OpSubgroupImageBlockWriteINTEL\000"
2128 /* 3718 */ "OpSubgroupBlockWriteINTEL\000"
2129 /* 3744 */ "OpControlBarrierArriveINTEL\000"
2130 /* 3772 */ "OpSubgroup2DBlockPrefetchINTEL\000"
2131 /* 3803 */ "OpCooperativeMatrixPrefetchINTEL\000"
2132 /* 3836 */ "OpAliasScopeDeclINTEL\000"
2133 /* 3858 */ "OpAliasDomainDeclINTEL\000"
2134 /* 3881 */ "OpAliasScopeListDeclINTEL\000"
2135 /* 3907 */ "OpAsmCallINTEL\000"
2136 /* 3922 */ "OpFunctionPointerCallINTEL\000"
2137 /* 3949 */ "OpLoopControlINTEL\000"
2138 /* 3968 */ "OpSubgroup2DBlockLoadTransformINTEL\000"
2139 /* 4004 */ "OpAsmINTEL\000"
2140 /* 4015 */ "OpBitwiseFunctionINTEL\000"
2141 /* 4038 */ "OpSubgroupShuffleDownINTEL\000"
2142 /* 4065 */ "OpSubgroupShuffleUpINTEL\000"
2143 /* 4090 */ "OpPtrCastToCrossWorkgroupINTEL\000"
2144 /* 4121 */ "OpMaskedGatherINTEL\000"
2145 /* 4141 */ "OpConvertHandleToSamplerINTEL\000"
2146 /* 4171 */ "OpConstantFunctionPointerINTEL\000"
2147 /* 4202 */ "OpMaskedScatterINTEL\000"
2148 /* 4223 */ "OpSubgroupShuffleXorINTEL\000"
2149 /* 4249 */ "OpCrossWorkgroupCastToPtrINTEL\000"
2150 /* 4280 */ "OpAsmTargetINTEL\000"
2151 /* 4297 */ "OpControlBarrierWaitINTEL\000"
2152 /* 4323 */ "OpVariableLengthArrayINTEL\000"
2153 /* 4350 */ "OpRestoreMemoryINTEL\000"
2154 /* 4371 */ "OpSaveMemoryINTEL\000"
2155 /* 4389 */ "G_FSHL\000"
2156 /* 4396 */ "G_SHL\000"
2157 /* 4402 */ "G_FCEIL\000"
2158 /* 4410 */ "G_SAVGCEIL\000"
2159 /* 4421 */ "G_UAVGCEIL\000"
2160 /* 4432 */ "PATCHABLE_TAIL_CALL\000"
2161 /* 4452 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2162 /* 4479 */ "PATCHABLE_EVENT_CALL\000"
2163 /* 4500 */ "FENTRY_CALL\000"
2164 /* 4512 */ "KILL\000"
2165 /* 4517 */ "G_CONSTANT_POOL\000"
2166 /* 4533 */ "G_ROTL\000"
2167 /* 4540 */ "G_VECREDUCE_FMUL\000"
2168 /* 4557 */ "G_FMUL\000"
2169 /* 4564 */ "G_VECREDUCE_SEQ_FMUL\000"
2170 /* 4585 */ "G_STRICT_FMUL\000"
2171 /* 4599 */ "G_CLMUL\000"
2172 /* 4607 */ "G_VECREDUCE_MUL\000"
2173 /* 4623 */ "G_MUL\000"
2174 /* 4629 */ "G_FREM\000"
2175 /* 4636 */ "G_STRICT_FREM\000"
2176 /* 4650 */ "G_SREM\000"
2177 /* 4657 */ "G_UREM\000"
2178 /* 4664 */ "G_SDIVREM\000"
2179 /* 4674 */ "G_UDIVREM\000"
2180 /* 4684 */ "INLINEASM\000"
2181 /* 4694 */ "G_VECREDUCE_FMINIMUM\000"
2182 /* 4715 */ "G_FMINIMUM\000"
2183 /* 4726 */ "G_ATOMICRMW_FMINIMUM\000"
2184 /* 4747 */ "G_VECREDUCE_FMAXIMUM\000"
2185 /* 4768 */ "G_FMAXIMUM\000"
2186 /* 4779 */ "G_ATOMICRMW_FMAXIMUM\000"
2187 /* 4800 */ "G_VECREDUCE_FMINIMUMNUM\000"
2188 /* 4824 */ "G_FMINIMUMNUM\000"
2189 /* 4838 */ "G_ATOMICRMW_FMINIMUMNUM\000"
2190 /* 4862 */ "G_VECREDUCE_FMAXIMUMNUM\000"
2191 /* 4886 */ "G_FMAXIMUMNUM\000"
2192 /* 4900 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
2193 /* 4924 */ "G_FMINNUM\000"
2194 /* 4934 */ "G_FMAXNUM\000"
2195 /* 4944 */ "G_FATAN\000"
2196 /* 4952 */ "G_FTAN\000"
2197 /* 4959 */ "G_INTRINSIC_ROUNDEVEN\000"
2198 /* 4981 */ "G_ASSERT_ALIGN\000"
2199 /* 4996 */ "G_FCOPYSIGN\000"
2200 /* 5008 */ "G_VECREDUCE_FMIN\000"
2201 /* 5025 */ "G_ATOMICRMW_FMIN\000"
2202 /* 5042 */ "G_VECREDUCE_SMIN\000"
2203 /* 5059 */ "G_SMIN\000"
2204 /* 5066 */ "G_VECREDUCE_UMIN\000"
2205 /* 5083 */ "G_UMIN\000"
2206 /* 5090 */ "G_ATOMICRMW_UMIN\000"
2207 /* 5107 */ "G_ATOMICRMW_MIN\000"
2208 /* 5123 */ "G_FASIN\000"
2209 /* 5131 */ "G_FSIN\000"
2210 /* 5138 */ "CFI_INSTRUCTION\000"
2211 /* 5154 */ "G_CTLZ_ZERO_POISON\000"
2212 /* 5173 */ "G_CTTZ_ZERO_POISON\000"
2213 /* 5192 */ "G_SSUBO\000"
2214 /* 5200 */ "G_USUBO\000"
2215 /* 5208 */ "G_SADDO\000"
2216 /* 5216 */ "G_UADDO\000"
2217 /* 5224 */ "JUMP_TABLE_DEBUG_INFO\000"
2218 /* 5246 */ "G_SMULO\000"
2219 /* 5254 */ "G_UMULO\000"
2220 /* 5262 */ "G_BZERO\000"
2221 /* 5270 */ "STACKMAP\000"
2222 /* 5279 */ "G_DEBUGTRAP\000"
2223 /* 5291 */ "G_UBSANTRAP\000"
2224 /* 5303 */ "G_TRAP\000"
2225 /* 5310 */ "G_ATOMICRMW_UDEC_WRAP\000"
2226 /* 5332 */ "G_ATOMICRMW_UINC_WRAP\000"
2227 /* 5354 */ "G_BSWAP\000"
2228 /* 5362 */ "G_SITOFP\000"
2229 /* 5371 */ "G_UITOFP\000"
2230 /* 5380 */ "G_FCMP\000"
2231 /* 5387 */ "G_STRICT_FCMP\000"
2232 /* 5401 */ "G_ICMP\000"
2233 /* 5408 */ "G_SCMP\000"
2234 /* 5415 */ "G_UCMP\000"
2235 /* 5422 */ "CONVERGENCECTRL_LOOP\000"
2236 /* 5443 */ "G_CTPOP\000"
2237 /* 5451 */ "PATCHABLE_OP\000"
2238 /* 5464 */ "FAULTING_OP\000"
2239 /* 5476 */ "PREALLOCATED_SETUP\000"
2240 /* 5495 */ "G_FLDEXP\000"
2241 /* 5504 */ "G_STRICT_FLDEXP\000"
2242 /* 5520 */ "G_FEXP\000"
2243 /* 5527 */ "G_FFREXP\000"
2244 /* 5536 */ "G_BR\000"
2245 /* 5541 */ "INLINEASM_BR\000"
2246 /* 5554 */ "G_BLOCK_ADDR\000"
2247 /* 5567 */ "MEMBARRIER\000"
2248 /* 5578 */ "G_CONSTANT_FOLD_BARRIER\000"
2249 /* 5602 */ "PATCHABLE_FUNCTION_ENTER\000"
2250 /* 5627 */ "G_READCYCLECOUNTER\000"
2251 /* 5646 */ "G_READSTEADYCOUNTER\000"
2252 /* 5666 */ "G_READ_REGISTER\000"
2253 /* 5682 */ "G_WRITE_REGISTER\000"
2254 /* 5699 */ "OpFmaKHR\000"
2255 /* 5708 */ "OpCooperativeMatrixLoadKHR\000"
2256 /* 5735 */ "OpCooperativeMatrixMulAddKHR\000"
2257 /* 5764 */ "OpGroupBitwiseAndKHR\000"
2258 /* 5785 */ "OpGroupLogicalAndKHR\000"
2259 /* 5806 */ "OpUntypedVariableKHR\000"
2260 /* 5827 */ "OpCooperativeMatrixStoreKHR\000"
2261 /* 5855 */ "OpGroupNonUniformRotateKHR\000"
2262 /* 5882 */ "OpAssumeTrueKHR\000"
2263 /* 5898 */ "OpFreezeKHR\000"
2264 /* 5910 */ "OpUntypedPrefetchKHR\000"
2265 /* 5931 */ "OpCooperativeMatrixLengthKHR\000"
2266 /* 5960 */ "OpReadClockKHR\000"
2267 /* 5975 */ "OpGroupFMulKHR\000"
2268 /* 5990 */ "OpGroupIMulKHR\000"
2269 /* 6005 */ "OpUntypedAccessChainKHR\000"
2270 /* 6029 */ "OpUntypedPtrAccessChainKHR\000"
2271 /* 6056 */ "OpUntypedInBoundsPtrAccessChainKHR\000"
2272 /* 6091 */ "OpUntypedInBoundsAccessChainKHR\000"
2273 /* 6123 */ "OpPoisonKHR\000"
2274 /* 6135 */ "OpGroupBitwiseOrKHR\000"
2275 /* 6155 */ "OpGroupLogicalOrKHR\000"
2276 /* 6175 */ "OpTypeUntypedPointerKHR\000"
2277 /* 6199 */ "OpGroupBitwiseXorKHR\000"
2278 /* 6220 */ "OpGroupLogicalXorKHR\000"
2279 /* 6241 */ "OpExpectKHR\000"
2280 /* 6253 */ "OpAbortKHR\000"
2281 /* 6264 */ "OpTypeCooperativeMatrixKHR\000"
2282 /* 6291 */ "OpUntypedGroupAsyncCopyKHR\000"
2283 /* 6318 */ "G_ASHR\000"
2284 /* 6325 */ "G_FSHR\000"
2285 /* 6332 */ "G_LSHR\000"
2286 /* 6339 */ "CONVERGENCECTRL_ANCHOR\000"
2287 /* 6362 */ "G_FFLOOR\000"
2288 /* 6371 */ "G_SAVGFLOOR\000"
2289 /* 6383 */ "G_UAVGFLOOR\000"
2290 /* 6395 */ "G_EXTRACT_SUBVECTOR\000"
2291 /* 6415 */ "G_INSERT_SUBVECTOR\000"
2292 /* 6434 */ "G_BUILD_VECTOR\000"
2293 /* 6449 */ "G_SHUFFLE_VECTOR\000"
2294 /* 6466 */ "G_STEP_VECTOR\000"
2295 /* 6480 */ "G_SPLAT_VECTOR\000"
2296 /* 6495 */ "G_VECREDUCE_XOR\000"
2297 /* 6511 */ "G_XOR\000"
2298 /* 6517 */ "G_ATOMICRMW_XOR\000"
2299 /* 6533 */ "G_VECREDUCE_OR\000"
2300 /* 6548 */ "G_OR\000"
2301 /* 6553 */ "G_ATOMICRMW_OR\000"
2302 /* 6568 */ "G_ROTR\000"
2303 /* 6575 */ "G_INTTOPTR\000"
2304 /* 6586 */ "G_FABS\000"
2305 /* 6593 */ "G_ABS\000"
2306 /* 6599 */ "G_ABDS\000"
2307 /* 6606 */ "G_UNMERGE_VALUES\000"
2308 /* 6623 */ "G_MERGE_VALUES\000"
2309 /* 6638 */ "G_CTLS\000"
2310 /* 6645 */ "G_FACOS\000"
2311 /* 6653 */ "G_FCOS\000"
2312 /* 6660 */ "G_FSINCOS\000"
2313 /* 6670 */ "G_STRICT_FCMPS\000"
2314 /* 6685 */ "G_CONCAT_VECTORS\000"
2315 /* 6702 */ "COPY_TO_REGCLASS\000"
2316 /* 6719 */ "G_IS_FPCLASS\000"
2317 /* 6732 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2318 /* 6762 */ "G_VECTOR_COMPRESS\000"
2319 /* 6780 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2320 /* 6807 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2321 /* 6845 */ "G_TRUNC_SSAT_S\000"
2322 /* 6860 */ "OpFSubS\000"
2323 /* 6868 */ "OpStrictFSubS\000"
2324 /* 6882 */ "OpISubS\000"
2325 /* 6890 */ "OpShiftRightArithmeticS\000"
2326 /* 6914 */ "OpFAddS\000"
2327 /* 6922 */ "OpStrictFAddS\000"
2328 /* 6936 */ "OpIAddS\000"
2329 /* 6944 */ "OpBitwiseAndS\000"
2330 /* 6958 */ "OpUModS\000"
2331 /* 6966 */ "OpShiftLeftLogicalS\000"
2332 /* 6986 */ "OpShiftRightLogicalS\000"
2333 /* 7007 */ "OpFMulS\000"
2334 /* 7015 */ "OpStrictFMulS\000"
2335 /* 7029 */ "OpIMulS\000"
2336 /* 7037 */ "OpFRemS\000"
2337 /* 7045 */ "OpStrictFRemS\000"
2338 /* 7059 */ "OpSRemS\000"
2339 /* 7067 */ "OpConvertFToS\000"
2340 /* 7081 */ "OpSatConvertUToS\000"
2341 /* 7098 */ "OpBitwiseOrS\000"
2342 /* 7111 */ "OpBitwiseXorS\000"
2343 /* 7125 */ "OpFDivS\000"
2344 /* 7133 */ "OpStrictFDivS\000"
2345 /* 7147 */ "OpSDivS\000"
2346 /* 7155 */ "OpUDivS\000"
2347 /* 7163 */ "OpISubBorrowS\000"
2348 /* 7177 */ "OpIAddCarryS\000"
2349 /* 7190 */ "G_SSUBSAT\000"
2350 /* 7200 */ "G_USUBSAT\000"
2351 /* 7210 */ "G_SADDSAT\000"
2352 /* 7220 */ "G_UADDSAT\000"
2353 /* 7230 */ "G_SSHLSAT\000"
2354 /* 7240 */ "G_USHLSAT\000"
2355 /* 7250 */ "G_SMULFIXSAT\000"
2356 /* 7263 */ "G_UMULFIXSAT\000"
2357 /* 7276 */ "G_SDIVFIXSAT\000"
2358 /* 7289 */ "G_UDIVFIXSAT\000"
2359 /* 7302 */ "G_ATOMICRMW_USUB_SAT\000"
2360 /* 7323 */ "G_FPTOSI_SAT\000"
2361 /* 7336 */ "G_FPTOUI_SAT\000"
2362 /* 7349 */ "G_EXTRACT\000"
2363 /* 7359 */ "G_SELECT\000"
2364 /* 7368 */ "G_BRINDIRECT\000"
2365 /* 7381 */ "PATCHABLE_RET\000"
2366 /* 7395 */ "G_MEMSET\000"
2367 /* 7404 */ "PATCHABLE_FUNCTION_EXIT\000"
2368 /* 7428 */ "G_BRJT\000"
2369 /* 7435 */ "G_EXTRACT_VECTOR_ELT\000"
2370 /* 7456 */ "G_INSERT_VECTOR_ELT\000"
2371 /* 7476 */ "G_FCONSTANT\000"
2372 /* 7488 */ "G_CONSTANT\000"
2373 /* 7499 */ "G_INTRINSIC_CONVERGENT\000"
2374 /* 7522 */ "STATEPOINT\000"
2375 /* 7533 */ "PATCHPOINT\000"
2376 /* 7544 */ "G_PTRTOINT\000"
2377 /* 7555 */ "G_FRINT\000"
2378 /* 7563 */ "G_INTRINSIC_LLRINT\000"
2379 /* 7582 */ "G_INTRINSIC_LRINT\000"
2380 /* 7600 */ "G_FNEARBYINT\000"
2381 /* 7613 */ "G_VASTART\000"
2382 /* 7623 */ "LIFETIME_START\000"
2383 /* 7638 */ "G_INVOKE_REGION_START\000"
2384 /* 7660 */ "G_INSERT\000"
2385 /* 7669 */ "G_FSQRT\000"
2386 /* 7677 */ "G_STRICT_FSQRT\000"
2387 /* 7692 */ "G_BITCAST\000"
2388 /* 7702 */ "G_ADDRSPACE_CAST\000"
2389 /* 7719 */ "DBG_VALUE_LIST\000"
2390 /* 7734 */ "G_FPEXT\000"
2391 /* 7742 */ "G_SEXT\000"
2392 /* 7749 */ "G_ASSERT_SEXT\000"
2393 /* 7763 */ "G_ANYEXT\000"
2394 /* 7772 */ "G_ZEXT\000"
2395 /* 7779 */ "G_ASSERT_ZEXT\000"
2396 /* 7793 */ "OpTypeVectorIdEXT\000"
2397 /* 7811 */ "OpAtomicFAddEXT\000"
2398 /* 7827 */ "OpArithmeticFenceEXT\000"
2399 /* 7848 */ "OpAtomicFMinEXT\000"
2400 /* 7864 */ "OpAtomicFMaxEXT\000"
2401 /* 7880 */ "G_ABDU\000"
2402 /* 7887 */ "G_TRUNC_SSAT_U\000"
2403 /* 7902 */ "G_TRUNC_USAT_U\000"
2404 /* 7917 */ "OpConvertFToU\000"
2405 /* 7931 */ "OpSatConvertSToU\000"
2406 /* 7948 */ "OpConvertPtrToU\000"
2407 /* 7964 */ "G_FDIV\000"
2408 /* 7971 */ "G_STRICT_FDIV\000"
2409 /* 7985 */ "G_SDIV\000"
2410 /* 7992 */ "G_UDIV\000"
2411 /* 7999 */ "G_GET_FPENV\000"
2412 /* 8011 */ "G_RESET_FPENV\000"
2413 /* 8025 */ "G_SET_FPENV\000"
2414 /* 8037 */ "OpTypeAccelerationStructureNV\000"
2415 /* 8067 */ "OpImageSampleFootprintNV\000"
2416 /* 8092 */ "OpTypeCooperativeMatrixNV\000"
2417 /* 8118 */ "OpFSubV\000"
2418 /* 8126 */ "OpStrictFSubV\000"
2419 /* 8140 */ "OpISubV\000"
2420 /* 8148 */ "OpShiftRightArithmeticV\000"
2421 /* 8172 */ "OpFAddV\000"
2422 /* 8180 */ "OpStrictFAddV\000"
2423 /* 8194 */ "OpIAddV\000"
2424 /* 8202 */ "OpBitwiseAndV\000"
2425 /* 8216 */ "OpUModV\000"
2426 /* 8224 */ "OpFNegateV\000"
2427 /* 8235 */ "OpShiftLeftLogicalV\000"
2428 /* 8255 */ "OpShiftRightLogicalV\000"
2429 /* 8276 */ "OpFMulV\000"
2430 /* 8284 */ "OpStrictFMulV\000"
2431 /* 8298 */ "OpIMulV\000"
2432 /* 8306 */ "OpFRemV\000"
2433 /* 8314 */ "OpStrictFRemV\000"
2434 /* 8328 */ "OpSRemV\000"
2435 /* 8336 */ "OpBitwiseOrV\000"
2436 /* 8349 */ "OpBitwiseXorV\000"
2437 /* 8363 */ "OpFDivV\000"
2438 /* 8371 */ "OpStrictFDivV\000"
2439 /* 8385 */ "OpSDivV\000"
2440 /* 8393 */ "OpUDivV\000"
2441 /* 8401 */ "OpISubBorrowV\000"
2442 /* 8415 */ "OpIAddCarryV\000"
2443 /* 8428 */ "G_FPOW\000"
2444 /* 8435 */ "G_VECREDUCE_FMAX\000"
2445 /* 8452 */ "G_ATOMICRMW_FMAX\000"
2446 /* 8469 */ "G_VECREDUCE_SMAX\000"
2447 /* 8486 */ "G_SMAX\000"
2448 /* 8493 */ "G_VECREDUCE_UMAX\000"
2449 /* 8510 */ "G_UMAX\000"
2450 /* 8517 */ "G_ATOMICRMW_UMAX\000"
2451 /* 8534 */ "G_ATOMICRMW_MAX\000"
2452 /* 8550 */ "G_FRAME_INDEX\000"
2453 /* 8564 */ "G_SBFX\000"
2454 /* 8571 */ "G_UBFX\000"
2455 /* 8578 */ "G_SMULFIX\000"
2456 /* 8588 */ "G_UMULFIX\000"
2457 /* 8598 */ "G_SDIVFIX\000"
2458 /* 8608 */ "G_UDIVFIX\000"
2459 /* 8618 */ "G_MEMCPY\000"
2460 /* 8627 */ "COPY\000"
2461 /* 8632 */ "CONVERGENCECTRL_ENTRY\000"
2462 /* 8654 */ "G_CTLZ\000"
2463 /* 8661 */ "G_CTTZ\000"
2464 /* 8668 */ "OpAtomicISub\000"
2465 /* 8681 */ "OpVectorExtractDynamic\000"
2466 /* 8704 */ "OpVectorInsertDynamic\000"
2467 /* 8726 */ "OpPtrCastToGeneric\000"
2468 /* 8745 */ "OpExecutionModeId\000"
2469 /* 8763 */ "OpDecorateId\000"
2470 /* 8776 */ "OpIsValidReserveId\000"
2471 /* 8795 */ "OpTypeReserveId\000"
2472 /* 8811 */ "OpImageRead\000"
2473 /* 8823 */ "OpImageSparseRead\000"
2474 /* 8841 */ "OpAtomicLoad\000"
2475 /* 8854 */ "OpLoad\000"
2476 /* 8861 */ "OpGroupNonUniformFAdd\000"
2477 /* 8883 */ "OpGroupFAdd\000"
2478 /* 8895 */ "OpAtomicIAdd\000"
2479 /* 8908 */ "OpGroupNonUniformIAdd\000"
2480 /* 8930 */ "OpGroupIAdd\000"
2481 /* 8942 */ "OpSMulExtended\000"
2482 /* 8957 */ "OpUMulExtended\000"
2483 /* 8972 */ "OpOrdered\000"
2484 /* 8982 */ "OpUnordered\000"
2485 /* 8994 */ "OpModuleProcessed\000"
2486 /* 9012 */ "OpSourceContinued\000"
2487 /* 9030 */ "OpCopyMemorySized\000"
2488 /* 9048 */ "OpTypeVoid\000"
2489 /* 9059 */ "OpAtomicAnd\000"
2490 /* 9071 */ "OpGroupNonUniformBitwiseAnd\000"
2491 /* 9099 */ "OpGroupNonUniformLogicalAnd\000"
2492 /* 9127 */ "OpLogicalAnd\000"
2493 /* 9140 */ "OpFunctionEnd\000"
2494 /* 9154 */ "OpSelectSFSCond\000"
2495 /* 9170 */ "OpSelectVFSCond\000"
2496 /* 9186 */ "OpSelectSISCond\000"
2497 /* 9202 */ "OpSelectVISCond\000"
2498 /* 9218 */ "OpSelectSPSCond\000"
2499 /* 9234 */ "OpSelectVPSCond\000"
2500 /* 9250 */ "OpSelectSFVCond\000"
2501 /* 9266 */ "OpSelectVFVCond\000"
2502 /* 9282 */ "OpSelectSIVCond\000"
2503 /* 9298 */ "OpSelectVIVCond\000"
2504 /* 9314 */ "OpSelectSPVCond\000"
2505 /* 9330 */ "OpSelectVPVCond\000"
2506 /* 9346 */ "OpImageQuerySizeLod\000"
2507 /* 9366 */ "OpImageSampleImplicitLod\000"
2508 /* 9391 */ "OpImageSparseSampleImplicitLod\000"
2509 /* 9422 */ "OpImageSampleDrefImplicitLod\000"
2510 /* 9451 */ "OpImageSparseSampleDrefImplicitLod\000"
2511 /* 9486 */ "OpImageSampleProjDrefImplicitLod\000"
2512 /* 9519 */ "OpImageSparseSampleProjDrefImplicitLod\000"
2513 /* 9558 */ "OpImageSampleProjImplicitLod\000"
2514 /* 9587 */ "OpImageSparseSampleProjImplicitLod\000"
2515 /* 9622 */ "OpImageSampleExplicitLod\000"
2516 /* 9647 */ "OpImageSparseSampleExplicitLod\000"
2517 /* 9678 */ "OpImageSampleDrefExplicitLod\000"
2518 /* 9707 */ "OpImageSparseSampleDrefExplicitLod\000"
2519 /* 9742 */ "OpImageSampleProjDrefExplicitLod\000"
2520 /* 9775 */ "OpImageSparseSampleProjDrefExplicitLod\000"
2521 /* 9814 */ "OpImageSampleProjExplicitLod\000"
2522 /* 9843 */ "OpImageSparseSampleProjExplicitLod\000"
2523 /* 9878 */ "OpImageQueryLod\000"
2524 /* 9894 */ "OpFMod\000"
2525 /* 9901 */ "OpSMod\000"
2526 /* 9908 */ "OpSource\000"
2527 /* 9917 */ "OpExecutionMode\000"
2528 /* 9933 */ "OpTypeSampledImage\000"
2529 /* 9952 */ "OpSampledImage\000"
2530 /* 9967 */ "OpTypeImage\000"
2531 /* 9979 */ "OpImage\000"
2532 /* 9987 */ "OpTypePipeStorage\000"
2533 /* 10005 */ "OpBuildNDRange\000"
2534 /* 10020 */ "OpAtomicExchange\000"
2535 /* 10037 */ "OpAtomicCompareExchange\000"
2536 /* 10061 */ "OpSelectionMerge\000"
2537 /* 10078 */ "OpLoopMerge\000"
2538 /* 10090 */ "OpUnreachable\000"
2539 /* 10104 */ "OpVariable\000"
2540 /* 10115 */ "OpGroupNonUniformShuffle\000"
2541 /* 10140 */ "OpVectorShuffle\000"
2542 /* 10156 */ "OpName\000"
2543 /* 10163 */ "OpMemberName\000"
2544 /* 10176 */ "OpFwidthFine\000"
2545 /* 10189 */ "OpDPdxFine\000"
2546 /* 10200 */ "OpDPdyFine\000"
2547 /* 10211 */ "OpNoLine\000"
2548 /* 10220 */ "OpLine\000"
2549 /* 10227 */ "OpReservedReadPipe\000"
2550 /* 10246 */ "OpReadPipe\000"
2551 /* 10257 */ "OpCommitReadPipe\000"
2552 /* 10274 */ "OpGroupCommitReadPipe\000"
2553 /* 10296 */ "OpTypePipe\000"
2554 /* 10307 */ "OpReservedWritePipe\000"
2555 /* 10327 */ "OpWritePipe\000"
2556 /* 10339 */ "OpCommitWritePipe\000"
2557 /* 10357 */ "OpGroupCommitWritePipe\000"
2558 /* 10380 */ "UNKNOWN_type\000"
2559 /* 10393 */ "OpAtomicStore\000"
2560 /* 10407 */ "OpStore\000"
2561 /* 10415 */ "OpSpecConstantFalse\000"
2562 /* 10435 */ "OpConstantFalse\000"
2563 /* 10451 */ "OpTranspose\000"
2564 /* 10463 */ "OpFwidthCoarse\000"
2565 /* 10478 */ "OpDPdxCoarse\000"
2566 /* 10491 */ "OpDPdyCoarse\000"
2567 /* 10504 */ "OpBitReverse\000"
2568 /* 10517 */ "OpFNegate\000"
2569 /* 10527 */ "OpSNegate\000"
2570 /* 10537 */ "OpDecorate\000"
2571 /* 10548 */ "OpMemberDecorate\000"
2572 /* 10565 */ "OpIsFinite\000"
2573 /* 10576 */ "OpImageWrite\000"
2574 /* 10589 */ "OpSpecConstantComposite\000"
2575 /* 10613 */ "OpConstantComposite\000"
2576 /* 10633 */ "OpTypeQueue\000"
2577 /* 10645 */ "OpGetDefaultQueue\000"
2578 /* 10663 */ "OpReturnValue\000"
2579 /* 10677 */ "OpTypeOpaque\000"
2580 /* 10690 */ "OpSpecConstantTrue\000"
2581 /* 10709 */ "OpConstantTrue\000"
2582 /* 10724 */ "OpEndPrimitive\000"
2583 /* 10739 */ "OpEndStreamPrimitive\000"
2584 /* 10760 */ "OpImageQuerySize\000"
2585 /* 10777 */ "OpNamedBarrierInitialize\000"
2586 /* 10802 */ "OpSizeOf\000"
2587 /* 10811 */ "OpUndef\000"
2588 /* 10819 */ "OpPtrDiff\000"
2589 /* 10829 */ "OpIsInf\000"
2590 /* 10837 */ "OpDecorateString\000"
2591 /* 10854 */ "OpMemberDecorateString\000"
2592 /* 10877 */ "OpString\000"
2593 /* 10886 */ "OpBranch\000"
2594 /* 10895 */ "OpImageFetch\000"
2595 /* 10908 */ "OpImageSparseFetch\000"
2596 /* 10927 */ "OpSwitch\000"
2597 /* 10936 */ "OpFwidth\000"
2598 /* 10945 */ "OpArrayLength\000"
2599 /* 10959 */ "OpPhi\000"
2600 /* 10965 */ "OpAtomicCompareExchangeWeak\000"
2601 /* 10993 */ "OpCopyLogical\000"
2602 /* 11007 */ "OpIsNormal\000"
2603 /* 11018 */ "OpBranchConditional\000"
2604 /* 11038 */ "OpIEqual\000"
2605 /* 11047 */ "OpFOrdEqual\000"
2606 /* 11059 */ "OpFUnordEqual\000"
2607 /* 11073 */ "OpLogicalEqual\000"
2608 /* 11088 */ "OpGroupNonUniformAllEqual\000"
2609 /* 11114 */ "OpSGreaterThanEqual\000"
2610 /* 11134 */ "OpUGreaterThanEqual\000"
2611 /* 11154 */ "OpFOrdGreaterThanEqual\000"
2612 /* 11177 */ "OpFUnordGreaterThanEqual\000"
2613 /* 11202 */ "OpSLessThanEqual\000"
2614 /* 11219 */ "OpULessThanEqual\000"
2615 /* 11236 */ "OpFOrdLessThanEqual\000"
2616 /* 11256 */ "OpFUnordLessThanEqual\000"
2617 /* 11278 */ "OpPtrEqual\000"
2618 /* 11289 */ "OpINotEqual\000"
2619 /* 11301 */ "OpFOrdNotEqual\000"
2620 /* 11316 */ "OpFUnordNotEqual\000"
2621 /* 11333 */ "OpLogicalNotEqual\000"
2622 /* 11351 */ "OpPtrNotEqual\000"
2623 /* 11365 */ "OpLabel\000"
2624 /* 11373 */ "OpMemoryModel\000"
2625 /* 11387 */ "OpEnqueueKernel\000"
2626 /* 11403 */ "OpGroupNonUniformAll\000"
2627 /* 11424 */ "OpAll\000"
2628 /* 11430 */ "OpGroupAll\000"
2629 /* 11441 */ "OpFunctionCall\000"
2630 /* 11456 */ "OpKill\000"
2631 /* 11463 */ "OpConstantNull\000"
2632 /* 11478 */ "OpTypeBool\000"
2633 /* 11489 */ "OpGroupNonUniformFMul\000"
2634 /* 11511 */ "OpGroupNonUniformIMul\000"
2635 /* 11533 */ "OpIsNan\000"
2636 /* 11541 */ "OpSGreaterThan\000"
2637 /* 11556 */ "OpUGreaterThan\000"
2638 /* 11571 */ "OpFOrdGreaterThan\000"
2639 /* 11589 */ "OpFUnordGreaterThan\000"
2640 /* 11609 */ "OpSLessThan\000"
2641 /* 11621 */ "OpULessThan\000"
2642 /* 11633 */ "OpFOrdLessThan\000"
2643 /* 11648 */ "OpFUnordLessThan\000"
2644 /* 11665 */ "OpGroupNonUniformFMin\000"
2645 /* 11687 */ "OpGroupFMin\000"
2646 /* 11699 */ "OpAtomicSMin\000"
2647 /* 11712 */ "OpGroupNonUniformSMin\000"
2648 /* 11734 */ "OpGroupSMin\000"
2649 /* 11746 */ "OpAtomicUMin\000"
2650 /* 11759 */ "OpGroupNonUniformUMin\000"
2651 /* 11781 */ "OpGroupUMin\000"
2652 /* 11793 */ "OpAccessChain\000"
2653 /* 11807 */ "OpPtrAccessChain\000"
2654 /* 11824 */ "OpInBoundsPtrAccessChain\000"
2655 /* 11849 */ "OpInBoundsAccessChain\000"
2656 /* 11871 */ "OpSourceExtension\000"
2657 /* 11889 */ "OpExtension\000"
2658 /* 11901 */ "OpDemoteToHelperInvocation\000"
2659 /* 11928 */ "OpTypeFunction\000"
2660 /* 11943 */ "OpFunction\000"
2661 /* 11954 */ "OpReturn\000"
2662 /* 11963 */ "OpGroupNonUniformShuffleDown\000"
2663 /* 11992 */ "OpCaptureEventProfilingInfo\000"
2664 /* 12020 */ "OpSpecConstantOp\000"
2665 /* 12037 */ "OpGroupNonUniformShuffleUp\000"
2666 /* 12064 */ "OpGroupNonUniformQuadSwap\000"
2667 /* 12090 */ "OpNop\000"
2668 /* 12096 */ "OpLifetimeStop\000"
2669 /* 12111 */ "OpAtomicOr\000"
2670 /* 12122 */ "OpGroupNonUniformBitwiseOr\000"
2671 /* 12149 */ "OpGroupNonUniformLogicalOr\000"
2672 /* 12176 */ "OpLogicalOr\000"
2673 /* 12188 */ "OpAtomicFlagClear\000"
2674 /* 12206 */ "OpVectorTimesScalar\000"
2675 /* 12226 */ "OpMatrixTimesScalar\000"
2676 /* 12246 */ "OpImageQueryOrder\000"
2677 /* 12264 */ "OpImageGather\000"
2678 /* 12278 */ "OpImageSparseGather\000"
2679 /* 12298 */ "OpImageDrefGather\000"
2680 /* 12316 */ "OpImageSparseDrefGather\000"
2681 /* 12340 */ "OpTypeNamedBarrier\000"
2682 /* 12359 */ "OpMemoryNamedBarrier\000"
2683 /* 12380 */ "OpControlBarrier\000"
2684 /* 12397 */ "OpMemoryBarrier\000"
2685 /* 12413 */ "OpTypeSampler\000"
2686 /* 12427 */ "OpConstantSampler\000"
2687 /* 12445 */ "OpLessOrGreater\000"
2688 /* 12461 */ "OpFunctionParameter\000"
2689 /* 12481 */ "OpTypeForwardPointer\000"
2690 /* 12502 */ "OpTypePointer\000"
2691 /* 12516 */ "OpImageTexelPointer\000"
2692 /* 12536 */ "OpAtomicXor\000"
2693 /* 12548 */ "OpGroupNonUniformShuffleXor\000"
2694 /* 12576 */ "OpGroupNonUniformBitwiseXor\000"
2695 /* 12604 */ "OpGroupNonUniformLogicalXor\000"
2696 /* 12632 */ "OpTypeVector\000"
2697 /* 12645 */ "OpMatrixTimesVector\000"
2698 /* 12665 */ "OpConvertUToPtr\000"
2699 /* 12681 */ "OpGenericCastToPtr\000"
2700 /* 12700 */ "OpGenericPtrMemSemantics\000"
2701 /* 12725 */ "OpImageQuerySamples\000"
2702 /* 12745 */ "OpImageQueryLevels\000"
2703 /* 12764 */ "OpReserveReadPipePackets\000"
2704 /* 12789 */ "OpGroupReserveReadPipePackets\000"
2705 /* 12819 */ "OpReserveWritePipePackets\000"
2706 /* 12845 */ "OpGroupReserveWritePipePackets\000"
2707 /* 12876 */ "OpGetNumPipePackets\000"
2708 /* 12896 */ "OpGetMaxPipePackets\000"
2709 /* 12916 */ "OpGroupWaitEvents\000"
2710 /* 12934 */ "OpSetUserEventStatus\000"
2711 /* 12955 */ "OpSDotAccSat\000"
2712 /* 12968 */ "OpSUDotAccSat\000"
2713 /* 12982 */ "OpUDotAccSat\000"
2714 /* 12995 */ "OpImageQueryFormat\000"
2715 /* 13014 */ "OpTypeFloat\000"
2716 /* 13026 */ "OpBitFieldSExtract\000"
2717 /* 13045 */ "OpBitFieldUExtract\000"
2718 /* 13064 */ "OpCompositeExtract\000"
2719 /* 13083 */ "OpGroupNonUniformBallotBitExtract\000"
2720 /* 13117 */ "OpCopyObject\000"
2721 /* 13130 */ "OpGroupNonUniformElect\000"
2722 /* 13153 */ "OpOuterProduct\000"
2723 /* 13168 */ "OpTypeStruct\000"
2724 /* 13181 */ "OpCompositeConstruct\000"
2725 /* 13202 */ "OpAtomicFlagTestAndSet\000"
2726 /* 13225 */ "OpSignBitSet\000"
2727 /* 13238 */ "OpGenericCastToPtrExplicit\000"
2728 /* 13265 */ "OpTypeInt\000"
2729 /* 13275 */ "OpSpecConstant\000"
2730 /* 13290 */ "OpImageSparseTexelsResident\000"
2731 /* 13318 */ "OpAtomicIDecrement\000"
2732 /* 13337 */ "OpAtomicIIncrement\000"
2733 /* 13356 */ "OpIsValidEvent\000"
2734 /* 13371 */ "OpTypeDeviceEvent\000"
2735 /* 13389 */ "OpTypeEvent\000"
2736 /* 13401 */ "OpReleaseEvent\000"
2737 /* 13416 */ "OpRetainEvent\000"
2738 /* 13430 */ "OpCreateUserEvent\000"
2739 /* 13448 */ "OpEntryPoint\000"
2740 /* 13461 */ "OpBitCount\000"
2741 /* 13472 */ "OpGroupNonUniformBallotBitCount\000"
2742 /* 13504 */ "OpSDot\000"
2743 /* 13511 */ "OpSUDot\000"
2744 /* 13519 */ "OpUDot\000"
2745 /* 13526 */ "OpDot\000"
2746 /* 13532 */ "OpLogicalNot\000"
2747 /* 13545 */ "OpNot\000"
2748 /* 13551 */ "OpGroupNonUniformInverseBallot\000"
2749 /* 13582 */ "OpGroupNonUniformBallot\000"
2750 /* 13606 */ "OpLifetimeStart\000"
2751 /* 13622 */ "OpBitFieldInsert\000"
2752 /* 13639 */ "OpCompositeInsert\000"
2753 /* 13657 */ "OpFConvert\000"
2754 /* 13668 */ "OpSConvert\000"
2755 /* 13679 */ "OpUConvert\000"
2756 /* 13690 */ "OpExtInstImport\000"
2757 /* 13706 */ "OpGroupNonUniformBroadcast\000"
2758 /* 13733 */ "OpGroupBroadcast\000"
2759 /* 13750 */ "OpBitcast\000"
2760 /* 13760 */ "OpExtInst\000"
2761 /* 13770 */ "OpGroupNonUniformBroadcastFirst\000"
2762 /* 13802 */ "OpGroupNonUniformFMax\000"
2763 /* 13824 */ "OpGroupFMax\000"
2764 /* 13836 */ "OpAtomicSMax\000"
2765 /* 13849 */ "OpGroupNonUniformSMax\000"
2766 /* 13871 */ "OpGroupSMax\000"
2767 /* 13883 */ "OpAtomicUMax\000"
2768 /* 13896 */ "OpGroupNonUniformUMax\000"
2769 /* 13918 */ "OpGroupUMax\000"
2770 /* 13930 */ "OpDPdx\000"
2771 /* 13937 */ "OpEmitStreamVertex\000"
2772 /* 13956 */ "OpEmitVertex\000"
2773 /* 13969 */ "OpTypeMatrix\000"
2774 /* 13982 */ "OpVectorTimesMatrix\000"
2775 /* 14002 */ "OpMatrixTimesMatrix\000"
2776 /* 14022 */ "OpTypeRuntimeArray\000"
2777 /* 14041 */ "OpTypeArray\000"
2778 /* 14053 */ "OpDPdy\000"
2779 /* 14060 */ "OpGroupNonUniformAny\000"
2780 /* 14081 */ "OpAny\000"
2781 /* 14087 */ "OpGroupAny\000"
2782 /* 14098 */ "OpGroupAsyncCopy\000"
2783 /* 14115 */ "OpCopyMemory\000"
2784 /* 14128 */ "OpCapability\000"
2785};
2786#ifdef __GNUC__
2787#pragma GCC diagnostic pop
2788#endif
2789
2790extern const unsigned SPIRVInstrNameIndices[] = {
2791 2816U, 4684U, 5541U, 5138U, 2901U, 2882U, 2910U, 4512U,
2792 2600U, 2615U, 2526U, 2513U, 2642U, 6702U, 2389U, 7719U,
2793 2539U, 2812U, 2891U, 2116U, 8627U, 2858U, 2238U, 7623U,
2794 1943U, 2067U, 2104U, 5270U, 4500U, 7533U, 2050U, 5476U,
2795 2735U, 7522U, 2288U, 5464U, 5451U, 5602U, 7381U, 7404U,
2796 4432U, 4479U, 4452U, 2927U, 2380U, 5567U, 5224U, 2277U,
2797 8632U, 6339U, 5422U, 2437U, 7749U, 7779U, 4981U, 1856U,
2798 1555U, 4623U, 7985U, 7992U, 4650U, 4657U, 4664U, 4674U,
2799 1921U, 6548U, 6511U, 6599U, 7880U, 6383U, 4421U, 6371U,
2800 4410U, 2524U, 2814U, 8550U, 2399U, 2414U, 4517U, 7349U,
2801 6606U, 7660U, 6623U, 6434U, 1625U, 6685U, 7544U, 6575U,
2802 7692U, 2480U, 5578U, 2024U, 1599U, 2006U, 7582U, 7563U,
2803 4959U, 5627U, 5646U, 1757U, 1701U, 1731U, 1670U, 1742U,
2804 1682U, 1712U, 2359U, 2313U, 2343U, 6732U, 2656U, 2673U,
2805 1872U, 1561U, 1927U, 1888U, 6553U, 6517U, 8534U, 5107U,
2806 8517U, 5090U, 1823U, 1538U, 8452U, 5025U, 4779U, 4726U,
2807 4900U, 4838U, 5332U, 5310U, 1965U, 7302U, 2096U, 2752U,
2808 1956U, 7368U, 7638U, 1577U, 6780U, 7499U, 6807U, 7763U,
2809 1617U, 6845U, 7887U, 7902U, 7488U, 7476U, 7613U, 2727U,
2810 7742U, 2629U, 7772U, 4396U, 6332U, 6318U, 4389U, 6325U,
2811 6568U, 4533U, 5401U, 5380U, 5408U, 5415U, 7359U, 5216U,
2812 2137U, 5200U, 2088U, 5208U, 2129U, 5192U, 2080U, 5254U,
2813 5246U, 2780U, 2772U, 7220U, 7210U, 7200U, 7190U, 7240U,
2814 7230U, 8578U, 8588U, 7250U, 7263U, 8598U, 8608U, 7276U,
2815 7289U, 1781U, 1517U, 4557U, 59U, 1663U, 7964U, 4629U,
2816 2505U, 8428U, 2838U, 5520U, 35U, 9U, 2720U, 18U,
2817 0U, 5495U, 5527U, 2593U, 7734U, 1589U, 2820U, 2829U,
2818 5362U, 5371U, 7323U, 7336U, 6586U, 4996U, 6719U, 2489U,
2819 4924U, 4934U, 2186U, 2201U, 4715U, 4768U, 4824U, 4886U,
2820 7999U, 8025U, 8011U, 2145U, 2173U, 2158U, 2690U, 2705U,
2821 1862U, 2872U, 5059U, 8486U, 5083U, 8510U, 6593U, 1997U,
2822 1987U, 5536U, 7428U, 2216U, 6415U, 6395U, 7456U, 7435U,
2823 6449U, 6480U, 6466U, 6762U, 8661U, 5173U, 8654U, 5154U,
2824 6638U, 5443U, 5354U, 2367U, 4599U, 2763U, 4402U, 6653U,
2825 5131U, 6660U, 4952U, 6645U, 5123U, 4944U, 26U, 2804U,
2826 2796U, 2788U, 7669U, 6362U, 7555U, 7600U, 7702U, 5554U,
2827 2225U, 1646U, 2458U, 2328U, 1809U, 1524U, 4585U, 7971U,
2828 4636U, 65U, 7677U, 5504U, 5387U, 6670U, 5666U, 5682U,
2829 8618U, 2261U, 2470U, 7395U, 5262U, 2245U, 5303U, 5279U,
2830 5291U, 1788U, 4564U, 1764U, 4540U, 8435U, 5008U, 4747U,
2831 4694U, 4862U, 4800U, 1840U, 4607U, 1905U, 6533U, 6495U,
2832 8469U, 5042U, 8493U, 5066U, 8564U, 8571U, 2301U, 10380U,
2833 6253U, 11793U, 3858U, 3836U, 3881U, 11424U, 14081U, 1044U,
2834 674U, 856U, 598U, 189U, 829U, 569U, 449U, 1376U,
2835 1163U, 1197U, 1257U, 1137U, 775U, 1403U, 321U, 106U,
2836 217U, 1018U, 134U, 244U, 373U, 1229U, 269U, 398U,
2837 78U, 926U, 162U, 543U, 803U, 1429U, 294U, 346U,
2838 1284U, 973U, 900U, 1108U, 744U, 646U, 1330U, 423U,
2839 7827U, 10945U, 3907U, 4004U, 4280U, 5882U, 9059U, 10037U,
2840 10965U, 10020U, 7811U, 7864U, 7848U, 12188U, 13202U, 8895U,
2841 13318U, 13337U, 8668U, 8841U, 12111U, 13836U, 11699U, 10393U,
2842 13883U, 11746U, 12536U, 13461U, 13622U, 13026U, 13045U, 10504U,
2843 13750U, 6944U, 8202U, 4015U, 7098U, 8336U, 7111U, 8349U,
2844 10886U, 11018U, 10005U, 14128U, 11992U, 10257U, 10339U, 13181U,
2845 3363U, 13064U, 13639U, 10613U, 3302U, 2581U, 10435U, 4171U,
2846 2846U, 11463U, 12427U, 10709U, 12380U, 3744U, 4297U, 2989U,
2847 2967U, 7067U, 7917U, 3473U, 3438U, 4141U, 7948U, 2553U,
2848 2567U, 12665U, 3223U, 3398U, 5931U, 3150U, 5708U, 5735U,
2849 3803U, 3186U, 5827U, 10993U, 14115U, 9030U, 13117U, 13430U,
2850 4249U, 13930U, 10478U, 10189U, 14053U, 10491U, 10200U, 10537U,
2851 8763U, 10837U, 11901U, 13526U, 13937U, 13956U, 10724U, 10739U,
2852 11387U, 13448U, 9917U, 8745U, 6241U, 13760U, 13690U, 11889U,
2853 6914U, 8172U, 13657U, 7125U, 8363U, 9894U, 7007U, 8276U,
2854 10517U, 8224U, 11047U, 11571U, 11154U, 11633U, 11236U, 11301U,
2855 7037U, 8306U, 6860U, 8118U, 11059U, 11589U, 11177U, 11648U,
2856 11256U, 11316U, 1071U, 703U, 1001U, 526U, 954U, 1357U,
2857 883U, 1088U, 722U, 627U, 1312U, 5699U, 5898U, 11943U,
2858 11441U, 9140U, 12461U, 3922U, 10936U, 10463U, 10176U, 12681U,
2859 13238U, 12700U, 10645U, 12896U, 12876U, 11430U, 14087U, 14098U,
2860 5764U, 6135U, 6199U, 13733U, 10274U, 10357U, 8883U, 13824U,
2861 11687U, 5975U, 8930U, 5990U, 5785U, 6155U, 6220U, 11403U,
2862 11088U, 14060U, 13582U, 13472U, 13083U, 1455U, 1486U, 9071U,
2863 12122U, 12576U, 13706U, 13770U, 13130U, 8861U, 13802U, 11665U,
2864 11489U, 8908U, 11511U, 13551U, 9099U, 12149U, 12604U, 12064U,
2865 5855U, 13849U, 11712U, 10115U, 11963U, 12037U, 12548U, 13896U,
2866 11759U, 12789U, 12845U, 13871U, 11734U, 13918U, 11781U, 12916U,
2867 7177U, 8415U, 6936U, 8194U, 11038U, 7029U, 8298U, 11289U,
2868 7163U, 8401U, 6882U, 8140U, 9979U, 12298U, 10895U, 12264U,
2869 12995U, 12745U, 9878U, 12246U, 12725U, 10760U, 9346U, 8811U,
2870 9678U, 9422U, 9622U, 8067U, 9366U, 9742U, 9486U, 9814U,
2871 9558U, 12316U, 10908U, 12278U, 8823U, 9707U, 9451U, 9647U,
2872 9391U, 9775U, 9519U, 9843U, 9587U, 13290U, 12516U, 10576U,
2873 11849U, 11824U, 10565U, 10829U, 11533U, 11007U, 13356U, 8776U,
2874 11456U, 11365U, 12445U, 13606U, 12096U, 10220U, 8854U, 9127U,
2875 11073U, 13532U, 11333U, 12176U, 3949U, 10078U, 4121U, 4202U,
2876 14002U, 12226U, 12645U, 10548U, 10854U, 10163U, 12397U, 11373U,
2877 12359U, 8994U, 10156U, 10777U, 10211U, 12090U, 13545U, 8972U,
2878 13153U, 10959U, 6123U, 3101U, 3524U, 11807U, 4090U, 8726U,
2879 10819U, 11278U, 11351U, 43U, 5960U, 10246U, 475U, 13401U,
2880 12764U, 12819U, 10227U, 10307U, 4350U, 13416U, 11954U, 10663U,
2881 2947U, 13668U, 7147U, 8385U, 13504U, 12955U, 11541U, 11114U,
2882 11609U, 11202U, 9901U, 8942U, 10527U, 7059U, 8328U, 13511U,
2883 12968U, 9952U, 7931U, 7081U, 4371U, 9154U, 9250U, 9186U,
2884 9282U, 9218U, 9314U, 9170U, 9266U, 9202U, 9298U, 9234U,
2885 9330U, 10061U, 12934U, 6966U, 8235U, 6890U, 8148U, 6986U,
2886 8255U, 13225U, 10802U, 9908U, 9012U, 11871U, 13275U, 10589U,
2887 3264U, 10415U, 12020U, 10690U, 10407U, 6922U, 8180U, 7133U,
2888 8371U, 7015U, 8284U, 7045U, 8314U, 6868U, 8126U, 10877U,
2889 3123U, 3968U, 3575U, 3772U, 3547U, 3076U, 3718U, 3046U,
2890 3687U, 3011U, 3651U, 3611U, 4038U, 3501U, 4065U, 4223U,
2891 10927U, 10451U, 8037U, 14041U, 11478U, 6264U, 8092U, 13371U,
2892 13389U, 13014U, 12481U, 11928U, 9967U, 13265U, 13969U, 12340U,
2893 10677U, 10296U, 9987U, 12502U, 10633U, 8795U, 14022U, 9933U,
2894 12413U, 13168U, 3336U, 6175U, 12632U, 7793U, 9048U, 13679U,
2895 7155U, 8393U, 13519U, 12982U, 11556U, 11134U, 11621U, 11219U,
2896 6958U, 8216U, 8957U, 10811U, 8982U, 10090U, 6005U, 6291U,
2897 6091U, 6056U, 5910U, 6029U, 5806U, 10104U, 4323U, 8681U,
2898 8704U, 10140U, 13982U, 12206U, 10327U, 500U,
2899};
2900
2901static inline void InitSPIRVMCInstrInfo(MCInstrInfo *II) {
2902 II->InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 862, nullptr, 0);
2903}
2904
2905
2906} // namespace llvm
2907
2908#endif // GET_INSTRINFO_MC_DESC
2909
2910#ifdef GET_INSTRINFO_HEADER
2911#undef GET_INSTRINFO_HEADER
2912
2913namespace llvm {
2914
2915struct SPIRVGenInstrInfo : public TargetInstrInfo {
2916 explicit SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2917 ~SPIRVGenInstrInfo() override = default;
2918};
2919
2920} // namespace llvm
2921
2922namespace llvm::SPIRV {
2923
2924
2925} // namespace llvm::SPIRV
2926
2927#endif // GET_INSTRINFO_HEADER
2928
2929#ifdef GET_INSTRINFO_HELPER_DECLS
2930#undef GET_INSTRINFO_HELPER_DECLS
2931
2932
2933#endif // GET_INSTRINFO_HELPER_DECLS
2934
2935#ifdef GET_INSTRINFO_HELPERS
2936#undef GET_INSTRINFO_HELPERS
2937
2938
2939#endif // GET_INSTRINFO_HELPERS
2940
2941#ifdef GET_INSTRINFO_CTOR_DTOR
2942#undef GET_INSTRINFO_CTOR_DTOR
2943
2944namespace llvm {
2945
2946extern const SPIRVInstrTable SPIRVDescs;
2947extern const unsigned SPIRVInstrNameIndices[];
2948extern const char SPIRVInstrNameData[];
2949SPIRVGenInstrInfo::SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2950 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2951 InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 862);
2952}
2953
2954} // namespace llvm
2955
2956#endif // GET_INSTRINFO_CTOR_DTOR
2957
2958#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2959#undef GET_INSTRINFO_MC_HELPER_DECLS
2960
2961namespace llvm {
2962
2963class MCInst;
2964class FeatureBitset;
2965
2966namespace SPIRV_MC {
2967
2968void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2969
2970} // namespace SPIRV_MC
2971
2972} // namespace llvm
2973
2974#endif // GET_INSTRINFO_MC_HELPER_DECLS
2975
2976#ifdef GET_INSTRINFO_MC_HELPERS
2977#undef GET_INSTRINFO_MC_HELPERS
2978
2979namespace llvm::SPIRV_MC {
2980
2981
2982} // namespace llvm::SPIRV_MC
2983
2984#endif // GET_INSTRINFO_MC_HELPERS
2985
2986#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2987 defined(GET_AVAILABLE_OPCODE_CHECKER)
2988#define GET_COMPUTE_FEATURES
2989#endif
2990#ifdef GET_COMPUTE_FEATURES
2991#undef GET_COMPUTE_FEATURES
2992
2993namespace llvm::SPIRV_MC {
2994
2995// Bits for subtarget features that participate in instruction matching.
2996enum SubtargetFeatureBits : uint8_t {
2997};
2998
2999inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3000 FeatureBitset Features;
3001 return Features;
3002}
3003
3004inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3005 enum : uint8_t {
3006 CEFBS_None,
3007 };
3008
3009 static constexpr FeatureBitset FeatureBitsets[] = {
3010 {}, // CEFBS_None
3011 };
3012 static constexpr uint8_t RequiredFeaturesRefs[] = {
3013 CEFBS_None, // PHI
3014 CEFBS_None, // INLINEASM
3015 CEFBS_None, // INLINEASM_BR
3016 CEFBS_None, // CFI_INSTRUCTION
3017 CEFBS_None, // EH_LABEL
3018 CEFBS_None, // GC_LABEL
3019 CEFBS_None, // ANNOTATION_LABEL
3020 CEFBS_None, // KILL
3021 CEFBS_None, // EXTRACT_SUBREG
3022 CEFBS_None, // INSERT_SUBREG
3023 CEFBS_None, // IMPLICIT_DEF
3024 CEFBS_None, // INIT_UNDEF
3025 CEFBS_None, // SUBREG_TO_REG
3026 CEFBS_None, // COPY_TO_REGCLASS
3027 CEFBS_None, // DBG_VALUE
3028 CEFBS_None, // DBG_VALUE_LIST
3029 CEFBS_None, // DBG_INSTR_REF
3030 CEFBS_None, // DBG_PHI
3031 CEFBS_None, // DBG_LABEL
3032 CEFBS_None, // REG_SEQUENCE
3033 CEFBS_None, // COPY
3034 CEFBS_None, // COPY_LANEMASK
3035 CEFBS_None, // BUNDLE
3036 CEFBS_None, // LIFETIME_START
3037 CEFBS_None, // LIFETIME_END
3038 CEFBS_None, // PSEUDO_PROBE
3039 CEFBS_None, // ARITH_FENCE
3040 CEFBS_None, // STACKMAP
3041 CEFBS_None, // FENTRY_CALL
3042 CEFBS_None, // PATCHPOINT
3043 CEFBS_None, // LOAD_STACK_GUARD
3044 CEFBS_None, // PREALLOCATED_SETUP
3045 CEFBS_None, // PREALLOCATED_ARG
3046 CEFBS_None, // STATEPOINT
3047 CEFBS_None, // LOCAL_ESCAPE
3048 CEFBS_None, // FAULTING_OP
3049 CEFBS_None, // PATCHABLE_OP
3050 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
3051 CEFBS_None, // PATCHABLE_RET
3052 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
3053 CEFBS_None, // PATCHABLE_TAIL_CALL
3054 CEFBS_None, // PATCHABLE_EVENT_CALL
3055 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
3056 CEFBS_None, // ICALL_BRANCH_FUNNEL
3057 CEFBS_None, // FAKE_USE
3058 CEFBS_None, // MEMBARRIER
3059 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
3060 CEFBS_None, // RELOC_NONE
3061 CEFBS_None, // CONVERGENCECTRL_ENTRY
3062 CEFBS_None, // CONVERGENCECTRL_ANCHOR
3063 CEFBS_None, // CONVERGENCECTRL_LOOP
3064 CEFBS_None, // CONVERGENCECTRL_GLUE
3065 CEFBS_None, // G_ASSERT_SEXT
3066 CEFBS_None, // G_ASSERT_ZEXT
3067 CEFBS_None, // G_ASSERT_ALIGN
3068 CEFBS_None, // G_ADD
3069 CEFBS_None, // G_SUB
3070 CEFBS_None, // G_MUL
3071 CEFBS_None, // G_SDIV
3072 CEFBS_None, // G_UDIV
3073 CEFBS_None, // G_SREM
3074 CEFBS_None, // G_UREM
3075 CEFBS_None, // G_SDIVREM
3076 CEFBS_None, // G_UDIVREM
3077 CEFBS_None, // G_AND
3078 CEFBS_None, // G_OR
3079 CEFBS_None, // G_XOR
3080 CEFBS_None, // G_ABDS
3081 CEFBS_None, // G_ABDU
3082 CEFBS_None, // G_UAVGFLOOR
3083 CEFBS_None, // G_UAVGCEIL
3084 CEFBS_None, // G_SAVGFLOOR
3085 CEFBS_None, // G_SAVGCEIL
3086 CEFBS_None, // G_IMPLICIT_DEF
3087 CEFBS_None, // G_PHI
3088 CEFBS_None, // G_FRAME_INDEX
3089 CEFBS_None, // G_GLOBAL_VALUE
3090 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3091 CEFBS_None, // G_CONSTANT_POOL
3092 CEFBS_None, // G_EXTRACT
3093 CEFBS_None, // G_UNMERGE_VALUES
3094 CEFBS_None, // G_INSERT
3095 CEFBS_None, // G_MERGE_VALUES
3096 CEFBS_None, // G_BUILD_VECTOR
3097 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3098 CEFBS_None, // G_CONCAT_VECTORS
3099 CEFBS_None, // G_PTRTOINT
3100 CEFBS_None, // G_INTTOPTR
3101 CEFBS_None, // G_BITCAST
3102 CEFBS_None, // G_FREEZE
3103 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3104 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3105 CEFBS_None, // G_INTRINSIC_TRUNC
3106 CEFBS_None, // G_INTRINSIC_ROUND
3107 CEFBS_None, // G_INTRINSIC_LRINT
3108 CEFBS_None, // G_INTRINSIC_LLRINT
3109 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3110 CEFBS_None, // G_READCYCLECOUNTER
3111 CEFBS_None, // G_READSTEADYCOUNTER
3112 CEFBS_None, // G_LOAD
3113 CEFBS_None, // G_SEXTLOAD
3114 CEFBS_None, // G_ZEXTLOAD
3115 CEFBS_None, // G_FPEXTLOAD
3116 CEFBS_None, // G_INDEXED_LOAD
3117 CEFBS_None, // G_INDEXED_SEXTLOAD
3118 CEFBS_None, // G_INDEXED_ZEXTLOAD
3119 CEFBS_None, // G_STORE
3120 CEFBS_None, // G_FPTRUNCSTORE
3121 CEFBS_None, // G_INDEXED_STORE
3122 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3123 CEFBS_None, // G_ATOMIC_CMPXCHG
3124 CEFBS_None, // G_ATOMICRMW_XCHG
3125 CEFBS_None, // G_ATOMICRMW_ADD
3126 CEFBS_None, // G_ATOMICRMW_SUB
3127 CEFBS_None, // G_ATOMICRMW_AND
3128 CEFBS_None, // G_ATOMICRMW_NAND
3129 CEFBS_None, // G_ATOMICRMW_OR
3130 CEFBS_None, // G_ATOMICRMW_XOR
3131 CEFBS_None, // G_ATOMICRMW_MAX
3132 CEFBS_None, // G_ATOMICRMW_MIN
3133 CEFBS_None, // G_ATOMICRMW_UMAX
3134 CEFBS_None, // G_ATOMICRMW_UMIN
3135 CEFBS_None, // G_ATOMICRMW_FADD
3136 CEFBS_None, // G_ATOMICRMW_FSUB
3137 CEFBS_None, // G_ATOMICRMW_FMAX
3138 CEFBS_None, // G_ATOMICRMW_FMIN
3139 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3140 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3141 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
3142 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
3143 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3144 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3145 CEFBS_None, // G_ATOMICRMW_USUB_COND
3146 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3147 CEFBS_None, // G_FENCE
3148 CEFBS_None, // G_PREFETCH
3149 CEFBS_None, // G_BRCOND
3150 CEFBS_None, // G_BRINDIRECT
3151 CEFBS_None, // G_INVOKE_REGION_START
3152 CEFBS_None, // G_INTRINSIC
3153 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3154 CEFBS_None, // G_INTRINSIC_CONVERGENT
3155 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3156 CEFBS_None, // G_ANYEXT
3157 CEFBS_None, // G_TRUNC
3158 CEFBS_None, // G_TRUNC_SSAT_S
3159 CEFBS_None, // G_TRUNC_SSAT_U
3160 CEFBS_None, // G_TRUNC_USAT_U
3161 CEFBS_None, // G_CONSTANT
3162 CEFBS_None, // G_FCONSTANT
3163 CEFBS_None, // G_VASTART
3164 CEFBS_None, // G_VAARG
3165 CEFBS_None, // G_SEXT
3166 CEFBS_None, // G_SEXT_INREG
3167 CEFBS_None, // G_ZEXT
3168 CEFBS_None, // G_SHL
3169 CEFBS_None, // G_LSHR
3170 CEFBS_None, // G_ASHR
3171 CEFBS_None, // G_FSHL
3172 CEFBS_None, // G_FSHR
3173 CEFBS_None, // G_ROTR
3174 CEFBS_None, // G_ROTL
3175 CEFBS_None, // G_ICMP
3176 CEFBS_None, // G_FCMP
3177 CEFBS_None, // G_SCMP
3178 CEFBS_None, // G_UCMP
3179 CEFBS_None, // G_SELECT
3180 CEFBS_None, // G_UADDO
3181 CEFBS_None, // G_UADDE
3182 CEFBS_None, // G_USUBO
3183 CEFBS_None, // G_USUBE
3184 CEFBS_None, // G_SADDO
3185 CEFBS_None, // G_SADDE
3186 CEFBS_None, // G_SSUBO
3187 CEFBS_None, // G_SSUBE
3188 CEFBS_None, // G_UMULO
3189 CEFBS_None, // G_SMULO
3190 CEFBS_None, // G_UMULH
3191 CEFBS_None, // G_SMULH
3192 CEFBS_None, // G_UADDSAT
3193 CEFBS_None, // G_SADDSAT
3194 CEFBS_None, // G_USUBSAT
3195 CEFBS_None, // G_SSUBSAT
3196 CEFBS_None, // G_USHLSAT
3197 CEFBS_None, // G_SSHLSAT
3198 CEFBS_None, // G_SMULFIX
3199 CEFBS_None, // G_UMULFIX
3200 CEFBS_None, // G_SMULFIXSAT
3201 CEFBS_None, // G_UMULFIXSAT
3202 CEFBS_None, // G_SDIVFIX
3203 CEFBS_None, // G_UDIVFIX
3204 CEFBS_None, // G_SDIVFIXSAT
3205 CEFBS_None, // G_UDIVFIXSAT
3206 CEFBS_None, // G_FADD
3207 CEFBS_None, // G_FSUB
3208 CEFBS_None, // G_FMUL
3209 CEFBS_None, // G_FMA
3210 CEFBS_None, // G_FMAD
3211 CEFBS_None, // G_FDIV
3212 CEFBS_None, // G_FREM
3213 CEFBS_None, // G_FMODF
3214 CEFBS_None, // G_FPOW
3215 CEFBS_None, // G_FPOWI
3216 CEFBS_None, // G_FEXP
3217 CEFBS_None, // G_FEXP2
3218 CEFBS_None, // G_FEXP10
3219 CEFBS_None, // G_FLOG
3220 CEFBS_None, // G_FLOG2
3221 CEFBS_None, // G_FLOG10
3222 CEFBS_None, // G_FLDEXP
3223 CEFBS_None, // G_FFREXP
3224 CEFBS_None, // G_FNEG
3225 CEFBS_None, // G_FPEXT
3226 CEFBS_None, // G_FPTRUNC
3227 CEFBS_None, // G_FPTOSI
3228 CEFBS_None, // G_FPTOUI
3229 CEFBS_None, // G_SITOFP
3230 CEFBS_None, // G_UITOFP
3231 CEFBS_None, // G_FPTOSI_SAT
3232 CEFBS_None, // G_FPTOUI_SAT
3233 CEFBS_None, // G_FABS
3234 CEFBS_None, // G_FCOPYSIGN
3235 CEFBS_None, // G_IS_FPCLASS
3236 CEFBS_None, // G_FCANONICALIZE
3237 CEFBS_None, // G_FMINNUM
3238 CEFBS_None, // G_FMAXNUM
3239 CEFBS_None, // G_FMINNUM_IEEE
3240 CEFBS_None, // G_FMAXNUM_IEEE
3241 CEFBS_None, // G_FMINIMUM
3242 CEFBS_None, // G_FMAXIMUM
3243 CEFBS_None, // G_FMINIMUMNUM
3244 CEFBS_None, // G_FMAXIMUMNUM
3245 CEFBS_None, // G_GET_FPENV
3246 CEFBS_None, // G_SET_FPENV
3247 CEFBS_None, // G_RESET_FPENV
3248 CEFBS_None, // G_GET_FPMODE
3249 CEFBS_None, // G_SET_FPMODE
3250 CEFBS_None, // G_RESET_FPMODE
3251 CEFBS_None, // G_GET_ROUNDING
3252 CEFBS_None, // G_SET_ROUNDING
3253 CEFBS_None, // G_PTR_ADD
3254 CEFBS_None, // G_PTRMASK
3255 CEFBS_None, // G_SMIN
3256 CEFBS_None, // G_SMAX
3257 CEFBS_None, // G_UMIN
3258 CEFBS_None, // G_UMAX
3259 CEFBS_None, // G_ABS
3260 CEFBS_None, // G_LROUND
3261 CEFBS_None, // G_LLROUND
3262 CEFBS_None, // G_BR
3263 CEFBS_None, // G_BRJT
3264 CEFBS_None, // G_VSCALE
3265 CEFBS_None, // G_INSERT_SUBVECTOR
3266 CEFBS_None, // G_EXTRACT_SUBVECTOR
3267 CEFBS_None, // G_INSERT_VECTOR_ELT
3268 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3269 CEFBS_None, // G_SHUFFLE_VECTOR
3270 CEFBS_None, // G_SPLAT_VECTOR
3271 CEFBS_None, // G_STEP_VECTOR
3272 CEFBS_None, // G_VECTOR_COMPRESS
3273 CEFBS_None, // G_CTTZ
3274 CEFBS_None, // G_CTTZ_ZERO_POISON
3275 CEFBS_None, // G_CTLZ
3276 CEFBS_None, // G_CTLZ_ZERO_POISON
3277 CEFBS_None, // G_CTLS
3278 CEFBS_None, // G_CTPOP
3279 CEFBS_None, // G_BSWAP
3280 CEFBS_None, // G_BITREVERSE
3281 CEFBS_None, // G_CLMUL
3282 CEFBS_None, // G_CLMULH
3283 CEFBS_None, // G_FCEIL
3284 CEFBS_None, // G_FCOS
3285 CEFBS_None, // G_FSIN
3286 CEFBS_None, // G_FSINCOS
3287 CEFBS_None, // G_FTAN
3288 CEFBS_None, // G_FACOS
3289 CEFBS_None, // G_FASIN
3290 CEFBS_None, // G_FATAN
3291 CEFBS_None, // G_FATAN2
3292 CEFBS_None, // G_FCOSH
3293 CEFBS_None, // G_FSINH
3294 CEFBS_None, // G_FTANH
3295 CEFBS_None, // G_FSQRT
3296 CEFBS_None, // G_FFLOOR
3297 CEFBS_None, // G_FRINT
3298 CEFBS_None, // G_FNEARBYINT
3299 CEFBS_None, // G_ADDRSPACE_CAST
3300 CEFBS_None, // G_BLOCK_ADDR
3301 CEFBS_None, // G_JUMP_TABLE
3302 CEFBS_None, // G_DYN_STACKALLOC
3303 CEFBS_None, // G_STACKSAVE
3304 CEFBS_None, // G_STACKRESTORE
3305 CEFBS_None, // G_STRICT_FADD
3306 CEFBS_None, // G_STRICT_FSUB
3307 CEFBS_None, // G_STRICT_FMUL
3308 CEFBS_None, // G_STRICT_FDIV
3309 CEFBS_None, // G_STRICT_FREM
3310 CEFBS_None, // G_STRICT_FMA
3311 CEFBS_None, // G_STRICT_FSQRT
3312 CEFBS_None, // G_STRICT_FLDEXP
3313 CEFBS_None, // G_STRICT_FCMP
3314 CEFBS_None, // G_STRICT_FCMPS
3315 CEFBS_None, // G_READ_REGISTER
3316 CEFBS_None, // G_WRITE_REGISTER
3317 CEFBS_None, // G_MEMCPY
3318 CEFBS_None, // G_MEMCPY_INLINE
3319 CEFBS_None, // G_MEMMOVE
3320 CEFBS_None, // G_MEMSET
3321 CEFBS_None, // G_BZERO
3322 CEFBS_None, // G_MEMSET_INLINE
3323 CEFBS_None, // G_TRAP
3324 CEFBS_None, // G_DEBUGTRAP
3325 CEFBS_None, // G_UBSANTRAP
3326 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3327 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3328 CEFBS_None, // G_VECREDUCE_FADD
3329 CEFBS_None, // G_VECREDUCE_FMUL
3330 CEFBS_None, // G_VECREDUCE_FMAX
3331 CEFBS_None, // G_VECREDUCE_FMIN
3332 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3333 CEFBS_None, // G_VECREDUCE_FMINIMUM
3334 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
3335 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
3336 CEFBS_None, // G_VECREDUCE_ADD
3337 CEFBS_None, // G_VECREDUCE_MUL
3338 CEFBS_None, // G_VECREDUCE_AND
3339 CEFBS_None, // G_VECREDUCE_OR
3340 CEFBS_None, // G_VECREDUCE_XOR
3341 CEFBS_None, // G_VECREDUCE_SMAX
3342 CEFBS_None, // G_VECREDUCE_SMIN
3343 CEFBS_None, // G_VECREDUCE_UMAX
3344 CEFBS_None, // G_VECREDUCE_UMIN
3345 CEFBS_None, // G_SBFX
3346 CEFBS_None, // G_UBFX
3347 CEFBS_None, // ASSIGN_TYPE
3348 CEFBS_None, // UNKNOWN_type
3349 CEFBS_None, // OpAbortKHR
3350 CEFBS_None, // OpAccessChain
3351 CEFBS_None, // OpAliasDomainDeclINTEL
3352 CEFBS_None, // OpAliasScopeDeclINTEL
3353 CEFBS_None, // OpAliasScopeListDeclINTEL
3354 CEFBS_None, // OpAll
3355 CEFBS_None, // OpAny
3356 CEFBS_None, // OpArbitraryFloatACosALTERA
3357 CEFBS_None, // OpArbitraryFloatACosPiALTERA
3358 CEFBS_None, // OpArbitraryFloatASinALTERA
3359 CEFBS_None, // OpArbitraryFloatASinPiALTERA
3360 CEFBS_None, // OpArbitraryFloatATan2ALTERA
3361 CEFBS_None, // OpArbitraryFloatATanALTERA
3362 CEFBS_None, // OpArbitraryFloatATanPiALTERA
3363 CEFBS_None, // OpArbitraryFloatAddALTERA
3364 CEFBS_None, // OpArbitraryFloatCastALTERA
3365 CEFBS_None, // OpArbitraryFloatCastFromIntALTERA
3366 CEFBS_None, // OpArbitraryFloatCastToIntALTERA
3367 CEFBS_None, // OpArbitraryFloatCbrtALTERA
3368 CEFBS_None, // OpArbitraryFloatCosALTERA
3369 CEFBS_None, // OpArbitraryFloatCosPiALTERA
3370 CEFBS_None, // OpArbitraryFloatDivALTERA
3371 CEFBS_None, // OpArbitraryFloatEQALTERA
3372 CEFBS_None, // OpArbitraryFloatExp10ALTERA
3373 CEFBS_None, // OpArbitraryFloatExp2ALTERA
3374 CEFBS_None, // OpArbitraryFloatExpALTERA
3375 CEFBS_None, // OpArbitraryFloatExpm1ALTERA
3376 CEFBS_None, // OpArbitraryFloatGEALTERA
3377 CEFBS_None, // OpArbitraryFloatGTALTERA
3378 CEFBS_None, // OpArbitraryFloatHypotALTERA
3379 CEFBS_None, // OpArbitraryFloatLEALTERA
3380 CEFBS_None, // OpArbitraryFloatLTALTERA
3381 CEFBS_None, // OpArbitraryFloatLog10ALTERA
3382 CEFBS_None, // OpArbitraryFloatLog1pALTERA
3383 CEFBS_None, // OpArbitraryFloatLog2ALTERA
3384 CEFBS_None, // OpArbitraryFloatLogALTERA
3385 CEFBS_None, // OpArbitraryFloatMulALTERA
3386 CEFBS_None, // OpArbitraryFloatPowALTERA
3387 CEFBS_None, // OpArbitraryFloatPowNALTERA
3388 CEFBS_None, // OpArbitraryFloatPowRALTERA
3389 CEFBS_None, // OpArbitraryFloatRSqrtALTERA
3390 CEFBS_None, // OpArbitraryFloatRecipALTERA
3391 CEFBS_None, // OpArbitraryFloatSinALTERA
3392 CEFBS_None, // OpArbitraryFloatSinCosALTERA
3393 CEFBS_None, // OpArbitraryFloatSinCosPiALTERA
3394 CEFBS_None, // OpArbitraryFloatSinPiALTERA
3395 CEFBS_None, // OpArbitraryFloatSqrtALTERA
3396 CEFBS_None, // OpArbitraryFloatSubALTERA
3397 CEFBS_None, // OpArithmeticFenceEXT
3398 CEFBS_None, // OpArrayLength
3399 CEFBS_None, // OpAsmCallINTEL
3400 CEFBS_None, // OpAsmINTEL
3401 CEFBS_None, // OpAsmTargetINTEL
3402 CEFBS_None, // OpAssumeTrueKHR
3403 CEFBS_None, // OpAtomicAnd
3404 CEFBS_None, // OpAtomicCompareExchange
3405 CEFBS_None, // OpAtomicCompareExchangeWeak
3406 CEFBS_None, // OpAtomicExchange
3407 CEFBS_None, // OpAtomicFAddEXT
3408 CEFBS_None, // OpAtomicFMaxEXT
3409 CEFBS_None, // OpAtomicFMinEXT
3410 CEFBS_None, // OpAtomicFlagClear
3411 CEFBS_None, // OpAtomicFlagTestAndSet
3412 CEFBS_None, // OpAtomicIAdd
3413 CEFBS_None, // OpAtomicIDecrement
3414 CEFBS_None, // OpAtomicIIncrement
3415 CEFBS_None, // OpAtomicISub
3416 CEFBS_None, // OpAtomicLoad
3417 CEFBS_None, // OpAtomicOr
3418 CEFBS_None, // OpAtomicSMax
3419 CEFBS_None, // OpAtomicSMin
3420 CEFBS_None, // OpAtomicStore
3421 CEFBS_None, // OpAtomicUMax
3422 CEFBS_None, // OpAtomicUMin
3423 CEFBS_None, // OpAtomicXor
3424 CEFBS_None, // OpBitCount
3425 CEFBS_None, // OpBitFieldInsert
3426 CEFBS_None, // OpBitFieldSExtract
3427 CEFBS_None, // OpBitFieldUExtract
3428 CEFBS_None, // OpBitReverse
3429 CEFBS_None, // OpBitcast
3430 CEFBS_None, // OpBitwiseAndS
3431 CEFBS_None, // OpBitwiseAndV
3432 CEFBS_None, // OpBitwiseFunctionINTEL
3433 CEFBS_None, // OpBitwiseOrS
3434 CEFBS_None, // OpBitwiseOrV
3435 CEFBS_None, // OpBitwiseXorS
3436 CEFBS_None, // OpBitwiseXorV
3437 CEFBS_None, // OpBranch
3438 CEFBS_None, // OpBranchConditional
3439 CEFBS_None, // OpBuildNDRange
3440 CEFBS_None, // OpCapability
3441 CEFBS_None, // OpCaptureEventProfilingInfo
3442 CEFBS_None, // OpCommitReadPipe
3443 CEFBS_None, // OpCommitWritePipe
3444 CEFBS_None, // OpCompositeConstruct
3445 CEFBS_None, // OpCompositeConstructContinuedINTEL
3446 CEFBS_None, // OpCompositeExtract
3447 CEFBS_None, // OpCompositeInsert
3448 CEFBS_None, // OpConstantComposite
3449 CEFBS_None, // OpConstantCompositeContinuedINTEL
3450 CEFBS_None, // OpConstantF
3451 CEFBS_None, // OpConstantFalse
3452 CEFBS_None, // OpConstantFunctionPointerINTEL
3453 CEFBS_None, // OpConstantI
3454 CEFBS_None, // OpConstantNull
3455 CEFBS_None, // OpConstantSampler
3456 CEFBS_None, // OpConstantTrue
3457 CEFBS_None, // OpControlBarrier
3458 CEFBS_None, // OpControlBarrierArriveINTEL
3459 CEFBS_None, // OpControlBarrierWaitINTEL
3460 CEFBS_None, // OpConvertBF16ToFINTEL
3461 CEFBS_None, // OpConvertFToBF16INTEL
3462 CEFBS_None, // OpConvertFToS
3463 CEFBS_None, // OpConvertFToU
3464 CEFBS_None, // OpConvertHandleToImageINTEL
3465 CEFBS_None, // OpConvertHandleToSampledImageINTEL
3466 CEFBS_None, // OpConvertHandleToSamplerINTEL
3467 CEFBS_None, // OpConvertPtrToU
3468 CEFBS_None, // OpConvertSToF
3469 CEFBS_None, // OpConvertUToF
3470 CEFBS_None, // OpConvertUToPtr
3471 CEFBS_None, // OpCooperativeMatrixConstructCheckedINTEL
3472 CEFBS_None, // OpCooperativeMatrixGetElementCoordINTEL
3473 CEFBS_None, // OpCooperativeMatrixLengthKHR
3474 CEFBS_None, // OpCooperativeMatrixLoadCheckedINTEL
3475 CEFBS_None, // OpCooperativeMatrixLoadKHR
3476 CEFBS_None, // OpCooperativeMatrixMulAddKHR
3477 CEFBS_None, // OpCooperativeMatrixPrefetchINTEL
3478 CEFBS_None, // OpCooperativeMatrixStoreCheckedINTEL
3479 CEFBS_None, // OpCooperativeMatrixStoreKHR
3480 CEFBS_None, // OpCopyLogical
3481 CEFBS_None, // OpCopyMemory
3482 CEFBS_None, // OpCopyMemorySized
3483 CEFBS_None, // OpCopyObject
3484 CEFBS_None, // OpCreateUserEvent
3485 CEFBS_None, // OpCrossWorkgroupCastToPtrINTEL
3486 CEFBS_None, // OpDPdx
3487 CEFBS_None, // OpDPdxCoarse
3488 CEFBS_None, // OpDPdxFine
3489 CEFBS_None, // OpDPdy
3490 CEFBS_None, // OpDPdyCoarse
3491 CEFBS_None, // OpDPdyFine
3492 CEFBS_None, // OpDecorate
3493 CEFBS_None, // OpDecorateId
3494 CEFBS_None, // OpDecorateString
3495 CEFBS_None, // OpDemoteToHelperInvocation
3496 CEFBS_None, // OpDot
3497 CEFBS_None, // OpEmitStreamVertex
3498 CEFBS_None, // OpEmitVertex
3499 CEFBS_None, // OpEndPrimitive
3500 CEFBS_None, // OpEndStreamPrimitive
3501 CEFBS_None, // OpEnqueueKernel
3502 CEFBS_None, // OpEntryPoint
3503 CEFBS_None, // OpExecutionMode
3504 CEFBS_None, // OpExecutionModeId
3505 CEFBS_None, // OpExpectKHR
3506 CEFBS_None, // OpExtInst
3507 CEFBS_None, // OpExtInstImport
3508 CEFBS_None, // OpExtension
3509 CEFBS_None, // OpFAddS
3510 CEFBS_None, // OpFAddV
3511 CEFBS_None, // OpFConvert
3512 CEFBS_None, // OpFDivS
3513 CEFBS_None, // OpFDivV
3514 CEFBS_None, // OpFMod
3515 CEFBS_None, // OpFMulS
3516 CEFBS_None, // OpFMulV
3517 CEFBS_None, // OpFNegate
3518 CEFBS_None, // OpFNegateV
3519 CEFBS_None, // OpFOrdEqual
3520 CEFBS_None, // OpFOrdGreaterThan
3521 CEFBS_None, // OpFOrdGreaterThanEqual
3522 CEFBS_None, // OpFOrdLessThan
3523 CEFBS_None, // OpFOrdLessThanEqual
3524 CEFBS_None, // OpFOrdNotEqual
3525 CEFBS_None, // OpFRemS
3526 CEFBS_None, // OpFRemV
3527 CEFBS_None, // OpFSubS
3528 CEFBS_None, // OpFSubV
3529 CEFBS_None, // OpFUnordEqual
3530 CEFBS_None, // OpFUnordGreaterThan
3531 CEFBS_None, // OpFUnordGreaterThanEqual
3532 CEFBS_None, // OpFUnordLessThan
3533 CEFBS_None, // OpFUnordLessThanEqual
3534 CEFBS_None, // OpFUnordNotEqual
3535 CEFBS_None, // OpFixedCosALTERA
3536 CEFBS_None, // OpFixedCosPiALTERA
3537 CEFBS_None, // OpFixedExpALTERA
3538 CEFBS_None, // OpFixedLogALTERA
3539 CEFBS_None, // OpFixedRecipALTERA
3540 CEFBS_None, // OpFixedRsqrtALTERA
3541 CEFBS_None, // OpFixedSinALTERA
3542 CEFBS_None, // OpFixedSinCosALTERA
3543 CEFBS_None, // OpFixedSinCosPiALTERA
3544 CEFBS_None, // OpFixedSinPiALTERA
3545 CEFBS_None, // OpFixedSqrtALTERA
3546 CEFBS_None, // OpFmaKHR
3547 CEFBS_None, // OpFreezeKHR
3548 CEFBS_None, // OpFunction
3549 CEFBS_None, // OpFunctionCall
3550 CEFBS_None, // OpFunctionEnd
3551 CEFBS_None, // OpFunctionParameter
3552 CEFBS_None, // OpFunctionPointerCallINTEL
3553 CEFBS_None, // OpFwidth
3554 CEFBS_None, // OpFwidthCoarse
3555 CEFBS_None, // OpFwidthFine
3556 CEFBS_None, // OpGenericCastToPtr
3557 CEFBS_None, // OpGenericCastToPtrExplicit
3558 CEFBS_None, // OpGenericPtrMemSemantics
3559 CEFBS_None, // OpGetDefaultQueue
3560 CEFBS_None, // OpGetMaxPipePackets
3561 CEFBS_None, // OpGetNumPipePackets
3562 CEFBS_None, // OpGroupAll
3563 CEFBS_None, // OpGroupAny
3564 CEFBS_None, // OpGroupAsyncCopy
3565 CEFBS_None, // OpGroupBitwiseAndKHR
3566 CEFBS_None, // OpGroupBitwiseOrKHR
3567 CEFBS_None, // OpGroupBitwiseXorKHR
3568 CEFBS_None, // OpGroupBroadcast
3569 CEFBS_None, // OpGroupCommitReadPipe
3570 CEFBS_None, // OpGroupCommitWritePipe
3571 CEFBS_None, // OpGroupFAdd
3572 CEFBS_None, // OpGroupFMax
3573 CEFBS_None, // OpGroupFMin
3574 CEFBS_None, // OpGroupFMulKHR
3575 CEFBS_None, // OpGroupIAdd
3576 CEFBS_None, // OpGroupIMulKHR
3577 CEFBS_None, // OpGroupLogicalAndKHR
3578 CEFBS_None, // OpGroupLogicalOrKHR
3579 CEFBS_None, // OpGroupLogicalXorKHR
3580 CEFBS_None, // OpGroupNonUniformAll
3581 CEFBS_None, // OpGroupNonUniformAllEqual
3582 CEFBS_None, // OpGroupNonUniformAny
3583 CEFBS_None, // OpGroupNonUniformBallot
3584 CEFBS_None, // OpGroupNonUniformBallotBitCount
3585 CEFBS_None, // OpGroupNonUniformBallotBitExtract
3586 CEFBS_None, // OpGroupNonUniformBallotFindLSB
3587 CEFBS_None, // OpGroupNonUniformBallotFindMSB
3588 CEFBS_None, // OpGroupNonUniformBitwiseAnd
3589 CEFBS_None, // OpGroupNonUniformBitwiseOr
3590 CEFBS_None, // OpGroupNonUniformBitwiseXor
3591 CEFBS_None, // OpGroupNonUniformBroadcast
3592 CEFBS_None, // OpGroupNonUniformBroadcastFirst
3593 CEFBS_None, // OpGroupNonUniformElect
3594 CEFBS_None, // OpGroupNonUniformFAdd
3595 CEFBS_None, // OpGroupNonUniformFMax
3596 CEFBS_None, // OpGroupNonUniformFMin
3597 CEFBS_None, // OpGroupNonUniformFMul
3598 CEFBS_None, // OpGroupNonUniformIAdd
3599 CEFBS_None, // OpGroupNonUniformIMul
3600 CEFBS_None, // OpGroupNonUniformInverseBallot
3601 CEFBS_None, // OpGroupNonUniformLogicalAnd
3602 CEFBS_None, // OpGroupNonUniformLogicalOr
3603 CEFBS_None, // OpGroupNonUniformLogicalXor
3604 CEFBS_None, // OpGroupNonUniformQuadSwap
3605 CEFBS_None, // OpGroupNonUniformRotateKHR
3606 CEFBS_None, // OpGroupNonUniformSMax
3607 CEFBS_None, // OpGroupNonUniformSMin
3608 CEFBS_None, // OpGroupNonUniformShuffle
3609 CEFBS_None, // OpGroupNonUniformShuffleDown
3610 CEFBS_None, // OpGroupNonUniformShuffleUp
3611 CEFBS_None, // OpGroupNonUniformShuffleXor
3612 CEFBS_None, // OpGroupNonUniformUMax
3613 CEFBS_None, // OpGroupNonUniformUMin
3614 CEFBS_None, // OpGroupReserveReadPipePackets
3615 CEFBS_None, // OpGroupReserveWritePipePackets
3616 CEFBS_None, // OpGroupSMax
3617 CEFBS_None, // OpGroupSMin
3618 CEFBS_None, // OpGroupUMax
3619 CEFBS_None, // OpGroupUMin
3620 CEFBS_None, // OpGroupWaitEvents
3621 CEFBS_None, // OpIAddCarryS
3622 CEFBS_None, // OpIAddCarryV
3623 CEFBS_None, // OpIAddS
3624 CEFBS_None, // OpIAddV
3625 CEFBS_None, // OpIEqual
3626 CEFBS_None, // OpIMulS
3627 CEFBS_None, // OpIMulV
3628 CEFBS_None, // OpINotEqual
3629 CEFBS_None, // OpISubBorrowS
3630 CEFBS_None, // OpISubBorrowV
3631 CEFBS_None, // OpISubS
3632 CEFBS_None, // OpISubV
3633 CEFBS_None, // OpImage
3634 CEFBS_None, // OpImageDrefGather
3635 CEFBS_None, // OpImageFetch
3636 CEFBS_None, // OpImageGather
3637 CEFBS_None, // OpImageQueryFormat
3638 CEFBS_None, // OpImageQueryLevels
3639 CEFBS_None, // OpImageQueryLod
3640 CEFBS_None, // OpImageQueryOrder
3641 CEFBS_None, // OpImageQuerySamples
3642 CEFBS_None, // OpImageQuerySize
3643 CEFBS_None, // OpImageQuerySizeLod
3644 CEFBS_None, // OpImageRead
3645 CEFBS_None, // OpImageSampleDrefExplicitLod
3646 CEFBS_None, // OpImageSampleDrefImplicitLod
3647 CEFBS_None, // OpImageSampleExplicitLod
3648 CEFBS_None, // OpImageSampleFootprintNV
3649 CEFBS_None, // OpImageSampleImplicitLod
3650 CEFBS_None, // OpImageSampleProjDrefExplicitLod
3651 CEFBS_None, // OpImageSampleProjDrefImplicitLod
3652 CEFBS_None, // OpImageSampleProjExplicitLod
3653 CEFBS_None, // OpImageSampleProjImplicitLod
3654 CEFBS_None, // OpImageSparseDrefGather
3655 CEFBS_None, // OpImageSparseFetch
3656 CEFBS_None, // OpImageSparseGather
3657 CEFBS_None, // OpImageSparseRead
3658 CEFBS_None, // OpImageSparseSampleDrefExplicitLod
3659 CEFBS_None, // OpImageSparseSampleDrefImplicitLod
3660 CEFBS_None, // OpImageSparseSampleExplicitLod
3661 CEFBS_None, // OpImageSparseSampleImplicitLod
3662 CEFBS_None, // OpImageSparseSampleProjDrefExplicitLod
3663 CEFBS_None, // OpImageSparseSampleProjDrefImplicitLod
3664 CEFBS_None, // OpImageSparseSampleProjExplicitLod
3665 CEFBS_None, // OpImageSparseSampleProjImplicitLod
3666 CEFBS_None, // OpImageSparseTexelsResident
3667 CEFBS_None, // OpImageTexelPointer
3668 CEFBS_None, // OpImageWrite
3669 CEFBS_None, // OpInBoundsAccessChain
3670 CEFBS_None, // OpInBoundsPtrAccessChain
3671 CEFBS_None, // OpIsFinite
3672 CEFBS_None, // OpIsInf
3673 CEFBS_None, // OpIsNan
3674 CEFBS_None, // OpIsNormal
3675 CEFBS_None, // OpIsValidEvent
3676 CEFBS_None, // OpIsValidReserveId
3677 CEFBS_None, // OpKill
3678 CEFBS_None, // OpLabel
3679 CEFBS_None, // OpLessOrGreater
3680 CEFBS_None, // OpLifetimeStart
3681 CEFBS_None, // OpLifetimeStop
3682 CEFBS_None, // OpLine
3683 CEFBS_None, // OpLoad
3684 CEFBS_None, // OpLogicalAnd
3685 CEFBS_None, // OpLogicalEqual
3686 CEFBS_None, // OpLogicalNot
3687 CEFBS_None, // OpLogicalNotEqual
3688 CEFBS_None, // OpLogicalOr
3689 CEFBS_None, // OpLoopControlINTEL
3690 CEFBS_None, // OpLoopMerge
3691 CEFBS_None, // OpMaskedGatherINTEL
3692 CEFBS_None, // OpMaskedScatterINTEL
3693 CEFBS_None, // OpMatrixTimesMatrix
3694 CEFBS_None, // OpMatrixTimesScalar
3695 CEFBS_None, // OpMatrixTimesVector
3696 CEFBS_None, // OpMemberDecorate
3697 CEFBS_None, // OpMemberDecorateString
3698 CEFBS_None, // OpMemberName
3699 CEFBS_None, // OpMemoryBarrier
3700 CEFBS_None, // OpMemoryModel
3701 CEFBS_None, // OpMemoryNamedBarrier
3702 CEFBS_None, // OpModuleProcessed
3703 CEFBS_None, // OpName
3704 CEFBS_None, // OpNamedBarrierInitialize
3705 CEFBS_None, // OpNoLine
3706 CEFBS_None, // OpNop
3707 CEFBS_None, // OpNot
3708 CEFBS_None, // OpOrdered
3709 CEFBS_None, // OpOuterProduct
3710 CEFBS_None, // OpPhi
3711 CEFBS_None, // OpPoisonKHR
3712 CEFBS_None, // OpPredicatedLoadINTEL
3713 CEFBS_None, // OpPredicatedStoreINTEL
3714 CEFBS_None, // OpPtrAccessChain
3715 CEFBS_None, // OpPtrCastToCrossWorkgroupINTEL
3716 CEFBS_None, // OpPtrCastToGeneric
3717 CEFBS_None, // OpPtrDiff
3718 CEFBS_None, // OpPtrEqual
3719 CEFBS_None, // OpPtrNotEqual
3720 CEFBS_None, // OpQuantizeToF16
3721 CEFBS_None, // OpReadClockKHR
3722 CEFBS_None, // OpReadPipe
3723 CEFBS_None, // OpReadPipeBlockingALTERA
3724 CEFBS_None, // OpReleaseEvent
3725 CEFBS_None, // OpReserveReadPipePackets
3726 CEFBS_None, // OpReserveWritePipePackets
3727 CEFBS_None, // OpReservedReadPipe
3728 CEFBS_None, // OpReservedWritePipe
3729 CEFBS_None, // OpRestoreMemoryINTEL
3730 CEFBS_None, // OpRetainEvent
3731 CEFBS_None, // OpReturn
3732 CEFBS_None, // OpReturnValue
3733 CEFBS_None, // OpRoundFToTF32INTEL
3734 CEFBS_None, // OpSConvert
3735 CEFBS_None, // OpSDivS
3736 CEFBS_None, // OpSDivV
3737 CEFBS_None, // OpSDot
3738 CEFBS_None, // OpSDotAccSat
3739 CEFBS_None, // OpSGreaterThan
3740 CEFBS_None, // OpSGreaterThanEqual
3741 CEFBS_None, // OpSLessThan
3742 CEFBS_None, // OpSLessThanEqual
3743 CEFBS_None, // OpSMod
3744 CEFBS_None, // OpSMulExtended
3745 CEFBS_None, // OpSNegate
3746 CEFBS_None, // OpSRemS
3747 CEFBS_None, // OpSRemV
3748 CEFBS_None, // OpSUDot
3749 CEFBS_None, // OpSUDotAccSat
3750 CEFBS_None, // OpSampledImage
3751 CEFBS_None, // OpSatConvertSToU
3752 CEFBS_None, // OpSatConvertUToS
3753 CEFBS_None, // OpSaveMemoryINTEL
3754 CEFBS_None, // OpSelectSFSCond
3755 CEFBS_None, // OpSelectSFVCond
3756 CEFBS_None, // OpSelectSISCond
3757 CEFBS_None, // OpSelectSIVCond
3758 CEFBS_None, // OpSelectSPSCond
3759 CEFBS_None, // OpSelectSPVCond
3760 CEFBS_None, // OpSelectVFSCond
3761 CEFBS_None, // OpSelectVFVCond
3762 CEFBS_None, // OpSelectVISCond
3763 CEFBS_None, // OpSelectVIVCond
3764 CEFBS_None, // OpSelectVPSCond
3765 CEFBS_None, // OpSelectVPVCond
3766 CEFBS_None, // OpSelectionMerge
3767 CEFBS_None, // OpSetUserEventStatus
3768 CEFBS_None, // OpShiftLeftLogicalS
3769 CEFBS_None, // OpShiftLeftLogicalV
3770 CEFBS_None, // OpShiftRightArithmeticS
3771 CEFBS_None, // OpShiftRightArithmeticV
3772 CEFBS_None, // OpShiftRightLogicalS
3773 CEFBS_None, // OpShiftRightLogicalV
3774 CEFBS_None, // OpSignBitSet
3775 CEFBS_None, // OpSizeOf
3776 CEFBS_None, // OpSource
3777 CEFBS_None, // OpSourceContinued
3778 CEFBS_None, // OpSourceExtension
3779 CEFBS_None, // OpSpecConstant
3780 CEFBS_None, // OpSpecConstantComposite
3781 CEFBS_None, // OpSpecConstantCompositeContinuedINTEL
3782 CEFBS_None, // OpSpecConstantFalse
3783 CEFBS_None, // OpSpecConstantOp
3784 CEFBS_None, // OpSpecConstantTrue
3785 CEFBS_None, // OpStore
3786 CEFBS_None, // OpStrictFAddS
3787 CEFBS_None, // OpStrictFAddV
3788 CEFBS_None, // OpStrictFDivS
3789 CEFBS_None, // OpStrictFDivV
3790 CEFBS_None, // OpStrictFMulS
3791 CEFBS_None, // OpStrictFMulV
3792 CEFBS_None, // OpStrictFRemS
3793 CEFBS_None, // OpStrictFRemV
3794 CEFBS_None, // OpStrictFSubS
3795 CEFBS_None, // OpStrictFSubV
3796 CEFBS_None, // OpString
3797 CEFBS_None, // OpSubgroup2DBlockLoadINTEL
3798 CEFBS_None, // OpSubgroup2DBlockLoadTransformINTEL
3799 CEFBS_None, // OpSubgroup2DBlockLoadTransposeINTEL
3800 CEFBS_None, // OpSubgroup2DBlockPrefetchINTEL
3801 CEFBS_None, // OpSubgroup2DBlockStoreINTEL
3802 CEFBS_None, // OpSubgroupBlockReadINTEL
3803 CEFBS_None, // OpSubgroupBlockWriteINTEL
3804 CEFBS_None, // OpSubgroupImageBlockReadINTEL
3805 CEFBS_None, // OpSubgroupImageBlockWriteINTEL
3806 CEFBS_None, // OpSubgroupImageMediaBlockReadINTEL
3807 CEFBS_None, // OpSubgroupImageMediaBlockWriteINTEL
3808 CEFBS_None, // OpSubgroupMatrixMultiplyAccumulateINTEL
3809 CEFBS_None, // OpSubgroupShuffleDownINTEL
3810 CEFBS_None, // OpSubgroupShuffleINTEL
3811 CEFBS_None, // OpSubgroupShuffleUpINTEL
3812 CEFBS_None, // OpSubgroupShuffleXorINTEL
3813 CEFBS_None, // OpSwitch
3814 CEFBS_None, // OpTranspose
3815 CEFBS_None, // OpTypeAccelerationStructureNV
3816 CEFBS_None, // OpTypeArray
3817 CEFBS_None, // OpTypeBool
3818 CEFBS_None, // OpTypeCooperativeMatrixKHR
3819 CEFBS_None, // OpTypeCooperativeMatrixNV
3820 CEFBS_None, // OpTypeDeviceEvent
3821 CEFBS_None, // OpTypeEvent
3822 CEFBS_None, // OpTypeFloat
3823 CEFBS_None, // OpTypeForwardPointer
3824 CEFBS_None, // OpTypeFunction
3825 CEFBS_None, // OpTypeImage
3826 CEFBS_None, // OpTypeInt
3827 CEFBS_None, // OpTypeMatrix
3828 CEFBS_None, // OpTypeNamedBarrier
3829 CEFBS_None, // OpTypeOpaque
3830 CEFBS_None, // OpTypePipe
3831 CEFBS_None, // OpTypePipeStorage
3832 CEFBS_None, // OpTypePointer
3833 CEFBS_None, // OpTypeQueue
3834 CEFBS_None, // OpTypeReserveId
3835 CEFBS_None, // OpTypeRuntimeArray
3836 CEFBS_None, // OpTypeSampledImage
3837 CEFBS_None, // OpTypeSampler
3838 CEFBS_None, // OpTypeStruct
3839 CEFBS_None, // OpTypeStructContinuedINTEL
3840 CEFBS_None, // OpTypeUntypedPointerKHR
3841 CEFBS_None, // OpTypeVector
3842 CEFBS_None, // OpTypeVectorIdEXT
3843 CEFBS_None, // OpTypeVoid
3844 CEFBS_None, // OpUConvert
3845 CEFBS_None, // OpUDivS
3846 CEFBS_None, // OpUDivV
3847 CEFBS_None, // OpUDot
3848 CEFBS_None, // OpUDotAccSat
3849 CEFBS_None, // OpUGreaterThan
3850 CEFBS_None, // OpUGreaterThanEqual
3851 CEFBS_None, // OpULessThan
3852 CEFBS_None, // OpULessThanEqual
3853 CEFBS_None, // OpUModS
3854 CEFBS_None, // OpUModV
3855 CEFBS_None, // OpUMulExtended
3856 CEFBS_None, // OpUndef
3857 CEFBS_None, // OpUnordered
3858 CEFBS_None, // OpUnreachable
3859 CEFBS_None, // OpUntypedAccessChainKHR
3860 CEFBS_None, // OpUntypedGroupAsyncCopyKHR
3861 CEFBS_None, // OpUntypedInBoundsAccessChainKHR
3862 CEFBS_None, // OpUntypedInBoundsPtrAccessChainKHR
3863 CEFBS_None, // OpUntypedPrefetchKHR
3864 CEFBS_None, // OpUntypedPtrAccessChainKHR
3865 CEFBS_None, // OpUntypedVariableKHR
3866 CEFBS_None, // OpVariable
3867 CEFBS_None, // OpVariableLengthArrayINTEL
3868 CEFBS_None, // OpVectorExtractDynamic
3869 CEFBS_None, // OpVectorInsertDynamic
3870 CEFBS_None, // OpVectorShuffle
3871 CEFBS_None, // OpVectorTimesMatrix
3872 CEFBS_None, // OpVectorTimesScalar
3873 CEFBS_None, // OpWritePipe
3874 CEFBS_None, // OpWritePipeBlockingALTERA
3875 };
3876
3877 assert(Opcode < 862);
3878 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3879}
3880
3881
3882} // namespace llvm::SPIRV_MC
3883
3884#endif // GET_COMPUTE_FEATURES
3885
3886#ifdef GET_AVAILABLE_OPCODE_CHECKER
3887#undef GET_AVAILABLE_OPCODE_CHECKER
3888
3889namespace llvm::SPIRV_MC {
3890
3891bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3892 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3893 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3894 FeatureBitset MissingFeatures =
3895 (AvailableFeatures & RequiredFeatures) ^
3896 RequiredFeatures;
3897 return !MissingFeatures.any();
3898}
3899
3900} // namespace llvm::SPIRV_MC
3901
3902#endif // GET_AVAILABLE_OPCODE_CHECKER
3903
3904#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3905#undef ENABLE_INSTR_PREDICATE_VERIFIER
3906
3907#include <sstream>
3908
3909namespace llvm::SPIRV_MC {
3910
3911#ifndef NDEBUG
3912static const char *SubtargetFeatureNames[] = {
3913 nullptr
3914};
3915
3916#endif // NDEBUG
3917
3918void verifyInstructionPredicates(
3919 unsigned Opcode, const FeatureBitset &Features) {
3920#ifndef NDEBUG
3921 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3922 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3923 FeatureBitset MissingFeatures =
3924 (AvailableFeatures & RequiredFeatures) ^
3925 RequiredFeatures;
3926 if (MissingFeatures.any()) {
3927 std::ostringstream Msg;
3928 Msg << "Attempting to emit " << &SPIRVInstrNameData[SPIRVInstrNameIndices[Opcode]]
3929 << " instruction but the ";
3930 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3931 if (MissingFeatures.test(i))
3932 Msg << SubtargetFeatureNames[i] << " ";
3933 Msg << "predicate(s) are not met";
3934 report_fatal_error(Msg.str().c_str());
3935 }
3936#endif // NDEBUG
3937}
3938
3939} // namespace llvm::SPIRV_MC
3940
3941#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3942
3943