1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SPIRV {
13
14 enum {
15 PHI = 0, // Target.td:1206
16 INLINEASM = 1, // Target.td:1212
17 INLINEASM_BR = 2, // Target.td:1218
18 CFI_INSTRUCTION = 3, // Target.td:1227
19 EH_LABEL = 4, // Target.td:1236
20 GC_LABEL = 5, // Target.td:1245
21 ANNOTATION_LABEL = 6, // Target.td:1254
22 KILL = 7, // Target.td:1262
23 EXTRACT_SUBREG = 8, // Target.td:1269
24 INSERT_SUBREG = 9, // Target.td:1275
25 IMPLICIT_DEF = 10, // Target.td:1282
26 INIT_UNDEF = 11, // Target.td:1291
27 SUBREG_TO_REG = 12, // Target.td:1298
28 COPY_TO_REGCLASS = 13, // Target.td:1304
29 DBG_VALUE = 14, // Target.td:1311
30 DBG_VALUE_LIST = 15, // Target.td:1318
31 DBG_INSTR_REF = 16, // Target.td:1325
32 DBG_PHI = 17, // Target.td:1332
33 DBG_LABEL = 18, // Target.td:1339
34 REG_SEQUENCE = 19, // Target.td:1346
35 COPY = 20, // Target.td:1353
36 COPY_LANEMASK = 21, // Target.td:1361
37 BUNDLE = 22, // Target.td:1368
38 LIFETIME_START = 23, // Target.td:1374
39 LIFETIME_END = 24, // Target.td:1381
40 PSEUDO_PROBE = 25, // Target.td:1388
41 ARITH_FENCE = 26, // Target.td:1395
42 STACKMAP = 27, // Target.td:1404
43 FENTRY_CALL = 28, // Target.td:1539
44 PATCHPOINT = 29, // Target.td:1412
45 LOAD_STACK_GUARD = 30, // Target.td:1430
46 PREALLOCATED_SETUP = 31, // Target.td:1438
47 PREALLOCATED_ARG = 32, // Target.td:1444
48 STATEPOINT = 33, // Target.td:1421
49 LOCAL_ESCAPE = 34, // Target.td:1450
50 FAULTING_OP = 35, // Target.td:1459
51 PATCHABLE_OP = 36, // Target.td:1479
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1487
53 PATCHABLE_RET = 38, // Target.td:1494
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1503
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1511
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1519
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1529
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1549
59 FAKE_USE = 44, // Target.td:1469
60 MEMBARRIER = 45, // Target.td:1555
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1563
62 RELOC_NONE = 47, // Target.td:1571
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1583
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1579
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1587
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1591
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1540
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553
96 G_INSERT = 81, // GenericOpcodes.td:1562
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1572
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340
114 G_LOAD = 99, // GenericOpcodes.td:1367
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1376
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1384
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1393
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420
121 G_STORE = 106, // GenericOpcodes.td:1428
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1446
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502
149 G_FENCE = 134, // GenericOpcodes.td:1518
150 G_PREFETCH = 135, // GenericOpcodes.td:1525
151 G_BRCOND = 136, // GenericOpcodes.td:1665
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1674
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697
154 G_INTRINSIC = 139, // GenericOpcodes.td:1617
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:619
183 G_UADDE = 168, // GenericOpcodes.td:627
184 G_USUBO = 169, // GenericOpcodes.td:649
185 G_USUBE = 170, // GenericOpcodes.td:655
186 G_SADDO = 171, // GenericOpcodes.td:634
187 G_SADDE = 172, // GenericOpcodes.td:642
188 G_SSUBO = 173, // GenericOpcodes.td:662
189 G_SSUBE = 174, // GenericOpcodes.td:669
190 G_UMULO = 175, // GenericOpcodes.td:676
191 G_SMULO = 176, // GenericOpcodes.td:684
192 G_UMULH = 177, // GenericOpcodes.td:693
193 G_SMULH = 178, // GenericOpcodes.td:702
194 G_UADDSAT = 179, // GenericOpcodes.td:714
195 G_SADDSAT = 180, // GenericOpcodes.td:722
196 G_USUBSAT = 181, // GenericOpcodes.td:730
197 G_SSUBSAT = 182, // GenericOpcodes.td:738
198 G_USHLSAT = 183, // GenericOpcodes.td:746
199 G_SSHLSAT = 184, // GenericOpcodes.td:754
200 G_SMULFIX = 185, // GenericOpcodes.td:766
201 G_UMULFIX = 186, // GenericOpcodes.td:773
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:783
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:790
204 G_SDIVFIX = 189, // GenericOpcodes.td:801
205 G_UDIVFIX = 190, // GenericOpcodes.td:808
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:818
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:825
208 G_FADD = 193, // GenericOpcodes.td:998
209 G_FSUB = 194, // GenericOpcodes.td:1006
210 G_FMUL = 195, // GenericOpcodes.td:1014
211 G_FMA = 196, // GenericOpcodes.td:1023
212 G_FMAD = 197, // GenericOpcodes.td:1032
213 G_FDIV = 198, // GenericOpcodes.td:1040
214 G_FREM = 199, // GenericOpcodes.td:1047
215 G_FMODF = 200, // GenericOpcodes.td:1054
216 G_FPOW = 201, // GenericOpcodes.td:1061
217 G_FPOWI = 202, // GenericOpcodes.td:1068
218 G_FEXP = 203, // GenericOpcodes.td:1075
219 G_FEXP2 = 204, // GenericOpcodes.td:1082
220 G_FEXP10 = 205, // GenericOpcodes.td:1089
221 G_FLOG = 206, // GenericOpcodes.td:1096
222 G_FLOG2 = 207, // GenericOpcodes.td:1103
223 G_FLOG10 = 208, // GenericOpcodes.td:1110
224 G_FLDEXP = 209, // GenericOpcodes.td:1117
225 G_FFREXP = 210, // GenericOpcodes.td:1124
226 G_FNEG = 211, // GenericOpcodes.td:836
227 G_FPEXT = 212, // GenericOpcodes.td:842
228 G_FPTRUNC = 213, // GenericOpcodes.td:848
229 G_FPTOSI = 214, // GenericOpcodes.td:854
230 G_FPTOUI = 215, // GenericOpcodes.td:860
231 G_SITOFP = 216, // GenericOpcodes.td:866
232 G_UITOFP = 217, // GenericOpcodes.td:872
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:878
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:884
235 G_FABS = 220, // GenericOpcodes.td:890
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:896
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:909
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:902
239 G_FMINNUM = 224, // GenericOpcodes.td:922
240 G_FMAXNUM = 225, // GenericOpcodes.td:929
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954
243 G_FMINIMUM = 228, // GenericOpcodes.td:964
244 G_FMAXIMUM = 229, // GenericOpcodes.td:971
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:979
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986
247 G_GET_FPENV = 232, // GenericOpcodes.td:1254
248 G_SET_FPENV = 233, // GenericOpcodes.td:1261
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1268
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1275
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1282
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1289
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1346
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1352
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1655
265 G_BRJT = 250, // GenericOpcodes.td:1685
266 G_VSCALE = 251, // GenericOpcodes.td:1583
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1780
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_CLMULR = 270, // GenericOpcodes.td:606
286 G_FCEIL = 271, // GenericOpcodes.td:1131
287 G_FCOS = 272, // GenericOpcodes.td:1138
288 G_FSIN = 273, // GenericOpcodes.td:1145
289 G_FSINCOS = 274, // GenericOpcodes.td:1152
290 G_FTAN = 275, // GenericOpcodes.td:1159
291 G_FACOS = 276, // GenericOpcodes.td:1166
292 G_FASIN = 277, // GenericOpcodes.td:1173
293 G_FATAN = 278, // GenericOpcodes.td:1180
294 G_FATAN2 = 279, // GenericOpcodes.td:1187
295 G_FCOSH = 280, // GenericOpcodes.td:1194
296 G_FSINH = 281, // GenericOpcodes.td:1201
297 G_FTANH = 282, // GenericOpcodes.td:1208
298 G_FSQRT = 283, // GenericOpcodes.td:1218
299 G_FFLOOR = 284, // GenericOpcodes.td:1225
300 G_FRINT = 285, // GenericOpcodes.td:1232
301 G_FNEARBYINT = 286, // GenericOpcodes.td:1239
302 G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248
303 G_BLOCK_ADDR = 288, // GenericOpcodes.td:254
304 G_JUMP_TABLE = 289, // GenericOpcodes.td:260
305 G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266
306 G_STACKSAVE = 291, // GenericOpcodes.td:272
307 G_STACKRESTORE = 292, // GenericOpcodes.td:278
308 G_STRICT_FADD = 293, // GenericOpcodes.td:1839
309 G_STRICT_FSUB = 294, // GenericOpcodes.td:1840
310 G_STRICT_FMUL = 295, // GenericOpcodes.td:1841
311 G_STRICT_FDIV = 296, // GenericOpcodes.td:1842
312 G_STRICT_FREM = 297, // GenericOpcodes.td:1843
313 G_STRICT_FMA = 298, // GenericOpcodes.td:1844
314 G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845
315 G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846
316 G_STRICT_FCMP = 301, // GenericOpcodes.td:1847
317 G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848
318 G_READ_REGISTER = 303, // GenericOpcodes.td:1704
319 G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714
320 G_MEMCPY = 305, // GenericOpcodes.td:1854
321 G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862
322 G_MEMMOVE = 307, // GenericOpcodes.td:1870
323 G_MEMSET = 308, // GenericOpcodes.td:1878
324 G_BZERO = 309, // GenericOpcodes.td:1885
325 G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892
326 G_TRAP = 311, // GenericOpcodes.td:1902
327 G_DEBUGTRAP = 312, // GenericOpcodes.td:1909
328 G_UBSANTRAP = 313, // GenericOpcodes.td:1915
329 G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803
330 G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809
331 G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815
332 G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816
333 G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818
334 G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819
335 G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820
336 G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821
337 G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822
338 G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823
339 G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825
340 G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826
341 G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827
342 G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828
343 G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829
344 G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830
345 G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831
346 G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832
347 G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833
348 G_SBFX = 333, // GenericOpcodes.td:1927
349 G_UBFX = 334, // GenericOpcodes.td:1935
350 ASSIGN_TYPE = 335, // SPIRVInstrInfo.td:18
351 UNKNOWN_type = 336, // SPIRVInstrInfo.td:21
352 OpAbortKHR = 337, // SPIRVInstrInfo.td:684
353 OpAccessChain = 338, // SPIRVInstrInfo.td:277
354 OpAliasDomainDeclINTEL = 339, // SPIRVInstrInfo.td:1011
355 OpAliasScopeDeclINTEL = 340, // SPIRVInstrInfo.td:1013
356 OpAliasScopeListDeclINTEL = 341, // SPIRVInstrInfo.td:1015
357 OpAll = 342, // SPIRVInstrInfo.td:600
358 OpAny = 343, // SPIRVInstrInfo.td:598
359 OpArbitraryFloatACosALTERA = 344, // SPIRVInstrInfo.td:1102
360 OpArbitraryFloatACosPiALTERA = 345, // SPIRVInstrInfo.td:1104
361 OpArbitraryFloatASinALTERA = 346, // SPIRVInstrInfo.td:1098
362 OpArbitraryFloatASinPiALTERA = 347, // SPIRVInstrInfo.td:1100
363 OpArbitraryFloatATan2ALTERA = 348, // SPIRVInstrInfo.td:1110
364 OpArbitraryFloatATanALTERA = 349, // SPIRVInstrInfo.td:1106
365 OpArbitraryFloatATanPiALTERA = 350, // SPIRVInstrInfo.td:1108
366 OpArbitraryFloatAddALTERA = 351, // SPIRVInstrInfo.td:1087
367 OpArbitraryFloatCastALTERA = 352, // SPIRVInstrInfo.td:1118
368 OpArbitraryFloatCastFromIntALTERA = 353, // SPIRVInstrInfo.td:1120
369 OpArbitraryFloatCastToIntALTERA = 354, // SPIRVInstrInfo.td:1122
370 OpArbitraryFloatCbrtALTERA = 355, // SPIRVInstrInfo.td:1036
371 OpArbitraryFloatCosALTERA = 356, // SPIRVInstrInfo.td:1072
372 OpArbitraryFloatCosPiALTERA = 357, // SPIRVInstrInfo.td:1081
373 OpArbitraryFloatDivALTERA = 358, // SPIRVInstrInfo.td:1094
374 OpArbitraryFloatEQALTERA = 359, // SPIRVInstrInfo.td:1031
375 OpArbitraryFloatExp10ALTERA = 360, // SPIRVInstrInfo.td:1063
376 OpArbitraryFloatExp2ALTERA = 361, // SPIRVInstrInfo.td:1060
377 OpArbitraryFloatExpALTERA = 362, // SPIRVInstrInfo.td:1057
378 OpArbitraryFloatExpm1ALTERA = 363, // SPIRVInstrInfo.td:1066
379 OpArbitraryFloatGEALTERA = 364, // SPIRVInstrInfo.td:1025
380 OpArbitraryFloatGTALTERA = 365, // SPIRVInstrInfo.td:1023
381 OpArbitraryFloatHypotALTERA = 366, // SPIRVInstrInfo.td:1039
382 OpArbitraryFloatLEALTERA = 367, // SPIRVInstrInfo.td:1029
383 OpArbitraryFloatLTALTERA = 368, // SPIRVInstrInfo.td:1027
384 OpArbitraryFloatLog10ALTERA = 369, // SPIRVInstrInfo.td:1051
385 OpArbitraryFloatLog1pALTERA = 370, // SPIRVInstrInfo.td:1054
386 OpArbitraryFloatLog2ALTERA = 371, // SPIRVInstrInfo.td:1048
387 OpArbitraryFloatLogALTERA = 372, // SPIRVInstrInfo.td:1045
388 OpArbitraryFloatMulALTERA = 373, // SPIRVInstrInfo.td:1092
389 OpArbitraryFloatPowALTERA = 374, // SPIRVInstrInfo.td:1112
390 OpArbitraryFloatPowNALTERA = 375, // SPIRVInstrInfo.td:1116
391 OpArbitraryFloatPowRALTERA = 376, // SPIRVInstrInfo.td:1114
392 OpArbitraryFloatRSqrtALTERA = 377, // SPIRVInstrInfo.td:1096
393 OpArbitraryFloatRecipALTERA = 378, // SPIRVInstrInfo.td:1033
394 OpArbitraryFloatSinALTERA = 379, // SPIRVInstrInfo.td:1069
395 OpArbitraryFloatSinCosALTERA = 380, // SPIRVInstrInfo.td:1075
396 OpArbitraryFloatSinCosPiALTERA = 381, // SPIRVInstrInfo.td:1084
397 OpArbitraryFloatSinPiALTERA = 382, // SPIRVInstrInfo.td:1078
398 OpArbitraryFloatSqrtALTERA = 383, // SPIRVInstrInfo.td:1042
399 OpArbitraryFloatSubALTERA = 384, // SPIRVInstrInfo.td:1090
400 OpArithmeticFenceEXT = 385, // SPIRVInstrInfo.td:999
401 OpArrayLength = 386, // SPIRVInstrInfo.td:285
402 OpAsmCallINTEL = 387, // SPIRVInstrInfo.td:965
403 OpAsmINTEL = 388, // SPIRVInstrInfo.td:962
404 OpAsmTargetINTEL = 389, // SPIRVInstrInfo.td:961
405 OpAssumeTrueKHR = 390, // SPIRVInstrInfo.td:106
406 OpAtomicAnd = 391, // SPIRVInstrInfo.td:728
407 OpAtomicCompareExchange = 392, // SPIRVInstrInfo.td:708
408 OpAtomicCompareExchangeWeak = 393, // SPIRVInstrInfo.td:712
409 OpAtomicExchange = 394, // SPIRVInstrInfo.td:705
410 OpAtomicFAddEXT = 395, // SPIRVInstrInfo.td:732
411 OpAtomicFMaxEXT = 396, // SPIRVInstrInfo.td:734
412 OpAtomicFMinEXT = 397, // SPIRVInstrInfo.td:733
413 OpAtomicFlagClear = 398, // SPIRVInstrInfo.td:737
414 OpAtomicFlagTestAndSet = 399, // SPIRVInstrInfo.td:736
415 OpAtomicIAdd = 400, // SPIRVInstrInfo.td:720
416 OpAtomicIDecrement = 401, // SPIRVInstrInfo.td:718
417 OpAtomicIIncrement = 402, // SPIRVInstrInfo.td:717
418 OpAtomicISub = 403, // SPIRVInstrInfo.td:721
419 OpAtomicLoad = 404, // SPIRVInstrInfo.td:701
420 OpAtomicOr = 405, // SPIRVInstrInfo.td:729
421 OpAtomicSMax = 406, // SPIRVInstrInfo.td:725
422 OpAtomicSMin = 407, // SPIRVInstrInfo.td:723
423 OpAtomicStore = 408, // SPIRVInstrInfo.td:703
424 OpAtomicUMax = 409, // SPIRVInstrInfo.td:726
425 OpAtomicUMin = 410, // SPIRVInstrInfo.td:724
426 OpAtomicXor = 411, // SPIRVInstrInfo.td:730
427 OpBitCount = 412, // SPIRVInstrInfo.td:594
428 OpBitFieldInsert = 413, // SPIRVInstrInfo.td:584
429 OpBitFieldSExtract = 414, // SPIRVInstrInfo.td:587
430 OpBitFieldUExtract = 415, // SPIRVInstrInfo.td:590
431 OpBitReverse = 416, // SPIRVInstrInfo.td:593
432 OpBitcast = 417, // SPIRVInstrInfo.td:478
433 OpBitwiseAndS = 418, // SPIRVInstrInfo.td:48
434 OpBitwiseAndV = 419, // SPIRVInstrInfo.td:53
435 OpBitwiseFunctionINTEL = 420, // SPIRVInstrInfo.td:1019
436 OpBitwiseOrS = 421, // SPIRVInstrInfo.td:48
437 OpBitwiseOrV = 422, // SPIRVInstrInfo.td:53
438 OpBitwiseXorS = 423, // SPIRVInstrInfo.td:48
439 OpBitwiseXorV = 424, // SPIRVInstrInfo.td:53
440 OpBranch = 425, // SPIRVInstrInfo.td:674
441 OpBranchConditional = 426, // SPIRVInstrInfo.td:675
442 OpBuildNDRange = 427, // SPIRVInstrInfo.td:818
443 OpCapability = 428, // SPIRVInstrInfo.td:167
444 OpCaptureEventProfilingInfo = 429, // SPIRVInstrInfo.td:813
445 OpCommitReadPipe = 430, // SPIRVInstrInfo.td:835
446 OpCommitWritePipe = 431, // SPIRVInstrInfo.td:837
447 OpCompositeConstruct = 432, // SPIRVInstrInfo.td:499
448 OpCompositeConstructContinuedINTEL = 433, // SPIRVInstrInfo.td:501
449 OpCompositeExtract = 434, // SPIRVInstrInfo.td:503
450 OpCompositeInsert = 435, // SPIRVInstrInfo.td:505
451 OpConstantComposite = 436, // SPIRVInstrInfo.td:239
452 OpConstantCompositeContinuedINTEL = 437, // SPIRVInstrInfo.td:241
453 OpConstantF = 438, // SPIRVInstrInfo.td:227
454 OpConstantFalse = 439, // SPIRVInstrInfo.td:236
455 OpConstantFunctionPointerINTEL = 440, // SPIRVInstrInfo.td:917
456 OpConstantI = 441, // SPIRVInstrInfo.td:225
457 OpConstantNull = 442, // SPIRVInstrInfo.td:247
458 OpConstantSampler = 443, // SPIRVInstrInfo.td:244
459 OpConstantTrue = 444, // SPIRVInstrInfo.td:234
460 OpControlBarrier = 445, // SPIRVInstrInfo.td:749
461 OpControlBarrierArriveINTEL = 446, // SPIRVInstrInfo.td:758
462 OpControlBarrierWaitINTEL = 447, // SPIRVInstrInfo.td:760
463 OpConvertBF16ToFINTEL = 448, // SPIRVInstrInfo.td:486
464 OpConvertFToBF16INTEL = 449, // SPIRVInstrInfo.td:485
465 OpConvertFToS = 450, // SPIRVInstrInfo.td:458
466 OpConvertFToU = 451, // SPIRVInstrInfo.td:457
467 OpConvertHandleToImageINTEL = 452, // SPIRVInstrInfo.td:1003
468 OpConvertHandleToSampledImageINTEL = 453, // SPIRVInstrInfo.td:1007
469 OpConvertHandleToSamplerINTEL = 454, // SPIRVInstrInfo.td:1005
470 OpConvertPtrToU = 455, // SPIRVInstrInfo.td:468
471 OpConvertSToF = 456, // SPIRVInstrInfo.td:459
472 OpConvertUToF = 457, // SPIRVInstrInfo.td:460
473 OpConvertUToPtr = 458, // SPIRVInstrInfo.td:473
474 OpCooperativeMatrixConstructCheckedINTEL = 459, // SPIRVInstrInfo.td:988
475 OpCooperativeMatrixGetElementCoordINTEL = 460, // SPIRVInstrInfo.td:991
476 OpCooperativeMatrixLengthKHR = 461, // SPIRVInstrInfo.td:978
477 OpCooperativeMatrixLoadCheckedINTEL = 462, // SPIRVInstrInfo.td:982
478 OpCooperativeMatrixLoadKHR = 463, // SPIRVInstrInfo.td:969
479 OpCooperativeMatrixMulAddKHR = 464, // SPIRVInstrInfo.td:975
480 OpCooperativeMatrixPrefetchINTEL = 465, // SPIRVInstrInfo.td:994
481 OpCooperativeMatrixStoreCheckedINTEL = 466, // SPIRVInstrInfo.td:985
482 OpCooperativeMatrixStoreKHR = 467, // SPIRVInstrInfo.td:972
483 OpCopyLogical = 468, // SPIRVInstrInfo.td:509
484 OpCopyMemory = 469, // SPIRVInstrInfo.td:273
485 OpCopyMemorySized = 470, // SPIRVInstrInfo.td:275
486 OpCopyObject = 471, // SPIRVInstrInfo.td:507
487 OpCreateUserEvent = 472, // SPIRVInstrInfo.td:807
488 OpCrossWorkgroupCastToPtrINTEL = 473, // SPIRVInstrInfo.td:482
489 OpDPdx = 474, // SPIRVInstrInfo.td:650
490 OpDPdxCoarse = 475, // SPIRVInstrInfo.td:658
491 OpDPdxFine = 476, // SPIRVInstrInfo.td:654
492 OpDPdy = 477, // SPIRVInstrInfo.td:651
493 OpDPdyCoarse = 478, // SPIRVInstrInfo.td:659
494 OpDPdyFine = 479, // SPIRVInstrInfo.td:655
495 OpDecorate = 480, // SPIRVInstrInfo.td:128
496 OpDecorateId = 481, // SPIRVInstrInfo.td:136
497 OpDecorateString = 482, // SPIRVInstrInfo.td:138
498 OpDemoteToHelperInvocation = 483, // SPIRVInstrInfo.td:689
499 OpDot = 484, // SPIRVInstrInfo.td:550
500 OpEmitStreamVertex = 485, // SPIRVInstrInfo.td:744
501 OpEmitVertex = 486, // SPIRVInstrInfo.td:742
502 OpEndPrimitive = 487, // SPIRVInstrInfo.td:743
503 OpEndStreamPrimitive = 488, // SPIRVInstrInfo.td:745
504 OpEnqueueKernel = 489, // SPIRVInstrInfo.td:794
505 OpEntryPoint = 490, // SPIRVInstrInfo.td:162
506 OpExecutionMode = 491, // SPIRVInstrInfo.td:165
507 OpExecutionModeId = 492, // SPIRVInstrInfo.td:168
508 OpExpectKHR = 493, // SPIRVInstrInfo.td:107
509 OpExtInst = 494, // SPIRVInstrInfo.td:153
510 OpExtInstImport = 495, // SPIRVInstrInfo.td:147
511 OpExtInstWithForwardRefsKHR = 496, // SPIRVInstrInfo.td:155
512 OpExtension = 497, // SPIRVInstrInfo.td:146
513 OpFAddS = 498, // SPIRVInstrInfo.td:46
514 OpFAddV = 499, // SPIRVInstrInfo.td:51
515 OpFConvert = 500, // SPIRVInstrInfo.td:464
516 OpFDivS = 501, // SPIRVInstrInfo.td:46
517 OpFDivV = 502, // SPIRVInstrInfo.td:51
518 OpFMod = 503, // SPIRVInstrInfo.td:541
519 OpFMulS = 504, // SPIRVInstrInfo.td:46
520 OpFMulV = 505, // SPIRVInstrInfo.td:51
521 OpFNegate = 506, // SPIRVInstrInfo.td:514
522 OpFNegateV = 507, // SPIRVInstrInfo.td:515
523 OpFOrdEqual = 508, // SPIRVInstrInfo.td:633
524 OpFOrdGreaterThan = 509, // SPIRVInstrInfo.td:640
525 OpFOrdGreaterThanEqual = 510, // SPIRVInstrInfo.td:645
526 OpFOrdLessThan = 511, // SPIRVInstrInfo.td:638
527 OpFOrdLessThanEqual = 512, // SPIRVInstrInfo.td:643
528 OpFOrdNotEqual = 513, // SPIRVInstrInfo.td:635
529 OpFRemS = 514, // SPIRVInstrInfo.td:46
530 OpFRemV = 515, // SPIRVInstrInfo.td:51
531 OpFSubS = 516, // SPIRVInstrInfo.td:46
532 OpFSubV = 517, // SPIRVInstrInfo.td:51
533 OpFUnordEqual = 518, // SPIRVInstrInfo.td:634
534 OpFUnordGreaterThan = 519, // SPIRVInstrInfo.td:641
535 OpFUnordGreaterThanEqual = 520, // SPIRVInstrInfo.td:646
536 OpFUnordLessThan = 521, // SPIRVInstrInfo.td:639
537 OpFUnordLessThanEqual = 522, // SPIRVInstrInfo.td:644
538 OpFUnordNotEqual = 523, // SPIRVInstrInfo.td:636
539 OpFixedCosALTERA = 524, // SPIRVInstrInfo.td:1163
540 OpFixedCosPiALTERA = 525, // SPIRVInstrInfo.td:1169
541 OpFixedExpALTERA = 526, // SPIRVInstrInfo.td:1175
542 OpFixedLogALTERA = 527, // SPIRVInstrInfo.td:1173
543 OpFixedRecipALTERA = 528, // SPIRVInstrInfo.td:1157
544 OpFixedRsqrtALTERA = 529, // SPIRVInstrInfo.td:1159
545 OpFixedSinALTERA = 530, // SPIRVInstrInfo.td:1161
546 OpFixedSinCosALTERA = 531, // SPIRVInstrInfo.td:1165
547 OpFixedSinCosPiALTERA = 532, // SPIRVInstrInfo.td:1171
548 OpFixedSinPiALTERA = 533, // SPIRVInstrInfo.td:1167
549 OpFixedSqrtALTERA = 534, // SPIRVInstrInfo.td:1155
550 OpFmaKHR = 535, // SPIRVInstrInfo.td:570
551 OpFreezeKHR = 536, // SPIRVInstrInfo.td:103
552 OpFunction = 537, // SPIRVInstrInfo.td:339
553 OpFunctionCall = 538, // SPIRVInstrInfo.td:347
554 OpFunctionEnd = 539, // SPIRVInstrInfo.td:344
555 OpFunctionParameter = 540, // SPIRVInstrInfo.td:342
556 OpFunctionPointerCallINTEL = 541, // SPIRVInstrInfo.td:922
557 OpFwidth = 542, // SPIRVInstrInfo.td:652
558 OpFwidthCoarse = 543, // SPIRVInstrInfo.td:660
559 OpFwidthFine = 544, // SPIRVInstrInfo.td:656
560 OpGenericCastToPtr = 545, // SPIRVInstrInfo.td:475
561 OpGenericCastToPtrExplicit = 546, // SPIRVInstrInfo.td:476
562 OpGenericPtrMemSemantics = 547, // SPIRVInstrInfo.td:287
563 OpGetDefaultQueue = 548, // SPIRVInstrInfo.td:816
564 OpGetKernelNDrangeMaxSubGroupSize = 549, // SPIRVInstrInfo.td:799
565 OpGetKernelNDrangeSubGroupCount = 550, // SPIRVInstrInfo.td:797
566 OpGetKernelPreferredWorkGroupSizeMultiple = 551, // SPIRVInstrInfo.td:803
567 OpGetKernelWorkGroupSize = 552, // SPIRVInstrInfo.td:801
568 OpGetMaxPipePackets = 553, // SPIRVInstrInfo.td:843
569 OpGetNumPipePackets = 554, // SPIRVInstrInfo.td:841
570 OpGroupAll = 555, // SPIRVInstrInfo.td:770
571 OpGroupAny = 556, // SPIRVInstrInfo.td:772
572 OpGroupAsyncCopy = 557, // SPIRVInstrInfo.td:765
573 OpGroupBitwiseAndKHR = 558, // SPIRVInstrInfo.td:953
574 OpGroupBitwiseOrKHR = 559, // SPIRVInstrInfo.td:954
575 OpGroupBitwiseXorKHR = 560, // SPIRVInstrInfo.td:955
576 OpGroupBroadcast = 561, // SPIRVInstrInfo.td:774
577 OpGroupCommitReadPipe = 562, // SPIRVInstrInfo.td:849
578 OpGroupCommitWritePipe = 563, // SPIRVInstrInfo.td:851
579 OpGroupFAdd = 564, // SPIRVInstrInfo.td:781
580 OpGroupFMax = 565, // SPIRVInstrInfo.td:785
581 OpGroupFMin = 566, // SPIRVInstrInfo.td:782
582 OpGroupFMulKHR = 567, // SPIRVInstrInfo.td:952
583 OpGroupIAdd = 568, // SPIRVInstrInfo.td:780
584 OpGroupIMulKHR = 569, // SPIRVInstrInfo.td:951
585 OpGroupLogicalAndKHR = 570, // SPIRVInstrInfo.td:956
586 OpGroupLogicalOrKHR = 571, // SPIRVInstrInfo.td:957
587 OpGroupLogicalXorKHR = 572, // SPIRVInstrInfo.td:958
588 OpGroupNonUniformAll = 573, // SPIRVInstrInfo.td:864
589 OpGroupNonUniformAllEqual = 574, // SPIRVInstrInfo.td:866
590 OpGroupNonUniformAny = 575, // SPIRVInstrInfo.td:865
591 OpGroupNonUniformBallot = 576, // SPIRVInstrInfo.td:869
592 OpGroupNonUniformBallotBitCount = 577, // SPIRVInstrInfo.td:872
593 OpGroupNonUniformBallotBitExtract = 578, // SPIRVInstrInfo.td:871
594 OpGroupNonUniformBallotFindLSB = 579, // SPIRVInstrInfo.td:876
595 OpGroupNonUniformBallotFindMSB = 580, // SPIRVInstrInfo.td:877
596 OpGroupNonUniformBitwiseAnd = 581, // SPIRVInstrInfo.td:896
597 OpGroupNonUniformBitwiseOr = 582, // SPIRVInstrInfo.td:897
598 OpGroupNonUniformBitwiseXor = 583, // SPIRVInstrInfo.td:898
599 OpGroupNonUniformBroadcast = 584, // SPIRVInstrInfo.td:867
600 OpGroupNonUniformBroadcastFirst = 585, // SPIRVInstrInfo.td:868
601 OpGroupNonUniformElect = 586, // SPIRVInstrInfo.td:856
602 OpGroupNonUniformFAdd = 587, // SPIRVInstrInfo.td:887
603 OpGroupNonUniformFMax = 588, // SPIRVInstrInfo.td:895
604 OpGroupNonUniformFMin = 589, // SPIRVInstrInfo.td:892
605 OpGroupNonUniformFMul = 590, // SPIRVInstrInfo.td:889
606 OpGroupNonUniformIAdd = 591, // SPIRVInstrInfo.td:886
607 OpGroupNonUniformIMul = 592, // SPIRVInstrInfo.td:888
608 OpGroupNonUniformInverseBallot = 593, // SPIRVInstrInfo.td:870
609 OpGroupNonUniformLogicalAnd = 594, // SPIRVInstrInfo.td:899
610 OpGroupNonUniformLogicalOr = 595, // SPIRVInstrInfo.td:900
611 OpGroupNonUniformLogicalXor = 596, // SPIRVInstrInfo.td:901
612 OpGroupNonUniformQuadSwap = 597, // SPIRVInstrInfo.td:902
613 OpGroupNonUniformRotateKHR = 598, // SPIRVInstrInfo.td:905
614 OpGroupNonUniformSMax = 599, // SPIRVInstrInfo.td:893
615 OpGroupNonUniformSMin = 600, // SPIRVInstrInfo.td:890
616 OpGroupNonUniformShuffle = 601, // SPIRVInstrInfo.td:878
617 OpGroupNonUniformShuffleDown = 602, // SPIRVInstrInfo.td:881
618 OpGroupNonUniformShuffleUp = 603, // SPIRVInstrInfo.td:880
619 OpGroupNonUniformShuffleXor = 604, // SPIRVInstrInfo.td:879
620 OpGroupNonUniformUMax = 605, // SPIRVInstrInfo.td:894
621 OpGroupNonUniformUMin = 606, // SPIRVInstrInfo.td:891
622 OpGroupReserveReadPipePackets = 607, // SPIRVInstrInfo.td:845
623 OpGroupReserveWritePipePackets = 608, // SPIRVInstrInfo.td:847
624 OpGroupSMax = 609, // SPIRVInstrInfo.td:787
625 OpGroupSMin = 610, // SPIRVInstrInfo.td:784
626 OpGroupUMax = 611, // SPIRVInstrInfo.td:786
627 OpGroupUMin = 612, // SPIRVInstrInfo.td:783
628 OpGroupWaitEvents = 613, // SPIRVInstrInfo.td:768
629 OpIAddCarryS = 614, // SPIRVInstrInfo.td:48
630 OpIAddCarryV = 615, // SPIRVInstrInfo.td:53
631 OpIAddS = 616, // SPIRVInstrInfo.td:48
632 OpIAddV = 617, // SPIRVInstrInfo.td:53
633 OpIEqual = 618, // SPIRVInstrInfo.td:621
634 OpIMulS = 619, // SPIRVInstrInfo.td:48
635 OpIMulV = 620, // SPIRVInstrInfo.td:53
636 OpINotEqual = 621, // SPIRVInstrInfo.td:622
637 OpISubBorrowS = 622, // SPIRVInstrInfo.td:48
638 OpISubBorrowV = 623, // SPIRVInstrInfo.td:53
639 OpISubS = 624, // SPIRVInstrInfo.td:48
640 OpISubV = 625, // SPIRVInstrInfo.td:53
641 OpImage = 626, // SPIRVInstrInfo.td:398
642 OpImageDrefGather = 627, // SPIRVInstrInfo.td:388
643 OpImageFetch = 628, // SPIRVInstrInfo.td:382
644 OpImageGather = 629, // SPIRVInstrInfo.td:385
645 OpImageQueryFormat = 630, // SPIRVInstrInfo.td:399
646 OpImageQueryLevels = 631, // SPIRVInstrInfo.td:404
647 OpImageQueryLod = 632, // SPIRVInstrInfo.td:403
648 OpImageQueryOrder = 633, // SPIRVInstrInfo.td:400
649 OpImageQuerySamples = 634, // SPIRVInstrInfo.td:405
650 OpImageQuerySize = 635, // SPIRVInstrInfo.td:402
651 OpImageQuerySizeLod = 636, // SPIRVInstrInfo.td:401
652 OpImageRead = 637, // SPIRVInstrInfo.td:392
653 OpImageSampleDrefExplicitLod = 638, // SPIRVInstrInfo.td:364
654 OpImageSampleDrefImplicitLod = 639, // SPIRVInstrInfo.td:361
655 OpImageSampleExplicitLod = 640, // SPIRVInstrInfo.td:357
656 OpImageSampleFootprintNV = 641, // SPIRVInstrInfo.td:451
657 OpImageSampleImplicitLod = 642, // SPIRVInstrInfo.td:354
658 OpImageSampleProjDrefExplicitLod = 643, // SPIRVInstrInfo.td:378
659 OpImageSampleProjDrefImplicitLod = 644, // SPIRVInstrInfo.td:375
660 OpImageSampleProjExplicitLod = 645, // SPIRVInstrInfo.td:371
661 OpImageSampleProjImplicitLod = 646, // SPIRVInstrInfo.td:368
662 OpImageSparseDrefGather = 647, // SPIRVInstrInfo.td:441
663 OpImageSparseFetch = 648, // SPIRVInstrInfo.td:435
664 OpImageSparseGather = 649, // SPIRVInstrInfo.td:438
665 OpImageSparseRead = 650, // SPIRVInstrInfo.td:447
666 OpImageSparseSampleDrefExplicitLod = 651, // SPIRVInstrInfo.td:417
667 OpImageSparseSampleDrefImplicitLod = 652, // SPIRVInstrInfo.td:414
668 OpImageSparseSampleExplicitLod = 653, // SPIRVInstrInfo.td:410
669 OpImageSparseSampleImplicitLod = 654, // SPIRVInstrInfo.td:407
670 OpImageSparseSampleProjDrefExplicitLod = 655, // SPIRVInstrInfo.td:431
671 OpImageSparseSampleProjDrefImplicitLod = 656, // SPIRVInstrInfo.td:428
672 OpImageSparseSampleProjExplicitLod = 657, // SPIRVInstrInfo.td:424
673 OpImageSparseSampleProjImplicitLod = 658, // SPIRVInstrInfo.td:421
674 OpImageSparseTexelsResident = 659, // SPIRVInstrInfo.td:445
675 OpImageTexelPointer = 660, // SPIRVInstrInfo.td:266
676 OpImageWrite = 661, // SPIRVInstrInfo.td:395
677 OpInBoundsAccessChain = 662, // SPIRVInstrInfo.td:279
678 OpInBoundsPtrAccessChain = 663, // SPIRVInstrInfo.td:289
679 OpIsFinite = 664, // SPIRVInstrInfo.td:605
680 OpIsInf = 665, // SPIRVInstrInfo.td:604
681 OpIsNan = 666, // SPIRVInstrInfo.td:603
682 OpIsNormal = 667, // SPIRVInstrInfo.td:606
683 OpIsValidEvent = 668, // SPIRVInstrInfo.td:809
684 OpIsValidReserveId = 669, // SPIRVInstrInfo.td:839
685 OpKill = 670, // SPIRVInstrInfo.td:680
686 OpLabel = 671, // SPIRVInstrInfo.td:672
687 OpLessOrGreater = 672, // SPIRVInstrInfo.td:609
688 OpLifetimeStart = 673, // SPIRVInstrInfo.td:687
689 OpLifetimeStop = 674, // SPIRVInstrInfo.td:688
690 OpLine = 675, // SPIRVInstrInfo.td:121
691 OpLoad = 676, // SPIRVInstrInfo.td:269
692 OpLogicalAnd = 677, // SPIRVInstrInfo.td:616
693 OpLogicalEqual = 678, // SPIRVInstrInfo.td:613
694 OpLogicalNot = 679, // SPIRVInstrInfo.td:617
695 OpLogicalNotEqual = 680, // SPIRVInstrInfo.td:614
696 OpLogicalOr = 681, // SPIRVInstrInfo.td:615
697 OpLoopControlINTEL = 682, // SPIRVInstrInfo.td:668
698 OpLoopMerge = 683, // SPIRVInstrInfo.td:666
699 OpMaskedGatherINTEL = 684, // SPIRVInstrInfo.td:1179
700 OpMaskedScatterINTEL = 685, // SPIRVInstrInfo.td:1181
701 OpMatrixTimesMatrix = 686, // SPIRVInstrInfo.td:547
702 OpMatrixTimesScalar = 687, // SPIRVInstrInfo.td:544
703 OpMatrixTimesVector = 688, // SPIRVInstrInfo.td:546
704 OpMemberDecorate = 689, // SPIRVInstrInfo.td:130
705 OpMemberDecorateString = 690, // SPIRVInstrInfo.td:140
706 OpMemberName = 691, // SPIRVInstrInfo.td:118
707 OpMemoryBarrier = 692, // SPIRVInstrInfo.td:751
708 OpMemoryModel = 693, // SPIRVInstrInfo.td:160
709 OpMemoryNamedBarrier = 694, // SPIRVInstrInfo.td:754
710 OpModuleProcessed = 695, // SPIRVInstrInfo.td:123
711 OpName = 696, // SPIRVInstrInfo.td:117
712 OpNamedBarrierInitialize = 697, // SPIRVInstrInfo.td:753
713 OpNoLine = 698, // SPIRVInstrInfo.td:122
714 OpNop = 699, // SPIRVInstrInfo.td:97
715 OpNot = 700, // SPIRVInstrInfo.td:582
716 OpOrdered = 701, // SPIRVInstrInfo.td:610
717 OpOuterProduct = 702, // SPIRVInstrInfo.td:549
718 OpPhi = 703, // SPIRVInstrInfo.td:664
719 OpPoisonKHR = 704, // SPIRVInstrInfo.td:102
720 OpPredicatedLoadINTEL = 705, // SPIRVInstrInfo.td:1143
721 OpPredicatedStoreINTEL = 706, // SPIRVInstrInfo.td:1145
722 OpPtrAccessChain = 707, // SPIRVInstrInfo.td:282
723 OpPtrCastToCrossWorkgroupINTEL = 708, // SPIRVInstrInfo.td:481
724 OpPtrCastToGeneric = 709, // SPIRVInstrInfo.td:474
725 OpPtrDiff = 710, // SPIRVInstrInfo.td:296
726 OpPtrEqual = 711, // SPIRVInstrInfo.td:292
727 OpPtrNotEqual = 712, // SPIRVInstrInfo.td:294
728 OpQuantizeToF16 = 713, // SPIRVInstrInfo.td:466
729 OpReadClockKHR = 714, // SPIRVInstrInfo.td:910
730 OpReadPipe = 715, // SPIRVInstrInfo.td:823
731 OpReadPipeBlockingALTERA = 716, // SPIRVInstrInfo.td:1149
732 OpReleaseEvent = 717, // SPIRVInstrInfo.td:806
733 OpReserveReadPipePackets = 718, // SPIRVInstrInfo.td:831
734 OpReserveWritePipePackets = 719, // SPIRVInstrInfo.td:833
735 OpReservedReadPipe = 720, // SPIRVInstrInfo.td:827
736 OpReservedWritePipe = 721, // SPIRVInstrInfo.td:829
737 OpRestoreMemoryINTEL = 722, // SPIRVInstrInfo.td:334
738 OpRetainEvent = 723, // SPIRVInstrInfo.td:805
739 OpReturn = 724, // SPIRVInstrInfo.td:681
740 OpReturnValue = 725, // SPIRVInstrInfo.td:682
741 OpRoundFToTF32INTEL = 726, // SPIRVInstrInfo.td:489
742 OpSConvert = 727, // SPIRVInstrInfo.td:463
743 OpSDivS = 728, // SPIRVInstrInfo.td:48
744 OpSDivV = 729, // SPIRVInstrInfo.td:53
745 OpSDot = 730, // SPIRVInstrInfo.td:557
746 OpSDotAccSat = 731, // SPIRVInstrInfo.td:563
747 OpSGreaterThan = 732, // SPIRVInstrInfo.td:625
748 OpSGreaterThanEqual = 733, // SPIRVInstrInfo.td:627
749 OpSLessThan = 734, // SPIRVInstrInfo.td:629
750 OpSLessThanEqual = 735, // SPIRVInstrInfo.td:631
751 OpSMod = 736, // SPIRVInstrInfo.td:536
752 OpSMulExtended = 737, // SPIRVInstrInfo.td:555
753 OpSNegate = 738, // SPIRVInstrInfo.td:513
754 OpSRemS = 739, // SPIRVInstrInfo.td:48
755 OpSRemV = 740, // SPIRVInstrInfo.td:53
756 OpSUDot = 741, // SPIRVInstrInfo.td:561
757 OpSUDotAccSat = 742, // SPIRVInstrInfo.td:567
758 OpSampledImage = 743, // SPIRVInstrInfo.td:352
759 OpSatConvertSToU = 744, // SPIRVInstrInfo.td:470
760 OpSatConvertUToS = 745, // SPIRVInstrInfo.td:471
761 OpSaveMemoryINTEL = 746, // SPIRVInstrInfo.td:332
762 OpSelectSFSCond = 747, // SPIRVInstrInfo.td:67
763 OpSelectSFVCond = 748, // SPIRVInstrInfo.td:68
764 OpSelectSISCond = 749, // SPIRVInstrInfo.td:63
765 OpSelectSIVCond = 750, // SPIRVInstrInfo.td:64
766 OpSelectSPSCond = 751, // SPIRVInstrInfo.td:59
767 OpSelectSPVCond = 752, // SPIRVInstrInfo.td:60
768 OpSelectVFSCond = 753, // SPIRVInstrInfo.td:80
769 OpSelectVFVCond = 754, // SPIRVInstrInfo.td:81
770 OpSelectVISCond = 755, // SPIRVInstrInfo.td:76
771 OpSelectVIVCond = 756, // SPIRVInstrInfo.td:77
772 OpSelectVPSCond = 757, // SPIRVInstrInfo.td:72
773 OpSelectVPVCond = 758, // SPIRVInstrInfo.td:73
774 OpSelectionMerge = 759, // SPIRVInstrInfo.td:670
775 OpSetUserEventStatus = 760, // SPIRVInstrInfo.td:811
776 OpShiftLeftLogicalS = 761, // SPIRVInstrInfo.td:48
777 OpShiftLeftLogicalV = 762, // SPIRVInstrInfo.td:53
778 OpShiftRightArithmeticS = 763, // SPIRVInstrInfo.td:48
779 OpShiftRightArithmeticV = 764, // SPIRVInstrInfo.td:53
780 OpShiftRightLogicalS = 765, // SPIRVInstrInfo.td:48
781 OpShiftRightLogicalV = 766, // SPIRVInstrInfo.td:53
782 OpSignBitSet = 767, // SPIRVInstrInfo.td:607
783 OpSizeOf = 768, // SPIRVInstrInfo.td:99
784 OpSource = 769, // SPIRVInstrInfo.td:113
785 OpSourceContinued = 770, // SPIRVInstrInfo.td:111
786 OpSourceExtension = 771, // SPIRVInstrInfo.td:115
787 OpSpecConstant = 772, // SPIRVInstrInfo.td:251
788 OpSpecConstantComposite = 773, // SPIRVInstrInfo.td:253
789 OpSpecConstantCompositeContinuedINTEL = 774, // SPIRVInstrInfo.td:255
790 OpSpecConstantFalse = 775, // SPIRVInstrInfo.td:250
791 OpSpecConstantOp = 776, // SPIRVInstrInfo.td:259
792 OpSpecConstantTrue = 777, // SPIRVInstrInfo.td:249
793 OpStore = 778, // SPIRVInstrInfo.td:271
794 OpStrictFAddS = 779, // SPIRVInstrInfo.td:46
795 OpStrictFAddV = 780, // SPIRVInstrInfo.td:51
796 OpStrictFDivS = 781, // SPIRVInstrInfo.td:46
797 OpStrictFDivV = 782, // SPIRVInstrInfo.td:51
798 OpStrictFMulS = 783, // SPIRVInstrInfo.td:46
799 OpStrictFMulV = 784, // SPIRVInstrInfo.td:51
800 OpStrictFRemS = 785, // SPIRVInstrInfo.td:46
801 OpStrictFRemV = 786, // SPIRVInstrInfo.td:51
802 OpStrictFSubS = 787, // SPIRVInstrInfo.td:46
803 OpStrictFSubV = 788, // SPIRVInstrInfo.td:51
804 OpString = 789, // SPIRVInstrInfo.td:120
805 OpSubgroup2DBlockLoadINTEL = 790, // SPIRVInstrInfo.td:1126
806 OpSubgroup2DBlockLoadTransformINTEL = 791, // SPIRVInstrInfo.td:1132
807 OpSubgroup2DBlockLoadTransposeINTEL = 792, // SPIRVInstrInfo.td:1129
808 OpSubgroup2DBlockPrefetchINTEL = 793, // SPIRVInstrInfo.td:1135
809 OpSubgroup2DBlockStoreINTEL = 794, // SPIRVInstrInfo.td:1138
810 OpSubgroupBlockReadINTEL = 795, // SPIRVInstrInfo.td:935
811 OpSubgroupBlockWriteINTEL = 796, // SPIRVInstrInfo.td:937
812 OpSubgroupImageBlockReadINTEL = 797, // SPIRVInstrInfo.td:939
813 OpSubgroupImageBlockWriteINTEL = 798, // SPIRVInstrInfo.td:941
814 OpSubgroupImageMediaBlockReadINTEL = 799, // SPIRVInstrInfo.td:945
815 OpSubgroupImageMediaBlockWriteINTEL = 800, // SPIRVInstrInfo.td:947
816 OpSubgroupMatrixMultiplyAccumulateINTEL = 801, // SPIRVInstrInfo.td:789
817 OpSubgroupShuffleDownINTEL = 802, // SPIRVInstrInfo.td:929
818 OpSubgroupShuffleINTEL = 803, // SPIRVInstrInfo.td:927
819 OpSubgroupShuffleUpINTEL = 804, // SPIRVInstrInfo.td:931
820 OpSubgroupShuffleXorINTEL = 805, // SPIRVInstrInfo.td:933
821 OpSwitch = 806, // SPIRVInstrInfo.td:677
822 OpTranspose = 807, // SPIRVInstrInfo.td:508
823 OpTypeAccelerationStructureNV = 808, // SPIRVInstrInfo.td:211
824 OpTypeArray = 809, // SPIRVInstrInfo.td:189
825 OpTypeBool = 810, // SPIRVInstrInfo.td:174
826 OpTypeCooperativeMatrixKHR = 811, // SPIRVInstrInfo.td:216
827 OpTypeCooperativeMatrixNV = 812, // SPIRVInstrInfo.td:213
828 OpTypeDeviceEvent = 813, // SPIRVInstrInfo.td:203
829 OpTypeEvent = 814, // SPIRVInstrInfo.td:202
830 OpTypeFloat = 815, // SPIRVInstrInfo.td:177
831 OpTypeForwardPointer = 816, // SPIRVInstrInfo.td:207
832 OpTypeFunction = 817, // SPIRVInstrInfo.td:200
833 OpTypeImage = 818, // SPIRVInstrInfo.td:183
834 OpTypeInt = 819, // SPIRVInstrInfo.td:175
835 OpTypeMatrix = 820, // SPIRVInstrInfo.td:181
836 OpTypeNamedBarrier = 821, // SPIRVInstrInfo.td:210
837 OpTypeOpaque = 822, // SPIRVInstrInfo.td:196
838 OpTypePipe = 823, // SPIRVInstrInfo.td:206
839 OpTypePipeStorage = 824, // SPIRVInstrInfo.td:209
840 OpTypePointer = 825, // SPIRVInstrInfo.td:198
841 OpTypeQueue = 826, // SPIRVInstrInfo.td:205
842 OpTypeReserveId = 827, // SPIRVInstrInfo.td:204
843 OpTypeRuntimeArray = 828, // SPIRVInstrInfo.td:191
844 OpTypeSampledImage = 829, // SPIRVInstrInfo.td:187
845 OpTypeSampler = 830, // SPIRVInstrInfo.td:186
846 OpTypeStruct = 831, // SPIRVInstrInfo.td:193
847 OpTypeStructContinuedINTEL = 832, // SPIRVInstrInfo.td:194
848 OpTypeUntypedPointerKHR = 833, // SPIRVInstrInfo.td:301
849 OpTypeVector = 834, // SPIRVInstrInfo.td:179
850 OpTypeVectorIdEXT = 835, // SPIRVInstrInfo.td:219
851 OpTypeVoid = 836, // SPIRVInstrInfo.td:173
852 OpUConvert = 837, // SPIRVInstrInfo.td:462
853 OpUDivS = 838, // SPIRVInstrInfo.td:48
854 OpUDivV = 839, // SPIRVInstrInfo.td:53
855 OpUDot = 840, // SPIRVInstrInfo.td:559
856 OpUDotAccSat = 841, // SPIRVInstrInfo.td:565
857 OpUGreaterThan = 842, // SPIRVInstrInfo.td:624
858 OpUGreaterThanEqual = 843, // SPIRVInstrInfo.td:626
859 OpULessThan = 844, // SPIRVInstrInfo.td:628
860 OpULessThanEqual = 845, // SPIRVInstrInfo.td:630
861 OpUModS = 846, // SPIRVInstrInfo.td:48
862 OpUModV = 847, // SPIRVInstrInfo.td:53
863 OpUMulExtended = 848, // SPIRVInstrInfo.td:554
864 OpUndef = 849, // SPIRVInstrInfo.td:98
865 OpUnordered = 850, // SPIRVInstrInfo.td:611
866 OpUnreachable = 851, // SPIRVInstrInfo.td:683
867 OpUntypedAccessChainKHR = 852, // SPIRVInstrInfo.td:306
868 OpUntypedGroupAsyncCopyKHR = 853, // SPIRVInstrInfo.td:321
869 OpUntypedInBoundsAccessChainKHR = 854, // SPIRVInstrInfo.td:309
870 OpUntypedInBoundsPtrAccessChainKHR = 855, // SPIRVInstrInfo.td:315
871 OpUntypedPrefetchKHR = 856, // SPIRVInstrInfo.td:318
872 OpUntypedPtrAccessChainKHR = 857, // SPIRVInstrInfo.td:312
873 OpUntypedVariableKHR = 858, // SPIRVInstrInfo.td:303
874 OpUntypedVariableLengthArrayINTEL = 859, // SPIRVInstrInfo.td:330
875 OpVariable = 860, // SPIRVInstrInfo.td:264
876 OpVariableLengthArrayINTEL = 861, // SPIRVInstrInfo.td:328
877 OpVectorExtractDynamic = 862, // SPIRVInstrInfo.td:493
878 OpVectorInsertDynamic = 863, // SPIRVInstrInfo.td:495
879 OpVectorShuffle = 864, // SPIRVInstrInfo.td:497
880 OpVectorTimesMatrix = 865, // SPIRVInstrInfo.td:545
881 OpVectorTimesScalar = 866, // SPIRVInstrInfo.td:543
882 OpWritePipe = 867, // SPIRVInstrInfo.td:825
883 OpWritePipeBlockingALTERA = 868, // SPIRVInstrInfo.td:1151
884 INSTRUCTION_LIST_END = 869
885 };
886
887} // namespace llvm::SPIRV
888
889#endif // GET_INSTRINFO_ENUM
890
891#ifdef GET_INSTRINFO_SCHED_ENUM
892#undef GET_INSTRINFO_SCHED_ENUM
893
894namespace llvm::SPIRV::Sched {
895
896 enum {
897 NoInstrModel = 0,
898 SCHED_LIST_END = 1
899 };
900
901} // namespace llvm::SPIRV::Sched
902
903#endif // GET_INSTRINFO_SCHED_ENUM
904
905#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
906
907namespace llvm {
908
909struct SPIRVInstrTable {
910 MCInstrDesc Insts[869];
911 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
912 MCPhysReg ImplicitOps[1];
913 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
914 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
915 MCOperandInfo OperandInfo[499];
916};
917} // namespace llvm
918
919#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
920
921#ifdef GET_INSTRINFO_MC_DESC
922#undef GET_INSTRINFO_MC_DESC
923
924namespace llvm {
925
926static_assert((sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
927static constexpr unsigned SPIRVOpInfoBase = (sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) / sizeof(MCOperandInfo);
928
929extern const SPIRVInstrTable SPIRVDescs = {
930 {
931 { 868, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipeBlockingALTERA
932 { 867, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipe
933 { 866, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesScalar
934 { 865, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesMatrix
935 { 864, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorShuffle
936 { 863, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorInsertDynamic
937 { 862, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorExtractDynamic
938 { 861, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariableLengthArrayINTEL
939 { 860, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 496, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariable
940 { 859, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedVariableLengthArrayINTEL
941 { 858, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 313, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedVariableKHR
942 { 857, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 491, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedPtrAccessChainKHR
943 { 856, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedPrefetchKHR
944 { 855, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 491, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedInBoundsPtrAccessChainKHR
945 { 854, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedInBoundsAccessChainKHR
946 { 853, 9, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 482, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedGroupAsyncCopyKHR
947 { 852, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedAccessChainKHR
948 { 851, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnreachable
949 { 850, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnordered
950 { 849, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUndef
951 { 848, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUMulExtended
952 { 847, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModV
953 { 846, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModS
954 { 845, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThanEqual
955 { 844, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThan
956 { 843, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThanEqual
957 { 842, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThan
958 { 841, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDotAccSat
959 { 840, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDot
960 { 839, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivV
961 { 838, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivS
962 { 837, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUConvert
963 { 836, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVoid
964 { 835, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 443, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVectorIdEXT
965 { 834, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 472, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVector
966 { 833, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeUntypedPointerKHR
967 { 832, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStructContinuedINTEL
968 { 831, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStruct
969 { 830, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampler
970 { 829, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampledImage
971 { 828, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeRuntimeArray
972 { 827, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeReserveId
973 { 826, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeQueue
974 { 825, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 475, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePointer
975 { 824, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipeStorage
976 { 823, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipe
977 { 822, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeOpaque
978 { 821, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeNamedBarrier
979 { 820, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 472, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeMatrix
980 { 819, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 469, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeInt
981 { 818, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 461, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeImage
982 { 817, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFunction
983 { 816, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeForwardPointer
984 { 815, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFloat
985 { 814, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeEvent
986 { 813, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeDeviceEvent
987 { 812, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 452, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixNV
988 { 811, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixKHR
989 { 810, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeBool
990 { 809, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 443, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeArray
991 { 808, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeAccelerationStructureNV
992 { 807, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTranspose
993 { 806, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSwitch
994 { 805, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleXorINTEL
995 { 804, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleUpINTEL
996 { 803, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleINTEL
997 { 802, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleDownINTEL
998 { 801, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupMatrixMultiplyAccumulateINTEL
999 { 800, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockWriteINTEL
1000 { 799, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockReadINTEL
1001 { 798, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockWriteINTEL
1002 { 797, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockReadINTEL
1003 { 796, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockWriteINTEL
1004 { 795, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockReadINTEL
1005 { 794, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockStoreINTEL
1006 { 793, 9, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 433, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockPrefetchINTEL
1007 { 792, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransposeINTEL
1008 { 791, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransformINTEL
1009 { 790, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadINTEL
1010 { 789, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpString
1011 { 788, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubV
1012 { 787, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubS
1013 { 786, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemV
1014 { 785, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemS
1015 { 784, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulV
1016 { 783, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulS
1017 { 782, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivV
1018 { 781, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivS
1019 { 780, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddV
1020 { 779, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddS
1021 { 778, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStore
1022 { 777, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantTrue
1023 { 776, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 419, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantOp
1024 { 775, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantFalse
1025 { 774, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantCompositeContinuedINTEL
1026 { 773, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantComposite
1027 { 772, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 416, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstant
1028 { 771, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceExtension
1029 { 770, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceContinued
1030 { 769, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSource
1031 { 768, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSizeOf
1032 { 767, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSignBitSet
1033 { 766, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalV
1034 { 765, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalS
1035 { 764, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticV
1036 { 763, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticS
1037 { 762, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalV
1038 { 761, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalS
1039 { 760, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSetUserEventStatus
1040 { 759, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectionMerge
1041 { 758, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 411, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPVCond
1042 { 757, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 406, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPSCond
1043 { 756, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 401, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVIVCond
1044 { 755, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 396, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVISCond
1045 { 754, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 391, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFVCond
1046 { 753, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 386, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFSCond
1047 { 752, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 381, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPVCond
1048 { 751, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 376, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPSCond
1049 { 750, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 371, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSIVCond
1050 { 749, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 366, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSISCond
1051 { 748, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 361, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFVCond
1052 { 747, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 356, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFSCond
1053 { 746, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSaveMemoryINTEL
1054 { 745, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertUToS
1055 { 744, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertSToU
1056 { 743, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSampledImage
1057 { 742, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDotAccSat
1058 { 741, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDot
1059 { 740, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemV
1060 { 739, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemS
1061 { 738, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSNegate
1062 { 737, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMulExtended
1063 { 736, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMod
1064 { 735, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThanEqual
1065 { 734, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThan
1066 { 733, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThanEqual
1067 { 732, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThan
1068 { 731, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDotAccSat
1069 { 730, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDot
1070 { 729, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivV
1071 { 728, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivS
1072 { 727, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSConvert
1073 { 726, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRoundFToTF32INTEL
1074 { 725, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturnValue
1075 { 724, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturn
1076 { 723, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRetainEvent
1077 { 722, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRestoreMemoryINTEL
1078 { 721, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedWritePipe
1079 { 720, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedReadPipe
1080 { 719, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveWritePipePackets
1081 { 718, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveReadPipePackets
1082 { 717, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReleaseEvent
1083 { 716, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipeBlockingALTERA
1084 { 715, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipe
1085 { 714, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadClockKHR
1086 { 713, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpQuantizeToF16
1087 { 712, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrNotEqual
1088 { 711, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrEqual
1089 { 710, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrDiff
1090 { 709, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToGeneric
1091 { 708, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToCrossWorkgroupINTEL
1092 { 707, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrAccessChain
1093 { 706, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedStoreINTEL
1094 { 705, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedLoadINTEL
1095 { 704, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPoisonKHR
1096 { 703, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPhi
1097 { 702, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOuterProduct
1098 { 701, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOrdered
1099 { 700, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNot
1100 { 699, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNop
1101 { 698, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNoLine
1102 { 697, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNamedBarrierInitialize
1103 { 696, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpName
1104 { 695, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpModuleProcessed
1105 { 694, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryNamedBarrier
1106 { 693, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryModel
1107 { 692, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryBarrier
1108 { 691, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberName
1109 { 690, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 352, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorateString
1110 { 689, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorate
1111 { 688, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesVector
1112 { 687, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesScalar
1113 { 686, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesMatrix
1114 { 685, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedScatterINTEL
1115 { 684, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedGatherINTEL
1116 { 683, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopMerge
1117 { 682, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopControlINTEL
1118 { 681, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalOr
1119 { 680, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNotEqual
1120 { 679, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNot
1121 { 678, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalEqual
1122 { 677, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalAnd
1123 { 676, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoad
1124 { 675, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 346, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLine
1125 { 674, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 344, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStop
1126 { 673, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 344, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStart
1127 { 672, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLessOrGreater
1128 { 671, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLabel
1129 { 670, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpKill
1130 { 669, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidReserveId
1131 { 668, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidEvent
1132 { 667, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNormal
1133 { 666, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNan
1134 { 665, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsInf
1135 { 664, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsFinite
1136 { 663, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsPtrAccessChain
1137 { 662, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsAccessChain
1138 { 661, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageWrite
1139 { 660, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageTexelPointer
1140 { 659, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseTexelsResident
1141 { 658, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjImplicitLod
1142 { 657, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjExplicitLod
1143 { 656, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefImplicitLod
1144 { 655, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefExplicitLod
1145 { 654, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleImplicitLod
1146 { 653, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 338, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleExplicitLod
1147 { 652, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefImplicitLod
1148 { 651, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefExplicitLod
1149 { 650, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseRead
1150 { 649, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseGather
1151 { 648, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseFetch
1152 { 647, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseDrefGather
1153 { 646, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjImplicitLod
1154 { 645, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjExplicitLod
1155 { 644, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefImplicitLod
1156 { 643, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefExplicitLod
1157 { 642, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleImplicitLod
1158 { 641, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleFootprintNV
1159 { 640, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 338, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleExplicitLod
1160 { 639, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefImplicitLod
1161 { 638, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefExplicitLod
1162 { 637, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageRead
1163 { 636, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySizeLod
1164 { 635, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySize
1165 { 634, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySamples
1166 { 633, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryOrder
1167 { 632, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLod
1168 { 631, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLevels
1169 { 630, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryFormat
1170 { 629, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageGather
1171 { 628, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageFetch
1172 { 627, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageDrefGather
1173 { 626, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImage
1174 { 625, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubV
1175 { 624, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubS
1176 { 623, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowV
1177 { 622, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowS
1178 { 621, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpINotEqual
1179 { 620, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulV
1180 { 619, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulS
1181 { 618, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIEqual
1182 { 617, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddV
1183 { 616, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddS
1184 { 615, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryV
1185 { 614, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryS
1186 { 613, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupWaitEvents
1187 { 612, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMin
1188 { 611, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMax
1189 { 610, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMin
1190 { 609, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMax
1191 { 608, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveWritePipePackets
1192 { 607, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveReadPipePackets
1193 { 606, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMin
1194 { 605, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMax
1195 { 604, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleXor
1196 { 603, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleUp
1197 { 602, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleDown
1198 { 601, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffle
1199 { 600, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMin
1200 { 599, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMax
1201 { 598, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformRotateKHR
1202 { 597, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformQuadSwap
1203 { 596, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalXor
1204 { 595, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalOr
1205 { 594, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalAnd
1206 { 593, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformInverseBallot
1207 { 592, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIMul
1208 { 591, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIAdd
1209 { 590, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMul
1210 { 589, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMin
1211 { 588, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMax
1212 { 587, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFAdd
1213 { 586, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformElect
1214 { 585, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcastFirst
1215 { 584, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcast
1216 { 583, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseXor
1217 { 582, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseOr
1218 { 581, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseAnd
1219 { 580, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindMSB
1220 { 579, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindLSB
1221 { 578, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitExtract
1222 { 577, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitCount
1223 { 576, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallot
1224 { 575, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAny
1225 { 574, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAllEqual
1226 { 573, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAll
1227 { 572, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalXorKHR
1228 { 571, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalOrKHR
1229 { 570, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalAndKHR
1230 { 569, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIMulKHR
1231 { 568, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIAdd
1232 { 567, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMulKHR
1233 { 566, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMin
1234 { 565, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMax
1235 { 564, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFAdd
1236 { 563, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitWritePipe
1237 { 562, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitReadPipe
1238 { 561, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBroadcast
1239 { 560, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseXorKHR
1240 { 559, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseOrKHR
1241 { 558, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseAndKHR
1242 { 557, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAsyncCopy
1243 { 556, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAny
1244 { 555, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAll
1245 { 554, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetNumPipePackets
1246 { 553, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetMaxPipePackets
1247 { 552, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetKernelWorkGroupSize
1248 { 551, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetKernelPreferredWorkGroupSizeMultiple
1249 { 550, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetKernelNDrangeSubGroupCount
1250 { 549, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetKernelNDrangeMaxSubGroupSize
1251 { 548, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetDefaultQueue
1252 { 547, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericPtrMemSemantics
1253 { 546, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 317, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtrExplicit
1254 { 545, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtr
1255 { 544, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthFine
1256 { 543, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthCoarse
1257 { 542, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidth
1258 { 541, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionPointerCallINTEL
1259 { 540, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionParameter
1260 { 539, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionEnd
1261 { 538, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionCall
1262 { 537, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 313, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunction
1263 { 536, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFreezeKHR
1264 { 535, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFmaKHR
1265 { 534, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSqrtALTERA
1266 { 533, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinPiALTERA
1267 { 532, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosPiALTERA
1268 { 531, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosALTERA
1269 { 530, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinALTERA
1270 { 529, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRsqrtALTERA
1271 { 528, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRecipALTERA
1272 { 527, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedLogALTERA
1273 { 526, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedExpALTERA
1274 { 525, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosPiALTERA
1275 { 524, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosALTERA
1276 { 523, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordNotEqual
1277 { 522, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThanEqual
1278 { 521, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThan
1279 { 520, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThanEqual
1280 { 519, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThan
1281 { 518, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordEqual
1282 { 517, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubV
1283 { 516, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubS
1284 { 515, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemV
1285 { 514, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemS
1286 { 513, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdNotEqual
1287 { 512, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThanEqual
1288 { 511, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThan
1289 { 510, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThanEqual
1290 { 509, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThan
1291 { 508, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdEqual
1292 { 507, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 310, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegateV
1293 { 506, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegate
1294 { 505, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulV
1295 { 504, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulS
1296 { 503, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMod
1297 { 502, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivV
1298 { 501, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivS
1299 { 500, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFConvert
1300 { 499, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddV
1301 { 498, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddS
1302 { 497, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtension
1303 { 496, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 298, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInstWithForwardRefsKHR
1304 { 495, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInstImport
1305 { 494, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 298, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInst
1306 { 493, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExpectKHR
1307 { 492, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionModeId
1308 { 491, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionMode
1309 { 490, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 295, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEntryPoint
1310 { 489, 12, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 283, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEnqueueKernel
1311 { 488, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndStreamPrimitive
1312 { 487, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndPrimitive
1313 { 486, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitVertex
1314 { 485, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitStreamVertex
1315 { 484, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDot
1316 { 483, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDemoteToHelperInvocation
1317 { 482, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 280, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateString
1318 { 481, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateId
1319 { 480, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorate
1320 { 479, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyFine
1321 { 478, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyCoarse
1322 { 477, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdy
1323 { 476, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxFine
1324 { 475, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxCoarse
1325 { 474, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdx
1326 { 473, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCrossWorkgroupCastToPtrINTEL
1327 { 472, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCreateUserEvent
1328 { 471, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyObject
1329 { 470, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemorySized
1330 { 469, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemory
1331 { 468, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyLogical
1332 { 467, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreKHR
1333 { 466, 7, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 271, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreCheckedINTEL
1334 { 465, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 266, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixPrefetchINTEL
1335 { 464, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixMulAddKHR
1336 { 463, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadKHR
1337 { 462, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadCheckedINTEL
1338 { 461, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 263, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLengthKHR
1339 { 460, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixGetElementCoordINTEL
1340 { 459, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixConstructCheckedINTEL
1341 { 458, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToPtr
1342 { 457, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToF
1343 { 456, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertSToF
1344 { 455, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertPtrToU
1345 { 454, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSamplerINTEL
1346 { 453, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSampledImageINTEL
1347 { 452, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToImageINTEL
1348 { 451, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToU
1349 { 450, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToS
1350 { 449, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToBF16INTEL
1351 { 448, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertBF16ToFINTEL
1352 { 447, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierWaitINTEL
1353 { 446, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierArriveINTEL
1354 { 445, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrier
1355 { 444, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantTrue
1356 { 443, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantSampler
1357 { 442, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantNull
1358 { 441, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 248, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantI
1359 { 440, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFunctionPointerINTEL
1360 { 439, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFalse
1361 { 438, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantF
1362 { 437, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantCompositeContinuedINTEL
1363 { 436, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantComposite
1364 { 435, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeInsert
1365 { 434, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeExtract
1366 { 433, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstructContinuedINTEL
1367 { 432, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstruct
1368 { 431, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitWritePipe
1369 { 430, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitReadPipe
1370 { 429, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCaptureEventProfilingInfo
1371 { 428, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCapability
1372 { 427, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBuildNDRange
1373 { 426, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 234, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranchConditional
1374 { 425, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranch
1375 { 424, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorV
1376 { 423, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorS
1377 { 422, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrV
1378 { 421, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrS
1379 { 420, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseFunctionINTEL
1380 { 419, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndV
1381 { 418, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndS
1382 { 417, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitcast
1383 { 416, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitReverse
1384 { 415, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldUExtract
1385 { 414, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldSExtract
1386 { 413, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldInsert
1387 { 412, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitCount
1388 { 411, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicXor
1389 { 410, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMin
1390 { 409, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMax
1391 { 408, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicStore
1392 { 407, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMin
1393 { 406, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMax
1394 { 405, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicOr
1395 { 404, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicLoad
1396 { 403, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicISub
1397 { 402, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIIncrement
1398 { 401, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIDecrement
1399 { 400, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIAdd
1400 { 399, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagTestAndSet
1401 { 398, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagClear
1402 { 397, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMinEXT
1403 { 396, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMaxEXT
1404 { 395, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFAddEXT
1405 { 394, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicExchange
1406 { 393, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchangeWeak
1407 { 392, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchange
1408 { 391, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicAnd
1409 { 390, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAssumeTrueKHR
1410 { 389, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmTargetINTEL
1411 { 388, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 192, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmINTEL
1412 { 387, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmCallINTEL
1413 { 386, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 188, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArrayLength
1414 { 385, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArithmeticFenceEXT
1415 { 384, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSubALTERA
1416 { 383, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSqrtALTERA
1417 { 382, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinPiALTERA
1418 { 381, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosPiALTERA
1419 { 380, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosALTERA
1420 { 379, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinALTERA
1421 { 378, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRecipALTERA
1422 { 377, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRSqrtALTERA
1423 { 376, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowRALTERA
1424 { 375, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowNALTERA
1425 { 374, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowALTERA
1426 { 373, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatMulALTERA
1427 { 372, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLogALTERA
1428 { 371, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog2ALTERA
1429 { 370, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog1pALTERA
1430 { 369, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog10ALTERA
1431 { 368, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLTALTERA
1432 { 367, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLEALTERA
1433 { 366, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatHypotALTERA
1434 { 365, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGTALTERA
1435 { 364, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGEALTERA
1436 { 363, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpm1ALTERA
1437 { 362, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpALTERA
1438 { 361, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp2ALTERA
1439 { 360, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp10ALTERA
1440 { 359, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatEQALTERA
1441 { 358, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatDivALTERA
1442 { 357, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosPiALTERA
1443 { 356, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosALTERA
1444 { 355, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCbrtALTERA
1445 { 354, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastToIntALTERA
1446 { 353, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastFromIntALTERA
1447 { 352, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastALTERA
1448 { 351, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatAddALTERA
1449 { 350, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanPiALTERA
1450 { 349, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanALTERA
1451 { 348, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATan2ALTERA
1452 { 347, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinPiALTERA
1453 { 346, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinALTERA
1454 { 345, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosPiALTERA
1455 { 344, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosALTERA
1456 { 343, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAny
1457 { 342, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAll
1458 { 341, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeListDeclINTEL
1459 { 340, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeDeclINTEL
1460 { 339, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasDomainDeclINTEL
1461 { 338, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAccessChain
1462 { 337, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAbortKHR
1463 { 336, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNKNOWN_type
1464 { 335, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASSIGN_TYPE
1465 { 334, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1466 { 333, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1467 { 332, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1468 { 331, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1469 { 330, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1470 { 329, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1471 { 328, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1472 { 327, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1473 { 326, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1474 { 325, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1475 { 324, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1476 { 323, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1477 { 322, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1478 { 321, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1479 { 320, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1480 { 319, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1481 { 318, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1482 { 317, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1483 { 316, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1484 { 315, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1485 { 314, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1486 { 313, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1487 { 312, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1488 { 311, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1489 { 310, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
1490 { 309, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1491 { 308, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1492 { 307, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1493 { 306, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1494 { 305, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1495 { 304, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1496 { 303, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1497 { 302, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
1498 { 301, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
1499 { 300, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1500 { 299, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1501 { 298, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1502 { 297, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1503 { 296, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1504 { 295, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1505 { 294, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1506 { 293, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1507 { 292, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1508 { 291, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1509 { 290, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1510 { 289, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1511 { 288, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1512 { 287, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1513 { 286, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1514 { 285, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1515 { 284, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1516 { 283, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1517 { 282, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1518 { 281, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1519 { 280, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1520 { 279, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1521 { 278, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1522 { 277, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1523 { 276, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1524 { 275, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1525 { 274, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1526 { 273, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1527 { 272, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1528 { 271, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1529 { 270, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULR
1530 { 269, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
1531 { 268, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
1532 { 267, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1533 { 266, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1534 { 265, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1535 { 264, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1536 { 263, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
1537 { 262, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1538 { 261, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
1539 { 260, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1540 { 259, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1541 { 258, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1542 { 257, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1543 { 256, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1544 { 255, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1545 { 254, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1546 { 253, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1547 { 252, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1548 { 251, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1549 { 250, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1550 { 249, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1551 { 248, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1552 { 247, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1553 { 246, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1554 { 245, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1555 { 244, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1556 { 243, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1557 { 242, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1558 { 241, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1559 { 240, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1560 { 239, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1561 { 238, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1562 { 237, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1563 { 236, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1564 { 235, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1565 { 234, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1566 { 233, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1567 { 232, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1568 { 231, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1569 { 230, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1570 { 229, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1571 { 228, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1572 { 227, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1573 { 226, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1574 { 225, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1575 { 224, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1576 { 223, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1577 { 222, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1578 { 221, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1579 { 220, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1580 { 219, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1581 { 218, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1582 { 217, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1583 { 216, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1584 { 215, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1585 { 214, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1586 { 213, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1587 { 212, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1588 { 211, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1589 { 210, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1590 { 209, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1591 { 208, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1592 { 207, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1593 { 206, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1594 { 205, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1595 { 204, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1596 { 203, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1597 { 202, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1598 { 201, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1599 { 200, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1600 { 199, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1601 { 198, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1602 { 197, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1603 { 196, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1604 { 195, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1605 { 194, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1606 { 193, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1607 { 192, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1608 { 191, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1609 { 190, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1610 { 189, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1611 { 188, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1612 { 187, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1613 { 186, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1614 { 185, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1615 { 184, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1616 { 183, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1617 { 182, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1618 { 181, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1619 { 180, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1620 { 179, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1621 { 178, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1622 { 177, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1623 { 176, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1624 { 175, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1625 { 174, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1626 { 173, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1627 { 172, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1628 { 171, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1629 { 170, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1630 { 169, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1631 { 168, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1632 { 167, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1633 { 166, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1634 { 165, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1635 { 164, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1636 { 163, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1637 { 162, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1638 { 161, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1639 { 160, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1640 { 159, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1641 { 158, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1642 { 157, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1643 { 156, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1644 { 155, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1645 { 154, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1646 { 153, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1647 { 152, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1648 { 151, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1649 { 150, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1650 { 149, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1651 { 148, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1652 { 147, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1653 { 146, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1654 { 145, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1655 { 144, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1656 { 143, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1657 { 142, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1658 { 141, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1659 { 140, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1660 { 139, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1661 { 138, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1662 { 137, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1663 { 136, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1664 { 135, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1665 { 134, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1666 { 133, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1667 { 132, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1668 { 131, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1669 { 130, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1670 { 129, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1671 { 128, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1672 { 127, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1673 { 126, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1674 { 125, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1675 { 124, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1676 { 123, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1677 { 122, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1678 { 121, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1679 { 120, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1680 { 119, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1681 { 118, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1682 { 117, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1683 { 116, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1684 { 115, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1685 { 114, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1686 { 113, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1687 { 112, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1688 { 111, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1689 { 110, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1690 { 109, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1691 { 108, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1692 { 107, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1693 { 106, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1694 { 105, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1695 { 104, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1696 { 103, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1697 { 102, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1698 { 101, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1699 { 100, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1700 { 99, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1701 { 98, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1702 { 97, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1703 { 96, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1704 { 95, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1705 { 94, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1706 { 93, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1707 { 92, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1708 { 91, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1709 { 90, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1710 { 89, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1711 { 88, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1712 { 87, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1713 { 86, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1714 { 85, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1715 { 84, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1716 { 83, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1717 { 82, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1718 { 81, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1719 { 80, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1720 { 79, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1721 { 78, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1722 { 77, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1723 { 76, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1724 { 75, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1725 { 74, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1726 { 73, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1727 { 72, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1728 { 71, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1729 { 70, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1730 { 69, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1731 { 68, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1732 { 67, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1733 { 66, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1734 { 65, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1735 { 64, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1736 { 63, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1737 { 62, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1738 { 61, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1739 { 60, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1740 { 59, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1741 { 58, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1742 { 57, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1743 { 56, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1744 { 55, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1745 { 54, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1746 { 53, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1747 { 52, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1748 { 51, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1749 { 50, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1750 { 49, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1751 { 48, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1752 { 47, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1753 { 46, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1754 { 45, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1755 { 44, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1756 { 43, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1757 { 42, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21966
1758 { 41, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21965
1759 { 40, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1760 { 39, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1761 { 38, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1762 { 37, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1763 { 36, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1764 { 35, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1765 { 34, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1766 { 33, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1767 { 32, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21964
1768 { 31, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1769 { 30, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14417
1770 { 29, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1771 { 28, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1772 { 27, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1773 { 26, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1774 { 25, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1775 { 24, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1776 { 23, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1777 { 22, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1778 { 21, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1779 { 20, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1780 { 19, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1781 { 18, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1782 { 17, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1783 { 16, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1784 { 15, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1785 { 14, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1786 { 13, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1787 { 12, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1788 { 11, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1789 { 10, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1790 { 9, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1791 { 8, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1792 { 7, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1793 { 6, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1794 { 5, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1795 { 4, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1796 { 3, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1797 { 2, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1798 { 1, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1799 { 0, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1800 }, {
1801 /* 0 */
1802 }, {
1803 0
1804 }, {
1805 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1806 /* 1 */
1807 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1808 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1809 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1810 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1811 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1812 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1813 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1814 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1815 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1816 /* 28 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1817 /* 29 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1818 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1819 /* 34 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1820 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1821 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1822 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1823 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1824 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1825 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1826 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1827 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1828 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1829 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1830 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1831 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1832 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1833 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1834 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1835 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1836 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1837 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1838 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1839 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1840 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1841 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1842 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1843 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1844 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1845 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1846 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1847 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1848 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1849 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1850 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1851 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1852 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1853 /* 151 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1854 /* 154 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1855 /* 156 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1856 /* 158 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1857 /* 161 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1858 /* 162 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1859 /* 164 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1860 /* 172 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1861 /* 182 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1862 /* 188 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1863 /* 192 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1864 /* 198 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1865 /* 200 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1866 /* 206 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1867 /* 214 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1868 /* 217 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1869 /* 222 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1870 /* 226 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1871 /* 230 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1872 /* 234 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1873 /* 237 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1874 /* 239 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1875 /* 243 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1876 /* 246 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1877 /* 248 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1878 /* 251 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1879 /* 256 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1880 /* 263 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1881 /* 266 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1882 /* 271 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1883 /* 278 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1884 /* 280 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1885 /* 283 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1886 /* 295 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1887 /* 298 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1888 /* 302 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1889 /* 306 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1890 /* 310 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1891 /* 313 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1892 /* 317 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1893 /* 321 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1894 /* 326 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1895 /* 331 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1896 /* 338 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1897 /* 344 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1898 /* 346 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1899 /* 349 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1900 /* 352 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1901 /* 356 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1902 /* 361 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1903 /* 366 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1904 /* 371 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1905 /* 376 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1906 /* 381 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1907 /* 386 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1908 /* 391 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1909 /* 396 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1910 /* 401 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1911 /* 406 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1912 /* 411 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1913 /* 416 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1914 /* 419 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1915 /* 423 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1916 /* 433 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1917 /* 442 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1918 /* 443 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1919 /* 446 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1920 /* 452 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1921 /* 457 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1922 /* 459 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1923 /* 461 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1924 /* 469 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1925 /* 472 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1926 /* 475 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1927 /* 478 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1928 /* 482 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1929 /* 491 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1930 /* 496 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1931 }
1932};
1933
1934
1935#ifdef __GNUC__
1936#pragma GCC diagnostic push
1937#pragma GCC diagnostic ignored "-Woverlength-strings"
1938#endif
1939extern const char SPIRVInstrNameData[] = {
1940 /* 0 */ "G_FLOG10\000"
1941 /* 9 */ "G_FEXP10\000"
1942 /* 18 */ "G_FLOG2\000"
1943 /* 26 */ "G_FATAN2\000"
1944 /* 35 */ "G_FEXP2\000"
1945 /* 43 */ "OpQuantizeToF16\000"
1946 /* 59 */ "G_FMA\000"
1947 /* 65 */ "G_STRICT_FMA\000"
1948 /* 78 */ "OpArbitraryFloatLog10ALTERA\000"
1949 /* 106 */ "OpArbitraryFloatExp10ALTERA\000"
1950 /* 134 */ "OpArbitraryFloatExpm1ALTERA\000"
1951 /* 162 */ "OpArbitraryFloatLog2ALTERA\000"
1952 /* 189 */ "OpArbitraryFloatATan2ALTERA\000"
1953 /* 217 */ "OpArbitraryFloatExp2ALTERA\000"
1954 /* 244 */ "OpArbitraryFloatGEALTERA\000"
1955 /* 269 */ "OpArbitraryFloatLEALTERA\000"
1956 /* 294 */ "OpArbitraryFloatPowNALTERA\000"
1957 /* 321 */ "OpArbitraryFloatEQALTERA\000"
1958 /* 346 */ "OpArbitraryFloatPowRALTERA\000"
1959 /* 373 */ "OpArbitraryFloatGTALTERA\000"
1960 /* 398 */ "OpArbitraryFloatLTALTERA\000"
1961 /* 423 */ "OpArbitraryFloatSubALTERA\000"
1962 /* 449 */ "OpArbitraryFloatAddALTERA\000"
1963 /* 475 */ "OpReadPipeBlockingALTERA\000"
1964 /* 500 */ "OpWritePipeBlockingALTERA\000"
1965 /* 526 */ "OpFixedLogALTERA\000"
1966 /* 543 */ "OpArbitraryFloatLogALTERA\000"
1967 /* 569 */ "OpArbitraryFloatATanPiALTERA\000"
1968 /* 598 */ "OpArbitraryFloatASinPiALTERA\000"
1969 /* 627 */ "OpFixedSinPiALTERA\000"
1970 /* 646 */ "OpArbitraryFloatSinPiALTERA\000"
1971 /* 674 */ "OpArbitraryFloatACosPiALTERA\000"
1972 /* 703 */ "OpFixedCosPiALTERA\000"
1973 /* 722 */ "OpFixedSinCosPiALTERA\000"
1974 /* 744 */ "OpArbitraryFloatSinCosPiALTERA\000"
1975 /* 775 */ "OpArbitraryFloatCosPiALTERA\000"
1976 /* 803 */ "OpArbitraryFloatMulALTERA\000"
1977 /* 829 */ "OpArbitraryFloatATanALTERA\000"
1978 /* 856 */ "OpArbitraryFloatASinALTERA\000"
1979 /* 883 */ "OpFixedSinALTERA\000"
1980 /* 900 */ "OpArbitraryFloatSinALTERA\000"
1981 /* 926 */ "OpArbitraryFloatLog1pALTERA\000"
1982 /* 954 */ "OpFixedRecipALTERA\000"
1983 /* 973 */ "OpArbitraryFloatRecipALTERA\000"
1984 /* 1001 */ "OpFixedExpALTERA\000"
1985 /* 1018 */ "OpArbitraryFloatExpALTERA\000"
1986 /* 1044 */ "OpArbitraryFloatACosALTERA\000"
1987 /* 1071 */ "OpFixedCosALTERA\000"
1988 /* 1088 */ "OpFixedSinCosALTERA\000"
1989 /* 1108 */ "OpArbitraryFloatSinCosALTERA\000"
1990 /* 1137 */ "OpArbitraryFloatCosALTERA\000"
1991 /* 1163 */ "OpArbitraryFloatCastFromIntALTERA\000"
1992 /* 1197 */ "OpArbitraryFloatCastToIntALTERA\000"
1993 /* 1229 */ "OpArbitraryFloatHypotALTERA\000"
1994 /* 1257 */ "OpArbitraryFloatCbrtALTERA\000"
1995 /* 1284 */ "OpArbitraryFloatRSqrtALTERA\000"
1996 /* 1312 */ "OpFixedSqrtALTERA\000"
1997 /* 1330 */ "OpArbitraryFloatSqrtALTERA\000"
1998 /* 1357 */ "OpFixedRsqrtALTERA\000"
1999 /* 1376 */ "OpArbitraryFloatCastALTERA\000"
2000 /* 1403 */ "OpArbitraryFloatDivALTERA\000"
2001 /* 1429 */ "OpArbitraryFloatPowALTERA\000"
2002 /* 1455 */ "OpGroupNonUniformBallotFindLSB\000"
2003 /* 1486 */ "OpGroupNonUniformBallotFindMSB\000"
2004 /* 1517 */ "G_FSUB\000"
2005 /* 1524 */ "G_STRICT_FSUB\000"
2006 /* 1538 */ "G_ATOMICRMW_FSUB\000"
2007 /* 1555 */ "G_SUB\000"
2008 /* 1561 */ "G_ATOMICRMW_SUB\000"
2009 /* 1577 */ "G_INTRINSIC\000"
2010 /* 1589 */ "G_FPTRUNC\000"
2011 /* 1599 */ "G_INTRINSIC_TRUNC\000"
2012 /* 1617 */ "G_TRUNC\000"
2013 /* 1625 */ "G_BUILD_VECTOR_TRUNC\000"
2014 /* 1646 */ "G_DYN_STACKALLOC\000"
2015 /* 1663 */ "G_FMAD\000"
2016 /* 1670 */ "G_FPEXTLOAD\000"
2017 /* 1682 */ "G_INDEXED_SEXTLOAD\000"
2018 /* 1701 */ "G_SEXTLOAD\000"
2019 /* 1712 */ "G_INDEXED_ZEXTLOAD\000"
2020 /* 1731 */ "G_ZEXTLOAD\000"
2021 /* 1742 */ "G_INDEXED_LOAD\000"
2022 /* 1757 */ "G_LOAD\000"
2023 /* 1764 */ "G_VECREDUCE_FADD\000"
2024 /* 1781 */ "G_FADD\000"
2025 /* 1788 */ "G_VECREDUCE_SEQ_FADD\000"
2026 /* 1809 */ "G_STRICT_FADD\000"
2027 /* 1823 */ "G_ATOMICRMW_FADD\000"
2028 /* 1840 */ "G_VECREDUCE_ADD\000"
2029 /* 1856 */ "G_ADD\000"
2030 /* 1862 */ "G_PTR_ADD\000"
2031 /* 1872 */ "G_ATOMICRMW_ADD\000"
2032 /* 1888 */ "G_ATOMICRMW_NAND\000"
2033 /* 1905 */ "G_VECREDUCE_AND\000"
2034 /* 1921 */ "G_AND\000"
2035 /* 1927 */ "G_ATOMICRMW_AND\000"
2036 /* 1943 */ "LIFETIME_END\000"
2037 /* 1956 */ "G_BRCOND\000"
2038 /* 1965 */ "G_ATOMICRMW_USUB_COND\000"
2039 /* 1987 */ "G_LLROUND\000"
2040 /* 1997 */ "G_LROUND\000"
2041 /* 2006 */ "G_INTRINSIC_ROUND\000"
2042 /* 2024 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
2043 /* 2050 */ "LOAD_STACK_GUARD\000"
2044 /* 2067 */ "PSEUDO_PROBE\000"
2045 /* 2080 */ "G_SSUBE\000"
2046 /* 2088 */ "G_USUBE\000"
2047 /* 2096 */ "G_FENCE\000"
2048 /* 2104 */ "ARITH_FENCE\000"
2049 /* 2116 */ "REG_SEQUENCE\000"
2050 /* 2129 */ "G_SADDE\000"
2051 /* 2137 */ "G_UADDE\000"
2052 /* 2145 */ "G_GET_FPMODE\000"
2053 /* 2158 */ "G_RESET_FPMODE\000"
2054 /* 2173 */ "G_SET_FPMODE\000"
2055 /* 2186 */ "G_FMINNUM_IEEE\000"
2056 /* 2201 */ "G_FMAXNUM_IEEE\000"
2057 /* 2216 */ "G_VSCALE\000"
2058 /* 2225 */ "G_JUMP_TABLE\000"
2059 /* 2238 */ "BUNDLE\000"
2060 /* 2245 */ "G_MEMSET_INLINE\000"
2061 /* 2261 */ "G_MEMCPY_INLINE\000"
2062 /* 2277 */ "RELOC_NONE\000"
2063 /* 2288 */ "LOCAL_ESCAPE\000"
2064 /* 2301 */ "ASSIGN_TYPE\000"
2065 /* 2313 */ "G_FPTRUNCSTORE\000"
2066 /* 2328 */ "G_STACKRESTORE\000"
2067 /* 2343 */ "G_INDEXED_STORE\000"
2068 /* 2359 */ "G_STORE\000"
2069 /* 2367 */ "G_BITREVERSE\000"
2070 /* 2380 */ "FAKE_USE\000"
2071 /* 2389 */ "DBG_VALUE\000"
2072 /* 2399 */ "G_GLOBAL_VALUE\000"
2073 /* 2414 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2074 /* 2437 */ "CONVERGENCECTRL_GLUE\000"
2075 /* 2458 */ "G_STACKSAVE\000"
2076 /* 2470 */ "G_MEMMOVE\000"
2077 /* 2480 */ "G_FREEZE\000"
2078 /* 2489 */ "G_FCANONICALIZE\000"
2079 /* 2505 */ "G_FMODF\000"
2080 /* 2513 */ "INIT_UNDEF\000"
2081 /* 2524 */ "G_IMPLICIT_DEF\000"
2082 /* 2539 */ "DBG_INSTR_REF\000"
2083 /* 2553 */ "OpConvertSToF\000"
2084 /* 2567 */ "OpConvertUToF\000"
2085 /* 2581 */ "OpConstantF\000"
2086 /* 2593 */ "G_FNEG\000"
2087 /* 2600 */ "EXTRACT_SUBREG\000"
2088 /* 2615 */ "INSERT_SUBREG\000"
2089 /* 2629 */ "G_SEXT_INREG\000"
2090 /* 2642 */ "SUBREG_TO_REG\000"
2091 /* 2656 */ "G_ATOMIC_CMPXCHG\000"
2092 /* 2673 */ "G_ATOMICRMW_XCHG\000"
2093 /* 2690 */ "G_GET_ROUNDING\000"
2094 /* 2705 */ "G_SET_ROUNDING\000"
2095 /* 2720 */ "G_FLOG\000"
2096 /* 2727 */ "G_VAARG\000"
2097 /* 2735 */ "PREALLOCATED_ARG\000"
2098 /* 2752 */ "G_PREFETCH\000"
2099 /* 2763 */ "G_CLMULH\000"
2100 /* 2772 */ "G_SMULH\000"
2101 /* 2780 */ "G_UMULH\000"
2102 /* 2788 */ "G_FTANH\000"
2103 /* 2796 */ "G_FSINH\000"
2104 /* 2804 */ "G_FCOSH\000"
2105 /* 2812 */ "DBG_PHI\000"
2106 /* 2820 */ "G_FPTOSI\000"
2107 /* 2829 */ "G_FPTOUI\000"
2108 /* 2838 */ "G_FPOWI\000"
2109 /* 2846 */ "OpConstantI\000"
2110 /* 2858 */ "COPY_LANEMASK\000"
2111 /* 2872 */ "G_PTRMASK\000"
2112 /* 2882 */ "GC_LABEL\000"
2113 /* 2891 */ "DBG_LABEL\000"
2114 /* 2901 */ "EH_LABEL\000"
2115 /* 2910 */ "ANNOTATION_LABEL\000"
2116 /* 2927 */ "ICALL_BRANCH_FUNNEL\000"
2117 /* 2947 */ "OpRoundFToTF32INTEL\000"
2118 /* 2967 */ "OpConvertFToBF16INTEL\000"
2119 /* 2989 */ "OpConvertBF16ToFINTEL\000"
2120 /* 3011 */ "OpSubgroupImageMediaBlockReadINTEL\000"
2121 /* 3046 */ "OpSubgroupImageBlockReadINTEL\000"
2122 /* 3076 */ "OpSubgroupBlockReadINTEL\000"
2123 /* 3101 */ "OpPredicatedLoadINTEL\000"
2124 /* 3123 */ "OpSubgroup2DBlockLoadINTEL\000"
2125 /* 3150 */ "OpCooperativeMatrixLoadCheckedINTEL\000"
2126 /* 3186 */ "OpCooperativeMatrixStoreCheckedINTEL\000"
2127 /* 3223 */ "OpCooperativeMatrixConstructCheckedINTEL\000"
2128 /* 3264 */ "OpSpecConstantCompositeContinuedINTEL\000"
2129 /* 3302 */ "OpConstantCompositeContinuedINTEL\000"
2130 /* 3336 */ "OpTypeStructContinuedINTEL\000"
2131 /* 3363 */ "OpCompositeConstructContinuedINTEL\000"
2132 /* 3398 */ "OpCooperativeMatrixGetElementCoordINTEL\000"
2133 /* 3438 */ "OpConvertHandleToSampledImageINTEL\000"
2134 /* 3473 */ "OpConvertHandleToImageINTEL\000"
2135 /* 3501 */ "OpSubgroupShuffleINTEL\000"
2136 /* 3524 */ "OpPredicatedStoreINTEL\000"
2137 /* 3547 */ "OpSubgroup2DBlockStoreINTEL\000"
2138 /* 3575 */ "OpSubgroup2DBlockLoadTransposeINTEL\000"
2139 /* 3611 */ "OpSubgroupMatrixMultiplyAccumulateINTEL\000"
2140 /* 3651 */ "OpSubgroupImageMediaBlockWriteINTEL\000"
2141 /* 3687 */ "OpSubgroupImageBlockWriteINTEL\000"
2142 /* 3718 */ "OpSubgroupBlockWriteINTEL\000"
2143 /* 3744 */ "OpControlBarrierArriveINTEL\000"
2144 /* 3772 */ "OpSubgroup2DBlockPrefetchINTEL\000"
2145 /* 3803 */ "OpCooperativeMatrixPrefetchINTEL\000"
2146 /* 3836 */ "OpAliasScopeDeclINTEL\000"
2147 /* 3858 */ "OpAliasDomainDeclINTEL\000"
2148 /* 3881 */ "OpAliasScopeListDeclINTEL\000"
2149 /* 3907 */ "OpAsmCallINTEL\000"
2150 /* 3922 */ "OpFunctionPointerCallINTEL\000"
2151 /* 3949 */ "OpLoopControlINTEL\000"
2152 /* 3968 */ "OpSubgroup2DBlockLoadTransformINTEL\000"
2153 /* 4004 */ "OpAsmINTEL\000"
2154 /* 4015 */ "OpBitwiseFunctionINTEL\000"
2155 /* 4038 */ "OpSubgroupShuffleDownINTEL\000"
2156 /* 4065 */ "OpSubgroupShuffleUpINTEL\000"
2157 /* 4090 */ "OpPtrCastToCrossWorkgroupINTEL\000"
2158 /* 4121 */ "OpMaskedGatherINTEL\000"
2159 /* 4141 */ "OpConvertHandleToSamplerINTEL\000"
2160 /* 4171 */ "OpConstantFunctionPointerINTEL\000"
2161 /* 4202 */ "OpMaskedScatterINTEL\000"
2162 /* 4223 */ "OpSubgroupShuffleXorINTEL\000"
2163 /* 4249 */ "OpCrossWorkgroupCastToPtrINTEL\000"
2164 /* 4280 */ "OpAsmTargetINTEL\000"
2165 /* 4297 */ "OpControlBarrierWaitINTEL\000"
2166 /* 4323 */ "OpUntypedVariableLengthArrayINTEL\000"
2167 /* 4357 */ "OpVariableLengthArrayINTEL\000"
2168 /* 4384 */ "OpRestoreMemoryINTEL\000"
2169 /* 4405 */ "OpSaveMemoryINTEL\000"
2170 /* 4423 */ "G_FSHL\000"
2171 /* 4430 */ "G_SHL\000"
2172 /* 4436 */ "G_FCEIL\000"
2173 /* 4444 */ "G_SAVGCEIL\000"
2174 /* 4455 */ "G_UAVGCEIL\000"
2175 /* 4466 */ "PATCHABLE_TAIL_CALL\000"
2176 /* 4486 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2177 /* 4513 */ "PATCHABLE_EVENT_CALL\000"
2178 /* 4534 */ "FENTRY_CALL\000"
2179 /* 4546 */ "KILL\000"
2180 /* 4551 */ "G_CONSTANT_POOL\000"
2181 /* 4567 */ "G_ROTL\000"
2182 /* 4574 */ "G_VECREDUCE_FMUL\000"
2183 /* 4591 */ "G_FMUL\000"
2184 /* 4598 */ "G_VECREDUCE_SEQ_FMUL\000"
2185 /* 4619 */ "G_STRICT_FMUL\000"
2186 /* 4633 */ "G_CLMUL\000"
2187 /* 4641 */ "G_VECREDUCE_MUL\000"
2188 /* 4657 */ "G_MUL\000"
2189 /* 4663 */ "G_FREM\000"
2190 /* 4670 */ "G_STRICT_FREM\000"
2191 /* 4684 */ "G_SREM\000"
2192 /* 4691 */ "G_UREM\000"
2193 /* 4698 */ "G_SDIVREM\000"
2194 /* 4708 */ "G_UDIVREM\000"
2195 /* 4718 */ "INLINEASM\000"
2196 /* 4728 */ "G_VECREDUCE_FMINIMUM\000"
2197 /* 4749 */ "G_FMINIMUM\000"
2198 /* 4760 */ "G_ATOMICRMW_FMINIMUM\000"
2199 /* 4781 */ "G_VECREDUCE_FMAXIMUM\000"
2200 /* 4802 */ "G_FMAXIMUM\000"
2201 /* 4813 */ "G_ATOMICRMW_FMAXIMUM\000"
2202 /* 4834 */ "G_VECREDUCE_FMINIMUMNUM\000"
2203 /* 4858 */ "G_FMINIMUMNUM\000"
2204 /* 4872 */ "G_ATOMICRMW_FMINIMUMNUM\000"
2205 /* 4896 */ "G_VECREDUCE_FMAXIMUMNUM\000"
2206 /* 4920 */ "G_FMAXIMUMNUM\000"
2207 /* 4934 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
2208 /* 4958 */ "G_FMINNUM\000"
2209 /* 4968 */ "G_FMAXNUM\000"
2210 /* 4978 */ "G_FATAN\000"
2211 /* 4986 */ "G_FTAN\000"
2212 /* 4993 */ "G_INTRINSIC_ROUNDEVEN\000"
2213 /* 5015 */ "G_ASSERT_ALIGN\000"
2214 /* 5030 */ "G_FCOPYSIGN\000"
2215 /* 5042 */ "G_VECREDUCE_FMIN\000"
2216 /* 5059 */ "G_ATOMICRMW_FMIN\000"
2217 /* 5076 */ "G_VECREDUCE_SMIN\000"
2218 /* 5093 */ "G_SMIN\000"
2219 /* 5100 */ "G_VECREDUCE_UMIN\000"
2220 /* 5117 */ "G_UMIN\000"
2221 /* 5124 */ "G_ATOMICRMW_UMIN\000"
2222 /* 5141 */ "G_ATOMICRMW_MIN\000"
2223 /* 5157 */ "G_FASIN\000"
2224 /* 5165 */ "G_FSIN\000"
2225 /* 5172 */ "CFI_INSTRUCTION\000"
2226 /* 5188 */ "G_CTLZ_ZERO_POISON\000"
2227 /* 5207 */ "G_CTTZ_ZERO_POISON\000"
2228 /* 5226 */ "G_SSUBO\000"
2229 /* 5234 */ "G_USUBO\000"
2230 /* 5242 */ "G_SADDO\000"
2231 /* 5250 */ "G_UADDO\000"
2232 /* 5258 */ "JUMP_TABLE_DEBUG_INFO\000"
2233 /* 5280 */ "G_SMULO\000"
2234 /* 5288 */ "G_UMULO\000"
2235 /* 5296 */ "G_BZERO\000"
2236 /* 5304 */ "STACKMAP\000"
2237 /* 5313 */ "G_DEBUGTRAP\000"
2238 /* 5325 */ "G_UBSANTRAP\000"
2239 /* 5337 */ "G_TRAP\000"
2240 /* 5344 */ "G_ATOMICRMW_UDEC_WRAP\000"
2241 /* 5366 */ "G_ATOMICRMW_UINC_WRAP\000"
2242 /* 5388 */ "G_BSWAP\000"
2243 /* 5396 */ "G_SITOFP\000"
2244 /* 5405 */ "G_UITOFP\000"
2245 /* 5414 */ "G_FCMP\000"
2246 /* 5421 */ "G_STRICT_FCMP\000"
2247 /* 5435 */ "G_ICMP\000"
2248 /* 5442 */ "G_SCMP\000"
2249 /* 5449 */ "G_UCMP\000"
2250 /* 5456 */ "CONVERGENCECTRL_LOOP\000"
2251 /* 5477 */ "G_CTPOP\000"
2252 /* 5485 */ "PATCHABLE_OP\000"
2253 /* 5498 */ "FAULTING_OP\000"
2254 /* 5510 */ "PREALLOCATED_SETUP\000"
2255 /* 5529 */ "G_FLDEXP\000"
2256 /* 5538 */ "G_STRICT_FLDEXP\000"
2257 /* 5554 */ "G_FEXP\000"
2258 /* 5561 */ "G_FFREXP\000"
2259 /* 5570 */ "G_BR\000"
2260 /* 5575 */ "INLINEASM_BR\000"
2261 /* 5588 */ "G_BLOCK_ADDR\000"
2262 /* 5601 */ "MEMBARRIER\000"
2263 /* 5612 */ "G_CONSTANT_FOLD_BARRIER\000"
2264 /* 5636 */ "PATCHABLE_FUNCTION_ENTER\000"
2265 /* 5661 */ "G_READCYCLECOUNTER\000"
2266 /* 5680 */ "G_READSTEADYCOUNTER\000"
2267 /* 5700 */ "G_READ_REGISTER\000"
2268 /* 5716 */ "G_WRITE_REGISTER\000"
2269 /* 5733 */ "OpFmaKHR\000"
2270 /* 5742 */ "OpCooperativeMatrixLoadKHR\000"
2271 /* 5769 */ "OpCooperativeMatrixMulAddKHR\000"
2272 /* 5798 */ "OpGroupBitwiseAndKHR\000"
2273 /* 5819 */ "OpGroupLogicalAndKHR\000"
2274 /* 5840 */ "OpUntypedVariableKHR\000"
2275 /* 5861 */ "OpCooperativeMatrixStoreKHR\000"
2276 /* 5889 */ "OpGroupNonUniformRotateKHR\000"
2277 /* 5916 */ "OpAssumeTrueKHR\000"
2278 /* 5932 */ "OpFreezeKHR\000"
2279 /* 5944 */ "OpUntypedPrefetchKHR\000"
2280 /* 5965 */ "OpCooperativeMatrixLengthKHR\000"
2281 /* 5994 */ "OpReadClockKHR\000"
2282 /* 6009 */ "OpGroupFMulKHR\000"
2283 /* 6024 */ "OpGroupIMulKHR\000"
2284 /* 6039 */ "OpUntypedAccessChainKHR\000"
2285 /* 6063 */ "OpUntypedPtrAccessChainKHR\000"
2286 /* 6090 */ "OpUntypedInBoundsPtrAccessChainKHR\000"
2287 /* 6125 */ "OpUntypedInBoundsAccessChainKHR\000"
2288 /* 6157 */ "OpPoisonKHR\000"
2289 /* 6169 */ "OpGroupBitwiseOrKHR\000"
2290 /* 6189 */ "OpGroupLogicalOrKHR\000"
2291 /* 6209 */ "OpTypeUntypedPointerKHR\000"
2292 /* 6233 */ "OpGroupBitwiseXorKHR\000"
2293 /* 6254 */ "OpGroupLogicalXorKHR\000"
2294 /* 6275 */ "OpExtInstWithForwardRefsKHR\000"
2295 /* 6303 */ "OpExpectKHR\000"
2296 /* 6315 */ "OpAbortKHR\000"
2297 /* 6326 */ "OpTypeCooperativeMatrixKHR\000"
2298 /* 6353 */ "OpUntypedGroupAsyncCopyKHR\000"
2299 /* 6380 */ "G_ASHR\000"
2300 /* 6387 */ "G_FSHR\000"
2301 /* 6394 */ "G_LSHR\000"
2302 /* 6401 */ "G_CLMULR\000"
2303 /* 6410 */ "CONVERGENCECTRL_ANCHOR\000"
2304 /* 6433 */ "G_FFLOOR\000"
2305 /* 6442 */ "G_SAVGFLOOR\000"
2306 /* 6454 */ "G_UAVGFLOOR\000"
2307 /* 6466 */ "G_EXTRACT_SUBVECTOR\000"
2308 /* 6486 */ "G_INSERT_SUBVECTOR\000"
2309 /* 6505 */ "G_BUILD_VECTOR\000"
2310 /* 6520 */ "G_SHUFFLE_VECTOR\000"
2311 /* 6537 */ "G_STEP_VECTOR\000"
2312 /* 6551 */ "G_SPLAT_VECTOR\000"
2313 /* 6566 */ "G_VECREDUCE_XOR\000"
2314 /* 6582 */ "G_XOR\000"
2315 /* 6588 */ "G_ATOMICRMW_XOR\000"
2316 /* 6604 */ "G_VECREDUCE_OR\000"
2317 /* 6619 */ "G_OR\000"
2318 /* 6624 */ "G_ATOMICRMW_OR\000"
2319 /* 6639 */ "G_ROTR\000"
2320 /* 6646 */ "G_INTTOPTR\000"
2321 /* 6657 */ "G_FABS\000"
2322 /* 6664 */ "G_ABS\000"
2323 /* 6670 */ "G_ABDS\000"
2324 /* 6677 */ "G_UNMERGE_VALUES\000"
2325 /* 6694 */ "G_MERGE_VALUES\000"
2326 /* 6709 */ "G_CTLS\000"
2327 /* 6716 */ "G_FACOS\000"
2328 /* 6724 */ "G_FCOS\000"
2329 /* 6731 */ "G_FSINCOS\000"
2330 /* 6741 */ "G_STRICT_FCMPS\000"
2331 /* 6756 */ "G_CONCAT_VECTORS\000"
2332 /* 6773 */ "COPY_TO_REGCLASS\000"
2333 /* 6790 */ "G_IS_FPCLASS\000"
2334 /* 6803 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2335 /* 6833 */ "G_VECTOR_COMPRESS\000"
2336 /* 6851 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2337 /* 6878 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2338 /* 6916 */ "G_TRUNC_SSAT_S\000"
2339 /* 6931 */ "OpFSubS\000"
2340 /* 6939 */ "OpStrictFSubS\000"
2341 /* 6953 */ "OpISubS\000"
2342 /* 6961 */ "OpShiftRightArithmeticS\000"
2343 /* 6985 */ "OpFAddS\000"
2344 /* 6993 */ "OpStrictFAddS\000"
2345 /* 7007 */ "OpIAddS\000"
2346 /* 7015 */ "OpBitwiseAndS\000"
2347 /* 7029 */ "OpUModS\000"
2348 /* 7037 */ "OpShiftLeftLogicalS\000"
2349 /* 7057 */ "OpShiftRightLogicalS\000"
2350 /* 7078 */ "OpFMulS\000"
2351 /* 7086 */ "OpStrictFMulS\000"
2352 /* 7100 */ "OpIMulS\000"
2353 /* 7108 */ "OpFRemS\000"
2354 /* 7116 */ "OpStrictFRemS\000"
2355 /* 7130 */ "OpSRemS\000"
2356 /* 7138 */ "OpConvertFToS\000"
2357 /* 7152 */ "OpSatConvertUToS\000"
2358 /* 7169 */ "OpBitwiseOrS\000"
2359 /* 7182 */ "OpBitwiseXorS\000"
2360 /* 7196 */ "OpFDivS\000"
2361 /* 7204 */ "OpStrictFDivS\000"
2362 /* 7218 */ "OpSDivS\000"
2363 /* 7226 */ "OpUDivS\000"
2364 /* 7234 */ "OpISubBorrowS\000"
2365 /* 7248 */ "OpIAddCarryS\000"
2366 /* 7261 */ "G_SSUBSAT\000"
2367 /* 7271 */ "G_USUBSAT\000"
2368 /* 7281 */ "G_SADDSAT\000"
2369 /* 7291 */ "G_UADDSAT\000"
2370 /* 7301 */ "G_SSHLSAT\000"
2371 /* 7311 */ "G_USHLSAT\000"
2372 /* 7321 */ "G_SMULFIXSAT\000"
2373 /* 7334 */ "G_UMULFIXSAT\000"
2374 /* 7347 */ "G_SDIVFIXSAT\000"
2375 /* 7360 */ "G_UDIVFIXSAT\000"
2376 /* 7373 */ "G_ATOMICRMW_USUB_SAT\000"
2377 /* 7394 */ "G_FPTOSI_SAT\000"
2378 /* 7407 */ "G_FPTOUI_SAT\000"
2379 /* 7420 */ "G_EXTRACT\000"
2380 /* 7430 */ "G_SELECT\000"
2381 /* 7439 */ "G_BRINDIRECT\000"
2382 /* 7452 */ "PATCHABLE_RET\000"
2383 /* 7466 */ "G_MEMSET\000"
2384 /* 7475 */ "PATCHABLE_FUNCTION_EXIT\000"
2385 /* 7499 */ "G_BRJT\000"
2386 /* 7506 */ "G_EXTRACT_VECTOR_ELT\000"
2387 /* 7527 */ "G_INSERT_VECTOR_ELT\000"
2388 /* 7547 */ "G_FCONSTANT\000"
2389 /* 7559 */ "G_CONSTANT\000"
2390 /* 7570 */ "G_INTRINSIC_CONVERGENT\000"
2391 /* 7593 */ "STATEPOINT\000"
2392 /* 7604 */ "PATCHPOINT\000"
2393 /* 7615 */ "G_PTRTOINT\000"
2394 /* 7626 */ "G_FRINT\000"
2395 /* 7634 */ "G_INTRINSIC_LLRINT\000"
2396 /* 7653 */ "G_INTRINSIC_LRINT\000"
2397 /* 7671 */ "G_FNEARBYINT\000"
2398 /* 7684 */ "G_VASTART\000"
2399 /* 7694 */ "LIFETIME_START\000"
2400 /* 7709 */ "G_INVOKE_REGION_START\000"
2401 /* 7731 */ "G_INSERT\000"
2402 /* 7740 */ "G_FSQRT\000"
2403 /* 7748 */ "G_STRICT_FSQRT\000"
2404 /* 7763 */ "G_BITCAST\000"
2405 /* 7773 */ "G_ADDRSPACE_CAST\000"
2406 /* 7790 */ "DBG_VALUE_LIST\000"
2407 /* 7805 */ "G_FPEXT\000"
2408 /* 7813 */ "G_SEXT\000"
2409 /* 7820 */ "G_ASSERT_SEXT\000"
2410 /* 7834 */ "G_ANYEXT\000"
2411 /* 7843 */ "G_ZEXT\000"
2412 /* 7850 */ "G_ASSERT_ZEXT\000"
2413 /* 7864 */ "OpTypeVectorIdEXT\000"
2414 /* 7882 */ "OpAtomicFAddEXT\000"
2415 /* 7898 */ "OpArithmeticFenceEXT\000"
2416 /* 7919 */ "OpAtomicFMinEXT\000"
2417 /* 7935 */ "OpAtomicFMaxEXT\000"
2418 /* 7951 */ "G_ABDU\000"
2419 /* 7958 */ "G_TRUNC_SSAT_U\000"
2420 /* 7973 */ "G_TRUNC_USAT_U\000"
2421 /* 7988 */ "OpConvertFToU\000"
2422 /* 8002 */ "OpSatConvertSToU\000"
2423 /* 8019 */ "OpConvertPtrToU\000"
2424 /* 8035 */ "G_FDIV\000"
2425 /* 8042 */ "G_STRICT_FDIV\000"
2426 /* 8056 */ "G_SDIV\000"
2427 /* 8063 */ "G_UDIV\000"
2428 /* 8070 */ "G_GET_FPENV\000"
2429 /* 8082 */ "G_RESET_FPENV\000"
2430 /* 8096 */ "G_SET_FPENV\000"
2431 /* 8108 */ "OpTypeAccelerationStructureNV\000"
2432 /* 8138 */ "OpImageSampleFootprintNV\000"
2433 /* 8163 */ "OpTypeCooperativeMatrixNV\000"
2434 /* 8189 */ "OpFSubV\000"
2435 /* 8197 */ "OpStrictFSubV\000"
2436 /* 8211 */ "OpISubV\000"
2437 /* 8219 */ "OpShiftRightArithmeticV\000"
2438 /* 8243 */ "OpFAddV\000"
2439 /* 8251 */ "OpStrictFAddV\000"
2440 /* 8265 */ "OpIAddV\000"
2441 /* 8273 */ "OpBitwiseAndV\000"
2442 /* 8287 */ "OpUModV\000"
2443 /* 8295 */ "OpFNegateV\000"
2444 /* 8306 */ "OpShiftLeftLogicalV\000"
2445 /* 8326 */ "OpShiftRightLogicalV\000"
2446 /* 8347 */ "OpFMulV\000"
2447 /* 8355 */ "OpStrictFMulV\000"
2448 /* 8369 */ "OpIMulV\000"
2449 /* 8377 */ "OpFRemV\000"
2450 /* 8385 */ "OpStrictFRemV\000"
2451 /* 8399 */ "OpSRemV\000"
2452 /* 8407 */ "OpBitwiseOrV\000"
2453 /* 8420 */ "OpBitwiseXorV\000"
2454 /* 8434 */ "OpFDivV\000"
2455 /* 8442 */ "OpStrictFDivV\000"
2456 /* 8456 */ "OpSDivV\000"
2457 /* 8464 */ "OpUDivV\000"
2458 /* 8472 */ "OpISubBorrowV\000"
2459 /* 8486 */ "OpIAddCarryV\000"
2460 /* 8499 */ "G_FPOW\000"
2461 /* 8506 */ "G_VECREDUCE_FMAX\000"
2462 /* 8523 */ "G_ATOMICRMW_FMAX\000"
2463 /* 8540 */ "G_VECREDUCE_SMAX\000"
2464 /* 8557 */ "G_SMAX\000"
2465 /* 8564 */ "G_VECREDUCE_UMAX\000"
2466 /* 8581 */ "G_UMAX\000"
2467 /* 8588 */ "G_ATOMICRMW_UMAX\000"
2468 /* 8605 */ "G_ATOMICRMW_MAX\000"
2469 /* 8621 */ "G_FRAME_INDEX\000"
2470 /* 8635 */ "G_SBFX\000"
2471 /* 8642 */ "G_UBFX\000"
2472 /* 8649 */ "G_SMULFIX\000"
2473 /* 8659 */ "G_UMULFIX\000"
2474 /* 8669 */ "G_SDIVFIX\000"
2475 /* 8679 */ "G_UDIVFIX\000"
2476 /* 8689 */ "G_MEMCPY\000"
2477 /* 8698 */ "COPY\000"
2478 /* 8703 */ "CONVERGENCECTRL_ENTRY\000"
2479 /* 8725 */ "G_CTLZ\000"
2480 /* 8732 */ "G_CTTZ\000"
2481 /* 8739 */ "OpAtomicISub\000"
2482 /* 8752 */ "OpVectorExtractDynamic\000"
2483 /* 8775 */ "OpVectorInsertDynamic\000"
2484 /* 8797 */ "OpPtrCastToGeneric\000"
2485 /* 8816 */ "OpExecutionModeId\000"
2486 /* 8834 */ "OpDecorateId\000"
2487 /* 8847 */ "OpIsValidReserveId\000"
2488 /* 8866 */ "OpTypeReserveId\000"
2489 /* 8882 */ "OpImageRead\000"
2490 /* 8894 */ "OpImageSparseRead\000"
2491 /* 8912 */ "OpAtomicLoad\000"
2492 /* 8925 */ "OpLoad\000"
2493 /* 8932 */ "OpGroupNonUniformFAdd\000"
2494 /* 8954 */ "OpGroupFAdd\000"
2495 /* 8966 */ "OpAtomicIAdd\000"
2496 /* 8979 */ "OpGroupNonUniformIAdd\000"
2497 /* 9001 */ "OpGroupIAdd\000"
2498 /* 9013 */ "OpSMulExtended\000"
2499 /* 9028 */ "OpUMulExtended\000"
2500 /* 9043 */ "OpOrdered\000"
2501 /* 9053 */ "OpUnordered\000"
2502 /* 9065 */ "OpModuleProcessed\000"
2503 /* 9083 */ "OpSourceContinued\000"
2504 /* 9101 */ "OpCopyMemorySized\000"
2505 /* 9119 */ "OpTypeVoid\000"
2506 /* 9130 */ "OpAtomicAnd\000"
2507 /* 9142 */ "OpGroupNonUniformBitwiseAnd\000"
2508 /* 9170 */ "OpGroupNonUniformLogicalAnd\000"
2509 /* 9198 */ "OpLogicalAnd\000"
2510 /* 9211 */ "OpFunctionEnd\000"
2511 /* 9225 */ "OpSelectSFSCond\000"
2512 /* 9241 */ "OpSelectVFSCond\000"
2513 /* 9257 */ "OpSelectSISCond\000"
2514 /* 9273 */ "OpSelectVISCond\000"
2515 /* 9289 */ "OpSelectSPSCond\000"
2516 /* 9305 */ "OpSelectVPSCond\000"
2517 /* 9321 */ "OpSelectSFVCond\000"
2518 /* 9337 */ "OpSelectVFVCond\000"
2519 /* 9353 */ "OpSelectSIVCond\000"
2520 /* 9369 */ "OpSelectVIVCond\000"
2521 /* 9385 */ "OpSelectSPVCond\000"
2522 /* 9401 */ "OpSelectVPVCond\000"
2523 /* 9417 */ "OpImageQuerySizeLod\000"
2524 /* 9437 */ "OpImageSampleImplicitLod\000"
2525 /* 9462 */ "OpImageSparseSampleImplicitLod\000"
2526 /* 9493 */ "OpImageSampleDrefImplicitLod\000"
2527 /* 9522 */ "OpImageSparseSampleDrefImplicitLod\000"
2528 /* 9557 */ "OpImageSampleProjDrefImplicitLod\000"
2529 /* 9590 */ "OpImageSparseSampleProjDrefImplicitLod\000"
2530 /* 9629 */ "OpImageSampleProjImplicitLod\000"
2531 /* 9658 */ "OpImageSparseSampleProjImplicitLod\000"
2532 /* 9693 */ "OpImageSampleExplicitLod\000"
2533 /* 9718 */ "OpImageSparseSampleExplicitLod\000"
2534 /* 9749 */ "OpImageSampleDrefExplicitLod\000"
2535 /* 9778 */ "OpImageSparseSampleDrefExplicitLod\000"
2536 /* 9813 */ "OpImageSampleProjDrefExplicitLod\000"
2537 /* 9846 */ "OpImageSparseSampleProjDrefExplicitLod\000"
2538 /* 9885 */ "OpImageSampleProjExplicitLod\000"
2539 /* 9914 */ "OpImageSparseSampleProjExplicitLod\000"
2540 /* 9949 */ "OpImageQueryLod\000"
2541 /* 9965 */ "OpFMod\000"
2542 /* 9972 */ "OpSMod\000"
2543 /* 9979 */ "OpSource\000"
2544 /* 9988 */ "OpExecutionMode\000"
2545 /* 10004 */ "OpTypeSampledImage\000"
2546 /* 10023 */ "OpSampledImage\000"
2547 /* 10038 */ "OpTypeImage\000"
2548 /* 10050 */ "OpImage\000"
2549 /* 10058 */ "OpTypePipeStorage\000"
2550 /* 10076 */ "OpBuildNDRange\000"
2551 /* 10091 */ "OpAtomicExchange\000"
2552 /* 10108 */ "OpAtomicCompareExchange\000"
2553 /* 10132 */ "OpSelectionMerge\000"
2554 /* 10149 */ "OpLoopMerge\000"
2555 /* 10161 */ "OpUnreachable\000"
2556 /* 10175 */ "OpVariable\000"
2557 /* 10186 */ "OpGroupNonUniformShuffle\000"
2558 /* 10211 */ "OpVectorShuffle\000"
2559 /* 10227 */ "OpGetKernelPreferredWorkGroupSizeMultiple\000"
2560 /* 10269 */ "OpName\000"
2561 /* 10276 */ "OpMemberName\000"
2562 /* 10289 */ "OpFwidthFine\000"
2563 /* 10302 */ "OpDPdxFine\000"
2564 /* 10313 */ "OpDPdyFine\000"
2565 /* 10324 */ "OpNoLine\000"
2566 /* 10333 */ "OpLine\000"
2567 /* 10340 */ "OpReservedReadPipe\000"
2568 /* 10359 */ "OpReadPipe\000"
2569 /* 10370 */ "OpCommitReadPipe\000"
2570 /* 10387 */ "OpGroupCommitReadPipe\000"
2571 /* 10409 */ "OpTypePipe\000"
2572 /* 10420 */ "OpReservedWritePipe\000"
2573 /* 10440 */ "OpWritePipe\000"
2574 /* 10452 */ "OpCommitWritePipe\000"
2575 /* 10470 */ "OpGroupCommitWritePipe\000"
2576 /* 10493 */ "UNKNOWN_type\000"
2577 /* 10506 */ "OpAtomicStore\000"
2578 /* 10520 */ "OpStore\000"
2579 /* 10528 */ "OpSpecConstantFalse\000"
2580 /* 10548 */ "OpConstantFalse\000"
2581 /* 10564 */ "OpTranspose\000"
2582 /* 10576 */ "OpFwidthCoarse\000"
2583 /* 10591 */ "OpDPdxCoarse\000"
2584 /* 10604 */ "OpDPdyCoarse\000"
2585 /* 10617 */ "OpBitReverse\000"
2586 /* 10630 */ "OpFNegate\000"
2587 /* 10640 */ "OpSNegate\000"
2588 /* 10650 */ "OpDecorate\000"
2589 /* 10661 */ "OpMemberDecorate\000"
2590 /* 10678 */ "OpIsFinite\000"
2591 /* 10689 */ "OpImageWrite\000"
2592 /* 10702 */ "OpSpecConstantComposite\000"
2593 /* 10726 */ "OpConstantComposite\000"
2594 /* 10746 */ "OpTypeQueue\000"
2595 /* 10758 */ "OpGetDefaultQueue\000"
2596 /* 10776 */ "OpReturnValue\000"
2597 /* 10790 */ "OpTypeOpaque\000"
2598 /* 10803 */ "OpSpecConstantTrue\000"
2599 /* 10822 */ "OpConstantTrue\000"
2600 /* 10837 */ "OpEndPrimitive\000"
2601 /* 10852 */ "OpEndStreamPrimitive\000"
2602 /* 10873 */ "OpGetKernelNDrangeMaxSubGroupSize\000"
2603 /* 10907 */ "OpGetKernelWorkGroupSize\000"
2604 /* 10932 */ "OpImageQuerySize\000"
2605 /* 10949 */ "OpNamedBarrierInitialize\000"
2606 /* 10974 */ "OpSizeOf\000"
2607 /* 10983 */ "OpUndef\000"
2608 /* 10991 */ "OpPtrDiff\000"
2609 /* 11001 */ "OpIsInf\000"
2610 /* 11009 */ "OpDecorateString\000"
2611 /* 11026 */ "OpMemberDecorateString\000"
2612 /* 11049 */ "OpString\000"
2613 /* 11058 */ "OpBranch\000"
2614 /* 11067 */ "OpImageFetch\000"
2615 /* 11080 */ "OpImageSparseFetch\000"
2616 /* 11099 */ "OpSwitch\000"
2617 /* 11108 */ "OpFwidth\000"
2618 /* 11117 */ "OpArrayLength\000"
2619 /* 11131 */ "OpPhi\000"
2620 /* 11137 */ "OpAtomicCompareExchangeWeak\000"
2621 /* 11165 */ "OpCopyLogical\000"
2622 /* 11179 */ "OpIsNormal\000"
2623 /* 11190 */ "OpBranchConditional\000"
2624 /* 11210 */ "OpIEqual\000"
2625 /* 11219 */ "OpFOrdEqual\000"
2626 /* 11231 */ "OpFUnordEqual\000"
2627 /* 11245 */ "OpLogicalEqual\000"
2628 /* 11260 */ "OpGroupNonUniformAllEqual\000"
2629 /* 11286 */ "OpSGreaterThanEqual\000"
2630 /* 11306 */ "OpUGreaterThanEqual\000"
2631 /* 11326 */ "OpFOrdGreaterThanEqual\000"
2632 /* 11349 */ "OpFUnordGreaterThanEqual\000"
2633 /* 11374 */ "OpSLessThanEqual\000"
2634 /* 11391 */ "OpULessThanEqual\000"
2635 /* 11408 */ "OpFOrdLessThanEqual\000"
2636 /* 11428 */ "OpFUnordLessThanEqual\000"
2637 /* 11450 */ "OpPtrEqual\000"
2638 /* 11461 */ "OpINotEqual\000"
2639 /* 11473 */ "OpFOrdNotEqual\000"
2640 /* 11488 */ "OpFUnordNotEqual\000"
2641 /* 11505 */ "OpLogicalNotEqual\000"
2642 /* 11523 */ "OpPtrNotEqual\000"
2643 /* 11537 */ "OpLabel\000"
2644 /* 11545 */ "OpMemoryModel\000"
2645 /* 11559 */ "OpEnqueueKernel\000"
2646 /* 11575 */ "OpGroupNonUniformAll\000"
2647 /* 11596 */ "OpAll\000"
2648 /* 11602 */ "OpGroupAll\000"
2649 /* 11613 */ "OpFunctionCall\000"
2650 /* 11628 */ "OpKill\000"
2651 /* 11635 */ "OpConstantNull\000"
2652 /* 11650 */ "OpTypeBool\000"
2653 /* 11661 */ "OpGroupNonUniformFMul\000"
2654 /* 11683 */ "OpGroupNonUniformIMul\000"
2655 /* 11705 */ "OpIsNan\000"
2656 /* 11713 */ "OpSGreaterThan\000"
2657 /* 11728 */ "OpUGreaterThan\000"
2658 /* 11743 */ "OpFOrdGreaterThan\000"
2659 /* 11761 */ "OpFUnordGreaterThan\000"
2660 /* 11781 */ "OpSLessThan\000"
2661 /* 11793 */ "OpULessThan\000"
2662 /* 11805 */ "OpFOrdLessThan\000"
2663 /* 11820 */ "OpFUnordLessThan\000"
2664 /* 11837 */ "OpGroupNonUniformFMin\000"
2665 /* 11859 */ "OpGroupFMin\000"
2666 /* 11871 */ "OpAtomicSMin\000"
2667 /* 11884 */ "OpGroupNonUniformSMin\000"
2668 /* 11906 */ "OpGroupSMin\000"
2669 /* 11918 */ "OpAtomicUMin\000"
2670 /* 11931 */ "OpGroupNonUniformUMin\000"
2671 /* 11953 */ "OpGroupUMin\000"
2672 /* 11965 */ "OpAccessChain\000"
2673 /* 11979 */ "OpPtrAccessChain\000"
2674 /* 11996 */ "OpInBoundsPtrAccessChain\000"
2675 /* 12021 */ "OpInBoundsAccessChain\000"
2676 /* 12043 */ "OpSourceExtension\000"
2677 /* 12061 */ "OpExtension\000"
2678 /* 12073 */ "OpDemoteToHelperInvocation\000"
2679 /* 12100 */ "OpTypeFunction\000"
2680 /* 12115 */ "OpFunction\000"
2681 /* 12126 */ "OpReturn\000"
2682 /* 12135 */ "OpGroupNonUniformShuffleDown\000"
2683 /* 12164 */ "OpCaptureEventProfilingInfo\000"
2684 /* 12192 */ "OpSpecConstantOp\000"
2685 /* 12209 */ "OpGroupNonUniformShuffleUp\000"
2686 /* 12236 */ "OpGroupNonUniformQuadSwap\000"
2687 /* 12262 */ "OpNop\000"
2688 /* 12268 */ "OpLifetimeStop\000"
2689 /* 12283 */ "OpAtomicOr\000"
2690 /* 12294 */ "OpGroupNonUniformBitwiseOr\000"
2691 /* 12321 */ "OpGroupNonUniformLogicalOr\000"
2692 /* 12348 */ "OpLogicalOr\000"
2693 /* 12360 */ "OpAtomicFlagClear\000"
2694 /* 12378 */ "OpVectorTimesScalar\000"
2695 /* 12398 */ "OpMatrixTimesScalar\000"
2696 /* 12418 */ "OpImageQueryOrder\000"
2697 /* 12436 */ "OpImageGather\000"
2698 /* 12450 */ "OpImageSparseGather\000"
2699 /* 12470 */ "OpImageDrefGather\000"
2700 /* 12488 */ "OpImageSparseDrefGather\000"
2701 /* 12512 */ "OpTypeNamedBarrier\000"
2702 /* 12531 */ "OpMemoryNamedBarrier\000"
2703 /* 12552 */ "OpControlBarrier\000"
2704 /* 12569 */ "OpMemoryBarrier\000"
2705 /* 12585 */ "OpTypeSampler\000"
2706 /* 12599 */ "OpConstantSampler\000"
2707 /* 12617 */ "OpLessOrGreater\000"
2708 /* 12633 */ "OpFunctionParameter\000"
2709 /* 12653 */ "OpTypeForwardPointer\000"
2710 /* 12674 */ "OpTypePointer\000"
2711 /* 12688 */ "OpImageTexelPointer\000"
2712 /* 12708 */ "OpAtomicXor\000"
2713 /* 12720 */ "OpGroupNonUniformShuffleXor\000"
2714 /* 12748 */ "OpGroupNonUniformBitwiseXor\000"
2715 /* 12776 */ "OpGroupNonUniformLogicalXor\000"
2716 /* 12804 */ "OpTypeVector\000"
2717 /* 12817 */ "OpMatrixTimesVector\000"
2718 /* 12837 */ "OpConvertUToPtr\000"
2719 /* 12853 */ "OpGenericCastToPtr\000"
2720 /* 12872 */ "OpGenericPtrMemSemantics\000"
2721 /* 12897 */ "OpImageQuerySamples\000"
2722 /* 12917 */ "OpImageQueryLevels\000"
2723 /* 12936 */ "OpReserveReadPipePackets\000"
2724 /* 12961 */ "OpGroupReserveReadPipePackets\000"
2725 /* 12991 */ "OpReserveWritePipePackets\000"
2726 /* 13017 */ "OpGroupReserveWritePipePackets\000"
2727 /* 13048 */ "OpGetNumPipePackets\000"
2728 /* 13068 */ "OpGetMaxPipePackets\000"
2729 /* 13088 */ "OpGroupWaitEvents\000"
2730 /* 13106 */ "OpSetUserEventStatus\000"
2731 /* 13127 */ "OpSDotAccSat\000"
2732 /* 13140 */ "OpSUDotAccSat\000"
2733 /* 13154 */ "OpUDotAccSat\000"
2734 /* 13167 */ "OpImageQueryFormat\000"
2735 /* 13186 */ "OpTypeFloat\000"
2736 /* 13198 */ "OpBitFieldSExtract\000"
2737 /* 13217 */ "OpBitFieldUExtract\000"
2738 /* 13236 */ "OpCompositeExtract\000"
2739 /* 13255 */ "OpGroupNonUniformBallotBitExtract\000"
2740 /* 13289 */ "OpCopyObject\000"
2741 /* 13302 */ "OpGroupNonUniformElect\000"
2742 /* 13325 */ "OpOuterProduct\000"
2743 /* 13340 */ "OpTypeStruct\000"
2744 /* 13353 */ "OpCompositeConstruct\000"
2745 /* 13374 */ "OpAtomicFlagTestAndSet\000"
2746 /* 13397 */ "OpSignBitSet\000"
2747 /* 13410 */ "OpGenericCastToPtrExplicit\000"
2748 /* 13437 */ "OpTypeInt\000"
2749 /* 13447 */ "OpSpecConstant\000"
2750 /* 13462 */ "OpImageSparseTexelsResident\000"
2751 /* 13490 */ "OpAtomicIDecrement\000"
2752 /* 13509 */ "OpAtomicIIncrement\000"
2753 /* 13528 */ "OpIsValidEvent\000"
2754 /* 13543 */ "OpTypeDeviceEvent\000"
2755 /* 13561 */ "OpTypeEvent\000"
2756 /* 13573 */ "OpReleaseEvent\000"
2757 /* 13588 */ "OpRetainEvent\000"
2758 /* 13602 */ "OpCreateUserEvent\000"
2759 /* 13620 */ "OpEntryPoint\000"
2760 /* 13633 */ "OpGetKernelNDrangeSubGroupCount\000"
2761 /* 13665 */ "OpBitCount\000"
2762 /* 13676 */ "OpGroupNonUniformBallotBitCount\000"
2763 /* 13708 */ "OpSDot\000"
2764 /* 13715 */ "OpSUDot\000"
2765 /* 13723 */ "OpUDot\000"
2766 /* 13730 */ "OpDot\000"
2767 /* 13736 */ "OpLogicalNot\000"
2768 /* 13749 */ "OpNot\000"
2769 /* 13755 */ "OpGroupNonUniformInverseBallot\000"
2770 /* 13786 */ "OpGroupNonUniformBallot\000"
2771 /* 13810 */ "OpLifetimeStart\000"
2772 /* 13826 */ "OpBitFieldInsert\000"
2773 /* 13843 */ "OpCompositeInsert\000"
2774 /* 13861 */ "OpFConvert\000"
2775 /* 13872 */ "OpSConvert\000"
2776 /* 13883 */ "OpUConvert\000"
2777 /* 13894 */ "OpExtInstImport\000"
2778 /* 13910 */ "OpGroupNonUniformBroadcast\000"
2779 /* 13937 */ "OpGroupBroadcast\000"
2780 /* 13954 */ "OpBitcast\000"
2781 /* 13964 */ "OpExtInst\000"
2782 /* 13974 */ "OpGroupNonUniformBroadcastFirst\000"
2783 /* 14006 */ "OpGroupNonUniformFMax\000"
2784 /* 14028 */ "OpGroupFMax\000"
2785 /* 14040 */ "OpAtomicSMax\000"
2786 /* 14053 */ "OpGroupNonUniformSMax\000"
2787 /* 14075 */ "OpGroupSMax\000"
2788 /* 14087 */ "OpAtomicUMax\000"
2789 /* 14100 */ "OpGroupNonUniformUMax\000"
2790 /* 14122 */ "OpGroupUMax\000"
2791 /* 14134 */ "OpDPdx\000"
2792 /* 14141 */ "OpEmitStreamVertex\000"
2793 /* 14160 */ "OpEmitVertex\000"
2794 /* 14173 */ "OpTypeMatrix\000"
2795 /* 14186 */ "OpVectorTimesMatrix\000"
2796 /* 14206 */ "OpMatrixTimesMatrix\000"
2797 /* 14226 */ "OpTypeRuntimeArray\000"
2798 /* 14245 */ "OpTypeArray\000"
2799 /* 14257 */ "OpDPdy\000"
2800 /* 14264 */ "OpGroupNonUniformAny\000"
2801 /* 14285 */ "OpAny\000"
2802 /* 14291 */ "OpGroupAny\000"
2803 /* 14302 */ "OpGroupAsyncCopy\000"
2804 /* 14319 */ "OpCopyMemory\000"
2805 /* 14332 */ "OpCapability\000"
2806};
2807#ifdef __GNUC__
2808#pragma GCC diagnostic pop
2809#endif
2810
2811extern const unsigned SPIRVInstrNameIndices[] = {
2812 2816U, 4718U, 5575U, 5172U, 2901U, 2882U, 2910U, 4546U,
2813 2600U, 2615U, 2526U, 2513U, 2642U, 6773U, 2389U, 7790U,
2814 2539U, 2812U, 2891U, 2116U, 8698U, 2858U, 2238U, 7694U,
2815 1943U, 2067U, 2104U, 5304U, 4534U, 7604U, 2050U, 5510U,
2816 2735U, 7593U, 2288U, 5498U, 5485U, 5636U, 7452U, 7475U,
2817 4466U, 4513U, 4486U, 2927U, 2380U, 5601U, 5258U, 2277U,
2818 8703U, 6410U, 5456U, 2437U, 7820U, 7850U, 5015U, 1856U,
2819 1555U, 4657U, 8056U, 8063U, 4684U, 4691U, 4698U, 4708U,
2820 1921U, 6619U, 6582U, 6670U, 7951U, 6454U, 4455U, 6442U,
2821 4444U, 2524U, 2814U, 8621U, 2399U, 2414U, 4551U, 7420U,
2822 6677U, 7731U, 6694U, 6505U, 1625U, 6756U, 7615U, 6646U,
2823 7763U, 2480U, 5612U, 2024U, 1599U, 2006U, 7653U, 7634U,
2824 4993U, 5661U, 5680U, 1757U, 1701U, 1731U, 1670U, 1742U,
2825 1682U, 1712U, 2359U, 2313U, 2343U, 6803U, 2656U, 2673U,
2826 1872U, 1561U, 1927U, 1888U, 6624U, 6588U, 8605U, 5141U,
2827 8588U, 5124U, 1823U, 1538U, 8523U, 5059U, 4813U, 4760U,
2828 4934U, 4872U, 5366U, 5344U, 1965U, 7373U, 2096U, 2752U,
2829 1956U, 7439U, 7709U, 1577U, 6851U, 7570U, 6878U, 7834U,
2830 1617U, 6916U, 7958U, 7973U, 7559U, 7547U, 7684U, 2727U,
2831 7813U, 2629U, 7843U, 4430U, 6394U, 6380U, 4423U, 6387U,
2832 6639U, 4567U, 5435U, 5414U, 5442U, 5449U, 7430U, 5250U,
2833 2137U, 5234U, 2088U, 5242U, 2129U, 5226U, 2080U, 5288U,
2834 5280U, 2780U, 2772U, 7291U, 7281U, 7271U, 7261U, 7311U,
2835 7301U, 8649U, 8659U, 7321U, 7334U, 8669U, 8679U, 7347U,
2836 7360U, 1781U, 1517U, 4591U, 59U, 1663U, 8035U, 4663U,
2837 2505U, 8499U, 2838U, 5554U, 35U, 9U, 2720U, 18U,
2838 0U, 5529U, 5561U, 2593U, 7805U, 1589U, 2820U, 2829U,
2839 5396U, 5405U, 7394U, 7407U, 6657U, 5030U, 6790U, 2489U,
2840 4958U, 4968U, 2186U, 2201U, 4749U, 4802U, 4858U, 4920U,
2841 8070U, 8096U, 8082U, 2145U, 2173U, 2158U, 2690U, 2705U,
2842 1862U, 2872U, 5093U, 8557U, 5117U, 8581U, 6664U, 1997U,
2843 1987U, 5570U, 7499U, 2216U, 6486U, 6466U, 7527U, 7506U,
2844 6520U, 6551U, 6537U, 6833U, 8732U, 5207U, 8725U, 5188U,
2845 6709U, 5477U, 5388U, 2367U, 4633U, 2763U, 6401U, 4436U,
2846 6724U, 5165U, 6731U, 4986U, 6716U, 5157U, 4978U, 26U,
2847 2804U, 2796U, 2788U, 7740U, 6433U, 7626U, 7671U, 7773U,
2848 5588U, 2225U, 1646U, 2458U, 2328U, 1809U, 1524U, 4619U,
2849 8042U, 4670U, 65U, 7748U, 5538U, 5421U, 6741U, 5700U,
2850 5716U, 8689U, 2261U, 2470U, 7466U, 5296U, 2245U, 5337U,
2851 5313U, 5325U, 1788U, 4598U, 1764U, 4574U, 8506U, 5042U,
2852 4781U, 4728U, 4896U, 4834U, 1840U, 4641U, 1905U, 6604U,
2853 6566U, 8540U, 5076U, 8564U, 5100U, 8635U, 8642U, 2301U,
2854 10493U, 6315U, 11965U, 3858U, 3836U, 3881U, 11596U, 14285U,
2855 1044U, 674U, 856U, 598U, 189U, 829U, 569U, 449U,
2856 1376U, 1163U, 1197U, 1257U, 1137U, 775U, 1403U, 321U,
2857 106U, 217U, 1018U, 134U, 244U, 373U, 1229U, 269U,
2858 398U, 78U, 926U, 162U, 543U, 803U, 1429U, 294U,
2859 346U, 1284U, 973U, 900U, 1108U, 744U, 646U, 1330U,
2860 423U, 7898U, 11117U, 3907U, 4004U, 4280U, 5916U, 9130U,
2861 10108U, 11137U, 10091U, 7882U, 7935U, 7919U, 12360U, 13374U,
2862 8966U, 13490U, 13509U, 8739U, 8912U, 12283U, 14040U, 11871U,
2863 10506U, 14087U, 11918U, 12708U, 13665U, 13826U, 13198U, 13217U,
2864 10617U, 13954U, 7015U, 8273U, 4015U, 7169U, 8407U, 7182U,
2865 8420U, 11058U, 11190U, 10076U, 14332U, 12164U, 10370U, 10452U,
2866 13353U, 3363U, 13236U, 13843U, 10726U, 3302U, 2581U, 10548U,
2867 4171U, 2846U, 11635U, 12599U, 10822U, 12552U, 3744U, 4297U,
2868 2989U, 2967U, 7138U, 7988U, 3473U, 3438U, 4141U, 8019U,
2869 2553U, 2567U, 12837U, 3223U, 3398U, 5965U, 3150U, 5742U,
2870 5769U, 3803U, 3186U, 5861U, 11165U, 14319U, 9101U, 13289U,
2871 13602U, 4249U, 14134U, 10591U, 10302U, 14257U, 10604U, 10313U,
2872 10650U, 8834U, 11009U, 12073U, 13730U, 14141U, 14160U, 10837U,
2873 10852U, 11559U, 13620U, 9988U, 8816U, 6303U, 13964U, 13894U,
2874 6275U, 12061U, 6985U, 8243U, 13861U, 7196U, 8434U, 9965U,
2875 7078U, 8347U, 10630U, 8295U, 11219U, 11743U, 11326U, 11805U,
2876 11408U, 11473U, 7108U, 8377U, 6931U, 8189U, 11231U, 11761U,
2877 11349U, 11820U, 11428U, 11488U, 1071U, 703U, 1001U, 526U,
2878 954U, 1357U, 883U, 1088U, 722U, 627U, 1312U, 5733U,
2879 5932U, 12115U, 11613U, 9211U, 12633U, 3922U, 11108U, 10576U,
2880 10289U, 12853U, 13410U, 12872U, 10758U, 10873U, 13633U, 10227U,
2881 10907U, 13068U, 13048U, 11602U, 14291U, 14302U, 5798U, 6169U,
2882 6233U, 13937U, 10387U, 10470U, 8954U, 14028U, 11859U, 6009U,
2883 9001U, 6024U, 5819U, 6189U, 6254U, 11575U, 11260U, 14264U,
2884 13786U, 13676U, 13255U, 1455U, 1486U, 9142U, 12294U, 12748U,
2885 13910U, 13974U, 13302U, 8932U, 14006U, 11837U, 11661U, 8979U,
2886 11683U, 13755U, 9170U, 12321U, 12776U, 12236U, 5889U, 14053U,
2887 11884U, 10186U, 12135U, 12209U, 12720U, 14100U, 11931U, 12961U,
2888 13017U, 14075U, 11906U, 14122U, 11953U, 13088U, 7248U, 8486U,
2889 7007U, 8265U, 11210U, 7100U, 8369U, 11461U, 7234U, 8472U,
2890 6953U, 8211U, 10050U, 12470U, 11067U, 12436U, 13167U, 12917U,
2891 9949U, 12418U, 12897U, 10932U, 9417U, 8882U, 9749U, 9493U,
2892 9693U, 8138U, 9437U, 9813U, 9557U, 9885U, 9629U, 12488U,
2893 11080U, 12450U, 8894U, 9778U, 9522U, 9718U, 9462U, 9846U,
2894 9590U, 9914U, 9658U, 13462U, 12688U, 10689U, 12021U, 11996U,
2895 10678U, 11001U, 11705U, 11179U, 13528U, 8847U, 11628U, 11537U,
2896 12617U, 13810U, 12268U, 10333U, 8925U, 9198U, 11245U, 13736U,
2897 11505U, 12348U, 3949U, 10149U, 4121U, 4202U, 14206U, 12398U,
2898 12817U, 10661U, 11026U, 10276U, 12569U, 11545U, 12531U, 9065U,
2899 10269U, 10949U, 10324U, 12262U, 13749U, 9043U, 13325U, 11131U,
2900 6157U, 3101U, 3524U, 11979U, 4090U, 8797U, 10991U, 11450U,
2901 11523U, 43U, 5994U, 10359U, 475U, 13573U, 12936U, 12991U,
2902 10340U, 10420U, 4384U, 13588U, 12126U, 10776U, 2947U, 13872U,
2903 7218U, 8456U, 13708U, 13127U, 11713U, 11286U, 11781U, 11374U,
2904 9972U, 9013U, 10640U, 7130U, 8399U, 13715U, 13140U, 10023U,
2905 8002U, 7152U, 4405U, 9225U, 9321U, 9257U, 9353U, 9289U,
2906 9385U, 9241U, 9337U, 9273U, 9369U, 9305U, 9401U, 10132U,
2907 13106U, 7037U, 8306U, 6961U, 8219U, 7057U, 8326U, 13397U,
2908 10974U, 9979U, 9083U, 12043U, 13447U, 10702U, 3264U, 10528U,
2909 12192U, 10803U, 10520U, 6993U, 8251U, 7204U, 8442U, 7086U,
2910 8355U, 7116U, 8385U, 6939U, 8197U, 11049U, 3123U, 3968U,
2911 3575U, 3772U, 3547U, 3076U, 3718U, 3046U, 3687U, 3011U,
2912 3651U, 3611U, 4038U, 3501U, 4065U, 4223U, 11099U, 10564U,
2913 8108U, 14245U, 11650U, 6326U, 8163U, 13543U, 13561U, 13186U,
2914 12653U, 12100U, 10038U, 13437U, 14173U, 12512U, 10790U, 10409U,
2915 10058U, 12674U, 10746U, 8866U, 14226U, 10004U, 12585U, 13340U,
2916 3336U, 6209U, 12804U, 7864U, 9119U, 13883U, 7226U, 8464U,
2917 13723U, 13154U, 11728U, 11306U, 11793U, 11391U, 7029U, 8287U,
2918 9028U, 10983U, 9053U, 10161U, 6039U, 6353U, 6125U, 6090U,
2919 5944U, 6063U, 5840U, 4323U, 10175U, 4357U, 8752U, 8775U,
2920 10211U, 14186U, 12378U, 10440U, 500U,
2921};
2922
2923static inline void InitSPIRVMCInstrInfo(MCInstrInfo *II) {
2924 II->InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 869, nullptr, 0);
2925}
2926
2927
2928} // namespace llvm
2929
2930#endif // GET_INSTRINFO_MC_DESC
2931
2932#ifdef GET_INSTRINFO_HEADER
2933#undef GET_INSTRINFO_HEADER
2934
2935namespace llvm {
2936
2937struct SPIRVGenInstrInfo : public TargetInstrInfo {
2938 explicit SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2939 ~SPIRVGenInstrInfo() override = default;
2940};
2941
2942} // namespace llvm
2943
2944namespace llvm::SPIRV {
2945
2946
2947} // namespace llvm::SPIRV
2948
2949#endif // GET_INSTRINFO_HEADER
2950
2951#ifdef GET_INSTRINFO_HELPER_DECLS
2952#undef GET_INSTRINFO_HELPER_DECLS
2953
2954
2955#endif // GET_INSTRINFO_HELPER_DECLS
2956
2957#ifdef GET_INSTRINFO_HELPERS
2958#undef GET_INSTRINFO_HELPERS
2959
2960
2961#endif // GET_INSTRINFO_HELPERS
2962
2963#ifdef GET_INSTRINFO_CTOR_DTOR
2964#undef GET_INSTRINFO_CTOR_DTOR
2965
2966namespace llvm {
2967
2968extern const SPIRVInstrTable SPIRVDescs;
2969extern const unsigned SPIRVInstrNameIndices[];
2970extern const char SPIRVInstrNameData[];
2971SPIRVGenInstrInfo::SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2972 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2973 InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 869);
2974}
2975
2976} // namespace llvm
2977
2978#endif // GET_INSTRINFO_CTOR_DTOR
2979
2980#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2981#undef GET_INSTRINFO_MC_HELPER_DECLS
2982
2983namespace llvm {
2984
2985class MCInst;
2986class FeatureBitset;
2987
2988namespace SPIRV_MC {
2989
2990void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2991
2992} // namespace SPIRV_MC
2993
2994} // namespace llvm
2995
2996#endif // GET_INSTRINFO_MC_HELPER_DECLS
2997
2998#ifdef GET_INSTRINFO_MC_HELPERS
2999#undef GET_INSTRINFO_MC_HELPERS
3000
3001namespace llvm::SPIRV_MC {
3002
3003
3004} // namespace llvm::SPIRV_MC
3005
3006#endif // GET_INSTRINFO_MC_HELPERS
3007
3008#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3009 defined(GET_AVAILABLE_OPCODE_CHECKER)
3010#define GET_COMPUTE_FEATURES
3011#endif
3012#ifdef GET_COMPUTE_FEATURES
3013#undef GET_COMPUTE_FEATURES
3014
3015namespace llvm::SPIRV_MC {
3016
3017// Bits for subtarget features that participate in instruction matching.
3018enum SubtargetFeatureBits : uint8_t {
3019};
3020
3021inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3022 FeatureBitset Features;
3023 return Features;
3024}
3025
3026inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3027 enum : uint8_t {
3028 CEFBS_None,
3029 };
3030
3031 static constexpr FeatureBitset FeatureBitsets[] = {
3032 {}, // CEFBS_None
3033 };
3034 static constexpr uint8_t RequiredFeaturesRefs[] = {
3035 CEFBS_None, // PHI
3036 CEFBS_None, // INLINEASM
3037 CEFBS_None, // INLINEASM_BR
3038 CEFBS_None, // CFI_INSTRUCTION
3039 CEFBS_None, // EH_LABEL
3040 CEFBS_None, // GC_LABEL
3041 CEFBS_None, // ANNOTATION_LABEL
3042 CEFBS_None, // KILL
3043 CEFBS_None, // EXTRACT_SUBREG
3044 CEFBS_None, // INSERT_SUBREG
3045 CEFBS_None, // IMPLICIT_DEF
3046 CEFBS_None, // INIT_UNDEF
3047 CEFBS_None, // SUBREG_TO_REG
3048 CEFBS_None, // COPY_TO_REGCLASS
3049 CEFBS_None, // DBG_VALUE
3050 CEFBS_None, // DBG_VALUE_LIST
3051 CEFBS_None, // DBG_INSTR_REF
3052 CEFBS_None, // DBG_PHI
3053 CEFBS_None, // DBG_LABEL
3054 CEFBS_None, // REG_SEQUENCE
3055 CEFBS_None, // COPY
3056 CEFBS_None, // COPY_LANEMASK
3057 CEFBS_None, // BUNDLE
3058 CEFBS_None, // LIFETIME_START
3059 CEFBS_None, // LIFETIME_END
3060 CEFBS_None, // PSEUDO_PROBE
3061 CEFBS_None, // ARITH_FENCE
3062 CEFBS_None, // STACKMAP
3063 CEFBS_None, // FENTRY_CALL
3064 CEFBS_None, // PATCHPOINT
3065 CEFBS_None, // LOAD_STACK_GUARD
3066 CEFBS_None, // PREALLOCATED_SETUP
3067 CEFBS_None, // PREALLOCATED_ARG
3068 CEFBS_None, // STATEPOINT
3069 CEFBS_None, // LOCAL_ESCAPE
3070 CEFBS_None, // FAULTING_OP
3071 CEFBS_None, // PATCHABLE_OP
3072 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
3073 CEFBS_None, // PATCHABLE_RET
3074 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
3075 CEFBS_None, // PATCHABLE_TAIL_CALL
3076 CEFBS_None, // PATCHABLE_EVENT_CALL
3077 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
3078 CEFBS_None, // ICALL_BRANCH_FUNNEL
3079 CEFBS_None, // FAKE_USE
3080 CEFBS_None, // MEMBARRIER
3081 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
3082 CEFBS_None, // RELOC_NONE
3083 CEFBS_None, // CONVERGENCECTRL_ENTRY
3084 CEFBS_None, // CONVERGENCECTRL_ANCHOR
3085 CEFBS_None, // CONVERGENCECTRL_LOOP
3086 CEFBS_None, // CONVERGENCECTRL_GLUE
3087 CEFBS_None, // G_ASSERT_SEXT
3088 CEFBS_None, // G_ASSERT_ZEXT
3089 CEFBS_None, // G_ASSERT_ALIGN
3090 CEFBS_None, // G_ADD
3091 CEFBS_None, // G_SUB
3092 CEFBS_None, // G_MUL
3093 CEFBS_None, // G_SDIV
3094 CEFBS_None, // G_UDIV
3095 CEFBS_None, // G_SREM
3096 CEFBS_None, // G_UREM
3097 CEFBS_None, // G_SDIVREM
3098 CEFBS_None, // G_UDIVREM
3099 CEFBS_None, // G_AND
3100 CEFBS_None, // G_OR
3101 CEFBS_None, // G_XOR
3102 CEFBS_None, // G_ABDS
3103 CEFBS_None, // G_ABDU
3104 CEFBS_None, // G_UAVGFLOOR
3105 CEFBS_None, // G_UAVGCEIL
3106 CEFBS_None, // G_SAVGFLOOR
3107 CEFBS_None, // G_SAVGCEIL
3108 CEFBS_None, // G_IMPLICIT_DEF
3109 CEFBS_None, // G_PHI
3110 CEFBS_None, // G_FRAME_INDEX
3111 CEFBS_None, // G_GLOBAL_VALUE
3112 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3113 CEFBS_None, // G_CONSTANT_POOL
3114 CEFBS_None, // G_EXTRACT
3115 CEFBS_None, // G_UNMERGE_VALUES
3116 CEFBS_None, // G_INSERT
3117 CEFBS_None, // G_MERGE_VALUES
3118 CEFBS_None, // G_BUILD_VECTOR
3119 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3120 CEFBS_None, // G_CONCAT_VECTORS
3121 CEFBS_None, // G_PTRTOINT
3122 CEFBS_None, // G_INTTOPTR
3123 CEFBS_None, // G_BITCAST
3124 CEFBS_None, // G_FREEZE
3125 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3126 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3127 CEFBS_None, // G_INTRINSIC_TRUNC
3128 CEFBS_None, // G_INTRINSIC_ROUND
3129 CEFBS_None, // G_INTRINSIC_LRINT
3130 CEFBS_None, // G_INTRINSIC_LLRINT
3131 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3132 CEFBS_None, // G_READCYCLECOUNTER
3133 CEFBS_None, // G_READSTEADYCOUNTER
3134 CEFBS_None, // G_LOAD
3135 CEFBS_None, // G_SEXTLOAD
3136 CEFBS_None, // G_ZEXTLOAD
3137 CEFBS_None, // G_FPEXTLOAD
3138 CEFBS_None, // G_INDEXED_LOAD
3139 CEFBS_None, // G_INDEXED_SEXTLOAD
3140 CEFBS_None, // G_INDEXED_ZEXTLOAD
3141 CEFBS_None, // G_STORE
3142 CEFBS_None, // G_FPTRUNCSTORE
3143 CEFBS_None, // G_INDEXED_STORE
3144 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3145 CEFBS_None, // G_ATOMIC_CMPXCHG
3146 CEFBS_None, // G_ATOMICRMW_XCHG
3147 CEFBS_None, // G_ATOMICRMW_ADD
3148 CEFBS_None, // G_ATOMICRMW_SUB
3149 CEFBS_None, // G_ATOMICRMW_AND
3150 CEFBS_None, // G_ATOMICRMW_NAND
3151 CEFBS_None, // G_ATOMICRMW_OR
3152 CEFBS_None, // G_ATOMICRMW_XOR
3153 CEFBS_None, // G_ATOMICRMW_MAX
3154 CEFBS_None, // G_ATOMICRMW_MIN
3155 CEFBS_None, // G_ATOMICRMW_UMAX
3156 CEFBS_None, // G_ATOMICRMW_UMIN
3157 CEFBS_None, // G_ATOMICRMW_FADD
3158 CEFBS_None, // G_ATOMICRMW_FSUB
3159 CEFBS_None, // G_ATOMICRMW_FMAX
3160 CEFBS_None, // G_ATOMICRMW_FMIN
3161 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3162 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3163 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
3164 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
3165 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3166 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3167 CEFBS_None, // G_ATOMICRMW_USUB_COND
3168 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3169 CEFBS_None, // G_FENCE
3170 CEFBS_None, // G_PREFETCH
3171 CEFBS_None, // G_BRCOND
3172 CEFBS_None, // G_BRINDIRECT
3173 CEFBS_None, // G_INVOKE_REGION_START
3174 CEFBS_None, // G_INTRINSIC
3175 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3176 CEFBS_None, // G_INTRINSIC_CONVERGENT
3177 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3178 CEFBS_None, // G_ANYEXT
3179 CEFBS_None, // G_TRUNC
3180 CEFBS_None, // G_TRUNC_SSAT_S
3181 CEFBS_None, // G_TRUNC_SSAT_U
3182 CEFBS_None, // G_TRUNC_USAT_U
3183 CEFBS_None, // G_CONSTANT
3184 CEFBS_None, // G_FCONSTANT
3185 CEFBS_None, // G_VASTART
3186 CEFBS_None, // G_VAARG
3187 CEFBS_None, // G_SEXT
3188 CEFBS_None, // G_SEXT_INREG
3189 CEFBS_None, // G_ZEXT
3190 CEFBS_None, // G_SHL
3191 CEFBS_None, // G_LSHR
3192 CEFBS_None, // G_ASHR
3193 CEFBS_None, // G_FSHL
3194 CEFBS_None, // G_FSHR
3195 CEFBS_None, // G_ROTR
3196 CEFBS_None, // G_ROTL
3197 CEFBS_None, // G_ICMP
3198 CEFBS_None, // G_FCMP
3199 CEFBS_None, // G_SCMP
3200 CEFBS_None, // G_UCMP
3201 CEFBS_None, // G_SELECT
3202 CEFBS_None, // G_UADDO
3203 CEFBS_None, // G_UADDE
3204 CEFBS_None, // G_USUBO
3205 CEFBS_None, // G_USUBE
3206 CEFBS_None, // G_SADDO
3207 CEFBS_None, // G_SADDE
3208 CEFBS_None, // G_SSUBO
3209 CEFBS_None, // G_SSUBE
3210 CEFBS_None, // G_UMULO
3211 CEFBS_None, // G_SMULO
3212 CEFBS_None, // G_UMULH
3213 CEFBS_None, // G_SMULH
3214 CEFBS_None, // G_UADDSAT
3215 CEFBS_None, // G_SADDSAT
3216 CEFBS_None, // G_USUBSAT
3217 CEFBS_None, // G_SSUBSAT
3218 CEFBS_None, // G_USHLSAT
3219 CEFBS_None, // G_SSHLSAT
3220 CEFBS_None, // G_SMULFIX
3221 CEFBS_None, // G_UMULFIX
3222 CEFBS_None, // G_SMULFIXSAT
3223 CEFBS_None, // G_UMULFIXSAT
3224 CEFBS_None, // G_SDIVFIX
3225 CEFBS_None, // G_UDIVFIX
3226 CEFBS_None, // G_SDIVFIXSAT
3227 CEFBS_None, // G_UDIVFIXSAT
3228 CEFBS_None, // G_FADD
3229 CEFBS_None, // G_FSUB
3230 CEFBS_None, // G_FMUL
3231 CEFBS_None, // G_FMA
3232 CEFBS_None, // G_FMAD
3233 CEFBS_None, // G_FDIV
3234 CEFBS_None, // G_FREM
3235 CEFBS_None, // G_FMODF
3236 CEFBS_None, // G_FPOW
3237 CEFBS_None, // G_FPOWI
3238 CEFBS_None, // G_FEXP
3239 CEFBS_None, // G_FEXP2
3240 CEFBS_None, // G_FEXP10
3241 CEFBS_None, // G_FLOG
3242 CEFBS_None, // G_FLOG2
3243 CEFBS_None, // G_FLOG10
3244 CEFBS_None, // G_FLDEXP
3245 CEFBS_None, // G_FFREXP
3246 CEFBS_None, // G_FNEG
3247 CEFBS_None, // G_FPEXT
3248 CEFBS_None, // G_FPTRUNC
3249 CEFBS_None, // G_FPTOSI
3250 CEFBS_None, // G_FPTOUI
3251 CEFBS_None, // G_SITOFP
3252 CEFBS_None, // G_UITOFP
3253 CEFBS_None, // G_FPTOSI_SAT
3254 CEFBS_None, // G_FPTOUI_SAT
3255 CEFBS_None, // G_FABS
3256 CEFBS_None, // G_FCOPYSIGN
3257 CEFBS_None, // G_IS_FPCLASS
3258 CEFBS_None, // G_FCANONICALIZE
3259 CEFBS_None, // G_FMINNUM
3260 CEFBS_None, // G_FMAXNUM
3261 CEFBS_None, // G_FMINNUM_IEEE
3262 CEFBS_None, // G_FMAXNUM_IEEE
3263 CEFBS_None, // G_FMINIMUM
3264 CEFBS_None, // G_FMAXIMUM
3265 CEFBS_None, // G_FMINIMUMNUM
3266 CEFBS_None, // G_FMAXIMUMNUM
3267 CEFBS_None, // G_GET_FPENV
3268 CEFBS_None, // G_SET_FPENV
3269 CEFBS_None, // G_RESET_FPENV
3270 CEFBS_None, // G_GET_FPMODE
3271 CEFBS_None, // G_SET_FPMODE
3272 CEFBS_None, // G_RESET_FPMODE
3273 CEFBS_None, // G_GET_ROUNDING
3274 CEFBS_None, // G_SET_ROUNDING
3275 CEFBS_None, // G_PTR_ADD
3276 CEFBS_None, // G_PTRMASK
3277 CEFBS_None, // G_SMIN
3278 CEFBS_None, // G_SMAX
3279 CEFBS_None, // G_UMIN
3280 CEFBS_None, // G_UMAX
3281 CEFBS_None, // G_ABS
3282 CEFBS_None, // G_LROUND
3283 CEFBS_None, // G_LLROUND
3284 CEFBS_None, // G_BR
3285 CEFBS_None, // G_BRJT
3286 CEFBS_None, // G_VSCALE
3287 CEFBS_None, // G_INSERT_SUBVECTOR
3288 CEFBS_None, // G_EXTRACT_SUBVECTOR
3289 CEFBS_None, // G_INSERT_VECTOR_ELT
3290 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3291 CEFBS_None, // G_SHUFFLE_VECTOR
3292 CEFBS_None, // G_SPLAT_VECTOR
3293 CEFBS_None, // G_STEP_VECTOR
3294 CEFBS_None, // G_VECTOR_COMPRESS
3295 CEFBS_None, // G_CTTZ
3296 CEFBS_None, // G_CTTZ_ZERO_POISON
3297 CEFBS_None, // G_CTLZ
3298 CEFBS_None, // G_CTLZ_ZERO_POISON
3299 CEFBS_None, // G_CTLS
3300 CEFBS_None, // G_CTPOP
3301 CEFBS_None, // G_BSWAP
3302 CEFBS_None, // G_BITREVERSE
3303 CEFBS_None, // G_CLMUL
3304 CEFBS_None, // G_CLMULH
3305 CEFBS_None, // G_CLMULR
3306 CEFBS_None, // G_FCEIL
3307 CEFBS_None, // G_FCOS
3308 CEFBS_None, // G_FSIN
3309 CEFBS_None, // G_FSINCOS
3310 CEFBS_None, // G_FTAN
3311 CEFBS_None, // G_FACOS
3312 CEFBS_None, // G_FASIN
3313 CEFBS_None, // G_FATAN
3314 CEFBS_None, // G_FATAN2
3315 CEFBS_None, // G_FCOSH
3316 CEFBS_None, // G_FSINH
3317 CEFBS_None, // G_FTANH
3318 CEFBS_None, // G_FSQRT
3319 CEFBS_None, // G_FFLOOR
3320 CEFBS_None, // G_FRINT
3321 CEFBS_None, // G_FNEARBYINT
3322 CEFBS_None, // G_ADDRSPACE_CAST
3323 CEFBS_None, // G_BLOCK_ADDR
3324 CEFBS_None, // G_JUMP_TABLE
3325 CEFBS_None, // G_DYN_STACKALLOC
3326 CEFBS_None, // G_STACKSAVE
3327 CEFBS_None, // G_STACKRESTORE
3328 CEFBS_None, // G_STRICT_FADD
3329 CEFBS_None, // G_STRICT_FSUB
3330 CEFBS_None, // G_STRICT_FMUL
3331 CEFBS_None, // G_STRICT_FDIV
3332 CEFBS_None, // G_STRICT_FREM
3333 CEFBS_None, // G_STRICT_FMA
3334 CEFBS_None, // G_STRICT_FSQRT
3335 CEFBS_None, // G_STRICT_FLDEXP
3336 CEFBS_None, // G_STRICT_FCMP
3337 CEFBS_None, // G_STRICT_FCMPS
3338 CEFBS_None, // G_READ_REGISTER
3339 CEFBS_None, // G_WRITE_REGISTER
3340 CEFBS_None, // G_MEMCPY
3341 CEFBS_None, // G_MEMCPY_INLINE
3342 CEFBS_None, // G_MEMMOVE
3343 CEFBS_None, // G_MEMSET
3344 CEFBS_None, // G_BZERO
3345 CEFBS_None, // G_MEMSET_INLINE
3346 CEFBS_None, // G_TRAP
3347 CEFBS_None, // G_DEBUGTRAP
3348 CEFBS_None, // G_UBSANTRAP
3349 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3350 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3351 CEFBS_None, // G_VECREDUCE_FADD
3352 CEFBS_None, // G_VECREDUCE_FMUL
3353 CEFBS_None, // G_VECREDUCE_FMAX
3354 CEFBS_None, // G_VECREDUCE_FMIN
3355 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3356 CEFBS_None, // G_VECREDUCE_FMINIMUM
3357 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
3358 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
3359 CEFBS_None, // G_VECREDUCE_ADD
3360 CEFBS_None, // G_VECREDUCE_MUL
3361 CEFBS_None, // G_VECREDUCE_AND
3362 CEFBS_None, // G_VECREDUCE_OR
3363 CEFBS_None, // G_VECREDUCE_XOR
3364 CEFBS_None, // G_VECREDUCE_SMAX
3365 CEFBS_None, // G_VECREDUCE_SMIN
3366 CEFBS_None, // G_VECREDUCE_UMAX
3367 CEFBS_None, // G_VECREDUCE_UMIN
3368 CEFBS_None, // G_SBFX
3369 CEFBS_None, // G_UBFX
3370 CEFBS_None, // ASSIGN_TYPE
3371 CEFBS_None, // UNKNOWN_type
3372 CEFBS_None, // OpAbortKHR
3373 CEFBS_None, // OpAccessChain
3374 CEFBS_None, // OpAliasDomainDeclINTEL
3375 CEFBS_None, // OpAliasScopeDeclINTEL
3376 CEFBS_None, // OpAliasScopeListDeclINTEL
3377 CEFBS_None, // OpAll
3378 CEFBS_None, // OpAny
3379 CEFBS_None, // OpArbitraryFloatACosALTERA
3380 CEFBS_None, // OpArbitraryFloatACosPiALTERA
3381 CEFBS_None, // OpArbitraryFloatASinALTERA
3382 CEFBS_None, // OpArbitraryFloatASinPiALTERA
3383 CEFBS_None, // OpArbitraryFloatATan2ALTERA
3384 CEFBS_None, // OpArbitraryFloatATanALTERA
3385 CEFBS_None, // OpArbitraryFloatATanPiALTERA
3386 CEFBS_None, // OpArbitraryFloatAddALTERA
3387 CEFBS_None, // OpArbitraryFloatCastALTERA
3388 CEFBS_None, // OpArbitraryFloatCastFromIntALTERA
3389 CEFBS_None, // OpArbitraryFloatCastToIntALTERA
3390 CEFBS_None, // OpArbitraryFloatCbrtALTERA
3391 CEFBS_None, // OpArbitraryFloatCosALTERA
3392 CEFBS_None, // OpArbitraryFloatCosPiALTERA
3393 CEFBS_None, // OpArbitraryFloatDivALTERA
3394 CEFBS_None, // OpArbitraryFloatEQALTERA
3395 CEFBS_None, // OpArbitraryFloatExp10ALTERA
3396 CEFBS_None, // OpArbitraryFloatExp2ALTERA
3397 CEFBS_None, // OpArbitraryFloatExpALTERA
3398 CEFBS_None, // OpArbitraryFloatExpm1ALTERA
3399 CEFBS_None, // OpArbitraryFloatGEALTERA
3400 CEFBS_None, // OpArbitraryFloatGTALTERA
3401 CEFBS_None, // OpArbitraryFloatHypotALTERA
3402 CEFBS_None, // OpArbitraryFloatLEALTERA
3403 CEFBS_None, // OpArbitraryFloatLTALTERA
3404 CEFBS_None, // OpArbitraryFloatLog10ALTERA
3405 CEFBS_None, // OpArbitraryFloatLog1pALTERA
3406 CEFBS_None, // OpArbitraryFloatLog2ALTERA
3407 CEFBS_None, // OpArbitraryFloatLogALTERA
3408 CEFBS_None, // OpArbitraryFloatMulALTERA
3409 CEFBS_None, // OpArbitraryFloatPowALTERA
3410 CEFBS_None, // OpArbitraryFloatPowNALTERA
3411 CEFBS_None, // OpArbitraryFloatPowRALTERA
3412 CEFBS_None, // OpArbitraryFloatRSqrtALTERA
3413 CEFBS_None, // OpArbitraryFloatRecipALTERA
3414 CEFBS_None, // OpArbitraryFloatSinALTERA
3415 CEFBS_None, // OpArbitraryFloatSinCosALTERA
3416 CEFBS_None, // OpArbitraryFloatSinCosPiALTERA
3417 CEFBS_None, // OpArbitraryFloatSinPiALTERA
3418 CEFBS_None, // OpArbitraryFloatSqrtALTERA
3419 CEFBS_None, // OpArbitraryFloatSubALTERA
3420 CEFBS_None, // OpArithmeticFenceEXT
3421 CEFBS_None, // OpArrayLength
3422 CEFBS_None, // OpAsmCallINTEL
3423 CEFBS_None, // OpAsmINTEL
3424 CEFBS_None, // OpAsmTargetINTEL
3425 CEFBS_None, // OpAssumeTrueKHR
3426 CEFBS_None, // OpAtomicAnd
3427 CEFBS_None, // OpAtomicCompareExchange
3428 CEFBS_None, // OpAtomicCompareExchangeWeak
3429 CEFBS_None, // OpAtomicExchange
3430 CEFBS_None, // OpAtomicFAddEXT
3431 CEFBS_None, // OpAtomicFMaxEXT
3432 CEFBS_None, // OpAtomicFMinEXT
3433 CEFBS_None, // OpAtomicFlagClear
3434 CEFBS_None, // OpAtomicFlagTestAndSet
3435 CEFBS_None, // OpAtomicIAdd
3436 CEFBS_None, // OpAtomicIDecrement
3437 CEFBS_None, // OpAtomicIIncrement
3438 CEFBS_None, // OpAtomicISub
3439 CEFBS_None, // OpAtomicLoad
3440 CEFBS_None, // OpAtomicOr
3441 CEFBS_None, // OpAtomicSMax
3442 CEFBS_None, // OpAtomicSMin
3443 CEFBS_None, // OpAtomicStore
3444 CEFBS_None, // OpAtomicUMax
3445 CEFBS_None, // OpAtomicUMin
3446 CEFBS_None, // OpAtomicXor
3447 CEFBS_None, // OpBitCount
3448 CEFBS_None, // OpBitFieldInsert
3449 CEFBS_None, // OpBitFieldSExtract
3450 CEFBS_None, // OpBitFieldUExtract
3451 CEFBS_None, // OpBitReverse
3452 CEFBS_None, // OpBitcast
3453 CEFBS_None, // OpBitwiseAndS
3454 CEFBS_None, // OpBitwiseAndV
3455 CEFBS_None, // OpBitwiseFunctionINTEL
3456 CEFBS_None, // OpBitwiseOrS
3457 CEFBS_None, // OpBitwiseOrV
3458 CEFBS_None, // OpBitwiseXorS
3459 CEFBS_None, // OpBitwiseXorV
3460 CEFBS_None, // OpBranch
3461 CEFBS_None, // OpBranchConditional
3462 CEFBS_None, // OpBuildNDRange
3463 CEFBS_None, // OpCapability
3464 CEFBS_None, // OpCaptureEventProfilingInfo
3465 CEFBS_None, // OpCommitReadPipe
3466 CEFBS_None, // OpCommitWritePipe
3467 CEFBS_None, // OpCompositeConstruct
3468 CEFBS_None, // OpCompositeConstructContinuedINTEL
3469 CEFBS_None, // OpCompositeExtract
3470 CEFBS_None, // OpCompositeInsert
3471 CEFBS_None, // OpConstantComposite
3472 CEFBS_None, // OpConstantCompositeContinuedINTEL
3473 CEFBS_None, // OpConstantF
3474 CEFBS_None, // OpConstantFalse
3475 CEFBS_None, // OpConstantFunctionPointerINTEL
3476 CEFBS_None, // OpConstantI
3477 CEFBS_None, // OpConstantNull
3478 CEFBS_None, // OpConstantSampler
3479 CEFBS_None, // OpConstantTrue
3480 CEFBS_None, // OpControlBarrier
3481 CEFBS_None, // OpControlBarrierArriveINTEL
3482 CEFBS_None, // OpControlBarrierWaitINTEL
3483 CEFBS_None, // OpConvertBF16ToFINTEL
3484 CEFBS_None, // OpConvertFToBF16INTEL
3485 CEFBS_None, // OpConvertFToS
3486 CEFBS_None, // OpConvertFToU
3487 CEFBS_None, // OpConvertHandleToImageINTEL
3488 CEFBS_None, // OpConvertHandleToSampledImageINTEL
3489 CEFBS_None, // OpConvertHandleToSamplerINTEL
3490 CEFBS_None, // OpConvertPtrToU
3491 CEFBS_None, // OpConvertSToF
3492 CEFBS_None, // OpConvertUToF
3493 CEFBS_None, // OpConvertUToPtr
3494 CEFBS_None, // OpCooperativeMatrixConstructCheckedINTEL
3495 CEFBS_None, // OpCooperativeMatrixGetElementCoordINTEL
3496 CEFBS_None, // OpCooperativeMatrixLengthKHR
3497 CEFBS_None, // OpCooperativeMatrixLoadCheckedINTEL
3498 CEFBS_None, // OpCooperativeMatrixLoadKHR
3499 CEFBS_None, // OpCooperativeMatrixMulAddKHR
3500 CEFBS_None, // OpCooperativeMatrixPrefetchINTEL
3501 CEFBS_None, // OpCooperativeMatrixStoreCheckedINTEL
3502 CEFBS_None, // OpCooperativeMatrixStoreKHR
3503 CEFBS_None, // OpCopyLogical
3504 CEFBS_None, // OpCopyMemory
3505 CEFBS_None, // OpCopyMemorySized
3506 CEFBS_None, // OpCopyObject
3507 CEFBS_None, // OpCreateUserEvent
3508 CEFBS_None, // OpCrossWorkgroupCastToPtrINTEL
3509 CEFBS_None, // OpDPdx
3510 CEFBS_None, // OpDPdxCoarse
3511 CEFBS_None, // OpDPdxFine
3512 CEFBS_None, // OpDPdy
3513 CEFBS_None, // OpDPdyCoarse
3514 CEFBS_None, // OpDPdyFine
3515 CEFBS_None, // OpDecorate
3516 CEFBS_None, // OpDecorateId
3517 CEFBS_None, // OpDecorateString
3518 CEFBS_None, // OpDemoteToHelperInvocation
3519 CEFBS_None, // OpDot
3520 CEFBS_None, // OpEmitStreamVertex
3521 CEFBS_None, // OpEmitVertex
3522 CEFBS_None, // OpEndPrimitive
3523 CEFBS_None, // OpEndStreamPrimitive
3524 CEFBS_None, // OpEnqueueKernel
3525 CEFBS_None, // OpEntryPoint
3526 CEFBS_None, // OpExecutionMode
3527 CEFBS_None, // OpExecutionModeId
3528 CEFBS_None, // OpExpectKHR
3529 CEFBS_None, // OpExtInst
3530 CEFBS_None, // OpExtInstImport
3531 CEFBS_None, // OpExtInstWithForwardRefsKHR
3532 CEFBS_None, // OpExtension
3533 CEFBS_None, // OpFAddS
3534 CEFBS_None, // OpFAddV
3535 CEFBS_None, // OpFConvert
3536 CEFBS_None, // OpFDivS
3537 CEFBS_None, // OpFDivV
3538 CEFBS_None, // OpFMod
3539 CEFBS_None, // OpFMulS
3540 CEFBS_None, // OpFMulV
3541 CEFBS_None, // OpFNegate
3542 CEFBS_None, // OpFNegateV
3543 CEFBS_None, // OpFOrdEqual
3544 CEFBS_None, // OpFOrdGreaterThan
3545 CEFBS_None, // OpFOrdGreaterThanEqual
3546 CEFBS_None, // OpFOrdLessThan
3547 CEFBS_None, // OpFOrdLessThanEqual
3548 CEFBS_None, // OpFOrdNotEqual
3549 CEFBS_None, // OpFRemS
3550 CEFBS_None, // OpFRemV
3551 CEFBS_None, // OpFSubS
3552 CEFBS_None, // OpFSubV
3553 CEFBS_None, // OpFUnordEqual
3554 CEFBS_None, // OpFUnordGreaterThan
3555 CEFBS_None, // OpFUnordGreaterThanEqual
3556 CEFBS_None, // OpFUnordLessThan
3557 CEFBS_None, // OpFUnordLessThanEqual
3558 CEFBS_None, // OpFUnordNotEqual
3559 CEFBS_None, // OpFixedCosALTERA
3560 CEFBS_None, // OpFixedCosPiALTERA
3561 CEFBS_None, // OpFixedExpALTERA
3562 CEFBS_None, // OpFixedLogALTERA
3563 CEFBS_None, // OpFixedRecipALTERA
3564 CEFBS_None, // OpFixedRsqrtALTERA
3565 CEFBS_None, // OpFixedSinALTERA
3566 CEFBS_None, // OpFixedSinCosALTERA
3567 CEFBS_None, // OpFixedSinCosPiALTERA
3568 CEFBS_None, // OpFixedSinPiALTERA
3569 CEFBS_None, // OpFixedSqrtALTERA
3570 CEFBS_None, // OpFmaKHR
3571 CEFBS_None, // OpFreezeKHR
3572 CEFBS_None, // OpFunction
3573 CEFBS_None, // OpFunctionCall
3574 CEFBS_None, // OpFunctionEnd
3575 CEFBS_None, // OpFunctionParameter
3576 CEFBS_None, // OpFunctionPointerCallINTEL
3577 CEFBS_None, // OpFwidth
3578 CEFBS_None, // OpFwidthCoarse
3579 CEFBS_None, // OpFwidthFine
3580 CEFBS_None, // OpGenericCastToPtr
3581 CEFBS_None, // OpGenericCastToPtrExplicit
3582 CEFBS_None, // OpGenericPtrMemSemantics
3583 CEFBS_None, // OpGetDefaultQueue
3584 CEFBS_None, // OpGetKernelNDrangeMaxSubGroupSize
3585 CEFBS_None, // OpGetKernelNDrangeSubGroupCount
3586 CEFBS_None, // OpGetKernelPreferredWorkGroupSizeMultiple
3587 CEFBS_None, // OpGetKernelWorkGroupSize
3588 CEFBS_None, // OpGetMaxPipePackets
3589 CEFBS_None, // OpGetNumPipePackets
3590 CEFBS_None, // OpGroupAll
3591 CEFBS_None, // OpGroupAny
3592 CEFBS_None, // OpGroupAsyncCopy
3593 CEFBS_None, // OpGroupBitwiseAndKHR
3594 CEFBS_None, // OpGroupBitwiseOrKHR
3595 CEFBS_None, // OpGroupBitwiseXorKHR
3596 CEFBS_None, // OpGroupBroadcast
3597 CEFBS_None, // OpGroupCommitReadPipe
3598 CEFBS_None, // OpGroupCommitWritePipe
3599 CEFBS_None, // OpGroupFAdd
3600 CEFBS_None, // OpGroupFMax
3601 CEFBS_None, // OpGroupFMin
3602 CEFBS_None, // OpGroupFMulKHR
3603 CEFBS_None, // OpGroupIAdd
3604 CEFBS_None, // OpGroupIMulKHR
3605 CEFBS_None, // OpGroupLogicalAndKHR
3606 CEFBS_None, // OpGroupLogicalOrKHR
3607 CEFBS_None, // OpGroupLogicalXorKHR
3608 CEFBS_None, // OpGroupNonUniformAll
3609 CEFBS_None, // OpGroupNonUniformAllEqual
3610 CEFBS_None, // OpGroupNonUniformAny
3611 CEFBS_None, // OpGroupNonUniformBallot
3612 CEFBS_None, // OpGroupNonUniformBallotBitCount
3613 CEFBS_None, // OpGroupNonUniformBallotBitExtract
3614 CEFBS_None, // OpGroupNonUniformBallotFindLSB
3615 CEFBS_None, // OpGroupNonUniformBallotFindMSB
3616 CEFBS_None, // OpGroupNonUniformBitwiseAnd
3617 CEFBS_None, // OpGroupNonUniformBitwiseOr
3618 CEFBS_None, // OpGroupNonUniformBitwiseXor
3619 CEFBS_None, // OpGroupNonUniformBroadcast
3620 CEFBS_None, // OpGroupNonUniformBroadcastFirst
3621 CEFBS_None, // OpGroupNonUniformElect
3622 CEFBS_None, // OpGroupNonUniformFAdd
3623 CEFBS_None, // OpGroupNonUniformFMax
3624 CEFBS_None, // OpGroupNonUniformFMin
3625 CEFBS_None, // OpGroupNonUniformFMul
3626 CEFBS_None, // OpGroupNonUniformIAdd
3627 CEFBS_None, // OpGroupNonUniformIMul
3628 CEFBS_None, // OpGroupNonUniformInverseBallot
3629 CEFBS_None, // OpGroupNonUniformLogicalAnd
3630 CEFBS_None, // OpGroupNonUniformLogicalOr
3631 CEFBS_None, // OpGroupNonUniformLogicalXor
3632 CEFBS_None, // OpGroupNonUniformQuadSwap
3633 CEFBS_None, // OpGroupNonUniformRotateKHR
3634 CEFBS_None, // OpGroupNonUniformSMax
3635 CEFBS_None, // OpGroupNonUniformSMin
3636 CEFBS_None, // OpGroupNonUniformShuffle
3637 CEFBS_None, // OpGroupNonUniformShuffleDown
3638 CEFBS_None, // OpGroupNonUniformShuffleUp
3639 CEFBS_None, // OpGroupNonUniformShuffleXor
3640 CEFBS_None, // OpGroupNonUniformUMax
3641 CEFBS_None, // OpGroupNonUniformUMin
3642 CEFBS_None, // OpGroupReserveReadPipePackets
3643 CEFBS_None, // OpGroupReserveWritePipePackets
3644 CEFBS_None, // OpGroupSMax
3645 CEFBS_None, // OpGroupSMin
3646 CEFBS_None, // OpGroupUMax
3647 CEFBS_None, // OpGroupUMin
3648 CEFBS_None, // OpGroupWaitEvents
3649 CEFBS_None, // OpIAddCarryS
3650 CEFBS_None, // OpIAddCarryV
3651 CEFBS_None, // OpIAddS
3652 CEFBS_None, // OpIAddV
3653 CEFBS_None, // OpIEqual
3654 CEFBS_None, // OpIMulS
3655 CEFBS_None, // OpIMulV
3656 CEFBS_None, // OpINotEqual
3657 CEFBS_None, // OpISubBorrowS
3658 CEFBS_None, // OpISubBorrowV
3659 CEFBS_None, // OpISubS
3660 CEFBS_None, // OpISubV
3661 CEFBS_None, // OpImage
3662 CEFBS_None, // OpImageDrefGather
3663 CEFBS_None, // OpImageFetch
3664 CEFBS_None, // OpImageGather
3665 CEFBS_None, // OpImageQueryFormat
3666 CEFBS_None, // OpImageQueryLevels
3667 CEFBS_None, // OpImageQueryLod
3668 CEFBS_None, // OpImageQueryOrder
3669 CEFBS_None, // OpImageQuerySamples
3670 CEFBS_None, // OpImageQuerySize
3671 CEFBS_None, // OpImageQuerySizeLod
3672 CEFBS_None, // OpImageRead
3673 CEFBS_None, // OpImageSampleDrefExplicitLod
3674 CEFBS_None, // OpImageSampleDrefImplicitLod
3675 CEFBS_None, // OpImageSampleExplicitLod
3676 CEFBS_None, // OpImageSampleFootprintNV
3677 CEFBS_None, // OpImageSampleImplicitLod
3678 CEFBS_None, // OpImageSampleProjDrefExplicitLod
3679 CEFBS_None, // OpImageSampleProjDrefImplicitLod
3680 CEFBS_None, // OpImageSampleProjExplicitLod
3681 CEFBS_None, // OpImageSampleProjImplicitLod
3682 CEFBS_None, // OpImageSparseDrefGather
3683 CEFBS_None, // OpImageSparseFetch
3684 CEFBS_None, // OpImageSparseGather
3685 CEFBS_None, // OpImageSparseRead
3686 CEFBS_None, // OpImageSparseSampleDrefExplicitLod
3687 CEFBS_None, // OpImageSparseSampleDrefImplicitLod
3688 CEFBS_None, // OpImageSparseSampleExplicitLod
3689 CEFBS_None, // OpImageSparseSampleImplicitLod
3690 CEFBS_None, // OpImageSparseSampleProjDrefExplicitLod
3691 CEFBS_None, // OpImageSparseSampleProjDrefImplicitLod
3692 CEFBS_None, // OpImageSparseSampleProjExplicitLod
3693 CEFBS_None, // OpImageSparseSampleProjImplicitLod
3694 CEFBS_None, // OpImageSparseTexelsResident
3695 CEFBS_None, // OpImageTexelPointer
3696 CEFBS_None, // OpImageWrite
3697 CEFBS_None, // OpInBoundsAccessChain
3698 CEFBS_None, // OpInBoundsPtrAccessChain
3699 CEFBS_None, // OpIsFinite
3700 CEFBS_None, // OpIsInf
3701 CEFBS_None, // OpIsNan
3702 CEFBS_None, // OpIsNormal
3703 CEFBS_None, // OpIsValidEvent
3704 CEFBS_None, // OpIsValidReserveId
3705 CEFBS_None, // OpKill
3706 CEFBS_None, // OpLabel
3707 CEFBS_None, // OpLessOrGreater
3708 CEFBS_None, // OpLifetimeStart
3709 CEFBS_None, // OpLifetimeStop
3710 CEFBS_None, // OpLine
3711 CEFBS_None, // OpLoad
3712 CEFBS_None, // OpLogicalAnd
3713 CEFBS_None, // OpLogicalEqual
3714 CEFBS_None, // OpLogicalNot
3715 CEFBS_None, // OpLogicalNotEqual
3716 CEFBS_None, // OpLogicalOr
3717 CEFBS_None, // OpLoopControlINTEL
3718 CEFBS_None, // OpLoopMerge
3719 CEFBS_None, // OpMaskedGatherINTEL
3720 CEFBS_None, // OpMaskedScatterINTEL
3721 CEFBS_None, // OpMatrixTimesMatrix
3722 CEFBS_None, // OpMatrixTimesScalar
3723 CEFBS_None, // OpMatrixTimesVector
3724 CEFBS_None, // OpMemberDecorate
3725 CEFBS_None, // OpMemberDecorateString
3726 CEFBS_None, // OpMemberName
3727 CEFBS_None, // OpMemoryBarrier
3728 CEFBS_None, // OpMemoryModel
3729 CEFBS_None, // OpMemoryNamedBarrier
3730 CEFBS_None, // OpModuleProcessed
3731 CEFBS_None, // OpName
3732 CEFBS_None, // OpNamedBarrierInitialize
3733 CEFBS_None, // OpNoLine
3734 CEFBS_None, // OpNop
3735 CEFBS_None, // OpNot
3736 CEFBS_None, // OpOrdered
3737 CEFBS_None, // OpOuterProduct
3738 CEFBS_None, // OpPhi
3739 CEFBS_None, // OpPoisonKHR
3740 CEFBS_None, // OpPredicatedLoadINTEL
3741 CEFBS_None, // OpPredicatedStoreINTEL
3742 CEFBS_None, // OpPtrAccessChain
3743 CEFBS_None, // OpPtrCastToCrossWorkgroupINTEL
3744 CEFBS_None, // OpPtrCastToGeneric
3745 CEFBS_None, // OpPtrDiff
3746 CEFBS_None, // OpPtrEqual
3747 CEFBS_None, // OpPtrNotEqual
3748 CEFBS_None, // OpQuantizeToF16
3749 CEFBS_None, // OpReadClockKHR
3750 CEFBS_None, // OpReadPipe
3751 CEFBS_None, // OpReadPipeBlockingALTERA
3752 CEFBS_None, // OpReleaseEvent
3753 CEFBS_None, // OpReserveReadPipePackets
3754 CEFBS_None, // OpReserveWritePipePackets
3755 CEFBS_None, // OpReservedReadPipe
3756 CEFBS_None, // OpReservedWritePipe
3757 CEFBS_None, // OpRestoreMemoryINTEL
3758 CEFBS_None, // OpRetainEvent
3759 CEFBS_None, // OpReturn
3760 CEFBS_None, // OpReturnValue
3761 CEFBS_None, // OpRoundFToTF32INTEL
3762 CEFBS_None, // OpSConvert
3763 CEFBS_None, // OpSDivS
3764 CEFBS_None, // OpSDivV
3765 CEFBS_None, // OpSDot
3766 CEFBS_None, // OpSDotAccSat
3767 CEFBS_None, // OpSGreaterThan
3768 CEFBS_None, // OpSGreaterThanEqual
3769 CEFBS_None, // OpSLessThan
3770 CEFBS_None, // OpSLessThanEqual
3771 CEFBS_None, // OpSMod
3772 CEFBS_None, // OpSMulExtended
3773 CEFBS_None, // OpSNegate
3774 CEFBS_None, // OpSRemS
3775 CEFBS_None, // OpSRemV
3776 CEFBS_None, // OpSUDot
3777 CEFBS_None, // OpSUDotAccSat
3778 CEFBS_None, // OpSampledImage
3779 CEFBS_None, // OpSatConvertSToU
3780 CEFBS_None, // OpSatConvertUToS
3781 CEFBS_None, // OpSaveMemoryINTEL
3782 CEFBS_None, // OpSelectSFSCond
3783 CEFBS_None, // OpSelectSFVCond
3784 CEFBS_None, // OpSelectSISCond
3785 CEFBS_None, // OpSelectSIVCond
3786 CEFBS_None, // OpSelectSPSCond
3787 CEFBS_None, // OpSelectSPVCond
3788 CEFBS_None, // OpSelectVFSCond
3789 CEFBS_None, // OpSelectVFVCond
3790 CEFBS_None, // OpSelectVISCond
3791 CEFBS_None, // OpSelectVIVCond
3792 CEFBS_None, // OpSelectVPSCond
3793 CEFBS_None, // OpSelectVPVCond
3794 CEFBS_None, // OpSelectionMerge
3795 CEFBS_None, // OpSetUserEventStatus
3796 CEFBS_None, // OpShiftLeftLogicalS
3797 CEFBS_None, // OpShiftLeftLogicalV
3798 CEFBS_None, // OpShiftRightArithmeticS
3799 CEFBS_None, // OpShiftRightArithmeticV
3800 CEFBS_None, // OpShiftRightLogicalS
3801 CEFBS_None, // OpShiftRightLogicalV
3802 CEFBS_None, // OpSignBitSet
3803 CEFBS_None, // OpSizeOf
3804 CEFBS_None, // OpSource
3805 CEFBS_None, // OpSourceContinued
3806 CEFBS_None, // OpSourceExtension
3807 CEFBS_None, // OpSpecConstant
3808 CEFBS_None, // OpSpecConstantComposite
3809 CEFBS_None, // OpSpecConstantCompositeContinuedINTEL
3810 CEFBS_None, // OpSpecConstantFalse
3811 CEFBS_None, // OpSpecConstantOp
3812 CEFBS_None, // OpSpecConstantTrue
3813 CEFBS_None, // OpStore
3814 CEFBS_None, // OpStrictFAddS
3815 CEFBS_None, // OpStrictFAddV
3816 CEFBS_None, // OpStrictFDivS
3817 CEFBS_None, // OpStrictFDivV
3818 CEFBS_None, // OpStrictFMulS
3819 CEFBS_None, // OpStrictFMulV
3820 CEFBS_None, // OpStrictFRemS
3821 CEFBS_None, // OpStrictFRemV
3822 CEFBS_None, // OpStrictFSubS
3823 CEFBS_None, // OpStrictFSubV
3824 CEFBS_None, // OpString
3825 CEFBS_None, // OpSubgroup2DBlockLoadINTEL
3826 CEFBS_None, // OpSubgroup2DBlockLoadTransformINTEL
3827 CEFBS_None, // OpSubgroup2DBlockLoadTransposeINTEL
3828 CEFBS_None, // OpSubgroup2DBlockPrefetchINTEL
3829 CEFBS_None, // OpSubgroup2DBlockStoreINTEL
3830 CEFBS_None, // OpSubgroupBlockReadINTEL
3831 CEFBS_None, // OpSubgroupBlockWriteINTEL
3832 CEFBS_None, // OpSubgroupImageBlockReadINTEL
3833 CEFBS_None, // OpSubgroupImageBlockWriteINTEL
3834 CEFBS_None, // OpSubgroupImageMediaBlockReadINTEL
3835 CEFBS_None, // OpSubgroupImageMediaBlockWriteINTEL
3836 CEFBS_None, // OpSubgroupMatrixMultiplyAccumulateINTEL
3837 CEFBS_None, // OpSubgroupShuffleDownINTEL
3838 CEFBS_None, // OpSubgroupShuffleINTEL
3839 CEFBS_None, // OpSubgroupShuffleUpINTEL
3840 CEFBS_None, // OpSubgroupShuffleXorINTEL
3841 CEFBS_None, // OpSwitch
3842 CEFBS_None, // OpTranspose
3843 CEFBS_None, // OpTypeAccelerationStructureNV
3844 CEFBS_None, // OpTypeArray
3845 CEFBS_None, // OpTypeBool
3846 CEFBS_None, // OpTypeCooperativeMatrixKHR
3847 CEFBS_None, // OpTypeCooperativeMatrixNV
3848 CEFBS_None, // OpTypeDeviceEvent
3849 CEFBS_None, // OpTypeEvent
3850 CEFBS_None, // OpTypeFloat
3851 CEFBS_None, // OpTypeForwardPointer
3852 CEFBS_None, // OpTypeFunction
3853 CEFBS_None, // OpTypeImage
3854 CEFBS_None, // OpTypeInt
3855 CEFBS_None, // OpTypeMatrix
3856 CEFBS_None, // OpTypeNamedBarrier
3857 CEFBS_None, // OpTypeOpaque
3858 CEFBS_None, // OpTypePipe
3859 CEFBS_None, // OpTypePipeStorage
3860 CEFBS_None, // OpTypePointer
3861 CEFBS_None, // OpTypeQueue
3862 CEFBS_None, // OpTypeReserveId
3863 CEFBS_None, // OpTypeRuntimeArray
3864 CEFBS_None, // OpTypeSampledImage
3865 CEFBS_None, // OpTypeSampler
3866 CEFBS_None, // OpTypeStruct
3867 CEFBS_None, // OpTypeStructContinuedINTEL
3868 CEFBS_None, // OpTypeUntypedPointerKHR
3869 CEFBS_None, // OpTypeVector
3870 CEFBS_None, // OpTypeVectorIdEXT
3871 CEFBS_None, // OpTypeVoid
3872 CEFBS_None, // OpUConvert
3873 CEFBS_None, // OpUDivS
3874 CEFBS_None, // OpUDivV
3875 CEFBS_None, // OpUDot
3876 CEFBS_None, // OpUDotAccSat
3877 CEFBS_None, // OpUGreaterThan
3878 CEFBS_None, // OpUGreaterThanEqual
3879 CEFBS_None, // OpULessThan
3880 CEFBS_None, // OpULessThanEqual
3881 CEFBS_None, // OpUModS
3882 CEFBS_None, // OpUModV
3883 CEFBS_None, // OpUMulExtended
3884 CEFBS_None, // OpUndef
3885 CEFBS_None, // OpUnordered
3886 CEFBS_None, // OpUnreachable
3887 CEFBS_None, // OpUntypedAccessChainKHR
3888 CEFBS_None, // OpUntypedGroupAsyncCopyKHR
3889 CEFBS_None, // OpUntypedInBoundsAccessChainKHR
3890 CEFBS_None, // OpUntypedInBoundsPtrAccessChainKHR
3891 CEFBS_None, // OpUntypedPrefetchKHR
3892 CEFBS_None, // OpUntypedPtrAccessChainKHR
3893 CEFBS_None, // OpUntypedVariableKHR
3894 CEFBS_None, // OpUntypedVariableLengthArrayINTEL
3895 CEFBS_None, // OpVariable
3896 CEFBS_None, // OpVariableLengthArrayINTEL
3897 CEFBS_None, // OpVectorExtractDynamic
3898 CEFBS_None, // OpVectorInsertDynamic
3899 CEFBS_None, // OpVectorShuffle
3900 CEFBS_None, // OpVectorTimesMatrix
3901 CEFBS_None, // OpVectorTimesScalar
3902 CEFBS_None, // OpWritePipe
3903 CEFBS_None, // OpWritePipeBlockingALTERA
3904 };
3905
3906 assert(Opcode < 869);
3907 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3908}
3909
3910
3911} // namespace llvm::SPIRV_MC
3912
3913#endif // GET_COMPUTE_FEATURES
3914
3915#ifdef GET_AVAILABLE_OPCODE_CHECKER
3916#undef GET_AVAILABLE_OPCODE_CHECKER
3917
3918namespace llvm::SPIRV_MC {
3919
3920bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3921 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3922 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3923 FeatureBitset MissingFeatures =
3924 (AvailableFeatures & RequiredFeatures) ^
3925 RequiredFeatures;
3926 return !MissingFeatures.any();
3927}
3928
3929} // namespace llvm::SPIRV_MC
3930
3931#endif // GET_AVAILABLE_OPCODE_CHECKER
3932
3933#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3934#undef ENABLE_INSTR_PREDICATE_VERIFIER
3935
3936#include <sstream>
3937
3938namespace llvm::SPIRV_MC {
3939
3940#ifndef NDEBUG
3941static const char *SubtargetFeatureNames[] = {
3942 nullptr
3943};
3944
3945#endif // NDEBUG
3946
3947void verifyInstructionPredicates(
3948 unsigned Opcode, const FeatureBitset &Features) {
3949#ifndef NDEBUG
3950 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3951 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3952 FeatureBitset MissingFeatures =
3953 (AvailableFeatures & RequiredFeatures) ^
3954 RequiredFeatures;
3955 if (MissingFeatures.any()) {
3956 std::ostringstream Msg;
3957 Msg << "Attempting to emit " << &SPIRVInstrNameData[SPIRVInstrNameIndices[Opcode]]
3958 << " instruction but the ";
3959 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3960 if (MissingFeatures.test(i))
3961 Msg << SubtargetFeatureNames[i] << " ";
3962 Msg << "predicate(s) are not met";
3963 report_fatal_error(Msg.str().c_str());
3964 }
3965#endif // NDEBUG
3966}
3967
3968} // namespace llvm::SPIRV_MC
3969
3970#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3971
3972