1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SPIRV {
13
14 enum {
15 PHI = 0, // Target.td:1200
16 INLINEASM = 1, // Target.td:1206
17 INLINEASM_BR = 2, // Target.td:1212
18 CFI_INSTRUCTION = 3, // Target.td:1221
19 EH_LABEL = 4, // Target.td:1230
20 GC_LABEL = 5, // Target.td:1239
21 ANNOTATION_LABEL = 6, // Target.td:1248
22 KILL = 7, // Target.td:1256
23 EXTRACT_SUBREG = 8, // Target.td:1263
24 INSERT_SUBREG = 9, // Target.td:1269
25 IMPLICIT_DEF = 10, // Target.td:1276
26 INIT_UNDEF = 11, // Target.td:1285
27 SUBREG_TO_REG = 12, // Target.td:1292
28 COPY_TO_REGCLASS = 13, // Target.td:1298
29 DBG_VALUE = 14, // Target.td:1305
30 DBG_VALUE_LIST = 15, // Target.td:1312
31 DBG_INSTR_REF = 16, // Target.td:1319
32 DBG_PHI = 17, // Target.td:1326
33 DBG_LABEL = 18, // Target.td:1333
34 REG_SEQUENCE = 19, // Target.td:1340
35 COPY = 20, // Target.td:1347
36 COPY_LANEMASK = 21, // Target.td:1355
37 BUNDLE = 22, // Target.td:1362
38 LIFETIME_START = 23, // Target.td:1368
39 LIFETIME_END = 24, // Target.td:1375
40 PSEUDO_PROBE = 25, // Target.td:1382
41 ARITH_FENCE = 26, // Target.td:1389
42 STACKMAP = 27, // Target.td:1398
43 FENTRY_CALL = 28, // Target.td:1533
44 PATCHPOINT = 29, // Target.td:1406
45 LOAD_STACK_GUARD = 30, // Target.td:1424
46 PREALLOCATED_SETUP = 31, // Target.td:1432
47 PREALLOCATED_ARG = 32, // Target.td:1438
48 STATEPOINT = 33, // Target.td:1415
49 LOCAL_ESCAPE = 34, // Target.td:1444
50 FAULTING_OP = 35, // Target.td:1453
51 PATCHABLE_OP = 36, // Target.td:1473
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1481
53 PATCHABLE_RET = 38, // Target.td:1488
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1497
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1505
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1513
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1523
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1543
59 FAKE_USE = 44, // Target.td:1463
60 MEMBARRIER = 45, // Target.td:1549
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1557
62 RELOC_NONE = 47, // Target.td:1565
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1576
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1572
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1580
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1584
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1472
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484
96 G_INSERT = 81, // GenericOpcodes.td:1492
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1502
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448
145 G_FENCE = 130, // GenericOpcodes.td:1450
146 G_PREFETCH = 131, // GenericOpcodes.td:1457
147 G_BRCOND = 132, // GenericOpcodes.td:1592
148 G_BRINDIRECT = 133, // GenericOpcodes.td:1601
149 G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624
150 G_INTRINSIC = 135, // GenericOpcodes.td:1544
151 G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551
152 G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560
153 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568
154 G_ANYEXT = 139, // GenericOpcodes.td:44
155 G_TRUNC = 140, // GenericOpcodes.td:83
156 G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90
157 G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97
158 G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104
159 G_CONSTANT = 144, // GenericOpcodes.td:165
160 G_FCONSTANT = 145, // GenericOpcodes.td:172
161 G_VASTART = 146, // GenericOpcodes.td:178
162 G_VAARG = 147, // GenericOpcodes.td:185
163 G_SEXT = 148, // GenericOpcodes.td:52
164 G_SEXT_INREG = 149, // GenericOpcodes.td:66
165 G_ZEXT = 150, // GenericOpcodes.td:74
166 G_SHL = 151, // GenericOpcodes.td:396
167 G_LSHR = 152, // GenericOpcodes.td:403
168 G_ASHR = 153, // GenericOpcodes.td:410
169 G_FSHL = 154, // GenericOpcodes.td:462
170 G_FSHR = 155, // GenericOpcodes.td:470
171 G_ROTR = 156, // GenericOpcodes.td:477
172 G_ROTL = 157, // GenericOpcodes.td:484
173 G_ICMP = 158, // GenericOpcodes.td:491
174 G_FCMP = 159, // GenericOpcodes.td:498
175 G_SCMP = 160, // GenericOpcodes.td:505
176 G_UCMP = 161, // GenericOpcodes.td:512
177 G_SELECT = 162, // GenericOpcodes.td:519
178 G_UADDO = 163, // GenericOpcodes.td:584
179 G_UADDE = 164, // GenericOpcodes.td:592
180 G_USUBO = 165, // GenericOpcodes.td:614
181 G_USUBE = 166, // GenericOpcodes.td:620
182 G_SADDO = 167, // GenericOpcodes.td:599
183 G_SADDE = 168, // GenericOpcodes.td:607
184 G_SSUBO = 169, // GenericOpcodes.td:627
185 G_SSUBE = 170, // GenericOpcodes.td:634
186 G_UMULO = 171, // GenericOpcodes.td:641
187 G_SMULO = 172, // GenericOpcodes.td:649
188 G_UMULH = 173, // GenericOpcodes.td:658
189 G_SMULH = 174, // GenericOpcodes.td:667
190 G_UADDSAT = 175, // GenericOpcodes.td:679
191 G_SADDSAT = 176, // GenericOpcodes.td:687
192 G_USUBSAT = 177, // GenericOpcodes.td:695
193 G_SSUBSAT = 178, // GenericOpcodes.td:703
194 G_USHLSAT = 179, // GenericOpcodes.td:711
195 G_SSHLSAT = 180, // GenericOpcodes.td:719
196 G_SMULFIX = 181, // GenericOpcodes.td:731
197 G_UMULFIX = 182, // GenericOpcodes.td:738
198 G_SMULFIXSAT = 183, // GenericOpcodes.td:748
199 G_UMULFIXSAT = 184, // GenericOpcodes.td:755
200 G_SDIVFIX = 185, // GenericOpcodes.td:766
201 G_UDIVFIX = 186, // GenericOpcodes.td:773
202 G_SDIVFIXSAT = 187, // GenericOpcodes.td:783
203 G_UDIVFIXSAT = 188, // GenericOpcodes.td:790
204 G_FADD = 189, // GenericOpcodes.td:963
205 G_FSUB = 190, // GenericOpcodes.td:971
206 G_FMUL = 191, // GenericOpcodes.td:979
207 G_FMA = 192, // GenericOpcodes.td:988
208 G_FMAD = 193, // GenericOpcodes.td:997
209 G_FDIV = 194, // GenericOpcodes.td:1005
210 G_FREM = 195, // GenericOpcodes.td:1012
211 G_FMODF = 196, // GenericOpcodes.td:1019
212 G_FPOW = 197, // GenericOpcodes.td:1026
213 G_FPOWI = 198, // GenericOpcodes.td:1033
214 G_FEXP = 199, // GenericOpcodes.td:1040
215 G_FEXP2 = 200, // GenericOpcodes.td:1047
216 G_FEXP10 = 201, // GenericOpcodes.td:1054
217 G_FLOG = 202, // GenericOpcodes.td:1061
218 G_FLOG2 = 203, // GenericOpcodes.td:1068
219 G_FLOG10 = 204, // GenericOpcodes.td:1075
220 G_FLDEXP = 205, // GenericOpcodes.td:1082
221 G_FFREXP = 206, // GenericOpcodes.td:1089
222 G_FNEG = 207, // GenericOpcodes.td:801
223 G_FPEXT = 208, // GenericOpcodes.td:807
224 G_FPTRUNC = 209, // GenericOpcodes.td:813
225 G_FPTOSI = 210, // GenericOpcodes.td:819
226 G_FPTOUI = 211, // GenericOpcodes.td:825
227 G_SITOFP = 212, // GenericOpcodes.td:831
228 G_UITOFP = 213, // GenericOpcodes.td:837
229 G_FPTOSI_SAT = 214, // GenericOpcodes.td:843
230 G_FPTOUI_SAT = 215, // GenericOpcodes.td:849
231 G_FABS = 216, // GenericOpcodes.td:855
232 G_FCOPYSIGN = 217, // GenericOpcodes.td:861
233 G_IS_FPCLASS = 218, // GenericOpcodes.td:874
234 G_FCANONICALIZE = 219, // GenericOpcodes.td:867
235 G_FMINNUM = 220, // GenericOpcodes.td:887
236 G_FMAXNUM = 221, // GenericOpcodes.td:894
237 G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912
238 G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919
239 G_FMINIMUM = 224, // GenericOpcodes.td:929
240 G_FMAXIMUM = 225, // GenericOpcodes.td:936
241 G_FMINIMUMNUM = 226, // GenericOpcodes.td:944
242 G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951
243 G_GET_FPENV = 228, // GenericOpcodes.td:1219
244 G_SET_FPENV = 229, // GenericOpcodes.td:1226
245 G_RESET_FPENV = 230, // GenericOpcodes.td:1233
246 G_GET_FPMODE = 231, // GenericOpcodes.td:1240
247 G_SET_FPMODE = 232, // GenericOpcodes.td:1247
248 G_RESET_FPMODE = 233, // GenericOpcodes.td:1254
249 G_GET_ROUNDING = 234, // GenericOpcodes.td:1311
250 G_SET_ROUNDING = 235, // GenericOpcodes.td:1317
251 G_PTR_ADD = 236, // GenericOpcodes.td:526
252 G_PTRMASK = 237, // GenericOpcodes.td:534
253 G_SMIN = 238, // GenericOpcodes.td:541
254 G_SMAX = 239, // GenericOpcodes.td:549
255 G_UMIN = 240, // GenericOpcodes.td:557
256 G_UMAX = 241, // GenericOpcodes.td:565
257 G_ABS = 242, // GenericOpcodes.td:573
258 G_LROUND = 243, // GenericOpcodes.td:283
259 G_LLROUND = 244, // GenericOpcodes.td:289
260 G_BR = 245, // GenericOpcodes.td:1582
261 G_BRJT = 246, // GenericOpcodes.td:1612
262 G_VSCALE = 247, // GenericOpcodes.td:1512
263 G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656
264 G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663
265 G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670
266 G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677
267 G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687
268 G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694
269 G_STEP_VECTOR = 254, // GenericOpcodes.td:1701
270 G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708
271 G_CTTZ = 256, // GenericOpcodes.td:205
272 G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211
273 G_CTLZ = 258, // GenericOpcodes.td:193
274 G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199
275 G_CTLS = 260, // GenericOpcodes.td:217
276 G_CTPOP = 261, // GenericOpcodes.td:223
277 G_BSWAP = 262, // GenericOpcodes.td:229
278 G_BITREVERSE = 263, // GenericOpcodes.td:235
279 G_FCEIL = 264, // GenericOpcodes.td:1096
280 G_FCOS = 265, // GenericOpcodes.td:1103
281 G_FSIN = 266, // GenericOpcodes.td:1110
282 G_FSINCOS = 267, // GenericOpcodes.td:1117
283 G_FTAN = 268, // GenericOpcodes.td:1124
284 G_FACOS = 269, // GenericOpcodes.td:1131
285 G_FASIN = 270, // GenericOpcodes.td:1138
286 G_FATAN = 271, // GenericOpcodes.td:1145
287 G_FATAN2 = 272, // GenericOpcodes.td:1152
288 G_FCOSH = 273, // GenericOpcodes.td:1159
289 G_FSINH = 274, // GenericOpcodes.td:1166
290 G_FTANH = 275, // GenericOpcodes.td:1173
291 G_FSQRT = 276, // GenericOpcodes.td:1183
292 G_FFLOOR = 277, // GenericOpcodes.td:1190
293 G_FRINT = 278, // GenericOpcodes.td:1197
294 G_FNEARBYINT = 279, // GenericOpcodes.td:1204
295 G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241
296 G_BLOCK_ADDR = 281, // GenericOpcodes.td:247
297 G_JUMP_TABLE = 282, // GenericOpcodes.td:253
298 G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259
299 G_STACKSAVE = 284, // GenericOpcodes.td:265
300 G_STACKRESTORE = 285, // GenericOpcodes.td:271
301 G_STRICT_FADD = 286, // GenericOpcodes.td:1758
302 G_STRICT_FSUB = 287, // GenericOpcodes.td:1759
303 G_STRICT_FMUL = 288, // GenericOpcodes.td:1760
304 G_STRICT_FDIV = 289, // GenericOpcodes.td:1761
305 G_STRICT_FREM = 290, // GenericOpcodes.td:1762
306 G_STRICT_FMA = 291, // GenericOpcodes.td:1763
307 G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764
308 G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765
309 G_READ_REGISTER = 294, // GenericOpcodes.td:1631
310 G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641
311 G_MEMCPY = 296, // GenericOpcodes.td:1771
312 G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779
313 G_MEMMOVE = 298, // GenericOpcodes.td:1787
314 G_MEMSET = 299, // GenericOpcodes.td:1795
315 G_BZERO = 300, // GenericOpcodes.td:1802
316 G_TRAP = 301, // GenericOpcodes.td:1812
317 G_DEBUGTRAP = 302, // GenericOpcodes.td:1819
318 G_UBSANTRAP = 303, // GenericOpcodes.td:1825
319 G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724
320 G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730
321 G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736
322 G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737
323 G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739
324 G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740
325 G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744
328 G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745
329 G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752
336 G_SBFX = 321, // GenericOpcodes.td:1837
337 G_UBFX = 322, // GenericOpcodes.td:1845
338 ASSIGN_TYPE = 323, // SPIRVInstrInfo.td:18
339 UNKNOWN_type = 324, // SPIRVInstrInfo.td:21
340 OpAccessChain = 325, // SPIRVInstrInfo.td:266
341 OpAliasDomainDeclINTEL = 326, // SPIRVInstrInfo.td:968
342 OpAliasScopeDeclINTEL = 327, // SPIRVInstrInfo.td:970
343 OpAliasScopeListDeclINTEL = 328, // SPIRVInstrInfo.td:972
344 OpAll = 329, // SPIRVInstrInfo.td:560
345 OpAny = 330, // SPIRVInstrInfo.td:558
346 OpArbitraryFloatACosALTERA = 331, // SPIRVInstrInfo.td:1059
347 OpArbitraryFloatACosPiALTERA = 332, // SPIRVInstrInfo.td:1061
348 OpArbitraryFloatASinALTERA = 333, // SPIRVInstrInfo.td:1055
349 OpArbitraryFloatASinPiALTERA = 334, // SPIRVInstrInfo.td:1057
350 OpArbitraryFloatATan2ALTERA = 335, // SPIRVInstrInfo.td:1067
351 OpArbitraryFloatATanALTERA = 336, // SPIRVInstrInfo.td:1063
352 OpArbitraryFloatATanPiALTERA = 337, // SPIRVInstrInfo.td:1065
353 OpArbitraryFloatAddALTERA = 338, // SPIRVInstrInfo.td:1044
354 OpArbitraryFloatCastALTERA = 339, // SPIRVInstrInfo.td:1075
355 OpArbitraryFloatCastFromIntALTERA = 340, // SPIRVInstrInfo.td:1077
356 OpArbitraryFloatCastToIntALTERA = 341, // SPIRVInstrInfo.td:1079
357 OpArbitraryFloatCbrtALTERA = 342, // SPIRVInstrInfo.td:993
358 OpArbitraryFloatCosALTERA = 343, // SPIRVInstrInfo.td:1029
359 OpArbitraryFloatCosPiALTERA = 344, // SPIRVInstrInfo.td:1038
360 OpArbitraryFloatDivALTERA = 345, // SPIRVInstrInfo.td:1051
361 OpArbitraryFloatEQALTERA = 346, // SPIRVInstrInfo.td:988
362 OpArbitraryFloatExp10ALTERA = 347, // SPIRVInstrInfo.td:1020
363 OpArbitraryFloatExp2ALTERA = 348, // SPIRVInstrInfo.td:1017
364 OpArbitraryFloatExpALTERA = 349, // SPIRVInstrInfo.td:1014
365 OpArbitraryFloatExpm1ALTERA = 350, // SPIRVInstrInfo.td:1023
366 OpArbitraryFloatGEALTERA = 351, // SPIRVInstrInfo.td:982
367 OpArbitraryFloatGTALTERA = 352, // SPIRVInstrInfo.td:980
368 OpArbitraryFloatHypotALTERA = 353, // SPIRVInstrInfo.td:996
369 OpArbitraryFloatLEALTERA = 354, // SPIRVInstrInfo.td:986
370 OpArbitraryFloatLTALTERA = 355, // SPIRVInstrInfo.td:984
371 OpArbitraryFloatLog10ALTERA = 356, // SPIRVInstrInfo.td:1008
372 OpArbitraryFloatLog1pALTERA = 357, // SPIRVInstrInfo.td:1011
373 OpArbitraryFloatLog2ALTERA = 358, // SPIRVInstrInfo.td:1005
374 OpArbitraryFloatLogALTERA = 359, // SPIRVInstrInfo.td:1002
375 OpArbitraryFloatMulALTERA = 360, // SPIRVInstrInfo.td:1049
376 OpArbitraryFloatPowALTERA = 361, // SPIRVInstrInfo.td:1069
377 OpArbitraryFloatPowNALTERA = 362, // SPIRVInstrInfo.td:1073
378 OpArbitraryFloatPowRALTERA = 363, // SPIRVInstrInfo.td:1071
379 OpArbitraryFloatRSqrtALTERA = 364, // SPIRVInstrInfo.td:1053
380 OpArbitraryFloatRecipALTERA = 365, // SPIRVInstrInfo.td:990
381 OpArbitraryFloatSinALTERA = 366, // SPIRVInstrInfo.td:1026
382 OpArbitraryFloatSinCosALTERA = 367, // SPIRVInstrInfo.td:1032
383 OpArbitraryFloatSinCosPiALTERA = 368, // SPIRVInstrInfo.td:1041
384 OpArbitraryFloatSinPiALTERA = 369, // SPIRVInstrInfo.td:1035
385 OpArbitraryFloatSqrtALTERA = 370, // SPIRVInstrInfo.td:999
386 OpArbitraryFloatSubALTERA = 371, // SPIRVInstrInfo.td:1047
387 OpArithmeticFenceEXT = 372, // SPIRVInstrInfo.td:956
388 OpArrayLength = 373, // SPIRVInstrInfo.td:274
389 OpAsmCallINTEL = 374, // SPIRVInstrInfo.td:922
390 OpAsmINTEL = 375, // SPIRVInstrInfo.td:919
391 OpAsmTargetINTEL = 376, // SPIRVInstrInfo.td:918
392 OpAssumeTrueKHR = 377, // SPIRVInstrInfo.td:102
393 OpAtomicAnd = 378, // SPIRVInstrInfo.td:686
394 OpAtomicCompareExchange = 379, // SPIRVInstrInfo.td:666
395 OpAtomicCompareExchangeWeak = 380, // SPIRVInstrInfo.td:670
396 OpAtomicExchange = 381, // SPIRVInstrInfo.td:663
397 OpAtomicFAddEXT = 382, // SPIRVInstrInfo.td:690
398 OpAtomicFMaxEXT = 383, // SPIRVInstrInfo.td:692
399 OpAtomicFMinEXT = 384, // SPIRVInstrInfo.td:691
400 OpAtomicFlagClear = 385, // SPIRVInstrInfo.td:695
401 OpAtomicFlagTestAndSet = 386, // SPIRVInstrInfo.td:694
402 OpAtomicIAdd = 387, // SPIRVInstrInfo.td:678
403 OpAtomicIDecrement = 388, // SPIRVInstrInfo.td:676
404 OpAtomicIIncrement = 389, // SPIRVInstrInfo.td:675
405 OpAtomicISub = 390, // SPIRVInstrInfo.td:679
406 OpAtomicLoad = 391, // SPIRVInstrInfo.td:659
407 OpAtomicOr = 392, // SPIRVInstrInfo.td:687
408 OpAtomicSMax = 393, // SPIRVInstrInfo.td:683
409 OpAtomicSMin = 394, // SPIRVInstrInfo.td:681
410 OpAtomicStore = 395, // SPIRVInstrInfo.td:661
411 OpAtomicUMax = 396, // SPIRVInstrInfo.td:684
412 OpAtomicUMin = 397, // SPIRVInstrInfo.td:682
413 OpAtomicXor = 398, // SPIRVInstrInfo.td:688
414 OpBitCount = 399, // SPIRVInstrInfo.td:554
415 OpBitFieldInsert = 400, // SPIRVInstrInfo.td:544
416 OpBitFieldSExtract = 401, // SPIRVInstrInfo.td:547
417 OpBitFieldUExtract = 402, // SPIRVInstrInfo.td:550
418 OpBitReverse = 403, // SPIRVInstrInfo.td:553
419 OpBitcast = 404, // SPIRVInstrInfo.td:438
420 OpBitwiseAndS = 405, // SPIRVInstrInfo.td:48
421 OpBitwiseAndV = 406, // SPIRVInstrInfo.td:53
422 OpBitwiseFunctionINTEL = 407, // SPIRVInstrInfo.td:976
423 OpBitwiseOrS = 408, // SPIRVInstrInfo.td:48
424 OpBitwiseOrV = 409, // SPIRVInstrInfo.td:53
425 OpBitwiseXorS = 410, // SPIRVInstrInfo.td:48
426 OpBitwiseXorV = 411, // SPIRVInstrInfo.td:53
427 OpBranch = 412, // SPIRVInstrInfo.td:634
428 OpBranchConditional = 413, // SPIRVInstrInfo.td:635
429 OpBuildNDRange = 414, // SPIRVInstrInfo.td:768
430 OpCapability = 415, // SPIRVInstrInfo.td:160
431 OpCaptureEventProfilingInfo = 416, // SPIRVInstrInfo.td:763
432 OpCommitReadPipe = 417, // SPIRVInstrInfo.td:785
433 OpCommitWritePipe = 418, // SPIRVInstrInfo.td:787
434 OpCompositeConstruct = 419, // SPIRVInstrInfo.td:459
435 OpCompositeConstructContinuedINTEL = 420, // SPIRVInstrInfo.td:461
436 OpCompositeExtract = 421, // SPIRVInstrInfo.td:463
437 OpCompositeInsert = 422, // SPIRVInstrInfo.td:465
438 OpConstantComposite = 423, // SPIRVInstrInfo.td:230
439 OpConstantCompositeContinuedINTEL = 424, // SPIRVInstrInfo.td:232
440 OpConstantF = 425, // SPIRVInstrInfo.td:218
441 OpConstantFalse = 426, // SPIRVInstrInfo.td:227
442 OpConstantFunctionPointerINTEL = 427, // SPIRVInstrInfo.td:866
443 OpConstantI = 428, // SPIRVInstrInfo.td:216
444 OpConstantNull = 429, // SPIRVInstrInfo.td:238
445 OpConstantSampler = 430, // SPIRVInstrInfo.td:235
446 OpConstantTrue = 431, // SPIRVInstrInfo.td:225
447 OpControlBarrier = 432, // SPIRVInstrInfo.td:707
448 OpControlBarrierArriveINTEL = 433, // SPIRVInstrInfo.td:716
449 OpControlBarrierWaitINTEL = 434, // SPIRVInstrInfo.td:718
450 OpConvertBF16ToFINTEL = 435, // SPIRVInstrInfo.td:446
451 OpConvertFToBF16INTEL = 436, // SPIRVInstrInfo.td:445
452 OpConvertFToS = 437, // SPIRVInstrInfo.td:418
453 OpConvertFToU = 438, // SPIRVInstrInfo.td:417
454 OpConvertHandleToImageINTEL = 439, // SPIRVInstrInfo.td:960
455 OpConvertHandleToSampledImageINTEL = 440, // SPIRVInstrInfo.td:964
456 OpConvertHandleToSamplerINTEL = 441, // SPIRVInstrInfo.td:962
457 OpConvertPtrToU = 442, // SPIRVInstrInfo.td:428
458 OpConvertSToF = 443, // SPIRVInstrInfo.td:419
459 OpConvertUToF = 444, // SPIRVInstrInfo.td:420
460 OpConvertUToPtr = 445, // SPIRVInstrInfo.td:433
461 OpCooperativeMatrixConstructCheckedINTEL = 446, // SPIRVInstrInfo.td:945
462 OpCooperativeMatrixGetElementCoordINTEL = 447, // SPIRVInstrInfo.td:948
463 OpCooperativeMatrixLengthKHR = 448, // SPIRVInstrInfo.td:935
464 OpCooperativeMatrixLoadCheckedINTEL = 449, // SPIRVInstrInfo.td:939
465 OpCooperativeMatrixLoadKHR = 450, // SPIRVInstrInfo.td:926
466 OpCooperativeMatrixMulAddKHR = 451, // SPIRVInstrInfo.td:932
467 OpCooperativeMatrixPrefetchINTEL = 452, // SPIRVInstrInfo.td:951
468 OpCooperativeMatrixStoreCheckedINTEL = 453, // SPIRVInstrInfo.td:942
469 OpCooperativeMatrixStoreKHR = 454, // SPIRVInstrInfo.td:929
470 OpCopyLogical = 455, // SPIRVInstrInfo.td:469
471 OpCopyMemory = 456, // SPIRVInstrInfo.td:262
472 OpCopyMemorySized = 457, // SPIRVInstrInfo.td:264
473 OpCopyObject = 458, // SPIRVInstrInfo.td:467
474 OpCreateUserEvent = 459, // SPIRVInstrInfo.td:757
475 OpCrossWorkgroupCastToPtrINTEL = 460, // SPIRVInstrInfo.td:442
476 OpDPdx = 461, // SPIRVInstrInfo.td:610
477 OpDPdxCoarse = 462, // SPIRVInstrInfo.td:618
478 OpDPdxFine = 463, // SPIRVInstrInfo.td:614
479 OpDPdy = 464, // SPIRVInstrInfo.td:611
480 OpDPdyCoarse = 465, // SPIRVInstrInfo.td:619
481 OpDPdyFine = 466, // SPIRVInstrInfo.td:615
482 OpDecorate = 467, // SPIRVInstrInfo.td:124
483 OpDecorateId = 468, // SPIRVInstrInfo.td:132
484 OpDecorateString = 469, // SPIRVInstrInfo.td:134
485 OpDemoteToHelperInvocation = 470, // SPIRVInstrInfo.td:647
486 OpDot = 471, // SPIRVInstrInfo.td:510
487 OpEmitStreamVertex = 472, // SPIRVInstrInfo.td:702
488 OpEmitVertex = 473, // SPIRVInstrInfo.td:700
489 OpEndPrimitive = 474, // SPIRVInstrInfo.td:701
490 OpEndStreamPrimitive = 475, // SPIRVInstrInfo.td:703
491 OpEnqueueKernel = 476, // SPIRVInstrInfo.td:752
492 OpEntryPoint = 477, // SPIRVInstrInfo.td:155
493 OpExecutionMode = 478, // SPIRVInstrInfo.td:158
494 OpExecutionModeId = 479, // SPIRVInstrInfo.td:161
495 OpExpectKHR = 480, // SPIRVInstrInfo.td:103
496 OpExtInst = 481, // SPIRVInstrInfo.td:149
497 OpExtInstImport = 482, // SPIRVInstrInfo.td:143
498 OpExtension = 483, // SPIRVInstrInfo.td:142
499 OpFAddS = 484, // SPIRVInstrInfo.td:46
500 OpFAddV = 485, // SPIRVInstrInfo.td:51
501 OpFConvert = 486, // SPIRVInstrInfo.td:424
502 OpFDivS = 487, // SPIRVInstrInfo.td:46
503 OpFDivV = 488, // SPIRVInstrInfo.td:51
504 OpFMod = 489, // SPIRVInstrInfo.td:501
505 OpFMulS = 490, // SPIRVInstrInfo.td:46
506 OpFMulV = 491, // SPIRVInstrInfo.td:51
507 OpFNegate = 492, // SPIRVInstrInfo.td:474
508 OpFNegateV = 493, // SPIRVInstrInfo.td:475
509 OpFOrdEqual = 494, // SPIRVInstrInfo.td:593
510 OpFOrdGreaterThan = 495, // SPIRVInstrInfo.td:600
511 OpFOrdGreaterThanEqual = 496, // SPIRVInstrInfo.td:605
512 OpFOrdLessThan = 497, // SPIRVInstrInfo.td:598
513 OpFOrdLessThanEqual = 498, // SPIRVInstrInfo.td:603
514 OpFOrdNotEqual = 499, // SPIRVInstrInfo.td:595
515 OpFRemS = 500, // SPIRVInstrInfo.td:46
516 OpFRemV = 501, // SPIRVInstrInfo.td:51
517 OpFSubS = 502, // SPIRVInstrInfo.td:46
518 OpFSubV = 503, // SPIRVInstrInfo.td:51
519 OpFUnordEqual = 504, // SPIRVInstrInfo.td:594
520 OpFUnordGreaterThan = 505, // SPIRVInstrInfo.td:601
521 OpFUnordGreaterThanEqual = 506, // SPIRVInstrInfo.td:606
522 OpFUnordLessThan = 507, // SPIRVInstrInfo.td:599
523 OpFUnordLessThanEqual = 508, // SPIRVInstrInfo.td:604
524 OpFUnordNotEqual = 509, // SPIRVInstrInfo.td:596
525 OpFixedCosALTERA = 510, // SPIRVInstrInfo.td:1120
526 OpFixedCosPiALTERA = 511, // SPIRVInstrInfo.td:1126
527 OpFixedExpALTERA = 512, // SPIRVInstrInfo.td:1132
528 OpFixedLogALTERA = 513, // SPIRVInstrInfo.td:1130
529 OpFixedRecipALTERA = 514, // SPIRVInstrInfo.td:1114
530 OpFixedRsqrtALTERA = 515, // SPIRVInstrInfo.td:1116
531 OpFixedSinALTERA = 516, // SPIRVInstrInfo.td:1118
532 OpFixedSinCosALTERA = 517, // SPIRVInstrInfo.td:1122
533 OpFixedSinCosPiALTERA = 518, // SPIRVInstrInfo.td:1128
534 OpFixedSinPiALTERA = 519, // SPIRVInstrInfo.td:1124
535 OpFixedSqrtALTERA = 520, // SPIRVInstrInfo.td:1112
536 OpFmaKHR = 521, // SPIRVInstrInfo.td:530
537 OpFunction = 522, // SPIRVInstrInfo.td:299
538 OpFunctionCall = 523, // SPIRVInstrInfo.td:307
539 OpFunctionEnd = 524, // SPIRVInstrInfo.td:304
540 OpFunctionParameter = 525, // SPIRVInstrInfo.td:302
541 OpFunctionPointerCallINTEL = 526, // SPIRVInstrInfo.td:871
542 OpFwidth = 527, // SPIRVInstrInfo.td:612
543 OpFwidthCoarse = 528, // SPIRVInstrInfo.td:620
544 OpFwidthFine = 529, // SPIRVInstrInfo.td:616
545 OpGenericCastToPtr = 530, // SPIRVInstrInfo.td:435
546 OpGenericCastToPtrExplicit = 531, // SPIRVInstrInfo.td:436
547 OpGenericPtrMemSemantics = 532, // SPIRVInstrInfo.td:276
548 OpGetDefaultQueue = 533, // SPIRVInstrInfo.td:766
549 OpGetMaxPipePackets = 534, // SPIRVInstrInfo.td:793
550 OpGetNumPipePackets = 535, // SPIRVInstrInfo.td:791
551 OpGroupAll = 536, // SPIRVInstrInfo.td:728
552 OpGroupAny = 537, // SPIRVInstrInfo.td:730
553 OpGroupAsyncCopy = 538, // SPIRVInstrInfo.td:723
554 OpGroupBitwiseAndKHR = 539, // SPIRVInstrInfo.td:904
555 OpGroupBitwiseOrKHR = 540, // SPIRVInstrInfo.td:906
556 OpGroupBitwiseXorKHR = 541, // SPIRVInstrInfo.td:908
557 OpGroupBroadcast = 542, // SPIRVInstrInfo.td:732
558 OpGroupCommitReadPipe = 543, // SPIRVInstrInfo.td:799
559 OpGroupCommitWritePipe = 544, // SPIRVInstrInfo.td:801
560 OpGroupFAdd = 545, // SPIRVInstrInfo.td:739
561 OpGroupFMax = 546, // SPIRVInstrInfo.td:743
562 OpGroupFMin = 547, // SPIRVInstrInfo.td:740
563 OpGroupFMulKHR = 548, // SPIRVInstrInfo.td:902
564 OpGroupIAdd = 549, // SPIRVInstrInfo.td:738
565 OpGroupIMulKHR = 550, // SPIRVInstrInfo.td:900
566 OpGroupLogicalAndKHR = 551, // SPIRVInstrInfo.td:910
567 OpGroupLogicalOrKHR = 552, // SPIRVInstrInfo.td:912
568 OpGroupLogicalXorKHR = 553, // SPIRVInstrInfo.td:914
569 OpGroupNonUniformAll = 554, // SPIRVInstrInfo.td:814
570 OpGroupNonUniformAllEqual = 555, // SPIRVInstrInfo.td:816
571 OpGroupNonUniformAny = 556, // SPIRVInstrInfo.td:815
572 OpGroupNonUniformBallot = 557, // SPIRVInstrInfo.td:819
573 OpGroupNonUniformBallotBitCount = 558, // SPIRVInstrInfo.td:822
574 OpGroupNonUniformBallotBitExtract = 559, // SPIRVInstrInfo.td:821
575 OpGroupNonUniformBallotFindLSB = 560, // SPIRVInstrInfo.td:826
576 OpGroupNonUniformBallotFindMSB = 561, // SPIRVInstrInfo.td:827
577 OpGroupNonUniformBitwiseAnd = 562, // SPIRVInstrInfo.td:846
578 OpGroupNonUniformBitwiseOr = 563, // SPIRVInstrInfo.td:847
579 OpGroupNonUniformBitwiseXor = 564, // SPIRVInstrInfo.td:848
580 OpGroupNonUniformBroadcast = 565, // SPIRVInstrInfo.td:817
581 OpGroupNonUniformBroadcastFirst = 566, // SPIRVInstrInfo.td:818
582 OpGroupNonUniformElect = 567, // SPIRVInstrInfo.td:806
583 OpGroupNonUniformFAdd = 568, // SPIRVInstrInfo.td:837
584 OpGroupNonUniformFMax = 569, // SPIRVInstrInfo.td:845
585 OpGroupNonUniformFMin = 570, // SPIRVInstrInfo.td:842
586 OpGroupNonUniformFMul = 571, // SPIRVInstrInfo.td:839
587 OpGroupNonUniformIAdd = 572, // SPIRVInstrInfo.td:836
588 OpGroupNonUniformIMul = 573, // SPIRVInstrInfo.td:838
589 OpGroupNonUniformInverseBallot = 574, // SPIRVInstrInfo.td:820
590 OpGroupNonUniformLogicalAnd = 575, // SPIRVInstrInfo.td:849
591 OpGroupNonUniformLogicalOr = 576, // SPIRVInstrInfo.td:850
592 OpGroupNonUniformLogicalXor = 577, // SPIRVInstrInfo.td:851
593 OpGroupNonUniformRotateKHR = 578, // SPIRVInstrInfo.td:854
594 OpGroupNonUniformSMax = 579, // SPIRVInstrInfo.td:843
595 OpGroupNonUniformSMin = 580, // SPIRVInstrInfo.td:840
596 OpGroupNonUniformShuffle = 581, // SPIRVInstrInfo.td:828
597 OpGroupNonUniformShuffleDown = 582, // SPIRVInstrInfo.td:831
598 OpGroupNonUniformShuffleUp = 583, // SPIRVInstrInfo.td:830
599 OpGroupNonUniformShuffleXor = 584, // SPIRVInstrInfo.td:829
600 OpGroupNonUniformUMax = 585, // SPIRVInstrInfo.td:844
601 OpGroupNonUniformUMin = 586, // SPIRVInstrInfo.td:841
602 OpGroupReserveReadPipePackets = 587, // SPIRVInstrInfo.td:795
603 OpGroupReserveWritePipePackets = 588, // SPIRVInstrInfo.td:797
604 OpGroupSMax = 589, // SPIRVInstrInfo.td:745
605 OpGroupSMin = 590, // SPIRVInstrInfo.td:742
606 OpGroupUMax = 591, // SPIRVInstrInfo.td:744
607 OpGroupUMin = 592, // SPIRVInstrInfo.td:741
608 OpGroupWaitEvents = 593, // SPIRVInstrInfo.td:726
609 OpIAddCarryS = 594, // SPIRVInstrInfo.td:48
610 OpIAddCarryV = 595, // SPIRVInstrInfo.td:53
611 OpIAddS = 596, // SPIRVInstrInfo.td:48
612 OpIAddV = 597, // SPIRVInstrInfo.td:53
613 OpIEqual = 598, // SPIRVInstrInfo.td:581
614 OpIMulS = 599, // SPIRVInstrInfo.td:48
615 OpIMulV = 600, // SPIRVInstrInfo.td:53
616 OpINotEqual = 601, // SPIRVInstrInfo.td:582
617 OpISubBorrowS = 602, // SPIRVInstrInfo.td:48
618 OpISubBorrowV = 603, // SPIRVInstrInfo.td:53
619 OpISubS = 604, // SPIRVInstrInfo.td:48
620 OpISubV = 605, // SPIRVInstrInfo.td:53
621 OpImage = 606, // SPIRVInstrInfo.td:358
622 OpImageDrefGather = 607, // SPIRVInstrInfo.td:348
623 OpImageFetch = 608, // SPIRVInstrInfo.td:342
624 OpImageGather = 609, // SPIRVInstrInfo.td:345
625 OpImageQueryFormat = 610, // SPIRVInstrInfo.td:359
626 OpImageQueryLevels = 611, // SPIRVInstrInfo.td:364
627 OpImageQueryLod = 612, // SPIRVInstrInfo.td:363
628 OpImageQueryOrder = 613, // SPIRVInstrInfo.td:360
629 OpImageQuerySamples = 614, // SPIRVInstrInfo.td:365
630 OpImageQuerySize = 615, // SPIRVInstrInfo.td:362
631 OpImageQuerySizeLod = 616, // SPIRVInstrInfo.td:361
632 OpImageRead = 617, // SPIRVInstrInfo.td:352
633 OpImageSampleDrefExplicitLod = 618, // SPIRVInstrInfo.td:324
634 OpImageSampleDrefImplicitLod = 619, // SPIRVInstrInfo.td:321
635 OpImageSampleExplicitLod = 620, // SPIRVInstrInfo.td:317
636 OpImageSampleFootprintNV = 621, // SPIRVInstrInfo.td:411
637 OpImageSampleImplicitLod = 622, // SPIRVInstrInfo.td:314
638 OpImageSampleProjDrefExplicitLod = 623, // SPIRVInstrInfo.td:338
639 OpImageSampleProjDrefImplicitLod = 624, // SPIRVInstrInfo.td:335
640 OpImageSampleProjExplicitLod = 625, // SPIRVInstrInfo.td:331
641 OpImageSampleProjImplicitLod = 626, // SPIRVInstrInfo.td:328
642 OpImageSparseDrefGather = 627, // SPIRVInstrInfo.td:401
643 OpImageSparseFetch = 628, // SPIRVInstrInfo.td:395
644 OpImageSparseGather = 629, // SPIRVInstrInfo.td:398
645 OpImageSparseRead = 630, // SPIRVInstrInfo.td:407
646 OpImageSparseSampleDrefExplicitLod = 631, // SPIRVInstrInfo.td:377
647 OpImageSparseSampleDrefImplicitLod = 632, // SPIRVInstrInfo.td:374
648 OpImageSparseSampleExplicitLod = 633, // SPIRVInstrInfo.td:370
649 OpImageSparseSampleImplicitLod = 634, // SPIRVInstrInfo.td:367
650 OpImageSparseSampleProjDrefExplicitLod = 635, // SPIRVInstrInfo.td:391
651 OpImageSparseSampleProjDrefImplicitLod = 636, // SPIRVInstrInfo.td:388
652 OpImageSparseSampleProjExplicitLod = 637, // SPIRVInstrInfo.td:384
653 OpImageSparseSampleProjImplicitLod = 638, // SPIRVInstrInfo.td:381
654 OpImageSparseTexelsResident = 639, // SPIRVInstrInfo.td:405
655 OpImageTexelPointer = 640, // SPIRVInstrInfo.td:255
656 OpImageWrite = 641, // SPIRVInstrInfo.td:355
657 OpInBoundsAccessChain = 642, // SPIRVInstrInfo.td:268
658 OpInBoundsPtrAccessChain = 643, // SPIRVInstrInfo.td:278
659 OpIsFinite = 644, // SPIRVInstrInfo.td:565
660 OpIsInf = 645, // SPIRVInstrInfo.td:564
661 OpIsNan = 646, // SPIRVInstrInfo.td:563
662 OpIsNormal = 647, // SPIRVInstrInfo.td:566
663 OpIsValidEvent = 648, // SPIRVInstrInfo.td:759
664 OpIsValidReserveId = 649, // SPIRVInstrInfo.td:789
665 OpKill = 650, // SPIRVInstrInfo.td:640
666 OpLabel = 651, // SPIRVInstrInfo.td:632
667 OpLessOrGreater = 652, // SPIRVInstrInfo.td:569
668 OpLifetimeStart = 653, // SPIRVInstrInfo.td:645
669 OpLifetimeStop = 654, // SPIRVInstrInfo.td:646
670 OpLine = 655, // SPIRVInstrInfo.td:117
671 OpLoad = 656, // SPIRVInstrInfo.td:258
672 OpLogicalAnd = 657, // SPIRVInstrInfo.td:576
673 OpLogicalEqual = 658, // SPIRVInstrInfo.td:573
674 OpLogicalNot = 659, // SPIRVInstrInfo.td:577
675 OpLogicalNotEqual = 660, // SPIRVInstrInfo.td:574
676 OpLogicalOr = 661, // SPIRVInstrInfo.td:575
677 OpLoopControlINTEL = 662, // SPIRVInstrInfo.td:628
678 OpLoopMerge = 663, // SPIRVInstrInfo.td:626
679 OpMatrixTimesMatrix = 664, // SPIRVInstrInfo.td:507
680 OpMatrixTimesScalar = 665, // SPIRVInstrInfo.td:504
681 OpMatrixTimesVector = 666, // SPIRVInstrInfo.td:506
682 OpMemberDecorate = 667, // SPIRVInstrInfo.td:126
683 OpMemberDecorateString = 668, // SPIRVInstrInfo.td:136
684 OpMemberName = 669, // SPIRVInstrInfo.td:114
685 OpMemoryBarrier = 670, // SPIRVInstrInfo.td:709
686 OpMemoryModel = 671, // SPIRVInstrInfo.td:153
687 OpMemoryNamedBarrier = 672, // SPIRVInstrInfo.td:712
688 OpModuleProcessed = 673, // SPIRVInstrInfo.td:119
689 OpName = 674, // SPIRVInstrInfo.td:113
690 OpNamedBarrierInitialize = 675, // SPIRVInstrInfo.td:711
691 OpNoLine = 676, // SPIRVInstrInfo.td:118
692 OpNop = 677, // SPIRVInstrInfo.td:97
693 OpNot = 678, // SPIRVInstrInfo.td:542
694 OpOrdered = 679, // SPIRVInstrInfo.td:570
695 OpOuterProduct = 680, // SPIRVInstrInfo.td:509
696 OpPhi = 681, // SPIRVInstrInfo.td:624
697 OpPredicatedLoadINTEL = 682, // SPIRVInstrInfo.td:1100
698 OpPredicatedStoreINTEL = 683, // SPIRVInstrInfo.td:1102
699 OpPtrAccessChain = 684, // SPIRVInstrInfo.td:271
700 OpPtrCastToCrossWorkgroupINTEL = 685, // SPIRVInstrInfo.td:441
701 OpPtrCastToGeneric = 686, // SPIRVInstrInfo.td:434
702 OpPtrDiff = 687, // SPIRVInstrInfo.td:285
703 OpPtrEqual = 688, // SPIRVInstrInfo.td:281
704 OpPtrNotEqual = 689, // SPIRVInstrInfo.td:283
705 OpQuantizeToF16 = 690, // SPIRVInstrInfo.td:426
706 OpReadClockKHR = 691, // SPIRVInstrInfo.td:859
707 OpReadPipe = 692, // SPIRVInstrInfo.td:773
708 OpReadPipeBlockingALTERA = 693, // SPIRVInstrInfo.td:1106
709 OpReleaseEvent = 694, // SPIRVInstrInfo.td:756
710 OpReserveReadPipePackets = 695, // SPIRVInstrInfo.td:781
711 OpReserveWritePipePackets = 696, // SPIRVInstrInfo.td:783
712 OpReservedReadPipe = 697, // SPIRVInstrInfo.td:777
713 OpReservedWritePipe = 698, // SPIRVInstrInfo.td:779
714 OpRestoreMemoryINTEL = 699, // SPIRVInstrInfo.td:294
715 OpRetainEvent = 700, // SPIRVInstrInfo.td:755
716 OpReturn = 701, // SPIRVInstrInfo.td:641
717 OpReturnValue = 702, // SPIRVInstrInfo.td:642
718 OpRoundFToTF32INTEL = 703, // SPIRVInstrInfo.td:449
719 OpSConvert = 704, // SPIRVInstrInfo.td:423
720 OpSDivS = 705, // SPIRVInstrInfo.td:48
721 OpSDivV = 706, // SPIRVInstrInfo.td:53
722 OpSDot = 707, // SPIRVInstrInfo.td:517
723 OpSDotAccSat = 708, // SPIRVInstrInfo.td:523
724 OpSGreaterThan = 709, // SPIRVInstrInfo.td:585
725 OpSGreaterThanEqual = 710, // SPIRVInstrInfo.td:587
726 OpSLessThan = 711, // SPIRVInstrInfo.td:589
727 OpSLessThanEqual = 712, // SPIRVInstrInfo.td:591
728 OpSMod = 713, // SPIRVInstrInfo.td:496
729 OpSMulExtended = 714, // SPIRVInstrInfo.td:515
730 OpSNegate = 715, // SPIRVInstrInfo.td:473
731 OpSRemS = 716, // SPIRVInstrInfo.td:48
732 OpSRemV = 717, // SPIRVInstrInfo.td:53
733 OpSUDot = 718, // SPIRVInstrInfo.td:521
734 OpSUDotAccSat = 719, // SPIRVInstrInfo.td:527
735 OpSampledImage = 720, // SPIRVInstrInfo.td:312
736 OpSatConvertSToU = 721, // SPIRVInstrInfo.td:430
737 OpSatConvertUToS = 722, // SPIRVInstrInfo.td:431
738 OpSaveMemoryINTEL = 723, // SPIRVInstrInfo.td:292
739 OpSelectSFSCond = 724, // SPIRVInstrInfo.td:67
740 OpSelectSFVCond = 725, // SPIRVInstrInfo.td:68
741 OpSelectSISCond = 726, // SPIRVInstrInfo.td:63
742 OpSelectSIVCond = 727, // SPIRVInstrInfo.td:64
743 OpSelectSPSCond = 728, // SPIRVInstrInfo.td:59
744 OpSelectSPVCond = 729, // SPIRVInstrInfo.td:60
745 OpSelectVFSCond = 730, // SPIRVInstrInfo.td:80
746 OpSelectVFVCond = 731, // SPIRVInstrInfo.td:81
747 OpSelectVISCond = 732, // SPIRVInstrInfo.td:76
748 OpSelectVIVCond = 733, // SPIRVInstrInfo.td:77
749 OpSelectVPSCond = 734, // SPIRVInstrInfo.td:72
750 OpSelectVPVCond = 735, // SPIRVInstrInfo.td:73
751 OpSelectionMerge = 736, // SPIRVInstrInfo.td:630
752 OpSetUserEventStatus = 737, // SPIRVInstrInfo.td:761
753 OpShiftLeftLogicalS = 738, // SPIRVInstrInfo.td:48
754 OpShiftLeftLogicalV = 739, // SPIRVInstrInfo.td:53
755 OpShiftRightArithmeticS = 740, // SPIRVInstrInfo.td:48
756 OpShiftRightArithmeticV = 741, // SPIRVInstrInfo.td:53
757 OpShiftRightLogicalS = 742, // SPIRVInstrInfo.td:48
758 OpShiftRightLogicalV = 743, // SPIRVInstrInfo.td:53
759 OpSignBitSet = 744, // SPIRVInstrInfo.td:567
760 OpSizeOf = 745, // SPIRVInstrInfo.td:99
761 OpSource = 746, // SPIRVInstrInfo.td:109
762 OpSourceContinued = 747, // SPIRVInstrInfo.td:107
763 OpSourceExtension = 748, // SPIRVInstrInfo.td:111
764 OpSpecConstant = 749, // SPIRVInstrInfo.td:242
765 OpSpecConstantComposite = 750, // SPIRVInstrInfo.td:244
766 OpSpecConstantCompositeContinuedINTEL = 751, // SPIRVInstrInfo.td:246
767 OpSpecConstantFalse = 752, // SPIRVInstrInfo.td:241
768 OpSpecConstantOp = 753, // SPIRVInstrInfo.td:248
769 OpSpecConstantTrue = 754, // SPIRVInstrInfo.td:240
770 OpStore = 755, // SPIRVInstrInfo.td:260
771 OpStrictFAddS = 756, // SPIRVInstrInfo.td:46
772 OpStrictFAddV = 757, // SPIRVInstrInfo.td:51
773 OpStrictFDivS = 758, // SPIRVInstrInfo.td:46
774 OpStrictFDivV = 759, // SPIRVInstrInfo.td:51
775 OpStrictFMulS = 760, // SPIRVInstrInfo.td:46
776 OpStrictFMulV = 761, // SPIRVInstrInfo.td:51
777 OpStrictFRemS = 762, // SPIRVInstrInfo.td:46
778 OpStrictFRemV = 763, // SPIRVInstrInfo.td:51
779 OpStrictFSubS = 764, // SPIRVInstrInfo.td:46
780 OpStrictFSubV = 765, // SPIRVInstrInfo.td:51
781 OpString = 766, // SPIRVInstrInfo.td:116
782 OpSubgroup2DBlockLoadINTEL = 767, // SPIRVInstrInfo.td:1083
783 OpSubgroup2DBlockLoadTransformINTEL = 768, // SPIRVInstrInfo.td:1089
784 OpSubgroup2DBlockLoadTransposeINTEL = 769, // SPIRVInstrInfo.td:1086
785 OpSubgroup2DBlockPrefetchINTEL = 770, // SPIRVInstrInfo.td:1092
786 OpSubgroup2DBlockStoreINTEL = 771, // SPIRVInstrInfo.td:1095
787 OpSubgroupBlockReadINTEL = 772, // SPIRVInstrInfo.td:884
788 OpSubgroupBlockWriteINTEL = 773, // SPIRVInstrInfo.td:886
789 OpSubgroupImageBlockReadINTEL = 774, // SPIRVInstrInfo.td:888
790 OpSubgroupImageBlockWriteINTEL = 775, // SPIRVInstrInfo.td:890
791 OpSubgroupImageMediaBlockReadINTEL = 776, // SPIRVInstrInfo.td:894
792 OpSubgroupImageMediaBlockWriteINTEL = 777, // SPIRVInstrInfo.td:896
793 OpSubgroupMatrixMultiplyAccumulateINTEL = 778, // SPIRVInstrInfo.td:747
794 OpSubgroupShuffleDownINTEL = 779, // SPIRVInstrInfo.td:878
795 OpSubgroupShuffleINTEL = 780, // SPIRVInstrInfo.td:876
796 OpSubgroupShuffleUpINTEL = 781, // SPIRVInstrInfo.td:880
797 OpSubgroupShuffleXorINTEL = 782, // SPIRVInstrInfo.td:882
798 OpSwitch = 783, // SPIRVInstrInfo.td:637
799 OpTranspose = 784, // SPIRVInstrInfo.td:468
800 OpTypeAccelerationStructureNV = 785, // SPIRVInstrInfo.td:204
801 OpTypeArray = 786, // SPIRVInstrInfo.td:182
802 OpTypeBool = 787, // SPIRVInstrInfo.td:167
803 OpTypeCooperativeMatrixKHR = 788, // SPIRVInstrInfo.td:209
804 OpTypeCooperativeMatrixNV = 789, // SPIRVInstrInfo.td:206
805 OpTypeDeviceEvent = 790, // SPIRVInstrInfo.td:196
806 OpTypeEvent = 791, // SPIRVInstrInfo.td:195
807 OpTypeFloat = 792, // SPIRVInstrInfo.td:170
808 OpTypeForwardPointer = 793, // SPIRVInstrInfo.td:200
809 OpTypeFunction = 794, // SPIRVInstrInfo.td:193
810 OpTypeImage = 795, // SPIRVInstrInfo.td:176
811 OpTypeInt = 796, // SPIRVInstrInfo.td:168
812 OpTypeMatrix = 797, // SPIRVInstrInfo.td:174
813 OpTypeNamedBarrier = 798, // SPIRVInstrInfo.td:203
814 OpTypeOpaque = 799, // SPIRVInstrInfo.td:189
815 OpTypePipe = 800, // SPIRVInstrInfo.td:199
816 OpTypePipeStorage = 801, // SPIRVInstrInfo.td:202
817 OpTypePointer = 802, // SPIRVInstrInfo.td:191
818 OpTypeQueue = 803, // SPIRVInstrInfo.td:198
819 OpTypeReserveId = 804, // SPIRVInstrInfo.td:197
820 OpTypeRuntimeArray = 805, // SPIRVInstrInfo.td:184
821 OpTypeSampledImage = 806, // SPIRVInstrInfo.td:180
822 OpTypeSampler = 807, // SPIRVInstrInfo.td:179
823 OpTypeStruct = 808, // SPIRVInstrInfo.td:186
824 OpTypeStructContinuedINTEL = 809, // SPIRVInstrInfo.td:187
825 OpTypeVector = 810, // SPIRVInstrInfo.td:172
826 OpTypeVoid = 811, // SPIRVInstrInfo.td:166
827 OpUConvert = 812, // SPIRVInstrInfo.td:422
828 OpUDivS = 813, // SPIRVInstrInfo.td:48
829 OpUDivV = 814, // SPIRVInstrInfo.td:53
830 OpUDot = 815, // SPIRVInstrInfo.td:519
831 OpUDotAccSat = 816, // SPIRVInstrInfo.td:525
832 OpUGreaterThan = 817, // SPIRVInstrInfo.td:584
833 OpUGreaterThanEqual = 818, // SPIRVInstrInfo.td:586
834 OpULessThan = 819, // SPIRVInstrInfo.td:588
835 OpULessThanEqual = 820, // SPIRVInstrInfo.td:590
836 OpUModS = 821, // SPIRVInstrInfo.td:48
837 OpUModV = 822, // SPIRVInstrInfo.td:53
838 OpUMulExtended = 823, // SPIRVInstrInfo.td:514
839 OpUndef = 824, // SPIRVInstrInfo.td:98
840 OpUnordered = 825, // SPIRVInstrInfo.td:571
841 OpUnreachable = 826, // SPIRVInstrInfo.td:643
842 OpVariable = 827, // SPIRVInstrInfo.td:253
843 OpVariableLengthArrayINTEL = 828, // SPIRVInstrInfo.td:290
844 OpVectorExtractDynamic = 829, // SPIRVInstrInfo.td:453
845 OpVectorInsertDynamic = 830, // SPIRVInstrInfo.td:455
846 OpVectorShuffle = 831, // SPIRVInstrInfo.td:457
847 OpVectorTimesMatrix = 832, // SPIRVInstrInfo.td:505
848 OpVectorTimesScalar = 833, // SPIRVInstrInfo.td:503
849 OpWritePipe = 834, // SPIRVInstrInfo.td:775
850 OpWritePipeBlockingALTERA = 835, // SPIRVInstrInfo.td:1108
851 INSTRUCTION_LIST_END = 836
852 };
853
854} // namespace llvm::SPIRV
855
856#endif // GET_INSTRINFO_ENUM
857
858#ifdef GET_INSTRINFO_SCHED_ENUM
859#undef GET_INSTRINFO_SCHED_ENUM
860
861namespace llvm::SPIRV::Sched {
862
863 enum {
864 NoInstrModel = 0,
865 SCHED_LIST_END = 1
866 };
867
868} // namespace llvm::SPIRV::Sched
869
870#endif // GET_INSTRINFO_SCHED_ENUM
871
872#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
873
874namespace llvm {
875
876struct SPIRVInstrTable {
877 MCInstrDesc Insts[836];
878 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
879 MCPhysReg ImplicitOps[1];
880 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
881 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
882 MCOperandInfo OperandInfo[489];
883};
884} // namespace llvm
885
886#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
887
888#ifdef GET_INSTRINFO_MC_DESC
889#undef GET_INSTRINFO_MC_DESC
890
891namespace llvm {
892
893static_assert((sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
894static constexpr unsigned SPIRVOpInfoBase = (sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) / sizeof(MCOperandInfo);
895
896extern const SPIRVInstrTable SPIRVDescs = {
897 {
898 { 835, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipeBlockingALTERA
899 { 834, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipe
900 { 833, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesScalar
901 { 832, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesMatrix
902 { 831, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorShuffle
903 { 830, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorInsertDynamic
904 { 829, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 485, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorExtractDynamic
905 { 828, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariableLengthArrayINTEL
906 { 827, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 482, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariable
907 { 826, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnreachable
908 { 825, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnordered
909 { 824, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUndef
910 { 823, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUMulExtended
911 { 822, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModV
912 { 821, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModS
913 { 820, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThanEqual
914 { 819, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThan
915 { 818, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThanEqual
916 { 817, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThan
917 { 816, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDotAccSat
918 { 815, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDot
919 { 814, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivV
920 { 813, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivS
921 { 812, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUConvert
922 { 811, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVoid
923 { 810, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 476, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVector
924 { 809, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStructContinuedINTEL
925 { 808, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStruct
926 { 807, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampler
927 { 806, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 463, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampledImage
928 { 805, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 463, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeRuntimeArray
929 { 804, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeReserveId
930 { 803, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeQueue
931 { 802, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 479, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePointer
932 { 801, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipeStorage
933 { 800, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 461, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipe
934 { 799, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 461, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeOpaque
935 { 798, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeNamedBarrier
936 { 797, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 476, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeMatrix
937 { 796, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 473, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeInt
938 { 795, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 465, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeImage
939 { 794, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 463, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFunction
940 { 793, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 461, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeForwardPointer
941 { 792, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFloat
942 { 791, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeEvent
943 { 790, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeDeviceEvent
944 { 789, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 456, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixNV
945 { 788, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 450, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixKHR
946 { 787, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeBool
947 { 786, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeArray
948 { 785, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeAccelerationStructureNV
949 { 784, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTranspose
950 { 783, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSwitch
951 { 782, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleXorINTEL
952 { 781, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleUpINTEL
953 { 780, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleINTEL
954 { 779, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleDownINTEL
955 { 778, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupMatrixMultiplyAccumulateINTEL
956 { 777, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 325, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockWriteINTEL
957 { 776, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockReadINTEL
958 { 775, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockWriteINTEL
959 { 774, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockReadINTEL
960 { 773, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockWriteINTEL
961 { 772, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockReadINTEL
962 { 771, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 427, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockStoreINTEL
963 { 770, 9, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 437, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockPrefetchINTEL
964 { 769, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 427, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransposeINTEL
965 { 768, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 427, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransformINTEL
966 { 767, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 427, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadINTEL
967 { 766, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpString
968 { 765, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubV
969 { 764, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubS
970 { 763, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemV
971 { 762, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemS
972 { 761, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulV
973 { 760, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulS
974 { 759, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivV
975 { 758, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivS
976 { 757, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddV
977 { 756, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddS
978 { 755, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStore
979 { 754, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantTrue
980 { 753, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantOp
981 { 752, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantFalse
982 { 751, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantCompositeContinuedINTEL
983 { 750, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantComposite
984 { 749, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 420, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstant
985 { 748, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceExtension
986 { 747, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceContinued
987 { 746, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 36, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSource
988 { 745, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSizeOf
989 { 744, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSignBitSet
990 { 743, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalV
991 { 742, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalS
992 { 741, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticV
993 { 740, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticS
994 { 739, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalV
995 { 738, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalS
996 { 737, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSetUserEventStatus
997 { 736, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 13, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectionMerge
998 { 735, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 415, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPVCond
999 { 734, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 410, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPSCond
1000 { 733, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 405, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVIVCond
1001 { 732, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 400, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVISCond
1002 { 731, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 395, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFVCond
1003 { 730, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 390, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFSCond
1004 { 729, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 385, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPVCond
1005 { 728, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 380, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPSCond
1006 { 727, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 375, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSIVCond
1007 { 726, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 370, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSISCond
1008 { 725, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 365, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFVCond
1009 { 724, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 360, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFSCond
1010 { 723, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSaveMemoryINTEL
1011 { 722, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertUToS
1012 { 721, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertSToU
1013 { 720, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSampledImage
1014 { 719, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDotAccSat
1015 { 718, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDot
1016 { 717, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemV
1017 { 716, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemS
1018 { 715, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSNegate
1019 { 714, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMulExtended
1020 { 713, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMod
1021 { 712, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThanEqual
1022 { 711, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThan
1023 { 710, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThanEqual
1024 { 709, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThan
1025 { 708, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDotAccSat
1026 { 707, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDot
1027 { 706, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivV
1028 { 705, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivS
1029 { 704, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSConvert
1030 { 703, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRoundFToTF32INTEL
1031 { 702, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturnValue
1032 { 701, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturn
1033 { 700, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRetainEvent
1034 { 699, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRestoreMemoryINTEL
1035 { 698, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 208, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedWritePipe
1036 { 697, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 208, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedReadPipe
1037 { 696, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveWritePipePackets
1038 { 695, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveReadPipePackets
1039 { 694, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReleaseEvent
1040 { 693, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipeBlockingALTERA
1041 { 692, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipe
1042 { 691, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadClockKHR
1043 { 690, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpQuantizeToF16
1044 { 689, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrNotEqual
1045 { 688, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrEqual
1046 { 687, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrDiff
1047 { 686, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToGeneric
1048 { 685, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToCrossWorkgroupINTEL
1049 { 684, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrAccessChain
1050 { 683, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedStoreINTEL
1051 { 682, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedLoadINTEL
1052 { 681, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPhi
1053 { 680, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOuterProduct
1054 { 679, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOrdered
1055 { 678, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNot
1056 { 677, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNop
1057 { 676, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNoLine
1058 { 675, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNamedBarrierInitialize
1059 { 674, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 277, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpName
1060 { 673, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpModuleProcessed
1061 { 672, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryNamedBarrier
1062 { 671, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 13, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryModel
1063 { 670, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryBarrier
1064 { 669, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 353, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberName
1065 { 668, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 356, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorateString
1066 { 667, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 353, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorate
1067 { 666, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesVector
1068 { 665, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesScalar
1069 { 664, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesMatrix
1070 { 663, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 15, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopMerge
1071 { 662, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopControlINTEL
1072 { 661, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalOr
1073 { 660, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNotEqual
1074 { 659, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNot
1075 { 658, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalEqual
1076 { 657, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalAnd
1077 { 656, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoad
1078 { 655, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 350, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLine
1079 { 654, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 348, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStop
1080 { 653, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 348, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStart
1081 { 652, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLessOrGreater
1082 { 651, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLabel
1083 { 650, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpKill
1084 { 649, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidReserveId
1085 { 648, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidEvent
1086 { 647, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNormal
1087 { 646, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNan
1088 { 645, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsInf
1089 { 644, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsFinite
1090 { 643, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsPtrAccessChain
1091 { 642, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsAccessChain
1092 { 641, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageWrite
1093 { 640, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageTexelPointer
1094 { 639, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseTexelsResident
1095 { 638, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjImplicitLod
1096 { 637, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 335, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjExplicitLod
1097 { 636, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefImplicitLod
1098 { 635, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 335, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefExplicitLod
1099 { 634, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleImplicitLod
1100 { 633, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 342, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleExplicitLod
1101 { 632, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefImplicitLod
1102 { 631, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 335, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefExplicitLod
1103 { 630, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseRead
1104 { 629, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseGather
1105 { 628, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseFetch
1106 { 627, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseDrefGather
1107 { 626, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjImplicitLod
1108 { 625, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 335, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjExplicitLod
1109 { 624, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefImplicitLod
1110 { 623, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 335, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefExplicitLod
1111 { 622, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleImplicitLod
1112 { 621, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleFootprintNV
1113 { 620, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 342, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleExplicitLod
1114 { 619, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefImplicitLod
1115 { 618, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 335, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefExplicitLod
1116 { 617, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageRead
1117 { 616, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySizeLod
1118 { 615, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySize
1119 { 614, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySamples
1120 { 613, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryOrder
1121 { 612, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLod
1122 { 611, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLevels
1123 { 610, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryFormat
1124 { 609, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageGather
1125 { 608, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageFetch
1126 { 607, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageDrefGather
1127 { 606, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImage
1128 { 605, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubV
1129 { 604, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubS
1130 { 603, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowV
1131 { 602, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowS
1132 { 601, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpINotEqual
1133 { 600, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulV
1134 { 599, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulS
1135 { 598, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIEqual
1136 { 597, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddV
1137 { 596, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddS
1138 { 595, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryV
1139 { 594, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryS
1140 { 593, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupWaitEvents
1141 { 592, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMin
1142 { 591, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMax
1143 { 590, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMin
1144 { 589, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMax
1145 { 588, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 258, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveWritePipePackets
1146 { 587, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 258, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveReadPipePackets
1147 { 586, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMin
1148 { 585, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMax
1149 { 584, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleXor
1150 { 583, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleUp
1151 { 582, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleDown
1152 { 581, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffle
1153 { 580, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMin
1154 { 579, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMax
1155 { 578, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformRotateKHR
1156 { 577, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalXor
1157 { 576, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalOr
1158 { 575, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalAnd
1159 { 574, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformInverseBallot
1160 { 573, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIMul
1161 { 572, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIAdd
1162 { 571, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMul
1163 { 570, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMin
1164 { 569, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMax
1165 { 568, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFAdd
1166 { 567, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformElect
1167 { 566, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcastFirst
1168 { 565, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcast
1169 { 564, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseXor
1170 { 563, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseOr
1171 { 562, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseAnd
1172 { 561, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindMSB
1173 { 560, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindLSB
1174 { 559, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitExtract
1175 { 558, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitCount
1176 { 557, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallot
1177 { 556, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAny
1178 { 555, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAllEqual
1179 { 554, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAll
1180 { 553, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalXorKHR
1181 { 552, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalOrKHR
1182 { 551, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalAndKHR
1183 { 550, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIMulKHR
1184 { 549, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIAdd
1185 { 548, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMulKHR
1186 { 547, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMin
1187 { 546, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMax
1188 { 545, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 330, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFAdd
1189 { 544, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 325, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitWritePipe
1190 { 543, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 325, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitReadPipe
1191 { 542, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBroadcast
1192 { 541, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseXorKHR
1193 { 540, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseOrKHR
1194 { 539, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseAndKHR
1195 { 538, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 208, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAsyncCopy
1196 { 537, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAny
1197 { 536, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAll
1198 { 535, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetNumPipePackets
1199 { 534, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetMaxPipePackets
1200 { 533, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetDefaultQueue
1201 { 532, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericPtrMemSemantics
1202 { 531, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtrExplicit
1203 { 530, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtr
1204 { 529, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthFine
1205 { 528, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthCoarse
1206 { 527, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidth
1207 { 526, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionPointerCallINTEL
1208 { 525, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionParameter
1209 { 524, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionEnd
1210 { 523, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionCall
1211 { 522, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 312, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunction
1212 { 521, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFmaKHR
1213 { 520, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSqrtALTERA
1214 { 519, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinPiALTERA
1215 { 518, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosPiALTERA
1216 { 517, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosALTERA
1217 { 516, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinALTERA
1218 { 515, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRsqrtALTERA
1219 { 514, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRecipALTERA
1220 { 513, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedLogALTERA
1221 { 512, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedExpALTERA
1222 { 511, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosPiALTERA
1223 { 510, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosALTERA
1224 { 509, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordNotEqual
1225 { 508, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThanEqual
1226 { 507, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThan
1227 { 506, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThanEqual
1228 { 505, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThan
1229 { 504, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordEqual
1230 { 503, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubV
1231 { 502, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubS
1232 { 501, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemV
1233 { 500, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemS
1234 { 499, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdNotEqual
1235 { 498, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThanEqual
1236 { 497, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThan
1237 { 496, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThanEqual
1238 { 495, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThan
1239 { 494, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdEqual
1240 { 493, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 309, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegateV
1241 { 492, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 245, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegate
1242 { 491, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulV
1243 { 490, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulS
1244 { 489, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMod
1245 { 488, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivV
1246 { 487, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivS
1247 { 486, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFConvert
1248 { 485, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddV
1249 { 484, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddS
1250 { 483, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtension
1251 { 482, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInstImport
1252 { 481, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInst
1253 { 480, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExpectKHR
1254 { 479, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionModeId
1255 { 478, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionMode
1256 { 477, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 294, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEntryPoint
1257 { 476, 12, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 282, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEnqueueKernel
1258 { 475, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndStreamPrimitive
1259 { 474, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndPrimitive
1260 { 473, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitVertex
1261 { 472, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitStreamVertex
1262 { 471, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDot
1263 { 470, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDemoteToHelperInvocation
1264 { 469, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 279, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateString
1265 { 468, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 277, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateId
1266 { 467, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 277, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorate
1267 { 466, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyFine
1268 { 465, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyCoarse
1269 { 464, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdy
1270 { 463, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxFine
1271 { 462, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxCoarse
1272 { 461, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdx
1273 { 460, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCrossWorkgroupCastToPtrINTEL
1274 { 459, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCreateUserEvent
1275 { 458, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyObject
1276 { 457, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemorySized
1277 { 456, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemory
1278 { 455, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyLogical
1279 { 454, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreKHR
1280 { 453, 7, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 270, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreCheckedINTEL
1281 { 452, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 265, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixPrefetchINTEL
1282 { 451, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixMulAddKHR
1283 { 450, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadKHR
1284 { 449, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 208, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadCheckedINTEL
1285 { 448, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLengthKHR
1286 { 447, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixGetElementCoordINTEL
1287 { 446, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 258, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixConstructCheckedINTEL
1288 { 445, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToPtr
1289 { 444, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToF
1290 { 443, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertSToF
1291 { 442, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertPtrToU
1292 { 441, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSamplerINTEL
1293 { 440, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSampledImageINTEL
1294 { 439, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToImageINTEL
1295 { 438, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToU
1296 { 437, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToS
1297 { 436, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToBF16INTEL
1298 { 435, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertBF16ToFINTEL
1299 { 434, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierWaitINTEL
1300 { 433, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierArriveINTEL
1301 { 432, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrier
1302 { 431, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 248, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantTrue
1303 { 430, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 253, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantSampler
1304 { 429, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantNull
1305 { 428, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 250, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantI
1306 { 427, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFunctionPointerINTEL
1307 { 426, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 248, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFalse
1308 { 425, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 245, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantF
1309 { 424, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantCompositeContinuedINTEL
1310 { 423, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantComposite
1311 { 422, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeInsert
1312 { 421, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeExtract
1313 { 420, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstructContinuedINTEL
1314 { 419, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstruct
1315 { 418, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitWritePipe
1316 { 417, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitReadPipe
1317 { 416, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCaptureEventProfilingInfo
1318 { 415, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCapability
1319 { 414, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBuildNDRange
1320 { 413, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 236, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranchConditional
1321 { 412, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranch
1322 { 411, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorV
1323 { 410, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorS
1324 { 409, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrV
1325 { 408, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrS
1326 { 407, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseFunctionINTEL
1327 { 406, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndV
1328 { 405, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndS
1329 { 404, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitcast
1330 { 403, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitReverse
1331 { 402, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldUExtract
1332 { 401, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldSExtract
1333 { 400, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldInsert
1334 { 399, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitCount
1335 { 398, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicXor
1336 { 397, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMin
1337 { 396, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMax
1338 { 395, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicStore
1339 { 394, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMin
1340 { 393, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMax
1341 { 392, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicOr
1342 { 391, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicLoad
1343 { 390, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicISub
1344 { 389, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIIncrement
1345 { 388, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIDecrement
1346 { 387, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIAdd
1347 { 386, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagTestAndSet
1348 { 385, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 216, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagClear
1349 { 384, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMinEXT
1350 { 383, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMaxEXT
1351 { 382, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFAddEXT
1352 { 381, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicExchange
1353 { 380, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 208, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchangeWeak
1354 { 379, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 208, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchange
1355 { 378, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 202, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicAnd
1356 { 377, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAssumeTrueKHR
1357 { 376, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmTargetINTEL
1358 { 375, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 194, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmINTEL
1359 { 374, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmCallINTEL
1360 { 373, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 190, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArrayLength
1361 { 372, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArithmeticFenceEXT
1362 { 371, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 174, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSubALTERA
1363 { 370, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSqrtALTERA
1364 { 369, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinPiALTERA
1365 { 368, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosPiALTERA
1366 { 367, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosALTERA
1367 { 366, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinALTERA
1368 { 365, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRecipALTERA
1369 { 364, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRSqrtALTERA
1370 { 363, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 174, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowRALTERA
1371 { 362, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 174, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowNALTERA
1372 { 361, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 174, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowALTERA
1373 { 360, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 174, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatMulALTERA
1374 { 359, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLogALTERA
1375 { 358, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog2ALTERA
1376 { 357, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog1pALTERA
1377 { 356, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog10ALTERA
1378 { 355, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 184, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLTALTERA
1379 { 354, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 184, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLEALTERA
1380 { 353, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 174, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatHypotALTERA
1381 { 352, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 184, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGTALTERA
1382 { 351, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 184, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGEALTERA
1383 { 350, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpm1ALTERA
1384 { 349, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpALTERA
1385 { 348, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp2ALTERA
1386 { 347, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp10ALTERA
1387 { 346, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 184, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatEQALTERA
1388 { 345, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 174, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatDivALTERA
1389 { 344, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosPiALTERA
1390 { 343, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosALTERA
1391 { 342, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCbrtALTERA
1392 { 341, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastToIntALTERA
1393 { 340, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastFromIntALTERA
1394 { 339, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastALTERA
1395 { 338, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 174, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatAddALTERA
1396 { 337, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanPiALTERA
1397 { 336, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanALTERA
1398 { 335, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 174, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATan2ALTERA
1399 { 334, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinPiALTERA
1400 { 333, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinALTERA
1401 { 332, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosPiALTERA
1402 { 331, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 166, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosALTERA
1403 { 330, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAny
1404 { 329, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAll
1405 { 328, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeListDeclINTEL
1406 { 327, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeDeclINTEL
1407 { 326, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 163, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasDomainDeclINTEL
1408 { 325, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAccessChain
1409 { 324, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNKNOWN_type
1410 { 323, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASSIGN_TYPE
1411 { 322, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1412 { 321, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1413 { 320, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1414 { 319, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1415 { 318, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1416 { 317, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1417 { 316, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1418 { 315, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1419 { 314, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1420 { 313, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1421 { 312, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1422 { 311, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1423 { 310, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1424 { 309, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1425 { 308, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1426 { 307, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1427 { 306, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1428 { 305, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1429 { 304, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1430 { 303, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1431 { 302, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1432 { 301, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1433 { 300, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1434 { 299, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1435 { 298, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1436 { 297, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1437 { 296, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1438 { 295, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 145, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1439 { 294, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1440 { 293, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1441 { 292, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1442 { 291, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1443 { 290, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1444 { 289, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1445 { 288, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1446 { 287, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1447 { 286, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1448 { 285, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1449 { 284, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1450 { 283, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1451 { 282, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1452 { 281, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1453 { 280, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1454 { 279, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1455 { 278, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1456 { 277, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1457 { 276, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1458 { 275, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1459 { 274, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1460 { 273, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1461 { 272, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1462 { 271, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1463 { 270, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1464 { 269, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1465 { 268, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1466 { 267, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1467 { 266, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1468 { 265, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1469 { 264, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1470 { 263, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1471 { 262, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1472 { 261, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1473 { 260, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1474 { 259, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
1475 { 258, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1476 { 257, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
1477 { 256, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1478 { 255, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1479 { 254, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1480 { 253, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1481 { 252, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1482 { 251, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1483 { 250, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1484 { 249, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1485 { 248, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1486 { 247, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1487 { 246, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 127, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1488 { 245, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1489 { 244, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1490 { 243, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1491 { 242, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1492 { 241, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1493 { 240, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1494 { 239, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1495 { 238, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1496 { 237, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1497 { 236, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1498 { 235, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1499 { 234, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1500 { 233, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1501 { 232, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1502 { 231, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1503 { 230, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1504 { 229, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1505 { 228, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1506 { 227, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1507 { 226, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1508 { 225, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1509 { 224, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1510 { 223, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1511 { 222, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1512 { 221, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1513 { 220, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1514 { 219, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1515 { 218, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1516 { 217, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1517 { 216, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1518 { 215, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1519 { 214, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1520 { 213, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1521 { 212, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1522 { 211, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1523 { 210, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1524 { 209, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1525 { 208, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1526 { 207, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1527 { 206, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1528 { 205, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1529 { 204, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1530 { 203, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1531 { 202, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1532 { 201, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1533 { 200, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1534 { 199, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1535 { 198, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1536 { 197, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1537 { 196, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1538 { 195, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1539 { 194, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1540 { 193, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1541 { 192, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1542 { 191, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1543 { 190, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1544 { 189, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1545 { 188, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1546 { 187, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1547 { 186, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1548 { 185, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1549 { 184, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1550 { 183, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1551 { 182, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1552 { 181, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1553 { 180, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1554 { 179, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1555 { 178, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1556 { 177, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1557 { 176, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1558 { 175, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1559 { 174, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1560 { 173, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1561 { 172, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1562 { 171, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1563 { 170, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1564 { 169, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1565 { 168, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1566 { 167, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1567 { 166, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1568 { 165, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1569 { 164, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1570 { 163, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1571 { 162, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1572 { 161, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1573 { 160, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1574 { 159, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1575 { 158, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1576 { 157, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1577 { 156, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1578 { 155, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1579 { 154, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1580 { 153, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1581 { 152, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1582 { 151, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1583 { 150, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1584 { 149, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1585 { 148, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1586 { 147, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1587 { 146, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1588 { 145, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1589 { 144, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1590 { 143, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1591 { 142, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1592 { 141, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1593 { 140, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1594 { 139, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1595 { 138, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1596 { 137, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1597 { 136, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1598 { 135, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1599 { 134, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1600 { 133, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1601 { 132, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1602 { 131, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1603 { 130, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 24, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1604 { 129, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1605 { 128, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1606 { 127, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1607 { 126, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1608 { 125, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1609 { 124, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1610 { 123, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1611 { 122, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1612 { 121, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1613 { 120, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1614 { 119, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1615 { 118, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1616 { 117, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1617 { 116, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1618 { 115, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1619 { 114, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1620 { 113, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1621 { 112, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1622 { 111, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1623 { 110, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1624 { 109, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1625 { 108, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1626 { 107, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 85, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1627 { 106, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 80, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1628 { 105, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1629 { 104, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1630 { 103, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1631 { 102, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1632 { 101, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1633 { 100, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1634 { 99, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1635 { 98, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1636 { 97, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1637 { 96, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1638 { 95, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1639 { 94, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1640 { 93, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1641 { 92, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1642 { 91, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1643 { 90, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1644 { 89, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1645 { 88, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1646 { 87, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1647 { 86, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1648 { 85, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1649 { 84, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1650 { 83, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1651 { 82, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1652 { 81, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1653 { 80, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1654 { 79, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1655 { 78, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1656 { 77, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 56, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1657 { 76, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1658 { 75, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1659 { 74, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1660 { 73, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1661 { 72, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1662 { 71, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1663 { 70, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1664 { 69, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1665 { 68, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1666 { 67, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1667 { 66, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1668 { 65, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1669 { 64, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1670 { 63, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1671 { 62, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1672 { 61, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1673 { 60, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1674 { 59, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1675 { 58, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1676 { 57, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1677 { 56, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1678 { 55, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1679 { 54, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1680 { 53, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1681 { 52, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1682 { 51, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1683 { 50, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1684 { 49, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1685 { 48, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1686 { 47, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1687 { 46, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1688 { 45, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1689 { 44, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1690 { 43, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1691 { 42, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 40, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21657
1692 { 41, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 38, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21656
1693 { 40, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1694 { 39, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1695 { 38, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1696 { 37, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1697 { 36, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1698 { 35, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1699 { 34, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1700 { 33, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1701 { 32, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 33, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21655
1702 { 31, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1703 { 30, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14301
1704 { 29, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 26, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1705 { 28, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1706 { 27, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1707 { 26, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1708 { 25, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1709 { 24, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1710 { 23, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1711 { 22, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1712 { 21, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1713 { 20, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1714 { 19, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1715 { 18, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1716 { 17, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1717 { 16, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1718 { 15, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1719 { 14, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1720 { 13, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1721 { 12, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1722 { 11, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1723 { 10, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1724 { 9, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1725 { 8, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1726 { 7, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1727 { 6, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1728 { 5, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1729 { 4, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1730 { 3, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1731 { 2, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1732 { 1, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1733 { 0, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1734 }, {
1735 /* 0 */
1736 }, {
1737 0
1738 }, {
1739 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1740 /* 1 */
1741 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1742 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1743 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1744 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1745 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1746 /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1747 /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1748 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1749 /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1750 /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1751 /* 32 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1752 /* 33 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1753 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1754 /* 38 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1755 /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1756 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1757 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1758 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1759 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1760 /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1761 /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1762 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1763 /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1764 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1765 /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1766 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1767 /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1768 /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1769 /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1770 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1771 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1772 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1773 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1774 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1775 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1776 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1777 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1778 /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1779 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1780 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1781 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1782 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1783 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1784 /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1785 /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1786 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1787 /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1788 /* 155 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1789 /* 158 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1790 /* 160 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1791 /* 163 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1792 /* 164 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1793 /* 166 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1794 /* 174 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1795 /* 184 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1796 /* 190 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1797 /* 194 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1798 /* 200 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1799 /* 202 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1800 /* 208 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1801 /* 216 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1802 /* 219 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1803 /* 224 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1804 /* 228 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1805 /* 232 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1806 /* 236 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1807 /* 239 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1808 /* 241 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1809 /* 245 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1810 /* 248 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1811 /* 250 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1812 /* 253 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1813 /* 258 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1814 /* 265 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1815 /* 270 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1816 /* 277 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1817 /* 279 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1818 /* 282 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1819 /* 294 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1820 /* 297 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1821 /* 301 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1822 /* 305 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1823 /* 309 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1824 /* 312 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1825 /* 316 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1826 /* 320 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1827 /* 325 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1828 /* 330 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1829 /* 335 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1830 /* 342 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1831 /* 348 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1832 /* 350 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1833 /* 353 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1834 /* 356 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1835 /* 360 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1836 /* 365 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1837 /* 370 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1838 /* 375 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1839 /* 380 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1840 /* 385 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1841 /* 390 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1842 /* 395 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1843 /* 400 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1844 /* 405 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1845 /* 410 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1846 /* 415 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1847 /* 420 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1848 /* 423 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1849 /* 427 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1850 /* 437 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1851 /* 446 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1852 /* 447 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1853 /* 450 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1854 /* 456 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1855 /* 461 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1856 /* 463 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1857 /* 465 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1858 /* 473 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1859 /* 476 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1860 /* 479 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1861 /* 482 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1862 /* 485 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1863 }
1864};
1865
1866
1867#ifdef __GNUC__
1868#pragma GCC diagnostic push
1869#pragma GCC diagnostic ignored "-Woverlength-strings"
1870#endif
1871extern const char SPIRVInstrNameData[] = {
1872 /* 0 */ "G_FLOG10\000"
1873 /* 9 */ "G_FEXP10\000"
1874 /* 18 */ "G_FLOG2\000"
1875 /* 26 */ "G_FATAN2\000"
1876 /* 35 */ "G_FEXP2\000"
1877 /* 43 */ "OpQuantizeToF16\000"
1878 /* 59 */ "G_FMA\000"
1879 /* 65 */ "G_STRICT_FMA\000"
1880 /* 78 */ "OpArbitraryFloatLog10ALTERA\000"
1881 /* 106 */ "OpArbitraryFloatExp10ALTERA\000"
1882 /* 134 */ "OpArbitraryFloatExpm1ALTERA\000"
1883 /* 162 */ "OpArbitraryFloatLog2ALTERA\000"
1884 /* 189 */ "OpArbitraryFloatATan2ALTERA\000"
1885 /* 217 */ "OpArbitraryFloatExp2ALTERA\000"
1886 /* 244 */ "OpArbitraryFloatGEALTERA\000"
1887 /* 269 */ "OpArbitraryFloatLEALTERA\000"
1888 /* 294 */ "OpArbitraryFloatPowNALTERA\000"
1889 /* 321 */ "OpArbitraryFloatEQALTERA\000"
1890 /* 346 */ "OpArbitraryFloatPowRALTERA\000"
1891 /* 373 */ "OpArbitraryFloatGTALTERA\000"
1892 /* 398 */ "OpArbitraryFloatLTALTERA\000"
1893 /* 423 */ "OpArbitraryFloatSubALTERA\000"
1894 /* 449 */ "OpArbitraryFloatAddALTERA\000"
1895 /* 475 */ "OpReadPipeBlockingALTERA\000"
1896 /* 500 */ "OpWritePipeBlockingALTERA\000"
1897 /* 526 */ "OpFixedLogALTERA\000"
1898 /* 543 */ "OpArbitraryFloatLogALTERA\000"
1899 /* 569 */ "OpArbitraryFloatATanPiALTERA\000"
1900 /* 598 */ "OpArbitraryFloatASinPiALTERA\000"
1901 /* 627 */ "OpFixedSinPiALTERA\000"
1902 /* 646 */ "OpArbitraryFloatSinPiALTERA\000"
1903 /* 674 */ "OpArbitraryFloatACosPiALTERA\000"
1904 /* 703 */ "OpFixedCosPiALTERA\000"
1905 /* 722 */ "OpFixedSinCosPiALTERA\000"
1906 /* 744 */ "OpArbitraryFloatSinCosPiALTERA\000"
1907 /* 775 */ "OpArbitraryFloatCosPiALTERA\000"
1908 /* 803 */ "OpArbitraryFloatMulALTERA\000"
1909 /* 829 */ "OpArbitraryFloatATanALTERA\000"
1910 /* 856 */ "OpArbitraryFloatASinALTERA\000"
1911 /* 883 */ "OpFixedSinALTERA\000"
1912 /* 900 */ "OpArbitraryFloatSinALTERA\000"
1913 /* 926 */ "OpArbitraryFloatLog1pALTERA\000"
1914 /* 954 */ "OpFixedRecipALTERA\000"
1915 /* 973 */ "OpArbitraryFloatRecipALTERA\000"
1916 /* 1001 */ "OpFixedExpALTERA\000"
1917 /* 1018 */ "OpArbitraryFloatExpALTERA\000"
1918 /* 1044 */ "OpArbitraryFloatACosALTERA\000"
1919 /* 1071 */ "OpFixedCosALTERA\000"
1920 /* 1088 */ "OpFixedSinCosALTERA\000"
1921 /* 1108 */ "OpArbitraryFloatSinCosALTERA\000"
1922 /* 1137 */ "OpArbitraryFloatCosALTERA\000"
1923 /* 1163 */ "OpArbitraryFloatCastFromIntALTERA\000"
1924 /* 1197 */ "OpArbitraryFloatCastToIntALTERA\000"
1925 /* 1229 */ "OpArbitraryFloatHypotALTERA\000"
1926 /* 1257 */ "OpArbitraryFloatCbrtALTERA\000"
1927 /* 1284 */ "OpArbitraryFloatRSqrtALTERA\000"
1928 /* 1312 */ "OpFixedSqrtALTERA\000"
1929 /* 1330 */ "OpArbitraryFloatSqrtALTERA\000"
1930 /* 1357 */ "OpFixedRsqrtALTERA\000"
1931 /* 1376 */ "OpArbitraryFloatCastALTERA\000"
1932 /* 1403 */ "OpArbitraryFloatDivALTERA\000"
1933 /* 1429 */ "OpArbitraryFloatPowALTERA\000"
1934 /* 1455 */ "OpGroupNonUniformBallotFindLSB\000"
1935 /* 1486 */ "OpGroupNonUniformBallotFindMSB\000"
1936 /* 1517 */ "G_FSUB\000"
1937 /* 1524 */ "G_STRICT_FSUB\000"
1938 /* 1538 */ "G_ATOMICRMW_FSUB\000"
1939 /* 1555 */ "G_SUB\000"
1940 /* 1561 */ "G_ATOMICRMW_SUB\000"
1941 /* 1577 */ "G_INTRINSIC\000"
1942 /* 1589 */ "G_FPTRUNC\000"
1943 /* 1599 */ "G_INTRINSIC_TRUNC\000"
1944 /* 1617 */ "G_TRUNC\000"
1945 /* 1625 */ "G_BUILD_VECTOR_TRUNC\000"
1946 /* 1646 */ "G_DYN_STACKALLOC\000"
1947 /* 1663 */ "G_FMAD\000"
1948 /* 1670 */ "G_INDEXED_SEXTLOAD\000"
1949 /* 1689 */ "G_SEXTLOAD\000"
1950 /* 1700 */ "G_INDEXED_ZEXTLOAD\000"
1951 /* 1719 */ "G_ZEXTLOAD\000"
1952 /* 1730 */ "G_INDEXED_LOAD\000"
1953 /* 1745 */ "G_LOAD\000"
1954 /* 1752 */ "G_VECREDUCE_FADD\000"
1955 /* 1769 */ "G_FADD\000"
1956 /* 1776 */ "G_VECREDUCE_SEQ_FADD\000"
1957 /* 1797 */ "G_STRICT_FADD\000"
1958 /* 1811 */ "G_ATOMICRMW_FADD\000"
1959 /* 1828 */ "G_VECREDUCE_ADD\000"
1960 /* 1844 */ "G_ADD\000"
1961 /* 1850 */ "G_PTR_ADD\000"
1962 /* 1860 */ "G_ATOMICRMW_ADD\000"
1963 /* 1876 */ "G_ATOMICRMW_NAND\000"
1964 /* 1893 */ "G_VECREDUCE_AND\000"
1965 /* 1909 */ "G_AND\000"
1966 /* 1915 */ "G_ATOMICRMW_AND\000"
1967 /* 1931 */ "LIFETIME_END\000"
1968 /* 1944 */ "G_BRCOND\000"
1969 /* 1953 */ "G_ATOMICRMW_USUB_COND\000"
1970 /* 1975 */ "G_LLROUND\000"
1971 /* 1985 */ "G_LROUND\000"
1972 /* 1994 */ "G_INTRINSIC_ROUND\000"
1973 /* 2012 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1974 /* 2038 */ "LOAD_STACK_GUARD\000"
1975 /* 2055 */ "PSEUDO_PROBE\000"
1976 /* 2068 */ "G_SSUBE\000"
1977 /* 2076 */ "G_USUBE\000"
1978 /* 2084 */ "G_FENCE\000"
1979 /* 2092 */ "ARITH_FENCE\000"
1980 /* 2104 */ "REG_SEQUENCE\000"
1981 /* 2117 */ "G_SADDE\000"
1982 /* 2125 */ "G_UADDE\000"
1983 /* 2133 */ "G_GET_FPMODE\000"
1984 /* 2146 */ "G_RESET_FPMODE\000"
1985 /* 2161 */ "G_SET_FPMODE\000"
1986 /* 2174 */ "G_FMINNUM_IEEE\000"
1987 /* 2189 */ "G_FMAXNUM_IEEE\000"
1988 /* 2204 */ "G_VSCALE\000"
1989 /* 2213 */ "G_JUMP_TABLE\000"
1990 /* 2226 */ "BUNDLE\000"
1991 /* 2233 */ "G_MEMCPY_INLINE\000"
1992 /* 2249 */ "RELOC_NONE\000"
1993 /* 2260 */ "LOCAL_ESCAPE\000"
1994 /* 2273 */ "ASSIGN_TYPE\000"
1995 /* 2285 */ "G_STACKRESTORE\000"
1996 /* 2300 */ "G_INDEXED_STORE\000"
1997 /* 2316 */ "G_STORE\000"
1998 /* 2324 */ "G_BITREVERSE\000"
1999 /* 2337 */ "FAKE_USE\000"
2000 /* 2346 */ "DBG_VALUE\000"
2001 /* 2356 */ "G_GLOBAL_VALUE\000"
2002 /* 2371 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2003 /* 2394 */ "CONVERGENCECTRL_GLUE\000"
2004 /* 2415 */ "G_STACKSAVE\000"
2005 /* 2427 */ "G_MEMMOVE\000"
2006 /* 2437 */ "G_FREEZE\000"
2007 /* 2446 */ "G_FCANONICALIZE\000"
2008 /* 2462 */ "G_FMODF\000"
2009 /* 2470 */ "G_CTLZ_ZERO_UNDEF\000"
2010 /* 2488 */ "G_CTTZ_ZERO_UNDEF\000"
2011 /* 2506 */ "INIT_UNDEF\000"
2012 /* 2517 */ "G_IMPLICIT_DEF\000"
2013 /* 2532 */ "DBG_INSTR_REF\000"
2014 /* 2546 */ "OpConvertSToF\000"
2015 /* 2560 */ "OpConvertUToF\000"
2016 /* 2574 */ "OpConstantF\000"
2017 /* 2586 */ "G_FNEG\000"
2018 /* 2593 */ "EXTRACT_SUBREG\000"
2019 /* 2608 */ "INSERT_SUBREG\000"
2020 /* 2622 */ "G_SEXT_INREG\000"
2021 /* 2635 */ "SUBREG_TO_REG\000"
2022 /* 2649 */ "G_ATOMIC_CMPXCHG\000"
2023 /* 2666 */ "G_ATOMICRMW_XCHG\000"
2024 /* 2683 */ "G_GET_ROUNDING\000"
2025 /* 2698 */ "G_SET_ROUNDING\000"
2026 /* 2713 */ "G_FLOG\000"
2027 /* 2720 */ "G_VAARG\000"
2028 /* 2728 */ "PREALLOCATED_ARG\000"
2029 /* 2745 */ "G_PREFETCH\000"
2030 /* 2756 */ "G_SMULH\000"
2031 /* 2764 */ "G_UMULH\000"
2032 /* 2772 */ "G_FTANH\000"
2033 /* 2780 */ "G_FSINH\000"
2034 /* 2788 */ "G_FCOSH\000"
2035 /* 2796 */ "DBG_PHI\000"
2036 /* 2804 */ "G_FPTOSI\000"
2037 /* 2813 */ "G_FPTOUI\000"
2038 /* 2822 */ "G_FPOWI\000"
2039 /* 2830 */ "OpConstantI\000"
2040 /* 2842 */ "COPY_LANEMASK\000"
2041 /* 2856 */ "G_PTRMASK\000"
2042 /* 2866 */ "GC_LABEL\000"
2043 /* 2875 */ "DBG_LABEL\000"
2044 /* 2885 */ "EH_LABEL\000"
2045 /* 2894 */ "ANNOTATION_LABEL\000"
2046 /* 2911 */ "ICALL_BRANCH_FUNNEL\000"
2047 /* 2931 */ "OpRoundFToTF32INTEL\000"
2048 /* 2951 */ "OpConvertFToBF16INTEL\000"
2049 /* 2973 */ "OpConvertBF16ToFINTEL\000"
2050 /* 2995 */ "OpSubgroupImageMediaBlockReadINTEL\000"
2051 /* 3030 */ "OpSubgroupImageBlockReadINTEL\000"
2052 /* 3060 */ "OpSubgroupBlockReadINTEL\000"
2053 /* 3085 */ "OpPredicatedLoadINTEL\000"
2054 /* 3107 */ "OpSubgroup2DBlockLoadINTEL\000"
2055 /* 3134 */ "OpCooperativeMatrixLoadCheckedINTEL\000"
2056 /* 3170 */ "OpCooperativeMatrixStoreCheckedINTEL\000"
2057 /* 3207 */ "OpCooperativeMatrixConstructCheckedINTEL\000"
2058 /* 3248 */ "OpSpecConstantCompositeContinuedINTEL\000"
2059 /* 3286 */ "OpConstantCompositeContinuedINTEL\000"
2060 /* 3320 */ "OpTypeStructContinuedINTEL\000"
2061 /* 3347 */ "OpCompositeConstructContinuedINTEL\000"
2062 /* 3382 */ "OpCooperativeMatrixGetElementCoordINTEL\000"
2063 /* 3422 */ "OpConvertHandleToSampledImageINTEL\000"
2064 /* 3457 */ "OpConvertHandleToImageINTEL\000"
2065 /* 3485 */ "OpSubgroupShuffleINTEL\000"
2066 /* 3508 */ "OpPredicatedStoreINTEL\000"
2067 /* 3531 */ "OpSubgroup2DBlockStoreINTEL\000"
2068 /* 3559 */ "OpSubgroup2DBlockLoadTransposeINTEL\000"
2069 /* 3595 */ "OpSubgroupMatrixMultiplyAccumulateINTEL\000"
2070 /* 3635 */ "OpSubgroupImageMediaBlockWriteINTEL\000"
2071 /* 3671 */ "OpSubgroupImageBlockWriteINTEL\000"
2072 /* 3702 */ "OpSubgroupBlockWriteINTEL\000"
2073 /* 3728 */ "OpControlBarrierArriveINTEL\000"
2074 /* 3756 */ "OpSubgroup2DBlockPrefetchINTEL\000"
2075 /* 3787 */ "OpCooperativeMatrixPrefetchINTEL\000"
2076 /* 3820 */ "OpAliasScopeDeclINTEL\000"
2077 /* 3842 */ "OpAliasDomainDeclINTEL\000"
2078 /* 3865 */ "OpAliasScopeListDeclINTEL\000"
2079 /* 3891 */ "OpAsmCallINTEL\000"
2080 /* 3906 */ "OpFunctionPointerCallINTEL\000"
2081 /* 3933 */ "OpLoopControlINTEL\000"
2082 /* 3952 */ "OpSubgroup2DBlockLoadTransformINTEL\000"
2083 /* 3988 */ "OpAsmINTEL\000"
2084 /* 3999 */ "OpBitwiseFunctionINTEL\000"
2085 /* 4022 */ "OpSubgroupShuffleDownINTEL\000"
2086 /* 4049 */ "OpSubgroupShuffleUpINTEL\000"
2087 /* 4074 */ "OpPtrCastToCrossWorkgroupINTEL\000"
2088 /* 4105 */ "OpConvertHandleToSamplerINTEL\000"
2089 /* 4135 */ "OpConstantFunctionPointerINTEL\000"
2090 /* 4166 */ "OpSubgroupShuffleXorINTEL\000"
2091 /* 4192 */ "OpCrossWorkgroupCastToPtrINTEL\000"
2092 /* 4223 */ "OpAsmTargetINTEL\000"
2093 /* 4240 */ "OpControlBarrierWaitINTEL\000"
2094 /* 4266 */ "OpVariableLengthArrayINTEL\000"
2095 /* 4293 */ "OpRestoreMemoryINTEL\000"
2096 /* 4314 */ "OpSaveMemoryINTEL\000"
2097 /* 4332 */ "G_FSHL\000"
2098 /* 4339 */ "G_SHL\000"
2099 /* 4345 */ "G_FCEIL\000"
2100 /* 4353 */ "G_SAVGCEIL\000"
2101 /* 4364 */ "G_UAVGCEIL\000"
2102 /* 4375 */ "PATCHABLE_TAIL_CALL\000"
2103 /* 4395 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2104 /* 4422 */ "PATCHABLE_EVENT_CALL\000"
2105 /* 4443 */ "FENTRY_CALL\000"
2106 /* 4455 */ "KILL\000"
2107 /* 4460 */ "G_CONSTANT_POOL\000"
2108 /* 4476 */ "G_ROTL\000"
2109 /* 4483 */ "G_VECREDUCE_FMUL\000"
2110 /* 4500 */ "G_FMUL\000"
2111 /* 4507 */ "G_VECREDUCE_SEQ_FMUL\000"
2112 /* 4528 */ "G_STRICT_FMUL\000"
2113 /* 4542 */ "G_VECREDUCE_MUL\000"
2114 /* 4558 */ "G_MUL\000"
2115 /* 4564 */ "G_FREM\000"
2116 /* 4571 */ "G_STRICT_FREM\000"
2117 /* 4585 */ "G_SREM\000"
2118 /* 4592 */ "G_UREM\000"
2119 /* 4599 */ "G_SDIVREM\000"
2120 /* 4609 */ "G_UDIVREM\000"
2121 /* 4619 */ "INLINEASM\000"
2122 /* 4629 */ "G_VECREDUCE_FMINIMUM\000"
2123 /* 4650 */ "G_FMINIMUM\000"
2124 /* 4661 */ "G_ATOMICRMW_FMINIMUM\000"
2125 /* 4682 */ "G_VECREDUCE_FMAXIMUM\000"
2126 /* 4703 */ "G_FMAXIMUM\000"
2127 /* 4714 */ "G_ATOMICRMW_FMAXIMUM\000"
2128 /* 4735 */ "G_FMINIMUMNUM\000"
2129 /* 4749 */ "G_FMAXIMUMNUM\000"
2130 /* 4763 */ "G_FMINNUM\000"
2131 /* 4773 */ "G_FMAXNUM\000"
2132 /* 4783 */ "G_FATAN\000"
2133 /* 4791 */ "G_FTAN\000"
2134 /* 4798 */ "G_INTRINSIC_ROUNDEVEN\000"
2135 /* 4820 */ "G_ASSERT_ALIGN\000"
2136 /* 4835 */ "G_FCOPYSIGN\000"
2137 /* 4847 */ "G_VECREDUCE_FMIN\000"
2138 /* 4864 */ "G_ATOMICRMW_FMIN\000"
2139 /* 4881 */ "G_VECREDUCE_SMIN\000"
2140 /* 4898 */ "G_SMIN\000"
2141 /* 4905 */ "G_VECREDUCE_UMIN\000"
2142 /* 4922 */ "G_UMIN\000"
2143 /* 4929 */ "G_ATOMICRMW_UMIN\000"
2144 /* 4946 */ "G_ATOMICRMW_MIN\000"
2145 /* 4962 */ "G_FASIN\000"
2146 /* 4970 */ "G_FSIN\000"
2147 /* 4977 */ "CFI_INSTRUCTION\000"
2148 /* 4993 */ "G_SSUBO\000"
2149 /* 5001 */ "G_USUBO\000"
2150 /* 5009 */ "G_SADDO\000"
2151 /* 5017 */ "G_UADDO\000"
2152 /* 5025 */ "JUMP_TABLE_DEBUG_INFO\000"
2153 /* 5047 */ "G_SMULO\000"
2154 /* 5055 */ "G_UMULO\000"
2155 /* 5063 */ "G_BZERO\000"
2156 /* 5071 */ "STACKMAP\000"
2157 /* 5080 */ "G_DEBUGTRAP\000"
2158 /* 5092 */ "G_UBSANTRAP\000"
2159 /* 5104 */ "G_TRAP\000"
2160 /* 5111 */ "G_ATOMICRMW_UDEC_WRAP\000"
2161 /* 5133 */ "G_ATOMICRMW_UINC_WRAP\000"
2162 /* 5155 */ "G_BSWAP\000"
2163 /* 5163 */ "G_SITOFP\000"
2164 /* 5172 */ "G_UITOFP\000"
2165 /* 5181 */ "G_FCMP\000"
2166 /* 5188 */ "G_ICMP\000"
2167 /* 5195 */ "G_SCMP\000"
2168 /* 5202 */ "G_UCMP\000"
2169 /* 5209 */ "CONVERGENCECTRL_LOOP\000"
2170 /* 5230 */ "G_CTPOP\000"
2171 /* 5238 */ "PATCHABLE_OP\000"
2172 /* 5251 */ "FAULTING_OP\000"
2173 /* 5263 */ "PREALLOCATED_SETUP\000"
2174 /* 5282 */ "G_FLDEXP\000"
2175 /* 5291 */ "G_STRICT_FLDEXP\000"
2176 /* 5307 */ "G_FEXP\000"
2177 /* 5314 */ "G_FFREXP\000"
2178 /* 5323 */ "G_BR\000"
2179 /* 5328 */ "INLINEASM_BR\000"
2180 /* 5341 */ "G_BLOCK_ADDR\000"
2181 /* 5354 */ "MEMBARRIER\000"
2182 /* 5365 */ "G_CONSTANT_FOLD_BARRIER\000"
2183 /* 5389 */ "PATCHABLE_FUNCTION_ENTER\000"
2184 /* 5414 */ "G_READCYCLECOUNTER\000"
2185 /* 5433 */ "G_READSTEADYCOUNTER\000"
2186 /* 5453 */ "G_READ_REGISTER\000"
2187 /* 5469 */ "G_WRITE_REGISTER\000"
2188 /* 5486 */ "OpFmaKHR\000"
2189 /* 5495 */ "OpCooperativeMatrixLoadKHR\000"
2190 /* 5522 */ "OpCooperativeMatrixMulAddKHR\000"
2191 /* 5551 */ "OpGroupBitwiseAndKHR\000"
2192 /* 5572 */ "OpGroupLogicalAndKHR\000"
2193 /* 5593 */ "OpCooperativeMatrixStoreKHR\000"
2194 /* 5621 */ "OpGroupNonUniformRotateKHR\000"
2195 /* 5648 */ "OpAssumeTrueKHR\000"
2196 /* 5664 */ "OpCooperativeMatrixLengthKHR\000"
2197 /* 5693 */ "OpReadClockKHR\000"
2198 /* 5708 */ "OpGroupFMulKHR\000"
2199 /* 5723 */ "OpGroupIMulKHR\000"
2200 /* 5738 */ "OpGroupBitwiseOrKHR\000"
2201 /* 5758 */ "OpGroupLogicalOrKHR\000"
2202 /* 5778 */ "OpGroupBitwiseXorKHR\000"
2203 /* 5799 */ "OpGroupLogicalXorKHR\000"
2204 /* 5820 */ "OpExpectKHR\000"
2205 /* 5832 */ "OpTypeCooperativeMatrixKHR\000"
2206 /* 5859 */ "G_ASHR\000"
2207 /* 5866 */ "G_FSHR\000"
2208 /* 5873 */ "G_LSHR\000"
2209 /* 5880 */ "CONVERGENCECTRL_ANCHOR\000"
2210 /* 5903 */ "G_FFLOOR\000"
2211 /* 5912 */ "G_SAVGFLOOR\000"
2212 /* 5924 */ "G_UAVGFLOOR\000"
2213 /* 5936 */ "G_EXTRACT_SUBVECTOR\000"
2214 /* 5956 */ "G_INSERT_SUBVECTOR\000"
2215 /* 5975 */ "G_BUILD_VECTOR\000"
2216 /* 5990 */ "G_SHUFFLE_VECTOR\000"
2217 /* 6007 */ "G_STEP_VECTOR\000"
2218 /* 6021 */ "G_SPLAT_VECTOR\000"
2219 /* 6036 */ "G_VECREDUCE_XOR\000"
2220 /* 6052 */ "G_XOR\000"
2221 /* 6058 */ "G_ATOMICRMW_XOR\000"
2222 /* 6074 */ "G_VECREDUCE_OR\000"
2223 /* 6089 */ "G_OR\000"
2224 /* 6094 */ "G_ATOMICRMW_OR\000"
2225 /* 6109 */ "G_ROTR\000"
2226 /* 6116 */ "G_INTTOPTR\000"
2227 /* 6127 */ "G_FABS\000"
2228 /* 6134 */ "G_ABS\000"
2229 /* 6140 */ "G_ABDS\000"
2230 /* 6147 */ "G_UNMERGE_VALUES\000"
2231 /* 6164 */ "G_MERGE_VALUES\000"
2232 /* 6179 */ "G_CTLS\000"
2233 /* 6186 */ "G_FACOS\000"
2234 /* 6194 */ "G_FCOS\000"
2235 /* 6201 */ "G_FSINCOS\000"
2236 /* 6211 */ "G_CONCAT_VECTORS\000"
2237 /* 6228 */ "COPY_TO_REGCLASS\000"
2238 /* 6245 */ "G_IS_FPCLASS\000"
2239 /* 6258 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2240 /* 6288 */ "G_VECTOR_COMPRESS\000"
2241 /* 6306 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2242 /* 6333 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2243 /* 6371 */ "G_TRUNC_SSAT_S\000"
2244 /* 6386 */ "OpFSubS\000"
2245 /* 6394 */ "OpStrictFSubS\000"
2246 /* 6408 */ "OpISubS\000"
2247 /* 6416 */ "OpShiftRightArithmeticS\000"
2248 /* 6440 */ "OpFAddS\000"
2249 /* 6448 */ "OpStrictFAddS\000"
2250 /* 6462 */ "OpIAddS\000"
2251 /* 6470 */ "OpBitwiseAndS\000"
2252 /* 6484 */ "OpUModS\000"
2253 /* 6492 */ "OpShiftLeftLogicalS\000"
2254 /* 6512 */ "OpShiftRightLogicalS\000"
2255 /* 6533 */ "OpFMulS\000"
2256 /* 6541 */ "OpStrictFMulS\000"
2257 /* 6555 */ "OpIMulS\000"
2258 /* 6563 */ "OpFRemS\000"
2259 /* 6571 */ "OpStrictFRemS\000"
2260 /* 6585 */ "OpSRemS\000"
2261 /* 6593 */ "OpConvertFToS\000"
2262 /* 6607 */ "OpSatConvertUToS\000"
2263 /* 6624 */ "OpBitwiseOrS\000"
2264 /* 6637 */ "OpBitwiseXorS\000"
2265 /* 6651 */ "OpFDivS\000"
2266 /* 6659 */ "OpStrictFDivS\000"
2267 /* 6673 */ "OpSDivS\000"
2268 /* 6681 */ "OpUDivS\000"
2269 /* 6689 */ "OpISubBorrowS\000"
2270 /* 6703 */ "OpIAddCarryS\000"
2271 /* 6716 */ "G_SSUBSAT\000"
2272 /* 6726 */ "G_USUBSAT\000"
2273 /* 6736 */ "G_SADDSAT\000"
2274 /* 6746 */ "G_UADDSAT\000"
2275 /* 6756 */ "G_SSHLSAT\000"
2276 /* 6766 */ "G_USHLSAT\000"
2277 /* 6776 */ "G_SMULFIXSAT\000"
2278 /* 6789 */ "G_UMULFIXSAT\000"
2279 /* 6802 */ "G_SDIVFIXSAT\000"
2280 /* 6815 */ "G_UDIVFIXSAT\000"
2281 /* 6828 */ "G_ATOMICRMW_USUB_SAT\000"
2282 /* 6849 */ "G_FPTOSI_SAT\000"
2283 /* 6862 */ "G_FPTOUI_SAT\000"
2284 /* 6875 */ "G_EXTRACT\000"
2285 /* 6885 */ "G_SELECT\000"
2286 /* 6894 */ "G_BRINDIRECT\000"
2287 /* 6907 */ "PATCHABLE_RET\000"
2288 /* 6921 */ "G_MEMSET\000"
2289 /* 6930 */ "PATCHABLE_FUNCTION_EXIT\000"
2290 /* 6954 */ "G_BRJT\000"
2291 /* 6961 */ "G_EXTRACT_VECTOR_ELT\000"
2292 /* 6982 */ "G_INSERT_VECTOR_ELT\000"
2293 /* 7002 */ "G_FCONSTANT\000"
2294 /* 7014 */ "G_CONSTANT\000"
2295 /* 7025 */ "G_INTRINSIC_CONVERGENT\000"
2296 /* 7048 */ "STATEPOINT\000"
2297 /* 7059 */ "PATCHPOINT\000"
2298 /* 7070 */ "G_PTRTOINT\000"
2299 /* 7081 */ "G_FRINT\000"
2300 /* 7089 */ "G_INTRINSIC_LLRINT\000"
2301 /* 7108 */ "G_INTRINSIC_LRINT\000"
2302 /* 7126 */ "G_FNEARBYINT\000"
2303 /* 7139 */ "G_VASTART\000"
2304 /* 7149 */ "LIFETIME_START\000"
2305 /* 7164 */ "G_INVOKE_REGION_START\000"
2306 /* 7186 */ "G_INSERT\000"
2307 /* 7195 */ "G_FSQRT\000"
2308 /* 7203 */ "G_STRICT_FSQRT\000"
2309 /* 7218 */ "G_BITCAST\000"
2310 /* 7228 */ "G_ADDRSPACE_CAST\000"
2311 /* 7245 */ "DBG_VALUE_LIST\000"
2312 /* 7260 */ "G_FPEXT\000"
2313 /* 7268 */ "G_SEXT\000"
2314 /* 7275 */ "G_ASSERT_SEXT\000"
2315 /* 7289 */ "G_ANYEXT\000"
2316 /* 7298 */ "G_ZEXT\000"
2317 /* 7305 */ "G_ASSERT_ZEXT\000"
2318 /* 7319 */ "OpAtomicFAddEXT\000"
2319 /* 7335 */ "OpArithmeticFenceEXT\000"
2320 /* 7356 */ "OpAtomicFMinEXT\000"
2321 /* 7372 */ "OpAtomicFMaxEXT\000"
2322 /* 7388 */ "G_ABDU\000"
2323 /* 7395 */ "G_TRUNC_SSAT_U\000"
2324 /* 7410 */ "G_TRUNC_USAT_U\000"
2325 /* 7425 */ "OpConvertFToU\000"
2326 /* 7439 */ "OpSatConvertSToU\000"
2327 /* 7456 */ "OpConvertPtrToU\000"
2328 /* 7472 */ "G_FDIV\000"
2329 /* 7479 */ "G_STRICT_FDIV\000"
2330 /* 7493 */ "G_SDIV\000"
2331 /* 7500 */ "G_UDIV\000"
2332 /* 7507 */ "G_GET_FPENV\000"
2333 /* 7519 */ "G_RESET_FPENV\000"
2334 /* 7533 */ "G_SET_FPENV\000"
2335 /* 7545 */ "OpTypeAccelerationStructureNV\000"
2336 /* 7575 */ "OpImageSampleFootprintNV\000"
2337 /* 7600 */ "OpTypeCooperativeMatrixNV\000"
2338 /* 7626 */ "OpFSubV\000"
2339 /* 7634 */ "OpStrictFSubV\000"
2340 /* 7648 */ "OpISubV\000"
2341 /* 7656 */ "OpShiftRightArithmeticV\000"
2342 /* 7680 */ "OpFAddV\000"
2343 /* 7688 */ "OpStrictFAddV\000"
2344 /* 7702 */ "OpIAddV\000"
2345 /* 7710 */ "OpBitwiseAndV\000"
2346 /* 7724 */ "OpUModV\000"
2347 /* 7732 */ "OpFNegateV\000"
2348 /* 7743 */ "OpShiftLeftLogicalV\000"
2349 /* 7763 */ "OpShiftRightLogicalV\000"
2350 /* 7784 */ "OpFMulV\000"
2351 /* 7792 */ "OpStrictFMulV\000"
2352 /* 7806 */ "OpIMulV\000"
2353 /* 7814 */ "OpFRemV\000"
2354 /* 7822 */ "OpStrictFRemV\000"
2355 /* 7836 */ "OpSRemV\000"
2356 /* 7844 */ "OpBitwiseOrV\000"
2357 /* 7857 */ "OpBitwiseXorV\000"
2358 /* 7871 */ "OpFDivV\000"
2359 /* 7879 */ "OpStrictFDivV\000"
2360 /* 7893 */ "OpSDivV\000"
2361 /* 7901 */ "OpUDivV\000"
2362 /* 7909 */ "OpISubBorrowV\000"
2363 /* 7923 */ "OpIAddCarryV\000"
2364 /* 7936 */ "G_FPOW\000"
2365 /* 7943 */ "G_VECREDUCE_FMAX\000"
2366 /* 7960 */ "G_ATOMICRMW_FMAX\000"
2367 /* 7977 */ "G_VECREDUCE_SMAX\000"
2368 /* 7994 */ "G_SMAX\000"
2369 /* 8001 */ "G_VECREDUCE_UMAX\000"
2370 /* 8018 */ "G_UMAX\000"
2371 /* 8025 */ "G_ATOMICRMW_UMAX\000"
2372 /* 8042 */ "G_ATOMICRMW_MAX\000"
2373 /* 8058 */ "G_FRAME_INDEX\000"
2374 /* 8072 */ "G_SBFX\000"
2375 /* 8079 */ "G_UBFX\000"
2376 /* 8086 */ "G_SMULFIX\000"
2377 /* 8096 */ "G_UMULFIX\000"
2378 /* 8106 */ "G_SDIVFIX\000"
2379 /* 8116 */ "G_UDIVFIX\000"
2380 /* 8126 */ "G_MEMCPY\000"
2381 /* 8135 */ "COPY\000"
2382 /* 8140 */ "CONVERGENCECTRL_ENTRY\000"
2383 /* 8162 */ "G_CTLZ\000"
2384 /* 8169 */ "G_CTTZ\000"
2385 /* 8176 */ "OpAtomicISub\000"
2386 /* 8189 */ "OpVectorExtractDynamic\000"
2387 /* 8212 */ "OpVectorInsertDynamic\000"
2388 /* 8234 */ "OpPtrCastToGeneric\000"
2389 /* 8253 */ "OpExecutionModeId\000"
2390 /* 8271 */ "OpDecorateId\000"
2391 /* 8284 */ "OpIsValidReserveId\000"
2392 /* 8303 */ "OpTypeReserveId\000"
2393 /* 8319 */ "OpImageRead\000"
2394 /* 8331 */ "OpImageSparseRead\000"
2395 /* 8349 */ "OpAtomicLoad\000"
2396 /* 8362 */ "OpLoad\000"
2397 /* 8369 */ "OpGroupNonUniformFAdd\000"
2398 /* 8391 */ "OpGroupFAdd\000"
2399 /* 8403 */ "OpAtomicIAdd\000"
2400 /* 8416 */ "OpGroupNonUniformIAdd\000"
2401 /* 8438 */ "OpGroupIAdd\000"
2402 /* 8450 */ "OpSMulExtended\000"
2403 /* 8465 */ "OpUMulExtended\000"
2404 /* 8480 */ "OpOrdered\000"
2405 /* 8490 */ "OpUnordered\000"
2406 /* 8502 */ "OpModuleProcessed\000"
2407 /* 8520 */ "OpSourceContinued\000"
2408 /* 8538 */ "OpCopyMemorySized\000"
2409 /* 8556 */ "OpTypeVoid\000"
2410 /* 8567 */ "OpAtomicAnd\000"
2411 /* 8579 */ "OpGroupNonUniformBitwiseAnd\000"
2412 /* 8607 */ "OpGroupNonUniformLogicalAnd\000"
2413 /* 8635 */ "OpLogicalAnd\000"
2414 /* 8648 */ "OpFunctionEnd\000"
2415 /* 8662 */ "OpSelectSFSCond\000"
2416 /* 8678 */ "OpSelectVFSCond\000"
2417 /* 8694 */ "OpSelectSISCond\000"
2418 /* 8710 */ "OpSelectVISCond\000"
2419 /* 8726 */ "OpSelectSPSCond\000"
2420 /* 8742 */ "OpSelectVPSCond\000"
2421 /* 8758 */ "OpSelectSFVCond\000"
2422 /* 8774 */ "OpSelectVFVCond\000"
2423 /* 8790 */ "OpSelectSIVCond\000"
2424 /* 8806 */ "OpSelectVIVCond\000"
2425 /* 8822 */ "OpSelectSPVCond\000"
2426 /* 8838 */ "OpSelectVPVCond\000"
2427 /* 8854 */ "OpImageQuerySizeLod\000"
2428 /* 8874 */ "OpImageSampleImplicitLod\000"
2429 /* 8899 */ "OpImageSparseSampleImplicitLod\000"
2430 /* 8930 */ "OpImageSampleDrefImplicitLod\000"
2431 /* 8959 */ "OpImageSparseSampleDrefImplicitLod\000"
2432 /* 8994 */ "OpImageSampleProjDrefImplicitLod\000"
2433 /* 9027 */ "OpImageSparseSampleProjDrefImplicitLod\000"
2434 /* 9066 */ "OpImageSampleProjImplicitLod\000"
2435 /* 9095 */ "OpImageSparseSampleProjImplicitLod\000"
2436 /* 9130 */ "OpImageSampleExplicitLod\000"
2437 /* 9155 */ "OpImageSparseSampleExplicitLod\000"
2438 /* 9186 */ "OpImageSampleDrefExplicitLod\000"
2439 /* 9215 */ "OpImageSparseSampleDrefExplicitLod\000"
2440 /* 9250 */ "OpImageSampleProjDrefExplicitLod\000"
2441 /* 9283 */ "OpImageSparseSampleProjDrefExplicitLod\000"
2442 /* 9322 */ "OpImageSampleProjExplicitLod\000"
2443 /* 9351 */ "OpImageSparseSampleProjExplicitLod\000"
2444 /* 9386 */ "OpImageQueryLod\000"
2445 /* 9402 */ "OpFMod\000"
2446 /* 9409 */ "OpSMod\000"
2447 /* 9416 */ "OpSource\000"
2448 /* 9425 */ "OpExecutionMode\000"
2449 /* 9441 */ "OpTypeSampledImage\000"
2450 /* 9460 */ "OpSampledImage\000"
2451 /* 9475 */ "OpTypeImage\000"
2452 /* 9487 */ "OpImage\000"
2453 /* 9495 */ "OpTypePipeStorage\000"
2454 /* 9513 */ "OpBuildNDRange\000"
2455 /* 9528 */ "OpAtomicExchange\000"
2456 /* 9545 */ "OpAtomicCompareExchange\000"
2457 /* 9569 */ "OpSelectionMerge\000"
2458 /* 9586 */ "OpLoopMerge\000"
2459 /* 9598 */ "OpUnreachable\000"
2460 /* 9612 */ "OpVariable\000"
2461 /* 9623 */ "OpGroupNonUniformShuffle\000"
2462 /* 9648 */ "OpVectorShuffle\000"
2463 /* 9664 */ "OpName\000"
2464 /* 9671 */ "OpMemberName\000"
2465 /* 9684 */ "OpFwidthFine\000"
2466 /* 9697 */ "OpDPdxFine\000"
2467 /* 9708 */ "OpDPdyFine\000"
2468 /* 9719 */ "OpNoLine\000"
2469 /* 9728 */ "OpLine\000"
2470 /* 9735 */ "OpReservedReadPipe\000"
2471 /* 9754 */ "OpReadPipe\000"
2472 /* 9765 */ "OpCommitReadPipe\000"
2473 /* 9782 */ "OpGroupCommitReadPipe\000"
2474 /* 9804 */ "OpTypePipe\000"
2475 /* 9815 */ "OpReservedWritePipe\000"
2476 /* 9835 */ "OpWritePipe\000"
2477 /* 9847 */ "OpCommitWritePipe\000"
2478 /* 9865 */ "OpGroupCommitWritePipe\000"
2479 /* 9888 */ "UNKNOWN_type\000"
2480 /* 9901 */ "OpAtomicStore\000"
2481 /* 9915 */ "OpStore\000"
2482 /* 9923 */ "OpSpecConstantFalse\000"
2483 /* 9943 */ "OpConstantFalse\000"
2484 /* 9959 */ "OpTranspose\000"
2485 /* 9971 */ "OpFwidthCoarse\000"
2486 /* 9986 */ "OpDPdxCoarse\000"
2487 /* 9999 */ "OpDPdyCoarse\000"
2488 /* 10012 */ "OpBitReverse\000"
2489 /* 10025 */ "OpFNegate\000"
2490 /* 10035 */ "OpSNegate\000"
2491 /* 10045 */ "OpDecorate\000"
2492 /* 10056 */ "OpMemberDecorate\000"
2493 /* 10073 */ "OpIsFinite\000"
2494 /* 10084 */ "OpImageWrite\000"
2495 /* 10097 */ "OpSpecConstantComposite\000"
2496 /* 10121 */ "OpConstantComposite\000"
2497 /* 10141 */ "OpTypeQueue\000"
2498 /* 10153 */ "OpGetDefaultQueue\000"
2499 /* 10171 */ "OpReturnValue\000"
2500 /* 10185 */ "OpTypeOpaque\000"
2501 /* 10198 */ "OpSpecConstantTrue\000"
2502 /* 10217 */ "OpConstantTrue\000"
2503 /* 10232 */ "OpEndPrimitive\000"
2504 /* 10247 */ "OpEndStreamPrimitive\000"
2505 /* 10268 */ "OpImageQuerySize\000"
2506 /* 10285 */ "OpNamedBarrierInitialize\000"
2507 /* 10310 */ "OpSizeOf\000"
2508 /* 10319 */ "OpUndef\000"
2509 /* 10327 */ "OpPtrDiff\000"
2510 /* 10337 */ "OpIsInf\000"
2511 /* 10345 */ "OpDecorateString\000"
2512 /* 10362 */ "OpMemberDecorateString\000"
2513 /* 10385 */ "OpString\000"
2514 /* 10394 */ "OpBranch\000"
2515 /* 10403 */ "OpImageFetch\000"
2516 /* 10416 */ "OpImageSparseFetch\000"
2517 /* 10435 */ "OpSwitch\000"
2518 /* 10444 */ "OpFwidth\000"
2519 /* 10453 */ "OpArrayLength\000"
2520 /* 10467 */ "OpPhi\000"
2521 /* 10473 */ "OpAtomicCompareExchangeWeak\000"
2522 /* 10501 */ "OpCopyLogical\000"
2523 /* 10515 */ "OpIsNormal\000"
2524 /* 10526 */ "OpBranchConditional\000"
2525 /* 10546 */ "OpIEqual\000"
2526 /* 10555 */ "OpFOrdEqual\000"
2527 /* 10567 */ "OpFUnordEqual\000"
2528 /* 10581 */ "OpLogicalEqual\000"
2529 /* 10596 */ "OpGroupNonUniformAllEqual\000"
2530 /* 10622 */ "OpSGreaterThanEqual\000"
2531 /* 10642 */ "OpUGreaterThanEqual\000"
2532 /* 10662 */ "OpFOrdGreaterThanEqual\000"
2533 /* 10685 */ "OpFUnordGreaterThanEqual\000"
2534 /* 10710 */ "OpSLessThanEqual\000"
2535 /* 10727 */ "OpULessThanEqual\000"
2536 /* 10744 */ "OpFOrdLessThanEqual\000"
2537 /* 10764 */ "OpFUnordLessThanEqual\000"
2538 /* 10786 */ "OpPtrEqual\000"
2539 /* 10797 */ "OpINotEqual\000"
2540 /* 10809 */ "OpFOrdNotEqual\000"
2541 /* 10824 */ "OpFUnordNotEqual\000"
2542 /* 10841 */ "OpLogicalNotEqual\000"
2543 /* 10859 */ "OpPtrNotEqual\000"
2544 /* 10873 */ "OpLabel\000"
2545 /* 10881 */ "OpMemoryModel\000"
2546 /* 10895 */ "OpEnqueueKernel\000"
2547 /* 10911 */ "OpGroupNonUniformAll\000"
2548 /* 10932 */ "OpAll\000"
2549 /* 10938 */ "OpGroupAll\000"
2550 /* 10949 */ "OpFunctionCall\000"
2551 /* 10964 */ "OpKill\000"
2552 /* 10971 */ "OpConstantNull\000"
2553 /* 10986 */ "OpTypeBool\000"
2554 /* 10997 */ "OpGroupNonUniformFMul\000"
2555 /* 11019 */ "OpGroupNonUniformIMul\000"
2556 /* 11041 */ "OpIsNan\000"
2557 /* 11049 */ "OpSGreaterThan\000"
2558 /* 11064 */ "OpUGreaterThan\000"
2559 /* 11079 */ "OpFOrdGreaterThan\000"
2560 /* 11097 */ "OpFUnordGreaterThan\000"
2561 /* 11117 */ "OpSLessThan\000"
2562 /* 11129 */ "OpULessThan\000"
2563 /* 11141 */ "OpFOrdLessThan\000"
2564 /* 11156 */ "OpFUnordLessThan\000"
2565 /* 11173 */ "OpGroupNonUniformFMin\000"
2566 /* 11195 */ "OpGroupFMin\000"
2567 /* 11207 */ "OpAtomicSMin\000"
2568 /* 11220 */ "OpGroupNonUniformSMin\000"
2569 /* 11242 */ "OpGroupSMin\000"
2570 /* 11254 */ "OpAtomicUMin\000"
2571 /* 11267 */ "OpGroupNonUniformUMin\000"
2572 /* 11289 */ "OpGroupUMin\000"
2573 /* 11301 */ "OpAccessChain\000"
2574 /* 11315 */ "OpPtrAccessChain\000"
2575 /* 11332 */ "OpInBoundsPtrAccessChain\000"
2576 /* 11357 */ "OpInBoundsAccessChain\000"
2577 /* 11379 */ "OpSourceExtension\000"
2578 /* 11397 */ "OpExtension\000"
2579 /* 11409 */ "OpDemoteToHelperInvocation\000"
2580 /* 11436 */ "OpTypeFunction\000"
2581 /* 11451 */ "OpFunction\000"
2582 /* 11462 */ "OpReturn\000"
2583 /* 11471 */ "OpGroupNonUniformShuffleDown\000"
2584 /* 11500 */ "OpCaptureEventProfilingInfo\000"
2585 /* 11528 */ "OpSpecConstantOp\000"
2586 /* 11545 */ "OpGroupNonUniformShuffleUp\000"
2587 /* 11572 */ "OpNop\000"
2588 /* 11578 */ "OpLifetimeStop\000"
2589 /* 11593 */ "OpAtomicOr\000"
2590 /* 11604 */ "OpGroupNonUniformBitwiseOr\000"
2591 /* 11631 */ "OpGroupNonUniformLogicalOr\000"
2592 /* 11658 */ "OpLogicalOr\000"
2593 /* 11670 */ "OpAtomicFlagClear\000"
2594 /* 11688 */ "OpVectorTimesScalar\000"
2595 /* 11708 */ "OpMatrixTimesScalar\000"
2596 /* 11728 */ "OpImageQueryOrder\000"
2597 /* 11746 */ "OpImageGather\000"
2598 /* 11760 */ "OpImageSparseGather\000"
2599 /* 11780 */ "OpImageDrefGather\000"
2600 /* 11798 */ "OpImageSparseDrefGather\000"
2601 /* 11822 */ "OpTypeNamedBarrier\000"
2602 /* 11841 */ "OpMemoryNamedBarrier\000"
2603 /* 11862 */ "OpControlBarrier\000"
2604 /* 11879 */ "OpMemoryBarrier\000"
2605 /* 11895 */ "OpTypeSampler\000"
2606 /* 11909 */ "OpConstantSampler\000"
2607 /* 11927 */ "OpLessOrGreater\000"
2608 /* 11943 */ "OpFunctionParameter\000"
2609 /* 11963 */ "OpTypeForwardPointer\000"
2610 /* 11984 */ "OpTypePointer\000"
2611 /* 11998 */ "OpImageTexelPointer\000"
2612 /* 12018 */ "OpAtomicXor\000"
2613 /* 12030 */ "OpGroupNonUniformShuffleXor\000"
2614 /* 12058 */ "OpGroupNonUniformBitwiseXor\000"
2615 /* 12086 */ "OpGroupNonUniformLogicalXor\000"
2616 /* 12114 */ "OpTypeVector\000"
2617 /* 12127 */ "OpMatrixTimesVector\000"
2618 /* 12147 */ "OpConvertUToPtr\000"
2619 /* 12163 */ "OpGenericCastToPtr\000"
2620 /* 12182 */ "OpGenericPtrMemSemantics\000"
2621 /* 12207 */ "OpImageQuerySamples\000"
2622 /* 12227 */ "OpImageQueryLevels\000"
2623 /* 12246 */ "OpReserveReadPipePackets\000"
2624 /* 12271 */ "OpGroupReserveReadPipePackets\000"
2625 /* 12301 */ "OpReserveWritePipePackets\000"
2626 /* 12327 */ "OpGroupReserveWritePipePackets\000"
2627 /* 12358 */ "OpGetNumPipePackets\000"
2628 /* 12378 */ "OpGetMaxPipePackets\000"
2629 /* 12398 */ "OpGroupWaitEvents\000"
2630 /* 12416 */ "OpSetUserEventStatus\000"
2631 /* 12437 */ "OpSDotAccSat\000"
2632 /* 12450 */ "OpSUDotAccSat\000"
2633 /* 12464 */ "OpUDotAccSat\000"
2634 /* 12477 */ "OpImageQueryFormat\000"
2635 /* 12496 */ "OpTypeFloat\000"
2636 /* 12508 */ "OpBitFieldSExtract\000"
2637 /* 12527 */ "OpBitFieldUExtract\000"
2638 /* 12546 */ "OpCompositeExtract\000"
2639 /* 12565 */ "OpGroupNonUniformBallotBitExtract\000"
2640 /* 12599 */ "OpCopyObject\000"
2641 /* 12612 */ "OpGroupNonUniformElect\000"
2642 /* 12635 */ "OpOuterProduct\000"
2643 /* 12650 */ "OpTypeStruct\000"
2644 /* 12663 */ "OpCompositeConstruct\000"
2645 /* 12684 */ "OpAtomicFlagTestAndSet\000"
2646 /* 12707 */ "OpSignBitSet\000"
2647 /* 12720 */ "OpGenericCastToPtrExplicit\000"
2648 /* 12747 */ "OpTypeInt\000"
2649 /* 12757 */ "OpSpecConstant\000"
2650 /* 12772 */ "OpImageSparseTexelsResident\000"
2651 /* 12800 */ "OpAtomicIDecrement\000"
2652 /* 12819 */ "OpAtomicIIncrement\000"
2653 /* 12838 */ "OpIsValidEvent\000"
2654 /* 12853 */ "OpTypeDeviceEvent\000"
2655 /* 12871 */ "OpTypeEvent\000"
2656 /* 12883 */ "OpReleaseEvent\000"
2657 /* 12898 */ "OpRetainEvent\000"
2658 /* 12912 */ "OpCreateUserEvent\000"
2659 /* 12930 */ "OpEntryPoint\000"
2660 /* 12943 */ "OpBitCount\000"
2661 /* 12954 */ "OpGroupNonUniformBallotBitCount\000"
2662 /* 12986 */ "OpSDot\000"
2663 /* 12993 */ "OpSUDot\000"
2664 /* 13001 */ "OpUDot\000"
2665 /* 13008 */ "OpDot\000"
2666 /* 13014 */ "OpLogicalNot\000"
2667 /* 13027 */ "OpNot\000"
2668 /* 13033 */ "OpGroupNonUniformInverseBallot\000"
2669 /* 13064 */ "OpGroupNonUniformBallot\000"
2670 /* 13088 */ "OpLifetimeStart\000"
2671 /* 13104 */ "OpBitFieldInsert\000"
2672 /* 13121 */ "OpCompositeInsert\000"
2673 /* 13139 */ "OpFConvert\000"
2674 /* 13150 */ "OpSConvert\000"
2675 /* 13161 */ "OpUConvert\000"
2676 /* 13172 */ "OpExtInstImport\000"
2677 /* 13188 */ "OpGroupNonUniformBroadcast\000"
2678 /* 13215 */ "OpGroupBroadcast\000"
2679 /* 13232 */ "OpBitcast\000"
2680 /* 13242 */ "OpExtInst\000"
2681 /* 13252 */ "OpGroupNonUniformBroadcastFirst\000"
2682 /* 13284 */ "OpGroupNonUniformFMax\000"
2683 /* 13306 */ "OpGroupFMax\000"
2684 /* 13318 */ "OpAtomicSMax\000"
2685 /* 13331 */ "OpGroupNonUniformSMax\000"
2686 /* 13353 */ "OpGroupSMax\000"
2687 /* 13365 */ "OpAtomicUMax\000"
2688 /* 13378 */ "OpGroupNonUniformUMax\000"
2689 /* 13400 */ "OpGroupUMax\000"
2690 /* 13412 */ "OpDPdx\000"
2691 /* 13419 */ "OpEmitStreamVertex\000"
2692 /* 13438 */ "OpEmitVertex\000"
2693 /* 13451 */ "OpTypeMatrix\000"
2694 /* 13464 */ "OpVectorTimesMatrix\000"
2695 /* 13484 */ "OpMatrixTimesMatrix\000"
2696 /* 13504 */ "OpTypeRuntimeArray\000"
2697 /* 13523 */ "OpTypeArray\000"
2698 /* 13535 */ "OpDPdy\000"
2699 /* 13542 */ "OpGroupNonUniformAny\000"
2700 /* 13563 */ "OpAny\000"
2701 /* 13569 */ "OpGroupAny\000"
2702 /* 13580 */ "OpGroupAsyncCopy\000"
2703 /* 13597 */ "OpCopyMemory\000"
2704 /* 13610 */ "OpCapability\000"
2705};
2706#ifdef __GNUC__
2707#pragma GCC diagnostic pop
2708#endif
2709
2710extern const unsigned SPIRVInstrNameIndices[] = {
2711 2800U, 4619U, 5328U, 4977U, 2885U, 2866U, 2894U, 4455U,
2712 2593U, 2608U, 2519U, 2506U, 2635U, 6228U, 2346U, 7245U,
2713 2532U, 2796U, 2875U, 2104U, 8135U, 2842U, 2226U, 7149U,
2714 1931U, 2055U, 2092U, 5071U, 4443U, 7059U, 2038U, 5263U,
2715 2728U, 7048U, 2260U, 5251U, 5238U, 5389U, 6907U, 6930U,
2716 4375U, 4422U, 4395U, 2911U, 2337U, 5354U, 5025U, 2249U,
2717 8140U, 5880U, 5209U, 2394U, 7275U, 7305U, 4820U, 1844U,
2718 1555U, 4558U, 7493U, 7500U, 4585U, 4592U, 4599U, 4609U,
2719 1909U, 6089U, 6052U, 6140U, 7388U, 5924U, 4364U, 5912U,
2720 4353U, 2517U, 2798U, 8058U, 2356U, 2371U, 4460U, 6875U,
2721 6147U, 7186U, 6164U, 5975U, 1625U, 6211U, 7070U, 6116U,
2722 7218U, 2437U, 5365U, 2012U, 1599U, 1994U, 7108U, 7089U,
2723 4798U, 5414U, 5433U, 1745U, 1689U, 1719U, 1730U, 1670U,
2724 1700U, 2316U, 2300U, 6258U, 2649U, 2666U, 1860U, 1561U,
2725 1915U, 1876U, 6094U, 6058U, 8042U, 4946U, 8025U, 4929U,
2726 1811U, 1538U, 7960U, 4864U, 4714U, 4661U, 5133U, 5111U,
2727 1953U, 6828U, 2084U, 2745U, 1944U, 6894U, 7164U, 1577U,
2728 6306U, 7025U, 6333U, 7289U, 1617U, 6371U, 7395U, 7410U,
2729 7014U, 7002U, 7139U, 2720U, 7268U, 2622U, 7298U, 4339U,
2730 5873U, 5859U, 4332U, 5866U, 6109U, 4476U, 5188U, 5181U,
2731 5195U, 5202U, 6885U, 5017U, 2125U, 5001U, 2076U, 5009U,
2732 2117U, 4993U, 2068U, 5055U, 5047U, 2764U, 2756U, 6746U,
2733 6736U, 6726U, 6716U, 6766U, 6756U, 8086U, 8096U, 6776U,
2734 6789U, 8106U, 8116U, 6802U, 6815U, 1769U, 1517U, 4500U,
2735 59U, 1663U, 7472U, 4564U, 2462U, 7936U, 2822U, 5307U,
2736 35U, 9U, 2713U, 18U, 0U, 5282U, 5314U, 2586U,
2737 7260U, 1589U, 2804U, 2813U, 5163U, 5172U, 6849U, 6862U,
2738 6127U, 4835U, 6245U, 2446U, 4763U, 4773U, 2174U, 2189U,
2739 4650U, 4703U, 4735U, 4749U, 7507U, 7533U, 7519U, 2133U,
2740 2161U, 2146U, 2683U, 2698U, 1850U, 2856U, 4898U, 7994U,
2741 4922U, 8018U, 6134U, 1985U, 1975U, 5323U, 6954U, 2204U,
2742 5956U, 5936U, 6982U, 6961U, 5990U, 6021U, 6007U, 6288U,
2743 8169U, 2488U, 8162U, 2470U, 6179U, 5230U, 5155U, 2324U,
2744 4345U, 6194U, 4970U, 6201U, 4791U, 6186U, 4962U, 4783U,
2745 26U, 2788U, 2780U, 2772U, 7195U, 5903U, 7081U, 7126U,
2746 7228U, 5341U, 2213U, 1646U, 2415U, 2285U, 1797U, 1524U,
2747 4528U, 7479U, 4571U, 65U, 7203U, 5291U, 5453U, 5469U,
2748 8126U, 2233U, 2427U, 6921U, 5063U, 5104U, 5080U, 5092U,
2749 1776U, 4507U, 1752U, 4483U, 7943U, 4847U, 4682U, 4629U,
2750 1828U, 4542U, 1893U, 6074U, 6036U, 7977U, 4881U, 8001U,
2751 4905U, 8072U, 8079U, 2273U, 9888U, 11301U, 3842U, 3820U,
2752 3865U, 10932U, 13563U, 1044U, 674U, 856U, 598U, 189U,
2753 829U, 569U, 449U, 1376U, 1163U, 1197U, 1257U, 1137U,
2754 775U, 1403U, 321U, 106U, 217U, 1018U, 134U, 244U,
2755 373U, 1229U, 269U, 398U, 78U, 926U, 162U, 543U,
2756 803U, 1429U, 294U, 346U, 1284U, 973U, 900U, 1108U,
2757 744U, 646U, 1330U, 423U, 7335U, 10453U, 3891U, 3988U,
2758 4223U, 5648U, 8567U, 9545U, 10473U, 9528U, 7319U, 7372U,
2759 7356U, 11670U, 12684U, 8403U, 12800U, 12819U, 8176U, 8349U,
2760 11593U, 13318U, 11207U, 9901U, 13365U, 11254U, 12018U, 12943U,
2761 13104U, 12508U, 12527U, 10012U, 13232U, 6470U, 7710U, 3999U,
2762 6624U, 7844U, 6637U, 7857U, 10394U, 10526U, 9513U, 13610U,
2763 11500U, 9765U, 9847U, 12663U, 3347U, 12546U, 13121U, 10121U,
2764 3286U, 2574U, 9943U, 4135U, 2830U, 10971U, 11909U, 10217U,
2765 11862U, 3728U, 4240U, 2973U, 2951U, 6593U, 7425U, 3457U,
2766 3422U, 4105U, 7456U, 2546U, 2560U, 12147U, 3207U, 3382U,
2767 5664U, 3134U, 5495U, 5522U, 3787U, 3170U, 5593U, 10501U,
2768 13597U, 8538U, 12599U, 12912U, 4192U, 13412U, 9986U, 9697U,
2769 13535U, 9999U, 9708U, 10045U, 8271U, 10345U, 11409U, 13008U,
2770 13419U, 13438U, 10232U, 10247U, 10895U, 12930U, 9425U, 8253U,
2771 5820U, 13242U, 13172U, 11397U, 6440U, 7680U, 13139U, 6651U,
2772 7871U, 9402U, 6533U, 7784U, 10025U, 7732U, 10555U, 11079U,
2773 10662U, 11141U, 10744U, 10809U, 6563U, 7814U, 6386U, 7626U,
2774 10567U, 11097U, 10685U, 11156U, 10764U, 10824U, 1071U, 703U,
2775 1001U, 526U, 954U, 1357U, 883U, 1088U, 722U, 627U,
2776 1312U, 5486U, 11451U, 10949U, 8648U, 11943U, 3906U, 10444U,
2777 9971U, 9684U, 12163U, 12720U, 12182U, 10153U, 12378U, 12358U,
2778 10938U, 13569U, 13580U, 5551U, 5738U, 5778U, 13215U, 9782U,
2779 9865U, 8391U, 13306U, 11195U, 5708U, 8438U, 5723U, 5572U,
2780 5758U, 5799U, 10911U, 10596U, 13542U, 13064U, 12954U, 12565U,
2781 1455U, 1486U, 8579U, 11604U, 12058U, 13188U, 13252U, 12612U,
2782 8369U, 13284U, 11173U, 10997U, 8416U, 11019U, 13033U, 8607U,
2783 11631U, 12086U, 5621U, 13331U, 11220U, 9623U, 11471U, 11545U,
2784 12030U, 13378U, 11267U, 12271U, 12327U, 13353U, 11242U, 13400U,
2785 11289U, 12398U, 6703U, 7923U, 6462U, 7702U, 10546U, 6555U,
2786 7806U, 10797U, 6689U, 7909U, 6408U, 7648U, 9487U, 11780U,
2787 10403U, 11746U, 12477U, 12227U, 9386U, 11728U, 12207U, 10268U,
2788 8854U, 8319U, 9186U, 8930U, 9130U, 7575U, 8874U, 9250U,
2789 8994U, 9322U, 9066U, 11798U, 10416U, 11760U, 8331U, 9215U,
2790 8959U, 9155U, 8899U, 9283U, 9027U, 9351U, 9095U, 12772U,
2791 11998U, 10084U, 11357U, 11332U, 10073U, 10337U, 11041U, 10515U,
2792 12838U, 8284U, 10964U, 10873U, 11927U, 13088U, 11578U, 9728U,
2793 8362U, 8635U, 10581U, 13014U, 10841U, 11658U, 3933U, 9586U,
2794 13484U, 11708U, 12127U, 10056U, 10362U, 9671U, 11879U, 10881U,
2795 11841U, 8502U, 9664U, 10285U, 9719U, 11572U, 13027U, 8480U,
2796 12635U, 10467U, 3085U, 3508U, 11315U, 4074U, 8234U, 10327U,
2797 10786U, 10859U, 43U, 5693U, 9754U, 475U, 12883U, 12246U,
2798 12301U, 9735U, 9815U, 4293U, 12898U, 11462U, 10171U, 2931U,
2799 13150U, 6673U, 7893U, 12986U, 12437U, 11049U, 10622U, 11117U,
2800 10710U, 9409U, 8450U, 10035U, 6585U, 7836U, 12993U, 12450U,
2801 9460U, 7439U, 6607U, 4314U, 8662U, 8758U, 8694U, 8790U,
2802 8726U, 8822U, 8678U, 8774U, 8710U, 8806U, 8742U, 8838U,
2803 9569U, 12416U, 6492U, 7743U, 6416U, 7656U, 6512U, 7763U,
2804 12707U, 10310U, 9416U, 8520U, 11379U, 12757U, 10097U, 3248U,
2805 9923U, 11528U, 10198U, 9915U, 6448U, 7688U, 6659U, 7879U,
2806 6541U, 7792U, 6571U, 7822U, 6394U, 7634U, 10385U, 3107U,
2807 3952U, 3559U, 3756U, 3531U, 3060U, 3702U, 3030U, 3671U,
2808 2995U, 3635U, 3595U, 4022U, 3485U, 4049U, 4166U, 10435U,
2809 9959U, 7545U, 13523U, 10986U, 5832U, 7600U, 12853U, 12871U,
2810 12496U, 11963U, 11436U, 9475U, 12747U, 13451U, 11822U, 10185U,
2811 9804U, 9495U, 11984U, 10141U, 8303U, 13504U, 9441U, 11895U,
2812 12650U, 3320U, 12114U, 8556U, 13161U, 6681U, 7901U, 13001U,
2813 12464U, 11064U, 10642U, 11129U, 10727U, 6484U, 7724U, 8465U,
2814 10319U, 8490U, 9598U, 9612U, 4266U, 8189U, 8212U, 9648U,
2815 13464U, 11688U, 9835U, 500U,
2816};
2817
2818static inline void InitSPIRVMCInstrInfo(MCInstrInfo *II) {
2819 II->InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 836, nullptr, 0);
2820}
2821
2822
2823} // namespace llvm
2824
2825#endif // GET_INSTRINFO_MC_DESC
2826
2827#ifdef GET_INSTRINFO_HEADER
2828#undef GET_INSTRINFO_HEADER
2829
2830namespace llvm {
2831
2832struct SPIRVGenInstrInfo : public TargetInstrInfo {
2833 explicit SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2834 ~SPIRVGenInstrInfo() override = default;
2835};
2836
2837} // namespace llvm
2838
2839namespace llvm::SPIRV {
2840
2841
2842} // namespace llvm::SPIRV
2843
2844#endif // GET_INSTRINFO_HEADER
2845
2846#ifdef GET_INSTRINFO_HELPER_DECLS
2847#undef GET_INSTRINFO_HELPER_DECLS
2848
2849
2850#endif // GET_INSTRINFO_HELPER_DECLS
2851
2852#ifdef GET_INSTRINFO_HELPERS
2853#undef GET_INSTRINFO_HELPERS
2854
2855
2856#endif // GET_INSTRINFO_HELPERS
2857
2858#ifdef GET_INSTRINFO_CTOR_DTOR
2859#undef GET_INSTRINFO_CTOR_DTOR
2860
2861namespace llvm {
2862
2863extern const SPIRVInstrTable SPIRVDescs;
2864extern const unsigned SPIRVInstrNameIndices[];
2865extern const char SPIRVInstrNameData[];
2866SPIRVGenInstrInfo::SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2867 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2868 InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 836);
2869}
2870
2871} // namespace llvm
2872
2873#endif // GET_INSTRINFO_CTOR_DTOR
2874
2875#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2876#undef GET_INSTRINFO_MC_HELPER_DECLS
2877
2878namespace llvm {
2879
2880class MCInst;
2881class FeatureBitset;
2882
2883namespace SPIRV_MC {
2884
2885void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2886
2887} // namespace SPIRV_MC
2888
2889} // namespace llvm
2890
2891#endif // GET_INSTRINFO_MC_HELPER_DECLS
2892
2893#ifdef GET_INSTRINFO_MC_HELPERS
2894#undef GET_INSTRINFO_MC_HELPERS
2895
2896namespace llvm::SPIRV_MC {
2897
2898
2899} // namespace llvm::SPIRV_MC
2900
2901#endif // GET_INSTRINFO_MC_HELPERS
2902
2903#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2904 defined(GET_AVAILABLE_OPCODE_CHECKER)
2905#define GET_COMPUTE_FEATURES
2906#endif
2907#ifdef GET_COMPUTE_FEATURES
2908#undef GET_COMPUTE_FEATURES
2909
2910namespace llvm::SPIRV_MC {
2911
2912// Bits for subtarget features that participate in instruction matching.
2913enum SubtargetFeatureBits : uint8_t {
2914};
2915
2916inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2917 FeatureBitset Features;
2918 return Features;
2919}
2920
2921inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2922 enum : uint8_t {
2923 CEFBS_None,
2924 };
2925
2926 static constexpr FeatureBitset FeatureBitsets[] = {
2927 {}, // CEFBS_None
2928 };
2929 static constexpr uint8_t RequiredFeaturesRefs[] = {
2930 CEFBS_None, // PHI
2931 CEFBS_None, // INLINEASM
2932 CEFBS_None, // INLINEASM_BR
2933 CEFBS_None, // CFI_INSTRUCTION
2934 CEFBS_None, // EH_LABEL
2935 CEFBS_None, // GC_LABEL
2936 CEFBS_None, // ANNOTATION_LABEL
2937 CEFBS_None, // KILL
2938 CEFBS_None, // EXTRACT_SUBREG
2939 CEFBS_None, // INSERT_SUBREG
2940 CEFBS_None, // IMPLICIT_DEF
2941 CEFBS_None, // INIT_UNDEF
2942 CEFBS_None, // SUBREG_TO_REG
2943 CEFBS_None, // COPY_TO_REGCLASS
2944 CEFBS_None, // DBG_VALUE
2945 CEFBS_None, // DBG_VALUE_LIST
2946 CEFBS_None, // DBG_INSTR_REF
2947 CEFBS_None, // DBG_PHI
2948 CEFBS_None, // DBG_LABEL
2949 CEFBS_None, // REG_SEQUENCE
2950 CEFBS_None, // COPY
2951 CEFBS_None, // COPY_LANEMASK
2952 CEFBS_None, // BUNDLE
2953 CEFBS_None, // LIFETIME_START
2954 CEFBS_None, // LIFETIME_END
2955 CEFBS_None, // PSEUDO_PROBE
2956 CEFBS_None, // ARITH_FENCE
2957 CEFBS_None, // STACKMAP
2958 CEFBS_None, // FENTRY_CALL
2959 CEFBS_None, // PATCHPOINT
2960 CEFBS_None, // LOAD_STACK_GUARD
2961 CEFBS_None, // PREALLOCATED_SETUP
2962 CEFBS_None, // PREALLOCATED_ARG
2963 CEFBS_None, // STATEPOINT
2964 CEFBS_None, // LOCAL_ESCAPE
2965 CEFBS_None, // FAULTING_OP
2966 CEFBS_None, // PATCHABLE_OP
2967 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2968 CEFBS_None, // PATCHABLE_RET
2969 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2970 CEFBS_None, // PATCHABLE_TAIL_CALL
2971 CEFBS_None, // PATCHABLE_EVENT_CALL
2972 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2973 CEFBS_None, // ICALL_BRANCH_FUNNEL
2974 CEFBS_None, // FAKE_USE
2975 CEFBS_None, // MEMBARRIER
2976 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2977 CEFBS_None, // RELOC_NONE
2978 CEFBS_None, // CONVERGENCECTRL_ENTRY
2979 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2980 CEFBS_None, // CONVERGENCECTRL_LOOP
2981 CEFBS_None, // CONVERGENCECTRL_GLUE
2982 CEFBS_None, // G_ASSERT_SEXT
2983 CEFBS_None, // G_ASSERT_ZEXT
2984 CEFBS_None, // G_ASSERT_ALIGN
2985 CEFBS_None, // G_ADD
2986 CEFBS_None, // G_SUB
2987 CEFBS_None, // G_MUL
2988 CEFBS_None, // G_SDIV
2989 CEFBS_None, // G_UDIV
2990 CEFBS_None, // G_SREM
2991 CEFBS_None, // G_UREM
2992 CEFBS_None, // G_SDIVREM
2993 CEFBS_None, // G_UDIVREM
2994 CEFBS_None, // G_AND
2995 CEFBS_None, // G_OR
2996 CEFBS_None, // G_XOR
2997 CEFBS_None, // G_ABDS
2998 CEFBS_None, // G_ABDU
2999 CEFBS_None, // G_UAVGFLOOR
3000 CEFBS_None, // G_UAVGCEIL
3001 CEFBS_None, // G_SAVGFLOOR
3002 CEFBS_None, // G_SAVGCEIL
3003 CEFBS_None, // G_IMPLICIT_DEF
3004 CEFBS_None, // G_PHI
3005 CEFBS_None, // G_FRAME_INDEX
3006 CEFBS_None, // G_GLOBAL_VALUE
3007 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3008 CEFBS_None, // G_CONSTANT_POOL
3009 CEFBS_None, // G_EXTRACT
3010 CEFBS_None, // G_UNMERGE_VALUES
3011 CEFBS_None, // G_INSERT
3012 CEFBS_None, // G_MERGE_VALUES
3013 CEFBS_None, // G_BUILD_VECTOR
3014 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3015 CEFBS_None, // G_CONCAT_VECTORS
3016 CEFBS_None, // G_PTRTOINT
3017 CEFBS_None, // G_INTTOPTR
3018 CEFBS_None, // G_BITCAST
3019 CEFBS_None, // G_FREEZE
3020 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3021 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3022 CEFBS_None, // G_INTRINSIC_TRUNC
3023 CEFBS_None, // G_INTRINSIC_ROUND
3024 CEFBS_None, // G_INTRINSIC_LRINT
3025 CEFBS_None, // G_INTRINSIC_LLRINT
3026 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3027 CEFBS_None, // G_READCYCLECOUNTER
3028 CEFBS_None, // G_READSTEADYCOUNTER
3029 CEFBS_None, // G_LOAD
3030 CEFBS_None, // G_SEXTLOAD
3031 CEFBS_None, // G_ZEXTLOAD
3032 CEFBS_None, // G_INDEXED_LOAD
3033 CEFBS_None, // G_INDEXED_SEXTLOAD
3034 CEFBS_None, // G_INDEXED_ZEXTLOAD
3035 CEFBS_None, // G_STORE
3036 CEFBS_None, // G_INDEXED_STORE
3037 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3038 CEFBS_None, // G_ATOMIC_CMPXCHG
3039 CEFBS_None, // G_ATOMICRMW_XCHG
3040 CEFBS_None, // G_ATOMICRMW_ADD
3041 CEFBS_None, // G_ATOMICRMW_SUB
3042 CEFBS_None, // G_ATOMICRMW_AND
3043 CEFBS_None, // G_ATOMICRMW_NAND
3044 CEFBS_None, // G_ATOMICRMW_OR
3045 CEFBS_None, // G_ATOMICRMW_XOR
3046 CEFBS_None, // G_ATOMICRMW_MAX
3047 CEFBS_None, // G_ATOMICRMW_MIN
3048 CEFBS_None, // G_ATOMICRMW_UMAX
3049 CEFBS_None, // G_ATOMICRMW_UMIN
3050 CEFBS_None, // G_ATOMICRMW_FADD
3051 CEFBS_None, // G_ATOMICRMW_FSUB
3052 CEFBS_None, // G_ATOMICRMW_FMAX
3053 CEFBS_None, // G_ATOMICRMW_FMIN
3054 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3055 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3056 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3057 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3058 CEFBS_None, // G_ATOMICRMW_USUB_COND
3059 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3060 CEFBS_None, // G_FENCE
3061 CEFBS_None, // G_PREFETCH
3062 CEFBS_None, // G_BRCOND
3063 CEFBS_None, // G_BRINDIRECT
3064 CEFBS_None, // G_INVOKE_REGION_START
3065 CEFBS_None, // G_INTRINSIC
3066 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3067 CEFBS_None, // G_INTRINSIC_CONVERGENT
3068 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3069 CEFBS_None, // G_ANYEXT
3070 CEFBS_None, // G_TRUNC
3071 CEFBS_None, // G_TRUNC_SSAT_S
3072 CEFBS_None, // G_TRUNC_SSAT_U
3073 CEFBS_None, // G_TRUNC_USAT_U
3074 CEFBS_None, // G_CONSTANT
3075 CEFBS_None, // G_FCONSTANT
3076 CEFBS_None, // G_VASTART
3077 CEFBS_None, // G_VAARG
3078 CEFBS_None, // G_SEXT
3079 CEFBS_None, // G_SEXT_INREG
3080 CEFBS_None, // G_ZEXT
3081 CEFBS_None, // G_SHL
3082 CEFBS_None, // G_LSHR
3083 CEFBS_None, // G_ASHR
3084 CEFBS_None, // G_FSHL
3085 CEFBS_None, // G_FSHR
3086 CEFBS_None, // G_ROTR
3087 CEFBS_None, // G_ROTL
3088 CEFBS_None, // G_ICMP
3089 CEFBS_None, // G_FCMP
3090 CEFBS_None, // G_SCMP
3091 CEFBS_None, // G_UCMP
3092 CEFBS_None, // G_SELECT
3093 CEFBS_None, // G_UADDO
3094 CEFBS_None, // G_UADDE
3095 CEFBS_None, // G_USUBO
3096 CEFBS_None, // G_USUBE
3097 CEFBS_None, // G_SADDO
3098 CEFBS_None, // G_SADDE
3099 CEFBS_None, // G_SSUBO
3100 CEFBS_None, // G_SSUBE
3101 CEFBS_None, // G_UMULO
3102 CEFBS_None, // G_SMULO
3103 CEFBS_None, // G_UMULH
3104 CEFBS_None, // G_SMULH
3105 CEFBS_None, // G_UADDSAT
3106 CEFBS_None, // G_SADDSAT
3107 CEFBS_None, // G_USUBSAT
3108 CEFBS_None, // G_SSUBSAT
3109 CEFBS_None, // G_USHLSAT
3110 CEFBS_None, // G_SSHLSAT
3111 CEFBS_None, // G_SMULFIX
3112 CEFBS_None, // G_UMULFIX
3113 CEFBS_None, // G_SMULFIXSAT
3114 CEFBS_None, // G_UMULFIXSAT
3115 CEFBS_None, // G_SDIVFIX
3116 CEFBS_None, // G_UDIVFIX
3117 CEFBS_None, // G_SDIVFIXSAT
3118 CEFBS_None, // G_UDIVFIXSAT
3119 CEFBS_None, // G_FADD
3120 CEFBS_None, // G_FSUB
3121 CEFBS_None, // G_FMUL
3122 CEFBS_None, // G_FMA
3123 CEFBS_None, // G_FMAD
3124 CEFBS_None, // G_FDIV
3125 CEFBS_None, // G_FREM
3126 CEFBS_None, // G_FMODF
3127 CEFBS_None, // G_FPOW
3128 CEFBS_None, // G_FPOWI
3129 CEFBS_None, // G_FEXP
3130 CEFBS_None, // G_FEXP2
3131 CEFBS_None, // G_FEXP10
3132 CEFBS_None, // G_FLOG
3133 CEFBS_None, // G_FLOG2
3134 CEFBS_None, // G_FLOG10
3135 CEFBS_None, // G_FLDEXP
3136 CEFBS_None, // G_FFREXP
3137 CEFBS_None, // G_FNEG
3138 CEFBS_None, // G_FPEXT
3139 CEFBS_None, // G_FPTRUNC
3140 CEFBS_None, // G_FPTOSI
3141 CEFBS_None, // G_FPTOUI
3142 CEFBS_None, // G_SITOFP
3143 CEFBS_None, // G_UITOFP
3144 CEFBS_None, // G_FPTOSI_SAT
3145 CEFBS_None, // G_FPTOUI_SAT
3146 CEFBS_None, // G_FABS
3147 CEFBS_None, // G_FCOPYSIGN
3148 CEFBS_None, // G_IS_FPCLASS
3149 CEFBS_None, // G_FCANONICALIZE
3150 CEFBS_None, // G_FMINNUM
3151 CEFBS_None, // G_FMAXNUM
3152 CEFBS_None, // G_FMINNUM_IEEE
3153 CEFBS_None, // G_FMAXNUM_IEEE
3154 CEFBS_None, // G_FMINIMUM
3155 CEFBS_None, // G_FMAXIMUM
3156 CEFBS_None, // G_FMINIMUMNUM
3157 CEFBS_None, // G_FMAXIMUMNUM
3158 CEFBS_None, // G_GET_FPENV
3159 CEFBS_None, // G_SET_FPENV
3160 CEFBS_None, // G_RESET_FPENV
3161 CEFBS_None, // G_GET_FPMODE
3162 CEFBS_None, // G_SET_FPMODE
3163 CEFBS_None, // G_RESET_FPMODE
3164 CEFBS_None, // G_GET_ROUNDING
3165 CEFBS_None, // G_SET_ROUNDING
3166 CEFBS_None, // G_PTR_ADD
3167 CEFBS_None, // G_PTRMASK
3168 CEFBS_None, // G_SMIN
3169 CEFBS_None, // G_SMAX
3170 CEFBS_None, // G_UMIN
3171 CEFBS_None, // G_UMAX
3172 CEFBS_None, // G_ABS
3173 CEFBS_None, // G_LROUND
3174 CEFBS_None, // G_LLROUND
3175 CEFBS_None, // G_BR
3176 CEFBS_None, // G_BRJT
3177 CEFBS_None, // G_VSCALE
3178 CEFBS_None, // G_INSERT_SUBVECTOR
3179 CEFBS_None, // G_EXTRACT_SUBVECTOR
3180 CEFBS_None, // G_INSERT_VECTOR_ELT
3181 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3182 CEFBS_None, // G_SHUFFLE_VECTOR
3183 CEFBS_None, // G_SPLAT_VECTOR
3184 CEFBS_None, // G_STEP_VECTOR
3185 CEFBS_None, // G_VECTOR_COMPRESS
3186 CEFBS_None, // G_CTTZ
3187 CEFBS_None, // G_CTTZ_ZERO_UNDEF
3188 CEFBS_None, // G_CTLZ
3189 CEFBS_None, // G_CTLZ_ZERO_UNDEF
3190 CEFBS_None, // G_CTLS
3191 CEFBS_None, // G_CTPOP
3192 CEFBS_None, // G_BSWAP
3193 CEFBS_None, // G_BITREVERSE
3194 CEFBS_None, // G_FCEIL
3195 CEFBS_None, // G_FCOS
3196 CEFBS_None, // G_FSIN
3197 CEFBS_None, // G_FSINCOS
3198 CEFBS_None, // G_FTAN
3199 CEFBS_None, // G_FACOS
3200 CEFBS_None, // G_FASIN
3201 CEFBS_None, // G_FATAN
3202 CEFBS_None, // G_FATAN2
3203 CEFBS_None, // G_FCOSH
3204 CEFBS_None, // G_FSINH
3205 CEFBS_None, // G_FTANH
3206 CEFBS_None, // G_FSQRT
3207 CEFBS_None, // G_FFLOOR
3208 CEFBS_None, // G_FRINT
3209 CEFBS_None, // G_FNEARBYINT
3210 CEFBS_None, // G_ADDRSPACE_CAST
3211 CEFBS_None, // G_BLOCK_ADDR
3212 CEFBS_None, // G_JUMP_TABLE
3213 CEFBS_None, // G_DYN_STACKALLOC
3214 CEFBS_None, // G_STACKSAVE
3215 CEFBS_None, // G_STACKRESTORE
3216 CEFBS_None, // G_STRICT_FADD
3217 CEFBS_None, // G_STRICT_FSUB
3218 CEFBS_None, // G_STRICT_FMUL
3219 CEFBS_None, // G_STRICT_FDIV
3220 CEFBS_None, // G_STRICT_FREM
3221 CEFBS_None, // G_STRICT_FMA
3222 CEFBS_None, // G_STRICT_FSQRT
3223 CEFBS_None, // G_STRICT_FLDEXP
3224 CEFBS_None, // G_READ_REGISTER
3225 CEFBS_None, // G_WRITE_REGISTER
3226 CEFBS_None, // G_MEMCPY
3227 CEFBS_None, // G_MEMCPY_INLINE
3228 CEFBS_None, // G_MEMMOVE
3229 CEFBS_None, // G_MEMSET
3230 CEFBS_None, // G_BZERO
3231 CEFBS_None, // G_TRAP
3232 CEFBS_None, // G_DEBUGTRAP
3233 CEFBS_None, // G_UBSANTRAP
3234 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3235 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3236 CEFBS_None, // G_VECREDUCE_FADD
3237 CEFBS_None, // G_VECREDUCE_FMUL
3238 CEFBS_None, // G_VECREDUCE_FMAX
3239 CEFBS_None, // G_VECREDUCE_FMIN
3240 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3241 CEFBS_None, // G_VECREDUCE_FMINIMUM
3242 CEFBS_None, // G_VECREDUCE_ADD
3243 CEFBS_None, // G_VECREDUCE_MUL
3244 CEFBS_None, // G_VECREDUCE_AND
3245 CEFBS_None, // G_VECREDUCE_OR
3246 CEFBS_None, // G_VECREDUCE_XOR
3247 CEFBS_None, // G_VECREDUCE_SMAX
3248 CEFBS_None, // G_VECREDUCE_SMIN
3249 CEFBS_None, // G_VECREDUCE_UMAX
3250 CEFBS_None, // G_VECREDUCE_UMIN
3251 CEFBS_None, // G_SBFX
3252 CEFBS_None, // G_UBFX
3253 CEFBS_None, // ASSIGN_TYPE
3254 CEFBS_None, // UNKNOWN_type
3255 CEFBS_None, // OpAccessChain
3256 CEFBS_None, // OpAliasDomainDeclINTEL
3257 CEFBS_None, // OpAliasScopeDeclINTEL
3258 CEFBS_None, // OpAliasScopeListDeclINTEL
3259 CEFBS_None, // OpAll
3260 CEFBS_None, // OpAny
3261 CEFBS_None, // OpArbitraryFloatACosALTERA
3262 CEFBS_None, // OpArbitraryFloatACosPiALTERA
3263 CEFBS_None, // OpArbitraryFloatASinALTERA
3264 CEFBS_None, // OpArbitraryFloatASinPiALTERA
3265 CEFBS_None, // OpArbitraryFloatATan2ALTERA
3266 CEFBS_None, // OpArbitraryFloatATanALTERA
3267 CEFBS_None, // OpArbitraryFloatATanPiALTERA
3268 CEFBS_None, // OpArbitraryFloatAddALTERA
3269 CEFBS_None, // OpArbitraryFloatCastALTERA
3270 CEFBS_None, // OpArbitraryFloatCastFromIntALTERA
3271 CEFBS_None, // OpArbitraryFloatCastToIntALTERA
3272 CEFBS_None, // OpArbitraryFloatCbrtALTERA
3273 CEFBS_None, // OpArbitraryFloatCosALTERA
3274 CEFBS_None, // OpArbitraryFloatCosPiALTERA
3275 CEFBS_None, // OpArbitraryFloatDivALTERA
3276 CEFBS_None, // OpArbitraryFloatEQALTERA
3277 CEFBS_None, // OpArbitraryFloatExp10ALTERA
3278 CEFBS_None, // OpArbitraryFloatExp2ALTERA
3279 CEFBS_None, // OpArbitraryFloatExpALTERA
3280 CEFBS_None, // OpArbitraryFloatExpm1ALTERA
3281 CEFBS_None, // OpArbitraryFloatGEALTERA
3282 CEFBS_None, // OpArbitraryFloatGTALTERA
3283 CEFBS_None, // OpArbitraryFloatHypotALTERA
3284 CEFBS_None, // OpArbitraryFloatLEALTERA
3285 CEFBS_None, // OpArbitraryFloatLTALTERA
3286 CEFBS_None, // OpArbitraryFloatLog10ALTERA
3287 CEFBS_None, // OpArbitraryFloatLog1pALTERA
3288 CEFBS_None, // OpArbitraryFloatLog2ALTERA
3289 CEFBS_None, // OpArbitraryFloatLogALTERA
3290 CEFBS_None, // OpArbitraryFloatMulALTERA
3291 CEFBS_None, // OpArbitraryFloatPowALTERA
3292 CEFBS_None, // OpArbitraryFloatPowNALTERA
3293 CEFBS_None, // OpArbitraryFloatPowRALTERA
3294 CEFBS_None, // OpArbitraryFloatRSqrtALTERA
3295 CEFBS_None, // OpArbitraryFloatRecipALTERA
3296 CEFBS_None, // OpArbitraryFloatSinALTERA
3297 CEFBS_None, // OpArbitraryFloatSinCosALTERA
3298 CEFBS_None, // OpArbitraryFloatSinCosPiALTERA
3299 CEFBS_None, // OpArbitraryFloatSinPiALTERA
3300 CEFBS_None, // OpArbitraryFloatSqrtALTERA
3301 CEFBS_None, // OpArbitraryFloatSubALTERA
3302 CEFBS_None, // OpArithmeticFenceEXT
3303 CEFBS_None, // OpArrayLength
3304 CEFBS_None, // OpAsmCallINTEL
3305 CEFBS_None, // OpAsmINTEL
3306 CEFBS_None, // OpAsmTargetINTEL
3307 CEFBS_None, // OpAssumeTrueKHR
3308 CEFBS_None, // OpAtomicAnd
3309 CEFBS_None, // OpAtomicCompareExchange
3310 CEFBS_None, // OpAtomicCompareExchangeWeak
3311 CEFBS_None, // OpAtomicExchange
3312 CEFBS_None, // OpAtomicFAddEXT
3313 CEFBS_None, // OpAtomicFMaxEXT
3314 CEFBS_None, // OpAtomicFMinEXT
3315 CEFBS_None, // OpAtomicFlagClear
3316 CEFBS_None, // OpAtomicFlagTestAndSet
3317 CEFBS_None, // OpAtomicIAdd
3318 CEFBS_None, // OpAtomicIDecrement
3319 CEFBS_None, // OpAtomicIIncrement
3320 CEFBS_None, // OpAtomicISub
3321 CEFBS_None, // OpAtomicLoad
3322 CEFBS_None, // OpAtomicOr
3323 CEFBS_None, // OpAtomicSMax
3324 CEFBS_None, // OpAtomicSMin
3325 CEFBS_None, // OpAtomicStore
3326 CEFBS_None, // OpAtomicUMax
3327 CEFBS_None, // OpAtomicUMin
3328 CEFBS_None, // OpAtomicXor
3329 CEFBS_None, // OpBitCount
3330 CEFBS_None, // OpBitFieldInsert
3331 CEFBS_None, // OpBitFieldSExtract
3332 CEFBS_None, // OpBitFieldUExtract
3333 CEFBS_None, // OpBitReverse
3334 CEFBS_None, // OpBitcast
3335 CEFBS_None, // OpBitwiseAndS
3336 CEFBS_None, // OpBitwiseAndV
3337 CEFBS_None, // OpBitwiseFunctionINTEL
3338 CEFBS_None, // OpBitwiseOrS
3339 CEFBS_None, // OpBitwiseOrV
3340 CEFBS_None, // OpBitwiseXorS
3341 CEFBS_None, // OpBitwiseXorV
3342 CEFBS_None, // OpBranch
3343 CEFBS_None, // OpBranchConditional
3344 CEFBS_None, // OpBuildNDRange
3345 CEFBS_None, // OpCapability
3346 CEFBS_None, // OpCaptureEventProfilingInfo
3347 CEFBS_None, // OpCommitReadPipe
3348 CEFBS_None, // OpCommitWritePipe
3349 CEFBS_None, // OpCompositeConstruct
3350 CEFBS_None, // OpCompositeConstructContinuedINTEL
3351 CEFBS_None, // OpCompositeExtract
3352 CEFBS_None, // OpCompositeInsert
3353 CEFBS_None, // OpConstantComposite
3354 CEFBS_None, // OpConstantCompositeContinuedINTEL
3355 CEFBS_None, // OpConstantF
3356 CEFBS_None, // OpConstantFalse
3357 CEFBS_None, // OpConstantFunctionPointerINTEL
3358 CEFBS_None, // OpConstantI
3359 CEFBS_None, // OpConstantNull
3360 CEFBS_None, // OpConstantSampler
3361 CEFBS_None, // OpConstantTrue
3362 CEFBS_None, // OpControlBarrier
3363 CEFBS_None, // OpControlBarrierArriveINTEL
3364 CEFBS_None, // OpControlBarrierWaitINTEL
3365 CEFBS_None, // OpConvertBF16ToFINTEL
3366 CEFBS_None, // OpConvertFToBF16INTEL
3367 CEFBS_None, // OpConvertFToS
3368 CEFBS_None, // OpConvertFToU
3369 CEFBS_None, // OpConvertHandleToImageINTEL
3370 CEFBS_None, // OpConvertHandleToSampledImageINTEL
3371 CEFBS_None, // OpConvertHandleToSamplerINTEL
3372 CEFBS_None, // OpConvertPtrToU
3373 CEFBS_None, // OpConvertSToF
3374 CEFBS_None, // OpConvertUToF
3375 CEFBS_None, // OpConvertUToPtr
3376 CEFBS_None, // OpCooperativeMatrixConstructCheckedINTEL
3377 CEFBS_None, // OpCooperativeMatrixGetElementCoordINTEL
3378 CEFBS_None, // OpCooperativeMatrixLengthKHR
3379 CEFBS_None, // OpCooperativeMatrixLoadCheckedINTEL
3380 CEFBS_None, // OpCooperativeMatrixLoadKHR
3381 CEFBS_None, // OpCooperativeMatrixMulAddKHR
3382 CEFBS_None, // OpCooperativeMatrixPrefetchINTEL
3383 CEFBS_None, // OpCooperativeMatrixStoreCheckedINTEL
3384 CEFBS_None, // OpCooperativeMatrixStoreKHR
3385 CEFBS_None, // OpCopyLogical
3386 CEFBS_None, // OpCopyMemory
3387 CEFBS_None, // OpCopyMemorySized
3388 CEFBS_None, // OpCopyObject
3389 CEFBS_None, // OpCreateUserEvent
3390 CEFBS_None, // OpCrossWorkgroupCastToPtrINTEL
3391 CEFBS_None, // OpDPdx
3392 CEFBS_None, // OpDPdxCoarse
3393 CEFBS_None, // OpDPdxFine
3394 CEFBS_None, // OpDPdy
3395 CEFBS_None, // OpDPdyCoarse
3396 CEFBS_None, // OpDPdyFine
3397 CEFBS_None, // OpDecorate
3398 CEFBS_None, // OpDecorateId
3399 CEFBS_None, // OpDecorateString
3400 CEFBS_None, // OpDemoteToHelperInvocation
3401 CEFBS_None, // OpDot
3402 CEFBS_None, // OpEmitStreamVertex
3403 CEFBS_None, // OpEmitVertex
3404 CEFBS_None, // OpEndPrimitive
3405 CEFBS_None, // OpEndStreamPrimitive
3406 CEFBS_None, // OpEnqueueKernel
3407 CEFBS_None, // OpEntryPoint
3408 CEFBS_None, // OpExecutionMode
3409 CEFBS_None, // OpExecutionModeId
3410 CEFBS_None, // OpExpectKHR
3411 CEFBS_None, // OpExtInst
3412 CEFBS_None, // OpExtInstImport
3413 CEFBS_None, // OpExtension
3414 CEFBS_None, // OpFAddS
3415 CEFBS_None, // OpFAddV
3416 CEFBS_None, // OpFConvert
3417 CEFBS_None, // OpFDivS
3418 CEFBS_None, // OpFDivV
3419 CEFBS_None, // OpFMod
3420 CEFBS_None, // OpFMulS
3421 CEFBS_None, // OpFMulV
3422 CEFBS_None, // OpFNegate
3423 CEFBS_None, // OpFNegateV
3424 CEFBS_None, // OpFOrdEqual
3425 CEFBS_None, // OpFOrdGreaterThan
3426 CEFBS_None, // OpFOrdGreaterThanEqual
3427 CEFBS_None, // OpFOrdLessThan
3428 CEFBS_None, // OpFOrdLessThanEqual
3429 CEFBS_None, // OpFOrdNotEqual
3430 CEFBS_None, // OpFRemS
3431 CEFBS_None, // OpFRemV
3432 CEFBS_None, // OpFSubS
3433 CEFBS_None, // OpFSubV
3434 CEFBS_None, // OpFUnordEqual
3435 CEFBS_None, // OpFUnordGreaterThan
3436 CEFBS_None, // OpFUnordGreaterThanEqual
3437 CEFBS_None, // OpFUnordLessThan
3438 CEFBS_None, // OpFUnordLessThanEqual
3439 CEFBS_None, // OpFUnordNotEqual
3440 CEFBS_None, // OpFixedCosALTERA
3441 CEFBS_None, // OpFixedCosPiALTERA
3442 CEFBS_None, // OpFixedExpALTERA
3443 CEFBS_None, // OpFixedLogALTERA
3444 CEFBS_None, // OpFixedRecipALTERA
3445 CEFBS_None, // OpFixedRsqrtALTERA
3446 CEFBS_None, // OpFixedSinALTERA
3447 CEFBS_None, // OpFixedSinCosALTERA
3448 CEFBS_None, // OpFixedSinCosPiALTERA
3449 CEFBS_None, // OpFixedSinPiALTERA
3450 CEFBS_None, // OpFixedSqrtALTERA
3451 CEFBS_None, // OpFmaKHR
3452 CEFBS_None, // OpFunction
3453 CEFBS_None, // OpFunctionCall
3454 CEFBS_None, // OpFunctionEnd
3455 CEFBS_None, // OpFunctionParameter
3456 CEFBS_None, // OpFunctionPointerCallINTEL
3457 CEFBS_None, // OpFwidth
3458 CEFBS_None, // OpFwidthCoarse
3459 CEFBS_None, // OpFwidthFine
3460 CEFBS_None, // OpGenericCastToPtr
3461 CEFBS_None, // OpGenericCastToPtrExplicit
3462 CEFBS_None, // OpGenericPtrMemSemantics
3463 CEFBS_None, // OpGetDefaultQueue
3464 CEFBS_None, // OpGetMaxPipePackets
3465 CEFBS_None, // OpGetNumPipePackets
3466 CEFBS_None, // OpGroupAll
3467 CEFBS_None, // OpGroupAny
3468 CEFBS_None, // OpGroupAsyncCopy
3469 CEFBS_None, // OpGroupBitwiseAndKHR
3470 CEFBS_None, // OpGroupBitwiseOrKHR
3471 CEFBS_None, // OpGroupBitwiseXorKHR
3472 CEFBS_None, // OpGroupBroadcast
3473 CEFBS_None, // OpGroupCommitReadPipe
3474 CEFBS_None, // OpGroupCommitWritePipe
3475 CEFBS_None, // OpGroupFAdd
3476 CEFBS_None, // OpGroupFMax
3477 CEFBS_None, // OpGroupFMin
3478 CEFBS_None, // OpGroupFMulKHR
3479 CEFBS_None, // OpGroupIAdd
3480 CEFBS_None, // OpGroupIMulKHR
3481 CEFBS_None, // OpGroupLogicalAndKHR
3482 CEFBS_None, // OpGroupLogicalOrKHR
3483 CEFBS_None, // OpGroupLogicalXorKHR
3484 CEFBS_None, // OpGroupNonUniformAll
3485 CEFBS_None, // OpGroupNonUniformAllEqual
3486 CEFBS_None, // OpGroupNonUniformAny
3487 CEFBS_None, // OpGroupNonUniformBallot
3488 CEFBS_None, // OpGroupNonUniformBallotBitCount
3489 CEFBS_None, // OpGroupNonUniformBallotBitExtract
3490 CEFBS_None, // OpGroupNonUniformBallotFindLSB
3491 CEFBS_None, // OpGroupNonUniformBallotFindMSB
3492 CEFBS_None, // OpGroupNonUniformBitwiseAnd
3493 CEFBS_None, // OpGroupNonUniformBitwiseOr
3494 CEFBS_None, // OpGroupNonUniformBitwiseXor
3495 CEFBS_None, // OpGroupNonUniformBroadcast
3496 CEFBS_None, // OpGroupNonUniformBroadcastFirst
3497 CEFBS_None, // OpGroupNonUniformElect
3498 CEFBS_None, // OpGroupNonUniformFAdd
3499 CEFBS_None, // OpGroupNonUniformFMax
3500 CEFBS_None, // OpGroupNonUniformFMin
3501 CEFBS_None, // OpGroupNonUniformFMul
3502 CEFBS_None, // OpGroupNonUniformIAdd
3503 CEFBS_None, // OpGroupNonUniformIMul
3504 CEFBS_None, // OpGroupNonUniformInverseBallot
3505 CEFBS_None, // OpGroupNonUniformLogicalAnd
3506 CEFBS_None, // OpGroupNonUniformLogicalOr
3507 CEFBS_None, // OpGroupNonUniformLogicalXor
3508 CEFBS_None, // OpGroupNonUniformRotateKHR
3509 CEFBS_None, // OpGroupNonUniformSMax
3510 CEFBS_None, // OpGroupNonUniformSMin
3511 CEFBS_None, // OpGroupNonUniformShuffle
3512 CEFBS_None, // OpGroupNonUniformShuffleDown
3513 CEFBS_None, // OpGroupNonUniformShuffleUp
3514 CEFBS_None, // OpGroupNonUniformShuffleXor
3515 CEFBS_None, // OpGroupNonUniformUMax
3516 CEFBS_None, // OpGroupNonUniformUMin
3517 CEFBS_None, // OpGroupReserveReadPipePackets
3518 CEFBS_None, // OpGroupReserveWritePipePackets
3519 CEFBS_None, // OpGroupSMax
3520 CEFBS_None, // OpGroupSMin
3521 CEFBS_None, // OpGroupUMax
3522 CEFBS_None, // OpGroupUMin
3523 CEFBS_None, // OpGroupWaitEvents
3524 CEFBS_None, // OpIAddCarryS
3525 CEFBS_None, // OpIAddCarryV
3526 CEFBS_None, // OpIAddS
3527 CEFBS_None, // OpIAddV
3528 CEFBS_None, // OpIEqual
3529 CEFBS_None, // OpIMulS
3530 CEFBS_None, // OpIMulV
3531 CEFBS_None, // OpINotEqual
3532 CEFBS_None, // OpISubBorrowS
3533 CEFBS_None, // OpISubBorrowV
3534 CEFBS_None, // OpISubS
3535 CEFBS_None, // OpISubV
3536 CEFBS_None, // OpImage
3537 CEFBS_None, // OpImageDrefGather
3538 CEFBS_None, // OpImageFetch
3539 CEFBS_None, // OpImageGather
3540 CEFBS_None, // OpImageQueryFormat
3541 CEFBS_None, // OpImageQueryLevels
3542 CEFBS_None, // OpImageQueryLod
3543 CEFBS_None, // OpImageQueryOrder
3544 CEFBS_None, // OpImageQuerySamples
3545 CEFBS_None, // OpImageQuerySize
3546 CEFBS_None, // OpImageQuerySizeLod
3547 CEFBS_None, // OpImageRead
3548 CEFBS_None, // OpImageSampleDrefExplicitLod
3549 CEFBS_None, // OpImageSampleDrefImplicitLod
3550 CEFBS_None, // OpImageSampleExplicitLod
3551 CEFBS_None, // OpImageSampleFootprintNV
3552 CEFBS_None, // OpImageSampleImplicitLod
3553 CEFBS_None, // OpImageSampleProjDrefExplicitLod
3554 CEFBS_None, // OpImageSampleProjDrefImplicitLod
3555 CEFBS_None, // OpImageSampleProjExplicitLod
3556 CEFBS_None, // OpImageSampleProjImplicitLod
3557 CEFBS_None, // OpImageSparseDrefGather
3558 CEFBS_None, // OpImageSparseFetch
3559 CEFBS_None, // OpImageSparseGather
3560 CEFBS_None, // OpImageSparseRead
3561 CEFBS_None, // OpImageSparseSampleDrefExplicitLod
3562 CEFBS_None, // OpImageSparseSampleDrefImplicitLod
3563 CEFBS_None, // OpImageSparseSampleExplicitLod
3564 CEFBS_None, // OpImageSparseSampleImplicitLod
3565 CEFBS_None, // OpImageSparseSampleProjDrefExplicitLod
3566 CEFBS_None, // OpImageSparseSampleProjDrefImplicitLod
3567 CEFBS_None, // OpImageSparseSampleProjExplicitLod
3568 CEFBS_None, // OpImageSparseSampleProjImplicitLod
3569 CEFBS_None, // OpImageSparseTexelsResident
3570 CEFBS_None, // OpImageTexelPointer
3571 CEFBS_None, // OpImageWrite
3572 CEFBS_None, // OpInBoundsAccessChain
3573 CEFBS_None, // OpInBoundsPtrAccessChain
3574 CEFBS_None, // OpIsFinite
3575 CEFBS_None, // OpIsInf
3576 CEFBS_None, // OpIsNan
3577 CEFBS_None, // OpIsNormal
3578 CEFBS_None, // OpIsValidEvent
3579 CEFBS_None, // OpIsValidReserveId
3580 CEFBS_None, // OpKill
3581 CEFBS_None, // OpLabel
3582 CEFBS_None, // OpLessOrGreater
3583 CEFBS_None, // OpLifetimeStart
3584 CEFBS_None, // OpLifetimeStop
3585 CEFBS_None, // OpLine
3586 CEFBS_None, // OpLoad
3587 CEFBS_None, // OpLogicalAnd
3588 CEFBS_None, // OpLogicalEqual
3589 CEFBS_None, // OpLogicalNot
3590 CEFBS_None, // OpLogicalNotEqual
3591 CEFBS_None, // OpLogicalOr
3592 CEFBS_None, // OpLoopControlINTEL
3593 CEFBS_None, // OpLoopMerge
3594 CEFBS_None, // OpMatrixTimesMatrix
3595 CEFBS_None, // OpMatrixTimesScalar
3596 CEFBS_None, // OpMatrixTimesVector
3597 CEFBS_None, // OpMemberDecorate
3598 CEFBS_None, // OpMemberDecorateString
3599 CEFBS_None, // OpMemberName
3600 CEFBS_None, // OpMemoryBarrier
3601 CEFBS_None, // OpMemoryModel
3602 CEFBS_None, // OpMemoryNamedBarrier
3603 CEFBS_None, // OpModuleProcessed
3604 CEFBS_None, // OpName
3605 CEFBS_None, // OpNamedBarrierInitialize
3606 CEFBS_None, // OpNoLine
3607 CEFBS_None, // OpNop
3608 CEFBS_None, // OpNot
3609 CEFBS_None, // OpOrdered
3610 CEFBS_None, // OpOuterProduct
3611 CEFBS_None, // OpPhi
3612 CEFBS_None, // OpPredicatedLoadINTEL
3613 CEFBS_None, // OpPredicatedStoreINTEL
3614 CEFBS_None, // OpPtrAccessChain
3615 CEFBS_None, // OpPtrCastToCrossWorkgroupINTEL
3616 CEFBS_None, // OpPtrCastToGeneric
3617 CEFBS_None, // OpPtrDiff
3618 CEFBS_None, // OpPtrEqual
3619 CEFBS_None, // OpPtrNotEqual
3620 CEFBS_None, // OpQuantizeToF16
3621 CEFBS_None, // OpReadClockKHR
3622 CEFBS_None, // OpReadPipe
3623 CEFBS_None, // OpReadPipeBlockingALTERA
3624 CEFBS_None, // OpReleaseEvent
3625 CEFBS_None, // OpReserveReadPipePackets
3626 CEFBS_None, // OpReserveWritePipePackets
3627 CEFBS_None, // OpReservedReadPipe
3628 CEFBS_None, // OpReservedWritePipe
3629 CEFBS_None, // OpRestoreMemoryINTEL
3630 CEFBS_None, // OpRetainEvent
3631 CEFBS_None, // OpReturn
3632 CEFBS_None, // OpReturnValue
3633 CEFBS_None, // OpRoundFToTF32INTEL
3634 CEFBS_None, // OpSConvert
3635 CEFBS_None, // OpSDivS
3636 CEFBS_None, // OpSDivV
3637 CEFBS_None, // OpSDot
3638 CEFBS_None, // OpSDotAccSat
3639 CEFBS_None, // OpSGreaterThan
3640 CEFBS_None, // OpSGreaterThanEqual
3641 CEFBS_None, // OpSLessThan
3642 CEFBS_None, // OpSLessThanEqual
3643 CEFBS_None, // OpSMod
3644 CEFBS_None, // OpSMulExtended
3645 CEFBS_None, // OpSNegate
3646 CEFBS_None, // OpSRemS
3647 CEFBS_None, // OpSRemV
3648 CEFBS_None, // OpSUDot
3649 CEFBS_None, // OpSUDotAccSat
3650 CEFBS_None, // OpSampledImage
3651 CEFBS_None, // OpSatConvertSToU
3652 CEFBS_None, // OpSatConvertUToS
3653 CEFBS_None, // OpSaveMemoryINTEL
3654 CEFBS_None, // OpSelectSFSCond
3655 CEFBS_None, // OpSelectSFVCond
3656 CEFBS_None, // OpSelectSISCond
3657 CEFBS_None, // OpSelectSIVCond
3658 CEFBS_None, // OpSelectSPSCond
3659 CEFBS_None, // OpSelectSPVCond
3660 CEFBS_None, // OpSelectVFSCond
3661 CEFBS_None, // OpSelectVFVCond
3662 CEFBS_None, // OpSelectVISCond
3663 CEFBS_None, // OpSelectVIVCond
3664 CEFBS_None, // OpSelectVPSCond
3665 CEFBS_None, // OpSelectVPVCond
3666 CEFBS_None, // OpSelectionMerge
3667 CEFBS_None, // OpSetUserEventStatus
3668 CEFBS_None, // OpShiftLeftLogicalS
3669 CEFBS_None, // OpShiftLeftLogicalV
3670 CEFBS_None, // OpShiftRightArithmeticS
3671 CEFBS_None, // OpShiftRightArithmeticV
3672 CEFBS_None, // OpShiftRightLogicalS
3673 CEFBS_None, // OpShiftRightLogicalV
3674 CEFBS_None, // OpSignBitSet
3675 CEFBS_None, // OpSizeOf
3676 CEFBS_None, // OpSource
3677 CEFBS_None, // OpSourceContinued
3678 CEFBS_None, // OpSourceExtension
3679 CEFBS_None, // OpSpecConstant
3680 CEFBS_None, // OpSpecConstantComposite
3681 CEFBS_None, // OpSpecConstantCompositeContinuedINTEL
3682 CEFBS_None, // OpSpecConstantFalse
3683 CEFBS_None, // OpSpecConstantOp
3684 CEFBS_None, // OpSpecConstantTrue
3685 CEFBS_None, // OpStore
3686 CEFBS_None, // OpStrictFAddS
3687 CEFBS_None, // OpStrictFAddV
3688 CEFBS_None, // OpStrictFDivS
3689 CEFBS_None, // OpStrictFDivV
3690 CEFBS_None, // OpStrictFMulS
3691 CEFBS_None, // OpStrictFMulV
3692 CEFBS_None, // OpStrictFRemS
3693 CEFBS_None, // OpStrictFRemV
3694 CEFBS_None, // OpStrictFSubS
3695 CEFBS_None, // OpStrictFSubV
3696 CEFBS_None, // OpString
3697 CEFBS_None, // OpSubgroup2DBlockLoadINTEL
3698 CEFBS_None, // OpSubgroup2DBlockLoadTransformINTEL
3699 CEFBS_None, // OpSubgroup2DBlockLoadTransposeINTEL
3700 CEFBS_None, // OpSubgroup2DBlockPrefetchINTEL
3701 CEFBS_None, // OpSubgroup2DBlockStoreINTEL
3702 CEFBS_None, // OpSubgroupBlockReadINTEL
3703 CEFBS_None, // OpSubgroupBlockWriteINTEL
3704 CEFBS_None, // OpSubgroupImageBlockReadINTEL
3705 CEFBS_None, // OpSubgroupImageBlockWriteINTEL
3706 CEFBS_None, // OpSubgroupImageMediaBlockReadINTEL
3707 CEFBS_None, // OpSubgroupImageMediaBlockWriteINTEL
3708 CEFBS_None, // OpSubgroupMatrixMultiplyAccumulateINTEL
3709 CEFBS_None, // OpSubgroupShuffleDownINTEL
3710 CEFBS_None, // OpSubgroupShuffleINTEL
3711 CEFBS_None, // OpSubgroupShuffleUpINTEL
3712 CEFBS_None, // OpSubgroupShuffleXorINTEL
3713 CEFBS_None, // OpSwitch
3714 CEFBS_None, // OpTranspose
3715 CEFBS_None, // OpTypeAccelerationStructureNV
3716 CEFBS_None, // OpTypeArray
3717 CEFBS_None, // OpTypeBool
3718 CEFBS_None, // OpTypeCooperativeMatrixKHR
3719 CEFBS_None, // OpTypeCooperativeMatrixNV
3720 CEFBS_None, // OpTypeDeviceEvent
3721 CEFBS_None, // OpTypeEvent
3722 CEFBS_None, // OpTypeFloat
3723 CEFBS_None, // OpTypeForwardPointer
3724 CEFBS_None, // OpTypeFunction
3725 CEFBS_None, // OpTypeImage
3726 CEFBS_None, // OpTypeInt
3727 CEFBS_None, // OpTypeMatrix
3728 CEFBS_None, // OpTypeNamedBarrier
3729 CEFBS_None, // OpTypeOpaque
3730 CEFBS_None, // OpTypePipe
3731 CEFBS_None, // OpTypePipeStorage
3732 CEFBS_None, // OpTypePointer
3733 CEFBS_None, // OpTypeQueue
3734 CEFBS_None, // OpTypeReserveId
3735 CEFBS_None, // OpTypeRuntimeArray
3736 CEFBS_None, // OpTypeSampledImage
3737 CEFBS_None, // OpTypeSampler
3738 CEFBS_None, // OpTypeStruct
3739 CEFBS_None, // OpTypeStructContinuedINTEL
3740 CEFBS_None, // OpTypeVector
3741 CEFBS_None, // OpTypeVoid
3742 CEFBS_None, // OpUConvert
3743 CEFBS_None, // OpUDivS
3744 CEFBS_None, // OpUDivV
3745 CEFBS_None, // OpUDot
3746 CEFBS_None, // OpUDotAccSat
3747 CEFBS_None, // OpUGreaterThan
3748 CEFBS_None, // OpUGreaterThanEqual
3749 CEFBS_None, // OpULessThan
3750 CEFBS_None, // OpULessThanEqual
3751 CEFBS_None, // OpUModS
3752 CEFBS_None, // OpUModV
3753 CEFBS_None, // OpUMulExtended
3754 CEFBS_None, // OpUndef
3755 CEFBS_None, // OpUnordered
3756 CEFBS_None, // OpUnreachable
3757 CEFBS_None, // OpVariable
3758 CEFBS_None, // OpVariableLengthArrayINTEL
3759 CEFBS_None, // OpVectorExtractDynamic
3760 CEFBS_None, // OpVectorInsertDynamic
3761 CEFBS_None, // OpVectorShuffle
3762 CEFBS_None, // OpVectorTimesMatrix
3763 CEFBS_None, // OpVectorTimesScalar
3764 CEFBS_None, // OpWritePipe
3765 CEFBS_None, // OpWritePipeBlockingALTERA
3766 };
3767
3768 assert(Opcode < 836);
3769 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3770}
3771
3772
3773} // namespace llvm::SPIRV_MC
3774
3775#endif // GET_COMPUTE_FEATURES
3776
3777#ifdef GET_AVAILABLE_OPCODE_CHECKER
3778#undef GET_AVAILABLE_OPCODE_CHECKER
3779
3780namespace llvm::SPIRV_MC {
3781
3782bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3783 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3784 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3785 FeatureBitset MissingFeatures =
3786 (AvailableFeatures & RequiredFeatures) ^
3787 RequiredFeatures;
3788 return !MissingFeatures.any();
3789}
3790
3791} // namespace llvm::SPIRV_MC
3792
3793#endif // GET_AVAILABLE_OPCODE_CHECKER
3794
3795#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3796#undef ENABLE_INSTR_PREDICATE_VERIFIER
3797
3798#include <sstream>
3799
3800namespace llvm::SPIRV_MC {
3801
3802#ifndef NDEBUG
3803static const char *SubtargetFeatureNames[] = {
3804 nullptr
3805};
3806
3807#endif // NDEBUG
3808
3809void verifyInstructionPredicates(
3810 unsigned Opcode, const FeatureBitset &Features) {
3811#ifndef NDEBUG
3812 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3813 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3814 FeatureBitset MissingFeatures =
3815 (AvailableFeatures & RequiredFeatures) ^
3816 RequiredFeatures;
3817 if (MissingFeatures.any()) {
3818 std::ostringstream Msg;
3819 Msg << "Attempting to emit " << &SPIRVInstrNameData[SPIRVInstrNameIndices[Opcode]]
3820 << " instruction but the ";
3821 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3822 if (MissingFeatures.test(i))
3823 Msg << SubtargetFeatureNames[i] << " ";
3824 Msg << "predicate(s) are not met";
3825 report_fatal_error(Msg.str().c_str());
3826 }
3827#endif // NDEBUG
3828}
3829
3830} // namespace llvm::SPIRV_MC
3831
3832#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3833
3834