1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SPIRV {
13
14 enum {
15 PHI = 0, // Target.td:1324
16 INLINEASM = 1, // Target.td:1330
17 INLINEASM_BR = 2, // Target.td:1336
18 CFI_INSTRUCTION = 3, // Target.td:1345
19 EH_LABEL = 4, // Target.td:1354
20 GC_LABEL = 5, // Target.td:1363
21 ANNOTATION_LABEL = 6, // Target.td:1372
22 KILL = 7, // Target.td:1380
23 EXTRACT_SUBREG = 8, // Target.td:1387
24 INSERT_SUBREG = 9, // Target.td:1393
25 IMPLICIT_DEF = 10, // Target.td:1400
26 INIT_UNDEF = 11, // Target.td:1409
27 SUBREG_TO_REG = 12, // Target.td:1416
28 COPY_TO_REGCLASS = 13, // Target.td:1422
29 DBG_VALUE = 14, // Target.td:1429
30 DBG_VALUE_LIST = 15, // Target.td:1436
31 DBG_INSTR_REF = 16, // Target.td:1443
32 DBG_PHI = 17, // Target.td:1450
33 DBG_LABEL = 18, // Target.td:1457
34 REG_SEQUENCE = 19, // Target.td:1464
35 COPY = 20, // Target.td:1471
36 COPY_LANEMASK = 21, // Target.td:1479
37 BUNDLE = 22, // Target.td:1486
38 LIFETIME_START = 23, // Target.td:1492
39 LIFETIME_END = 24, // Target.td:1499
40 PSEUDO_PROBE = 25, // Target.td:1506
41 ARITH_FENCE = 26, // Target.td:1513
42 STACKMAP = 27, // Target.td:1522
43 FENTRY_CALL = 28, // Target.td:1657
44 PATCHPOINT = 29, // Target.td:1530
45 LOAD_STACK_GUARD = 30, // Target.td:1548
46 PREALLOCATED_SETUP = 31, // Target.td:1556
47 PREALLOCATED_ARG = 32, // Target.td:1562
48 STATEPOINT = 33, // Target.td:1539
49 LOCAL_ESCAPE = 34, // Target.td:1568
50 FAULTING_OP = 35, // Target.td:1577
51 PATCHABLE_OP = 36, // Target.td:1597
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1605
53 PATCHABLE_RET = 38, // Target.td:1612
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1621
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1629
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1637
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1647
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1667
59 FAKE_USE = 44, // Target.td:1587
60 MEMBARRIER = 45, // Target.td:1673
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1681
62 RELOC_NONE = 47, // Target.td:1689
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1701
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1697
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1705
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1709
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1929
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1921
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1936
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1516
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1529
96 G_INSERT = 81, // GenericOpcodes.td:1538
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1548
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1568
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1578
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1585
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1943
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1481
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1482
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1483
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1484
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1485
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1486
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1487
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1488
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1494
150 G_PREFETCH = 135, // GenericOpcodes.td:1501
151 G_BRCOND = 136, // GenericOpcodes.td:1641
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1650
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1673
154 G_INTRINSIC = 139, // GenericOpcodes.td:1593
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1600
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1609
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1617
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1631
265 G_BRJT = 250, // GenericOpcodes.td:1661
266 G_VSCALE = 251, // GenericOpcodes.td:1559
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1705
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1713
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1721
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1729
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1740
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1748
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1756
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1763
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1813
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1814
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1815
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1816
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1817
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1818
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1819
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1820
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1821
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1822
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1680
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1690
318 G_MEMCPY = 303, // GenericOpcodes.td:1828
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1836
320 G_MEMMOVE = 305, // GenericOpcodes.td:1844
321 G_MEMSET = 306, // GenericOpcodes.td:1852
322 G_BZERO = 307, // GenericOpcodes.td:1859
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1866
324 G_TRAP = 309, // GenericOpcodes.td:1876
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1883
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1889
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1779
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1785
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1791
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1792
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1794
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1795
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1796
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1797
335 G_VECREDUCE_ADD = 320, // GenericOpcodes.td:1799
336 G_VECREDUCE_MUL = 321, // GenericOpcodes.td:1800
337 G_VECREDUCE_AND = 322, // GenericOpcodes.td:1801
338 G_VECREDUCE_OR = 323, // GenericOpcodes.td:1802
339 G_VECREDUCE_XOR = 324, // GenericOpcodes.td:1803
340 G_VECREDUCE_SMAX = 325, // GenericOpcodes.td:1804
341 G_VECREDUCE_SMIN = 326, // GenericOpcodes.td:1805
342 G_VECREDUCE_UMAX = 327, // GenericOpcodes.td:1806
343 G_VECREDUCE_UMIN = 328, // GenericOpcodes.td:1807
344 G_SBFX = 329, // GenericOpcodes.td:1901
345 G_UBFX = 330, // GenericOpcodes.td:1909
346 ASSIGN_TYPE = 331, // SPIRVInstrInfo.td:18
347 UNKNOWN_type = 332, // SPIRVInstrInfo.td:21
348 OpAbortKHR = 333, // SPIRVInstrInfo.td:648
349 OpAccessChain = 334, // SPIRVInstrInfo.td:270
350 OpAliasDomainDeclINTEL = 335, // SPIRVInstrInfo.td:975
351 OpAliasScopeDeclINTEL = 336, // SPIRVInstrInfo.td:977
352 OpAliasScopeListDeclINTEL = 337, // SPIRVInstrInfo.td:979
353 OpAll = 338, // SPIRVInstrInfo.td:564
354 OpAny = 339, // SPIRVInstrInfo.td:562
355 OpArbitraryFloatACosALTERA = 340, // SPIRVInstrInfo.td:1066
356 OpArbitraryFloatACosPiALTERA = 341, // SPIRVInstrInfo.td:1068
357 OpArbitraryFloatASinALTERA = 342, // SPIRVInstrInfo.td:1062
358 OpArbitraryFloatASinPiALTERA = 343, // SPIRVInstrInfo.td:1064
359 OpArbitraryFloatATan2ALTERA = 344, // SPIRVInstrInfo.td:1074
360 OpArbitraryFloatATanALTERA = 345, // SPIRVInstrInfo.td:1070
361 OpArbitraryFloatATanPiALTERA = 346, // SPIRVInstrInfo.td:1072
362 OpArbitraryFloatAddALTERA = 347, // SPIRVInstrInfo.td:1051
363 OpArbitraryFloatCastALTERA = 348, // SPIRVInstrInfo.td:1082
364 OpArbitraryFloatCastFromIntALTERA = 349, // SPIRVInstrInfo.td:1084
365 OpArbitraryFloatCastToIntALTERA = 350, // SPIRVInstrInfo.td:1086
366 OpArbitraryFloatCbrtALTERA = 351, // SPIRVInstrInfo.td:1000
367 OpArbitraryFloatCosALTERA = 352, // SPIRVInstrInfo.td:1036
368 OpArbitraryFloatCosPiALTERA = 353, // SPIRVInstrInfo.td:1045
369 OpArbitraryFloatDivALTERA = 354, // SPIRVInstrInfo.td:1058
370 OpArbitraryFloatEQALTERA = 355, // SPIRVInstrInfo.td:995
371 OpArbitraryFloatExp10ALTERA = 356, // SPIRVInstrInfo.td:1027
372 OpArbitraryFloatExp2ALTERA = 357, // SPIRVInstrInfo.td:1024
373 OpArbitraryFloatExpALTERA = 358, // SPIRVInstrInfo.td:1021
374 OpArbitraryFloatExpm1ALTERA = 359, // SPIRVInstrInfo.td:1030
375 OpArbitraryFloatGEALTERA = 360, // SPIRVInstrInfo.td:989
376 OpArbitraryFloatGTALTERA = 361, // SPIRVInstrInfo.td:987
377 OpArbitraryFloatHypotALTERA = 362, // SPIRVInstrInfo.td:1003
378 OpArbitraryFloatLEALTERA = 363, // SPIRVInstrInfo.td:993
379 OpArbitraryFloatLTALTERA = 364, // SPIRVInstrInfo.td:991
380 OpArbitraryFloatLog10ALTERA = 365, // SPIRVInstrInfo.td:1015
381 OpArbitraryFloatLog1pALTERA = 366, // SPIRVInstrInfo.td:1018
382 OpArbitraryFloatLog2ALTERA = 367, // SPIRVInstrInfo.td:1012
383 OpArbitraryFloatLogALTERA = 368, // SPIRVInstrInfo.td:1009
384 OpArbitraryFloatMulALTERA = 369, // SPIRVInstrInfo.td:1056
385 OpArbitraryFloatPowALTERA = 370, // SPIRVInstrInfo.td:1076
386 OpArbitraryFloatPowNALTERA = 371, // SPIRVInstrInfo.td:1080
387 OpArbitraryFloatPowRALTERA = 372, // SPIRVInstrInfo.td:1078
388 OpArbitraryFloatRSqrtALTERA = 373, // SPIRVInstrInfo.td:1060
389 OpArbitraryFloatRecipALTERA = 374, // SPIRVInstrInfo.td:997
390 OpArbitraryFloatSinALTERA = 375, // SPIRVInstrInfo.td:1033
391 OpArbitraryFloatSinCosALTERA = 376, // SPIRVInstrInfo.td:1039
392 OpArbitraryFloatSinCosPiALTERA = 377, // SPIRVInstrInfo.td:1048
393 OpArbitraryFloatSinPiALTERA = 378, // SPIRVInstrInfo.td:1042
394 OpArbitraryFloatSqrtALTERA = 379, // SPIRVInstrInfo.td:1006
395 OpArbitraryFloatSubALTERA = 380, // SPIRVInstrInfo.td:1054
396 OpArithmeticFenceEXT = 381, // SPIRVInstrInfo.td:963
397 OpArrayLength = 382, // SPIRVInstrInfo.td:278
398 OpAsmCallINTEL = 383, // SPIRVInstrInfo.td:929
399 OpAsmINTEL = 384, // SPIRVInstrInfo.td:926
400 OpAsmTargetINTEL = 385, // SPIRVInstrInfo.td:925
401 OpAssumeTrueKHR = 386, // SPIRVInstrInfo.td:106
402 OpAtomicAnd = 387, // SPIRVInstrInfo.td:692
403 OpAtomicCompareExchange = 388, // SPIRVInstrInfo.td:672
404 OpAtomicCompareExchangeWeak = 389, // SPIRVInstrInfo.td:676
405 OpAtomicExchange = 390, // SPIRVInstrInfo.td:669
406 OpAtomicFAddEXT = 391, // SPIRVInstrInfo.td:696
407 OpAtomicFMaxEXT = 392, // SPIRVInstrInfo.td:698
408 OpAtomicFMinEXT = 393, // SPIRVInstrInfo.td:697
409 OpAtomicFlagClear = 394, // SPIRVInstrInfo.td:701
410 OpAtomicFlagTestAndSet = 395, // SPIRVInstrInfo.td:700
411 OpAtomicIAdd = 396, // SPIRVInstrInfo.td:684
412 OpAtomicIDecrement = 397, // SPIRVInstrInfo.td:682
413 OpAtomicIIncrement = 398, // SPIRVInstrInfo.td:681
414 OpAtomicISub = 399, // SPIRVInstrInfo.td:685
415 OpAtomicLoad = 400, // SPIRVInstrInfo.td:665
416 OpAtomicOr = 401, // SPIRVInstrInfo.td:693
417 OpAtomicSMax = 402, // SPIRVInstrInfo.td:689
418 OpAtomicSMin = 403, // SPIRVInstrInfo.td:687
419 OpAtomicStore = 404, // SPIRVInstrInfo.td:667
420 OpAtomicUMax = 405, // SPIRVInstrInfo.td:690
421 OpAtomicUMin = 406, // SPIRVInstrInfo.td:688
422 OpAtomicXor = 407, // SPIRVInstrInfo.td:694
423 OpBitCount = 408, // SPIRVInstrInfo.td:558
424 OpBitFieldInsert = 409, // SPIRVInstrInfo.td:548
425 OpBitFieldSExtract = 410, // SPIRVInstrInfo.td:551
426 OpBitFieldUExtract = 411, // SPIRVInstrInfo.td:554
427 OpBitReverse = 412, // SPIRVInstrInfo.td:557
428 OpBitcast = 413, // SPIRVInstrInfo.td:442
429 OpBitwiseAndS = 414, // SPIRVInstrInfo.td:48
430 OpBitwiseAndV = 415, // SPIRVInstrInfo.td:53
431 OpBitwiseFunctionINTEL = 416, // SPIRVInstrInfo.td:983
432 OpBitwiseOrS = 417, // SPIRVInstrInfo.td:48
433 OpBitwiseOrV = 418, // SPIRVInstrInfo.td:53
434 OpBitwiseXorS = 419, // SPIRVInstrInfo.td:48
435 OpBitwiseXorV = 420, // SPIRVInstrInfo.td:53
436 OpBranch = 421, // SPIRVInstrInfo.td:638
437 OpBranchConditional = 422, // SPIRVInstrInfo.td:639
438 OpBuildNDRange = 423, // SPIRVInstrInfo.td:774
439 OpCapability = 424, // SPIRVInstrInfo.td:164
440 OpCaptureEventProfilingInfo = 425, // SPIRVInstrInfo.td:769
441 OpCommitReadPipe = 426, // SPIRVInstrInfo.td:791
442 OpCommitWritePipe = 427, // SPIRVInstrInfo.td:793
443 OpCompositeConstruct = 428, // SPIRVInstrInfo.td:463
444 OpCompositeConstructContinuedINTEL = 429, // SPIRVInstrInfo.td:465
445 OpCompositeExtract = 430, // SPIRVInstrInfo.td:467
446 OpCompositeInsert = 431, // SPIRVInstrInfo.td:469
447 OpConstantComposite = 432, // SPIRVInstrInfo.td:234
448 OpConstantCompositeContinuedINTEL = 433, // SPIRVInstrInfo.td:236
449 OpConstantF = 434, // SPIRVInstrInfo.td:222
450 OpConstantFalse = 435, // SPIRVInstrInfo.td:231
451 OpConstantFunctionPointerINTEL = 436, // SPIRVInstrInfo.td:873
452 OpConstantI = 437, // SPIRVInstrInfo.td:220
453 OpConstantNull = 438, // SPIRVInstrInfo.td:242
454 OpConstantSampler = 439, // SPIRVInstrInfo.td:239
455 OpConstantTrue = 440, // SPIRVInstrInfo.td:229
456 OpControlBarrier = 441, // SPIRVInstrInfo.td:713
457 OpControlBarrierArriveINTEL = 442, // SPIRVInstrInfo.td:722
458 OpControlBarrierWaitINTEL = 443, // SPIRVInstrInfo.td:724
459 OpConvertBF16ToFINTEL = 444, // SPIRVInstrInfo.td:450
460 OpConvertFToBF16INTEL = 445, // SPIRVInstrInfo.td:449
461 OpConvertFToS = 446, // SPIRVInstrInfo.td:422
462 OpConvertFToU = 447, // SPIRVInstrInfo.td:421
463 OpConvertHandleToImageINTEL = 448, // SPIRVInstrInfo.td:967
464 OpConvertHandleToSampledImageINTEL = 449, // SPIRVInstrInfo.td:971
465 OpConvertHandleToSamplerINTEL = 450, // SPIRVInstrInfo.td:969
466 OpConvertPtrToU = 451, // SPIRVInstrInfo.td:432
467 OpConvertSToF = 452, // SPIRVInstrInfo.td:423
468 OpConvertUToF = 453, // SPIRVInstrInfo.td:424
469 OpConvertUToPtr = 454, // SPIRVInstrInfo.td:437
470 OpCooperativeMatrixConstructCheckedINTEL = 455, // SPIRVInstrInfo.td:952
471 OpCooperativeMatrixGetElementCoordINTEL = 456, // SPIRVInstrInfo.td:955
472 OpCooperativeMatrixLengthKHR = 457, // SPIRVInstrInfo.td:942
473 OpCooperativeMatrixLoadCheckedINTEL = 458, // SPIRVInstrInfo.td:946
474 OpCooperativeMatrixLoadKHR = 459, // SPIRVInstrInfo.td:933
475 OpCooperativeMatrixMulAddKHR = 460, // SPIRVInstrInfo.td:939
476 OpCooperativeMatrixPrefetchINTEL = 461, // SPIRVInstrInfo.td:958
477 OpCooperativeMatrixStoreCheckedINTEL = 462, // SPIRVInstrInfo.td:949
478 OpCooperativeMatrixStoreKHR = 463, // SPIRVInstrInfo.td:936
479 OpCopyLogical = 464, // SPIRVInstrInfo.td:473
480 OpCopyMemory = 465, // SPIRVInstrInfo.td:266
481 OpCopyMemorySized = 466, // SPIRVInstrInfo.td:268
482 OpCopyObject = 467, // SPIRVInstrInfo.td:471
483 OpCreateUserEvent = 468, // SPIRVInstrInfo.td:763
484 OpCrossWorkgroupCastToPtrINTEL = 469, // SPIRVInstrInfo.td:446
485 OpDPdx = 470, // SPIRVInstrInfo.td:614
486 OpDPdxCoarse = 471, // SPIRVInstrInfo.td:622
487 OpDPdxFine = 472, // SPIRVInstrInfo.td:618
488 OpDPdy = 473, // SPIRVInstrInfo.td:615
489 OpDPdyCoarse = 474, // SPIRVInstrInfo.td:623
490 OpDPdyFine = 475, // SPIRVInstrInfo.td:619
491 OpDecorate = 476, // SPIRVInstrInfo.td:128
492 OpDecorateId = 477, // SPIRVInstrInfo.td:136
493 OpDecorateString = 478, // SPIRVInstrInfo.td:138
494 OpDemoteToHelperInvocation = 479, // SPIRVInstrInfo.td:653
495 OpDot = 480, // SPIRVInstrInfo.td:514
496 OpEmitStreamVertex = 481, // SPIRVInstrInfo.td:708
497 OpEmitVertex = 482, // SPIRVInstrInfo.td:706
498 OpEndPrimitive = 483, // SPIRVInstrInfo.td:707
499 OpEndStreamPrimitive = 484, // SPIRVInstrInfo.td:709
500 OpEnqueueKernel = 485, // SPIRVInstrInfo.td:758
501 OpEntryPoint = 486, // SPIRVInstrInfo.td:159
502 OpExecutionMode = 487, // SPIRVInstrInfo.td:162
503 OpExecutionModeId = 488, // SPIRVInstrInfo.td:165
504 OpExpectKHR = 489, // SPIRVInstrInfo.td:107
505 OpExtInst = 490, // SPIRVInstrInfo.td:153
506 OpExtInstImport = 491, // SPIRVInstrInfo.td:147
507 OpExtension = 492, // SPIRVInstrInfo.td:146
508 OpFAddS = 493, // SPIRVInstrInfo.td:46
509 OpFAddV = 494, // SPIRVInstrInfo.td:51
510 OpFConvert = 495, // SPIRVInstrInfo.td:428
511 OpFDivS = 496, // SPIRVInstrInfo.td:46
512 OpFDivV = 497, // SPIRVInstrInfo.td:51
513 OpFMod = 498, // SPIRVInstrInfo.td:505
514 OpFMulS = 499, // SPIRVInstrInfo.td:46
515 OpFMulV = 500, // SPIRVInstrInfo.td:51
516 OpFNegate = 501, // SPIRVInstrInfo.td:478
517 OpFNegateV = 502, // SPIRVInstrInfo.td:479
518 OpFOrdEqual = 503, // SPIRVInstrInfo.td:597
519 OpFOrdGreaterThan = 504, // SPIRVInstrInfo.td:604
520 OpFOrdGreaterThanEqual = 505, // SPIRVInstrInfo.td:609
521 OpFOrdLessThan = 506, // SPIRVInstrInfo.td:602
522 OpFOrdLessThanEqual = 507, // SPIRVInstrInfo.td:607
523 OpFOrdNotEqual = 508, // SPIRVInstrInfo.td:599
524 OpFRemS = 509, // SPIRVInstrInfo.td:46
525 OpFRemV = 510, // SPIRVInstrInfo.td:51
526 OpFSubS = 511, // SPIRVInstrInfo.td:46
527 OpFSubV = 512, // SPIRVInstrInfo.td:51
528 OpFUnordEqual = 513, // SPIRVInstrInfo.td:598
529 OpFUnordGreaterThan = 514, // SPIRVInstrInfo.td:605
530 OpFUnordGreaterThanEqual = 515, // SPIRVInstrInfo.td:610
531 OpFUnordLessThan = 516, // SPIRVInstrInfo.td:603
532 OpFUnordLessThanEqual = 517, // SPIRVInstrInfo.td:608
533 OpFUnordNotEqual = 518, // SPIRVInstrInfo.td:600
534 OpFixedCosALTERA = 519, // SPIRVInstrInfo.td:1127
535 OpFixedCosPiALTERA = 520, // SPIRVInstrInfo.td:1133
536 OpFixedExpALTERA = 521, // SPIRVInstrInfo.td:1139
537 OpFixedLogALTERA = 522, // SPIRVInstrInfo.td:1137
538 OpFixedRecipALTERA = 523, // SPIRVInstrInfo.td:1121
539 OpFixedRsqrtALTERA = 524, // SPIRVInstrInfo.td:1123
540 OpFixedSinALTERA = 525, // SPIRVInstrInfo.td:1125
541 OpFixedSinCosALTERA = 526, // SPIRVInstrInfo.td:1129
542 OpFixedSinCosPiALTERA = 527, // SPIRVInstrInfo.td:1135
543 OpFixedSinPiALTERA = 528, // SPIRVInstrInfo.td:1131
544 OpFixedSqrtALTERA = 529, // SPIRVInstrInfo.td:1119
545 OpFmaKHR = 530, // SPIRVInstrInfo.td:534
546 OpFreezeKHR = 531, // SPIRVInstrInfo.td:103
547 OpFunction = 532, // SPIRVInstrInfo.td:303
548 OpFunctionCall = 533, // SPIRVInstrInfo.td:311
549 OpFunctionEnd = 534, // SPIRVInstrInfo.td:308
550 OpFunctionParameter = 535, // SPIRVInstrInfo.td:306
551 OpFunctionPointerCallINTEL = 536, // SPIRVInstrInfo.td:878
552 OpFwidth = 537, // SPIRVInstrInfo.td:616
553 OpFwidthCoarse = 538, // SPIRVInstrInfo.td:624
554 OpFwidthFine = 539, // SPIRVInstrInfo.td:620
555 OpGenericCastToPtr = 540, // SPIRVInstrInfo.td:439
556 OpGenericCastToPtrExplicit = 541, // SPIRVInstrInfo.td:440
557 OpGenericPtrMemSemantics = 542, // SPIRVInstrInfo.td:280
558 OpGetDefaultQueue = 543, // SPIRVInstrInfo.td:772
559 OpGetMaxPipePackets = 544, // SPIRVInstrInfo.td:799
560 OpGetNumPipePackets = 545, // SPIRVInstrInfo.td:797
561 OpGroupAll = 546, // SPIRVInstrInfo.td:734
562 OpGroupAny = 547, // SPIRVInstrInfo.td:736
563 OpGroupAsyncCopy = 548, // SPIRVInstrInfo.td:729
564 OpGroupBitwiseAndKHR = 549, // SPIRVInstrInfo.td:911
565 OpGroupBitwiseOrKHR = 550, // SPIRVInstrInfo.td:913
566 OpGroupBitwiseXorKHR = 551, // SPIRVInstrInfo.td:915
567 OpGroupBroadcast = 552, // SPIRVInstrInfo.td:738
568 OpGroupCommitReadPipe = 553, // SPIRVInstrInfo.td:805
569 OpGroupCommitWritePipe = 554, // SPIRVInstrInfo.td:807
570 OpGroupFAdd = 555, // SPIRVInstrInfo.td:745
571 OpGroupFMax = 556, // SPIRVInstrInfo.td:749
572 OpGroupFMin = 557, // SPIRVInstrInfo.td:746
573 OpGroupFMulKHR = 558, // SPIRVInstrInfo.td:909
574 OpGroupIAdd = 559, // SPIRVInstrInfo.td:744
575 OpGroupIMulKHR = 560, // SPIRVInstrInfo.td:907
576 OpGroupLogicalAndKHR = 561, // SPIRVInstrInfo.td:917
577 OpGroupLogicalOrKHR = 562, // SPIRVInstrInfo.td:919
578 OpGroupLogicalXorKHR = 563, // SPIRVInstrInfo.td:921
579 OpGroupNonUniformAll = 564, // SPIRVInstrInfo.td:820
580 OpGroupNonUniformAllEqual = 565, // SPIRVInstrInfo.td:822
581 OpGroupNonUniformAny = 566, // SPIRVInstrInfo.td:821
582 OpGroupNonUniformBallot = 567, // SPIRVInstrInfo.td:825
583 OpGroupNonUniformBallotBitCount = 568, // SPIRVInstrInfo.td:828
584 OpGroupNonUniformBallotBitExtract = 569, // SPIRVInstrInfo.td:827
585 OpGroupNonUniformBallotFindLSB = 570, // SPIRVInstrInfo.td:832
586 OpGroupNonUniformBallotFindMSB = 571, // SPIRVInstrInfo.td:833
587 OpGroupNonUniformBitwiseAnd = 572, // SPIRVInstrInfo.td:852
588 OpGroupNonUniformBitwiseOr = 573, // SPIRVInstrInfo.td:853
589 OpGroupNonUniformBitwiseXor = 574, // SPIRVInstrInfo.td:854
590 OpGroupNonUniformBroadcast = 575, // SPIRVInstrInfo.td:823
591 OpGroupNonUniformBroadcastFirst = 576, // SPIRVInstrInfo.td:824
592 OpGroupNonUniformElect = 577, // SPIRVInstrInfo.td:812
593 OpGroupNonUniformFAdd = 578, // SPIRVInstrInfo.td:843
594 OpGroupNonUniformFMax = 579, // SPIRVInstrInfo.td:851
595 OpGroupNonUniformFMin = 580, // SPIRVInstrInfo.td:848
596 OpGroupNonUniformFMul = 581, // SPIRVInstrInfo.td:845
597 OpGroupNonUniformIAdd = 582, // SPIRVInstrInfo.td:842
598 OpGroupNonUniformIMul = 583, // SPIRVInstrInfo.td:844
599 OpGroupNonUniformInverseBallot = 584, // SPIRVInstrInfo.td:826
600 OpGroupNonUniformLogicalAnd = 585, // SPIRVInstrInfo.td:855
601 OpGroupNonUniformLogicalOr = 586, // SPIRVInstrInfo.td:856
602 OpGroupNonUniformLogicalXor = 587, // SPIRVInstrInfo.td:857
603 OpGroupNonUniformQuadSwap = 588, // SPIRVInstrInfo.td:858
604 OpGroupNonUniformRotateKHR = 589, // SPIRVInstrInfo.td:861
605 OpGroupNonUniformSMax = 590, // SPIRVInstrInfo.td:849
606 OpGroupNonUniformSMin = 591, // SPIRVInstrInfo.td:846
607 OpGroupNonUniformShuffle = 592, // SPIRVInstrInfo.td:834
608 OpGroupNonUniformShuffleDown = 593, // SPIRVInstrInfo.td:837
609 OpGroupNonUniformShuffleUp = 594, // SPIRVInstrInfo.td:836
610 OpGroupNonUniformShuffleXor = 595, // SPIRVInstrInfo.td:835
611 OpGroupNonUniformUMax = 596, // SPIRVInstrInfo.td:850
612 OpGroupNonUniformUMin = 597, // SPIRVInstrInfo.td:847
613 OpGroupReserveReadPipePackets = 598, // SPIRVInstrInfo.td:801
614 OpGroupReserveWritePipePackets = 599, // SPIRVInstrInfo.td:803
615 OpGroupSMax = 600, // SPIRVInstrInfo.td:751
616 OpGroupSMin = 601, // SPIRVInstrInfo.td:748
617 OpGroupUMax = 602, // SPIRVInstrInfo.td:750
618 OpGroupUMin = 603, // SPIRVInstrInfo.td:747
619 OpGroupWaitEvents = 604, // SPIRVInstrInfo.td:732
620 OpIAddCarryS = 605, // SPIRVInstrInfo.td:48
621 OpIAddCarryV = 606, // SPIRVInstrInfo.td:53
622 OpIAddS = 607, // SPIRVInstrInfo.td:48
623 OpIAddV = 608, // SPIRVInstrInfo.td:53
624 OpIEqual = 609, // SPIRVInstrInfo.td:585
625 OpIMulS = 610, // SPIRVInstrInfo.td:48
626 OpIMulV = 611, // SPIRVInstrInfo.td:53
627 OpINotEqual = 612, // SPIRVInstrInfo.td:586
628 OpISubBorrowS = 613, // SPIRVInstrInfo.td:48
629 OpISubBorrowV = 614, // SPIRVInstrInfo.td:53
630 OpISubS = 615, // SPIRVInstrInfo.td:48
631 OpISubV = 616, // SPIRVInstrInfo.td:53
632 OpImage = 617, // SPIRVInstrInfo.td:362
633 OpImageDrefGather = 618, // SPIRVInstrInfo.td:352
634 OpImageFetch = 619, // SPIRVInstrInfo.td:346
635 OpImageGather = 620, // SPIRVInstrInfo.td:349
636 OpImageQueryFormat = 621, // SPIRVInstrInfo.td:363
637 OpImageQueryLevels = 622, // SPIRVInstrInfo.td:368
638 OpImageQueryLod = 623, // SPIRVInstrInfo.td:367
639 OpImageQueryOrder = 624, // SPIRVInstrInfo.td:364
640 OpImageQuerySamples = 625, // SPIRVInstrInfo.td:369
641 OpImageQuerySize = 626, // SPIRVInstrInfo.td:366
642 OpImageQuerySizeLod = 627, // SPIRVInstrInfo.td:365
643 OpImageRead = 628, // SPIRVInstrInfo.td:356
644 OpImageSampleDrefExplicitLod = 629, // SPIRVInstrInfo.td:328
645 OpImageSampleDrefImplicitLod = 630, // SPIRVInstrInfo.td:325
646 OpImageSampleExplicitLod = 631, // SPIRVInstrInfo.td:321
647 OpImageSampleFootprintNV = 632, // SPIRVInstrInfo.td:415
648 OpImageSampleImplicitLod = 633, // SPIRVInstrInfo.td:318
649 OpImageSampleProjDrefExplicitLod = 634, // SPIRVInstrInfo.td:342
650 OpImageSampleProjDrefImplicitLod = 635, // SPIRVInstrInfo.td:339
651 OpImageSampleProjExplicitLod = 636, // SPIRVInstrInfo.td:335
652 OpImageSampleProjImplicitLod = 637, // SPIRVInstrInfo.td:332
653 OpImageSparseDrefGather = 638, // SPIRVInstrInfo.td:405
654 OpImageSparseFetch = 639, // SPIRVInstrInfo.td:399
655 OpImageSparseGather = 640, // SPIRVInstrInfo.td:402
656 OpImageSparseRead = 641, // SPIRVInstrInfo.td:411
657 OpImageSparseSampleDrefExplicitLod = 642, // SPIRVInstrInfo.td:381
658 OpImageSparseSampleDrefImplicitLod = 643, // SPIRVInstrInfo.td:378
659 OpImageSparseSampleExplicitLod = 644, // SPIRVInstrInfo.td:374
660 OpImageSparseSampleImplicitLod = 645, // SPIRVInstrInfo.td:371
661 OpImageSparseSampleProjDrefExplicitLod = 646, // SPIRVInstrInfo.td:395
662 OpImageSparseSampleProjDrefImplicitLod = 647, // SPIRVInstrInfo.td:392
663 OpImageSparseSampleProjExplicitLod = 648, // SPIRVInstrInfo.td:388
664 OpImageSparseSampleProjImplicitLod = 649, // SPIRVInstrInfo.td:385
665 OpImageSparseTexelsResident = 650, // SPIRVInstrInfo.td:409
666 OpImageTexelPointer = 651, // SPIRVInstrInfo.td:259
667 OpImageWrite = 652, // SPIRVInstrInfo.td:359
668 OpInBoundsAccessChain = 653, // SPIRVInstrInfo.td:272
669 OpInBoundsPtrAccessChain = 654, // SPIRVInstrInfo.td:282
670 OpIsFinite = 655, // SPIRVInstrInfo.td:569
671 OpIsInf = 656, // SPIRVInstrInfo.td:568
672 OpIsNan = 657, // SPIRVInstrInfo.td:567
673 OpIsNormal = 658, // SPIRVInstrInfo.td:570
674 OpIsValidEvent = 659, // SPIRVInstrInfo.td:765
675 OpIsValidReserveId = 660, // SPIRVInstrInfo.td:795
676 OpKill = 661, // SPIRVInstrInfo.td:644
677 OpLabel = 662, // SPIRVInstrInfo.td:636
678 OpLessOrGreater = 663, // SPIRVInstrInfo.td:573
679 OpLifetimeStart = 664, // SPIRVInstrInfo.td:651
680 OpLifetimeStop = 665, // SPIRVInstrInfo.td:652
681 OpLine = 666, // SPIRVInstrInfo.td:121
682 OpLoad = 667, // SPIRVInstrInfo.td:262
683 OpLogicalAnd = 668, // SPIRVInstrInfo.td:580
684 OpLogicalEqual = 669, // SPIRVInstrInfo.td:577
685 OpLogicalNot = 670, // SPIRVInstrInfo.td:581
686 OpLogicalNotEqual = 671, // SPIRVInstrInfo.td:578
687 OpLogicalOr = 672, // SPIRVInstrInfo.td:579
688 OpLoopControlINTEL = 673, // SPIRVInstrInfo.td:632
689 OpLoopMerge = 674, // SPIRVInstrInfo.td:630
690 OpMaskedGatherINTEL = 675, // SPIRVInstrInfo.td:1143
691 OpMaskedScatterINTEL = 676, // SPIRVInstrInfo.td:1145
692 OpMatrixTimesMatrix = 677, // SPIRVInstrInfo.td:511
693 OpMatrixTimesScalar = 678, // SPIRVInstrInfo.td:508
694 OpMatrixTimesVector = 679, // SPIRVInstrInfo.td:510
695 OpMemberDecorate = 680, // SPIRVInstrInfo.td:130
696 OpMemberDecorateString = 681, // SPIRVInstrInfo.td:140
697 OpMemberName = 682, // SPIRVInstrInfo.td:118
698 OpMemoryBarrier = 683, // SPIRVInstrInfo.td:715
699 OpMemoryModel = 684, // SPIRVInstrInfo.td:157
700 OpMemoryNamedBarrier = 685, // SPIRVInstrInfo.td:718
701 OpModuleProcessed = 686, // SPIRVInstrInfo.td:123
702 OpName = 687, // SPIRVInstrInfo.td:117
703 OpNamedBarrierInitialize = 688, // SPIRVInstrInfo.td:717
704 OpNoLine = 689, // SPIRVInstrInfo.td:122
705 OpNop = 690, // SPIRVInstrInfo.td:97
706 OpNot = 691, // SPIRVInstrInfo.td:546
707 OpOrdered = 692, // SPIRVInstrInfo.td:574
708 OpOuterProduct = 693, // SPIRVInstrInfo.td:513
709 OpPhi = 694, // SPIRVInstrInfo.td:628
710 OpPoisonKHR = 695, // SPIRVInstrInfo.td:102
711 OpPredicatedLoadINTEL = 696, // SPIRVInstrInfo.td:1107
712 OpPredicatedStoreINTEL = 697, // SPIRVInstrInfo.td:1109
713 OpPtrAccessChain = 698, // SPIRVInstrInfo.td:275
714 OpPtrCastToCrossWorkgroupINTEL = 699, // SPIRVInstrInfo.td:445
715 OpPtrCastToGeneric = 700, // SPIRVInstrInfo.td:438
716 OpPtrDiff = 701, // SPIRVInstrInfo.td:289
717 OpPtrEqual = 702, // SPIRVInstrInfo.td:285
718 OpPtrNotEqual = 703, // SPIRVInstrInfo.td:287
719 OpQuantizeToF16 = 704, // SPIRVInstrInfo.td:430
720 OpReadClockKHR = 705, // SPIRVInstrInfo.td:866
721 OpReadPipe = 706, // SPIRVInstrInfo.td:779
722 OpReadPipeBlockingALTERA = 707, // SPIRVInstrInfo.td:1113
723 OpReleaseEvent = 708, // SPIRVInstrInfo.td:762
724 OpReserveReadPipePackets = 709, // SPIRVInstrInfo.td:787
725 OpReserveWritePipePackets = 710, // SPIRVInstrInfo.td:789
726 OpReservedReadPipe = 711, // SPIRVInstrInfo.td:783
727 OpReservedWritePipe = 712, // SPIRVInstrInfo.td:785
728 OpRestoreMemoryINTEL = 713, // SPIRVInstrInfo.td:298
729 OpRetainEvent = 714, // SPIRVInstrInfo.td:761
730 OpReturn = 715, // SPIRVInstrInfo.td:645
731 OpReturnValue = 716, // SPIRVInstrInfo.td:646
732 OpRoundFToTF32INTEL = 717, // SPIRVInstrInfo.td:453
733 OpSConvert = 718, // SPIRVInstrInfo.td:427
734 OpSDivS = 719, // SPIRVInstrInfo.td:48
735 OpSDivV = 720, // SPIRVInstrInfo.td:53
736 OpSDot = 721, // SPIRVInstrInfo.td:521
737 OpSDotAccSat = 722, // SPIRVInstrInfo.td:527
738 OpSGreaterThan = 723, // SPIRVInstrInfo.td:589
739 OpSGreaterThanEqual = 724, // SPIRVInstrInfo.td:591
740 OpSLessThan = 725, // SPIRVInstrInfo.td:593
741 OpSLessThanEqual = 726, // SPIRVInstrInfo.td:595
742 OpSMod = 727, // SPIRVInstrInfo.td:500
743 OpSMulExtended = 728, // SPIRVInstrInfo.td:519
744 OpSNegate = 729, // SPIRVInstrInfo.td:477
745 OpSRemS = 730, // SPIRVInstrInfo.td:48
746 OpSRemV = 731, // SPIRVInstrInfo.td:53
747 OpSUDot = 732, // SPIRVInstrInfo.td:525
748 OpSUDotAccSat = 733, // SPIRVInstrInfo.td:531
749 OpSampledImage = 734, // SPIRVInstrInfo.td:316
750 OpSatConvertSToU = 735, // SPIRVInstrInfo.td:434
751 OpSatConvertUToS = 736, // SPIRVInstrInfo.td:435
752 OpSaveMemoryINTEL = 737, // SPIRVInstrInfo.td:296
753 OpSelectSFSCond = 738, // SPIRVInstrInfo.td:67
754 OpSelectSFVCond = 739, // SPIRVInstrInfo.td:68
755 OpSelectSISCond = 740, // SPIRVInstrInfo.td:63
756 OpSelectSIVCond = 741, // SPIRVInstrInfo.td:64
757 OpSelectSPSCond = 742, // SPIRVInstrInfo.td:59
758 OpSelectSPVCond = 743, // SPIRVInstrInfo.td:60
759 OpSelectVFSCond = 744, // SPIRVInstrInfo.td:80
760 OpSelectVFVCond = 745, // SPIRVInstrInfo.td:81
761 OpSelectVISCond = 746, // SPIRVInstrInfo.td:76
762 OpSelectVIVCond = 747, // SPIRVInstrInfo.td:77
763 OpSelectVPSCond = 748, // SPIRVInstrInfo.td:72
764 OpSelectVPVCond = 749, // SPIRVInstrInfo.td:73
765 OpSelectionMerge = 750, // SPIRVInstrInfo.td:634
766 OpSetUserEventStatus = 751, // SPIRVInstrInfo.td:767
767 OpShiftLeftLogicalS = 752, // SPIRVInstrInfo.td:48
768 OpShiftLeftLogicalV = 753, // SPIRVInstrInfo.td:53
769 OpShiftRightArithmeticS = 754, // SPIRVInstrInfo.td:48
770 OpShiftRightArithmeticV = 755, // SPIRVInstrInfo.td:53
771 OpShiftRightLogicalS = 756, // SPIRVInstrInfo.td:48
772 OpShiftRightLogicalV = 757, // SPIRVInstrInfo.td:53
773 OpSignBitSet = 758, // SPIRVInstrInfo.td:571
774 OpSizeOf = 759, // SPIRVInstrInfo.td:99
775 OpSource = 760, // SPIRVInstrInfo.td:113
776 OpSourceContinued = 761, // SPIRVInstrInfo.td:111
777 OpSourceExtension = 762, // SPIRVInstrInfo.td:115
778 OpSpecConstant = 763, // SPIRVInstrInfo.td:246
779 OpSpecConstantComposite = 764, // SPIRVInstrInfo.td:248
780 OpSpecConstantCompositeContinuedINTEL = 765, // SPIRVInstrInfo.td:250
781 OpSpecConstantFalse = 766, // SPIRVInstrInfo.td:245
782 OpSpecConstantOp = 767, // SPIRVInstrInfo.td:252
783 OpSpecConstantTrue = 768, // SPIRVInstrInfo.td:244
784 OpStore = 769, // SPIRVInstrInfo.td:264
785 OpStrictFAddS = 770, // SPIRVInstrInfo.td:46
786 OpStrictFAddV = 771, // SPIRVInstrInfo.td:51
787 OpStrictFDivS = 772, // SPIRVInstrInfo.td:46
788 OpStrictFDivV = 773, // SPIRVInstrInfo.td:51
789 OpStrictFMulS = 774, // SPIRVInstrInfo.td:46
790 OpStrictFMulV = 775, // SPIRVInstrInfo.td:51
791 OpStrictFRemS = 776, // SPIRVInstrInfo.td:46
792 OpStrictFRemV = 777, // SPIRVInstrInfo.td:51
793 OpStrictFSubS = 778, // SPIRVInstrInfo.td:46
794 OpStrictFSubV = 779, // SPIRVInstrInfo.td:51
795 OpString = 780, // SPIRVInstrInfo.td:120
796 OpSubgroup2DBlockLoadINTEL = 781, // SPIRVInstrInfo.td:1090
797 OpSubgroup2DBlockLoadTransformINTEL = 782, // SPIRVInstrInfo.td:1096
798 OpSubgroup2DBlockLoadTransposeINTEL = 783, // SPIRVInstrInfo.td:1093
799 OpSubgroup2DBlockPrefetchINTEL = 784, // SPIRVInstrInfo.td:1099
800 OpSubgroup2DBlockStoreINTEL = 785, // SPIRVInstrInfo.td:1102
801 OpSubgroupBlockReadINTEL = 786, // SPIRVInstrInfo.td:891
802 OpSubgroupBlockWriteINTEL = 787, // SPIRVInstrInfo.td:893
803 OpSubgroupImageBlockReadINTEL = 788, // SPIRVInstrInfo.td:895
804 OpSubgroupImageBlockWriteINTEL = 789, // SPIRVInstrInfo.td:897
805 OpSubgroupImageMediaBlockReadINTEL = 790, // SPIRVInstrInfo.td:901
806 OpSubgroupImageMediaBlockWriteINTEL = 791, // SPIRVInstrInfo.td:903
807 OpSubgroupMatrixMultiplyAccumulateINTEL = 792, // SPIRVInstrInfo.td:753
808 OpSubgroupShuffleDownINTEL = 793, // SPIRVInstrInfo.td:885
809 OpSubgroupShuffleINTEL = 794, // SPIRVInstrInfo.td:883
810 OpSubgroupShuffleUpINTEL = 795, // SPIRVInstrInfo.td:887
811 OpSubgroupShuffleXorINTEL = 796, // SPIRVInstrInfo.td:889
812 OpSwitch = 797, // SPIRVInstrInfo.td:641
813 OpTranspose = 798, // SPIRVInstrInfo.td:472
814 OpTypeAccelerationStructureNV = 799, // SPIRVInstrInfo.td:208
815 OpTypeArray = 800, // SPIRVInstrInfo.td:186
816 OpTypeBool = 801, // SPIRVInstrInfo.td:171
817 OpTypeCooperativeMatrixKHR = 802, // SPIRVInstrInfo.td:213
818 OpTypeCooperativeMatrixNV = 803, // SPIRVInstrInfo.td:210
819 OpTypeDeviceEvent = 804, // SPIRVInstrInfo.td:200
820 OpTypeEvent = 805, // SPIRVInstrInfo.td:199
821 OpTypeFloat = 806, // SPIRVInstrInfo.td:174
822 OpTypeForwardPointer = 807, // SPIRVInstrInfo.td:204
823 OpTypeFunction = 808, // SPIRVInstrInfo.td:197
824 OpTypeImage = 809, // SPIRVInstrInfo.td:180
825 OpTypeInt = 810, // SPIRVInstrInfo.td:172
826 OpTypeMatrix = 811, // SPIRVInstrInfo.td:178
827 OpTypeNamedBarrier = 812, // SPIRVInstrInfo.td:207
828 OpTypeOpaque = 813, // SPIRVInstrInfo.td:193
829 OpTypePipe = 814, // SPIRVInstrInfo.td:203
830 OpTypePipeStorage = 815, // SPIRVInstrInfo.td:206
831 OpTypePointer = 816, // SPIRVInstrInfo.td:195
832 OpTypeQueue = 817, // SPIRVInstrInfo.td:202
833 OpTypeReserveId = 818, // SPIRVInstrInfo.td:201
834 OpTypeRuntimeArray = 819, // SPIRVInstrInfo.td:188
835 OpTypeSampledImage = 820, // SPIRVInstrInfo.td:184
836 OpTypeSampler = 821, // SPIRVInstrInfo.td:183
837 OpTypeStruct = 822, // SPIRVInstrInfo.td:190
838 OpTypeStructContinuedINTEL = 823, // SPIRVInstrInfo.td:191
839 OpTypeVector = 824, // SPIRVInstrInfo.td:176
840 OpTypeVoid = 825, // SPIRVInstrInfo.td:170
841 OpUConvert = 826, // SPIRVInstrInfo.td:426
842 OpUDivS = 827, // SPIRVInstrInfo.td:48
843 OpUDivV = 828, // SPIRVInstrInfo.td:53
844 OpUDot = 829, // SPIRVInstrInfo.td:523
845 OpUDotAccSat = 830, // SPIRVInstrInfo.td:529
846 OpUGreaterThan = 831, // SPIRVInstrInfo.td:588
847 OpUGreaterThanEqual = 832, // SPIRVInstrInfo.td:590
848 OpULessThan = 833, // SPIRVInstrInfo.td:592
849 OpULessThanEqual = 834, // SPIRVInstrInfo.td:594
850 OpUModS = 835, // SPIRVInstrInfo.td:48
851 OpUModV = 836, // SPIRVInstrInfo.td:53
852 OpUMulExtended = 837, // SPIRVInstrInfo.td:518
853 OpUndef = 838, // SPIRVInstrInfo.td:98
854 OpUnordered = 839, // SPIRVInstrInfo.td:575
855 OpUnreachable = 840, // SPIRVInstrInfo.td:647
856 OpVariable = 841, // SPIRVInstrInfo.td:257
857 OpVariableLengthArrayINTEL = 842, // SPIRVInstrInfo.td:294
858 OpVectorExtractDynamic = 843, // SPIRVInstrInfo.td:457
859 OpVectorInsertDynamic = 844, // SPIRVInstrInfo.td:459
860 OpVectorShuffle = 845, // SPIRVInstrInfo.td:461
861 OpVectorTimesMatrix = 846, // SPIRVInstrInfo.td:509
862 OpVectorTimesScalar = 847, // SPIRVInstrInfo.td:507
863 OpWritePipe = 848, // SPIRVInstrInfo.td:781
864 OpWritePipeBlockingALTERA = 849, // SPIRVInstrInfo.td:1115
865 INSTRUCTION_LIST_END = 850
866 };
867
868} // namespace llvm::SPIRV
869
870#endif // GET_INSTRINFO_ENUM
871
872#ifdef GET_INSTRINFO_SCHED_ENUM
873#undef GET_INSTRINFO_SCHED_ENUM
874
875namespace llvm::SPIRV::Sched {
876
877 enum {
878 NoInstrModel = 0,
879 SCHED_LIST_END = 1
880 };
881
882} // namespace llvm::SPIRV::Sched
883
884#endif // GET_INSTRINFO_SCHED_ENUM
885
886#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
887
888namespace llvm {
889
890struct SPIRVInstrTable {
891 MCInstrDesc Insts[850];
892 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
893 MCPhysReg ImplicitOps[1];
894 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
895 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
896 MCOperandInfo OperandInfo[486];
897};
898} // namespace llvm
899
900#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
901
902#ifdef GET_INSTRINFO_MC_DESC
903#undef GET_INSTRINFO_MC_DESC
904
905namespace llvm {
906
907static_assert((sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
908static constexpr unsigned SPIRVOpInfoBase = (sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) / sizeof(MCOperandInfo);
909
910extern const SPIRVInstrTable SPIRVDescs = {
911 {
912 { 849, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipeBlockingALTERA
913 { 848, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipe
914 { 847, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesScalar
915 { 846, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesMatrix
916 { 845, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorShuffle
917 { 844, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorInsertDynamic
918 { 843, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorExtractDynamic
919 { 842, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariableLengthArrayINTEL
920 { 841, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 483, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariable
921 { 840, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnreachable
922 { 839, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnordered
923 { 838, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUndef
924 { 837, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUMulExtended
925 { 836, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModV
926 { 835, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModS
927 { 834, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThanEqual
928 { 833, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThan
929 { 832, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThanEqual
930 { 831, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThan
931 { 830, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDotAccSat
932 { 829, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDot
933 { 828, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivV
934 { 827, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivS
935 { 826, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUConvert
936 { 825, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVoid
937 { 824, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 477, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVector
938 { 823, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStructContinuedINTEL
939 { 822, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStruct
940 { 821, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampler
941 { 820, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 464, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampledImage
942 { 819, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 464, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeRuntimeArray
943 { 818, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeReserveId
944 { 817, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeQueue
945 { 816, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 480, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePointer
946 { 815, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipeStorage
947 { 814, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipe
948 { 813, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeOpaque
949 { 812, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeNamedBarrier
950 { 811, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 477, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeMatrix
951 { 810, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 474, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeInt
952 { 809, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 466, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeImage
953 { 808, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 464, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFunction
954 { 807, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeForwardPointer
955 { 806, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFloat
956 { 805, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeEvent
957 { 804, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeDeviceEvent
958 { 803, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixNV
959 { 802, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 451, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixKHR
960 { 801, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeBool
961 { 800, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 448, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeArray
962 { 799, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeAccelerationStructureNV
963 { 798, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTranspose
964 { 797, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSwitch
965 { 796, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleXorINTEL
966 { 795, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleUpINTEL
967 { 794, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleINTEL
968 { 793, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleDownINTEL
969 { 792, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupMatrixMultiplyAccumulateINTEL
970 { 791, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockWriteINTEL
971 { 790, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockReadINTEL
972 { 789, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockWriteINTEL
973 { 788, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockReadINTEL
974 { 787, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockWriteINTEL
975 { 786, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockReadINTEL
976 { 785, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 428, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockStoreINTEL
977 { 784, 9, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 438, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockPrefetchINTEL
978 { 783, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 428, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransposeINTEL
979 { 782, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 428, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransformINTEL
980 { 781, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 428, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadINTEL
981 { 780, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpString
982 { 779, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubV
983 { 778, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubS
984 { 777, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemV
985 { 776, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemS
986 { 775, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulV
987 { 774, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulS
988 { 773, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivV
989 { 772, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivS
990 { 771, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddV
991 { 770, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddS
992 { 769, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStore
993 { 768, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantTrue
994 { 767, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 424, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantOp
995 { 766, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantFalse
996 { 765, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantCompositeContinuedINTEL
997 { 764, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantComposite
998 { 763, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 421, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstant
999 { 762, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceExtension
1000 { 761, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceContinued
1001 { 760, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSource
1002 { 759, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSizeOf
1003 { 758, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSignBitSet
1004 { 757, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalV
1005 { 756, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalS
1006 { 755, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticV
1007 { 754, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticS
1008 { 753, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalV
1009 { 752, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalS
1010 { 751, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSetUserEventStatus
1011 { 750, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectionMerge
1012 { 749, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 416, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPVCond
1013 { 748, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 411, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPSCond
1014 { 747, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 406, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVIVCond
1015 { 746, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 401, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVISCond
1016 { 745, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 396, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFVCond
1017 { 744, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 391, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFSCond
1018 { 743, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 386, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPVCond
1019 { 742, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 381, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPSCond
1020 { 741, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 376, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSIVCond
1021 { 740, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 371, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSISCond
1022 { 739, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 366, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFVCond
1023 { 738, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 361, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFSCond
1024 { 737, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSaveMemoryINTEL
1025 { 736, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertUToS
1026 { 735, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertSToU
1027 { 734, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSampledImage
1028 { 733, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDotAccSat
1029 { 732, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDot
1030 { 731, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemV
1031 { 730, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemS
1032 { 729, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSNegate
1033 { 728, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMulExtended
1034 { 727, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMod
1035 { 726, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThanEqual
1036 { 725, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThan
1037 { 724, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThanEqual
1038 { 723, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThan
1039 { 722, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDotAccSat
1040 { 721, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDot
1041 { 720, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivV
1042 { 719, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivS
1043 { 718, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSConvert
1044 { 717, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRoundFToTF32INTEL
1045 { 716, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturnValue
1046 { 715, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturn
1047 { 714, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRetainEvent
1048 { 713, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRestoreMemoryINTEL
1049 { 712, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedWritePipe
1050 { 711, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedReadPipe
1051 { 710, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveWritePipePackets
1052 { 709, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveReadPipePackets
1053 { 708, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReleaseEvent
1054 { 707, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipeBlockingALTERA
1055 { 706, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipe
1056 { 705, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadClockKHR
1057 { 704, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpQuantizeToF16
1058 { 703, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrNotEqual
1059 { 702, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrEqual
1060 { 701, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrDiff
1061 { 700, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToGeneric
1062 { 699, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToCrossWorkgroupINTEL
1063 { 698, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrAccessChain
1064 { 697, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedStoreINTEL
1065 { 696, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedLoadINTEL
1066 { 695, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPoisonKHR
1067 { 694, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPhi
1068 { 693, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOuterProduct
1069 { 692, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOrdered
1070 { 691, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNot
1071 { 690, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNop
1072 { 689, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNoLine
1073 { 688, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNamedBarrierInitialize
1074 { 687, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpName
1075 { 686, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpModuleProcessed
1076 { 685, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryNamedBarrier
1077 { 684, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryModel
1078 { 683, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryBarrier
1079 { 682, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 354, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberName
1080 { 681, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 357, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorateString
1081 { 680, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 354, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorate
1082 { 679, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesVector
1083 { 678, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesScalar
1084 { 677, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesMatrix
1085 { 676, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedScatterINTEL
1086 { 675, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedGatherINTEL
1087 { 674, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopMerge
1088 { 673, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopControlINTEL
1089 { 672, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalOr
1090 { 671, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNotEqual
1091 { 670, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNot
1092 { 669, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalEqual
1093 { 668, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalAnd
1094 { 667, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoad
1095 { 666, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 351, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLine
1096 { 665, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStop
1097 { 664, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStart
1098 { 663, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLessOrGreater
1099 { 662, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLabel
1100 { 661, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpKill
1101 { 660, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidReserveId
1102 { 659, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidEvent
1103 { 658, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNormal
1104 { 657, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNan
1105 { 656, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsInf
1106 { 655, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsFinite
1107 { 654, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsPtrAccessChain
1108 { 653, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsAccessChain
1109 { 652, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageWrite
1110 { 651, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageTexelPointer
1111 { 650, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseTexelsResident
1112 { 649, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjImplicitLod
1113 { 648, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjExplicitLod
1114 { 647, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefImplicitLod
1115 { 646, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefExplicitLod
1116 { 645, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleImplicitLod
1117 { 644, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 343, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleExplicitLod
1118 { 643, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefImplicitLod
1119 { 642, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefExplicitLod
1120 { 641, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseRead
1121 { 640, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseGather
1122 { 639, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseFetch
1123 { 638, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseDrefGather
1124 { 637, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjImplicitLod
1125 { 636, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjExplicitLod
1126 { 635, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefImplicitLod
1127 { 634, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefExplicitLod
1128 { 633, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleImplicitLod
1129 { 632, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleFootprintNV
1130 { 631, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 343, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleExplicitLod
1131 { 630, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefImplicitLod
1132 { 629, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefExplicitLod
1133 { 628, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageRead
1134 { 627, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySizeLod
1135 { 626, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySize
1136 { 625, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySamples
1137 { 624, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryOrder
1138 { 623, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLod
1139 { 622, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLevels
1140 { 621, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryFormat
1141 { 620, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageGather
1142 { 619, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageFetch
1143 { 618, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageDrefGather
1144 { 617, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImage
1145 { 616, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubV
1146 { 615, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubS
1147 { 614, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowV
1148 { 613, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowS
1149 { 612, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpINotEqual
1150 { 611, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulV
1151 { 610, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulS
1152 { 609, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIEqual
1153 { 608, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddV
1154 { 607, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddS
1155 { 606, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryV
1156 { 605, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryS
1157 { 604, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupWaitEvents
1158 { 603, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMin
1159 { 602, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMax
1160 { 601, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMin
1161 { 600, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMax
1162 { 599, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveWritePipePackets
1163 { 598, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveReadPipePackets
1164 { 597, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMin
1165 { 596, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMax
1166 { 595, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleXor
1167 { 594, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleUp
1168 { 593, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleDown
1169 { 592, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffle
1170 { 591, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMin
1171 { 590, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMax
1172 { 589, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformRotateKHR
1173 { 588, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformQuadSwap
1174 { 587, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalXor
1175 { 586, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalOr
1176 { 585, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalAnd
1177 { 584, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformInverseBallot
1178 { 583, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIMul
1179 { 582, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIAdd
1180 { 581, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMul
1181 { 580, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMin
1182 { 579, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMax
1183 { 578, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFAdd
1184 { 577, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformElect
1185 { 576, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcastFirst
1186 { 575, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcast
1187 { 574, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseXor
1188 { 573, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseOr
1189 { 572, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseAnd
1190 { 571, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindMSB
1191 { 570, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindLSB
1192 { 569, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitExtract
1193 { 568, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitCount
1194 { 567, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallot
1195 { 566, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAny
1196 { 565, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAllEqual
1197 { 564, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAll
1198 { 563, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalXorKHR
1199 { 562, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalOrKHR
1200 { 561, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalAndKHR
1201 { 560, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIMulKHR
1202 { 559, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIAdd
1203 { 558, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMulKHR
1204 { 557, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMin
1205 { 556, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMax
1206 { 555, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFAdd
1207 { 554, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitWritePipe
1208 { 553, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitReadPipe
1209 { 552, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBroadcast
1210 { 551, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseXorKHR
1211 { 550, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseOrKHR
1212 { 549, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseAndKHR
1213 { 548, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAsyncCopy
1214 { 547, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAny
1215 { 546, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAll
1216 { 545, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetNumPipePackets
1217 { 544, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetMaxPipePackets
1218 { 543, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetDefaultQueue
1219 { 542, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericPtrMemSemantics
1220 { 541, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 317, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtrExplicit
1221 { 540, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtr
1222 { 539, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthFine
1223 { 538, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthCoarse
1224 { 537, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidth
1225 { 536, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionPointerCallINTEL
1226 { 535, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionParameter
1227 { 534, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionEnd
1228 { 533, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionCall
1229 { 532, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 313, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunction
1230 { 531, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFreezeKHR
1231 { 530, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFmaKHR
1232 { 529, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSqrtALTERA
1233 { 528, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinPiALTERA
1234 { 527, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosPiALTERA
1235 { 526, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosALTERA
1236 { 525, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinALTERA
1237 { 524, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRsqrtALTERA
1238 { 523, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRecipALTERA
1239 { 522, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedLogALTERA
1240 { 521, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedExpALTERA
1241 { 520, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosPiALTERA
1242 { 519, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosALTERA
1243 { 518, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordNotEqual
1244 { 517, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThanEqual
1245 { 516, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThan
1246 { 515, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThanEqual
1247 { 514, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThan
1248 { 513, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordEqual
1249 { 512, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubV
1250 { 511, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubS
1251 { 510, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemV
1252 { 509, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemS
1253 { 508, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdNotEqual
1254 { 507, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThanEqual
1255 { 506, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThan
1256 { 505, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThanEqual
1257 { 504, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThan
1258 { 503, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdEqual
1259 { 502, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 310, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegateV
1260 { 501, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegate
1261 { 500, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulV
1262 { 499, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulS
1263 { 498, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMod
1264 { 497, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivV
1265 { 496, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivS
1266 { 495, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFConvert
1267 { 494, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddV
1268 { 493, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddS
1269 { 492, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtension
1270 { 491, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInstImport
1271 { 490, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 298, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInst
1272 { 489, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExpectKHR
1273 { 488, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionModeId
1274 { 487, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionMode
1275 { 486, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 295, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEntryPoint
1276 { 485, 12, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 283, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEnqueueKernel
1277 { 484, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndStreamPrimitive
1278 { 483, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndPrimitive
1279 { 482, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitVertex
1280 { 481, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitStreamVertex
1281 { 480, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDot
1282 { 479, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDemoteToHelperInvocation
1283 { 478, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 280, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateString
1284 { 477, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateId
1285 { 476, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorate
1286 { 475, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyFine
1287 { 474, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyCoarse
1288 { 473, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdy
1289 { 472, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxFine
1290 { 471, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxCoarse
1291 { 470, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdx
1292 { 469, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCrossWorkgroupCastToPtrINTEL
1293 { 468, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCreateUserEvent
1294 { 467, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyObject
1295 { 466, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemorySized
1296 { 465, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemory
1297 { 464, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyLogical
1298 { 463, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreKHR
1299 { 462, 7, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 271, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreCheckedINTEL
1300 { 461, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 266, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixPrefetchINTEL
1301 { 460, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixMulAddKHR
1302 { 459, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadKHR
1303 { 458, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadCheckedINTEL
1304 { 457, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 263, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLengthKHR
1305 { 456, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixGetElementCoordINTEL
1306 { 455, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixConstructCheckedINTEL
1307 { 454, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToPtr
1308 { 453, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToF
1309 { 452, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertSToF
1310 { 451, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertPtrToU
1311 { 450, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSamplerINTEL
1312 { 449, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSampledImageINTEL
1313 { 448, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToImageINTEL
1314 { 447, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToU
1315 { 446, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToS
1316 { 445, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToBF16INTEL
1317 { 444, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertBF16ToFINTEL
1318 { 443, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierWaitINTEL
1319 { 442, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierArriveINTEL
1320 { 441, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrier
1321 { 440, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantTrue
1322 { 439, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantSampler
1323 { 438, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantNull
1324 { 437, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 248, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantI
1325 { 436, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFunctionPointerINTEL
1326 { 435, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFalse
1327 { 434, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantF
1328 { 433, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantCompositeContinuedINTEL
1329 { 432, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantComposite
1330 { 431, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeInsert
1331 { 430, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeExtract
1332 { 429, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstructContinuedINTEL
1333 { 428, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstruct
1334 { 427, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitWritePipe
1335 { 426, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitReadPipe
1336 { 425, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCaptureEventProfilingInfo
1337 { 424, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCapability
1338 { 423, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBuildNDRange
1339 { 422, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 234, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranchConditional
1340 { 421, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranch
1341 { 420, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorV
1342 { 419, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorS
1343 { 418, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrV
1344 { 417, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrS
1345 { 416, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseFunctionINTEL
1346 { 415, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndV
1347 { 414, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndS
1348 { 413, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitcast
1349 { 412, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitReverse
1350 { 411, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldUExtract
1351 { 410, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldSExtract
1352 { 409, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldInsert
1353 { 408, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitCount
1354 { 407, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicXor
1355 { 406, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMin
1356 { 405, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMax
1357 { 404, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicStore
1358 { 403, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMin
1359 { 402, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMax
1360 { 401, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicOr
1361 { 400, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicLoad
1362 { 399, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicISub
1363 { 398, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIIncrement
1364 { 397, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIDecrement
1365 { 396, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIAdd
1366 { 395, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagTestAndSet
1367 { 394, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagClear
1368 { 393, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMinEXT
1369 { 392, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMaxEXT
1370 { 391, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFAddEXT
1371 { 390, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicExchange
1372 { 389, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchangeWeak
1373 { 388, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchange
1374 { 387, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicAnd
1375 { 386, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAssumeTrueKHR
1376 { 385, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmTargetINTEL
1377 { 384, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 192, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmINTEL
1378 { 383, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmCallINTEL
1379 { 382, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 188, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArrayLength
1380 { 381, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArithmeticFenceEXT
1381 { 380, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSubALTERA
1382 { 379, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSqrtALTERA
1383 { 378, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinPiALTERA
1384 { 377, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosPiALTERA
1385 { 376, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosALTERA
1386 { 375, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinALTERA
1387 { 374, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRecipALTERA
1388 { 373, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRSqrtALTERA
1389 { 372, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowRALTERA
1390 { 371, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowNALTERA
1391 { 370, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowALTERA
1392 { 369, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatMulALTERA
1393 { 368, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLogALTERA
1394 { 367, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog2ALTERA
1395 { 366, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog1pALTERA
1396 { 365, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog10ALTERA
1397 { 364, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLTALTERA
1398 { 363, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLEALTERA
1399 { 362, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatHypotALTERA
1400 { 361, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGTALTERA
1401 { 360, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGEALTERA
1402 { 359, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpm1ALTERA
1403 { 358, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpALTERA
1404 { 357, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp2ALTERA
1405 { 356, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp10ALTERA
1406 { 355, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatEQALTERA
1407 { 354, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatDivALTERA
1408 { 353, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosPiALTERA
1409 { 352, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosALTERA
1410 { 351, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCbrtALTERA
1411 { 350, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastToIntALTERA
1412 { 349, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastFromIntALTERA
1413 { 348, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastALTERA
1414 { 347, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatAddALTERA
1415 { 346, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanPiALTERA
1416 { 345, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanALTERA
1417 { 344, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATan2ALTERA
1418 { 343, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinPiALTERA
1419 { 342, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinALTERA
1420 { 341, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosPiALTERA
1421 { 340, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosALTERA
1422 { 339, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAny
1423 { 338, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAll
1424 { 337, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeListDeclINTEL
1425 { 336, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeDeclINTEL
1426 { 335, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasDomainDeclINTEL
1427 { 334, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAccessChain
1428 { 333, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAbortKHR
1429 { 332, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNKNOWN_type
1430 { 331, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASSIGN_TYPE
1431 { 330, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1432 { 329, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1433 { 328, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1434 { 327, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1435 { 326, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1436 { 325, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1437 { 324, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1438 { 323, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1439 { 322, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1440 { 321, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1441 { 320, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1442 { 319, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1443 { 318, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1444 { 317, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1445 { 316, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1446 { 315, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1447 { 314, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1448 { 313, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1449 { 312, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1450 { 311, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1451 { 310, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1452 { 309, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1453 { 308, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
1454 { 307, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1455 { 306, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1456 { 305, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1457 { 304, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1458 { 303, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1459 { 302, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1460 { 301, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1461 { 300, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
1462 { 299, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
1463 { 298, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1464 { 297, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1465 { 296, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1466 { 295, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1467 { 294, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1468 { 293, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1469 { 292, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1470 { 291, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1471 { 290, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1472 { 289, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1473 { 288, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1474 { 287, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1475 { 286, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1476 { 285, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1477 { 284, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1478 { 283, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1479 { 282, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1480 { 281, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1481 { 280, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1482 { 279, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1483 { 278, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1484 { 277, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1485 { 276, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1486 { 275, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1487 { 274, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1488 { 273, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1489 { 272, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1490 { 271, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1491 { 270, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1492 { 269, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1493 { 268, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
1494 { 267, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1495 { 266, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1496 { 265, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1497 { 264, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1498 { 263, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
1499 { 262, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1500 { 261, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
1501 { 260, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1502 { 259, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1503 { 258, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1504 { 257, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1505 { 256, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1506 { 255, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1507 { 254, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1508 { 253, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1509 { 252, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1510 { 251, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1511 { 250, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1512 { 249, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1513 { 248, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1514 { 247, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1515 { 246, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1516 { 245, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1517 { 244, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1518 { 243, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1519 { 242, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1520 { 241, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1521 { 240, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1522 { 239, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1523 { 238, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1524 { 237, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1525 { 236, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1526 { 235, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1527 { 234, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1528 { 233, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1529 { 232, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1530 { 231, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1531 { 230, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1532 { 229, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1533 { 228, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1534 { 227, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1535 { 226, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1536 { 225, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1537 { 224, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1538 { 223, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1539 { 222, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1540 { 221, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1541 { 220, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1542 { 219, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1543 { 218, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1544 { 217, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1545 { 216, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1546 { 215, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1547 { 214, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1548 { 213, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1549 { 212, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1550 { 211, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1551 { 210, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1552 { 209, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1553 { 208, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1554 { 207, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1555 { 206, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1556 { 205, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1557 { 204, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1558 { 203, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1559 { 202, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1560 { 201, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1561 { 200, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1562 { 199, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1563 { 198, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1564 { 197, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1565 { 196, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1566 { 195, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1567 { 194, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1568 { 193, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1569 { 192, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1570 { 191, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1571 { 190, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1572 { 189, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1573 { 188, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1574 { 187, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1575 { 186, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1576 { 185, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1577 { 184, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1578 { 183, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1579 { 182, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1580 { 181, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1581 { 180, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1582 { 179, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1583 { 178, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1584 { 177, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1585 { 176, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1586 { 175, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1587 { 174, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1588 { 173, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1589 { 172, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1590 { 171, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1591 { 170, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1592 { 169, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1593 { 168, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1594 { 167, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1595 { 166, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1596 { 165, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1597 { 164, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1598 { 163, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1599 { 162, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1600 { 161, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1601 { 160, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1602 { 159, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1603 { 158, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1604 { 157, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1605 { 156, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1606 { 155, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1607 { 154, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1608 { 153, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1609 { 152, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1610 { 151, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1611 { 150, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1612 { 149, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1613 { 148, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1614 { 147, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1615 { 146, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1616 { 145, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1617 { 144, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1618 { 143, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1619 { 142, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1620 { 141, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1621 { 140, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1622 { 139, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1623 { 138, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1624 { 137, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1625 { 136, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1626 { 135, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1627 { 134, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1628 { 133, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1629 { 132, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1630 { 131, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1631 { 130, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1632 { 129, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1633 { 128, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1634 { 127, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1635 { 126, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1636 { 125, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1637 { 124, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1638 { 123, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1639 { 122, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1640 { 121, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1641 { 120, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1642 { 119, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1643 { 118, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1644 { 117, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1645 { 116, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1646 { 115, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1647 { 114, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1648 { 113, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1649 { 112, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1650 { 111, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1651 { 110, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1652 { 109, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1653 { 108, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1654 { 107, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1655 { 106, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1656 { 105, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1657 { 104, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1658 { 103, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1659 { 102, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1660 { 101, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1661 { 100, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1662 { 99, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1663 { 98, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1664 { 97, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1665 { 96, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1666 { 95, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1667 { 94, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1668 { 93, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1669 { 92, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1670 { 91, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1671 { 90, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1672 { 89, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1673 { 88, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1674 { 87, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1675 { 86, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1676 { 85, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1677 { 84, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1678 { 83, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1679 { 82, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1680 { 81, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1681 { 80, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1682 { 79, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1683 { 78, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1684 { 77, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1685 { 76, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1686 { 75, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1687 { 74, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1688 { 73, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1689 { 72, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1690 { 71, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1691 { 70, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1692 { 69, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1693 { 68, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1694 { 67, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1695 { 66, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1696 { 65, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1697 { 64, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1698 { 63, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1699 { 62, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1700 { 61, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1701 { 60, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1702 { 59, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1703 { 58, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1704 { 57, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1705 { 56, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1706 { 55, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1707 { 54, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1708 { 53, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1709 { 52, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1710 { 51, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1711 { 50, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1712 { 49, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1713 { 48, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1714 { 47, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1715 { 46, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1716 { 45, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1717 { 44, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1718 { 43, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1719 { 42, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21018
1720 { 41, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21017
1721 { 40, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1722 { 39, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1723 { 38, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1724 { 37, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1725 { 36, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1726 { 35, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1727 { 34, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1728 { 33, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1729 { 32, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21016
1730 { 31, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1731 { 30, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13555
1732 { 29, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1733 { 28, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1734 { 27, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1735 { 26, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1736 { 25, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1737 { 24, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1738 { 23, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1739 { 22, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1740 { 21, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1741 { 20, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1742 { 19, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1743 { 18, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1744 { 17, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1745 { 16, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1746 { 15, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1747 { 14, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1748 { 13, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1749 { 12, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1750 { 11, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1751 { 10, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1752 { 9, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1753 { 8, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1754 { 7, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1755 { 6, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1756 { 5, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1757 { 4, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1758 { 3, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1759 { 2, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1760 { 1, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1761 { 0, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1762 }, {
1763 /* 0 */
1764 }, {
1765 0
1766 }, {
1767 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1768 /* 1 */
1769 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1770 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1771 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1772 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1773 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1774 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1775 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1776 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1777 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1778 /* 28 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1779 /* 29 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1780 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1781 /* 34 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1782 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1783 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1784 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1785 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1786 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1787 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1788 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1789 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1790 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1791 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1792 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1793 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1794 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1795 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1796 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1797 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1798 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1799 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1800 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1801 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1802 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1803 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1804 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1805 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1806 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1807 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1808 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1809 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1810 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1811 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1812 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1813 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1814 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1815 /* 151 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1816 /* 154 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1817 /* 156 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1818 /* 158 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1819 /* 161 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1820 /* 162 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1821 /* 164 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1822 /* 172 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1823 /* 182 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1824 /* 188 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1825 /* 192 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1826 /* 198 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1827 /* 200 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1828 /* 206 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1829 /* 214 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1830 /* 217 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1831 /* 222 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1832 /* 226 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1833 /* 230 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1834 /* 234 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1835 /* 237 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1836 /* 239 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1837 /* 243 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1838 /* 246 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1839 /* 248 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1840 /* 251 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1841 /* 256 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1842 /* 263 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1843 /* 266 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1844 /* 271 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1845 /* 278 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1846 /* 280 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1847 /* 283 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1848 /* 295 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1849 /* 298 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1850 /* 302 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1851 /* 306 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1852 /* 310 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1853 /* 313 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1854 /* 317 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1855 /* 321 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1856 /* 326 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1857 /* 331 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1858 /* 336 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1859 /* 343 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1860 /* 349 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1861 /* 351 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1862 /* 354 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1863 /* 357 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1864 /* 361 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1865 /* 366 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1866 /* 371 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1867 /* 376 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1868 /* 381 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1869 /* 386 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1870 /* 391 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1871 /* 396 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1872 /* 401 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1873 /* 406 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1874 /* 411 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1875 /* 416 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1876 /* 421 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1877 /* 424 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1878 /* 428 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1879 /* 438 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1880 /* 447 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1881 /* 448 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1882 /* 451 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1883 /* 457 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1884 /* 462 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1885 /* 464 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1886 /* 466 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1887 /* 474 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1888 /* 477 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1889 /* 480 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1890 /* 483 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1891 }
1892};
1893
1894
1895#ifdef __GNUC__
1896#pragma GCC diagnostic push
1897#pragma GCC diagnostic ignored "-Woverlength-strings"
1898#endif
1899extern const char SPIRVInstrNameData[] = {
1900 /* 0 */ "G_FLOG10\000"
1901 /* 9 */ "G_FEXP10\000"
1902 /* 18 */ "G_FLOG2\000"
1903 /* 26 */ "G_FATAN2\000"
1904 /* 35 */ "G_FEXP2\000"
1905 /* 43 */ "OpQuantizeToF16\000"
1906 /* 59 */ "G_FMA\000"
1907 /* 65 */ "G_STRICT_FMA\000"
1908 /* 78 */ "OpArbitraryFloatLog10ALTERA\000"
1909 /* 106 */ "OpArbitraryFloatExp10ALTERA\000"
1910 /* 134 */ "OpArbitraryFloatExpm1ALTERA\000"
1911 /* 162 */ "OpArbitraryFloatLog2ALTERA\000"
1912 /* 189 */ "OpArbitraryFloatATan2ALTERA\000"
1913 /* 217 */ "OpArbitraryFloatExp2ALTERA\000"
1914 /* 244 */ "OpArbitraryFloatGEALTERA\000"
1915 /* 269 */ "OpArbitraryFloatLEALTERA\000"
1916 /* 294 */ "OpArbitraryFloatPowNALTERA\000"
1917 /* 321 */ "OpArbitraryFloatEQALTERA\000"
1918 /* 346 */ "OpArbitraryFloatPowRALTERA\000"
1919 /* 373 */ "OpArbitraryFloatGTALTERA\000"
1920 /* 398 */ "OpArbitraryFloatLTALTERA\000"
1921 /* 423 */ "OpArbitraryFloatSubALTERA\000"
1922 /* 449 */ "OpArbitraryFloatAddALTERA\000"
1923 /* 475 */ "OpReadPipeBlockingALTERA\000"
1924 /* 500 */ "OpWritePipeBlockingALTERA\000"
1925 /* 526 */ "OpFixedLogALTERA\000"
1926 /* 543 */ "OpArbitraryFloatLogALTERA\000"
1927 /* 569 */ "OpArbitraryFloatATanPiALTERA\000"
1928 /* 598 */ "OpArbitraryFloatASinPiALTERA\000"
1929 /* 627 */ "OpFixedSinPiALTERA\000"
1930 /* 646 */ "OpArbitraryFloatSinPiALTERA\000"
1931 /* 674 */ "OpArbitraryFloatACosPiALTERA\000"
1932 /* 703 */ "OpFixedCosPiALTERA\000"
1933 /* 722 */ "OpFixedSinCosPiALTERA\000"
1934 /* 744 */ "OpArbitraryFloatSinCosPiALTERA\000"
1935 /* 775 */ "OpArbitraryFloatCosPiALTERA\000"
1936 /* 803 */ "OpArbitraryFloatMulALTERA\000"
1937 /* 829 */ "OpArbitraryFloatATanALTERA\000"
1938 /* 856 */ "OpArbitraryFloatASinALTERA\000"
1939 /* 883 */ "OpFixedSinALTERA\000"
1940 /* 900 */ "OpArbitraryFloatSinALTERA\000"
1941 /* 926 */ "OpArbitraryFloatLog1pALTERA\000"
1942 /* 954 */ "OpFixedRecipALTERA\000"
1943 /* 973 */ "OpArbitraryFloatRecipALTERA\000"
1944 /* 1001 */ "OpFixedExpALTERA\000"
1945 /* 1018 */ "OpArbitraryFloatExpALTERA\000"
1946 /* 1044 */ "OpArbitraryFloatACosALTERA\000"
1947 /* 1071 */ "OpFixedCosALTERA\000"
1948 /* 1088 */ "OpFixedSinCosALTERA\000"
1949 /* 1108 */ "OpArbitraryFloatSinCosALTERA\000"
1950 /* 1137 */ "OpArbitraryFloatCosALTERA\000"
1951 /* 1163 */ "OpArbitraryFloatCastFromIntALTERA\000"
1952 /* 1197 */ "OpArbitraryFloatCastToIntALTERA\000"
1953 /* 1229 */ "OpArbitraryFloatHypotALTERA\000"
1954 /* 1257 */ "OpArbitraryFloatCbrtALTERA\000"
1955 /* 1284 */ "OpArbitraryFloatRSqrtALTERA\000"
1956 /* 1312 */ "OpFixedSqrtALTERA\000"
1957 /* 1330 */ "OpArbitraryFloatSqrtALTERA\000"
1958 /* 1357 */ "OpFixedRsqrtALTERA\000"
1959 /* 1376 */ "OpArbitraryFloatCastALTERA\000"
1960 /* 1403 */ "OpArbitraryFloatDivALTERA\000"
1961 /* 1429 */ "OpArbitraryFloatPowALTERA\000"
1962 /* 1455 */ "OpGroupNonUniformBallotFindLSB\000"
1963 /* 1486 */ "OpGroupNonUniformBallotFindMSB\000"
1964 /* 1517 */ "G_FSUB\000"
1965 /* 1524 */ "G_STRICT_FSUB\000"
1966 /* 1538 */ "G_ATOMICRMW_FSUB\000"
1967 /* 1555 */ "G_SUB\000"
1968 /* 1561 */ "G_ATOMICRMW_SUB\000"
1969 /* 1577 */ "G_INTRINSIC\000"
1970 /* 1589 */ "G_FPTRUNC\000"
1971 /* 1599 */ "G_INTRINSIC_TRUNC\000"
1972 /* 1617 */ "G_TRUNC\000"
1973 /* 1625 */ "G_BUILD_VECTOR_TRUNC\000"
1974 /* 1646 */ "G_DYN_STACKALLOC\000"
1975 /* 1663 */ "G_FMAD\000"
1976 /* 1670 */ "G_FPEXTLOAD\000"
1977 /* 1682 */ "G_INDEXED_SEXTLOAD\000"
1978 /* 1701 */ "G_SEXTLOAD\000"
1979 /* 1712 */ "G_INDEXED_ZEXTLOAD\000"
1980 /* 1731 */ "G_ZEXTLOAD\000"
1981 /* 1742 */ "G_INDEXED_LOAD\000"
1982 /* 1757 */ "G_LOAD\000"
1983 /* 1764 */ "G_VECREDUCE_FADD\000"
1984 /* 1781 */ "G_FADD\000"
1985 /* 1788 */ "G_VECREDUCE_SEQ_FADD\000"
1986 /* 1809 */ "G_STRICT_FADD\000"
1987 /* 1823 */ "G_ATOMICRMW_FADD\000"
1988 /* 1840 */ "G_VECREDUCE_ADD\000"
1989 /* 1856 */ "G_ADD\000"
1990 /* 1862 */ "G_PTR_ADD\000"
1991 /* 1872 */ "G_ATOMICRMW_ADD\000"
1992 /* 1888 */ "G_ATOMICRMW_NAND\000"
1993 /* 1905 */ "G_VECREDUCE_AND\000"
1994 /* 1921 */ "G_AND\000"
1995 /* 1927 */ "G_ATOMICRMW_AND\000"
1996 /* 1943 */ "LIFETIME_END\000"
1997 /* 1956 */ "G_BRCOND\000"
1998 /* 1965 */ "G_ATOMICRMW_USUB_COND\000"
1999 /* 1987 */ "G_LLROUND\000"
2000 /* 1997 */ "G_LROUND\000"
2001 /* 2006 */ "G_INTRINSIC_ROUND\000"
2002 /* 2024 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
2003 /* 2050 */ "LOAD_STACK_GUARD\000"
2004 /* 2067 */ "PSEUDO_PROBE\000"
2005 /* 2080 */ "G_SSUBE\000"
2006 /* 2088 */ "G_USUBE\000"
2007 /* 2096 */ "G_FENCE\000"
2008 /* 2104 */ "ARITH_FENCE\000"
2009 /* 2116 */ "REG_SEQUENCE\000"
2010 /* 2129 */ "G_SADDE\000"
2011 /* 2137 */ "G_UADDE\000"
2012 /* 2145 */ "G_GET_FPMODE\000"
2013 /* 2158 */ "G_RESET_FPMODE\000"
2014 /* 2173 */ "G_SET_FPMODE\000"
2015 /* 2186 */ "G_FMINNUM_IEEE\000"
2016 /* 2201 */ "G_FMAXNUM_IEEE\000"
2017 /* 2216 */ "G_VSCALE\000"
2018 /* 2225 */ "G_JUMP_TABLE\000"
2019 /* 2238 */ "BUNDLE\000"
2020 /* 2245 */ "G_MEMSET_INLINE\000"
2021 /* 2261 */ "G_MEMCPY_INLINE\000"
2022 /* 2277 */ "RELOC_NONE\000"
2023 /* 2288 */ "LOCAL_ESCAPE\000"
2024 /* 2301 */ "ASSIGN_TYPE\000"
2025 /* 2313 */ "G_FPTRUNCSTORE\000"
2026 /* 2328 */ "G_STACKRESTORE\000"
2027 /* 2343 */ "G_INDEXED_STORE\000"
2028 /* 2359 */ "G_STORE\000"
2029 /* 2367 */ "G_BITREVERSE\000"
2030 /* 2380 */ "FAKE_USE\000"
2031 /* 2389 */ "DBG_VALUE\000"
2032 /* 2399 */ "G_GLOBAL_VALUE\000"
2033 /* 2414 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2034 /* 2437 */ "CONVERGENCECTRL_GLUE\000"
2035 /* 2458 */ "G_STACKSAVE\000"
2036 /* 2470 */ "G_MEMMOVE\000"
2037 /* 2480 */ "G_FREEZE\000"
2038 /* 2489 */ "G_FCANONICALIZE\000"
2039 /* 2505 */ "G_FMODF\000"
2040 /* 2513 */ "INIT_UNDEF\000"
2041 /* 2524 */ "G_IMPLICIT_DEF\000"
2042 /* 2539 */ "DBG_INSTR_REF\000"
2043 /* 2553 */ "OpConvertSToF\000"
2044 /* 2567 */ "OpConvertUToF\000"
2045 /* 2581 */ "OpConstantF\000"
2046 /* 2593 */ "G_FNEG\000"
2047 /* 2600 */ "EXTRACT_SUBREG\000"
2048 /* 2615 */ "INSERT_SUBREG\000"
2049 /* 2629 */ "G_SEXT_INREG\000"
2050 /* 2642 */ "SUBREG_TO_REG\000"
2051 /* 2656 */ "G_ATOMIC_CMPXCHG\000"
2052 /* 2673 */ "G_ATOMICRMW_XCHG\000"
2053 /* 2690 */ "G_GET_ROUNDING\000"
2054 /* 2705 */ "G_SET_ROUNDING\000"
2055 /* 2720 */ "G_FLOG\000"
2056 /* 2727 */ "G_VAARG\000"
2057 /* 2735 */ "PREALLOCATED_ARG\000"
2058 /* 2752 */ "G_PREFETCH\000"
2059 /* 2763 */ "G_SMULH\000"
2060 /* 2771 */ "G_UMULH\000"
2061 /* 2779 */ "G_FTANH\000"
2062 /* 2787 */ "G_FSINH\000"
2063 /* 2795 */ "G_FCOSH\000"
2064 /* 2803 */ "DBG_PHI\000"
2065 /* 2811 */ "G_FPTOSI\000"
2066 /* 2820 */ "G_FPTOUI\000"
2067 /* 2829 */ "G_FPOWI\000"
2068 /* 2837 */ "OpConstantI\000"
2069 /* 2849 */ "COPY_LANEMASK\000"
2070 /* 2863 */ "G_PTRMASK\000"
2071 /* 2873 */ "GC_LABEL\000"
2072 /* 2882 */ "DBG_LABEL\000"
2073 /* 2892 */ "EH_LABEL\000"
2074 /* 2901 */ "ANNOTATION_LABEL\000"
2075 /* 2918 */ "ICALL_BRANCH_FUNNEL\000"
2076 /* 2938 */ "OpRoundFToTF32INTEL\000"
2077 /* 2958 */ "OpConvertFToBF16INTEL\000"
2078 /* 2980 */ "OpConvertBF16ToFINTEL\000"
2079 /* 3002 */ "OpSubgroupImageMediaBlockReadINTEL\000"
2080 /* 3037 */ "OpSubgroupImageBlockReadINTEL\000"
2081 /* 3067 */ "OpSubgroupBlockReadINTEL\000"
2082 /* 3092 */ "OpPredicatedLoadINTEL\000"
2083 /* 3114 */ "OpSubgroup2DBlockLoadINTEL\000"
2084 /* 3141 */ "OpCooperativeMatrixLoadCheckedINTEL\000"
2085 /* 3177 */ "OpCooperativeMatrixStoreCheckedINTEL\000"
2086 /* 3214 */ "OpCooperativeMatrixConstructCheckedINTEL\000"
2087 /* 3255 */ "OpSpecConstantCompositeContinuedINTEL\000"
2088 /* 3293 */ "OpConstantCompositeContinuedINTEL\000"
2089 /* 3327 */ "OpTypeStructContinuedINTEL\000"
2090 /* 3354 */ "OpCompositeConstructContinuedINTEL\000"
2091 /* 3389 */ "OpCooperativeMatrixGetElementCoordINTEL\000"
2092 /* 3429 */ "OpConvertHandleToSampledImageINTEL\000"
2093 /* 3464 */ "OpConvertHandleToImageINTEL\000"
2094 /* 3492 */ "OpSubgroupShuffleINTEL\000"
2095 /* 3515 */ "OpPredicatedStoreINTEL\000"
2096 /* 3538 */ "OpSubgroup2DBlockStoreINTEL\000"
2097 /* 3566 */ "OpSubgroup2DBlockLoadTransposeINTEL\000"
2098 /* 3602 */ "OpSubgroupMatrixMultiplyAccumulateINTEL\000"
2099 /* 3642 */ "OpSubgroupImageMediaBlockWriteINTEL\000"
2100 /* 3678 */ "OpSubgroupImageBlockWriteINTEL\000"
2101 /* 3709 */ "OpSubgroupBlockWriteINTEL\000"
2102 /* 3735 */ "OpControlBarrierArriveINTEL\000"
2103 /* 3763 */ "OpSubgroup2DBlockPrefetchINTEL\000"
2104 /* 3794 */ "OpCooperativeMatrixPrefetchINTEL\000"
2105 /* 3827 */ "OpAliasScopeDeclINTEL\000"
2106 /* 3849 */ "OpAliasDomainDeclINTEL\000"
2107 /* 3872 */ "OpAliasScopeListDeclINTEL\000"
2108 /* 3898 */ "OpAsmCallINTEL\000"
2109 /* 3913 */ "OpFunctionPointerCallINTEL\000"
2110 /* 3940 */ "OpLoopControlINTEL\000"
2111 /* 3959 */ "OpSubgroup2DBlockLoadTransformINTEL\000"
2112 /* 3995 */ "OpAsmINTEL\000"
2113 /* 4006 */ "OpBitwiseFunctionINTEL\000"
2114 /* 4029 */ "OpSubgroupShuffleDownINTEL\000"
2115 /* 4056 */ "OpSubgroupShuffleUpINTEL\000"
2116 /* 4081 */ "OpPtrCastToCrossWorkgroupINTEL\000"
2117 /* 4112 */ "OpMaskedGatherINTEL\000"
2118 /* 4132 */ "OpConvertHandleToSamplerINTEL\000"
2119 /* 4162 */ "OpConstantFunctionPointerINTEL\000"
2120 /* 4193 */ "OpMaskedScatterINTEL\000"
2121 /* 4214 */ "OpSubgroupShuffleXorINTEL\000"
2122 /* 4240 */ "OpCrossWorkgroupCastToPtrINTEL\000"
2123 /* 4271 */ "OpAsmTargetINTEL\000"
2124 /* 4288 */ "OpControlBarrierWaitINTEL\000"
2125 /* 4314 */ "OpVariableLengthArrayINTEL\000"
2126 /* 4341 */ "OpRestoreMemoryINTEL\000"
2127 /* 4362 */ "OpSaveMemoryINTEL\000"
2128 /* 4380 */ "G_FSHL\000"
2129 /* 4387 */ "G_SHL\000"
2130 /* 4393 */ "G_FCEIL\000"
2131 /* 4401 */ "G_SAVGCEIL\000"
2132 /* 4412 */ "G_UAVGCEIL\000"
2133 /* 4423 */ "PATCHABLE_TAIL_CALL\000"
2134 /* 4443 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2135 /* 4470 */ "PATCHABLE_EVENT_CALL\000"
2136 /* 4491 */ "FENTRY_CALL\000"
2137 /* 4503 */ "KILL\000"
2138 /* 4508 */ "G_CONSTANT_POOL\000"
2139 /* 4524 */ "G_ROTL\000"
2140 /* 4531 */ "G_VECREDUCE_FMUL\000"
2141 /* 4548 */ "G_FMUL\000"
2142 /* 4555 */ "G_VECREDUCE_SEQ_FMUL\000"
2143 /* 4576 */ "G_STRICT_FMUL\000"
2144 /* 4590 */ "G_CLMUL\000"
2145 /* 4598 */ "G_VECREDUCE_MUL\000"
2146 /* 4614 */ "G_MUL\000"
2147 /* 4620 */ "G_FREM\000"
2148 /* 4627 */ "G_STRICT_FREM\000"
2149 /* 4641 */ "G_SREM\000"
2150 /* 4648 */ "G_UREM\000"
2151 /* 4655 */ "G_SDIVREM\000"
2152 /* 4665 */ "G_UDIVREM\000"
2153 /* 4675 */ "INLINEASM\000"
2154 /* 4685 */ "G_VECREDUCE_FMINIMUM\000"
2155 /* 4706 */ "G_FMINIMUM\000"
2156 /* 4717 */ "G_ATOMICRMW_FMINIMUM\000"
2157 /* 4738 */ "G_VECREDUCE_FMAXIMUM\000"
2158 /* 4759 */ "G_FMAXIMUM\000"
2159 /* 4770 */ "G_ATOMICRMW_FMAXIMUM\000"
2160 /* 4791 */ "G_FMINIMUMNUM\000"
2161 /* 4805 */ "G_ATOMICRMW_FMINIMUMNUM\000"
2162 /* 4829 */ "G_FMAXIMUMNUM\000"
2163 /* 4843 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
2164 /* 4867 */ "G_FMINNUM\000"
2165 /* 4877 */ "G_FMAXNUM\000"
2166 /* 4887 */ "G_FATAN\000"
2167 /* 4895 */ "G_FTAN\000"
2168 /* 4902 */ "G_INTRINSIC_ROUNDEVEN\000"
2169 /* 4924 */ "G_ASSERT_ALIGN\000"
2170 /* 4939 */ "G_FCOPYSIGN\000"
2171 /* 4951 */ "G_VECREDUCE_FMIN\000"
2172 /* 4968 */ "G_ATOMICRMW_FMIN\000"
2173 /* 4985 */ "G_VECREDUCE_SMIN\000"
2174 /* 5002 */ "G_SMIN\000"
2175 /* 5009 */ "G_VECREDUCE_UMIN\000"
2176 /* 5026 */ "G_UMIN\000"
2177 /* 5033 */ "G_ATOMICRMW_UMIN\000"
2178 /* 5050 */ "G_ATOMICRMW_MIN\000"
2179 /* 5066 */ "G_FASIN\000"
2180 /* 5074 */ "G_FSIN\000"
2181 /* 5081 */ "CFI_INSTRUCTION\000"
2182 /* 5097 */ "G_CTLZ_ZERO_POISON\000"
2183 /* 5116 */ "G_CTTZ_ZERO_POISON\000"
2184 /* 5135 */ "G_SSUBO\000"
2185 /* 5143 */ "G_USUBO\000"
2186 /* 5151 */ "G_SADDO\000"
2187 /* 5159 */ "G_UADDO\000"
2188 /* 5167 */ "JUMP_TABLE_DEBUG_INFO\000"
2189 /* 5189 */ "G_SMULO\000"
2190 /* 5197 */ "G_UMULO\000"
2191 /* 5205 */ "G_BZERO\000"
2192 /* 5213 */ "STACKMAP\000"
2193 /* 5222 */ "G_DEBUGTRAP\000"
2194 /* 5234 */ "G_UBSANTRAP\000"
2195 /* 5246 */ "G_TRAP\000"
2196 /* 5253 */ "G_ATOMICRMW_UDEC_WRAP\000"
2197 /* 5275 */ "G_ATOMICRMW_UINC_WRAP\000"
2198 /* 5297 */ "G_BSWAP\000"
2199 /* 5305 */ "G_SITOFP\000"
2200 /* 5314 */ "G_UITOFP\000"
2201 /* 5323 */ "G_FCMP\000"
2202 /* 5330 */ "G_STRICT_FCMP\000"
2203 /* 5344 */ "G_ICMP\000"
2204 /* 5351 */ "G_SCMP\000"
2205 /* 5358 */ "G_UCMP\000"
2206 /* 5365 */ "CONVERGENCECTRL_LOOP\000"
2207 /* 5386 */ "G_CTPOP\000"
2208 /* 5394 */ "PATCHABLE_OP\000"
2209 /* 5407 */ "FAULTING_OP\000"
2210 /* 5419 */ "PREALLOCATED_SETUP\000"
2211 /* 5438 */ "G_FLDEXP\000"
2212 /* 5447 */ "G_STRICT_FLDEXP\000"
2213 /* 5463 */ "G_FEXP\000"
2214 /* 5470 */ "G_FFREXP\000"
2215 /* 5479 */ "G_BR\000"
2216 /* 5484 */ "INLINEASM_BR\000"
2217 /* 5497 */ "G_BLOCK_ADDR\000"
2218 /* 5510 */ "MEMBARRIER\000"
2219 /* 5521 */ "G_CONSTANT_FOLD_BARRIER\000"
2220 /* 5545 */ "PATCHABLE_FUNCTION_ENTER\000"
2221 /* 5570 */ "G_READCYCLECOUNTER\000"
2222 /* 5589 */ "G_READSTEADYCOUNTER\000"
2223 /* 5609 */ "G_READ_REGISTER\000"
2224 /* 5625 */ "G_WRITE_REGISTER\000"
2225 /* 5642 */ "OpFmaKHR\000"
2226 /* 5651 */ "OpCooperativeMatrixLoadKHR\000"
2227 /* 5678 */ "OpCooperativeMatrixMulAddKHR\000"
2228 /* 5707 */ "OpGroupBitwiseAndKHR\000"
2229 /* 5728 */ "OpGroupLogicalAndKHR\000"
2230 /* 5749 */ "OpCooperativeMatrixStoreKHR\000"
2231 /* 5777 */ "OpGroupNonUniformRotateKHR\000"
2232 /* 5804 */ "OpAssumeTrueKHR\000"
2233 /* 5820 */ "OpFreezeKHR\000"
2234 /* 5832 */ "OpCooperativeMatrixLengthKHR\000"
2235 /* 5861 */ "OpReadClockKHR\000"
2236 /* 5876 */ "OpGroupFMulKHR\000"
2237 /* 5891 */ "OpGroupIMulKHR\000"
2238 /* 5906 */ "OpPoisonKHR\000"
2239 /* 5918 */ "OpGroupBitwiseOrKHR\000"
2240 /* 5938 */ "OpGroupLogicalOrKHR\000"
2241 /* 5958 */ "OpGroupBitwiseXorKHR\000"
2242 /* 5979 */ "OpGroupLogicalXorKHR\000"
2243 /* 6000 */ "OpExpectKHR\000"
2244 /* 6012 */ "OpAbortKHR\000"
2245 /* 6023 */ "OpTypeCooperativeMatrixKHR\000"
2246 /* 6050 */ "G_ASHR\000"
2247 /* 6057 */ "G_FSHR\000"
2248 /* 6064 */ "G_LSHR\000"
2249 /* 6071 */ "CONVERGENCECTRL_ANCHOR\000"
2250 /* 6094 */ "G_FFLOOR\000"
2251 /* 6103 */ "G_SAVGFLOOR\000"
2252 /* 6115 */ "G_UAVGFLOOR\000"
2253 /* 6127 */ "G_EXTRACT_SUBVECTOR\000"
2254 /* 6147 */ "G_INSERT_SUBVECTOR\000"
2255 /* 6166 */ "G_BUILD_VECTOR\000"
2256 /* 6181 */ "G_SHUFFLE_VECTOR\000"
2257 /* 6198 */ "G_STEP_VECTOR\000"
2258 /* 6212 */ "G_SPLAT_VECTOR\000"
2259 /* 6227 */ "G_VECREDUCE_XOR\000"
2260 /* 6243 */ "G_XOR\000"
2261 /* 6249 */ "G_ATOMICRMW_XOR\000"
2262 /* 6265 */ "G_VECREDUCE_OR\000"
2263 /* 6280 */ "G_OR\000"
2264 /* 6285 */ "G_ATOMICRMW_OR\000"
2265 /* 6300 */ "G_ROTR\000"
2266 /* 6307 */ "G_INTTOPTR\000"
2267 /* 6318 */ "G_FABS\000"
2268 /* 6325 */ "G_ABS\000"
2269 /* 6331 */ "G_ABDS\000"
2270 /* 6338 */ "G_UNMERGE_VALUES\000"
2271 /* 6355 */ "G_MERGE_VALUES\000"
2272 /* 6370 */ "G_CTLS\000"
2273 /* 6377 */ "G_FACOS\000"
2274 /* 6385 */ "G_FCOS\000"
2275 /* 6392 */ "G_FSINCOS\000"
2276 /* 6402 */ "G_STRICT_FCMPS\000"
2277 /* 6417 */ "G_CONCAT_VECTORS\000"
2278 /* 6434 */ "COPY_TO_REGCLASS\000"
2279 /* 6451 */ "G_IS_FPCLASS\000"
2280 /* 6464 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2281 /* 6494 */ "G_VECTOR_COMPRESS\000"
2282 /* 6512 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2283 /* 6539 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2284 /* 6577 */ "G_TRUNC_SSAT_S\000"
2285 /* 6592 */ "OpFSubS\000"
2286 /* 6600 */ "OpStrictFSubS\000"
2287 /* 6614 */ "OpISubS\000"
2288 /* 6622 */ "OpShiftRightArithmeticS\000"
2289 /* 6646 */ "OpFAddS\000"
2290 /* 6654 */ "OpStrictFAddS\000"
2291 /* 6668 */ "OpIAddS\000"
2292 /* 6676 */ "OpBitwiseAndS\000"
2293 /* 6690 */ "OpUModS\000"
2294 /* 6698 */ "OpShiftLeftLogicalS\000"
2295 /* 6718 */ "OpShiftRightLogicalS\000"
2296 /* 6739 */ "OpFMulS\000"
2297 /* 6747 */ "OpStrictFMulS\000"
2298 /* 6761 */ "OpIMulS\000"
2299 /* 6769 */ "OpFRemS\000"
2300 /* 6777 */ "OpStrictFRemS\000"
2301 /* 6791 */ "OpSRemS\000"
2302 /* 6799 */ "OpConvertFToS\000"
2303 /* 6813 */ "OpSatConvertUToS\000"
2304 /* 6830 */ "OpBitwiseOrS\000"
2305 /* 6843 */ "OpBitwiseXorS\000"
2306 /* 6857 */ "OpFDivS\000"
2307 /* 6865 */ "OpStrictFDivS\000"
2308 /* 6879 */ "OpSDivS\000"
2309 /* 6887 */ "OpUDivS\000"
2310 /* 6895 */ "OpISubBorrowS\000"
2311 /* 6909 */ "OpIAddCarryS\000"
2312 /* 6922 */ "G_SSUBSAT\000"
2313 /* 6932 */ "G_USUBSAT\000"
2314 /* 6942 */ "G_SADDSAT\000"
2315 /* 6952 */ "G_UADDSAT\000"
2316 /* 6962 */ "G_SSHLSAT\000"
2317 /* 6972 */ "G_USHLSAT\000"
2318 /* 6982 */ "G_SMULFIXSAT\000"
2319 /* 6995 */ "G_UMULFIXSAT\000"
2320 /* 7008 */ "G_SDIVFIXSAT\000"
2321 /* 7021 */ "G_UDIVFIXSAT\000"
2322 /* 7034 */ "G_ATOMICRMW_USUB_SAT\000"
2323 /* 7055 */ "G_FPTOSI_SAT\000"
2324 /* 7068 */ "G_FPTOUI_SAT\000"
2325 /* 7081 */ "G_EXTRACT\000"
2326 /* 7091 */ "G_SELECT\000"
2327 /* 7100 */ "G_BRINDIRECT\000"
2328 /* 7113 */ "PATCHABLE_RET\000"
2329 /* 7127 */ "G_MEMSET\000"
2330 /* 7136 */ "PATCHABLE_FUNCTION_EXIT\000"
2331 /* 7160 */ "G_BRJT\000"
2332 /* 7167 */ "G_EXTRACT_VECTOR_ELT\000"
2333 /* 7188 */ "G_INSERT_VECTOR_ELT\000"
2334 /* 7208 */ "G_FCONSTANT\000"
2335 /* 7220 */ "G_CONSTANT\000"
2336 /* 7231 */ "G_INTRINSIC_CONVERGENT\000"
2337 /* 7254 */ "STATEPOINT\000"
2338 /* 7265 */ "PATCHPOINT\000"
2339 /* 7276 */ "G_PTRTOINT\000"
2340 /* 7287 */ "G_FRINT\000"
2341 /* 7295 */ "G_INTRINSIC_LLRINT\000"
2342 /* 7314 */ "G_INTRINSIC_LRINT\000"
2343 /* 7332 */ "G_FNEARBYINT\000"
2344 /* 7345 */ "G_VASTART\000"
2345 /* 7355 */ "LIFETIME_START\000"
2346 /* 7370 */ "G_INVOKE_REGION_START\000"
2347 /* 7392 */ "G_INSERT\000"
2348 /* 7401 */ "G_FSQRT\000"
2349 /* 7409 */ "G_STRICT_FSQRT\000"
2350 /* 7424 */ "G_BITCAST\000"
2351 /* 7434 */ "G_ADDRSPACE_CAST\000"
2352 /* 7451 */ "DBG_VALUE_LIST\000"
2353 /* 7466 */ "G_FPEXT\000"
2354 /* 7474 */ "G_SEXT\000"
2355 /* 7481 */ "G_ASSERT_SEXT\000"
2356 /* 7495 */ "G_ANYEXT\000"
2357 /* 7504 */ "G_ZEXT\000"
2358 /* 7511 */ "G_ASSERT_ZEXT\000"
2359 /* 7525 */ "OpAtomicFAddEXT\000"
2360 /* 7541 */ "OpArithmeticFenceEXT\000"
2361 /* 7562 */ "OpAtomicFMinEXT\000"
2362 /* 7578 */ "OpAtomicFMaxEXT\000"
2363 /* 7594 */ "G_ABDU\000"
2364 /* 7601 */ "G_TRUNC_SSAT_U\000"
2365 /* 7616 */ "G_TRUNC_USAT_U\000"
2366 /* 7631 */ "OpConvertFToU\000"
2367 /* 7645 */ "OpSatConvertSToU\000"
2368 /* 7662 */ "OpConvertPtrToU\000"
2369 /* 7678 */ "G_FDIV\000"
2370 /* 7685 */ "G_STRICT_FDIV\000"
2371 /* 7699 */ "G_SDIV\000"
2372 /* 7706 */ "G_UDIV\000"
2373 /* 7713 */ "G_GET_FPENV\000"
2374 /* 7725 */ "G_RESET_FPENV\000"
2375 /* 7739 */ "G_SET_FPENV\000"
2376 /* 7751 */ "OpTypeAccelerationStructureNV\000"
2377 /* 7781 */ "OpImageSampleFootprintNV\000"
2378 /* 7806 */ "OpTypeCooperativeMatrixNV\000"
2379 /* 7832 */ "OpFSubV\000"
2380 /* 7840 */ "OpStrictFSubV\000"
2381 /* 7854 */ "OpISubV\000"
2382 /* 7862 */ "OpShiftRightArithmeticV\000"
2383 /* 7886 */ "OpFAddV\000"
2384 /* 7894 */ "OpStrictFAddV\000"
2385 /* 7908 */ "OpIAddV\000"
2386 /* 7916 */ "OpBitwiseAndV\000"
2387 /* 7930 */ "OpUModV\000"
2388 /* 7938 */ "OpFNegateV\000"
2389 /* 7949 */ "OpShiftLeftLogicalV\000"
2390 /* 7969 */ "OpShiftRightLogicalV\000"
2391 /* 7990 */ "OpFMulV\000"
2392 /* 7998 */ "OpStrictFMulV\000"
2393 /* 8012 */ "OpIMulV\000"
2394 /* 8020 */ "OpFRemV\000"
2395 /* 8028 */ "OpStrictFRemV\000"
2396 /* 8042 */ "OpSRemV\000"
2397 /* 8050 */ "OpBitwiseOrV\000"
2398 /* 8063 */ "OpBitwiseXorV\000"
2399 /* 8077 */ "OpFDivV\000"
2400 /* 8085 */ "OpStrictFDivV\000"
2401 /* 8099 */ "OpSDivV\000"
2402 /* 8107 */ "OpUDivV\000"
2403 /* 8115 */ "OpISubBorrowV\000"
2404 /* 8129 */ "OpIAddCarryV\000"
2405 /* 8142 */ "G_FPOW\000"
2406 /* 8149 */ "G_VECREDUCE_FMAX\000"
2407 /* 8166 */ "G_ATOMICRMW_FMAX\000"
2408 /* 8183 */ "G_VECREDUCE_SMAX\000"
2409 /* 8200 */ "G_SMAX\000"
2410 /* 8207 */ "G_VECREDUCE_UMAX\000"
2411 /* 8224 */ "G_UMAX\000"
2412 /* 8231 */ "G_ATOMICRMW_UMAX\000"
2413 /* 8248 */ "G_ATOMICRMW_MAX\000"
2414 /* 8264 */ "G_FRAME_INDEX\000"
2415 /* 8278 */ "G_SBFX\000"
2416 /* 8285 */ "G_UBFX\000"
2417 /* 8292 */ "G_SMULFIX\000"
2418 /* 8302 */ "G_UMULFIX\000"
2419 /* 8312 */ "G_SDIVFIX\000"
2420 /* 8322 */ "G_UDIVFIX\000"
2421 /* 8332 */ "G_MEMCPY\000"
2422 /* 8341 */ "COPY\000"
2423 /* 8346 */ "CONVERGENCECTRL_ENTRY\000"
2424 /* 8368 */ "G_CTLZ\000"
2425 /* 8375 */ "G_CTTZ\000"
2426 /* 8382 */ "OpAtomicISub\000"
2427 /* 8395 */ "OpVectorExtractDynamic\000"
2428 /* 8418 */ "OpVectorInsertDynamic\000"
2429 /* 8440 */ "OpPtrCastToGeneric\000"
2430 /* 8459 */ "OpExecutionModeId\000"
2431 /* 8477 */ "OpDecorateId\000"
2432 /* 8490 */ "OpIsValidReserveId\000"
2433 /* 8509 */ "OpTypeReserveId\000"
2434 /* 8525 */ "OpImageRead\000"
2435 /* 8537 */ "OpImageSparseRead\000"
2436 /* 8555 */ "OpAtomicLoad\000"
2437 /* 8568 */ "OpLoad\000"
2438 /* 8575 */ "OpGroupNonUniformFAdd\000"
2439 /* 8597 */ "OpGroupFAdd\000"
2440 /* 8609 */ "OpAtomicIAdd\000"
2441 /* 8622 */ "OpGroupNonUniformIAdd\000"
2442 /* 8644 */ "OpGroupIAdd\000"
2443 /* 8656 */ "OpSMulExtended\000"
2444 /* 8671 */ "OpUMulExtended\000"
2445 /* 8686 */ "OpOrdered\000"
2446 /* 8696 */ "OpUnordered\000"
2447 /* 8708 */ "OpModuleProcessed\000"
2448 /* 8726 */ "OpSourceContinued\000"
2449 /* 8744 */ "OpCopyMemorySized\000"
2450 /* 8762 */ "OpTypeVoid\000"
2451 /* 8773 */ "OpAtomicAnd\000"
2452 /* 8785 */ "OpGroupNonUniformBitwiseAnd\000"
2453 /* 8813 */ "OpGroupNonUniformLogicalAnd\000"
2454 /* 8841 */ "OpLogicalAnd\000"
2455 /* 8854 */ "OpFunctionEnd\000"
2456 /* 8868 */ "OpSelectSFSCond\000"
2457 /* 8884 */ "OpSelectVFSCond\000"
2458 /* 8900 */ "OpSelectSISCond\000"
2459 /* 8916 */ "OpSelectVISCond\000"
2460 /* 8932 */ "OpSelectSPSCond\000"
2461 /* 8948 */ "OpSelectVPSCond\000"
2462 /* 8964 */ "OpSelectSFVCond\000"
2463 /* 8980 */ "OpSelectVFVCond\000"
2464 /* 8996 */ "OpSelectSIVCond\000"
2465 /* 9012 */ "OpSelectVIVCond\000"
2466 /* 9028 */ "OpSelectSPVCond\000"
2467 /* 9044 */ "OpSelectVPVCond\000"
2468 /* 9060 */ "OpImageQuerySizeLod\000"
2469 /* 9080 */ "OpImageSampleImplicitLod\000"
2470 /* 9105 */ "OpImageSparseSampleImplicitLod\000"
2471 /* 9136 */ "OpImageSampleDrefImplicitLod\000"
2472 /* 9165 */ "OpImageSparseSampleDrefImplicitLod\000"
2473 /* 9200 */ "OpImageSampleProjDrefImplicitLod\000"
2474 /* 9233 */ "OpImageSparseSampleProjDrefImplicitLod\000"
2475 /* 9272 */ "OpImageSampleProjImplicitLod\000"
2476 /* 9301 */ "OpImageSparseSampleProjImplicitLod\000"
2477 /* 9336 */ "OpImageSampleExplicitLod\000"
2478 /* 9361 */ "OpImageSparseSampleExplicitLod\000"
2479 /* 9392 */ "OpImageSampleDrefExplicitLod\000"
2480 /* 9421 */ "OpImageSparseSampleDrefExplicitLod\000"
2481 /* 9456 */ "OpImageSampleProjDrefExplicitLod\000"
2482 /* 9489 */ "OpImageSparseSampleProjDrefExplicitLod\000"
2483 /* 9528 */ "OpImageSampleProjExplicitLod\000"
2484 /* 9557 */ "OpImageSparseSampleProjExplicitLod\000"
2485 /* 9592 */ "OpImageQueryLod\000"
2486 /* 9608 */ "OpFMod\000"
2487 /* 9615 */ "OpSMod\000"
2488 /* 9622 */ "OpSource\000"
2489 /* 9631 */ "OpExecutionMode\000"
2490 /* 9647 */ "OpTypeSampledImage\000"
2491 /* 9666 */ "OpSampledImage\000"
2492 /* 9681 */ "OpTypeImage\000"
2493 /* 9693 */ "OpImage\000"
2494 /* 9701 */ "OpTypePipeStorage\000"
2495 /* 9719 */ "OpBuildNDRange\000"
2496 /* 9734 */ "OpAtomicExchange\000"
2497 /* 9751 */ "OpAtomicCompareExchange\000"
2498 /* 9775 */ "OpSelectionMerge\000"
2499 /* 9792 */ "OpLoopMerge\000"
2500 /* 9804 */ "OpUnreachable\000"
2501 /* 9818 */ "OpVariable\000"
2502 /* 9829 */ "OpGroupNonUniformShuffle\000"
2503 /* 9854 */ "OpVectorShuffle\000"
2504 /* 9870 */ "OpName\000"
2505 /* 9877 */ "OpMemberName\000"
2506 /* 9890 */ "OpFwidthFine\000"
2507 /* 9903 */ "OpDPdxFine\000"
2508 /* 9914 */ "OpDPdyFine\000"
2509 /* 9925 */ "OpNoLine\000"
2510 /* 9934 */ "OpLine\000"
2511 /* 9941 */ "OpReservedReadPipe\000"
2512 /* 9960 */ "OpReadPipe\000"
2513 /* 9971 */ "OpCommitReadPipe\000"
2514 /* 9988 */ "OpGroupCommitReadPipe\000"
2515 /* 10010 */ "OpTypePipe\000"
2516 /* 10021 */ "OpReservedWritePipe\000"
2517 /* 10041 */ "OpWritePipe\000"
2518 /* 10053 */ "OpCommitWritePipe\000"
2519 /* 10071 */ "OpGroupCommitWritePipe\000"
2520 /* 10094 */ "UNKNOWN_type\000"
2521 /* 10107 */ "OpAtomicStore\000"
2522 /* 10121 */ "OpStore\000"
2523 /* 10129 */ "OpSpecConstantFalse\000"
2524 /* 10149 */ "OpConstantFalse\000"
2525 /* 10165 */ "OpTranspose\000"
2526 /* 10177 */ "OpFwidthCoarse\000"
2527 /* 10192 */ "OpDPdxCoarse\000"
2528 /* 10205 */ "OpDPdyCoarse\000"
2529 /* 10218 */ "OpBitReverse\000"
2530 /* 10231 */ "OpFNegate\000"
2531 /* 10241 */ "OpSNegate\000"
2532 /* 10251 */ "OpDecorate\000"
2533 /* 10262 */ "OpMemberDecorate\000"
2534 /* 10279 */ "OpIsFinite\000"
2535 /* 10290 */ "OpImageWrite\000"
2536 /* 10303 */ "OpSpecConstantComposite\000"
2537 /* 10327 */ "OpConstantComposite\000"
2538 /* 10347 */ "OpTypeQueue\000"
2539 /* 10359 */ "OpGetDefaultQueue\000"
2540 /* 10377 */ "OpReturnValue\000"
2541 /* 10391 */ "OpTypeOpaque\000"
2542 /* 10404 */ "OpSpecConstantTrue\000"
2543 /* 10423 */ "OpConstantTrue\000"
2544 /* 10438 */ "OpEndPrimitive\000"
2545 /* 10453 */ "OpEndStreamPrimitive\000"
2546 /* 10474 */ "OpImageQuerySize\000"
2547 /* 10491 */ "OpNamedBarrierInitialize\000"
2548 /* 10516 */ "OpSizeOf\000"
2549 /* 10525 */ "OpUndef\000"
2550 /* 10533 */ "OpPtrDiff\000"
2551 /* 10543 */ "OpIsInf\000"
2552 /* 10551 */ "OpDecorateString\000"
2553 /* 10568 */ "OpMemberDecorateString\000"
2554 /* 10591 */ "OpString\000"
2555 /* 10600 */ "OpBranch\000"
2556 /* 10609 */ "OpImageFetch\000"
2557 /* 10622 */ "OpImageSparseFetch\000"
2558 /* 10641 */ "OpSwitch\000"
2559 /* 10650 */ "OpFwidth\000"
2560 /* 10659 */ "OpArrayLength\000"
2561 /* 10673 */ "OpPhi\000"
2562 /* 10679 */ "OpAtomicCompareExchangeWeak\000"
2563 /* 10707 */ "OpCopyLogical\000"
2564 /* 10721 */ "OpIsNormal\000"
2565 /* 10732 */ "OpBranchConditional\000"
2566 /* 10752 */ "OpIEqual\000"
2567 /* 10761 */ "OpFOrdEqual\000"
2568 /* 10773 */ "OpFUnordEqual\000"
2569 /* 10787 */ "OpLogicalEqual\000"
2570 /* 10802 */ "OpGroupNonUniformAllEqual\000"
2571 /* 10828 */ "OpSGreaterThanEqual\000"
2572 /* 10848 */ "OpUGreaterThanEqual\000"
2573 /* 10868 */ "OpFOrdGreaterThanEqual\000"
2574 /* 10891 */ "OpFUnordGreaterThanEqual\000"
2575 /* 10916 */ "OpSLessThanEqual\000"
2576 /* 10933 */ "OpULessThanEqual\000"
2577 /* 10950 */ "OpFOrdLessThanEqual\000"
2578 /* 10970 */ "OpFUnordLessThanEqual\000"
2579 /* 10992 */ "OpPtrEqual\000"
2580 /* 11003 */ "OpINotEqual\000"
2581 /* 11015 */ "OpFOrdNotEqual\000"
2582 /* 11030 */ "OpFUnordNotEqual\000"
2583 /* 11047 */ "OpLogicalNotEqual\000"
2584 /* 11065 */ "OpPtrNotEqual\000"
2585 /* 11079 */ "OpLabel\000"
2586 /* 11087 */ "OpMemoryModel\000"
2587 /* 11101 */ "OpEnqueueKernel\000"
2588 /* 11117 */ "OpGroupNonUniformAll\000"
2589 /* 11138 */ "OpAll\000"
2590 /* 11144 */ "OpGroupAll\000"
2591 /* 11155 */ "OpFunctionCall\000"
2592 /* 11170 */ "OpKill\000"
2593 /* 11177 */ "OpConstantNull\000"
2594 /* 11192 */ "OpTypeBool\000"
2595 /* 11203 */ "OpGroupNonUniformFMul\000"
2596 /* 11225 */ "OpGroupNonUniformIMul\000"
2597 /* 11247 */ "OpIsNan\000"
2598 /* 11255 */ "OpSGreaterThan\000"
2599 /* 11270 */ "OpUGreaterThan\000"
2600 /* 11285 */ "OpFOrdGreaterThan\000"
2601 /* 11303 */ "OpFUnordGreaterThan\000"
2602 /* 11323 */ "OpSLessThan\000"
2603 /* 11335 */ "OpULessThan\000"
2604 /* 11347 */ "OpFOrdLessThan\000"
2605 /* 11362 */ "OpFUnordLessThan\000"
2606 /* 11379 */ "OpGroupNonUniformFMin\000"
2607 /* 11401 */ "OpGroupFMin\000"
2608 /* 11413 */ "OpAtomicSMin\000"
2609 /* 11426 */ "OpGroupNonUniformSMin\000"
2610 /* 11448 */ "OpGroupSMin\000"
2611 /* 11460 */ "OpAtomicUMin\000"
2612 /* 11473 */ "OpGroupNonUniformUMin\000"
2613 /* 11495 */ "OpGroupUMin\000"
2614 /* 11507 */ "OpAccessChain\000"
2615 /* 11521 */ "OpPtrAccessChain\000"
2616 /* 11538 */ "OpInBoundsPtrAccessChain\000"
2617 /* 11563 */ "OpInBoundsAccessChain\000"
2618 /* 11585 */ "OpSourceExtension\000"
2619 /* 11603 */ "OpExtension\000"
2620 /* 11615 */ "OpDemoteToHelperInvocation\000"
2621 /* 11642 */ "OpTypeFunction\000"
2622 /* 11657 */ "OpFunction\000"
2623 /* 11668 */ "OpReturn\000"
2624 /* 11677 */ "OpGroupNonUniformShuffleDown\000"
2625 /* 11706 */ "OpCaptureEventProfilingInfo\000"
2626 /* 11734 */ "OpSpecConstantOp\000"
2627 /* 11751 */ "OpGroupNonUniformShuffleUp\000"
2628 /* 11778 */ "OpGroupNonUniformQuadSwap\000"
2629 /* 11804 */ "OpNop\000"
2630 /* 11810 */ "OpLifetimeStop\000"
2631 /* 11825 */ "OpAtomicOr\000"
2632 /* 11836 */ "OpGroupNonUniformBitwiseOr\000"
2633 /* 11863 */ "OpGroupNonUniformLogicalOr\000"
2634 /* 11890 */ "OpLogicalOr\000"
2635 /* 11902 */ "OpAtomicFlagClear\000"
2636 /* 11920 */ "OpVectorTimesScalar\000"
2637 /* 11940 */ "OpMatrixTimesScalar\000"
2638 /* 11960 */ "OpImageQueryOrder\000"
2639 /* 11978 */ "OpImageGather\000"
2640 /* 11992 */ "OpImageSparseGather\000"
2641 /* 12012 */ "OpImageDrefGather\000"
2642 /* 12030 */ "OpImageSparseDrefGather\000"
2643 /* 12054 */ "OpTypeNamedBarrier\000"
2644 /* 12073 */ "OpMemoryNamedBarrier\000"
2645 /* 12094 */ "OpControlBarrier\000"
2646 /* 12111 */ "OpMemoryBarrier\000"
2647 /* 12127 */ "OpTypeSampler\000"
2648 /* 12141 */ "OpConstantSampler\000"
2649 /* 12159 */ "OpLessOrGreater\000"
2650 /* 12175 */ "OpFunctionParameter\000"
2651 /* 12195 */ "OpTypeForwardPointer\000"
2652 /* 12216 */ "OpTypePointer\000"
2653 /* 12230 */ "OpImageTexelPointer\000"
2654 /* 12250 */ "OpAtomicXor\000"
2655 /* 12262 */ "OpGroupNonUniformShuffleXor\000"
2656 /* 12290 */ "OpGroupNonUniformBitwiseXor\000"
2657 /* 12318 */ "OpGroupNonUniformLogicalXor\000"
2658 /* 12346 */ "OpTypeVector\000"
2659 /* 12359 */ "OpMatrixTimesVector\000"
2660 /* 12379 */ "OpConvertUToPtr\000"
2661 /* 12395 */ "OpGenericCastToPtr\000"
2662 /* 12414 */ "OpGenericPtrMemSemantics\000"
2663 /* 12439 */ "OpImageQuerySamples\000"
2664 /* 12459 */ "OpImageQueryLevels\000"
2665 /* 12478 */ "OpReserveReadPipePackets\000"
2666 /* 12503 */ "OpGroupReserveReadPipePackets\000"
2667 /* 12533 */ "OpReserveWritePipePackets\000"
2668 /* 12559 */ "OpGroupReserveWritePipePackets\000"
2669 /* 12590 */ "OpGetNumPipePackets\000"
2670 /* 12610 */ "OpGetMaxPipePackets\000"
2671 /* 12630 */ "OpGroupWaitEvents\000"
2672 /* 12648 */ "OpSetUserEventStatus\000"
2673 /* 12669 */ "OpSDotAccSat\000"
2674 /* 12682 */ "OpSUDotAccSat\000"
2675 /* 12696 */ "OpUDotAccSat\000"
2676 /* 12709 */ "OpImageQueryFormat\000"
2677 /* 12728 */ "OpTypeFloat\000"
2678 /* 12740 */ "OpBitFieldSExtract\000"
2679 /* 12759 */ "OpBitFieldUExtract\000"
2680 /* 12778 */ "OpCompositeExtract\000"
2681 /* 12797 */ "OpGroupNonUniformBallotBitExtract\000"
2682 /* 12831 */ "OpCopyObject\000"
2683 /* 12844 */ "OpGroupNonUniformElect\000"
2684 /* 12867 */ "OpOuterProduct\000"
2685 /* 12882 */ "OpTypeStruct\000"
2686 /* 12895 */ "OpCompositeConstruct\000"
2687 /* 12916 */ "OpAtomicFlagTestAndSet\000"
2688 /* 12939 */ "OpSignBitSet\000"
2689 /* 12952 */ "OpGenericCastToPtrExplicit\000"
2690 /* 12979 */ "OpTypeInt\000"
2691 /* 12989 */ "OpSpecConstant\000"
2692 /* 13004 */ "OpImageSparseTexelsResident\000"
2693 /* 13032 */ "OpAtomicIDecrement\000"
2694 /* 13051 */ "OpAtomicIIncrement\000"
2695 /* 13070 */ "OpIsValidEvent\000"
2696 /* 13085 */ "OpTypeDeviceEvent\000"
2697 /* 13103 */ "OpTypeEvent\000"
2698 /* 13115 */ "OpReleaseEvent\000"
2699 /* 13130 */ "OpRetainEvent\000"
2700 /* 13144 */ "OpCreateUserEvent\000"
2701 /* 13162 */ "OpEntryPoint\000"
2702 /* 13175 */ "OpBitCount\000"
2703 /* 13186 */ "OpGroupNonUniformBallotBitCount\000"
2704 /* 13218 */ "OpSDot\000"
2705 /* 13225 */ "OpSUDot\000"
2706 /* 13233 */ "OpUDot\000"
2707 /* 13240 */ "OpDot\000"
2708 /* 13246 */ "OpLogicalNot\000"
2709 /* 13259 */ "OpNot\000"
2710 /* 13265 */ "OpGroupNonUniformInverseBallot\000"
2711 /* 13296 */ "OpGroupNonUniformBallot\000"
2712 /* 13320 */ "OpLifetimeStart\000"
2713 /* 13336 */ "OpBitFieldInsert\000"
2714 /* 13353 */ "OpCompositeInsert\000"
2715 /* 13371 */ "OpFConvert\000"
2716 /* 13382 */ "OpSConvert\000"
2717 /* 13393 */ "OpUConvert\000"
2718 /* 13404 */ "OpExtInstImport\000"
2719 /* 13420 */ "OpGroupNonUniformBroadcast\000"
2720 /* 13447 */ "OpGroupBroadcast\000"
2721 /* 13464 */ "OpBitcast\000"
2722 /* 13474 */ "OpExtInst\000"
2723 /* 13484 */ "OpGroupNonUniformBroadcastFirst\000"
2724 /* 13516 */ "OpGroupNonUniformFMax\000"
2725 /* 13538 */ "OpGroupFMax\000"
2726 /* 13550 */ "OpAtomicSMax\000"
2727 /* 13563 */ "OpGroupNonUniformSMax\000"
2728 /* 13585 */ "OpGroupSMax\000"
2729 /* 13597 */ "OpAtomicUMax\000"
2730 /* 13610 */ "OpGroupNonUniformUMax\000"
2731 /* 13632 */ "OpGroupUMax\000"
2732 /* 13644 */ "OpDPdx\000"
2733 /* 13651 */ "OpEmitStreamVertex\000"
2734 /* 13670 */ "OpEmitVertex\000"
2735 /* 13683 */ "OpTypeMatrix\000"
2736 /* 13696 */ "OpVectorTimesMatrix\000"
2737 /* 13716 */ "OpMatrixTimesMatrix\000"
2738 /* 13736 */ "OpTypeRuntimeArray\000"
2739 /* 13755 */ "OpTypeArray\000"
2740 /* 13767 */ "OpDPdy\000"
2741 /* 13774 */ "OpGroupNonUniformAny\000"
2742 /* 13795 */ "OpAny\000"
2743 /* 13801 */ "OpGroupAny\000"
2744 /* 13812 */ "OpGroupAsyncCopy\000"
2745 /* 13829 */ "OpCopyMemory\000"
2746 /* 13842 */ "OpCapability\000"
2747};
2748#ifdef __GNUC__
2749#pragma GCC diagnostic pop
2750#endif
2751
2752extern const unsigned SPIRVInstrNameIndices[] = {
2753 2807U, 4675U, 5484U, 5081U, 2892U, 2873U, 2901U, 4503U,
2754 2600U, 2615U, 2526U, 2513U, 2642U, 6434U, 2389U, 7451U,
2755 2539U, 2803U, 2882U, 2116U, 8341U, 2849U, 2238U, 7355U,
2756 1943U, 2067U, 2104U, 5213U, 4491U, 7265U, 2050U, 5419U,
2757 2735U, 7254U, 2288U, 5407U, 5394U, 5545U, 7113U, 7136U,
2758 4423U, 4470U, 4443U, 2918U, 2380U, 5510U, 5167U, 2277U,
2759 8346U, 6071U, 5365U, 2437U, 7481U, 7511U, 4924U, 1856U,
2760 1555U, 4614U, 7699U, 7706U, 4641U, 4648U, 4655U, 4665U,
2761 1921U, 6280U, 6243U, 6331U, 7594U, 6115U, 4412U, 6103U,
2762 4401U, 2524U, 2805U, 8264U, 2399U, 2414U, 4508U, 7081U,
2763 6338U, 7392U, 6355U, 6166U, 1625U, 6417U, 7276U, 6307U,
2764 7424U, 2480U, 5521U, 2024U, 1599U, 2006U, 7314U, 7295U,
2765 4902U, 5570U, 5589U, 1757U, 1701U, 1731U, 1670U, 1742U,
2766 1682U, 1712U, 2359U, 2313U, 2343U, 6464U, 2656U, 2673U,
2767 1872U, 1561U, 1927U, 1888U, 6285U, 6249U, 8248U, 5050U,
2768 8231U, 5033U, 1823U, 1538U, 8166U, 4968U, 4770U, 4717U,
2769 4843U, 4805U, 5275U, 5253U, 1965U, 7034U, 2096U, 2752U,
2770 1956U, 7100U, 7370U, 1577U, 6512U, 7231U, 6539U, 7495U,
2771 1617U, 6577U, 7601U, 7616U, 7220U, 7208U, 7345U, 2727U,
2772 7474U, 2629U, 7504U, 4387U, 6064U, 6050U, 4380U, 6057U,
2773 6300U, 4524U, 5344U, 5323U, 5351U, 5358U, 7091U, 5159U,
2774 2137U, 5143U, 2088U, 5151U, 2129U, 5135U, 2080U, 5197U,
2775 5189U, 2771U, 2763U, 6952U, 6942U, 6932U, 6922U, 6972U,
2776 6962U, 8292U, 8302U, 6982U, 6995U, 8312U, 8322U, 7008U,
2777 7021U, 1781U, 1517U, 4548U, 59U, 1663U, 7678U, 4620U,
2778 2505U, 8142U, 2829U, 5463U, 35U, 9U, 2720U, 18U,
2779 0U, 5438U, 5470U, 2593U, 7466U, 1589U, 2811U, 2820U,
2780 5305U, 5314U, 7055U, 7068U, 6318U, 4939U, 6451U, 2489U,
2781 4867U, 4877U, 2186U, 2201U, 4706U, 4759U, 4791U, 4829U,
2782 7713U, 7739U, 7725U, 2145U, 2173U, 2158U, 2690U, 2705U,
2783 1862U, 2863U, 5002U, 8200U, 5026U, 8224U, 6325U, 1997U,
2784 1987U, 5479U, 7160U, 2216U, 6147U, 6127U, 7188U, 7167U,
2785 6181U, 6212U, 6198U, 6494U, 8375U, 5116U, 8368U, 5097U,
2786 6370U, 5386U, 5297U, 2367U, 4590U, 4393U, 6385U, 5074U,
2787 6392U, 4895U, 6377U, 5066U, 4887U, 26U, 2795U, 2787U,
2788 2779U, 7401U, 6094U, 7287U, 7332U, 7434U, 5497U, 2225U,
2789 1646U, 2458U, 2328U, 1809U, 1524U, 4576U, 7685U, 4627U,
2790 65U, 7409U, 5447U, 5330U, 6402U, 5609U, 5625U, 8332U,
2791 2261U, 2470U, 7127U, 5205U, 2245U, 5246U, 5222U, 5234U,
2792 1788U, 4555U, 1764U, 4531U, 8149U, 4951U, 4738U, 4685U,
2793 1840U, 4598U, 1905U, 6265U, 6227U, 8183U, 4985U, 8207U,
2794 5009U, 8278U, 8285U, 2301U, 10094U, 6012U, 11507U, 3849U,
2795 3827U, 3872U, 11138U, 13795U, 1044U, 674U, 856U, 598U,
2796 189U, 829U, 569U, 449U, 1376U, 1163U, 1197U, 1257U,
2797 1137U, 775U, 1403U, 321U, 106U, 217U, 1018U, 134U,
2798 244U, 373U, 1229U, 269U, 398U, 78U, 926U, 162U,
2799 543U, 803U, 1429U, 294U, 346U, 1284U, 973U, 900U,
2800 1108U, 744U, 646U, 1330U, 423U, 7541U, 10659U, 3898U,
2801 3995U, 4271U, 5804U, 8773U, 9751U, 10679U, 9734U, 7525U,
2802 7578U, 7562U, 11902U, 12916U, 8609U, 13032U, 13051U, 8382U,
2803 8555U, 11825U, 13550U, 11413U, 10107U, 13597U, 11460U, 12250U,
2804 13175U, 13336U, 12740U, 12759U, 10218U, 13464U, 6676U, 7916U,
2805 4006U, 6830U, 8050U, 6843U, 8063U, 10600U, 10732U, 9719U,
2806 13842U, 11706U, 9971U, 10053U, 12895U, 3354U, 12778U, 13353U,
2807 10327U, 3293U, 2581U, 10149U, 4162U, 2837U, 11177U, 12141U,
2808 10423U, 12094U, 3735U, 4288U, 2980U, 2958U, 6799U, 7631U,
2809 3464U, 3429U, 4132U, 7662U, 2553U, 2567U, 12379U, 3214U,
2810 3389U, 5832U, 3141U, 5651U, 5678U, 3794U, 3177U, 5749U,
2811 10707U, 13829U, 8744U, 12831U, 13144U, 4240U, 13644U, 10192U,
2812 9903U, 13767U, 10205U, 9914U, 10251U, 8477U, 10551U, 11615U,
2813 13240U, 13651U, 13670U, 10438U, 10453U, 11101U, 13162U, 9631U,
2814 8459U, 6000U, 13474U, 13404U, 11603U, 6646U, 7886U, 13371U,
2815 6857U, 8077U, 9608U, 6739U, 7990U, 10231U, 7938U, 10761U,
2816 11285U, 10868U, 11347U, 10950U, 11015U, 6769U, 8020U, 6592U,
2817 7832U, 10773U, 11303U, 10891U, 11362U, 10970U, 11030U, 1071U,
2818 703U, 1001U, 526U, 954U, 1357U, 883U, 1088U, 722U,
2819 627U, 1312U, 5642U, 5820U, 11657U, 11155U, 8854U, 12175U,
2820 3913U, 10650U, 10177U, 9890U, 12395U, 12952U, 12414U, 10359U,
2821 12610U, 12590U, 11144U, 13801U, 13812U, 5707U, 5918U, 5958U,
2822 13447U, 9988U, 10071U, 8597U, 13538U, 11401U, 5876U, 8644U,
2823 5891U, 5728U, 5938U, 5979U, 11117U, 10802U, 13774U, 13296U,
2824 13186U, 12797U, 1455U, 1486U, 8785U, 11836U, 12290U, 13420U,
2825 13484U, 12844U, 8575U, 13516U, 11379U, 11203U, 8622U, 11225U,
2826 13265U, 8813U, 11863U, 12318U, 11778U, 5777U, 13563U, 11426U,
2827 9829U, 11677U, 11751U, 12262U, 13610U, 11473U, 12503U, 12559U,
2828 13585U, 11448U, 13632U, 11495U, 12630U, 6909U, 8129U, 6668U,
2829 7908U, 10752U, 6761U, 8012U, 11003U, 6895U, 8115U, 6614U,
2830 7854U, 9693U, 12012U, 10609U, 11978U, 12709U, 12459U, 9592U,
2831 11960U, 12439U, 10474U, 9060U, 8525U, 9392U, 9136U, 9336U,
2832 7781U, 9080U, 9456U, 9200U, 9528U, 9272U, 12030U, 10622U,
2833 11992U, 8537U, 9421U, 9165U, 9361U, 9105U, 9489U, 9233U,
2834 9557U, 9301U, 13004U, 12230U, 10290U, 11563U, 11538U, 10279U,
2835 10543U, 11247U, 10721U, 13070U, 8490U, 11170U, 11079U, 12159U,
2836 13320U, 11810U, 9934U, 8568U, 8841U, 10787U, 13246U, 11047U,
2837 11890U, 3940U, 9792U, 4112U, 4193U, 13716U, 11940U, 12359U,
2838 10262U, 10568U, 9877U, 12111U, 11087U, 12073U, 8708U, 9870U,
2839 10491U, 9925U, 11804U, 13259U, 8686U, 12867U, 10673U, 5906U,
2840 3092U, 3515U, 11521U, 4081U, 8440U, 10533U, 10992U, 11065U,
2841 43U, 5861U, 9960U, 475U, 13115U, 12478U, 12533U, 9941U,
2842 10021U, 4341U, 13130U, 11668U, 10377U, 2938U, 13382U, 6879U,
2843 8099U, 13218U, 12669U, 11255U, 10828U, 11323U, 10916U, 9615U,
2844 8656U, 10241U, 6791U, 8042U, 13225U, 12682U, 9666U, 7645U,
2845 6813U, 4362U, 8868U, 8964U, 8900U, 8996U, 8932U, 9028U,
2846 8884U, 8980U, 8916U, 9012U, 8948U, 9044U, 9775U, 12648U,
2847 6698U, 7949U, 6622U, 7862U, 6718U, 7969U, 12939U, 10516U,
2848 9622U, 8726U, 11585U, 12989U, 10303U, 3255U, 10129U, 11734U,
2849 10404U, 10121U, 6654U, 7894U, 6865U, 8085U, 6747U, 7998U,
2850 6777U, 8028U, 6600U, 7840U, 10591U, 3114U, 3959U, 3566U,
2851 3763U, 3538U, 3067U, 3709U, 3037U, 3678U, 3002U, 3642U,
2852 3602U, 4029U, 3492U, 4056U, 4214U, 10641U, 10165U, 7751U,
2853 13755U, 11192U, 6023U, 7806U, 13085U, 13103U, 12728U, 12195U,
2854 11642U, 9681U, 12979U, 13683U, 12054U, 10391U, 10010U, 9701U,
2855 12216U, 10347U, 8509U, 13736U, 9647U, 12127U, 12882U, 3327U,
2856 12346U, 8762U, 13393U, 6887U, 8107U, 13233U, 12696U, 11270U,
2857 10848U, 11335U, 10933U, 6690U, 7930U, 8671U, 10525U, 8696U,
2858 9804U, 9818U, 4314U, 8395U, 8418U, 9854U, 13696U, 11920U,
2859 10041U, 500U,
2860};
2861
2862static inline void InitSPIRVMCInstrInfo(MCInstrInfo *II) {
2863 II->InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 850, nullptr, 0);
2864}
2865
2866
2867} // namespace llvm
2868
2869#endif // GET_INSTRINFO_MC_DESC
2870
2871#ifdef GET_INSTRINFO_HEADER
2872#undef GET_INSTRINFO_HEADER
2873
2874namespace llvm {
2875
2876struct SPIRVGenInstrInfo : public TargetInstrInfo {
2877 explicit SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2878 ~SPIRVGenInstrInfo() override = default;
2879};
2880
2881} // namespace llvm
2882
2883namespace llvm::SPIRV {
2884
2885
2886} // namespace llvm::SPIRV
2887
2888#endif // GET_INSTRINFO_HEADER
2889
2890#ifdef GET_INSTRINFO_HELPER_DECLS
2891#undef GET_INSTRINFO_HELPER_DECLS
2892
2893
2894#endif // GET_INSTRINFO_HELPER_DECLS
2895
2896#ifdef GET_INSTRINFO_HELPERS
2897#undef GET_INSTRINFO_HELPERS
2898
2899
2900#endif // GET_INSTRINFO_HELPERS
2901
2902#ifdef GET_INSTRINFO_CTOR_DTOR
2903#undef GET_INSTRINFO_CTOR_DTOR
2904
2905namespace llvm {
2906
2907extern const SPIRVInstrTable SPIRVDescs;
2908extern const unsigned SPIRVInstrNameIndices[];
2909extern const char SPIRVInstrNameData[];
2910SPIRVGenInstrInfo::SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2911 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2912 InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 850);
2913}
2914
2915} // namespace llvm
2916
2917#endif // GET_INSTRINFO_CTOR_DTOR
2918
2919#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2920#undef GET_INSTRINFO_MC_HELPER_DECLS
2921
2922namespace llvm {
2923
2924class MCInst;
2925class FeatureBitset;
2926
2927namespace SPIRV_MC {
2928
2929void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2930
2931} // namespace SPIRV_MC
2932
2933} // namespace llvm
2934
2935#endif // GET_INSTRINFO_MC_HELPER_DECLS
2936
2937#ifdef GET_INSTRINFO_MC_HELPERS
2938#undef GET_INSTRINFO_MC_HELPERS
2939
2940namespace llvm::SPIRV_MC {
2941
2942
2943} // namespace llvm::SPIRV_MC
2944
2945#endif // GET_INSTRINFO_MC_HELPERS
2946
2947#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2948 defined(GET_AVAILABLE_OPCODE_CHECKER)
2949#define GET_COMPUTE_FEATURES
2950#endif
2951#ifdef GET_COMPUTE_FEATURES
2952#undef GET_COMPUTE_FEATURES
2953
2954namespace llvm::SPIRV_MC {
2955
2956// Bits for subtarget features that participate in instruction matching.
2957enum SubtargetFeatureBits : uint8_t {
2958};
2959
2960inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2961 FeatureBitset Features;
2962 return Features;
2963}
2964
2965inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2966 enum : uint8_t {
2967 CEFBS_None,
2968 };
2969
2970 static constexpr FeatureBitset FeatureBitsets[] = {
2971 {}, // CEFBS_None
2972 };
2973 static constexpr uint8_t RequiredFeaturesRefs[] = {
2974 CEFBS_None, // PHI
2975 CEFBS_None, // INLINEASM
2976 CEFBS_None, // INLINEASM_BR
2977 CEFBS_None, // CFI_INSTRUCTION
2978 CEFBS_None, // EH_LABEL
2979 CEFBS_None, // GC_LABEL
2980 CEFBS_None, // ANNOTATION_LABEL
2981 CEFBS_None, // KILL
2982 CEFBS_None, // EXTRACT_SUBREG
2983 CEFBS_None, // INSERT_SUBREG
2984 CEFBS_None, // IMPLICIT_DEF
2985 CEFBS_None, // INIT_UNDEF
2986 CEFBS_None, // SUBREG_TO_REG
2987 CEFBS_None, // COPY_TO_REGCLASS
2988 CEFBS_None, // DBG_VALUE
2989 CEFBS_None, // DBG_VALUE_LIST
2990 CEFBS_None, // DBG_INSTR_REF
2991 CEFBS_None, // DBG_PHI
2992 CEFBS_None, // DBG_LABEL
2993 CEFBS_None, // REG_SEQUENCE
2994 CEFBS_None, // COPY
2995 CEFBS_None, // COPY_LANEMASK
2996 CEFBS_None, // BUNDLE
2997 CEFBS_None, // LIFETIME_START
2998 CEFBS_None, // LIFETIME_END
2999 CEFBS_None, // PSEUDO_PROBE
3000 CEFBS_None, // ARITH_FENCE
3001 CEFBS_None, // STACKMAP
3002 CEFBS_None, // FENTRY_CALL
3003 CEFBS_None, // PATCHPOINT
3004 CEFBS_None, // LOAD_STACK_GUARD
3005 CEFBS_None, // PREALLOCATED_SETUP
3006 CEFBS_None, // PREALLOCATED_ARG
3007 CEFBS_None, // STATEPOINT
3008 CEFBS_None, // LOCAL_ESCAPE
3009 CEFBS_None, // FAULTING_OP
3010 CEFBS_None, // PATCHABLE_OP
3011 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
3012 CEFBS_None, // PATCHABLE_RET
3013 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
3014 CEFBS_None, // PATCHABLE_TAIL_CALL
3015 CEFBS_None, // PATCHABLE_EVENT_CALL
3016 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
3017 CEFBS_None, // ICALL_BRANCH_FUNNEL
3018 CEFBS_None, // FAKE_USE
3019 CEFBS_None, // MEMBARRIER
3020 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
3021 CEFBS_None, // RELOC_NONE
3022 CEFBS_None, // CONVERGENCECTRL_ENTRY
3023 CEFBS_None, // CONVERGENCECTRL_ANCHOR
3024 CEFBS_None, // CONVERGENCECTRL_LOOP
3025 CEFBS_None, // CONVERGENCECTRL_GLUE
3026 CEFBS_None, // G_ASSERT_SEXT
3027 CEFBS_None, // G_ASSERT_ZEXT
3028 CEFBS_None, // G_ASSERT_ALIGN
3029 CEFBS_None, // G_ADD
3030 CEFBS_None, // G_SUB
3031 CEFBS_None, // G_MUL
3032 CEFBS_None, // G_SDIV
3033 CEFBS_None, // G_UDIV
3034 CEFBS_None, // G_SREM
3035 CEFBS_None, // G_UREM
3036 CEFBS_None, // G_SDIVREM
3037 CEFBS_None, // G_UDIVREM
3038 CEFBS_None, // G_AND
3039 CEFBS_None, // G_OR
3040 CEFBS_None, // G_XOR
3041 CEFBS_None, // G_ABDS
3042 CEFBS_None, // G_ABDU
3043 CEFBS_None, // G_UAVGFLOOR
3044 CEFBS_None, // G_UAVGCEIL
3045 CEFBS_None, // G_SAVGFLOOR
3046 CEFBS_None, // G_SAVGCEIL
3047 CEFBS_None, // G_IMPLICIT_DEF
3048 CEFBS_None, // G_PHI
3049 CEFBS_None, // G_FRAME_INDEX
3050 CEFBS_None, // G_GLOBAL_VALUE
3051 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3052 CEFBS_None, // G_CONSTANT_POOL
3053 CEFBS_None, // G_EXTRACT
3054 CEFBS_None, // G_UNMERGE_VALUES
3055 CEFBS_None, // G_INSERT
3056 CEFBS_None, // G_MERGE_VALUES
3057 CEFBS_None, // G_BUILD_VECTOR
3058 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3059 CEFBS_None, // G_CONCAT_VECTORS
3060 CEFBS_None, // G_PTRTOINT
3061 CEFBS_None, // G_INTTOPTR
3062 CEFBS_None, // G_BITCAST
3063 CEFBS_None, // G_FREEZE
3064 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3065 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3066 CEFBS_None, // G_INTRINSIC_TRUNC
3067 CEFBS_None, // G_INTRINSIC_ROUND
3068 CEFBS_None, // G_INTRINSIC_LRINT
3069 CEFBS_None, // G_INTRINSIC_LLRINT
3070 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3071 CEFBS_None, // G_READCYCLECOUNTER
3072 CEFBS_None, // G_READSTEADYCOUNTER
3073 CEFBS_None, // G_LOAD
3074 CEFBS_None, // G_SEXTLOAD
3075 CEFBS_None, // G_ZEXTLOAD
3076 CEFBS_None, // G_FPEXTLOAD
3077 CEFBS_None, // G_INDEXED_LOAD
3078 CEFBS_None, // G_INDEXED_SEXTLOAD
3079 CEFBS_None, // G_INDEXED_ZEXTLOAD
3080 CEFBS_None, // G_STORE
3081 CEFBS_None, // G_FPTRUNCSTORE
3082 CEFBS_None, // G_INDEXED_STORE
3083 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3084 CEFBS_None, // G_ATOMIC_CMPXCHG
3085 CEFBS_None, // G_ATOMICRMW_XCHG
3086 CEFBS_None, // G_ATOMICRMW_ADD
3087 CEFBS_None, // G_ATOMICRMW_SUB
3088 CEFBS_None, // G_ATOMICRMW_AND
3089 CEFBS_None, // G_ATOMICRMW_NAND
3090 CEFBS_None, // G_ATOMICRMW_OR
3091 CEFBS_None, // G_ATOMICRMW_XOR
3092 CEFBS_None, // G_ATOMICRMW_MAX
3093 CEFBS_None, // G_ATOMICRMW_MIN
3094 CEFBS_None, // G_ATOMICRMW_UMAX
3095 CEFBS_None, // G_ATOMICRMW_UMIN
3096 CEFBS_None, // G_ATOMICRMW_FADD
3097 CEFBS_None, // G_ATOMICRMW_FSUB
3098 CEFBS_None, // G_ATOMICRMW_FMAX
3099 CEFBS_None, // G_ATOMICRMW_FMIN
3100 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3101 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3102 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
3103 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
3104 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3105 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3106 CEFBS_None, // G_ATOMICRMW_USUB_COND
3107 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3108 CEFBS_None, // G_FENCE
3109 CEFBS_None, // G_PREFETCH
3110 CEFBS_None, // G_BRCOND
3111 CEFBS_None, // G_BRINDIRECT
3112 CEFBS_None, // G_INVOKE_REGION_START
3113 CEFBS_None, // G_INTRINSIC
3114 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3115 CEFBS_None, // G_INTRINSIC_CONVERGENT
3116 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3117 CEFBS_None, // G_ANYEXT
3118 CEFBS_None, // G_TRUNC
3119 CEFBS_None, // G_TRUNC_SSAT_S
3120 CEFBS_None, // G_TRUNC_SSAT_U
3121 CEFBS_None, // G_TRUNC_USAT_U
3122 CEFBS_None, // G_CONSTANT
3123 CEFBS_None, // G_FCONSTANT
3124 CEFBS_None, // G_VASTART
3125 CEFBS_None, // G_VAARG
3126 CEFBS_None, // G_SEXT
3127 CEFBS_None, // G_SEXT_INREG
3128 CEFBS_None, // G_ZEXT
3129 CEFBS_None, // G_SHL
3130 CEFBS_None, // G_LSHR
3131 CEFBS_None, // G_ASHR
3132 CEFBS_None, // G_FSHL
3133 CEFBS_None, // G_FSHR
3134 CEFBS_None, // G_ROTR
3135 CEFBS_None, // G_ROTL
3136 CEFBS_None, // G_ICMP
3137 CEFBS_None, // G_FCMP
3138 CEFBS_None, // G_SCMP
3139 CEFBS_None, // G_UCMP
3140 CEFBS_None, // G_SELECT
3141 CEFBS_None, // G_UADDO
3142 CEFBS_None, // G_UADDE
3143 CEFBS_None, // G_USUBO
3144 CEFBS_None, // G_USUBE
3145 CEFBS_None, // G_SADDO
3146 CEFBS_None, // G_SADDE
3147 CEFBS_None, // G_SSUBO
3148 CEFBS_None, // G_SSUBE
3149 CEFBS_None, // G_UMULO
3150 CEFBS_None, // G_SMULO
3151 CEFBS_None, // G_UMULH
3152 CEFBS_None, // G_SMULH
3153 CEFBS_None, // G_UADDSAT
3154 CEFBS_None, // G_SADDSAT
3155 CEFBS_None, // G_USUBSAT
3156 CEFBS_None, // G_SSUBSAT
3157 CEFBS_None, // G_USHLSAT
3158 CEFBS_None, // G_SSHLSAT
3159 CEFBS_None, // G_SMULFIX
3160 CEFBS_None, // G_UMULFIX
3161 CEFBS_None, // G_SMULFIXSAT
3162 CEFBS_None, // G_UMULFIXSAT
3163 CEFBS_None, // G_SDIVFIX
3164 CEFBS_None, // G_UDIVFIX
3165 CEFBS_None, // G_SDIVFIXSAT
3166 CEFBS_None, // G_UDIVFIXSAT
3167 CEFBS_None, // G_FADD
3168 CEFBS_None, // G_FSUB
3169 CEFBS_None, // G_FMUL
3170 CEFBS_None, // G_FMA
3171 CEFBS_None, // G_FMAD
3172 CEFBS_None, // G_FDIV
3173 CEFBS_None, // G_FREM
3174 CEFBS_None, // G_FMODF
3175 CEFBS_None, // G_FPOW
3176 CEFBS_None, // G_FPOWI
3177 CEFBS_None, // G_FEXP
3178 CEFBS_None, // G_FEXP2
3179 CEFBS_None, // G_FEXP10
3180 CEFBS_None, // G_FLOG
3181 CEFBS_None, // G_FLOG2
3182 CEFBS_None, // G_FLOG10
3183 CEFBS_None, // G_FLDEXP
3184 CEFBS_None, // G_FFREXP
3185 CEFBS_None, // G_FNEG
3186 CEFBS_None, // G_FPEXT
3187 CEFBS_None, // G_FPTRUNC
3188 CEFBS_None, // G_FPTOSI
3189 CEFBS_None, // G_FPTOUI
3190 CEFBS_None, // G_SITOFP
3191 CEFBS_None, // G_UITOFP
3192 CEFBS_None, // G_FPTOSI_SAT
3193 CEFBS_None, // G_FPTOUI_SAT
3194 CEFBS_None, // G_FABS
3195 CEFBS_None, // G_FCOPYSIGN
3196 CEFBS_None, // G_IS_FPCLASS
3197 CEFBS_None, // G_FCANONICALIZE
3198 CEFBS_None, // G_FMINNUM
3199 CEFBS_None, // G_FMAXNUM
3200 CEFBS_None, // G_FMINNUM_IEEE
3201 CEFBS_None, // G_FMAXNUM_IEEE
3202 CEFBS_None, // G_FMINIMUM
3203 CEFBS_None, // G_FMAXIMUM
3204 CEFBS_None, // G_FMINIMUMNUM
3205 CEFBS_None, // G_FMAXIMUMNUM
3206 CEFBS_None, // G_GET_FPENV
3207 CEFBS_None, // G_SET_FPENV
3208 CEFBS_None, // G_RESET_FPENV
3209 CEFBS_None, // G_GET_FPMODE
3210 CEFBS_None, // G_SET_FPMODE
3211 CEFBS_None, // G_RESET_FPMODE
3212 CEFBS_None, // G_GET_ROUNDING
3213 CEFBS_None, // G_SET_ROUNDING
3214 CEFBS_None, // G_PTR_ADD
3215 CEFBS_None, // G_PTRMASK
3216 CEFBS_None, // G_SMIN
3217 CEFBS_None, // G_SMAX
3218 CEFBS_None, // G_UMIN
3219 CEFBS_None, // G_UMAX
3220 CEFBS_None, // G_ABS
3221 CEFBS_None, // G_LROUND
3222 CEFBS_None, // G_LLROUND
3223 CEFBS_None, // G_BR
3224 CEFBS_None, // G_BRJT
3225 CEFBS_None, // G_VSCALE
3226 CEFBS_None, // G_INSERT_SUBVECTOR
3227 CEFBS_None, // G_EXTRACT_SUBVECTOR
3228 CEFBS_None, // G_INSERT_VECTOR_ELT
3229 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3230 CEFBS_None, // G_SHUFFLE_VECTOR
3231 CEFBS_None, // G_SPLAT_VECTOR
3232 CEFBS_None, // G_STEP_VECTOR
3233 CEFBS_None, // G_VECTOR_COMPRESS
3234 CEFBS_None, // G_CTTZ
3235 CEFBS_None, // G_CTTZ_ZERO_POISON
3236 CEFBS_None, // G_CTLZ
3237 CEFBS_None, // G_CTLZ_ZERO_POISON
3238 CEFBS_None, // G_CTLS
3239 CEFBS_None, // G_CTPOP
3240 CEFBS_None, // G_BSWAP
3241 CEFBS_None, // G_BITREVERSE
3242 CEFBS_None, // G_CLMUL
3243 CEFBS_None, // G_FCEIL
3244 CEFBS_None, // G_FCOS
3245 CEFBS_None, // G_FSIN
3246 CEFBS_None, // G_FSINCOS
3247 CEFBS_None, // G_FTAN
3248 CEFBS_None, // G_FACOS
3249 CEFBS_None, // G_FASIN
3250 CEFBS_None, // G_FATAN
3251 CEFBS_None, // G_FATAN2
3252 CEFBS_None, // G_FCOSH
3253 CEFBS_None, // G_FSINH
3254 CEFBS_None, // G_FTANH
3255 CEFBS_None, // G_FSQRT
3256 CEFBS_None, // G_FFLOOR
3257 CEFBS_None, // G_FRINT
3258 CEFBS_None, // G_FNEARBYINT
3259 CEFBS_None, // G_ADDRSPACE_CAST
3260 CEFBS_None, // G_BLOCK_ADDR
3261 CEFBS_None, // G_JUMP_TABLE
3262 CEFBS_None, // G_DYN_STACKALLOC
3263 CEFBS_None, // G_STACKSAVE
3264 CEFBS_None, // G_STACKRESTORE
3265 CEFBS_None, // G_STRICT_FADD
3266 CEFBS_None, // G_STRICT_FSUB
3267 CEFBS_None, // G_STRICT_FMUL
3268 CEFBS_None, // G_STRICT_FDIV
3269 CEFBS_None, // G_STRICT_FREM
3270 CEFBS_None, // G_STRICT_FMA
3271 CEFBS_None, // G_STRICT_FSQRT
3272 CEFBS_None, // G_STRICT_FLDEXP
3273 CEFBS_None, // G_STRICT_FCMP
3274 CEFBS_None, // G_STRICT_FCMPS
3275 CEFBS_None, // G_READ_REGISTER
3276 CEFBS_None, // G_WRITE_REGISTER
3277 CEFBS_None, // G_MEMCPY
3278 CEFBS_None, // G_MEMCPY_INLINE
3279 CEFBS_None, // G_MEMMOVE
3280 CEFBS_None, // G_MEMSET
3281 CEFBS_None, // G_BZERO
3282 CEFBS_None, // G_MEMSET_INLINE
3283 CEFBS_None, // G_TRAP
3284 CEFBS_None, // G_DEBUGTRAP
3285 CEFBS_None, // G_UBSANTRAP
3286 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3287 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3288 CEFBS_None, // G_VECREDUCE_FADD
3289 CEFBS_None, // G_VECREDUCE_FMUL
3290 CEFBS_None, // G_VECREDUCE_FMAX
3291 CEFBS_None, // G_VECREDUCE_FMIN
3292 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3293 CEFBS_None, // G_VECREDUCE_FMINIMUM
3294 CEFBS_None, // G_VECREDUCE_ADD
3295 CEFBS_None, // G_VECREDUCE_MUL
3296 CEFBS_None, // G_VECREDUCE_AND
3297 CEFBS_None, // G_VECREDUCE_OR
3298 CEFBS_None, // G_VECREDUCE_XOR
3299 CEFBS_None, // G_VECREDUCE_SMAX
3300 CEFBS_None, // G_VECREDUCE_SMIN
3301 CEFBS_None, // G_VECREDUCE_UMAX
3302 CEFBS_None, // G_VECREDUCE_UMIN
3303 CEFBS_None, // G_SBFX
3304 CEFBS_None, // G_UBFX
3305 CEFBS_None, // ASSIGN_TYPE
3306 CEFBS_None, // UNKNOWN_type
3307 CEFBS_None, // OpAbortKHR
3308 CEFBS_None, // OpAccessChain
3309 CEFBS_None, // OpAliasDomainDeclINTEL
3310 CEFBS_None, // OpAliasScopeDeclINTEL
3311 CEFBS_None, // OpAliasScopeListDeclINTEL
3312 CEFBS_None, // OpAll
3313 CEFBS_None, // OpAny
3314 CEFBS_None, // OpArbitraryFloatACosALTERA
3315 CEFBS_None, // OpArbitraryFloatACosPiALTERA
3316 CEFBS_None, // OpArbitraryFloatASinALTERA
3317 CEFBS_None, // OpArbitraryFloatASinPiALTERA
3318 CEFBS_None, // OpArbitraryFloatATan2ALTERA
3319 CEFBS_None, // OpArbitraryFloatATanALTERA
3320 CEFBS_None, // OpArbitraryFloatATanPiALTERA
3321 CEFBS_None, // OpArbitraryFloatAddALTERA
3322 CEFBS_None, // OpArbitraryFloatCastALTERA
3323 CEFBS_None, // OpArbitraryFloatCastFromIntALTERA
3324 CEFBS_None, // OpArbitraryFloatCastToIntALTERA
3325 CEFBS_None, // OpArbitraryFloatCbrtALTERA
3326 CEFBS_None, // OpArbitraryFloatCosALTERA
3327 CEFBS_None, // OpArbitraryFloatCosPiALTERA
3328 CEFBS_None, // OpArbitraryFloatDivALTERA
3329 CEFBS_None, // OpArbitraryFloatEQALTERA
3330 CEFBS_None, // OpArbitraryFloatExp10ALTERA
3331 CEFBS_None, // OpArbitraryFloatExp2ALTERA
3332 CEFBS_None, // OpArbitraryFloatExpALTERA
3333 CEFBS_None, // OpArbitraryFloatExpm1ALTERA
3334 CEFBS_None, // OpArbitraryFloatGEALTERA
3335 CEFBS_None, // OpArbitraryFloatGTALTERA
3336 CEFBS_None, // OpArbitraryFloatHypotALTERA
3337 CEFBS_None, // OpArbitraryFloatLEALTERA
3338 CEFBS_None, // OpArbitraryFloatLTALTERA
3339 CEFBS_None, // OpArbitraryFloatLog10ALTERA
3340 CEFBS_None, // OpArbitraryFloatLog1pALTERA
3341 CEFBS_None, // OpArbitraryFloatLog2ALTERA
3342 CEFBS_None, // OpArbitraryFloatLogALTERA
3343 CEFBS_None, // OpArbitraryFloatMulALTERA
3344 CEFBS_None, // OpArbitraryFloatPowALTERA
3345 CEFBS_None, // OpArbitraryFloatPowNALTERA
3346 CEFBS_None, // OpArbitraryFloatPowRALTERA
3347 CEFBS_None, // OpArbitraryFloatRSqrtALTERA
3348 CEFBS_None, // OpArbitraryFloatRecipALTERA
3349 CEFBS_None, // OpArbitraryFloatSinALTERA
3350 CEFBS_None, // OpArbitraryFloatSinCosALTERA
3351 CEFBS_None, // OpArbitraryFloatSinCosPiALTERA
3352 CEFBS_None, // OpArbitraryFloatSinPiALTERA
3353 CEFBS_None, // OpArbitraryFloatSqrtALTERA
3354 CEFBS_None, // OpArbitraryFloatSubALTERA
3355 CEFBS_None, // OpArithmeticFenceEXT
3356 CEFBS_None, // OpArrayLength
3357 CEFBS_None, // OpAsmCallINTEL
3358 CEFBS_None, // OpAsmINTEL
3359 CEFBS_None, // OpAsmTargetINTEL
3360 CEFBS_None, // OpAssumeTrueKHR
3361 CEFBS_None, // OpAtomicAnd
3362 CEFBS_None, // OpAtomicCompareExchange
3363 CEFBS_None, // OpAtomicCompareExchangeWeak
3364 CEFBS_None, // OpAtomicExchange
3365 CEFBS_None, // OpAtomicFAddEXT
3366 CEFBS_None, // OpAtomicFMaxEXT
3367 CEFBS_None, // OpAtomicFMinEXT
3368 CEFBS_None, // OpAtomicFlagClear
3369 CEFBS_None, // OpAtomicFlagTestAndSet
3370 CEFBS_None, // OpAtomicIAdd
3371 CEFBS_None, // OpAtomicIDecrement
3372 CEFBS_None, // OpAtomicIIncrement
3373 CEFBS_None, // OpAtomicISub
3374 CEFBS_None, // OpAtomicLoad
3375 CEFBS_None, // OpAtomicOr
3376 CEFBS_None, // OpAtomicSMax
3377 CEFBS_None, // OpAtomicSMin
3378 CEFBS_None, // OpAtomicStore
3379 CEFBS_None, // OpAtomicUMax
3380 CEFBS_None, // OpAtomicUMin
3381 CEFBS_None, // OpAtomicXor
3382 CEFBS_None, // OpBitCount
3383 CEFBS_None, // OpBitFieldInsert
3384 CEFBS_None, // OpBitFieldSExtract
3385 CEFBS_None, // OpBitFieldUExtract
3386 CEFBS_None, // OpBitReverse
3387 CEFBS_None, // OpBitcast
3388 CEFBS_None, // OpBitwiseAndS
3389 CEFBS_None, // OpBitwiseAndV
3390 CEFBS_None, // OpBitwiseFunctionINTEL
3391 CEFBS_None, // OpBitwiseOrS
3392 CEFBS_None, // OpBitwiseOrV
3393 CEFBS_None, // OpBitwiseXorS
3394 CEFBS_None, // OpBitwiseXorV
3395 CEFBS_None, // OpBranch
3396 CEFBS_None, // OpBranchConditional
3397 CEFBS_None, // OpBuildNDRange
3398 CEFBS_None, // OpCapability
3399 CEFBS_None, // OpCaptureEventProfilingInfo
3400 CEFBS_None, // OpCommitReadPipe
3401 CEFBS_None, // OpCommitWritePipe
3402 CEFBS_None, // OpCompositeConstruct
3403 CEFBS_None, // OpCompositeConstructContinuedINTEL
3404 CEFBS_None, // OpCompositeExtract
3405 CEFBS_None, // OpCompositeInsert
3406 CEFBS_None, // OpConstantComposite
3407 CEFBS_None, // OpConstantCompositeContinuedINTEL
3408 CEFBS_None, // OpConstantF
3409 CEFBS_None, // OpConstantFalse
3410 CEFBS_None, // OpConstantFunctionPointerINTEL
3411 CEFBS_None, // OpConstantI
3412 CEFBS_None, // OpConstantNull
3413 CEFBS_None, // OpConstantSampler
3414 CEFBS_None, // OpConstantTrue
3415 CEFBS_None, // OpControlBarrier
3416 CEFBS_None, // OpControlBarrierArriveINTEL
3417 CEFBS_None, // OpControlBarrierWaitINTEL
3418 CEFBS_None, // OpConvertBF16ToFINTEL
3419 CEFBS_None, // OpConvertFToBF16INTEL
3420 CEFBS_None, // OpConvertFToS
3421 CEFBS_None, // OpConvertFToU
3422 CEFBS_None, // OpConvertHandleToImageINTEL
3423 CEFBS_None, // OpConvertHandleToSampledImageINTEL
3424 CEFBS_None, // OpConvertHandleToSamplerINTEL
3425 CEFBS_None, // OpConvertPtrToU
3426 CEFBS_None, // OpConvertSToF
3427 CEFBS_None, // OpConvertUToF
3428 CEFBS_None, // OpConvertUToPtr
3429 CEFBS_None, // OpCooperativeMatrixConstructCheckedINTEL
3430 CEFBS_None, // OpCooperativeMatrixGetElementCoordINTEL
3431 CEFBS_None, // OpCooperativeMatrixLengthKHR
3432 CEFBS_None, // OpCooperativeMatrixLoadCheckedINTEL
3433 CEFBS_None, // OpCooperativeMatrixLoadKHR
3434 CEFBS_None, // OpCooperativeMatrixMulAddKHR
3435 CEFBS_None, // OpCooperativeMatrixPrefetchINTEL
3436 CEFBS_None, // OpCooperativeMatrixStoreCheckedINTEL
3437 CEFBS_None, // OpCooperativeMatrixStoreKHR
3438 CEFBS_None, // OpCopyLogical
3439 CEFBS_None, // OpCopyMemory
3440 CEFBS_None, // OpCopyMemorySized
3441 CEFBS_None, // OpCopyObject
3442 CEFBS_None, // OpCreateUserEvent
3443 CEFBS_None, // OpCrossWorkgroupCastToPtrINTEL
3444 CEFBS_None, // OpDPdx
3445 CEFBS_None, // OpDPdxCoarse
3446 CEFBS_None, // OpDPdxFine
3447 CEFBS_None, // OpDPdy
3448 CEFBS_None, // OpDPdyCoarse
3449 CEFBS_None, // OpDPdyFine
3450 CEFBS_None, // OpDecorate
3451 CEFBS_None, // OpDecorateId
3452 CEFBS_None, // OpDecorateString
3453 CEFBS_None, // OpDemoteToHelperInvocation
3454 CEFBS_None, // OpDot
3455 CEFBS_None, // OpEmitStreamVertex
3456 CEFBS_None, // OpEmitVertex
3457 CEFBS_None, // OpEndPrimitive
3458 CEFBS_None, // OpEndStreamPrimitive
3459 CEFBS_None, // OpEnqueueKernel
3460 CEFBS_None, // OpEntryPoint
3461 CEFBS_None, // OpExecutionMode
3462 CEFBS_None, // OpExecutionModeId
3463 CEFBS_None, // OpExpectKHR
3464 CEFBS_None, // OpExtInst
3465 CEFBS_None, // OpExtInstImport
3466 CEFBS_None, // OpExtension
3467 CEFBS_None, // OpFAddS
3468 CEFBS_None, // OpFAddV
3469 CEFBS_None, // OpFConvert
3470 CEFBS_None, // OpFDivS
3471 CEFBS_None, // OpFDivV
3472 CEFBS_None, // OpFMod
3473 CEFBS_None, // OpFMulS
3474 CEFBS_None, // OpFMulV
3475 CEFBS_None, // OpFNegate
3476 CEFBS_None, // OpFNegateV
3477 CEFBS_None, // OpFOrdEqual
3478 CEFBS_None, // OpFOrdGreaterThan
3479 CEFBS_None, // OpFOrdGreaterThanEqual
3480 CEFBS_None, // OpFOrdLessThan
3481 CEFBS_None, // OpFOrdLessThanEqual
3482 CEFBS_None, // OpFOrdNotEqual
3483 CEFBS_None, // OpFRemS
3484 CEFBS_None, // OpFRemV
3485 CEFBS_None, // OpFSubS
3486 CEFBS_None, // OpFSubV
3487 CEFBS_None, // OpFUnordEqual
3488 CEFBS_None, // OpFUnordGreaterThan
3489 CEFBS_None, // OpFUnordGreaterThanEqual
3490 CEFBS_None, // OpFUnordLessThan
3491 CEFBS_None, // OpFUnordLessThanEqual
3492 CEFBS_None, // OpFUnordNotEqual
3493 CEFBS_None, // OpFixedCosALTERA
3494 CEFBS_None, // OpFixedCosPiALTERA
3495 CEFBS_None, // OpFixedExpALTERA
3496 CEFBS_None, // OpFixedLogALTERA
3497 CEFBS_None, // OpFixedRecipALTERA
3498 CEFBS_None, // OpFixedRsqrtALTERA
3499 CEFBS_None, // OpFixedSinALTERA
3500 CEFBS_None, // OpFixedSinCosALTERA
3501 CEFBS_None, // OpFixedSinCosPiALTERA
3502 CEFBS_None, // OpFixedSinPiALTERA
3503 CEFBS_None, // OpFixedSqrtALTERA
3504 CEFBS_None, // OpFmaKHR
3505 CEFBS_None, // OpFreezeKHR
3506 CEFBS_None, // OpFunction
3507 CEFBS_None, // OpFunctionCall
3508 CEFBS_None, // OpFunctionEnd
3509 CEFBS_None, // OpFunctionParameter
3510 CEFBS_None, // OpFunctionPointerCallINTEL
3511 CEFBS_None, // OpFwidth
3512 CEFBS_None, // OpFwidthCoarse
3513 CEFBS_None, // OpFwidthFine
3514 CEFBS_None, // OpGenericCastToPtr
3515 CEFBS_None, // OpGenericCastToPtrExplicit
3516 CEFBS_None, // OpGenericPtrMemSemantics
3517 CEFBS_None, // OpGetDefaultQueue
3518 CEFBS_None, // OpGetMaxPipePackets
3519 CEFBS_None, // OpGetNumPipePackets
3520 CEFBS_None, // OpGroupAll
3521 CEFBS_None, // OpGroupAny
3522 CEFBS_None, // OpGroupAsyncCopy
3523 CEFBS_None, // OpGroupBitwiseAndKHR
3524 CEFBS_None, // OpGroupBitwiseOrKHR
3525 CEFBS_None, // OpGroupBitwiseXorKHR
3526 CEFBS_None, // OpGroupBroadcast
3527 CEFBS_None, // OpGroupCommitReadPipe
3528 CEFBS_None, // OpGroupCommitWritePipe
3529 CEFBS_None, // OpGroupFAdd
3530 CEFBS_None, // OpGroupFMax
3531 CEFBS_None, // OpGroupFMin
3532 CEFBS_None, // OpGroupFMulKHR
3533 CEFBS_None, // OpGroupIAdd
3534 CEFBS_None, // OpGroupIMulKHR
3535 CEFBS_None, // OpGroupLogicalAndKHR
3536 CEFBS_None, // OpGroupLogicalOrKHR
3537 CEFBS_None, // OpGroupLogicalXorKHR
3538 CEFBS_None, // OpGroupNonUniformAll
3539 CEFBS_None, // OpGroupNonUniformAllEqual
3540 CEFBS_None, // OpGroupNonUniformAny
3541 CEFBS_None, // OpGroupNonUniformBallot
3542 CEFBS_None, // OpGroupNonUniformBallotBitCount
3543 CEFBS_None, // OpGroupNonUniformBallotBitExtract
3544 CEFBS_None, // OpGroupNonUniformBallotFindLSB
3545 CEFBS_None, // OpGroupNonUniformBallotFindMSB
3546 CEFBS_None, // OpGroupNonUniformBitwiseAnd
3547 CEFBS_None, // OpGroupNonUniformBitwiseOr
3548 CEFBS_None, // OpGroupNonUniformBitwiseXor
3549 CEFBS_None, // OpGroupNonUniformBroadcast
3550 CEFBS_None, // OpGroupNonUniformBroadcastFirst
3551 CEFBS_None, // OpGroupNonUniformElect
3552 CEFBS_None, // OpGroupNonUniformFAdd
3553 CEFBS_None, // OpGroupNonUniformFMax
3554 CEFBS_None, // OpGroupNonUniformFMin
3555 CEFBS_None, // OpGroupNonUniformFMul
3556 CEFBS_None, // OpGroupNonUniformIAdd
3557 CEFBS_None, // OpGroupNonUniformIMul
3558 CEFBS_None, // OpGroupNonUniformInverseBallot
3559 CEFBS_None, // OpGroupNonUniformLogicalAnd
3560 CEFBS_None, // OpGroupNonUniformLogicalOr
3561 CEFBS_None, // OpGroupNonUniformLogicalXor
3562 CEFBS_None, // OpGroupNonUniformQuadSwap
3563 CEFBS_None, // OpGroupNonUniformRotateKHR
3564 CEFBS_None, // OpGroupNonUniformSMax
3565 CEFBS_None, // OpGroupNonUniformSMin
3566 CEFBS_None, // OpGroupNonUniformShuffle
3567 CEFBS_None, // OpGroupNonUniformShuffleDown
3568 CEFBS_None, // OpGroupNonUniformShuffleUp
3569 CEFBS_None, // OpGroupNonUniformShuffleXor
3570 CEFBS_None, // OpGroupNonUniformUMax
3571 CEFBS_None, // OpGroupNonUniformUMin
3572 CEFBS_None, // OpGroupReserveReadPipePackets
3573 CEFBS_None, // OpGroupReserveWritePipePackets
3574 CEFBS_None, // OpGroupSMax
3575 CEFBS_None, // OpGroupSMin
3576 CEFBS_None, // OpGroupUMax
3577 CEFBS_None, // OpGroupUMin
3578 CEFBS_None, // OpGroupWaitEvents
3579 CEFBS_None, // OpIAddCarryS
3580 CEFBS_None, // OpIAddCarryV
3581 CEFBS_None, // OpIAddS
3582 CEFBS_None, // OpIAddV
3583 CEFBS_None, // OpIEqual
3584 CEFBS_None, // OpIMulS
3585 CEFBS_None, // OpIMulV
3586 CEFBS_None, // OpINotEqual
3587 CEFBS_None, // OpISubBorrowS
3588 CEFBS_None, // OpISubBorrowV
3589 CEFBS_None, // OpISubS
3590 CEFBS_None, // OpISubV
3591 CEFBS_None, // OpImage
3592 CEFBS_None, // OpImageDrefGather
3593 CEFBS_None, // OpImageFetch
3594 CEFBS_None, // OpImageGather
3595 CEFBS_None, // OpImageQueryFormat
3596 CEFBS_None, // OpImageQueryLevels
3597 CEFBS_None, // OpImageQueryLod
3598 CEFBS_None, // OpImageQueryOrder
3599 CEFBS_None, // OpImageQuerySamples
3600 CEFBS_None, // OpImageQuerySize
3601 CEFBS_None, // OpImageQuerySizeLod
3602 CEFBS_None, // OpImageRead
3603 CEFBS_None, // OpImageSampleDrefExplicitLod
3604 CEFBS_None, // OpImageSampleDrefImplicitLod
3605 CEFBS_None, // OpImageSampleExplicitLod
3606 CEFBS_None, // OpImageSampleFootprintNV
3607 CEFBS_None, // OpImageSampleImplicitLod
3608 CEFBS_None, // OpImageSampleProjDrefExplicitLod
3609 CEFBS_None, // OpImageSampleProjDrefImplicitLod
3610 CEFBS_None, // OpImageSampleProjExplicitLod
3611 CEFBS_None, // OpImageSampleProjImplicitLod
3612 CEFBS_None, // OpImageSparseDrefGather
3613 CEFBS_None, // OpImageSparseFetch
3614 CEFBS_None, // OpImageSparseGather
3615 CEFBS_None, // OpImageSparseRead
3616 CEFBS_None, // OpImageSparseSampleDrefExplicitLod
3617 CEFBS_None, // OpImageSparseSampleDrefImplicitLod
3618 CEFBS_None, // OpImageSparseSampleExplicitLod
3619 CEFBS_None, // OpImageSparseSampleImplicitLod
3620 CEFBS_None, // OpImageSparseSampleProjDrefExplicitLod
3621 CEFBS_None, // OpImageSparseSampleProjDrefImplicitLod
3622 CEFBS_None, // OpImageSparseSampleProjExplicitLod
3623 CEFBS_None, // OpImageSparseSampleProjImplicitLod
3624 CEFBS_None, // OpImageSparseTexelsResident
3625 CEFBS_None, // OpImageTexelPointer
3626 CEFBS_None, // OpImageWrite
3627 CEFBS_None, // OpInBoundsAccessChain
3628 CEFBS_None, // OpInBoundsPtrAccessChain
3629 CEFBS_None, // OpIsFinite
3630 CEFBS_None, // OpIsInf
3631 CEFBS_None, // OpIsNan
3632 CEFBS_None, // OpIsNormal
3633 CEFBS_None, // OpIsValidEvent
3634 CEFBS_None, // OpIsValidReserveId
3635 CEFBS_None, // OpKill
3636 CEFBS_None, // OpLabel
3637 CEFBS_None, // OpLessOrGreater
3638 CEFBS_None, // OpLifetimeStart
3639 CEFBS_None, // OpLifetimeStop
3640 CEFBS_None, // OpLine
3641 CEFBS_None, // OpLoad
3642 CEFBS_None, // OpLogicalAnd
3643 CEFBS_None, // OpLogicalEqual
3644 CEFBS_None, // OpLogicalNot
3645 CEFBS_None, // OpLogicalNotEqual
3646 CEFBS_None, // OpLogicalOr
3647 CEFBS_None, // OpLoopControlINTEL
3648 CEFBS_None, // OpLoopMerge
3649 CEFBS_None, // OpMaskedGatherINTEL
3650 CEFBS_None, // OpMaskedScatterINTEL
3651 CEFBS_None, // OpMatrixTimesMatrix
3652 CEFBS_None, // OpMatrixTimesScalar
3653 CEFBS_None, // OpMatrixTimesVector
3654 CEFBS_None, // OpMemberDecorate
3655 CEFBS_None, // OpMemberDecorateString
3656 CEFBS_None, // OpMemberName
3657 CEFBS_None, // OpMemoryBarrier
3658 CEFBS_None, // OpMemoryModel
3659 CEFBS_None, // OpMemoryNamedBarrier
3660 CEFBS_None, // OpModuleProcessed
3661 CEFBS_None, // OpName
3662 CEFBS_None, // OpNamedBarrierInitialize
3663 CEFBS_None, // OpNoLine
3664 CEFBS_None, // OpNop
3665 CEFBS_None, // OpNot
3666 CEFBS_None, // OpOrdered
3667 CEFBS_None, // OpOuterProduct
3668 CEFBS_None, // OpPhi
3669 CEFBS_None, // OpPoisonKHR
3670 CEFBS_None, // OpPredicatedLoadINTEL
3671 CEFBS_None, // OpPredicatedStoreINTEL
3672 CEFBS_None, // OpPtrAccessChain
3673 CEFBS_None, // OpPtrCastToCrossWorkgroupINTEL
3674 CEFBS_None, // OpPtrCastToGeneric
3675 CEFBS_None, // OpPtrDiff
3676 CEFBS_None, // OpPtrEqual
3677 CEFBS_None, // OpPtrNotEqual
3678 CEFBS_None, // OpQuantizeToF16
3679 CEFBS_None, // OpReadClockKHR
3680 CEFBS_None, // OpReadPipe
3681 CEFBS_None, // OpReadPipeBlockingALTERA
3682 CEFBS_None, // OpReleaseEvent
3683 CEFBS_None, // OpReserveReadPipePackets
3684 CEFBS_None, // OpReserveWritePipePackets
3685 CEFBS_None, // OpReservedReadPipe
3686 CEFBS_None, // OpReservedWritePipe
3687 CEFBS_None, // OpRestoreMemoryINTEL
3688 CEFBS_None, // OpRetainEvent
3689 CEFBS_None, // OpReturn
3690 CEFBS_None, // OpReturnValue
3691 CEFBS_None, // OpRoundFToTF32INTEL
3692 CEFBS_None, // OpSConvert
3693 CEFBS_None, // OpSDivS
3694 CEFBS_None, // OpSDivV
3695 CEFBS_None, // OpSDot
3696 CEFBS_None, // OpSDotAccSat
3697 CEFBS_None, // OpSGreaterThan
3698 CEFBS_None, // OpSGreaterThanEqual
3699 CEFBS_None, // OpSLessThan
3700 CEFBS_None, // OpSLessThanEqual
3701 CEFBS_None, // OpSMod
3702 CEFBS_None, // OpSMulExtended
3703 CEFBS_None, // OpSNegate
3704 CEFBS_None, // OpSRemS
3705 CEFBS_None, // OpSRemV
3706 CEFBS_None, // OpSUDot
3707 CEFBS_None, // OpSUDotAccSat
3708 CEFBS_None, // OpSampledImage
3709 CEFBS_None, // OpSatConvertSToU
3710 CEFBS_None, // OpSatConvertUToS
3711 CEFBS_None, // OpSaveMemoryINTEL
3712 CEFBS_None, // OpSelectSFSCond
3713 CEFBS_None, // OpSelectSFVCond
3714 CEFBS_None, // OpSelectSISCond
3715 CEFBS_None, // OpSelectSIVCond
3716 CEFBS_None, // OpSelectSPSCond
3717 CEFBS_None, // OpSelectSPVCond
3718 CEFBS_None, // OpSelectVFSCond
3719 CEFBS_None, // OpSelectVFVCond
3720 CEFBS_None, // OpSelectVISCond
3721 CEFBS_None, // OpSelectVIVCond
3722 CEFBS_None, // OpSelectVPSCond
3723 CEFBS_None, // OpSelectVPVCond
3724 CEFBS_None, // OpSelectionMerge
3725 CEFBS_None, // OpSetUserEventStatus
3726 CEFBS_None, // OpShiftLeftLogicalS
3727 CEFBS_None, // OpShiftLeftLogicalV
3728 CEFBS_None, // OpShiftRightArithmeticS
3729 CEFBS_None, // OpShiftRightArithmeticV
3730 CEFBS_None, // OpShiftRightLogicalS
3731 CEFBS_None, // OpShiftRightLogicalV
3732 CEFBS_None, // OpSignBitSet
3733 CEFBS_None, // OpSizeOf
3734 CEFBS_None, // OpSource
3735 CEFBS_None, // OpSourceContinued
3736 CEFBS_None, // OpSourceExtension
3737 CEFBS_None, // OpSpecConstant
3738 CEFBS_None, // OpSpecConstantComposite
3739 CEFBS_None, // OpSpecConstantCompositeContinuedINTEL
3740 CEFBS_None, // OpSpecConstantFalse
3741 CEFBS_None, // OpSpecConstantOp
3742 CEFBS_None, // OpSpecConstantTrue
3743 CEFBS_None, // OpStore
3744 CEFBS_None, // OpStrictFAddS
3745 CEFBS_None, // OpStrictFAddV
3746 CEFBS_None, // OpStrictFDivS
3747 CEFBS_None, // OpStrictFDivV
3748 CEFBS_None, // OpStrictFMulS
3749 CEFBS_None, // OpStrictFMulV
3750 CEFBS_None, // OpStrictFRemS
3751 CEFBS_None, // OpStrictFRemV
3752 CEFBS_None, // OpStrictFSubS
3753 CEFBS_None, // OpStrictFSubV
3754 CEFBS_None, // OpString
3755 CEFBS_None, // OpSubgroup2DBlockLoadINTEL
3756 CEFBS_None, // OpSubgroup2DBlockLoadTransformINTEL
3757 CEFBS_None, // OpSubgroup2DBlockLoadTransposeINTEL
3758 CEFBS_None, // OpSubgroup2DBlockPrefetchINTEL
3759 CEFBS_None, // OpSubgroup2DBlockStoreINTEL
3760 CEFBS_None, // OpSubgroupBlockReadINTEL
3761 CEFBS_None, // OpSubgroupBlockWriteINTEL
3762 CEFBS_None, // OpSubgroupImageBlockReadINTEL
3763 CEFBS_None, // OpSubgroupImageBlockWriteINTEL
3764 CEFBS_None, // OpSubgroupImageMediaBlockReadINTEL
3765 CEFBS_None, // OpSubgroupImageMediaBlockWriteINTEL
3766 CEFBS_None, // OpSubgroupMatrixMultiplyAccumulateINTEL
3767 CEFBS_None, // OpSubgroupShuffleDownINTEL
3768 CEFBS_None, // OpSubgroupShuffleINTEL
3769 CEFBS_None, // OpSubgroupShuffleUpINTEL
3770 CEFBS_None, // OpSubgroupShuffleXorINTEL
3771 CEFBS_None, // OpSwitch
3772 CEFBS_None, // OpTranspose
3773 CEFBS_None, // OpTypeAccelerationStructureNV
3774 CEFBS_None, // OpTypeArray
3775 CEFBS_None, // OpTypeBool
3776 CEFBS_None, // OpTypeCooperativeMatrixKHR
3777 CEFBS_None, // OpTypeCooperativeMatrixNV
3778 CEFBS_None, // OpTypeDeviceEvent
3779 CEFBS_None, // OpTypeEvent
3780 CEFBS_None, // OpTypeFloat
3781 CEFBS_None, // OpTypeForwardPointer
3782 CEFBS_None, // OpTypeFunction
3783 CEFBS_None, // OpTypeImage
3784 CEFBS_None, // OpTypeInt
3785 CEFBS_None, // OpTypeMatrix
3786 CEFBS_None, // OpTypeNamedBarrier
3787 CEFBS_None, // OpTypeOpaque
3788 CEFBS_None, // OpTypePipe
3789 CEFBS_None, // OpTypePipeStorage
3790 CEFBS_None, // OpTypePointer
3791 CEFBS_None, // OpTypeQueue
3792 CEFBS_None, // OpTypeReserveId
3793 CEFBS_None, // OpTypeRuntimeArray
3794 CEFBS_None, // OpTypeSampledImage
3795 CEFBS_None, // OpTypeSampler
3796 CEFBS_None, // OpTypeStruct
3797 CEFBS_None, // OpTypeStructContinuedINTEL
3798 CEFBS_None, // OpTypeVector
3799 CEFBS_None, // OpTypeVoid
3800 CEFBS_None, // OpUConvert
3801 CEFBS_None, // OpUDivS
3802 CEFBS_None, // OpUDivV
3803 CEFBS_None, // OpUDot
3804 CEFBS_None, // OpUDotAccSat
3805 CEFBS_None, // OpUGreaterThan
3806 CEFBS_None, // OpUGreaterThanEqual
3807 CEFBS_None, // OpULessThan
3808 CEFBS_None, // OpULessThanEqual
3809 CEFBS_None, // OpUModS
3810 CEFBS_None, // OpUModV
3811 CEFBS_None, // OpUMulExtended
3812 CEFBS_None, // OpUndef
3813 CEFBS_None, // OpUnordered
3814 CEFBS_None, // OpUnreachable
3815 CEFBS_None, // OpVariable
3816 CEFBS_None, // OpVariableLengthArrayINTEL
3817 CEFBS_None, // OpVectorExtractDynamic
3818 CEFBS_None, // OpVectorInsertDynamic
3819 CEFBS_None, // OpVectorShuffle
3820 CEFBS_None, // OpVectorTimesMatrix
3821 CEFBS_None, // OpVectorTimesScalar
3822 CEFBS_None, // OpWritePipe
3823 CEFBS_None, // OpWritePipeBlockingALTERA
3824 };
3825
3826 assert(Opcode < 850);
3827 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3828}
3829
3830
3831} // namespace llvm::SPIRV_MC
3832
3833#endif // GET_COMPUTE_FEATURES
3834
3835#ifdef GET_AVAILABLE_OPCODE_CHECKER
3836#undef GET_AVAILABLE_OPCODE_CHECKER
3837
3838namespace llvm::SPIRV_MC {
3839
3840bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3841 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3842 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3843 FeatureBitset MissingFeatures =
3844 (AvailableFeatures & RequiredFeatures) ^
3845 RequiredFeatures;
3846 return !MissingFeatures.any();
3847}
3848
3849} // namespace llvm::SPIRV_MC
3850
3851#endif // GET_AVAILABLE_OPCODE_CHECKER
3852
3853#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3854#undef ENABLE_INSTR_PREDICATE_VERIFIER
3855
3856#include <sstream>
3857
3858namespace llvm::SPIRV_MC {
3859
3860#ifndef NDEBUG
3861static const char *SubtargetFeatureNames[] = {
3862 nullptr
3863};
3864
3865#endif // NDEBUG
3866
3867void verifyInstructionPredicates(
3868 unsigned Opcode, const FeatureBitset &Features) {
3869#ifndef NDEBUG
3870 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3871 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3872 FeatureBitset MissingFeatures =
3873 (AvailableFeatures & RequiredFeatures) ^
3874 RequiredFeatures;
3875 if (MissingFeatures.any()) {
3876 std::ostringstream Msg;
3877 Msg << "Attempting to emit " << &SPIRVInstrNameData[SPIRVInstrNameIndices[Opcode]]
3878 << " instruction but the ";
3879 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3880 if (MissingFeatures.test(i))
3881 Msg << SubtargetFeatureNames[i] << " ";
3882 Msg << "predicate(s) are not met";
3883 report_fatal_error(Msg.str().c_str());
3884 }
3885#endif // NDEBUG
3886}
3887
3888} // namespace llvm::SPIRV_MC
3889
3890#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3891
3892