1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SPIRV {
13
14 enum {
15 PHI = 0, // Target.td:1301
16 INLINEASM = 1, // Target.td:1307
17 INLINEASM_BR = 2, // Target.td:1313
18 CFI_INSTRUCTION = 3, // Target.td:1322
19 EH_LABEL = 4, // Target.td:1331
20 GC_LABEL = 5, // Target.td:1340
21 ANNOTATION_LABEL = 6, // Target.td:1349
22 KILL = 7, // Target.td:1357
23 EXTRACT_SUBREG = 8, // Target.td:1364
24 INSERT_SUBREG = 9, // Target.td:1370
25 IMPLICIT_DEF = 10, // Target.td:1377
26 INIT_UNDEF = 11, // Target.td:1386
27 SUBREG_TO_REG = 12, // Target.td:1393
28 COPY_TO_REGCLASS = 13, // Target.td:1399
29 DBG_VALUE = 14, // Target.td:1406
30 DBG_VALUE_LIST = 15, // Target.td:1413
31 DBG_INSTR_REF = 16, // Target.td:1420
32 DBG_PHI = 17, // Target.td:1427
33 DBG_LABEL = 18, // Target.td:1434
34 REG_SEQUENCE = 19, // Target.td:1441
35 COPY = 20, // Target.td:1448
36 COPY_LANEMASK = 21, // Target.td:1456
37 BUNDLE = 22, // Target.td:1463
38 LIFETIME_START = 23, // Target.td:1469
39 LIFETIME_END = 24, // Target.td:1476
40 PSEUDO_PROBE = 25, // Target.td:1483
41 ARITH_FENCE = 26, // Target.td:1490
42 STACKMAP = 27, // Target.td:1499
43 FENTRY_CALL = 28, // Target.td:1634
44 PATCHPOINT = 29, // Target.td:1507
45 LOAD_STACK_GUARD = 30, // Target.td:1525
46 PREALLOCATED_SETUP = 31, // Target.td:1533
47 PREALLOCATED_ARG = 32, // Target.td:1539
48 STATEPOINT = 33, // Target.td:1516
49 LOCAL_ESCAPE = 34, // Target.td:1545
50 FAULTING_OP = 35, // Target.td:1554
51 PATCHABLE_OP = 36, // Target.td:1574
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1582
53 PATCHABLE_RET = 38, // Target.td:1589
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1598
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1606
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1614
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1624
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1644
59 FAKE_USE = 44, // Target.td:1564
60 MEMBARRIER = 45, // Target.td:1650
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1658
62 RELOC_NONE = 47, // Target.td:1666
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1677
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1673
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1681
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1685
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1472
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484
96 G_INSERT = 81, // GenericOpcodes.td:1492
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1502
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448
145 G_FENCE = 130, // GenericOpcodes.td:1450
146 G_PREFETCH = 131, // GenericOpcodes.td:1457
147 G_BRCOND = 132, // GenericOpcodes.td:1592
148 G_BRINDIRECT = 133, // GenericOpcodes.td:1601
149 G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624
150 G_INTRINSIC = 135, // GenericOpcodes.td:1544
151 G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551
152 G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560
153 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568
154 G_ANYEXT = 139, // GenericOpcodes.td:44
155 G_TRUNC = 140, // GenericOpcodes.td:83
156 G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90
157 G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97
158 G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104
159 G_CONSTANT = 144, // GenericOpcodes.td:165
160 G_FCONSTANT = 145, // GenericOpcodes.td:172
161 G_VASTART = 146, // GenericOpcodes.td:178
162 G_VAARG = 147, // GenericOpcodes.td:185
163 G_SEXT = 148, // GenericOpcodes.td:52
164 G_SEXT_INREG = 149, // GenericOpcodes.td:66
165 G_ZEXT = 150, // GenericOpcodes.td:74
166 G_SHL = 151, // GenericOpcodes.td:396
167 G_LSHR = 152, // GenericOpcodes.td:403
168 G_ASHR = 153, // GenericOpcodes.td:410
169 G_FSHL = 154, // GenericOpcodes.td:462
170 G_FSHR = 155, // GenericOpcodes.td:470
171 G_ROTR = 156, // GenericOpcodes.td:477
172 G_ROTL = 157, // GenericOpcodes.td:484
173 G_ICMP = 158, // GenericOpcodes.td:491
174 G_FCMP = 159, // GenericOpcodes.td:498
175 G_SCMP = 160, // GenericOpcodes.td:505
176 G_UCMP = 161, // GenericOpcodes.td:512
177 G_SELECT = 162, // GenericOpcodes.td:519
178 G_UADDO = 163, // GenericOpcodes.td:584
179 G_UADDE = 164, // GenericOpcodes.td:592
180 G_USUBO = 165, // GenericOpcodes.td:614
181 G_USUBE = 166, // GenericOpcodes.td:620
182 G_SADDO = 167, // GenericOpcodes.td:599
183 G_SADDE = 168, // GenericOpcodes.td:607
184 G_SSUBO = 169, // GenericOpcodes.td:627
185 G_SSUBE = 170, // GenericOpcodes.td:634
186 G_UMULO = 171, // GenericOpcodes.td:641
187 G_SMULO = 172, // GenericOpcodes.td:649
188 G_UMULH = 173, // GenericOpcodes.td:658
189 G_SMULH = 174, // GenericOpcodes.td:667
190 G_UADDSAT = 175, // GenericOpcodes.td:679
191 G_SADDSAT = 176, // GenericOpcodes.td:687
192 G_USUBSAT = 177, // GenericOpcodes.td:695
193 G_SSUBSAT = 178, // GenericOpcodes.td:703
194 G_USHLSAT = 179, // GenericOpcodes.td:711
195 G_SSHLSAT = 180, // GenericOpcodes.td:719
196 G_SMULFIX = 181, // GenericOpcodes.td:731
197 G_UMULFIX = 182, // GenericOpcodes.td:738
198 G_SMULFIXSAT = 183, // GenericOpcodes.td:748
199 G_UMULFIXSAT = 184, // GenericOpcodes.td:755
200 G_SDIVFIX = 185, // GenericOpcodes.td:766
201 G_UDIVFIX = 186, // GenericOpcodes.td:773
202 G_SDIVFIXSAT = 187, // GenericOpcodes.td:783
203 G_UDIVFIXSAT = 188, // GenericOpcodes.td:790
204 G_FADD = 189, // GenericOpcodes.td:963
205 G_FSUB = 190, // GenericOpcodes.td:971
206 G_FMUL = 191, // GenericOpcodes.td:979
207 G_FMA = 192, // GenericOpcodes.td:988
208 G_FMAD = 193, // GenericOpcodes.td:997
209 G_FDIV = 194, // GenericOpcodes.td:1005
210 G_FREM = 195, // GenericOpcodes.td:1012
211 G_FMODF = 196, // GenericOpcodes.td:1019
212 G_FPOW = 197, // GenericOpcodes.td:1026
213 G_FPOWI = 198, // GenericOpcodes.td:1033
214 G_FEXP = 199, // GenericOpcodes.td:1040
215 G_FEXP2 = 200, // GenericOpcodes.td:1047
216 G_FEXP10 = 201, // GenericOpcodes.td:1054
217 G_FLOG = 202, // GenericOpcodes.td:1061
218 G_FLOG2 = 203, // GenericOpcodes.td:1068
219 G_FLOG10 = 204, // GenericOpcodes.td:1075
220 G_FLDEXP = 205, // GenericOpcodes.td:1082
221 G_FFREXP = 206, // GenericOpcodes.td:1089
222 G_FNEG = 207, // GenericOpcodes.td:801
223 G_FPEXT = 208, // GenericOpcodes.td:807
224 G_FPTRUNC = 209, // GenericOpcodes.td:813
225 G_FPTOSI = 210, // GenericOpcodes.td:819
226 G_FPTOUI = 211, // GenericOpcodes.td:825
227 G_SITOFP = 212, // GenericOpcodes.td:831
228 G_UITOFP = 213, // GenericOpcodes.td:837
229 G_FPTOSI_SAT = 214, // GenericOpcodes.td:843
230 G_FPTOUI_SAT = 215, // GenericOpcodes.td:849
231 G_FABS = 216, // GenericOpcodes.td:855
232 G_FCOPYSIGN = 217, // GenericOpcodes.td:861
233 G_IS_FPCLASS = 218, // GenericOpcodes.td:874
234 G_FCANONICALIZE = 219, // GenericOpcodes.td:867
235 G_FMINNUM = 220, // GenericOpcodes.td:887
236 G_FMAXNUM = 221, // GenericOpcodes.td:894
237 G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912
238 G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919
239 G_FMINIMUM = 224, // GenericOpcodes.td:929
240 G_FMAXIMUM = 225, // GenericOpcodes.td:936
241 G_FMINIMUMNUM = 226, // GenericOpcodes.td:944
242 G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951
243 G_GET_FPENV = 228, // GenericOpcodes.td:1219
244 G_SET_FPENV = 229, // GenericOpcodes.td:1226
245 G_RESET_FPENV = 230, // GenericOpcodes.td:1233
246 G_GET_FPMODE = 231, // GenericOpcodes.td:1240
247 G_SET_FPMODE = 232, // GenericOpcodes.td:1247
248 G_RESET_FPMODE = 233, // GenericOpcodes.td:1254
249 G_GET_ROUNDING = 234, // GenericOpcodes.td:1311
250 G_SET_ROUNDING = 235, // GenericOpcodes.td:1317
251 G_PTR_ADD = 236, // GenericOpcodes.td:526
252 G_PTRMASK = 237, // GenericOpcodes.td:534
253 G_SMIN = 238, // GenericOpcodes.td:541
254 G_SMAX = 239, // GenericOpcodes.td:549
255 G_UMIN = 240, // GenericOpcodes.td:557
256 G_UMAX = 241, // GenericOpcodes.td:565
257 G_ABS = 242, // GenericOpcodes.td:573
258 G_LROUND = 243, // GenericOpcodes.td:283
259 G_LLROUND = 244, // GenericOpcodes.td:289
260 G_BR = 245, // GenericOpcodes.td:1582
261 G_BRJT = 246, // GenericOpcodes.td:1612
262 G_VSCALE = 247, // GenericOpcodes.td:1512
263 G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656
264 G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663
265 G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670
266 G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677
267 G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687
268 G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694
269 G_STEP_VECTOR = 254, // GenericOpcodes.td:1701
270 G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708
271 G_CTTZ = 256, // GenericOpcodes.td:205
272 G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211
273 G_CTLZ = 258, // GenericOpcodes.td:193
274 G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199
275 G_CTLS = 260, // GenericOpcodes.td:217
276 G_CTPOP = 261, // GenericOpcodes.td:223
277 G_BSWAP = 262, // GenericOpcodes.td:229
278 G_BITREVERSE = 263, // GenericOpcodes.td:235
279 G_FCEIL = 264, // GenericOpcodes.td:1096
280 G_FCOS = 265, // GenericOpcodes.td:1103
281 G_FSIN = 266, // GenericOpcodes.td:1110
282 G_FSINCOS = 267, // GenericOpcodes.td:1117
283 G_FTAN = 268, // GenericOpcodes.td:1124
284 G_FACOS = 269, // GenericOpcodes.td:1131
285 G_FASIN = 270, // GenericOpcodes.td:1138
286 G_FATAN = 271, // GenericOpcodes.td:1145
287 G_FATAN2 = 272, // GenericOpcodes.td:1152
288 G_FCOSH = 273, // GenericOpcodes.td:1159
289 G_FSINH = 274, // GenericOpcodes.td:1166
290 G_FTANH = 275, // GenericOpcodes.td:1173
291 G_FSQRT = 276, // GenericOpcodes.td:1183
292 G_FFLOOR = 277, // GenericOpcodes.td:1190
293 G_FRINT = 278, // GenericOpcodes.td:1197
294 G_FNEARBYINT = 279, // GenericOpcodes.td:1204
295 G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241
296 G_BLOCK_ADDR = 281, // GenericOpcodes.td:247
297 G_JUMP_TABLE = 282, // GenericOpcodes.td:253
298 G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259
299 G_STACKSAVE = 284, // GenericOpcodes.td:265
300 G_STACKRESTORE = 285, // GenericOpcodes.td:271
301 G_STRICT_FADD = 286, // GenericOpcodes.td:1758
302 G_STRICT_FSUB = 287, // GenericOpcodes.td:1759
303 G_STRICT_FMUL = 288, // GenericOpcodes.td:1760
304 G_STRICT_FDIV = 289, // GenericOpcodes.td:1761
305 G_STRICT_FREM = 290, // GenericOpcodes.td:1762
306 G_STRICT_FMA = 291, // GenericOpcodes.td:1763
307 G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764
308 G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765
309 G_READ_REGISTER = 294, // GenericOpcodes.td:1631
310 G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641
311 G_MEMCPY = 296, // GenericOpcodes.td:1771
312 G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779
313 G_MEMMOVE = 298, // GenericOpcodes.td:1787
314 G_MEMSET = 299, // GenericOpcodes.td:1795
315 G_BZERO = 300, // GenericOpcodes.td:1802
316 G_TRAP = 301, // GenericOpcodes.td:1812
317 G_DEBUGTRAP = 302, // GenericOpcodes.td:1819
318 G_UBSANTRAP = 303, // GenericOpcodes.td:1825
319 G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724
320 G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730
321 G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736
322 G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737
323 G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739
324 G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740
325 G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744
328 G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745
329 G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752
336 G_SBFX = 321, // GenericOpcodes.td:1837
337 G_UBFX = 322, // GenericOpcodes.td:1845
338 ASSIGN_TYPE = 323, // SPIRVInstrInfo.td:18
339 UNKNOWN_type = 324, // SPIRVInstrInfo.td:21
340 OpAccessChain = 325, // SPIRVInstrInfo.td:266
341 OpAliasDomainDeclINTEL = 326, // SPIRVInstrInfo.td:968
342 OpAliasScopeDeclINTEL = 327, // SPIRVInstrInfo.td:970
343 OpAliasScopeListDeclINTEL = 328, // SPIRVInstrInfo.td:972
344 OpAll = 329, // SPIRVInstrInfo.td:560
345 OpAny = 330, // SPIRVInstrInfo.td:558
346 OpArbitraryFloatACosALTERA = 331, // SPIRVInstrInfo.td:1059
347 OpArbitraryFloatACosPiALTERA = 332, // SPIRVInstrInfo.td:1061
348 OpArbitraryFloatASinALTERA = 333, // SPIRVInstrInfo.td:1055
349 OpArbitraryFloatASinPiALTERA = 334, // SPIRVInstrInfo.td:1057
350 OpArbitraryFloatATan2ALTERA = 335, // SPIRVInstrInfo.td:1067
351 OpArbitraryFloatATanALTERA = 336, // SPIRVInstrInfo.td:1063
352 OpArbitraryFloatATanPiALTERA = 337, // SPIRVInstrInfo.td:1065
353 OpArbitraryFloatAddALTERA = 338, // SPIRVInstrInfo.td:1044
354 OpArbitraryFloatCastALTERA = 339, // SPIRVInstrInfo.td:1075
355 OpArbitraryFloatCastFromIntALTERA = 340, // SPIRVInstrInfo.td:1077
356 OpArbitraryFloatCastToIntALTERA = 341, // SPIRVInstrInfo.td:1079
357 OpArbitraryFloatCbrtALTERA = 342, // SPIRVInstrInfo.td:993
358 OpArbitraryFloatCosALTERA = 343, // SPIRVInstrInfo.td:1029
359 OpArbitraryFloatCosPiALTERA = 344, // SPIRVInstrInfo.td:1038
360 OpArbitraryFloatDivALTERA = 345, // SPIRVInstrInfo.td:1051
361 OpArbitraryFloatEQALTERA = 346, // SPIRVInstrInfo.td:988
362 OpArbitraryFloatExp10ALTERA = 347, // SPIRVInstrInfo.td:1020
363 OpArbitraryFloatExp2ALTERA = 348, // SPIRVInstrInfo.td:1017
364 OpArbitraryFloatExpALTERA = 349, // SPIRVInstrInfo.td:1014
365 OpArbitraryFloatExpm1ALTERA = 350, // SPIRVInstrInfo.td:1023
366 OpArbitraryFloatGEALTERA = 351, // SPIRVInstrInfo.td:982
367 OpArbitraryFloatGTALTERA = 352, // SPIRVInstrInfo.td:980
368 OpArbitraryFloatHypotALTERA = 353, // SPIRVInstrInfo.td:996
369 OpArbitraryFloatLEALTERA = 354, // SPIRVInstrInfo.td:986
370 OpArbitraryFloatLTALTERA = 355, // SPIRVInstrInfo.td:984
371 OpArbitraryFloatLog10ALTERA = 356, // SPIRVInstrInfo.td:1008
372 OpArbitraryFloatLog1pALTERA = 357, // SPIRVInstrInfo.td:1011
373 OpArbitraryFloatLog2ALTERA = 358, // SPIRVInstrInfo.td:1005
374 OpArbitraryFloatLogALTERA = 359, // SPIRVInstrInfo.td:1002
375 OpArbitraryFloatMulALTERA = 360, // SPIRVInstrInfo.td:1049
376 OpArbitraryFloatPowALTERA = 361, // SPIRVInstrInfo.td:1069
377 OpArbitraryFloatPowNALTERA = 362, // SPIRVInstrInfo.td:1073
378 OpArbitraryFloatPowRALTERA = 363, // SPIRVInstrInfo.td:1071
379 OpArbitraryFloatRSqrtALTERA = 364, // SPIRVInstrInfo.td:1053
380 OpArbitraryFloatRecipALTERA = 365, // SPIRVInstrInfo.td:990
381 OpArbitraryFloatSinALTERA = 366, // SPIRVInstrInfo.td:1026
382 OpArbitraryFloatSinCosALTERA = 367, // SPIRVInstrInfo.td:1032
383 OpArbitraryFloatSinCosPiALTERA = 368, // SPIRVInstrInfo.td:1041
384 OpArbitraryFloatSinPiALTERA = 369, // SPIRVInstrInfo.td:1035
385 OpArbitraryFloatSqrtALTERA = 370, // SPIRVInstrInfo.td:999
386 OpArbitraryFloatSubALTERA = 371, // SPIRVInstrInfo.td:1047
387 OpArithmeticFenceEXT = 372, // SPIRVInstrInfo.td:956
388 OpArrayLength = 373, // SPIRVInstrInfo.td:274
389 OpAsmCallINTEL = 374, // SPIRVInstrInfo.td:922
390 OpAsmINTEL = 375, // SPIRVInstrInfo.td:919
391 OpAsmTargetINTEL = 376, // SPIRVInstrInfo.td:918
392 OpAssumeTrueKHR = 377, // SPIRVInstrInfo.td:102
393 OpAtomicAnd = 378, // SPIRVInstrInfo.td:686
394 OpAtomicCompareExchange = 379, // SPIRVInstrInfo.td:666
395 OpAtomicCompareExchangeWeak = 380, // SPIRVInstrInfo.td:670
396 OpAtomicExchange = 381, // SPIRVInstrInfo.td:663
397 OpAtomicFAddEXT = 382, // SPIRVInstrInfo.td:690
398 OpAtomicFMaxEXT = 383, // SPIRVInstrInfo.td:692
399 OpAtomicFMinEXT = 384, // SPIRVInstrInfo.td:691
400 OpAtomicFlagClear = 385, // SPIRVInstrInfo.td:695
401 OpAtomicFlagTestAndSet = 386, // SPIRVInstrInfo.td:694
402 OpAtomicIAdd = 387, // SPIRVInstrInfo.td:678
403 OpAtomicIDecrement = 388, // SPIRVInstrInfo.td:676
404 OpAtomicIIncrement = 389, // SPIRVInstrInfo.td:675
405 OpAtomicISub = 390, // SPIRVInstrInfo.td:679
406 OpAtomicLoad = 391, // SPIRVInstrInfo.td:659
407 OpAtomicOr = 392, // SPIRVInstrInfo.td:687
408 OpAtomicSMax = 393, // SPIRVInstrInfo.td:683
409 OpAtomicSMin = 394, // SPIRVInstrInfo.td:681
410 OpAtomicStore = 395, // SPIRVInstrInfo.td:661
411 OpAtomicUMax = 396, // SPIRVInstrInfo.td:684
412 OpAtomicUMin = 397, // SPIRVInstrInfo.td:682
413 OpAtomicXor = 398, // SPIRVInstrInfo.td:688
414 OpBitCount = 399, // SPIRVInstrInfo.td:554
415 OpBitFieldInsert = 400, // SPIRVInstrInfo.td:544
416 OpBitFieldSExtract = 401, // SPIRVInstrInfo.td:547
417 OpBitFieldUExtract = 402, // SPIRVInstrInfo.td:550
418 OpBitReverse = 403, // SPIRVInstrInfo.td:553
419 OpBitcast = 404, // SPIRVInstrInfo.td:438
420 OpBitwiseAndS = 405, // SPIRVInstrInfo.td:48
421 OpBitwiseAndV = 406, // SPIRVInstrInfo.td:53
422 OpBitwiseFunctionINTEL = 407, // SPIRVInstrInfo.td:976
423 OpBitwiseOrS = 408, // SPIRVInstrInfo.td:48
424 OpBitwiseOrV = 409, // SPIRVInstrInfo.td:53
425 OpBitwiseXorS = 410, // SPIRVInstrInfo.td:48
426 OpBitwiseXorV = 411, // SPIRVInstrInfo.td:53
427 OpBranch = 412, // SPIRVInstrInfo.td:634
428 OpBranchConditional = 413, // SPIRVInstrInfo.td:635
429 OpBuildNDRange = 414, // SPIRVInstrInfo.td:768
430 OpCapability = 415, // SPIRVInstrInfo.td:160
431 OpCaptureEventProfilingInfo = 416, // SPIRVInstrInfo.td:763
432 OpCommitReadPipe = 417, // SPIRVInstrInfo.td:785
433 OpCommitWritePipe = 418, // SPIRVInstrInfo.td:787
434 OpCompositeConstruct = 419, // SPIRVInstrInfo.td:459
435 OpCompositeConstructContinuedINTEL = 420, // SPIRVInstrInfo.td:461
436 OpCompositeExtract = 421, // SPIRVInstrInfo.td:463
437 OpCompositeInsert = 422, // SPIRVInstrInfo.td:465
438 OpConstantComposite = 423, // SPIRVInstrInfo.td:230
439 OpConstantCompositeContinuedINTEL = 424, // SPIRVInstrInfo.td:232
440 OpConstantF = 425, // SPIRVInstrInfo.td:218
441 OpConstantFalse = 426, // SPIRVInstrInfo.td:227
442 OpConstantFunctionPointerINTEL = 427, // SPIRVInstrInfo.td:866
443 OpConstantI = 428, // SPIRVInstrInfo.td:216
444 OpConstantNull = 429, // SPIRVInstrInfo.td:238
445 OpConstantSampler = 430, // SPIRVInstrInfo.td:235
446 OpConstantTrue = 431, // SPIRVInstrInfo.td:225
447 OpControlBarrier = 432, // SPIRVInstrInfo.td:707
448 OpControlBarrierArriveINTEL = 433, // SPIRVInstrInfo.td:716
449 OpControlBarrierWaitINTEL = 434, // SPIRVInstrInfo.td:718
450 OpConvertBF16ToFINTEL = 435, // SPIRVInstrInfo.td:446
451 OpConvertFToBF16INTEL = 436, // SPIRVInstrInfo.td:445
452 OpConvertFToS = 437, // SPIRVInstrInfo.td:418
453 OpConvertFToU = 438, // SPIRVInstrInfo.td:417
454 OpConvertHandleToImageINTEL = 439, // SPIRVInstrInfo.td:960
455 OpConvertHandleToSampledImageINTEL = 440, // SPIRVInstrInfo.td:964
456 OpConvertHandleToSamplerINTEL = 441, // SPIRVInstrInfo.td:962
457 OpConvertPtrToU = 442, // SPIRVInstrInfo.td:428
458 OpConvertSToF = 443, // SPIRVInstrInfo.td:419
459 OpConvertUToF = 444, // SPIRVInstrInfo.td:420
460 OpConvertUToPtr = 445, // SPIRVInstrInfo.td:433
461 OpCooperativeMatrixConstructCheckedINTEL = 446, // SPIRVInstrInfo.td:945
462 OpCooperativeMatrixGetElementCoordINTEL = 447, // SPIRVInstrInfo.td:948
463 OpCooperativeMatrixLengthKHR = 448, // SPIRVInstrInfo.td:935
464 OpCooperativeMatrixLoadCheckedINTEL = 449, // SPIRVInstrInfo.td:939
465 OpCooperativeMatrixLoadKHR = 450, // SPIRVInstrInfo.td:926
466 OpCooperativeMatrixMulAddKHR = 451, // SPIRVInstrInfo.td:932
467 OpCooperativeMatrixPrefetchINTEL = 452, // SPIRVInstrInfo.td:951
468 OpCooperativeMatrixStoreCheckedINTEL = 453, // SPIRVInstrInfo.td:942
469 OpCooperativeMatrixStoreKHR = 454, // SPIRVInstrInfo.td:929
470 OpCopyLogical = 455, // SPIRVInstrInfo.td:469
471 OpCopyMemory = 456, // SPIRVInstrInfo.td:262
472 OpCopyMemorySized = 457, // SPIRVInstrInfo.td:264
473 OpCopyObject = 458, // SPIRVInstrInfo.td:467
474 OpCreateUserEvent = 459, // SPIRVInstrInfo.td:757
475 OpCrossWorkgroupCastToPtrINTEL = 460, // SPIRVInstrInfo.td:442
476 OpDPdx = 461, // SPIRVInstrInfo.td:610
477 OpDPdxCoarse = 462, // SPIRVInstrInfo.td:618
478 OpDPdxFine = 463, // SPIRVInstrInfo.td:614
479 OpDPdy = 464, // SPIRVInstrInfo.td:611
480 OpDPdyCoarse = 465, // SPIRVInstrInfo.td:619
481 OpDPdyFine = 466, // SPIRVInstrInfo.td:615
482 OpDecorate = 467, // SPIRVInstrInfo.td:124
483 OpDecorateId = 468, // SPIRVInstrInfo.td:132
484 OpDecorateString = 469, // SPIRVInstrInfo.td:134
485 OpDemoteToHelperInvocation = 470, // SPIRVInstrInfo.td:647
486 OpDot = 471, // SPIRVInstrInfo.td:510
487 OpEmitStreamVertex = 472, // SPIRVInstrInfo.td:702
488 OpEmitVertex = 473, // SPIRVInstrInfo.td:700
489 OpEndPrimitive = 474, // SPIRVInstrInfo.td:701
490 OpEndStreamPrimitive = 475, // SPIRVInstrInfo.td:703
491 OpEnqueueKernel = 476, // SPIRVInstrInfo.td:752
492 OpEntryPoint = 477, // SPIRVInstrInfo.td:155
493 OpExecutionMode = 478, // SPIRVInstrInfo.td:158
494 OpExecutionModeId = 479, // SPIRVInstrInfo.td:161
495 OpExpectKHR = 480, // SPIRVInstrInfo.td:103
496 OpExtInst = 481, // SPIRVInstrInfo.td:149
497 OpExtInstImport = 482, // SPIRVInstrInfo.td:143
498 OpExtension = 483, // SPIRVInstrInfo.td:142
499 OpFAddS = 484, // SPIRVInstrInfo.td:46
500 OpFAddV = 485, // SPIRVInstrInfo.td:51
501 OpFConvert = 486, // SPIRVInstrInfo.td:424
502 OpFDivS = 487, // SPIRVInstrInfo.td:46
503 OpFDivV = 488, // SPIRVInstrInfo.td:51
504 OpFMod = 489, // SPIRVInstrInfo.td:501
505 OpFMulS = 490, // SPIRVInstrInfo.td:46
506 OpFMulV = 491, // SPIRVInstrInfo.td:51
507 OpFNegate = 492, // SPIRVInstrInfo.td:474
508 OpFNegateV = 493, // SPIRVInstrInfo.td:475
509 OpFOrdEqual = 494, // SPIRVInstrInfo.td:593
510 OpFOrdGreaterThan = 495, // SPIRVInstrInfo.td:600
511 OpFOrdGreaterThanEqual = 496, // SPIRVInstrInfo.td:605
512 OpFOrdLessThan = 497, // SPIRVInstrInfo.td:598
513 OpFOrdLessThanEqual = 498, // SPIRVInstrInfo.td:603
514 OpFOrdNotEqual = 499, // SPIRVInstrInfo.td:595
515 OpFRemS = 500, // SPIRVInstrInfo.td:46
516 OpFRemV = 501, // SPIRVInstrInfo.td:51
517 OpFSubS = 502, // SPIRVInstrInfo.td:46
518 OpFSubV = 503, // SPIRVInstrInfo.td:51
519 OpFUnordEqual = 504, // SPIRVInstrInfo.td:594
520 OpFUnordGreaterThan = 505, // SPIRVInstrInfo.td:601
521 OpFUnordGreaterThanEqual = 506, // SPIRVInstrInfo.td:606
522 OpFUnordLessThan = 507, // SPIRVInstrInfo.td:599
523 OpFUnordLessThanEqual = 508, // SPIRVInstrInfo.td:604
524 OpFUnordNotEqual = 509, // SPIRVInstrInfo.td:596
525 OpFixedCosALTERA = 510, // SPIRVInstrInfo.td:1120
526 OpFixedCosPiALTERA = 511, // SPIRVInstrInfo.td:1126
527 OpFixedExpALTERA = 512, // SPIRVInstrInfo.td:1132
528 OpFixedLogALTERA = 513, // SPIRVInstrInfo.td:1130
529 OpFixedRecipALTERA = 514, // SPIRVInstrInfo.td:1114
530 OpFixedRsqrtALTERA = 515, // SPIRVInstrInfo.td:1116
531 OpFixedSinALTERA = 516, // SPIRVInstrInfo.td:1118
532 OpFixedSinCosALTERA = 517, // SPIRVInstrInfo.td:1122
533 OpFixedSinCosPiALTERA = 518, // SPIRVInstrInfo.td:1128
534 OpFixedSinPiALTERA = 519, // SPIRVInstrInfo.td:1124
535 OpFixedSqrtALTERA = 520, // SPIRVInstrInfo.td:1112
536 OpFmaKHR = 521, // SPIRVInstrInfo.td:530
537 OpFunction = 522, // SPIRVInstrInfo.td:299
538 OpFunctionCall = 523, // SPIRVInstrInfo.td:307
539 OpFunctionEnd = 524, // SPIRVInstrInfo.td:304
540 OpFunctionParameter = 525, // SPIRVInstrInfo.td:302
541 OpFunctionPointerCallINTEL = 526, // SPIRVInstrInfo.td:871
542 OpFwidth = 527, // SPIRVInstrInfo.td:612
543 OpFwidthCoarse = 528, // SPIRVInstrInfo.td:620
544 OpFwidthFine = 529, // SPIRVInstrInfo.td:616
545 OpGenericCastToPtr = 530, // SPIRVInstrInfo.td:435
546 OpGenericCastToPtrExplicit = 531, // SPIRVInstrInfo.td:436
547 OpGenericPtrMemSemantics = 532, // SPIRVInstrInfo.td:276
548 OpGetDefaultQueue = 533, // SPIRVInstrInfo.td:766
549 OpGetMaxPipePackets = 534, // SPIRVInstrInfo.td:793
550 OpGetNumPipePackets = 535, // SPIRVInstrInfo.td:791
551 OpGroupAll = 536, // SPIRVInstrInfo.td:728
552 OpGroupAny = 537, // SPIRVInstrInfo.td:730
553 OpGroupAsyncCopy = 538, // SPIRVInstrInfo.td:723
554 OpGroupBitwiseAndKHR = 539, // SPIRVInstrInfo.td:904
555 OpGroupBitwiseOrKHR = 540, // SPIRVInstrInfo.td:906
556 OpGroupBitwiseXorKHR = 541, // SPIRVInstrInfo.td:908
557 OpGroupBroadcast = 542, // SPIRVInstrInfo.td:732
558 OpGroupCommitReadPipe = 543, // SPIRVInstrInfo.td:799
559 OpGroupCommitWritePipe = 544, // SPIRVInstrInfo.td:801
560 OpGroupFAdd = 545, // SPIRVInstrInfo.td:739
561 OpGroupFMax = 546, // SPIRVInstrInfo.td:743
562 OpGroupFMin = 547, // SPIRVInstrInfo.td:740
563 OpGroupFMulKHR = 548, // SPIRVInstrInfo.td:902
564 OpGroupIAdd = 549, // SPIRVInstrInfo.td:738
565 OpGroupIMulKHR = 550, // SPIRVInstrInfo.td:900
566 OpGroupLogicalAndKHR = 551, // SPIRVInstrInfo.td:910
567 OpGroupLogicalOrKHR = 552, // SPIRVInstrInfo.td:912
568 OpGroupLogicalXorKHR = 553, // SPIRVInstrInfo.td:914
569 OpGroupNonUniformAll = 554, // SPIRVInstrInfo.td:814
570 OpGroupNonUniformAllEqual = 555, // SPIRVInstrInfo.td:816
571 OpGroupNonUniformAny = 556, // SPIRVInstrInfo.td:815
572 OpGroupNonUniformBallot = 557, // SPIRVInstrInfo.td:819
573 OpGroupNonUniformBallotBitCount = 558, // SPIRVInstrInfo.td:822
574 OpGroupNonUniformBallotBitExtract = 559, // SPIRVInstrInfo.td:821
575 OpGroupNonUniformBallotFindLSB = 560, // SPIRVInstrInfo.td:826
576 OpGroupNonUniformBallotFindMSB = 561, // SPIRVInstrInfo.td:827
577 OpGroupNonUniformBitwiseAnd = 562, // SPIRVInstrInfo.td:846
578 OpGroupNonUniformBitwiseOr = 563, // SPIRVInstrInfo.td:847
579 OpGroupNonUniformBitwiseXor = 564, // SPIRVInstrInfo.td:848
580 OpGroupNonUniformBroadcast = 565, // SPIRVInstrInfo.td:817
581 OpGroupNonUniformBroadcastFirst = 566, // SPIRVInstrInfo.td:818
582 OpGroupNonUniformElect = 567, // SPIRVInstrInfo.td:806
583 OpGroupNonUniformFAdd = 568, // SPIRVInstrInfo.td:837
584 OpGroupNonUniformFMax = 569, // SPIRVInstrInfo.td:845
585 OpGroupNonUniformFMin = 570, // SPIRVInstrInfo.td:842
586 OpGroupNonUniformFMul = 571, // SPIRVInstrInfo.td:839
587 OpGroupNonUniformIAdd = 572, // SPIRVInstrInfo.td:836
588 OpGroupNonUniformIMul = 573, // SPIRVInstrInfo.td:838
589 OpGroupNonUniformInverseBallot = 574, // SPIRVInstrInfo.td:820
590 OpGroupNonUniformLogicalAnd = 575, // SPIRVInstrInfo.td:849
591 OpGroupNonUniformLogicalOr = 576, // SPIRVInstrInfo.td:850
592 OpGroupNonUniformLogicalXor = 577, // SPIRVInstrInfo.td:851
593 OpGroupNonUniformRotateKHR = 578, // SPIRVInstrInfo.td:854
594 OpGroupNonUniformSMax = 579, // SPIRVInstrInfo.td:843
595 OpGroupNonUniformSMin = 580, // SPIRVInstrInfo.td:840
596 OpGroupNonUniformShuffle = 581, // SPIRVInstrInfo.td:828
597 OpGroupNonUniformShuffleDown = 582, // SPIRVInstrInfo.td:831
598 OpGroupNonUniformShuffleUp = 583, // SPIRVInstrInfo.td:830
599 OpGroupNonUniformShuffleXor = 584, // SPIRVInstrInfo.td:829
600 OpGroupNonUniformUMax = 585, // SPIRVInstrInfo.td:844
601 OpGroupNonUniformUMin = 586, // SPIRVInstrInfo.td:841
602 OpGroupReserveReadPipePackets = 587, // SPIRVInstrInfo.td:795
603 OpGroupReserveWritePipePackets = 588, // SPIRVInstrInfo.td:797
604 OpGroupSMax = 589, // SPIRVInstrInfo.td:745
605 OpGroupSMin = 590, // SPIRVInstrInfo.td:742
606 OpGroupUMax = 591, // SPIRVInstrInfo.td:744
607 OpGroupUMin = 592, // SPIRVInstrInfo.td:741
608 OpGroupWaitEvents = 593, // SPIRVInstrInfo.td:726
609 OpIAddCarryS = 594, // SPIRVInstrInfo.td:48
610 OpIAddCarryV = 595, // SPIRVInstrInfo.td:53
611 OpIAddS = 596, // SPIRVInstrInfo.td:48
612 OpIAddV = 597, // SPIRVInstrInfo.td:53
613 OpIEqual = 598, // SPIRVInstrInfo.td:581
614 OpIMulS = 599, // SPIRVInstrInfo.td:48
615 OpIMulV = 600, // SPIRVInstrInfo.td:53
616 OpINotEqual = 601, // SPIRVInstrInfo.td:582
617 OpISubBorrowS = 602, // SPIRVInstrInfo.td:48
618 OpISubBorrowV = 603, // SPIRVInstrInfo.td:53
619 OpISubS = 604, // SPIRVInstrInfo.td:48
620 OpISubV = 605, // SPIRVInstrInfo.td:53
621 OpImage = 606, // SPIRVInstrInfo.td:358
622 OpImageDrefGather = 607, // SPIRVInstrInfo.td:348
623 OpImageFetch = 608, // SPIRVInstrInfo.td:342
624 OpImageGather = 609, // SPIRVInstrInfo.td:345
625 OpImageQueryFormat = 610, // SPIRVInstrInfo.td:359
626 OpImageQueryLevels = 611, // SPIRVInstrInfo.td:364
627 OpImageQueryLod = 612, // SPIRVInstrInfo.td:363
628 OpImageQueryOrder = 613, // SPIRVInstrInfo.td:360
629 OpImageQuerySamples = 614, // SPIRVInstrInfo.td:365
630 OpImageQuerySize = 615, // SPIRVInstrInfo.td:362
631 OpImageQuerySizeLod = 616, // SPIRVInstrInfo.td:361
632 OpImageRead = 617, // SPIRVInstrInfo.td:352
633 OpImageSampleDrefExplicitLod = 618, // SPIRVInstrInfo.td:324
634 OpImageSampleDrefImplicitLod = 619, // SPIRVInstrInfo.td:321
635 OpImageSampleExplicitLod = 620, // SPIRVInstrInfo.td:317
636 OpImageSampleFootprintNV = 621, // SPIRVInstrInfo.td:411
637 OpImageSampleImplicitLod = 622, // SPIRVInstrInfo.td:314
638 OpImageSampleProjDrefExplicitLod = 623, // SPIRVInstrInfo.td:338
639 OpImageSampleProjDrefImplicitLod = 624, // SPIRVInstrInfo.td:335
640 OpImageSampleProjExplicitLod = 625, // SPIRVInstrInfo.td:331
641 OpImageSampleProjImplicitLod = 626, // SPIRVInstrInfo.td:328
642 OpImageSparseDrefGather = 627, // SPIRVInstrInfo.td:401
643 OpImageSparseFetch = 628, // SPIRVInstrInfo.td:395
644 OpImageSparseGather = 629, // SPIRVInstrInfo.td:398
645 OpImageSparseRead = 630, // SPIRVInstrInfo.td:407
646 OpImageSparseSampleDrefExplicitLod = 631, // SPIRVInstrInfo.td:377
647 OpImageSparseSampleDrefImplicitLod = 632, // SPIRVInstrInfo.td:374
648 OpImageSparseSampleExplicitLod = 633, // SPIRVInstrInfo.td:370
649 OpImageSparseSampleImplicitLod = 634, // SPIRVInstrInfo.td:367
650 OpImageSparseSampleProjDrefExplicitLod = 635, // SPIRVInstrInfo.td:391
651 OpImageSparseSampleProjDrefImplicitLod = 636, // SPIRVInstrInfo.td:388
652 OpImageSparseSampleProjExplicitLod = 637, // SPIRVInstrInfo.td:384
653 OpImageSparseSampleProjImplicitLod = 638, // SPIRVInstrInfo.td:381
654 OpImageSparseTexelsResident = 639, // SPIRVInstrInfo.td:405
655 OpImageTexelPointer = 640, // SPIRVInstrInfo.td:255
656 OpImageWrite = 641, // SPIRVInstrInfo.td:355
657 OpInBoundsAccessChain = 642, // SPIRVInstrInfo.td:268
658 OpInBoundsPtrAccessChain = 643, // SPIRVInstrInfo.td:278
659 OpIsFinite = 644, // SPIRVInstrInfo.td:565
660 OpIsInf = 645, // SPIRVInstrInfo.td:564
661 OpIsNan = 646, // SPIRVInstrInfo.td:563
662 OpIsNormal = 647, // SPIRVInstrInfo.td:566
663 OpIsValidEvent = 648, // SPIRVInstrInfo.td:759
664 OpIsValidReserveId = 649, // SPIRVInstrInfo.td:789
665 OpKill = 650, // SPIRVInstrInfo.td:640
666 OpLabel = 651, // SPIRVInstrInfo.td:632
667 OpLessOrGreater = 652, // SPIRVInstrInfo.td:569
668 OpLifetimeStart = 653, // SPIRVInstrInfo.td:645
669 OpLifetimeStop = 654, // SPIRVInstrInfo.td:646
670 OpLine = 655, // SPIRVInstrInfo.td:117
671 OpLoad = 656, // SPIRVInstrInfo.td:258
672 OpLogicalAnd = 657, // SPIRVInstrInfo.td:576
673 OpLogicalEqual = 658, // SPIRVInstrInfo.td:573
674 OpLogicalNot = 659, // SPIRVInstrInfo.td:577
675 OpLogicalNotEqual = 660, // SPIRVInstrInfo.td:574
676 OpLogicalOr = 661, // SPIRVInstrInfo.td:575
677 OpLoopControlINTEL = 662, // SPIRVInstrInfo.td:628
678 OpLoopMerge = 663, // SPIRVInstrInfo.td:626
679 OpMaskedGatherINTEL = 664, // SPIRVInstrInfo.td:1136
680 OpMaskedScatterINTEL = 665, // SPIRVInstrInfo.td:1138
681 OpMatrixTimesMatrix = 666, // SPIRVInstrInfo.td:507
682 OpMatrixTimesScalar = 667, // SPIRVInstrInfo.td:504
683 OpMatrixTimesVector = 668, // SPIRVInstrInfo.td:506
684 OpMemberDecorate = 669, // SPIRVInstrInfo.td:126
685 OpMemberDecorateString = 670, // SPIRVInstrInfo.td:136
686 OpMemberName = 671, // SPIRVInstrInfo.td:114
687 OpMemoryBarrier = 672, // SPIRVInstrInfo.td:709
688 OpMemoryModel = 673, // SPIRVInstrInfo.td:153
689 OpMemoryNamedBarrier = 674, // SPIRVInstrInfo.td:712
690 OpModuleProcessed = 675, // SPIRVInstrInfo.td:119
691 OpName = 676, // SPIRVInstrInfo.td:113
692 OpNamedBarrierInitialize = 677, // SPIRVInstrInfo.td:711
693 OpNoLine = 678, // SPIRVInstrInfo.td:118
694 OpNop = 679, // SPIRVInstrInfo.td:97
695 OpNot = 680, // SPIRVInstrInfo.td:542
696 OpOrdered = 681, // SPIRVInstrInfo.td:570
697 OpOuterProduct = 682, // SPIRVInstrInfo.td:509
698 OpPhi = 683, // SPIRVInstrInfo.td:624
699 OpPredicatedLoadINTEL = 684, // SPIRVInstrInfo.td:1100
700 OpPredicatedStoreINTEL = 685, // SPIRVInstrInfo.td:1102
701 OpPtrAccessChain = 686, // SPIRVInstrInfo.td:271
702 OpPtrCastToCrossWorkgroupINTEL = 687, // SPIRVInstrInfo.td:441
703 OpPtrCastToGeneric = 688, // SPIRVInstrInfo.td:434
704 OpPtrDiff = 689, // SPIRVInstrInfo.td:285
705 OpPtrEqual = 690, // SPIRVInstrInfo.td:281
706 OpPtrNotEqual = 691, // SPIRVInstrInfo.td:283
707 OpQuantizeToF16 = 692, // SPIRVInstrInfo.td:426
708 OpReadClockKHR = 693, // SPIRVInstrInfo.td:859
709 OpReadPipe = 694, // SPIRVInstrInfo.td:773
710 OpReadPipeBlockingALTERA = 695, // SPIRVInstrInfo.td:1106
711 OpReleaseEvent = 696, // SPIRVInstrInfo.td:756
712 OpReserveReadPipePackets = 697, // SPIRVInstrInfo.td:781
713 OpReserveWritePipePackets = 698, // SPIRVInstrInfo.td:783
714 OpReservedReadPipe = 699, // SPIRVInstrInfo.td:777
715 OpReservedWritePipe = 700, // SPIRVInstrInfo.td:779
716 OpRestoreMemoryINTEL = 701, // SPIRVInstrInfo.td:294
717 OpRetainEvent = 702, // SPIRVInstrInfo.td:755
718 OpReturn = 703, // SPIRVInstrInfo.td:641
719 OpReturnValue = 704, // SPIRVInstrInfo.td:642
720 OpRoundFToTF32INTEL = 705, // SPIRVInstrInfo.td:449
721 OpSConvert = 706, // SPIRVInstrInfo.td:423
722 OpSDivS = 707, // SPIRVInstrInfo.td:48
723 OpSDivV = 708, // SPIRVInstrInfo.td:53
724 OpSDot = 709, // SPIRVInstrInfo.td:517
725 OpSDotAccSat = 710, // SPIRVInstrInfo.td:523
726 OpSGreaterThan = 711, // SPIRVInstrInfo.td:585
727 OpSGreaterThanEqual = 712, // SPIRVInstrInfo.td:587
728 OpSLessThan = 713, // SPIRVInstrInfo.td:589
729 OpSLessThanEqual = 714, // SPIRVInstrInfo.td:591
730 OpSMod = 715, // SPIRVInstrInfo.td:496
731 OpSMulExtended = 716, // SPIRVInstrInfo.td:515
732 OpSNegate = 717, // SPIRVInstrInfo.td:473
733 OpSRemS = 718, // SPIRVInstrInfo.td:48
734 OpSRemV = 719, // SPIRVInstrInfo.td:53
735 OpSUDot = 720, // SPIRVInstrInfo.td:521
736 OpSUDotAccSat = 721, // SPIRVInstrInfo.td:527
737 OpSampledImage = 722, // SPIRVInstrInfo.td:312
738 OpSatConvertSToU = 723, // SPIRVInstrInfo.td:430
739 OpSatConvertUToS = 724, // SPIRVInstrInfo.td:431
740 OpSaveMemoryINTEL = 725, // SPIRVInstrInfo.td:292
741 OpSelectSFSCond = 726, // SPIRVInstrInfo.td:67
742 OpSelectSFVCond = 727, // SPIRVInstrInfo.td:68
743 OpSelectSISCond = 728, // SPIRVInstrInfo.td:63
744 OpSelectSIVCond = 729, // SPIRVInstrInfo.td:64
745 OpSelectSPSCond = 730, // SPIRVInstrInfo.td:59
746 OpSelectSPVCond = 731, // SPIRVInstrInfo.td:60
747 OpSelectVFSCond = 732, // SPIRVInstrInfo.td:80
748 OpSelectVFVCond = 733, // SPIRVInstrInfo.td:81
749 OpSelectVISCond = 734, // SPIRVInstrInfo.td:76
750 OpSelectVIVCond = 735, // SPIRVInstrInfo.td:77
751 OpSelectVPSCond = 736, // SPIRVInstrInfo.td:72
752 OpSelectVPVCond = 737, // SPIRVInstrInfo.td:73
753 OpSelectionMerge = 738, // SPIRVInstrInfo.td:630
754 OpSetUserEventStatus = 739, // SPIRVInstrInfo.td:761
755 OpShiftLeftLogicalS = 740, // SPIRVInstrInfo.td:48
756 OpShiftLeftLogicalV = 741, // SPIRVInstrInfo.td:53
757 OpShiftRightArithmeticS = 742, // SPIRVInstrInfo.td:48
758 OpShiftRightArithmeticV = 743, // SPIRVInstrInfo.td:53
759 OpShiftRightLogicalS = 744, // SPIRVInstrInfo.td:48
760 OpShiftRightLogicalV = 745, // SPIRVInstrInfo.td:53
761 OpSignBitSet = 746, // SPIRVInstrInfo.td:567
762 OpSizeOf = 747, // SPIRVInstrInfo.td:99
763 OpSource = 748, // SPIRVInstrInfo.td:109
764 OpSourceContinued = 749, // SPIRVInstrInfo.td:107
765 OpSourceExtension = 750, // SPIRVInstrInfo.td:111
766 OpSpecConstant = 751, // SPIRVInstrInfo.td:242
767 OpSpecConstantComposite = 752, // SPIRVInstrInfo.td:244
768 OpSpecConstantCompositeContinuedINTEL = 753, // SPIRVInstrInfo.td:246
769 OpSpecConstantFalse = 754, // SPIRVInstrInfo.td:241
770 OpSpecConstantOp = 755, // SPIRVInstrInfo.td:248
771 OpSpecConstantTrue = 756, // SPIRVInstrInfo.td:240
772 OpStore = 757, // SPIRVInstrInfo.td:260
773 OpStrictFAddS = 758, // SPIRVInstrInfo.td:46
774 OpStrictFAddV = 759, // SPIRVInstrInfo.td:51
775 OpStrictFDivS = 760, // SPIRVInstrInfo.td:46
776 OpStrictFDivV = 761, // SPIRVInstrInfo.td:51
777 OpStrictFMulS = 762, // SPIRVInstrInfo.td:46
778 OpStrictFMulV = 763, // SPIRVInstrInfo.td:51
779 OpStrictFRemS = 764, // SPIRVInstrInfo.td:46
780 OpStrictFRemV = 765, // SPIRVInstrInfo.td:51
781 OpStrictFSubS = 766, // SPIRVInstrInfo.td:46
782 OpStrictFSubV = 767, // SPIRVInstrInfo.td:51
783 OpString = 768, // SPIRVInstrInfo.td:116
784 OpSubgroup2DBlockLoadINTEL = 769, // SPIRVInstrInfo.td:1083
785 OpSubgroup2DBlockLoadTransformINTEL = 770, // SPIRVInstrInfo.td:1089
786 OpSubgroup2DBlockLoadTransposeINTEL = 771, // SPIRVInstrInfo.td:1086
787 OpSubgroup2DBlockPrefetchINTEL = 772, // SPIRVInstrInfo.td:1092
788 OpSubgroup2DBlockStoreINTEL = 773, // SPIRVInstrInfo.td:1095
789 OpSubgroupBlockReadINTEL = 774, // SPIRVInstrInfo.td:884
790 OpSubgroupBlockWriteINTEL = 775, // SPIRVInstrInfo.td:886
791 OpSubgroupImageBlockReadINTEL = 776, // SPIRVInstrInfo.td:888
792 OpSubgroupImageBlockWriteINTEL = 777, // SPIRVInstrInfo.td:890
793 OpSubgroupImageMediaBlockReadINTEL = 778, // SPIRVInstrInfo.td:894
794 OpSubgroupImageMediaBlockWriteINTEL = 779, // SPIRVInstrInfo.td:896
795 OpSubgroupMatrixMultiplyAccumulateINTEL = 780, // SPIRVInstrInfo.td:747
796 OpSubgroupShuffleDownINTEL = 781, // SPIRVInstrInfo.td:878
797 OpSubgroupShuffleINTEL = 782, // SPIRVInstrInfo.td:876
798 OpSubgroupShuffleUpINTEL = 783, // SPIRVInstrInfo.td:880
799 OpSubgroupShuffleXorINTEL = 784, // SPIRVInstrInfo.td:882
800 OpSwitch = 785, // SPIRVInstrInfo.td:637
801 OpTranspose = 786, // SPIRVInstrInfo.td:468
802 OpTypeAccelerationStructureNV = 787, // SPIRVInstrInfo.td:204
803 OpTypeArray = 788, // SPIRVInstrInfo.td:182
804 OpTypeBool = 789, // SPIRVInstrInfo.td:167
805 OpTypeCooperativeMatrixKHR = 790, // SPIRVInstrInfo.td:209
806 OpTypeCooperativeMatrixNV = 791, // SPIRVInstrInfo.td:206
807 OpTypeDeviceEvent = 792, // SPIRVInstrInfo.td:196
808 OpTypeEvent = 793, // SPIRVInstrInfo.td:195
809 OpTypeFloat = 794, // SPIRVInstrInfo.td:170
810 OpTypeForwardPointer = 795, // SPIRVInstrInfo.td:200
811 OpTypeFunction = 796, // SPIRVInstrInfo.td:193
812 OpTypeImage = 797, // SPIRVInstrInfo.td:176
813 OpTypeInt = 798, // SPIRVInstrInfo.td:168
814 OpTypeMatrix = 799, // SPIRVInstrInfo.td:174
815 OpTypeNamedBarrier = 800, // SPIRVInstrInfo.td:203
816 OpTypeOpaque = 801, // SPIRVInstrInfo.td:189
817 OpTypePipe = 802, // SPIRVInstrInfo.td:199
818 OpTypePipeStorage = 803, // SPIRVInstrInfo.td:202
819 OpTypePointer = 804, // SPIRVInstrInfo.td:191
820 OpTypeQueue = 805, // SPIRVInstrInfo.td:198
821 OpTypeReserveId = 806, // SPIRVInstrInfo.td:197
822 OpTypeRuntimeArray = 807, // SPIRVInstrInfo.td:184
823 OpTypeSampledImage = 808, // SPIRVInstrInfo.td:180
824 OpTypeSampler = 809, // SPIRVInstrInfo.td:179
825 OpTypeStruct = 810, // SPIRVInstrInfo.td:186
826 OpTypeStructContinuedINTEL = 811, // SPIRVInstrInfo.td:187
827 OpTypeVector = 812, // SPIRVInstrInfo.td:172
828 OpTypeVoid = 813, // SPIRVInstrInfo.td:166
829 OpUConvert = 814, // SPIRVInstrInfo.td:422
830 OpUDivS = 815, // SPIRVInstrInfo.td:48
831 OpUDivV = 816, // SPIRVInstrInfo.td:53
832 OpUDot = 817, // SPIRVInstrInfo.td:519
833 OpUDotAccSat = 818, // SPIRVInstrInfo.td:525
834 OpUGreaterThan = 819, // SPIRVInstrInfo.td:584
835 OpUGreaterThanEqual = 820, // SPIRVInstrInfo.td:586
836 OpULessThan = 821, // SPIRVInstrInfo.td:588
837 OpULessThanEqual = 822, // SPIRVInstrInfo.td:590
838 OpUModS = 823, // SPIRVInstrInfo.td:48
839 OpUModV = 824, // SPIRVInstrInfo.td:53
840 OpUMulExtended = 825, // SPIRVInstrInfo.td:514
841 OpUndef = 826, // SPIRVInstrInfo.td:98
842 OpUnordered = 827, // SPIRVInstrInfo.td:571
843 OpUnreachable = 828, // SPIRVInstrInfo.td:643
844 OpVariable = 829, // SPIRVInstrInfo.td:253
845 OpVariableLengthArrayINTEL = 830, // SPIRVInstrInfo.td:290
846 OpVectorExtractDynamic = 831, // SPIRVInstrInfo.td:453
847 OpVectorInsertDynamic = 832, // SPIRVInstrInfo.td:455
848 OpVectorShuffle = 833, // SPIRVInstrInfo.td:457
849 OpVectorTimesMatrix = 834, // SPIRVInstrInfo.td:505
850 OpVectorTimesScalar = 835, // SPIRVInstrInfo.td:503
851 OpWritePipe = 836, // SPIRVInstrInfo.td:775
852 OpWritePipeBlockingALTERA = 837, // SPIRVInstrInfo.td:1108
853 INSTRUCTION_LIST_END = 838
854 };
855
856} // namespace llvm::SPIRV
857
858#endif // GET_INSTRINFO_ENUM
859
860#ifdef GET_INSTRINFO_SCHED_ENUM
861#undef GET_INSTRINFO_SCHED_ENUM
862
863namespace llvm::SPIRV::Sched {
864
865 enum {
866 NoInstrModel = 0,
867 SCHED_LIST_END = 1
868 };
869
870} // namespace llvm::SPIRV::Sched
871
872#endif // GET_INSTRINFO_SCHED_ENUM
873
874#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
875
876namespace llvm {
877
878struct SPIRVInstrTable {
879 MCInstrDesc Insts[838];
880 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
881 MCPhysReg ImplicitOps[1];
882 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
883 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
884 MCOperandInfo OperandInfo[485];
885};
886} // namespace llvm
887
888#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
889
890#ifdef GET_INSTRINFO_MC_DESC
891#undef GET_INSTRINFO_MC_DESC
892
893namespace llvm {
894
895static_assert((sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
896static constexpr unsigned SPIRVOpInfoBase = (sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) / sizeof(MCOperandInfo);
897
898extern const SPIRVInstrTable SPIRVDescs = {
899 {
900 { 837, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipeBlockingALTERA
901 { 836, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipe
902 { 835, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesScalar
903 { 834, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesMatrix
904 { 833, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorShuffle
905 { 832, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorInsertDynamic
906 { 831, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 481, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorExtractDynamic
907 { 830, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariableLengthArrayINTEL
908 { 829, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariable
909 { 828, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnreachable
910 { 827, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnordered
911 { 826, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUndef
912 { 825, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUMulExtended
913 { 824, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModV
914 { 823, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModS
915 { 822, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThanEqual
916 { 821, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThan
917 { 820, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThanEqual
918 { 819, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThan
919 { 818, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDotAccSat
920 { 817, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDot
921 { 816, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivV
922 { 815, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivS
923 { 814, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUConvert
924 { 813, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVoid
925 { 812, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 472, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVector
926 { 811, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStructContinuedINTEL
927 { 810, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStruct
928 { 809, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampler
929 { 808, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampledImage
930 { 807, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeRuntimeArray
931 { 806, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeReserveId
932 { 805, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeQueue
933 { 804, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 475, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePointer
934 { 803, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipeStorage
935 { 802, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipe
936 { 801, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeOpaque
937 { 800, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeNamedBarrier
938 { 799, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 472, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeMatrix
939 { 798, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 469, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeInt
940 { 797, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 461, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeImage
941 { 796, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFunction
942 { 795, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeForwardPointer
943 { 794, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFloat
944 { 793, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeEvent
945 { 792, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeDeviceEvent
946 { 791, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 452, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixNV
947 { 790, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixKHR
948 { 789, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeBool
949 { 788, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 443, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeArray
950 { 787, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeAccelerationStructureNV
951 { 786, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTranspose
952 { 785, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSwitch
953 { 784, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleXorINTEL
954 { 783, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleUpINTEL
955 { 782, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleINTEL
956 { 781, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleDownINTEL
957 { 780, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupMatrixMultiplyAccumulateINTEL
958 { 779, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockWriteINTEL
959 { 778, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockReadINTEL
960 { 777, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockWriteINTEL
961 { 776, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockReadINTEL
962 { 775, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockWriteINTEL
963 { 774, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockReadINTEL
964 { 773, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockStoreINTEL
965 { 772, 9, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 433, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockPrefetchINTEL
966 { 771, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransposeINTEL
967 { 770, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransformINTEL
968 { 769, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadINTEL
969 { 768, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpString
970 { 767, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubV
971 { 766, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubS
972 { 765, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemV
973 { 764, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemS
974 { 763, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulV
975 { 762, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulS
976 { 761, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivV
977 { 760, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivS
978 { 759, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddV
979 { 758, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddS
980 { 757, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStore
981 { 756, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantTrue
982 { 755, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 419, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantOp
983 { 754, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantFalse
984 { 753, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantCompositeContinuedINTEL
985 { 752, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantComposite
986 { 751, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 416, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstant
987 { 750, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceExtension
988 { 749, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceContinued
989 { 748, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSource
990 { 747, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSizeOf
991 { 746, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSignBitSet
992 { 745, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalV
993 { 744, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalS
994 { 743, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticV
995 { 742, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticS
996 { 741, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalV
997 { 740, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalS
998 { 739, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSetUserEventStatus
999 { 738, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectionMerge
1000 { 737, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 411, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPVCond
1001 { 736, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 406, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPSCond
1002 { 735, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 401, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVIVCond
1003 { 734, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 396, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVISCond
1004 { 733, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 391, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFVCond
1005 { 732, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 386, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFSCond
1006 { 731, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 381, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPVCond
1007 { 730, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 376, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPSCond
1008 { 729, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 371, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSIVCond
1009 { 728, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 366, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSISCond
1010 { 727, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 361, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFVCond
1011 { 726, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 356, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFSCond
1012 { 725, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSaveMemoryINTEL
1013 { 724, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertUToS
1014 { 723, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertSToU
1015 { 722, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSampledImage
1016 { 721, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDotAccSat
1017 { 720, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDot
1018 { 719, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemV
1019 { 718, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemS
1020 { 717, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSNegate
1021 { 716, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMulExtended
1022 { 715, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMod
1023 { 714, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThanEqual
1024 { 713, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThan
1025 { 712, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThanEqual
1026 { 711, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThan
1027 { 710, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDotAccSat
1028 { 709, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDot
1029 { 708, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivV
1030 { 707, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivS
1031 { 706, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSConvert
1032 { 705, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRoundFToTF32INTEL
1033 { 704, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturnValue
1034 { 703, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturn
1035 { 702, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRetainEvent
1036 { 701, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRestoreMemoryINTEL
1037 { 700, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedWritePipe
1038 { 699, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedReadPipe
1039 { 698, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveWritePipePackets
1040 { 697, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveReadPipePackets
1041 { 696, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReleaseEvent
1042 { 695, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipeBlockingALTERA
1043 { 694, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipe
1044 { 693, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadClockKHR
1045 { 692, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpQuantizeToF16
1046 { 691, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrNotEqual
1047 { 690, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrEqual
1048 { 689, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrDiff
1049 { 688, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToGeneric
1050 { 687, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToCrossWorkgroupINTEL
1051 { 686, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrAccessChain
1052 { 685, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedStoreINTEL
1053 { 684, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedLoadINTEL
1054 { 683, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPhi
1055 { 682, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOuterProduct
1056 { 681, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOrdered
1057 { 680, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNot
1058 { 679, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNop
1059 { 678, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNoLine
1060 { 677, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNamedBarrierInitialize
1061 { 676, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 273, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpName
1062 { 675, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpModuleProcessed
1063 { 674, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryNamedBarrier
1064 { 673, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryModel
1065 { 672, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryBarrier
1066 { 671, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberName
1067 { 670, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 352, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorateString
1068 { 669, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorate
1069 { 668, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesVector
1070 { 667, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesScalar
1071 { 666, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesMatrix
1072 { 665, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedScatterINTEL
1073 { 664, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedGatherINTEL
1074 { 663, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopMerge
1075 { 662, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopControlINTEL
1076 { 661, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalOr
1077 { 660, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNotEqual
1078 { 659, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNot
1079 { 658, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalEqual
1080 { 657, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalAnd
1081 { 656, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoad
1082 { 655, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 346, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLine
1083 { 654, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 344, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStop
1084 { 653, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 344, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStart
1085 { 652, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLessOrGreater
1086 { 651, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLabel
1087 { 650, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpKill
1088 { 649, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidReserveId
1089 { 648, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidEvent
1090 { 647, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNormal
1091 { 646, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNan
1092 { 645, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsInf
1093 { 644, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsFinite
1094 { 643, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsPtrAccessChain
1095 { 642, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsAccessChain
1096 { 641, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageWrite
1097 { 640, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageTexelPointer
1098 { 639, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseTexelsResident
1099 { 638, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjImplicitLod
1100 { 637, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjExplicitLod
1101 { 636, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefImplicitLod
1102 { 635, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefExplicitLod
1103 { 634, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleImplicitLod
1104 { 633, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 338, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleExplicitLod
1105 { 632, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefImplicitLod
1106 { 631, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefExplicitLod
1107 { 630, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseRead
1108 { 629, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseGather
1109 { 628, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseFetch
1110 { 627, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseDrefGather
1111 { 626, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjImplicitLod
1112 { 625, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjExplicitLod
1113 { 624, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefImplicitLod
1114 { 623, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefExplicitLod
1115 { 622, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleImplicitLod
1116 { 621, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleFootprintNV
1117 { 620, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 338, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleExplicitLod
1118 { 619, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefImplicitLod
1119 { 618, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefExplicitLod
1120 { 617, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageRead
1121 { 616, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySizeLod
1122 { 615, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySize
1123 { 614, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySamples
1124 { 613, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryOrder
1125 { 612, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLod
1126 { 611, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLevels
1127 { 610, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryFormat
1128 { 609, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageGather
1129 { 608, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageFetch
1130 { 607, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageDrefGather
1131 { 606, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImage
1132 { 605, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubV
1133 { 604, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubS
1134 { 603, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowV
1135 { 602, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowS
1136 { 601, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpINotEqual
1137 { 600, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulV
1138 { 599, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulS
1139 { 598, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIEqual
1140 { 597, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddV
1141 { 596, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddS
1142 { 595, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryV
1143 { 594, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryS
1144 { 593, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupWaitEvents
1145 { 592, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMin
1146 { 591, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMax
1147 { 590, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMin
1148 { 589, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMax
1149 { 588, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 254, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveWritePipePackets
1150 { 587, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 254, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveReadPipePackets
1151 { 586, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMin
1152 { 585, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMax
1153 { 584, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleXor
1154 { 583, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleUp
1155 { 582, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleDown
1156 { 581, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffle
1157 { 580, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMin
1158 { 579, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMax
1159 { 578, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformRotateKHR
1160 { 577, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalXor
1161 { 576, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalOr
1162 { 575, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalAnd
1163 { 574, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformInverseBallot
1164 { 573, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIMul
1165 { 572, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIAdd
1166 { 571, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMul
1167 { 570, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMin
1168 { 569, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMax
1169 { 568, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFAdd
1170 { 567, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformElect
1171 { 566, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcastFirst
1172 { 565, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcast
1173 { 564, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseXor
1174 { 563, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseOr
1175 { 562, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseAnd
1176 { 561, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindMSB
1177 { 560, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindLSB
1178 { 559, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitExtract
1179 { 558, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitCount
1180 { 557, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallot
1181 { 556, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAny
1182 { 555, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAllEqual
1183 { 554, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAll
1184 { 553, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalXorKHR
1185 { 552, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalOrKHR
1186 { 551, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalAndKHR
1187 { 550, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIMulKHR
1188 { 549, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIAdd
1189 { 548, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMulKHR
1190 { 547, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMin
1191 { 546, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMax
1192 { 545, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFAdd
1193 { 544, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitWritePipe
1194 { 543, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitReadPipe
1195 { 542, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBroadcast
1196 { 541, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseXorKHR
1197 { 540, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseOrKHR
1198 { 539, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseAndKHR
1199 { 538, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAsyncCopy
1200 { 537, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAny
1201 { 536, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAll
1202 { 535, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetNumPipePackets
1203 { 534, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetMaxPipePackets
1204 { 533, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetDefaultQueue
1205 { 532, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericPtrMemSemantics
1206 { 531, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 312, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtrExplicit
1207 { 530, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtr
1208 { 529, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthFine
1209 { 528, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthCoarse
1210 { 527, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidth
1211 { 526, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionPointerCallINTEL
1212 { 525, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionParameter
1213 { 524, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionEnd
1214 { 523, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionCall
1215 { 522, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 308, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunction
1216 { 521, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFmaKHR
1217 { 520, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSqrtALTERA
1218 { 519, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinPiALTERA
1219 { 518, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosPiALTERA
1220 { 517, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosALTERA
1221 { 516, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinALTERA
1222 { 515, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRsqrtALTERA
1223 { 514, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRecipALTERA
1224 { 513, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedLogALTERA
1225 { 512, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedExpALTERA
1226 { 511, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosPiALTERA
1227 { 510, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosALTERA
1228 { 509, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordNotEqual
1229 { 508, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThanEqual
1230 { 507, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThan
1231 { 506, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThanEqual
1232 { 505, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThan
1233 { 504, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordEqual
1234 { 503, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubV
1235 { 502, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubS
1236 { 501, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemV
1237 { 500, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemS
1238 { 499, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdNotEqual
1239 { 498, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThanEqual
1240 { 497, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThan
1241 { 496, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThanEqual
1242 { 495, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThan
1243 { 494, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdEqual
1244 { 493, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 305, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegateV
1245 { 492, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegate
1246 { 491, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulV
1247 { 490, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulS
1248 { 489, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMod
1249 { 488, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivV
1250 { 487, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivS
1251 { 486, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFConvert
1252 { 485, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 301, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddV
1253 { 484, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 297, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddS
1254 { 483, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtension
1255 { 482, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInstImport
1256 { 481, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 293, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInst
1257 { 480, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExpectKHR
1258 { 479, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionModeId
1259 { 478, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionMode
1260 { 477, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 290, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEntryPoint
1261 { 476, 12, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEnqueueKernel
1262 { 475, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndStreamPrimitive
1263 { 474, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndPrimitive
1264 { 473, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitVertex
1265 { 472, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitStreamVertex
1266 { 471, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDot
1267 { 470, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDemoteToHelperInvocation
1268 { 469, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 275, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateString
1269 { 468, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 273, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateId
1270 { 467, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 273, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorate
1271 { 466, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyFine
1272 { 465, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyCoarse
1273 { 464, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdy
1274 { 463, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxFine
1275 { 462, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxCoarse
1276 { 461, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdx
1277 { 460, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCrossWorkgroupCastToPtrINTEL
1278 { 459, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCreateUserEvent
1279 { 458, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyObject
1280 { 457, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemorySized
1281 { 456, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemory
1282 { 455, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyLogical
1283 { 454, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreKHR
1284 { 453, 7, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 266, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreCheckedINTEL
1285 { 452, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 261, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixPrefetchINTEL
1286 { 451, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixMulAddKHR
1287 { 450, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadKHR
1288 { 449, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadCheckedINTEL
1289 { 448, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLengthKHR
1290 { 447, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixGetElementCoordINTEL
1291 { 446, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 254, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixConstructCheckedINTEL
1292 { 445, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToPtr
1293 { 444, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToF
1294 { 443, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertSToF
1295 { 442, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertPtrToU
1296 { 441, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSamplerINTEL
1297 { 440, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSampledImageINTEL
1298 { 439, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToImageINTEL
1299 { 438, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToU
1300 { 437, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToS
1301 { 436, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToBF16INTEL
1302 { 435, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertBF16ToFINTEL
1303 { 434, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierWaitINTEL
1304 { 433, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierArriveINTEL
1305 { 432, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrier
1306 { 431, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 244, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantTrue
1307 { 430, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 249, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantSampler
1308 { 429, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantNull
1309 { 428, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantI
1310 { 427, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFunctionPointerINTEL
1311 { 426, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 244, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFalse
1312 { 425, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 241, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantF
1313 { 424, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantCompositeContinuedINTEL
1314 { 423, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantComposite
1315 { 422, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeInsert
1316 { 421, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeExtract
1317 { 420, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstructContinuedINTEL
1318 { 419, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 235, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstruct
1319 { 418, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitWritePipe
1320 { 417, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitReadPipe
1321 { 416, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCaptureEventProfilingInfo
1322 { 415, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCapability
1323 { 414, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBuildNDRange
1324 { 413, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 232, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranchConditional
1325 { 412, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranch
1326 { 411, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorV
1327 { 410, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorS
1328 { 409, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrV
1329 { 408, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrS
1330 { 407, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseFunctionINTEL
1331 { 406, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndV
1332 { 405, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndS
1333 { 404, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitcast
1334 { 403, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitReverse
1335 { 402, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldUExtract
1336 { 401, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldSExtract
1337 { 400, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldInsert
1338 { 399, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitCount
1339 { 398, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicXor
1340 { 397, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMin
1341 { 396, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMax
1342 { 395, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 220, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicStore
1343 { 394, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMin
1344 { 393, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMax
1345 { 392, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicOr
1346 { 391, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicLoad
1347 { 390, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicISub
1348 { 389, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIIncrement
1349 { 388, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIDecrement
1350 { 387, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIAdd
1351 { 386, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagTestAndSet
1352 { 385, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 212, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagClear
1353 { 384, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMinEXT
1354 { 383, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMaxEXT
1355 { 382, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFAddEXT
1356 { 381, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicExchange
1357 { 380, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchangeWeak
1358 { 379, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchange
1359 { 378, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicAnd
1360 { 377, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAssumeTrueKHR
1361 { 376, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 196, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmTargetINTEL
1362 { 375, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 190, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmINTEL
1363 { 374, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmCallINTEL
1364 { 373, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 186, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArrayLength
1365 { 372, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArithmeticFenceEXT
1366 { 371, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSubALTERA
1367 { 370, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSqrtALTERA
1368 { 369, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinPiALTERA
1369 { 368, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosPiALTERA
1370 { 367, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosALTERA
1371 { 366, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinALTERA
1372 { 365, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRecipALTERA
1373 { 364, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRSqrtALTERA
1374 { 363, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowRALTERA
1375 { 362, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowNALTERA
1376 { 361, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowALTERA
1377 { 360, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatMulALTERA
1378 { 359, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLogALTERA
1379 { 358, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog2ALTERA
1380 { 357, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog1pALTERA
1381 { 356, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog10ALTERA
1382 { 355, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLTALTERA
1383 { 354, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLEALTERA
1384 { 353, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatHypotALTERA
1385 { 352, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGTALTERA
1386 { 351, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGEALTERA
1387 { 350, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpm1ALTERA
1388 { 349, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpALTERA
1389 { 348, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp2ALTERA
1390 { 347, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp10ALTERA
1391 { 346, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 180, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatEQALTERA
1392 { 345, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatDivALTERA
1393 { 344, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosPiALTERA
1394 { 343, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosALTERA
1395 { 342, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCbrtALTERA
1396 { 341, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastToIntALTERA
1397 { 340, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastFromIntALTERA
1398 { 339, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastALTERA
1399 { 338, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatAddALTERA
1400 { 337, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanPiALTERA
1401 { 336, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanALTERA
1402 { 335, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 170, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATan2ALTERA
1403 { 334, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinPiALTERA
1404 { 333, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinALTERA
1405 { 332, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosPiALTERA
1406 { 331, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosALTERA
1407 { 330, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAny
1408 { 329, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAll
1409 { 328, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeListDeclINTEL
1410 { 327, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 160, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeDeclINTEL
1411 { 326, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 159, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasDomainDeclINTEL
1412 { 325, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAccessChain
1413 { 324, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNKNOWN_type
1414 { 323, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASSIGN_TYPE
1415 { 322, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1416 { 321, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1417 { 320, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1418 { 319, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1419 { 318, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1420 { 317, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1421 { 316, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1422 { 315, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1423 { 314, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1424 { 313, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1425 { 312, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1426 { 311, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1427 { 310, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1428 { 309, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1429 { 308, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1430 { 307, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1431 { 306, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1432 { 305, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1433 { 304, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1434 { 303, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1435 { 302, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1436 { 301, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1437 { 300, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1438 { 299, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1439 { 298, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1440 { 297, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1441 { 296, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1442 { 295, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1443 { 294, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1444 { 293, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1445 { 292, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1446 { 291, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1447 { 290, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1448 { 289, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1449 { 288, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1450 { 287, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1451 { 286, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1452 { 285, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1453 { 284, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1454 { 283, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1455 { 282, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1456 { 281, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1457 { 280, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1458 { 279, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1459 { 278, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1460 { 277, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1461 { 276, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1462 { 275, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1463 { 274, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1464 { 273, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1465 { 272, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1466 { 271, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1467 { 270, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1468 { 269, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1469 { 268, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1470 { 267, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1471 { 266, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1472 { 265, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1473 { 264, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1474 { 263, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1475 { 262, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1476 { 261, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1477 { 260, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1478 { 259, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
1479 { 258, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1480 { 257, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
1481 { 256, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1482 { 255, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1483 { 254, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1484 { 253, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1485 { 252, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1486 { 251, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1487 { 250, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1488 { 249, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1489 { 248, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1490 { 247, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1491 { 246, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1492 { 245, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1493 { 244, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1494 { 243, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1495 { 242, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1496 { 241, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1497 { 240, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1498 { 239, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1499 { 238, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1500 { 237, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1501 { 236, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1502 { 235, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1503 { 234, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1504 { 233, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1505 { 232, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1506 { 231, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1507 { 230, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1508 { 229, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1509 { 228, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1510 { 227, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1511 { 226, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1512 { 225, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1513 { 224, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1514 { 223, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1515 { 222, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1516 { 221, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1517 { 220, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1518 { 219, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1519 { 218, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1520 { 217, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1521 { 216, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1522 { 215, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1523 { 214, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1524 { 213, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1525 { 212, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1526 { 211, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1527 { 210, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1528 { 209, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1529 { 208, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1530 { 207, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1531 { 206, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1532 { 205, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1533 { 204, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1534 { 203, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1535 { 202, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1536 { 201, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1537 { 200, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1538 { 199, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1539 { 198, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1540 { 197, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1541 { 196, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1542 { 195, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1543 { 194, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1544 { 193, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1545 { 192, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1546 { 191, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1547 { 190, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1548 { 189, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1549 { 188, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1550 { 187, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1551 { 186, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1552 { 185, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1553 { 184, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1554 { 183, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1555 { 182, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1556 { 181, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1557 { 180, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1558 { 179, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1559 { 178, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1560 { 177, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1561 { 176, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1562 { 175, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1563 { 174, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1564 { 173, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1565 { 172, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1566 { 171, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1567 { 170, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1568 { 169, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1569 { 168, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1570 { 167, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1571 { 166, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1572 { 165, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1573 { 164, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1574 { 163, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1575 { 162, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1576 { 161, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1577 { 160, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1578 { 159, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1579 { 158, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1580 { 157, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1581 { 156, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1582 { 155, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1583 { 154, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1584 { 153, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1585 { 152, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1586 { 151, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1587 { 150, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1588 { 149, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1589 { 148, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1590 { 147, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1591 { 146, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1592 { 145, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1593 { 144, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1594 { 143, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1595 { 142, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1596 { 141, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1597 { 140, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1598 { 139, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1599 { 138, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1600 { 137, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1601 { 136, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1602 { 135, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1603 { 134, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1604 { 133, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1605 { 132, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1606 { 131, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1607 { 130, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1608 { 129, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1609 { 128, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1610 { 127, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1611 { 126, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1612 { 125, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1613 { 124, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1614 { 123, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1615 { 122, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1616 { 121, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1617 { 120, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1618 { 119, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1619 { 118, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1620 { 117, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1621 { 116, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1622 { 115, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1623 { 114, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1624 { 113, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1625 { 112, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1626 { 111, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1627 { 110, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1628 { 109, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1629 { 108, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1630 { 107, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1631 { 106, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1632 { 105, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1633 { 104, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1634 { 103, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1635 { 102, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1636 { 101, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1637 { 100, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1638 { 99, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1639 { 98, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1640 { 97, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1641 { 96, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1642 { 95, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1643 { 94, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1644 { 93, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1645 { 92, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1646 { 91, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1647 { 90, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1648 { 89, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1649 { 88, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1650 { 87, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1651 { 86, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1652 { 85, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1653 { 84, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1654 { 83, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1655 { 82, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1656 { 81, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1657 { 80, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1658 { 79, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1659 { 78, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1660 { 77, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1661 { 76, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1662 { 75, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1663 { 74, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1664 { 73, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1665 { 72, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1666 { 71, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1667 { 70, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1668 { 69, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1669 { 68, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1670 { 67, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1671 { 66, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1672 { 65, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1673 { 64, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1674 { 63, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1675 { 62, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1676 { 61, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1677 { 60, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1678 { 59, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1679 { 58, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1680 { 57, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1681 { 56, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1682 { 55, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1683 { 54, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1684 { 53, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1685 { 52, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1686 { 51, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1687 { 50, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1688 { 49, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1689 { 48, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1690 { 47, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1691 { 46, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1692 { 45, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1693 { 44, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1694 { 43, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1695 { 42, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21705
1696 { 41, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21704
1697 { 40, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1698 { 39, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1699 { 38, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1700 { 37, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1701 { 36, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1702 { 35, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1703 { 34, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1704 { 33, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1705 { 32, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21703
1706 { 31, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1707 { 30, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14343
1708 { 29, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1709 { 28, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1710 { 27, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1711 { 26, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1712 { 25, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1713 { 24, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1714 { 23, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1715 { 22, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1716 { 21, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1717 { 20, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1718 { 19, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1719 { 18, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1720 { 17, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1721 { 16, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1722 { 15, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1723 { 14, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1724 { 13, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1725 { 12, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1726 { 11, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1727 { 10, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1728 { 9, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1729 { 8, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1730 { 7, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1731 { 6, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1732 { 5, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1733 { 4, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1734 { 3, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1735 { 2, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1736 { 1, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1737 { 0, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1738 }, {
1739 /* 0 */
1740 }, {
1741 0
1742 }, {
1743 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1744 /* 1 */
1745 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1746 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1747 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1748 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1749 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1750 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1751 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1752 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1753 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1754 /* 28 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1755 /* 29 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1756 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1757 /* 34 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1758 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1759 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1760 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1761 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1762 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1763 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1764 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1765 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1766 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1767 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1768 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1769 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1770 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1771 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1772 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1773 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1774 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1775 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1776 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1777 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1778 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1779 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1780 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1781 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1782 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1783 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1784 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1785 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1786 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1787 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1788 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1789 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1790 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1791 /* 151 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1792 /* 154 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1793 /* 156 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1794 /* 159 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1795 /* 160 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1796 /* 162 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1797 /* 170 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1798 /* 180 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1799 /* 186 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1800 /* 190 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1801 /* 196 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1802 /* 198 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1803 /* 204 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1804 /* 212 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1805 /* 215 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1806 /* 220 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1807 /* 224 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1808 /* 228 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1809 /* 232 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1810 /* 235 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1811 /* 237 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1812 /* 241 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1813 /* 244 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1814 /* 246 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1815 /* 249 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1816 /* 254 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1817 /* 261 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1818 /* 266 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1819 /* 273 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1820 /* 275 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1821 /* 278 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1822 /* 290 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1823 /* 293 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1824 /* 297 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1825 /* 301 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1826 /* 305 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1827 /* 308 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1828 /* 312 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1829 /* 316 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1830 /* 321 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1831 /* 326 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1832 /* 331 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1833 /* 338 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1834 /* 344 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1835 /* 346 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1836 /* 349 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1837 /* 352 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1838 /* 356 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1839 /* 361 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1840 /* 366 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1841 /* 371 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1842 /* 376 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1843 /* 381 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1844 /* 386 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1845 /* 391 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1846 /* 396 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1847 /* 401 */ { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1848 /* 406 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1849 /* 411 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1850 /* 416 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1851 /* 419 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1852 /* 423 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1853 /* 433 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1854 /* 442 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1855 /* 443 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1856 /* 446 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1857 /* 452 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1858 /* 457 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1859 /* 459 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1860 /* 461 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1861 /* 469 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1862 /* 472 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1863 /* 475 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1864 /* 478 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1865 /* 481 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1866 }
1867};
1868
1869
1870#ifdef __GNUC__
1871#pragma GCC diagnostic push
1872#pragma GCC diagnostic ignored "-Woverlength-strings"
1873#endif
1874extern const char SPIRVInstrNameData[] = {
1875 /* 0 */ "G_FLOG10\000"
1876 /* 9 */ "G_FEXP10\000"
1877 /* 18 */ "G_FLOG2\000"
1878 /* 26 */ "G_FATAN2\000"
1879 /* 35 */ "G_FEXP2\000"
1880 /* 43 */ "OpQuantizeToF16\000"
1881 /* 59 */ "G_FMA\000"
1882 /* 65 */ "G_STRICT_FMA\000"
1883 /* 78 */ "OpArbitraryFloatLog10ALTERA\000"
1884 /* 106 */ "OpArbitraryFloatExp10ALTERA\000"
1885 /* 134 */ "OpArbitraryFloatExpm1ALTERA\000"
1886 /* 162 */ "OpArbitraryFloatLog2ALTERA\000"
1887 /* 189 */ "OpArbitraryFloatATan2ALTERA\000"
1888 /* 217 */ "OpArbitraryFloatExp2ALTERA\000"
1889 /* 244 */ "OpArbitraryFloatGEALTERA\000"
1890 /* 269 */ "OpArbitraryFloatLEALTERA\000"
1891 /* 294 */ "OpArbitraryFloatPowNALTERA\000"
1892 /* 321 */ "OpArbitraryFloatEQALTERA\000"
1893 /* 346 */ "OpArbitraryFloatPowRALTERA\000"
1894 /* 373 */ "OpArbitraryFloatGTALTERA\000"
1895 /* 398 */ "OpArbitraryFloatLTALTERA\000"
1896 /* 423 */ "OpArbitraryFloatSubALTERA\000"
1897 /* 449 */ "OpArbitraryFloatAddALTERA\000"
1898 /* 475 */ "OpReadPipeBlockingALTERA\000"
1899 /* 500 */ "OpWritePipeBlockingALTERA\000"
1900 /* 526 */ "OpFixedLogALTERA\000"
1901 /* 543 */ "OpArbitraryFloatLogALTERA\000"
1902 /* 569 */ "OpArbitraryFloatATanPiALTERA\000"
1903 /* 598 */ "OpArbitraryFloatASinPiALTERA\000"
1904 /* 627 */ "OpFixedSinPiALTERA\000"
1905 /* 646 */ "OpArbitraryFloatSinPiALTERA\000"
1906 /* 674 */ "OpArbitraryFloatACosPiALTERA\000"
1907 /* 703 */ "OpFixedCosPiALTERA\000"
1908 /* 722 */ "OpFixedSinCosPiALTERA\000"
1909 /* 744 */ "OpArbitraryFloatSinCosPiALTERA\000"
1910 /* 775 */ "OpArbitraryFloatCosPiALTERA\000"
1911 /* 803 */ "OpArbitraryFloatMulALTERA\000"
1912 /* 829 */ "OpArbitraryFloatATanALTERA\000"
1913 /* 856 */ "OpArbitraryFloatASinALTERA\000"
1914 /* 883 */ "OpFixedSinALTERA\000"
1915 /* 900 */ "OpArbitraryFloatSinALTERA\000"
1916 /* 926 */ "OpArbitraryFloatLog1pALTERA\000"
1917 /* 954 */ "OpFixedRecipALTERA\000"
1918 /* 973 */ "OpArbitraryFloatRecipALTERA\000"
1919 /* 1001 */ "OpFixedExpALTERA\000"
1920 /* 1018 */ "OpArbitraryFloatExpALTERA\000"
1921 /* 1044 */ "OpArbitraryFloatACosALTERA\000"
1922 /* 1071 */ "OpFixedCosALTERA\000"
1923 /* 1088 */ "OpFixedSinCosALTERA\000"
1924 /* 1108 */ "OpArbitraryFloatSinCosALTERA\000"
1925 /* 1137 */ "OpArbitraryFloatCosALTERA\000"
1926 /* 1163 */ "OpArbitraryFloatCastFromIntALTERA\000"
1927 /* 1197 */ "OpArbitraryFloatCastToIntALTERA\000"
1928 /* 1229 */ "OpArbitraryFloatHypotALTERA\000"
1929 /* 1257 */ "OpArbitraryFloatCbrtALTERA\000"
1930 /* 1284 */ "OpArbitraryFloatRSqrtALTERA\000"
1931 /* 1312 */ "OpFixedSqrtALTERA\000"
1932 /* 1330 */ "OpArbitraryFloatSqrtALTERA\000"
1933 /* 1357 */ "OpFixedRsqrtALTERA\000"
1934 /* 1376 */ "OpArbitraryFloatCastALTERA\000"
1935 /* 1403 */ "OpArbitraryFloatDivALTERA\000"
1936 /* 1429 */ "OpArbitraryFloatPowALTERA\000"
1937 /* 1455 */ "OpGroupNonUniformBallotFindLSB\000"
1938 /* 1486 */ "OpGroupNonUniformBallotFindMSB\000"
1939 /* 1517 */ "G_FSUB\000"
1940 /* 1524 */ "G_STRICT_FSUB\000"
1941 /* 1538 */ "G_ATOMICRMW_FSUB\000"
1942 /* 1555 */ "G_SUB\000"
1943 /* 1561 */ "G_ATOMICRMW_SUB\000"
1944 /* 1577 */ "G_INTRINSIC\000"
1945 /* 1589 */ "G_FPTRUNC\000"
1946 /* 1599 */ "G_INTRINSIC_TRUNC\000"
1947 /* 1617 */ "G_TRUNC\000"
1948 /* 1625 */ "G_BUILD_VECTOR_TRUNC\000"
1949 /* 1646 */ "G_DYN_STACKALLOC\000"
1950 /* 1663 */ "G_FMAD\000"
1951 /* 1670 */ "G_INDEXED_SEXTLOAD\000"
1952 /* 1689 */ "G_SEXTLOAD\000"
1953 /* 1700 */ "G_INDEXED_ZEXTLOAD\000"
1954 /* 1719 */ "G_ZEXTLOAD\000"
1955 /* 1730 */ "G_INDEXED_LOAD\000"
1956 /* 1745 */ "G_LOAD\000"
1957 /* 1752 */ "G_VECREDUCE_FADD\000"
1958 /* 1769 */ "G_FADD\000"
1959 /* 1776 */ "G_VECREDUCE_SEQ_FADD\000"
1960 /* 1797 */ "G_STRICT_FADD\000"
1961 /* 1811 */ "G_ATOMICRMW_FADD\000"
1962 /* 1828 */ "G_VECREDUCE_ADD\000"
1963 /* 1844 */ "G_ADD\000"
1964 /* 1850 */ "G_PTR_ADD\000"
1965 /* 1860 */ "G_ATOMICRMW_ADD\000"
1966 /* 1876 */ "G_ATOMICRMW_NAND\000"
1967 /* 1893 */ "G_VECREDUCE_AND\000"
1968 /* 1909 */ "G_AND\000"
1969 /* 1915 */ "G_ATOMICRMW_AND\000"
1970 /* 1931 */ "LIFETIME_END\000"
1971 /* 1944 */ "G_BRCOND\000"
1972 /* 1953 */ "G_ATOMICRMW_USUB_COND\000"
1973 /* 1975 */ "G_LLROUND\000"
1974 /* 1985 */ "G_LROUND\000"
1975 /* 1994 */ "G_INTRINSIC_ROUND\000"
1976 /* 2012 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1977 /* 2038 */ "LOAD_STACK_GUARD\000"
1978 /* 2055 */ "PSEUDO_PROBE\000"
1979 /* 2068 */ "G_SSUBE\000"
1980 /* 2076 */ "G_USUBE\000"
1981 /* 2084 */ "G_FENCE\000"
1982 /* 2092 */ "ARITH_FENCE\000"
1983 /* 2104 */ "REG_SEQUENCE\000"
1984 /* 2117 */ "G_SADDE\000"
1985 /* 2125 */ "G_UADDE\000"
1986 /* 2133 */ "G_GET_FPMODE\000"
1987 /* 2146 */ "G_RESET_FPMODE\000"
1988 /* 2161 */ "G_SET_FPMODE\000"
1989 /* 2174 */ "G_FMINNUM_IEEE\000"
1990 /* 2189 */ "G_FMAXNUM_IEEE\000"
1991 /* 2204 */ "G_VSCALE\000"
1992 /* 2213 */ "G_JUMP_TABLE\000"
1993 /* 2226 */ "BUNDLE\000"
1994 /* 2233 */ "G_MEMCPY_INLINE\000"
1995 /* 2249 */ "RELOC_NONE\000"
1996 /* 2260 */ "LOCAL_ESCAPE\000"
1997 /* 2273 */ "ASSIGN_TYPE\000"
1998 /* 2285 */ "G_STACKRESTORE\000"
1999 /* 2300 */ "G_INDEXED_STORE\000"
2000 /* 2316 */ "G_STORE\000"
2001 /* 2324 */ "G_BITREVERSE\000"
2002 /* 2337 */ "FAKE_USE\000"
2003 /* 2346 */ "DBG_VALUE\000"
2004 /* 2356 */ "G_GLOBAL_VALUE\000"
2005 /* 2371 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2006 /* 2394 */ "CONVERGENCECTRL_GLUE\000"
2007 /* 2415 */ "G_STACKSAVE\000"
2008 /* 2427 */ "G_MEMMOVE\000"
2009 /* 2437 */ "G_FREEZE\000"
2010 /* 2446 */ "G_FCANONICALIZE\000"
2011 /* 2462 */ "G_FMODF\000"
2012 /* 2470 */ "G_CTLZ_ZERO_UNDEF\000"
2013 /* 2488 */ "G_CTTZ_ZERO_UNDEF\000"
2014 /* 2506 */ "INIT_UNDEF\000"
2015 /* 2517 */ "G_IMPLICIT_DEF\000"
2016 /* 2532 */ "DBG_INSTR_REF\000"
2017 /* 2546 */ "OpConvertSToF\000"
2018 /* 2560 */ "OpConvertUToF\000"
2019 /* 2574 */ "OpConstantF\000"
2020 /* 2586 */ "G_FNEG\000"
2021 /* 2593 */ "EXTRACT_SUBREG\000"
2022 /* 2608 */ "INSERT_SUBREG\000"
2023 /* 2622 */ "G_SEXT_INREG\000"
2024 /* 2635 */ "SUBREG_TO_REG\000"
2025 /* 2649 */ "G_ATOMIC_CMPXCHG\000"
2026 /* 2666 */ "G_ATOMICRMW_XCHG\000"
2027 /* 2683 */ "G_GET_ROUNDING\000"
2028 /* 2698 */ "G_SET_ROUNDING\000"
2029 /* 2713 */ "G_FLOG\000"
2030 /* 2720 */ "G_VAARG\000"
2031 /* 2728 */ "PREALLOCATED_ARG\000"
2032 /* 2745 */ "G_PREFETCH\000"
2033 /* 2756 */ "G_SMULH\000"
2034 /* 2764 */ "G_UMULH\000"
2035 /* 2772 */ "G_FTANH\000"
2036 /* 2780 */ "G_FSINH\000"
2037 /* 2788 */ "G_FCOSH\000"
2038 /* 2796 */ "DBG_PHI\000"
2039 /* 2804 */ "G_FPTOSI\000"
2040 /* 2813 */ "G_FPTOUI\000"
2041 /* 2822 */ "G_FPOWI\000"
2042 /* 2830 */ "OpConstantI\000"
2043 /* 2842 */ "COPY_LANEMASK\000"
2044 /* 2856 */ "G_PTRMASK\000"
2045 /* 2866 */ "GC_LABEL\000"
2046 /* 2875 */ "DBG_LABEL\000"
2047 /* 2885 */ "EH_LABEL\000"
2048 /* 2894 */ "ANNOTATION_LABEL\000"
2049 /* 2911 */ "ICALL_BRANCH_FUNNEL\000"
2050 /* 2931 */ "OpRoundFToTF32INTEL\000"
2051 /* 2951 */ "OpConvertFToBF16INTEL\000"
2052 /* 2973 */ "OpConvertBF16ToFINTEL\000"
2053 /* 2995 */ "OpSubgroupImageMediaBlockReadINTEL\000"
2054 /* 3030 */ "OpSubgroupImageBlockReadINTEL\000"
2055 /* 3060 */ "OpSubgroupBlockReadINTEL\000"
2056 /* 3085 */ "OpPredicatedLoadINTEL\000"
2057 /* 3107 */ "OpSubgroup2DBlockLoadINTEL\000"
2058 /* 3134 */ "OpCooperativeMatrixLoadCheckedINTEL\000"
2059 /* 3170 */ "OpCooperativeMatrixStoreCheckedINTEL\000"
2060 /* 3207 */ "OpCooperativeMatrixConstructCheckedINTEL\000"
2061 /* 3248 */ "OpSpecConstantCompositeContinuedINTEL\000"
2062 /* 3286 */ "OpConstantCompositeContinuedINTEL\000"
2063 /* 3320 */ "OpTypeStructContinuedINTEL\000"
2064 /* 3347 */ "OpCompositeConstructContinuedINTEL\000"
2065 /* 3382 */ "OpCooperativeMatrixGetElementCoordINTEL\000"
2066 /* 3422 */ "OpConvertHandleToSampledImageINTEL\000"
2067 /* 3457 */ "OpConvertHandleToImageINTEL\000"
2068 /* 3485 */ "OpSubgroupShuffleINTEL\000"
2069 /* 3508 */ "OpPredicatedStoreINTEL\000"
2070 /* 3531 */ "OpSubgroup2DBlockStoreINTEL\000"
2071 /* 3559 */ "OpSubgroup2DBlockLoadTransposeINTEL\000"
2072 /* 3595 */ "OpSubgroupMatrixMultiplyAccumulateINTEL\000"
2073 /* 3635 */ "OpSubgroupImageMediaBlockWriteINTEL\000"
2074 /* 3671 */ "OpSubgroupImageBlockWriteINTEL\000"
2075 /* 3702 */ "OpSubgroupBlockWriteINTEL\000"
2076 /* 3728 */ "OpControlBarrierArriveINTEL\000"
2077 /* 3756 */ "OpSubgroup2DBlockPrefetchINTEL\000"
2078 /* 3787 */ "OpCooperativeMatrixPrefetchINTEL\000"
2079 /* 3820 */ "OpAliasScopeDeclINTEL\000"
2080 /* 3842 */ "OpAliasDomainDeclINTEL\000"
2081 /* 3865 */ "OpAliasScopeListDeclINTEL\000"
2082 /* 3891 */ "OpAsmCallINTEL\000"
2083 /* 3906 */ "OpFunctionPointerCallINTEL\000"
2084 /* 3933 */ "OpLoopControlINTEL\000"
2085 /* 3952 */ "OpSubgroup2DBlockLoadTransformINTEL\000"
2086 /* 3988 */ "OpAsmINTEL\000"
2087 /* 3999 */ "OpBitwiseFunctionINTEL\000"
2088 /* 4022 */ "OpSubgroupShuffleDownINTEL\000"
2089 /* 4049 */ "OpSubgroupShuffleUpINTEL\000"
2090 /* 4074 */ "OpPtrCastToCrossWorkgroupINTEL\000"
2091 /* 4105 */ "OpMaskedGatherINTEL\000"
2092 /* 4125 */ "OpConvertHandleToSamplerINTEL\000"
2093 /* 4155 */ "OpConstantFunctionPointerINTEL\000"
2094 /* 4186 */ "OpMaskedScatterINTEL\000"
2095 /* 4207 */ "OpSubgroupShuffleXorINTEL\000"
2096 /* 4233 */ "OpCrossWorkgroupCastToPtrINTEL\000"
2097 /* 4264 */ "OpAsmTargetINTEL\000"
2098 /* 4281 */ "OpControlBarrierWaitINTEL\000"
2099 /* 4307 */ "OpVariableLengthArrayINTEL\000"
2100 /* 4334 */ "OpRestoreMemoryINTEL\000"
2101 /* 4355 */ "OpSaveMemoryINTEL\000"
2102 /* 4373 */ "G_FSHL\000"
2103 /* 4380 */ "G_SHL\000"
2104 /* 4386 */ "G_FCEIL\000"
2105 /* 4394 */ "G_SAVGCEIL\000"
2106 /* 4405 */ "G_UAVGCEIL\000"
2107 /* 4416 */ "PATCHABLE_TAIL_CALL\000"
2108 /* 4436 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2109 /* 4463 */ "PATCHABLE_EVENT_CALL\000"
2110 /* 4484 */ "FENTRY_CALL\000"
2111 /* 4496 */ "KILL\000"
2112 /* 4501 */ "G_CONSTANT_POOL\000"
2113 /* 4517 */ "G_ROTL\000"
2114 /* 4524 */ "G_VECREDUCE_FMUL\000"
2115 /* 4541 */ "G_FMUL\000"
2116 /* 4548 */ "G_VECREDUCE_SEQ_FMUL\000"
2117 /* 4569 */ "G_STRICT_FMUL\000"
2118 /* 4583 */ "G_VECREDUCE_MUL\000"
2119 /* 4599 */ "G_MUL\000"
2120 /* 4605 */ "G_FREM\000"
2121 /* 4612 */ "G_STRICT_FREM\000"
2122 /* 4626 */ "G_SREM\000"
2123 /* 4633 */ "G_UREM\000"
2124 /* 4640 */ "G_SDIVREM\000"
2125 /* 4650 */ "G_UDIVREM\000"
2126 /* 4660 */ "INLINEASM\000"
2127 /* 4670 */ "G_VECREDUCE_FMINIMUM\000"
2128 /* 4691 */ "G_FMINIMUM\000"
2129 /* 4702 */ "G_ATOMICRMW_FMINIMUM\000"
2130 /* 4723 */ "G_VECREDUCE_FMAXIMUM\000"
2131 /* 4744 */ "G_FMAXIMUM\000"
2132 /* 4755 */ "G_ATOMICRMW_FMAXIMUM\000"
2133 /* 4776 */ "G_FMINIMUMNUM\000"
2134 /* 4790 */ "G_FMAXIMUMNUM\000"
2135 /* 4804 */ "G_FMINNUM\000"
2136 /* 4814 */ "G_FMAXNUM\000"
2137 /* 4824 */ "G_FATAN\000"
2138 /* 4832 */ "G_FTAN\000"
2139 /* 4839 */ "G_INTRINSIC_ROUNDEVEN\000"
2140 /* 4861 */ "G_ASSERT_ALIGN\000"
2141 /* 4876 */ "G_FCOPYSIGN\000"
2142 /* 4888 */ "G_VECREDUCE_FMIN\000"
2143 /* 4905 */ "G_ATOMICRMW_FMIN\000"
2144 /* 4922 */ "G_VECREDUCE_SMIN\000"
2145 /* 4939 */ "G_SMIN\000"
2146 /* 4946 */ "G_VECREDUCE_UMIN\000"
2147 /* 4963 */ "G_UMIN\000"
2148 /* 4970 */ "G_ATOMICRMW_UMIN\000"
2149 /* 4987 */ "G_ATOMICRMW_MIN\000"
2150 /* 5003 */ "G_FASIN\000"
2151 /* 5011 */ "G_FSIN\000"
2152 /* 5018 */ "CFI_INSTRUCTION\000"
2153 /* 5034 */ "G_SSUBO\000"
2154 /* 5042 */ "G_USUBO\000"
2155 /* 5050 */ "G_SADDO\000"
2156 /* 5058 */ "G_UADDO\000"
2157 /* 5066 */ "JUMP_TABLE_DEBUG_INFO\000"
2158 /* 5088 */ "G_SMULO\000"
2159 /* 5096 */ "G_UMULO\000"
2160 /* 5104 */ "G_BZERO\000"
2161 /* 5112 */ "STACKMAP\000"
2162 /* 5121 */ "G_DEBUGTRAP\000"
2163 /* 5133 */ "G_UBSANTRAP\000"
2164 /* 5145 */ "G_TRAP\000"
2165 /* 5152 */ "G_ATOMICRMW_UDEC_WRAP\000"
2166 /* 5174 */ "G_ATOMICRMW_UINC_WRAP\000"
2167 /* 5196 */ "G_BSWAP\000"
2168 /* 5204 */ "G_SITOFP\000"
2169 /* 5213 */ "G_UITOFP\000"
2170 /* 5222 */ "G_FCMP\000"
2171 /* 5229 */ "G_ICMP\000"
2172 /* 5236 */ "G_SCMP\000"
2173 /* 5243 */ "G_UCMP\000"
2174 /* 5250 */ "CONVERGENCECTRL_LOOP\000"
2175 /* 5271 */ "G_CTPOP\000"
2176 /* 5279 */ "PATCHABLE_OP\000"
2177 /* 5292 */ "FAULTING_OP\000"
2178 /* 5304 */ "PREALLOCATED_SETUP\000"
2179 /* 5323 */ "G_FLDEXP\000"
2180 /* 5332 */ "G_STRICT_FLDEXP\000"
2181 /* 5348 */ "G_FEXP\000"
2182 /* 5355 */ "G_FFREXP\000"
2183 /* 5364 */ "G_BR\000"
2184 /* 5369 */ "INLINEASM_BR\000"
2185 /* 5382 */ "G_BLOCK_ADDR\000"
2186 /* 5395 */ "MEMBARRIER\000"
2187 /* 5406 */ "G_CONSTANT_FOLD_BARRIER\000"
2188 /* 5430 */ "PATCHABLE_FUNCTION_ENTER\000"
2189 /* 5455 */ "G_READCYCLECOUNTER\000"
2190 /* 5474 */ "G_READSTEADYCOUNTER\000"
2191 /* 5494 */ "G_READ_REGISTER\000"
2192 /* 5510 */ "G_WRITE_REGISTER\000"
2193 /* 5527 */ "OpFmaKHR\000"
2194 /* 5536 */ "OpCooperativeMatrixLoadKHR\000"
2195 /* 5563 */ "OpCooperativeMatrixMulAddKHR\000"
2196 /* 5592 */ "OpGroupBitwiseAndKHR\000"
2197 /* 5613 */ "OpGroupLogicalAndKHR\000"
2198 /* 5634 */ "OpCooperativeMatrixStoreKHR\000"
2199 /* 5662 */ "OpGroupNonUniformRotateKHR\000"
2200 /* 5689 */ "OpAssumeTrueKHR\000"
2201 /* 5705 */ "OpCooperativeMatrixLengthKHR\000"
2202 /* 5734 */ "OpReadClockKHR\000"
2203 /* 5749 */ "OpGroupFMulKHR\000"
2204 /* 5764 */ "OpGroupIMulKHR\000"
2205 /* 5779 */ "OpGroupBitwiseOrKHR\000"
2206 /* 5799 */ "OpGroupLogicalOrKHR\000"
2207 /* 5819 */ "OpGroupBitwiseXorKHR\000"
2208 /* 5840 */ "OpGroupLogicalXorKHR\000"
2209 /* 5861 */ "OpExpectKHR\000"
2210 /* 5873 */ "OpTypeCooperativeMatrixKHR\000"
2211 /* 5900 */ "G_ASHR\000"
2212 /* 5907 */ "G_FSHR\000"
2213 /* 5914 */ "G_LSHR\000"
2214 /* 5921 */ "CONVERGENCECTRL_ANCHOR\000"
2215 /* 5944 */ "G_FFLOOR\000"
2216 /* 5953 */ "G_SAVGFLOOR\000"
2217 /* 5965 */ "G_UAVGFLOOR\000"
2218 /* 5977 */ "G_EXTRACT_SUBVECTOR\000"
2219 /* 5997 */ "G_INSERT_SUBVECTOR\000"
2220 /* 6016 */ "G_BUILD_VECTOR\000"
2221 /* 6031 */ "G_SHUFFLE_VECTOR\000"
2222 /* 6048 */ "G_STEP_VECTOR\000"
2223 /* 6062 */ "G_SPLAT_VECTOR\000"
2224 /* 6077 */ "G_VECREDUCE_XOR\000"
2225 /* 6093 */ "G_XOR\000"
2226 /* 6099 */ "G_ATOMICRMW_XOR\000"
2227 /* 6115 */ "G_VECREDUCE_OR\000"
2228 /* 6130 */ "G_OR\000"
2229 /* 6135 */ "G_ATOMICRMW_OR\000"
2230 /* 6150 */ "G_ROTR\000"
2231 /* 6157 */ "G_INTTOPTR\000"
2232 /* 6168 */ "G_FABS\000"
2233 /* 6175 */ "G_ABS\000"
2234 /* 6181 */ "G_ABDS\000"
2235 /* 6188 */ "G_UNMERGE_VALUES\000"
2236 /* 6205 */ "G_MERGE_VALUES\000"
2237 /* 6220 */ "G_CTLS\000"
2238 /* 6227 */ "G_FACOS\000"
2239 /* 6235 */ "G_FCOS\000"
2240 /* 6242 */ "G_FSINCOS\000"
2241 /* 6252 */ "G_CONCAT_VECTORS\000"
2242 /* 6269 */ "COPY_TO_REGCLASS\000"
2243 /* 6286 */ "G_IS_FPCLASS\000"
2244 /* 6299 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2245 /* 6329 */ "G_VECTOR_COMPRESS\000"
2246 /* 6347 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2247 /* 6374 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2248 /* 6412 */ "G_TRUNC_SSAT_S\000"
2249 /* 6427 */ "OpFSubS\000"
2250 /* 6435 */ "OpStrictFSubS\000"
2251 /* 6449 */ "OpISubS\000"
2252 /* 6457 */ "OpShiftRightArithmeticS\000"
2253 /* 6481 */ "OpFAddS\000"
2254 /* 6489 */ "OpStrictFAddS\000"
2255 /* 6503 */ "OpIAddS\000"
2256 /* 6511 */ "OpBitwiseAndS\000"
2257 /* 6525 */ "OpUModS\000"
2258 /* 6533 */ "OpShiftLeftLogicalS\000"
2259 /* 6553 */ "OpShiftRightLogicalS\000"
2260 /* 6574 */ "OpFMulS\000"
2261 /* 6582 */ "OpStrictFMulS\000"
2262 /* 6596 */ "OpIMulS\000"
2263 /* 6604 */ "OpFRemS\000"
2264 /* 6612 */ "OpStrictFRemS\000"
2265 /* 6626 */ "OpSRemS\000"
2266 /* 6634 */ "OpConvertFToS\000"
2267 /* 6648 */ "OpSatConvertUToS\000"
2268 /* 6665 */ "OpBitwiseOrS\000"
2269 /* 6678 */ "OpBitwiseXorS\000"
2270 /* 6692 */ "OpFDivS\000"
2271 /* 6700 */ "OpStrictFDivS\000"
2272 /* 6714 */ "OpSDivS\000"
2273 /* 6722 */ "OpUDivS\000"
2274 /* 6730 */ "OpISubBorrowS\000"
2275 /* 6744 */ "OpIAddCarryS\000"
2276 /* 6757 */ "G_SSUBSAT\000"
2277 /* 6767 */ "G_USUBSAT\000"
2278 /* 6777 */ "G_SADDSAT\000"
2279 /* 6787 */ "G_UADDSAT\000"
2280 /* 6797 */ "G_SSHLSAT\000"
2281 /* 6807 */ "G_USHLSAT\000"
2282 /* 6817 */ "G_SMULFIXSAT\000"
2283 /* 6830 */ "G_UMULFIXSAT\000"
2284 /* 6843 */ "G_SDIVFIXSAT\000"
2285 /* 6856 */ "G_UDIVFIXSAT\000"
2286 /* 6869 */ "G_ATOMICRMW_USUB_SAT\000"
2287 /* 6890 */ "G_FPTOSI_SAT\000"
2288 /* 6903 */ "G_FPTOUI_SAT\000"
2289 /* 6916 */ "G_EXTRACT\000"
2290 /* 6926 */ "G_SELECT\000"
2291 /* 6935 */ "G_BRINDIRECT\000"
2292 /* 6948 */ "PATCHABLE_RET\000"
2293 /* 6962 */ "G_MEMSET\000"
2294 /* 6971 */ "PATCHABLE_FUNCTION_EXIT\000"
2295 /* 6995 */ "G_BRJT\000"
2296 /* 7002 */ "G_EXTRACT_VECTOR_ELT\000"
2297 /* 7023 */ "G_INSERT_VECTOR_ELT\000"
2298 /* 7043 */ "G_FCONSTANT\000"
2299 /* 7055 */ "G_CONSTANT\000"
2300 /* 7066 */ "G_INTRINSIC_CONVERGENT\000"
2301 /* 7089 */ "STATEPOINT\000"
2302 /* 7100 */ "PATCHPOINT\000"
2303 /* 7111 */ "G_PTRTOINT\000"
2304 /* 7122 */ "G_FRINT\000"
2305 /* 7130 */ "G_INTRINSIC_LLRINT\000"
2306 /* 7149 */ "G_INTRINSIC_LRINT\000"
2307 /* 7167 */ "G_FNEARBYINT\000"
2308 /* 7180 */ "G_VASTART\000"
2309 /* 7190 */ "LIFETIME_START\000"
2310 /* 7205 */ "G_INVOKE_REGION_START\000"
2311 /* 7227 */ "G_INSERT\000"
2312 /* 7236 */ "G_FSQRT\000"
2313 /* 7244 */ "G_STRICT_FSQRT\000"
2314 /* 7259 */ "G_BITCAST\000"
2315 /* 7269 */ "G_ADDRSPACE_CAST\000"
2316 /* 7286 */ "DBG_VALUE_LIST\000"
2317 /* 7301 */ "G_FPEXT\000"
2318 /* 7309 */ "G_SEXT\000"
2319 /* 7316 */ "G_ASSERT_SEXT\000"
2320 /* 7330 */ "G_ANYEXT\000"
2321 /* 7339 */ "G_ZEXT\000"
2322 /* 7346 */ "G_ASSERT_ZEXT\000"
2323 /* 7360 */ "OpAtomicFAddEXT\000"
2324 /* 7376 */ "OpArithmeticFenceEXT\000"
2325 /* 7397 */ "OpAtomicFMinEXT\000"
2326 /* 7413 */ "OpAtomicFMaxEXT\000"
2327 /* 7429 */ "G_ABDU\000"
2328 /* 7436 */ "G_TRUNC_SSAT_U\000"
2329 /* 7451 */ "G_TRUNC_USAT_U\000"
2330 /* 7466 */ "OpConvertFToU\000"
2331 /* 7480 */ "OpSatConvertSToU\000"
2332 /* 7497 */ "OpConvertPtrToU\000"
2333 /* 7513 */ "G_FDIV\000"
2334 /* 7520 */ "G_STRICT_FDIV\000"
2335 /* 7534 */ "G_SDIV\000"
2336 /* 7541 */ "G_UDIV\000"
2337 /* 7548 */ "G_GET_FPENV\000"
2338 /* 7560 */ "G_RESET_FPENV\000"
2339 /* 7574 */ "G_SET_FPENV\000"
2340 /* 7586 */ "OpTypeAccelerationStructureNV\000"
2341 /* 7616 */ "OpImageSampleFootprintNV\000"
2342 /* 7641 */ "OpTypeCooperativeMatrixNV\000"
2343 /* 7667 */ "OpFSubV\000"
2344 /* 7675 */ "OpStrictFSubV\000"
2345 /* 7689 */ "OpISubV\000"
2346 /* 7697 */ "OpShiftRightArithmeticV\000"
2347 /* 7721 */ "OpFAddV\000"
2348 /* 7729 */ "OpStrictFAddV\000"
2349 /* 7743 */ "OpIAddV\000"
2350 /* 7751 */ "OpBitwiseAndV\000"
2351 /* 7765 */ "OpUModV\000"
2352 /* 7773 */ "OpFNegateV\000"
2353 /* 7784 */ "OpShiftLeftLogicalV\000"
2354 /* 7804 */ "OpShiftRightLogicalV\000"
2355 /* 7825 */ "OpFMulV\000"
2356 /* 7833 */ "OpStrictFMulV\000"
2357 /* 7847 */ "OpIMulV\000"
2358 /* 7855 */ "OpFRemV\000"
2359 /* 7863 */ "OpStrictFRemV\000"
2360 /* 7877 */ "OpSRemV\000"
2361 /* 7885 */ "OpBitwiseOrV\000"
2362 /* 7898 */ "OpBitwiseXorV\000"
2363 /* 7912 */ "OpFDivV\000"
2364 /* 7920 */ "OpStrictFDivV\000"
2365 /* 7934 */ "OpSDivV\000"
2366 /* 7942 */ "OpUDivV\000"
2367 /* 7950 */ "OpISubBorrowV\000"
2368 /* 7964 */ "OpIAddCarryV\000"
2369 /* 7977 */ "G_FPOW\000"
2370 /* 7984 */ "G_VECREDUCE_FMAX\000"
2371 /* 8001 */ "G_ATOMICRMW_FMAX\000"
2372 /* 8018 */ "G_VECREDUCE_SMAX\000"
2373 /* 8035 */ "G_SMAX\000"
2374 /* 8042 */ "G_VECREDUCE_UMAX\000"
2375 /* 8059 */ "G_UMAX\000"
2376 /* 8066 */ "G_ATOMICRMW_UMAX\000"
2377 /* 8083 */ "G_ATOMICRMW_MAX\000"
2378 /* 8099 */ "G_FRAME_INDEX\000"
2379 /* 8113 */ "G_SBFX\000"
2380 /* 8120 */ "G_UBFX\000"
2381 /* 8127 */ "G_SMULFIX\000"
2382 /* 8137 */ "G_UMULFIX\000"
2383 /* 8147 */ "G_SDIVFIX\000"
2384 /* 8157 */ "G_UDIVFIX\000"
2385 /* 8167 */ "G_MEMCPY\000"
2386 /* 8176 */ "COPY\000"
2387 /* 8181 */ "CONVERGENCECTRL_ENTRY\000"
2388 /* 8203 */ "G_CTLZ\000"
2389 /* 8210 */ "G_CTTZ\000"
2390 /* 8217 */ "OpAtomicISub\000"
2391 /* 8230 */ "OpVectorExtractDynamic\000"
2392 /* 8253 */ "OpVectorInsertDynamic\000"
2393 /* 8275 */ "OpPtrCastToGeneric\000"
2394 /* 8294 */ "OpExecutionModeId\000"
2395 /* 8312 */ "OpDecorateId\000"
2396 /* 8325 */ "OpIsValidReserveId\000"
2397 /* 8344 */ "OpTypeReserveId\000"
2398 /* 8360 */ "OpImageRead\000"
2399 /* 8372 */ "OpImageSparseRead\000"
2400 /* 8390 */ "OpAtomicLoad\000"
2401 /* 8403 */ "OpLoad\000"
2402 /* 8410 */ "OpGroupNonUniformFAdd\000"
2403 /* 8432 */ "OpGroupFAdd\000"
2404 /* 8444 */ "OpAtomicIAdd\000"
2405 /* 8457 */ "OpGroupNonUniformIAdd\000"
2406 /* 8479 */ "OpGroupIAdd\000"
2407 /* 8491 */ "OpSMulExtended\000"
2408 /* 8506 */ "OpUMulExtended\000"
2409 /* 8521 */ "OpOrdered\000"
2410 /* 8531 */ "OpUnordered\000"
2411 /* 8543 */ "OpModuleProcessed\000"
2412 /* 8561 */ "OpSourceContinued\000"
2413 /* 8579 */ "OpCopyMemorySized\000"
2414 /* 8597 */ "OpTypeVoid\000"
2415 /* 8608 */ "OpAtomicAnd\000"
2416 /* 8620 */ "OpGroupNonUniformBitwiseAnd\000"
2417 /* 8648 */ "OpGroupNonUniformLogicalAnd\000"
2418 /* 8676 */ "OpLogicalAnd\000"
2419 /* 8689 */ "OpFunctionEnd\000"
2420 /* 8703 */ "OpSelectSFSCond\000"
2421 /* 8719 */ "OpSelectVFSCond\000"
2422 /* 8735 */ "OpSelectSISCond\000"
2423 /* 8751 */ "OpSelectVISCond\000"
2424 /* 8767 */ "OpSelectSPSCond\000"
2425 /* 8783 */ "OpSelectVPSCond\000"
2426 /* 8799 */ "OpSelectSFVCond\000"
2427 /* 8815 */ "OpSelectVFVCond\000"
2428 /* 8831 */ "OpSelectSIVCond\000"
2429 /* 8847 */ "OpSelectVIVCond\000"
2430 /* 8863 */ "OpSelectSPVCond\000"
2431 /* 8879 */ "OpSelectVPVCond\000"
2432 /* 8895 */ "OpImageQuerySizeLod\000"
2433 /* 8915 */ "OpImageSampleImplicitLod\000"
2434 /* 8940 */ "OpImageSparseSampleImplicitLod\000"
2435 /* 8971 */ "OpImageSampleDrefImplicitLod\000"
2436 /* 9000 */ "OpImageSparseSampleDrefImplicitLod\000"
2437 /* 9035 */ "OpImageSampleProjDrefImplicitLod\000"
2438 /* 9068 */ "OpImageSparseSampleProjDrefImplicitLod\000"
2439 /* 9107 */ "OpImageSampleProjImplicitLod\000"
2440 /* 9136 */ "OpImageSparseSampleProjImplicitLod\000"
2441 /* 9171 */ "OpImageSampleExplicitLod\000"
2442 /* 9196 */ "OpImageSparseSampleExplicitLod\000"
2443 /* 9227 */ "OpImageSampleDrefExplicitLod\000"
2444 /* 9256 */ "OpImageSparseSampleDrefExplicitLod\000"
2445 /* 9291 */ "OpImageSampleProjDrefExplicitLod\000"
2446 /* 9324 */ "OpImageSparseSampleProjDrefExplicitLod\000"
2447 /* 9363 */ "OpImageSampleProjExplicitLod\000"
2448 /* 9392 */ "OpImageSparseSampleProjExplicitLod\000"
2449 /* 9427 */ "OpImageQueryLod\000"
2450 /* 9443 */ "OpFMod\000"
2451 /* 9450 */ "OpSMod\000"
2452 /* 9457 */ "OpSource\000"
2453 /* 9466 */ "OpExecutionMode\000"
2454 /* 9482 */ "OpTypeSampledImage\000"
2455 /* 9501 */ "OpSampledImage\000"
2456 /* 9516 */ "OpTypeImage\000"
2457 /* 9528 */ "OpImage\000"
2458 /* 9536 */ "OpTypePipeStorage\000"
2459 /* 9554 */ "OpBuildNDRange\000"
2460 /* 9569 */ "OpAtomicExchange\000"
2461 /* 9586 */ "OpAtomicCompareExchange\000"
2462 /* 9610 */ "OpSelectionMerge\000"
2463 /* 9627 */ "OpLoopMerge\000"
2464 /* 9639 */ "OpUnreachable\000"
2465 /* 9653 */ "OpVariable\000"
2466 /* 9664 */ "OpGroupNonUniformShuffle\000"
2467 /* 9689 */ "OpVectorShuffle\000"
2468 /* 9705 */ "OpName\000"
2469 /* 9712 */ "OpMemberName\000"
2470 /* 9725 */ "OpFwidthFine\000"
2471 /* 9738 */ "OpDPdxFine\000"
2472 /* 9749 */ "OpDPdyFine\000"
2473 /* 9760 */ "OpNoLine\000"
2474 /* 9769 */ "OpLine\000"
2475 /* 9776 */ "OpReservedReadPipe\000"
2476 /* 9795 */ "OpReadPipe\000"
2477 /* 9806 */ "OpCommitReadPipe\000"
2478 /* 9823 */ "OpGroupCommitReadPipe\000"
2479 /* 9845 */ "OpTypePipe\000"
2480 /* 9856 */ "OpReservedWritePipe\000"
2481 /* 9876 */ "OpWritePipe\000"
2482 /* 9888 */ "OpCommitWritePipe\000"
2483 /* 9906 */ "OpGroupCommitWritePipe\000"
2484 /* 9929 */ "UNKNOWN_type\000"
2485 /* 9942 */ "OpAtomicStore\000"
2486 /* 9956 */ "OpStore\000"
2487 /* 9964 */ "OpSpecConstantFalse\000"
2488 /* 9984 */ "OpConstantFalse\000"
2489 /* 10000 */ "OpTranspose\000"
2490 /* 10012 */ "OpFwidthCoarse\000"
2491 /* 10027 */ "OpDPdxCoarse\000"
2492 /* 10040 */ "OpDPdyCoarse\000"
2493 /* 10053 */ "OpBitReverse\000"
2494 /* 10066 */ "OpFNegate\000"
2495 /* 10076 */ "OpSNegate\000"
2496 /* 10086 */ "OpDecorate\000"
2497 /* 10097 */ "OpMemberDecorate\000"
2498 /* 10114 */ "OpIsFinite\000"
2499 /* 10125 */ "OpImageWrite\000"
2500 /* 10138 */ "OpSpecConstantComposite\000"
2501 /* 10162 */ "OpConstantComposite\000"
2502 /* 10182 */ "OpTypeQueue\000"
2503 /* 10194 */ "OpGetDefaultQueue\000"
2504 /* 10212 */ "OpReturnValue\000"
2505 /* 10226 */ "OpTypeOpaque\000"
2506 /* 10239 */ "OpSpecConstantTrue\000"
2507 /* 10258 */ "OpConstantTrue\000"
2508 /* 10273 */ "OpEndPrimitive\000"
2509 /* 10288 */ "OpEndStreamPrimitive\000"
2510 /* 10309 */ "OpImageQuerySize\000"
2511 /* 10326 */ "OpNamedBarrierInitialize\000"
2512 /* 10351 */ "OpSizeOf\000"
2513 /* 10360 */ "OpUndef\000"
2514 /* 10368 */ "OpPtrDiff\000"
2515 /* 10378 */ "OpIsInf\000"
2516 /* 10386 */ "OpDecorateString\000"
2517 /* 10403 */ "OpMemberDecorateString\000"
2518 /* 10426 */ "OpString\000"
2519 /* 10435 */ "OpBranch\000"
2520 /* 10444 */ "OpImageFetch\000"
2521 /* 10457 */ "OpImageSparseFetch\000"
2522 /* 10476 */ "OpSwitch\000"
2523 /* 10485 */ "OpFwidth\000"
2524 /* 10494 */ "OpArrayLength\000"
2525 /* 10508 */ "OpPhi\000"
2526 /* 10514 */ "OpAtomicCompareExchangeWeak\000"
2527 /* 10542 */ "OpCopyLogical\000"
2528 /* 10556 */ "OpIsNormal\000"
2529 /* 10567 */ "OpBranchConditional\000"
2530 /* 10587 */ "OpIEqual\000"
2531 /* 10596 */ "OpFOrdEqual\000"
2532 /* 10608 */ "OpFUnordEqual\000"
2533 /* 10622 */ "OpLogicalEqual\000"
2534 /* 10637 */ "OpGroupNonUniformAllEqual\000"
2535 /* 10663 */ "OpSGreaterThanEqual\000"
2536 /* 10683 */ "OpUGreaterThanEqual\000"
2537 /* 10703 */ "OpFOrdGreaterThanEqual\000"
2538 /* 10726 */ "OpFUnordGreaterThanEqual\000"
2539 /* 10751 */ "OpSLessThanEqual\000"
2540 /* 10768 */ "OpULessThanEqual\000"
2541 /* 10785 */ "OpFOrdLessThanEqual\000"
2542 /* 10805 */ "OpFUnordLessThanEqual\000"
2543 /* 10827 */ "OpPtrEqual\000"
2544 /* 10838 */ "OpINotEqual\000"
2545 /* 10850 */ "OpFOrdNotEqual\000"
2546 /* 10865 */ "OpFUnordNotEqual\000"
2547 /* 10882 */ "OpLogicalNotEqual\000"
2548 /* 10900 */ "OpPtrNotEqual\000"
2549 /* 10914 */ "OpLabel\000"
2550 /* 10922 */ "OpMemoryModel\000"
2551 /* 10936 */ "OpEnqueueKernel\000"
2552 /* 10952 */ "OpGroupNonUniformAll\000"
2553 /* 10973 */ "OpAll\000"
2554 /* 10979 */ "OpGroupAll\000"
2555 /* 10990 */ "OpFunctionCall\000"
2556 /* 11005 */ "OpKill\000"
2557 /* 11012 */ "OpConstantNull\000"
2558 /* 11027 */ "OpTypeBool\000"
2559 /* 11038 */ "OpGroupNonUniformFMul\000"
2560 /* 11060 */ "OpGroupNonUniformIMul\000"
2561 /* 11082 */ "OpIsNan\000"
2562 /* 11090 */ "OpSGreaterThan\000"
2563 /* 11105 */ "OpUGreaterThan\000"
2564 /* 11120 */ "OpFOrdGreaterThan\000"
2565 /* 11138 */ "OpFUnordGreaterThan\000"
2566 /* 11158 */ "OpSLessThan\000"
2567 /* 11170 */ "OpULessThan\000"
2568 /* 11182 */ "OpFOrdLessThan\000"
2569 /* 11197 */ "OpFUnordLessThan\000"
2570 /* 11214 */ "OpGroupNonUniformFMin\000"
2571 /* 11236 */ "OpGroupFMin\000"
2572 /* 11248 */ "OpAtomicSMin\000"
2573 /* 11261 */ "OpGroupNonUniformSMin\000"
2574 /* 11283 */ "OpGroupSMin\000"
2575 /* 11295 */ "OpAtomicUMin\000"
2576 /* 11308 */ "OpGroupNonUniformUMin\000"
2577 /* 11330 */ "OpGroupUMin\000"
2578 /* 11342 */ "OpAccessChain\000"
2579 /* 11356 */ "OpPtrAccessChain\000"
2580 /* 11373 */ "OpInBoundsPtrAccessChain\000"
2581 /* 11398 */ "OpInBoundsAccessChain\000"
2582 /* 11420 */ "OpSourceExtension\000"
2583 /* 11438 */ "OpExtension\000"
2584 /* 11450 */ "OpDemoteToHelperInvocation\000"
2585 /* 11477 */ "OpTypeFunction\000"
2586 /* 11492 */ "OpFunction\000"
2587 /* 11503 */ "OpReturn\000"
2588 /* 11512 */ "OpGroupNonUniformShuffleDown\000"
2589 /* 11541 */ "OpCaptureEventProfilingInfo\000"
2590 /* 11569 */ "OpSpecConstantOp\000"
2591 /* 11586 */ "OpGroupNonUniformShuffleUp\000"
2592 /* 11613 */ "OpNop\000"
2593 /* 11619 */ "OpLifetimeStop\000"
2594 /* 11634 */ "OpAtomicOr\000"
2595 /* 11645 */ "OpGroupNonUniformBitwiseOr\000"
2596 /* 11672 */ "OpGroupNonUniformLogicalOr\000"
2597 /* 11699 */ "OpLogicalOr\000"
2598 /* 11711 */ "OpAtomicFlagClear\000"
2599 /* 11729 */ "OpVectorTimesScalar\000"
2600 /* 11749 */ "OpMatrixTimesScalar\000"
2601 /* 11769 */ "OpImageQueryOrder\000"
2602 /* 11787 */ "OpImageGather\000"
2603 /* 11801 */ "OpImageSparseGather\000"
2604 /* 11821 */ "OpImageDrefGather\000"
2605 /* 11839 */ "OpImageSparseDrefGather\000"
2606 /* 11863 */ "OpTypeNamedBarrier\000"
2607 /* 11882 */ "OpMemoryNamedBarrier\000"
2608 /* 11903 */ "OpControlBarrier\000"
2609 /* 11920 */ "OpMemoryBarrier\000"
2610 /* 11936 */ "OpTypeSampler\000"
2611 /* 11950 */ "OpConstantSampler\000"
2612 /* 11968 */ "OpLessOrGreater\000"
2613 /* 11984 */ "OpFunctionParameter\000"
2614 /* 12004 */ "OpTypeForwardPointer\000"
2615 /* 12025 */ "OpTypePointer\000"
2616 /* 12039 */ "OpImageTexelPointer\000"
2617 /* 12059 */ "OpAtomicXor\000"
2618 /* 12071 */ "OpGroupNonUniformShuffleXor\000"
2619 /* 12099 */ "OpGroupNonUniformBitwiseXor\000"
2620 /* 12127 */ "OpGroupNonUniformLogicalXor\000"
2621 /* 12155 */ "OpTypeVector\000"
2622 /* 12168 */ "OpMatrixTimesVector\000"
2623 /* 12188 */ "OpConvertUToPtr\000"
2624 /* 12204 */ "OpGenericCastToPtr\000"
2625 /* 12223 */ "OpGenericPtrMemSemantics\000"
2626 /* 12248 */ "OpImageQuerySamples\000"
2627 /* 12268 */ "OpImageQueryLevels\000"
2628 /* 12287 */ "OpReserveReadPipePackets\000"
2629 /* 12312 */ "OpGroupReserveReadPipePackets\000"
2630 /* 12342 */ "OpReserveWritePipePackets\000"
2631 /* 12368 */ "OpGroupReserveWritePipePackets\000"
2632 /* 12399 */ "OpGetNumPipePackets\000"
2633 /* 12419 */ "OpGetMaxPipePackets\000"
2634 /* 12439 */ "OpGroupWaitEvents\000"
2635 /* 12457 */ "OpSetUserEventStatus\000"
2636 /* 12478 */ "OpSDotAccSat\000"
2637 /* 12491 */ "OpSUDotAccSat\000"
2638 /* 12505 */ "OpUDotAccSat\000"
2639 /* 12518 */ "OpImageQueryFormat\000"
2640 /* 12537 */ "OpTypeFloat\000"
2641 /* 12549 */ "OpBitFieldSExtract\000"
2642 /* 12568 */ "OpBitFieldUExtract\000"
2643 /* 12587 */ "OpCompositeExtract\000"
2644 /* 12606 */ "OpGroupNonUniformBallotBitExtract\000"
2645 /* 12640 */ "OpCopyObject\000"
2646 /* 12653 */ "OpGroupNonUniformElect\000"
2647 /* 12676 */ "OpOuterProduct\000"
2648 /* 12691 */ "OpTypeStruct\000"
2649 /* 12704 */ "OpCompositeConstruct\000"
2650 /* 12725 */ "OpAtomicFlagTestAndSet\000"
2651 /* 12748 */ "OpSignBitSet\000"
2652 /* 12761 */ "OpGenericCastToPtrExplicit\000"
2653 /* 12788 */ "OpTypeInt\000"
2654 /* 12798 */ "OpSpecConstant\000"
2655 /* 12813 */ "OpImageSparseTexelsResident\000"
2656 /* 12841 */ "OpAtomicIDecrement\000"
2657 /* 12860 */ "OpAtomicIIncrement\000"
2658 /* 12879 */ "OpIsValidEvent\000"
2659 /* 12894 */ "OpTypeDeviceEvent\000"
2660 /* 12912 */ "OpTypeEvent\000"
2661 /* 12924 */ "OpReleaseEvent\000"
2662 /* 12939 */ "OpRetainEvent\000"
2663 /* 12953 */ "OpCreateUserEvent\000"
2664 /* 12971 */ "OpEntryPoint\000"
2665 /* 12984 */ "OpBitCount\000"
2666 /* 12995 */ "OpGroupNonUniformBallotBitCount\000"
2667 /* 13027 */ "OpSDot\000"
2668 /* 13034 */ "OpSUDot\000"
2669 /* 13042 */ "OpUDot\000"
2670 /* 13049 */ "OpDot\000"
2671 /* 13055 */ "OpLogicalNot\000"
2672 /* 13068 */ "OpNot\000"
2673 /* 13074 */ "OpGroupNonUniformInverseBallot\000"
2674 /* 13105 */ "OpGroupNonUniformBallot\000"
2675 /* 13129 */ "OpLifetimeStart\000"
2676 /* 13145 */ "OpBitFieldInsert\000"
2677 /* 13162 */ "OpCompositeInsert\000"
2678 /* 13180 */ "OpFConvert\000"
2679 /* 13191 */ "OpSConvert\000"
2680 /* 13202 */ "OpUConvert\000"
2681 /* 13213 */ "OpExtInstImport\000"
2682 /* 13229 */ "OpGroupNonUniformBroadcast\000"
2683 /* 13256 */ "OpGroupBroadcast\000"
2684 /* 13273 */ "OpBitcast\000"
2685 /* 13283 */ "OpExtInst\000"
2686 /* 13293 */ "OpGroupNonUniformBroadcastFirst\000"
2687 /* 13325 */ "OpGroupNonUniformFMax\000"
2688 /* 13347 */ "OpGroupFMax\000"
2689 /* 13359 */ "OpAtomicSMax\000"
2690 /* 13372 */ "OpGroupNonUniformSMax\000"
2691 /* 13394 */ "OpGroupSMax\000"
2692 /* 13406 */ "OpAtomicUMax\000"
2693 /* 13419 */ "OpGroupNonUniformUMax\000"
2694 /* 13441 */ "OpGroupUMax\000"
2695 /* 13453 */ "OpDPdx\000"
2696 /* 13460 */ "OpEmitStreamVertex\000"
2697 /* 13479 */ "OpEmitVertex\000"
2698 /* 13492 */ "OpTypeMatrix\000"
2699 /* 13505 */ "OpVectorTimesMatrix\000"
2700 /* 13525 */ "OpMatrixTimesMatrix\000"
2701 /* 13545 */ "OpTypeRuntimeArray\000"
2702 /* 13564 */ "OpTypeArray\000"
2703 /* 13576 */ "OpDPdy\000"
2704 /* 13583 */ "OpGroupNonUniformAny\000"
2705 /* 13604 */ "OpAny\000"
2706 /* 13610 */ "OpGroupAny\000"
2707 /* 13621 */ "OpGroupAsyncCopy\000"
2708 /* 13638 */ "OpCopyMemory\000"
2709 /* 13651 */ "OpCapability\000"
2710};
2711#ifdef __GNUC__
2712#pragma GCC diagnostic pop
2713#endif
2714
2715extern const unsigned SPIRVInstrNameIndices[] = {
2716 2800U, 4660U, 5369U, 5018U, 2885U, 2866U, 2894U, 4496U,
2717 2593U, 2608U, 2519U, 2506U, 2635U, 6269U, 2346U, 7286U,
2718 2532U, 2796U, 2875U, 2104U, 8176U, 2842U, 2226U, 7190U,
2719 1931U, 2055U, 2092U, 5112U, 4484U, 7100U, 2038U, 5304U,
2720 2728U, 7089U, 2260U, 5292U, 5279U, 5430U, 6948U, 6971U,
2721 4416U, 4463U, 4436U, 2911U, 2337U, 5395U, 5066U, 2249U,
2722 8181U, 5921U, 5250U, 2394U, 7316U, 7346U, 4861U, 1844U,
2723 1555U, 4599U, 7534U, 7541U, 4626U, 4633U, 4640U, 4650U,
2724 1909U, 6130U, 6093U, 6181U, 7429U, 5965U, 4405U, 5953U,
2725 4394U, 2517U, 2798U, 8099U, 2356U, 2371U, 4501U, 6916U,
2726 6188U, 7227U, 6205U, 6016U, 1625U, 6252U, 7111U, 6157U,
2727 7259U, 2437U, 5406U, 2012U, 1599U, 1994U, 7149U, 7130U,
2728 4839U, 5455U, 5474U, 1745U, 1689U, 1719U, 1730U, 1670U,
2729 1700U, 2316U, 2300U, 6299U, 2649U, 2666U, 1860U, 1561U,
2730 1915U, 1876U, 6135U, 6099U, 8083U, 4987U, 8066U, 4970U,
2731 1811U, 1538U, 8001U, 4905U, 4755U, 4702U, 5174U, 5152U,
2732 1953U, 6869U, 2084U, 2745U, 1944U, 6935U, 7205U, 1577U,
2733 6347U, 7066U, 6374U, 7330U, 1617U, 6412U, 7436U, 7451U,
2734 7055U, 7043U, 7180U, 2720U, 7309U, 2622U, 7339U, 4380U,
2735 5914U, 5900U, 4373U, 5907U, 6150U, 4517U, 5229U, 5222U,
2736 5236U, 5243U, 6926U, 5058U, 2125U, 5042U, 2076U, 5050U,
2737 2117U, 5034U, 2068U, 5096U, 5088U, 2764U, 2756U, 6787U,
2738 6777U, 6767U, 6757U, 6807U, 6797U, 8127U, 8137U, 6817U,
2739 6830U, 8147U, 8157U, 6843U, 6856U, 1769U, 1517U, 4541U,
2740 59U, 1663U, 7513U, 4605U, 2462U, 7977U, 2822U, 5348U,
2741 35U, 9U, 2713U, 18U, 0U, 5323U, 5355U, 2586U,
2742 7301U, 1589U, 2804U, 2813U, 5204U, 5213U, 6890U, 6903U,
2743 6168U, 4876U, 6286U, 2446U, 4804U, 4814U, 2174U, 2189U,
2744 4691U, 4744U, 4776U, 4790U, 7548U, 7574U, 7560U, 2133U,
2745 2161U, 2146U, 2683U, 2698U, 1850U, 2856U, 4939U, 8035U,
2746 4963U, 8059U, 6175U, 1985U, 1975U, 5364U, 6995U, 2204U,
2747 5997U, 5977U, 7023U, 7002U, 6031U, 6062U, 6048U, 6329U,
2748 8210U, 2488U, 8203U, 2470U, 6220U, 5271U, 5196U, 2324U,
2749 4386U, 6235U, 5011U, 6242U, 4832U, 6227U, 5003U, 4824U,
2750 26U, 2788U, 2780U, 2772U, 7236U, 5944U, 7122U, 7167U,
2751 7269U, 5382U, 2213U, 1646U, 2415U, 2285U, 1797U, 1524U,
2752 4569U, 7520U, 4612U, 65U, 7244U, 5332U, 5494U, 5510U,
2753 8167U, 2233U, 2427U, 6962U, 5104U, 5145U, 5121U, 5133U,
2754 1776U, 4548U, 1752U, 4524U, 7984U, 4888U, 4723U, 4670U,
2755 1828U, 4583U, 1893U, 6115U, 6077U, 8018U, 4922U, 8042U,
2756 4946U, 8113U, 8120U, 2273U, 9929U, 11342U, 3842U, 3820U,
2757 3865U, 10973U, 13604U, 1044U, 674U, 856U, 598U, 189U,
2758 829U, 569U, 449U, 1376U, 1163U, 1197U, 1257U, 1137U,
2759 775U, 1403U, 321U, 106U, 217U, 1018U, 134U, 244U,
2760 373U, 1229U, 269U, 398U, 78U, 926U, 162U, 543U,
2761 803U, 1429U, 294U, 346U, 1284U, 973U, 900U, 1108U,
2762 744U, 646U, 1330U, 423U, 7376U, 10494U, 3891U, 3988U,
2763 4264U, 5689U, 8608U, 9586U, 10514U, 9569U, 7360U, 7413U,
2764 7397U, 11711U, 12725U, 8444U, 12841U, 12860U, 8217U, 8390U,
2765 11634U, 13359U, 11248U, 9942U, 13406U, 11295U, 12059U, 12984U,
2766 13145U, 12549U, 12568U, 10053U, 13273U, 6511U, 7751U, 3999U,
2767 6665U, 7885U, 6678U, 7898U, 10435U, 10567U, 9554U, 13651U,
2768 11541U, 9806U, 9888U, 12704U, 3347U, 12587U, 13162U, 10162U,
2769 3286U, 2574U, 9984U, 4155U, 2830U, 11012U, 11950U, 10258U,
2770 11903U, 3728U, 4281U, 2973U, 2951U, 6634U, 7466U, 3457U,
2771 3422U, 4125U, 7497U, 2546U, 2560U, 12188U, 3207U, 3382U,
2772 5705U, 3134U, 5536U, 5563U, 3787U, 3170U, 5634U, 10542U,
2773 13638U, 8579U, 12640U, 12953U, 4233U, 13453U, 10027U, 9738U,
2774 13576U, 10040U, 9749U, 10086U, 8312U, 10386U, 11450U, 13049U,
2775 13460U, 13479U, 10273U, 10288U, 10936U, 12971U, 9466U, 8294U,
2776 5861U, 13283U, 13213U, 11438U, 6481U, 7721U, 13180U, 6692U,
2777 7912U, 9443U, 6574U, 7825U, 10066U, 7773U, 10596U, 11120U,
2778 10703U, 11182U, 10785U, 10850U, 6604U, 7855U, 6427U, 7667U,
2779 10608U, 11138U, 10726U, 11197U, 10805U, 10865U, 1071U, 703U,
2780 1001U, 526U, 954U, 1357U, 883U, 1088U, 722U, 627U,
2781 1312U, 5527U, 11492U, 10990U, 8689U, 11984U, 3906U, 10485U,
2782 10012U, 9725U, 12204U, 12761U, 12223U, 10194U, 12419U, 12399U,
2783 10979U, 13610U, 13621U, 5592U, 5779U, 5819U, 13256U, 9823U,
2784 9906U, 8432U, 13347U, 11236U, 5749U, 8479U, 5764U, 5613U,
2785 5799U, 5840U, 10952U, 10637U, 13583U, 13105U, 12995U, 12606U,
2786 1455U, 1486U, 8620U, 11645U, 12099U, 13229U, 13293U, 12653U,
2787 8410U, 13325U, 11214U, 11038U, 8457U, 11060U, 13074U, 8648U,
2788 11672U, 12127U, 5662U, 13372U, 11261U, 9664U, 11512U, 11586U,
2789 12071U, 13419U, 11308U, 12312U, 12368U, 13394U, 11283U, 13441U,
2790 11330U, 12439U, 6744U, 7964U, 6503U, 7743U, 10587U, 6596U,
2791 7847U, 10838U, 6730U, 7950U, 6449U, 7689U, 9528U, 11821U,
2792 10444U, 11787U, 12518U, 12268U, 9427U, 11769U, 12248U, 10309U,
2793 8895U, 8360U, 9227U, 8971U, 9171U, 7616U, 8915U, 9291U,
2794 9035U, 9363U, 9107U, 11839U, 10457U, 11801U, 8372U, 9256U,
2795 9000U, 9196U, 8940U, 9324U, 9068U, 9392U, 9136U, 12813U,
2796 12039U, 10125U, 11398U, 11373U, 10114U, 10378U, 11082U, 10556U,
2797 12879U, 8325U, 11005U, 10914U, 11968U, 13129U, 11619U, 9769U,
2798 8403U, 8676U, 10622U, 13055U, 10882U, 11699U, 3933U, 9627U,
2799 4105U, 4186U, 13525U, 11749U, 12168U, 10097U, 10403U, 9712U,
2800 11920U, 10922U, 11882U, 8543U, 9705U, 10326U, 9760U, 11613U,
2801 13068U, 8521U, 12676U, 10508U, 3085U, 3508U, 11356U, 4074U,
2802 8275U, 10368U, 10827U, 10900U, 43U, 5734U, 9795U, 475U,
2803 12924U, 12287U, 12342U, 9776U, 9856U, 4334U, 12939U, 11503U,
2804 10212U, 2931U, 13191U, 6714U, 7934U, 13027U, 12478U, 11090U,
2805 10663U, 11158U, 10751U, 9450U, 8491U, 10076U, 6626U, 7877U,
2806 13034U, 12491U, 9501U, 7480U, 6648U, 4355U, 8703U, 8799U,
2807 8735U, 8831U, 8767U, 8863U, 8719U, 8815U, 8751U, 8847U,
2808 8783U, 8879U, 9610U, 12457U, 6533U, 7784U, 6457U, 7697U,
2809 6553U, 7804U, 12748U, 10351U, 9457U, 8561U, 11420U, 12798U,
2810 10138U, 3248U, 9964U, 11569U, 10239U, 9956U, 6489U, 7729U,
2811 6700U, 7920U, 6582U, 7833U, 6612U, 7863U, 6435U, 7675U,
2812 10426U, 3107U, 3952U, 3559U, 3756U, 3531U, 3060U, 3702U,
2813 3030U, 3671U, 2995U, 3635U, 3595U, 4022U, 3485U, 4049U,
2814 4207U, 10476U, 10000U, 7586U, 13564U, 11027U, 5873U, 7641U,
2815 12894U, 12912U, 12537U, 12004U, 11477U, 9516U, 12788U, 13492U,
2816 11863U, 10226U, 9845U, 9536U, 12025U, 10182U, 8344U, 13545U,
2817 9482U, 11936U, 12691U, 3320U, 12155U, 8597U, 13202U, 6722U,
2818 7942U, 13042U, 12505U, 11105U, 10683U, 11170U, 10768U, 6525U,
2819 7765U, 8506U, 10360U, 8531U, 9639U, 9653U, 4307U, 8230U,
2820 8253U, 9689U, 13505U, 11729U, 9876U, 500U,
2821};
2822
2823static inline void InitSPIRVMCInstrInfo(MCInstrInfo *II) {
2824 II->InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 838, nullptr, 0);
2825}
2826
2827
2828} // namespace llvm
2829
2830#endif // GET_INSTRINFO_MC_DESC
2831
2832#ifdef GET_INSTRINFO_HEADER
2833#undef GET_INSTRINFO_HEADER
2834
2835namespace llvm {
2836
2837struct SPIRVGenInstrInfo : public TargetInstrInfo {
2838 explicit SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2839 ~SPIRVGenInstrInfo() override = default;
2840};
2841
2842} // namespace llvm
2843
2844namespace llvm::SPIRV {
2845
2846
2847} // namespace llvm::SPIRV
2848
2849#endif // GET_INSTRINFO_HEADER
2850
2851#ifdef GET_INSTRINFO_HELPER_DECLS
2852#undef GET_INSTRINFO_HELPER_DECLS
2853
2854
2855#endif // GET_INSTRINFO_HELPER_DECLS
2856
2857#ifdef GET_INSTRINFO_HELPERS
2858#undef GET_INSTRINFO_HELPERS
2859
2860
2861#endif // GET_INSTRINFO_HELPERS
2862
2863#ifdef GET_INSTRINFO_CTOR_DTOR
2864#undef GET_INSTRINFO_CTOR_DTOR
2865
2866namespace llvm {
2867
2868extern const SPIRVInstrTable SPIRVDescs;
2869extern const unsigned SPIRVInstrNameIndices[];
2870extern const char SPIRVInstrNameData[];
2871SPIRVGenInstrInfo::SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2872 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2873 InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 838);
2874}
2875
2876} // namespace llvm
2877
2878#endif // GET_INSTRINFO_CTOR_DTOR
2879
2880#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2881#undef GET_INSTRINFO_MC_HELPER_DECLS
2882
2883namespace llvm {
2884
2885class MCInst;
2886class FeatureBitset;
2887
2888namespace SPIRV_MC {
2889
2890void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2891
2892} // namespace SPIRV_MC
2893
2894} // namespace llvm
2895
2896#endif // GET_INSTRINFO_MC_HELPER_DECLS
2897
2898#ifdef GET_INSTRINFO_MC_HELPERS
2899#undef GET_INSTRINFO_MC_HELPERS
2900
2901namespace llvm::SPIRV_MC {
2902
2903
2904} // namespace llvm::SPIRV_MC
2905
2906#endif // GET_INSTRINFO_MC_HELPERS
2907
2908#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2909 defined(GET_AVAILABLE_OPCODE_CHECKER)
2910#define GET_COMPUTE_FEATURES
2911#endif
2912#ifdef GET_COMPUTE_FEATURES
2913#undef GET_COMPUTE_FEATURES
2914
2915namespace llvm::SPIRV_MC {
2916
2917// Bits for subtarget features that participate in instruction matching.
2918enum SubtargetFeatureBits : uint8_t {
2919};
2920
2921inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2922 FeatureBitset Features;
2923 return Features;
2924}
2925
2926inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2927 enum : uint8_t {
2928 CEFBS_None,
2929 };
2930
2931 static constexpr FeatureBitset FeatureBitsets[] = {
2932 {}, // CEFBS_None
2933 };
2934 static constexpr uint8_t RequiredFeaturesRefs[] = {
2935 CEFBS_None, // PHI
2936 CEFBS_None, // INLINEASM
2937 CEFBS_None, // INLINEASM_BR
2938 CEFBS_None, // CFI_INSTRUCTION
2939 CEFBS_None, // EH_LABEL
2940 CEFBS_None, // GC_LABEL
2941 CEFBS_None, // ANNOTATION_LABEL
2942 CEFBS_None, // KILL
2943 CEFBS_None, // EXTRACT_SUBREG
2944 CEFBS_None, // INSERT_SUBREG
2945 CEFBS_None, // IMPLICIT_DEF
2946 CEFBS_None, // INIT_UNDEF
2947 CEFBS_None, // SUBREG_TO_REG
2948 CEFBS_None, // COPY_TO_REGCLASS
2949 CEFBS_None, // DBG_VALUE
2950 CEFBS_None, // DBG_VALUE_LIST
2951 CEFBS_None, // DBG_INSTR_REF
2952 CEFBS_None, // DBG_PHI
2953 CEFBS_None, // DBG_LABEL
2954 CEFBS_None, // REG_SEQUENCE
2955 CEFBS_None, // COPY
2956 CEFBS_None, // COPY_LANEMASK
2957 CEFBS_None, // BUNDLE
2958 CEFBS_None, // LIFETIME_START
2959 CEFBS_None, // LIFETIME_END
2960 CEFBS_None, // PSEUDO_PROBE
2961 CEFBS_None, // ARITH_FENCE
2962 CEFBS_None, // STACKMAP
2963 CEFBS_None, // FENTRY_CALL
2964 CEFBS_None, // PATCHPOINT
2965 CEFBS_None, // LOAD_STACK_GUARD
2966 CEFBS_None, // PREALLOCATED_SETUP
2967 CEFBS_None, // PREALLOCATED_ARG
2968 CEFBS_None, // STATEPOINT
2969 CEFBS_None, // LOCAL_ESCAPE
2970 CEFBS_None, // FAULTING_OP
2971 CEFBS_None, // PATCHABLE_OP
2972 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2973 CEFBS_None, // PATCHABLE_RET
2974 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2975 CEFBS_None, // PATCHABLE_TAIL_CALL
2976 CEFBS_None, // PATCHABLE_EVENT_CALL
2977 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2978 CEFBS_None, // ICALL_BRANCH_FUNNEL
2979 CEFBS_None, // FAKE_USE
2980 CEFBS_None, // MEMBARRIER
2981 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2982 CEFBS_None, // RELOC_NONE
2983 CEFBS_None, // CONVERGENCECTRL_ENTRY
2984 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2985 CEFBS_None, // CONVERGENCECTRL_LOOP
2986 CEFBS_None, // CONVERGENCECTRL_GLUE
2987 CEFBS_None, // G_ASSERT_SEXT
2988 CEFBS_None, // G_ASSERT_ZEXT
2989 CEFBS_None, // G_ASSERT_ALIGN
2990 CEFBS_None, // G_ADD
2991 CEFBS_None, // G_SUB
2992 CEFBS_None, // G_MUL
2993 CEFBS_None, // G_SDIV
2994 CEFBS_None, // G_UDIV
2995 CEFBS_None, // G_SREM
2996 CEFBS_None, // G_UREM
2997 CEFBS_None, // G_SDIVREM
2998 CEFBS_None, // G_UDIVREM
2999 CEFBS_None, // G_AND
3000 CEFBS_None, // G_OR
3001 CEFBS_None, // G_XOR
3002 CEFBS_None, // G_ABDS
3003 CEFBS_None, // G_ABDU
3004 CEFBS_None, // G_UAVGFLOOR
3005 CEFBS_None, // G_UAVGCEIL
3006 CEFBS_None, // G_SAVGFLOOR
3007 CEFBS_None, // G_SAVGCEIL
3008 CEFBS_None, // G_IMPLICIT_DEF
3009 CEFBS_None, // G_PHI
3010 CEFBS_None, // G_FRAME_INDEX
3011 CEFBS_None, // G_GLOBAL_VALUE
3012 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3013 CEFBS_None, // G_CONSTANT_POOL
3014 CEFBS_None, // G_EXTRACT
3015 CEFBS_None, // G_UNMERGE_VALUES
3016 CEFBS_None, // G_INSERT
3017 CEFBS_None, // G_MERGE_VALUES
3018 CEFBS_None, // G_BUILD_VECTOR
3019 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3020 CEFBS_None, // G_CONCAT_VECTORS
3021 CEFBS_None, // G_PTRTOINT
3022 CEFBS_None, // G_INTTOPTR
3023 CEFBS_None, // G_BITCAST
3024 CEFBS_None, // G_FREEZE
3025 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3026 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3027 CEFBS_None, // G_INTRINSIC_TRUNC
3028 CEFBS_None, // G_INTRINSIC_ROUND
3029 CEFBS_None, // G_INTRINSIC_LRINT
3030 CEFBS_None, // G_INTRINSIC_LLRINT
3031 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3032 CEFBS_None, // G_READCYCLECOUNTER
3033 CEFBS_None, // G_READSTEADYCOUNTER
3034 CEFBS_None, // G_LOAD
3035 CEFBS_None, // G_SEXTLOAD
3036 CEFBS_None, // G_ZEXTLOAD
3037 CEFBS_None, // G_INDEXED_LOAD
3038 CEFBS_None, // G_INDEXED_SEXTLOAD
3039 CEFBS_None, // G_INDEXED_ZEXTLOAD
3040 CEFBS_None, // G_STORE
3041 CEFBS_None, // G_INDEXED_STORE
3042 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3043 CEFBS_None, // G_ATOMIC_CMPXCHG
3044 CEFBS_None, // G_ATOMICRMW_XCHG
3045 CEFBS_None, // G_ATOMICRMW_ADD
3046 CEFBS_None, // G_ATOMICRMW_SUB
3047 CEFBS_None, // G_ATOMICRMW_AND
3048 CEFBS_None, // G_ATOMICRMW_NAND
3049 CEFBS_None, // G_ATOMICRMW_OR
3050 CEFBS_None, // G_ATOMICRMW_XOR
3051 CEFBS_None, // G_ATOMICRMW_MAX
3052 CEFBS_None, // G_ATOMICRMW_MIN
3053 CEFBS_None, // G_ATOMICRMW_UMAX
3054 CEFBS_None, // G_ATOMICRMW_UMIN
3055 CEFBS_None, // G_ATOMICRMW_FADD
3056 CEFBS_None, // G_ATOMICRMW_FSUB
3057 CEFBS_None, // G_ATOMICRMW_FMAX
3058 CEFBS_None, // G_ATOMICRMW_FMIN
3059 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3060 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3061 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3062 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3063 CEFBS_None, // G_ATOMICRMW_USUB_COND
3064 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3065 CEFBS_None, // G_FENCE
3066 CEFBS_None, // G_PREFETCH
3067 CEFBS_None, // G_BRCOND
3068 CEFBS_None, // G_BRINDIRECT
3069 CEFBS_None, // G_INVOKE_REGION_START
3070 CEFBS_None, // G_INTRINSIC
3071 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3072 CEFBS_None, // G_INTRINSIC_CONVERGENT
3073 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3074 CEFBS_None, // G_ANYEXT
3075 CEFBS_None, // G_TRUNC
3076 CEFBS_None, // G_TRUNC_SSAT_S
3077 CEFBS_None, // G_TRUNC_SSAT_U
3078 CEFBS_None, // G_TRUNC_USAT_U
3079 CEFBS_None, // G_CONSTANT
3080 CEFBS_None, // G_FCONSTANT
3081 CEFBS_None, // G_VASTART
3082 CEFBS_None, // G_VAARG
3083 CEFBS_None, // G_SEXT
3084 CEFBS_None, // G_SEXT_INREG
3085 CEFBS_None, // G_ZEXT
3086 CEFBS_None, // G_SHL
3087 CEFBS_None, // G_LSHR
3088 CEFBS_None, // G_ASHR
3089 CEFBS_None, // G_FSHL
3090 CEFBS_None, // G_FSHR
3091 CEFBS_None, // G_ROTR
3092 CEFBS_None, // G_ROTL
3093 CEFBS_None, // G_ICMP
3094 CEFBS_None, // G_FCMP
3095 CEFBS_None, // G_SCMP
3096 CEFBS_None, // G_UCMP
3097 CEFBS_None, // G_SELECT
3098 CEFBS_None, // G_UADDO
3099 CEFBS_None, // G_UADDE
3100 CEFBS_None, // G_USUBO
3101 CEFBS_None, // G_USUBE
3102 CEFBS_None, // G_SADDO
3103 CEFBS_None, // G_SADDE
3104 CEFBS_None, // G_SSUBO
3105 CEFBS_None, // G_SSUBE
3106 CEFBS_None, // G_UMULO
3107 CEFBS_None, // G_SMULO
3108 CEFBS_None, // G_UMULH
3109 CEFBS_None, // G_SMULH
3110 CEFBS_None, // G_UADDSAT
3111 CEFBS_None, // G_SADDSAT
3112 CEFBS_None, // G_USUBSAT
3113 CEFBS_None, // G_SSUBSAT
3114 CEFBS_None, // G_USHLSAT
3115 CEFBS_None, // G_SSHLSAT
3116 CEFBS_None, // G_SMULFIX
3117 CEFBS_None, // G_UMULFIX
3118 CEFBS_None, // G_SMULFIXSAT
3119 CEFBS_None, // G_UMULFIXSAT
3120 CEFBS_None, // G_SDIVFIX
3121 CEFBS_None, // G_UDIVFIX
3122 CEFBS_None, // G_SDIVFIXSAT
3123 CEFBS_None, // G_UDIVFIXSAT
3124 CEFBS_None, // G_FADD
3125 CEFBS_None, // G_FSUB
3126 CEFBS_None, // G_FMUL
3127 CEFBS_None, // G_FMA
3128 CEFBS_None, // G_FMAD
3129 CEFBS_None, // G_FDIV
3130 CEFBS_None, // G_FREM
3131 CEFBS_None, // G_FMODF
3132 CEFBS_None, // G_FPOW
3133 CEFBS_None, // G_FPOWI
3134 CEFBS_None, // G_FEXP
3135 CEFBS_None, // G_FEXP2
3136 CEFBS_None, // G_FEXP10
3137 CEFBS_None, // G_FLOG
3138 CEFBS_None, // G_FLOG2
3139 CEFBS_None, // G_FLOG10
3140 CEFBS_None, // G_FLDEXP
3141 CEFBS_None, // G_FFREXP
3142 CEFBS_None, // G_FNEG
3143 CEFBS_None, // G_FPEXT
3144 CEFBS_None, // G_FPTRUNC
3145 CEFBS_None, // G_FPTOSI
3146 CEFBS_None, // G_FPTOUI
3147 CEFBS_None, // G_SITOFP
3148 CEFBS_None, // G_UITOFP
3149 CEFBS_None, // G_FPTOSI_SAT
3150 CEFBS_None, // G_FPTOUI_SAT
3151 CEFBS_None, // G_FABS
3152 CEFBS_None, // G_FCOPYSIGN
3153 CEFBS_None, // G_IS_FPCLASS
3154 CEFBS_None, // G_FCANONICALIZE
3155 CEFBS_None, // G_FMINNUM
3156 CEFBS_None, // G_FMAXNUM
3157 CEFBS_None, // G_FMINNUM_IEEE
3158 CEFBS_None, // G_FMAXNUM_IEEE
3159 CEFBS_None, // G_FMINIMUM
3160 CEFBS_None, // G_FMAXIMUM
3161 CEFBS_None, // G_FMINIMUMNUM
3162 CEFBS_None, // G_FMAXIMUMNUM
3163 CEFBS_None, // G_GET_FPENV
3164 CEFBS_None, // G_SET_FPENV
3165 CEFBS_None, // G_RESET_FPENV
3166 CEFBS_None, // G_GET_FPMODE
3167 CEFBS_None, // G_SET_FPMODE
3168 CEFBS_None, // G_RESET_FPMODE
3169 CEFBS_None, // G_GET_ROUNDING
3170 CEFBS_None, // G_SET_ROUNDING
3171 CEFBS_None, // G_PTR_ADD
3172 CEFBS_None, // G_PTRMASK
3173 CEFBS_None, // G_SMIN
3174 CEFBS_None, // G_SMAX
3175 CEFBS_None, // G_UMIN
3176 CEFBS_None, // G_UMAX
3177 CEFBS_None, // G_ABS
3178 CEFBS_None, // G_LROUND
3179 CEFBS_None, // G_LLROUND
3180 CEFBS_None, // G_BR
3181 CEFBS_None, // G_BRJT
3182 CEFBS_None, // G_VSCALE
3183 CEFBS_None, // G_INSERT_SUBVECTOR
3184 CEFBS_None, // G_EXTRACT_SUBVECTOR
3185 CEFBS_None, // G_INSERT_VECTOR_ELT
3186 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3187 CEFBS_None, // G_SHUFFLE_VECTOR
3188 CEFBS_None, // G_SPLAT_VECTOR
3189 CEFBS_None, // G_STEP_VECTOR
3190 CEFBS_None, // G_VECTOR_COMPRESS
3191 CEFBS_None, // G_CTTZ
3192 CEFBS_None, // G_CTTZ_ZERO_UNDEF
3193 CEFBS_None, // G_CTLZ
3194 CEFBS_None, // G_CTLZ_ZERO_UNDEF
3195 CEFBS_None, // G_CTLS
3196 CEFBS_None, // G_CTPOP
3197 CEFBS_None, // G_BSWAP
3198 CEFBS_None, // G_BITREVERSE
3199 CEFBS_None, // G_FCEIL
3200 CEFBS_None, // G_FCOS
3201 CEFBS_None, // G_FSIN
3202 CEFBS_None, // G_FSINCOS
3203 CEFBS_None, // G_FTAN
3204 CEFBS_None, // G_FACOS
3205 CEFBS_None, // G_FASIN
3206 CEFBS_None, // G_FATAN
3207 CEFBS_None, // G_FATAN2
3208 CEFBS_None, // G_FCOSH
3209 CEFBS_None, // G_FSINH
3210 CEFBS_None, // G_FTANH
3211 CEFBS_None, // G_FSQRT
3212 CEFBS_None, // G_FFLOOR
3213 CEFBS_None, // G_FRINT
3214 CEFBS_None, // G_FNEARBYINT
3215 CEFBS_None, // G_ADDRSPACE_CAST
3216 CEFBS_None, // G_BLOCK_ADDR
3217 CEFBS_None, // G_JUMP_TABLE
3218 CEFBS_None, // G_DYN_STACKALLOC
3219 CEFBS_None, // G_STACKSAVE
3220 CEFBS_None, // G_STACKRESTORE
3221 CEFBS_None, // G_STRICT_FADD
3222 CEFBS_None, // G_STRICT_FSUB
3223 CEFBS_None, // G_STRICT_FMUL
3224 CEFBS_None, // G_STRICT_FDIV
3225 CEFBS_None, // G_STRICT_FREM
3226 CEFBS_None, // G_STRICT_FMA
3227 CEFBS_None, // G_STRICT_FSQRT
3228 CEFBS_None, // G_STRICT_FLDEXP
3229 CEFBS_None, // G_READ_REGISTER
3230 CEFBS_None, // G_WRITE_REGISTER
3231 CEFBS_None, // G_MEMCPY
3232 CEFBS_None, // G_MEMCPY_INLINE
3233 CEFBS_None, // G_MEMMOVE
3234 CEFBS_None, // G_MEMSET
3235 CEFBS_None, // G_BZERO
3236 CEFBS_None, // G_TRAP
3237 CEFBS_None, // G_DEBUGTRAP
3238 CEFBS_None, // G_UBSANTRAP
3239 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3240 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3241 CEFBS_None, // G_VECREDUCE_FADD
3242 CEFBS_None, // G_VECREDUCE_FMUL
3243 CEFBS_None, // G_VECREDUCE_FMAX
3244 CEFBS_None, // G_VECREDUCE_FMIN
3245 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3246 CEFBS_None, // G_VECREDUCE_FMINIMUM
3247 CEFBS_None, // G_VECREDUCE_ADD
3248 CEFBS_None, // G_VECREDUCE_MUL
3249 CEFBS_None, // G_VECREDUCE_AND
3250 CEFBS_None, // G_VECREDUCE_OR
3251 CEFBS_None, // G_VECREDUCE_XOR
3252 CEFBS_None, // G_VECREDUCE_SMAX
3253 CEFBS_None, // G_VECREDUCE_SMIN
3254 CEFBS_None, // G_VECREDUCE_UMAX
3255 CEFBS_None, // G_VECREDUCE_UMIN
3256 CEFBS_None, // G_SBFX
3257 CEFBS_None, // G_UBFX
3258 CEFBS_None, // ASSIGN_TYPE
3259 CEFBS_None, // UNKNOWN_type
3260 CEFBS_None, // OpAccessChain
3261 CEFBS_None, // OpAliasDomainDeclINTEL
3262 CEFBS_None, // OpAliasScopeDeclINTEL
3263 CEFBS_None, // OpAliasScopeListDeclINTEL
3264 CEFBS_None, // OpAll
3265 CEFBS_None, // OpAny
3266 CEFBS_None, // OpArbitraryFloatACosALTERA
3267 CEFBS_None, // OpArbitraryFloatACosPiALTERA
3268 CEFBS_None, // OpArbitraryFloatASinALTERA
3269 CEFBS_None, // OpArbitraryFloatASinPiALTERA
3270 CEFBS_None, // OpArbitraryFloatATan2ALTERA
3271 CEFBS_None, // OpArbitraryFloatATanALTERA
3272 CEFBS_None, // OpArbitraryFloatATanPiALTERA
3273 CEFBS_None, // OpArbitraryFloatAddALTERA
3274 CEFBS_None, // OpArbitraryFloatCastALTERA
3275 CEFBS_None, // OpArbitraryFloatCastFromIntALTERA
3276 CEFBS_None, // OpArbitraryFloatCastToIntALTERA
3277 CEFBS_None, // OpArbitraryFloatCbrtALTERA
3278 CEFBS_None, // OpArbitraryFloatCosALTERA
3279 CEFBS_None, // OpArbitraryFloatCosPiALTERA
3280 CEFBS_None, // OpArbitraryFloatDivALTERA
3281 CEFBS_None, // OpArbitraryFloatEQALTERA
3282 CEFBS_None, // OpArbitraryFloatExp10ALTERA
3283 CEFBS_None, // OpArbitraryFloatExp2ALTERA
3284 CEFBS_None, // OpArbitraryFloatExpALTERA
3285 CEFBS_None, // OpArbitraryFloatExpm1ALTERA
3286 CEFBS_None, // OpArbitraryFloatGEALTERA
3287 CEFBS_None, // OpArbitraryFloatGTALTERA
3288 CEFBS_None, // OpArbitraryFloatHypotALTERA
3289 CEFBS_None, // OpArbitraryFloatLEALTERA
3290 CEFBS_None, // OpArbitraryFloatLTALTERA
3291 CEFBS_None, // OpArbitraryFloatLog10ALTERA
3292 CEFBS_None, // OpArbitraryFloatLog1pALTERA
3293 CEFBS_None, // OpArbitraryFloatLog2ALTERA
3294 CEFBS_None, // OpArbitraryFloatLogALTERA
3295 CEFBS_None, // OpArbitraryFloatMulALTERA
3296 CEFBS_None, // OpArbitraryFloatPowALTERA
3297 CEFBS_None, // OpArbitraryFloatPowNALTERA
3298 CEFBS_None, // OpArbitraryFloatPowRALTERA
3299 CEFBS_None, // OpArbitraryFloatRSqrtALTERA
3300 CEFBS_None, // OpArbitraryFloatRecipALTERA
3301 CEFBS_None, // OpArbitraryFloatSinALTERA
3302 CEFBS_None, // OpArbitraryFloatSinCosALTERA
3303 CEFBS_None, // OpArbitraryFloatSinCosPiALTERA
3304 CEFBS_None, // OpArbitraryFloatSinPiALTERA
3305 CEFBS_None, // OpArbitraryFloatSqrtALTERA
3306 CEFBS_None, // OpArbitraryFloatSubALTERA
3307 CEFBS_None, // OpArithmeticFenceEXT
3308 CEFBS_None, // OpArrayLength
3309 CEFBS_None, // OpAsmCallINTEL
3310 CEFBS_None, // OpAsmINTEL
3311 CEFBS_None, // OpAsmTargetINTEL
3312 CEFBS_None, // OpAssumeTrueKHR
3313 CEFBS_None, // OpAtomicAnd
3314 CEFBS_None, // OpAtomicCompareExchange
3315 CEFBS_None, // OpAtomicCompareExchangeWeak
3316 CEFBS_None, // OpAtomicExchange
3317 CEFBS_None, // OpAtomicFAddEXT
3318 CEFBS_None, // OpAtomicFMaxEXT
3319 CEFBS_None, // OpAtomicFMinEXT
3320 CEFBS_None, // OpAtomicFlagClear
3321 CEFBS_None, // OpAtomicFlagTestAndSet
3322 CEFBS_None, // OpAtomicIAdd
3323 CEFBS_None, // OpAtomicIDecrement
3324 CEFBS_None, // OpAtomicIIncrement
3325 CEFBS_None, // OpAtomicISub
3326 CEFBS_None, // OpAtomicLoad
3327 CEFBS_None, // OpAtomicOr
3328 CEFBS_None, // OpAtomicSMax
3329 CEFBS_None, // OpAtomicSMin
3330 CEFBS_None, // OpAtomicStore
3331 CEFBS_None, // OpAtomicUMax
3332 CEFBS_None, // OpAtomicUMin
3333 CEFBS_None, // OpAtomicXor
3334 CEFBS_None, // OpBitCount
3335 CEFBS_None, // OpBitFieldInsert
3336 CEFBS_None, // OpBitFieldSExtract
3337 CEFBS_None, // OpBitFieldUExtract
3338 CEFBS_None, // OpBitReverse
3339 CEFBS_None, // OpBitcast
3340 CEFBS_None, // OpBitwiseAndS
3341 CEFBS_None, // OpBitwiseAndV
3342 CEFBS_None, // OpBitwiseFunctionINTEL
3343 CEFBS_None, // OpBitwiseOrS
3344 CEFBS_None, // OpBitwiseOrV
3345 CEFBS_None, // OpBitwiseXorS
3346 CEFBS_None, // OpBitwiseXorV
3347 CEFBS_None, // OpBranch
3348 CEFBS_None, // OpBranchConditional
3349 CEFBS_None, // OpBuildNDRange
3350 CEFBS_None, // OpCapability
3351 CEFBS_None, // OpCaptureEventProfilingInfo
3352 CEFBS_None, // OpCommitReadPipe
3353 CEFBS_None, // OpCommitWritePipe
3354 CEFBS_None, // OpCompositeConstruct
3355 CEFBS_None, // OpCompositeConstructContinuedINTEL
3356 CEFBS_None, // OpCompositeExtract
3357 CEFBS_None, // OpCompositeInsert
3358 CEFBS_None, // OpConstantComposite
3359 CEFBS_None, // OpConstantCompositeContinuedINTEL
3360 CEFBS_None, // OpConstantF
3361 CEFBS_None, // OpConstantFalse
3362 CEFBS_None, // OpConstantFunctionPointerINTEL
3363 CEFBS_None, // OpConstantI
3364 CEFBS_None, // OpConstantNull
3365 CEFBS_None, // OpConstantSampler
3366 CEFBS_None, // OpConstantTrue
3367 CEFBS_None, // OpControlBarrier
3368 CEFBS_None, // OpControlBarrierArriveINTEL
3369 CEFBS_None, // OpControlBarrierWaitINTEL
3370 CEFBS_None, // OpConvertBF16ToFINTEL
3371 CEFBS_None, // OpConvertFToBF16INTEL
3372 CEFBS_None, // OpConvertFToS
3373 CEFBS_None, // OpConvertFToU
3374 CEFBS_None, // OpConvertHandleToImageINTEL
3375 CEFBS_None, // OpConvertHandleToSampledImageINTEL
3376 CEFBS_None, // OpConvertHandleToSamplerINTEL
3377 CEFBS_None, // OpConvertPtrToU
3378 CEFBS_None, // OpConvertSToF
3379 CEFBS_None, // OpConvertUToF
3380 CEFBS_None, // OpConvertUToPtr
3381 CEFBS_None, // OpCooperativeMatrixConstructCheckedINTEL
3382 CEFBS_None, // OpCooperativeMatrixGetElementCoordINTEL
3383 CEFBS_None, // OpCooperativeMatrixLengthKHR
3384 CEFBS_None, // OpCooperativeMatrixLoadCheckedINTEL
3385 CEFBS_None, // OpCooperativeMatrixLoadKHR
3386 CEFBS_None, // OpCooperativeMatrixMulAddKHR
3387 CEFBS_None, // OpCooperativeMatrixPrefetchINTEL
3388 CEFBS_None, // OpCooperativeMatrixStoreCheckedINTEL
3389 CEFBS_None, // OpCooperativeMatrixStoreKHR
3390 CEFBS_None, // OpCopyLogical
3391 CEFBS_None, // OpCopyMemory
3392 CEFBS_None, // OpCopyMemorySized
3393 CEFBS_None, // OpCopyObject
3394 CEFBS_None, // OpCreateUserEvent
3395 CEFBS_None, // OpCrossWorkgroupCastToPtrINTEL
3396 CEFBS_None, // OpDPdx
3397 CEFBS_None, // OpDPdxCoarse
3398 CEFBS_None, // OpDPdxFine
3399 CEFBS_None, // OpDPdy
3400 CEFBS_None, // OpDPdyCoarse
3401 CEFBS_None, // OpDPdyFine
3402 CEFBS_None, // OpDecorate
3403 CEFBS_None, // OpDecorateId
3404 CEFBS_None, // OpDecorateString
3405 CEFBS_None, // OpDemoteToHelperInvocation
3406 CEFBS_None, // OpDot
3407 CEFBS_None, // OpEmitStreamVertex
3408 CEFBS_None, // OpEmitVertex
3409 CEFBS_None, // OpEndPrimitive
3410 CEFBS_None, // OpEndStreamPrimitive
3411 CEFBS_None, // OpEnqueueKernel
3412 CEFBS_None, // OpEntryPoint
3413 CEFBS_None, // OpExecutionMode
3414 CEFBS_None, // OpExecutionModeId
3415 CEFBS_None, // OpExpectKHR
3416 CEFBS_None, // OpExtInst
3417 CEFBS_None, // OpExtInstImport
3418 CEFBS_None, // OpExtension
3419 CEFBS_None, // OpFAddS
3420 CEFBS_None, // OpFAddV
3421 CEFBS_None, // OpFConvert
3422 CEFBS_None, // OpFDivS
3423 CEFBS_None, // OpFDivV
3424 CEFBS_None, // OpFMod
3425 CEFBS_None, // OpFMulS
3426 CEFBS_None, // OpFMulV
3427 CEFBS_None, // OpFNegate
3428 CEFBS_None, // OpFNegateV
3429 CEFBS_None, // OpFOrdEqual
3430 CEFBS_None, // OpFOrdGreaterThan
3431 CEFBS_None, // OpFOrdGreaterThanEqual
3432 CEFBS_None, // OpFOrdLessThan
3433 CEFBS_None, // OpFOrdLessThanEqual
3434 CEFBS_None, // OpFOrdNotEqual
3435 CEFBS_None, // OpFRemS
3436 CEFBS_None, // OpFRemV
3437 CEFBS_None, // OpFSubS
3438 CEFBS_None, // OpFSubV
3439 CEFBS_None, // OpFUnordEqual
3440 CEFBS_None, // OpFUnordGreaterThan
3441 CEFBS_None, // OpFUnordGreaterThanEqual
3442 CEFBS_None, // OpFUnordLessThan
3443 CEFBS_None, // OpFUnordLessThanEqual
3444 CEFBS_None, // OpFUnordNotEqual
3445 CEFBS_None, // OpFixedCosALTERA
3446 CEFBS_None, // OpFixedCosPiALTERA
3447 CEFBS_None, // OpFixedExpALTERA
3448 CEFBS_None, // OpFixedLogALTERA
3449 CEFBS_None, // OpFixedRecipALTERA
3450 CEFBS_None, // OpFixedRsqrtALTERA
3451 CEFBS_None, // OpFixedSinALTERA
3452 CEFBS_None, // OpFixedSinCosALTERA
3453 CEFBS_None, // OpFixedSinCosPiALTERA
3454 CEFBS_None, // OpFixedSinPiALTERA
3455 CEFBS_None, // OpFixedSqrtALTERA
3456 CEFBS_None, // OpFmaKHR
3457 CEFBS_None, // OpFunction
3458 CEFBS_None, // OpFunctionCall
3459 CEFBS_None, // OpFunctionEnd
3460 CEFBS_None, // OpFunctionParameter
3461 CEFBS_None, // OpFunctionPointerCallINTEL
3462 CEFBS_None, // OpFwidth
3463 CEFBS_None, // OpFwidthCoarse
3464 CEFBS_None, // OpFwidthFine
3465 CEFBS_None, // OpGenericCastToPtr
3466 CEFBS_None, // OpGenericCastToPtrExplicit
3467 CEFBS_None, // OpGenericPtrMemSemantics
3468 CEFBS_None, // OpGetDefaultQueue
3469 CEFBS_None, // OpGetMaxPipePackets
3470 CEFBS_None, // OpGetNumPipePackets
3471 CEFBS_None, // OpGroupAll
3472 CEFBS_None, // OpGroupAny
3473 CEFBS_None, // OpGroupAsyncCopy
3474 CEFBS_None, // OpGroupBitwiseAndKHR
3475 CEFBS_None, // OpGroupBitwiseOrKHR
3476 CEFBS_None, // OpGroupBitwiseXorKHR
3477 CEFBS_None, // OpGroupBroadcast
3478 CEFBS_None, // OpGroupCommitReadPipe
3479 CEFBS_None, // OpGroupCommitWritePipe
3480 CEFBS_None, // OpGroupFAdd
3481 CEFBS_None, // OpGroupFMax
3482 CEFBS_None, // OpGroupFMin
3483 CEFBS_None, // OpGroupFMulKHR
3484 CEFBS_None, // OpGroupIAdd
3485 CEFBS_None, // OpGroupIMulKHR
3486 CEFBS_None, // OpGroupLogicalAndKHR
3487 CEFBS_None, // OpGroupLogicalOrKHR
3488 CEFBS_None, // OpGroupLogicalXorKHR
3489 CEFBS_None, // OpGroupNonUniformAll
3490 CEFBS_None, // OpGroupNonUniformAllEqual
3491 CEFBS_None, // OpGroupNonUniformAny
3492 CEFBS_None, // OpGroupNonUniformBallot
3493 CEFBS_None, // OpGroupNonUniformBallotBitCount
3494 CEFBS_None, // OpGroupNonUniformBallotBitExtract
3495 CEFBS_None, // OpGroupNonUniformBallotFindLSB
3496 CEFBS_None, // OpGroupNonUniformBallotFindMSB
3497 CEFBS_None, // OpGroupNonUniformBitwiseAnd
3498 CEFBS_None, // OpGroupNonUniformBitwiseOr
3499 CEFBS_None, // OpGroupNonUniformBitwiseXor
3500 CEFBS_None, // OpGroupNonUniformBroadcast
3501 CEFBS_None, // OpGroupNonUniformBroadcastFirst
3502 CEFBS_None, // OpGroupNonUniformElect
3503 CEFBS_None, // OpGroupNonUniformFAdd
3504 CEFBS_None, // OpGroupNonUniformFMax
3505 CEFBS_None, // OpGroupNonUniformFMin
3506 CEFBS_None, // OpGroupNonUniformFMul
3507 CEFBS_None, // OpGroupNonUniformIAdd
3508 CEFBS_None, // OpGroupNonUniformIMul
3509 CEFBS_None, // OpGroupNonUniformInverseBallot
3510 CEFBS_None, // OpGroupNonUniformLogicalAnd
3511 CEFBS_None, // OpGroupNonUniformLogicalOr
3512 CEFBS_None, // OpGroupNonUniformLogicalXor
3513 CEFBS_None, // OpGroupNonUniformRotateKHR
3514 CEFBS_None, // OpGroupNonUniformSMax
3515 CEFBS_None, // OpGroupNonUniformSMin
3516 CEFBS_None, // OpGroupNonUniformShuffle
3517 CEFBS_None, // OpGroupNonUniformShuffleDown
3518 CEFBS_None, // OpGroupNonUniformShuffleUp
3519 CEFBS_None, // OpGroupNonUniformShuffleXor
3520 CEFBS_None, // OpGroupNonUniformUMax
3521 CEFBS_None, // OpGroupNonUniformUMin
3522 CEFBS_None, // OpGroupReserveReadPipePackets
3523 CEFBS_None, // OpGroupReserveWritePipePackets
3524 CEFBS_None, // OpGroupSMax
3525 CEFBS_None, // OpGroupSMin
3526 CEFBS_None, // OpGroupUMax
3527 CEFBS_None, // OpGroupUMin
3528 CEFBS_None, // OpGroupWaitEvents
3529 CEFBS_None, // OpIAddCarryS
3530 CEFBS_None, // OpIAddCarryV
3531 CEFBS_None, // OpIAddS
3532 CEFBS_None, // OpIAddV
3533 CEFBS_None, // OpIEqual
3534 CEFBS_None, // OpIMulS
3535 CEFBS_None, // OpIMulV
3536 CEFBS_None, // OpINotEqual
3537 CEFBS_None, // OpISubBorrowS
3538 CEFBS_None, // OpISubBorrowV
3539 CEFBS_None, // OpISubS
3540 CEFBS_None, // OpISubV
3541 CEFBS_None, // OpImage
3542 CEFBS_None, // OpImageDrefGather
3543 CEFBS_None, // OpImageFetch
3544 CEFBS_None, // OpImageGather
3545 CEFBS_None, // OpImageQueryFormat
3546 CEFBS_None, // OpImageQueryLevels
3547 CEFBS_None, // OpImageQueryLod
3548 CEFBS_None, // OpImageQueryOrder
3549 CEFBS_None, // OpImageQuerySamples
3550 CEFBS_None, // OpImageQuerySize
3551 CEFBS_None, // OpImageQuerySizeLod
3552 CEFBS_None, // OpImageRead
3553 CEFBS_None, // OpImageSampleDrefExplicitLod
3554 CEFBS_None, // OpImageSampleDrefImplicitLod
3555 CEFBS_None, // OpImageSampleExplicitLod
3556 CEFBS_None, // OpImageSampleFootprintNV
3557 CEFBS_None, // OpImageSampleImplicitLod
3558 CEFBS_None, // OpImageSampleProjDrefExplicitLod
3559 CEFBS_None, // OpImageSampleProjDrefImplicitLod
3560 CEFBS_None, // OpImageSampleProjExplicitLod
3561 CEFBS_None, // OpImageSampleProjImplicitLod
3562 CEFBS_None, // OpImageSparseDrefGather
3563 CEFBS_None, // OpImageSparseFetch
3564 CEFBS_None, // OpImageSparseGather
3565 CEFBS_None, // OpImageSparseRead
3566 CEFBS_None, // OpImageSparseSampleDrefExplicitLod
3567 CEFBS_None, // OpImageSparseSampleDrefImplicitLod
3568 CEFBS_None, // OpImageSparseSampleExplicitLod
3569 CEFBS_None, // OpImageSparseSampleImplicitLod
3570 CEFBS_None, // OpImageSparseSampleProjDrefExplicitLod
3571 CEFBS_None, // OpImageSparseSampleProjDrefImplicitLod
3572 CEFBS_None, // OpImageSparseSampleProjExplicitLod
3573 CEFBS_None, // OpImageSparseSampleProjImplicitLod
3574 CEFBS_None, // OpImageSparseTexelsResident
3575 CEFBS_None, // OpImageTexelPointer
3576 CEFBS_None, // OpImageWrite
3577 CEFBS_None, // OpInBoundsAccessChain
3578 CEFBS_None, // OpInBoundsPtrAccessChain
3579 CEFBS_None, // OpIsFinite
3580 CEFBS_None, // OpIsInf
3581 CEFBS_None, // OpIsNan
3582 CEFBS_None, // OpIsNormal
3583 CEFBS_None, // OpIsValidEvent
3584 CEFBS_None, // OpIsValidReserveId
3585 CEFBS_None, // OpKill
3586 CEFBS_None, // OpLabel
3587 CEFBS_None, // OpLessOrGreater
3588 CEFBS_None, // OpLifetimeStart
3589 CEFBS_None, // OpLifetimeStop
3590 CEFBS_None, // OpLine
3591 CEFBS_None, // OpLoad
3592 CEFBS_None, // OpLogicalAnd
3593 CEFBS_None, // OpLogicalEqual
3594 CEFBS_None, // OpLogicalNot
3595 CEFBS_None, // OpLogicalNotEqual
3596 CEFBS_None, // OpLogicalOr
3597 CEFBS_None, // OpLoopControlINTEL
3598 CEFBS_None, // OpLoopMerge
3599 CEFBS_None, // OpMaskedGatherINTEL
3600 CEFBS_None, // OpMaskedScatterINTEL
3601 CEFBS_None, // OpMatrixTimesMatrix
3602 CEFBS_None, // OpMatrixTimesScalar
3603 CEFBS_None, // OpMatrixTimesVector
3604 CEFBS_None, // OpMemberDecorate
3605 CEFBS_None, // OpMemberDecorateString
3606 CEFBS_None, // OpMemberName
3607 CEFBS_None, // OpMemoryBarrier
3608 CEFBS_None, // OpMemoryModel
3609 CEFBS_None, // OpMemoryNamedBarrier
3610 CEFBS_None, // OpModuleProcessed
3611 CEFBS_None, // OpName
3612 CEFBS_None, // OpNamedBarrierInitialize
3613 CEFBS_None, // OpNoLine
3614 CEFBS_None, // OpNop
3615 CEFBS_None, // OpNot
3616 CEFBS_None, // OpOrdered
3617 CEFBS_None, // OpOuterProduct
3618 CEFBS_None, // OpPhi
3619 CEFBS_None, // OpPredicatedLoadINTEL
3620 CEFBS_None, // OpPredicatedStoreINTEL
3621 CEFBS_None, // OpPtrAccessChain
3622 CEFBS_None, // OpPtrCastToCrossWorkgroupINTEL
3623 CEFBS_None, // OpPtrCastToGeneric
3624 CEFBS_None, // OpPtrDiff
3625 CEFBS_None, // OpPtrEqual
3626 CEFBS_None, // OpPtrNotEqual
3627 CEFBS_None, // OpQuantizeToF16
3628 CEFBS_None, // OpReadClockKHR
3629 CEFBS_None, // OpReadPipe
3630 CEFBS_None, // OpReadPipeBlockingALTERA
3631 CEFBS_None, // OpReleaseEvent
3632 CEFBS_None, // OpReserveReadPipePackets
3633 CEFBS_None, // OpReserveWritePipePackets
3634 CEFBS_None, // OpReservedReadPipe
3635 CEFBS_None, // OpReservedWritePipe
3636 CEFBS_None, // OpRestoreMemoryINTEL
3637 CEFBS_None, // OpRetainEvent
3638 CEFBS_None, // OpReturn
3639 CEFBS_None, // OpReturnValue
3640 CEFBS_None, // OpRoundFToTF32INTEL
3641 CEFBS_None, // OpSConvert
3642 CEFBS_None, // OpSDivS
3643 CEFBS_None, // OpSDivV
3644 CEFBS_None, // OpSDot
3645 CEFBS_None, // OpSDotAccSat
3646 CEFBS_None, // OpSGreaterThan
3647 CEFBS_None, // OpSGreaterThanEqual
3648 CEFBS_None, // OpSLessThan
3649 CEFBS_None, // OpSLessThanEqual
3650 CEFBS_None, // OpSMod
3651 CEFBS_None, // OpSMulExtended
3652 CEFBS_None, // OpSNegate
3653 CEFBS_None, // OpSRemS
3654 CEFBS_None, // OpSRemV
3655 CEFBS_None, // OpSUDot
3656 CEFBS_None, // OpSUDotAccSat
3657 CEFBS_None, // OpSampledImage
3658 CEFBS_None, // OpSatConvertSToU
3659 CEFBS_None, // OpSatConvertUToS
3660 CEFBS_None, // OpSaveMemoryINTEL
3661 CEFBS_None, // OpSelectSFSCond
3662 CEFBS_None, // OpSelectSFVCond
3663 CEFBS_None, // OpSelectSISCond
3664 CEFBS_None, // OpSelectSIVCond
3665 CEFBS_None, // OpSelectSPSCond
3666 CEFBS_None, // OpSelectSPVCond
3667 CEFBS_None, // OpSelectVFSCond
3668 CEFBS_None, // OpSelectVFVCond
3669 CEFBS_None, // OpSelectVISCond
3670 CEFBS_None, // OpSelectVIVCond
3671 CEFBS_None, // OpSelectVPSCond
3672 CEFBS_None, // OpSelectVPVCond
3673 CEFBS_None, // OpSelectionMerge
3674 CEFBS_None, // OpSetUserEventStatus
3675 CEFBS_None, // OpShiftLeftLogicalS
3676 CEFBS_None, // OpShiftLeftLogicalV
3677 CEFBS_None, // OpShiftRightArithmeticS
3678 CEFBS_None, // OpShiftRightArithmeticV
3679 CEFBS_None, // OpShiftRightLogicalS
3680 CEFBS_None, // OpShiftRightLogicalV
3681 CEFBS_None, // OpSignBitSet
3682 CEFBS_None, // OpSizeOf
3683 CEFBS_None, // OpSource
3684 CEFBS_None, // OpSourceContinued
3685 CEFBS_None, // OpSourceExtension
3686 CEFBS_None, // OpSpecConstant
3687 CEFBS_None, // OpSpecConstantComposite
3688 CEFBS_None, // OpSpecConstantCompositeContinuedINTEL
3689 CEFBS_None, // OpSpecConstantFalse
3690 CEFBS_None, // OpSpecConstantOp
3691 CEFBS_None, // OpSpecConstantTrue
3692 CEFBS_None, // OpStore
3693 CEFBS_None, // OpStrictFAddS
3694 CEFBS_None, // OpStrictFAddV
3695 CEFBS_None, // OpStrictFDivS
3696 CEFBS_None, // OpStrictFDivV
3697 CEFBS_None, // OpStrictFMulS
3698 CEFBS_None, // OpStrictFMulV
3699 CEFBS_None, // OpStrictFRemS
3700 CEFBS_None, // OpStrictFRemV
3701 CEFBS_None, // OpStrictFSubS
3702 CEFBS_None, // OpStrictFSubV
3703 CEFBS_None, // OpString
3704 CEFBS_None, // OpSubgroup2DBlockLoadINTEL
3705 CEFBS_None, // OpSubgroup2DBlockLoadTransformINTEL
3706 CEFBS_None, // OpSubgroup2DBlockLoadTransposeINTEL
3707 CEFBS_None, // OpSubgroup2DBlockPrefetchINTEL
3708 CEFBS_None, // OpSubgroup2DBlockStoreINTEL
3709 CEFBS_None, // OpSubgroupBlockReadINTEL
3710 CEFBS_None, // OpSubgroupBlockWriteINTEL
3711 CEFBS_None, // OpSubgroupImageBlockReadINTEL
3712 CEFBS_None, // OpSubgroupImageBlockWriteINTEL
3713 CEFBS_None, // OpSubgroupImageMediaBlockReadINTEL
3714 CEFBS_None, // OpSubgroupImageMediaBlockWriteINTEL
3715 CEFBS_None, // OpSubgroupMatrixMultiplyAccumulateINTEL
3716 CEFBS_None, // OpSubgroupShuffleDownINTEL
3717 CEFBS_None, // OpSubgroupShuffleINTEL
3718 CEFBS_None, // OpSubgroupShuffleUpINTEL
3719 CEFBS_None, // OpSubgroupShuffleXorINTEL
3720 CEFBS_None, // OpSwitch
3721 CEFBS_None, // OpTranspose
3722 CEFBS_None, // OpTypeAccelerationStructureNV
3723 CEFBS_None, // OpTypeArray
3724 CEFBS_None, // OpTypeBool
3725 CEFBS_None, // OpTypeCooperativeMatrixKHR
3726 CEFBS_None, // OpTypeCooperativeMatrixNV
3727 CEFBS_None, // OpTypeDeviceEvent
3728 CEFBS_None, // OpTypeEvent
3729 CEFBS_None, // OpTypeFloat
3730 CEFBS_None, // OpTypeForwardPointer
3731 CEFBS_None, // OpTypeFunction
3732 CEFBS_None, // OpTypeImage
3733 CEFBS_None, // OpTypeInt
3734 CEFBS_None, // OpTypeMatrix
3735 CEFBS_None, // OpTypeNamedBarrier
3736 CEFBS_None, // OpTypeOpaque
3737 CEFBS_None, // OpTypePipe
3738 CEFBS_None, // OpTypePipeStorage
3739 CEFBS_None, // OpTypePointer
3740 CEFBS_None, // OpTypeQueue
3741 CEFBS_None, // OpTypeReserveId
3742 CEFBS_None, // OpTypeRuntimeArray
3743 CEFBS_None, // OpTypeSampledImage
3744 CEFBS_None, // OpTypeSampler
3745 CEFBS_None, // OpTypeStruct
3746 CEFBS_None, // OpTypeStructContinuedINTEL
3747 CEFBS_None, // OpTypeVector
3748 CEFBS_None, // OpTypeVoid
3749 CEFBS_None, // OpUConvert
3750 CEFBS_None, // OpUDivS
3751 CEFBS_None, // OpUDivV
3752 CEFBS_None, // OpUDot
3753 CEFBS_None, // OpUDotAccSat
3754 CEFBS_None, // OpUGreaterThan
3755 CEFBS_None, // OpUGreaterThanEqual
3756 CEFBS_None, // OpULessThan
3757 CEFBS_None, // OpULessThanEqual
3758 CEFBS_None, // OpUModS
3759 CEFBS_None, // OpUModV
3760 CEFBS_None, // OpUMulExtended
3761 CEFBS_None, // OpUndef
3762 CEFBS_None, // OpUnordered
3763 CEFBS_None, // OpUnreachable
3764 CEFBS_None, // OpVariable
3765 CEFBS_None, // OpVariableLengthArrayINTEL
3766 CEFBS_None, // OpVectorExtractDynamic
3767 CEFBS_None, // OpVectorInsertDynamic
3768 CEFBS_None, // OpVectorShuffle
3769 CEFBS_None, // OpVectorTimesMatrix
3770 CEFBS_None, // OpVectorTimesScalar
3771 CEFBS_None, // OpWritePipe
3772 CEFBS_None, // OpWritePipeBlockingALTERA
3773 };
3774
3775 assert(Opcode < 838);
3776 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3777}
3778
3779
3780} // namespace llvm::SPIRV_MC
3781
3782#endif // GET_COMPUTE_FEATURES
3783
3784#ifdef GET_AVAILABLE_OPCODE_CHECKER
3785#undef GET_AVAILABLE_OPCODE_CHECKER
3786
3787namespace llvm::SPIRV_MC {
3788
3789bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3790 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3791 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3792 FeatureBitset MissingFeatures =
3793 (AvailableFeatures & RequiredFeatures) ^
3794 RequiredFeatures;
3795 return !MissingFeatures.any();
3796}
3797
3798} // namespace llvm::SPIRV_MC
3799
3800#endif // GET_AVAILABLE_OPCODE_CHECKER
3801
3802#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3803#undef ENABLE_INSTR_PREDICATE_VERIFIER
3804
3805#include <sstream>
3806
3807namespace llvm::SPIRV_MC {
3808
3809#ifndef NDEBUG
3810static const char *SubtargetFeatureNames[] = {
3811 nullptr
3812};
3813
3814#endif // NDEBUG
3815
3816void verifyInstructionPredicates(
3817 unsigned Opcode, const FeatureBitset &Features) {
3818#ifndef NDEBUG
3819 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3820 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3821 FeatureBitset MissingFeatures =
3822 (AvailableFeatures & RequiredFeatures) ^
3823 RequiredFeatures;
3824 if (MissingFeatures.any()) {
3825 std::ostringstream Msg;
3826 Msg << "Attempting to emit " << &SPIRVInstrNameData[SPIRVInstrNameIndices[Opcode]]
3827 << " instruction but the ";
3828 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3829 if (MissingFeatures.test(i))
3830 Msg << SubtargetFeatureNames[i] << " ";
3831 Msg << "predicate(s) are not met";
3832 report_fatal_error(Msg.str().c_str());
3833 }
3834#endif // NDEBUG
3835}
3836
3837} // namespace llvm::SPIRV_MC
3838
3839#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3840
3841