1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SPIRV {
13
14 enum {
15 PHI = 0, // Target.td:1329
16 INLINEASM = 1, // Target.td:1335
17 INLINEASM_BR = 2, // Target.td:1341
18 CFI_INSTRUCTION = 3, // Target.td:1350
19 EH_LABEL = 4, // Target.td:1359
20 GC_LABEL = 5, // Target.td:1368
21 ANNOTATION_LABEL = 6, // Target.td:1377
22 KILL = 7, // Target.td:1385
23 EXTRACT_SUBREG = 8, // Target.td:1392
24 INSERT_SUBREG = 9, // Target.td:1398
25 IMPLICIT_DEF = 10, // Target.td:1405
26 INIT_UNDEF = 11, // Target.td:1414
27 SUBREG_TO_REG = 12, // Target.td:1421
28 COPY_TO_REGCLASS = 13, // Target.td:1427
29 DBG_VALUE = 14, // Target.td:1434
30 DBG_VALUE_LIST = 15, // Target.td:1441
31 DBG_INSTR_REF = 16, // Target.td:1448
32 DBG_PHI = 17, // Target.td:1455
33 DBG_LABEL = 18, // Target.td:1462
34 REG_SEQUENCE = 19, // Target.td:1469
35 COPY = 20, // Target.td:1476
36 COPY_LANEMASK = 21, // Target.td:1484
37 BUNDLE = 22, // Target.td:1491
38 LIFETIME_START = 23, // Target.td:1497
39 LIFETIME_END = 24, // Target.td:1504
40 PSEUDO_PROBE = 25, // Target.td:1511
41 ARITH_FENCE = 26, // Target.td:1518
42 STACKMAP = 27, // Target.td:1527
43 FENTRY_CALL = 28, // Target.td:1662
44 PATCHPOINT = 29, // Target.td:1535
45 LOAD_STACK_GUARD = 30, // Target.td:1553
46 PREALLOCATED_SETUP = 31, // Target.td:1561
47 PREALLOCATED_ARG = 32, // Target.td:1567
48 STATEPOINT = 33, // Target.td:1544
49 LOCAL_ESCAPE = 34, // Target.td:1573
50 FAULTING_OP = 35, // Target.td:1582
51 PATCHABLE_OP = 36, // Target.td:1602
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1610
53 PATCHABLE_RET = 38, // Target.td:1617
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1626
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1634
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1642
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1652
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1672
59 FAKE_USE = 44, // Target.td:1592
60 MEMBARRIER = 45, // Target.td:1678
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1686
62 RELOC_NONE = 47, // Target.td:1694
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1706
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1702
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1710
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1714
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1937
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1929
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1944
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1522
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1535
96 G_INSERT = 81, // GenericOpcodes.td:1544
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1554
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1574
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1584
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1591
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1951
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1491
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1492
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1493
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1494
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1495
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1496
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1497
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1498
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1481
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1482
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1483
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1484
149 G_FENCE = 134, // GenericOpcodes.td:1500
150 G_PREFETCH = 135, // GenericOpcodes.td:1507
151 G_BRCOND = 136, // GenericOpcodes.td:1647
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1656
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1679
154 G_INTRINSIC = 139, // GenericOpcodes.td:1599
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1606
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1615
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1623
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1637
265 G_BRJT = 250, // GenericOpcodes.td:1667
266 G_VSCALE = 251, // GenericOpcodes.td:1565
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1711
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1719
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1727
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1735
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1746
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1754
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1762
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1769
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1821
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1822
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1823
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1824
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1825
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1826
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1827
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1828
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1829
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1830
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1686
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1696
318 G_MEMCPY = 303, // GenericOpcodes.td:1836
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1844
320 G_MEMMOVE = 305, // GenericOpcodes.td:1852
321 G_MEMSET = 306, // GenericOpcodes.td:1860
322 G_BZERO = 307, // GenericOpcodes.td:1867
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1874
324 G_TRAP = 309, // GenericOpcodes.td:1884
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1891
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1897
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1785
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1791
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1797
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1798
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1800
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1801
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1802
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1803
335 G_VECREDUCE_FMAXIMUMNUM = 320, // GenericOpcodes.td:1804
336 G_VECREDUCE_FMINIMUMNUM = 321, // GenericOpcodes.td:1805
337 G_VECREDUCE_ADD = 322, // GenericOpcodes.td:1807
338 G_VECREDUCE_MUL = 323, // GenericOpcodes.td:1808
339 G_VECREDUCE_AND = 324, // GenericOpcodes.td:1809
340 G_VECREDUCE_OR = 325, // GenericOpcodes.td:1810
341 G_VECREDUCE_XOR = 326, // GenericOpcodes.td:1811
342 G_VECREDUCE_SMAX = 327, // GenericOpcodes.td:1812
343 G_VECREDUCE_SMIN = 328, // GenericOpcodes.td:1813
344 G_VECREDUCE_UMAX = 329, // GenericOpcodes.td:1814
345 G_VECREDUCE_UMIN = 330, // GenericOpcodes.td:1815
346 G_SBFX = 331, // GenericOpcodes.td:1909
347 G_UBFX = 332, // GenericOpcodes.td:1917
348 ASSIGN_TYPE = 333, // SPIRVInstrInfo.td:18
349 UNKNOWN_type = 334, // SPIRVInstrInfo.td:21
350 OpAbortKHR = 335, // SPIRVInstrInfo.td:679
351 OpAccessChain = 336, // SPIRVInstrInfo.td:274
352 OpAliasDomainDeclINTEL = 337, // SPIRVInstrInfo.td:1006
353 OpAliasScopeDeclINTEL = 338, // SPIRVInstrInfo.td:1008
354 OpAliasScopeListDeclINTEL = 339, // SPIRVInstrInfo.td:1010
355 OpAll = 340, // SPIRVInstrInfo.td:595
356 OpAny = 341, // SPIRVInstrInfo.td:593
357 OpArbitraryFloatACosALTERA = 342, // SPIRVInstrInfo.td:1097
358 OpArbitraryFloatACosPiALTERA = 343, // SPIRVInstrInfo.td:1099
359 OpArbitraryFloatASinALTERA = 344, // SPIRVInstrInfo.td:1093
360 OpArbitraryFloatASinPiALTERA = 345, // SPIRVInstrInfo.td:1095
361 OpArbitraryFloatATan2ALTERA = 346, // SPIRVInstrInfo.td:1105
362 OpArbitraryFloatATanALTERA = 347, // SPIRVInstrInfo.td:1101
363 OpArbitraryFloatATanPiALTERA = 348, // SPIRVInstrInfo.td:1103
364 OpArbitraryFloatAddALTERA = 349, // SPIRVInstrInfo.td:1082
365 OpArbitraryFloatCastALTERA = 350, // SPIRVInstrInfo.td:1113
366 OpArbitraryFloatCastFromIntALTERA = 351, // SPIRVInstrInfo.td:1115
367 OpArbitraryFloatCastToIntALTERA = 352, // SPIRVInstrInfo.td:1117
368 OpArbitraryFloatCbrtALTERA = 353, // SPIRVInstrInfo.td:1031
369 OpArbitraryFloatCosALTERA = 354, // SPIRVInstrInfo.td:1067
370 OpArbitraryFloatCosPiALTERA = 355, // SPIRVInstrInfo.td:1076
371 OpArbitraryFloatDivALTERA = 356, // SPIRVInstrInfo.td:1089
372 OpArbitraryFloatEQALTERA = 357, // SPIRVInstrInfo.td:1026
373 OpArbitraryFloatExp10ALTERA = 358, // SPIRVInstrInfo.td:1058
374 OpArbitraryFloatExp2ALTERA = 359, // SPIRVInstrInfo.td:1055
375 OpArbitraryFloatExpALTERA = 360, // SPIRVInstrInfo.td:1052
376 OpArbitraryFloatExpm1ALTERA = 361, // SPIRVInstrInfo.td:1061
377 OpArbitraryFloatGEALTERA = 362, // SPIRVInstrInfo.td:1020
378 OpArbitraryFloatGTALTERA = 363, // SPIRVInstrInfo.td:1018
379 OpArbitraryFloatHypotALTERA = 364, // SPIRVInstrInfo.td:1034
380 OpArbitraryFloatLEALTERA = 365, // SPIRVInstrInfo.td:1024
381 OpArbitraryFloatLTALTERA = 366, // SPIRVInstrInfo.td:1022
382 OpArbitraryFloatLog10ALTERA = 367, // SPIRVInstrInfo.td:1046
383 OpArbitraryFloatLog1pALTERA = 368, // SPIRVInstrInfo.td:1049
384 OpArbitraryFloatLog2ALTERA = 369, // SPIRVInstrInfo.td:1043
385 OpArbitraryFloatLogALTERA = 370, // SPIRVInstrInfo.td:1040
386 OpArbitraryFloatMulALTERA = 371, // SPIRVInstrInfo.td:1087
387 OpArbitraryFloatPowALTERA = 372, // SPIRVInstrInfo.td:1107
388 OpArbitraryFloatPowNALTERA = 373, // SPIRVInstrInfo.td:1111
389 OpArbitraryFloatPowRALTERA = 374, // SPIRVInstrInfo.td:1109
390 OpArbitraryFloatRSqrtALTERA = 375, // SPIRVInstrInfo.td:1091
391 OpArbitraryFloatRecipALTERA = 376, // SPIRVInstrInfo.td:1028
392 OpArbitraryFloatSinALTERA = 377, // SPIRVInstrInfo.td:1064
393 OpArbitraryFloatSinCosALTERA = 378, // SPIRVInstrInfo.td:1070
394 OpArbitraryFloatSinCosPiALTERA = 379, // SPIRVInstrInfo.td:1079
395 OpArbitraryFloatSinPiALTERA = 380, // SPIRVInstrInfo.td:1073
396 OpArbitraryFloatSqrtALTERA = 381, // SPIRVInstrInfo.td:1037
397 OpArbitraryFloatSubALTERA = 382, // SPIRVInstrInfo.td:1085
398 OpArithmeticFenceEXT = 383, // SPIRVInstrInfo.td:994
399 OpArrayLength = 384, // SPIRVInstrInfo.td:282
400 OpAsmCallINTEL = 385, // SPIRVInstrInfo.td:960
401 OpAsmINTEL = 386, // SPIRVInstrInfo.td:957
402 OpAsmTargetINTEL = 387, // SPIRVInstrInfo.td:956
403 OpAssumeTrueKHR = 388, // SPIRVInstrInfo.td:106
404 OpAtomicAnd = 389, // SPIRVInstrInfo.td:723
405 OpAtomicCompareExchange = 390, // SPIRVInstrInfo.td:703
406 OpAtomicCompareExchangeWeak = 391, // SPIRVInstrInfo.td:707
407 OpAtomicExchange = 392, // SPIRVInstrInfo.td:700
408 OpAtomicFAddEXT = 393, // SPIRVInstrInfo.td:727
409 OpAtomicFMaxEXT = 394, // SPIRVInstrInfo.td:729
410 OpAtomicFMinEXT = 395, // SPIRVInstrInfo.td:728
411 OpAtomicFlagClear = 396, // SPIRVInstrInfo.td:732
412 OpAtomicFlagTestAndSet = 397, // SPIRVInstrInfo.td:731
413 OpAtomicIAdd = 398, // SPIRVInstrInfo.td:715
414 OpAtomicIDecrement = 399, // SPIRVInstrInfo.td:713
415 OpAtomicIIncrement = 400, // SPIRVInstrInfo.td:712
416 OpAtomicISub = 401, // SPIRVInstrInfo.td:716
417 OpAtomicLoad = 402, // SPIRVInstrInfo.td:696
418 OpAtomicOr = 403, // SPIRVInstrInfo.td:724
419 OpAtomicSMax = 404, // SPIRVInstrInfo.td:720
420 OpAtomicSMin = 405, // SPIRVInstrInfo.td:718
421 OpAtomicStore = 406, // SPIRVInstrInfo.td:698
422 OpAtomicUMax = 407, // SPIRVInstrInfo.td:721
423 OpAtomicUMin = 408, // SPIRVInstrInfo.td:719
424 OpAtomicXor = 409, // SPIRVInstrInfo.td:725
425 OpBitCount = 410, // SPIRVInstrInfo.td:589
426 OpBitFieldInsert = 411, // SPIRVInstrInfo.td:579
427 OpBitFieldSExtract = 412, // SPIRVInstrInfo.td:582
428 OpBitFieldUExtract = 413, // SPIRVInstrInfo.td:585
429 OpBitReverse = 414, // SPIRVInstrInfo.td:588
430 OpBitcast = 415, // SPIRVInstrInfo.td:473
431 OpBitwiseAndS = 416, // SPIRVInstrInfo.td:48
432 OpBitwiseAndV = 417, // SPIRVInstrInfo.td:53
433 OpBitwiseFunctionINTEL = 418, // SPIRVInstrInfo.td:1014
434 OpBitwiseOrS = 419, // SPIRVInstrInfo.td:48
435 OpBitwiseOrV = 420, // SPIRVInstrInfo.td:53
436 OpBitwiseXorS = 421, // SPIRVInstrInfo.td:48
437 OpBitwiseXorV = 422, // SPIRVInstrInfo.td:53
438 OpBranch = 423, // SPIRVInstrInfo.td:669
439 OpBranchConditional = 424, // SPIRVInstrInfo.td:670
440 OpBuildNDRange = 425, // SPIRVInstrInfo.td:805
441 OpCapability = 426, // SPIRVInstrInfo.td:164
442 OpCaptureEventProfilingInfo = 427, // SPIRVInstrInfo.td:800
443 OpCommitReadPipe = 428, // SPIRVInstrInfo.td:822
444 OpCommitWritePipe = 429, // SPIRVInstrInfo.td:824
445 OpCompositeConstruct = 430, // SPIRVInstrInfo.td:494
446 OpCompositeConstructContinuedINTEL = 431, // SPIRVInstrInfo.td:496
447 OpCompositeExtract = 432, // SPIRVInstrInfo.td:498
448 OpCompositeInsert = 433, // SPIRVInstrInfo.td:500
449 OpConstantComposite = 434, // SPIRVInstrInfo.td:236
450 OpConstantCompositeContinuedINTEL = 435, // SPIRVInstrInfo.td:238
451 OpConstantF = 436, // SPIRVInstrInfo.td:224
452 OpConstantFalse = 437, // SPIRVInstrInfo.td:233
453 OpConstantFunctionPointerINTEL = 438, // SPIRVInstrInfo.td:904
454 OpConstantI = 439, // SPIRVInstrInfo.td:222
455 OpConstantNull = 440, // SPIRVInstrInfo.td:244
456 OpConstantSampler = 441, // SPIRVInstrInfo.td:241
457 OpConstantTrue = 442, // SPIRVInstrInfo.td:231
458 OpControlBarrier = 443, // SPIRVInstrInfo.td:744
459 OpControlBarrierArriveINTEL = 444, // SPIRVInstrInfo.td:753
460 OpControlBarrierWaitINTEL = 445, // SPIRVInstrInfo.td:755
461 OpConvertBF16ToFINTEL = 446, // SPIRVInstrInfo.td:481
462 OpConvertFToBF16INTEL = 447, // SPIRVInstrInfo.td:480
463 OpConvertFToS = 448, // SPIRVInstrInfo.td:453
464 OpConvertFToU = 449, // SPIRVInstrInfo.td:452
465 OpConvertHandleToImageINTEL = 450, // SPIRVInstrInfo.td:998
466 OpConvertHandleToSampledImageINTEL = 451, // SPIRVInstrInfo.td:1002
467 OpConvertHandleToSamplerINTEL = 452, // SPIRVInstrInfo.td:1000
468 OpConvertPtrToU = 453, // SPIRVInstrInfo.td:463
469 OpConvertSToF = 454, // SPIRVInstrInfo.td:454
470 OpConvertUToF = 455, // SPIRVInstrInfo.td:455
471 OpConvertUToPtr = 456, // SPIRVInstrInfo.td:468
472 OpCooperativeMatrixConstructCheckedINTEL = 457, // SPIRVInstrInfo.td:983
473 OpCooperativeMatrixGetElementCoordINTEL = 458, // SPIRVInstrInfo.td:986
474 OpCooperativeMatrixLengthKHR = 459, // SPIRVInstrInfo.td:973
475 OpCooperativeMatrixLoadCheckedINTEL = 460, // SPIRVInstrInfo.td:977
476 OpCooperativeMatrixLoadKHR = 461, // SPIRVInstrInfo.td:964
477 OpCooperativeMatrixMulAddKHR = 462, // SPIRVInstrInfo.td:970
478 OpCooperativeMatrixPrefetchINTEL = 463, // SPIRVInstrInfo.td:989
479 OpCooperativeMatrixStoreCheckedINTEL = 464, // SPIRVInstrInfo.td:980
480 OpCooperativeMatrixStoreKHR = 465, // SPIRVInstrInfo.td:967
481 OpCopyLogical = 466, // SPIRVInstrInfo.td:504
482 OpCopyMemory = 467, // SPIRVInstrInfo.td:270
483 OpCopyMemorySized = 468, // SPIRVInstrInfo.td:272
484 OpCopyObject = 469, // SPIRVInstrInfo.td:502
485 OpCreateUserEvent = 470, // SPIRVInstrInfo.td:794
486 OpCrossWorkgroupCastToPtrINTEL = 471, // SPIRVInstrInfo.td:477
487 OpDPdx = 472, // SPIRVInstrInfo.td:645
488 OpDPdxCoarse = 473, // SPIRVInstrInfo.td:653
489 OpDPdxFine = 474, // SPIRVInstrInfo.td:649
490 OpDPdy = 475, // SPIRVInstrInfo.td:646
491 OpDPdyCoarse = 476, // SPIRVInstrInfo.td:654
492 OpDPdyFine = 477, // SPIRVInstrInfo.td:650
493 OpDecorate = 478, // SPIRVInstrInfo.td:128
494 OpDecorateId = 479, // SPIRVInstrInfo.td:136
495 OpDecorateString = 480, // SPIRVInstrInfo.td:138
496 OpDemoteToHelperInvocation = 481, // SPIRVInstrInfo.td:684
497 OpDot = 482, // SPIRVInstrInfo.td:545
498 OpEmitStreamVertex = 483, // SPIRVInstrInfo.td:739
499 OpEmitVertex = 484, // SPIRVInstrInfo.td:737
500 OpEndPrimitive = 485, // SPIRVInstrInfo.td:738
501 OpEndStreamPrimitive = 486, // SPIRVInstrInfo.td:740
502 OpEnqueueKernel = 487, // SPIRVInstrInfo.td:789
503 OpEntryPoint = 488, // SPIRVInstrInfo.td:159
504 OpExecutionMode = 489, // SPIRVInstrInfo.td:162
505 OpExecutionModeId = 490, // SPIRVInstrInfo.td:165
506 OpExpectKHR = 491, // SPIRVInstrInfo.td:107
507 OpExtInst = 492, // SPIRVInstrInfo.td:153
508 OpExtInstImport = 493, // SPIRVInstrInfo.td:147
509 OpExtension = 494, // SPIRVInstrInfo.td:146
510 OpFAddS = 495, // SPIRVInstrInfo.td:46
511 OpFAddV = 496, // SPIRVInstrInfo.td:51
512 OpFConvert = 497, // SPIRVInstrInfo.td:459
513 OpFDivS = 498, // SPIRVInstrInfo.td:46
514 OpFDivV = 499, // SPIRVInstrInfo.td:51
515 OpFMod = 500, // SPIRVInstrInfo.td:536
516 OpFMulS = 501, // SPIRVInstrInfo.td:46
517 OpFMulV = 502, // SPIRVInstrInfo.td:51
518 OpFNegate = 503, // SPIRVInstrInfo.td:509
519 OpFNegateV = 504, // SPIRVInstrInfo.td:510
520 OpFOrdEqual = 505, // SPIRVInstrInfo.td:628
521 OpFOrdGreaterThan = 506, // SPIRVInstrInfo.td:635
522 OpFOrdGreaterThanEqual = 507, // SPIRVInstrInfo.td:640
523 OpFOrdLessThan = 508, // SPIRVInstrInfo.td:633
524 OpFOrdLessThanEqual = 509, // SPIRVInstrInfo.td:638
525 OpFOrdNotEqual = 510, // SPIRVInstrInfo.td:630
526 OpFRemS = 511, // SPIRVInstrInfo.td:46
527 OpFRemV = 512, // SPIRVInstrInfo.td:51
528 OpFSubS = 513, // SPIRVInstrInfo.td:46
529 OpFSubV = 514, // SPIRVInstrInfo.td:51
530 OpFUnordEqual = 515, // SPIRVInstrInfo.td:629
531 OpFUnordGreaterThan = 516, // SPIRVInstrInfo.td:636
532 OpFUnordGreaterThanEqual = 517, // SPIRVInstrInfo.td:641
533 OpFUnordLessThan = 518, // SPIRVInstrInfo.td:634
534 OpFUnordLessThanEqual = 519, // SPIRVInstrInfo.td:639
535 OpFUnordNotEqual = 520, // SPIRVInstrInfo.td:631
536 OpFixedCosALTERA = 521, // SPIRVInstrInfo.td:1158
537 OpFixedCosPiALTERA = 522, // SPIRVInstrInfo.td:1164
538 OpFixedExpALTERA = 523, // SPIRVInstrInfo.td:1170
539 OpFixedLogALTERA = 524, // SPIRVInstrInfo.td:1168
540 OpFixedRecipALTERA = 525, // SPIRVInstrInfo.td:1152
541 OpFixedRsqrtALTERA = 526, // SPIRVInstrInfo.td:1154
542 OpFixedSinALTERA = 527, // SPIRVInstrInfo.td:1156
543 OpFixedSinCosALTERA = 528, // SPIRVInstrInfo.td:1160
544 OpFixedSinCosPiALTERA = 529, // SPIRVInstrInfo.td:1166
545 OpFixedSinPiALTERA = 530, // SPIRVInstrInfo.td:1162
546 OpFixedSqrtALTERA = 531, // SPIRVInstrInfo.td:1150
547 OpFmaKHR = 532, // SPIRVInstrInfo.td:565
548 OpFreezeKHR = 533, // SPIRVInstrInfo.td:103
549 OpFunction = 534, // SPIRVInstrInfo.td:334
550 OpFunctionCall = 535, // SPIRVInstrInfo.td:342
551 OpFunctionEnd = 536, // SPIRVInstrInfo.td:339
552 OpFunctionParameter = 537, // SPIRVInstrInfo.td:337
553 OpFunctionPointerCallINTEL = 538, // SPIRVInstrInfo.td:909
554 OpFwidth = 539, // SPIRVInstrInfo.td:647
555 OpFwidthCoarse = 540, // SPIRVInstrInfo.td:655
556 OpFwidthFine = 541, // SPIRVInstrInfo.td:651
557 OpGenericCastToPtr = 542, // SPIRVInstrInfo.td:470
558 OpGenericCastToPtrExplicit = 543, // SPIRVInstrInfo.td:471
559 OpGenericPtrMemSemantics = 544, // SPIRVInstrInfo.td:284
560 OpGetDefaultQueue = 545, // SPIRVInstrInfo.td:803
561 OpGetMaxPipePackets = 546, // SPIRVInstrInfo.td:830
562 OpGetNumPipePackets = 547, // SPIRVInstrInfo.td:828
563 OpGroupAll = 548, // SPIRVInstrInfo.td:765
564 OpGroupAny = 549, // SPIRVInstrInfo.td:767
565 OpGroupAsyncCopy = 550, // SPIRVInstrInfo.td:760
566 OpGroupBitwiseAndKHR = 551, // SPIRVInstrInfo.td:942
567 OpGroupBitwiseOrKHR = 552, // SPIRVInstrInfo.td:944
568 OpGroupBitwiseXorKHR = 553, // SPIRVInstrInfo.td:946
569 OpGroupBroadcast = 554, // SPIRVInstrInfo.td:769
570 OpGroupCommitReadPipe = 555, // SPIRVInstrInfo.td:836
571 OpGroupCommitWritePipe = 556, // SPIRVInstrInfo.td:838
572 OpGroupFAdd = 557, // SPIRVInstrInfo.td:776
573 OpGroupFMax = 558, // SPIRVInstrInfo.td:780
574 OpGroupFMin = 559, // SPIRVInstrInfo.td:777
575 OpGroupFMulKHR = 560, // SPIRVInstrInfo.td:940
576 OpGroupIAdd = 561, // SPIRVInstrInfo.td:775
577 OpGroupIMulKHR = 562, // SPIRVInstrInfo.td:938
578 OpGroupLogicalAndKHR = 563, // SPIRVInstrInfo.td:948
579 OpGroupLogicalOrKHR = 564, // SPIRVInstrInfo.td:950
580 OpGroupLogicalXorKHR = 565, // SPIRVInstrInfo.td:952
581 OpGroupNonUniformAll = 566, // SPIRVInstrInfo.td:851
582 OpGroupNonUniformAllEqual = 567, // SPIRVInstrInfo.td:853
583 OpGroupNonUniformAny = 568, // SPIRVInstrInfo.td:852
584 OpGroupNonUniformBallot = 569, // SPIRVInstrInfo.td:856
585 OpGroupNonUniformBallotBitCount = 570, // SPIRVInstrInfo.td:859
586 OpGroupNonUniformBallotBitExtract = 571, // SPIRVInstrInfo.td:858
587 OpGroupNonUniformBallotFindLSB = 572, // SPIRVInstrInfo.td:863
588 OpGroupNonUniformBallotFindMSB = 573, // SPIRVInstrInfo.td:864
589 OpGroupNonUniformBitwiseAnd = 574, // SPIRVInstrInfo.td:883
590 OpGroupNonUniformBitwiseOr = 575, // SPIRVInstrInfo.td:884
591 OpGroupNonUniformBitwiseXor = 576, // SPIRVInstrInfo.td:885
592 OpGroupNonUniformBroadcast = 577, // SPIRVInstrInfo.td:854
593 OpGroupNonUniformBroadcastFirst = 578, // SPIRVInstrInfo.td:855
594 OpGroupNonUniformElect = 579, // SPIRVInstrInfo.td:843
595 OpGroupNonUniformFAdd = 580, // SPIRVInstrInfo.td:874
596 OpGroupNonUniformFMax = 581, // SPIRVInstrInfo.td:882
597 OpGroupNonUniformFMin = 582, // SPIRVInstrInfo.td:879
598 OpGroupNonUniformFMul = 583, // SPIRVInstrInfo.td:876
599 OpGroupNonUniformIAdd = 584, // SPIRVInstrInfo.td:873
600 OpGroupNonUniformIMul = 585, // SPIRVInstrInfo.td:875
601 OpGroupNonUniformInverseBallot = 586, // SPIRVInstrInfo.td:857
602 OpGroupNonUniformLogicalAnd = 587, // SPIRVInstrInfo.td:886
603 OpGroupNonUniformLogicalOr = 588, // SPIRVInstrInfo.td:887
604 OpGroupNonUniformLogicalXor = 589, // SPIRVInstrInfo.td:888
605 OpGroupNonUniformQuadSwap = 590, // SPIRVInstrInfo.td:889
606 OpGroupNonUniformRotateKHR = 591, // SPIRVInstrInfo.td:892
607 OpGroupNonUniformSMax = 592, // SPIRVInstrInfo.td:880
608 OpGroupNonUniformSMin = 593, // SPIRVInstrInfo.td:877
609 OpGroupNonUniformShuffle = 594, // SPIRVInstrInfo.td:865
610 OpGroupNonUniformShuffleDown = 595, // SPIRVInstrInfo.td:868
611 OpGroupNonUniformShuffleUp = 596, // SPIRVInstrInfo.td:867
612 OpGroupNonUniformShuffleXor = 597, // SPIRVInstrInfo.td:866
613 OpGroupNonUniformUMax = 598, // SPIRVInstrInfo.td:881
614 OpGroupNonUniformUMin = 599, // SPIRVInstrInfo.td:878
615 OpGroupReserveReadPipePackets = 600, // SPIRVInstrInfo.td:832
616 OpGroupReserveWritePipePackets = 601, // SPIRVInstrInfo.td:834
617 OpGroupSMax = 602, // SPIRVInstrInfo.td:782
618 OpGroupSMin = 603, // SPIRVInstrInfo.td:779
619 OpGroupUMax = 604, // SPIRVInstrInfo.td:781
620 OpGroupUMin = 605, // SPIRVInstrInfo.td:778
621 OpGroupWaitEvents = 606, // SPIRVInstrInfo.td:763
622 OpIAddCarryS = 607, // SPIRVInstrInfo.td:48
623 OpIAddCarryV = 608, // SPIRVInstrInfo.td:53
624 OpIAddS = 609, // SPIRVInstrInfo.td:48
625 OpIAddV = 610, // SPIRVInstrInfo.td:53
626 OpIEqual = 611, // SPIRVInstrInfo.td:616
627 OpIMulS = 612, // SPIRVInstrInfo.td:48
628 OpIMulV = 613, // SPIRVInstrInfo.td:53
629 OpINotEqual = 614, // SPIRVInstrInfo.td:617
630 OpISubBorrowS = 615, // SPIRVInstrInfo.td:48
631 OpISubBorrowV = 616, // SPIRVInstrInfo.td:53
632 OpISubS = 617, // SPIRVInstrInfo.td:48
633 OpISubV = 618, // SPIRVInstrInfo.td:53
634 OpImage = 619, // SPIRVInstrInfo.td:393
635 OpImageDrefGather = 620, // SPIRVInstrInfo.td:383
636 OpImageFetch = 621, // SPIRVInstrInfo.td:377
637 OpImageGather = 622, // SPIRVInstrInfo.td:380
638 OpImageQueryFormat = 623, // SPIRVInstrInfo.td:394
639 OpImageQueryLevels = 624, // SPIRVInstrInfo.td:399
640 OpImageQueryLod = 625, // SPIRVInstrInfo.td:398
641 OpImageQueryOrder = 626, // SPIRVInstrInfo.td:395
642 OpImageQuerySamples = 627, // SPIRVInstrInfo.td:400
643 OpImageQuerySize = 628, // SPIRVInstrInfo.td:397
644 OpImageQuerySizeLod = 629, // SPIRVInstrInfo.td:396
645 OpImageRead = 630, // SPIRVInstrInfo.td:387
646 OpImageSampleDrefExplicitLod = 631, // SPIRVInstrInfo.td:359
647 OpImageSampleDrefImplicitLod = 632, // SPIRVInstrInfo.td:356
648 OpImageSampleExplicitLod = 633, // SPIRVInstrInfo.td:352
649 OpImageSampleFootprintNV = 634, // SPIRVInstrInfo.td:446
650 OpImageSampleImplicitLod = 635, // SPIRVInstrInfo.td:349
651 OpImageSampleProjDrefExplicitLod = 636, // SPIRVInstrInfo.td:373
652 OpImageSampleProjDrefImplicitLod = 637, // SPIRVInstrInfo.td:370
653 OpImageSampleProjExplicitLod = 638, // SPIRVInstrInfo.td:366
654 OpImageSampleProjImplicitLod = 639, // SPIRVInstrInfo.td:363
655 OpImageSparseDrefGather = 640, // SPIRVInstrInfo.td:436
656 OpImageSparseFetch = 641, // SPIRVInstrInfo.td:430
657 OpImageSparseGather = 642, // SPIRVInstrInfo.td:433
658 OpImageSparseRead = 643, // SPIRVInstrInfo.td:442
659 OpImageSparseSampleDrefExplicitLod = 644, // SPIRVInstrInfo.td:412
660 OpImageSparseSampleDrefImplicitLod = 645, // SPIRVInstrInfo.td:409
661 OpImageSparseSampleExplicitLod = 646, // SPIRVInstrInfo.td:405
662 OpImageSparseSampleImplicitLod = 647, // SPIRVInstrInfo.td:402
663 OpImageSparseSampleProjDrefExplicitLod = 648, // SPIRVInstrInfo.td:426
664 OpImageSparseSampleProjDrefImplicitLod = 649, // SPIRVInstrInfo.td:423
665 OpImageSparseSampleProjExplicitLod = 650, // SPIRVInstrInfo.td:419
666 OpImageSparseSampleProjImplicitLod = 651, // SPIRVInstrInfo.td:416
667 OpImageSparseTexelsResident = 652, // SPIRVInstrInfo.td:440
668 OpImageTexelPointer = 653, // SPIRVInstrInfo.td:263
669 OpImageWrite = 654, // SPIRVInstrInfo.td:390
670 OpInBoundsAccessChain = 655, // SPIRVInstrInfo.td:276
671 OpInBoundsPtrAccessChain = 656, // SPIRVInstrInfo.td:286
672 OpIsFinite = 657, // SPIRVInstrInfo.td:600
673 OpIsInf = 658, // SPIRVInstrInfo.td:599
674 OpIsNan = 659, // SPIRVInstrInfo.td:598
675 OpIsNormal = 660, // SPIRVInstrInfo.td:601
676 OpIsValidEvent = 661, // SPIRVInstrInfo.td:796
677 OpIsValidReserveId = 662, // SPIRVInstrInfo.td:826
678 OpKill = 663, // SPIRVInstrInfo.td:675
679 OpLabel = 664, // SPIRVInstrInfo.td:667
680 OpLessOrGreater = 665, // SPIRVInstrInfo.td:604
681 OpLifetimeStart = 666, // SPIRVInstrInfo.td:682
682 OpLifetimeStop = 667, // SPIRVInstrInfo.td:683
683 OpLine = 668, // SPIRVInstrInfo.td:121
684 OpLoad = 669, // SPIRVInstrInfo.td:266
685 OpLogicalAnd = 670, // SPIRVInstrInfo.td:611
686 OpLogicalEqual = 671, // SPIRVInstrInfo.td:608
687 OpLogicalNot = 672, // SPIRVInstrInfo.td:612
688 OpLogicalNotEqual = 673, // SPIRVInstrInfo.td:609
689 OpLogicalOr = 674, // SPIRVInstrInfo.td:610
690 OpLoopControlINTEL = 675, // SPIRVInstrInfo.td:663
691 OpLoopMerge = 676, // SPIRVInstrInfo.td:661
692 OpMaskedGatherINTEL = 677, // SPIRVInstrInfo.td:1174
693 OpMaskedScatterINTEL = 678, // SPIRVInstrInfo.td:1176
694 OpMatrixTimesMatrix = 679, // SPIRVInstrInfo.td:542
695 OpMatrixTimesScalar = 680, // SPIRVInstrInfo.td:539
696 OpMatrixTimesVector = 681, // SPIRVInstrInfo.td:541
697 OpMemberDecorate = 682, // SPIRVInstrInfo.td:130
698 OpMemberDecorateString = 683, // SPIRVInstrInfo.td:140
699 OpMemberName = 684, // SPIRVInstrInfo.td:118
700 OpMemoryBarrier = 685, // SPIRVInstrInfo.td:746
701 OpMemoryModel = 686, // SPIRVInstrInfo.td:157
702 OpMemoryNamedBarrier = 687, // SPIRVInstrInfo.td:749
703 OpModuleProcessed = 688, // SPIRVInstrInfo.td:123
704 OpName = 689, // SPIRVInstrInfo.td:117
705 OpNamedBarrierInitialize = 690, // SPIRVInstrInfo.td:748
706 OpNoLine = 691, // SPIRVInstrInfo.td:122
707 OpNop = 692, // SPIRVInstrInfo.td:97
708 OpNot = 693, // SPIRVInstrInfo.td:577
709 OpOrdered = 694, // SPIRVInstrInfo.td:605
710 OpOuterProduct = 695, // SPIRVInstrInfo.td:544
711 OpPhi = 696, // SPIRVInstrInfo.td:659
712 OpPoisonKHR = 697, // SPIRVInstrInfo.td:102
713 OpPredicatedLoadINTEL = 698, // SPIRVInstrInfo.td:1138
714 OpPredicatedStoreINTEL = 699, // SPIRVInstrInfo.td:1140
715 OpPtrAccessChain = 700, // SPIRVInstrInfo.td:279
716 OpPtrCastToCrossWorkgroupINTEL = 701, // SPIRVInstrInfo.td:476
717 OpPtrCastToGeneric = 702, // SPIRVInstrInfo.td:469
718 OpPtrDiff = 703, // SPIRVInstrInfo.td:293
719 OpPtrEqual = 704, // SPIRVInstrInfo.td:289
720 OpPtrNotEqual = 705, // SPIRVInstrInfo.td:291
721 OpQuantizeToF16 = 706, // SPIRVInstrInfo.td:461
722 OpReadClockKHR = 707, // SPIRVInstrInfo.td:897
723 OpReadPipe = 708, // SPIRVInstrInfo.td:810
724 OpReadPipeBlockingALTERA = 709, // SPIRVInstrInfo.td:1144
725 OpReleaseEvent = 710, // SPIRVInstrInfo.td:793
726 OpReserveReadPipePackets = 711, // SPIRVInstrInfo.td:818
727 OpReserveWritePipePackets = 712, // SPIRVInstrInfo.td:820
728 OpReservedReadPipe = 713, // SPIRVInstrInfo.td:814
729 OpReservedWritePipe = 714, // SPIRVInstrInfo.td:816
730 OpRestoreMemoryINTEL = 715, // SPIRVInstrInfo.td:329
731 OpRetainEvent = 716, // SPIRVInstrInfo.td:792
732 OpReturn = 717, // SPIRVInstrInfo.td:676
733 OpReturnValue = 718, // SPIRVInstrInfo.td:677
734 OpRoundFToTF32INTEL = 719, // SPIRVInstrInfo.td:484
735 OpSConvert = 720, // SPIRVInstrInfo.td:458
736 OpSDivS = 721, // SPIRVInstrInfo.td:48
737 OpSDivV = 722, // SPIRVInstrInfo.td:53
738 OpSDot = 723, // SPIRVInstrInfo.td:552
739 OpSDotAccSat = 724, // SPIRVInstrInfo.td:558
740 OpSGreaterThan = 725, // SPIRVInstrInfo.td:620
741 OpSGreaterThanEqual = 726, // SPIRVInstrInfo.td:622
742 OpSLessThan = 727, // SPIRVInstrInfo.td:624
743 OpSLessThanEqual = 728, // SPIRVInstrInfo.td:626
744 OpSMod = 729, // SPIRVInstrInfo.td:531
745 OpSMulExtended = 730, // SPIRVInstrInfo.td:550
746 OpSNegate = 731, // SPIRVInstrInfo.td:508
747 OpSRemS = 732, // SPIRVInstrInfo.td:48
748 OpSRemV = 733, // SPIRVInstrInfo.td:53
749 OpSUDot = 734, // SPIRVInstrInfo.td:556
750 OpSUDotAccSat = 735, // SPIRVInstrInfo.td:562
751 OpSampledImage = 736, // SPIRVInstrInfo.td:347
752 OpSatConvertSToU = 737, // SPIRVInstrInfo.td:465
753 OpSatConvertUToS = 738, // SPIRVInstrInfo.td:466
754 OpSaveMemoryINTEL = 739, // SPIRVInstrInfo.td:327
755 OpSelectSFSCond = 740, // SPIRVInstrInfo.td:67
756 OpSelectSFVCond = 741, // SPIRVInstrInfo.td:68
757 OpSelectSISCond = 742, // SPIRVInstrInfo.td:63
758 OpSelectSIVCond = 743, // SPIRVInstrInfo.td:64
759 OpSelectSPSCond = 744, // SPIRVInstrInfo.td:59
760 OpSelectSPVCond = 745, // SPIRVInstrInfo.td:60
761 OpSelectVFSCond = 746, // SPIRVInstrInfo.td:80
762 OpSelectVFVCond = 747, // SPIRVInstrInfo.td:81
763 OpSelectVISCond = 748, // SPIRVInstrInfo.td:76
764 OpSelectVIVCond = 749, // SPIRVInstrInfo.td:77
765 OpSelectVPSCond = 750, // SPIRVInstrInfo.td:72
766 OpSelectVPVCond = 751, // SPIRVInstrInfo.td:73
767 OpSelectionMerge = 752, // SPIRVInstrInfo.td:665
768 OpSetUserEventStatus = 753, // SPIRVInstrInfo.td:798
769 OpShiftLeftLogicalS = 754, // SPIRVInstrInfo.td:48
770 OpShiftLeftLogicalV = 755, // SPIRVInstrInfo.td:53
771 OpShiftRightArithmeticS = 756, // SPIRVInstrInfo.td:48
772 OpShiftRightArithmeticV = 757, // SPIRVInstrInfo.td:53
773 OpShiftRightLogicalS = 758, // SPIRVInstrInfo.td:48
774 OpShiftRightLogicalV = 759, // SPIRVInstrInfo.td:53
775 OpSignBitSet = 760, // SPIRVInstrInfo.td:602
776 OpSizeOf = 761, // SPIRVInstrInfo.td:99
777 OpSource = 762, // SPIRVInstrInfo.td:113
778 OpSourceContinued = 763, // SPIRVInstrInfo.td:111
779 OpSourceExtension = 764, // SPIRVInstrInfo.td:115
780 OpSpecConstant = 765, // SPIRVInstrInfo.td:248
781 OpSpecConstantComposite = 766, // SPIRVInstrInfo.td:250
782 OpSpecConstantCompositeContinuedINTEL = 767, // SPIRVInstrInfo.td:252
783 OpSpecConstantFalse = 768, // SPIRVInstrInfo.td:247
784 OpSpecConstantOp = 769, // SPIRVInstrInfo.td:256
785 OpSpecConstantTrue = 770, // SPIRVInstrInfo.td:246
786 OpStore = 771, // SPIRVInstrInfo.td:268
787 OpStrictFAddS = 772, // SPIRVInstrInfo.td:46
788 OpStrictFAddV = 773, // SPIRVInstrInfo.td:51
789 OpStrictFDivS = 774, // SPIRVInstrInfo.td:46
790 OpStrictFDivV = 775, // SPIRVInstrInfo.td:51
791 OpStrictFMulS = 776, // SPIRVInstrInfo.td:46
792 OpStrictFMulV = 777, // SPIRVInstrInfo.td:51
793 OpStrictFRemS = 778, // SPIRVInstrInfo.td:46
794 OpStrictFRemV = 779, // SPIRVInstrInfo.td:51
795 OpStrictFSubS = 780, // SPIRVInstrInfo.td:46
796 OpStrictFSubV = 781, // SPIRVInstrInfo.td:51
797 OpString = 782, // SPIRVInstrInfo.td:120
798 OpSubgroup2DBlockLoadINTEL = 783, // SPIRVInstrInfo.td:1121
799 OpSubgroup2DBlockLoadTransformINTEL = 784, // SPIRVInstrInfo.td:1127
800 OpSubgroup2DBlockLoadTransposeINTEL = 785, // SPIRVInstrInfo.td:1124
801 OpSubgroup2DBlockPrefetchINTEL = 786, // SPIRVInstrInfo.td:1130
802 OpSubgroup2DBlockStoreINTEL = 787, // SPIRVInstrInfo.td:1133
803 OpSubgroupBlockReadINTEL = 788, // SPIRVInstrInfo.td:922
804 OpSubgroupBlockWriteINTEL = 789, // SPIRVInstrInfo.td:924
805 OpSubgroupImageBlockReadINTEL = 790, // SPIRVInstrInfo.td:926
806 OpSubgroupImageBlockWriteINTEL = 791, // SPIRVInstrInfo.td:928
807 OpSubgroupImageMediaBlockReadINTEL = 792, // SPIRVInstrInfo.td:932
808 OpSubgroupImageMediaBlockWriteINTEL = 793, // SPIRVInstrInfo.td:934
809 OpSubgroupMatrixMultiplyAccumulateINTEL = 794, // SPIRVInstrInfo.td:784
810 OpSubgroupShuffleDownINTEL = 795, // SPIRVInstrInfo.td:916
811 OpSubgroupShuffleINTEL = 796, // SPIRVInstrInfo.td:914
812 OpSubgroupShuffleUpINTEL = 797, // SPIRVInstrInfo.td:918
813 OpSubgroupShuffleXorINTEL = 798, // SPIRVInstrInfo.td:920
814 OpSwitch = 799, // SPIRVInstrInfo.td:672
815 OpTranspose = 800, // SPIRVInstrInfo.td:503
816 OpTypeAccelerationStructureNV = 801, // SPIRVInstrInfo.td:208
817 OpTypeArray = 802, // SPIRVInstrInfo.td:186
818 OpTypeBool = 803, // SPIRVInstrInfo.td:171
819 OpTypeCooperativeMatrixKHR = 804, // SPIRVInstrInfo.td:213
820 OpTypeCooperativeMatrixNV = 805, // SPIRVInstrInfo.td:210
821 OpTypeDeviceEvent = 806, // SPIRVInstrInfo.td:200
822 OpTypeEvent = 807, // SPIRVInstrInfo.td:199
823 OpTypeFloat = 808, // SPIRVInstrInfo.td:174
824 OpTypeForwardPointer = 809, // SPIRVInstrInfo.td:204
825 OpTypeFunction = 810, // SPIRVInstrInfo.td:197
826 OpTypeImage = 811, // SPIRVInstrInfo.td:180
827 OpTypeInt = 812, // SPIRVInstrInfo.td:172
828 OpTypeMatrix = 813, // SPIRVInstrInfo.td:178
829 OpTypeNamedBarrier = 814, // SPIRVInstrInfo.td:207
830 OpTypeOpaque = 815, // SPIRVInstrInfo.td:193
831 OpTypePipe = 816, // SPIRVInstrInfo.td:203
832 OpTypePipeStorage = 817, // SPIRVInstrInfo.td:206
833 OpTypePointer = 818, // SPIRVInstrInfo.td:195
834 OpTypeQueue = 819, // SPIRVInstrInfo.td:202
835 OpTypeReserveId = 820, // SPIRVInstrInfo.td:201
836 OpTypeRuntimeArray = 821, // SPIRVInstrInfo.td:188
837 OpTypeSampledImage = 822, // SPIRVInstrInfo.td:184
838 OpTypeSampler = 823, // SPIRVInstrInfo.td:183
839 OpTypeStruct = 824, // SPIRVInstrInfo.td:190
840 OpTypeStructContinuedINTEL = 825, // SPIRVInstrInfo.td:191
841 OpTypeUntypedPointerKHR = 826, // SPIRVInstrInfo.td:298
842 OpTypeVector = 827, // SPIRVInstrInfo.td:176
843 OpTypeVectorIdEXT = 828, // SPIRVInstrInfo.td:216
844 OpTypeVoid = 829, // SPIRVInstrInfo.td:170
845 OpUConvert = 830, // SPIRVInstrInfo.td:457
846 OpUDivS = 831, // SPIRVInstrInfo.td:48
847 OpUDivV = 832, // SPIRVInstrInfo.td:53
848 OpUDot = 833, // SPIRVInstrInfo.td:554
849 OpUDotAccSat = 834, // SPIRVInstrInfo.td:560
850 OpUGreaterThan = 835, // SPIRVInstrInfo.td:619
851 OpUGreaterThanEqual = 836, // SPIRVInstrInfo.td:621
852 OpULessThan = 837, // SPIRVInstrInfo.td:623
853 OpULessThanEqual = 838, // SPIRVInstrInfo.td:625
854 OpUModS = 839, // SPIRVInstrInfo.td:48
855 OpUModV = 840, // SPIRVInstrInfo.td:53
856 OpUMulExtended = 841, // SPIRVInstrInfo.td:549
857 OpUndef = 842, // SPIRVInstrInfo.td:98
858 OpUnordered = 843, // SPIRVInstrInfo.td:606
859 OpUnreachable = 844, // SPIRVInstrInfo.td:678
860 OpUntypedAccessChainKHR = 845, // SPIRVInstrInfo.td:303
861 OpUntypedGroupAsyncCopyKHR = 846, // SPIRVInstrInfo.td:318
862 OpUntypedInBoundsAccessChainKHR = 847, // SPIRVInstrInfo.td:306
863 OpUntypedInBoundsPtrAccessChainKHR = 848, // SPIRVInstrInfo.td:312
864 OpUntypedPrefetchKHR = 849, // SPIRVInstrInfo.td:315
865 OpUntypedPtrAccessChainKHR = 850, // SPIRVInstrInfo.td:309
866 OpUntypedVariableKHR = 851, // SPIRVInstrInfo.td:300
867 OpVariable = 852, // SPIRVInstrInfo.td:261
868 OpVariableLengthArrayINTEL = 853, // SPIRVInstrInfo.td:325
869 OpVectorExtractDynamic = 854, // SPIRVInstrInfo.td:488
870 OpVectorInsertDynamic = 855, // SPIRVInstrInfo.td:490
871 OpVectorShuffle = 856, // SPIRVInstrInfo.td:492
872 OpVectorTimesMatrix = 857, // SPIRVInstrInfo.td:540
873 OpVectorTimesScalar = 858, // SPIRVInstrInfo.td:538
874 OpWritePipe = 859, // SPIRVInstrInfo.td:812
875 OpWritePipeBlockingALTERA = 860, // SPIRVInstrInfo.td:1146
876 INSTRUCTION_LIST_END = 861
877 };
878
879} // namespace llvm::SPIRV
880
881#endif // GET_INSTRINFO_ENUM
882
883#ifdef GET_INSTRINFO_SCHED_ENUM
884#undef GET_INSTRINFO_SCHED_ENUM
885
886namespace llvm::SPIRV::Sched {
887
888 enum {
889 NoInstrModel = 0,
890 SCHED_LIST_END = 1
891 };
892
893} // namespace llvm::SPIRV::Sched
894
895#endif // GET_INSTRINFO_SCHED_ENUM
896
897#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
898
899namespace llvm {
900
901struct SPIRVInstrTable {
902 MCInstrDesc Insts[861];
903 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
904 MCPhysReg ImplicitOps[1];
905 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
906 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
907 MCOperandInfo OperandInfo[504];
908};
909} // namespace llvm
910
911#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
912
913#ifdef GET_INSTRINFO_MC_DESC
914#undef GET_INSTRINFO_MC_DESC
915
916namespace llvm {
917
918static_assert((sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
919static constexpr unsigned SPIRVOpInfoBase = (sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) / sizeof(MCOperandInfo);
920
921extern const SPIRVInstrTable SPIRVDescs = {
922 {
923 { 860, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipeBlockingALTERA
924 { 859, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipe
925 { 858, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesScalar
926 { 857, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesMatrix
927 { 856, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorShuffle
928 { 855, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorInsertDynamic
929 { 854, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorExtractDynamic
930 { 853, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariableLengthArrayINTEL
931 { 852, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 501, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariable
932 { 851, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 313, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedVariableKHR
933 { 850, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 496, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedPtrAccessChainKHR
934 { 849, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedPrefetchKHR
935 { 848, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 496, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedInBoundsPtrAccessChainKHR
936 { 847, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 483, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedInBoundsAccessChainKHR
937 { 846, 9, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 487, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedGroupAsyncCopyKHR
938 { 845, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 483, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedAccessChainKHR
939 { 844, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnreachable
940 { 843, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnordered
941 { 842, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUndef
942 { 841, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUMulExtended
943 { 840, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModV
944 { 839, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModS
945 { 838, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThanEqual
946 { 837, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThan
947 { 836, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThanEqual
948 { 835, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThan
949 { 834, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDotAccSat
950 { 833, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDot
951 { 832, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivV
952 { 831, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivS
953 { 830, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUConvert
954 { 829, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVoid
955 { 828, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 448, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVectorIdEXT
956 { 827, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 477, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVector
957 { 826, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeUntypedPointerKHR
958 { 825, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStructContinuedINTEL
959 { 824, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStruct
960 { 823, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampler
961 { 822, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 464, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampledImage
962 { 821, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 464, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeRuntimeArray
963 { 820, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeReserveId
964 { 819, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeQueue
965 { 818, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 480, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePointer
966 { 817, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipeStorage
967 { 816, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipe
968 { 815, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeOpaque
969 { 814, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeNamedBarrier
970 { 813, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 477, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeMatrix
971 { 812, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 474, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeInt
972 { 811, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 466, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeImage
973 { 810, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 464, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFunction
974 { 809, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 462, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeForwardPointer
975 { 808, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFloat
976 { 807, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeEvent
977 { 806, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeDeviceEvent
978 { 805, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixNV
979 { 804, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 451, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixKHR
980 { 803, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeBool
981 { 802, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 448, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeArray
982 { 801, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 447, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeAccelerationStructureNV
983 { 800, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTranspose
984 { 799, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSwitch
985 { 798, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleXorINTEL
986 { 797, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleUpINTEL
987 { 796, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleINTEL
988 { 795, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleDownINTEL
989 { 794, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupMatrixMultiplyAccumulateINTEL
990 { 793, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockWriteINTEL
991 { 792, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockReadINTEL
992 { 791, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockWriteINTEL
993 { 790, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockReadINTEL
994 { 789, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockWriteINTEL
995 { 788, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockReadINTEL
996 { 787, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 428, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockStoreINTEL
997 { 786, 9, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 438, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockPrefetchINTEL
998 { 785, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 428, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransposeINTEL
999 { 784, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 428, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransformINTEL
1000 { 783, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 428, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadINTEL
1001 { 782, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpString
1002 { 781, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubV
1003 { 780, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubS
1004 { 779, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemV
1005 { 778, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemS
1006 { 777, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulV
1007 { 776, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulS
1008 { 775, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivV
1009 { 774, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivS
1010 { 773, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddV
1011 { 772, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddS
1012 { 771, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStore
1013 { 770, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantTrue
1014 { 769, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 424, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantOp
1015 { 768, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantFalse
1016 { 767, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantCompositeContinuedINTEL
1017 { 766, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantComposite
1018 { 765, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 421, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstant
1019 { 764, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceExtension
1020 { 763, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceContinued
1021 { 762, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSource
1022 { 761, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSizeOf
1023 { 760, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSignBitSet
1024 { 759, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalV
1025 { 758, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalS
1026 { 757, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticV
1027 { 756, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticS
1028 { 755, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalV
1029 { 754, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalS
1030 { 753, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSetUserEventStatus
1031 { 752, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectionMerge
1032 { 751, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 416, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPVCond
1033 { 750, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 411, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPSCond
1034 { 749, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 406, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVIVCond
1035 { 748, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 401, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVISCond
1036 { 747, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 396, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFVCond
1037 { 746, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 391, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFSCond
1038 { 745, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 386, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPVCond
1039 { 744, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 381, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPSCond
1040 { 743, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 376, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSIVCond
1041 { 742, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 371, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSISCond
1042 { 741, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 366, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFVCond
1043 { 740, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 361, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFSCond
1044 { 739, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSaveMemoryINTEL
1045 { 738, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertUToS
1046 { 737, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertSToU
1047 { 736, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSampledImage
1048 { 735, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDotAccSat
1049 { 734, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDot
1050 { 733, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemV
1051 { 732, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemS
1052 { 731, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSNegate
1053 { 730, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMulExtended
1054 { 729, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMod
1055 { 728, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThanEqual
1056 { 727, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThan
1057 { 726, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThanEqual
1058 { 725, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThan
1059 { 724, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDotAccSat
1060 { 723, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDot
1061 { 722, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivV
1062 { 721, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivS
1063 { 720, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSConvert
1064 { 719, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRoundFToTF32INTEL
1065 { 718, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturnValue
1066 { 717, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturn
1067 { 716, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRetainEvent
1068 { 715, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRestoreMemoryINTEL
1069 { 714, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedWritePipe
1070 { 713, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedReadPipe
1071 { 712, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveWritePipePackets
1072 { 711, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveReadPipePackets
1073 { 710, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReleaseEvent
1074 { 709, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipeBlockingALTERA
1075 { 708, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipe
1076 { 707, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadClockKHR
1077 { 706, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpQuantizeToF16
1078 { 705, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrNotEqual
1079 { 704, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrEqual
1080 { 703, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrDiff
1081 { 702, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToGeneric
1082 { 701, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToCrossWorkgroupINTEL
1083 { 700, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrAccessChain
1084 { 699, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedStoreINTEL
1085 { 698, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedLoadINTEL
1086 { 697, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPoisonKHR
1087 { 696, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPhi
1088 { 695, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOuterProduct
1089 { 694, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOrdered
1090 { 693, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNot
1091 { 692, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNop
1092 { 691, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNoLine
1093 { 690, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNamedBarrierInitialize
1094 { 689, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpName
1095 { 688, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpModuleProcessed
1096 { 687, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryNamedBarrier
1097 { 686, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryModel
1098 { 685, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryBarrier
1099 { 684, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 354, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberName
1100 { 683, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 357, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorateString
1101 { 682, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 354, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorate
1102 { 681, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesVector
1103 { 680, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesScalar
1104 { 679, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesMatrix
1105 { 678, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedScatterINTEL
1106 { 677, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedGatherINTEL
1107 { 676, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopMerge
1108 { 675, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopControlINTEL
1109 { 674, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalOr
1110 { 673, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNotEqual
1111 { 672, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNot
1112 { 671, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalEqual
1113 { 670, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalAnd
1114 { 669, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoad
1115 { 668, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 351, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLine
1116 { 667, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStop
1117 { 666, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStart
1118 { 665, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLessOrGreater
1119 { 664, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLabel
1120 { 663, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpKill
1121 { 662, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidReserveId
1122 { 661, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidEvent
1123 { 660, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNormal
1124 { 659, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNan
1125 { 658, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsInf
1126 { 657, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsFinite
1127 { 656, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsPtrAccessChain
1128 { 655, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsAccessChain
1129 { 654, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageWrite
1130 { 653, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageTexelPointer
1131 { 652, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseTexelsResident
1132 { 651, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjImplicitLod
1133 { 650, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjExplicitLod
1134 { 649, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefImplicitLod
1135 { 648, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefExplicitLod
1136 { 647, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleImplicitLod
1137 { 646, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 343, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleExplicitLod
1138 { 645, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefImplicitLod
1139 { 644, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefExplicitLod
1140 { 643, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseRead
1141 { 642, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseGather
1142 { 641, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseFetch
1143 { 640, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseDrefGather
1144 { 639, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjImplicitLod
1145 { 638, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjExplicitLod
1146 { 637, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefImplicitLod
1147 { 636, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefExplicitLod
1148 { 635, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleImplicitLod
1149 { 634, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleFootprintNV
1150 { 633, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 343, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleExplicitLod
1151 { 632, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefImplicitLod
1152 { 631, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 336, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefExplicitLod
1153 { 630, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageRead
1154 { 629, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySizeLod
1155 { 628, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySize
1156 { 627, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySamples
1157 { 626, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryOrder
1158 { 625, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLod
1159 { 624, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLevels
1160 { 623, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryFormat
1161 { 622, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageGather
1162 { 621, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageFetch
1163 { 620, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageDrefGather
1164 { 619, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImage
1165 { 618, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubV
1166 { 617, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubS
1167 { 616, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowV
1168 { 615, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowS
1169 { 614, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpINotEqual
1170 { 613, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulV
1171 { 612, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulS
1172 { 611, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIEqual
1173 { 610, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddV
1174 { 609, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddS
1175 { 608, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryV
1176 { 607, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryS
1177 { 606, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupWaitEvents
1178 { 605, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMin
1179 { 604, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMax
1180 { 603, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMin
1181 { 602, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMax
1182 { 601, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveWritePipePackets
1183 { 600, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveReadPipePackets
1184 { 599, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMin
1185 { 598, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMax
1186 { 597, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleXor
1187 { 596, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleUp
1188 { 595, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleDown
1189 { 594, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffle
1190 { 593, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMin
1191 { 592, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMax
1192 { 591, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformRotateKHR
1193 { 590, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformQuadSwap
1194 { 589, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalXor
1195 { 588, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalOr
1196 { 587, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalAnd
1197 { 586, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformInverseBallot
1198 { 585, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIMul
1199 { 584, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIAdd
1200 { 583, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMul
1201 { 582, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMin
1202 { 581, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMax
1203 { 580, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFAdd
1204 { 579, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformElect
1205 { 578, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcastFirst
1206 { 577, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcast
1207 { 576, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseXor
1208 { 575, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseOr
1209 { 574, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseAnd
1210 { 573, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindMSB
1211 { 572, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindLSB
1212 { 571, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitExtract
1213 { 570, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitCount
1214 { 569, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallot
1215 { 568, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAny
1216 { 567, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAllEqual
1217 { 566, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAll
1218 { 565, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalXorKHR
1219 { 564, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalOrKHR
1220 { 563, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalAndKHR
1221 { 562, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIMulKHR
1222 { 561, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIAdd
1223 { 560, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMulKHR
1224 { 559, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMin
1225 { 558, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMax
1226 { 557, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFAdd
1227 { 556, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitWritePipe
1228 { 555, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitReadPipe
1229 { 554, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBroadcast
1230 { 553, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseXorKHR
1231 { 552, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseOrKHR
1232 { 551, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseAndKHR
1233 { 550, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAsyncCopy
1234 { 549, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAny
1235 { 548, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAll
1236 { 547, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetNumPipePackets
1237 { 546, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetMaxPipePackets
1238 { 545, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetDefaultQueue
1239 { 544, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericPtrMemSemantics
1240 { 543, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 317, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtrExplicit
1241 { 542, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtr
1242 { 541, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthFine
1243 { 540, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthCoarse
1244 { 539, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidth
1245 { 538, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionPointerCallINTEL
1246 { 537, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionParameter
1247 { 536, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionEnd
1248 { 535, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionCall
1249 { 534, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 313, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunction
1250 { 533, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFreezeKHR
1251 { 532, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFmaKHR
1252 { 531, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSqrtALTERA
1253 { 530, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinPiALTERA
1254 { 529, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosPiALTERA
1255 { 528, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosALTERA
1256 { 527, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinALTERA
1257 { 526, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRsqrtALTERA
1258 { 525, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRecipALTERA
1259 { 524, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedLogALTERA
1260 { 523, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedExpALTERA
1261 { 522, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosPiALTERA
1262 { 521, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosALTERA
1263 { 520, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordNotEqual
1264 { 519, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThanEqual
1265 { 518, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThan
1266 { 517, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThanEqual
1267 { 516, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThan
1268 { 515, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordEqual
1269 { 514, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubV
1270 { 513, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubS
1271 { 512, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemV
1272 { 511, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemS
1273 { 510, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdNotEqual
1274 { 509, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThanEqual
1275 { 508, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThan
1276 { 507, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThanEqual
1277 { 506, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThan
1278 { 505, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdEqual
1279 { 504, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 310, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegateV
1280 { 503, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegate
1281 { 502, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulV
1282 { 501, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulS
1283 { 500, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMod
1284 { 499, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivV
1285 { 498, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivS
1286 { 497, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFConvert
1287 { 496, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddV
1288 { 495, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddS
1289 { 494, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtension
1290 { 493, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInstImport
1291 { 492, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 298, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInst
1292 { 491, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExpectKHR
1293 { 490, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionModeId
1294 { 489, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionMode
1295 { 488, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 295, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEntryPoint
1296 { 487, 12, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 283, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEnqueueKernel
1297 { 486, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndStreamPrimitive
1298 { 485, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndPrimitive
1299 { 484, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitVertex
1300 { 483, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitStreamVertex
1301 { 482, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDot
1302 { 481, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDemoteToHelperInvocation
1303 { 480, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 280, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateString
1304 { 479, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateId
1305 { 478, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorate
1306 { 477, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyFine
1307 { 476, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyCoarse
1308 { 475, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdy
1309 { 474, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxFine
1310 { 473, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxCoarse
1311 { 472, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdx
1312 { 471, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCrossWorkgroupCastToPtrINTEL
1313 { 470, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCreateUserEvent
1314 { 469, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyObject
1315 { 468, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemorySized
1316 { 467, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemory
1317 { 466, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyLogical
1318 { 465, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreKHR
1319 { 464, 7, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 271, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreCheckedINTEL
1320 { 463, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 266, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixPrefetchINTEL
1321 { 462, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixMulAddKHR
1322 { 461, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadKHR
1323 { 460, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadCheckedINTEL
1324 { 459, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 263, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLengthKHR
1325 { 458, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixGetElementCoordINTEL
1326 { 457, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixConstructCheckedINTEL
1327 { 456, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToPtr
1328 { 455, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToF
1329 { 454, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertSToF
1330 { 453, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertPtrToU
1331 { 452, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSamplerINTEL
1332 { 451, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSampledImageINTEL
1333 { 450, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToImageINTEL
1334 { 449, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToU
1335 { 448, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToS
1336 { 447, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToBF16INTEL
1337 { 446, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertBF16ToFINTEL
1338 { 445, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierWaitINTEL
1339 { 444, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierArriveINTEL
1340 { 443, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrier
1341 { 442, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantTrue
1342 { 441, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantSampler
1343 { 440, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantNull
1344 { 439, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 248, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantI
1345 { 438, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFunctionPointerINTEL
1346 { 437, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFalse
1347 { 436, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantF
1348 { 435, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantCompositeContinuedINTEL
1349 { 434, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantComposite
1350 { 433, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeInsert
1351 { 432, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeExtract
1352 { 431, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstructContinuedINTEL
1353 { 430, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstruct
1354 { 429, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitWritePipe
1355 { 428, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitReadPipe
1356 { 427, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCaptureEventProfilingInfo
1357 { 426, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCapability
1358 { 425, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBuildNDRange
1359 { 424, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 234, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranchConditional
1360 { 423, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranch
1361 { 422, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorV
1362 { 421, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorS
1363 { 420, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrV
1364 { 419, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrS
1365 { 418, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseFunctionINTEL
1366 { 417, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndV
1367 { 416, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndS
1368 { 415, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitcast
1369 { 414, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitReverse
1370 { 413, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldUExtract
1371 { 412, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldSExtract
1372 { 411, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldInsert
1373 { 410, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitCount
1374 { 409, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicXor
1375 { 408, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMin
1376 { 407, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMax
1377 { 406, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicStore
1378 { 405, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMin
1379 { 404, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMax
1380 { 403, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicOr
1381 { 402, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicLoad
1382 { 401, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicISub
1383 { 400, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIIncrement
1384 { 399, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIDecrement
1385 { 398, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIAdd
1386 { 397, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagTestAndSet
1387 { 396, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagClear
1388 { 395, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMinEXT
1389 { 394, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMaxEXT
1390 { 393, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFAddEXT
1391 { 392, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicExchange
1392 { 391, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchangeWeak
1393 { 390, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchange
1394 { 389, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicAnd
1395 { 388, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAssumeTrueKHR
1396 { 387, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmTargetINTEL
1397 { 386, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 192, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmINTEL
1398 { 385, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmCallINTEL
1399 { 384, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 188, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArrayLength
1400 { 383, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArithmeticFenceEXT
1401 { 382, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSubALTERA
1402 { 381, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSqrtALTERA
1403 { 380, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinPiALTERA
1404 { 379, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosPiALTERA
1405 { 378, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosALTERA
1406 { 377, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinALTERA
1407 { 376, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRecipALTERA
1408 { 375, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRSqrtALTERA
1409 { 374, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowRALTERA
1410 { 373, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowNALTERA
1411 { 372, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowALTERA
1412 { 371, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatMulALTERA
1413 { 370, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLogALTERA
1414 { 369, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog2ALTERA
1415 { 368, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog1pALTERA
1416 { 367, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog10ALTERA
1417 { 366, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLTALTERA
1418 { 365, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLEALTERA
1419 { 364, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatHypotALTERA
1420 { 363, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGTALTERA
1421 { 362, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGEALTERA
1422 { 361, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpm1ALTERA
1423 { 360, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpALTERA
1424 { 359, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp2ALTERA
1425 { 358, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp10ALTERA
1426 { 357, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatEQALTERA
1427 { 356, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatDivALTERA
1428 { 355, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosPiALTERA
1429 { 354, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosALTERA
1430 { 353, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCbrtALTERA
1431 { 352, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastToIntALTERA
1432 { 351, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastFromIntALTERA
1433 { 350, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastALTERA
1434 { 349, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatAddALTERA
1435 { 348, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanPiALTERA
1436 { 347, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanALTERA
1437 { 346, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATan2ALTERA
1438 { 345, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinPiALTERA
1439 { 344, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinALTERA
1440 { 343, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosPiALTERA
1441 { 342, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosALTERA
1442 { 341, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAny
1443 { 340, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAll
1444 { 339, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeListDeclINTEL
1445 { 338, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeDeclINTEL
1446 { 337, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasDomainDeclINTEL
1447 { 336, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAccessChain
1448 { 335, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAbortKHR
1449 { 334, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNKNOWN_type
1450 { 333, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASSIGN_TYPE
1451 { 332, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1452 { 331, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1453 { 330, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1454 { 329, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1455 { 328, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1456 { 327, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1457 { 326, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1458 { 325, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1459 { 324, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1460 { 323, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1461 { 322, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1462 { 321, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1463 { 320, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1464 { 319, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1465 { 318, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1466 { 317, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1467 { 316, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1468 { 315, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1469 { 314, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1470 { 313, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1471 { 312, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1472 { 311, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1473 { 310, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1474 { 309, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1475 { 308, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
1476 { 307, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1477 { 306, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1478 { 305, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1479 { 304, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1480 { 303, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1481 { 302, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1482 { 301, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1483 { 300, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
1484 { 299, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
1485 { 298, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1486 { 297, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1487 { 296, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1488 { 295, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1489 { 294, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1490 { 293, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1491 { 292, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1492 { 291, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1493 { 290, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1494 { 289, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1495 { 288, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1496 { 287, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1497 { 286, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1498 { 285, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1499 { 284, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1500 { 283, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1501 { 282, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1502 { 281, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1503 { 280, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1504 { 279, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1505 { 278, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1506 { 277, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1507 { 276, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1508 { 275, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1509 { 274, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1510 { 273, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1511 { 272, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1512 { 271, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1513 { 270, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1514 { 269, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1515 { 268, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
1516 { 267, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1517 { 266, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1518 { 265, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1519 { 264, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1520 { 263, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
1521 { 262, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1522 { 261, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
1523 { 260, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1524 { 259, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1525 { 258, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1526 { 257, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1527 { 256, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1528 { 255, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1529 { 254, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1530 { 253, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1531 { 252, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1532 { 251, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1533 { 250, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1534 { 249, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1535 { 248, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1536 { 247, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1537 { 246, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1538 { 245, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1539 { 244, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1540 { 243, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1541 { 242, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1542 { 241, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1543 { 240, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1544 { 239, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1545 { 238, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1546 { 237, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1547 { 236, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1548 { 235, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1549 { 234, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1550 { 233, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1551 { 232, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1552 { 231, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1553 { 230, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1554 { 229, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1555 { 228, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1556 { 227, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1557 { 226, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1558 { 225, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1559 { 224, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1560 { 223, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1561 { 222, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1562 { 221, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1563 { 220, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1564 { 219, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1565 { 218, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1566 { 217, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1567 { 216, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1568 { 215, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1569 { 214, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1570 { 213, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1571 { 212, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1572 { 211, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1573 { 210, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1574 { 209, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1575 { 208, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1576 { 207, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1577 { 206, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1578 { 205, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1579 { 204, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1580 { 203, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1581 { 202, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1582 { 201, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1583 { 200, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1584 { 199, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1585 { 198, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1586 { 197, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1587 { 196, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1588 { 195, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1589 { 194, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1590 { 193, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1591 { 192, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1592 { 191, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1593 { 190, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1594 { 189, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1595 { 188, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1596 { 187, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1597 { 186, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1598 { 185, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1599 { 184, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1600 { 183, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1601 { 182, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1602 { 181, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1603 { 180, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1604 { 179, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1605 { 178, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1606 { 177, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1607 { 176, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1608 { 175, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1609 { 174, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1610 { 173, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1611 { 172, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1612 { 171, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1613 { 170, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1614 { 169, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1615 { 168, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1616 { 167, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1617 { 166, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1618 { 165, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1619 { 164, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1620 { 163, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1621 { 162, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1622 { 161, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1623 { 160, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1624 { 159, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1625 { 158, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1626 { 157, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1627 { 156, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1628 { 155, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1629 { 154, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1630 { 153, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1631 { 152, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1632 { 151, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1633 { 150, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1634 { 149, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1635 { 148, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1636 { 147, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1637 { 146, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1638 { 145, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1639 { 144, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1640 { 143, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1641 { 142, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1642 { 141, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1643 { 140, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1644 { 139, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1645 { 138, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1646 { 137, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1647 { 136, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1648 { 135, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1649 { 134, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1650 { 133, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1651 { 132, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1652 { 131, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1653 { 130, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1654 { 129, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1655 { 128, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1656 { 127, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1657 { 126, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1658 { 125, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1659 { 124, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1660 { 123, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1661 { 122, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1662 { 121, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1663 { 120, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1664 { 119, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1665 { 118, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1666 { 117, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1667 { 116, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1668 { 115, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1669 { 114, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1670 { 113, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1671 { 112, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1672 { 111, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1673 { 110, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1674 { 109, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1675 { 108, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1676 { 107, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1677 { 106, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1678 { 105, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1679 { 104, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1680 { 103, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1681 { 102, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1682 { 101, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1683 { 100, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1684 { 99, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1685 { 98, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1686 { 97, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1687 { 96, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1688 { 95, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1689 { 94, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1690 { 93, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1691 { 92, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1692 { 91, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1693 { 90, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1694 { 89, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1695 { 88, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1696 { 87, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1697 { 86, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1698 { 85, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1699 { 84, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1700 { 83, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1701 { 82, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1702 { 81, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1703 { 80, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1704 { 79, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1705 { 78, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1706 { 77, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1707 { 76, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1708 { 75, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1709 { 74, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1710 { 73, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1711 { 72, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1712 { 71, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1713 { 70, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1714 { 69, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1715 { 68, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1716 { 67, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1717 { 66, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1718 { 65, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1719 { 64, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1720 { 63, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1721 { 62, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1722 { 61, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1723 { 60, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1724 { 59, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1725 { 58, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1726 { 57, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1727 { 56, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1728 { 55, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1729 { 54, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1730 { 53, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1731 { 52, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1732 { 51, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1733 { 50, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1734 { 49, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1735 { 48, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1736 { 47, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1737 { 46, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1738 { 45, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1739 { 44, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1740 { 43, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1741 { 42, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21484
1742 { 41, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21483
1743 { 40, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1744 { 39, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1745 { 38, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1746 { 37, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1747 { 36, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1748 { 35, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1749 { 34, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1750 { 33, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1751 { 32, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21482
1752 { 31, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1753 { 30, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13978
1754 { 29, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1755 { 28, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1756 { 27, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1757 { 26, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1758 { 25, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1759 { 24, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1760 { 23, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1761 { 22, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1762 { 21, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1763 { 20, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1764 { 19, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1765 { 18, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1766 { 17, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1767 { 16, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1768 { 15, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1769 { 14, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1770 { 13, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1771 { 12, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1772 { 11, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1773 { 10, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1774 { 9, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1775 { 8, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1776 { 7, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1777 { 6, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1778 { 5, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1779 { 4, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1780 { 3, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1781 { 2, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1782 { 1, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1783 { 0, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1784 }, {
1785 /* 0 */
1786 }, {
1787 0
1788 }, {
1789 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1790 /* 1 */
1791 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1792 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1793 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1794 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1795 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1796 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1797 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1798 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1799 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1800 /* 28 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1801 /* 29 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1802 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1803 /* 34 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1804 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1805 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1806 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1807 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1808 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1809 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1810 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1811 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1812 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1813 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1814 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1815 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1816 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1817 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1818 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1819 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1820 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1821 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1822 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1823 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1824 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1825 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1826 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1827 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1828 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1829 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1830 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1831 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1832 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1833 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1834 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1835 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1836 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1837 /* 151 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1838 /* 154 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1839 /* 156 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1840 /* 158 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1841 /* 161 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1842 /* 162 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1843 /* 164 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1844 /* 172 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1845 /* 182 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1846 /* 188 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1847 /* 192 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1848 /* 198 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1849 /* 200 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1850 /* 206 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1851 /* 214 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1852 /* 217 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1853 /* 222 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1854 /* 226 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1855 /* 230 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1856 /* 234 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1857 /* 237 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1858 /* 239 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1859 /* 243 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1860 /* 246 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1861 /* 248 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1862 /* 251 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1863 /* 256 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1864 /* 263 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1865 /* 266 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1866 /* 271 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1867 /* 278 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1868 /* 280 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1869 /* 283 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1870 /* 295 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1871 /* 298 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1872 /* 302 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1873 /* 306 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1874 /* 310 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1875 /* 313 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1876 /* 317 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1877 /* 321 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1878 /* 326 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1879 /* 331 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1880 /* 336 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1881 /* 343 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1882 /* 349 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1883 /* 351 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1884 /* 354 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1885 /* 357 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1886 /* 361 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1887 /* 366 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1888 /* 371 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1889 /* 376 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1890 /* 381 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1891 /* 386 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1892 /* 391 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1893 /* 396 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1894 /* 401 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1895 /* 406 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1896 /* 411 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1897 /* 416 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1898 /* 421 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1899 /* 424 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1900 /* 428 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1901 /* 438 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1902 /* 447 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1903 /* 448 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1904 /* 451 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1905 /* 457 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1906 /* 462 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1907 /* 464 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1908 /* 466 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1909 /* 474 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1910 /* 477 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1911 /* 480 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1912 /* 483 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1913 /* 487 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1914 /* 496 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1915 /* 501 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1916 }
1917};
1918
1919
1920#ifdef __GNUC__
1921#pragma GCC diagnostic push
1922#pragma GCC diagnostic ignored "-Woverlength-strings"
1923#endif
1924extern const char SPIRVInstrNameData[] = {
1925 /* 0 */ "G_FLOG10\000"
1926 /* 9 */ "G_FEXP10\000"
1927 /* 18 */ "G_FLOG2\000"
1928 /* 26 */ "G_FATAN2\000"
1929 /* 35 */ "G_FEXP2\000"
1930 /* 43 */ "OpQuantizeToF16\000"
1931 /* 59 */ "G_FMA\000"
1932 /* 65 */ "G_STRICT_FMA\000"
1933 /* 78 */ "OpArbitraryFloatLog10ALTERA\000"
1934 /* 106 */ "OpArbitraryFloatExp10ALTERA\000"
1935 /* 134 */ "OpArbitraryFloatExpm1ALTERA\000"
1936 /* 162 */ "OpArbitraryFloatLog2ALTERA\000"
1937 /* 189 */ "OpArbitraryFloatATan2ALTERA\000"
1938 /* 217 */ "OpArbitraryFloatExp2ALTERA\000"
1939 /* 244 */ "OpArbitraryFloatGEALTERA\000"
1940 /* 269 */ "OpArbitraryFloatLEALTERA\000"
1941 /* 294 */ "OpArbitraryFloatPowNALTERA\000"
1942 /* 321 */ "OpArbitraryFloatEQALTERA\000"
1943 /* 346 */ "OpArbitraryFloatPowRALTERA\000"
1944 /* 373 */ "OpArbitraryFloatGTALTERA\000"
1945 /* 398 */ "OpArbitraryFloatLTALTERA\000"
1946 /* 423 */ "OpArbitraryFloatSubALTERA\000"
1947 /* 449 */ "OpArbitraryFloatAddALTERA\000"
1948 /* 475 */ "OpReadPipeBlockingALTERA\000"
1949 /* 500 */ "OpWritePipeBlockingALTERA\000"
1950 /* 526 */ "OpFixedLogALTERA\000"
1951 /* 543 */ "OpArbitraryFloatLogALTERA\000"
1952 /* 569 */ "OpArbitraryFloatATanPiALTERA\000"
1953 /* 598 */ "OpArbitraryFloatASinPiALTERA\000"
1954 /* 627 */ "OpFixedSinPiALTERA\000"
1955 /* 646 */ "OpArbitraryFloatSinPiALTERA\000"
1956 /* 674 */ "OpArbitraryFloatACosPiALTERA\000"
1957 /* 703 */ "OpFixedCosPiALTERA\000"
1958 /* 722 */ "OpFixedSinCosPiALTERA\000"
1959 /* 744 */ "OpArbitraryFloatSinCosPiALTERA\000"
1960 /* 775 */ "OpArbitraryFloatCosPiALTERA\000"
1961 /* 803 */ "OpArbitraryFloatMulALTERA\000"
1962 /* 829 */ "OpArbitraryFloatATanALTERA\000"
1963 /* 856 */ "OpArbitraryFloatASinALTERA\000"
1964 /* 883 */ "OpFixedSinALTERA\000"
1965 /* 900 */ "OpArbitraryFloatSinALTERA\000"
1966 /* 926 */ "OpArbitraryFloatLog1pALTERA\000"
1967 /* 954 */ "OpFixedRecipALTERA\000"
1968 /* 973 */ "OpArbitraryFloatRecipALTERA\000"
1969 /* 1001 */ "OpFixedExpALTERA\000"
1970 /* 1018 */ "OpArbitraryFloatExpALTERA\000"
1971 /* 1044 */ "OpArbitraryFloatACosALTERA\000"
1972 /* 1071 */ "OpFixedCosALTERA\000"
1973 /* 1088 */ "OpFixedSinCosALTERA\000"
1974 /* 1108 */ "OpArbitraryFloatSinCosALTERA\000"
1975 /* 1137 */ "OpArbitraryFloatCosALTERA\000"
1976 /* 1163 */ "OpArbitraryFloatCastFromIntALTERA\000"
1977 /* 1197 */ "OpArbitraryFloatCastToIntALTERA\000"
1978 /* 1229 */ "OpArbitraryFloatHypotALTERA\000"
1979 /* 1257 */ "OpArbitraryFloatCbrtALTERA\000"
1980 /* 1284 */ "OpArbitraryFloatRSqrtALTERA\000"
1981 /* 1312 */ "OpFixedSqrtALTERA\000"
1982 /* 1330 */ "OpArbitraryFloatSqrtALTERA\000"
1983 /* 1357 */ "OpFixedRsqrtALTERA\000"
1984 /* 1376 */ "OpArbitraryFloatCastALTERA\000"
1985 /* 1403 */ "OpArbitraryFloatDivALTERA\000"
1986 /* 1429 */ "OpArbitraryFloatPowALTERA\000"
1987 /* 1455 */ "OpGroupNonUniformBallotFindLSB\000"
1988 /* 1486 */ "OpGroupNonUniformBallotFindMSB\000"
1989 /* 1517 */ "G_FSUB\000"
1990 /* 1524 */ "G_STRICT_FSUB\000"
1991 /* 1538 */ "G_ATOMICRMW_FSUB\000"
1992 /* 1555 */ "G_SUB\000"
1993 /* 1561 */ "G_ATOMICRMW_SUB\000"
1994 /* 1577 */ "G_INTRINSIC\000"
1995 /* 1589 */ "G_FPTRUNC\000"
1996 /* 1599 */ "G_INTRINSIC_TRUNC\000"
1997 /* 1617 */ "G_TRUNC\000"
1998 /* 1625 */ "G_BUILD_VECTOR_TRUNC\000"
1999 /* 1646 */ "G_DYN_STACKALLOC\000"
2000 /* 1663 */ "G_FMAD\000"
2001 /* 1670 */ "G_FPEXTLOAD\000"
2002 /* 1682 */ "G_INDEXED_SEXTLOAD\000"
2003 /* 1701 */ "G_SEXTLOAD\000"
2004 /* 1712 */ "G_INDEXED_ZEXTLOAD\000"
2005 /* 1731 */ "G_ZEXTLOAD\000"
2006 /* 1742 */ "G_INDEXED_LOAD\000"
2007 /* 1757 */ "G_LOAD\000"
2008 /* 1764 */ "G_VECREDUCE_FADD\000"
2009 /* 1781 */ "G_FADD\000"
2010 /* 1788 */ "G_VECREDUCE_SEQ_FADD\000"
2011 /* 1809 */ "G_STRICT_FADD\000"
2012 /* 1823 */ "G_ATOMICRMW_FADD\000"
2013 /* 1840 */ "G_VECREDUCE_ADD\000"
2014 /* 1856 */ "G_ADD\000"
2015 /* 1862 */ "G_PTR_ADD\000"
2016 /* 1872 */ "G_ATOMICRMW_ADD\000"
2017 /* 1888 */ "G_ATOMICRMW_NAND\000"
2018 /* 1905 */ "G_VECREDUCE_AND\000"
2019 /* 1921 */ "G_AND\000"
2020 /* 1927 */ "G_ATOMICRMW_AND\000"
2021 /* 1943 */ "LIFETIME_END\000"
2022 /* 1956 */ "G_BRCOND\000"
2023 /* 1965 */ "G_ATOMICRMW_USUB_COND\000"
2024 /* 1987 */ "G_LLROUND\000"
2025 /* 1997 */ "G_LROUND\000"
2026 /* 2006 */ "G_INTRINSIC_ROUND\000"
2027 /* 2024 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
2028 /* 2050 */ "LOAD_STACK_GUARD\000"
2029 /* 2067 */ "PSEUDO_PROBE\000"
2030 /* 2080 */ "G_SSUBE\000"
2031 /* 2088 */ "G_USUBE\000"
2032 /* 2096 */ "G_FENCE\000"
2033 /* 2104 */ "ARITH_FENCE\000"
2034 /* 2116 */ "REG_SEQUENCE\000"
2035 /* 2129 */ "G_SADDE\000"
2036 /* 2137 */ "G_UADDE\000"
2037 /* 2145 */ "G_GET_FPMODE\000"
2038 /* 2158 */ "G_RESET_FPMODE\000"
2039 /* 2173 */ "G_SET_FPMODE\000"
2040 /* 2186 */ "G_FMINNUM_IEEE\000"
2041 /* 2201 */ "G_FMAXNUM_IEEE\000"
2042 /* 2216 */ "G_VSCALE\000"
2043 /* 2225 */ "G_JUMP_TABLE\000"
2044 /* 2238 */ "BUNDLE\000"
2045 /* 2245 */ "G_MEMSET_INLINE\000"
2046 /* 2261 */ "G_MEMCPY_INLINE\000"
2047 /* 2277 */ "RELOC_NONE\000"
2048 /* 2288 */ "LOCAL_ESCAPE\000"
2049 /* 2301 */ "ASSIGN_TYPE\000"
2050 /* 2313 */ "G_FPTRUNCSTORE\000"
2051 /* 2328 */ "G_STACKRESTORE\000"
2052 /* 2343 */ "G_INDEXED_STORE\000"
2053 /* 2359 */ "G_STORE\000"
2054 /* 2367 */ "G_BITREVERSE\000"
2055 /* 2380 */ "FAKE_USE\000"
2056 /* 2389 */ "DBG_VALUE\000"
2057 /* 2399 */ "G_GLOBAL_VALUE\000"
2058 /* 2414 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2059 /* 2437 */ "CONVERGENCECTRL_GLUE\000"
2060 /* 2458 */ "G_STACKSAVE\000"
2061 /* 2470 */ "G_MEMMOVE\000"
2062 /* 2480 */ "G_FREEZE\000"
2063 /* 2489 */ "G_FCANONICALIZE\000"
2064 /* 2505 */ "G_FMODF\000"
2065 /* 2513 */ "INIT_UNDEF\000"
2066 /* 2524 */ "G_IMPLICIT_DEF\000"
2067 /* 2539 */ "DBG_INSTR_REF\000"
2068 /* 2553 */ "OpConvertSToF\000"
2069 /* 2567 */ "OpConvertUToF\000"
2070 /* 2581 */ "OpConstantF\000"
2071 /* 2593 */ "G_FNEG\000"
2072 /* 2600 */ "EXTRACT_SUBREG\000"
2073 /* 2615 */ "INSERT_SUBREG\000"
2074 /* 2629 */ "G_SEXT_INREG\000"
2075 /* 2642 */ "SUBREG_TO_REG\000"
2076 /* 2656 */ "G_ATOMIC_CMPXCHG\000"
2077 /* 2673 */ "G_ATOMICRMW_XCHG\000"
2078 /* 2690 */ "G_GET_ROUNDING\000"
2079 /* 2705 */ "G_SET_ROUNDING\000"
2080 /* 2720 */ "G_FLOG\000"
2081 /* 2727 */ "G_VAARG\000"
2082 /* 2735 */ "PREALLOCATED_ARG\000"
2083 /* 2752 */ "G_PREFETCH\000"
2084 /* 2763 */ "G_SMULH\000"
2085 /* 2771 */ "G_UMULH\000"
2086 /* 2779 */ "G_FTANH\000"
2087 /* 2787 */ "G_FSINH\000"
2088 /* 2795 */ "G_FCOSH\000"
2089 /* 2803 */ "DBG_PHI\000"
2090 /* 2811 */ "G_FPTOSI\000"
2091 /* 2820 */ "G_FPTOUI\000"
2092 /* 2829 */ "G_FPOWI\000"
2093 /* 2837 */ "OpConstantI\000"
2094 /* 2849 */ "COPY_LANEMASK\000"
2095 /* 2863 */ "G_PTRMASK\000"
2096 /* 2873 */ "GC_LABEL\000"
2097 /* 2882 */ "DBG_LABEL\000"
2098 /* 2892 */ "EH_LABEL\000"
2099 /* 2901 */ "ANNOTATION_LABEL\000"
2100 /* 2918 */ "ICALL_BRANCH_FUNNEL\000"
2101 /* 2938 */ "OpRoundFToTF32INTEL\000"
2102 /* 2958 */ "OpConvertFToBF16INTEL\000"
2103 /* 2980 */ "OpConvertBF16ToFINTEL\000"
2104 /* 3002 */ "OpSubgroupImageMediaBlockReadINTEL\000"
2105 /* 3037 */ "OpSubgroupImageBlockReadINTEL\000"
2106 /* 3067 */ "OpSubgroupBlockReadINTEL\000"
2107 /* 3092 */ "OpPredicatedLoadINTEL\000"
2108 /* 3114 */ "OpSubgroup2DBlockLoadINTEL\000"
2109 /* 3141 */ "OpCooperativeMatrixLoadCheckedINTEL\000"
2110 /* 3177 */ "OpCooperativeMatrixStoreCheckedINTEL\000"
2111 /* 3214 */ "OpCooperativeMatrixConstructCheckedINTEL\000"
2112 /* 3255 */ "OpSpecConstantCompositeContinuedINTEL\000"
2113 /* 3293 */ "OpConstantCompositeContinuedINTEL\000"
2114 /* 3327 */ "OpTypeStructContinuedINTEL\000"
2115 /* 3354 */ "OpCompositeConstructContinuedINTEL\000"
2116 /* 3389 */ "OpCooperativeMatrixGetElementCoordINTEL\000"
2117 /* 3429 */ "OpConvertHandleToSampledImageINTEL\000"
2118 /* 3464 */ "OpConvertHandleToImageINTEL\000"
2119 /* 3492 */ "OpSubgroupShuffleINTEL\000"
2120 /* 3515 */ "OpPredicatedStoreINTEL\000"
2121 /* 3538 */ "OpSubgroup2DBlockStoreINTEL\000"
2122 /* 3566 */ "OpSubgroup2DBlockLoadTransposeINTEL\000"
2123 /* 3602 */ "OpSubgroupMatrixMultiplyAccumulateINTEL\000"
2124 /* 3642 */ "OpSubgroupImageMediaBlockWriteINTEL\000"
2125 /* 3678 */ "OpSubgroupImageBlockWriteINTEL\000"
2126 /* 3709 */ "OpSubgroupBlockWriteINTEL\000"
2127 /* 3735 */ "OpControlBarrierArriveINTEL\000"
2128 /* 3763 */ "OpSubgroup2DBlockPrefetchINTEL\000"
2129 /* 3794 */ "OpCooperativeMatrixPrefetchINTEL\000"
2130 /* 3827 */ "OpAliasScopeDeclINTEL\000"
2131 /* 3849 */ "OpAliasDomainDeclINTEL\000"
2132 /* 3872 */ "OpAliasScopeListDeclINTEL\000"
2133 /* 3898 */ "OpAsmCallINTEL\000"
2134 /* 3913 */ "OpFunctionPointerCallINTEL\000"
2135 /* 3940 */ "OpLoopControlINTEL\000"
2136 /* 3959 */ "OpSubgroup2DBlockLoadTransformINTEL\000"
2137 /* 3995 */ "OpAsmINTEL\000"
2138 /* 4006 */ "OpBitwiseFunctionINTEL\000"
2139 /* 4029 */ "OpSubgroupShuffleDownINTEL\000"
2140 /* 4056 */ "OpSubgroupShuffleUpINTEL\000"
2141 /* 4081 */ "OpPtrCastToCrossWorkgroupINTEL\000"
2142 /* 4112 */ "OpMaskedGatherINTEL\000"
2143 /* 4132 */ "OpConvertHandleToSamplerINTEL\000"
2144 /* 4162 */ "OpConstantFunctionPointerINTEL\000"
2145 /* 4193 */ "OpMaskedScatterINTEL\000"
2146 /* 4214 */ "OpSubgroupShuffleXorINTEL\000"
2147 /* 4240 */ "OpCrossWorkgroupCastToPtrINTEL\000"
2148 /* 4271 */ "OpAsmTargetINTEL\000"
2149 /* 4288 */ "OpControlBarrierWaitINTEL\000"
2150 /* 4314 */ "OpVariableLengthArrayINTEL\000"
2151 /* 4341 */ "OpRestoreMemoryINTEL\000"
2152 /* 4362 */ "OpSaveMemoryINTEL\000"
2153 /* 4380 */ "G_FSHL\000"
2154 /* 4387 */ "G_SHL\000"
2155 /* 4393 */ "G_FCEIL\000"
2156 /* 4401 */ "G_SAVGCEIL\000"
2157 /* 4412 */ "G_UAVGCEIL\000"
2158 /* 4423 */ "PATCHABLE_TAIL_CALL\000"
2159 /* 4443 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2160 /* 4470 */ "PATCHABLE_EVENT_CALL\000"
2161 /* 4491 */ "FENTRY_CALL\000"
2162 /* 4503 */ "KILL\000"
2163 /* 4508 */ "G_CONSTANT_POOL\000"
2164 /* 4524 */ "G_ROTL\000"
2165 /* 4531 */ "G_VECREDUCE_FMUL\000"
2166 /* 4548 */ "G_FMUL\000"
2167 /* 4555 */ "G_VECREDUCE_SEQ_FMUL\000"
2168 /* 4576 */ "G_STRICT_FMUL\000"
2169 /* 4590 */ "G_CLMUL\000"
2170 /* 4598 */ "G_VECREDUCE_MUL\000"
2171 /* 4614 */ "G_MUL\000"
2172 /* 4620 */ "G_FREM\000"
2173 /* 4627 */ "G_STRICT_FREM\000"
2174 /* 4641 */ "G_SREM\000"
2175 /* 4648 */ "G_UREM\000"
2176 /* 4655 */ "G_SDIVREM\000"
2177 /* 4665 */ "G_UDIVREM\000"
2178 /* 4675 */ "INLINEASM\000"
2179 /* 4685 */ "G_VECREDUCE_FMINIMUM\000"
2180 /* 4706 */ "G_FMINIMUM\000"
2181 /* 4717 */ "G_ATOMICRMW_FMINIMUM\000"
2182 /* 4738 */ "G_VECREDUCE_FMAXIMUM\000"
2183 /* 4759 */ "G_FMAXIMUM\000"
2184 /* 4770 */ "G_ATOMICRMW_FMAXIMUM\000"
2185 /* 4791 */ "G_VECREDUCE_FMINIMUMNUM\000"
2186 /* 4815 */ "G_FMINIMUMNUM\000"
2187 /* 4829 */ "G_ATOMICRMW_FMINIMUMNUM\000"
2188 /* 4853 */ "G_VECREDUCE_FMAXIMUMNUM\000"
2189 /* 4877 */ "G_FMAXIMUMNUM\000"
2190 /* 4891 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
2191 /* 4915 */ "G_FMINNUM\000"
2192 /* 4925 */ "G_FMAXNUM\000"
2193 /* 4935 */ "G_FATAN\000"
2194 /* 4943 */ "G_FTAN\000"
2195 /* 4950 */ "G_INTRINSIC_ROUNDEVEN\000"
2196 /* 4972 */ "G_ASSERT_ALIGN\000"
2197 /* 4987 */ "G_FCOPYSIGN\000"
2198 /* 4999 */ "G_VECREDUCE_FMIN\000"
2199 /* 5016 */ "G_ATOMICRMW_FMIN\000"
2200 /* 5033 */ "G_VECREDUCE_SMIN\000"
2201 /* 5050 */ "G_SMIN\000"
2202 /* 5057 */ "G_VECREDUCE_UMIN\000"
2203 /* 5074 */ "G_UMIN\000"
2204 /* 5081 */ "G_ATOMICRMW_UMIN\000"
2205 /* 5098 */ "G_ATOMICRMW_MIN\000"
2206 /* 5114 */ "G_FASIN\000"
2207 /* 5122 */ "G_FSIN\000"
2208 /* 5129 */ "CFI_INSTRUCTION\000"
2209 /* 5145 */ "G_CTLZ_ZERO_POISON\000"
2210 /* 5164 */ "G_CTTZ_ZERO_POISON\000"
2211 /* 5183 */ "G_SSUBO\000"
2212 /* 5191 */ "G_USUBO\000"
2213 /* 5199 */ "G_SADDO\000"
2214 /* 5207 */ "G_UADDO\000"
2215 /* 5215 */ "JUMP_TABLE_DEBUG_INFO\000"
2216 /* 5237 */ "G_SMULO\000"
2217 /* 5245 */ "G_UMULO\000"
2218 /* 5253 */ "G_BZERO\000"
2219 /* 5261 */ "STACKMAP\000"
2220 /* 5270 */ "G_DEBUGTRAP\000"
2221 /* 5282 */ "G_UBSANTRAP\000"
2222 /* 5294 */ "G_TRAP\000"
2223 /* 5301 */ "G_ATOMICRMW_UDEC_WRAP\000"
2224 /* 5323 */ "G_ATOMICRMW_UINC_WRAP\000"
2225 /* 5345 */ "G_BSWAP\000"
2226 /* 5353 */ "G_SITOFP\000"
2227 /* 5362 */ "G_UITOFP\000"
2228 /* 5371 */ "G_FCMP\000"
2229 /* 5378 */ "G_STRICT_FCMP\000"
2230 /* 5392 */ "G_ICMP\000"
2231 /* 5399 */ "G_SCMP\000"
2232 /* 5406 */ "G_UCMP\000"
2233 /* 5413 */ "CONVERGENCECTRL_LOOP\000"
2234 /* 5434 */ "G_CTPOP\000"
2235 /* 5442 */ "PATCHABLE_OP\000"
2236 /* 5455 */ "FAULTING_OP\000"
2237 /* 5467 */ "PREALLOCATED_SETUP\000"
2238 /* 5486 */ "G_FLDEXP\000"
2239 /* 5495 */ "G_STRICT_FLDEXP\000"
2240 /* 5511 */ "G_FEXP\000"
2241 /* 5518 */ "G_FFREXP\000"
2242 /* 5527 */ "G_BR\000"
2243 /* 5532 */ "INLINEASM_BR\000"
2244 /* 5545 */ "G_BLOCK_ADDR\000"
2245 /* 5558 */ "MEMBARRIER\000"
2246 /* 5569 */ "G_CONSTANT_FOLD_BARRIER\000"
2247 /* 5593 */ "PATCHABLE_FUNCTION_ENTER\000"
2248 /* 5618 */ "G_READCYCLECOUNTER\000"
2249 /* 5637 */ "G_READSTEADYCOUNTER\000"
2250 /* 5657 */ "G_READ_REGISTER\000"
2251 /* 5673 */ "G_WRITE_REGISTER\000"
2252 /* 5690 */ "OpFmaKHR\000"
2253 /* 5699 */ "OpCooperativeMatrixLoadKHR\000"
2254 /* 5726 */ "OpCooperativeMatrixMulAddKHR\000"
2255 /* 5755 */ "OpGroupBitwiseAndKHR\000"
2256 /* 5776 */ "OpGroupLogicalAndKHR\000"
2257 /* 5797 */ "OpUntypedVariableKHR\000"
2258 /* 5818 */ "OpCooperativeMatrixStoreKHR\000"
2259 /* 5846 */ "OpGroupNonUniformRotateKHR\000"
2260 /* 5873 */ "OpAssumeTrueKHR\000"
2261 /* 5889 */ "OpFreezeKHR\000"
2262 /* 5901 */ "OpUntypedPrefetchKHR\000"
2263 /* 5922 */ "OpCooperativeMatrixLengthKHR\000"
2264 /* 5951 */ "OpReadClockKHR\000"
2265 /* 5966 */ "OpGroupFMulKHR\000"
2266 /* 5981 */ "OpGroupIMulKHR\000"
2267 /* 5996 */ "OpUntypedAccessChainKHR\000"
2268 /* 6020 */ "OpUntypedPtrAccessChainKHR\000"
2269 /* 6047 */ "OpUntypedInBoundsPtrAccessChainKHR\000"
2270 /* 6082 */ "OpUntypedInBoundsAccessChainKHR\000"
2271 /* 6114 */ "OpPoisonKHR\000"
2272 /* 6126 */ "OpGroupBitwiseOrKHR\000"
2273 /* 6146 */ "OpGroupLogicalOrKHR\000"
2274 /* 6166 */ "OpTypeUntypedPointerKHR\000"
2275 /* 6190 */ "OpGroupBitwiseXorKHR\000"
2276 /* 6211 */ "OpGroupLogicalXorKHR\000"
2277 /* 6232 */ "OpExpectKHR\000"
2278 /* 6244 */ "OpAbortKHR\000"
2279 /* 6255 */ "OpTypeCooperativeMatrixKHR\000"
2280 /* 6282 */ "OpUntypedGroupAsyncCopyKHR\000"
2281 /* 6309 */ "G_ASHR\000"
2282 /* 6316 */ "G_FSHR\000"
2283 /* 6323 */ "G_LSHR\000"
2284 /* 6330 */ "CONVERGENCECTRL_ANCHOR\000"
2285 /* 6353 */ "G_FFLOOR\000"
2286 /* 6362 */ "G_SAVGFLOOR\000"
2287 /* 6374 */ "G_UAVGFLOOR\000"
2288 /* 6386 */ "G_EXTRACT_SUBVECTOR\000"
2289 /* 6406 */ "G_INSERT_SUBVECTOR\000"
2290 /* 6425 */ "G_BUILD_VECTOR\000"
2291 /* 6440 */ "G_SHUFFLE_VECTOR\000"
2292 /* 6457 */ "G_STEP_VECTOR\000"
2293 /* 6471 */ "G_SPLAT_VECTOR\000"
2294 /* 6486 */ "G_VECREDUCE_XOR\000"
2295 /* 6502 */ "G_XOR\000"
2296 /* 6508 */ "G_ATOMICRMW_XOR\000"
2297 /* 6524 */ "G_VECREDUCE_OR\000"
2298 /* 6539 */ "G_OR\000"
2299 /* 6544 */ "G_ATOMICRMW_OR\000"
2300 /* 6559 */ "G_ROTR\000"
2301 /* 6566 */ "G_INTTOPTR\000"
2302 /* 6577 */ "G_FABS\000"
2303 /* 6584 */ "G_ABS\000"
2304 /* 6590 */ "G_ABDS\000"
2305 /* 6597 */ "G_UNMERGE_VALUES\000"
2306 /* 6614 */ "G_MERGE_VALUES\000"
2307 /* 6629 */ "G_CTLS\000"
2308 /* 6636 */ "G_FACOS\000"
2309 /* 6644 */ "G_FCOS\000"
2310 /* 6651 */ "G_FSINCOS\000"
2311 /* 6661 */ "G_STRICT_FCMPS\000"
2312 /* 6676 */ "G_CONCAT_VECTORS\000"
2313 /* 6693 */ "COPY_TO_REGCLASS\000"
2314 /* 6710 */ "G_IS_FPCLASS\000"
2315 /* 6723 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2316 /* 6753 */ "G_VECTOR_COMPRESS\000"
2317 /* 6771 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2318 /* 6798 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2319 /* 6836 */ "G_TRUNC_SSAT_S\000"
2320 /* 6851 */ "OpFSubS\000"
2321 /* 6859 */ "OpStrictFSubS\000"
2322 /* 6873 */ "OpISubS\000"
2323 /* 6881 */ "OpShiftRightArithmeticS\000"
2324 /* 6905 */ "OpFAddS\000"
2325 /* 6913 */ "OpStrictFAddS\000"
2326 /* 6927 */ "OpIAddS\000"
2327 /* 6935 */ "OpBitwiseAndS\000"
2328 /* 6949 */ "OpUModS\000"
2329 /* 6957 */ "OpShiftLeftLogicalS\000"
2330 /* 6977 */ "OpShiftRightLogicalS\000"
2331 /* 6998 */ "OpFMulS\000"
2332 /* 7006 */ "OpStrictFMulS\000"
2333 /* 7020 */ "OpIMulS\000"
2334 /* 7028 */ "OpFRemS\000"
2335 /* 7036 */ "OpStrictFRemS\000"
2336 /* 7050 */ "OpSRemS\000"
2337 /* 7058 */ "OpConvertFToS\000"
2338 /* 7072 */ "OpSatConvertUToS\000"
2339 /* 7089 */ "OpBitwiseOrS\000"
2340 /* 7102 */ "OpBitwiseXorS\000"
2341 /* 7116 */ "OpFDivS\000"
2342 /* 7124 */ "OpStrictFDivS\000"
2343 /* 7138 */ "OpSDivS\000"
2344 /* 7146 */ "OpUDivS\000"
2345 /* 7154 */ "OpISubBorrowS\000"
2346 /* 7168 */ "OpIAddCarryS\000"
2347 /* 7181 */ "G_SSUBSAT\000"
2348 /* 7191 */ "G_USUBSAT\000"
2349 /* 7201 */ "G_SADDSAT\000"
2350 /* 7211 */ "G_UADDSAT\000"
2351 /* 7221 */ "G_SSHLSAT\000"
2352 /* 7231 */ "G_USHLSAT\000"
2353 /* 7241 */ "G_SMULFIXSAT\000"
2354 /* 7254 */ "G_UMULFIXSAT\000"
2355 /* 7267 */ "G_SDIVFIXSAT\000"
2356 /* 7280 */ "G_UDIVFIXSAT\000"
2357 /* 7293 */ "G_ATOMICRMW_USUB_SAT\000"
2358 /* 7314 */ "G_FPTOSI_SAT\000"
2359 /* 7327 */ "G_FPTOUI_SAT\000"
2360 /* 7340 */ "G_EXTRACT\000"
2361 /* 7350 */ "G_SELECT\000"
2362 /* 7359 */ "G_BRINDIRECT\000"
2363 /* 7372 */ "PATCHABLE_RET\000"
2364 /* 7386 */ "G_MEMSET\000"
2365 /* 7395 */ "PATCHABLE_FUNCTION_EXIT\000"
2366 /* 7419 */ "G_BRJT\000"
2367 /* 7426 */ "G_EXTRACT_VECTOR_ELT\000"
2368 /* 7447 */ "G_INSERT_VECTOR_ELT\000"
2369 /* 7467 */ "G_FCONSTANT\000"
2370 /* 7479 */ "G_CONSTANT\000"
2371 /* 7490 */ "G_INTRINSIC_CONVERGENT\000"
2372 /* 7513 */ "STATEPOINT\000"
2373 /* 7524 */ "PATCHPOINT\000"
2374 /* 7535 */ "G_PTRTOINT\000"
2375 /* 7546 */ "G_FRINT\000"
2376 /* 7554 */ "G_INTRINSIC_LLRINT\000"
2377 /* 7573 */ "G_INTRINSIC_LRINT\000"
2378 /* 7591 */ "G_FNEARBYINT\000"
2379 /* 7604 */ "G_VASTART\000"
2380 /* 7614 */ "LIFETIME_START\000"
2381 /* 7629 */ "G_INVOKE_REGION_START\000"
2382 /* 7651 */ "G_INSERT\000"
2383 /* 7660 */ "G_FSQRT\000"
2384 /* 7668 */ "G_STRICT_FSQRT\000"
2385 /* 7683 */ "G_BITCAST\000"
2386 /* 7693 */ "G_ADDRSPACE_CAST\000"
2387 /* 7710 */ "DBG_VALUE_LIST\000"
2388 /* 7725 */ "G_FPEXT\000"
2389 /* 7733 */ "G_SEXT\000"
2390 /* 7740 */ "G_ASSERT_SEXT\000"
2391 /* 7754 */ "G_ANYEXT\000"
2392 /* 7763 */ "G_ZEXT\000"
2393 /* 7770 */ "G_ASSERT_ZEXT\000"
2394 /* 7784 */ "OpTypeVectorIdEXT\000"
2395 /* 7802 */ "OpAtomicFAddEXT\000"
2396 /* 7818 */ "OpArithmeticFenceEXT\000"
2397 /* 7839 */ "OpAtomicFMinEXT\000"
2398 /* 7855 */ "OpAtomicFMaxEXT\000"
2399 /* 7871 */ "G_ABDU\000"
2400 /* 7878 */ "G_TRUNC_SSAT_U\000"
2401 /* 7893 */ "G_TRUNC_USAT_U\000"
2402 /* 7908 */ "OpConvertFToU\000"
2403 /* 7922 */ "OpSatConvertSToU\000"
2404 /* 7939 */ "OpConvertPtrToU\000"
2405 /* 7955 */ "G_FDIV\000"
2406 /* 7962 */ "G_STRICT_FDIV\000"
2407 /* 7976 */ "G_SDIV\000"
2408 /* 7983 */ "G_UDIV\000"
2409 /* 7990 */ "G_GET_FPENV\000"
2410 /* 8002 */ "G_RESET_FPENV\000"
2411 /* 8016 */ "G_SET_FPENV\000"
2412 /* 8028 */ "OpTypeAccelerationStructureNV\000"
2413 /* 8058 */ "OpImageSampleFootprintNV\000"
2414 /* 8083 */ "OpTypeCooperativeMatrixNV\000"
2415 /* 8109 */ "OpFSubV\000"
2416 /* 8117 */ "OpStrictFSubV\000"
2417 /* 8131 */ "OpISubV\000"
2418 /* 8139 */ "OpShiftRightArithmeticV\000"
2419 /* 8163 */ "OpFAddV\000"
2420 /* 8171 */ "OpStrictFAddV\000"
2421 /* 8185 */ "OpIAddV\000"
2422 /* 8193 */ "OpBitwiseAndV\000"
2423 /* 8207 */ "OpUModV\000"
2424 /* 8215 */ "OpFNegateV\000"
2425 /* 8226 */ "OpShiftLeftLogicalV\000"
2426 /* 8246 */ "OpShiftRightLogicalV\000"
2427 /* 8267 */ "OpFMulV\000"
2428 /* 8275 */ "OpStrictFMulV\000"
2429 /* 8289 */ "OpIMulV\000"
2430 /* 8297 */ "OpFRemV\000"
2431 /* 8305 */ "OpStrictFRemV\000"
2432 /* 8319 */ "OpSRemV\000"
2433 /* 8327 */ "OpBitwiseOrV\000"
2434 /* 8340 */ "OpBitwiseXorV\000"
2435 /* 8354 */ "OpFDivV\000"
2436 /* 8362 */ "OpStrictFDivV\000"
2437 /* 8376 */ "OpSDivV\000"
2438 /* 8384 */ "OpUDivV\000"
2439 /* 8392 */ "OpISubBorrowV\000"
2440 /* 8406 */ "OpIAddCarryV\000"
2441 /* 8419 */ "G_FPOW\000"
2442 /* 8426 */ "G_VECREDUCE_FMAX\000"
2443 /* 8443 */ "G_ATOMICRMW_FMAX\000"
2444 /* 8460 */ "G_VECREDUCE_SMAX\000"
2445 /* 8477 */ "G_SMAX\000"
2446 /* 8484 */ "G_VECREDUCE_UMAX\000"
2447 /* 8501 */ "G_UMAX\000"
2448 /* 8508 */ "G_ATOMICRMW_UMAX\000"
2449 /* 8525 */ "G_ATOMICRMW_MAX\000"
2450 /* 8541 */ "G_FRAME_INDEX\000"
2451 /* 8555 */ "G_SBFX\000"
2452 /* 8562 */ "G_UBFX\000"
2453 /* 8569 */ "G_SMULFIX\000"
2454 /* 8579 */ "G_UMULFIX\000"
2455 /* 8589 */ "G_SDIVFIX\000"
2456 /* 8599 */ "G_UDIVFIX\000"
2457 /* 8609 */ "G_MEMCPY\000"
2458 /* 8618 */ "COPY\000"
2459 /* 8623 */ "CONVERGENCECTRL_ENTRY\000"
2460 /* 8645 */ "G_CTLZ\000"
2461 /* 8652 */ "G_CTTZ\000"
2462 /* 8659 */ "OpAtomicISub\000"
2463 /* 8672 */ "OpVectorExtractDynamic\000"
2464 /* 8695 */ "OpVectorInsertDynamic\000"
2465 /* 8717 */ "OpPtrCastToGeneric\000"
2466 /* 8736 */ "OpExecutionModeId\000"
2467 /* 8754 */ "OpDecorateId\000"
2468 /* 8767 */ "OpIsValidReserveId\000"
2469 /* 8786 */ "OpTypeReserveId\000"
2470 /* 8802 */ "OpImageRead\000"
2471 /* 8814 */ "OpImageSparseRead\000"
2472 /* 8832 */ "OpAtomicLoad\000"
2473 /* 8845 */ "OpLoad\000"
2474 /* 8852 */ "OpGroupNonUniformFAdd\000"
2475 /* 8874 */ "OpGroupFAdd\000"
2476 /* 8886 */ "OpAtomicIAdd\000"
2477 /* 8899 */ "OpGroupNonUniformIAdd\000"
2478 /* 8921 */ "OpGroupIAdd\000"
2479 /* 8933 */ "OpSMulExtended\000"
2480 /* 8948 */ "OpUMulExtended\000"
2481 /* 8963 */ "OpOrdered\000"
2482 /* 8973 */ "OpUnordered\000"
2483 /* 8985 */ "OpModuleProcessed\000"
2484 /* 9003 */ "OpSourceContinued\000"
2485 /* 9021 */ "OpCopyMemorySized\000"
2486 /* 9039 */ "OpTypeVoid\000"
2487 /* 9050 */ "OpAtomicAnd\000"
2488 /* 9062 */ "OpGroupNonUniformBitwiseAnd\000"
2489 /* 9090 */ "OpGroupNonUniformLogicalAnd\000"
2490 /* 9118 */ "OpLogicalAnd\000"
2491 /* 9131 */ "OpFunctionEnd\000"
2492 /* 9145 */ "OpSelectSFSCond\000"
2493 /* 9161 */ "OpSelectVFSCond\000"
2494 /* 9177 */ "OpSelectSISCond\000"
2495 /* 9193 */ "OpSelectVISCond\000"
2496 /* 9209 */ "OpSelectSPSCond\000"
2497 /* 9225 */ "OpSelectVPSCond\000"
2498 /* 9241 */ "OpSelectSFVCond\000"
2499 /* 9257 */ "OpSelectVFVCond\000"
2500 /* 9273 */ "OpSelectSIVCond\000"
2501 /* 9289 */ "OpSelectVIVCond\000"
2502 /* 9305 */ "OpSelectSPVCond\000"
2503 /* 9321 */ "OpSelectVPVCond\000"
2504 /* 9337 */ "OpImageQuerySizeLod\000"
2505 /* 9357 */ "OpImageSampleImplicitLod\000"
2506 /* 9382 */ "OpImageSparseSampleImplicitLod\000"
2507 /* 9413 */ "OpImageSampleDrefImplicitLod\000"
2508 /* 9442 */ "OpImageSparseSampleDrefImplicitLod\000"
2509 /* 9477 */ "OpImageSampleProjDrefImplicitLod\000"
2510 /* 9510 */ "OpImageSparseSampleProjDrefImplicitLod\000"
2511 /* 9549 */ "OpImageSampleProjImplicitLod\000"
2512 /* 9578 */ "OpImageSparseSampleProjImplicitLod\000"
2513 /* 9613 */ "OpImageSampleExplicitLod\000"
2514 /* 9638 */ "OpImageSparseSampleExplicitLod\000"
2515 /* 9669 */ "OpImageSampleDrefExplicitLod\000"
2516 /* 9698 */ "OpImageSparseSampleDrefExplicitLod\000"
2517 /* 9733 */ "OpImageSampleProjDrefExplicitLod\000"
2518 /* 9766 */ "OpImageSparseSampleProjDrefExplicitLod\000"
2519 /* 9805 */ "OpImageSampleProjExplicitLod\000"
2520 /* 9834 */ "OpImageSparseSampleProjExplicitLod\000"
2521 /* 9869 */ "OpImageQueryLod\000"
2522 /* 9885 */ "OpFMod\000"
2523 /* 9892 */ "OpSMod\000"
2524 /* 9899 */ "OpSource\000"
2525 /* 9908 */ "OpExecutionMode\000"
2526 /* 9924 */ "OpTypeSampledImage\000"
2527 /* 9943 */ "OpSampledImage\000"
2528 /* 9958 */ "OpTypeImage\000"
2529 /* 9970 */ "OpImage\000"
2530 /* 9978 */ "OpTypePipeStorage\000"
2531 /* 9996 */ "OpBuildNDRange\000"
2532 /* 10011 */ "OpAtomicExchange\000"
2533 /* 10028 */ "OpAtomicCompareExchange\000"
2534 /* 10052 */ "OpSelectionMerge\000"
2535 /* 10069 */ "OpLoopMerge\000"
2536 /* 10081 */ "OpUnreachable\000"
2537 /* 10095 */ "OpVariable\000"
2538 /* 10106 */ "OpGroupNonUniformShuffle\000"
2539 /* 10131 */ "OpVectorShuffle\000"
2540 /* 10147 */ "OpName\000"
2541 /* 10154 */ "OpMemberName\000"
2542 /* 10167 */ "OpFwidthFine\000"
2543 /* 10180 */ "OpDPdxFine\000"
2544 /* 10191 */ "OpDPdyFine\000"
2545 /* 10202 */ "OpNoLine\000"
2546 /* 10211 */ "OpLine\000"
2547 /* 10218 */ "OpReservedReadPipe\000"
2548 /* 10237 */ "OpReadPipe\000"
2549 /* 10248 */ "OpCommitReadPipe\000"
2550 /* 10265 */ "OpGroupCommitReadPipe\000"
2551 /* 10287 */ "OpTypePipe\000"
2552 /* 10298 */ "OpReservedWritePipe\000"
2553 /* 10318 */ "OpWritePipe\000"
2554 /* 10330 */ "OpCommitWritePipe\000"
2555 /* 10348 */ "OpGroupCommitWritePipe\000"
2556 /* 10371 */ "UNKNOWN_type\000"
2557 /* 10384 */ "OpAtomicStore\000"
2558 /* 10398 */ "OpStore\000"
2559 /* 10406 */ "OpSpecConstantFalse\000"
2560 /* 10426 */ "OpConstantFalse\000"
2561 /* 10442 */ "OpTranspose\000"
2562 /* 10454 */ "OpFwidthCoarse\000"
2563 /* 10469 */ "OpDPdxCoarse\000"
2564 /* 10482 */ "OpDPdyCoarse\000"
2565 /* 10495 */ "OpBitReverse\000"
2566 /* 10508 */ "OpFNegate\000"
2567 /* 10518 */ "OpSNegate\000"
2568 /* 10528 */ "OpDecorate\000"
2569 /* 10539 */ "OpMemberDecorate\000"
2570 /* 10556 */ "OpIsFinite\000"
2571 /* 10567 */ "OpImageWrite\000"
2572 /* 10580 */ "OpSpecConstantComposite\000"
2573 /* 10604 */ "OpConstantComposite\000"
2574 /* 10624 */ "OpTypeQueue\000"
2575 /* 10636 */ "OpGetDefaultQueue\000"
2576 /* 10654 */ "OpReturnValue\000"
2577 /* 10668 */ "OpTypeOpaque\000"
2578 /* 10681 */ "OpSpecConstantTrue\000"
2579 /* 10700 */ "OpConstantTrue\000"
2580 /* 10715 */ "OpEndPrimitive\000"
2581 /* 10730 */ "OpEndStreamPrimitive\000"
2582 /* 10751 */ "OpImageQuerySize\000"
2583 /* 10768 */ "OpNamedBarrierInitialize\000"
2584 /* 10793 */ "OpSizeOf\000"
2585 /* 10802 */ "OpUndef\000"
2586 /* 10810 */ "OpPtrDiff\000"
2587 /* 10820 */ "OpIsInf\000"
2588 /* 10828 */ "OpDecorateString\000"
2589 /* 10845 */ "OpMemberDecorateString\000"
2590 /* 10868 */ "OpString\000"
2591 /* 10877 */ "OpBranch\000"
2592 /* 10886 */ "OpImageFetch\000"
2593 /* 10899 */ "OpImageSparseFetch\000"
2594 /* 10918 */ "OpSwitch\000"
2595 /* 10927 */ "OpFwidth\000"
2596 /* 10936 */ "OpArrayLength\000"
2597 /* 10950 */ "OpPhi\000"
2598 /* 10956 */ "OpAtomicCompareExchangeWeak\000"
2599 /* 10984 */ "OpCopyLogical\000"
2600 /* 10998 */ "OpIsNormal\000"
2601 /* 11009 */ "OpBranchConditional\000"
2602 /* 11029 */ "OpIEqual\000"
2603 /* 11038 */ "OpFOrdEqual\000"
2604 /* 11050 */ "OpFUnordEqual\000"
2605 /* 11064 */ "OpLogicalEqual\000"
2606 /* 11079 */ "OpGroupNonUniformAllEqual\000"
2607 /* 11105 */ "OpSGreaterThanEqual\000"
2608 /* 11125 */ "OpUGreaterThanEqual\000"
2609 /* 11145 */ "OpFOrdGreaterThanEqual\000"
2610 /* 11168 */ "OpFUnordGreaterThanEqual\000"
2611 /* 11193 */ "OpSLessThanEqual\000"
2612 /* 11210 */ "OpULessThanEqual\000"
2613 /* 11227 */ "OpFOrdLessThanEqual\000"
2614 /* 11247 */ "OpFUnordLessThanEqual\000"
2615 /* 11269 */ "OpPtrEqual\000"
2616 /* 11280 */ "OpINotEqual\000"
2617 /* 11292 */ "OpFOrdNotEqual\000"
2618 /* 11307 */ "OpFUnordNotEqual\000"
2619 /* 11324 */ "OpLogicalNotEqual\000"
2620 /* 11342 */ "OpPtrNotEqual\000"
2621 /* 11356 */ "OpLabel\000"
2622 /* 11364 */ "OpMemoryModel\000"
2623 /* 11378 */ "OpEnqueueKernel\000"
2624 /* 11394 */ "OpGroupNonUniformAll\000"
2625 /* 11415 */ "OpAll\000"
2626 /* 11421 */ "OpGroupAll\000"
2627 /* 11432 */ "OpFunctionCall\000"
2628 /* 11447 */ "OpKill\000"
2629 /* 11454 */ "OpConstantNull\000"
2630 /* 11469 */ "OpTypeBool\000"
2631 /* 11480 */ "OpGroupNonUniformFMul\000"
2632 /* 11502 */ "OpGroupNonUniformIMul\000"
2633 /* 11524 */ "OpIsNan\000"
2634 /* 11532 */ "OpSGreaterThan\000"
2635 /* 11547 */ "OpUGreaterThan\000"
2636 /* 11562 */ "OpFOrdGreaterThan\000"
2637 /* 11580 */ "OpFUnordGreaterThan\000"
2638 /* 11600 */ "OpSLessThan\000"
2639 /* 11612 */ "OpULessThan\000"
2640 /* 11624 */ "OpFOrdLessThan\000"
2641 /* 11639 */ "OpFUnordLessThan\000"
2642 /* 11656 */ "OpGroupNonUniformFMin\000"
2643 /* 11678 */ "OpGroupFMin\000"
2644 /* 11690 */ "OpAtomicSMin\000"
2645 /* 11703 */ "OpGroupNonUniformSMin\000"
2646 /* 11725 */ "OpGroupSMin\000"
2647 /* 11737 */ "OpAtomicUMin\000"
2648 /* 11750 */ "OpGroupNonUniformUMin\000"
2649 /* 11772 */ "OpGroupUMin\000"
2650 /* 11784 */ "OpAccessChain\000"
2651 /* 11798 */ "OpPtrAccessChain\000"
2652 /* 11815 */ "OpInBoundsPtrAccessChain\000"
2653 /* 11840 */ "OpInBoundsAccessChain\000"
2654 /* 11862 */ "OpSourceExtension\000"
2655 /* 11880 */ "OpExtension\000"
2656 /* 11892 */ "OpDemoteToHelperInvocation\000"
2657 /* 11919 */ "OpTypeFunction\000"
2658 /* 11934 */ "OpFunction\000"
2659 /* 11945 */ "OpReturn\000"
2660 /* 11954 */ "OpGroupNonUniformShuffleDown\000"
2661 /* 11983 */ "OpCaptureEventProfilingInfo\000"
2662 /* 12011 */ "OpSpecConstantOp\000"
2663 /* 12028 */ "OpGroupNonUniformShuffleUp\000"
2664 /* 12055 */ "OpGroupNonUniformQuadSwap\000"
2665 /* 12081 */ "OpNop\000"
2666 /* 12087 */ "OpLifetimeStop\000"
2667 /* 12102 */ "OpAtomicOr\000"
2668 /* 12113 */ "OpGroupNonUniformBitwiseOr\000"
2669 /* 12140 */ "OpGroupNonUniformLogicalOr\000"
2670 /* 12167 */ "OpLogicalOr\000"
2671 /* 12179 */ "OpAtomicFlagClear\000"
2672 /* 12197 */ "OpVectorTimesScalar\000"
2673 /* 12217 */ "OpMatrixTimesScalar\000"
2674 /* 12237 */ "OpImageQueryOrder\000"
2675 /* 12255 */ "OpImageGather\000"
2676 /* 12269 */ "OpImageSparseGather\000"
2677 /* 12289 */ "OpImageDrefGather\000"
2678 /* 12307 */ "OpImageSparseDrefGather\000"
2679 /* 12331 */ "OpTypeNamedBarrier\000"
2680 /* 12350 */ "OpMemoryNamedBarrier\000"
2681 /* 12371 */ "OpControlBarrier\000"
2682 /* 12388 */ "OpMemoryBarrier\000"
2683 /* 12404 */ "OpTypeSampler\000"
2684 /* 12418 */ "OpConstantSampler\000"
2685 /* 12436 */ "OpLessOrGreater\000"
2686 /* 12452 */ "OpFunctionParameter\000"
2687 /* 12472 */ "OpTypeForwardPointer\000"
2688 /* 12493 */ "OpTypePointer\000"
2689 /* 12507 */ "OpImageTexelPointer\000"
2690 /* 12527 */ "OpAtomicXor\000"
2691 /* 12539 */ "OpGroupNonUniformShuffleXor\000"
2692 /* 12567 */ "OpGroupNonUniformBitwiseXor\000"
2693 /* 12595 */ "OpGroupNonUniformLogicalXor\000"
2694 /* 12623 */ "OpTypeVector\000"
2695 /* 12636 */ "OpMatrixTimesVector\000"
2696 /* 12656 */ "OpConvertUToPtr\000"
2697 /* 12672 */ "OpGenericCastToPtr\000"
2698 /* 12691 */ "OpGenericPtrMemSemantics\000"
2699 /* 12716 */ "OpImageQuerySamples\000"
2700 /* 12736 */ "OpImageQueryLevels\000"
2701 /* 12755 */ "OpReserveReadPipePackets\000"
2702 /* 12780 */ "OpGroupReserveReadPipePackets\000"
2703 /* 12810 */ "OpReserveWritePipePackets\000"
2704 /* 12836 */ "OpGroupReserveWritePipePackets\000"
2705 /* 12867 */ "OpGetNumPipePackets\000"
2706 /* 12887 */ "OpGetMaxPipePackets\000"
2707 /* 12907 */ "OpGroupWaitEvents\000"
2708 /* 12925 */ "OpSetUserEventStatus\000"
2709 /* 12946 */ "OpSDotAccSat\000"
2710 /* 12959 */ "OpSUDotAccSat\000"
2711 /* 12973 */ "OpUDotAccSat\000"
2712 /* 12986 */ "OpImageQueryFormat\000"
2713 /* 13005 */ "OpTypeFloat\000"
2714 /* 13017 */ "OpBitFieldSExtract\000"
2715 /* 13036 */ "OpBitFieldUExtract\000"
2716 /* 13055 */ "OpCompositeExtract\000"
2717 /* 13074 */ "OpGroupNonUniformBallotBitExtract\000"
2718 /* 13108 */ "OpCopyObject\000"
2719 /* 13121 */ "OpGroupNonUniformElect\000"
2720 /* 13144 */ "OpOuterProduct\000"
2721 /* 13159 */ "OpTypeStruct\000"
2722 /* 13172 */ "OpCompositeConstruct\000"
2723 /* 13193 */ "OpAtomicFlagTestAndSet\000"
2724 /* 13216 */ "OpSignBitSet\000"
2725 /* 13229 */ "OpGenericCastToPtrExplicit\000"
2726 /* 13256 */ "OpTypeInt\000"
2727 /* 13266 */ "OpSpecConstant\000"
2728 /* 13281 */ "OpImageSparseTexelsResident\000"
2729 /* 13309 */ "OpAtomicIDecrement\000"
2730 /* 13328 */ "OpAtomicIIncrement\000"
2731 /* 13347 */ "OpIsValidEvent\000"
2732 /* 13362 */ "OpTypeDeviceEvent\000"
2733 /* 13380 */ "OpTypeEvent\000"
2734 /* 13392 */ "OpReleaseEvent\000"
2735 /* 13407 */ "OpRetainEvent\000"
2736 /* 13421 */ "OpCreateUserEvent\000"
2737 /* 13439 */ "OpEntryPoint\000"
2738 /* 13452 */ "OpBitCount\000"
2739 /* 13463 */ "OpGroupNonUniformBallotBitCount\000"
2740 /* 13495 */ "OpSDot\000"
2741 /* 13502 */ "OpSUDot\000"
2742 /* 13510 */ "OpUDot\000"
2743 /* 13517 */ "OpDot\000"
2744 /* 13523 */ "OpLogicalNot\000"
2745 /* 13536 */ "OpNot\000"
2746 /* 13542 */ "OpGroupNonUniformInverseBallot\000"
2747 /* 13573 */ "OpGroupNonUniformBallot\000"
2748 /* 13597 */ "OpLifetimeStart\000"
2749 /* 13613 */ "OpBitFieldInsert\000"
2750 /* 13630 */ "OpCompositeInsert\000"
2751 /* 13648 */ "OpFConvert\000"
2752 /* 13659 */ "OpSConvert\000"
2753 /* 13670 */ "OpUConvert\000"
2754 /* 13681 */ "OpExtInstImport\000"
2755 /* 13697 */ "OpGroupNonUniformBroadcast\000"
2756 /* 13724 */ "OpGroupBroadcast\000"
2757 /* 13741 */ "OpBitcast\000"
2758 /* 13751 */ "OpExtInst\000"
2759 /* 13761 */ "OpGroupNonUniformBroadcastFirst\000"
2760 /* 13793 */ "OpGroupNonUniformFMax\000"
2761 /* 13815 */ "OpGroupFMax\000"
2762 /* 13827 */ "OpAtomicSMax\000"
2763 /* 13840 */ "OpGroupNonUniformSMax\000"
2764 /* 13862 */ "OpGroupSMax\000"
2765 /* 13874 */ "OpAtomicUMax\000"
2766 /* 13887 */ "OpGroupNonUniformUMax\000"
2767 /* 13909 */ "OpGroupUMax\000"
2768 /* 13921 */ "OpDPdx\000"
2769 /* 13928 */ "OpEmitStreamVertex\000"
2770 /* 13947 */ "OpEmitVertex\000"
2771 /* 13960 */ "OpTypeMatrix\000"
2772 /* 13973 */ "OpVectorTimesMatrix\000"
2773 /* 13993 */ "OpMatrixTimesMatrix\000"
2774 /* 14013 */ "OpTypeRuntimeArray\000"
2775 /* 14032 */ "OpTypeArray\000"
2776 /* 14044 */ "OpDPdy\000"
2777 /* 14051 */ "OpGroupNonUniformAny\000"
2778 /* 14072 */ "OpAny\000"
2779 /* 14078 */ "OpGroupAny\000"
2780 /* 14089 */ "OpGroupAsyncCopy\000"
2781 /* 14106 */ "OpCopyMemory\000"
2782 /* 14119 */ "OpCapability\000"
2783};
2784#ifdef __GNUC__
2785#pragma GCC diagnostic pop
2786#endif
2787
2788extern const unsigned SPIRVInstrNameIndices[] = {
2789 2807U, 4675U, 5532U, 5129U, 2892U, 2873U, 2901U, 4503U,
2790 2600U, 2615U, 2526U, 2513U, 2642U, 6693U, 2389U, 7710U,
2791 2539U, 2803U, 2882U, 2116U, 8618U, 2849U, 2238U, 7614U,
2792 1943U, 2067U, 2104U, 5261U, 4491U, 7524U, 2050U, 5467U,
2793 2735U, 7513U, 2288U, 5455U, 5442U, 5593U, 7372U, 7395U,
2794 4423U, 4470U, 4443U, 2918U, 2380U, 5558U, 5215U, 2277U,
2795 8623U, 6330U, 5413U, 2437U, 7740U, 7770U, 4972U, 1856U,
2796 1555U, 4614U, 7976U, 7983U, 4641U, 4648U, 4655U, 4665U,
2797 1921U, 6539U, 6502U, 6590U, 7871U, 6374U, 4412U, 6362U,
2798 4401U, 2524U, 2805U, 8541U, 2399U, 2414U, 4508U, 7340U,
2799 6597U, 7651U, 6614U, 6425U, 1625U, 6676U, 7535U, 6566U,
2800 7683U, 2480U, 5569U, 2024U, 1599U, 2006U, 7573U, 7554U,
2801 4950U, 5618U, 5637U, 1757U, 1701U, 1731U, 1670U, 1742U,
2802 1682U, 1712U, 2359U, 2313U, 2343U, 6723U, 2656U, 2673U,
2803 1872U, 1561U, 1927U, 1888U, 6544U, 6508U, 8525U, 5098U,
2804 8508U, 5081U, 1823U, 1538U, 8443U, 5016U, 4770U, 4717U,
2805 4891U, 4829U, 5323U, 5301U, 1965U, 7293U, 2096U, 2752U,
2806 1956U, 7359U, 7629U, 1577U, 6771U, 7490U, 6798U, 7754U,
2807 1617U, 6836U, 7878U, 7893U, 7479U, 7467U, 7604U, 2727U,
2808 7733U, 2629U, 7763U, 4387U, 6323U, 6309U, 4380U, 6316U,
2809 6559U, 4524U, 5392U, 5371U, 5399U, 5406U, 7350U, 5207U,
2810 2137U, 5191U, 2088U, 5199U, 2129U, 5183U, 2080U, 5245U,
2811 5237U, 2771U, 2763U, 7211U, 7201U, 7191U, 7181U, 7231U,
2812 7221U, 8569U, 8579U, 7241U, 7254U, 8589U, 8599U, 7267U,
2813 7280U, 1781U, 1517U, 4548U, 59U, 1663U, 7955U, 4620U,
2814 2505U, 8419U, 2829U, 5511U, 35U, 9U, 2720U, 18U,
2815 0U, 5486U, 5518U, 2593U, 7725U, 1589U, 2811U, 2820U,
2816 5353U, 5362U, 7314U, 7327U, 6577U, 4987U, 6710U, 2489U,
2817 4915U, 4925U, 2186U, 2201U, 4706U, 4759U, 4815U, 4877U,
2818 7990U, 8016U, 8002U, 2145U, 2173U, 2158U, 2690U, 2705U,
2819 1862U, 2863U, 5050U, 8477U, 5074U, 8501U, 6584U, 1997U,
2820 1987U, 5527U, 7419U, 2216U, 6406U, 6386U, 7447U, 7426U,
2821 6440U, 6471U, 6457U, 6753U, 8652U, 5164U, 8645U, 5145U,
2822 6629U, 5434U, 5345U, 2367U, 4590U, 4393U, 6644U, 5122U,
2823 6651U, 4943U, 6636U, 5114U, 4935U, 26U, 2795U, 2787U,
2824 2779U, 7660U, 6353U, 7546U, 7591U, 7693U, 5545U, 2225U,
2825 1646U, 2458U, 2328U, 1809U, 1524U, 4576U, 7962U, 4627U,
2826 65U, 7668U, 5495U, 5378U, 6661U, 5657U, 5673U, 8609U,
2827 2261U, 2470U, 7386U, 5253U, 2245U, 5294U, 5270U, 5282U,
2828 1788U, 4555U, 1764U, 4531U, 8426U, 4999U, 4738U, 4685U,
2829 4853U, 4791U, 1840U, 4598U, 1905U, 6524U, 6486U, 8460U,
2830 5033U, 8484U, 5057U, 8555U, 8562U, 2301U, 10371U, 6244U,
2831 11784U, 3849U, 3827U, 3872U, 11415U, 14072U, 1044U, 674U,
2832 856U, 598U, 189U, 829U, 569U, 449U, 1376U, 1163U,
2833 1197U, 1257U, 1137U, 775U, 1403U, 321U, 106U, 217U,
2834 1018U, 134U, 244U, 373U, 1229U, 269U, 398U, 78U,
2835 926U, 162U, 543U, 803U, 1429U, 294U, 346U, 1284U,
2836 973U, 900U, 1108U, 744U, 646U, 1330U, 423U, 7818U,
2837 10936U, 3898U, 3995U, 4271U, 5873U, 9050U, 10028U, 10956U,
2838 10011U, 7802U, 7855U, 7839U, 12179U, 13193U, 8886U, 13309U,
2839 13328U, 8659U, 8832U, 12102U, 13827U, 11690U, 10384U, 13874U,
2840 11737U, 12527U, 13452U, 13613U, 13017U, 13036U, 10495U, 13741U,
2841 6935U, 8193U, 4006U, 7089U, 8327U, 7102U, 8340U, 10877U,
2842 11009U, 9996U, 14119U, 11983U, 10248U, 10330U, 13172U, 3354U,
2843 13055U, 13630U, 10604U, 3293U, 2581U, 10426U, 4162U, 2837U,
2844 11454U, 12418U, 10700U, 12371U, 3735U, 4288U, 2980U, 2958U,
2845 7058U, 7908U, 3464U, 3429U, 4132U, 7939U, 2553U, 2567U,
2846 12656U, 3214U, 3389U, 5922U, 3141U, 5699U, 5726U, 3794U,
2847 3177U, 5818U, 10984U, 14106U, 9021U, 13108U, 13421U, 4240U,
2848 13921U, 10469U, 10180U, 14044U, 10482U, 10191U, 10528U, 8754U,
2849 10828U, 11892U, 13517U, 13928U, 13947U, 10715U, 10730U, 11378U,
2850 13439U, 9908U, 8736U, 6232U, 13751U, 13681U, 11880U, 6905U,
2851 8163U, 13648U, 7116U, 8354U, 9885U, 6998U, 8267U, 10508U,
2852 8215U, 11038U, 11562U, 11145U, 11624U, 11227U, 11292U, 7028U,
2853 8297U, 6851U, 8109U, 11050U, 11580U, 11168U, 11639U, 11247U,
2854 11307U, 1071U, 703U, 1001U, 526U, 954U, 1357U, 883U,
2855 1088U, 722U, 627U, 1312U, 5690U, 5889U, 11934U, 11432U,
2856 9131U, 12452U, 3913U, 10927U, 10454U, 10167U, 12672U, 13229U,
2857 12691U, 10636U, 12887U, 12867U, 11421U, 14078U, 14089U, 5755U,
2858 6126U, 6190U, 13724U, 10265U, 10348U, 8874U, 13815U, 11678U,
2859 5966U, 8921U, 5981U, 5776U, 6146U, 6211U, 11394U, 11079U,
2860 14051U, 13573U, 13463U, 13074U, 1455U, 1486U, 9062U, 12113U,
2861 12567U, 13697U, 13761U, 13121U, 8852U, 13793U, 11656U, 11480U,
2862 8899U, 11502U, 13542U, 9090U, 12140U, 12595U, 12055U, 5846U,
2863 13840U, 11703U, 10106U, 11954U, 12028U, 12539U, 13887U, 11750U,
2864 12780U, 12836U, 13862U, 11725U, 13909U, 11772U, 12907U, 7168U,
2865 8406U, 6927U, 8185U, 11029U, 7020U, 8289U, 11280U, 7154U,
2866 8392U, 6873U, 8131U, 9970U, 12289U, 10886U, 12255U, 12986U,
2867 12736U, 9869U, 12237U, 12716U, 10751U, 9337U, 8802U, 9669U,
2868 9413U, 9613U, 8058U, 9357U, 9733U, 9477U, 9805U, 9549U,
2869 12307U, 10899U, 12269U, 8814U, 9698U, 9442U, 9638U, 9382U,
2870 9766U, 9510U, 9834U, 9578U, 13281U, 12507U, 10567U, 11840U,
2871 11815U, 10556U, 10820U, 11524U, 10998U, 13347U, 8767U, 11447U,
2872 11356U, 12436U, 13597U, 12087U, 10211U, 8845U, 9118U, 11064U,
2873 13523U, 11324U, 12167U, 3940U, 10069U, 4112U, 4193U, 13993U,
2874 12217U, 12636U, 10539U, 10845U, 10154U, 12388U, 11364U, 12350U,
2875 8985U, 10147U, 10768U, 10202U, 12081U, 13536U, 8963U, 13144U,
2876 10950U, 6114U, 3092U, 3515U, 11798U, 4081U, 8717U, 10810U,
2877 11269U, 11342U, 43U, 5951U, 10237U, 475U, 13392U, 12755U,
2878 12810U, 10218U, 10298U, 4341U, 13407U, 11945U, 10654U, 2938U,
2879 13659U, 7138U, 8376U, 13495U, 12946U, 11532U, 11105U, 11600U,
2880 11193U, 9892U, 8933U, 10518U, 7050U, 8319U, 13502U, 12959U,
2881 9943U, 7922U, 7072U, 4362U, 9145U, 9241U, 9177U, 9273U,
2882 9209U, 9305U, 9161U, 9257U, 9193U, 9289U, 9225U, 9321U,
2883 10052U, 12925U, 6957U, 8226U, 6881U, 8139U, 6977U, 8246U,
2884 13216U, 10793U, 9899U, 9003U, 11862U, 13266U, 10580U, 3255U,
2885 10406U, 12011U, 10681U, 10398U, 6913U, 8171U, 7124U, 8362U,
2886 7006U, 8275U, 7036U, 8305U, 6859U, 8117U, 10868U, 3114U,
2887 3959U, 3566U, 3763U, 3538U, 3067U, 3709U, 3037U, 3678U,
2888 3002U, 3642U, 3602U, 4029U, 3492U, 4056U, 4214U, 10918U,
2889 10442U, 8028U, 14032U, 11469U, 6255U, 8083U, 13362U, 13380U,
2890 13005U, 12472U, 11919U, 9958U, 13256U, 13960U, 12331U, 10668U,
2891 10287U, 9978U, 12493U, 10624U, 8786U, 14013U, 9924U, 12404U,
2892 13159U, 3327U, 6166U, 12623U, 7784U, 9039U, 13670U, 7146U,
2893 8384U, 13510U, 12973U, 11547U, 11125U, 11612U, 11210U, 6949U,
2894 8207U, 8948U, 10802U, 8973U, 10081U, 5996U, 6282U, 6082U,
2895 6047U, 5901U, 6020U, 5797U, 10095U, 4314U, 8672U, 8695U,
2896 10131U, 13973U, 12197U, 10318U, 500U,
2897};
2898
2899static inline void InitSPIRVMCInstrInfo(MCInstrInfo *II) {
2900 II->InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 861, nullptr, 0);
2901}
2902
2903
2904} // namespace llvm
2905
2906#endif // GET_INSTRINFO_MC_DESC
2907
2908#ifdef GET_INSTRINFO_HEADER
2909#undef GET_INSTRINFO_HEADER
2910
2911namespace llvm {
2912
2913struct SPIRVGenInstrInfo : public TargetInstrInfo {
2914 explicit SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2915 ~SPIRVGenInstrInfo() override = default;
2916};
2917
2918} // namespace llvm
2919
2920namespace llvm::SPIRV {
2921
2922
2923} // namespace llvm::SPIRV
2924
2925#endif // GET_INSTRINFO_HEADER
2926
2927#ifdef GET_INSTRINFO_HELPER_DECLS
2928#undef GET_INSTRINFO_HELPER_DECLS
2929
2930
2931#endif // GET_INSTRINFO_HELPER_DECLS
2932
2933#ifdef GET_INSTRINFO_HELPERS
2934#undef GET_INSTRINFO_HELPERS
2935
2936
2937#endif // GET_INSTRINFO_HELPERS
2938
2939#ifdef GET_INSTRINFO_CTOR_DTOR
2940#undef GET_INSTRINFO_CTOR_DTOR
2941
2942namespace llvm {
2943
2944extern const SPIRVInstrTable SPIRVDescs;
2945extern const unsigned SPIRVInstrNameIndices[];
2946extern const char SPIRVInstrNameData[];
2947SPIRVGenInstrInfo::SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2948 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2949 InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 861);
2950}
2951
2952} // namespace llvm
2953
2954#endif // GET_INSTRINFO_CTOR_DTOR
2955
2956#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2957#undef GET_INSTRINFO_MC_HELPER_DECLS
2958
2959namespace llvm {
2960
2961class MCInst;
2962class FeatureBitset;
2963
2964namespace SPIRV_MC {
2965
2966void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2967
2968} // namespace SPIRV_MC
2969
2970} // namespace llvm
2971
2972#endif // GET_INSTRINFO_MC_HELPER_DECLS
2973
2974#ifdef GET_INSTRINFO_MC_HELPERS
2975#undef GET_INSTRINFO_MC_HELPERS
2976
2977namespace llvm::SPIRV_MC {
2978
2979
2980} // namespace llvm::SPIRV_MC
2981
2982#endif // GET_INSTRINFO_MC_HELPERS
2983
2984#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2985 defined(GET_AVAILABLE_OPCODE_CHECKER)
2986#define GET_COMPUTE_FEATURES
2987#endif
2988#ifdef GET_COMPUTE_FEATURES
2989#undef GET_COMPUTE_FEATURES
2990
2991namespace llvm::SPIRV_MC {
2992
2993// Bits for subtarget features that participate in instruction matching.
2994enum SubtargetFeatureBits : uint8_t {
2995};
2996
2997inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2998 FeatureBitset Features;
2999 return Features;
3000}
3001
3002inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3003 enum : uint8_t {
3004 CEFBS_None,
3005 };
3006
3007 static constexpr FeatureBitset FeatureBitsets[] = {
3008 {}, // CEFBS_None
3009 };
3010 static constexpr uint8_t RequiredFeaturesRefs[] = {
3011 CEFBS_None, // PHI
3012 CEFBS_None, // INLINEASM
3013 CEFBS_None, // INLINEASM_BR
3014 CEFBS_None, // CFI_INSTRUCTION
3015 CEFBS_None, // EH_LABEL
3016 CEFBS_None, // GC_LABEL
3017 CEFBS_None, // ANNOTATION_LABEL
3018 CEFBS_None, // KILL
3019 CEFBS_None, // EXTRACT_SUBREG
3020 CEFBS_None, // INSERT_SUBREG
3021 CEFBS_None, // IMPLICIT_DEF
3022 CEFBS_None, // INIT_UNDEF
3023 CEFBS_None, // SUBREG_TO_REG
3024 CEFBS_None, // COPY_TO_REGCLASS
3025 CEFBS_None, // DBG_VALUE
3026 CEFBS_None, // DBG_VALUE_LIST
3027 CEFBS_None, // DBG_INSTR_REF
3028 CEFBS_None, // DBG_PHI
3029 CEFBS_None, // DBG_LABEL
3030 CEFBS_None, // REG_SEQUENCE
3031 CEFBS_None, // COPY
3032 CEFBS_None, // COPY_LANEMASK
3033 CEFBS_None, // BUNDLE
3034 CEFBS_None, // LIFETIME_START
3035 CEFBS_None, // LIFETIME_END
3036 CEFBS_None, // PSEUDO_PROBE
3037 CEFBS_None, // ARITH_FENCE
3038 CEFBS_None, // STACKMAP
3039 CEFBS_None, // FENTRY_CALL
3040 CEFBS_None, // PATCHPOINT
3041 CEFBS_None, // LOAD_STACK_GUARD
3042 CEFBS_None, // PREALLOCATED_SETUP
3043 CEFBS_None, // PREALLOCATED_ARG
3044 CEFBS_None, // STATEPOINT
3045 CEFBS_None, // LOCAL_ESCAPE
3046 CEFBS_None, // FAULTING_OP
3047 CEFBS_None, // PATCHABLE_OP
3048 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
3049 CEFBS_None, // PATCHABLE_RET
3050 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
3051 CEFBS_None, // PATCHABLE_TAIL_CALL
3052 CEFBS_None, // PATCHABLE_EVENT_CALL
3053 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
3054 CEFBS_None, // ICALL_BRANCH_FUNNEL
3055 CEFBS_None, // FAKE_USE
3056 CEFBS_None, // MEMBARRIER
3057 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
3058 CEFBS_None, // RELOC_NONE
3059 CEFBS_None, // CONVERGENCECTRL_ENTRY
3060 CEFBS_None, // CONVERGENCECTRL_ANCHOR
3061 CEFBS_None, // CONVERGENCECTRL_LOOP
3062 CEFBS_None, // CONVERGENCECTRL_GLUE
3063 CEFBS_None, // G_ASSERT_SEXT
3064 CEFBS_None, // G_ASSERT_ZEXT
3065 CEFBS_None, // G_ASSERT_ALIGN
3066 CEFBS_None, // G_ADD
3067 CEFBS_None, // G_SUB
3068 CEFBS_None, // G_MUL
3069 CEFBS_None, // G_SDIV
3070 CEFBS_None, // G_UDIV
3071 CEFBS_None, // G_SREM
3072 CEFBS_None, // G_UREM
3073 CEFBS_None, // G_SDIVREM
3074 CEFBS_None, // G_UDIVREM
3075 CEFBS_None, // G_AND
3076 CEFBS_None, // G_OR
3077 CEFBS_None, // G_XOR
3078 CEFBS_None, // G_ABDS
3079 CEFBS_None, // G_ABDU
3080 CEFBS_None, // G_UAVGFLOOR
3081 CEFBS_None, // G_UAVGCEIL
3082 CEFBS_None, // G_SAVGFLOOR
3083 CEFBS_None, // G_SAVGCEIL
3084 CEFBS_None, // G_IMPLICIT_DEF
3085 CEFBS_None, // G_PHI
3086 CEFBS_None, // G_FRAME_INDEX
3087 CEFBS_None, // G_GLOBAL_VALUE
3088 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3089 CEFBS_None, // G_CONSTANT_POOL
3090 CEFBS_None, // G_EXTRACT
3091 CEFBS_None, // G_UNMERGE_VALUES
3092 CEFBS_None, // G_INSERT
3093 CEFBS_None, // G_MERGE_VALUES
3094 CEFBS_None, // G_BUILD_VECTOR
3095 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3096 CEFBS_None, // G_CONCAT_VECTORS
3097 CEFBS_None, // G_PTRTOINT
3098 CEFBS_None, // G_INTTOPTR
3099 CEFBS_None, // G_BITCAST
3100 CEFBS_None, // G_FREEZE
3101 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3102 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3103 CEFBS_None, // G_INTRINSIC_TRUNC
3104 CEFBS_None, // G_INTRINSIC_ROUND
3105 CEFBS_None, // G_INTRINSIC_LRINT
3106 CEFBS_None, // G_INTRINSIC_LLRINT
3107 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3108 CEFBS_None, // G_READCYCLECOUNTER
3109 CEFBS_None, // G_READSTEADYCOUNTER
3110 CEFBS_None, // G_LOAD
3111 CEFBS_None, // G_SEXTLOAD
3112 CEFBS_None, // G_ZEXTLOAD
3113 CEFBS_None, // G_FPEXTLOAD
3114 CEFBS_None, // G_INDEXED_LOAD
3115 CEFBS_None, // G_INDEXED_SEXTLOAD
3116 CEFBS_None, // G_INDEXED_ZEXTLOAD
3117 CEFBS_None, // G_STORE
3118 CEFBS_None, // G_FPTRUNCSTORE
3119 CEFBS_None, // G_INDEXED_STORE
3120 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3121 CEFBS_None, // G_ATOMIC_CMPXCHG
3122 CEFBS_None, // G_ATOMICRMW_XCHG
3123 CEFBS_None, // G_ATOMICRMW_ADD
3124 CEFBS_None, // G_ATOMICRMW_SUB
3125 CEFBS_None, // G_ATOMICRMW_AND
3126 CEFBS_None, // G_ATOMICRMW_NAND
3127 CEFBS_None, // G_ATOMICRMW_OR
3128 CEFBS_None, // G_ATOMICRMW_XOR
3129 CEFBS_None, // G_ATOMICRMW_MAX
3130 CEFBS_None, // G_ATOMICRMW_MIN
3131 CEFBS_None, // G_ATOMICRMW_UMAX
3132 CEFBS_None, // G_ATOMICRMW_UMIN
3133 CEFBS_None, // G_ATOMICRMW_FADD
3134 CEFBS_None, // G_ATOMICRMW_FSUB
3135 CEFBS_None, // G_ATOMICRMW_FMAX
3136 CEFBS_None, // G_ATOMICRMW_FMIN
3137 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3138 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3139 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
3140 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
3141 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3142 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3143 CEFBS_None, // G_ATOMICRMW_USUB_COND
3144 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3145 CEFBS_None, // G_FENCE
3146 CEFBS_None, // G_PREFETCH
3147 CEFBS_None, // G_BRCOND
3148 CEFBS_None, // G_BRINDIRECT
3149 CEFBS_None, // G_INVOKE_REGION_START
3150 CEFBS_None, // G_INTRINSIC
3151 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3152 CEFBS_None, // G_INTRINSIC_CONVERGENT
3153 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3154 CEFBS_None, // G_ANYEXT
3155 CEFBS_None, // G_TRUNC
3156 CEFBS_None, // G_TRUNC_SSAT_S
3157 CEFBS_None, // G_TRUNC_SSAT_U
3158 CEFBS_None, // G_TRUNC_USAT_U
3159 CEFBS_None, // G_CONSTANT
3160 CEFBS_None, // G_FCONSTANT
3161 CEFBS_None, // G_VASTART
3162 CEFBS_None, // G_VAARG
3163 CEFBS_None, // G_SEXT
3164 CEFBS_None, // G_SEXT_INREG
3165 CEFBS_None, // G_ZEXT
3166 CEFBS_None, // G_SHL
3167 CEFBS_None, // G_LSHR
3168 CEFBS_None, // G_ASHR
3169 CEFBS_None, // G_FSHL
3170 CEFBS_None, // G_FSHR
3171 CEFBS_None, // G_ROTR
3172 CEFBS_None, // G_ROTL
3173 CEFBS_None, // G_ICMP
3174 CEFBS_None, // G_FCMP
3175 CEFBS_None, // G_SCMP
3176 CEFBS_None, // G_UCMP
3177 CEFBS_None, // G_SELECT
3178 CEFBS_None, // G_UADDO
3179 CEFBS_None, // G_UADDE
3180 CEFBS_None, // G_USUBO
3181 CEFBS_None, // G_USUBE
3182 CEFBS_None, // G_SADDO
3183 CEFBS_None, // G_SADDE
3184 CEFBS_None, // G_SSUBO
3185 CEFBS_None, // G_SSUBE
3186 CEFBS_None, // G_UMULO
3187 CEFBS_None, // G_SMULO
3188 CEFBS_None, // G_UMULH
3189 CEFBS_None, // G_SMULH
3190 CEFBS_None, // G_UADDSAT
3191 CEFBS_None, // G_SADDSAT
3192 CEFBS_None, // G_USUBSAT
3193 CEFBS_None, // G_SSUBSAT
3194 CEFBS_None, // G_USHLSAT
3195 CEFBS_None, // G_SSHLSAT
3196 CEFBS_None, // G_SMULFIX
3197 CEFBS_None, // G_UMULFIX
3198 CEFBS_None, // G_SMULFIXSAT
3199 CEFBS_None, // G_UMULFIXSAT
3200 CEFBS_None, // G_SDIVFIX
3201 CEFBS_None, // G_UDIVFIX
3202 CEFBS_None, // G_SDIVFIXSAT
3203 CEFBS_None, // G_UDIVFIXSAT
3204 CEFBS_None, // G_FADD
3205 CEFBS_None, // G_FSUB
3206 CEFBS_None, // G_FMUL
3207 CEFBS_None, // G_FMA
3208 CEFBS_None, // G_FMAD
3209 CEFBS_None, // G_FDIV
3210 CEFBS_None, // G_FREM
3211 CEFBS_None, // G_FMODF
3212 CEFBS_None, // G_FPOW
3213 CEFBS_None, // G_FPOWI
3214 CEFBS_None, // G_FEXP
3215 CEFBS_None, // G_FEXP2
3216 CEFBS_None, // G_FEXP10
3217 CEFBS_None, // G_FLOG
3218 CEFBS_None, // G_FLOG2
3219 CEFBS_None, // G_FLOG10
3220 CEFBS_None, // G_FLDEXP
3221 CEFBS_None, // G_FFREXP
3222 CEFBS_None, // G_FNEG
3223 CEFBS_None, // G_FPEXT
3224 CEFBS_None, // G_FPTRUNC
3225 CEFBS_None, // G_FPTOSI
3226 CEFBS_None, // G_FPTOUI
3227 CEFBS_None, // G_SITOFP
3228 CEFBS_None, // G_UITOFP
3229 CEFBS_None, // G_FPTOSI_SAT
3230 CEFBS_None, // G_FPTOUI_SAT
3231 CEFBS_None, // G_FABS
3232 CEFBS_None, // G_FCOPYSIGN
3233 CEFBS_None, // G_IS_FPCLASS
3234 CEFBS_None, // G_FCANONICALIZE
3235 CEFBS_None, // G_FMINNUM
3236 CEFBS_None, // G_FMAXNUM
3237 CEFBS_None, // G_FMINNUM_IEEE
3238 CEFBS_None, // G_FMAXNUM_IEEE
3239 CEFBS_None, // G_FMINIMUM
3240 CEFBS_None, // G_FMAXIMUM
3241 CEFBS_None, // G_FMINIMUMNUM
3242 CEFBS_None, // G_FMAXIMUMNUM
3243 CEFBS_None, // G_GET_FPENV
3244 CEFBS_None, // G_SET_FPENV
3245 CEFBS_None, // G_RESET_FPENV
3246 CEFBS_None, // G_GET_FPMODE
3247 CEFBS_None, // G_SET_FPMODE
3248 CEFBS_None, // G_RESET_FPMODE
3249 CEFBS_None, // G_GET_ROUNDING
3250 CEFBS_None, // G_SET_ROUNDING
3251 CEFBS_None, // G_PTR_ADD
3252 CEFBS_None, // G_PTRMASK
3253 CEFBS_None, // G_SMIN
3254 CEFBS_None, // G_SMAX
3255 CEFBS_None, // G_UMIN
3256 CEFBS_None, // G_UMAX
3257 CEFBS_None, // G_ABS
3258 CEFBS_None, // G_LROUND
3259 CEFBS_None, // G_LLROUND
3260 CEFBS_None, // G_BR
3261 CEFBS_None, // G_BRJT
3262 CEFBS_None, // G_VSCALE
3263 CEFBS_None, // G_INSERT_SUBVECTOR
3264 CEFBS_None, // G_EXTRACT_SUBVECTOR
3265 CEFBS_None, // G_INSERT_VECTOR_ELT
3266 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3267 CEFBS_None, // G_SHUFFLE_VECTOR
3268 CEFBS_None, // G_SPLAT_VECTOR
3269 CEFBS_None, // G_STEP_VECTOR
3270 CEFBS_None, // G_VECTOR_COMPRESS
3271 CEFBS_None, // G_CTTZ
3272 CEFBS_None, // G_CTTZ_ZERO_POISON
3273 CEFBS_None, // G_CTLZ
3274 CEFBS_None, // G_CTLZ_ZERO_POISON
3275 CEFBS_None, // G_CTLS
3276 CEFBS_None, // G_CTPOP
3277 CEFBS_None, // G_BSWAP
3278 CEFBS_None, // G_BITREVERSE
3279 CEFBS_None, // G_CLMUL
3280 CEFBS_None, // G_FCEIL
3281 CEFBS_None, // G_FCOS
3282 CEFBS_None, // G_FSIN
3283 CEFBS_None, // G_FSINCOS
3284 CEFBS_None, // G_FTAN
3285 CEFBS_None, // G_FACOS
3286 CEFBS_None, // G_FASIN
3287 CEFBS_None, // G_FATAN
3288 CEFBS_None, // G_FATAN2
3289 CEFBS_None, // G_FCOSH
3290 CEFBS_None, // G_FSINH
3291 CEFBS_None, // G_FTANH
3292 CEFBS_None, // G_FSQRT
3293 CEFBS_None, // G_FFLOOR
3294 CEFBS_None, // G_FRINT
3295 CEFBS_None, // G_FNEARBYINT
3296 CEFBS_None, // G_ADDRSPACE_CAST
3297 CEFBS_None, // G_BLOCK_ADDR
3298 CEFBS_None, // G_JUMP_TABLE
3299 CEFBS_None, // G_DYN_STACKALLOC
3300 CEFBS_None, // G_STACKSAVE
3301 CEFBS_None, // G_STACKRESTORE
3302 CEFBS_None, // G_STRICT_FADD
3303 CEFBS_None, // G_STRICT_FSUB
3304 CEFBS_None, // G_STRICT_FMUL
3305 CEFBS_None, // G_STRICT_FDIV
3306 CEFBS_None, // G_STRICT_FREM
3307 CEFBS_None, // G_STRICT_FMA
3308 CEFBS_None, // G_STRICT_FSQRT
3309 CEFBS_None, // G_STRICT_FLDEXP
3310 CEFBS_None, // G_STRICT_FCMP
3311 CEFBS_None, // G_STRICT_FCMPS
3312 CEFBS_None, // G_READ_REGISTER
3313 CEFBS_None, // G_WRITE_REGISTER
3314 CEFBS_None, // G_MEMCPY
3315 CEFBS_None, // G_MEMCPY_INLINE
3316 CEFBS_None, // G_MEMMOVE
3317 CEFBS_None, // G_MEMSET
3318 CEFBS_None, // G_BZERO
3319 CEFBS_None, // G_MEMSET_INLINE
3320 CEFBS_None, // G_TRAP
3321 CEFBS_None, // G_DEBUGTRAP
3322 CEFBS_None, // G_UBSANTRAP
3323 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3324 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3325 CEFBS_None, // G_VECREDUCE_FADD
3326 CEFBS_None, // G_VECREDUCE_FMUL
3327 CEFBS_None, // G_VECREDUCE_FMAX
3328 CEFBS_None, // G_VECREDUCE_FMIN
3329 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3330 CEFBS_None, // G_VECREDUCE_FMINIMUM
3331 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
3332 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
3333 CEFBS_None, // G_VECREDUCE_ADD
3334 CEFBS_None, // G_VECREDUCE_MUL
3335 CEFBS_None, // G_VECREDUCE_AND
3336 CEFBS_None, // G_VECREDUCE_OR
3337 CEFBS_None, // G_VECREDUCE_XOR
3338 CEFBS_None, // G_VECREDUCE_SMAX
3339 CEFBS_None, // G_VECREDUCE_SMIN
3340 CEFBS_None, // G_VECREDUCE_UMAX
3341 CEFBS_None, // G_VECREDUCE_UMIN
3342 CEFBS_None, // G_SBFX
3343 CEFBS_None, // G_UBFX
3344 CEFBS_None, // ASSIGN_TYPE
3345 CEFBS_None, // UNKNOWN_type
3346 CEFBS_None, // OpAbortKHR
3347 CEFBS_None, // OpAccessChain
3348 CEFBS_None, // OpAliasDomainDeclINTEL
3349 CEFBS_None, // OpAliasScopeDeclINTEL
3350 CEFBS_None, // OpAliasScopeListDeclINTEL
3351 CEFBS_None, // OpAll
3352 CEFBS_None, // OpAny
3353 CEFBS_None, // OpArbitraryFloatACosALTERA
3354 CEFBS_None, // OpArbitraryFloatACosPiALTERA
3355 CEFBS_None, // OpArbitraryFloatASinALTERA
3356 CEFBS_None, // OpArbitraryFloatASinPiALTERA
3357 CEFBS_None, // OpArbitraryFloatATan2ALTERA
3358 CEFBS_None, // OpArbitraryFloatATanALTERA
3359 CEFBS_None, // OpArbitraryFloatATanPiALTERA
3360 CEFBS_None, // OpArbitraryFloatAddALTERA
3361 CEFBS_None, // OpArbitraryFloatCastALTERA
3362 CEFBS_None, // OpArbitraryFloatCastFromIntALTERA
3363 CEFBS_None, // OpArbitraryFloatCastToIntALTERA
3364 CEFBS_None, // OpArbitraryFloatCbrtALTERA
3365 CEFBS_None, // OpArbitraryFloatCosALTERA
3366 CEFBS_None, // OpArbitraryFloatCosPiALTERA
3367 CEFBS_None, // OpArbitraryFloatDivALTERA
3368 CEFBS_None, // OpArbitraryFloatEQALTERA
3369 CEFBS_None, // OpArbitraryFloatExp10ALTERA
3370 CEFBS_None, // OpArbitraryFloatExp2ALTERA
3371 CEFBS_None, // OpArbitraryFloatExpALTERA
3372 CEFBS_None, // OpArbitraryFloatExpm1ALTERA
3373 CEFBS_None, // OpArbitraryFloatGEALTERA
3374 CEFBS_None, // OpArbitraryFloatGTALTERA
3375 CEFBS_None, // OpArbitraryFloatHypotALTERA
3376 CEFBS_None, // OpArbitraryFloatLEALTERA
3377 CEFBS_None, // OpArbitraryFloatLTALTERA
3378 CEFBS_None, // OpArbitraryFloatLog10ALTERA
3379 CEFBS_None, // OpArbitraryFloatLog1pALTERA
3380 CEFBS_None, // OpArbitraryFloatLog2ALTERA
3381 CEFBS_None, // OpArbitraryFloatLogALTERA
3382 CEFBS_None, // OpArbitraryFloatMulALTERA
3383 CEFBS_None, // OpArbitraryFloatPowALTERA
3384 CEFBS_None, // OpArbitraryFloatPowNALTERA
3385 CEFBS_None, // OpArbitraryFloatPowRALTERA
3386 CEFBS_None, // OpArbitraryFloatRSqrtALTERA
3387 CEFBS_None, // OpArbitraryFloatRecipALTERA
3388 CEFBS_None, // OpArbitraryFloatSinALTERA
3389 CEFBS_None, // OpArbitraryFloatSinCosALTERA
3390 CEFBS_None, // OpArbitraryFloatSinCosPiALTERA
3391 CEFBS_None, // OpArbitraryFloatSinPiALTERA
3392 CEFBS_None, // OpArbitraryFloatSqrtALTERA
3393 CEFBS_None, // OpArbitraryFloatSubALTERA
3394 CEFBS_None, // OpArithmeticFenceEXT
3395 CEFBS_None, // OpArrayLength
3396 CEFBS_None, // OpAsmCallINTEL
3397 CEFBS_None, // OpAsmINTEL
3398 CEFBS_None, // OpAsmTargetINTEL
3399 CEFBS_None, // OpAssumeTrueKHR
3400 CEFBS_None, // OpAtomicAnd
3401 CEFBS_None, // OpAtomicCompareExchange
3402 CEFBS_None, // OpAtomicCompareExchangeWeak
3403 CEFBS_None, // OpAtomicExchange
3404 CEFBS_None, // OpAtomicFAddEXT
3405 CEFBS_None, // OpAtomicFMaxEXT
3406 CEFBS_None, // OpAtomicFMinEXT
3407 CEFBS_None, // OpAtomicFlagClear
3408 CEFBS_None, // OpAtomicFlagTestAndSet
3409 CEFBS_None, // OpAtomicIAdd
3410 CEFBS_None, // OpAtomicIDecrement
3411 CEFBS_None, // OpAtomicIIncrement
3412 CEFBS_None, // OpAtomicISub
3413 CEFBS_None, // OpAtomicLoad
3414 CEFBS_None, // OpAtomicOr
3415 CEFBS_None, // OpAtomicSMax
3416 CEFBS_None, // OpAtomicSMin
3417 CEFBS_None, // OpAtomicStore
3418 CEFBS_None, // OpAtomicUMax
3419 CEFBS_None, // OpAtomicUMin
3420 CEFBS_None, // OpAtomicXor
3421 CEFBS_None, // OpBitCount
3422 CEFBS_None, // OpBitFieldInsert
3423 CEFBS_None, // OpBitFieldSExtract
3424 CEFBS_None, // OpBitFieldUExtract
3425 CEFBS_None, // OpBitReverse
3426 CEFBS_None, // OpBitcast
3427 CEFBS_None, // OpBitwiseAndS
3428 CEFBS_None, // OpBitwiseAndV
3429 CEFBS_None, // OpBitwiseFunctionINTEL
3430 CEFBS_None, // OpBitwiseOrS
3431 CEFBS_None, // OpBitwiseOrV
3432 CEFBS_None, // OpBitwiseXorS
3433 CEFBS_None, // OpBitwiseXorV
3434 CEFBS_None, // OpBranch
3435 CEFBS_None, // OpBranchConditional
3436 CEFBS_None, // OpBuildNDRange
3437 CEFBS_None, // OpCapability
3438 CEFBS_None, // OpCaptureEventProfilingInfo
3439 CEFBS_None, // OpCommitReadPipe
3440 CEFBS_None, // OpCommitWritePipe
3441 CEFBS_None, // OpCompositeConstruct
3442 CEFBS_None, // OpCompositeConstructContinuedINTEL
3443 CEFBS_None, // OpCompositeExtract
3444 CEFBS_None, // OpCompositeInsert
3445 CEFBS_None, // OpConstantComposite
3446 CEFBS_None, // OpConstantCompositeContinuedINTEL
3447 CEFBS_None, // OpConstantF
3448 CEFBS_None, // OpConstantFalse
3449 CEFBS_None, // OpConstantFunctionPointerINTEL
3450 CEFBS_None, // OpConstantI
3451 CEFBS_None, // OpConstantNull
3452 CEFBS_None, // OpConstantSampler
3453 CEFBS_None, // OpConstantTrue
3454 CEFBS_None, // OpControlBarrier
3455 CEFBS_None, // OpControlBarrierArriveINTEL
3456 CEFBS_None, // OpControlBarrierWaitINTEL
3457 CEFBS_None, // OpConvertBF16ToFINTEL
3458 CEFBS_None, // OpConvertFToBF16INTEL
3459 CEFBS_None, // OpConvertFToS
3460 CEFBS_None, // OpConvertFToU
3461 CEFBS_None, // OpConvertHandleToImageINTEL
3462 CEFBS_None, // OpConvertHandleToSampledImageINTEL
3463 CEFBS_None, // OpConvertHandleToSamplerINTEL
3464 CEFBS_None, // OpConvertPtrToU
3465 CEFBS_None, // OpConvertSToF
3466 CEFBS_None, // OpConvertUToF
3467 CEFBS_None, // OpConvertUToPtr
3468 CEFBS_None, // OpCooperativeMatrixConstructCheckedINTEL
3469 CEFBS_None, // OpCooperativeMatrixGetElementCoordINTEL
3470 CEFBS_None, // OpCooperativeMatrixLengthKHR
3471 CEFBS_None, // OpCooperativeMatrixLoadCheckedINTEL
3472 CEFBS_None, // OpCooperativeMatrixLoadKHR
3473 CEFBS_None, // OpCooperativeMatrixMulAddKHR
3474 CEFBS_None, // OpCooperativeMatrixPrefetchINTEL
3475 CEFBS_None, // OpCooperativeMatrixStoreCheckedINTEL
3476 CEFBS_None, // OpCooperativeMatrixStoreKHR
3477 CEFBS_None, // OpCopyLogical
3478 CEFBS_None, // OpCopyMemory
3479 CEFBS_None, // OpCopyMemorySized
3480 CEFBS_None, // OpCopyObject
3481 CEFBS_None, // OpCreateUserEvent
3482 CEFBS_None, // OpCrossWorkgroupCastToPtrINTEL
3483 CEFBS_None, // OpDPdx
3484 CEFBS_None, // OpDPdxCoarse
3485 CEFBS_None, // OpDPdxFine
3486 CEFBS_None, // OpDPdy
3487 CEFBS_None, // OpDPdyCoarse
3488 CEFBS_None, // OpDPdyFine
3489 CEFBS_None, // OpDecorate
3490 CEFBS_None, // OpDecorateId
3491 CEFBS_None, // OpDecorateString
3492 CEFBS_None, // OpDemoteToHelperInvocation
3493 CEFBS_None, // OpDot
3494 CEFBS_None, // OpEmitStreamVertex
3495 CEFBS_None, // OpEmitVertex
3496 CEFBS_None, // OpEndPrimitive
3497 CEFBS_None, // OpEndStreamPrimitive
3498 CEFBS_None, // OpEnqueueKernel
3499 CEFBS_None, // OpEntryPoint
3500 CEFBS_None, // OpExecutionMode
3501 CEFBS_None, // OpExecutionModeId
3502 CEFBS_None, // OpExpectKHR
3503 CEFBS_None, // OpExtInst
3504 CEFBS_None, // OpExtInstImport
3505 CEFBS_None, // OpExtension
3506 CEFBS_None, // OpFAddS
3507 CEFBS_None, // OpFAddV
3508 CEFBS_None, // OpFConvert
3509 CEFBS_None, // OpFDivS
3510 CEFBS_None, // OpFDivV
3511 CEFBS_None, // OpFMod
3512 CEFBS_None, // OpFMulS
3513 CEFBS_None, // OpFMulV
3514 CEFBS_None, // OpFNegate
3515 CEFBS_None, // OpFNegateV
3516 CEFBS_None, // OpFOrdEqual
3517 CEFBS_None, // OpFOrdGreaterThan
3518 CEFBS_None, // OpFOrdGreaterThanEqual
3519 CEFBS_None, // OpFOrdLessThan
3520 CEFBS_None, // OpFOrdLessThanEqual
3521 CEFBS_None, // OpFOrdNotEqual
3522 CEFBS_None, // OpFRemS
3523 CEFBS_None, // OpFRemV
3524 CEFBS_None, // OpFSubS
3525 CEFBS_None, // OpFSubV
3526 CEFBS_None, // OpFUnordEqual
3527 CEFBS_None, // OpFUnordGreaterThan
3528 CEFBS_None, // OpFUnordGreaterThanEqual
3529 CEFBS_None, // OpFUnordLessThan
3530 CEFBS_None, // OpFUnordLessThanEqual
3531 CEFBS_None, // OpFUnordNotEqual
3532 CEFBS_None, // OpFixedCosALTERA
3533 CEFBS_None, // OpFixedCosPiALTERA
3534 CEFBS_None, // OpFixedExpALTERA
3535 CEFBS_None, // OpFixedLogALTERA
3536 CEFBS_None, // OpFixedRecipALTERA
3537 CEFBS_None, // OpFixedRsqrtALTERA
3538 CEFBS_None, // OpFixedSinALTERA
3539 CEFBS_None, // OpFixedSinCosALTERA
3540 CEFBS_None, // OpFixedSinCosPiALTERA
3541 CEFBS_None, // OpFixedSinPiALTERA
3542 CEFBS_None, // OpFixedSqrtALTERA
3543 CEFBS_None, // OpFmaKHR
3544 CEFBS_None, // OpFreezeKHR
3545 CEFBS_None, // OpFunction
3546 CEFBS_None, // OpFunctionCall
3547 CEFBS_None, // OpFunctionEnd
3548 CEFBS_None, // OpFunctionParameter
3549 CEFBS_None, // OpFunctionPointerCallINTEL
3550 CEFBS_None, // OpFwidth
3551 CEFBS_None, // OpFwidthCoarse
3552 CEFBS_None, // OpFwidthFine
3553 CEFBS_None, // OpGenericCastToPtr
3554 CEFBS_None, // OpGenericCastToPtrExplicit
3555 CEFBS_None, // OpGenericPtrMemSemantics
3556 CEFBS_None, // OpGetDefaultQueue
3557 CEFBS_None, // OpGetMaxPipePackets
3558 CEFBS_None, // OpGetNumPipePackets
3559 CEFBS_None, // OpGroupAll
3560 CEFBS_None, // OpGroupAny
3561 CEFBS_None, // OpGroupAsyncCopy
3562 CEFBS_None, // OpGroupBitwiseAndKHR
3563 CEFBS_None, // OpGroupBitwiseOrKHR
3564 CEFBS_None, // OpGroupBitwiseXorKHR
3565 CEFBS_None, // OpGroupBroadcast
3566 CEFBS_None, // OpGroupCommitReadPipe
3567 CEFBS_None, // OpGroupCommitWritePipe
3568 CEFBS_None, // OpGroupFAdd
3569 CEFBS_None, // OpGroupFMax
3570 CEFBS_None, // OpGroupFMin
3571 CEFBS_None, // OpGroupFMulKHR
3572 CEFBS_None, // OpGroupIAdd
3573 CEFBS_None, // OpGroupIMulKHR
3574 CEFBS_None, // OpGroupLogicalAndKHR
3575 CEFBS_None, // OpGroupLogicalOrKHR
3576 CEFBS_None, // OpGroupLogicalXorKHR
3577 CEFBS_None, // OpGroupNonUniformAll
3578 CEFBS_None, // OpGroupNonUniformAllEqual
3579 CEFBS_None, // OpGroupNonUniformAny
3580 CEFBS_None, // OpGroupNonUniformBallot
3581 CEFBS_None, // OpGroupNonUniformBallotBitCount
3582 CEFBS_None, // OpGroupNonUniformBallotBitExtract
3583 CEFBS_None, // OpGroupNonUniformBallotFindLSB
3584 CEFBS_None, // OpGroupNonUniformBallotFindMSB
3585 CEFBS_None, // OpGroupNonUniformBitwiseAnd
3586 CEFBS_None, // OpGroupNonUniformBitwiseOr
3587 CEFBS_None, // OpGroupNonUniformBitwiseXor
3588 CEFBS_None, // OpGroupNonUniformBroadcast
3589 CEFBS_None, // OpGroupNonUniformBroadcastFirst
3590 CEFBS_None, // OpGroupNonUniformElect
3591 CEFBS_None, // OpGroupNonUniformFAdd
3592 CEFBS_None, // OpGroupNonUniformFMax
3593 CEFBS_None, // OpGroupNonUniformFMin
3594 CEFBS_None, // OpGroupNonUniformFMul
3595 CEFBS_None, // OpGroupNonUniformIAdd
3596 CEFBS_None, // OpGroupNonUniformIMul
3597 CEFBS_None, // OpGroupNonUniformInverseBallot
3598 CEFBS_None, // OpGroupNonUniformLogicalAnd
3599 CEFBS_None, // OpGroupNonUniformLogicalOr
3600 CEFBS_None, // OpGroupNonUniformLogicalXor
3601 CEFBS_None, // OpGroupNonUniformQuadSwap
3602 CEFBS_None, // OpGroupNonUniformRotateKHR
3603 CEFBS_None, // OpGroupNonUniformSMax
3604 CEFBS_None, // OpGroupNonUniformSMin
3605 CEFBS_None, // OpGroupNonUniformShuffle
3606 CEFBS_None, // OpGroupNonUniformShuffleDown
3607 CEFBS_None, // OpGroupNonUniformShuffleUp
3608 CEFBS_None, // OpGroupNonUniformShuffleXor
3609 CEFBS_None, // OpGroupNonUniformUMax
3610 CEFBS_None, // OpGroupNonUniformUMin
3611 CEFBS_None, // OpGroupReserveReadPipePackets
3612 CEFBS_None, // OpGroupReserveWritePipePackets
3613 CEFBS_None, // OpGroupSMax
3614 CEFBS_None, // OpGroupSMin
3615 CEFBS_None, // OpGroupUMax
3616 CEFBS_None, // OpGroupUMin
3617 CEFBS_None, // OpGroupWaitEvents
3618 CEFBS_None, // OpIAddCarryS
3619 CEFBS_None, // OpIAddCarryV
3620 CEFBS_None, // OpIAddS
3621 CEFBS_None, // OpIAddV
3622 CEFBS_None, // OpIEqual
3623 CEFBS_None, // OpIMulS
3624 CEFBS_None, // OpIMulV
3625 CEFBS_None, // OpINotEqual
3626 CEFBS_None, // OpISubBorrowS
3627 CEFBS_None, // OpISubBorrowV
3628 CEFBS_None, // OpISubS
3629 CEFBS_None, // OpISubV
3630 CEFBS_None, // OpImage
3631 CEFBS_None, // OpImageDrefGather
3632 CEFBS_None, // OpImageFetch
3633 CEFBS_None, // OpImageGather
3634 CEFBS_None, // OpImageQueryFormat
3635 CEFBS_None, // OpImageQueryLevels
3636 CEFBS_None, // OpImageQueryLod
3637 CEFBS_None, // OpImageQueryOrder
3638 CEFBS_None, // OpImageQuerySamples
3639 CEFBS_None, // OpImageQuerySize
3640 CEFBS_None, // OpImageQuerySizeLod
3641 CEFBS_None, // OpImageRead
3642 CEFBS_None, // OpImageSampleDrefExplicitLod
3643 CEFBS_None, // OpImageSampleDrefImplicitLod
3644 CEFBS_None, // OpImageSampleExplicitLod
3645 CEFBS_None, // OpImageSampleFootprintNV
3646 CEFBS_None, // OpImageSampleImplicitLod
3647 CEFBS_None, // OpImageSampleProjDrefExplicitLod
3648 CEFBS_None, // OpImageSampleProjDrefImplicitLod
3649 CEFBS_None, // OpImageSampleProjExplicitLod
3650 CEFBS_None, // OpImageSampleProjImplicitLod
3651 CEFBS_None, // OpImageSparseDrefGather
3652 CEFBS_None, // OpImageSparseFetch
3653 CEFBS_None, // OpImageSparseGather
3654 CEFBS_None, // OpImageSparseRead
3655 CEFBS_None, // OpImageSparseSampleDrefExplicitLod
3656 CEFBS_None, // OpImageSparseSampleDrefImplicitLod
3657 CEFBS_None, // OpImageSparseSampleExplicitLod
3658 CEFBS_None, // OpImageSparseSampleImplicitLod
3659 CEFBS_None, // OpImageSparseSampleProjDrefExplicitLod
3660 CEFBS_None, // OpImageSparseSampleProjDrefImplicitLod
3661 CEFBS_None, // OpImageSparseSampleProjExplicitLod
3662 CEFBS_None, // OpImageSparseSampleProjImplicitLod
3663 CEFBS_None, // OpImageSparseTexelsResident
3664 CEFBS_None, // OpImageTexelPointer
3665 CEFBS_None, // OpImageWrite
3666 CEFBS_None, // OpInBoundsAccessChain
3667 CEFBS_None, // OpInBoundsPtrAccessChain
3668 CEFBS_None, // OpIsFinite
3669 CEFBS_None, // OpIsInf
3670 CEFBS_None, // OpIsNan
3671 CEFBS_None, // OpIsNormal
3672 CEFBS_None, // OpIsValidEvent
3673 CEFBS_None, // OpIsValidReserveId
3674 CEFBS_None, // OpKill
3675 CEFBS_None, // OpLabel
3676 CEFBS_None, // OpLessOrGreater
3677 CEFBS_None, // OpLifetimeStart
3678 CEFBS_None, // OpLifetimeStop
3679 CEFBS_None, // OpLine
3680 CEFBS_None, // OpLoad
3681 CEFBS_None, // OpLogicalAnd
3682 CEFBS_None, // OpLogicalEqual
3683 CEFBS_None, // OpLogicalNot
3684 CEFBS_None, // OpLogicalNotEqual
3685 CEFBS_None, // OpLogicalOr
3686 CEFBS_None, // OpLoopControlINTEL
3687 CEFBS_None, // OpLoopMerge
3688 CEFBS_None, // OpMaskedGatherINTEL
3689 CEFBS_None, // OpMaskedScatterINTEL
3690 CEFBS_None, // OpMatrixTimesMatrix
3691 CEFBS_None, // OpMatrixTimesScalar
3692 CEFBS_None, // OpMatrixTimesVector
3693 CEFBS_None, // OpMemberDecorate
3694 CEFBS_None, // OpMemberDecorateString
3695 CEFBS_None, // OpMemberName
3696 CEFBS_None, // OpMemoryBarrier
3697 CEFBS_None, // OpMemoryModel
3698 CEFBS_None, // OpMemoryNamedBarrier
3699 CEFBS_None, // OpModuleProcessed
3700 CEFBS_None, // OpName
3701 CEFBS_None, // OpNamedBarrierInitialize
3702 CEFBS_None, // OpNoLine
3703 CEFBS_None, // OpNop
3704 CEFBS_None, // OpNot
3705 CEFBS_None, // OpOrdered
3706 CEFBS_None, // OpOuterProduct
3707 CEFBS_None, // OpPhi
3708 CEFBS_None, // OpPoisonKHR
3709 CEFBS_None, // OpPredicatedLoadINTEL
3710 CEFBS_None, // OpPredicatedStoreINTEL
3711 CEFBS_None, // OpPtrAccessChain
3712 CEFBS_None, // OpPtrCastToCrossWorkgroupINTEL
3713 CEFBS_None, // OpPtrCastToGeneric
3714 CEFBS_None, // OpPtrDiff
3715 CEFBS_None, // OpPtrEqual
3716 CEFBS_None, // OpPtrNotEqual
3717 CEFBS_None, // OpQuantizeToF16
3718 CEFBS_None, // OpReadClockKHR
3719 CEFBS_None, // OpReadPipe
3720 CEFBS_None, // OpReadPipeBlockingALTERA
3721 CEFBS_None, // OpReleaseEvent
3722 CEFBS_None, // OpReserveReadPipePackets
3723 CEFBS_None, // OpReserveWritePipePackets
3724 CEFBS_None, // OpReservedReadPipe
3725 CEFBS_None, // OpReservedWritePipe
3726 CEFBS_None, // OpRestoreMemoryINTEL
3727 CEFBS_None, // OpRetainEvent
3728 CEFBS_None, // OpReturn
3729 CEFBS_None, // OpReturnValue
3730 CEFBS_None, // OpRoundFToTF32INTEL
3731 CEFBS_None, // OpSConvert
3732 CEFBS_None, // OpSDivS
3733 CEFBS_None, // OpSDivV
3734 CEFBS_None, // OpSDot
3735 CEFBS_None, // OpSDotAccSat
3736 CEFBS_None, // OpSGreaterThan
3737 CEFBS_None, // OpSGreaterThanEqual
3738 CEFBS_None, // OpSLessThan
3739 CEFBS_None, // OpSLessThanEqual
3740 CEFBS_None, // OpSMod
3741 CEFBS_None, // OpSMulExtended
3742 CEFBS_None, // OpSNegate
3743 CEFBS_None, // OpSRemS
3744 CEFBS_None, // OpSRemV
3745 CEFBS_None, // OpSUDot
3746 CEFBS_None, // OpSUDotAccSat
3747 CEFBS_None, // OpSampledImage
3748 CEFBS_None, // OpSatConvertSToU
3749 CEFBS_None, // OpSatConvertUToS
3750 CEFBS_None, // OpSaveMemoryINTEL
3751 CEFBS_None, // OpSelectSFSCond
3752 CEFBS_None, // OpSelectSFVCond
3753 CEFBS_None, // OpSelectSISCond
3754 CEFBS_None, // OpSelectSIVCond
3755 CEFBS_None, // OpSelectSPSCond
3756 CEFBS_None, // OpSelectSPVCond
3757 CEFBS_None, // OpSelectVFSCond
3758 CEFBS_None, // OpSelectVFVCond
3759 CEFBS_None, // OpSelectVISCond
3760 CEFBS_None, // OpSelectVIVCond
3761 CEFBS_None, // OpSelectVPSCond
3762 CEFBS_None, // OpSelectVPVCond
3763 CEFBS_None, // OpSelectionMerge
3764 CEFBS_None, // OpSetUserEventStatus
3765 CEFBS_None, // OpShiftLeftLogicalS
3766 CEFBS_None, // OpShiftLeftLogicalV
3767 CEFBS_None, // OpShiftRightArithmeticS
3768 CEFBS_None, // OpShiftRightArithmeticV
3769 CEFBS_None, // OpShiftRightLogicalS
3770 CEFBS_None, // OpShiftRightLogicalV
3771 CEFBS_None, // OpSignBitSet
3772 CEFBS_None, // OpSizeOf
3773 CEFBS_None, // OpSource
3774 CEFBS_None, // OpSourceContinued
3775 CEFBS_None, // OpSourceExtension
3776 CEFBS_None, // OpSpecConstant
3777 CEFBS_None, // OpSpecConstantComposite
3778 CEFBS_None, // OpSpecConstantCompositeContinuedINTEL
3779 CEFBS_None, // OpSpecConstantFalse
3780 CEFBS_None, // OpSpecConstantOp
3781 CEFBS_None, // OpSpecConstantTrue
3782 CEFBS_None, // OpStore
3783 CEFBS_None, // OpStrictFAddS
3784 CEFBS_None, // OpStrictFAddV
3785 CEFBS_None, // OpStrictFDivS
3786 CEFBS_None, // OpStrictFDivV
3787 CEFBS_None, // OpStrictFMulS
3788 CEFBS_None, // OpStrictFMulV
3789 CEFBS_None, // OpStrictFRemS
3790 CEFBS_None, // OpStrictFRemV
3791 CEFBS_None, // OpStrictFSubS
3792 CEFBS_None, // OpStrictFSubV
3793 CEFBS_None, // OpString
3794 CEFBS_None, // OpSubgroup2DBlockLoadINTEL
3795 CEFBS_None, // OpSubgroup2DBlockLoadTransformINTEL
3796 CEFBS_None, // OpSubgroup2DBlockLoadTransposeINTEL
3797 CEFBS_None, // OpSubgroup2DBlockPrefetchINTEL
3798 CEFBS_None, // OpSubgroup2DBlockStoreINTEL
3799 CEFBS_None, // OpSubgroupBlockReadINTEL
3800 CEFBS_None, // OpSubgroupBlockWriteINTEL
3801 CEFBS_None, // OpSubgroupImageBlockReadINTEL
3802 CEFBS_None, // OpSubgroupImageBlockWriteINTEL
3803 CEFBS_None, // OpSubgroupImageMediaBlockReadINTEL
3804 CEFBS_None, // OpSubgroupImageMediaBlockWriteINTEL
3805 CEFBS_None, // OpSubgroupMatrixMultiplyAccumulateINTEL
3806 CEFBS_None, // OpSubgroupShuffleDownINTEL
3807 CEFBS_None, // OpSubgroupShuffleINTEL
3808 CEFBS_None, // OpSubgroupShuffleUpINTEL
3809 CEFBS_None, // OpSubgroupShuffleXorINTEL
3810 CEFBS_None, // OpSwitch
3811 CEFBS_None, // OpTranspose
3812 CEFBS_None, // OpTypeAccelerationStructureNV
3813 CEFBS_None, // OpTypeArray
3814 CEFBS_None, // OpTypeBool
3815 CEFBS_None, // OpTypeCooperativeMatrixKHR
3816 CEFBS_None, // OpTypeCooperativeMatrixNV
3817 CEFBS_None, // OpTypeDeviceEvent
3818 CEFBS_None, // OpTypeEvent
3819 CEFBS_None, // OpTypeFloat
3820 CEFBS_None, // OpTypeForwardPointer
3821 CEFBS_None, // OpTypeFunction
3822 CEFBS_None, // OpTypeImage
3823 CEFBS_None, // OpTypeInt
3824 CEFBS_None, // OpTypeMatrix
3825 CEFBS_None, // OpTypeNamedBarrier
3826 CEFBS_None, // OpTypeOpaque
3827 CEFBS_None, // OpTypePipe
3828 CEFBS_None, // OpTypePipeStorage
3829 CEFBS_None, // OpTypePointer
3830 CEFBS_None, // OpTypeQueue
3831 CEFBS_None, // OpTypeReserveId
3832 CEFBS_None, // OpTypeRuntimeArray
3833 CEFBS_None, // OpTypeSampledImage
3834 CEFBS_None, // OpTypeSampler
3835 CEFBS_None, // OpTypeStruct
3836 CEFBS_None, // OpTypeStructContinuedINTEL
3837 CEFBS_None, // OpTypeUntypedPointerKHR
3838 CEFBS_None, // OpTypeVector
3839 CEFBS_None, // OpTypeVectorIdEXT
3840 CEFBS_None, // OpTypeVoid
3841 CEFBS_None, // OpUConvert
3842 CEFBS_None, // OpUDivS
3843 CEFBS_None, // OpUDivV
3844 CEFBS_None, // OpUDot
3845 CEFBS_None, // OpUDotAccSat
3846 CEFBS_None, // OpUGreaterThan
3847 CEFBS_None, // OpUGreaterThanEqual
3848 CEFBS_None, // OpULessThan
3849 CEFBS_None, // OpULessThanEqual
3850 CEFBS_None, // OpUModS
3851 CEFBS_None, // OpUModV
3852 CEFBS_None, // OpUMulExtended
3853 CEFBS_None, // OpUndef
3854 CEFBS_None, // OpUnordered
3855 CEFBS_None, // OpUnreachable
3856 CEFBS_None, // OpUntypedAccessChainKHR
3857 CEFBS_None, // OpUntypedGroupAsyncCopyKHR
3858 CEFBS_None, // OpUntypedInBoundsAccessChainKHR
3859 CEFBS_None, // OpUntypedInBoundsPtrAccessChainKHR
3860 CEFBS_None, // OpUntypedPrefetchKHR
3861 CEFBS_None, // OpUntypedPtrAccessChainKHR
3862 CEFBS_None, // OpUntypedVariableKHR
3863 CEFBS_None, // OpVariable
3864 CEFBS_None, // OpVariableLengthArrayINTEL
3865 CEFBS_None, // OpVectorExtractDynamic
3866 CEFBS_None, // OpVectorInsertDynamic
3867 CEFBS_None, // OpVectorShuffle
3868 CEFBS_None, // OpVectorTimesMatrix
3869 CEFBS_None, // OpVectorTimesScalar
3870 CEFBS_None, // OpWritePipe
3871 CEFBS_None, // OpWritePipeBlockingALTERA
3872 };
3873
3874 assert(Opcode < 861);
3875 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3876}
3877
3878
3879} // namespace llvm::SPIRV_MC
3880
3881#endif // GET_COMPUTE_FEATURES
3882
3883#ifdef GET_AVAILABLE_OPCODE_CHECKER
3884#undef GET_AVAILABLE_OPCODE_CHECKER
3885
3886namespace llvm::SPIRV_MC {
3887
3888bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3889 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3890 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3891 FeatureBitset MissingFeatures =
3892 (AvailableFeatures & RequiredFeatures) ^
3893 RequiredFeatures;
3894 return !MissingFeatures.any();
3895}
3896
3897} // namespace llvm::SPIRV_MC
3898
3899#endif // GET_AVAILABLE_OPCODE_CHECKER
3900
3901#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3902#undef ENABLE_INSTR_PREDICATE_VERIFIER
3903
3904#include <sstream>
3905
3906namespace llvm::SPIRV_MC {
3907
3908#ifndef NDEBUG
3909static const char *SubtargetFeatureNames[] = {
3910 nullptr
3911};
3912
3913#endif // NDEBUG
3914
3915void verifyInstructionPredicates(
3916 unsigned Opcode, const FeatureBitset &Features) {
3917#ifndef NDEBUG
3918 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3919 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3920 FeatureBitset MissingFeatures =
3921 (AvailableFeatures & RequiredFeatures) ^
3922 RequiredFeatures;
3923 if (MissingFeatures.any()) {
3924 std::ostringstream Msg;
3925 Msg << "Attempting to emit " << &SPIRVInstrNameData[SPIRVInstrNameIndices[Opcode]]
3926 << " instruction but the ";
3927 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3928 if (MissingFeatures.test(i))
3929 Msg << SubtargetFeatureNames[i] << " ";
3930 Msg << "predicate(s) are not met";
3931 report_fatal_error(Msg.str().c_str());
3932 }
3933#endif // NDEBUG
3934}
3935
3936} // namespace llvm::SPIRV_MC
3937
3938#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3939
3940