1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SPIRV {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1540
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553
96 G_INSERT = 81, // GenericOpcodes.td:1562
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1572
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340
114 G_LOAD = 99, // GenericOpcodes.td:1367
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1376
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1384
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1393
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420
121 G_STORE = 106, // GenericOpcodes.td:1428
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1446
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502
149 G_FENCE = 134, // GenericOpcodes.td:1518
150 G_PREFETCH = 135, // GenericOpcodes.td:1525
151 G_BRCOND = 136, // GenericOpcodes.td:1665
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1674
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697
154 G_INTRINSIC = 139, // GenericOpcodes.td:1617
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:619
183 G_UADDE = 168, // GenericOpcodes.td:627
184 G_USUBO = 169, // GenericOpcodes.td:649
185 G_USUBE = 170, // GenericOpcodes.td:655
186 G_SADDO = 171, // GenericOpcodes.td:634
187 G_SADDE = 172, // GenericOpcodes.td:642
188 G_SSUBO = 173, // GenericOpcodes.td:662
189 G_SSUBE = 174, // GenericOpcodes.td:669
190 G_UMULO = 175, // GenericOpcodes.td:676
191 G_SMULO = 176, // GenericOpcodes.td:684
192 G_UMULH = 177, // GenericOpcodes.td:693
193 G_SMULH = 178, // GenericOpcodes.td:702
194 G_UADDSAT = 179, // GenericOpcodes.td:714
195 G_SADDSAT = 180, // GenericOpcodes.td:722
196 G_USUBSAT = 181, // GenericOpcodes.td:730
197 G_SSUBSAT = 182, // GenericOpcodes.td:738
198 G_USHLSAT = 183, // GenericOpcodes.td:746
199 G_SSHLSAT = 184, // GenericOpcodes.td:754
200 G_SMULFIX = 185, // GenericOpcodes.td:766
201 G_UMULFIX = 186, // GenericOpcodes.td:773
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:783
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:790
204 G_SDIVFIX = 189, // GenericOpcodes.td:801
205 G_UDIVFIX = 190, // GenericOpcodes.td:808
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:818
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:825
208 G_FADD = 193, // GenericOpcodes.td:998
209 G_FSUB = 194, // GenericOpcodes.td:1006
210 G_FMUL = 195, // GenericOpcodes.td:1014
211 G_FMA = 196, // GenericOpcodes.td:1023
212 G_FMAD = 197, // GenericOpcodes.td:1032
213 G_FDIV = 198, // GenericOpcodes.td:1040
214 G_FREM = 199, // GenericOpcodes.td:1047
215 G_FMODF = 200, // GenericOpcodes.td:1054
216 G_FPOW = 201, // GenericOpcodes.td:1061
217 G_FPOWI = 202, // GenericOpcodes.td:1068
218 G_FEXP = 203, // GenericOpcodes.td:1075
219 G_FEXP2 = 204, // GenericOpcodes.td:1082
220 G_FEXP10 = 205, // GenericOpcodes.td:1089
221 G_FLOG = 206, // GenericOpcodes.td:1096
222 G_FLOG2 = 207, // GenericOpcodes.td:1103
223 G_FLOG10 = 208, // GenericOpcodes.td:1110
224 G_FLDEXP = 209, // GenericOpcodes.td:1117
225 G_FFREXP = 210, // GenericOpcodes.td:1124
226 G_FNEG = 211, // GenericOpcodes.td:836
227 G_FPEXT = 212, // GenericOpcodes.td:842
228 G_FPTRUNC = 213, // GenericOpcodes.td:848
229 G_FPTOSI = 214, // GenericOpcodes.td:854
230 G_FPTOUI = 215, // GenericOpcodes.td:860
231 G_SITOFP = 216, // GenericOpcodes.td:866
232 G_UITOFP = 217, // GenericOpcodes.td:872
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:878
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:884
235 G_FABS = 220, // GenericOpcodes.td:890
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:896
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:909
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:902
239 G_FMINNUM = 224, // GenericOpcodes.td:922
240 G_FMAXNUM = 225, // GenericOpcodes.td:929
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954
243 G_FMINIMUM = 228, // GenericOpcodes.td:964
244 G_FMAXIMUM = 229, // GenericOpcodes.td:971
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:979
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986
247 G_GET_FPENV = 232, // GenericOpcodes.td:1254
248 G_SET_FPENV = 233, // GenericOpcodes.td:1261
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1268
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1275
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1282
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1289
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1346
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1352
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1655
265 G_BRJT = 250, // GenericOpcodes.td:1685
266 G_VSCALE = 251, // GenericOpcodes.td:1583
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1780
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_CLMULR = 270, // GenericOpcodes.td:606
286 G_FCEIL = 271, // GenericOpcodes.td:1131
287 G_FCOS = 272, // GenericOpcodes.td:1138
288 G_FSIN = 273, // GenericOpcodes.td:1145
289 G_FSINCOS = 274, // GenericOpcodes.td:1152
290 G_FTAN = 275, // GenericOpcodes.td:1159
291 G_FACOS = 276, // GenericOpcodes.td:1166
292 G_FASIN = 277, // GenericOpcodes.td:1173
293 G_FATAN = 278, // GenericOpcodes.td:1180
294 G_FATAN2 = 279, // GenericOpcodes.td:1187
295 G_FCOSH = 280, // GenericOpcodes.td:1194
296 G_FSINH = 281, // GenericOpcodes.td:1201
297 G_FTANH = 282, // GenericOpcodes.td:1208
298 G_FSQRT = 283, // GenericOpcodes.td:1218
299 G_FFLOOR = 284, // GenericOpcodes.td:1225
300 G_FRINT = 285, // GenericOpcodes.td:1232
301 G_FNEARBYINT = 286, // GenericOpcodes.td:1239
302 G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248
303 G_BLOCK_ADDR = 288, // GenericOpcodes.td:254
304 G_JUMP_TABLE = 289, // GenericOpcodes.td:260
305 G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266
306 G_STACKSAVE = 291, // GenericOpcodes.td:272
307 G_STACKRESTORE = 292, // GenericOpcodes.td:278
308 G_STRICT_FADD = 293, // GenericOpcodes.td:1839
309 G_STRICT_FSUB = 294, // GenericOpcodes.td:1840
310 G_STRICT_FMUL = 295, // GenericOpcodes.td:1841
311 G_STRICT_FDIV = 296, // GenericOpcodes.td:1842
312 G_STRICT_FREM = 297, // GenericOpcodes.td:1843
313 G_STRICT_FMA = 298, // GenericOpcodes.td:1844
314 G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845
315 G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846
316 G_STRICT_FCMP = 301, // GenericOpcodes.td:1847
317 G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848
318 G_READ_REGISTER = 303, // GenericOpcodes.td:1704
319 G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714
320 G_MEMCPY = 305, // GenericOpcodes.td:1854
321 G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862
322 G_MEMMOVE = 307, // GenericOpcodes.td:1870
323 G_MEMSET = 308, // GenericOpcodes.td:1878
324 G_BZERO = 309, // GenericOpcodes.td:1885
325 G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892
326 G_TRAP = 311, // GenericOpcodes.td:1902
327 G_DEBUGTRAP = 312, // GenericOpcodes.td:1909
328 G_UBSANTRAP = 313, // GenericOpcodes.td:1915
329 G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803
330 G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809
331 G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815
332 G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816
333 G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818
334 G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819
335 G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820
336 G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821
337 G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822
338 G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823
339 G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825
340 G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826
341 G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827
342 G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828
343 G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829
344 G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830
345 G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831
346 G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832
347 G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833
348 G_SBFX = 333, // GenericOpcodes.td:1927
349 G_UBFX = 334, // GenericOpcodes.td:1935
350 ASSIGN_TYPE = 335, // SPIRVInstrInfo.td:18
351 UNKNOWN_type = 336, // SPIRVInstrInfo.td:21
352 OpAbortKHR = 337, // SPIRVInstrInfo.td:681
353 OpAccessChain = 338, // SPIRVInstrInfo.td:274
354 OpAliasDomainDeclINTEL = 339, // SPIRVInstrInfo.td:1008
355 OpAliasScopeDeclINTEL = 340, // SPIRVInstrInfo.td:1010
356 OpAliasScopeListDeclINTEL = 341, // SPIRVInstrInfo.td:1012
357 OpAll = 342, // SPIRVInstrInfo.td:597
358 OpAny = 343, // SPIRVInstrInfo.td:595
359 OpArbitraryFloatACosALTERA = 344, // SPIRVInstrInfo.td:1099
360 OpArbitraryFloatACosPiALTERA = 345, // SPIRVInstrInfo.td:1101
361 OpArbitraryFloatASinALTERA = 346, // SPIRVInstrInfo.td:1095
362 OpArbitraryFloatASinPiALTERA = 347, // SPIRVInstrInfo.td:1097
363 OpArbitraryFloatATan2ALTERA = 348, // SPIRVInstrInfo.td:1107
364 OpArbitraryFloatATanALTERA = 349, // SPIRVInstrInfo.td:1103
365 OpArbitraryFloatATanPiALTERA = 350, // SPIRVInstrInfo.td:1105
366 OpArbitraryFloatAddALTERA = 351, // SPIRVInstrInfo.td:1084
367 OpArbitraryFloatCastALTERA = 352, // SPIRVInstrInfo.td:1115
368 OpArbitraryFloatCastFromIntALTERA = 353, // SPIRVInstrInfo.td:1117
369 OpArbitraryFloatCastToIntALTERA = 354, // SPIRVInstrInfo.td:1119
370 OpArbitraryFloatCbrtALTERA = 355, // SPIRVInstrInfo.td:1033
371 OpArbitraryFloatCosALTERA = 356, // SPIRVInstrInfo.td:1069
372 OpArbitraryFloatCosPiALTERA = 357, // SPIRVInstrInfo.td:1078
373 OpArbitraryFloatDivALTERA = 358, // SPIRVInstrInfo.td:1091
374 OpArbitraryFloatEQALTERA = 359, // SPIRVInstrInfo.td:1028
375 OpArbitraryFloatExp10ALTERA = 360, // SPIRVInstrInfo.td:1060
376 OpArbitraryFloatExp2ALTERA = 361, // SPIRVInstrInfo.td:1057
377 OpArbitraryFloatExpALTERA = 362, // SPIRVInstrInfo.td:1054
378 OpArbitraryFloatExpm1ALTERA = 363, // SPIRVInstrInfo.td:1063
379 OpArbitraryFloatGEALTERA = 364, // SPIRVInstrInfo.td:1022
380 OpArbitraryFloatGTALTERA = 365, // SPIRVInstrInfo.td:1020
381 OpArbitraryFloatHypotALTERA = 366, // SPIRVInstrInfo.td:1036
382 OpArbitraryFloatLEALTERA = 367, // SPIRVInstrInfo.td:1026
383 OpArbitraryFloatLTALTERA = 368, // SPIRVInstrInfo.td:1024
384 OpArbitraryFloatLog10ALTERA = 369, // SPIRVInstrInfo.td:1048
385 OpArbitraryFloatLog1pALTERA = 370, // SPIRVInstrInfo.td:1051
386 OpArbitraryFloatLog2ALTERA = 371, // SPIRVInstrInfo.td:1045
387 OpArbitraryFloatLogALTERA = 372, // SPIRVInstrInfo.td:1042
388 OpArbitraryFloatMulALTERA = 373, // SPIRVInstrInfo.td:1089
389 OpArbitraryFloatPowALTERA = 374, // SPIRVInstrInfo.td:1109
390 OpArbitraryFloatPowNALTERA = 375, // SPIRVInstrInfo.td:1113
391 OpArbitraryFloatPowRALTERA = 376, // SPIRVInstrInfo.td:1111
392 OpArbitraryFloatRSqrtALTERA = 377, // SPIRVInstrInfo.td:1093
393 OpArbitraryFloatRecipALTERA = 378, // SPIRVInstrInfo.td:1030
394 OpArbitraryFloatSinALTERA = 379, // SPIRVInstrInfo.td:1066
395 OpArbitraryFloatSinCosALTERA = 380, // SPIRVInstrInfo.td:1072
396 OpArbitraryFloatSinCosPiALTERA = 381, // SPIRVInstrInfo.td:1081
397 OpArbitraryFloatSinPiALTERA = 382, // SPIRVInstrInfo.td:1075
398 OpArbitraryFloatSqrtALTERA = 383, // SPIRVInstrInfo.td:1039
399 OpArbitraryFloatSubALTERA = 384, // SPIRVInstrInfo.td:1087
400 OpArithmeticFenceEXT = 385, // SPIRVInstrInfo.td:996
401 OpArrayLength = 386, // SPIRVInstrInfo.td:282
402 OpAsmCallINTEL = 387, // SPIRVInstrInfo.td:962
403 OpAsmINTEL = 388, // SPIRVInstrInfo.td:959
404 OpAsmTargetINTEL = 389, // SPIRVInstrInfo.td:958
405 OpAssumeTrueKHR = 390, // SPIRVInstrInfo.td:106
406 OpAtomicAnd = 391, // SPIRVInstrInfo.td:725
407 OpAtomicCompareExchange = 392, // SPIRVInstrInfo.td:705
408 OpAtomicCompareExchangeWeak = 393, // SPIRVInstrInfo.td:709
409 OpAtomicExchange = 394, // SPIRVInstrInfo.td:702
410 OpAtomicFAddEXT = 395, // SPIRVInstrInfo.td:729
411 OpAtomicFMaxEXT = 396, // SPIRVInstrInfo.td:731
412 OpAtomicFMinEXT = 397, // SPIRVInstrInfo.td:730
413 OpAtomicFlagClear = 398, // SPIRVInstrInfo.td:734
414 OpAtomicFlagTestAndSet = 399, // SPIRVInstrInfo.td:733
415 OpAtomicIAdd = 400, // SPIRVInstrInfo.td:717
416 OpAtomicIDecrement = 401, // SPIRVInstrInfo.td:715
417 OpAtomicIIncrement = 402, // SPIRVInstrInfo.td:714
418 OpAtomicISub = 403, // SPIRVInstrInfo.td:718
419 OpAtomicLoad = 404, // SPIRVInstrInfo.td:698
420 OpAtomicOr = 405, // SPIRVInstrInfo.td:726
421 OpAtomicSMax = 406, // SPIRVInstrInfo.td:722
422 OpAtomicSMin = 407, // SPIRVInstrInfo.td:720
423 OpAtomicStore = 408, // SPIRVInstrInfo.td:700
424 OpAtomicUMax = 409, // SPIRVInstrInfo.td:723
425 OpAtomicUMin = 410, // SPIRVInstrInfo.td:721
426 OpAtomicXor = 411, // SPIRVInstrInfo.td:727
427 OpBitCount = 412, // SPIRVInstrInfo.td:591
428 OpBitFieldInsert = 413, // SPIRVInstrInfo.td:581
429 OpBitFieldSExtract = 414, // SPIRVInstrInfo.td:584
430 OpBitFieldUExtract = 415, // SPIRVInstrInfo.td:587
431 OpBitReverse = 416, // SPIRVInstrInfo.td:590
432 OpBitcast = 417, // SPIRVInstrInfo.td:475
433 OpBitwiseAndS = 418, // SPIRVInstrInfo.td:48
434 OpBitwiseAndV = 419, // SPIRVInstrInfo.td:53
435 OpBitwiseFunctionINTEL = 420, // SPIRVInstrInfo.td:1016
436 OpBitwiseOrS = 421, // SPIRVInstrInfo.td:48
437 OpBitwiseOrV = 422, // SPIRVInstrInfo.td:53
438 OpBitwiseXorS = 423, // SPIRVInstrInfo.td:48
439 OpBitwiseXorV = 424, // SPIRVInstrInfo.td:53
440 OpBranch = 425, // SPIRVInstrInfo.td:671
441 OpBranchConditional = 426, // SPIRVInstrInfo.td:672
442 OpBuildNDRange = 427, // SPIRVInstrInfo.td:815
443 OpCapability = 428, // SPIRVInstrInfo.td:164
444 OpCaptureEventProfilingInfo = 429, // SPIRVInstrInfo.td:810
445 OpCommitReadPipe = 430, // SPIRVInstrInfo.td:832
446 OpCommitWritePipe = 431, // SPIRVInstrInfo.td:834
447 OpCompositeConstruct = 432, // SPIRVInstrInfo.td:496
448 OpCompositeConstructContinuedINTEL = 433, // SPIRVInstrInfo.td:498
449 OpCompositeExtract = 434, // SPIRVInstrInfo.td:500
450 OpCompositeInsert = 435, // SPIRVInstrInfo.td:502
451 OpConstantComposite = 436, // SPIRVInstrInfo.td:236
452 OpConstantCompositeContinuedINTEL = 437, // SPIRVInstrInfo.td:238
453 OpConstantF = 438, // SPIRVInstrInfo.td:224
454 OpConstantFalse = 439, // SPIRVInstrInfo.td:233
455 OpConstantFunctionPointerINTEL = 440, // SPIRVInstrInfo.td:914
456 OpConstantI = 441, // SPIRVInstrInfo.td:222
457 OpConstantNull = 442, // SPIRVInstrInfo.td:244
458 OpConstantSampler = 443, // SPIRVInstrInfo.td:241
459 OpConstantTrue = 444, // SPIRVInstrInfo.td:231
460 OpControlBarrier = 445, // SPIRVInstrInfo.td:746
461 OpControlBarrierArriveINTEL = 446, // SPIRVInstrInfo.td:755
462 OpControlBarrierWaitINTEL = 447, // SPIRVInstrInfo.td:757
463 OpConvertBF16ToFINTEL = 448, // SPIRVInstrInfo.td:483
464 OpConvertFToBF16INTEL = 449, // SPIRVInstrInfo.td:482
465 OpConvertFToS = 450, // SPIRVInstrInfo.td:455
466 OpConvertFToU = 451, // SPIRVInstrInfo.td:454
467 OpConvertHandleToImageINTEL = 452, // SPIRVInstrInfo.td:1000
468 OpConvertHandleToSampledImageINTEL = 453, // SPIRVInstrInfo.td:1004
469 OpConvertHandleToSamplerINTEL = 454, // SPIRVInstrInfo.td:1002
470 OpConvertPtrToU = 455, // SPIRVInstrInfo.td:465
471 OpConvertSToF = 456, // SPIRVInstrInfo.td:456
472 OpConvertUToF = 457, // SPIRVInstrInfo.td:457
473 OpConvertUToPtr = 458, // SPIRVInstrInfo.td:470
474 OpCooperativeMatrixConstructCheckedINTEL = 459, // SPIRVInstrInfo.td:985
475 OpCooperativeMatrixGetElementCoordINTEL = 460, // SPIRVInstrInfo.td:988
476 OpCooperativeMatrixLengthKHR = 461, // SPIRVInstrInfo.td:975
477 OpCooperativeMatrixLoadCheckedINTEL = 462, // SPIRVInstrInfo.td:979
478 OpCooperativeMatrixLoadKHR = 463, // SPIRVInstrInfo.td:966
479 OpCooperativeMatrixMulAddKHR = 464, // SPIRVInstrInfo.td:972
480 OpCooperativeMatrixPrefetchINTEL = 465, // SPIRVInstrInfo.td:991
481 OpCooperativeMatrixStoreCheckedINTEL = 466, // SPIRVInstrInfo.td:982
482 OpCooperativeMatrixStoreKHR = 467, // SPIRVInstrInfo.td:969
483 OpCopyLogical = 468, // SPIRVInstrInfo.td:506
484 OpCopyMemory = 469, // SPIRVInstrInfo.td:270
485 OpCopyMemorySized = 470, // SPIRVInstrInfo.td:272
486 OpCopyObject = 471, // SPIRVInstrInfo.td:504
487 OpCreateUserEvent = 472, // SPIRVInstrInfo.td:804
488 OpCrossWorkgroupCastToPtrINTEL = 473, // SPIRVInstrInfo.td:479
489 OpDPdx = 474, // SPIRVInstrInfo.td:647
490 OpDPdxCoarse = 475, // SPIRVInstrInfo.td:655
491 OpDPdxFine = 476, // SPIRVInstrInfo.td:651
492 OpDPdy = 477, // SPIRVInstrInfo.td:648
493 OpDPdyCoarse = 478, // SPIRVInstrInfo.td:656
494 OpDPdyFine = 479, // SPIRVInstrInfo.td:652
495 OpDecorate = 480, // SPIRVInstrInfo.td:128
496 OpDecorateId = 481, // SPIRVInstrInfo.td:136
497 OpDecorateString = 482, // SPIRVInstrInfo.td:138
498 OpDemoteToHelperInvocation = 483, // SPIRVInstrInfo.td:686
499 OpDot = 484, // SPIRVInstrInfo.td:547
500 OpEmitStreamVertex = 485, // SPIRVInstrInfo.td:741
501 OpEmitVertex = 486, // SPIRVInstrInfo.td:739
502 OpEndPrimitive = 487, // SPIRVInstrInfo.td:740
503 OpEndStreamPrimitive = 488, // SPIRVInstrInfo.td:742
504 OpEnqueueKernel = 489, // SPIRVInstrInfo.td:791
505 OpEntryPoint = 490, // SPIRVInstrInfo.td:159
506 OpExecutionMode = 491, // SPIRVInstrInfo.td:162
507 OpExecutionModeId = 492, // SPIRVInstrInfo.td:165
508 OpExpectKHR = 493, // SPIRVInstrInfo.td:107
509 OpExtInst = 494, // SPIRVInstrInfo.td:153
510 OpExtInstImport = 495, // SPIRVInstrInfo.td:147
511 OpExtension = 496, // SPIRVInstrInfo.td:146
512 OpFAddS = 497, // SPIRVInstrInfo.td:46
513 OpFAddV = 498, // SPIRVInstrInfo.td:51
514 OpFConvert = 499, // SPIRVInstrInfo.td:461
515 OpFDivS = 500, // SPIRVInstrInfo.td:46
516 OpFDivV = 501, // SPIRVInstrInfo.td:51
517 OpFMod = 502, // SPIRVInstrInfo.td:538
518 OpFMulS = 503, // SPIRVInstrInfo.td:46
519 OpFMulV = 504, // SPIRVInstrInfo.td:51
520 OpFNegate = 505, // SPIRVInstrInfo.td:511
521 OpFNegateV = 506, // SPIRVInstrInfo.td:512
522 OpFOrdEqual = 507, // SPIRVInstrInfo.td:630
523 OpFOrdGreaterThan = 508, // SPIRVInstrInfo.td:637
524 OpFOrdGreaterThanEqual = 509, // SPIRVInstrInfo.td:642
525 OpFOrdLessThan = 510, // SPIRVInstrInfo.td:635
526 OpFOrdLessThanEqual = 511, // SPIRVInstrInfo.td:640
527 OpFOrdNotEqual = 512, // SPIRVInstrInfo.td:632
528 OpFRemS = 513, // SPIRVInstrInfo.td:46
529 OpFRemV = 514, // SPIRVInstrInfo.td:51
530 OpFSubS = 515, // SPIRVInstrInfo.td:46
531 OpFSubV = 516, // SPIRVInstrInfo.td:51
532 OpFUnordEqual = 517, // SPIRVInstrInfo.td:631
533 OpFUnordGreaterThan = 518, // SPIRVInstrInfo.td:638
534 OpFUnordGreaterThanEqual = 519, // SPIRVInstrInfo.td:643
535 OpFUnordLessThan = 520, // SPIRVInstrInfo.td:636
536 OpFUnordLessThanEqual = 521, // SPIRVInstrInfo.td:641
537 OpFUnordNotEqual = 522, // SPIRVInstrInfo.td:633
538 OpFixedCosALTERA = 523, // SPIRVInstrInfo.td:1160
539 OpFixedCosPiALTERA = 524, // SPIRVInstrInfo.td:1166
540 OpFixedExpALTERA = 525, // SPIRVInstrInfo.td:1172
541 OpFixedLogALTERA = 526, // SPIRVInstrInfo.td:1170
542 OpFixedRecipALTERA = 527, // SPIRVInstrInfo.td:1154
543 OpFixedRsqrtALTERA = 528, // SPIRVInstrInfo.td:1156
544 OpFixedSinALTERA = 529, // SPIRVInstrInfo.td:1158
545 OpFixedSinCosALTERA = 530, // SPIRVInstrInfo.td:1162
546 OpFixedSinCosPiALTERA = 531, // SPIRVInstrInfo.td:1168
547 OpFixedSinPiALTERA = 532, // SPIRVInstrInfo.td:1164
548 OpFixedSqrtALTERA = 533, // SPIRVInstrInfo.td:1152
549 OpFmaKHR = 534, // SPIRVInstrInfo.td:567
550 OpFreezeKHR = 535, // SPIRVInstrInfo.td:103
551 OpFunction = 536, // SPIRVInstrInfo.td:336
552 OpFunctionCall = 537, // SPIRVInstrInfo.td:344
553 OpFunctionEnd = 538, // SPIRVInstrInfo.td:341
554 OpFunctionParameter = 539, // SPIRVInstrInfo.td:339
555 OpFunctionPointerCallINTEL = 540, // SPIRVInstrInfo.td:919
556 OpFwidth = 541, // SPIRVInstrInfo.td:649
557 OpFwidthCoarse = 542, // SPIRVInstrInfo.td:657
558 OpFwidthFine = 543, // SPIRVInstrInfo.td:653
559 OpGenericCastToPtr = 544, // SPIRVInstrInfo.td:472
560 OpGenericCastToPtrExplicit = 545, // SPIRVInstrInfo.td:473
561 OpGenericPtrMemSemantics = 546, // SPIRVInstrInfo.td:284
562 OpGetDefaultQueue = 547, // SPIRVInstrInfo.td:813
563 OpGetKernelNDrangeMaxSubGroupSize = 548, // SPIRVInstrInfo.td:796
564 OpGetKernelNDrangeSubGroupCount = 549, // SPIRVInstrInfo.td:794
565 OpGetKernelPreferredWorkGroupSizeMultiple = 550, // SPIRVInstrInfo.td:800
566 OpGetKernelWorkGroupSize = 551, // SPIRVInstrInfo.td:798
567 OpGetMaxPipePackets = 552, // SPIRVInstrInfo.td:840
568 OpGetNumPipePackets = 553, // SPIRVInstrInfo.td:838
569 OpGroupAll = 554, // SPIRVInstrInfo.td:767
570 OpGroupAny = 555, // SPIRVInstrInfo.td:769
571 OpGroupAsyncCopy = 556, // SPIRVInstrInfo.td:762
572 OpGroupBitwiseAndKHR = 557, // SPIRVInstrInfo.td:950
573 OpGroupBitwiseOrKHR = 558, // SPIRVInstrInfo.td:951
574 OpGroupBitwiseXorKHR = 559, // SPIRVInstrInfo.td:952
575 OpGroupBroadcast = 560, // SPIRVInstrInfo.td:771
576 OpGroupCommitReadPipe = 561, // SPIRVInstrInfo.td:846
577 OpGroupCommitWritePipe = 562, // SPIRVInstrInfo.td:848
578 OpGroupFAdd = 563, // SPIRVInstrInfo.td:778
579 OpGroupFMax = 564, // SPIRVInstrInfo.td:782
580 OpGroupFMin = 565, // SPIRVInstrInfo.td:779
581 OpGroupFMulKHR = 566, // SPIRVInstrInfo.td:949
582 OpGroupIAdd = 567, // SPIRVInstrInfo.td:777
583 OpGroupIMulKHR = 568, // SPIRVInstrInfo.td:948
584 OpGroupLogicalAndKHR = 569, // SPIRVInstrInfo.td:953
585 OpGroupLogicalOrKHR = 570, // SPIRVInstrInfo.td:954
586 OpGroupLogicalXorKHR = 571, // SPIRVInstrInfo.td:955
587 OpGroupNonUniformAll = 572, // SPIRVInstrInfo.td:861
588 OpGroupNonUniformAllEqual = 573, // SPIRVInstrInfo.td:863
589 OpGroupNonUniformAny = 574, // SPIRVInstrInfo.td:862
590 OpGroupNonUniformBallot = 575, // SPIRVInstrInfo.td:866
591 OpGroupNonUniformBallotBitCount = 576, // SPIRVInstrInfo.td:869
592 OpGroupNonUniformBallotBitExtract = 577, // SPIRVInstrInfo.td:868
593 OpGroupNonUniformBallotFindLSB = 578, // SPIRVInstrInfo.td:873
594 OpGroupNonUniformBallotFindMSB = 579, // SPIRVInstrInfo.td:874
595 OpGroupNonUniformBitwiseAnd = 580, // SPIRVInstrInfo.td:893
596 OpGroupNonUniformBitwiseOr = 581, // SPIRVInstrInfo.td:894
597 OpGroupNonUniformBitwiseXor = 582, // SPIRVInstrInfo.td:895
598 OpGroupNonUniformBroadcast = 583, // SPIRVInstrInfo.td:864
599 OpGroupNonUniformBroadcastFirst = 584, // SPIRVInstrInfo.td:865
600 OpGroupNonUniformElect = 585, // SPIRVInstrInfo.td:853
601 OpGroupNonUniformFAdd = 586, // SPIRVInstrInfo.td:884
602 OpGroupNonUniformFMax = 587, // SPIRVInstrInfo.td:892
603 OpGroupNonUniformFMin = 588, // SPIRVInstrInfo.td:889
604 OpGroupNonUniformFMul = 589, // SPIRVInstrInfo.td:886
605 OpGroupNonUniformIAdd = 590, // SPIRVInstrInfo.td:883
606 OpGroupNonUniformIMul = 591, // SPIRVInstrInfo.td:885
607 OpGroupNonUniformInverseBallot = 592, // SPIRVInstrInfo.td:867
608 OpGroupNonUniformLogicalAnd = 593, // SPIRVInstrInfo.td:896
609 OpGroupNonUniformLogicalOr = 594, // SPIRVInstrInfo.td:897
610 OpGroupNonUniformLogicalXor = 595, // SPIRVInstrInfo.td:898
611 OpGroupNonUniformQuadSwap = 596, // SPIRVInstrInfo.td:899
612 OpGroupNonUniformRotateKHR = 597, // SPIRVInstrInfo.td:902
613 OpGroupNonUniformSMax = 598, // SPIRVInstrInfo.td:890
614 OpGroupNonUniformSMin = 599, // SPIRVInstrInfo.td:887
615 OpGroupNonUniformShuffle = 600, // SPIRVInstrInfo.td:875
616 OpGroupNonUniformShuffleDown = 601, // SPIRVInstrInfo.td:878
617 OpGroupNonUniformShuffleUp = 602, // SPIRVInstrInfo.td:877
618 OpGroupNonUniformShuffleXor = 603, // SPIRVInstrInfo.td:876
619 OpGroupNonUniformUMax = 604, // SPIRVInstrInfo.td:891
620 OpGroupNonUniformUMin = 605, // SPIRVInstrInfo.td:888
621 OpGroupReserveReadPipePackets = 606, // SPIRVInstrInfo.td:842
622 OpGroupReserveWritePipePackets = 607, // SPIRVInstrInfo.td:844
623 OpGroupSMax = 608, // SPIRVInstrInfo.td:784
624 OpGroupSMin = 609, // SPIRVInstrInfo.td:781
625 OpGroupUMax = 610, // SPIRVInstrInfo.td:783
626 OpGroupUMin = 611, // SPIRVInstrInfo.td:780
627 OpGroupWaitEvents = 612, // SPIRVInstrInfo.td:765
628 OpIAddCarryS = 613, // SPIRVInstrInfo.td:48
629 OpIAddCarryV = 614, // SPIRVInstrInfo.td:53
630 OpIAddS = 615, // SPIRVInstrInfo.td:48
631 OpIAddV = 616, // SPIRVInstrInfo.td:53
632 OpIEqual = 617, // SPIRVInstrInfo.td:618
633 OpIMulS = 618, // SPIRVInstrInfo.td:48
634 OpIMulV = 619, // SPIRVInstrInfo.td:53
635 OpINotEqual = 620, // SPIRVInstrInfo.td:619
636 OpISubBorrowS = 621, // SPIRVInstrInfo.td:48
637 OpISubBorrowV = 622, // SPIRVInstrInfo.td:53
638 OpISubS = 623, // SPIRVInstrInfo.td:48
639 OpISubV = 624, // SPIRVInstrInfo.td:53
640 OpImage = 625, // SPIRVInstrInfo.td:395
641 OpImageDrefGather = 626, // SPIRVInstrInfo.td:385
642 OpImageFetch = 627, // SPIRVInstrInfo.td:379
643 OpImageGather = 628, // SPIRVInstrInfo.td:382
644 OpImageQueryFormat = 629, // SPIRVInstrInfo.td:396
645 OpImageQueryLevels = 630, // SPIRVInstrInfo.td:401
646 OpImageQueryLod = 631, // SPIRVInstrInfo.td:400
647 OpImageQueryOrder = 632, // SPIRVInstrInfo.td:397
648 OpImageQuerySamples = 633, // SPIRVInstrInfo.td:402
649 OpImageQuerySize = 634, // SPIRVInstrInfo.td:399
650 OpImageQuerySizeLod = 635, // SPIRVInstrInfo.td:398
651 OpImageRead = 636, // SPIRVInstrInfo.td:389
652 OpImageSampleDrefExplicitLod = 637, // SPIRVInstrInfo.td:361
653 OpImageSampleDrefImplicitLod = 638, // SPIRVInstrInfo.td:358
654 OpImageSampleExplicitLod = 639, // SPIRVInstrInfo.td:354
655 OpImageSampleFootprintNV = 640, // SPIRVInstrInfo.td:448
656 OpImageSampleImplicitLod = 641, // SPIRVInstrInfo.td:351
657 OpImageSampleProjDrefExplicitLod = 642, // SPIRVInstrInfo.td:375
658 OpImageSampleProjDrefImplicitLod = 643, // SPIRVInstrInfo.td:372
659 OpImageSampleProjExplicitLod = 644, // SPIRVInstrInfo.td:368
660 OpImageSampleProjImplicitLod = 645, // SPIRVInstrInfo.td:365
661 OpImageSparseDrefGather = 646, // SPIRVInstrInfo.td:438
662 OpImageSparseFetch = 647, // SPIRVInstrInfo.td:432
663 OpImageSparseGather = 648, // SPIRVInstrInfo.td:435
664 OpImageSparseRead = 649, // SPIRVInstrInfo.td:444
665 OpImageSparseSampleDrefExplicitLod = 650, // SPIRVInstrInfo.td:414
666 OpImageSparseSampleDrefImplicitLod = 651, // SPIRVInstrInfo.td:411
667 OpImageSparseSampleExplicitLod = 652, // SPIRVInstrInfo.td:407
668 OpImageSparseSampleImplicitLod = 653, // SPIRVInstrInfo.td:404
669 OpImageSparseSampleProjDrefExplicitLod = 654, // SPIRVInstrInfo.td:428
670 OpImageSparseSampleProjDrefImplicitLod = 655, // SPIRVInstrInfo.td:425
671 OpImageSparseSampleProjExplicitLod = 656, // SPIRVInstrInfo.td:421
672 OpImageSparseSampleProjImplicitLod = 657, // SPIRVInstrInfo.td:418
673 OpImageSparseTexelsResident = 658, // SPIRVInstrInfo.td:442
674 OpImageTexelPointer = 659, // SPIRVInstrInfo.td:263
675 OpImageWrite = 660, // SPIRVInstrInfo.td:392
676 OpInBoundsAccessChain = 661, // SPIRVInstrInfo.td:276
677 OpInBoundsPtrAccessChain = 662, // SPIRVInstrInfo.td:286
678 OpIsFinite = 663, // SPIRVInstrInfo.td:602
679 OpIsInf = 664, // SPIRVInstrInfo.td:601
680 OpIsNan = 665, // SPIRVInstrInfo.td:600
681 OpIsNormal = 666, // SPIRVInstrInfo.td:603
682 OpIsValidEvent = 667, // SPIRVInstrInfo.td:806
683 OpIsValidReserveId = 668, // SPIRVInstrInfo.td:836
684 OpKill = 669, // SPIRVInstrInfo.td:677
685 OpLabel = 670, // SPIRVInstrInfo.td:669
686 OpLessOrGreater = 671, // SPIRVInstrInfo.td:606
687 OpLifetimeStart = 672, // SPIRVInstrInfo.td:684
688 OpLifetimeStop = 673, // SPIRVInstrInfo.td:685
689 OpLine = 674, // SPIRVInstrInfo.td:121
690 OpLoad = 675, // SPIRVInstrInfo.td:266
691 OpLogicalAnd = 676, // SPIRVInstrInfo.td:613
692 OpLogicalEqual = 677, // SPIRVInstrInfo.td:610
693 OpLogicalNot = 678, // SPIRVInstrInfo.td:614
694 OpLogicalNotEqual = 679, // SPIRVInstrInfo.td:611
695 OpLogicalOr = 680, // SPIRVInstrInfo.td:612
696 OpLoopControlINTEL = 681, // SPIRVInstrInfo.td:665
697 OpLoopMerge = 682, // SPIRVInstrInfo.td:663
698 OpMaskedGatherINTEL = 683, // SPIRVInstrInfo.td:1176
699 OpMaskedScatterINTEL = 684, // SPIRVInstrInfo.td:1178
700 OpMatrixTimesMatrix = 685, // SPIRVInstrInfo.td:544
701 OpMatrixTimesScalar = 686, // SPIRVInstrInfo.td:541
702 OpMatrixTimesVector = 687, // SPIRVInstrInfo.td:543
703 OpMemberDecorate = 688, // SPIRVInstrInfo.td:130
704 OpMemberDecorateString = 689, // SPIRVInstrInfo.td:140
705 OpMemberName = 690, // SPIRVInstrInfo.td:118
706 OpMemoryBarrier = 691, // SPIRVInstrInfo.td:748
707 OpMemoryModel = 692, // SPIRVInstrInfo.td:157
708 OpMemoryNamedBarrier = 693, // SPIRVInstrInfo.td:751
709 OpModuleProcessed = 694, // SPIRVInstrInfo.td:123
710 OpName = 695, // SPIRVInstrInfo.td:117
711 OpNamedBarrierInitialize = 696, // SPIRVInstrInfo.td:750
712 OpNoLine = 697, // SPIRVInstrInfo.td:122
713 OpNop = 698, // SPIRVInstrInfo.td:97
714 OpNot = 699, // SPIRVInstrInfo.td:579
715 OpOrdered = 700, // SPIRVInstrInfo.td:607
716 OpOuterProduct = 701, // SPIRVInstrInfo.td:546
717 OpPhi = 702, // SPIRVInstrInfo.td:661
718 OpPoisonKHR = 703, // SPIRVInstrInfo.td:102
719 OpPredicatedLoadINTEL = 704, // SPIRVInstrInfo.td:1140
720 OpPredicatedStoreINTEL = 705, // SPIRVInstrInfo.td:1142
721 OpPtrAccessChain = 706, // SPIRVInstrInfo.td:279
722 OpPtrCastToCrossWorkgroupINTEL = 707, // SPIRVInstrInfo.td:478
723 OpPtrCastToGeneric = 708, // SPIRVInstrInfo.td:471
724 OpPtrDiff = 709, // SPIRVInstrInfo.td:293
725 OpPtrEqual = 710, // SPIRVInstrInfo.td:289
726 OpPtrNotEqual = 711, // SPIRVInstrInfo.td:291
727 OpQuantizeToF16 = 712, // SPIRVInstrInfo.td:463
728 OpReadClockKHR = 713, // SPIRVInstrInfo.td:907
729 OpReadPipe = 714, // SPIRVInstrInfo.td:820
730 OpReadPipeBlockingALTERA = 715, // SPIRVInstrInfo.td:1146
731 OpReleaseEvent = 716, // SPIRVInstrInfo.td:803
732 OpReserveReadPipePackets = 717, // SPIRVInstrInfo.td:828
733 OpReserveWritePipePackets = 718, // SPIRVInstrInfo.td:830
734 OpReservedReadPipe = 719, // SPIRVInstrInfo.td:824
735 OpReservedWritePipe = 720, // SPIRVInstrInfo.td:826
736 OpRestoreMemoryINTEL = 721, // SPIRVInstrInfo.td:331
737 OpRetainEvent = 722, // SPIRVInstrInfo.td:802
738 OpReturn = 723, // SPIRVInstrInfo.td:678
739 OpReturnValue = 724, // SPIRVInstrInfo.td:679
740 OpRoundFToTF32INTEL = 725, // SPIRVInstrInfo.td:486
741 OpSConvert = 726, // SPIRVInstrInfo.td:460
742 OpSDivS = 727, // SPIRVInstrInfo.td:48
743 OpSDivV = 728, // SPIRVInstrInfo.td:53
744 OpSDot = 729, // SPIRVInstrInfo.td:554
745 OpSDotAccSat = 730, // SPIRVInstrInfo.td:560
746 OpSGreaterThan = 731, // SPIRVInstrInfo.td:622
747 OpSGreaterThanEqual = 732, // SPIRVInstrInfo.td:624
748 OpSLessThan = 733, // SPIRVInstrInfo.td:626
749 OpSLessThanEqual = 734, // SPIRVInstrInfo.td:628
750 OpSMod = 735, // SPIRVInstrInfo.td:533
751 OpSMulExtended = 736, // SPIRVInstrInfo.td:552
752 OpSNegate = 737, // SPIRVInstrInfo.td:510
753 OpSRemS = 738, // SPIRVInstrInfo.td:48
754 OpSRemV = 739, // SPIRVInstrInfo.td:53
755 OpSUDot = 740, // SPIRVInstrInfo.td:558
756 OpSUDotAccSat = 741, // SPIRVInstrInfo.td:564
757 OpSampledImage = 742, // SPIRVInstrInfo.td:349
758 OpSatConvertSToU = 743, // SPIRVInstrInfo.td:467
759 OpSatConvertUToS = 744, // SPIRVInstrInfo.td:468
760 OpSaveMemoryINTEL = 745, // SPIRVInstrInfo.td:329
761 OpSelectSFSCond = 746, // SPIRVInstrInfo.td:67
762 OpSelectSFVCond = 747, // SPIRVInstrInfo.td:68
763 OpSelectSISCond = 748, // SPIRVInstrInfo.td:63
764 OpSelectSIVCond = 749, // SPIRVInstrInfo.td:64
765 OpSelectSPSCond = 750, // SPIRVInstrInfo.td:59
766 OpSelectSPVCond = 751, // SPIRVInstrInfo.td:60
767 OpSelectVFSCond = 752, // SPIRVInstrInfo.td:80
768 OpSelectVFVCond = 753, // SPIRVInstrInfo.td:81
769 OpSelectVISCond = 754, // SPIRVInstrInfo.td:76
770 OpSelectVIVCond = 755, // SPIRVInstrInfo.td:77
771 OpSelectVPSCond = 756, // SPIRVInstrInfo.td:72
772 OpSelectVPVCond = 757, // SPIRVInstrInfo.td:73
773 OpSelectionMerge = 758, // SPIRVInstrInfo.td:667
774 OpSetUserEventStatus = 759, // SPIRVInstrInfo.td:808
775 OpShiftLeftLogicalS = 760, // SPIRVInstrInfo.td:48
776 OpShiftLeftLogicalV = 761, // SPIRVInstrInfo.td:53
777 OpShiftRightArithmeticS = 762, // SPIRVInstrInfo.td:48
778 OpShiftRightArithmeticV = 763, // SPIRVInstrInfo.td:53
779 OpShiftRightLogicalS = 764, // SPIRVInstrInfo.td:48
780 OpShiftRightLogicalV = 765, // SPIRVInstrInfo.td:53
781 OpSignBitSet = 766, // SPIRVInstrInfo.td:604
782 OpSizeOf = 767, // SPIRVInstrInfo.td:99
783 OpSource = 768, // SPIRVInstrInfo.td:113
784 OpSourceContinued = 769, // SPIRVInstrInfo.td:111
785 OpSourceExtension = 770, // SPIRVInstrInfo.td:115
786 OpSpecConstant = 771, // SPIRVInstrInfo.td:248
787 OpSpecConstantComposite = 772, // SPIRVInstrInfo.td:250
788 OpSpecConstantCompositeContinuedINTEL = 773, // SPIRVInstrInfo.td:252
789 OpSpecConstantFalse = 774, // SPIRVInstrInfo.td:247
790 OpSpecConstantOp = 775, // SPIRVInstrInfo.td:256
791 OpSpecConstantTrue = 776, // SPIRVInstrInfo.td:246
792 OpStore = 777, // SPIRVInstrInfo.td:268
793 OpStrictFAddS = 778, // SPIRVInstrInfo.td:46
794 OpStrictFAddV = 779, // SPIRVInstrInfo.td:51
795 OpStrictFDivS = 780, // SPIRVInstrInfo.td:46
796 OpStrictFDivV = 781, // SPIRVInstrInfo.td:51
797 OpStrictFMulS = 782, // SPIRVInstrInfo.td:46
798 OpStrictFMulV = 783, // SPIRVInstrInfo.td:51
799 OpStrictFRemS = 784, // SPIRVInstrInfo.td:46
800 OpStrictFRemV = 785, // SPIRVInstrInfo.td:51
801 OpStrictFSubS = 786, // SPIRVInstrInfo.td:46
802 OpStrictFSubV = 787, // SPIRVInstrInfo.td:51
803 OpString = 788, // SPIRVInstrInfo.td:120
804 OpSubgroup2DBlockLoadINTEL = 789, // SPIRVInstrInfo.td:1123
805 OpSubgroup2DBlockLoadTransformINTEL = 790, // SPIRVInstrInfo.td:1129
806 OpSubgroup2DBlockLoadTransposeINTEL = 791, // SPIRVInstrInfo.td:1126
807 OpSubgroup2DBlockPrefetchINTEL = 792, // SPIRVInstrInfo.td:1132
808 OpSubgroup2DBlockStoreINTEL = 793, // SPIRVInstrInfo.td:1135
809 OpSubgroupBlockReadINTEL = 794, // SPIRVInstrInfo.td:932
810 OpSubgroupBlockWriteINTEL = 795, // SPIRVInstrInfo.td:934
811 OpSubgroupImageBlockReadINTEL = 796, // SPIRVInstrInfo.td:936
812 OpSubgroupImageBlockWriteINTEL = 797, // SPIRVInstrInfo.td:938
813 OpSubgroupImageMediaBlockReadINTEL = 798, // SPIRVInstrInfo.td:942
814 OpSubgroupImageMediaBlockWriteINTEL = 799, // SPIRVInstrInfo.td:944
815 OpSubgroupMatrixMultiplyAccumulateINTEL = 800, // SPIRVInstrInfo.td:786
816 OpSubgroupShuffleDownINTEL = 801, // SPIRVInstrInfo.td:926
817 OpSubgroupShuffleINTEL = 802, // SPIRVInstrInfo.td:924
818 OpSubgroupShuffleUpINTEL = 803, // SPIRVInstrInfo.td:928
819 OpSubgroupShuffleXorINTEL = 804, // SPIRVInstrInfo.td:930
820 OpSwitch = 805, // SPIRVInstrInfo.td:674
821 OpTranspose = 806, // SPIRVInstrInfo.td:505
822 OpTypeAccelerationStructureNV = 807, // SPIRVInstrInfo.td:208
823 OpTypeArray = 808, // SPIRVInstrInfo.td:186
824 OpTypeBool = 809, // SPIRVInstrInfo.td:171
825 OpTypeCooperativeMatrixKHR = 810, // SPIRVInstrInfo.td:213
826 OpTypeCooperativeMatrixNV = 811, // SPIRVInstrInfo.td:210
827 OpTypeDeviceEvent = 812, // SPIRVInstrInfo.td:200
828 OpTypeEvent = 813, // SPIRVInstrInfo.td:199
829 OpTypeFloat = 814, // SPIRVInstrInfo.td:174
830 OpTypeForwardPointer = 815, // SPIRVInstrInfo.td:204
831 OpTypeFunction = 816, // SPIRVInstrInfo.td:197
832 OpTypeImage = 817, // SPIRVInstrInfo.td:180
833 OpTypeInt = 818, // SPIRVInstrInfo.td:172
834 OpTypeMatrix = 819, // SPIRVInstrInfo.td:178
835 OpTypeNamedBarrier = 820, // SPIRVInstrInfo.td:207
836 OpTypeOpaque = 821, // SPIRVInstrInfo.td:193
837 OpTypePipe = 822, // SPIRVInstrInfo.td:203
838 OpTypePipeStorage = 823, // SPIRVInstrInfo.td:206
839 OpTypePointer = 824, // SPIRVInstrInfo.td:195
840 OpTypeQueue = 825, // SPIRVInstrInfo.td:202
841 OpTypeReserveId = 826, // SPIRVInstrInfo.td:201
842 OpTypeRuntimeArray = 827, // SPIRVInstrInfo.td:188
843 OpTypeSampledImage = 828, // SPIRVInstrInfo.td:184
844 OpTypeSampler = 829, // SPIRVInstrInfo.td:183
845 OpTypeStruct = 830, // SPIRVInstrInfo.td:190
846 OpTypeStructContinuedINTEL = 831, // SPIRVInstrInfo.td:191
847 OpTypeUntypedPointerKHR = 832, // SPIRVInstrInfo.td:298
848 OpTypeVector = 833, // SPIRVInstrInfo.td:176
849 OpTypeVectorIdEXT = 834, // SPIRVInstrInfo.td:216
850 OpTypeVoid = 835, // SPIRVInstrInfo.td:170
851 OpUConvert = 836, // SPIRVInstrInfo.td:459
852 OpUDivS = 837, // SPIRVInstrInfo.td:48
853 OpUDivV = 838, // SPIRVInstrInfo.td:53
854 OpUDot = 839, // SPIRVInstrInfo.td:556
855 OpUDotAccSat = 840, // SPIRVInstrInfo.td:562
856 OpUGreaterThan = 841, // SPIRVInstrInfo.td:621
857 OpUGreaterThanEqual = 842, // SPIRVInstrInfo.td:623
858 OpULessThan = 843, // SPIRVInstrInfo.td:625
859 OpULessThanEqual = 844, // SPIRVInstrInfo.td:627
860 OpUModS = 845, // SPIRVInstrInfo.td:48
861 OpUModV = 846, // SPIRVInstrInfo.td:53
862 OpUMulExtended = 847, // SPIRVInstrInfo.td:551
863 OpUndef = 848, // SPIRVInstrInfo.td:98
864 OpUnordered = 849, // SPIRVInstrInfo.td:608
865 OpUnreachable = 850, // SPIRVInstrInfo.td:680
866 OpUntypedAccessChainKHR = 851, // SPIRVInstrInfo.td:303
867 OpUntypedGroupAsyncCopyKHR = 852, // SPIRVInstrInfo.td:318
868 OpUntypedInBoundsAccessChainKHR = 853, // SPIRVInstrInfo.td:306
869 OpUntypedInBoundsPtrAccessChainKHR = 854, // SPIRVInstrInfo.td:312
870 OpUntypedPrefetchKHR = 855, // SPIRVInstrInfo.td:315
871 OpUntypedPtrAccessChainKHR = 856, // SPIRVInstrInfo.td:309
872 OpUntypedVariableKHR = 857, // SPIRVInstrInfo.td:300
873 OpUntypedVariableLengthArrayINTEL = 858, // SPIRVInstrInfo.td:327
874 OpVariable = 859, // SPIRVInstrInfo.td:261
875 OpVariableLengthArrayINTEL = 860, // SPIRVInstrInfo.td:325
876 OpVectorExtractDynamic = 861, // SPIRVInstrInfo.td:490
877 OpVectorInsertDynamic = 862, // SPIRVInstrInfo.td:492
878 OpVectorShuffle = 863, // SPIRVInstrInfo.td:494
879 OpVectorTimesMatrix = 864, // SPIRVInstrInfo.td:542
880 OpVectorTimesScalar = 865, // SPIRVInstrInfo.td:540
881 OpWritePipe = 866, // SPIRVInstrInfo.td:822
882 OpWritePipeBlockingALTERA = 867, // SPIRVInstrInfo.td:1148
883 INSTRUCTION_LIST_END = 868
884 };
885
886} // namespace llvm::SPIRV
887
888#endif // GET_INSTRINFO_ENUM
889
890#ifdef GET_INSTRINFO_SCHED_ENUM
891#undef GET_INSTRINFO_SCHED_ENUM
892
893namespace llvm::SPIRV::Sched {
894
895 enum {
896 NoInstrModel = 0,
897 SCHED_LIST_END = 1
898 };
899
900} // namespace llvm::SPIRV::Sched
901
902#endif // GET_INSTRINFO_SCHED_ENUM
903
904#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
905
906namespace llvm {
907
908struct SPIRVInstrTable {
909 MCInstrDesc Insts[868];
910 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
911 MCPhysReg ImplicitOps[1];
912 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
913 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
914 MCOperandInfo OperandInfo[499];
915};
916} // namespace llvm
917
918#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
919
920#ifdef GET_INSTRINFO_MC_DESC
921#undef GET_INSTRINFO_MC_DESC
922
923namespace llvm {
924
925static_assert((sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
926static constexpr unsigned SPIRVOpInfoBase = (sizeof SPIRVInstrTable::ImplicitOps + sizeof SPIRVInstrTable::Padding) / sizeof(MCOperandInfo);
927
928extern const SPIRVInstrTable SPIRVDescs = {
929 {
930 { 867, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipeBlockingALTERA
931 { 866, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpWritePipe
932 { 865, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesScalar
933 { 864, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorTimesMatrix
934 { 863, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorShuffle
935 { 862, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorInsertDynamic
936 { 861, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVectorExtractDynamic
937 { 860, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariableLengthArrayINTEL
938 { 859, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 496, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpVariable
939 { 858, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedVariableLengthArrayINTEL
940 { 857, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 313, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedVariableKHR
941 { 856, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 491, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedPtrAccessChainKHR
942 { 855, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedPrefetchKHR
943 { 854, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 491, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedInBoundsPtrAccessChainKHR
944 { 853, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedInBoundsAccessChainKHR
945 { 852, 9, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 482, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedGroupAsyncCopyKHR
946 { 851, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 478, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUntypedAccessChainKHR
947 { 850, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnreachable
948 { 849, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUnordered
949 { 848, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUndef
950 { 847, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUMulExtended
951 { 846, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModV
952 { 845, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUModS
953 { 844, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThanEqual
954 { 843, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpULessThan
955 { 842, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThanEqual
956 { 841, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUGreaterThan
957 { 840, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDotAccSat
958 { 839, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDot
959 { 838, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivV
960 { 837, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUDivS
961 { 836, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpUConvert
962 { 835, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVoid
963 { 834, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 443, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVectorIdEXT
964 { 833, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 472, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeVector
965 { 832, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeUntypedPointerKHR
966 { 831, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStructContinuedINTEL
967 { 830, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeStruct
968 { 829, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampler
969 { 828, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeSampledImage
970 { 827, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeRuntimeArray
971 { 826, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeReserveId
972 { 825, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeQueue
973 { 824, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 475, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePointer
974 { 823, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipeStorage
975 { 822, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypePipe
976 { 821, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeOpaque
977 { 820, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeNamedBarrier
978 { 819, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 472, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeMatrix
979 { 818, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 469, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeInt
980 { 817, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 461, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeImage
981 { 816, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 459, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFunction
982 { 815, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 457, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeForwardPointer
983 { 814, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeFloat
984 { 813, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeEvent
985 { 812, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeDeviceEvent
986 { 811, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 452, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixNV
987 { 810, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeCooperativeMatrixKHR
988 { 809, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeBool
989 { 808, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 443, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeArray
990 { 807, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 442, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTypeAccelerationStructureNV
991 { 806, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpTranspose
992 { 805, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSwitch
993 { 804, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleXorINTEL
994 { 803, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleUpINTEL
995 { 802, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleINTEL
996 { 801, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupShuffleDownINTEL
997 { 800, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupMatrixMultiplyAccumulateINTEL
998 { 799, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockWriteINTEL
999 { 798, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageMediaBlockReadINTEL
1000 { 797, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockWriteINTEL
1001 { 796, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupImageBlockReadINTEL
1002 { 795, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockWriteINTEL
1003 { 794, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroupBlockReadINTEL
1004 { 793, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockStoreINTEL
1005 { 792, 9, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 433, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockPrefetchINTEL
1006 { 791, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransposeINTEL
1007 { 790, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadTransformINTEL
1008 { 789, 10, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSubgroup2DBlockLoadINTEL
1009 { 788, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpString
1010 { 787, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubV
1011 { 786, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFSubS
1012 { 785, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemV
1013 { 784, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFRemS
1014 { 783, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulV
1015 { 782, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFMulS
1016 { 781, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivV
1017 { 780, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFDivS
1018 { 779, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddV
1019 { 778, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStrictFAddS
1020 { 777, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpStore
1021 { 776, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantTrue
1022 { 775, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 419, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantOp
1023 { 774, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantFalse
1024 { 773, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantCompositeContinuedINTEL
1025 { 772, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstantComposite
1026 { 771, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 416, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSpecConstant
1027 { 770, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceExtension
1028 { 769, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSourceContinued
1029 { 768, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSource
1030 { 767, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSizeOf
1031 { 766, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSignBitSet
1032 { 765, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalV
1033 { 764, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightLogicalS
1034 { 763, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticV
1035 { 762, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftRightArithmeticS
1036 { 761, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalV
1037 { 760, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpShiftLeftLogicalS
1038 { 759, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSetUserEventStatus
1039 { 758, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectionMerge
1040 { 757, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 411, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPVCond
1041 { 756, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 406, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVPSCond
1042 { 755, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 401, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVIVCond
1043 { 754, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 396, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVISCond
1044 { 753, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 391, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFVCond
1045 { 752, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 386, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectVFSCond
1046 { 751, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 381, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPVCond
1047 { 750, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 376, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSPSCond
1048 { 749, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 371, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSIVCond
1049 { 748, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 366, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSISCond
1050 { 747, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 361, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFVCond
1051 { 746, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 356, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSelectSFSCond
1052 { 745, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSaveMemoryINTEL
1053 { 744, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertUToS
1054 { 743, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSatConvertSToU
1055 { 742, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSampledImage
1056 { 741, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDotAccSat
1057 { 740, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSUDot
1058 { 739, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemV
1059 { 738, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSRemS
1060 { 737, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSNegate
1061 { 736, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMulExtended
1062 { 735, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSMod
1063 { 734, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThanEqual
1064 { 733, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSLessThan
1065 { 732, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThanEqual
1066 { 731, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSGreaterThan
1067 { 730, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDotAccSat
1068 { 729, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDot
1069 { 728, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivV
1070 { 727, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSDivS
1071 { 726, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpSConvert
1072 { 725, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRoundFToTF32INTEL
1073 { 724, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturnValue
1074 { 723, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReturn
1075 { 722, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRetainEvent
1076 { 721, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpRestoreMemoryINTEL
1077 { 720, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedWritePipe
1078 { 719, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReservedReadPipe
1079 { 718, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveWritePipePackets
1080 { 717, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReserveReadPipePackets
1081 { 716, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReleaseEvent
1082 { 715, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipeBlockingALTERA
1083 { 714, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadPipe
1084 { 713, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpReadClockKHR
1085 { 712, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpQuantizeToF16
1086 { 711, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrNotEqual
1087 { 710, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrEqual
1088 { 709, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrDiff
1089 { 708, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToGeneric
1090 { 707, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrCastToCrossWorkgroupINTEL
1091 { 706, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPtrAccessChain
1092 { 705, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedStoreINTEL
1093 { 704, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPredicatedLoadINTEL
1094 { 703, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPoisonKHR
1095 { 702, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpPhi
1096 { 701, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOuterProduct
1097 { 700, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpOrdered
1098 { 699, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNot
1099 { 698, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNop
1100 { 697, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNoLine
1101 { 696, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpNamedBarrierInitialize
1102 { 695, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpName
1103 { 694, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpModuleProcessed
1104 { 693, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryNamedBarrier
1105 { 692, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryModel
1106 { 691, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemoryBarrier
1107 { 690, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberName
1108 { 689, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 352, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorateString
1109 { 688, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 349, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMemberDecorate
1110 { 687, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesVector
1111 { 686, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesScalar
1112 { 685, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMatrixTimesMatrix
1113 { 684, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedScatterINTEL
1114 { 683, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpMaskedGatherINTEL
1115 { 682, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopMerge
1116 { 681, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoopControlINTEL
1117 { 680, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalOr
1118 { 679, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNotEqual
1119 { 678, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalNot
1120 { 677, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalEqual
1121 { 676, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLogicalAnd
1122 { 675, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLoad
1123 { 674, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 346, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLine
1124 { 673, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 344, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStop
1125 { 672, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 344, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLifetimeStart
1126 { 671, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLessOrGreater
1127 { 670, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpLabel
1128 { 669, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpKill
1129 { 668, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidReserveId
1130 { 667, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsValidEvent
1131 { 666, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNormal
1132 { 665, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsNan
1133 { 664, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsInf
1134 { 663, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIsFinite
1135 { 662, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsPtrAccessChain
1136 { 661, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpInBoundsAccessChain
1137 { 660, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageWrite
1138 { 659, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageTexelPointer
1139 { 658, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseTexelsResident
1140 { 657, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjImplicitLod
1141 { 656, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjExplicitLod
1142 { 655, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefImplicitLod
1143 { 654, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleProjDrefExplicitLod
1144 { 653, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleImplicitLod
1145 { 652, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 338, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleExplicitLod
1146 { 651, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefImplicitLod
1147 { 650, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseSampleDrefExplicitLod
1148 { 649, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseRead
1149 { 648, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseGather
1150 { 647, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseFetch
1151 { 646, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSparseDrefGather
1152 { 645, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjImplicitLod
1153 { 644, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjExplicitLod
1154 { 643, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefImplicitLod
1155 { 642, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleProjDrefExplicitLod
1156 { 641, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleImplicitLod
1157 { 640, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleFootprintNV
1158 { 639, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 338, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleExplicitLod
1159 { 638, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefImplicitLod
1160 { 637, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 331, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageSampleDrefExplicitLod
1161 { 636, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageRead
1162 { 635, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySizeLod
1163 { 634, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySize
1164 { 633, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQuerySamples
1165 { 632, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryOrder
1166 { 631, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLod
1167 { 630, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryLevels
1168 { 629, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageQueryFormat
1169 { 628, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageGather
1170 { 627, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageFetch
1171 { 626, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImageDrefGather
1172 { 625, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpImage
1173 { 624, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubV
1174 { 623, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubS
1175 { 622, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowV
1176 { 621, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpISubBorrowS
1177 { 620, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpINotEqual
1178 { 619, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulV
1179 { 618, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIMulS
1180 { 617, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIEqual
1181 { 616, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddV
1182 { 615, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddS
1183 { 614, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryV
1184 { 613, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpIAddCarryS
1185 { 612, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupWaitEvents
1186 { 611, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMin
1187 { 610, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupUMax
1188 { 609, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMin
1189 { 608, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupSMax
1190 { 607, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveWritePipePackets
1191 { 606, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupReserveReadPipePackets
1192 { 605, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMin
1193 { 604, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformUMax
1194 { 603, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleXor
1195 { 602, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleUp
1196 { 601, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffleDown
1197 { 600, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformShuffle
1198 { 599, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMin
1199 { 598, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformSMax
1200 { 597, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformRotateKHR
1201 { 596, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformQuadSwap
1202 { 595, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalXor
1203 { 594, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalOr
1204 { 593, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformLogicalAnd
1205 { 592, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformInverseBallot
1206 { 591, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIMul
1207 { 590, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformIAdd
1208 { 589, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMul
1209 { 588, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMin
1210 { 587, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFMax
1211 { 586, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformFAdd
1212 { 585, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformElect
1213 { 584, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcastFirst
1214 { 583, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBroadcast
1215 { 582, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseXor
1216 { 581, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseOr
1217 { 580, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBitwiseAnd
1218 { 579, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindMSB
1219 { 578, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotFindLSB
1220 { 577, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitExtract
1221 { 576, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallotBitCount
1222 { 575, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformBallot
1223 { 574, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAny
1224 { 573, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAllEqual
1225 { 572, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupNonUniformAll
1226 { 571, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalXorKHR
1227 { 570, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalOrKHR
1228 { 569, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupLogicalAndKHR
1229 { 568, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIMulKHR
1230 { 567, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupIAdd
1231 { 566, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMulKHR
1232 { 565, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMin
1233 { 564, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFMax
1234 { 563, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupFAdd
1235 { 562, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitWritePipe
1236 { 561, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupCommitReadPipe
1237 { 560, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBroadcast
1238 { 559, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseXorKHR
1239 { 558, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseOrKHR
1240 { 557, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 321, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupBitwiseAndKHR
1241 { 556, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAsyncCopy
1242 { 555, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAny
1243 { 554, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGroupAll
1244 { 553, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetNumPipePackets
1245 { 552, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetMaxPipePackets
1246 { 551, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetKernelWorkGroupSize
1247 { 550, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetKernelPreferredWorkGroupSizeMultiple
1248 { 549, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetKernelNDrangeSubGroupCount
1249 { 548, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetKernelNDrangeMaxSubGroupSize
1250 { 547, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGetDefaultQueue
1251 { 546, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericPtrMemSemantics
1252 { 545, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 317, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtrExplicit
1253 { 544, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpGenericCastToPtr
1254 { 543, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthFine
1255 { 542, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidthCoarse
1256 { 541, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFwidth
1257 { 540, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionPointerCallINTEL
1258 { 539, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionParameter
1259 { 538, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionEnd
1260 { 537, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunctionCall
1261 { 536, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 313, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFunction
1262 { 535, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFreezeKHR
1263 { 534, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFmaKHR
1264 { 533, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSqrtALTERA
1265 { 532, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinPiALTERA
1266 { 531, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosPiALTERA
1267 { 530, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinCosALTERA
1268 { 529, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedSinALTERA
1269 { 528, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRsqrtALTERA
1270 { 527, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedRecipALTERA
1271 { 526, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedLogALTERA
1272 { 525, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedExpALTERA
1273 { 524, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosPiALTERA
1274 { 523, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFixedCosALTERA
1275 { 522, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordNotEqual
1276 { 521, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThanEqual
1277 { 520, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordLessThan
1278 { 519, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThanEqual
1279 { 518, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordGreaterThan
1280 { 517, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFUnordEqual
1281 { 516, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubV
1282 { 515, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFSubS
1283 { 514, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemV
1284 { 513, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFRemS
1285 { 512, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdNotEqual
1286 { 511, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThanEqual
1287 { 510, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdLessThan
1288 { 509, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThanEqual
1289 { 508, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdGreaterThan
1290 { 507, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFOrdEqual
1291 { 506, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 310, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegateV
1292 { 505, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFNegate
1293 { 504, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulV
1294 { 503, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMulS
1295 { 502, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFMod
1296 { 501, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivV
1297 { 500, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFDivS
1298 { 499, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFConvert
1299 { 498, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 306, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddV
1300 { 497, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 302, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpFAddS
1301 { 496, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtension
1302 { 495, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInstImport
1303 { 494, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 298, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExtInst
1304 { 493, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExpectKHR
1305 { 492, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionModeId
1306 { 491, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpExecutionMode
1307 { 490, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 295, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEntryPoint
1308 { 489, 12, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 283, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEnqueueKernel
1309 { 488, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndStreamPrimitive
1310 { 487, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEndPrimitive
1311 { 486, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitVertex
1312 { 485, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpEmitStreamVertex
1313 { 484, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDot
1314 { 483, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDemoteToHelperInvocation
1315 { 482, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 280, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateString
1316 { 481, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorateId
1317 { 480, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 278, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDecorate
1318 { 479, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyFine
1319 { 478, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdyCoarse
1320 { 477, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdy
1321 { 476, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxFine
1322 { 475, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdxCoarse
1323 { 474, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpDPdx
1324 { 473, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCrossWorkgroupCastToPtrINTEL
1325 { 472, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCreateUserEvent
1326 { 471, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyObject
1327 { 470, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemorySized
1328 { 469, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyMemory
1329 { 468, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCopyLogical
1330 { 467, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreKHR
1331 { 466, 7, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 271, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixStoreCheckedINTEL
1332 { 465, 5, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 266, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixPrefetchINTEL
1333 { 464, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixMulAddKHR
1334 { 463, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadKHR
1335 { 462, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLoadCheckedINTEL
1336 { 461, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 263, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixLengthKHR
1337 { 460, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixGetElementCoordINTEL
1338 { 459, 7, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 256, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCooperativeMatrixConstructCheckedINTEL
1339 { 458, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToPtr
1340 { 457, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertUToF
1341 { 456, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertSToF
1342 { 455, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertPtrToU
1343 { 454, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSamplerINTEL
1344 { 453, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToSampledImageINTEL
1345 { 452, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertHandleToImageINTEL
1346 { 451, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToU
1347 { 450, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToS
1348 { 449, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertFToBF16INTEL
1349 { 448, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConvertBF16ToFINTEL
1350 { 447, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierWaitINTEL
1351 { 446, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrierArriveINTEL
1352 { 445, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpControlBarrier
1353 { 444, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantTrue
1354 { 443, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantSampler
1355 { 442, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantNull
1356 { 441, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 248, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantI
1357 { 440, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFunctionPointerINTEL
1358 { 439, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantFalse
1359 { 438, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 243, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantF
1360 { 437, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantCompositeContinuedINTEL
1361 { 436, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpConstantComposite
1362 { 435, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 239, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeInsert
1363 { 434, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeExtract
1364 { 433, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstructContinuedINTEL
1365 { 432, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 237, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCompositeConstruct
1366 { 431, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitWritePipe
1367 { 430, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCommitReadPipe
1368 { 429, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCaptureEventProfilingInfo
1369 { 428, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpCapability
1370 { 427, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBuildNDRange
1371 { 426, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 234, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranchConditional
1372 { 425, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBranch
1373 { 424, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorV
1374 { 423, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseXorS
1375 { 422, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrV
1376 { 421, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseOrS
1377 { 420, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseFunctionINTEL
1378 { 419, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 230, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndV
1379 { 418, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 226, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitwiseAndS
1380 { 417, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitcast
1381 { 416, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitReverse
1382 { 415, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldUExtract
1383 { 414, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldSExtract
1384 { 413, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitFieldInsert
1385 { 412, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpBitCount
1386 { 411, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicXor
1387 { 410, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMin
1388 { 409, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicUMax
1389 { 408, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 222, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicStore
1390 { 407, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMin
1391 { 406, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicSMax
1392 { 405, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicOr
1393 { 404, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicLoad
1394 { 403, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicISub
1395 { 402, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIIncrement
1396 { 401, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIDecrement
1397 { 400, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicIAdd
1398 { 399, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 217, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagTestAndSet
1399 { 398, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 214, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFlagClear
1400 { 397, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMinEXT
1401 { 396, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFMaxEXT
1402 { 395, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicFAddEXT
1403 { 394, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicExchange
1404 { 393, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchangeWeak
1405 { 392, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 206, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicCompareExchange
1406 { 391, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAtomicAnd
1407 { 390, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAssumeTrueKHR
1408 { 389, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 198, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmTargetINTEL
1409 { 388, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 192, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmINTEL
1410 { 387, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAsmCallINTEL
1411 { 386, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 188, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArrayLength
1412 { 385, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArithmeticFenceEXT
1413 { 384, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSubALTERA
1414 { 383, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSqrtALTERA
1415 { 382, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinPiALTERA
1416 { 381, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosPiALTERA
1417 { 380, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinCosALTERA
1418 { 379, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatSinALTERA
1419 { 378, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRecipALTERA
1420 { 377, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatRSqrtALTERA
1421 { 376, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowRALTERA
1422 { 375, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowNALTERA
1423 { 374, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatPowALTERA
1424 { 373, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatMulALTERA
1425 { 372, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLogALTERA
1426 { 371, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog2ALTERA
1427 { 370, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog1pALTERA
1428 { 369, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLog10ALTERA
1429 { 368, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLTALTERA
1430 { 367, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatLEALTERA
1431 { 366, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatHypotALTERA
1432 { 365, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGTALTERA
1433 { 364, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatGEALTERA
1434 { 363, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpm1ALTERA
1435 { 362, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExpALTERA
1436 { 361, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp2ALTERA
1437 { 360, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatExp10ALTERA
1438 { 359, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatEQALTERA
1439 { 358, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatDivALTERA
1440 { 357, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosPiALTERA
1441 { 356, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCosALTERA
1442 { 355, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCbrtALTERA
1443 { 354, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastToIntALTERA
1444 { 353, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastFromIntALTERA
1445 { 352, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatCastALTERA
1446 { 351, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatAddALTERA
1447 { 350, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanPiALTERA
1448 { 349, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATanALTERA
1449 { 348, 10, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatATan2ALTERA
1450 { 347, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinPiALTERA
1451 { 346, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatASinALTERA
1452 { 345, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosPiALTERA
1453 { 344, 8, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 164, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpArbitraryFloatACosALTERA
1454 { 343, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAny
1455 { 342, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAll
1456 { 341, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeListDeclINTEL
1457 { 340, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 162, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasScopeDeclINTEL
1458 { 339, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 161, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAliasDomainDeclINTEL
1459 { 338, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 158, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAccessChain
1460 { 337, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 156, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OpAbortKHR
1461 { 336, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNKNOWN_type
1462 { 335, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ASSIGN_TYPE
1463 { 334, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1464 { 333, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1465 { 332, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1466 { 331, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1467 { 330, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1468 { 329, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1469 { 328, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1470 { 327, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1471 { 326, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1472 { 325, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1473 { 324, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1474 { 323, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1475 { 322, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1476 { 321, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1477 { 320, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1478 { 319, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1479 { 318, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1480 { 317, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1481 { 316, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1482 { 315, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1483 { 314, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1484 { 313, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1485 { 312, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1486 { 311, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1487 { 310, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
1488 { 309, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1489 { 308, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1490 { 307, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1491 { 306, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1492 { 305, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1493 { 304, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1494 { 303, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1495 { 302, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
1496 { 301, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
1497 { 300, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1498 { 299, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1499 { 298, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1500 { 297, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1501 { 296, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1502 { 295, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1503 { 294, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1504 { 293, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1505 { 292, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1506 { 291, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1507 { 290, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1508 { 289, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1509 { 288, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1510 { 287, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1511 { 286, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1512 { 285, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1513 { 284, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1514 { 283, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1515 { 282, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1516 { 281, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1517 { 280, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1518 { 279, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1519 { 278, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1520 { 277, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1521 { 276, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1522 { 275, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1523 { 274, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1524 { 273, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1525 { 272, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1526 { 271, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1527 { 270, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULR
1528 { 269, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
1529 { 268, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
1530 { 267, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1531 { 266, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1532 { 265, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1533 { 264, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1534 { 263, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
1535 { 262, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1536 { 261, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
1537 { 260, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1538 { 259, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1539 { 258, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1540 { 257, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1541 { 256, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1542 { 255, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1543 { 254, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1544 { 253, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1545 { 252, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1546 { 251, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1547 { 250, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1548 { 249, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1549 { 248, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1550 { 247, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1551 { 246, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1552 { 245, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1553 { 244, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1554 { 243, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1555 { 242, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1556 { 241, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1557 { 240, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1558 { 239, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1559 { 238, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1560 { 237, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1561 { 236, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1562 { 235, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1563 { 234, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1564 { 233, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1565 { 232, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1566 { 231, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1567 { 230, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1568 { 229, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1569 { 228, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1570 { 227, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1571 { 226, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1572 { 225, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1573 { 224, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1574 { 223, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1575 { 222, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1576 { 221, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1577 { 220, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1578 { 219, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1579 { 218, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1580 { 217, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1581 { 216, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1582 { 215, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1583 { 214, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1584 { 213, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1585 { 212, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1586 { 211, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1587 { 210, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1588 { 209, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1589 { 208, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1590 { 207, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1591 { 206, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1592 { 205, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1593 { 204, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1594 { 203, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1595 { 202, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1596 { 201, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1597 { 200, 3, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1598 { 199, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1599 { 198, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1600 { 197, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1601 { 196, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1602 { 195, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1603 { 194, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1604 { 193, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1605 { 192, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1606 { 191, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1607 { 190, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1608 { 189, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1609 { 188, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1610 { 187, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1611 { 186, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1612 { 185, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1613 { 184, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1614 { 183, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1615 { 182, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1616 { 181, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1617 { 180, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1618 { 179, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1619 { 178, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1620 { 177, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1621 { 176, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1622 { 175, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1623 { 174, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1624 { 173, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1625 { 172, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1626 { 171, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1627 { 170, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1628 { 169, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1629 { 168, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1630 { 167, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1631 { 166, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1632 { 165, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1633 { 164, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1634 { 163, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1635 { 162, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1636 { 161, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1637 { 160, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1638 { 159, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1639 { 158, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1640 { 157, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1641 { 156, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1642 { 155, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1643 { 154, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1644 { 153, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1645 { 152, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1646 { 151, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1647 { 150, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1648 { 149, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1649 { 148, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1650 { 147, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1651 { 146, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1652 { 145, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1653 { 144, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1654 { 143, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1655 { 142, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1656 { 141, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1657 { 140, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1658 { 139, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1659 { 138, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1660 { 137, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1661 { 136, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1662 { 135, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1663 { 134, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1664 { 133, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1665 { 132, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1666 { 131, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1667 { 130, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1668 { 129, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1669 { 128, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1670 { 127, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1671 { 126, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1672 { 125, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1673 { 124, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1674 { 123, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1675 { 122, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1676 { 121, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1677 { 120, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1678 { 119, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1679 { 118, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1680 { 117, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1681 { 116, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1682 { 115, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1683 { 114, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1684 { 113, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1685 { 112, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1686 { 111, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1687 { 110, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1688 { 109, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1689 { 108, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1690 { 107, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1691 { 106, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1692 { 105, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1693 { 104, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1694 { 103, 5, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1695 { 102, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1696 { 101, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1697 { 100, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1698 { 99, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1699 { 98, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1700 { 97, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1701 { 96, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1702 { 95, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1703 { 94, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1704 { 93, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1705 { 92, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1706 { 91, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1707 { 90, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1708 { 89, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1709 { 88, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1710 { 87, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1711 { 86, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1712 { 85, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1713 { 84, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1714 { 83, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1715 { 82, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1716 { 81, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1717 { 80, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1718 { 79, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1719 { 78, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1720 { 77, 5, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1721 { 76, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1722 { 75, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1723 { 74, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1724 { 73, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1725 { 72, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1726 { 71, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1727 { 70, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1728 { 69, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1729 { 68, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1730 { 67, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1731 { 66, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1732 { 65, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1733 { 64, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1734 { 63, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1735 { 62, 4, 2, 0, 0, 0, 0, SPIRVOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1736 { 61, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1737 { 60, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1738 { 59, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1739 { 58, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1740 { 57, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1741 { 56, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1742 { 55, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1743 { 54, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1744 { 53, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1745 { 52, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1746 { 51, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1747 { 50, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1748 { 49, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1749 { 48, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1750 { 47, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1751 { 46, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1752 { 45, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1753 { 44, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1754 { 43, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1755 { 42, 3, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21963
1756 { 41, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21962
1757 { 40, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1758 { 39, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1759 { 38, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1760 { 37, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1761 { 36, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1762 { 35, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1763 { 34, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1764 { 33, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1765 { 32, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_21961
1766 { 31, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1767 { 30, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14418
1768 { 29, 6, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1769 { 28, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1770 { 27, 2, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1771 { 26, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1772 { 25, 4, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1773 { 24, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1774 { 23, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1775 { 22, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1776 { 21, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1777 { 20, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1778 { 19, 2, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1779 { 18, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1780 { 17, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1781 { 16, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1782 { 15, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1783 { 14, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1784 { 13, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1785 { 12, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1786 { 11, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1787 { 10, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1788 { 9, 4, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1789 { 8, 3, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1790 { 7, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1791 { 6, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1792 { 5, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1793 { 4, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1794 { 3, 1, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1795 { 2, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1796 { 1, 0, 0, 0, 0, 0, 0, SPIRVOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1797 { 0, 1, 1, 0, 0, 0, 0, SPIRVOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1798 }, {
1799 /* 0 */
1800 }, {
1801 0
1802 }, {
1803 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1804 /* 1 */
1805 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1806 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1807 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1808 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1809 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1810 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1811 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1812 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1813 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1814 /* 28 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1815 /* 29 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1816 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1817 /* 34 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1818 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1819 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1820 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1821 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1822 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1823 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1824 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1825 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1826 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1827 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1828 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1829 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1830 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1831 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1832 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1833 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1834 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1835 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1836 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1837 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1838 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1839 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1840 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1841 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1842 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1843 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1844 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1845 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1846 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1847 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1848 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1849 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1850 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1851 /* 151 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1852 /* 154 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1853 /* 156 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1854 /* 158 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1855 /* 161 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1856 /* 162 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1857 /* 164 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1858 /* 172 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1859 /* 182 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1860 /* 188 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1861 /* 192 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1862 /* 198 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1863 /* 200 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1864 /* 206 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1865 /* 214 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1866 /* 217 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1867 /* 222 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1868 /* 226 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1869 /* 230 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1870 /* 234 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1871 /* 237 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1872 /* 239 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1873 /* 243 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1874 /* 246 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1875 /* 248 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1876 /* 251 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1877 /* 256 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1878 /* 263 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1879 /* 266 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1880 /* 271 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1881 /* 278 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1882 /* 280 */ { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1883 /* 283 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1884 /* 295 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1885 /* 298 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1886 /* 302 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1887 /* 306 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1888 /* 310 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1889 /* 313 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1890 /* 317 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1891 /* 321 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1892 /* 326 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1893 /* 331 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1894 /* 338 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1895 /* 344 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1896 /* 346 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1897 /* 349 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1898 /* 352 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1899 /* 356 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1900 /* 361 */ { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::fIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1901 /* 366 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1902 /* 371 */ { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1903 /* 376 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1904 /* 381 */ { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::pIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1905 /* 386 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1906 /* 391 */ { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vfIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1907 /* 396 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1908 /* 401 */ { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1909 /* 406 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::iIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1910 /* 411 */ { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::viIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::vpIDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1911 /* 416 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1912 /* 419 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::ANYRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1913 /* 423 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1914 /* 433 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1915 /* 442 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1916 /* 443 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1917 /* 446 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1918 /* 452 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1919 /* 457 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1920 /* 459 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1921 /* 461 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1922 /* 469 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1923 /* 472 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1924 /* 475 */ { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1925 /* 478 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1926 /* 482 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1927 /* 491 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1928 /* 496 */ { SPIRV::IDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SPIRV::TYPERegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1929 }
1930};
1931
1932
1933#ifdef __GNUC__
1934#pragma GCC diagnostic push
1935#pragma GCC diagnostic ignored "-Woverlength-strings"
1936#endif
1937extern const char SPIRVInstrNameData[] = {
1938 /* 0 */ "G_FLOG10\000"
1939 /* 9 */ "G_FEXP10\000"
1940 /* 18 */ "G_FLOG2\000"
1941 /* 26 */ "G_FATAN2\000"
1942 /* 35 */ "G_FEXP2\000"
1943 /* 43 */ "OpQuantizeToF16\000"
1944 /* 59 */ "G_FMA\000"
1945 /* 65 */ "G_STRICT_FMA\000"
1946 /* 78 */ "OpArbitraryFloatLog10ALTERA\000"
1947 /* 106 */ "OpArbitraryFloatExp10ALTERA\000"
1948 /* 134 */ "OpArbitraryFloatExpm1ALTERA\000"
1949 /* 162 */ "OpArbitraryFloatLog2ALTERA\000"
1950 /* 189 */ "OpArbitraryFloatATan2ALTERA\000"
1951 /* 217 */ "OpArbitraryFloatExp2ALTERA\000"
1952 /* 244 */ "OpArbitraryFloatGEALTERA\000"
1953 /* 269 */ "OpArbitraryFloatLEALTERA\000"
1954 /* 294 */ "OpArbitraryFloatPowNALTERA\000"
1955 /* 321 */ "OpArbitraryFloatEQALTERA\000"
1956 /* 346 */ "OpArbitraryFloatPowRALTERA\000"
1957 /* 373 */ "OpArbitraryFloatGTALTERA\000"
1958 /* 398 */ "OpArbitraryFloatLTALTERA\000"
1959 /* 423 */ "OpArbitraryFloatSubALTERA\000"
1960 /* 449 */ "OpArbitraryFloatAddALTERA\000"
1961 /* 475 */ "OpReadPipeBlockingALTERA\000"
1962 /* 500 */ "OpWritePipeBlockingALTERA\000"
1963 /* 526 */ "OpFixedLogALTERA\000"
1964 /* 543 */ "OpArbitraryFloatLogALTERA\000"
1965 /* 569 */ "OpArbitraryFloatATanPiALTERA\000"
1966 /* 598 */ "OpArbitraryFloatASinPiALTERA\000"
1967 /* 627 */ "OpFixedSinPiALTERA\000"
1968 /* 646 */ "OpArbitraryFloatSinPiALTERA\000"
1969 /* 674 */ "OpArbitraryFloatACosPiALTERA\000"
1970 /* 703 */ "OpFixedCosPiALTERA\000"
1971 /* 722 */ "OpFixedSinCosPiALTERA\000"
1972 /* 744 */ "OpArbitraryFloatSinCosPiALTERA\000"
1973 /* 775 */ "OpArbitraryFloatCosPiALTERA\000"
1974 /* 803 */ "OpArbitraryFloatMulALTERA\000"
1975 /* 829 */ "OpArbitraryFloatATanALTERA\000"
1976 /* 856 */ "OpArbitraryFloatASinALTERA\000"
1977 /* 883 */ "OpFixedSinALTERA\000"
1978 /* 900 */ "OpArbitraryFloatSinALTERA\000"
1979 /* 926 */ "OpArbitraryFloatLog1pALTERA\000"
1980 /* 954 */ "OpFixedRecipALTERA\000"
1981 /* 973 */ "OpArbitraryFloatRecipALTERA\000"
1982 /* 1001 */ "OpFixedExpALTERA\000"
1983 /* 1018 */ "OpArbitraryFloatExpALTERA\000"
1984 /* 1044 */ "OpArbitraryFloatACosALTERA\000"
1985 /* 1071 */ "OpFixedCosALTERA\000"
1986 /* 1088 */ "OpFixedSinCosALTERA\000"
1987 /* 1108 */ "OpArbitraryFloatSinCosALTERA\000"
1988 /* 1137 */ "OpArbitraryFloatCosALTERA\000"
1989 /* 1163 */ "OpArbitraryFloatCastFromIntALTERA\000"
1990 /* 1197 */ "OpArbitraryFloatCastToIntALTERA\000"
1991 /* 1229 */ "OpArbitraryFloatHypotALTERA\000"
1992 /* 1257 */ "OpArbitraryFloatCbrtALTERA\000"
1993 /* 1284 */ "OpArbitraryFloatRSqrtALTERA\000"
1994 /* 1312 */ "OpFixedSqrtALTERA\000"
1995 /* 1330 */ "OpArbitraryFloatSqrtALTERA\000"
1996 /* 1357 */ "OpFixedRsqrtALTERA\000"
1997 /* 1376 */ "OpArbitraryFloatCastALTERA\000"
1998 /* 1403 */ "OpArbitraryFloatDivALTERA\000"
1999 /* 1429 */ "OpArbitraryFloatPowALTERA\000"
2000 /* 1455 */ "OpGroupNonUniformBallotFindLSB\000"
2001 /* 1486 */ "OpGroupNonUniformBallotFindMSB\000"
2002 /* 1517 */ "G_FSUB\000"
2003 /* 1524 */ "G_STRICT_FSUB\000"
2004 /* 1538 */ "G_ATOMICRMW_FSUB\000"
2005 /* 1555 */ "G_SUB\000"
2006 /* 1561 */ "G_ATOMICRMW_SUB\000"
2007 /* 1577 */ "G_INTRINSIC\000"
2008 /* 1589 */ "G_FPTRUNC\000"
2009 /* 1599 */ "G_INTRINSIC_TRUNC\000"
2010 /* 1617 */ "G_TRUNC\000"
2011 /* 1625 */ "G_BUILD_VECTOR_TRUNC\000"
2012 /* 1646 */ "G_DYN_STACKALLOC\000"
2013 /* 1663 */ "G_FMAD\000"
2014 /* 1670 */ "G_FPEXTLOAD\000"
2015 /* 1682 */ "G_INDEXED_SEXTLOAD\000"
2016 /* 1701 */ "G_SEXTLOAD\000"
2017 /* 1712 */ "G_INDEXED_ZEXTLOAD\000"
2018 /* 1731 */ "G_ZEXTLOAD\000"
2019 /* 1742 */ "G_INDEXED_LOAD\000"
2020 /* 1757 */ "G_LOAD\000"
2021 /* 1764 */ "G_VECREDUCE_FADD\000"
2022 /* 1781 */ "G_FADD\000"
2023 /* 1788 */ "G_VECREDUCE_SEQ_FADD\000"
2024 /* 1809 */ "G_STRICT_FADD\000"
2025 /* 1823 */ "G_ATOMICRMW_FADD\000"
2026 /* 1840 */ "G_VECREDUCE_ADD\000"
2027 /* 1856 */ "G_ADD\000"
2028 /* 1862 */ "G_PTR_ADD\000"
2029 /* 1872 */ "G_ATOMICRMW_ADD\000"
2030 /* 1888 */ "G_ATOMICRMW_NAND\000"
2031 /* 1905 */ "G_VECREDUCE_AND\000"
2032 /* 1921 */ "G_AND\000"
2033 /* 1927 */ "G_ATOMICRMW_AND\000"
2034 /* 1943 */ "LIFETIME_END\000"
2035 /* 1956 */ "G_BRCOND\000"
2036 /* 1965 */ "G_ATOMICRMW_USUB_COND\000"
2037 /* 1987 */ "G_LLROUND\000"
2038 /* 1997 */ "G_LROUND\000"
2039 /* 2006 */ "G_INTRINSIC_ROUND\000"
2040 /* 2024 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
2041 /* 2050 */ "LOAD_STACK_GUARD\000"
2042 /* 2067 */ "PSEUDO_PROBE\000"
2043 /* 2080 */ "G_SSUBE\000"
2044 /* 2088 */ "G_USUBE\000"
2045 /* 2096 */ "G_FENCE\000"
2046 /* 2104 */ "ARITH_FENCE\000"
2047 /* 2116 */ "REG_SEQUENCE\000"
2048 /* 2129 */ "G_SADDE\000"
2049 /* 2137 */ "G_UADDE\000"
2050 /* 2145 */ "G_GET_FPMODE\000"
2051 /* 2158 */ "G_RESET_FPMODE\000"
2052 /* 2173 */ "G_SET_FPMODE\000"
2053 /* 2186 */ "G_FMINNUM_IEEE\000"
2054 /* 2201 */ "G_FMAXNUM_IEEE\000"
2055 /* 2216 */ "G_VSCALE\000"
2056 /* 2225 */ "G_JUMP_TABLE\000"
2057 /* 2238 */ "BUNDLE\000"
2058 /* 2245 */ "G_MEMSET_INLINE\000"
2059 /* 2261 */ "G_MEMCPY_INLINE\000"
2060 /* 2277 */ "RELOC_NONE\000"
2061 /* 2288 */ "LOCAL_ESCAPE\000"
2062 /* 2301 */ "ASSIGN_TYPE\000"
2063 /* 2313 */ "G_FPTRUNCSTORE\000"
2064 /* 2328 */ "G_STACKRESTORE\000"
2065 /* 2343 */ "G_INDEXED_STORE\000"
2066 /* 2359 */ "G_STORE\000"
2067 /* 2367 */ "G_BITREVERSE\000"
2068 /* 2380 */ "FAKE_USE\000"
2069 /* 2389 */ "DBG_VALUE\000"
2070 /* 2399 */ "G_GLOBAL_VALUE\000"
2071 /* 2414 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2072 /* 2437 */ "CONVERGENCECTRL_GLUE\000"
2073 /* 2458 */ "G_STACKSAVE\000"
2074 /* 2470 */ "G_MEMMOVE\000"
2075 /* 2480 */ "G_FREEZE\000"
2076 /* 2489 */ "G_FCANONICALIZE\000"
2077 /* 2505 */ "G_FMODF\000"
2078 /* 2513 */ "INIT_UNDEF\000"
2079 /* 2524 */ "G_IMPLICIT_DEF\000"
2080 /* 2539 */ "DBG_INSTR_REF\000"
2081 /* 2553 */ "OpConvertSToF\000"
2082 /* 2567 */ "OpConvertUToF\000"
2083 /* 2581 */ "OpConstantF\000"
2084 /* 2593 */ "G_FNEG\000"
2085 /* 2600 */ "EXTRACT_SUBREG\000"
2086 /* 2615 */ "INSERT_SUBREG\000"
2087 /* 2629 */ "G_SEXT_INREG\000"
2088 /* 2642 */ "SUBREG_TO_REG\000"
2089 /* 2656 */ "G_ATOMIC_CMPXCHG\000"
2090 /* 2673 */ "G_ATOMICRMW_XCHG\000"
2091 /* 2690 */ "G_GET_ROUNDING\000"
2092 /* 2705 */ "G_SET_ROUNDING\000"
2093 /* 2720 */ "G_FLOG\000"
2094 /* 2727 */ "G_VAARG\000"
2095 /* 2735 */ "PREALLOCATED_ARG\000"
2096 /* 2752 */ "G_PREFETCH\000"
2097 /* 2763 */ "G_CLMULH\000"
2098 /* 2772 */ "G_SMULH\000"
2099 /* 2780 */ "G_UMULH\000"
2100 /* 2788 */ "G_FTANH\000"
2101 /* 2796 */ "G_FSINH\000"
2102 /* 2804 */ "G_FCOSH\000"
2103 /* 2812 */ "DBG_PHI\000"
2104 /* 2820 */ "G_FPTOSI\000"
2105 /* 2829 */ "G_FPTOUI\000"
2106 /* 2838 */ "G_FPOWI\000"
2107 /* 2846 */ "OpConstantI\000"
2108 /* 2858 */ "COPY_LANEMASK\000"
2109 /* 2872 */ "G_PTRMASK\000"
2110 /* 2882 */ "GC_LABEL\000"
2111 /* 2891 */ "DBG_LABEL\000"
2112 /* 2901 */ "EH_LABEL\000"
2113 /* 2910 */ "ANNOTATION_LABEL\000"
2114 /* 2927 */ "ICALL_BRANCH_FUNNEL\000"
2115 /* 2947 */ "OpRoundFToTF32INTEL\000"
2116 /* 2967 */ "OpConvertFToBF16INTEL\000"
2117 /* 2989 */ "OpConvertBF16ToFINTEL\000"
2118 /* 3011 */ "OpSubgroupImageMediaBlockReadINTEL\000"
2119 /* 3046 */ "OpSubgroupImageBlockReadINTEL\000"
2120 /* 3076 */ "OpSubgroupBlockReadINTEL\000"
2121 /* 3101 */ "OpPredicatedLoadINTEL\000"
2122 /* 3123 */ "OpSubgroup2DBlockLoadINTEL\000"
2123 /* 3150 */ "OpCooperativeMatrixLoadCheckedINTEL\000"
2124 /* 3186 */ "OpCooperativeMatrixStoreCheckedINTEL\000"
2125 /* 3223 */ "OpCooperativeMatrixConstructCheckedINTEL\000"
2126 /* 3264 */ "OpSpecConstantCompositeContinuedINTEL\000"
2127 /* 3302 */ "OpConstantCompositeContinuedINTEL\000"
2128 /* 3336 */ "OpTypeStructContinuedINTEL\000"
2129 /* 3363 */ "OpCompositeConstructContinuedINTEL\000"
2130 /* 3398 */ "OpCooperativeMatrixGetElementCoordINTEL\000"
2131 /* 3438 */ "OpConvertHandleToSampledImageINTEL\000"
2132 /* 3473 */ "OpConvertHandleToImageINTEL\000"
2133 /* 3501 */ "OpSubgroupShuffleINTEL\000"
2134 /* 3524 */ "OpPredicatedStoreINTEL\000"
2135 /* 3547 */ "OpSubgroup2DBlockStoreINTEL\000"
2136 /* 3575 */ "OpSubgroup2DBlockLoadTransposeINTEL\000"
2137 /* 3611 */ "OpSubgroupMatrixMultiplyAccumulateINTEL\000"
2138 /* 3651 */ "OpSubgroupImageMediaBlockWriteINTEL\000"
2139 /* 3687 */ "OpSubgroupImageBlockWriteINTEL\000"
2140 /* 3718 */ "OpSubgroupBlockWriteINTEL\000"
2141 /* 3744 */ "OpControlBarrierArriveINTEL\000"
2142 /* 3772 */ "OpSubgroup2DBlockPrefetchINTEL\000"
2143 /* 3803 */ "OpCooperativeMatrixPrefetchINTEL\000"
2144 /* 3836 */ "OpAliasScopeDeclINTEL\000"
2145 /* 3858 */ "OpAliasDomainDeclINTEL\000"
2146 /* 3881 */ "OpAliasScopeListDeclINTEL\000"
2147 /* 3907 */ "OpAsmCallINTEL\000"
2148 /* 3922 */ "OpFunctionPointerCallINTEL\000"
2149 /* 3949 */ "OpLoopControlINTEL\000"
2150 /* 3968 */ "OpSubgroup2DBlockLoadTransformINTEL\000"
2151 /* 4004 */ "OpAsmINTEL\000"
2152 /* 4015 */ "OpBitwiseFunctionINTEL\000"
2153 /* 4038 */ "OpSubgroupShuffleDownINTEL\000"
2154 /* 4065 */ "OpSubgroupShuffleUpINTEL\000"
2155 /* 4090 */ "OpPtrCastToCrossWorkgroupINTEL\000"
2156 /* 4121 */ "OpMaskedGatherINTEL\000"
2157 /* 4141 */ "OpConvertHandleToSamplerINTEL\000"
2158 /* 4171 */ "OpConstantFunctionPointerINTEL\000"
2159 /* 4202 */ "OpMaskedScatterINTEL\000"
2160 /* 4223 */ "OpSubgroupShuffleXorINTEL\000"
2161 /* 4249 */ "OpCrossWorkgroupCastToPtrINTEL\000"
2162 /* 4280 */ "OpAsmTargetINTEL\000"
2163 /* 4297 */ "OpControlBarrierWaitINTEL\000"
2164 /* 4323 */ "OpUntypedVariableLengthArrayINTEL\000"
2165 /* 4357 */ "OpVariableLengthArrayINTEL\000"
2166 /* 4384 */ "OpRestoreMemoryINTEL\000"
2167 /* 4405 */ "OpSaveMemoryINTEL\000"
2168 /* 4423 */ "G_FSHL\000"
2169 /* 4430 */ "G_SHL\000"
2170 /* 4436 */ "G_FCEIL\000"
2171 /* 4444 */ "G_SAVGCEIL\000"
2172 /* 4455 */ "G_UAVGCEIL\000"
2173 /* 4466 */ "PATCHABLE_TAIL_CALL\000"
2174 /* 4486 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2175 /* 4513 */ "PATCHABLE_EVENT_CALL\000"
2176 /* 4534 */ "FENTRY_CALL\000"
2177 /* 4546 */ "KILL\000"
2178 /* 4551 */ "G_CONSTANT_POOL\000"
2179 /* 4567 */ "G_ROTL\000"
2180 /* 4574 */ "G_VECREDUCE_FMUL\000"
2181 /* 4591 */ "G_FMUL\000"
2182 /* 4598 */ "G_VECREDUCE_SEQ_FMUL\000"
2183 /* 4619 */ "G_STRICT_FMUL\000"
2184 /* 4633 */ "G_CLMUL\000"
2185 /* 4641 */ "G_VECREDUCE_MUL\000"
2186 /* 4657 */ "G_MUL\000"
2187 /* 4663 */ "G_FREM\000"
2188 /* 4670 */ "G_STRICT_FREM\000"
2189 /* 4684 */ "G_SREM\000"
2190 /* 4691 */ "G_UREM\000"
2191 /* 4698 */ "G_SDIVREM\000"
2192 /* 4708 */ "G_UDIVREM\000"
2193 /* 4718 */ "INLINEASM\000"
2194 /* 4728 */ "G_VECREDUCE_FMINIMUM\000"
2195 /* 4749 */ "G_FMINIMUM\000"
2196 /* 4760 */ "G_ATOMICRMW_FMINIMUM\000"
2197 /* 4781 */ "G_VECREDUCE_FMAXIMUM\000"
2198 /* 4802 */ "G_FMAXIMUM\000"
2199 /* 4813 */ "G_ATOMICRMW_FMAXIMUM\000"
2200 /* 4834 */ "G_VECREDUCE_FMINIMUMNUM\000"
2201 /* 4858 */ "G_FMINIMUMNUM\000"
2202 /* 4872 */ "G_ATOMICRMW_FMINIMUMNUM\000"
2203 /* 4896 */ "G_VECREDUCE_FMAXIMUMNUM\000"
2204 /* 4920 */ "G_FMAXIMUMNUM\000"
2205 /* 4934 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
2206 /* 4958 */ "G_FMINNUM\000"
2207 /* 4968 */ "G_FMAXNUM\000"
2208 /* 4978 */ "G_FATAN\000"
2209 /* 4986 */ "G_FTAN\000"
2210 /* 4993 */ "G_INTRINSIC_ROUNDEVEN\000"
2211 /* 5015 */ "G_ASSERT_ALIGN\000"
2212 /* 5030 */ "G_FCOPYSIGN\000"
2213 /* 5042 */ "G_VECREDUCE_FMIN\000"
2214 /* 5059 */ "G_ATOMICRMW_FMIN\000"
2215 /* 5076 */ "G_VECREDUCE_SMIN\000"
2216 /* 5093 */ "G_SMIN\000"
2217 /* 5100 */ "G_VECREDUCE_UMIN\000"
2218 /* 5117 */ "G_UMIN\000"
2219 /* 5124 */ "G_ATOMICRMW_UMIN\000"
2220 /* 5141 */ "G_ATOMICRMW_MIN\000"
2221 /* 5157 */ "G_FASIN\000"
2222 /* 5165 */ "G_FSIN\000"
2223 /* 5172 */ "CFI_INSTRUCTION\000"
2224 /* 5188 */ "G_CTLZ_ZERO_POISON\000"
2225 /* 5207 */ "G_CTTZ_ZERO_POISON\000"
2226 /* 5226 */ "G_SSUBO\000"
2227 /* 5234 */ "G_USUBO\000"
2228 /* 5242 */ "G_SADDO\000"
2229 /* 5250 */ "G_UADDO\000"
2230 /* 5258 */ "JUMP_TABLE_DEBUG_INFO\000"
2231 /* 5280 */ "G_SMULO\000"
2232 /* 5288 */ "G_UMULO\000"
2233 /* 5296 */ "G_BZERO\000"
2234 /* 5304 */ "STACKMAP\000"
2235 /* 5313 */ "G_DEBUGTRAP\000"
2236 /* 5325 */ "G_UBSANTRAP\000"
2237 /* 5337 */ "G_TRAP\000"
2238 /* 5344 */ "G_ATOMICRMW_UDEC_WRAP\000"
2239 /* 5366 */ "G_ATOMICRMW_UINC_WRAP\000"
2240 /* 5388 */ "G_BSWAP\000"
2241 /* 5396 */ "G_SITOFP\000"
2242 /* 5405 */ "G_UITOFP\000"
2243 /* 5414 */ "G_FCMP\000"
2244 /* 5421 */ "G_STRICT_FCMP\000"
2245 /* 5435 */ "G_ICMP\000"
2246 /* 5442 */ "G_SCMP\000"
2247 /* 5449 */ "G_UCMP\000"
2248 /* 5456 */ "CONVERGENCECTRL_LOOP\000"
2249 /* 5477 */ "G_CTPOP\000"
2250 /* 5485 */ "PATCHABLE_OP\000"
2251 /* 5498 */ "FAULTING_OP\000"
2252 /* 5510 */ "PREALLOCATED_SETUP\000"
2253 /* 5529 */ "G_FLDEXP\000"
2254 /* 5538 */ "G_STRICT_FLDEXP\000"
2255 /* 5554 */ "G_FEXP\000"
2256 /* 5561 */ "G_FFREXP\000"
2257 /* 5570 */ "G_BR\000"
2258 /* 5575 */ "INLINEASM_BR\000"
2259 /* 5588 */ "G_BLOCK_ADDR\000"
2260 /* 5601 */ "MEMBARRIER\000"
2261 /* 5612 */ "G_CONSTANT_FOLD_BARRIER\000"
2262 /* 5636 */ "PATCHABLE_FUNCTION_ENTER\000"
2263 /* 5661 */ "G_READCYCLECOUNTER\000"
2264 /* 5680 */ "G_READSTEADYCOUNTER\000"
2265 /* 5700 */ "G_READ_REGISTER\000"
2266 /* 5716 */ "G_WRITE_REGISTER\000"
2267 /* 5733 */ "OpFmaKHR\000"
2268 /* 5742 */ "OpCooperativeMatrixLoadKHR\000"
2269 /* 5769 */ "OpCooperativeMatrixMulAddKHR\000"
2270 /* 5798 */ "OpGroupBitwiseAndKHR\000"
2271 /* 5819 */ "OpGroupLogicalAndKHR\000"
2272 /* 5840 */ "OpUntypedVariableKHR\000"
2273 /* 5861 */ "OpCooperativeMatrixStoreKHR\000"
2274 /* 5889 */ "OpGroupNonUniformRotateKHR\000"
2275 /* 5916 */ "OpAssumeTrueKHR\000"
2276 /* 5932 */ "OpFreezeKHR\000"
2277 /* 5944 */ "OpUntypedPrefetchKHR\000"
2278 /* 5965 */ "OpCooperativeMatrixLengthKHR\000"
2279 /* 5994 */ "OpReadClockKHR\000"
2280 /* 6009 */ "OpGroupFMulKHR\000"
2281 /* 6024 */ "OpGroupIMulKHR\000"
2282 /* 6039 */ "OpUntypedAccessChainKHR\000"
2283 /* 6063 */ "OpUntypedPtrAccessChainKHR\000"
2284 /* 6090 */ "OpUntypedInBoundsPtrAccessChainKHR\000"
2285 /* 6125 */ "OpUntypedInBoundsAccessChainKHR\000"
2286 /* 6157 */ "OpPoisonKHR\000"
2287 /* 6169 */ "OpGroupBitwiseOrKHR\000"
2288 /* 6189 */ "OpGroupLogicalOrKHR\000"
2289 /* 6209 */ "OpTypeUntypedPointerKHR\000"
2290 /* 6233 */ "OpGroupBitwiseXorKHR\000"
2291 /* 6254 */ "OpGroupLogicalXorKHR\000"
2292 /* 6275 */ "OpExpectKHR\000"
2293 /* 6287 */ "OpAbortKHR\000"
2294 /* 6298 */ "OpTypeCooperativeMatrixKHR\000"
2295 /* 6325 */ "OpUntypedGroupAsyncCopyKHR\000"
2296 /* 6352 */ "G_ASHR\000"
2297 /* 6359 */ "G_FSHR\000"
2298 /* 6366 */ "G_LSHR\000"
2299 /* 6373 */ "G_CLMULR\000"
2300 /* 6382 */ "CONVERGENCECTRL_ANCHOR\000"
2301 /* 6405 */ "G_FFLOOR\000"
2302 /* 6414 */ "G_SAVGFLOOR\000"
2303 /* 6426 */ "G_UAVGFLOOR\000"
2304 /* 6438 */ "G_EXTRACT_SUBVECTOR\000"
2305 /* 6458 */ "G_INSERT_SUBVECTOR\000"
2306 /* 6477 */ "G_BUILD_VECTOR\000"
2307 /* 6492 */ "G_SHUFFLE_VECTOR\000"
2308 /* 6509 */ "G_STEP_VECTOR\000"
2309 /* 6523 */ "G_SPLAT_VECTOR\000"
2310 /* 6538 */ "G_VECREDUCE_XOR\000"
2311 /* 6554 */ "G_XOR\000"
2312 /* 6560 */ "G_ATOMICRMW_XOR\000"
2313 /* 6576 */ "G_VECREDUCE_OR\000"
2314 /* 6591 */ "G_OR\000"
2315 /* 6596 */ "G_ATOMICRMW_OR\000"
2316 /* 6611 */ "G_ROTR\000"
2317 /* 6618 */ "G_INTTOPTR\000"
2318 /* 6629 */ "G_FABS\000"
2319 /* 6636 */ "G_ABS\000"
2320 /* 6642 */ "G_ABDS\000"
2321 /* 6649 */ "G_UNMERGE_VALUES\000"
2322 /* 6666 */ "G_MERGE_VALUES\000"
2323 /* 6681 */ "G_CTLS\000"
2324 /* 6688 */ "G_FACOS\000"
2325 /* 6696 */ "G_FCOS\000"
2326 /* 6703 */ "G_FSINCOS\000"
2327 /* 6713 */ "G_STRICT_FCMPS\000"
2328 /* 6728 */ "G_CONCAT_VECTORS\000"
2329 /* 6745 */ "COPY_TO_REGCLASS\000"
2330 /* 6762 */ "G_IS_FPCLASS\000"
2331 /* 6775 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2332 /* 6805 */ "G_VECTOR_COMPRESS\000"
2333 /* 6823 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2334 /* 6850 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2335 /* 6888 */ "G_TRUNC_SSAT_S\000"
2336 /* 6903 */ "OpFSubS\000"
2337 /* 6911 */ "OpStrictFSubS\000"
2338 /* 6925 */ "OpISubS\000"
2339 /* 6933 */ "OpShiftRightArithmeticS\000"
2340 /* 6957 */ "OpFAddS\000"
2341 /* 6965 */ "OpStrictFAddS\000"
2342 /* 6979 */ "OpIAddS\000"
2343 /* 6987 */ "OpBitwiseAndS\000"
2344 /* 7001 */ "OpUModS\000"
2345 /* 7009 */ "OpShiftLeftLogicalS\000"
2346 /* 7029 */ "OpShiftRightLogicalS\000"
2347 /* 7050 */ "OpFMulS\000"
2348 /* 7058 */ "OpStrictFMulS\000"
2349 /* 7072 */ "OpIMulS\000"
2350 /* 7080 */ "OpFRemS\000"
2351 /* 7088 */ "OpStrictFRemS\000"
2352 /* 7102 */ "OpSRemS\000"
2353 /* 7110 */ "OpConvertFToS\000"
2354 /* 7124 */ "OpSatConvertUToS\000"
2355 /* 7141 */ "OpBitwiseOrS\000"
2356 /* 7154 */ "OpBitwiseXorS\000"
2357 /* 7168 */ "OpFDivS\000"
2358 /* 7176 */ "OpStrictFDivS\000"
2359 /* 7190 */ "OpSDivS\000"
2360 /* 7198 */ "OpUDivS\000"
2361 /* 7206 */ "OpISubBorrowS\000"
2362 /* 7220 */ "OpIAddCarryS\000"
2363 /* 7233 */ "G_SSUBSAT\000"
2364 /* 7243 */ "G_USUBSAT\000"
2365 /* 7253 */ "G_SADDSAT\000"
2366 /* 7263 */ "G_UADDSAT\000"
2367 /* 7273 */ "G_SSHLSAT\000"
2368 /* 7283 */ "G_USHLSAT\000"
2369 /* 7293 */ "G_SMULFIXSAT\000"
2370 /* 7306 */ "G_UMULFIXSAT\000"
2371 /* 7319 */ "G_SDIVFIXSAT\000"
2372 /* 7332 */ "G_UDIVFIXSAT\000"
2373 /* 7345 */ "G_ATOMICRMW_USUB_SAT\000"
2374 /* 7366 */ "G_FPTOSI_SAT\000"
2375 /* 7379 */ "G_FPTOUI_SAT\000"
2376 /* 7392 */ "G_EXTRACT\000"
2377 /* 7402 */ "G_SELECT\000"
2378 /* 7411 */ "G_BRINDIRECT\000"
2379 /* 7424 */ "PATCHABLE_RET\000"
2380 /* 7438 */ "G_MEMSET\000"
2381 /* 7447 */ "PATCHABLE_FUNCTION_EXIT\000"
2382 /* 7471 */ "G_BRJT\000"
2383 /* 7478 */ "G_EXTRACT_VECTOR_ELT\000"
2384 /* 7499 */ "G_INSERT_VECTOR_ELT\000"
2385 /* 7519 */ "G_FCONSTANT\000"
2386 /* 7531 */ "G_CONSTANT\000"
2387 /* 7542 */ "G_INTRINSIC_CONVERGENT\000"
2388 /* 7565 */ "STATEPOINT\000"
2389 /* 7576 */ "PATCHPOINT\000"
2390 /* 7587 */ "G_PTRTOINT\000"
2391 /* 7598 */ "G_FRINT\000"
2392 /* 7606 */ "G_INTRINSIC_LLRINT\000"
2393 /* 7625 */ "G_INTRINSIC_LRINT\000"
2394 /* 7643 */ "G_FNEARBYINT\000"
2395 /* 7656 */ "G_VASTART\000"
2396 /* 7666 */ "LIFETIME_START\000"
2397 /* 7681 */ "G_INVOKE_REGION_START\000"
2398 /* 7703 */ "G_INSERT\000"
2399 /* 7712 */ "G_FSQRT\000"
2400 /* 7720 */ "G_STRICT_FSQRT\000"
2401 /* 7735 */ "G_BITCAST\000"
2402 /* 7745 */ "G_ADDRSPACE_CAST\000"
2403 /* 7762 */ "DBG_VALUE_LIST\000"
2404 /* 7777 */ "G_FPEXT\000"
2405 /* 7785 */ "G_SEXT\000"
2406 /* 7792 */ "G_ASSERT_SEXT\000"
2407 /* 7806 */ "G_ANYEXT\000"
2408 /* 7815 */ "G_ZEXT\000"
2409 /* 7822 */ "G_ASSERT_ZEXT\000"
2410 /* 7836 */ "OpTypeVectorIdEXT\000"
2411 /* 7854 */ "OpAtomicFAddEXT\000"
2412 /* 7870 */ "OpArithmeticFenceEXT\000"
2413 /* 7891 */ "OpAtomicFMinEXT\000"
2414 /* 7907 */ "OpAtomicFMaxEXT\000"
2415 /* 7923 */ "G_ABDU\000"
2416 /* 7930 */ "G_TRUNC_SSAT_U\000"
2417 /* 7945 */ "G_TRUNC_USAT_U\000"
2418 /* 7960 */ "OpConvertFToU\000"
2419 /* 7974 */ "OpSatConvertSToU\000"
2420 /* 7991 */ "OpConvertPtrToU\000"
2421 /* 8007 */ "G_FDIV\000"
2422 /* 8014 */ "G_STRICT_FDIV\000"
2423 /* 8028 */ "G_SDIV\000"
2424 /* 8035 */ "G_UDIV\000"
2425 /* 8042 */ "G_GET_FPENV\000"
2426 /* 8054 */ "G_RESET_FPENV\000"
2427 /* 8068 */ "G_SET_FPENV\000"
2428 /* 8080 */ "OpTypeAccelerationStructureNV\000"
2429 /* 8110 */ "OpImageSampleFootprintNV\000"
2430 /* 8135 */ "OpTypeCooperativeMatrixNV\000"
2431 /* 8161 */ "OpFSubV\000"
2432 /* 8169 */ "OpStrictFSubV\000"
2433 /* 8183 */ "OpISubV\000"
2434 /* 8191 */ "OpShiftRightArithmeticV\000"
2435 /* 8215 */ "OpFAddV\000"
2436 /* 8223 */ "OpStrictFAddV\000"
2437 /* 8237 */ "OpIAddV\000"
2438 /* 8245 */ "OpBitwiseAndV\000"
2439 /* 8259 */ "OpUModV\000"
2440 /* 8267 */ "OpFNegateV\000"
2441 /* 8278 */ "OpShiftLeftLogicalV\000"
2442 /* 8298 */ "OpShiftRightLogicalV\000"
2443 /* 8319 */ "OpFMulV\000"
2444 /* 8327 */ "OpStrictFMulV\000"
2445 /* 8341 */ "OpIMulV\000"
2446 /* 8349 */ "OpFRemV\000"
2447 /* 8357 */ "OpStrictFRemV\000"
2448 /* 8371 */ "OpSRemV\000"
2449 /* 8379 */ "OpBitwiseOrV\000"
2450 /* 8392 */ "OpBitwiseXorV\000"
2451 /* 8406 */ "OpFDivV\000"
2452 /* 8414 */ "OpStrictFDivV\000"
2453 /* 8428 */ "OpSDivV\000"
2454 /* 8436 */ "OpUDivV\000"
2455 /* 8444 */ "OpISubBorrowV\000"
2456 /* 8458 */ "OpIAddCarryV\000"
2457 /* 8471 */ "G_FPOW\000"
2458 /* 8478 */ "G_VECREDUCE_FMAX\000"
2459 /* 8495 */ "G_ATOMICRMW_FMAX\000"
2460 /* 8512 */ "G_VECREDUCE_SMAX\000"
2461 /* 8529 */ "G_SMAX\000"
2462 /* 8536 */ "G_VECREDUCE_UMAX\000"
2463 /* 8553 */ "G_UMAX\000"
2464 /* 8560 */ "G_ATOMICRMW_UMAX\000"
2465 /* 8577 */ "G_ATOMICRMW_MAX\000"
2466 /* 8593 */ "G_FRAME_INDEX\000"
2467 /* 8607 */ "G_SBFX\000"
2468 /* 8614 */ "G_UBFX\000"
2469 /* 8621 */ "G_SMULFIX\000"
2470 /* 8631 */ "G_UMULFIX\000"
2471 /* 8641 */ "G_SDIVFIX\000"
2472 /* 8651 */ "G_UDIVFIX\000"
2473 /* 8661 */ "G_MEMCPY\000"
2474 /* 8670 */ "COPY\000"
2475 /* 8675 */ "CONVERGENCECTRL_ENTRY\000"
2476 /* 8697 */ "G_CTLZ\000"
2477 /* 8704 */ "G_CTTZ\000"
2478 /* 8711 */ "OpAtomicISub\000"
2479 /* 8724 */ "OpVectorExtractDynamic\000"
2480 /* 8747 */ "OpVectorInsertDynamic\000"
2481 /* 8769 */ "OpPtrCastToGeneric\000"
2482 /* 8788 */ "OpExecutionModeId\000"
2483 /* 8806 */ "OpDecorateId\000"
2484 /* 8819 */ "OpIsValidReserveId\000"
2485 /* 8838 */ "OpTypeReserveId\000"
2486 /* 8854 */ "OpImageRead\000"
2487 /* 8866 */ "OpImageSparseRead\000"
2488 /* 8884 */ "OpAtomicLoad\000"
2489 /* 8897 */ "OpLoad\000"
2490 /* 8904 */ "OpGroupNonUniformFAdd\000"
2491 /* 8926 */ "OpGroupFAdd\000"
2492 /* 8938 */ "OpAtomicIAdd\000"
2493 /* 8951 */ "OpGroupNonUniformIAdd\000"
2494 /* 8973 */ "OpGroupIAdd\000"
2495 /* 8985 */ "OpSMulExtended\000"
2496 /* 9000 */ "OpUMulExtended\000"
2497 /* 9015 */ "OpOrdered\000"
2498 /* 9025 */ "OpUnordered\000"
2499 /* 9037 */ "OpModuleProcessed\000"
2500 /* 9055 */ "OpSourceContinued\000"
2501 /* 9073 */ "OpCopyMemorySized\000"
2502 /* 9091 */ "OpTypeVoid\000"
2503 /* 9102 */ "OpAtomicAnd\000"
2504 /* 9114 */ "OpGroupNonUniformBitwiseAnd\000"
2505 /* 9142 */ "OpGroupNonUniformLogicalAnd\000"
2506 /* 9170 */ "OpLogicalAnd\000"
2507 /* 9183 */ "OpFunctionEnd\000"
2508 /* 9197 */ "OpSelectSFSCond\000"
2509 /* 9213 */ "OpSelectVFSCond\000"
2510 /* 9229 */ "OpSelectSISCond\000"
2511 /* 9245 */ "OpSelectVISCond\000"
2512 /* 9261 */ "OpSelectSPSCond\000"
2513 /* 9277 */ "OpSelectVPSCond\000"
2514 /* 9293 */ "OpSelectSFVCond\000"
2515 /* 9309 */ "OpSelectVFVCond\000"
2516 /* 9325 */ "OpSelectSIVCond\000"
2517 /* 9341 */ "OpSelectVIVCond\000"
2518 /* 9357 */ "OpSelectSPVCond\000"
2519 /* 9373 */ "OpSelectVPVCond\000"
2520 /* 9389 */ "OpImageQuerySizeLod\000"
2521 /* 9409 */ "OpImageSampleImplicitLod\000"
2522 /* 9434 */ "OpImageSparseSampleImplicitLod\000"
2523 /* 9465 */ "OpImageSampleDrefImplicitLod\000"
2524 /* 9494 */ "OpImageSparseSampleDrefImplicitLod\000"
2525 /* 9529 */ "OpImageSampleProjDrefImplicitLod\000"
2526 /* 9562 */ "OpImageSparseSampleProjDrefImplicitLod\000"
2527 /* 9601 */ "OpImageSampleProjImplicitLod\000"
2528 /* 9630 */ "OpImageSparseSampleProjImplicitLod\000"
2529 /* 9665 */ "OpImageSampleExplicitLod\000"
2530 /* 9690 */ "OpImageSparseSampleExplicitLod\000"
2531 /* 9721 */ "OpImageSampleDrefExplicitLod\000"
2532 /* 9750 */ "OpImageSparseSampleDrefExplicitLod\000"
2533 /* 9785 */ "OpImageSampleProjDrefExplicitLod\000"
2534 /* 9818 */ "OpImageSparseSampleProjDrefExplicitLod\000"
2535 /* 9857 */ "OpImageSampleProjExplicitLod\000"
2536 /* 9886 */ "OpImageSparseSampleProjExplicitLod\000"
2537 /* 9921 */ "OpImageQueryLod\000"
2538 /* 9937 */ "OpFMod\000"
2539 /* 9944 */ "OpSMod\000"
2540 /* 9951 */ "OpSource\000"
2541 /* 9960 */ "OpExecutionMode\000"
2542 /* 9976 */ "OpTypeSampledImage\000"
2543 /* 9995 */ "OpSampledImage\000"
2544 /* 10010 */ "OpTypeImage\000"
2545 /* 10022 */ "OpImage\000"
2546 /* 10030 */ "OpTypePipeStorage\000"
2547 /* 10048 */ "OpBuildNDRange\000"
2548 /* 10063 */ "OpAtomicExchange\000"
2549 /* 10080 */ "OpAtomicCompareExchange\000"
2550 /* 10104 */ "OpSelectionMerge\000"
2551 /* 10121 */ "OpLoopMerge\000"
2552 /* 10133 */ "OpUnreachable\000"
2553 /* 10147 */ "OpVariable\000"
2554 /* 10158 */ "OpGroupNonUniformShuffle\000"
2555 /* 10183 */ "OpVectorShuffle\000"
2556 /* 10199 */ "OpGetKernelPreferredWorkGroupSizeMultiple\000"
2557 /* 10241 */ "OpName\000"
2558 /* 10248 */ "OpMemberName\000"
2559 /* 10261 */ "OpFwidthFine\000"
2560 /* 10274 */ "OpDPdxFine\000"
2561 /* 10285 */ "OpDPdyFine\000"
2562 /* 10296 */ "OpNoLine\000"
2563 /* 10305 */ "OpLine\000"
2564 /* 10312 */ "OpReservedReadPipe\000"
2565 /* 10331 */ "OpReadPipe\000"
2566 /* 10342 */ "OpCommitReadPipe\000"
2567 /* 10359 */ "OpGroupCommitReadPipe\000"
2568 /* 10381 */ "OpTypePipe\000"
2569 /* 10392 */ "OpReservedWritePipe\000"
2570 /* 10412 */ "OpWritePipe\000"
2571 /* 10424 */ "OpCommitWritePipe\000"
2572 /* 10442 */ "OpGroupCommitWritePipe\000"
2573 /* 10465 */ "UNKNOWN_type\000"
2574 /* 10478 */ "OpAtomicStore\000"
2575 /* 10492 */ "OpStore\000"
2576 /* 10500 */ "OpSpecConstantFalse\000"
2577 /* 10520 */ "OpConstantFalse\000"
2578 /* 10536 */ "OpTranspose\000"
2579 /* 10548 */ "OpFwidthCoarse\000"
2580 /* 10563 */ "OpDPdxCoarse\000"
2581 /* 10576 */ "OpDPdyCoarse\000"
2582 /* 10589 */ "OpBitReverse\000"
2583 /* 10602 */ "OpFNegate\000"
2584 /* 10612 */ "OpSNegate\000"
2585 /* 10622 */ "OpDecorate\000"
2586 /* 10633 */ "OpMemberDecorate\000"
2587 /* 10650 */ "OpIsFinite\000"
2588 /* 10661 */ "OpImageWrite\000"
2589 /* 10674 */ "OpSpecConstantComposite\000"
2590 /* 10698 */ "OpConstantComposite\000"
2591 /* 10718 */ "OpTypeQueue\000"
2592 /* 10730 */ "OpGetDefaultQueue\000"
2593 /* 10748 */ "OpReturnValue\000"
2594 /* 10762 */ "OpTypeOpaque\000"
2595 /* 10775 */ "OpSpecConstantTrue\000"
2596 /* 10794 */ "OpConstantTrue\000"
2597 /* 10809 */ "OpEndPrimitive\000"
2598 /* 10824 */ "OpEndStreamPrimitive\000"
2599 /* 10845 */ "OpGetKernelNDrangeMaxSubGroupSize\000"
2600 /* 10879 */ "OpGetKernelWorkGroupSize\000"
2601 /* 10904 */ "OpImageQuerySize\000"
2602 /* 10921 */ "OpNamedBarrierInitialize\000"
2603 /* 10946 */ "OpSizeOf\000"
2604 /* 10955 */ "OpUndef\000"
2605 /* 10963 */ "OpPtrDiff\000"
2606 /* 10973 */ "OpIsInf\000"
2607 /* 10981 */ "OpDecorateString\000"
2608 /* 10998 */ "OpMemberDecorateString\000"
2609 /* 11021 */ "OpString\000"
2610 /* 11030 */ "OpBranch\000"
2611 /* 11039 */ "OpImageFetch\000"
2612 /* 11052 */ "OpImageSparseFetch\000"
2613 /* 11071 */ "OpSwitch\000"
2614 /* 11080 */ "OpFwidth\000"
2615 /* 11089 */ "OpArrayLength\000"
2616 /* 11103 */ "OpPhi\000"
2617 /* 11109 */ "OpAtomicCompareExchangeWeak\000"
2618 /* 11137 */ "OpCopyLogical\000"
2619 /* 11151 */ "OpIsNormal\000"
2620 /* 11162 */ "OpBranchConditional\000"
2621 /* 11182 */ "OpIEqual\000"
2622 /* 11191 */ "OpFOrdEqual\000"
2623 /* 11203 */ "OpFUnordEqual\000"
2624 /* 11217 */ "OpLogicalEqual\000"
2625 /* 11232 */ "OpGroupNonUniformAllEqual\000"
2626 /* 11258 */ "OpSGreaterThanEqual\000"
2627 /* 11278 */ "OpUGreaterThanEqual\000"
2628 /* 11298 */ "OpFOrdGreaterThanEqual\000"
2629 /* 11321 */ "OpFUnordGreaterThanEqual\000"
2630 /* 11346 */ "OpSLessThanEqual\000"
2631 /* 11363 */ "OpULessThanEqual\000"
2632 /* 11380 */ "OpFOrdLessThanEqual\000"
2633 /* 11400 */ "OpFUnordLessThanEqual\000"
2634 /* 11422 */ "OpPtrEqual\000"
2635 /* 11433 */ "OpINotEqual\000"
2636 /* 11445 */ "OpFOrdNotEqual\000"
2637 /* 11460 */ "OpFUnordNotEqual\000"
2638 /* 11477 */ "OpLogicalNotEqual\000"
2639 /* 11495 */ "OpPtrNotEqual\000"
2640 /* 11509 */ "OpLabel\000"
2641 /* 11517 */ "OpMemoryModel\000"
2642 /* 11531 */ "OpEnqueueKernel\000"
2643 /* 11547 */ "OpGroupNonUniformAll\000"
2644 /* 11568 */ "OpAll\000"
2645 /* 11574 */ "OpGroupAll\000"
2646 /* 11585 */ "OpFunctionCall\000"
2647 /* 11600 */ "OpKill\000"
2648 /* 11607 */ "OpConstantNull\000"
2649 /* 11622 */ "OpTypeBool\000"
2650 /* 11633 */ "OpGroupNonUniformFMul\000"
2651 /* 11655 */ "OpGroupNonUniformIMul\000"
2652 /* 11677 */ "OpIsNan\000"
2653 /* 11685 */ "OpSGreaterThan\000"
2654 /* 11700 */ "OpUGreaterThan\000"
2655 /* 11715 */ "OpFOrdGreaterThan\000"
2656 /* 11733 */ "OpFUnordGreaterThan\000"
2657 /* 11753 */ "OpSLessThan\000"
2658 /* 11765 */ "OpULessThan\000"
2659 /* 11777 */ "OpFOrdLessThan\000"
2660 /* 11792 */ "OpFUnordLessThan\000"
2661 /* 11809 */ "OpGroupNonUniformFMin\000"
2662 /* 11831 */ "OpGroupFMin\000"
2663 /* 11843 */ "OpAtomicSMin\000"
2664 /* 11856 */ "OpGroupNonUniformSMin\000"
2665 /* 11878 */ "OpGroupSMin\000"
2666 /* 11890 */ "OpAtomicUMin\000"
2667 /* 11903 */ "OpGroupNonUniformUMin\000"
2668 /* 11925 */ "OpGroupUMin\000"
2669 /* 11937 */ "OpAccessChain\000"
2670 /* 11951 */ "OpPtrAccessChain\000"
2671 /* 11968 */ "OpInBoundsPtrAccessChain\000"
2672 /* 11993 */ "OpInBoundsAccessChain\000"
2673 /* 12015 */ "OpSourceExtension\000"
2674 /* 12033 */ "OpExtension\000"
2675 /* 12045 */ "OpDemoteToHelperInvocation\000"
2676 /* 12072 */ "OpTypeFunction\000"
2677 /* 12087 */ "OpFunction\000"
2678 /* 12098 */ "OpReturn\000"
2679 /* 12107 */ "OpGroupNonUniformShuffleDown\000"
2680 /* 12136 */ "OpCaptureEventProfilingInfo\000"
2681 /* 12164 */ "OpSpecConstantOp\000"
2682 /* 12181 */ "OpGroupNonUniformShuffleUp\000"
2683 /* 12208 */ "OpGroupNonUniformQuadSwap\000"
2684 /* 12234 */ "OpNop\000"
2685 /* 12240 */ "OpLifetimeStop\000"
2686 /* 12255 */ "OpAtomicOr\000"
2687 /* 12266 */ "OpGroupNonUniformBitwiseOr\000"
2688 /* 12293 */ "OpGroupNonUniformLogicalOr\000"
2689 /* 12320 */ "OpLogicalOr\000"
2690 /* 12332 */ "OpAtomicFlagClear\000"
2691 /* 12350 */ "OpVectorTimesScalar\000"
2692 /* 12370 */ "OpMatrixTimesScalar\000"
2693 /* 12390 */ "OpImageQueryOrder\000"
2694 /* 12408 */ "OpImageGather\000"
2695 /* 12422 */ "OpImageSparseGather\000"
2696 /* 12442 */ "OpImageDrefGather\000"
2697 /* 12460 */ "OpImageSparseDrefGather\000"
2698 /* 12484 */ "OpTypeNamedBarrier\000"
2699 /* 12503 */ "OpMemoryNamedBarrier\000"
2700 /* 12524 */ "OpControlBarrier\000"
2701 /* 12541 */ "OpMemoryBarrier\000"
2702 /* 12557 */ "OpTypeSampler\000"
2703 /* 12571 */ "OpConstantSampler\000"
2704 /* 12589 */ "OpLessOrGreater\000"
2705 /* 12605 */ "OpFunctionParameter\000"
2706 /* 12625 */ "OpTypeForwardPointer\000"
2707 /* 12646 */ "OpTypePointer\000"
2708 /* 12660 */ "OpImageTexelPointer\000"
2709 /* 12680 */ "OpAtomicXor\000"
2710 /* 12692 */ "OpGroupNonUniformShuffleXor\000"
2711 /* 12720 */ "OpGroupNonUniformBitwiseXor\000"
2712 /* 12748 */ "OpGroupNonUniformLogicalXor\000"
2713 /* 12776 */ "OpTypeVector\000"
2714 /* 12789 */ "OpMatrixTimesVector\000"
2715 /* 12809 */ "OpConvertUToPtr\000"
2716 /* 12825 */ "OpGenericCastToPtr\000"
2717 /* 12844 */ "OpGenericPtrMemSemantics\000"
2718 /* 12869 */ "OpImageQuerySamples\000"
2719 /* 12889 */ "OpImageQueryLevels\000"
2720 /* 12908 */ "OpReserveReadPipePackets\000"
2721 /* 12933 */ "OpGroupReserveReadPipePackets\000"
2722 /* 12963 */ "OpReserveWritePipePackets\000"
2723 /* 12989 */ "OpGroupReserveWritePipePackets\000"
2724 /* 13020 */ "OpGetNumPipePackets\000"
2725 /* 13040 */ "OpGetMaxPipePackets\000"
2726 /* 13060 */ "OpGroupWaitEvents\000"
2727 /* 13078 */ "OpSetUserEventStatus\000"
2728 /* 13099 */ "OpSDotAccSat\000"
2729 /* 13112 */ "OpSUDotAccSat\000"
2730 /* 13126 */ "OpUDotAccSat\000"
2731 /* 13139 */ "OpImageQueryFormat\000"
2732 /* 13158 */ "OpTypeFloat\000"
2733 /* 13170 */ "OpBitFieldSExtract\000"
2734 /* 13189 */ "OpBitFieldUExtract\000"
2735 /* 13208 */ "OpCompositeExtract\000"
2736 /* 13227 */ "OpGroupNonUniformBallotBitExtract\000"
2737 /* 13261 */ "OpCopyObject\000"
2738 /* 13274 */ "OpGroupNonUniformElect\000"
2739 /* 13297 */ "OpOuterProduct\000"
2740 /* 13312 */ "OpTypeStruct\000"
2741 /* 13325 */ "OpCompositeConstruct\000"
2742 /* 13346 */ "OpAtomicFlagTestAndSet\000"
2743 /* 13369 */ "OpSignBitSet\000"
2744 /* 13382 */ "OpGenericCastToPtrExplicit\000"
2745 /* 13409 */ "OpTypeInt\000"
2746 /* 13419 */ "OpSpecConstant\000"
2747 /* 13434 */ "OpImageSparseTexelsResident\000"
2748 /* 13462 */ "OpAtomicIDecrement\000"
2749 /* 13481 */ "OpAtomicIIncrement\000"
2750 /* 13500 */ "OpIsValidEvent\000"
2751 /* 13515 */ "OpTypeDeviceEvent\000"
2752 /* 13533 */ "OpTypeEvent\000"
2753 /* 13545 */ "OpReleaseEvent\000"
2754 /* 13560 */ "OpRetainEvent\000"
2755 /* 13574 */ "OpCreateUserEvent\000"
2756 /* 13592 */ "OpEntryPoint\000"
2757 /* 13605 */ "OpGetKernelNDrangeSubGroupCount\000"
2758 /* 13637 */ "OpBitCount\000"
2759 /* 13648 */ "OpGroupNonUniformBallotBitCount\000"
2760 /* 13680 */ "OpSDot\000"
2761 /* 13687 */ "OpSUDot\000"
2762 /* 13695 */ "OpUDot\000"
2763 /* 13702 */ "OpDot\000"
2764 /* 13708 */ "OpLogicalNot\000"
2765 /* 13721 */ "OpNot\000"
2766 /* 13727 */ "OpGroupNonUniformInverseBallot\000"
2767 /* 13758 */ "OpGroupNonUniformBallot\000"
2768 /* 13782 */ "OpLifetimeStart\000"
2769 /* 13798 */ "OpBitFieldInsert\000"
2770 /* 13815 */ "OpCompositeInsert\000"
2771 /* 13833 */ "OpFConvert\000"
2772 /* 13844 */ "OpSConvert\000"
2773 /* 13855 */ "OpUConvert\000"
2774 /* 13866 */ "OpExtInstImport\000"
2775 /* 13882 */ "OpGroupNonUniformBroadcast\000"
2776 /* 13909 */ "OpGroupBroadcast\000"
2777 /* 13926 */ "OpBitcast\000"
2778 /* 13936 */ "OpExtInst\000"
2779 /* 13946 */ "OpGroupNonUniformBroadcastFirst\000"
2780 /* 13978 */ "OpGroupNonUniformFMax\000"
2781 /* 14000 */ "OpGroupFMax\000"
2782 /* 14012 */ "OpAtomicSMax\000"
2783 /* 14025 */ "OpGroupNonUniformSMax\000"
2784 /* 14047 */ "OpGroupSMax\000"
2785 /* 14059 */ "OpAtomicUMax\000"
2786 /* 14072 */ "OpGroupNonUniformUMax\000"
2787 /* 14094 */ "OpGroupUMax\000"
2788 /* 14106 */ "OpDPdx\000"
2789 /* 14113 */ "OpEmitStreamVertex\000"
2790 /* 14132 */ "OpEmitVertex\000"
2791 /* 14145 */ "OpTypeMatrix\000"
2792 /* 14158 */ "OpVectorTimesMatrix\000"
2793 /* 14178 */ "OpMatrixTimesMatrix\000"
2794 /* 14198 */ "OpTypeRuntimeArray\000"
2795 /* 14217 */ "OpTypeArray\000"
2796 /* 14229 */ "OpDPdy\000"
2797 /* 14236 */ "OpGroupNonUniformAny\000"
2798 /* 14257 */ "OpAny\000"
2799 /* 14263 */ "OpGroupAny\000"
2800 /* 14274 */ "OpGroupAsyncCopy\000"
2801 /* 14291 */ "OpCopyMemory\000"
2802 /* 14304 */ "OpCapability\000"
2803};
2804#ifdef __GNUC__
2805#pragma GCC diagnostic pop
2806#endif
2807
2808extern const unsigned SPIRVInstrNameIndices[] = {
2809 2816U, 4718U, 5575U, 5172U, 2901U, 2882U, 2910U, 4546U,
2810 2600U, 2615U, 2526U, 2513U, 2642U, 6745U, 2389U, 7762U,
2811 2539U, 2812U, 2891U, 2116U, 8670U, 2858U, 2238U, 7666U,
2812 1943U, 2067U, 2104U, 5304U, 4534U, 7576U, 2050U, 5510U,
2813 2735U, 7565U, 2288U, 5498U, 5485U, 5636U, 7424U, 7447U,
2814 4466U, 4513U, 4486U, 2927U, 2380U, 5601U, 5258U, 2277U,
2815 8675U, 6382U, 5456U, 2437U, 7792U, 7822U, 5015U, 1856U,
2816 1555U, 4657U, 8028U, 8035U, 4684U, 4691U, 4698U, 4708U,
2817 1921U, 6591U, 6554U, 6642U, 7923U, 6426U, 4455U, 6414U,
2818 4444U, 2524U, 2814U, 8593U, 2399U, 2414U, 4551U, 7392U,
2819 6649U, 7703U, 6666U, 6477U, 1625U, 6728U, 7587U, 6618U,
2820 7735U, 2480U, 5612U, 2024U, 1599U, 2006U, 7625U, 7606U,
2821 4993U, 5661U, 5680U, 1757U, 1701U, 1731U, 1670U, 1742U,
2822 1682U, 1712U, 2359U, 2313U, 2343U, 6775U, 2656U, 2673U,
2823 1872U, 1561U, 1927U, 1888U, 6596U, 6560U, 8577U, 5141U,
2824 8560U, 5124U, 1823U, 1538U, 8495U, 5059U, 4813U, 4760U,
2825 4934U, 4872U, 5366U, 5344U, 1965U, 7345U, 2096U, 2752U,
2826 1956U, 7411U, 7681U, 1577U, 6823U, 7542U, 6850U, 7806U,
2827 1617U, 6888U, 7930U, 7945U, 7531U, 7519U, 7656U, 2727U,
2828 7785U, 2629U, 7815U, 4430U, 6366U, 6352U, 4423U, 6359U,
2829 6611U, 4567U, 5435U, 5414U, 5442U, 5449U, 7402U, 5250U,
2830 2137U, 5234U, 2088U, 5242U, 2129U, 5226U, 2080U, 5288U,
2831 5280U, 2780U, 2772U, 7263U, 7253U, 7243U, 7233U, 7283U,
2832 7273U, 8621U, 8631U, 7293U, 7306U, 8641U, 8651U, 7319U,
2833 7332U, 1781U, 1517U, 4591U, 59U, 1663U, 8007U, 4663U,
2834 2505U, 8471U, 2838U, 5554U, 35U, 9U, 2720U, 18U,
2835 0U, 5529U, 5561U, 2593U, 7777U, 1589U, 2820U, 2829U,
2836 5396U, 5405U, 7366U, 7379U, 6629U, 5030U, 6762U, 2489U,
2837 4958U, 4968U, 2186U, 2201U, 4749U, 4802U, 4858U, 4920U,
2838 8042U, 8068U, 8054U, 2145U, 2173U, 2158U, 2690U, 2705U,
2839 1862U, 2872U, 5093U, 8529U, 5117U, 8553U, 6636U, 1997U,
2840 1987U, 5570U, 7471U, 2216U, 6458U, 6438U, 7499U, 7478U,
2841 6492U, 6523U, 6509U, 6805U, 8704U, 5207U, 8697U, 5188U,
2842 6681U, 5477U, 5388U, 2367U, 4633U, 2763U, 6373U, 4436U,
2843 6696U, 5165U, 6703U, 4986U, 6688U, 5157U, 4978U, 26U,
2844 2804U, 2796U, 2788U, 7712U, 6405U, 7598U, 7643U, 7745U,
2845 5588U, 2225U, 1646U, 2458U, 2328U, 1809U, 1524U, 4619U,
2846 8014U, 4670U, 65U, 7720U, 5538U, 5421U, 6713U, 5700U,
2847 5716U, 8661U, 2261U, 2470U, 7438U, 5296U, 2245U, 5337U,
2848 5313U, 5325U, 1788U, 4598U, 1764U, 4574U, 8478U, 5042U,
2849 4781U, 4728U, 4896U, 4834U, 1840U, 4641U, 1905U, 6576U,
2850 6538U, 8512U, 5076U, 8536U, 5100U, 8607U, 8614U, 2301U,
2851 10465U, 6287U, 11937U, 3858U, 3836U, 3881U, 11568U, 14257U,
2852 1044U, 674U, 856U, 598U, 189U, 829U, 569U, 449U,
2853 1376U, 1163U, 1197U, 1257U, 1137U, 775U, 1403U, 321U,
2854 106U, 217U, 1018U, 134U, 244U, 373U, 1229U, 269U,
2855 398U, 78U, 926U, 162U, 543U, 803U, 1429U, 294U,
2856 346U, 1284U, 973U, 900U, 1108U, 744U, 646U, 1330U,
2857 423U, 7870U, 11089U, 3907U, 4004U, 4280U, 5916U, 9102U,
2858 10080U, 11109U, 10063U, 7854U, 7907U, 7891U, 12332U, 13346U,
2859 8938U, 13462U, 13481U, 8711U, 8884U, 12255U, 14012U, 11843U,
2860 10478U, 14059U, 11890U, 12680U, 13637U, 13798U, 13170U, 13189U,
2861 10589U, 13926U, 6987U, 8245U, 4015U, 7141U, 8379U, 7154U,
2862 8392U, 11030U, 11162U, 10048U, 14304U, 12136U, 10342U, 10424U,
2863 13325U, 3363U, 13208U, 13815U, 10698U, 3302U, 2581U, 10520U,
2864 4171U, 2846U, 11607U, 12571U, 10794U, 12524U, 3744U, 4297U,
2865 2989U, 2967U, 7110U, 7960U, 3473U, 3438U, 4141U, 7991U,
2866 2553U, 2567U, 12809U, 3223U, 3398U, 5965U, 3150U, 5742U,
2867 5769U, 3803U, 3186U, 5861U, 11137U, 14291U, 9073U, 13261U,
2868 13574U, 4249U, 14106U, 10563U, 10274U, 14229U, 10576U, 10285U,
2869 10622U, 8806U, 10981U, 12045U, 13702U, 14113U, 14132U, 10809U,
2870 10824U, 11531U, 13592U, 9960U, 8788U, 6275U, 13936U, 13866U,
2871 12033U, 6957U, 8215U, 13833U, 7168U, 8406U, 9937U, 7050U,
2872 8319U, 10602U, 8267U, 11191U, 11715U, 11298U, 11777U, 11380U,
2873 11445U, 7080U, 8349U, 6903U, 8161U, 11203U, 11733U, 11321U,
2874 11792U, 11400U, 11460U, 1071U, 703U, 1001U, 526U, 954U,
2875 1357U, 883U, 1088U, 722U, 627U, 1312U, 5733U, 5932U,
2876 12087U, 11585U, 9183U, 12605U, 3922U, 11080U, 10548U, 10261U,
2877 12825U, 13382U, 12844U, 10730U, 10845U, 13605U, 10199U, 10879U,
2878 13040U, 13020U, 11574U, 14263U, 14274U, 5798U, 6169U, 6233U,
2879 13909U, 10359U, 10442U, 8926U, 14000U, 11831U, 6009U, 8973U,
2880 6024U, 5819U, 6189U, 6254U, 11547U, 11232U, 14236U, 13758U,
2881 13648U, 13227U, 1455U, 1486U, 9114U, 12266U, 12720U, 13882U,
2882 13946U, 13274U, 8904U, 13978U, 11809U, 11633U, 8951U, 11655U,
2883 13727U, 9142U, 12293U, 12748U, 12208U, 5889U, 14025U, 11856U,
2884 10158U, 12107U, 12181U, 12692U, 14072U, 11903U, 12933U, 12989U,
2885 14047U, 11878U, 14094U, 11925U, 13060U, 7220U, 8458U, 6979U,
2886 8237U, 11182U, 7072U, 8341U, 11433U, 7206U, 8444U, 6925U,
2887 8183U, 10022U, 12442U, 11039U, 12408U, 13139U, 12889U, 9921U,
2888 12390U, 12869U, 10904U, 9389U, 8854U, 9721U, 9465U, 9665U,
2889 8110U, 9409U, 9785U, 9529U, 9857U, 9601U, 12460U, 11052U,
2890 12422U, 8866U, 9750U, 9494U, 9690U, 9434U, 9818U, 9562U,
2891 9886U, 9630U, 13434U, 12660U, 10661U, 11993U, 11968U, 10650U,
2892 10973U, 11677U, 11151U, 13500U, 8819U, 11600U, 11509U, 12589U,
2893 13782U, 12240U, 10305U, 8897U, 9170U, 11217U, 13708U, 11477U,
2894 12320U, 3949U, 10121U, 4121U, 4202U, 14178U, 12370U, 12789U,
2895 10633U, 10998U, 10248U, 12541U, 11517U, 12503U, 9037U, 10241U,
2896 10921U, 10296U, 12234U, 13721U, 9015U, 13297U, 11103U, 6157U,
2897 3101U, 3524U, 11951U, 4090U, 8769U, 10963U, 11422U, 11495U,
2898 43U, 5994U, 10331U, 475U, 13545U, 12908U, 12963U, 10312U,
2899 10392U, 4384U, 13560U, 12098U, 10748U, 2947U, 13844U, 7190U,
2900 8428U, 13680U, 13099U, 11685U, 11258U, 11753U, 11346U, 9944U,
2901 8985U, 10612U, 7102U, 8371U, 13687U, 13112U, 9995U, 7974U,
2902 7124U, 4405U, 9197U, 9293U, 9229U, 9325U, 9261U, 9357U,
2903 9213U, 9309U, 9245U, 9341U, 9277U, 9373U, 10104U, 13078U,
2904 7009U, 8278U, 6933U, 8191U, 7029U, 8298U, 13369U, 10946U,
2905 9951U, 9055U, 12015U, 13419U, 10674U, 3264U, 10500U, 12164U,
2906 10775U, 10492U, 6965U, 8223U, 7176U, 8414U, 7058U, 8327U,
2907 7088U, 8357U, 6911U, 8169U, 11021U, 3123U, 3968U, 3575U,
2908 3772U, 3547U, 3076U, 3718U, 3046U, 3687U, 3011U, 3651U,
2909 3611U, 4038U, 3501U, 4065U, 4223U, 11071U, 10536U, 8080U,
2910 14217U, 11622U, 6298U, 8135U, 13515U, 13533U, 13158U, 12625U,
2911 12072U, 10010U, 13409U, 14145U, 12484U, 10762U, 10381U, 10030U,
2912 12646U, 10718U, 8838U, 14198U, 9976U, 12557U, 13312U, 3336U,
2913 6209U, 12776U, 7836U, 9091U, 13855U, 7198U, 8436U, 13695U,
2914 13126U, 11700U, 11278U, 11765U, 11363U, 7001U, 8259U, 9000U,
2915 10955U, 9025U, 10133U, 6039U, 6325U, 6125U, 6090U, 5944U,
2916 6063U, 5840U, 4323U, 10147U, 4357U, 8724U, 8747U, 10183U,
2917 14158U, 12350U, 10412U, 500U,
2918};
2919
2920static inline void InitSPIRVMCInstrInfo(MCInstrInfo *II) {
2921 II->InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 868, nullptr, 0);
2922}
2923
2924
2925} // namespace llvm
2926
2927#endif // GET_INSTRINFO_MC_DESC
2928
2929#ifdef GET_INSTRINFO_HEADER
2930#undef GET_INSTRINFO_HEADER
2931
2932namespace llvm {
2933
2934struct SPIRVGenInstrInfo : public TargetInstrInfo {
2935 explicit SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2936 ~SPIRVGenInstrInfo() override = default;
2937};
2938
2939} // namespace llvm
2940
2941namespace llvm::SPIRV {
2942
2943
2944} // namespace llvm::SPIRV
2945
2946#endif // GET_INSTRINFO_HEADER
2947
2948#ifdef GET_INSTRINFO_HELPER_DECLS
2949#undef GET_INSTRINFO_HELPER_DECLS
2950
2951
2952#endif // GET_INSTRINFO_HELPER_DECLS
2953
2954#ifdef GET_INSTRINFO_HELPERS
2955#undef GET_INSTRINFO_HELPERS
2956
2957
2958#endif // GET_INSTRINFO_HELPERS
2959
2960#ifdef GET_INSTRINFO_CTOR_DTOR
2961#undef GET_INSTRINFO_CTOR_DTOR
2962
2963namespace llvm {
2964
2965extern const SPIRVInstrTable SPIRVDescs;
2966extern const unsigned SPIRVInstrNameIndices[];
2967extern const char SPIRVInstrNameData[];
2968SPIRVGenInstrInfo::SPIRVGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2969 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2970 InitMCInstrInfo(SPIRVDescs.Insts, SPIRVInstrNameIndices, SPIRVInstrNameData, nullptr, nullptr, 868);
2971}
2972
2973} // namespace llvm
2974
2975#endif // GET_INSTRINFO_CTOR_DTOR
2976
2977#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2978#undef GET_INSTRINFO_MC_HELPER_DECLS
2979
2980namespace llvm {
2981
2982class MCInst;
2983class FeatureBitset;
2984
2985namespace SPIRV_MC {
2986
2987void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2988
2989} // namespace SPIRV_MC
2990
2991} // namespace llvm
2992
2993#endif // GET_INSTRINFO_MC_HELPER_DECLS
2994
2995#ifdef GET_INSTRINFO_MC_HELPERS
2996#undef GET_INSTRINFO_MC_HELPERS
2997
2998namespace llvm::SPIRV_MC {
2999
3000
3001} // namespace llvm::SPIRV_MC
3002
3003#endif // GET_INSTRINFO_MC_HELPERS
3004
3005#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3006 defined(GET_AVAILABLE_OPCODE_CHECKER)
3007#define GET_COMPUTE_FEATURES
3008#endif
3009#ifdef GET_COMPUTE_FEATURES
3010#undef GET_COMPUTE_FEATURES
3011
3012namespace llvm::SPIRV_MC {
3013
3014// Bits for subtarget features that participate in instruction matching.
3015enum SubtargetFeatureBits : uint8_t {
3016};
3017
3018inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3019 FeatureBitset Features;
3020 return Features;
3021}
3022
3023inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3024 enum : uint8_t {
3025 CEFBS_None,
3026 };
3027
3028 static constexpr FeatureBitset FeatureBitsets[] = {
3029 {}, // CEFBS_None
3030 };
3031 static constexpr uint8_t RequiredFeaturesRefs[] = {
3032 CEFBS_None, // PHI
3033 CEFBS_None, // INLINEASM
3034 CEFBS_None, // INLINEASM_BR
3035 CEFBS_None, // CFI_INSTRUCTION
3036 CEFBS_None, // EH_LABEL
3037 CEFBS_None, // GC_LABEL
3038 CEFBS_None, // ANNOTATION_LABEL
3039 CEFBS_None, // KILL
3040 CEFBS_None, // EXTRACT_SUBREG
3041 CEFBS_None, // INSERT_SUBREG
3042 CEFBS_None, // IMPLICIT_DEF
3043 CEFBS_None, // INIT_UNDEF
3044 CEFBS_None, // SUBREG_TO_REG
3045 CEFBS_None, // COPY_TO_REGCLASS
3046 CEFBS_None, // DBG_VALUE
3047 CEFBS_None, // DBG_VALUE_LIST
3048 CEFBS_None, // DBG_INSTR_REF
3049 CEFBS_None, // DBG_PHI
3050 CEFBS_None, // DBG_LABEL
3051 CEFBS_None, // REG_SEQUENCE
3052 CEFBS_None, // COPY
3053 CEFBS_None, // COPY_LANEMASK
3054 CEFBS_None, // BUNDLE
3055 CEFBS_None, // LIFETIME_START
3056 CEFBS_None, // LIFETIME_END
3057 CEFBS_None, // PSEUDO_PROBE
3058 CEFBS_None, // ARITH_FENCE
3059 CEFBS_None, // STACKMAP
3060 CEFBS_None, // FENTRY_CALL
3061 CEFBS_None, // PATCHPOINT
3062 CEFBS_None, // LOAD_STACK_GUARD
3063 CEFBS_None, // PREALLOCATED_SETUP
3064 CEFBS_None, // PREALLOCATED_ARG
3065 CEFBS_None, // STATEPOINT
3066 CEFBS_None, // LOCAL_ESCAPE
3067 CEFBS_None, // FAULTING_OP
3068 CEFBS_None, // PATCHABLE_OP
3069 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
3070 CEFBS_None, // PATCHABLE_RET
3071 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
3072 CEFBS_None, // PATCHABLE_TAIL_CALL
3073 CEFBS_None, // PATCHABLE_EVENT_CALL
3074 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
3075 CEFBS_None, // ICALL_BRANCH_FUNNEL
3076 CEFBS_None, // FAKE_USE
3077 CEFBS_None, // MEMBARRIER
3078 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
3079 CEFBS_None, // RELOC_NONE
3080 CEFBS_None, // CONVERGENCECTRL_ENTRY
3081 CEFBS_None, // CONVERGENCECTRL_ANCHOR
3082 CEFBS_None, // CONVERGENCECTRL_LOOP
3083 CEFBS_None, // CONVERGENCECTRL_GLUE
3084 CEFBS_None, // G_ASSERT_SEXT
3085 CEFBS_None, // G_ASSERT_ZEXT
3086 CEFBS_None, // G_ASSERT_ALIGN
3087 CEFBS_None, // G_ADD
3088 CEFBS_None, // G_SUB
3089 CEFBS_None, // G_MUL
3090 CEFBS_None, // G_SDIV
3091 CEFBS_None, // G_UDIV
3092 CEFBS_None, // G_SREM
3093 CEFBS_None, // G_UREM
3094 CEFBS_None, // G_SDIVREM
3095 CEFBS_None, // G_UDIVREM
3096 CEFBS_None, // G_AND
3097 CEFBS_None, // G_OR
3098 CEFBS_None, // G_XOR
3099 CEFBS_None, // G_ABDS
3100 CEFBS_None, // G_ABDU
3101 CEFBS_None, // G_UAVGFLOOR
3102 CEFBS_None, // G_UAVGCEIL
3103 CEFBS_None, // G_SAVGFLOOR
3104 CEFBS_None, // G_SAVGCEIL
3105 CEFBS_None, // G_IMPLICIT_DEF
3106 CEFBS_None, // G_PHI
3107 CEFBS_None, // G_FRAME_INDEX
3108 CEFBS_None, // G_GLOBAL_VALUE
3109 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3110 CEFBS_None, // G_CONSTANT_POOL
3111 CEFBS_None, // G_EXTRACT
3112 CEFBS_None, // G_UNMERGE_VALUES
3113 CEFBS_None, // G_INSERT
3114 CEFBS_None, // G_MERGE_VALUES
3115 CEFBS_None, // G_BUILD_VECTOR
3116 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3117 CEFBS_None, // G_CONCAT_VECTORS
3118 CEFBS_None, // G_PTRTOINT
3119 CEFBS_None, // G_INTTOPTR
3120 CEFBS_None, // G_BITCAST
3121 CEFBS_None, // G_FREEZE
3122 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3123 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3124 CEFBS_None, // G_INTRINSIC_TRUNC
3125 CEFBS_None, // G_INTRINSIC_ROUND
3126 CEFBS_None, // G_INTRINSIC_LRINT
3127 CEFBS_None, // G_INTRINSIC_LLRINT
3128 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3129 CEFBS_None, // G_READCYCLECOUNTER
3130 CEFBS_None, // G_READSTEADYCOUNTER
3131 CEFBS_None, // G_LOAD
3132 CEFBS_None, // G_SEXTLOAD
3133 CEFBS_None, // G_ZEXTLOAD
3134 CEFBS_None, // G_FPEXTLOAD
3135 CEFBS_None, // G_INDEXED_LOAD
3136 CEFBS_None, // G_INDEXED_SEXTLOAD
3137 CEFBS_None, // G_INDEXED_ZEXTLOAD
3138 CEFBS_None, // G_STORE
3139 CEFBS_None, // G_FPTRUNCSTORE
3140 CEFBS_None, // G_INDEXED_STORE
3141 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3142 CEFBS_None, // G_ATOMIC_CMPXCHG
3143 CEFBS_None, // G_ATOMICRMW_XCHG
3144 CEFBS_None, // G_ATOMICRMW_ADD
3145 CEFBS_None, // G_ATOMICRMW_SUB
3146 CEFBS_None, // G_ATOMICRMW_AND
3147 CEFBS_None, // G_ATOMICRMW_NAND
3148 CEFBS_None, // G_ATOMICRMW_OR
3149 CEFBS_None, // G_ATOMICRMW_XOR
3150 CEFBS_None, // G_ATOMICRMW_MAX
3151 CEFBS_None, // G_ATOMICRMW_MIN
3152 CEFBS_None, // G_ATOMICRMW_UMAX
3153 CEFBS_None, // G_ATOMICRMW_UMIN
3154 CEFBS_None, // G_ATOMICRMW_FADD
3155 CEFBS_None, // G_ATOMICRMW_FSUB
3156 CEFBS_None, // G_ATOMICRMW_FMAX
3157 CEFBS_None, // G_ATOMICRMW_FMIN
3158 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3159 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3160 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
3161 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
3162 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3163 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3164 CEFBS_None, // G_ATOMICRMW_USUB_COND
3165 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3166 CEFBS_None, // G_FENCE
3167 CEFBS_None, // G_PREFETCH
3168 CEFBS_None, // G_BRCOND
3169 CEFBS_None, // G_BRINDIRECT
3170 CEFBS_None, // G_INVOKE_REGION_START
3171 CEFBS_None, // G_INTRINSIC
3172 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3173 CEFBS_None, // G_INTRINSIC_CONVERGENT
3174 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3175 CEFBS_None, // G_ANYEXT
3176 CEFBS_None, // G_TRUNC
3177 CEFBS_None, // G_TRUNC_SSAT_S
3178 CEFBS_None, // G_TRUNC_SSAT_U
3179 CEFBS_None, // G_TRUNC_USAT_U
3180 CEFBS_None, // G_CONSTANT
3181 CEFBS_None, // G_FCONSTANT
3182 CEFBS_None, // G_VASTART
3183 CEFBS_None, // G_VAARG
3184 CEFBS_None, // G_SEXT
3185 CEFBS_None, // G_SEXT_INREG
3186 CEFBS_None, // G_ZEXT
3187 CEFBS_None, // G_SHL
3188 CEFBS_None, // G_LSHR
3189 CEFBS_None, // G_ASHR
3190 CEFBS_None, // G_FSHL
3191 CEFBS_None, // G_FSHR
3192 CEFBS_None, // G_ROTR
3193 CEFBS_None, // G_ROTL
3194 CEFBS_None, // G_ICMP
3195 CEFBS_None, // G_FCMP
3196 CEFBS_None, // G_SCMP
3197 CEFBS_None, // G_UCMP
3198 CEFBS_None, // G_SELECT
3199 CEFBS_None, // G_UADDO
3200 CEFBS_None, // G_UADDE
3201 CEFBS_None, // G_USUBO
3202 CEFBS_None, // G_USUBE
3203 CEFBS_None, // G_SADDO
3204 CEFBS_None, // G_SADDE
3205 CEFBS_None, // G_SSUBO
3206 CEFBS_None, // G_SSUBE
3207 CEFBS_None, // G_UMULO
3208 CEFBS_None, // G_SMULO
3209 CEFBS_None, // G_UMULH
3210 CEFBS_None, // G_SMULH
3211 CEFBS_None, // G_UADDSAT
3212 CEFBS_None, // G_SADDSAT
3213 CEFBS_None, // G_USUBSAT
3214 CEFBS_None, // G_SSUBSAT
3215 CEFBS_None, // G_USHLSAT
3216 CEFBS_None, // G_SSHLSAT
3217 CEFBS_None, // G_SMULFIX
3218 CEFBS_None, // G_UMULFIX
3219 CEFBS_None, // G_SMULFIXSAT
3220 CEFBS_None, // G_UMULFIXSAT
3221 CEFBS_None, // G_SDIVFIX
3222 CEFBS_None, // G_UDIVFIX
3223 CEFBS_None, // G_SDIVFIXSAT
3224 CEFBS_None, // G_UDIVFIXSAT
3225 CEFBS_None, // G_FADD
3226 CEFBS_None, // G_FSUB
3227 CEFBS_None, // G_FMUL
3228 CEFBS_None, // G_FMA
3229 CEFBS_None, // G_FMAD
3230 CEFBS_None, // G_FDIV
3231 CEFBS_None, // G_FREM
3232 CEFBS_None, // G_FMODF
3233 CEFBS_None, // G_FPOW
3234 CEFBS_None, // G_FPOWI
3235 CEFBS_None, // G_FEXP
3236 CEFBS_None, // G_FEXP2
3237 CEFBS_None, // G_FEXP10
3238 CEFBS_None, // G_FLOG
3239 CEFBS_None, // G_FLOG2
3240 CEFBS_None, // G_FLOG10
3241 CEFBS_None, // G_FLDEXP
3242 CEFBS_None, // G_FFREXP
3243 CEFBS_None, // G_FNEG
3244 CEFBS_None, // G_FPEXT
3245 CEFBS_None, // G_FPTRUNC
3246 CEFBS_None, // G_FPTOSI
3247 CEFBS_None, // G_FPTOUI
3248 CEFBS_None, // G_SITOFP
3249 CEFBS_None, // G_UITOFP
3250 CEFBS_None, // G_FPTOSI_SAT
3251 CEFBS_None, // G_FPTOUI_SAT
3252 CEFBS_None, // G_FABS
3253 CEFBS_None, // G_FCOPYSIGN
3254 CEFBS_None, // G_IS_FPCLASS
3255 CEFBS_None, // G_FCANONICALIZE
3256 CEFBS_None, // G_FMINNUM
3257 CEFBS_None, // G_FMAXNUM
3258 CEFBS_None, // G_FMINNUM_IEEE
3259 CEFBS_None, // G_FMAXNUM_IEEE
3260 CEFBS_None, // G_FMINIMUM
3261 CEFBS_None, // G_FMAXIMUM
3262 CEFBS_None, // G_FMINIMUMNUM
3263 CEFBS_None, // G_FMAXIMUMNUM
3264 CEFBS_None, // G_GET_FPENV
3265 CEFBS_None, // G_SET_FPENV
3266 CEFBS_None, // G_RESET_FPENV
3267 CEFBS_None, // G_GET_FPMODE
3268 CEFBS_None, // G_SET_FPMODE
3269 CEFBS_None, // G_RESET_FPMODE
3270 CEFBS_None, // G_GET_ROUNDING
3271 CEFBS_None, // G_SET_ROUNDING
3272 CEFBS_None, // G_PTR_ADD
3273 CEFBS_None, // G_PTRMASK
3274 CEFBS_None, // G_SMIN
3275 CEFBS_None, // G_SMAX
3276 CEFBS_None, // G_UMIN
3277 CEFBS_None, // G_UMAX
3278 CEFBS_None, // G_ABS
3279 CEFBS_None, // G_LROUND
3280 CEFBS_None, // G_LLROUND
3281 CEFBS_None, // G_BR
3282 CEFBS_None, // G_BRJT
3283 CEFBS_None, // G_VSCALE
3284 CEFBS_None, // G_INSERT_SUBVECTOR
3285 CEFBS_None, // G_EXTRACT_SUBVECTOR
3286 CEFBS_None, // G_INSERT_VECTOR_ELT
3287 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3288 CEFBS_None, // G_SHUFFLE_VECTOR
3289 CEFBS_None, // G_SPLAT_VECTOR
3290 CEFBS_None, // G_STEP_VECTOR
3291 CEFBS_None, // G_VECTOR_COMPRESS
3292 CEFBS_None, // G_CTTZ
3293 CEFBS_None, // G_CTTZ_ZERO_POISON
3294 CEFBS_None, // G_CTLZ
3295 CEFBS_None, // G_CTLZ_ZERO_POISON
3296 CEFBS_None, // G_CTLS
3297 CEFBS_None, // G_CTPOP
3298 CEFBS_None, // G_BSWAP
3299 CEFBS_None, // G_BITREVERSE
3300 CEFBS_None, // G_CLMUL
3301 CEFBS_None, // G_CLMULH
3302 CEFBS_None, // G_CLMULR
3303 CEFBS_None, // G_FCEIL
3304 CEFBS_None, // G_FCOS
3305 CEFBS_None, // G_FSIN
3306 CEFBS_None, // G_FSINCOS
3307 CEFBS_None, // G_FTAN
3308 CEFBS_None, // G_FACOS
3309 CEFBS_None, // G_FASIN
3310 CEFBS_None, // G_FATAN
3311 CEFBS_None, // G_FATAN2
3312 CEFBS_None, // G_FCOSH
3313 CEFBS_None, // G_FSINH
3314 CEFBS_None, // G_FTANH
3315 CEFBS_None, // G_FSQRT
3316 CEFBS_None, // G_FFLOOR
3317 CEFBS_None, // G_FRINT
3318 CEFBS_None, // G_FNEARBYINT
3319 CEFBS_None, // G_ADDRSPACE_CAST
3320 CEFBS_None, // G_BLOCK_ADDR
3321 CEFBS_None, // G_JUMP_TABLE
3322 CEFBS_None, // G_DYN_STACKALLOC
3323 CEFBS_None, // G_STACKSAVE
3324 CEFBS_None, // G_STACKRESTORE
3325 CEFBS_None, // G_STRICT_FADD
3326 CEFBS_None, // G_STRICT_FSUB
3327 CEFBS_None, // G_STRICT_FMUL
3328 CEFBS_None, // G_STRICT_FDIV
3329 CEFBS_None, // G_STRICT_FREM
3330 CEFBS_None, // G_STRICT_FMA
3331 CEFBS_None, // G_STRICT_FSQRT
3332 CEFBS_None, // G_STRICT_FLDEXP
3333 CEFBS_None, // G_STRICT_FCMP
3334 CEFBS_None, // G_STRICT_FCMPS
3335 CEFBS_None, // G_READ_REGISTER
3336 CEFBS_None, // G_WRITE_REGISTER
3337 CEFBS_None, // G_MEMCPY
3338 CEFBS_None, // G_MEMCPY_INLINE
3339 CEFBS_None, // G_MEMMOVE
3340 CEFBS_None, // G_MEMSET
3341 CEFBS_None, // G_BZERO
3342 CEFBS_None, // G_MEMSET_INLINE
3343 CEFBS_None, // G_TRAP
3344 CEFBS_None, // G_DEBUGTRAP
3345 CEFBS_None, // G_UBSANTRAP
3346 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3347 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3348 CEFBS_None, // G_VECREDUCE_FADD
3349 CEFBS_None, // G_VECREDUCE_FMUL
3350 CEFBS_None, // G_VECREDUCE_FMAX
3351 CEFBS_None, // G_VECREDUCE_FMIN
3352 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3353 CEFBS_None, // G_VECREDUCE_FMINIMUM
3354 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
3355 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
3356 CEFBS_None, // G_VECREDUCE_ADD
3357 CEFBS_None, // G_VECREDUCE_MUL
3358 CEFBS_None, // G_VECREDUCE_AND
3359 CEFBS_None, // G_VECREDUCE_OR
3360 CEFBS_None, // G_VECREDUCE_XOR
3361 CEFBS_None, // G_VECREDUCE_SMAX
3362 CEFBS_None, // G_VECREDUCE_SMIN
3363 CEFBS_None, // G_VECREDUCE_UMAX
3364 CEFBS_None, // G_VECREDUCE_UMIN
3365 CEFBS_None, // G_SBFX
3366 CEFBS_None, // G_UBFX
3367 CEFBS_None, // ASSIGN_TYPE
3368 CEFBS_None, // UNKNOWN_type
3369 CEFBS_None, // OpAbortKHR
3370 CEFBS_None, // OpAccessChain
3371 CEFBS_None, // OpAliasDomainDeclINTEL
3372 CEFBS_None, // OpAliasScopeDeclINTEL
3373 CEFBS_None, // OpAliasScopeListDeclINTEL
3374 CEFBS_None, // OpAll
3375 CEFBS_None, // OpAny
3376 CEFBS_None, // OpArbitraryFloatACosALTERA
3377 CEFBS_None, // OpArbitraryFloatACosPiALTERA
3378 CEFBS_None, // OpArbitraryFloatASinALTERA
3379 CEFBS_None, // OpArbitraryFloatASinPiALTERA
3380 CEFBS_None, // OpArbitraryFloatATan2ALTERA
3381 CEFBS_None, // OpArbitraryFloatATanALTERA
3382 CEFBS_None, // OpArbitraryFloatATanPiALTERA
3383 CEFBS_None, // OpArbitraryFloatAddALTERA
3384 CEFBS_None, // OpArbitraryFloatCastALTERA
3385 CEFBS_None, // OpArbitraryFloatCastFromIntALTERA
3386 CEFBS_None, // OpArbitraryFloatCastToIntALTERA
3387 CEFBS_None, // OpArbitraryFloatCbrtALTERA
3388 CEFBS_None, // OpArbitraryFloatCosALTERA
3389 CEFBS_None, // OpArbitraryFloatCosPiALTERA
3390 CEFBS_None, // OpArbitraryFloatDivALTERA
3391 CEFBS_None, // OpArbitraryFloatEQALTERA
3392 CEFBS_None, // OpArbitraryFloatExp10ALTERA
3393 CEFBS_None, // OpArbitraryFloatExp2ALTERA
3394 CEFBS_None, // OpArbitraryFloatExpALTERA
3395 CEFBS_None, // OpArbitraryFloatExpm1ALTERA
3396 CEFBS_None, // OpArbitraryFloatGEALTERA
3397 CEFBS_None, // OpArbitraryFloatGTALTERA
3398 CEFBS_None, // OpArbitraryFloatHypotALTERA
3399 CEFBS_None, // OpArbitraryFloatLEALTERA
3400 CEFBS_None, // OpArbitraryFloatLTALTERA
3401 CEFBS_None, // OpArbitraryFloatLog10ALTERA
3402 CEFBS_None, // OpArbitraryFloatLog1pALTERA
3403 CEFBS_None, // OpArbitraryFloatLog2ALTERA
3404 CEFBS_None, // OpArbitraryFloatLogALTERA
3405 CEFBS_None, // OpArbitraryFloatMulALTERA
3406 CEFBS_None, // OpArbitraryFloatPowALTERA
3407 CEFBS_None, // OpArbitraryFloatPowNALTERA
3408 CEFBS_None, // OpArbitraryFloatPowRALTERA
3409 CEFBS_None, // OpArbitraryFloatRSqrtALTERA
3410 CEFBS_None, // OpArbitraryFloatRecipALTERA
3411 CEFBS_None, // OpArbitraryFloatSinALTERA
3412 CEFBS_None, // OpArbitraryFloatSinCosALTERA
3413 CEFBS_None, // OpArbitraryFloatSinCosPiALTERA
3414 CEFBS_None, // OpArbitraryFloatSinPiALTERA
3415 CEFBS_None, // OpArbitraryFloatSqrtALTERA
3416 CEFBS_None, // OpArbitraryFloatSubALTERA
3417 CEFBS_None, // OpArithmeticFenceEXT
3418 CEFBS_None, // OpArrayLength
3419 CEFBS_None, // OpAsmCallINTEL
3420 CEFBS_None, // OpAsmINTEL
3421 CEFBS_None, // OpAsmTargetINTEL
3422 CEFBS_None, // OpAssumeTrueKHR
3423 CEFBS_None, // OpAtomicAnd
3424 CEFBS_None, // OpAtomicCompareExchange
3425 CEFBS_None, // OpAtomicCompareExchangeWeak
3426 CEFBS_None, // OpAtomicExchange
3427 CEFBS_None, // OpAtomicFAddEXT
3428 CEFBS_None, // OpAtomicFMaxEXT
3429 CEFBS_None, // OpAtomicFMinEXT
3430 CEFBS_None, // OpAtomicFlagClear
3431 CEFBS_None, // OpAtomicFlagTestAndSet
3432 CEFBS_None, // OpAtomicIAdd
3433 CEFBS_None, // OpAtomicIDecrement
3434 CEFBS_None, // OpAtomicIIncrement
3435 CEFBS_None, // OpAtomicISub
3436 CEFBS_None, // OpAtomicLoad
3437 CEFBS_None, // OpAtomicOr
3438 CEFBS_None, // OpAtomicSMax
3439 CEFBS_None, // OpAtomicSMin
3440 CEFBS_None, // OpAtomicStore
3441 CEFBS_None, // OpAtomicUMax
3442 CEFBS_None, // OpAtomicUMin
3443 CEFBS_None, // OpAtomicXor
3444 CEFBS_None, // OpBitCount
3445 CEFBS_None, // OpBitFieldInsert
3446 CEFBS_None, // OpBitFieldSExtract
3447 CEFBS_None, // OpBitFieldUExtract
3448 CEFBS_None, // OpBitReverse
3449 CEFBS_None, // OpBitcast
3450 CEFBS_None, // OpBitwiseAndS
3451 CEFBS_None, // OpBitwiseAndV
3452 CEFBS_None, // OpBitwiseFunctionINTEL
3453 CEFBS_None, // OpBitwiseOrS
3454 CEFBS_None, // OpBitwiseOrV
3455 CEFBS_None, // OpBitwiseXorS
3456 CEFBS_None, // OpBitwiseXorV
3457 CEFBS_None, // OpBranch
3458 CEFBS_None, // OpBranchConditional
3459 CEFBS_None, // OpBuildNDRange
3460 CEFBS_None, // OpCapability
3461 CEFBS_None, // OpCaptureEventProfilingInfo
3462 CEFBS_None, // OpCommitReadPipe
3463 CEFBS_None, // OpCommitWritePipe
3464 CEFBS_None, // OpCompositeConstruct
3465 CEFBS_None, // OpCompositeConstructContinuedINTEL
3466 CEFBS_None, // OpCompositeExtract
3467 CEFBS_None, // OpCompositeInsert
3468 CEFBS_None, // OpConstantComposite
3469 CEFBS_None, // OpConstantCompositeContinuedINTEL
3470 CEFBS_None, // OpConstantF
3471 CEFBS_None, // OpConstantFalse
3472 CEFBS_None, // OpConstantFunctionPointerINTEL
3473 CEFBS_None, // OpConstantI
3474 CEFBS_None, // OpConstantNull
3475 CEFBS_None, // OpConstantSampler
3476 CEFBS_None, // OpConstantTrue
3477 CEFBS_None, // OpControlBarrier
3478 CEFBS_None, // OpControlBarrierArriveINTEL
3479 CEFBS_None, // OpControlBarrierWaitINTEL
3480 CEFBS_None, // OpConvertBF16ToFINTEL
3481 CEFBS_None, // OpConvertFToBF16INTEL
3482 CEFBS_None, // OpConvertFToS
3483 CEFBS_None, // OpConvertFToU
3484 CEFBS_None, // OpConvertHandleToImageINTEL
3485 CEFBS_None, // OpConvertHandleToSampledImageINTEL
3486 CEFBS_None, // OpConvertHandleToSamplerINTEL
3487 CEFBS_None, // OpConvertPtrToU
3488 CEFBS_None, // OpConvertSToF
3489 CEFBS_None, // OpConvertUToF
3490 CEFBS_None, // OpConvertUToPtr
3491 CEFBS_None, // OpCooperativeMatrixConstructCheckedINTEL
3492 CEFBS_None, // OpCooperativeMatrixGetElementCoordINTEL
3493 CEFBS_None, // OpCooperativeMatrixLengthKHR
3494 CEFBS_None, // OpCooperativeMatrixLoadCheckedINTEL
3495 CEFBS_None, // OpCooperativeMatrixLoadKHR
3496 CEFBS_None, // OpCooperativeMatrixMulAddKHR
3497 CEFBS_None, // OpCooperativeMatrixPrefetchINTEL
3498 CEFBS_None, // OpCooperativeMatrixStoreCheckedINTEL
3499 CEFBS_None, // OpCooperativeMatrixStoreKHR
3500 CEFBS_None, // OpCopyLogical
3501 CEFBS_None, // OpCopyMemory
3502 CEFBS_None, // OpCopyMemorySized
3503 CEFBS_None, // OpCopyObject
3504 CEFBS_None, // OpCreateUserEvent
3505 CEFBS_None, // OpCrossWorkgroupCastToPtrINTEL
3506 CEFBS_None, // OpDPdx
3507 CEFBS_None, // OpDPdxCoarse
3508 CEFBS_None, // OpDPdxFine
3509 CEFBS_None, // OpDPdy
3510 CEFBS_None, // OpDPdyCoarse
3511 CEFBS_None, // OpDPdyFine
3512 CEFBS_None, // OpDecorate
3513 CEFBS_None, // OpDecorateId
3514 CEFBS_None, // OpDecorateString
3515 CEFBS_None, // OpDemoteToHelperInvocation
3516 CEFBS_None, // OpDot
3517 CEFBS_None, // OpEmitStreamVertex
3518 CEFBS_None, // OpEmitVertex
3519 CEFBS_None, // OpEndPrimitive
3520 CEFBS_None, // OpEndStreamPrimitive
3521 CEFBS_None, // OpEnqueueKernel
3522 CEFBS_None, // OpEntryPoint
3523 CEFBS_None, // OpExecutionMode
3524 CEFBS_None, // OpExecutionModeId
3525 CEFBS_None, // OpExpectKHR
3526 CEFBS_None, // OpExtInst
3527 CEFBS_None, // OpExtInstImport
3528 CEFBS_None, // OpExtension
3529 CEFBS_None, // OpFAddS
3530 CEFBS_None, // OpFAddV
3531 CEFBS_None, // OpFConvert
3532 CEFBS_None, // OpFDivS
3533 CEFBS_None, // OpFDivV
3534 CEFBS_None, // OpFMod
3535 CEFBS_None, // OpFMulS
3536 CEFBS_None, // OpFMulV
3537 CEFBS_None, // OpFNegate
3538 CEFBS_None, // OpFNegateV
3539 CEFBS_None, // OpFOrdEqual
3540 CEFBS_None, // OpFOrdGreaterThan
3541 CEFBS_None, // OpFOrdGreaterThanEqual
3542 CEFBS_None, // OpFOrdLessThan
3543 CEFBS_None, // OpFOrdLessThanEqual
3544 CEFBS_None, // OpFOrdNotEqual
3545 CEFBS_None, // OpFRemS
3546 CEFBS_None, // OpFRemV
3547 CEFBS_None, // OpFSubS
3548 CEFBS_None, // OpFSubV
3549 CEFBS_None, // OpFUnordEqual
3550 CEFBS_None, // OpFUnordGreaterThan
3551 CEFBS_None, // OpFUnordGreaterThanEqual
3552 CEFBS_None, // OpFUnordLessThan
3553 CEFBS_None, // OpFUnordLessThanEqual
3554 CEFBS_None, // OpFUnordNotEqual
3555 CEFBS_None, // OpFixedCosALTERA
3556 CEFBS_None, // OpFixedCosPiALTERA
3557 CEFBS_None, // OpFixedExpALTERA
3558 CEFBS_None, // OpFixedLogALTERA
3559 CEFBS_None, // OpFixedRecipALTERA
3560 CEFBS_None, // OpFixedRsqrtALTERA
3561 CEFBS_None, // OpFixedSinALTERA
3562 CEFBS_None, // OpFixedSinCosALTERA
3563 CEFBS_None, // OpFixedSinCosPiALTERA
3564 CEFBS_None, // OpFixedSinPiALTERA
3565 CEFBS_None, // OpFixedSqrtALTERA
3566 CEFBS_None, // OpFmaKHR
3567 CEFBS_None, // OpFreezeKHR
3568 CEFBS_None, // OpFunction
3569 CEFBS_None, // OpFunctionCall
3570 CEFBS_None, // OpFunctionEnd
3571 CEFBS_None, // OpFunctionParameter
3572 CEFBS_None, // OpFunctionPointerCallINTEL
3573 CEFBS_None, // OpFwidth
3574 CEFBS_None, // OpFwidthCoarse
3575 CEFBS_None, // OpFwidthFine
3576 CEFBS_None, // OpGenericCastToPtr
3577 CEFBS_None, // OpGenericCastToPtrExplicit
3578 CEFBS_None, // OpGenericPtrMemSemantics
3579 CEFBS_None, // OpGetDefaultQueue
3580 CEFBS_None, // OpGetKernelNDrangeMaxSubGroupSize
3581 CEFBS_None, // OpGetKernelNDrangeSubGroupCount
3582 CEFBS_None, // OpGetKernelPreferredWorkGroupSizeMultiple
3583 CEFBS_None, // OpGetKernelWorkGroupSize
3584 CEFBS_None, // OpGetMaxPipePackets
3585 CEFBS_None, // OpGetNumPipePackets
3586 CEFBS_None, // OpGroupAll
3587 CEFBS_None, // OpGroupAny
3588 CEFBS_None, // OpGroupAsyncCopy
3589 CEFBS_None, // OpGroupBitwiseAndKHR
3590 CEFBS_None, // OpGroupBitwiseOrKHR
3591 CEFBS_None, // OpGroupBitwiseXorKHR
3592 CEFBS_None, // OpGroupBroadcast
3593 CEFBS_None, // OpGroupCommitReadPipe
3594 CEFBS_None, // OpGroupCommitWritePipe
3595 CEFBS_None, // OpGroupFAdd
3596 CEFBS_None, // OpGroupFMax
3597 CEFBS_None, // OpGroupFMin
3598 CEFBS_None, // OpGroupFMulKHR
3599 CEFBS_None, // OpGroupIAdd
3600 CEFBS_None, // OpGroupIMulKHR
3601 CEFBS_None, // OpGroupLogicalAndKHR
3602 CEFBS_None, // OpGroupLogicalOrKHR
3603 CEFBS_None, // OpGroupLogicalXorKHR
3604 CEFBS_None, // OpGroupNonUniformAll
3605 CEFBS_None, // OpGroupNonUniformAllEqual
3606 CEFBS_None, // OpGroupNonUniformAny
3607 CEFBS_None, // OpGroupNonUniformBallot
3608 CEFBS_None, // OpGroupNonUniformBallotBitCount
3609 CEFBS_None, // OpGroupNonUniformBallotBitExtract
3610 CEFBS_None, // OpGroupNonUniformBallotFindLSB
3611 CEFBS_None, // OpGroupNonUniformBallotFindMSB
3612 CEFBS_None, // OpGroupNonUniformBitwiseAnd
3613 CEFBS_None, // OpGroupNonUniformBitwiseOr
3614 CEFBS_None, // OpGroupNonUniformBitwiseXor
3615 CEFBS_None, // OpGroupNonUniformBroadcast
3616 CEFBS_None, // OpGroupNonUniformBroadcastFirst
3617 CEFBS_None, // OpGroupNonUniformElect
3618 CEFBS_None, // OpGroupNonUniformFAdd
3619 CEFBS_None, // OpGroupNonUniformFMax
3620 CEFBS_None, // OpGroupNonUniformFMin
3621 CEFBS_None, // OpGroupNonUniformFMul
3622 CEFBS_None, // OpGroupNonUniformIAdd
3623 CEFBS_None, // OpGroupNonUniformIMul
3624 CEFBS_None, // OpGroupNonUniformInverseBallot
3625 CEFBS_None, // OpGroupNonUniformLogicalAnd
3626 CEFBS_None, // OpGroupNonUniformLogicalOr
3627 CEFBS_None, // OpGroupNonUniformLogicalXor
3628 CEFBS_None, // OpGroupNonUniformQuadSwap
3629 CEFBS_None, // OpGroupNonUniformRotateKHR
3630 CEFBS_None, // OpGroupNonUniformSMax
3631 CEFBS_None, // OpGroupNonUniformSMin
3632 CEFBS_None, // OpGroupNonUniformShuffle
3633 CEFBS_None, // OpGroupNonUniformShuffleDown
3634 CEFBS_None, // OpGroupNonUniformShuffleUp
3635 CEFBS_None, // OpGroupNonUniformShuffleXor
3636 CEFBS_None, // OpGroupNonUniformUMax
3637 CEFBS_None, // OpGroupNonUniformUMin
3638 CEFBS_None, // OpGroupReserveReadPipePackets
3639 CEFBS_None, // OpGroupReserveWritePipePackets
3640 CEFBS_None, // OpGroupSMax
3641 CEFBS_None, // OpGroupSMin
3642 CEFBS_None, // OpGroupUMax
3643 CEFBS_None, // OpGroupUMin
3644 CEFBS_None, // OpGroupWaitEvents
3645 CEFBS_None, // OpIAddCarryS
3646 CEFBS_None, // OpIAddCarryV
3647 CEFBS_None, // OpIAddS
3648 CEFBS_None, // OpIAddV
3649 CEFBS_None, // OpIEqual
3650 CEFBS_None, // OpIMulS
3651 CEFBS_None, // OpIMulV
3652 CEFBS_None, // OpINotEqual
3653 CEFBS_None, // OpISubBorrowS
3654 CEFBS_None, // OpISubBorrowV
3655 CEFBS_None, // OpISubS
3656 CEFBS_None, // OpISubV
3657 CEFBS_None, // OpImage
3658 CEFBS_None, // OpImageDrefGather
3659 CEFBS_None, // OpImageFetch
3660 CEFBS_None, // OpImageGather
3661 CEFBS_None, // OpImageQueryFormat
3662 CEFBS_None, // OpImageQueryLevels
3663 CEFBS_None, // OpImageQueryLod
3664 CEFBS_None, // OpImageQueryOrder
3665 CEFBS_None, // OpImageQuerySamples
3666 CEFBS_None, // OpImageQuerySize
3667 CEFBS_None, // OpImageQuerySizeLod
3668 CEFBS_None, // OpImageRead
3669 CEFBS_None, // OpImageSampleDrefExplicitLod
3670 CEFBS_None, // OpImageSampleDrefImplicitLod
3671 CEFBS_None, // OpImageSampleExplicitLod
3672 CEFBS_None, // OpImageSampleFootprintNV
3673 CEFBS_None, // OpImageSampleImplicitLod
3674 CEFBS_None, // OpImageSampleProjDrefExplicitLod
3675 CEFBS_None, // OpImageSampleProjDrefImplicitLod
3676 CEFBS_None, // OpImageSampleProjExplicitLod
3677 CEFBS_None, // OpImageSampleProjImplicitLod
3678 CEFBS_None, // OpImageSparseDrefGather
3679 CEFBS_None, // OpImageSparseFetch
3680 CEFBS_None, // OpImageSparseGather
3681 CEFBS_None, // OpImageSparseRead
3682 CEFBS_None, // OpImageSparseSampleDrefExplicitLod
3683 CEFBS_None, // OpImageSparseSampleDrefImplicitLod
3684 CEFBS_None, // OpImageSparseSampleExplicitLod
3685 CEFBS_None, // OpImageSparseSampleImplicitLod
3686 CEFBS_None, // OpImageSparseSampleProjDrefExplicitLod
3687 CEFBS_None, // OpImageSparseSampleProjDrefImplicitLod
3688 CEFBS_None, // OpImageSparseSampleProjExplicitLod
3689 CEFBS_None, // OpImageSparseSampleProjImplicitLod
3690 CEFBS_None, // OpImageSparseTexelsResident
3691 CEFBS_None, // OpImageTexelPointer
3692 CEFBS_None, // OpImageWrite
3693 CEFBS_None, // OpInBoundsAccessChain
3694 CEFBS_None, // OpInBoundsPtrAccessChain
3695 CEFBS_None, // OpIsFinite
3696 CEFBS_None, // OpIsInf
3697 CEFBS_None, // OpIsNan
3698 CEFBS_None, // OpIsNormal
3699 CEFBS_None, // OpIsValidEvent
3700 CEFBS_None, // OpIsValidReserveId
3701 CEFBS_None, // OpKill
3702 CEFBS_None, // OpLabel
3703 CEFBS_None, // OpLessOrGreater
3704 CEFBS_None, // OpLifetimeStart
3705 CEFBS_None, // OpLifetimeStop
3706 CEFBS_None, // OpLine
3707 CEFBS_None, // OpLoad
3708 CEFBS_None, // OpLogicalAnd
3709 CEFBS_None, // OpLogicalEqual
3710 CEFBS_None, // OpLogicalNot
3711 CEFBS_None, // OpLogicalNotEqual
3712 CEFBS_None, // OpLogicalOr
3713 CEFBS_None, // OpLoopControlINTEL
3714 CEFBS_None, // OpLoopMerge
3715 CEFBS_None, // OpMaskedGatherINTEL
3716 CEFBS_None, // OpMaskedScatterINTEL
3717 CEFBS_None, // OpMatrixTimesMatrix
3718 CEFBS_None, // OpMatrixTimesScalar
3719 CEFBS_None, // OpMatrixTimesVector
3720 CEFBS_None, // OpMemberDecorate
3721 CEFBS_None, // OpMemberDecorateString
3722 CEFBS_None, // OpMemberName
3723 CEFBS_None, // OpMemoryBarrier
3724 CEFBS_None, // OpMemoryModel
3725 CEFBS_None, // OpMemoryNamedBarrier
3726 CEFBS_None, // OpModuleProcessed
3727 CEFBS_None, // OpName
3728 CEFBS_None, // OpNamedBarrierInitialize
3729 CEFBS_None, // OpNoLine
3730 CEFBS_None, // OpNop
3731 CEFBS_None, // OpNot
3732 CEFBS_None, // OpOrdered
3733 CEFBS_None, // OpOuterProduct
3734 CEFBS_None, // OpPhi
3735 CEFBS_None, // OpPoisonKHR
3736 CEFBS_None, // OpPredicatedLoadINTEL
3737 CEFBS_None, // OpPredicatedStoreINTEL
3738 CEFBS_None, // OpPtrAccessChain
3739 CEFBS_None, // OpPtrCastToCrossWorkgroupINTEL
3740 CEFBS_None, // OpPtrCastToGeneric
3741 CEFBS_None, // OpPtrDiff
3742 CEFBS_None, // OpPtrEqual
3743 CEFBS_None, // OpPtrNotEqual
3744 CEFBS_None, // OpQuantizeToF16
3745 CEFBS_None, // OpReadClockKHR
3746 CEFBS_None, // OpReadPipe
3747 CEFBS_None, // OpReadPipeBlockingALTERA
3748 CEFBS_None, // OpReleaseEvent
3749 CEFBS_None, // OpReserveReadPipePackets
3750 CEFBS_None, // OpReserveWritePipePackets
3751 CEFBS_None, // OpReservedReadPipe
3752 CEFBS_None, // OpReservedWritePipe
3753 CEFBS_None, // OpRestoreMemoryINTEL
3754 CEFBS_None, // OpRetainEvent
3755 CEFBS_None, // OpReturn
3756 CEFBS_None, // OpReturnValue
3757 CEFBS_None, // OpRoundFToTF32INTEL
3758 CEFBS_None, // OpSConvert
3759 CEFBS_None, // OpSDivS
3760 CEFBS_None, // OpSDivV
3761 CEFBS_None, // OpSDot
3762 CEFBS_None, // OpSDotAccSat
3763 CEFBS_None, // OpSGreaterThan
3764 CEFBS_None, // OpSGreaterThanEqual
3765 CEFBS_None, // OpSLessThan
3766 CEFBS_None, // OpSLessThanEqual
3767 CEFBS_None, // OpSMod
3768 CEFBS_None, // OpSMulExtended
3769 CEFBS_None, // OpSNegate
3770 CEFBS_None, // OpSRemS
3771 CEFBS_None, // OpSRemV
3772 CEFBS_None, // OpSUDot
3773 CEFBS_None, // OpSUDotAccSat
3774 CEFBS_None, // OpSampledImage
3775 CEFBS_None, // OpSatConvertSToU
3776 CEFBS_None, // OpSatConvertUToS
3777 CEFBS_None, // OpSaveMemoryINTEL
3778 CEFBS_None, // OpSelectSFSCond
3779 CEFBS_None, // OpSelectSFVCond
3780 CEFBS_None, // OpSelectSISCond
3781 CEFBS_None, // OpSelectSIVCond
3782 CEFBS_None, // OpSelectSPSCond
3783 CEFBS_None, // OpSelectSPVCond
3784 CEFBS_None, // OpSelectVFSCond
3785 CEFBS_None, // OpSelectVFVCond
3786 CEFBS_None, // OpSelectVISCond
3787 CEFBS_None, // OpSelectVIVCond
3788 CEFBS_None, // OpSelectVPSCond
3789 CEFBS_None, // OpSelectVPVCond
3790 CEFBS_None, // OpSelectionMerge
3791 CEFBS_None, // OpSetUserEventStatus
3792 CEFBS_None, // OpShiftLeftLogicalS
3793 CEFBS_None, // OpShiftLeftLogicalV
3794 CEFBS_None, // OpShiftRightArithmeticS
3795 CEFBS_None, // OpShiftRightArithmeticV
3796 CEFBS_None, // OpShiftRightLogicalS
3797 CEFBS_None, // OpShiftRightLogicalV
3798 CEFBS_None, // OpSignBitSet
3799 CEFBS_None, // OpSizeOf
3800 CEFBS_None, // OpSource
3801 CEFBS_None, // OpSourceContinued
3802 CEFBS_None, // OpSourceExtension
3803 CEFBS_None, // OpSpecConstant
3804 CEFBS_None, // OpSpecConstantComposite
3805 CEFBS_None, // OpSpecConstantCompositeContinuedINTEL
3806 CEFBS_None, // OpSpecConstantFalse
3807 CEFBS_None, // OpSpecConstantOp
3808 CEFBS_None, // OpSpecConstantTrue
3809 CEFBS_None, // OpStore
3810 CEFBS_None, // OpStrictFAddS
3811 CEFBS_None, // OpStrictFAddV
3812 CEFBS_None, // OpStrictFDivS
3813 CEFBS_None, // OpStrictFDivV
3814 CEFBS_None, // OpStrictFMulS
3815 CEFBS_None, // OpStrictFMulV
3816 CEFBS_None, // OpStrictFRemS
3817 CEFBS_None, // OpStrictFRemV
3818 CEFBS_None, // OpStrictFSubS
3819 CEFBS_None, // OpStrictFSubV
3820 CEFBS_None, // OpString
3821 CEFBS_None, // OpSubgroup2DBlockLoadINTEL
3822 CEFBS_None, // OpSubgroup2DBlockLoadTransformINTEL
3823 CEFBS_None, // OpSubgroup2DBlockLoadTransposeINTEL
3824 CEFBS_None, // OpSubgroup2DBlockPrefetchINTEL
3825 CEFBS_None, // OpSubgroup2DBlockStoreINTEL
3826 CEFBS_None, // OpSubgroupBlockReadINTEL
3827 CEFBS_None, // OpSubgroupBlockWriteINTEL
3828 CEFBS_None, // OpSubgroupImageBlockReadINTEL
3829 CEFBS_None, // OpSubgroupImageBlockWriteINTEL
3830 CEFBS_None, // OpSubgroupImageMediaBlockReadINTEL
3831 CEFBS_None, // OpSubgroupImageMediaBlockWriteINTEL
3832 CEFBS_None, // OpSubgroupMatrixMultiplyAccumulateINTEL
3833 CEFBS_None, // OpSubgroupShuffleDownINTEL
3834 CEFBS_None, // OpSubgroupShuffleINTEL
3835 CEFBS_None, // OpSubgroupShuffleUpINTEL
3836 CEFBS_None, // OpSubgroupShuffleXorINTEL
3837 CEFBS_None, // OpSwitch
3838 CEFBS_None, // OpTranspose
3839 CEFBS_None, // OpTypeAccelerationStructureNV
3840 CEFBS_None, // OpTypeArray
3841 CEFBS_None, // OpTypeBool
3842 CEFBS_None, // OpTypeCooperativeMatrixKHR
3843 CEFBS_None, // OpTypeCooperativeMatrixNV
3844 CEFBS_None, // OpTypeDeviceEvent
3845 CEFBS_None, // OpTypeEvent
3846 CEFBS_None, // OpTypeFloat
3847 CEFBS_None, // OpTypeForwardPointer
3848 CEFBS_None, // OpTypeFunction
3849 CEFBS_None, // OpTypeImage
3850 CEFBS_None, // OpTypeInt
3851 CEFBS_None, // OpTypeMatrix
3852 CEFBS_None, // OpTypeNamedBarrier
3853 CEFBS_None, // OpTypeOpaque
3854 CEFBS_None, // OpTypePipe
3855 CEFBS_None, // OpTypePipeStorage
3856 CEFBS_None, // OpTypePointer
3857 CEFBS_None, // OpTypeQueue
3858 CEFBS_None, // OpTypeReserveId
3859 CEFBS_None, // OpTypeRuntimeArray
3860 CEFBS_None, // OpTypeSampledImage
3861 CEFBS_None, // OpTypeSampler
3862 CEFBS_None, // OpTypeStruct
3863 CEFBS_None, // OpTypeStructContinuedINTEL
3864 CEFBS_None, // OpTypeUntypedPointerKHR
3865 CEFBS_None, // OpTypeVector
3866 CEFBS_None, // OpTypeVectorIdEXT
3867 CEFBS_None, // OpTypeVoid
3868 CEFBS_None, // OpUConvert
3869 CEFBS_None, // OpUDivS
3870 CEFBS_None, // OpUDivV
3871 CEFBS_None, // OpUDot
3872 CEFBS_None, // OpUDotAccSat
3873 CEFBS_None, // OpUGreaterThan
3874 CEFBS_None, // OpUGreaterThanEqual
3875 CEFBS_None, // OpULessThan
3876 CEFBS_None, // OpULessThanEqual
3877 CEFBS_None, // OpUModS
3878 CEFBS_None, // OpUModV
3879 CEFBS_None, // OpUMulExtended
3880 CEFBS_None, // OpUndef
3881 CEFBS_None, // OpUnordered
3882 CEFBS_None, // OpUnreachable
3883 CEFBS_None, // OpUntypedAccessChainKHR
3884 CEFBS_None, // OpUntypedGroupAsyncCopyKHR
3885 CEFBS_None, // OpUntypedInBoundsAccessChainKHR
3886 CEFBS_None, // OpUntypedInBoundsPtrAccessChainKHR
3887 CEFBS_None, // OpUntypedPrefetchKHR
3888 CEFBS_None, // OpUntypedPtrAccessChainKHR
3889 CEFBS_None, // OpUntypedVariableKHR
3890 CEFBS_None, // OpUntypedVariableLengthArrayINTEL
3891 CEFBS_None, // OpVariable
3892 CEFBS_None, // OpVariableLengthArrayINTEL
3893 CEFBS_None, // OpVectorExtractDynamic
3894 CEFBS_None, // OpVectorInsertDynamic
3895 CEFBS_None, // OpVectorShuffle
3896 CEFBS_None, // OpVectorTimesMatrix
3897 CEFBS_None, // OpVectorTimesScalar
3898 CEFBS_None, // OpWritePipe
3899 CEFBS_None, // OpWritePipeBlockingALTERA
3900 };
3901
3902 assert(Opcode < 868);
3903 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3904}
3905
3906
3907} // namespace llvm::SPIRV_MC
3908
3909#endif // GET_COMPUTE_FEATURES
3910
3911#ifdef GET_AVAILABLE_OPCODE_CHECKER
3912#undef GET_AVAILABLE_OPCODE_CHECKER
3913
3914namespace llvm::SPIRV_MC {
3915
3916bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3917 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3918 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3919 FeatureBitset MissingFeatures =
3920 (AvailableFeatures & RequiredFeatures) ^
3921 RequiredFeatures;
3922 return !MissingFeatures.any();
3923}
3924
3925} // namespace llvm::SPIRV_MC
3926
3927#endif // GET_AVAILABLE_OPCODE_CHECKER
3928
3929#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3930#undef ENABLE_INSTR_PREDICATE_VERIFIER
3931
3932#include <sstream>
3933
3934namespace llvm::SPIRV_MC {
3935
3936#ifndef NDEBUG
3937static const char *SubtargetFeatureNames[] = {
3938 nullptr
3939};
3940
3941#endif // NDEBUG
3942
3943void verifyInstructionPredicates(
3944 unsigned Opcode, const FeatureBitset &Features) {
3945#ifndef NDEBUG
3946 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3947 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3948 FeatureBitset MissingFeatures =
3949 (AvailableFeatures & RequiredFeatures) ^
3950 RequiredFeatures;
3951 if (MissingFeatures.any()) {
3952 std::ostringstream Msg;
3953 Msg << "Attempting to emit " << &SPIRVInstrNameData[SPIRVInstrNameIndices[Opcode]]
3954 << " instruction but the ";
3955 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3956 if (MissingFeatures.test(i))
3957 Msg << SubtargetFeatureNames[i] << " ";
3958 Msg << "predicate(s) are not met";
3959 report_fatal_error(Msg.str().c_str());
3960 }
3961#endif // NDEBUG
3962}
3963
3964} // namespace llvm::SPIRV_MC
3965
3966#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3967
3968