1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::SPIRV {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 IDRegBankID = 0,
17 TYPERegBankID = 1,
18 NumRegisterBanks,
19};
20
21} // namespace llvm::SPIRV
22
23#endif // GET_REGBANK_DECLARATIONS
24
25#ifdef GET_TARGET_REGBANK_CLASS
26#undef GET_TARGET_REGBANK_CLASS
27
28private:
29 static const RegisterBank *RegBanks[];
30 static const unsigned Sizes[];
31
32public:
33 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
34protected:
35 SPIRVGenRegisterBankInfo(unsigned HwMode = 0);
36
37
38#endif // GET_TARGET_REGBANK_CLASS
39
40#ifdef GET_TARGET_REGBANK_IMPL
41#undef GET_TARGET_REGBANK_IMPL
42
43namespace llvm {
44
45namespace SPIRV {
46
47const uint32_t IDRegBankCoverageData[] = {
48 // 0-31
49 (1u << (SPIRV::IDRegClassID - 0)) |
50 (1u << (SPIRV::fIDRegClassID - 0)) |
51 (1u << (SPIRV::iIDRegClassID - 0)) |
52 (1u << (SPIRV::pIDRegClassID - 0)) |
53 (1u << (SPIRV::vpIDRegClassID - 0)) |
54 (1u << (SPIRV::vIDRegClassID - 0)) |
55 (1u << (SPIRV::vfIDRegClassID - 0)) |
56 0,
57};
58const uint32_t TYPERegBankCoverageData[] = {
59 // 0-31
60 (1u << (SPIRV::TYPERegClassID - 0)) |
61 0,
62};
63
64constexpr RegisterBank IDRegBank(/* ID */ SPIRV::IDRegBankID, /* Name */ "IDBank", /* CoveredRegClasses */ IDRegBankCoverageData, /* NumRegClasses */ 9);
65constexpr RegisterBank TYPERegBank(/* ID */ SPIRV::TYPERegBankID, /* Name */ "TYPEBank", /* CoveredRegClasses */ TYPERegBankCoverageData, /* NumRegClasses */ 9);
66
67} // namespace SPIRV
68
69const RegisterBank *SPIRVGenRegisterBankInfo::RegBanks[] = {
70 &SPIRV::IDRegBank,
71 &SPIRV::TYPERegBank,
72};
73
74const unsigned SPIRVGenRegisterBankInfo::Sizes[] = {
75 // Mode = 0 (Default)
76 128,
77 64,
78};
79
80SPIRVGenRegisterBankInfo::SPIRVGenRegisterBankInfo(unsigned HwMode)
81 : RegisterBankInfo(RegBanks, SPIRV::NumRegisterBanks, Sizes, HwMode) {
82 // Assert that RegBank indices match their ID's
83#ifndef NDEBUG
84 for (auto RB : enumerate(RegBanks))
85 assert(RB.index() == RB.value()->getID() && "Index != ID");
86#endif // NDEBUG
87}
88
89const RegisterBank &
90SPIRVGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
91 constexpr uint32_t InvalidRegBankID = uint32_t(SPIRV::InvalidRegBankID) & 3;
92 static const uint32_t RegClass2RegBank[1] = {
93 (uint32_t(InvalidRegBankID) << 0) |
94 (uint32_t(SPIRV::IDRegBankID) << 2) | // IDRegClassID
95 (uint32_t(SPIRV::TYPERegBankID) << 4) | // TYPERegClassID
96 (uint32_t(SPIRV::IDRegBankID) << 6) | // fIDRegClassID
97 (uint32_t(SPIRV::IDRegBankID) << 8) | // iIDRegClassID
98 (uint32_t(SPIRV::IDRegBankID) << 10) | // pIDRegClassID
99 (uint32_t(SPIRV::IDRegBankID) << 12) | // vpIDRegClassID
100 (uint32_t(SPIRV::IDRegBankID) << 14) | // vIDRegClassID
101 (uint32_t(SPIRV::IDRegBankID) << 16) // vfIDRegClassID
102 };
103 const unsigned RegClassID = RC.getID();
104 if (LLVM_LIKELY(RegClassID < 9)) {
105 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
106 if (RegBankID != InvalidRegBankID)
107 return getRegBank(RegBankID);
108 }
109 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
110}
111
112} // namespace llvm
113
114#endif // GET_TARGET_REGBANK_IMPL
115
116