1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12const MCRegisterClass &getSPIRVMCRegisterClass(unsigned RC);
13namespace SPIRV {
14
15enum : unsigned {
16 NoRegister,
17 ID0 = 1,
18 TYPE0 = 2,
19 fID0 = 3,
20 pID0 = 4,
21 vfID0 = 5,
22 viID0 = 6,
23 vpID0 = 7,
24 NUM_TARGET_REGS // 8
25};
26
27} // namespace SPIRV
28
29// Register classes
30
31namespace SPIRV {
32
33enum {
34 ANYRegClassID = 0,
35 IDRegClassID = 1,
36 TYPERegClassID = 2,
37 fIDRegClassID = 3,
38 iIDRegClassID = 4,
39 pIDRegClassID = 5,
40 vpIDRegClassID = 6,
41 vfIDRegClassID = 7,
42 viIDRegClassID = 8,
43
44};
45
46} // namespace SPIRV
47// Register pressure sets enum.
48namespace SPIRV {
49
50enum RegisterPressureSets {
51 TYPE = 0,
52 fID = 1,
53 iID = 2,
54 pID = 3,
55 vpID = 4,
56 vfID = 5,
57 viID = 6,
58 ID = 7,
59};
60
61} // namespace SPIRV
62
63} // namespace llvm
64