1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass SPIRVMCRegisterClasses[];
13
14namespace SPIRV {
15
16enum : unsigned {
17 NoRegister,
18 ID0 = 1,
19 TYPE0 = 2,
20 fID0 = 3,
21 pID0 = 4,
22 vID0 = 5,
23 vfID0 = 6,
24 vpID0 = 7,
25 NUM_TARGET_REGS // 8
26};
27
28} // namespace SPIRV
29
30// Register classes
31
32namespace SPIRV {
33
34enum {
35 ANYRegClassID = 0,
36 IDRegClassID = 1,
37 TYPERegClassID = 2,
38 fIDRegClassID = 3,
39 iIDRegClassID = 4,
40 pIDRegClassID = 5,
41 vpIDRegClassID = 6,
42 vIDRegClassID = 7,
43 vfIDRegClassID = 8,
44
45};
46
47} // namespace SPIRV
48// Register pressure sets enum.
49namespace SPIRV {
50
51enum RegisterPressureSets {
52 TYPE = 0,
53 fID = 1,
54 iID = 2,
55 pID = 3,
56 vpID = 4,
57 vID = 5,
58 vfID = 6,
59 ID = 7,
60};
61
62} // namespace SPIRV
63
64} // namespace llvm
65