1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14
15} // namespace llvm
16
17#endif // GET_SUBTARGETINFO_ENUM
18
19#ifdef GET_SUBTARGETINFO_MACRO
20
21
22#undef GET_SUBTARGETINFO_MACRO
23#endif // GET_SUBTARGETINFO_MACRO
24
25#ifdef GET_SUBTARGETINFO_MC_DESC
26#undef GET_SUBTARGETINFO_MC_DESC
27
28namespace llvm {
29
30
31#ifdef DBGFIELD
32#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
33#endif
34#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
35#define DBGFIELD(x) x,
36#define DBGVAL_OR_NULLPTR(x) x
37#else
38#define DBGFIELD(x)
39#define DBGVAL_OR_NULLPTR(x) nullptr
40#endif
41
42// ===============================================================
43// Data tables for the new per-operand machine model.
44
45static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
46static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
47
48// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
49extern const llvm::MCWriteProcResEntry SPIRVWriteProcResTable[] = {
50 { 0, 0, 0 }, // Invalid
51}; // SPIRVWriteProcResTable
52
53// {Cycles, WriteResourceID}
54extern const llvm::MCWriteLatencyEntry SPIRVWriteLatencyTable[] = {
55 { 0, 0}, // Invalid
56}; // SPIRVWriteLatencyTable
57
58// {UseIdx, WriteResourceID, Cycles}
59extern const llvm::MCReadAdvanceEntry SPIRVReadAdvanceTable[] = {
60 {0, 0, 0}, // Invalid
61}; // SPIRVReadAdvanceTable
62
63#ifdef __GNUC__
64#pragma GCC diagnostic push
65#pragma GCC diagnostic ignored "-Woverlength-strings"
66#endif
67static constexpr char SPIRVSchedClassNamesStorage[] =
68 "\0"
69 "InvalidSchedClass\0"
70 ;
71#ifdef __GNUC__
72#pragma GCC diagnostic pop
73#endif
74
75static constexpr llvm::StringTable
76SPIRVSchedClassNames = SPIRVSchedClassNamesStorage;
77
78extern const llvm::MCSchedModel SPIRVSchedModels[] = {
79{ // NoSchedModel
80 MCSchedModel::DefaultIssueWidth,
81 MCSchedModel::DefaultMicroOpBufferSize,
82 MCSchedModel::DefaultLoopMicroOpBufferSize,
83 MCSchedModel::DefaultLoadLatency,
84 MCSchedModel::DefaultHighLatency,
85 MCSchedModel::DefaultMispredictPenalty,
86 false, // PostRAScheduler
87 false, // CompleteModel
88 false, // EnableIntervals
89 0, // Processor ID
90 nullptr, nullptr, 0, 0, // No instruction-level machine model.
91 DBGVAL_OR_NULLPTR(&SPIRVSchedClassNames), // SchedClassNames
92 nullptr, // No Itinerary
93 nullptr // No extra processor descriptor
94 },
95};
96
97#undef DBGFIELD
98
99#undef DBGVAL_OR_NULLPTR
100
101static constexpr size_t SPIRVCPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 0>);
102// Sorted (by key) array of values for CPU subtype.
103extern const llvm::SubtargetSubTypeKVStorage< 1, 0, 10> SPIRVSubTypeKVStorage = {
104 {
105 { sizeof(SubtargetSubTypeKV) * 1 + SPIRVCPUAliasArraySize + 1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
106 },
107 { {
108 } },
109 "\000generic\000"};
110
111namespace SPIRV_MC {
112
113unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
114 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
115 // Don't know how to resolve this scheduling class.
116 return 0;
117}
118
119} // namespace SPIRV_MC
120struct SPIRVGenMCSubtargetInfo : public MCSubtargetInfo {
121 SPIRVGenMCSubtargetInfo(const Triple &TT,
122 StringRef CPU, StringRef TuneCPU, StringRef FS,
123 StringTable PN,
124 ArrayRef<SubtargetFeatureKV> PF,
125 ArrayRef<SubtargetSubTypeKV> PD,
126 ArrayRef<SubtargetSubTypeAliasKV> PA,
127 const MCSchedModel *PSM,
128 const MCWriteProcResEntry *WPR,
129 const MCWriteLatencyEntry *WL,
130 const MCReadAdvanceEntry *RA, const InstrStage *IS,
131 const unsigned *OC, const unsigned *FP) :
132 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
133 WPR, WL, RA, IS, OC, FP) { }
134
135 unsigned resolveVariantSchedClass(unsigned SchedClass,
136 const MCInst *MI, const MCInstrInfo *MCII,
137 unsigned CPUID) const final {
138 return SPIRV_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
139 }
140};
141
142static inline MCSubtargetInfo *createSPIRVMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
143 return new SPIRVGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(SPIRVSubTypeKVStorage.Strings), {}, SPIRVSubTypeKVStorage.SubTypes, ArrayRef(SPIRVSubTypeKVStorage.Aliases).take_front(0), SPIRVSchedModels,
144 SPIRVWriteProcResTable, SPIRVWriteLatencyTable, SPIRVReadAdvanceTable,
145 nullptr, nullptr, nullptr);
146}
147
148
149} // namespace llvm
150
151#endif // GET_SUBTARGETINFO_MC_DESC
152
153#ifdef GET_SUBTARGETINFO_TARGET_DESC
154#undef GET_SUBTARGETINFO_TARGET_DESC
155
156#include "llvm/ADT/BitmaskEnum.h"
157#include "llvm/Support/Debug.h"
158#include "llvm/Support/raw_ostream.h"
159
160// ParseSubtargetFeatures - Parses features string setting specified
161// subtarget options.
162void llvm::SPIRVSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
163 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
164 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
165 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
166}
167
168#endif // GET_SUBTARGETINFO_TARGET_DESC
169
170#ifdef GET_SUBTARGETINFO_HEADER
171#undef GET_SUBTARGETINFO_HEADER
172
173namespace llvm {
174
175class DFAPacketizer;
176namespace SPIRV_MC {
177
178unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
179
180} // namespace SPIRV_MC
181struct SPIRVGenSubtargetInfo : public TargetSubtargetInfo {
182 explicit SPIRVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
183public:
184 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
185 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
186 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
187 const FeatureBitset &getInlineIgnoreFeatures() const override;
188 const FeatureBitset &getInlineInverseFeatures() const override;
189 const FeatureBitset &getInlineMustMatchFeatures() const override;
190};
191
192} // namespace llvm
193
194#endif // GET_SUBTARGETINFO_HEADER
195
196#ifdef GET_SUBTARGETINFO_CTOR
197#undef GET_SUBTARGETINFO_CTOR
198
199#include "llvm/CodeGen/TargetSchedule.h"
200
201namespace llvm {
202
203extern const llvm::StringRef SPIRVNames[];
204extern const llvm::SubtargetSubTypeKVStorage<1, 0, 10> SPIRVSubTypeKVStorage;
205extern const llvm::MCSchedModel SPIRVSchedModels[];
206extern const llvm::MCWriteProcResEntry SPIRVWriteProcResTable[];
207extern const llvm::MCWriteLatencyEntry SPIRVWriteLatencyTable[];
208extern const llvm::MCReadAdvanceEntry SPIRVReadAdvanceTable[];
209SPIRVGenSubtargetInfo::SPIRVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
210 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(SPIRVSubTypeKVStorage.Strings), {}, ArrayRef(SPIRVSubTypeKVStorage.SubTypes), ArrayRef(SPIRVSubTypeKVStorage.Aliases).take_front(0), SPIRVSchedModels,
211 SPIRVWriteProcResTable, SPIRVWriteLatencyTable, SPIRVReadAdvanceTable,
212 nullptr, nullptr, nullptr) {}
213
214unsigned SPIRVGenSubtargetInfo
215::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
216 report_fatal_error("Expected a variant SchedClass");
217} // SPIRVGenSubtargetInfo::resolveSchedClass
218
219unsigned SPIRVGenSubtargetInfo
220::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
221 return SPIRV_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
222} // SPIRVGenSubtargetInfo::resolveVariantSchedClass
223
224const FeatureBitset &SPIRVGenSubtargetInfo::getInlineIgnoreFeatures() const {
225 static constexpr FeatureBitset Features = {
226 };
227 return Features;
228}
229
230const FeatureBitset &SPIRVGenSubtargetInfo::getInlineInverseFeatures() const {
231 static constexpr FeatureBitset Features = {
232 };
233 return Features;
234}
235
236const FeatureBitset &SPIRVGenSubtargetInfo::getInlineMustMatchFeatures() const {
237 static constexpr FeatureBitset Features = {
238 };
239 return Features;
240}
241
242
243} // namespace llvm
244
245#endif // GET_SUBTARGETINFO_CTOR
246
247#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
248#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
249
250
251#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
252
253#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
254#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
255
256
257#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
258
259