1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14
15} // namespace llvm
16
17#endif // GET_SUBTARGETINFO_ENUM
18
19#ifdef GET_SUBTARGETINFO_MACRO
20
21
22#undef GET_SUBTARGETINFO_MACRO
23#endif // GET_SUBTARGETINFO_MACRO
24
25#ifdef GET_SUBTARGETINFO_MC_DESC
26#undef GET_SUBTARGETINFO_MC_DESC
27
28namespace llvm {
29
30
31#ifdef DBGFIELD
32#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
33#endif
34#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
35#define DBGFIELD(x) x,
36#define DBGVAL_OR_NULLPTR(x) x
37#else
38#define DBGFIELD(x)
39#define DBGVAL_OR_NULLPTR(x) nullptr
40#endif
41
42// ===============================================================
43// Data tables for the new per-operand machine model.
44
45// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
46extern const llvm::MCWriteProcResEntry SPIRVWriteProcResTable[] = {
47 { 0, 0, 0 }, // Invalid
48}; // SPIRVWriteProcResTable
49
50// {Cycles, WriteResourceID}
51extern const llvm::MCWriteLatencyEntry SPIRVWriteLatencyTable[] = {
52 { 0, 0}, // Invalid
53}; // SPIRVWriteLatencyTable
54
55// {UseIdx, WriteResourceID, Cycles}
56extern const llvm::MCReadAdvanceEntry SPIRVReadAdvanceTable[] = {
57 {0, 0, 0}, // Invalid
58}; // SPIRVReadAdvanceTable
59
60#ifdef __GNUC__
61#pragma GCC diagnostic push
62#pragma GCC diagnostic ignored "-Woverlength-strings"
63#endif
64static constexpr char SPIRVSchedClassNamesStorage[] =
65 "\0"
66 "InvalidSchedClass\0"
67 ;
68#ifdef __GNUC__
69#pragma GCC diagnostic pop
70#endif
71
72static constexpr llvm::StringTable
73SPIRVSchedClassNames = SPIRVSchedClassNamesStorage;
74
75static const llvm::MCSchedModel NoSchedModel = {
76 MCSchedModel::DefaultIssueWidth,
77 MCSchedModel::DefaultMicroOpBufferSize,
78 MCSchedModel::DefaultLoopMicroOpBufferSize,
79 MCSchedModel::DefaultLoadLatency,
80 MCSchedModel::DefaultHighLatency,
81 MCSchedModel::DefaultMispredictPenalty,
82 false, // PostRAScheduler
83 false, // CompleteModel
84 false, // EnableIntervals
85 0, // Processor ID
86 nullptr, nullptr, 0, 0, // No instruction-level machine model.
87 DBGVAL_OR_NULLPTR(&SPIRVSchedClassNames), // SchedClassNames
88 nullptr, // No Itinerary
89 nullptr // No extra processor descriptor
90};
91
92#undef DBGFIELD
93
94#undef DBGVAL_OR_NULLPTR
95
96// Sorted (by key) array of values for CPU subtype.
97extern const llvm::SubtargetSubTypeKV SPIRVSubTypeKV[] = {
98 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
99};
100
101// Sorted array of names of CPU subtypes, including aliases.
102extern const llvm::StringRef SPIRVNames[] = {
103"generic"};
104
105namespace SPIRV_MC {
106
107unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
108 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
109 // Don't know how to resolve this scheduling class.
110 return 0;
111}
112
113} // namespace SPIRV_MC
114struct SPIRVGenMCSubtargetInfo : public MCSubtargetInfo {
115 SPIRVGenMCSubtargetInfo(const Triple &TT,
116 StringRef CPU, StringRef TuneCPU, StringRef FS,
117 ArrayRef<StringRef> PN,
118 ArrayRef<SubtargetFeatureKV> PF,
119 ArrayRef<SubtargetSubTypeKV> PD,
120 const MCWriteProcResEntry *WPR,
121 const MCWriteLatencyEntry *WL,
122 const MCReadAdvanceEntry *RA, const InstrStage *IS,
123 const unsigned *OC, const unsigned *FP) :
124 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
125 WPR, WL, RA, IS, OC, FP) { }
126
127 unsigned resolveVariantSchedClass(unsigned SchedClass,
128 const MCInst *MI, const MCInstrInfo *MCII,
129 unsigned CPUID) const final {
130 return SPIRV_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
131 }
132};
133
134static inline MCSubtargetInfo *createSPIRVMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
135 return new SPIRVGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, SPIRVNames, {}, SPIRVSubTypeKV,
136 SPIRVWriteProcResTable, SPIRVWriteLatencyTable, SPIRVReadAdvanceTable,
137 nullptr, nullptr, nullptr);
138}
139
140
141} // namespace llvm
142
143#endif // GET_SUBTARGETINFO_MC_DESC
144
145#ifdef GET_SUBTARGETINFO_TARGET_DESC
146#undef GET_SUBTARGETINFO_TARGET_DESC
147
148#include "llvm/ADT/BitmaskEnum.h"
149#include "llvm/Support/Debug.h"
150#include "llvm/Support/raw_ostream.h"
151
152// ParseSubtargetFeatures - Parses features string setting specified
153// subtarget options.
154void llvm::SPIRVSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
155 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
156 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
157 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
158}
159
160#endif // GET_SUBTARGETINFO_TARGET_DESC
161
162#ifdef GET_SUBTARGETINFO_HEADER
163#undef GET_SUBTARGETINFO_HEADER
164
165namespace llvm {
166
167class DFAPacketizer;
168namespace SPIRV_MC {
169
170unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
171
172} // namespace SPIRV_MC
173struct SPIRVGenSubtargetInfo : public TargetSubtargetInfo {
174 explicit SPIRVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
175public:
176 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
177 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
178 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
179};
180
181} // namespace llvm
182
183#endif // GET_SUBTARGETINFO_HEADER
184
185#ifdef GET_SUBTARGETINFO_CTOR
186#undef GET_SUBTARGETINFO_CTOR
187
188#include "llvm/CodeGen/TargetSchedule.h"
189
190namespace llvm {
191
192extern const llvm::StringRef SPIRVNames[];
193extern const llvm::SubtargetFeatureKV SPIRVFeatureKV[];
194extern const llvm::SubtargetSubTypeKV SPIRVSubTypeKV[];
195extern const llvm::MCWriteProcResEntry SPIRVWriteProcResTable[];
196extern const llvm::MCWriteLatencyEntry SPIRVWriteLatencyTable[];
197extern const llvm::MCReadAdvanceEntry SPIRVReadAdvanceTable[];
198SPIRVGenSubtargetInfo::SPIRVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
199 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(SPIRVNames, 1), {}, ArrayRef(SPIRVSubTypeKV, 1),
200 SPIRVWriteProcResTable, SPIRVWriteLatencyTable, SPIRVReadAdvanceTable,
201 nullptr, nullptr, nullptr) {}
202
203unsigned SPIRVGenSubtargetInfo
204::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
205 report_fatal_error("Expected a variant SchedClass");
206} // SPIRVGenSubtargetInfo::resolveSchedClass
207
208unsigned SPIRVGenSubtargetInfo
209::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
210 return SPIRV_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
211} // SPIRVGenSubtargetInfo::resolveVariantSchedClass
212
213
214} // namespace llvm
215
216#endif // GET_SUBTARGETINFO_CTOR
217
218#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
219#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
220
221
222#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
223
224#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
225#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
226
227
228#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
229
230