1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14
15} // namespace llvm
16
17#endif // GET_SUBTARGETINFO_ENUM
18
19#ifdef GET_SUBTARGETINFO_MACRO
20
21
22#undef GET_SUBTARGETINFO_MACRO
23#endif // GET_SUBTARGETINFO_MACRO
24
25#ifdef GET_SUBTARGETINFO_MC_DESC
26#undef GET_SUBTARGETINFO_MC_DESC
27
28namespace llvm {
29
30
31#ifdef DBGFIELD
32#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
33#endif
34#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
35#define DBGFIELD(x) x,
36#define DBGVAL_OR_NULLPTR(x) x
37#else
38#define DBGFIELD(x)
39#define DBGVAL_OR_NULLPTR(x) nullptr
40#endif
41
42// ===============================================================
43// Data tables for the new per-operand machine model.
44
45static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
46static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
47
48// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
49extern const llvm::MCWriteProcResEntry SPIRVWriteProcResTable[] = {
50 { 0, 0, 0 }, // Invalid
51}; // SPIRVWriteProcResTable
52
53// {Cycles, WriteResourceID}
54extern const llvm::MCWriteLatencyEntry SPIRVWriteLatencyTable[] = {
55 { 0, 0}, // Invalid
56}; // SPIRVWriteLatencyTable
57
58// {UseIdx, WriteResourceID, Cycles}
59extern const llvm::MCReadAdvanceEntry SPIRVReadAdvanceTable[] = {
60 {0, 0, 0}, // Invalid
61}; // SPIRVReadAdvanceTable
62
63#ifdef __GNUC__
64#pragma GCC diagnostic push
65#pragma GCC diagnostic ignored "-Woverlength-strings"
66#endif
67static constexpr char SPIRVSchedClassNamesStorage[] =
68 "\0"
69 "InvalidSchedClass\0"
70 ;
71#ifdef __GNUC__
72#pragma GCC diagnostic pop
73#endif
74
75static constexpr llvm::StringTable
76SPIRVSchedClassNames = SPIRVSchedClassNamesStorage;
77
78extern const llvm::MCSchedModel SPIRVSchedModels[] = {
79{ // NoSchedModel
80 MCSchedModel::DefaultIssueWidth,
81 MCSchedModel::DefaultMicroOpBufferSize,
82 MCSchedModel::DefaultLoopMicroOpBufferSize,
83 MCSchedModel::DefaultLoadLatency,
84 MCSchedModel::DefaultHighLatency,
85 MCSchedModel::DefaultMispredictPenalty,
86 false, // PostRAScheduler
87 false, // CompleteModel
88 false, // EnableIntervals
89 0, // Processor ID
90 nullptr, nullptr, 0, 0, // No instruction-level machine model.
91 DBGVAL_OR_NULLPTR(&SPIRVSchedClassNames), // SchedClassNames
92 nullptr, // No Itinerary
93 nullptr // No extra processor descriptor
94 },
95};
96
97#undef DBGFIELD
98
99#undef DBGVAL_OR_NULLPTR
100
101// Sorted (by key) array of values for CPU subtype.
102extern const llvm::SubtargetSubTypeKVStorage< 1, 10> SPIRVSubTypeKVStorage = {
103 {
104 { sizeof(SubtargetSubTypeKV) * 1 + 1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
105 },
106 "\000generic\000"};
107
108namespace SPIRV_MC {
109
110unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
111 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
112 // Don't know how to resolve this scheduling class.
113 return 0;
114}
115
116} // namespace SPIRV_MC
117struct SPIRVGenMCSubtargetInfo : public MCSubtargetInfo {
118 SPIRVGenMCSubtargetInfo(const Triple &TT,
119 StringRef CPU, StringRef TuneCPU, StringRef FS,
120 StringTable PN,
121 ArrayRef<SubtargetFeatureKV> PF,
122 ArrayRef<SubtargetSubTypeKV> PD,
123 const MCSchedModel *PSM,
124 const MCWriteProcResEntry *WPR,
125 const MCWriteLatencyEntry *WL,
126 const MCReadAdvanceEntry *RA, const InstrStage *IS,
127 const unsigned *OC, const unsigned *FP) :
128 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
129 WPR, WL, RA, IS, OC, FP) { }
130
131 unsigned resolveVariantSchedClass(unsigned SchedClass,
132 const MCInst *MI, const MCInstrInfo *MCII,
133 unsigned CPUID) const final {
134 return SPIRV_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
135 }
136};
137
138static inline MCSubtargetInfo *createSPIRVMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
139 return new SPIRVGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(SPIRVSubTypeKVStorage.Strings), {}, SPIRVSubTypeKVStorage.SubTypes, SPIRVSchedModels,
140 SPIRVWriteProcResTable, SPIRVWriteLatencyTable, SPIRVReadAdvanceTable,
141 nullptr, nullptr, nullptr);
142}
143
144
145} // namespace llvm
146
147#endif // GET_SUBTARGETINFO_MC_DESC
148
149#ifdef GET_SUBTARGETINFO_TARGET_DESC
150#undef GET_SUBTARGETINFO_TARGET_DESC
151
152#include "llvm/ADT/BitmaskEnum.h"
153#include "llvm/Support/Debug.h"
154#include "llvm/Support/raw_ostream.h"
155
156// ParseSubtargetFeatures - Parses features string setting specified
157// subtarget options.
158void llvm::SPIRVSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
159 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
160 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
161 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
162}
163
164#endif // GET_SUBTARGETINFO_TARGET_DESC
165
166#ifdef GET_SUBTARGETINFO_HEADER
167#undef GET_SUBTARGETINFO_HEADER
168
169namespace llvm {
170
171class DFAPacketizer;
172namespace SPIRV_MC {
173
174unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
175
176} // namespace SPIRV_MC
177struct SPIRVGenSubtargetInfo : public TargetSubtargetInfo {
178 explicit SPIRVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
179public:
180 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
181 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
182 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
183 const FeatureBitset &getInlineIgnoreFeatures() const override;
184 const FeatureBitset &getInlineInverseFeatures() const override;
185 const FeatureBitset &getInlineMustMatchFeatures() const override;
186};
187
188} // namespace llvm
189
190#endif // GET_SUBTARGETINFO_HEADER
191
192#ifdef GET_SUBTARGETINFO_CTOR
193#undef GET_SUBTARGETINFO_CTOR
194
195#include "llvm/CodeGen/TargetSchedule.h"
196
197namespace llvm {
198
199extern const llvm::StringRef SPIRVNames[];
200extern const llvm::SubtargetSubTypeKVStorage<1, 10> SPIRVSubTypeKVStorage;
201extern const llvm::MCSchedModel SPIRVSchedModels[];
202extern const llvm::MCWriteProcResEntry SPIRVWriteProcResTable[];
203extern const llvm::MCWriteLatencyEntry SPIRVWriteLatencyTable[];
204extern const llvm::MCReadAdvanceEntry SPIRVReadAdvanceTable[];
205SPIRVGenSubtargetInfo::SPIRVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
206 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(SPIRVSubTypeKVStorage.Strings), {}, ArrayRef(SPIRVSubTypeKVStorage.SubTypes), SPIRVSchedModels,
207 SPIRVWriteProcResTable, SPIRVWriteLatencyTable, SPIRVReadAdvanceTable,
208 nullptr, nullptr, nullptr) {}
209
210unsigned SPIRVGenSubtargetInfo
211::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
212 report_fatal_error("Expected a variant SchedClass");
213} // SPIRVGenSubtargetInfo::resolveSchedClass
214
215unsigned SPIRVGenSubtargetInfo
216::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
217 return SPIRV_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
218} // SPIRVGenSubtargetInfo::resolveVariantSchedClass
219
220const FeatureBitset &SPIRVGenSubtargetInfo::getInlineIgnoreFeatures() const {
221 static constexpr FeatureBitset Features = {
222 };
223 return Features;
224}
225
226const FeatureBitset &SPIRVGenSubtargetInfo::getInlineInverseFeatures() const {
227 static constexpr FeatureBitset Features = {
228 };
229 return Features;
230}
231
232const FeatureBitset &SPIRVGenSubtargetInfo::getInlineMustMatchFeatures() const {
233 static constexpr FeatureBitset Features = {
234 };
235 return Features;
236}
237
238
239} // namespace llvm
240
241#endif // GET_SUBTARGETINFO_CTOR
242
243#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
244#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
245
246
247#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
248
249#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
250#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
251
252
253#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
254
255