1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Sparc.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands);
18 void convertToMapAndConstraints(unsigned Kind,
19 const OperandVector &Operands) override;
20 unsigned MatchInstructionImpl(const OperandVector &Operands,
21 MCInst &Inst,
22 uint64_t &ErrorInfo,
23 FeatureBitset &MissingFeatures,
24 bool matchingInlineAsm,
25 unsigned VariantID = 0);
26 unsigned MatchInstructionImpl(const OperandVector &Operands,
27 MCInst &Inst,
28 uint64_t &ErrorInfo,
29 bool matchingInlineAsm,
30 unsigned VariantID = 0) {
31 FeatureBitset MissingFeatures;
32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33 matchingInlineAsm, VariantID);
34 }
35
36 ParseStatus MatchOperandParserImpl(
37 OperandVector &Operands,
38 StringRef Mnemonic,
39 bool ParseForAllFeatures = false);
40 ParseStatus tryCustomParseOperand(
41 OperandVector &Operands,
42 unsigned MCK);
43
44#endif // GET_ASSEMBLER_HEADER
45
46
47#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
48#undef GET_OPERAND_DIAGNOSTIC_TYPES
49
50#endif // GET_OPERAND_DIAGNOSTIC_TYPES
51
52
53#ifdef GET_REGISTER_MATCHER
54#undef GET_REGISTER_MATCHER
55
56// Bits for subtarget features that participate in instruction matching.
57enum SubtargetFeatureBits : uint8_t {
58 Feature_Is32BitBit = 10,
59 Feature_Is64BitBit = 11,
60 Feature_UseSoftMulDivBit = 12,
61 Feature_HasV9Bit = 6,
62 Feature_HasVISBit = 7,
63 Feature_HasVIS2Bit = 8,
64 Feature_HasVIS3Bit = 9,
65 Feature_HasUA2005Bit = 4,
66 Feature_HasUA2007Bit = 5,
67 Feature_HasOSA2011Bit = 2,
68 Feature_HasCryptoBit = 1,
69 Feature_HasCASABit = 0,
70 Feature_HasPWRPSRBit = 3,
71};
72
73static MCRegister MatchRegisterName(StringRef Name) {
74 switch (Name.size()) {
75 default: break;
76 case 1: // 1 string to match.
77 if (Name[0] != 'y')
78 break;
79 return SP::Y; // "y"
80 case 2: // 86 strings to match.
81 switch (Name[0]) {
82 default: break;
83 case 'c': // 16 strings to match.
84 switch (Name[1]) {
85 default: break;
86 case '0': // 2 strings to match.
87 return SP::C0; // "c0"
88 case '1': // 1 string to match.
89 return SP::C1; // "c1"
90 case '2': // 2 strings to match.
91 return SP::C2; // "c2"
92 case '3': // 1 string to match.
93 return SP::C3; // "c3"
94 case '4': // 2 strings to match.
95 return SP::C4; // "c4"
96 case '5': // 1 string to match.
97 return SP::C5; // "c5"
98 case '6': // 2 strings to match.
99 return SP::C6; // "c6"
100 case '7': // 1 string to match.
101 return SP::C7; // "c7"
102 case '8': // 2 strings to match.
103 return SP::C8; // "c8"
104 case '9': // 1 string to match.
105 return SP::C9; // "c9"
106 case 'q': // 1 string to match.
107 return SP::CPQ; // "cq"
108 }
109 break;
110 case 'f': // 20 strings to match.
111 switch (Name[1]) {
112 default: break;
113 case '0': // 3 strings to match.
114 return SP::D0; // "f0"
115 case '1': // 1 string to match.
116 return SP::F1; // "f1"
117 case '2': // 2 strings to match.
118 return SP::D1; // "f2"
119 case '3': // 1 string to match.
120 return SP::F3; // "f3"
121 case '4': // 3 strings to match.
122 return SP::D2; // "f4"
123 case '5': // 1 string to match.
124 return SP::F5; // "f5"
125 case '6': // 2 strings to match.
126 return SP::D3; // "f6"
127 case '7': // 1 string to match.
128 return SP::F7; // "f7"
129 case '8': // 3 strings to match.
130 return SP::D4; // "f8"
131 case '9': // 1 string to match.
132 return SP::F9; // "f9"
133 case 'p': // 1 string to match.
134 return SP::I6; // "fp"
135 case 'q': // 1 string to match.
136 return SP::FQ; // "fq"
137 }
138 break;
139 case 'g': // 13 strings to match.
140 switch (Name[1]) {
141 default: break;
142 case '0': // 2 strings to match.
143 return SP::G0; // "g0"
144 case '1': // 1 string to match.
145 return SP::G1; // "g1"
146 case '2': // 2 strings to match.
147 return SP::G2; // "g2"
148 case '3': // 1 string to match.
149 return SP::G3; // "g3"
150 case '4': // 2 strings to match.
151 return SP::G4; // "g4"
152 case '5': // 1 string to match.
153 return SP::G5; // "g5"
154 case '6': // 2 strings to match.
155 return SP::G6; // "g6"
156 case '7': // 1 string to match.
157 return SP::G7; // "g7"
158 case 'l': // 1 string to match.
159 return SP::GL; // "gl"
160 }
161 break;
162 case 'i': // 11 strings to match.
163 switch (Name[1]) {
164 default: break;
165 case '0': // 2 strings to match.
166 return SP::I0; // "i0"
167 case '1': // 1 string to match.
168 return SP::I1; // "i1"
169 case '2': // 2 strings to match.
170 return SP::I2; // "i2"
171 case '3': // 1 string to match.
172 return SP::I3; // "i3"
173 case '4': // 2 strings to match.
174 return SP::I4; // "i4"
175 case '5': // 1 string to match.
176 return SP::I5; // "i5"
177 case '6': // 1 string to match.
178 return SP::I6_I7; // "i6"
179 case '7': // 1 string to match.
180 return SP::I7; // "i7"
181 }
182 break;
183 case 'l': // 12 strings to match.
184 switch (Name[1]) {
185 default: break;
186 case '0': // 2 strings to match.
187 return SP::L0; // "l0"
188 case '1': // 1 string to match.
189 return SP::L1; // "l1"
190 case '2': // 2 strings to match.
191 return SP::L2; // "l2"
192 case '3': // 1 string to match.
193 return SP::L3; // "l3"
194 case '4': // 2 strings to match.
195 return SP::L4; // "l4"
196 case '5': // 1 string to match.
197 return SP::L5; // "l5"
198 case '6': // 2 strings to match.
199 return SP::L6; // "l6"
200 case '7': // 1 string to match.
201 return SP::L7; // "l7"
202 }
203 break;
204 case 'o': // 11 strings to match.
205 switch (Name[1]) {
206 default: break;
207 case '0': // 2 strings to match.
208 return SP::O0; // "o0"
209 case '1': // 1 string to match.
210 return SP::O1; // "o1"
211 case '2': // 2 strings to match.
212 return SP::O2; // "o2"
213 case '3': // 1 string to match.
214 return SP::O3; // "o3"
215 case '4': // 2 strings to match.
216 return SP::O4; // "o4"
217 case '5': // 1 string to match.
218 return SP::O5; // "o5"
219 case '6': // 1 string to match.
220 return SP::O6_O7; // "o6"
221 case '7': // 1 string to match.
222 return SP::O7; // "o7"
223 }
224 break;
225 case 's': // 1 string to match.
226 if (Name[1] != 'p')
227 break;
228 return SP::O6; // "sp"
229 case 't': // 2 strings to match.
230 switch (Name[1]) {
231 default: break;
232 case 'l': // 1 string to match.
233 return SP::TL; // "tl"
234 case 't': // 1 string to match.
235 return SP::TT; // "tt"
236 }
237 break;
238 }
239 break;
240 case 3: // 106 strings to match.
241 switch (Name[0]) {
242 default: break;
243 case 'c': // 35 strings to match.
244 switch (Name[1]) {
245 default: break;
246 case '1': // 15 strings to match.
247 switch (Name[2]) {
248 default: break;
249 case '0': // 2 strings to match.
250 return SP::C10; // "c10"
251 case '1': // 1 string to match.
252 return SP::C11; // "c11"
253 case '2': // 2 strings to match.
254 return SP::C12; // "c12"
255 case '3': // 1 string to match.
256 return SP::C13; // "c13"
257 case '4': // 2 strings to match.
258 return SP::C14; // "c14"
259 case '5': // 1 string to match.
260 return SP::C15; // "c15"
261 case '6': // 2 strings to match.
262 return SP::C16; // "c16"
263 case '7': // 1 string to match.
264 return SP::C17; // "c17"
265 case '8': // 2 strings to match.
266 return SP::C18; // "c18"
267 case '9': // 1 string to match.
268 return SP::C19; // "c19"
269 }
270 break;
271 case '2': // 15 strings to match.
272 switch (Name[2]) {
273 default: break;
274 case '0': // 2 strings to match.
275 return SP::C20; // "c20"
276 case '1': // 1 string to match.
277 return SP::C21; // "c21"
278 case '2': // 2 strings to match.
279 return SP::C22; // "c22"
280 case '3': // 1 string to match.
281 return SP::C23; // "c23"
282 case '4': // 2 strings to match.
283 return SP::C24; // "c24"
284 case '5': // 1 string to match.
285 return SP::C25; // "c25"
286 case '6': // 2 strings to match.
287 return SP::C26; // "c26"
288 case '7': // 1 string to match.
289 return SP::C27; // "c27"
290 case '8': // 2 strings to match.
291 return SP::C28; // "c28"
292 case '9': // 1 string to match.
293 return SP::C29; // "c29"
294 }
295 break;
296 case '3': // 3 strings to match.
297 switch (Name[2]) {
298 default: break;
299 case '0': // 2 strings to match.
300 return SP::C30; // "c30"
301 case '1': // 1 string to match.
302 return SP::C31; // "c31"
303 }
304 break;
305 case 's': // 1 string to match.
306 if (Name[2] != 'r')
307 break;
308 return SP::CPSR; // "csr"
309 case 'w': // 1 string to match.
310 if (Name[2] != 'p')
311 break;
312 return SP::CWP; // "cwp"
313 }
314 break;
315 case 'f': // 63 strings to match.
316 switch (Name[1]) {
317 default: break;
318 case '1': // 17 strings to match.
319 switch (Name[2]) {
320 default: break;
321 case '0': // 2 strings to match.
322 return SP::D5; // "f10"
323 case '1': // 1 string to match.
324 return SP::F11; // "f11"
325 case '2': // 3 strings to match.
326 return SP::D6; // "f12"
327 case '3': // 1 string to match.
328 return SP::F13; // "f13"
329 case '4': // 2 strings to match.
330 return SP::D7; // "f14"
331 case '5': // 1 string to match.
332 return SP::F15; // "f15"
333 case '6': // 3 strings to match.
334 return SP::D8; // "f16"
335 case '7': // 1 string to match.
336 return SP::F17; // "f17"
337 case '8': // 2 strings to match.
338 return SP::D9; // "f18"
339 case '9': // 1 string to match.
340 return SP::F19; // "f19"
341 }
342 break;
343 case '2': // 18 strings to match.
344 switch (Name[2]) {
345 default: break;
346 case '0': // 3 strings to match.
347 return SP::D10; // "f20"
348 case '1': // 1 string to match.
349 return SP::F21; // "f21"
350 case '2': // 2 strings to match.
351 return SP::D11; // "f22"
352 case '3': // 1 string to match.
353 return SP::F23; // "f23"
354 case '4': // 3 strings to match.
355 return SP::D12; // "f24"
356 case '5': // 1 string to match.
357 return SP::F25; // "f25"
358 case '6': // 2 strings to match.
359 return SP::D13; // "f26"
360 case '7': // 1 string to match.
361 return SP::F27; // "f27"
362 case '8': // 3 strings to match.
363 return SP::D14; // "f28"
364 case '9': // 1 string to match.
365 return SP::F29; // "f29"
366 }
367 break;
368 case '3': // 9 strings to match.
369 switch (Name[2]) {
370 default: break;
371 case '0': // 2 strings to match.
372 return SP::D15; // "f30"
373 case '1': // 1 string to match.
374 return SP::F31; // "f31"
375 case '2': // 2 strings to match.
376 return SP::D16; // "f32"
377 case '4': // 1 string to match.
378 return SP::D17; // "f34"
379 case '6': // 2 strings to match.
380 return SP::D18; // "f36"
381 case '8': // 1 string to match.
382 return SP::D19; // "f38"
383 }
384 break;
385 case '4': // 8 strings to match.
386 switch (Name[2]) {
387 default: break;
388 case '0': // 2 strings to match.
389 return SP::D20; // "f40"
390 case '2': // 1 string to match.
391 return SP::D21; // "f42"
392 case '4': // 2 strings to match.
393 return SP::D22; // "f44"
394 case '6': // 1 string to match.
395 return SP::D23; // "f46"
396 case '8': // 2 strings to match.
397 return SP::D24; // "f48"
398 }
399 break;
400 case '5': // 7 strings to match.
401 switch (Name[2]) {
402 default: break;
403 case '0': // 1 string to match.
404 return SP::D25; // "f50"
405 case '2': // 2 strings to match.
406 return SP::D26; // "f52"
407 case '4': // 1 string to match.
408 return SP::D27; // "f54"
409 case '6': // 2 strings to match.
410 return SP::D28; // "f56"
411 case '8': // 1 string to match.
412 return SP::D29; // "f58"
413 }
414 break;
415 case '6': // 3 strings to match.
416 switch (Name[2]) {
417 default: break;
418 case '0': // 2 strings to match.
419 return SP::D30; // "f60"
420 case '2': // 1 string to match.
421 return SP::D31; // "f62"
422 }
423 break;
424 case 's': // 1 string to match.
425 if (Name[2] != 'r')
426 break;
427 return SP::FSR; // "fsr"
428 }
429 break;
430 case 'i': // 1 string to match.
431 if (memcmp(Name.data()+1, "cc", 2) != 0)
432 break;
433 return SP::ICC; // "icc"
434 case 'p': // 2 strings to match.
435 switch (Name[1]) {
436 default: break;
437 case 'i': // 1 string to match.
438 if (Name[2] != 'l')
439 break;
440 return SP::PIL; // "pil"
441 case 's': // 1 string to match.
442 if (Name[2] != 'r')
443 break;
444 return SP::PSR; // "psr"
445 }
446 break;
447 case 't': // 3 strings to match.
448 switch (Name[1]) {
449 default: break;
450 case 'b': // 2 strings to match.
451 switch (Name[2]) {
452 default: break;
453 case 'a': // 1 string to match.
454 return SP::TBA; // "tba"
455 case 'r': // 1 string to match.
456 return SP::TBR; // "tbr"
457 }
458 break;
459 case 'p': // 1 string to match.
460 if (Name[2] != 'c')
461 break;
462 return SP::TPC; // "tpc"
463 }
464 break;
465 case 'v': // 1 string to match.
466 if (memcmp(Name.data()+1, "er", 2) != 0)
467 break;
468 return SP::VER; // "ver"
469 case 'w': // 1 string to match.
470 if (memcmp(Name.data()+1, "im", 2) != 0)
471 break;
472 return SP::WIM; // "wim"
473 }
474 break;
475 case 4: // 15 strings to match.
476 switch (Name[0]) {
477 default: break;
478 case 'a': // 9 strings to match.
479 if (memcmp(Name.data()+1, "sr", 2) != 0)
480 break;
481 switch (Name[3]) {
482 default: break;
483 case '1': // 1 string to match.
484 return SP::ASR1; // "asr1"
485 case '2': // 1 string to match.
486 return SP::ASR2; // "asr2"
487 case '3': // 1 string to match.
488 return SP::ASR3; // "asr3"
489 case '4': // 1 string to match.
490 return SP::ASR4; // "asr4"
491 case '5': // 1 string to match.
492 return SP::ASR5; // "asr5"
493 case '6': // 1 string to match.
494 return SP::ASR6; // "asr6"
495 case '7': // 1 string to match.
496 return SP::ASR7; // "asr7"
497 case '8': // 1 string to match.
498 return SP::ASR8; // "asr8"
499 case '9': // 1 string to match.
500 return SP::ASR9; // "asr9"
501 }
502 break;
503 case 'f': // 4 strings to match.
504 if (memcmp(Name.data()+1, "cc", 2) != 0)
505 break;
506 switch (Name[3]) {
507 default: break;
508 case '0': // 1 string to match.
509 return SP::FCC0; // "fcc0"
510 case '1': // 1 string to match.
511 return SP::FCC1; // "fcc1"
512 case '2': // 1 string to match.
513 return SP::FCC2; // "fcc2"
514 case '3': // 1 string to match.
515 return SP::FCC3; // "fcc3"
516 }
517 break;
518 case 't': // 2 strings to match.
519 switch (Name[1]) {
520 default: break;
521 case 'i': // 1 string to match.
522 if (memcmp(Name.data()+2, "ck", 2) != 0)
523 break;
524 return SP::TICK; // "tick"
525 case 'n': // 1 string to match.
526 if (memcmp(Name.data()+2, "pc", 2) != 0)
527 break;
528 return SP::TNPC; // "tnpc"
529 }
530 break;
531 }
532 break;
533 case 5: // 22 strings to match.
534 if (memcmp(Name.data()+0, "asr", 3) != 0)
535 break;
536 switch (Name[3]) {
537 default: break;
538 case '1': // 10 strings to match.
539 switch (Name[4]) {
540 default: break;
541 case '0': // 1 string to match.
542 return SP::ASR10; // "asr10"
543 case '1': // 1 string to match.
544 return SP::ASR11; // "asr11"
545 case '2': // 1 string to match.
546 return SP::ASR12; // "asr12"
547 case '3': // 1 string to match.
548 return SP::ASR13; // "asr13"
549 case '4': // 1 string to match.
550 return SP::ASR14; // "asr14"
551 case '5': // 1 string to match.
552 return SP::ASR15; // "asr15"
553 case '6': // 1 string to match.
554 return SP::ASR16; // "asr16"
555 case '7': // 1 string to match.
556 return SP::ASR17; // "asr17"
557 case '8': // 1 string to match.
558 return SP::ASR18; // "asr18"
559 case '9': // 1 string to match.
560 return SP::ASR19; // "asr19"
561 }
562 break;
563 case '2': // 10 strings to match.
564 switch (Name[4]) {
565 default: break;
566 case '0': // 1 string to match.
567 return SP::ASR20; // "asr20"
568 case '1': // 1 string to match.
569 return SP::ASR21; // "asr21"
570 case '2': // 1 string to match.
571 return SP::ASR22; // "asr22"
572 case '3': // 1 string to match.
573 return SP::ASR23; // "asr23"
574 case '4': // 1 string to match.
575 return SP::ASR24; // "asr24"
576 case '5': // 1 string to match.
577 return SP::ASR25; // "asr25"
578 case '6': // 1 string to match.
579 return SP::ASR26; // "asr26"
580 case '7': // 1 string to match.
581 return SP::ASR27; // "asr27"
582 case '8': // 1 string to match.
583 return SP::ASR28; // "asr28"
584 case '9': // 1 string to match.
585 return SP::ASR29; // "asr29"
586 }
587 break;
588 case '3': // 2 strings to match.
589 switch (Name[4]) {
590 default: break;
591 case '0': // 1 string to match.
592 return SP::ASR30; // "asr30"
593 case '1': // 1 string to match.
594 return SP::ASR31; // "asr31"
595 }
596 break;
597 }
598 break;
599 case 6: // 3 strings to match.
600 switch (Name[0]) {
601 default: break;
602 case 'p': // 1 string to match.
603 if (memcmp(Name.data()+1, "state", 5) != 0)
604 break;
605 return SP::PSTATE; // "pstate"
606 case 't': // 1 string to match.
607 if (memcmp(Name.data()+1, "state", 5) != 0)
608 break;
609 return SP::TSTATE; // "tstate"
610 case 'w': // 1 string to match.
611 if (memcmp(Name.data()+1, "state", 5) != 0)
612 break;
613 return SP::WSTATE; // "wstate"
614 }
615 break;
616 case 7: // 1 string to match.
617 if (memcmp(Name.data()+0, "cansave", 7) != 0)
618 break;
619 return SP::CANSAVE; // "cansave"
620 case 8: // 2 strings to match.
621 switch (Name[0]) {
622 default: break;
623 case 'c': // 1 string to match.
624 if (memcmp(Name.data()+1, "leanwin", 7) != 0)
625 break;
626 return SP::CLEANWIN; // "cleanwin"
627 case 'o': // 1 string to match.
628 if (memcmp(Name.data()+1, "therwin", 7) != 0)
629 break;
630 return SP::OTHERWIN; // "otherwin"
631 }
632 break;
633 case 10: // 1 string to match.
634 if (memcmp(Name.data()+0, "canrestore", 10) != 0)
635 break;
636 return SP::CANRESTORE; // "canrestore"
637 }
638 return SP::NoRegister;
639}
640
641static MCRegister MatchRegisterAltName(StringRef Name) {
642 switch (Name.size()) {
643 default: break;
644 case 2: // 1 string to match.
645 if (memcmp(Name.data()+0, "pc", 2) != 0)
646 break;
647 return SP::ASR5; // "pc"
648 case 3: // 2 strings to match.
649 switch (Name[0]) {
650 default: break;
651 case 'a': // 1 string to match.
652 if (memcmp(Name.data()+1, "si", 2) != 0)
653 break;
654 return SP::ASR3; // "asi"
655 case 'c': // 1 string to match.
656 if (memcmp(Name.data()+1, "cr", 2) != 0)
657 break;
658 return SP::ASR2; // "ccr"
659 }
660 break;
661 case 4: // 2 strings to match.
662 switch (Name[0]) {
663 default: break;
664 case 'f': // 1 string to match.
665 if (memcmp(Name.data()+1, "prs", 3) != 0)
666 break;
667 return SP::ASR6; // "fprs"
668 case 't': // 1 string to match.
669 if (memcmp(Name.data()+1, "ick", 3) != 0)
670 break;
671 return SP::ASR4; // "tick"
672 }
673 break;
674 }
675 return SP::NoRegister;
676}
677
678#endif // GET_REGISTER_MATCHER
679
680
681#ifdef GET_SUBTARGET_FEATURE_NAME
682#undef GET_SUBTARGET_FEATURE_NAME
683
684// User-level names for subtarget features that participate in
685// instruction matching.
686static const char *getSubtargetFeatureName(uint64_t Val) {
687 switch(Val) {
688 case Feature_Is32BitBit: return "";
689 case Feature_Is64BitBit: return "";
690 case Feature_UseSoftMulDivBit: return "";
691 case Feature_HasV9Bit: return "";
692 case Feature_HasVISBit: return "";
693 case Feature_HasVIS2Bit: return "";
694 case Feature_HasVIS3Bit: return "";
695 case Feature_HasUA2005Bit: return "";
696 case Feature_HasUA2007Bit: return "";
697 case Feature_HasOSA2011Bit: return "";
698 case Feature_HasCryptoBit: return "";
699 case Feature_HasCASABit: return "";
700 case Feature_HasPWRPSRBit: return "";
701 default: return "(unknown)";
702 }
703}
704
705#endif // GET_SUBTARGET_FEATURE_NAME
706
707
708#ifdef GET_MATCHER_IMPLEMENTATION
709#undef GET_MATCHER_IMPLEMENTATION
710
711static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
712 switch (Mnemonic.size()) {
713 default: break;
714 case 3: // 4 strings to match.
715 switch (Mnemonic[0]) {
716 default: break;
717 case 'l': // 2 strings to match.
718 switch (Mnemonic[1]) {
719 default: break;
720 case 'd': // 1 string to match.
721 if (Mnemonic[2] != 'n')
722 break;
723 if (Features.test(Feature_Is32BitBit)) // "ldn"
724 Mnemonic = "ld";
725 else if (Features.test(Feature_Is64BitBit))
726 Mnemonic = "ldx";
727 return;
728 case 'z': // 1 string to match.
729 if (Mnemonic[2] != 'd')
730 break;
731 Mnemonic = "lzcnt"; // "lzd"
732 return;
733 }
734 break;
735 case 's': // 2 strings to match.
736 if (Mnemonic[1] != 't')
737 break;
738 switch (Mnemonic[2]) {
739 default: break;
740 case 'n': // 1 string to match.
741 if (Features.test(Feature_Is32BitBit)) // "stn"
742 Mnemonic = "st";
743 else if (Features.test(Feature_Is64BitBit))
744 Mnemonic = "stx";
745 return;
746 case 'w': // 1 string to match.
747 if (Features.test(Feature_HasV9Bit)) // "stw"
748 Mnemonic = "st";
749 return;
750 }
751 break;
752 }
753 break;
754 case 4: // 17 strings to match.
755 switch (Mnemonic[0]) {
756 default: break;
757 case 'a': // 1 string to match.
758 if (memcmp(Mnemonic.data()+1, "ddc", 3) != 0)
759 break;
760 if (Features.test(Feature_HasV9Bit)) // "addc"
761 Mnemonic = "addx";
762 return;
763 case 'c': // 2 strings to match.
764 switch (Mnemonic[1]) {
765 default: break;
766 case 'a': // 1 string to match.
767 if (memcmp(Mnemonic.data()+2, "sn", 2) != 0)
768 break;
769 if (Features.test(Feature_Is32BitBit)) // "casn"
770 Mnemonic = "cas";
771 else if (Features.test(Feature_Is64BitBit))
772 Mnemonic = "casx";
773 return;
774 case 'l': // 1 string to match.
775 if (memcmp(Mnemonic.data()+2, "rn", 2) != 0)
776 break;
777 if (Features.test(Feature_Is32BitBit)) // "clrn"
778 Mnemonic = "clr";
779 else if (Features.test(Feature_Is64BitBit))
780 Mnemonic = "clrx";
781 return;
782 }
783 break;
784 case 'l': // 2 strings to match.
785 if (Mnemonic[1] != 'd')
786 break;
787 switch (Mnemonic[2]) {
788 default: break;
789 case 'n': // 1 string to match.
790 if (Mnemonic[3] != 'a')
791 break;
792 if (Features.test(Feature_Is32BitBit)) // "ldna"
793 Mnemonic = "lda";
794 else if (Features.test(Feature_Is64BitBit))
795 Mnemonic = "ldxa";
796 return;
797 case 'u': // 1 string to match.
798 if (Mnemonic[3] != 'w')
799 break;
800 if (Features.test(Feature_HasV9Bit)) // "lduw"
801 Mnemonic = "ld";
802 return;
803 }
804 break;
805 case 's': // 12 strings to match.
806 switch (Mnemonic[1]) {
807 default: break;
808 case 'l': // 1 string to match.
809 if (memcmp(Mnemonic.data()+2, "ln", 2) != 0)
810 break;
811 if (Features.test(Feature_Is32BitBit)) // "slln"
812 Mnemonic = "sll";
813 else if (Features.test(Feature_Is64BitBit))
814 Mnemonic = "sllx";
815 return;
816 case 'r': // 2 strings to match.
817 switch (Mnemonic[2]) {
818 default: break;
819 case 'a': // 1 string to match.
820 if (Mnemonic[3] != 'n')
821 break;
822 if (Features.test(Feature_Is32BitBit)) // "sran"
823 Mnemonic = "sra";
824 else if (Features.test(Feature_Is64BitBit))
825 Mnemonic = "srax";
826 return;
827 case 'l': // 1 string to match.
828 if (Mnemonic[3] != 'n')
829 break;
830 if (Features.test(Feature_Is32BitBit)) // "srln"
831 Mnemonic = "srl";
832 else if (Features.test(Feature_Is64BitBit))
833 Mnemonic = "srlx";
834 return;
835 }
836 break;
837 case 't': // 8 strings to match.
838 switch (Mnemonic[2]) {
839 default: break;
840 case 'n': // 1 string to match.
841 if (Mnemonic[3] != 'a')
842 break;
843 if (Features.test(Feature_Is32BitBit)) // "stna"
844 Mnemonic = "sta";
845 else if (Features.test(Feature_Is64BitBit))
846 Mnemonic = "stxa";
847 return;
848 case 's': // 3 strings to match.
849 switch (Mnemonic[3]) {
850 default: break;
851 case 'b': // 1 string to match.
852 Mnemonic = "stb"; // "stsb"
853 return;
854 case 'h': // 1 string to match.
855 Mnemonic = "sth"; // "stsh"
856 return;
857 case 'w': // 1 string to match.
858 if (Features.test(Feature_HasV9Bit)) // "stsw"
859 Mnemonic = "st";
860 return;
861 }
862 break;
863 case 'u': // 3 strings to match.
864 switch (Mnemonic[3]) {
865 default: break;
866 case 'b': // 1 string to match.
867 Mnemonic = "stb"; // "stub"
868 return;
869 case 'h': // 1 string to match.
870 Mnemonic = "sth"; // "stuh"
871 return;
872 case 'w': // 1 string to match.
873 if (Features.test(Feature_HasV9Bit)) // "stuw"
874 Mnemonic = "st";
875 return;
876 }
877 break;
878 case 'w': // 1 string to match.
879 if (Mnemonic[3] != 'a')
880 break;
881 if (Features.test(Feature_HasV9Bit)) // "stwa"
882 Mnemonic = "sta";
883 return;
884 }
885 break;
886 case 'u': // 1 string to match.
887 if (memcmp(Mnemonic.data()+2, "bc", 2) != 0)
888 break;
889 if (Features.test(Feature_HasV9Bit)) // "subc"
890 Mnemonic = "subx";
891 return;
892 }
893 break;
894 }
895 break;
896 case 5: // 8 strings to match.
897 switch (Mnemonic[0]) {
898 default: break;
899 case 'l': // 1 string to match.
900 if (memcmp(Mnemonic.data()+1, "duwa", 4) != 0)
901 break;
902 if (Features.test(Feature_HasV9Bit)) // "lduwa"
903 Mnemonic = "lda";
904 return;
905 case 's': // 7 strings to match.
906 switch (Mnemonic[1]) {
907 default: break;
908 case 'e': // 1 string to match.
909 if (memcmp(Mnemonic.data()+2, "tuw", 3) != 0)
910 break;
911 if (Features.test(Feature_HasV9Bit)) // "setuw"
912 Mnemonic = "set";
913 return;
914 case 't': // 6 strings to match.
915 switch (Mnemonic[2]) {
916 default: break;
917 case 's': // 3 strings to match.
918 switch (Mnemonic[3]) {
919 default: break;
920 case 'b': // 1 string to match.
921 if (Mnemonic[4] != 'a')
922 break;
923 Mnemonic = "stba"; // "stsba"
924 return;
925 case 'h': // 1 string to match.
926 if (Mnemonic[4] != 'a')
927 break;
928 Mnemonic = "stha"; // "stsha"
929 return;
930 case 'w': // 1 string to match.
931 if (Mnemonic[4] != 'a')
932 break;
933 if (Features.test(Feature_HasV9Bit)) // "stswa"
934 Mnemonic = "sta";
935 return;
936 }
937 break;
938 case 'u': // 3 strings to match.
939 switch (Mnemonic[3]) {
940 default: break;
941 case 'b': // 1 string to match.
942 if (Mnemonic[4] != 'a')
943 break;
944 Mnemonic = "stba"; // "stuba"
945 return;
946 case 'h': // 1 string to match.
947 if (Mnemonic[4] != 'a')
948 break;
949 Mnemonic = "stha"; // "stuha"
950 return;
951 case 'w': // 1 string to match.
952 if (Mnemonic[4] != 'a')
953 break;
954 if (Features.test(Feature_HasV9Bit)) // "stuwa"
955 Mnemonic = "sta";
956 return;
957 }
958 break;
959 }
960 break;
961 }
962 break;
963 }
964 break;
965 case 6: // 4 strings to match.
966 switch (Mnemonic[0]) {
967 default: break;
968 case 'a': // 1 string to match.
969 if (memcmp(Mnemonic.data()+1, "ddccc", 5) != 0)
970 break;
971 if (Features.test(Feature_HasV9Bit)) // "addccc"
972 Mnemonic = "addxcc";
973 return;
974 case 'i': // 1 string to match.
975 if (memcmp(Mnemonic.data()+1, "flush", 5) != 0)
976 break;
977 Mnemonic = "flush"; // "iflush"
978 return;
979 case 'r': // 1 string to match.
980 if (memcmp(Mnemonic.data()+1, "eturn", 5) != 0)
981 break;
982 if (Features.test(Feature_HasV9Bit)) // "return"
983 Mnemonic = "rett";
984 return;
985 case 's': // 1 string to match.
986 if (memcmp(Mnemonic.data()+1, "ubccc", 5) != 0)
987 break;
988 if (Features.test(Feature_HasV9Bit)) // "subccc"
989 Mnemonic = "subxcc";
990 return;
991 }
992 break;
993 case 7: // 1 string to match.
994 if (memcmp(Mnemonic.data()+0, "illtrap", 7) != 0)
995 break;
996 Mnemonic = "unimp"; // "illtrap"
997 return;
998 }
999}
1000
1001enum {
1002 Tie0_1_1,
1003 Tie0_3_3,
1004 Tie0_5_5,
1005};
1006
1007static const uint8_t TiedAsmOperandTable[][3] = {
1008 /* Tie0_1_1 */ { 0, 1, 1 },
1009 /* Tie0_3_3 */ { 0, 3, 3 },
1010 /* Tie0_5_5 */ { 0, 5, 5 },
1011};
1012
1013namespace {
1014enum OperatorConversionKind {
1015 CVT_Done,
1016 CVT_Reg,
1017 CVT_Tied,
1018 CVT_95_Reg,
1019 CVT_95_addImmOperands,
1020 CVT_95_addTailRelocSymOperands,
1021 CVT_imm_95_8,
1022 CVT_imm_95_13,
1023 CVT_imm_95_5,
1024 CVT_imm_95_1,
1025 CVT_imm_95_10,
1026 CVT_imm_95_11,
1027 CVT_imm_95_12,
1028 CVT_imm_95_3,
1029 CVT_imm_95_2,
1030 CVT_imm_95_4,
1031 CVT_imm_95_0,
1032 CVT_imm_95_9,
1033 CVT_imm_95_6,
1034 CVT_imm_95_14,
1035 CVT_imm_95_7,
1036 CVT_regG0,
1037 CVT_imm_95_15,
1038 CVT_95_addCallTargetOperands,
1039 CVT_regO7,
1040 CVT_95_addMEMriOperands,
1041 CVT_95_addMEMrrOperands,
1042 CVT_imm_95_128,
1043 CVT_95_addASITagOperands,
1044 CVT_imm_95_136,
1045 CVT_regFCC0,
1046 CVT_95_addMembarTagOperands,
1047 CVT_regASR27,
1048 CVT_95_addPrefetchTagOperands,
1049 CVT_95_addShiftAmtImm5Operands,
1050 CVT_95_addShiftAmtImm6Operands,
1051 CVT_NUM_CONVERTERS
1052};
1053
1054enum InstructionConversionKind {
1055 Convert__Reg1_2__Reg1_0__Reg1_1,
1056 Convert__Reg1_2__Reg1_0__Imm1_1,
1057 Convert__Reg1_2__Reg1_0__Reg1_1__TailRelocSymAdd_TLS1_3,
1058 Convert__Reg1_2__Reg1_1__Imm1_0,
1059 Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2,
1060 Convert__Reg1_3__Reg1_0__Reg1_1__Imm1_2,
1061 Convert_NoOperands,
1062 Convert__Imm1_0__imm_95_8,
1063 Convert__Imm1_1__imm_95_8,
1064 Convert__Imm1_1__Imm1_0,
1065 Convert__Imm1_2__imm_95_8,
1066 Convert__Imm1_2__Imm1_0,
1067 Convert__Imm1_3__imm_95_8,
1068 Convert__Imm1_3__Imm1_0,
1069 Convert__Imm1_4__Imm1_0,
1070 Convert__Imm1_0,
1071 Convert__Imm1_0__imm_95_13,
1072 Convert__Imm1_1__imm_95_13,
1073 Convert__Imm1_2__imm_95_13,
1074 Convert__Imm1_3__imm_95_13,
1075 Convert__Reg1_1__Reg1_1__Reg1_0,
1076 Convert__Reg1_1__Reg1_1__Imm1_0,
1077 Convert__Imm1_0__imm_95_5,
1078 Convert__Imm1_1__imm_95_5,
1079 Convert__Imm1_2__imm_95_5,
1080 Convert__Imm1_3__imm_95_5,
1081 Convert__Imm1_0__imm_95_1,
1082 Convert__Imm1_1__imm_95_1,
1083 Convert__Imm1_2__imm_95_1,
1084 Convert__Imm1_3__imm_95_1,
1085 Convert__Imm1_0__imm_95_10,
1086 Convert__Imm1_1__imm_95_10,
1087 Convert__Imm1_2__imm_95_10,
1088 Convert__Imm1_3__imm_95_10,
1089 Convert__Imm1_0__imm_95_11,
1090 Convert__Imm1_1__imm_95_11,
1091 Convert__Imm1_2__imm_95_11,
1092 Convert__Imm1_3__imm_95_11,
1093 Convert__Imm1_0__imm_95_12,
1094 Convert__Imm1_1__imm_95_12,
1095 Convert__Imm1_2__imm_95_12,
1096 Convert__Imm1_3__imm_95_12,
1097 Convert__Imm1_0__imm_95_3,
1098 Convert__Imm1_1__imm_95_3,
1099 Convert__Imm1_2__imm_95_3,
1100 Convert__Imm1_3__imm_95_3,
1101 Convert__Imm1_0__imm_95_2,
1102 Convert__Imm1_1__imm_95_2,
1103 Convert__Imm1_2__imm_95_2,
1104 Convert__Imm1_3__imm_95_2,
1105 Convert__Imm1_0__imm_95_4,
1106 Convert__Imm1_1__imm_95_4,
1107 Convert__Imm1_2__imm_95_4,
1108 Convert__Imm1_3__imm_95_4,
1109 Convert__Imm1_0__imm_95_0,
1110 Convert__Imm1_1__imm_95_0,
1111 Convert__Imm1_2__imm_95_0,
1112 Convert__Imm1_3__imm_95_0,
1113 Convert__Imm1_0__imm_95_9,
1114 Convert__Imm1_1__imm_95_9,
1115 Convert__Imm1_2__imm_95_9,
1116 Convert__Imm1_3__imm_95_9,
1117 Convert__Imm1_0__imm_95_6,
1118 Convert__Imm1_1__imm_95_6,
1119 Convert__Imm1_2__imm_95_6,
1120 Convert__Imm1_3__imm_95_6,
1121 Convert__Imm1_0__imm_95_14,
1122 Convert__Imm1_1__imm_95_14,
1123 Convert__Imm1_2__imm_95_14,
1124 Convert__Imm1_3__imm_95_14,
1125 Convert__Imm1_2__Imm1_0__Reg1_1,
1126 Convert__Imm1_3__Imm1_0__Reg1_2,
1127 Convert__Imm1_4__Imm1_0__Reg1_3,
1128 Convert__Imm1_1__imm_95_1__Reg1_0,
1129 Convert__Imm1_2__imm_95_1__Reg1_1,
1130 Convert__Imm1_3__imm_95_1__Reg1_2,
1131 Convert__Imm1_1__imm_95_7__Reg1_0,
1132 Convert__Imm1_2__imm_95_7__Reg1_1,
1133 Convert__Imm1_3__imm_95_7__Reg1_2,
1134 Convert__Imm1_1__imm_95_6__Reg1_0,
1135 Convert__Imm1_2__imm_95_6__Reg1_1,
1136 Convert__Imm1_3__imm_95_6__Reg1_2,
1137 Convert__Imm1_1__imm_95_2__Reg1_0,
1138 Convert__Imm1_2__imm_95_2__Reg1_1,
1139 Convert__Imm1_3__imm_95_2__Reg1_2,
1140 Convert__Imm1_1__imm_95_3__Reg1_0,
1141 Convert__Imm1_2__imm_95_3__Reg1_1,
1142 Convert__Imm1_3__imm_95_3__Reg1_2,
1143 Convert__Imm1_1__imm_95_5__Reg1_0,
1144 Convert__Imm1_2__imm_95_5__Reg1_1,
1145 Convert__Imm1_3__imm_95_5__Reg1_2,
1146 Convert__regG0__Reg1_1__Reg1_0,
1147 Convert__regG0__Reg1_1__Imm1_0,
1148 Convert__Imm1_0__imm_95_15,
1149 Convert__Imm1_1__imm_95_15,
1150 Convert__Imm1_2__imm_95_15,
1151 Convert__Imm1_3__imm_95_15,
1152 Convert__Imm1_0__imm_95_7,
1153 Convert__Imm1_1__imm_95_7,
1154 Convert__Imm1_2__imm_95_7,
1155 Convert__Imm1_3__imm_95_7,
1156 Convert__CallTarget1_0,
1157 Convert__regO7__MEMri2_0,
1158 Convert__regO7__MEMrr2_0,
1159 Convert__CallTarget1_0__Imm1_1,
1160 Convert__CallTarget1_0__TailRelocSymCall_TLS1_1,
1161 Convert__MEMri2_0__Imm1_1,
1162 Convert__MEMrr2_0__Imm1_1,
1163 Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_128,
1164 Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1,
1165 Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1__ASITag1_3,
1166 Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_136,
1167 Convert__Reg1_0__regG0__regG0,
1168 Convert__MEMri2_1__regG0,
1169 Convert__MEMrr2_1__regG0,
1170 Convert__Reg1_0,
1171 Convert__regG0__Reg1_0__Reg1_1,
1172 Convert__regG0__Reg1_0__Imm1_1,
1173 Convert__Imm1_3__Imm1_0__Reg1_1__Reg1_2,
1174 Convert__Imm1_3__Imm1_0__Reg1_1__Imm1_2,
1175 Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1,
1176 Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1,
1177 Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1,
1178 Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1,
1179 Convert__Imm1_2__imm_95_1__Reg1_0__Reg1_1,
1180 Convert__Imm1_2__imm_95_1__Reg1_0__Imm1_1,
1181 Convert__Imm1_2__imm_95_10__Reg1_0__Reg1_1,
1182 Convert__Imm1_2__imm_95_10__Reg1_0__Imm1_1,
1183 Convert__Imm1_2__imm_95_11__Reg1_0__Reg1_1,
1184 Convert__Imm1_2__imm_95_11__Reg1_0__Imm1_1,
1185 Convert__Imm1_2__imm_95_12__Reg1_0__Reg1_1,
1186 Convert__Imm1_2__imm_95_12__Reg1_0__Imm1_1,
1187 Convert__Imm1_2__imm_95_3__Reg1_0__Reg1_1,
1188 Convert__Imm1_2__imm_95_3__Reg1_0__Imm1_1,
1189 Convert__Imm1_2__imm_95_2__Reg1_0__Reg1_1,
1190 Convert__Imm1_2__imm_95_2__Reg1_0__Imm1_1,
1191 Convert__Imm1_2__imm_95_4__Reg1_0__Reg1_1,
1192 Convert__Imm1_2__imm_95_4__Reg1_0__Imm1_1,
1193 Convert__Imm1_2__imm_95_9__Reg1_0__Reg1_1,
1194 Convert__Imm1_2__imm_95_9__Reg1_0__Imm1_1,
1195 Convert__Imm1_2__imm_95_6__Reg1_0__Reg1_1,
1196 Convert__Imm1_2__imm_95_6__Reg1_0__Imm1_1,
1197 Convert__Imm1_2__imm_95_14__Reg1_0__Reg1_1,
1198 Convert__Imm1_2__imm_95_14__Reg1_0__Imm1_1,
1199 Convert__Imm1_2__imm_95_15__Reg1_0__Reg1_1,
1200 Convert__Imm1_2__imm_95_15__Reg1_0__Imm1_1,
1201 Convert__Imm1_2__imm_95_7__Reg1_0__Reg1_1,
1202 Convert__Imm1_2__imm_95_7__Reg1_0__Imm1_1,
1203 Convert__Reg1_0__Reg1_0__imm_95_1,
1204 Convert__Reg1_1__Reg1_0,
1205 Convert__Imm1_1__imm_95_8__Reg1_0,
1206 Convert__Imm1_2__imm_95_8__Reg1_1,
1207 Convert__Imm1_3__imm_95_8__Reg1_2,
1208 Convert__Imm1_1__imm_95_9__Reg1_0,
1209 Convert__Imm1_2__imm_95_9__Reg1_1,
1210 Convert__Imm1_3__imm_95_9__Reg1_2,
1211 Convert__Imm1_1__imm_95_11__Reg1_0,
1212 Convert__Imm1_2__imm_95_11__Reg1_1,
1213 Convert__Imm1_3__imm_95_11__Reg1_2,
1214 Convert__Imm1_1__imm_95_4__Reg1_0,
1215 Convert__Imm1_2__imm_95_4__Reg1_1,
1216 Convert__Imm1_3__imm_95_4__Reg1_2,
1217 Convert__Imm1_1__imm_95_13__Reg1_0,
1218 Convert__Imm1_2__imm_95_13__Reg1_1,
1219 Convert__Imm1_3__imm_95_13__Reg1_2,
1220 Convert__Imm1_1__imm_95_0__Reg1_0,
1221 Convert__Imm1_2__imm_95_0__Reg1_1,
1222 Convert__Imm1_3__imm_95_0__Reg1_2,
1223 Convert__Imm1_1__imm_95_15__Reg1_0,
1224 Convert__Imm1_2__imm_95_15__Reg1_1,
1225 Convert__Imm1_3__imm_95_15__Reg1_2,
1226 Convert__Imm1_1__imm_95_10__Reg1_0,
1227 Convert__Imm1_2__imm_95_10__Reg1_1,
1228 Convert__Imm1_3__imm_95_10__Reg1_2,
1229 Convert__Imm1_1__imm_95_12__Reg1_0,
1230 Convert__Imm1_2__imm_95_12__Reg1_1,
1231 Convert__Imm1_3__imm_95_12__Reg1_2,
1232 Convert__Imm1_1__imm_95_14__Reg1_0,
1233 Convert__Imm1_2__imm_95_14__Reg1_1,
1234 Convert__Imm1_3__imm_95_14__Reg1_2,
1235 Convert__regFCC0__Reg1_0__Reg1_1,
1236 Convert__Reg1_0__Reg1_1__Reg1_2,
1237 Convert__MEMri2_0,
1238 Convert__MEMrr2_0,
1239 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8,
1240 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8,
1241 Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0,
1242 Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0,
1243 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13,
1244 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5,
1245 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1,
1246 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9,
1247 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10,
1248 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6,
1249 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11,
1250 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11,
1251 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12,
1252 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3,
1253 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4,
1254 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2,
1255 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13,
1256 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4,
1257 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2,
1258 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0,
1259 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0,
1260 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9,
1261 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1,
1262 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6,
1263 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15,
1264 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14,
1265 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7,
1266 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10,
1267 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5,
1268 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12,
1269 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3,
1270 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14,
1271 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15,
1272 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7,
1273 Convert__regG0__MEMri2_0,
1274 Convert__regG0__MEMrr2_0,
1275 Convert__Reg1_1__MEMri2_0,
1276 Convert__Reg1_1__MEMrr2_0,
1277 Convert__MEMri2_1,
1278 Convert__Reg1_3__MEMri2_1,
1279 Convert__MEMrr2_1,
1280 Convert__Reg1_3__MEMrr2_1,
1281 Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_GOT1_4,
1282 Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_TLS1_4,
1283 Convert__Reg1_4__MEMri2_1,
1284 Convert__Reg1_4__MEMrr2_1__ASITag1_3,
1285 Convert__MembarTag1_0,
1286 Convert__Reg1_1,
1287 Convert__regG0__Reg1_0,
1288 Convert__Reg1_1__regG0__Reg1_0,
1289 Convert__regG0__Imm1_0,
1290 Convert__Reg1_1__regG0__Imm1_0,
1291 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8,
1292 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_8,
1293 Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0,
1294 Convert__Reg1_3__Reg1_1__Imm1_2__Tie0_1_1__Imm1_0,
1295 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13,
1296 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5,
1297 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1,
1298 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_9,
1299 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10,
1300 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_6,
1301 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11,
1302 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_11,
1303 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12,
1304 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3,
1305 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_4,
1306 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2,
1307 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_13,
1308 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4,
1309 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_2,
1310 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0,
1311 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_0,
1312 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9,
1313 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1,
1314 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6,
1315 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_15,
1316 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14,
1317 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_7,
1318 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_3,
1319 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5,
1320 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_10,
1321 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_12,
1322 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_14,
1323 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15,
1324 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7,
1325 Convert__Reg1_0__regG0__Reg1_0,
1326 Convert__Reg1_0__Reg1_0__regG0,
1327 Convert__Reg1_1__Reg1_0__regG0,
1328 Convert__regASR27__regG0__Reg1_0,
1329 Convert__regASR27__regG0__Imm1_0,
1330 Convert__MEMri2_1__PrefetchTag1_3,
1331 Convert__MEMrr2_1__PrefetchTag1_3,
1332 Convert__MEMri2_1__PrefetchTag1_4,
1333 Convert__MEMrr2_1__ASITag1_3__PrefetchTag1_4,
1334 Convert__Reg1_0__Reg1_1,
1335 Convert__Reg1_0__Imm1_1,
1336 Convert__regG0__regG0__regG0,
1337 Convert__imm_95_8,
1338 Convert__Reg1_1__Imm1_0,
1339 Convert__Reg1_2__Imm1_0__Reg1_1,
1340 Convert__imm_95_0,
1341 Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1,
1342 Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1,
1343 Convert__MEMri2_2,
1344 Convert__MEMrr2_2,
1345 Convert__MEMri2_2__Reg1_0,
1346 Convert__MEMrr2_2__Reg1_0,
1347 Convert__MEMrr2_2__Reg1_0__ASITag1_4,
1348 Convert__Reg1_3__MEMri2_1__Tie0_1_1,
1349 Convert__Reg1_3__MEMrr2_1__Tie0_1_1,
1350 Convert__Reg1_4__MEMri2_1__Tie0_1_1,
1351 Convert__Reg1_4__MEMrr2_1__ASITag1_3__Tie0_1_1,
1352 Convert__regG0__Reg1_0__imm_95_8,
1353 Convert__regG0__Imm1_0__imm_95_8,
1354 Convert__regG0__Reg1_1__imm_95_8,
1355 Convert__regG0__Imm1_1__imm_95_8,
1356 Convert__Reg1_0__Reg1_2__imm_95_8,
1357 Convert__Reg1_0__Imm1_2__imm_95_8,
1358 Convert__Reg1_1__Reg1_3__imm_95_8,
1359 Convert__Reg1_1__Imm1_3__imm_95_8,
1360 Convert__Reg1_1__Reg1_3__Imm1_0,
1361 Convert__Reg1_1__Imm1_3__Imm1_0,
1362 Convert__Reg1_2__Reg1_4__Imm1_0,
1363 Convert__Reg1_2__Imm1_4__Imm1_0,
1364 Convert__regG0__Reg1_0__imm_95_13,
1365 Convert__regG0__Imm1_0__imm_95_13,
1366 Convert__regG0__Reg1_1__imm_95_13,
1367 Convert__regG0__Imm1_1__imm_95_13,
1368 Convert__Reg1_0__Reg1_2__imm_95_13,
1369 Convert__Reg1_0__Imm1_2__imm_95_13,
1370 Convert__Reg1_1__Reg1_3__imm_95_13,
1371 Convert__Reg1_1__Imm1_3__imm_95_13,
1372 Convert__regG0__Reg1_0__imm_95_5,
1373 Convert__regG0__Imm1_0__imm_95_5,
1374 Convert__regG0__Reg1_1__imm_95_5,
1375 Convert__regG0__Imm1_1__imm_95_5,
1376 Convert__Reg1_0__Reg1_2__imm_95_5,
1377 Convert__Reg1_0__Imm1_2__imm_95_5,
1378 Convert__Reg1_1__Reg1_3__imm_95_5,
1379 Convert__Reg1_1__Imm1_3__imm_95_5,
1380 Convert__regG0__Reg1_0__imm_95_1,
1381 Convert__regG0__Imm1_0__imm_95_1,
1382 Convert__regG0__Reg1_1__imm_95_1,
1383 Convert__regG0__Imm1_1__imm_95_1,
1384 Convert__Reg1_0__Reg1_2__imm_95_1,
1385 Convert__Reg1_0__Imm1_2__imm_95_1,
1386 Convert__Reg1_1__Reg1_3__imm_95_1,
1387 Convert__Reg1_1__Imm1_3__imm_95_1,
1388 Convert__regG0__Reg1_0__imm_95_10,
1389 Convert__regG0__Imm1_0__imm_95_10,
1390 Convert__regG0__Reg1_1__imm_95_10,
1391 Convert__regG0__Imm1_1__imm_95_10,
1392 Convert__Reg1_0__Reg1_2__imm_95_10,
1393 Convert__Reg1_0__Imm1_2__imm_95_10,
1394 Convert__Reg1_1__Reg1_3__imm_95_10,
1395 Convert__Reg1_1__Imm1_3__imm_95_10,
1396 Convert__regG0__Reg1_0__imm_95_11,
1397 Convert__regG0__Imm1_0__imm_95_11,
1398 Convert__regG0__Reg1_1__imm_95_11,
1399 Convert__regG0__Imm1_1__imm_95_11,
1400 Convert__Reg1_0__Reg1_2__imm_95_11,
1401 Convert__Reg1_0__Imm1_2__imm_95_11,
1402 Convert__Reg1_1__Reg1_3__imm_95_11,
1403 Convert__Reg1_1__Imm1_3__imm_95_11,
1404 Convert__regG0__Reg1_0__imm_95_12,
1405 Convert__regG0__Imm1_0__imm_95_12,
1406 Convert__regG0__Reg1_1__imm_95_12,
1407 Convert__regG0__Imm1_1__imm_95_12,
1408 Convert__Reg1_0__Reg1_2__imm_95_12,
1409 Convert__Reg1_0__Imm1_2__imm_95_12,
1410 Convert__Reg1_1__Reg1_3__imm_95_12,
1411 Convert__Reg1_1__Imm1_3__imm_95_12,
1412 Convert__regG0__Reg1_0__imm_95_3,
1413 Convert__regG0__Imm1_0__imm_95_3,
1414 Convert__regG0__Reg1_1__imm_95_3,
1415 Convert__regG0__Imm1_1__imm_95_3,
1416 Convert__Reg1_0__Reg1_2__imm_95_3,
1417 Convert__Reg1_0__Imm1_2__imm_95_3,
1418 Convert__Reg1_1__Reg1_3__imm_95_3,
1419 Convert__Reg1_1__Imm1_3__imm_95_3,
1420 Convert__regG0__Reg1_0__imm_95_2,
1421 Convert__regG0__Imm1_0__imm_95_2,
1422 Convert__regG0__Reg1_1__imm_95_2,
1423 Convert__regG0__Imm1_1__imm_95_2,
1424 Convert__Reg1_0__Reg1_2__imm_95_2,
1425 Convert__Reg1_0__Imm1_2__imm_95_2,
1426 Convert__Reg1_1__Reg1_3__imm_95_2,
1427 Convert__Reg1_1__Imm1_3__imm_95_2,
1428 Convert__regG0__Reg1_0__imm_95_4,
1429 Convert__regG0__Imm1_0__imm_95_4,
1430 Convert__regG0__Reg1_1__imm_95_4,
1431 Convert__regG0__Imm1_1__imm_95_4,
1432 Convert__Reg1_0__Reg1_2__imm_95_4,
1433 Convert__Reg1_0__Imm1_2__imm_95_4,
1434 Convert__Reg1_1__Reg1_3__imm_95_4,
1435 Convert__Reg1_1__Imm1_3__imm_95_4,
1436 Convert__regG0__Reg1_0__imm_95_0,
1437 Convert__regG0__Imm1_0__imm_95_0,
1438 Convert__regG0__Reg1_1__imm_95_0,
1439 Convert__regG0__Imm1_1__imm_95_0,
1440 Convert__Reg1_0__Reg1_2__imm_95_0,
1441 Convert__Reg1_0__Imm1_2__imm_95_0,
1442 Convert__Reg1_1__Reg1_3__imm_95_0,
1443 Convert__Reg1_1__Imm1_3__imm_95_0,
1444 Convert__regG0__Reg1_0__imm_95_9,
1445 Convert__regG0__Imm1_0__imm_95_9,
1446 Convert__regG0__Reg1_1__imm_95_9,
1447 Convert__regG0__Imm1_1__imm_95_9,
1448 Convert__Reg1_0__Reg1_2__imm_95_9,
1449 Convert__Reg1_0__Imm1_2__imm_95_9,
1450 Convert__Reg1_1__Reg1_3__imm_95_9,
1451 Convert__Reg1_1__Imm1_3__imm_95_9,
1452 Convert__regG0__Reg1_0__imm_95_6,
1453 Convert__regG0__Imm1_0__imm_95_6,
1454 Convert__regG0__Reg1_1__imm_95_6,
1455 Convert__regG0__Imm1_1__imm_95_6,
1456 Convert__Reg1_0__Reg1_2__imm_95_6,
1457 Convert__Reg1_0__Imm1_2__imm_95_6,
1458 Convert__Reg1_1__Reg1_3__imm_95_6,
1459 Convert__Reg1_1__Imm1_3__imm_95_6,
1460 Convert__regG0__Reg1_0__imm_95_14,
1461 Convert__regG0__Imm1_0__imm_95_14,
1462 Convert__regG0__Reg1_1__imm_95_14,
1463 Convert__regG0__Imm1_1__imm_95_14,
1464 Convert__Reg1_0__Reg1_2__imm_95_14,
1465 Convert__Reg1_0__Imm1_2__imm_95_14,
1466 Convert__Reg1_1__Reg1_3__imm_95_14,
1467 Convert__Reg1_1__Imm1_3__imm_95_14,
1468 Convert__regG0__Reg1_0__regG0,
1469 Convert__regG0__Reg1_0__imm_95_15,
1470 Convert__regG0__Imm1_0__imm_95_15,
1471 Convert__regG0__Reg1_1__imm_95_15,
1472 Convert__regG0__Imm1_1__imm_95_15,
1473 Convert__Reg1_0__Reg1_2__imm_95_15,
1474 Convert__Reg1_0__Imm1_2__imm_95_15,
1475 Convert__Reg1_1__Reg1_3__imm_95_15,
1476 Convert__Reg1_1__Imm1_3__imm_95_15,
1477 Convert__regG0__Reg1_0__imm_95_7,
1478 Convert__regG0__Imm1_0__imm_95_7,
1479 Convert__regG0__Reg1_1__imm_95_7,
1480 Convert__regG0__Imm1_1__imm_95_7,
1481 Convert__Reg1_0__Reg1_2__imm_95_7,
1482 Convert__Reg1_0__Imm1_2__imm_95_7,
1483 Convert__Reg1_1__Reg1_3__imm_95_7,
1484 Convert__Reg1_1__Imm1_3__imm_95_7,
1485 CVT_NUM_SIGNATURES
1486};
1487
1488} // end anonymous namespace
1489
1490static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
1491 // Convert__Reg1_2__Reg1_0__Reg1_1
1492 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1493 // Convert__Reg1_2__Reg1_0__Imm1_1
1494 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1495 // Convert__Reg1_2__Reg1_0__Reg1_1__TailRelocSymAdd_TLS1_3
1496 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addTailRelocSymOperands, 4, CVT_Done },
1497 // Convert__Reg1_2__Reg1_1__Imm1_0
1498 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
1499 // Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2
1500 { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1501 // Convert__Reg1_3__Reg1_0__Reg1_1__Imm1_2
1502 { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1503 // Convert_NoOperands
1504 { CVT_Done },
1505 // Convert__Imm1_0__imm_95_8
1506 { CVT_95_addImmOperands, 1, CVT_imm_95_8, 0, CVT_Done },
1507 // Convert__Imm1_1__imm_95_8
1508 { CVT_95_addImmOperands, 2, CVT_imm_95_8, 0, CVT_Done },
1509 // Convert__Imm1_1__Imm1_0
1510 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
1511 // Convert__Imm1_2__imm_95_8
1512 { CVT_95_addImmOperands, 3, CVT_imm_95_8, 0, CVT_Done },
1513 // Convert__Imm1_2__Imm1_0
1514 { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
1515 // Convert__Imm1_3__imm_95_8
1516 { CVT_95_addImmOperands, 4, CVT_imm_95_8, 0, CVT_Done },
1517 // Convert__Imm1_3__Imm1_0
1518 { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
1519 // Convert__Imm1_4__Imm1_0
1520 { CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
1521 // Convert__Imm1_0
1522 { CVT_95_addImmOperands, 1, CVT_Done },
1523 // Convert__Imm1_0__imm_95_13
1524 { CVT_95_addImmOperands, 1, CVT_imm_95_13, 0, CVT_Done },
1525 // Convert__Imm1_1__imm_95_13
1526 { CVT_95_addImmOperands, 2, CVT_imm_95_13, 0, CVT_Done },
1527 // Convert__Imm1_2__imm_95_13
1528 { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_Done },
1529 // Convert__Imm1_3__imm_95_13
1530 { CVT_95_addImmOperands, 4, CVT_imm_95_13, 0, CVT_Done },
1531 // Convert__Reg1_1__Reg1_1__Reg1_0
1532 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
1533 // Convert__Reg1_1__Reg1_1__Imm1_0
1534 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
1535 // Convert__Imm1_0__imm_95_5
1536 { CVT_95_addImmOperands, 1, CVT_imm_95_5, 0, CVT_Done },
1537 // Convert__Imm1_1__imm_95_5
1538 { CVT_95_addImmOperands, 2, CVT_imm_95_5, 0, CVT_Done },
1539 // Convert__Imm1_2__imm_95_5
1540 { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_Done },
1541 // Convert__Imm1_3__imm_95_5
1542 { CVT_95_addImmOperands, 4, CVT_imm_95_5, 0, CVT_Done },
1543 // Convert__Imm1_0__imm_95_1
1544 { CVT_95_addImmOperands, 1, CVT_imm_95_1, 0, CVT_Done },
1545 // Convert__Imm1_1__imm_95_1
1546 { CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
1547 // Convert__Imm1_2__imm_95_1
1548 { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_Done },
1549 // Convert__Imm1_3__imm_95_1
1550 { CVT_95_addImmOperands, 4, CVT_imm_95_1, 0, CVT_Done },
1551 // Convert__Imm1_0__imm_95_10
1552 { CVT_95_addImmOperands, 1, CVT_imm_95_10, 0, CVT_Done },
1553 // Convert__Imm1_1__imm_95_10
1554 { CVT_95_addImmOperands, 2, CVT_imm_95_10, 0, CVT_Done },
1555 // Convert__Imm1_2__imm_95_10
1556 { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_Done },
1557 // Convert__Imm1_3__imm_95_10
1558 { CVT_95_addImmOperands, 4, CVT_imm_95_10, 0, CVT_Done },
1559 // Convert__Imm1_0__imm_95_11
1560 { CVT_95_addImmOperands, 1, CVT_imm_95_11, 0, CVT_Done },
1561 // Convert__Imm1_1__imm_95_11
1562 { CVT_95_addImmOperands, 2, CVT_imm_95_11, 0, CVT_Done },
1563 // Convert__Imm1_2__imm_95_11
1564 { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_Done },
1565 // Convert__Imm1_3__imm_95_11
1566 { CVT_95_addImmOperands, 4, CVT_imm_95_11, 0, CVT_Done },
1567 // Convert__Imm1_0__imm_95_12
1568 { CVT_95_addImmOperands, 1, CVT_imm_95_12, 0, CVT_Done },
1569 // Convert__Imm1_1__imm_95_12
1570 { CVT_95_addImmOperands, 2, CVT_imm_95_12, 0, CVT_Done },
1571 // Convert__Imm1_2__imm_95_12
1572 { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_Done },
1573 // Convert__Imm1_3__imm_95_12
1574 { CVT_95_addImmOperands, 4, CVT_imm_95_12, 0, CVT_Done },
1575 // Convert__Imm1_0__imm_95_3
1576 { CVT_95_addImmOperands, 1, CVT_imm_95_3, 0, CVT_Done },
1577 // Convert__Imm1_1__imm_95_3
1578 { CVT_95_addImmOperands, 2, CVT_imm_95_3, 0, CVT_Done },
1579 // Convert__Imm1_2__imm_95_3
1580 { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_Done },
1581 // Convert__Imm1_3__imm_95_3
1582 { CVT_95_addImmOperands, 4, CVT_imm_95_3, 0, CVT_Done },
1583 // Convert__Imm1_0__imm_95_2
1584 { CVT_95_addImmOperands, 1, CVT_imm_95_2, 0, CVT_Done },
1585 // Convert__Imm1_1__imm_95_2
1586 { CVT_95_addImmOperands, 2, CVT_imm_95_2, 0, CVT_Done },
1587 // Convert__Imm1_2__imm_95_2
1588 { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_Done },
1589 // Convert__Imm1_3__imm_95_2
1590 { CVT_95_addImmOperands, 4, CVT_imm_95_2, 0, CVT_Done },
1591 // Convert__Imm1_0__imm_95_4
1592 { CVT_95_addImmOperands, 1, CVT_imm_95_4, 0, CVT_Done },
1593 // Convert__Imm1_1__imm_95_4
1594 { CVT_95_addImmOperands, 2, CVT_imm_95_4, 0, CVT_Done },
1595 // Convert__Imm1_2__imm_95_4
1596 { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_Done },
1597 // Convert__Imm1_3__imm_95_4
1598 { CVT_95_addImmOperands, 4, CVT_imm_95_4, 0, CVT_Done },
1599 // Convert__Imm1_0__imm_95_0
1600 { CVT_95_addImmOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1601 // Convert__Imm1_1__imm_95_0
1602 { CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1603 // Convert__Imm1_2__imm_95_0
1604 { CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
1605 // Convert__Imm1_3__imm_95_0
1606 { CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_Done },
1607 // Convert__Imm1_0__imm_95_9
1608 { CVT_95_addImmOperands, 1, CVT_imm_95_9, 0, CVT_Done },
1609 // Convert__Imm1_1__imm_95_9
1610 { CVT_95_addImmOperands, 2, CVT_imm_95_9, 0, CVT_Done },
1611 // Convert__Imm1_2__imm_95_9
1612 { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_Done },
1613 // Convert__Imm1_3__imm_95_9
1614 { CVT_95_addImmOperands, 4, CVT_imm_95_9, 0, CVT_Done },
1615 // Convert__Imm1_0__imm_95_6
1616 { CVT_95_addImmOperands, 1, CVT_imm_95_6, 0, CVT_Done },
1617 // Convert__Imm1_1__imm_95_6
1618 { CVT_95_addImmOperands, 2, CVT_imm_95_6, 0, CVT_Done },
1619 // Convert__Imm1_2__imm_95_6
1620 { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_Done },
1621 // Convert__Imm1_3__imm_95_6
1622 { CVT_95_addImmOperands, 4, CVT_imm_95_6, 0, CVT_Done },
1623 // Convert__Imm1_0__imm_95_14
1624 { CVT_95_addImmOperands, 1, CVT_imm_95_14, 0, CVT_Done },
1625 // Convert__Imm1_1__imm_95_14
1626 { CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_Done },
1627 // Convert__Imm1_2__imm_95_14
1628 { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_Done },
1629 // Convert__Imm1_3__imm_95_14
1630 { CVT_95_addImmOperands, 4, CVT_imm_95_14, 0, CVT_Done },
1631 // Convert__Imm1_2__Imm1_0__Reg1_1
1632 { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
1633 // Convert__Imm1_3__Imm1_0__Reg1_2
1634 { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_Done },
1635 // Convert__Imm1_4__Imm1_0__Reg1_3
1636 { CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 1, CVT_95_Reg, 4, CVT_Done },
1637 // Convert__Imm1_1__imm_95_1__Reg1_0
1638 { CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
1639 // Convert__Imm1_2__imm_95_1__Reg1_1
1640 { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
1641 // Convert__Imm1_3__imm_95_1__Reg1_2
1642 { CVT_95_addImmOperands, 4, CVT_imm_95_1, 0, CVT_95_Reg, 3, CVT_Done },
1643 // Convert__Imm1_1__imm_95_7__Reg1_0
1644 { CVT_95_addImmOperands, 2, CVT_imm_95_7, 0, CVT_95_Reg, 1, CVT_Done },
1645 // Convert__Imm1_2__imm_95_7__Reg1_1
1646 { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_95_Reg, 2, CVT_Done },
1647 // Convert__Imm1_3__imm_95_7__Reg1_2
1648 { CVT_95_addImmOperands, 4, CVT_imm_95_7, 0, CVT_95_Reg, 3, CVT_Done },
1649 // Convert__Imm1_1__imm_95_6__Reg1_0
1650 { CVT_95_addImmOperands, 2, CVT_imm_95_6, 0, CVT_95_Reg, 1, CVT_Done },
1651 // Convert__Imm1_2__imm_95_6__Reg1_1
1652 { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_95_Reg, 2, CVT_Done },
1653 // Convert__Imm1_3__imm_95_6__Reg1_2
1654 { CVT_95_addImmOperands, 4, CVT_imm_95_6, 0, CVT_95_Reg, 3, CVT_Done },
1655 // Convert__Imm1_1__imm_95_2__Reg1_0
1656 { CVT_95_addImmOperands, 2, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
1657 // Convert__Imm1_2__imm_95_2__Reg1_1
1658 { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
1659 // Convert__Imm1_3__imm_95_2__Reg1_2
1660 { CVT_95_addImmOperands, 4, CVT_imm_95_2, 0, CVT_95_Reg, 3, CVT_Done },
1661 // Convert__Imm1_1__imm_95_3__Reg1_0
1662 { CVT_95_addImmOperands, 2, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
1663 // Convert__Imm1_2__imm_95_3__Reg1_1
1664 { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
1665 // Convert__Imm1_3__imm_95_3__Reg1_2
1666 { CVT_95_addImmOperands, 4, CVT_imm_95_3, 0, CVT_95_Reg, 3, CVT_Done },
1667 // Convert__Imm1_1__imm_95_5__Reg1_0
1668 { CVT_95_addImmOperands, 2, CVT_imm_95_5, 0, CVT_95_Reg, 1, CVT_Done },
1669 // Convert__Imm1_2__imm_95_5__Reg1_1
1670 { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_95_Reg, 2, CVT_Done },
1671 // Convert__Imm1_3__imm_95_5__Reg1_2
1672 { CVT_95_addImmOperands, 4, CVT_imm_95_5, 0, CVT_95_Reg, 3, CVT_Done },
1673 // Convert__regG0__Reg1_1__Reg1_0
1674 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
1675 // Convert__regG0__Reg1_1__Imm1_0
1676 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
1677 // Convert__Imm1_0__imm_95_15
1678 { CVT_95_addImmOperands, 1, CVT_imm_95_15, 0, CVT_Done },
1679 // Convert__Imm1_1__imm_95_15
1680 { CVT_95_addImmOperands, 2, CVT_imm_95_15, 0, CVT_Done },
1681 // Convert__Imm1_2__imm_95_15
1682 { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_Done },
1683 // Convert__Imm1_3__imm_95_15
1684 { CVT_95_addImmOperands, 4, CVT_imm_95_15, 0, CVT_Done },
1685 // Convert__Imm1_0__imm_95_7
1686 { CVT_95_addImmOperands, 1, CVT_imm_95_7, 0, CVT_Done },
1687 // Convert__Imm1_1__imm_95_7
1688 { CVT_95_addImmOperands, 2, CVT_imm_95_7, 0, CVT_Done },
1689 // Convert__Imm1_2__imm_95_7
1690 { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_Done },
1691 // Convert__Imm1_3__imm_95_7
1692 { CVT_95_addImmOperands, 4, CVT_imm_95_7, 0, CVT_Done },
1693 // Convert__CallTarget1_0
1694 { CVT_95_addCallTargetOperands, 1, CVT_Done },
1695 // Convert__regO7__MEMri2_0
1696 { CVT_regO7, 0, CVT_95_addMEMriOperands, 1, CVT_Done },
1697 // Convert__regO7__MEMrr2_0
1698 { CVT_regO7, 0, CVT_95_addMEMrrOperands, 1, CVT_Done },
1699 // Convert__CallTarget1_0__Imm1_1
1700 { CVT_95_addCallTargetOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1701 // Convert__CallTarget1_0__TailRelocSymCall_TLS1_1
1702 { CVT_95_addCallTargetOperands, 1, CVT_95_addTailRelocSymOperands, 2, CVT_Done },
1703 // Convert__MEMri2_0__Imm1_1
1704 { CVT_95_addMEMriOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1705 // Convert__MEMrr2_0__Imm1_1
1706 { CVT_95_addMEMrrOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1707 // Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_128
1708 { CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_5_5, CVT_imm_95_128, 0, CVT_Done },
1709 // Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1
1710 { CVT_95_Reg, 6, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Done },
1711 // Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1__ASITag1_3
1712 { CVT_95_Reg, 6, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_addASITagOperands, 4, CVT_Done },
1713 // Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_136
1714 { CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_5_5, CVT_imm_95_136, 0, CVT_Done },
1715 // Convert__Reg1_0__regG0__regG0
1716 { CVT_95_Reg, 1, CVT_regG0, 0, CVT_regG0, 0, CVT_Done },
1717 // Convert__MEMri2_1__regG0
1718 { CVT_95_addMEMriOperands, 2, CVT_regG0, 0, CVT_Done },
1719 // Convert__MEMrr2_1__regG0
1720 { CVT_95_addMEMrrOperands, 2, CVT_regG0, 0, CVT_Done },
1721 // Convert__Reg1_0
1722 { CVT_95_Reg, 1, CVT_Done },
1723 // Convert__regG0__Reg1_0__Reg1_1
1724 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1725 // Convert__regG0__Reg1_0__Imm1_1
1726 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1727 // Convert__Imm1_3__Imm1_0__Reg1_1__Reg1_2
1728 { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1729 // Convert__Imm1_3__Imm1_0__Reg1_1__Imm1_2
1730 { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1731 // Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1
1732 { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1733 // Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1
1734 { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1735 // Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1
1736 { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1737 // Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1
1738 { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1739 // Convert__Imm1_2__imm_95_1__Reg1_0__Reg1_1
1740 { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1741 // Convert__Imm1_2__imm_95_1__Reg1_0__Imm1_1
1742 { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1743 // Convert__Imm1_2__imm_95_10__Reg1_0__Reg1_1
1744 { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1745 // Convert__Imm1_2__imm_95_10__Reg1_0__Imm1_1
1746 { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1747 // Convert__Imm1_2__imm_95_11__Reg1_0__Reg1_1
1748 { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1749 // Convert__Imm1_2__imm_95_11__Reg1_0__Imm1_1
1750 { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1751 // Convert__Imm1_2__imm_95_12__Reg1_0__Reg1_1
1752 { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1753 // Convert__Imm1_2__imm_95_12__Reg1_0__Imm1_1
1754 { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1755 // Convert__Imm1_2__imm_95_3__Reg1_0__Reg1_1
1756 { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1757 // Convert__Imm1_2__imm_95_3__Reg1_0__Imm1_1
1758 { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1759 // Convert__Imm1_2__imm_95_2__Reg1_0__Reg1_1
1760 { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1761 // Convert__Imm1_2__imm_95_2__Reg1_0__Imm1_1
1762 { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1763 // Convert__Imm1_2__imm_95_4__Reg1_0__Reg1_1
1764 { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1765 // Convert__Imm1_2__imm_95_4__Reg1_0__Imm1_1
1766 { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1767 // Convert__Imm1_2__imm_95_9__Reg1_0__Reg1_1
1768 { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1769 // Convert__Imm1_2__imm_95_9__Reg1_0__Imm1_1
1770 { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1771 // Convert__Imm1_2__imm_95_6__Reg1_0__Reg1_1
1772 { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1773 // Convert__Imm1_2__imm_95_6__Reg1_0__Imm1_1
1774 { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1775 // Convert__Imm1_2__imm_95_14__Reg1_0__Reg1_1
1776 { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1777 // Convert__Imm1_2__imm_95_14__Reg1_0__Imm1_1
1778 { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1779 // Convert__Imm1_2__imm_95_15__Reg1_0__Reg1_1
1780 { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1781 // Convert__Imm1_2__imm_95_15__Reg1_0__Imm1_1
1782 { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1783 // Convert__Imm1_2__imm_95_7__Reg1_0__Reg1_1
1784 { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1785 // Convert__Imm1_2__imm_95_7__Reg1_0__Imm1_1
1786 { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1787 // Convert__Reg1_0__Reg1_0__imm_95_1
1788 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
1789 // Convert__Reg1_1__Reg1_0
1790 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
1791 // Convert__Imm1_1__imm_95_8__Reg1_0
1792 { CVT_95_addImmOperands, 2, CVT_imm_95_8, 0, CVT_95_Reg, 1, CVT_Done },
1793 // Convert__Imm1_2__imm_95_8__Reg1_1
1794 { CVT_95_addImmOperands, 3, CVT_imm_95_8, 0, CVT_95_Reg, 2, CVT_Done },
1795 // Convert__Imm1_3__imm_95_8__Reg1_2
1796 { CVT_95_addImmOperands, 4, CVT_imm_95_8, 0, CVT_95_Reg, 3, CVT_Done },
1797 // Convert__Imm1_1__imm_95_9__Reg1_0
1798 { CVT_95_addImmOperands, 2, CVT_imm_95_9, 0, CVT_95_Reg, 1, CVT_Done },
1799 // Convert__Imm1_2__imm_95_9__Reg1_1
1800 { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_95_Reg, 2, CVT_Done },
1801 // Convert__Imm1_3__imm_95_9__Reg1_2
1802 { CVT_95_addImmOperands, 4, CVT_imm_95_9, 0, CVT_95_Reg, 3, CVT_Done },
1803 // Convert__Imm1_1__imm_95_11__Reg1_0
1804 { CVT_95_addImmOperands, 2, CVT_imm_95_11, 0, CVT_95_Reg, 1, CVT_Done },
1805 // Convert__Imm1_2__imm_95_11__Reg1_1
1806 { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_95_Reg, 2, CVT_Done },
1807 // Convert__Imm1_3__imm_95_11__Reg1_2
1808 { CVT_95_addImmOperands, 4, CVT_imm_95_11, 0, CVT_95_Reg, 3, CVT_Done },
1809 // Convert__Imm1_1__imm_95_4__Reg1_0
1810 { CVT_95_addImmOperands, 2, CVT_imm_95_4, 0, CVT_95_Reg, 1, CVT_Done },
1811 // Convert__Imm1_2__imm_95_4__Reg1_1
1812 { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_95_Reg, 2, CVT_Done },
1813 // Convert__Imm1_3__imm_95_4__Reg1_2
1814 { CVT_95_addImmOperands, 4, CVT_imm_95_4, 0, CVT_95_Reg, 3, CVT_Done },
1815 // Convert__Imm1_1__imm_95_13__Reg1_0
1816 { CVT_95_addImmOperands, 2, CVT_imm_95_13, 0, CVT_95_Reg, 1, CVT_Done },
1817 // Convert__Imm1_2__imm_95_13__Reg1_1
1818 { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_95_Reg, 2, CVT_Done },
1819 // Convert__Imm1_3__imm_95_13__Reg1_2
1820 { CVT_95_addImmOperands, 4, CVT_imm_95_13, 0, CVT_95_Reg, 3, CVT_Done },
1821 // Convert__Imm1_1__imm_95_0__Reg1_0
1822 { CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_Done },
1823 // Convert__Imm1_2__imm_95_0__Reg1_1
1824 { CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_Done },
1825 // Convert__Imm1_3__imm_95_0__Reg1_2
1826 { CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_Done },
1827 // Convert__Imm1_1__imm_95_15__Reg1_0
1828 { CVT_95_addImmOperands, 2, CVT_imm_95_15, 0, CVT_95_Reg, 1, CVT_Done },
1829 // Convert__Imm1_2__imm_95_15__Reg1_1
1830 { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_95_Reg, 2, CVT_Done },
1831 // Convert__Imm1_3__imm_95_15__Reg1_2
1832 { CVT_95_addImmOperands, 4, CVT_imm_95_15, 0, CVT_95_Reg, 3, CVT_Done },
1833 // Convert__Imm1_1__imm_95_10__Reg1_0
1834 { CVT_95_addImmOperands, 2, CVT_imm_95_10, 0, CVT_95_Reg, 1, CVT_Done },
1835 // Convert__Imm1_2__imm_95_10__Reg1_1
1836 { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_95_Reg, 2, CVT_Done },
1837 // Convert__Imm1_3__imm_95_10__Reg1_2
1838 { CVT_95_addImmOperands, 4, CVT_imm_95_10, 0, CVT_95_Reg, 3, CVT_Done },
1839 // Convert__Imm1_1__imm_95_12__Reg1_0
1840 { CVT_95_addImmOperands, 2, CVT_imm_95_12, 0, CVT_95_Reg, 1, CVT_Done },
1841 // Convert__Imm1_2__imm_95_12__Reg1_1
1842 { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_95_Reg, 2, CVT_Done },
1843 // Convert__Imm1_3__imm_95_12__Reg1_2
1844 { CVT_95_addImmOperands, 4, CVT_imm_95_12, 0, CVT_95_Reg, 3, CVT_Done },
1845 // Convert__Imm1_1__imm_95_14__Reg1_0
1846 { CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_95_Reg, 1, CVT_Done },
1847 // Convert__Imm1_2__imm_95_14__Reg1_1
1848 { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_95_Reg, 2, CVT_Done },
1849 // Convert__Imm1_3__imm_95_14__Reg1_2
1850 { CVT_95_addImmOperands, 4, CVT_imm_95_14, 0, CVT_95_Reg, 3, CVT_Done },
1851 // Convert__regFCC0__Reg1_0__Reg1_1
1852 { CVT_regFCC0, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1853 // Convert__Reg1_0__Reg1_1__Reg1_2
1854 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1855 // Convert__MEMri2_0
1856 { CVT_95_addMEMriOperands, 1, CVT_Done },
1857 // Convert__MEMrr2_0
1858 { CVT_95_addMEMrrOperands, 1, CVT_Done },
1859 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8
1860 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_8, 0, CVT_Done },
1861 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8
1862 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_8, 0, CVT_Done },
1863 // Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0
1864 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
1865 // Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0
1866 { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
1867 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13
1868 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_13, 0, CVT_Done },
1869 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5
1870 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_5, 0, CVT_Done },
1871 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1
1872 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_1, 0, CVT_Done },
1873 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9
1874 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_9, 0, CVT_Done },
1875 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10
1876 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_10, 0, CVT_Done },
1877 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6
1878 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_6, 0, CVT_Done },
1879 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11
1880 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_11, 0, CVT_Done },
1881 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11
1882 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_11, 0, CVT_Done },
1883 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12
1884 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_12, 0, CVT_Done },
1885 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3
1886 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_3, 0, CVT_Done },
1887 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4
1888 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_4, 0, CVT_Done },
1889 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2
1890 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_2, 0, CVT_Done },
1891 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13
1892 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_13, 0, CVT_Done },
1893 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4
1894 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_4, 0, CVT_Done },
1895 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2
1896 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_2, 0, CVT_Done },
1897 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0
1898 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_0, 0, CVT_Done },
1899 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0
1900 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_0, 0, CVT_Done },
1901 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9
1902 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_9, 0, CVT_Done },
1903 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1
1904 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_1, 0, CVT_Done },
1905 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6
1906 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_6, 0, CVT_Done },
1907 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15
1908 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_15, 0, CVT_Done },
1909 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14
1910 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_14, 0, CVT_Done },
1911 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7
1912 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_7, 0, CVT_Done },
1913 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10
1914 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_10, 0, CVT_Done },
1915 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5
1916 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_5, 0, CVT_Done },
1917 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12
1918 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_12, 0, CVT_Done },
1919 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3
1920 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_3, 0, CVT_Done },
1921 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14
1922 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_14, 0, CVT_Done },
1923 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15
1924 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_15, 0, CVT_Done },
1925 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7
1926 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_7, 0, CVT_Done },
1927 // Convert__regG0__MEMri2_0
1928 { CVT_regG0, 0, CVT_95_addMEMriOperands, 1, CVT_Done },
1929 // Convert__regG0__MEMrr2_0
1930 { CVT_regG0, 0, CVT_95_addMEMrrOperands, 1, CVT_Done },
1931 // Convert__Reg1_1__MEMri2_0
1932 { CVT_95_Reg, 2, CVT_95_addMEMriOperands, 1, CVT_Done },
1933 // Convert__Reg1_1__MEMrr2_0
1934 { CVT_95_Reg, 2, CVT_95_addMEMrrOperands, 1, CVT_Done },
1935 // Convert__MEMri2_1
1936 { CVT_95_addMEMriOperands, 2, CVT_Done },
1937 // Convert__Reg1_3__MEMri2_1
1938 { CVT_95_Reg, 4, CVT_95_addMEMriOperands, 2, CVT_Done },
1939 // Convert__MEMrr2_1
1940 { CVT_95_addMEMrrOperands, 2, CVT_Done },
1941 // Convert__Reg1_3__MEMrr2_1
1942 { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_Done },
1943 // Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_GOT1_4
1944 { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_95_addTailRelocSymOperands, 5, CVT_Done },
1945 // Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_TLS1_4
1946 { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_95_addTailRelocSymOperands, 5, CVT_Done },
1947 // Convert__Reg1_4__MEMri2_1
1948 { CVT_95_Reg, 5, CVT_95_addMEMriOperands, 2, CVT_Done },
1949 // Convert__Reg1_4__MEMrr2_1__ASITag1_3
1950 { CVT_95_Reg, 5, CVT_95_addMEMrrOperands, 2, CVT_95_addASITagOperands, 4, CVT_Done },
1951 // Convert__MembarTag1_0
1952 { CVT_95_addMembarTagOperands, 1, CVT_Done },
1953 // Convert__Reg1_1
1954 { CVT_95_Reg, 2, CVT_Done },
1955 // Convert__regG0__Reg1_0
1956 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
1957 // Convert__Reg1_1__regG0__Reg1_0
1958 { CVT_95_Reg, 2, CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
1959 // Convert__regG0__Imm1_0
1960 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_Done },
1961 // Convert__Reg1_1__regG0__Imm1_0
1962 { CVT_95_Reg, 2, CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_Done },
1963 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8
1964 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_8, 0, CVT_Done },
1965 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_8
1966 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_8, 0, CVT_Done },
1967 // Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0
1968 { CVT_95_Reg, 4, CVT_95_addImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
1969 // Convert__Reg1_3__Reg1_1__Imm1_2__Tie0_1_1__Imm1_0
1970 { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
1971 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13
1972 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_13, 0, CVT_Done },
1973 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5
1974 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_5, 0, CVT_Done },
1975 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1
1976 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_1, 0, CVT_Done },
1977 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_9
1978 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_9, 0, CVT_Done },
1979 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10
1980 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_10, 0, CVT_Done },
1981 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_6
1982 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_6, 0, CVT_Done },
1983 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11
1984 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_11, 0, CVT_Done },
1985 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_11
1986 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_11, 0, CVT_Done },
1987 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12
1988 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_12, 0, CVT_Done },
1989 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3
1990 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_3, 0, CVT_Done },
1991 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_4
1992 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_4, 0, CVT_Done },
1993 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2
1994 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_2, 0, CVT_Done },
1995 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_13
1996 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_13, 0, CVT_Done },
1997 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4
1998 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_4, 0, CVT_Done },
1999 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_2
2000 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_2, 0, CVT_Done },
2001 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0
2002 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_0, 0, CVT_Done },
2003 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_0
2004 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_0, 0, CVT_Done },
2005 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9
2006 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_9, 0, CVT_Done },
2007 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1
2008 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_1, 0, CVT_Done },
2009 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6
2010 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_6, 0, CVT_Done },
2011 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_15
2012 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_15, 0, CVT_Done },
2013 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14
2014 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_14, 0, CVT_Done },
2015 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_7
2016 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_7, 0, CVT_Done },
2017 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_3
2018 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_3, 0, CVT_Done },
2019 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5
2020 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_5, 0, CVT_Done },
2021 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_10
2022 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_10, 0, CVT_Done },
2023 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_12
2024 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_12, 0, CVT_Done },
2025 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_14
2026 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_14, 0, CVT_Done },
2027 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15
2028 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_15, 0, CVT_Done },
2029 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7
2030 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_7, 0, CVT_Done },
2031 // Convert__Reg1_0__regG0__Reg1_0
2032 { CVT_95_Reg, 1, CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
2033 // Convert__Reg1_0__Reg1_0__regG0
2034 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_regG0, 0, CVT_Done },
2035 // Convert__Reg1_1__Reg1_0__regG0
2036 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_regG0, 0, CVT_Done },
2037 // Convert__regASR27__regG0__Reg1_0
2038 { CVT_regASR27, 0, CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
2039 // Convert__regASR27__regG0__Imm1_0
2040 { CVT_regASR27, 0, CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_Done },
2041 // Convert__MEMri2_1__PrefetchTag1_3
2042 { CVT_95_addMEMriOperands, 2, CVT_95_addPrefetchTagOperands, 4, CVT_Done },
2043 // Convert__MEMrr2_1__PrefetchTag1_3
2044 { CVT_95_addMEMrrOperands, 2, CVT_95_addPrefetchTagOperands, 4, CVT_Done },
2045 // Convert__MEMri2_1__PrefetchTag1_4
2046 { CVT_95_addMEMriOperands, 2, CVT_95_addPrefetchTagOperands, 5, CVT_Done },
2047 // Convert__MEMrr2_1__ASITag1_3__PrefetchTag1_4
2048 { CVT_95_addMEMrrOperands, 2, CVT_95_addASITagOperands, 4, CVT_95_addPrefetchTagOperands, 5, CVT_Done },
2049 // Convert__Reg1_0__Reg1_1
2050 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
2051 // Convert__Reg1_0__Imm1_1
2052 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
2053 // Convert__regG0__regG0__regG0
2054 { CVT_regG0, 0, CVT_regG0, 0, CVT_regG0, 0, CVT_Done },
2055 // Convert__imm_95_8
2056 { CVT_imm_95_8, 0, CVT_Done },
2057 // Convert__Reg1_1__Imm1_0
2058 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
2059 // Convert__Reg1_2__Imm1_0__Reg1_1
2060 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
2061 // Convert__imm_95_0
2062 { CVT_imm_95_0, 0, CVT_Done },
2063 // Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1
2064 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addShiftAmtImm5Operands, 2, CVT_Done },
2065 // Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1
2066 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addShiftAmtImm6Operands, 2, CVT_Done },
2067 // Convert__MEMri2_2
2068 { CVT_95_addMEMriOperands, 3, CVT_Done },
2069 // Convert__MEMrr2_2
2070 { CVT_95_addMEMrrOperands, 3, CVT_Done },
2071 // Convert__MEMri2_2__Reg1_0
2072 { CVT_95_addMEMriOperands, 3, CVT_95_Reg, 1, CVT_Done },
2073 // Convert__MEMrr2_2__Reg1_0
2074 { CVT_95_addMEMrrOperands, 3, CVT_95_Reg, 1, CVT_Done },
2075 // Convert__MEMrr2_2__Reg1_0__ASITag1_4
2076 { CVT_95_addMEMrrOperands, 3, CVT_95_Reg, 1, CVT_95_addASITagOperands, 5, CVT_Done },
2077 // Convert__Reg1_3__MEMri2_1__Tie0_1_1
2078 { CVT_95_Reg, 4, CVT_95_addMEMriOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
2079 // Convert__Reg1_3__MEMrr2_1__Tie0_1_1
2080 { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
2081 // Convert__Reg1_4__MEMri2_1__Tie0_1_1
2082 { CVT_95_Reg, 5, CVT_95_addMEMriOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
2083 // Convert__Reg1_4__MEMrr2_1__ASITag1_3__Tie0_1_1
2084 { CVT_95_Reg, 5, CVT_95_addMEMrrOperands, 2, CVT_95_addASITagOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
2085 // Convert__regG0__Reg1_0__imm_95_8
2086 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_8, 0, CVT_Done },
2087 // Convert__regG0__Imm1_0__imm_95_8
2088 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_8, 0, CVT_Done },
2089 // Convert__regG0__Reg1_1__imm_95_8
2090 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_8, 0, CVT_Done },
2091 // Convert__regG0__Imm1_1__imm_95_8
2092 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_8, 0, CVT_Done },
2093 // Convert__Reg1_0__Reg1_2__imm_95_8
2094 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_8, 0, CVT_Done },
2095 // Convert__Reg1_0__Imm1_2__imm_95_8
2096 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_8, 0, CVT_Done },
2097 // Convert__Reg1_1__Reg1_3__imm_95_8
2098 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_8, 0, CVT_Done },
2099 // Convert__Reg1_1__Imm1_3__imm_95_8
2100 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_8, 0, CVT_Done },
2101 // Convert__Reg1_1__Reg1_3__Imm1_0
2102 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
2103 // Convert__Reg1_1__Imm1_3__Imm1_0
2104 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
2105 // Convert__Reg1_2__Reg1_4__Imm1_0
2106 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 1, CVT_Done },
2107 // Convert__Reg1_2__Imm1_4__Imm1_0
2108 { CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
2109 // Convert__regG0__Reg1_0__imm_95_13
2110 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_13, 0, CVT_Done },
2111 // Convert__regG0__Imm1_0__imm_95_13
2112 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_13, 0, CVT_Done },
2113 // Convert__regG0__Reg1_1__imm_95_13
2114 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_13, 0, CVT_Done },
2115 // Convert__regG0__Imm1_1__imm_95_13
2116 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_13, 0, CVT_Done },
2117 // Convert__Reg1_0__Reg1_2__imm_95_13
2118 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_13, 0, CVT_Done },
2119 // Convert__Reg1_0__Imm1_2__imm_95_13
2120 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_Done },
2121 // Convert__Reg1_1__Reg1_3__imm_95_13
2122 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_13, 0, CVT_Done },
2123 // Convert__Reg1_1__Imm1_3__imm_95_13
2124 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_13, 0, CVT_Done },
2125 // Convert__regG0__Reg1_0__imm_95_5
2126 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_5, 0, CVT_Done },
2127 // Convert__regG0__Imm1_0__imm_95_5
2128 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_5, 0, CVT_Done },
2129 // Convert__regG0__Reg1_1__imm_95_5
2130 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_5, 0, CVT_Done },
2131 // Convert__regG0__Imm1_1__imm_95_5
2132 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_5, 0, CVT_Done },
2133 // Convert__Reg1_0__Reg1_2__imm_95_5
2134 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_5, 0, CVT_Done },
2135 // Convert__Reg1_0__Imm1_2__imm_95_5
2136 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_Done },
2137 // Convert__Reg1_1__Reg1_3__imm_95_5
2138 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_5, 0, CVT_Done },
2139 // Convert__Reg1_1__Imm1_3__imm_95_5
2140 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_5, 0, CVT_Done },
2141 // Convert__regG0__Reg1_0__imm_95_1
2142 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
2143 // Convert__regG0__Imm1_0__imm_95_1
2144 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_1, 0, CVT_Done },
2145 // Convert__regG0__Reg1_1__imm_95_1
2146 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
2147 // Convert__regG0__Imm1_1__imm_95_1
2148 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
2149 // Convert__Reg1_0__Reg1_2__imm_95_1
2150 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_Done },
2151 // Convert__Reg1_0__Imm1_2__imm_95_1
2152 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_Done },
2153 // Convert__Reg1_1__Reg1_3__imm_95_1
2154 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_1, 0, CVT_Done },
2155 // Convert__Reg1_1__Imm1_3__imm_95_1
2156 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_1, 0, CVT_Done },
2157 // Convert__regG0__Reg1_0__imm_95_10
2158 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_10, 0, CVT_Done },
2159 // Convert__regG0__Imm1_0__imm_95_10
2160 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_10, 0, CVT_Done },
2161 // Convert__regG0__Reg1_1__imm_95_10
2162 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_10, 0, CVT_Done },
2163 // Convert__regG0__Imm1_1__imm_95_10
2164 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_10, 0, CVT_Done },
2165 // Convert__Reg1_0__Reg1_2__imm_95_10
2166 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_10, 0, CVT_Done },
2167 // Convert__Reg1_0__Imm1_2__imm_95_10
2168 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_Done },
2169 // Convert__Reg1_1__Reg1_3__imm_95_10
2170 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_10, 0, CVT_Done },
2171 // Convert__Reg1_1__Imm1_3__imm_95_10
2172 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_10, 0, CVT_Done },
2173 // Convert__regG0__Reg1_0__imm_95_11
2174 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_11, 0, CVT_Done },
2175 // Convert__regG0__Imm1_0__imm_95_11
2176 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_11, 0, CVT_Done },
2177 // Convert__regG0__Reg1_1__imm_95_11
2178 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_11, 0, CVT_Done },
2179 // Convert__regG0__Imm1_1__imm_95_11
2180 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_11, 0, CVT_Done },
2181 // Convert__Reg1_0__Reg1_2__imm_95_11
2182 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_11, 0, CVT_Done },
2183 // Convert__Reg1_0__Imm1_2__imm_95_11
2184 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_Done },
2185 // Convert__Reg1_1__Reg1_3__imm_95_11
2186 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_11, 0, CVT_Done },
2187 // Convert__Reg1_1__Imm1_3__imm_95_11
2188 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_11, 0, CVT_Done },
2189 // Convert__regG0__Reg1_0__imm_95_12
2190 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_12, 0, CVT_Done },
2191 // Convert__regG0__Imm1_0__imm_95_12
2192 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_12, 0, CVT_Done },
2193 // Convert__regG0__Reg1_1__imm_95_12
2194 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_12, 0, CVT_Done },
2195 // Convert__regG0__Imm1_1__imm_95_12
2196 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_12, 0, CVT_Done },
2197 // Convert__Reg1_0__Reg1_2__imm_95_12
2198 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_12, 0, CVT_Done },
2199 // Convert__Reg1_0__Imm1_2__imm_95_12
2200 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_Done },
2201 // Convert__Reg1_1__Reg1_3__imm_95_12
2202 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_12, 0, CVT_Done },
2203 // Convert__Reg1_1__Imm1_3__imm_95_12
2204 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_12, 0, CVT_Done },
2205 // Convert__regG0__Reg1_0__imm_95_3
2206 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_Done },
2207 // Convert__regG0__Imm1_0__imm_95_3
2208 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_3, 0, CVT_Done },
2209 // Convert__regG0__Reg1_1__imm_95_3
2210 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_3, 0, CVT_Done },
2211 // Convert__regG0__Imm1_1__imm_95_3
2212 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_3, 0, CVT_Done },
2213 // Convert__Reg1_0__Reg1_2__imm_95_3
2214 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_3, 0, CVT_Done },
2215 // Convert__Reg1_0__Imm1_2__imm_95_3
2216 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_Done },
2217 // Convert__Reg1_1__Reg1_3__imm_95_3
2218 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_3, 0, CVT_Done },
2219 // Convert__Reg1_1__Imm1_3__imm_95_3
2220 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_3, 0, CVT_Done },
2221 // Convert__regG0__Reg1_0__imm_95_2
2222 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_Done },
2223 // Convert__regG0__Imm1_0__imm_95_2
2224 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_2, 0, CVT_Done },
2225 // Convert__regG0__Reg1_1__imm_95_2
2226 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_2, 0, CVT_Done },
2227 // Convert__regG0__Imm1_1__imm_95_2
2228 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_2, 0, CVT_Done },
2229 // Convert__Reg1_0__Reg1_2__imm_95_2
2230 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_2, 0, CVT_Done },
2231 // Convert__Reg1_0__Imm1_2__imm_95_2
2232 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_Done },
2233 // Convert__Reg1_1__Reg1_3__imm_95_2
2234 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_2, 0, CVT_Done },
2235 // Convert__Reg1_1__Imm1_3__imm_95_2
2236 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_2, 0, CVT_Done },
2237 // Convert__regG0__Reg1_0__imm_95_4
2238 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_4, 0, CVT_Done },
2239 // Convert__regG0__Imm1_0__imm_95_4
2240 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_4, 0, CVT_Done },
2241 // Convert__regG0__Reg1_1__imm_95_4
2242 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_4, 0, CVT_Done },
2243 // Convert__regG0__Imm1_1__imm_95_4
2244 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_4, 0, CVT_Done },
2245 // Convert__Reg1_0__Reg1_2__imm_95_4
2246 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_4, 0, CVT_Done },
2247 // Convert__Reg1_0__Imm1_2__imm_95_4
2248 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_Done },
2249 // Convert__Reg1_1__Reg1_3__imm_95_4
2250 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_4, 0, CVT_Done },
2251 // Convert__Reg1_1__Imm1_3__imm_95_4
2252 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_4, 0, CVT_Done },
2253 // Convert__regG0__Reg1_0__imm_95_0
2254 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2255 // Convert__regG0__Imm1_0__imm_95_0
2256 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_0, 0, CVT_Done },
2257 // Convert__regG0__Reg1_1__imm_95_0
2258 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2259 // Convert__regG0__Imm1_1__imm_95_0
2260 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2261 // Convert__Reg1_0__Reg1_2__imm_95_0
2262 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
2263 // Convert__Reg1_0__Imm1_2__imm_95_0
2264 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
2265 // Convert__Reg1_1__Reg1_3__imm_95_0
2266 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
2267 // Convert__Reg1_1__Imm1_3__imm_95_0
2268 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_Done },
2269 // Convert__regG0__Reg1_0__imm_95_9
2270 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_9, 0, CVT_Done },
2271 // Convert__regG0__Imm1_0__imm_95_9
2272 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_9, 0, CVT_Done },
2273 // Convert__regG0__Reg1_1__imm_95_9
2274 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_9, 0, CVT_Done },
2275 // Convert__regG0__Imm1_1__imm_95_9
2276 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_9, 0, CVT_Done },
2277 // Convert__Reg1_0__Reg1_2__imm_95_9
2278 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_9, 0, CVT_Done },
2279 // Convert__Reg1_0__Imm1_2__imm_95_9
2280 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_Done },
2281 // Convert__Reg1_1__Reg1_3__imm_95_9
2282 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_9, 0, CVT_Done },
2283 // Convert__Reg1_1__Imm1_3__imm_95_9
2284 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_9, 0, CVT_Done },
2285 // Convert__regG0__Reg1_0__imm_95_6
2286 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_6, 0, CVT_Done },
2287 // Convert__regG0__Imm1_0__imm_95_6
2288 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_6, 0, CVT_Done },
2289 // Convert__regG0__Reg1_1__imm_95_6
2290 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_6, 0, CVT_Done },
2291 // Convert__regG0__Imm1_1__imm_95_6
2292 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_6, 0, CVT_Done },
2293 // Convert__Reg1_0__Reg1_2__imm_95_6
2294 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_6, 0, CVT_Done },
2295 // Convert__Reg1_0__Imm1_2__imm_95_6
2296 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_Done },
2297 // Convert__Reg1_1__Reg1_3__imm_95_6
2298 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_6, 0, CVT_Done },
2299 // Convert__Reg1_1__Imm1_3__imm_95_6
2300 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_6, 0, CVT_Done },
2301 // Convert__regG0__Reg1_0__imm_95_14
2302 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_14, 0, CVT_Done },
2303 // Convert__regG0__Imm1_0__imm_95_14
2304 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_14, 0, CVT_Done },
2305 // Convert__regG0__Reg1_1__imm_95_14
2306 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_14, 0, CVT_Done },
2307 // Convert__regG0__Imm1_1__imm_95_14
2308 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_Done },
2309 // Convert__Reg1_0__Reg1_2__imm_95_14
2310 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_14, 0, CVT_Done },
2311 // Convert__Reg1_0__Imm1_2__imm_95_14
2312 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_Done },
2313 // Convert__Reg1_1__Reg1_3__imm_95_14
2314 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_14, 0, CVT_Done },
2315 // Convert__Reg1_1__Imm1_3__imm_95_14
2316 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_14, 0, CVT_Done },
2317 // Convert__regG0__Reg1_0__regG0
2318 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_regG0, 0, CVT_Done },
2319 // Convert__regG0__Reg1_0__imm_95_15
2320 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_15, 0, CVT_Done },
2321 // Convert__regG0__Imm1_0__imm_95_15
2322 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_15, 0, CVT_Done },
2323 // Convert__regG0__Reg1_1__imm_95_15
2324 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_15, 0, CVT_Done },
2325 // Convert__regG0__Imm1_1__imm_95_15
2326 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_15, 0, CVT_Done },
2327 // Convert__Reg1_0__Reg1_2__imm_95_15
2328 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_15, 0, CVT_Done },
2329 // Convert__Reg1_0__Imm1_2__imm_95_15
2330 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_Done },
2331 // Convert__Reg1_1__Reg1_3__imm_95_15
2332 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_15, 0, CVT_Done },
2333 // Convert__Reg1_1__Imm1_3__imm_95_15
2334 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_15, 0, CVT_Done },
2335 // Convert__regG0__Reg1_0__imm_95_7
2336 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_7, 0, CVT_Done },
2337 // Convert__regG0__Imm1_0__imm_95_7
2338 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_7, 0, CVT_Done },
2339 // Convert__regG0__Reg1_1__imm_95_7
2340 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done },
2341 // Convert__regG0__Imm1_1__imm_95_7
2342 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_7, 0, CVT_Done },
2343 // Convert__Reg1_0__Reg1_2__imm_95_7
2344 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_7, 0, CVT_Done },
2345 // Convert__Reg1_0__Imm1_2__imm_95_7
2346 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_Done },
2347 // Convert__Reg1_1__Reg1_3__imm_95_7
2348 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_7, 0, CVT_Done },
2349 // Convert__Reg1_1__Imm1_3__imm_95_7
2350 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_7, 0, CVT_Done },
2351};
2352
2353void SparcAsmParser::
2354convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2355 const OperandVector &Operands) {
2356 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2357 const uint8_t *Converter = ConversionTable[Kind];
2358 Inst.setOpcode(Opcode);
2359 for (const uint8_t *p = Converter; *p; p += 2) {
2360 unsigned OpIdx = *(p + 1);
2361 switch (*p) {
2362 default: llvm_unreachable("invalid conversion entry!");
2363 case CVT_Reg:
2364 static_cast<SparcOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2365 break;
2366 case CVT_Tied: {
2367 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
2368 std::begin(TiedAsmOperandTable)) &&
2369 "Tied operand not found");
2370 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
2371 if (TiedResOpnd != (uint8_t)-1)
2372 Inst.addOperand(Inst.getOperand(TiedResOpnd));
2373 break;
2374 }
2375 case CVT_95_Reg:
2376 static_cast<SparcOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2377 break;
2378 case CVT_95_addImmOperands:
2379 static_cast<SparcOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2380 break;
2381 case CVT_95_addTailRelocSymOperands:
2382 static_cast<SparcOperand &>(*Operands[OpIdx]).addTailRelocSymOperands(Inst, 1);
2383 break;
2384 case CVT_imm_95_8:
2385 Inst.addOperand(MCOperand::createImm(8));
2386 break;
2387 case CVT_imm_95_13:
2388 Inst.addOperand(MCOperand::createImm(13));
2389 break;
2390 case CVT_imm_95_5:
2391 Inst.addOperand(MCOperand::createImm(5));
2392 break;
2393 case CVT_imm_95_1:
2394 Inst.addOperand(MCOperand::createImm(1));
2395 break;
2396 case CVT_imm_95_10:
2397 Inst.addOperand(MCOperand::createImm(10));
2398 break;
2399 case CVT_imm_95_11:
2400 Inst.addOperand(MCOperand::createImm(11));
2401 break;
2402 case CVT_imm_95_12:
2403 Inst.addOperand(MCOperand::createImm(12));
2404 break;
2405 case CVT_imm_95_3:
2406 Inst.addOperand(MCOperand::createImm(3));
2407 break;
2408 case CVT_imm_95_2:
2409 Inst.addOperand(MCOperand::createImm(2));
2410 break;
2411 case CVT_imm_95_4:
2412 Inst.addOperand(MCOperand::createImm(4));
2413 break;
2414 case CVT_imm_95_0:
2415 Inst.addOperand(MCOperand::createImm(0));
2416 break;
2417 case CVT_imm_95_9:
2418 Inst.addOperand(MCOperand::createImm(9));
2419 break;
2420 case CVT_imm_95_6:
2421 Inst.addOperand(MCOperand::createImm(6));
2422 break;
2423 case CVT_imm_95_14:
2424 Inst.addOperand(MCOperand::createImm(14));
2425 break;
2426 case CVT_imm_95_7:
2427 Inst.addOperand(MCOperand::createImm(7));
2428 break;
2429 case CVT_regG0:
2430 Inst.addOperand(MCOperand::createReg(SP::G0));
2431 break;
2432 case CVT_imm_95_15:
2433 Inst.addOperand(MCOperand::createImm(15));
2434 break;
2435 case CVT_95_addCallTargetOperands:
2436 static_cast<SparcOperand &>(*Operands[OpIdx]).addCallTargetOperands(Inst, 1);
2437 break;
2438 case CVT_regO7:
2439 Inst.addOperand(MCOperand::createReg(SP::O7));
2440 break;
2441 case CVT_95_addMEMriOperands:
2442 static_cast<SparcOperand &>(*Operands[OpIdx]).addMEMriOperands(Inst, 2);
2443 break;
2444 case CVT_95_addMEMrrOperands:
2445 static_cast<SparcOperand &>(*Operands[OpIdx]).addMEMrrOperands(Inst, 2);
2446 break;
2447 case CVT_imm_95_128:
2448 Inst.addOperand(MCOperand::createImm(128));
2449 break;
2450 case CVT_95_addASITagOperands:
2451 static_cast<SparcOperand &>(*Operands[OpIdx]).addASITagOperands(Inst, 1);
2452 break;
2453 case CVT_imm_95_136:
2454 Inst.addOperand(MCOperand::createImm(136));
2455 break;
2456 case CVT_regFCC0:
2457 Inst.addOperand(MCOperand::createReg(SP::FCC0));
2458 break;
2459 case CVT_95_addMembarTagOperands:
2460 static_cast<SparcOperand &>(*Operands[OpIdx]).addMembarTagOperands(Inst, 1);
2461 break;
2462 case CVT_regASR27:
2463 Inst.addOperand(MCOperand::createReg(SP::ASR27));
2464 break;
2465 case CVT_95_addPrefetchTagOperands:
2466 static_cast<SparcOperand &>(*Operands[OpIdx]).addPrefetchTagOperands(Inst, 1);
2467 break;
2468 case CVT_95_addShiftAmtImm5Operands:
2469 static_cast<SparcOperand &>(*Operands[OpIdx]).addShiftAmtImm5Operands(Inst, 1);
2470 break;
2471 case CVT_95_addShiftAmtImm6Operands:
2472 static_cast<SparcOperand &>(*Operands[OpIdx]).addShiftAmtImm6Operands(Inst, 1);
2473 break;
2474 }
2475 }
2476}
2477
2478void SparcAsmParser::
2479convertToMapAndConstraints(unsigned Kind,
2480 const OperandVector &Operands) {
2481 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2482 unsigned NumMCOperands = 0;
2483 const uint8_t *Converter = ConversionTable[Kind];
2484 for (const uint8_t *p = Converter; *p; p += 2) {
2485 switch (*p) {
2486 default: llvm_unreachable("invalid conversion entry!");
2487 case CVT_Reg:
2488 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2489 Operands[*(p + 1)]->setConstraint("r");
2490 ++NumMCOperands;
2491 break;
2492 case CVT_Tied:
2493 ++NumMCOperands;
2494 break;
2495 case CVT_95_Reg:
2496 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2497 Operands[*(p + 1)]->setConstraint("r");
2498 NumMCOperands += 1;
2499 break;
2500 case CVT_95_addImmOperands:
2501 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2502 Operands[*(p + 1)]->setConstraint("m");
2503 NumMCOperands += 1;
2504 break;
2505 case CVT_95_addTailRelocSymOperands:
2506 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2507 Operands[*(p + 1)]->setConstraint("m");
2508 NumMCOperands += 1;
2509 break;
2510 case CVT_imm_95_8:
2511 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2512 Operands[*(p + 1)]->setConstraint("");
2513 ++NumMCOperands;
2514 break;
2515 case CVT_imm_95_13:
2516 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2517 Operands[*(p + 1)]->setConstraint("");
2518 ++NumMCOperands;
2519 break;
2520 case CVT_imm_95_5:
2521 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2522 Operands[*(p + 1)]->setConstraint("");
2523 ++NumMCOperands;
2524 break;
2525 case CVT_imm_95_1:
2526 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2527 Operands[*(p + 1)]->setConstraint("");
2528 ++NumMCOperands;
2529 break;
2530 case CVT_imm_95_10:
2531 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2532 Operands[*(p + 1)]->setConstraint("");
2533 ++NumMCOperands;
2534 break;
2535 case CVT_imm_95_11:
2536 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2537 Operands[*(p + 1)]->setConstraint("");
2538 ++NumMCOperands;
2539 break;
2540 case CVT_imm_95_12:
2541 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2542 Operands[*(p + 1)]->setConstraint("");
2543 ++NumMCOperands;
2544 break;
2545 case CVT_imm_95_3:
2546 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2547 Operands[*(p + 1)]->setConstraint("");
2548 ++NumMCOperands;
2549 break;
2550 case CVT_imm_95_2:
2551 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2552 Operands[*(p + 1)]->setConstraint("");
2553 ++NumMCOperands;
2554 break;
2555 case CVT_imm_95_4:
2556 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2557 Operands[*(p + 1)]->setConstraint("");
2558 ++NumMCOperands;
2559 break;
2560 case CVT_imm_95_0:
2561 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2562 Operands[*(p + 1)]->setConstraint("");
2563 ++NumMCOperands;
2564 break;
2565 case CVT_imm_95_9:
2566 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2567 Operands[*(p + 1)]->setConstraint("");
2568 ++NumMCOperands;
2569 break;
2570 case CVT_imm_95_6:
2571 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2572 Operands[*(p + 1)]->setConstraint("");
2573 ++NumMCOperands;
2574 break;
2575 case CVT_imm_95_14:
2576 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2577 Operands[*(p + 1)]->setConstraint("");
2578 ++NumMCOperands;
2579 break;
2580 case CVT_imm_95_7:
2581 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2582 Operands[*(p + 1)]->setConstraint("");
2583 ++NumMCOperands;
2584 break;
2585 case CVT_regG0:
2586 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2587 Operands[*(p + 1)]->setConstraint("m");
2588 ++NumMCOperands;
2589 break;
2590 case CVT_imm_95_15:
2591 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2592 Operands[*(p + 1)]->setConstraint("");
2593 ++NumMCOperands;
2594 break;
2595 case CVT_95_addCallTargetOperands:
2596 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2597 Operands[*(p + 1)]->setConstraint("m");
2598 NumMCOperands += 1;
2599 break;
2600 case CVT_regO7:
2601 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2602 Operands[*(p + 1)]->setConstraint("m");
2603 ++NumMCOperands;
2604 break;
2605 case CVT_95_addMEMriOperands:
2606 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2607 Operands[*(p + 1)]->setConstraint("m");
2608 NumMCOperands += 2;
2609 break;
2610 case CVT_95_addMEMrrOperands:
2611 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2612 Operands[*(p + 1)]->setConstraint("m");
2613 NumMCOperands += 2;
2614 break;
2615 case CVT_imm_95_128:
2616 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2617 Operands[*(p + 1)]->setConstraint("");
2618 ++NumMCOperands;
2619 break;
2620 case CVT_95_addASITagOperands:
2621 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2622 Operands[*(p + 1)]->setConstraint("m");
2623 NumMCOperands += 1;
2624 break;
2625 case CVT_imm_95_136:
2626 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2627 Operands[*(p + 1)]->setConstraint("");
2628 ++NumMCOperands;
2629 break;
2630 case CVT_regFCC0:
2631 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2632 Operands[*(p + 1)]->setConstraint("m");
2633 ++NumMCOperands;
2634 break;
2635 case CVT_95_addMembarTagOperands:
2636 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2637 Operands[*(p + 1)]->setConstraint("m");
2638 NumMCOperands += 1;
2639 break;
2640 case CVT_regASR27:
2641 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2642 Operands[*(p + 1)]->setConstraint("m");
2643 ++NumMCOperands;
2644 break;
2645 case CVT_95_addPrefetchTagOperands:
2646 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2647 Operands[*(p + 1)]->setConstraint("m");
2648 NumMCOperands += 1;
2649 break;
2650 case CVT_95_addShiftAmtImm5Operands:
2651 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2652 Operands[*(p + 1)]->setConstraint("m");
2653 NumMCOperands += 1;
2654 break;
2655 case CVT_95_addShiftAmtImm6Operands:
2656 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2657 Operands[*(p + 1)]->setConstraint("m");
2658 NumMCOperands += 1;
2659 break;
2660 }
2661 }
2662}
2663
2664namespace {
2665
2666/// MatchClassKind - The kinds of classes which participate in
2667/// instruction matching.
2668enum MatchClassKind {
2669 InvalidMatchClass = 0,
2670 OptionalMatchClass = 1,
2671 MCK__PCT_asi, // '%asi'
2672 MCK__PCT_ncc, // '%ncc'
2673 MCK__PCT_xcc, // '%xcc'
2674 MCK__43_, // '+'
2675 MCK_1, // '1'
2676 MCK_3, // '3'
2677 MCK_5, // '5'
2678 MCK__91_, // '['
2679 MCK__93_, // ']'
2680 MCK_a, // 'a'
2681 MCK_pn, // 'pn'
2682 MCK_pt, // 'pt'
2683 MCK_LAST_TOKEN = MCK_pt,
2684 MCK_Reg12, // derived register class
2685 MCK_CPQ, // register class 'CPQ'
2686 MCK_CPSR, // register class 'CPSR'
2687 MCK_FCC0, // register class 'FCC0'
2688 MCK_FQ, // register class 'FQ'
2689 MCK_FSR, // register class 'FSR'
2690 MCK_G0, // register class 'G0'
2691 MCK_ICC, // register class 'ICC'
2692 MCK_PSR, // register class 'PSR'
2693 MCK_TBR, // register class 'TBR'
2694 MCK_WIM, // register class 'WIM'
2695 MCK_Reg25, // derived register class
2696 MCK_Reg24, // derived register class
2697 MCK_FCCRegs, // register class 'FCCRegs'
2698 MCK_GPRIncomingArg, // register class 'GPRIncomingArg'
2699 MCK_GPROutgoingArg, // register class 'GPROutgoingArg'
2700 MCK_LowQFPRegs, // register class 'LowQFPRegs'
2701 MCK_CoprocPair, // register class 'CoprocPair'
2702 MCK_IntPair, // register class 'IntPair'
2703 MCK_LowDFPRegs, // register class 'LowDFPRegs'
2704 MCK_QFPRegs, // register class 'QFPRegs'
2705 MCK_PRRegs, // register class 'PRRegs'
2706 MCK_CoprocRegs, // register class 'CoprocRegs'
2707 MCK_DFPRegs, // register class 'DFPRegs'
2708 MCK_FPRegs, // register class 'FPRegs'
2709 MCK_IntRegs, // register class 'IntRegs,I64Regs'
2710 MCK_ASRRegs, // register class 'ASRRegs'
2711 MCK_LAST_REGISTER = MCK_ASRRegs,
2712 MCK_RegByHwMode_sparc_ptr_rc, // register class by hwmode
2713 MCK_LAST_REGCLASS_BY_HWMODE = MCK_RegByHwMode_sparc_ptr_rc,
2714 MCK_Imm, // user defined class 'ImmAsmOperand'
2715 MCK_ASITag, // user defined class 'SparcASITagAsmOperand'
2716 MCK_CallTarget, // user defined class 'SparcCallTargetAsmOperand'
2717 MCK_MEMri, // user defined class 'SparcMEMriAsmOperand'
2718 MCK_MEMrr, // user defined class 'SparcMEMrrAsmOperand'
2719 MCK_MembarTag, // user defined class 'SparcMembarTagAsmOperand'
2720 MCK_PrefetchTag, // user defined class 'SparcPrefetchTagAsmOperand'
2721 MCK_ShiftAmtImm5, // user defined class 'anonymous_14692'
2722 MCK_ShiftAmtImm6, // user defined class 'anonymous_14693'
2723 MCK_TailRelocSymLoad_GOT, // user defined class 'anonymous_14694'
2724 MCK_TailRelocSymAdd_TLS, // user defined class 'anonymous_14695'
2725 MCK_TailRelocSymLoad_TLS, // user defined class 'anonymous_14696'
2726 MCK_TailRelocSymCall_TLS, // user defined class 'anonymous_14697'
2727 NumMatchClassKinds
2728};
2729
2730} // end anonymous namespace
2731
2732static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
2733 return MCTargetAsmParser::Match_InvalidOperand;
2734}
2735
2736static MatchClassKind matchTokenString(StringRef Name) {
2737 switch (Name.size()) {
2738 default: break;
2739 case 1: // 7 strings to match.
2740 switch (Name[0]) {
2741 default: break;
2742 case '+': // 1 string to match.
2743 return MCK__43_; // "+"
2744 case '1': // 1 string to match.
2745 return MCK_1; // "1"
2746 case '3': // 1 string to match.
2747 return MCK_3; // "3"
2748 case '5': // 1 string to match.
2749 return MCK_5; // "5"
2750 case '[': // 1 string to match.
2751 return MCK__91_; // "["
2752 case ']': // 1 string to match.
2753 return MCK__93_; // "]"
2754 case 'a': // 1 string to match.
2755 return MCK_a; // "a"
2756 }
2757 break;
2758 case 2: // 2 strings to match.
2759 if (Name[0] != 'p')
2760 break;
2761 switch (Name[1]) {
2762 default: break;
2763 case 'n': // 1 string to match.
2764 return MCK_pn; // "pn"
2765 case 't': // 1 string to match.
2766 return MCK_pt; // "pt"
2767 }
2768 break;
2769 case 4: // 3 strings to match.
2770 if (Name[0] != '%')
2771 break;
2772 switch (Name[1]) {
2773 default: break;
2774 case 'a': // 1 string to match.
2775 if (memcmp(Name.data()+2, "si", 2) != 0)
2776 break;
2777 return MCK__PCT_asi; // "%asi"
2778 case 'n': // 1 string to match.
2779 if (memcmp(Name.data()+2, "cc", 2) != 0)
2780 break;
2781 return MCK__PCT_ncc; // "%ncc"
2782 case 'x': // 1 string to match.
2783 if (memcmp(Name.data()+2, "cc", 2) != 0)
2784 break;
2785 return MCK__PCT_xcc; // "%xcc"
2786 }
2787 break;
2788 }
2789 return InvalidMatchClass;
2790}
2791
2792/// isSubclass - Compute whether \p A is a subclass of \p B.
2793static bool isSubclass(MatchClassKind A, MatchClassKind B) {
2794 if (A == B)
2795 return true;
2796
2797 [[maybe_unused]] static constexpr struct {
2798 uint32_t Offset;
2799 uint16_t Start;
2800 uint16_t Length;
2801 } Table[] = {
2802 {0, 0, 0},
2803 {0, 0, 0},
2804 {0, 0, 0},
2805 {0, 0, 0},
2806 {0, 0, 0},
2807 {0, 0, 0},
2808 {0, 0, 0},
2809 {0, 0, 0},
2810 {0, 0, 0},
2811 {0, 0, 0},
2812 {0, 0, 0},
2813 {0, 0, 0},
2814 {0, 0, 0},
2815 {0, 0, 0},
2816 {0, 35, 6},
2817 {6, 0, 0},
2818 {6, 0, 0},
2819 {6, 27, 1},
2820 {7, 0, 0},
2821 {7, 0, 0},
2822 {7, 39, 1},
2823 {8, 0, 0},
2824 {8, 0, 0},
2825 {8, 0, 0},
2826 {8, 0, 0},
2827 {8, 32, 1},
2828 {9, 32, 1},
2829 {10, 0, 0},
2830 {10, 39, 1},
2831 {11, 39, 1},
2832 {12, 34, 1},
2833 {13, 0, 0},
2834 {13, 0, 0},
2835 {13, 37, 1},
2836 {14, 0, 0},
2837 {14, 0, 0},
2838 {14, 0, 0},
2839 {14, 0, 0},
2840 {14, 0, 0},
2841 {14, 0, 0},
2842 {14, 0, 0},
2843 {14, 0, 0},
2844 {14, 0, 0},
2845 {14, 0, 0},
2846 {14, 0, 0},
2847 {14, 0, 0},
2848 {14, 0, 0},
2849 {14, 0, 0},
2850 {14, 0, 0},
2851 {14, 0, 0},
2852 {14, 0, 0},
2853 {14, 0, 0},
2854 {14, 0, 0},
2855 {14, 0, 0},
2856 {14, 0, 0},
2857 };
2858
2859 static constexpr uint8_t Data[] = {
2860 0xE1,
2861 0x3F,
2862 };
2863
2864 auto &Entry = Table[A];
2865 unsigned Idx = B - Entry.Start;
2866 if (Idx >= Entry.Length)
2867 return false;
2868 Idx += Entry.Offset;
2869 return (Data[Idx / 8] >> (Idx % 8)) & 1;
2870}
2871
2872static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
2873 SparcOperand &Operand = (SparcOperand &)GOp;
2874 if (Kind == InvalidMatchClass)
2875 return MCTargetAsmParser::Match_InvalidOperand;
2876
2877 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
2878 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
2879 MCTargetAsmParser::Match_Success :
2880 MCTargetAsmParser::Match_InvalidOperand;
2881
2882 switch (Kind) {
2883 default: break;
2884 case MCK_Imm: {
2885 DiagnosticPredicate DP(Operand.isImm());
2886 if (DP.isMatch())
2887 return MCTargetAsmParser::Match_Success;
2888 break;
2889 }
2890 case MCK_ASITag: {
2891 DiagnosticPredicate DP(Operand.isASITag());
2892 if (DP.isMatch())
2893 return MCTargetAsmParser::Match_Success;
2894 break;
2895 }
2896 case MCK_CallTarget: {
2897 DiagnosticPredicate DP(Operand.isCallTarget());
2898 if (DP.isMatch())
2899 return MCTargetAsmParser::Match_Success;
2900 break;
2901 }
2902 case MCK_MEMri: {
2903 DiagnosticPredicate DP(Operand.isMEMri());
2904 if (DP.isMatch())
2905 return MCTargetAsmParser::Match_Success;
2906 break;
2907 }
2908 case MCK_MEMrr: {
2909 DiagnosticPredicate DP(Operand.isMEMrr());
2910 if (DP.isMatch())
2911 return MCTargetAsmParser::Match_Success;
2912 break;
2913 }
2914 case MCK_MembarTag: {
2915 DiagnosticPredicate DP(Operand.isMembarTag());
2916 if (DP.isMatch())
2917 return MCTargetAsmParser::Match_Success;
2918 break;
2919 }
2920 case MCK_PrefetchTag: {
2921 DiagnosticPredicate DP(Operand.isPrefetchTag());
2922 if (DP.isMatch())
2923 return MCTargetAsmParser::Match_Success;
2924 break;
2925 }
2926 case MCK_ShiftAmtImm5: {
2927 DiagnosticPredicate DP(Operand.isShiftAmtImm5());
2928 if (DP.isMatch())
2929 return MCTargetAsmParser::Match_Success;
2930 break;
2931 }
2932 case MCK_ShiftAmtImm6: {
2933 DiagnosticPredicate DP(Operand.isShiftAmtImm6());
2934 if (DP.isMatch())
2935 return MCTargetAsmParser::Match_Success;
2936 break;
2937 }
2938 case MCK_TailRelocSymLoad_GOT: {
2939 DiagnosticPredicate DP(Operand.isTailRelocSym());
2940 if (DP.isMatch())
2941 return MCTargetAsmParser::Match_Success;
2942 break;
2943 }
2944 case MCK_TailRelocSymAdd_TLS: {
2945 DiagnosticPredicate DP(Operand.isTailRelocSym());
2946 if (DP.isMatch())
2947 return MCTargetAsmParser::Match_Success;
2948 break;
2949 }
2950 case MCK_TailRelocSymLoad_TLS: {
2951 DiagnosticPredicate DP(Operand.isTailRelocSym());
2952 if (DP.isMatch())
2953 return MCTargetAsmParser::Match_Success;
2954 break;
2955 }
2956 case MCK_TailRelocSymCall_TLS: {
2957 DiagnosticPredicate DP(Operand.isTailRelocSym());
2958 if (DP.isMatch())
2959 return MCTargetAsmParser::Match_Success;
2960 break;
2961 }
2962 } // end switch (Kind)
2963
2964 if (Operand.isReg() && Kind > MCK_LAST_REGISTER && Kind <= MCK_LAST_REGCLASS_BY_HWMODE) {
2965 static constexpr MatchClassKind RegClassByHwModeMatchTable[2][1] = {
2966 { // DefaultMode
2967 MCK_IntRegs, // sparc_ptr_rc
2968 },
2969 { // SPARC64
2970 MCK_IntRegs, // sparc_ptr_rc
2971 },
2972 };
2973
2974 static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == 1);
2975 const unsigned HwMode = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
2976Kind = RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER + 1)];
2977 }
2978
2979 if (Operand.isReg()) {
2980 static constexpr uint16_t Table[SP::NUM_TARGET_REGS] = {
2981 InvalidMatchClass,
2982 MCK_PRRegs,
2983 MCK_PRRegs,
2984 MCK_PRRegs,
2985 MCK_CPQ,
2986 MCK_CPSR,
2987 MCK_PRRegs,
2988 MCK_FQ,
2989 MCK_FSR,
2990 MCK_PRRegs,
2991 MCK_ICC,
2992 MCK_PRRegs,
2993 MCK_PRRegs,
2994 MCK_PSR,
2995 MCK_PRRegs,
2996 MCK_PRRegs,
2997 MCK_TBR,
2998 MCK_Reg12,
2999 MCK_PRRegs,
3000 MCK_PRRegs,
3001 MCK_PRRegs,
3002 MCK_PRRegs,
3003 MCK_PRRegs,
3004 MCK_PRRegs,
3005 MCK_WIM,
3006 MCK_PRRegs,
3007 MCK_ASRRegs,
3008 MCK_ASRRegs,
3009 MCK_ASRRegs,
3010 MCK_ASRRegs,
3011 MCK_ASRRegs,
3012 MCK_ASRRegs,
3013 MCK_ASRRegs,
3014 MCK_ASRRegs,
3015 MCK_ASRRegs,
3016 MCK_ASRRegs,
3017 MCK_ASRRegs,
3018 MCK_ASRRegs,
3019 MCK_ASRRegs,
3020 MCK_ASRRegs,
3021 MCK_ASRRegs,
3022 MCK_ASRRegs,
3023 MCK_ASRRegs,
3024 MCK_ASRRegs,
3025 MCK_ASRRegs,
3026 MCK_ASRRegs,
3027 MCK_ASRRegs,
3028 MCK_ASRRegs,
3029 MCK_ASRRegs,
3030 MCK_ASRRegs,
3031 MCK_ASRRegs,
3032 MCK_ASRRegs,
3033 MCK_ASRRegs,
3034 MCK_ASRRegs,
3035 MCK_ASRRegs,
3036 MCK_ASRRegs,
3037 MCK_ASRRegs,
3038 MCK_ASRRegs,
3039 MCK_CoprocRegs,
3040 MCK_CoprocRegs,
3041 MCK_CoprocRegs,
3042 MCK_CoprocRegs,
3043 MCK_CoprocRegs,
3044 MCK_CoprocRegs,
3045 MCK_CoprocRegs,
3046 MCK_CoprocRegs,
3047 MCK_CoprocRegs,
3048 MCK_CoprocRegs,
3049 MCK_CoprocRegs,
3050 MCK_CoprocRegs,
3051 MCK_CoprocRegs,
3052 MCK_CoprocRegs,
3053 MCK_CoprocRegs,
3054 MCK_CoprocRegs,
3055 MCK_CoprocRegs,
3056 MCK_CoprocRegs,
3057 MCK_CoprocRegs,
3058 MCK_CoprocRegs,
3059 MCK_CoprocRegs,
3060 MCK_CoprocRegs,
3061 MCK_CoprocRegs,
3062 MCK_CoprocRegs,
3063 MCK_CoprocRegs,
3064 MCK_CoprocRegs,
3065 MCK_CoprocRegs,
3066 MCK_CoprocRegs,
3067 MCK_CoprocRegs,
3068 MCK_CoprocRegs,
3069 MCK_CoprocRegs,
3070 MCK_CoprocRegs,
3071 MCK_LowDFPRegs,
3072 MCK_LowDFPRegs,
3073 MCK_LowDFPRegs,
3074 MCK_LowDFPRegs,
3075 MCK_LowDFPRegs,
3076 MCK_LowDFPRegs,
3077 MCK_LowDFPRegs,
3078 MCK_LowDFPRegs,
3079 MCK_LowDFPRegs,
3080 MCK_LowDFPRegs,
3081 MCK_LowDFPRegs,
3082 MCK_LowDFPRegs,
3083 MCK_LowDFPRegs,
3084 MCK_LowDFPRegs,
3085 MCK_LowDFPRegs,
3086 MCK_LowDFPRegs,
3087 MCK_DFPRegs,
3088 MCK_DFPRegs,
3089 MCK_DFPRegs,
3090 MCK_DFPRegs,
3091 MCK_DFPRegs,
3092 MCK_DFPRegs,
3093 MCK_DFPRegs,
3094 MCK_DFPRegs,
3095 MCK_DFPRegs,
3096 MCK_DFPRegs,
3097 MCK_DFPRegs,
3098 MCK_DFPRegs,
3099 MCK_DFPRegs,
3100 MCK_DFPRegs,
3101 MCK_DFPRegs,
3102 MCK_DFPRegs,
3103 MCK_FPRegs,
3104 MCK_FPRegs,
3105 MCK_FPRegs,
3106 MCK_FPRegs,
3107 MCK_FPRegs,
3108 MCK_FPRegs,
3109 MCK_FPRegs,
3110 MCK_FPRegs,
3111 MCK_FPRegs,
3112 MCK_FPRegs,
3113 MCK_FPRegs,
3114 MCK_FPRegs,
3115 MCK_FPRegs,
3116 MCK_FPRegs,
3117 MCK_FPRegs,
3118 MCK_FPRegs,
3119 MCK_FPRegs,
3120 MCK_FPRegs,
3121 MCK_FPRegs,
3122 MCK_FPRegs,
3123 MCK_FPRegs,
3124 MCK_FPRegs,
3125 MCK_FPRegs,
3126 MCK_FPRegs,
3127 MCK_FPRegs,
3128 MCK_FPRegs,
3129 MCK_FPRegs,
3130 MCK_FPRegs,
3131 MCK_FPRegs,
3132 MCK_FPRegs,
3133 MCK_FPRegs,
3134 MCK_FPRegs,
3135 MCK_FCC0,
3136 MCK_FCCRegs,
3137 MCK_FCCRegs,
3138 MCK_FCCRegs,
3139 MCK_G0,
3140 MCK_IntRegs,
3141 MCK_IntRegs,
3142 MCK_IntRegs,
3143 MCK_IntRegs,
3144 MCK_IntRegs,
3145 MCK_IntRegs,
3146 MCK_IntRegs,
3147 MCK_GPRIncomingArg,
3148 MCK_GPRIncomingArg,
3149 MCK_GPRIncomingArg,
3150 MCK_GPRIncomingArg,
3151 MCK_GPRIncomingArg,
3152 MCK_GPRIncomingArg,
3153 MCK_IntRegs,
3154 MCK_IntRegs,
3155 MCK_IntRegs,
3156 MCK_IntRegs,
3157 MCK_IntRegs,
3158 MCK_IntRegs,
3159 MCK_IntRegs,
3160 MCK_IntRegs,
3161 MCK_IntRegs,
3162 MCK_IntRegs,
3163 MCK_GPROutgoingArg,
3164 MCK_GPROutgoingArg,
3165 MCK_GPROutgoingArg,
3166 MCK_GPROutgoingArg,
3167 MCK_GPROutgoingArg,
3168 MCK_GPROutgoingArg,
3169 MCK_IntRegs,
3170 MCK_IntRegs,
3171 MCK_LowQFPRegs,
3172 MCK_LowQFPRegs,
3173 MCK_LowQFPRegs,
3174 MCK_LowQFPRegs,
3175 MCK_LowQFPRegs,
3176 MCK_LowQFPRegs,
3177 MCK_LowQFPRegs,
3178 MCK_LowQFPRegs,
3179 MCK_QFPRegs,
3180 MCK_QFPRegs,
3181 MCK_QFPRegs,
3182 MCK_QFPRegs,
3183 MCK_QFPRegs,
3184 MCK_QFPRegs,
3185 MCK_QFPRegs,
3186 MCK_QFPRegs,
3187 MCK_CoprocPair,
3188 MCK_CoprocPair,
3189 MCK_CoprocPair,
3190 MCK_CoprocPair,
3191 MCK_CoprocPair,
3192 MCK_CoprocPair,
3193 MCK_CoprocPair,
3194 MCK_CoprocPair,
3195 MCK_CoprocPair,
3196 MCK_CoprocPair,
3197 MCK_CoprocPair,
3198 MCK_CoprocPair,
3199 MCK_CoprocPair,
3200 MCK_CoprocPair,
3201 MCK_CoprocPair,
3202 MCK_CoprocPair,
3203 MCK_IntPair,
3204 MCK_IntPair,
3205 MCK_IntPair,
3206 MCK_IntPair,
3207 MCK_Reg25,
3208 MCK_Reg25,
3209 MCK_Reg25,
3210 MCK_IntPair,
3211 MCK_IntPair,
3212 MCK_IntPair,
3213 MCK_IntPair,
3214 MCK_IntPair,
3215 MCK_Reg24,
3216 MCK_Reg24,
3217 MCK_Reg24,
3218 MCK_IntPair,
3219 };
3220
3221 MCRegister Reg = Operand.getReg();
3222 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
3223 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
3224 getDiagKindFromRegisterClass(Kind);
3225 }
3226
3227 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
3228 return getDiagKindFromRegisterClass(Kind);
3229
3230 return MCTargetAsmParser::Match_InvalidOperand;
3231}
3232
3233#ifndef NDEBUG
3234const char *getMatchClassName(MatchClassKind Kind) {
3235 switch (Kind) {
3236 case InvalidMatchClass: return "InvalidMatchClass";
3237 case OptionalMatchClass: return "OptionalMatchClass";
3238 case MCK__PCT_asi: return "MCK__PCT_asi";
3239 case MCK__PCT_ncc: return "MCK__PCT_ncc";
3240 case MCK__PCT_xcc: return "MCK__PCT_xcc";
3241 case MCK__43_: return "MCK__43_";
3242 case MCK_1: return "MCK_1";
3243 case MCK_3: return "MCK_3";
3244 case MCK_5: return "MCK_5";
3245 case MCK__91_: return "MCK__91_";
3246 case MCK__93_: return "MCK__93_";
3247 case MCK_a: return "MCK_a";
3248 case MCK_pn: return "MCK_pn";
3249 case MCK_pt: return "MCK_pt";
3250 case MCK_Reg12: return "MCK_Reg12";
3251 case MCK_CPQ: return "MCK_CPQ";
3252 case MCK_CPSR: return "MCK_CPSR";
3253 case MCK_FCC0: return "MCK_FCC0";
3254 case MCK_FQ: return "MCK_FQ";
3255 case MCK_FSR: return "MCK_FSR";
3256 case MCK_G0: return "MCK_G0";
3257 case MCK_ICC: return "MCK_ICC";
3258 case MCK_PSR: return "MCK_PSR";
3259 case MCK_TBR: return "MCK_TBR";
3260 case MCK_WIM: return "MCK_WIM";
3261 case MCK_Reg25: return "MCK_Reg25";
3262 case MCK_Reg24: return "MCK_Reg24";
3263 case MCK_FCCRegs: return "MCK_FCCRegs";
3264 case MCK_GPRIncomingArg: return "MCK_GPRIncomingArg";
3265 case MCK_GPROutgoingArg: return "MCK_GPROutgoingArg";
3266 case MCK_LowQFPRegs: return "MCK_LowQFPRegs";
3267 case MCK_CoprocPair: return "MCK_CoprocPair";
3268 case MCK_IntPair: return "MCK_IntPair";
3269 case MCK_LowDFPRegs: return "MCK_LowDFPRegs";
3270 case MCK_QFPRegs: return "MCK_QFPRegs";
3271 case MCK_PRRegs: return "MCK_PRRegs";
3272 case MCK_CoprocRegs: return "MCK_CoprocRegs";
3273 case MCK_DFPRegs: return "MCK_DFPRegs";
3274 case MCK_FPRegs: return "MCK_FPRegs";
3275 case MCK_IntRegs: return "MCK_IntRegs";
3276 case MCK_ASRRegs: return "MCK_ASRRegs";
3277 case MCK_RegByHwMode_sparc_ptr_rc: return "MCK_RegByHwMode_sparc_ptr_rc";
3278 case MCK_Imm: return "MCK_Imm";
3279 case MCK_ASITag: return "MCK_ASITag";
3280 case MCK_CallTarget: return "MCK_CallTarget";
3281 case MCK_MEMri: return "MCK_MEMri";
3282 case MCK_MEMrr: return "MCK_MEMrr";
3283 case MCK_MembarTag: return "MCK_MembarTag";
3284 case MCK_PrefetchTag: return "MCK_PrefetchTag";
3285 case MCK_ShiftAmtImm5: return "MCK_ShiftAmtImm5";
3286 case MCK_ShiftAmtImm6: return "MCK_ShiftAmtImm6";
3287 case MCK_TailRelocSymLoad_GOT: return "MCK_TailRelocSymLoad_GOT";
3288 case MCK_TailRelocSymAdd_TLS: return "MCK_TailRelocSymAdd_TLS";
3289 case MCK_TailRelocSymLoad_TLS: return "MCK_TailRelocSymLoad_TLS";
3290 case MCK_TailRelocSymCall_TLS: return "MCK_TailRelocSymCall_TLS";
3291 case NumMatchClassKinds: return "NumMatchClassKinds";
3292 }
3293 llvm_unreachable("unhandled MatchClassKind!");
3294}
3295
3296#endif // NDEBUG
3297FeatureBitset SparcAsmParser::
3298ComputeAvailableFeatures(const FeatureBitset &FB) const {
3299 FeatureBitset Features;
3300 if (!FB[Sparc::Feature64Bit])
3301 Features.set(Feature_Is32BitBit);
3302 if (FB[Sparc::Feature64Bit])
3303 Features.set(Feature_Is64BitBit);
3304 if (FB[Sparc::FeatureSoftMulDiv])
3305 Features.set(Feature_UseSoftMulDivBit);
3306 if (FB[Sparc::FeatureV9])
3307 Features.set(Feature_HasV9Bit);
3308 if (FB[Sparc::FeatureVIS])
3309 Features.set(Feature_HasVISBit);
3310 if (FB[Sparc::FeatureVIS2])
3311 Features.set(Feature_HasVIS2Bit);
3312 if (FB[Sparc::FeatureVIS3])
3313 Features.set(Feature_HasVIS3Bit);
3314 if (FB[Sparc::FeatureUA2005])
3315 Features.set(Feature_HasUA2005Bit);
3316 if (FB[Sparc::FeatureUA2007])
3317 Features.set(Feature_HasUA2007Bit);
3318 if (FB[Sparc::FeatureOSA2011])
3319 Features.set(Feature_HasOSA2011Bit);
3320 if (FB[Sparc::FeatureCrypto])
3321 Features.set(Feature_HasCryptoBit);
3322 if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
3323 Features.set(Feature_HasCASABit);
3324 if (FB[Sparc::FeaturePWRPSR])
3325 Features.set(Feature_HasPWRPSRBit);
3326 return Features;
3327}
3328
3329static bool checkAsmTiedOperandConstraints(const SparcAsmParser&AsmParser,
3330 unsigned Kind, const OperandVector &Operands,
3331 uint64_t &ErrorInfo) {
3332 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
3333 const uint8_t *Converter = ConversionTable[Kind];
3334 for (const uint8_t *p = Converter; *p; p += 2) {
3335 switch (*p) {
3336 case CVT_Tied: {
3337 unsigned OpIdx = *(p + 1);
3338 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
3339 std::begin(TiedAsmOperandTable)) &&
3340 "Tied operand not found");
3341 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
3342 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
3343 if (OpndNum1 != OpndNum2) {
3344 auto &SrcOp1 = Operands[OpndNum1];
3345 auto &SrcOp2 = Operands[OpndNum2];
3346 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
3347 ErrorInfo = OpndNum2;
3348 return false;
3349 }
3350 }
3351 break;
3352 }
3353 default:
3354 break;
3355 }
3356 }
3357 return true;
3358}
3359
3360static const char MnemonicTable[] =
3361 "\003add\005addcc\004addx\005addxc\006addxcc\007addxccc\014aes_dround01\016"
3362 "aes_dround01_l\014aes_dround23\016aes_dround23_l\014aes_eround01\016aes"
3363 "_eround01_l\014aes_eround23\016aes_eround23_l\014aes_kexpand0\014aes_ke"
3364 "xpand1\014aes_kexpand2\talignaddr\nalignaddrl\010allclean\003and\005and"
3365 "cc\004andn\006andncc\007array16\007array32\006array8\001b\002ba\003bcc\004"
3366 "bclr\003bcs\002be\003beq\002bg\003bge\004bgeu\003bgt\003bgu\002bl\003bl"
3367 "e\004bleu\003blt\003blu\005bmask\002bn\003bne\004bneg\003bnz\004bpos\002"
3368 "br\003bre\005brgez\004brgz\005brlez\004brlz\004brne\004brnz\003brz\004b"
3369 "set\010bshuffle\004btog\004btst\003bvc\003bvs\002bz\004call\ncamellia_f"
3370 "\013camellia_fl\014camellia_fli\003cas\004casa\004casl\004casx\005casxa"
3371 "\005casxl\002cb\003cb0\004cb01\005cb012\005cb013\004cb02\005cb023\004cb"
3372 "03\003cb1\004cb12\005cb123\004cb13\003cb2\004cb23\003cb3\003cba\003cbn\003"
3373 "clr\004clrb\004clrh\004clrx\007cmask16\007cmask32\006cmask8\003cmp\006c"
3374 "rc32c\003cwb\005cwbcc\005cwbcs\004cwbe\004cwbg\005cwbge\006cwbgeu\005cw"
3375 "bgu\004cwbl\005cwble\006cwbleu\005cwblu\005cwbne\006cwbneg\006cwbpos\005"
3376 "cwbvc\005cwbvs\003cxb\005cxbcc\005cxbcs\004cxbe\004cxbg\005cxbge\006cxb"
3377 "geu\005cxbgu\004cxbl\005cxble\006cxbleu\005cxblu\005cxbne\006cxbneg\006"
3378 "cxbpos\005cxbvc\005cxbvs\003dec\005deccc\007des_iip\006des_ip\013des_ke"
3379 "xpand\tdes_round\004done\006edge16\007edge16l\010edge16ln\007edge16n\006"
3380 "edge32\007edge32l\010edge32ln\007edge32n\005edge8\006edge8l\007edge8ln\006"
3381 "edge8n\005fabsd\005fabsq\005fabss\005faddd\005faddq\005fadds\nfaligndat"
3382 "a\004fand\010fandnot1\tfandnot1s\010fandnot2\tfandnot2s\005fands\002fb\003"
3383 "fba\003fbe\003fbg\004fbge\003fbl\004fble\004fblg\003fbn\004fbne\004fbnz"
3384 "\003fbo\003fbu\004fbue\004fbug\005fbuge\004fbul\005fbule\003fbz\010fchk"
3385 "sm16\005fcmpd\006fcmped\006fcmpeq\010fcmpeq16\010fcmpeq32\006fcmpes\010"
3386 "fcmpgt16\010fcmpgt32\010fcmple16\010fcmple32\010fcmpne16\010fcmpne32\005"
3387 "fcmpq\005fcmps\005fdivd\005fdivq\005fdivs\006fdmulq\005fdtoi\005fdtoq\005"
3388 "fdtos\005fdtox\007fexpand\006fhaddd\006fhadds\006fhsubd\006fhsubs\005fi"
3389 "tod\005fitoq\005fitos\006flcmpd\006flcmps\005flush\006flushw\006fmaddd\006"
3390 "fmadds\007fmean16\005fmovd\006fmovda\007fmovdcc\007fmovdcs\006fmovde\007"
3391 "fmovdeq\006fmovdg\007fmovdge\010fmovdgeu\007fmovdgt\007fmovdgu\006fmovd"
3392 "l\007fmovdle\010fmovdleu\007fmovdlg\007fmovdlt\007fmovdlu\006fmovdn\007"
3393 "fmovdne\010fmovdneg\007fmovdnz\006fmovdo\010fmovdpos\006fmovdu\007fmovd"
3394 "ue\007fmovdug\010fmovduge\007fmovdul\010fmovdule\007fmovdvc\007fmovdvs\006"
3395 "fmovdz\005fmovq\006fmovqa\007fmovqcc\007fmovqcs\006fmovqe\007fmovqeq\006"
3396 "fmovqg\007fmovqge\010fmovqgeu\007fmovqgt\007fmovqgu\006fmovql\007fmovql"
3397 "e\010fmovqleu\007fmovqlg\007fmovqlt\007fmovqlu\006fmovqn\007fmovqne\010"
3398 "fmovqneg\007fmovqnz\006fmovqo\010fmovqpos\006fmovqu\007fmovque\007fmovq"
3399 "ug\010fmovquge\007fmovqul\010fmovqule\007fmovqvc\007fmovqvs\006fmovqz\006"
3400 "fmovrd\007fmovrde\tfmovrdgez\010fmovrdgz\tfmovrdlez\010fmovrdlz\010fmov"
3401 "rdne\010fmovrdnz\007fmovrdz\006fmovrq\007fmovrqe\tfmovrqgez\010fmovrqgz"
3402 "\tfmovrqlez\010fmovrqlz\010fmovrqne\010fmovrqnz\007fmovrqz\006fmovrs\007"
3403 "fmovrse\tfmovrsgez\010fmovrsgz\tfmovrslez\010fmovrslz\010fmovrsne\010fm"
3404 "ovrsnz\007fmovrsz\005fmovs\006fmovsa\007fmovscc\007fmovscs\006fmovse\007"
3405 "fmovseq\006fmovsg\007fmovsge\010fmovsgeu\007fmovsgt\007fmovsgu\006fmovs"
3406 "l\007fmovsle\010fmovsleu\007fmovslg\007fmovslt\007fmovslu\006fmovsn\007"
3407 "fmovsne\010fmovsneg\007fmovsnz\006fmovso\010fmovspos\006fmovsu\007fmovs"
3408 "ue\007fmovsug\010fmovsuge\007fmovsul\010fmovsule\007fmovsvc\007fmovsvs\006"
3409 "fmovsz\006fmsubd\006fmsubs\nfmul8sux16\nfmul8ulx16\010fmul8x16\nfmul8x1"
3410 "6al\nfmul8x16au\005fmuld\013fmuld8sux16\013fmuld8ulx16\005fmulq\005fmul"
3411 "s\006fnaddd\006fnadds\005fnand\006fnands\005fnegd\005fnegq\005fnegs\007"
3412 "fnhaddd\007fnhadds\007fnmaddd\007fnmadds\007fnmsubd\007fnmsubs\006fnmul"
3413 "d\006fnmuls\004fnor\005fnors\005fnot1\006fnot1s\005fnot2\006fnot2s\007f"
3414 "nsmuld\004fone\005fones\003for\007fornot1\010fornot1s\007fornot2\010for"
3415 "not2s\004fors\007fpack16\007fpack32\010fpackfix\007fpadd16\010fpadd16s\007"
3416 "fpadd32\010fpadd32s\007fpadd64\007fpmaddx\tfpmaddxhi\007fpmerge\007fpsu"
3417 "b16\010fpsub16s\007fpsub32\010fpsub32s\005fqtod\005fqtoi\005fqtos\005fq"
3418 "tox\007fslas16\007fslas32\006fsll16\006fsll32\006fsmuld\006fsqrtd\006fs"
3419 "qrtq\006fsqrts\006fsra16\006fsra32\005fsrc1\006fsrc1s\005fsrc2\006fsrc2"
3420 "s\006fsrl16\006fsrl32\005fstod\005fstoi\005fstoq\005fstox\005fsubd\005f"
3421 "subq\005fsubs\005fxnor\006fxnors\004fxor\005fxors\005fxtod\005fxtoq\005"
3422 "fxtos\005fzero\006fzeros\003inc\005inccc\006invalw\003jmp\004jmpl\002ld"
3423 "\003lda\003ldd\004ldda\003ldq\004ldqa\004ldsb\005ldsba\004ldsh\005ldsha"
3424 "\006ldstub\007ldstuba\004ldsw\005ldswa\004ldub\005lduba\004lduh\005lduh"
3425 "a\003ldx\004ldxa\005lzcnt\003md5\006membar\007montmul\007montsqr\003mov"
3426 "\004mova\005movcc\005movcs\007movdtox\004move\005moveq\004movg\005movge"
3427 "\006movgeu\005movgt\005movgu\004movl\005movle\006movleu\005movlg\005mov"
3428 "lt\005movlu\004movn\005movne\006movneg\005movnz\004movo\006movpos\004mo"
3429 "vr\005movre\007movrgez\006movrgz\007movrlez\006movrlz\006movrne\006movr"
3430 "nz\005movrz\010movstosw\010movstouw\004movu\005movue\005movug\006movuge"
3431 "\005movul\006movule\005movvc\005movvs\007movwtos\007movxtod\004movz\005"
3432 "mpmul\006mulscc\004mulx\003neg\003nop\007normalw\003not\002or\004orcc\003"
3433 "orn\005orncc\006otherw\005pause\005pdist\006pdistn\004popc\010prefetch\t"
3434 "prefetcha\003pwr\002rd\004rdpr\007restore\010restored\003ret\004retl\005"
3435 "retry\004rett\004save\005saved\004sdiv\006sdivcc\005sdivx\003set\005set"
3436 "hi\005setsw\004setx\004sha1\006sha256\006sha512\010shutdown\004siam\005"
3437 "signx\003sir\003sll\004sllx\004smac\004smul\006smulcc\003sra\004srax\003"
3438 "srl\004srlx\002st\003sta\003stb\004stba\005stbar\003std\004stda\003sth\004"
3439 "stha\003stq\004stqa\003stx\004stxa\003sub\005subcc\004subx\006subxcc\004"
3440 "swap\005swapa\001t\002ta\006taddcc\010taddcctv\003tcc\003tcs\002te\003t"
3441 "eq\002tg\003tge\004tgeu\003tgt\003tgu\002tl\003tle\004tleu\003tlt\003tl"
3442 "u\002tn\003tne\004tneg\003tnz\004tpos\003tst\006tsubcc\010tsubcctv\003t"
3443 "vc\003tvs\002tz\004udiv\006udivcc\005udivx\004umac\004umul\006umulcc\007"
3444 "umulxhi\005unimp\002wr\004wrpr\005xmulx\007xmulxhi\004xnor\006xnorcc\003"
3445 "xor\005xorcc";
3446
3447// Feature bitsets.
3448enum : uint8_t {
3449 AMFBS_None,
3450 AMFBS_HasCASA,
3451 AMFBS_HasCrypto,
3452 AMFBS_HasOSA2011,
3453 AMFBS_HasPWRPSR,
3454 AMFBS_HasUA2005,
3455 AMFBS_HasUA2007,
3456 AMFBS_HasV9,
3457 AMFBS_HasVIS,
3458 AMFBS_HasVIS2,
3459 AMFBS_HasVIS3,
3460 AMFBS_Is64Bit,
3461 AMFBS_HasV9_Is32Bit,
3462 AMFBS_HasV9_Is64Bit,
3463 AMFBS_Is32Bit_HasV9,
3464 AMFBS_Is64Bit_HasV9,
3465};
3466
3467static constexpr FeatureBitset FeatureBitsets[] = {
3468 {}, // AMFBS_None
3469 {Feature_HasCASABit, },
3470 {Feature_HasCryptoBit, },
3471 {Feature_HasOSA2011Bit, },
3472 {Feature_HasPWRPSRBit, },
3473 {Feature_HasUA2005Bit, },
3474 {Feature_HasUA2007Bit, },
3475 {Feature_HasV9Bit, },
3476 {Feature_HasVISBit, },
3477 {Feature_HasVIS2Bit, },
3478 {Feature_HasVIS3Bit, },
3479 {Feature_Is64BitBit, },
3480 {Feature_HasV9Bit, Feature_Is32BitBit, },
3481 {Feature_HasV9Bit, Feature_Is64BitBit, },
3482 {Feature_Is32BitBit, Feature_HasV9Bit, },
3483 {Feature_Is64BitBit, Feature_HasV9Bit, },
3484};
3485
3486namespace {
3487 struct MatchEntry {
3488 uint16_t Mnemonic;
3489 uint32_t Opcode;
3490 uint16_t ConvertFn;
3491 uint8_t RequiredFeaturesIdx;
3492 uint8_t Classes[6];
3493 StringRef getMnemonic() const {
3494 return StringRef(MnemonicTable + Mnemonic + 1,
3495 MnemonicTable[Mnemonic]);
3496 }
3497 };
3498
3499 // Predicate for searching for an opcode.
3500 struct LessOpcode {
3501 bool operator()(const MatchEntry &LHS, StringRef RHS) {
3502 return LHS.getMnemonic() < RHS;
3503 }
3504 bool operator()(StringRef LHS, const MatchEntry &RHS) {
3505 return LHS < RHS.getMnemonic();
3506 }
3507 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
3508 return LHS.getMnemonic() < RHS.getMnemonic();
3509 }
3510 };
3511} // end anonymous namespace
3512
3513static const MatchEntry MatchTable0[] = {
3514 { 0 /* add */, SP::ADDrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3515 { 0 /* add */, SP::ADDri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3516 { 0 /* add */, SP::TLS_ADDrr, Convert__Reg1_2__Reg1_0__Reg1_1__TailRelocSymAdd_TLS1_3, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs, MCK_TailRelocSymAdd_TLS }, },
3517 { 4 /* addcc */, SP::ADDCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3518 { 4 /* addcc */, SP::ADDCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3519 { 10 /* addx */, SP::ADDCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3520 { 10 /* addx */, SP::ADDCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3521 { 10 /* addx */, SP::ADDCri, Convert__Reg1_2__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK_IntRegs }, },
3522 { 15 /* addxc */, SP::ADDXC, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3523 { 21 /* addxcc */, SP::ADDErr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3524 { 21 /* addxcc */, SP::ADDEri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3525 { 28 /* addxccc */, SP::ADDXCCC, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3526 { 36 /* aes_dround01 */, SP::AES_DROUND01, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3527 { 49 /* aes_dround01_l */, SP::AES_DROUND01_LAST, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3528 { 64 /* aes_dround23 */, SP::AES_DROUND23, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3529 { 77 /* aes_dround23_l */, SP::AES_DROUND23_LAST, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3530 { 92 /* aes_eround01 */, SP::AES_EROUND01, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3531 { 105 /* aes_eround01_l */, SP::AES_EROUND01_LAST, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3532 { 120 /* aes_eround23 */, SP::AES_EROUND23, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3533 { 133 /* aes_eround23_l */, SP::AES_EROUND23_LAST, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3534 { 148 /* aes_kexpand0 */, SP::AES_KEXPAND0, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3535 { 161 /* aes_kexpand1 */, SP::AES_KEXPAND1, Convert__Reg1_3__Reg1_0__Reg1_1__Imm1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_Imm, MCK_DFPRegs }, },
3536 { 174 /* aes_kexpand2 */, SP::AES_KEXPAND2, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3537 { 187 /* alignaddr */, SP::ALIGNADDR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3538 { 197 /* alignaddrl */, SP::ALIGNADDRL, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3539 { 208 /* allclean */, SP::ALLCLEAN, Convert_NoOperands, AMFBS_HasUA2005, { }, },
3540 { 217 /* and */, SP::ANDrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3541 { 217 /* and */, SP::ANDri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3542 { 221 /* andcc */, SP::ANDCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3543 { 221 /* andcc */, SP::ANDCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3544 { 227 /* andn */, SP::ANDNrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3545 { 227 /* andn */, SP::ANDNri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3546 { 232 /* andncc */, SP::ANDNCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3547 { 232 /* andncc */, SP::ANDNCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3548 { 239 /* array16 */, SP::ARRAY16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3549 { 247 /* array32 */, SP::ARRAY32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3550 { 255 /* array8 */, SP::ARRAY8, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3551 { 262 /* b */, SP::BCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
3552 { 262 /* b */, SP::BPICC, Convert__Imm1_1__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3553 { 262 /* b */, SP::BPXCC, Convert__Imm1_1__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3554 { 262 /* b */, SP::BPXCC, Convert__Imm1_1__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3555 { 262 /* b */, SP::BCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
3556 { 262 /* b */, SP::BPICC, Convert__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3557 { 262 /* b */, SP::BCOND, Convert__Imm1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Imm }, },
3558 { 262 /* b */, SP::BPICCA, Convert__Imm1_2__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3559 { 262 /* b */, SP::BPXCCA, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3560 { 262 /* b */, SP::BPXCCA, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3561 { 262 /* b */, SP::BPICCA, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3562 { 262 /* b */, SP::BPICCNT, Convert__Imm1_2__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3563 { 262 /* b */, SP::BPXCCNT, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3564 { 262 /* b */, SP::BPXCCNT, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3565 { 262 /* b */, SP::BPICCNT, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3566 { 262 /* b */, SP::BPICC, Convert__Imm1_2__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3567 { 262 /* b */, SP::BPXCC, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3568 { 262 /* b */, SP::BPXCC, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3569 { 262 /* b */, SP::BPICC, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3570 { 262 /* b */, SP::BPXCC, Convert__Imm1_2__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_Imm }, },
3571 { 262 /* b */, SP::BCONDA, Convert__Imm1_2__Imm1_0, AMFBS_None, { MCK_Imm, MCK_a, MCK_Imm }, },
3572 { 262 /* b */, SP::BPICC, Convert__Imm1_2__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_Imm }, },
3573 { 262 /* b */, SP::BPICCANT, Convert__Imm1_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3574 { 262 /* b */, SP::BPXCCANT, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3575 { 262 /* b */, SP::BPXCCANT, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3576 { 262 /* b */, SP::BPICCANT, Convert__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3577 { 262 /* b */, SP::BPICCA, Convert__Imm1_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3578 { 262 /* b */, SP::BPXCCA, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3579 { 262 /* b */, SP::BPXCCA, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3580 { 262 /* b */, SP::BPICCA, Convert__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3581 { 262 /* b */, SP::BPXCCA, Convert__Imm1_3__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3582 { 262 /* b */, SP::BPICCA, Convert__Imm1_3__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_ICC, MCK_Imm }, },
3583 { 262 /* b */, SP::BPXCCNT, Convert__Imm1_3__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3584 { 262 /* b */, SP::BPICCNT, Convert__Imm1_3__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_pn, MCK_ICC, MCK_Imm }, },
3585 { 262 /* b */, SP::BPXCCANT, Convert__Imm1_4__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3586 { 262 /* b */, SP::BPICCANT, Convert__Imm1_4__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3587 { 264 /* ba */, SP::BA, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
3588 { 264 /* ba */, SP::BCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
3589 { 264 /* ba */, SP::BPICC, Convert__Imm1_1__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3590 { 264 /* ba */, SP::BPXCC, Convert__Imm1_1__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3591 { 264 /* ba */, SP::BPXCC, Convert__Imm1_1__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3592 { 264 /* ba */, SP::BCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
3593 { 264 /* ba */, SP::BPICC, Convert__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3594 { 264 /* ba */, SP::BPICCA, Convert__Imm1_2__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3595 { 264 /* ba */, SP::BPXCCA, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3596 { 264 /* ba */, SP::BPXCCA, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3597 { 264 /* ba */, SP::BPICCA, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3598 { 264 /* ba */, SP::BPICCNT, Convert__Imm1_2__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3599 { 264 /* ba */, SP::BPXCCNT, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3600 { 264 /* ba */, SP::BPXCCNT, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3601 { 264 /* ba */, SP::BPICCNT, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3602 { 264 /* ba */, SP::BPICC, Convert__Imm1_2__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3603 { 264 /* ba */, SP::BPXCC, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3604 { 264 /* ba */, SP::BPXCC, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3605 { 264 /* ba */, SP::BPICC, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3606 { 264 /* ba */, SP::BPICCANT, Convert__Imm1_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3607 { 264 /* ba */, SP::BPXCCANT, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3608 { 264 /* ba */, SP::BPXCCANT, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3609 { 264 /* ba */, SP::BPICCANT, Convert__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3610 { 264 /* ba */, SP::BPICCA, Convert__Imm1_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3611 { 264 /* ba */, SP::BPXCCA, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3612 { 264 /* ba */, SP::BPXCCA, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3613 { 264 /* ba */, SP::BPICCA, Convert__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3614 { 267 /* bcc */, SP::BCOND, Convert__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
3615 { 267 /* bcc */, SP::BPICC, Convert__Imm1_1__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3616 { 267 /* bcc */, SP::BPXCC, Convert__Imm1_1__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3617 { 267 /* bcc */, SP::BPXCC, Convert__Imm1_1__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3618 { 267 /* bcc */, SP::BCONDA, Convert__Imm1_1__imm_95_13, AMFBS_None, { MCK_a, MCK_Imm }, },
3619 { 267 /* bcc */, SP::BPICC, Convert__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3620 { 267 /* bcc */, SP::BPICCA, Convert__Imm1_2__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3621 { 267 /* bcc */, SP::BPXCCA, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3622 { 267 /* bcc */, SP::BPXCCA, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3623 { 267 /* bcc */, SP::BPICCA, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3624 { 267 /* bcc */, SP::BPICCNT, Convert__Imm1_2__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3625 { 267 /* bcc */, SP::BPXCCNT, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3626 { 267 /* bcc */, SP::BPXCCNT, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3627 { 267 /* bcc */, SP::BPICCNT, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3628 { 267 /* bcc */, SP::BPICC, Convert__Imm1_2__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3629 { 267 /* bcc */, SP::BPXCC, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3630 { 267 /* bcc */, SP::BPXCC, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3631 { 267 /* bcc */, SP::BPICC, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3632 { 267 /* bcc */, SP::BPICCANT, Convert__Imm1_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3633 { 267 /* bcc */, SP::BPXCCANT, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3634 { 267 /* bcc */, SP::BPXCCANT, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3635 { 267 /* bcc */, SP::BPICCANT, Convert__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3636 { 267 /* bcc */, SP::BPICCA, Convert__Imm1_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3637 { 267 /* bcc */, SP::BPXCCA, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3638 { 267 /* bcc */, SP::BPXCCA, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3639 { 267 /* bcc */, SP::BPICCA, Convert__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3640 { 271 /* bclr */, SP::ANDNrr, Convert__Reg1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
3641 { 271 /* bclr */, SP::ANDNri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
3642 { 276 /* bcs */, SP::BCOND, Convert__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
3643 { 276 /* bcs */, SP::BPICC, Convert__Imm1_1__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3644 { 276 /* bcs */, SP::BPXCC, Convert__Imm1_1__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3645 { 276 /* bcs */, SP::BPXCC, Convert__Imm1_1__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3646 { 276 /* bcs */, SP::BCONDA, Convert__Imm1_1__imm_95_5, AMFBS_None, { MCK_a, MCK_Imm }, },
3647 { 276 /* bcs */, SP::BPICC, Convert__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3648 { 276 /* bcs */, SP::BPICCA, Convert__Imm1_2__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3649 { 276 /* bcs */, SP::BPXCCA, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3650 { 276 /* bcs */, SP::BPXCCA, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3651 { 276 /* bcs */, SP::BPICCA, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3652 { 276 /* bcs */, SP::BPICCNT, Convert__Imm1_2__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3653 { 276 /* bcs */, SP::BPXCCNT, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3654 { 276 /* bcs */, SP::BPXCCNT, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3655 { 276 /* bcs */, SP::BPICCNT, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3656 { 276 /* bcs */, SP::BPICC, Convert__Imm1_2__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3657 { 276 /* bcs */, SP::BPXCC, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3658 { 276 /* bcs */, SP::BPXCC, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3659 { 276 /* bcs */, SP::BPICC, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3660 { 276 /* bcs */, SP::BPICCANT, Convert__Imm1_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3661 { 276 /* bcs */, SP::BPXCCANT, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3662 { 276 /* bcs */, SP::BPXCCANT, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3663 { 276 /* bcs */, SP::BPICCANT, Convert__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3664 { 276 /* bcs */, SP::BPICCA, Convert__Imm1_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3665 { 276 /* bcs */, SP::BPXCCA, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3666 { 276 /* bcs */, SP::BPXCCA, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3667 { 276 /* bcs */, SP::BPICCA, Convert__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3668 { 280 /* be */, SP::BCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
3669 { 280 /* be */, SP::BPICC, Convert__Imm1_1__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3670 { 280 /* be */, SP::BPXCC, Convert__Imm1_1__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3671 { 280 /* be */, SP::BPXCC, Convert__Imm1_1__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3672 { 280 /* be */, SP::BCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
3673 { 280 /* be */, SP::BPICC, Convert__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3674 { 280 /* be */, SP::BPICCA, Convert__Imm1_2__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3675 { 280 /* be */, SP::BPXCCA, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3676 { 280 /* be */, SP::BPXCCA, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3677 { 280 /* be */, SP::BPICCA, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3678 { 280 /* be */, SP::BPICCNT, Convert__Imm1_2__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3679 { 280 /* be */, SP::BPXCCNT, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3680 { 280 /* be */, SP::BPXCCNT, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3681 { 280 /* be */, SP::BPICCNT, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3682 { 280 /* be */, SP::BPICC, Convert__Imm1_2__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3683 { 280 /* be */, SP::BPXCC, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3684 { 280 /* be */, SP::BPXCC, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3685 { 280 /* be */, SP::BPICC, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3686 { 280 /* be */, SP::BPICCANT, Convert__Imm1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3687 { 280 /* be */, SP::BPXCCANT, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3688 { 280 /* be */, SP::BPXCCANT, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3689 { 280 /* be */, SP::BPICCANT, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3690 { 280 /* be */, SP::BPICCA, Convert__Imm1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3691 { 280 /* be */, SP::BPXCCA, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3692 { 280 /* be */, SP::BPXCCA, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3693 { 280 /* be */, SP::BPICCA, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3694 { 283 /* beq */, SP::BCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
3695 { 283 /* beq */, SP::BPICC, Convert__Imm1_1__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3696 { 283 /* beq */, SP::BPXCC, Convert__Imm1_1__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3697 { 283 /* beq */, SP::BPXCC, Convert__Imm1_1__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3698 { 283 /* beq */, SP::BCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
3699 { 283 /* beq */, SP::BPICC, Convert__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3700 { 283 /* beq */, SP::BPICCA, Convert__Imm1_2__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3701 { 283 /* beq */, SP::BPXCCA, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3702 { 283 /* beq */, SP::BPXCCA, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3703 { 283 /* beq */, SP::BPICCA, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3704 { 283 /* beq */, SP::BPICCNT, Convert__Imm1_2__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3705 { 283 /* beq */, SP::BPXCCNT, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3706 { 283 /* beq */, SP::BPXCCNT, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3707 { 283 /* beq */, SP::BPICCNT, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3708 { 283 /* beq */, SP::BPICC, Convert__Imm1_2__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3709 { 283 /* beq */, SP::BPXCC, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3710 { 283 /* beq */, SP::BPXCC, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3711 { 283 /* beq */, SP::BPICC, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3712 { 283 /* beq */, SP::BPICCANT, Convert__Imm1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3713 { 283 /* beq */, SP::BPXCCANT, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3714 { 283 /* beq */, SP::BPXCCANT, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3715 { 283 /* beq */, SP::BPICCANT, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3716 { 283 /* beq */, SP::BPICCA, Convert__Imm1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3717 { 283 /* beq */, SP::BPXCCA, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3718 { 283 /* beq */, SP::BPXCCA, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3719 { 283 /* beq */, SP::BPICCA, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3720 { 287 /* bg */, SP::BCOND, Convert__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
3721 { 287 /* bg */, SP::BPICC, Convert__Imm1_1__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3722 { 287 /* bg */, SP::BPXCC, Convert__Imm1_1__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3723 { 287 /* bg */, SP::BPXCC, Convert__Imm1_1__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3724 { 287 /* bg */, SP::BCONDA, Convert__Imm1_1__imm_95_10, AMFBS_None, { MCK_a, MCK_Imm }, },
3725 { 287 /* bg */, SP::BPICC, Convert__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3726 { 287 /* bg */, SP::BPICCA, Convert__Imm1_2__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3727 { 287 /* bg */, SP::BPXCCA, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3728 { 287 /* bg */, SP::BPXCCA, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3729 { 287 /* bg */, SP::BPICCA, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3730 { 287 /* bg */, SP::BPICCNT, Convert__Imm1_2__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3731 { 287 /* bg */, SP::BPXCCNT, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3732 { 287 /* bg */, SP::BPXCCNT, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3733 { 287 /* bg */, SP::BPICCNT, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3734 { 287 /* bg */, SP::BPICC, Convert__Imm1_2__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3735 { 287 /* bg */, SP::BPXCC, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3736 { 287 /* bg */, SP::BPXCC, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3737 { 287 /* bg */, SP::BPICC, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3738 { 287 /* bg */, SP::BPICCANT, Convert__Imm1_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3739 { 287 /* bg */, SP::BPXCCANT, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3740 { 287 /* bg */, SP::BPXCCANT, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3741 { 287 /* bg */, SP::BPICCANT, Convert__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3742 { 287 /* bg */, SP::BPICCA, Convert__Imm1_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3743 { 287 /* bg */, SP::BPXCCA, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3744 { 287 /* bg */, SP::BPXCCA, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3745 { 287 /* bg */, SP::BPICCA, Convert__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3746 { 290 /* bge */, SP::BCOND, Convert__Imm1_0__imm_95_11, AMFBS_None, { MCK_Imm }, },
3747 { 290 /* bge */, SP::BPICC, Convert__Imm1_1__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3748 { 290 /* bge */, SP::BPXCC, Convert__Imm1_1__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3749 { 290 /* bge */, SP::BPXCC, Convert__Imm1_1__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3750 { 290 /* bge */, SP::BCONDA, Convert__Imm1_1__imm_95_11, AMFBS_None, { MCK_a, MCK_Imm }, },
3751 { 290 /* bge */, SP::BPICC, Convert__Imm1_1__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3752 { 290 /* bge */, SP::BPICCA, Convert__Imm1_2__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3753 { 290 /* bge */, SP::BPXCCA, Convert__Imm1_2__imm_95_11, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3754 { 290 /* bge */, SP::BPXCCA, Convert__Imm1_2__imm_95_11, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3755 { 290 /* bge */, SP::BPICCA, Convert__Imm1_2__imm_95_11, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3756 { 290 /* bge */, SP::BPICCNT, Convert__Imm1_2__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3757 { 290 /* bge */, SP::BPXCCNT, Convert__Imm1_2__imm_95_11, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3758 { 290 /* bge */, SP::BPXCCNT, Convert__Imm1_2__imm_95_11, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3759 { 290 /* bge */, SP::BPICCNT, Convert__Imm1_2__imm_95_11, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3760 { 290 /* bge */, SP::BPICC, Convert__Imm1_2__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3761 { 290 /* bge */, SP::BPXCC, Convert__Imm1_2__imm_95_11, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3762 { 290 /* bge */, SP::BPXCC, Convert__Imm1_2__imm_95_11, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3763 { 290 /* bge */, SP::BPICC, Convert__Imm1_2__imm_95_11, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3764 { 290 /* bge */, SP::BPICCANT, Convert__Imm1_3__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3765 { 290 /* bge */, SP::BPXCCANT, Convert__Imm1_3__imm_95_11, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3766 { 290 /* bge */, SP::BPXCCANT, Convert__Imm1_3__imm_95_11, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3767 { 290 /* bge */, SP::BPICCANT, Convert__Imm1_3__imm_95_11, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3768 { 290 /* bge */, SP::BPICCA, Convert__Imm1_3__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3769 { 290 /* bge */, SP::BPXCCA, Convert__Imm1_3__imm_95_11, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3770 { 290 /* bge */, SP::BPXCCA, Convert__Imm1_3__imm_95_11, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3771 { 290 /* bge */, SP::BPICCA, Convert__Imm1_3__imm_95_11, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3772 { 294 /* bgeu */, SP::BCOND, Convert__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
3773 { 294 /* bgeu */, SP::BPICC, Convert__Imm1_1__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3774 { 294 /* bgeu */, SP::BPXCC, Convert__Imm1_1__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3775 { 294 /* bgeu */, SP::BPXCC, Convert__Imm1_1__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3776 { 294 /* bgeu */, SP::BCONDA, Convert__Imm1_1__imm_95_13, AMFBS_None, { MCK_a, MCK_Imm }, },
3777 { 294 /* bgeu */, SP::BPICC, Convert__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3778 { 294 /* bgeu */, SP::BPICCA, Convert__Imm1_2__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3779 { 294 /* bgeu */, SP::BPXCCA, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3780 { 294 /* bgeu */, SP::BPXCCA, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3781 { 294 /* bgeu */, SP::BPICCA, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3782 { 294 /* bgeu */, SP::BPICCNT, Convert__Imm1_2__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3783 { 294 /* bgeu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3784 { 294 /* bgeu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3785 { 294 /* bgeu */, SP::BPICCNT, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3786 { 294 /* bgeu */, SP::BPICC, Convert__Imm1_2__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3787 { 294 /* bgeu */, SP::BPXCC, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3788 { 294 /* bgeu */, SP::BPXCC, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3789 { 294 /* bgeu */, SP::BPICC, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3790 { 294 /* bgeu */, SP::BPICCANT, Convert__Imm1_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3791 { 294 /* bgeu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3792 { 294 /* bgeu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3793 { 294 /* bgeu */, SP::BPICCANT, Convert__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3794 { 294 /* bgeu */, SP::BPICCA, Convert__Imm1_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3795 { 294 /* bgeu */, SP::BPXCCA, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3796 { 294 /* bgeu */, SP::BPXCCA, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3797 { 294 /* bgeu */, SP::BPICCA, Convert__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3798 { 299 /* bgt */, SP::BCOND, Convert__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
3799 { 299 /* bgt */, SP::BPICC, Convert__Imm1_1__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3800 { 299 /* bgt */, SP::BPXCC, Convert__Imm1_1__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3801 { 299 /* bgt */, SP::BPXCC, Convert__Imm1_1__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3802 { 299 /* bgt */, SP::BCONDA, Convert__Imm1_1__imm_95_10, AMFBS_None, { MCK_a, MCK_Imm }, },
3803 { 299 /* bgt */, SP::BPICC, Convert__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3804 { 299 /* bgt */, SP::BPICCA, Convert__Imm1_2__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3805 { 299 /* bgt */, SP::BPXCCA, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3806 { 299 /* bgt */, SP::BPXCCA, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3807 { 299 /* bgt */, SP::BPICCA, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3808 { 299 /* bgt */, SP::BPICCNT, Convert__Imm1_2__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3809 { 299 /* bgt */, SP::BPXCCNT, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3810 { 299 /* bgt */, SP::BPXCCNT, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3811 { 299 /* bgt */, SP::BPICCNT, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3812 { 299 /* bgt */, SP::BPICC, Convert__Imm1_2__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3813 { 299 /* bgt */, SP::BPXCC, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3814 { 299 /* bgt */, SP::BPXCC, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3815 { 299 /* bgt */, SP::BPICC, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3816 { 299 /* bgt */, SP::BPICCANT, Convert__Imm1_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3817 { 299 /* bgt */, SP::BPXCCANT, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3818 { 299 /* bgt */, SP::BPXCCANT, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3819 { 299 /* bgt */, SP::BPICCANT, Convert__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3820 { 299 /* bgt */, SP::BPICCA, Convert__Imm1_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3821 { 299 /* bgt */, SP::BPXCCA, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3822 { 299 /* bgt */, SP::BPXCCA, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3823 { 299 /* bgt */, SP::BPICCA, Convert__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3824 { 303 /* bgu */, SP::BCOND, Convert__Imm1_0__imm_95_12, AMFBS_None, { MCK_Imm }, },
3825 { 303 /* bgu */, SP::BPICC, Convert__Imm1_1__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3826 { 303 /* bgu */, SP::BPXCC, Convert__Imm1_1__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3827 { 303 /* bgu */, SP::BPXCC, Convert__Imm1_1__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3828 { 303 /* bgu */, SP::BCONDA, Convert__Imm1_1__imm_95_12, AMFBS_None, { MCK_a, MCK_Imm }, },
3829 { 303 /* bgu */, SP::BPICC, Convert__Imm1_1__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3830 { 303 /* bgu */, SP::BPICCA, Convert__Imm1_2__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3831 { 303 /* bgu */, SP::BPXCCA, Convert__Imm1_2__imm_95_12, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3832 { 303 /* bgu */, SP::BPXCCA, Convert__Imm1_2__imm_95_12, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3833 { 303 /* bgu */, SP::BPICCA, Convert__Imm1_2__imm_95_12, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3834 { 303 /* bgu */, SP::BPICCNT, Convert__Imm1_2__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3835 { 303 /* bgu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_12, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3836 { 303 /* bgu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_12, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3837 { 303 /* bgu */, SP::BPICCNT, Convert__Imm1_2__imm_95_12, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3838 { 303 /* bgu */, SP::BPICC, Convert__Imm1_2__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3839 { 303 /* bgu */, SP::BPXCC, Convert__Imm1_2__imm_95_12, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3840 { 303 /* bgu */, SP::BPXCC, Convert__Imm1_2__imm_95_12, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3841 { 303 /* bgu */, SP::BPICC, Convert__Imm1_2__imm_95_12, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3842 { 303 /* bgu */, SP::BPICCANT, Convert__Imm1_3__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3843 { 303 /* bgu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_12, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3844 { 303 /* bgu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_12, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3845 { 303 /* bgu */, SP::BPICCANT, Convert__Imm1_3__imm_95_12, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3846 { 303 /* bgu */, SP::BPICCA, Convert__Imm1_3__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3847 { 303 /* bgu */, SP::BPXCCA, Convert__Imm1_3__imm_95_12, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3848 { 303 /* bgu */, SP::BPXCCA, Convert__Imm1_3__imm_95_12, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3849 { 303 /* bgu */, SP::BPICCA, Convert__Imm1_3__imm_95_12, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3850 { 307 /* bl */, SP::BCOND, Convert__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
3851 { 307 /* bl */, SP::BPICC, Convert__Imm1_1__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3852 { 307 /* bl */, SP::BPXCC, Convert__Imm1_1__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3853 { 307 /* bl */, SP::BPXCC, Convert__Imm1_1__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3854 { 307 /* bl */, SP::BCONDA, Convert__Imm1_1__imm_95_3, AMFBS_None, { MCK_a, MCK_Imm }, },
3855 { 307 /* bl */, SP::BPICC, Convert__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3856 { 307 /* bl */, SP::BPICCA, Convert__Imm1_2__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3857 { 307 /* bl */, SP::BPXCCA, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3858 { 307 /* bl */, SP::BPXCCA, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3859 { 307 /* bl */, SP::BPICCA, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3860 { 307 /* bl */, SP::BPICCNT, Convert__Imm1_2__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3861 { 307 /* bl */, SP::BPXCCNT, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3862 { 307 /* bl */, SP::BPXCCNT, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3863 { 307 /* bl */, SP::BPICCNT, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3864 { 307 /* bl */, SP::BPICC, Convert__Imm1_2__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3865 { 307 /* bl */, SP::BPXCC, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3866 { 307 /* bl */, SP::BPXCC, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3867 { 307 /* bl */, SP::BPICC, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3868 { 307 /* bl */, SP::BPICCANT, Convert__Imm1_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3869 { 307 /* bl */, SP::BPXCCANT, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3870 { 307 /* bl */, SP::BPXCCANT, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3871 { 307 /* bl */, SP::BPICCANT, Convert__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3872 { 307 /* bl */, SP::BPICCA, Convert__Imm1_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3873 { 307 /* bl */, SP::BPXCCA, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3874 { 307 /* bl */, SP::BPXCCA, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3875 { 307 /* bl */, SP::BPICCA, Convert__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3876 { 310 /* ble */, SP::BCOND, Convert__Imm1_0__imm_95_2, AMFBS_None, { MCK_Imm }, },
3877 { 310 /* ble */, SP::BPICC, Convert__Imm1_1__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3878 { 310 /* ble */, SP::BPXCC, Convert__Imm1_1__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3879 { 310 /* ble */, SP::BPXCC, Convert__Imm1_1__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3880 { 310 /* ble */, SP::BCONDA, Convert__Imm1_1__imm_95_2, AMFBS_None, { MCK_a, MCK_Imm }, },
3881 { 310 /* ble */, SP::BPICC, Convert__Imm1_1__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3882 { 310 /* ble */, SP::BPICCA, Convert__Imm1_2__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3883 { 310 /* ble */, SP::BPXCCA, Convert__Imm1_2__imm_95_2, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3884 { 310 /* ble */, SP::BPXCCA, Convert__Imm1_2__imm_95_2, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3885 { 310 /* ble */, SP::BPICCA, Convert__Imm1_2__imm_95_2, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3886 { 310 /* ble */, SP::BPICCNT, Convert__Imm1_2__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3887 { 310 /* ble */, SP::BPXCCNT, Convert__Imm1_2__imm_95_2, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3888 { 310 /* ble */, SP::BPXCCNT, Convert__Imm1_2__imm_95_2, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3889 { 310 /* ble */, SP::BPICCNT, Convert__Imm1_2__imm_95_2, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3890 { 310 /* ble */, SP::BPICC, Convert__Imm1_2__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3891 { 310 /* ble */, SP::BPXCC, Convert__Imm1_2__imm_95_2, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3892 { 310 /* ble */, SP::BPXCC, Convert__Imm1_2__imm_95_2, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3893 { 310 /* ble */, SP::BPICC, Convert__Imm1_2__imm_95_2, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3894 { 310 /* ble */, SP::BPICCANT, Convert__Imm1_3__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3895 { 310 /* ble */, SP::BPXCCANT, Convert__Imm1_3__imm_95_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3896 { 310 /* ble */, SP::BPXCCANT, Convert__Imm1_3__imm_95_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3897 { 310 /* ble */, SP::BPICCANT, Convert__Imm1_3__imm_95_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3898 { 310 /* ble */, SP::BPICCA, Convert__Imm1_3__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3899 { 310 /* ble */, SP::BPXCCA, Convert__Imm1_3__imm_95_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3900 { 310 /* ble */, SP::BPXCCA, Convert__Imm1_3__imm_95_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3901 { 310 /* ble */, SP::BPICCA, Convert__Imm1_3__imm_95_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3902 { 314 /* bleu */, SP::BCOND, Convert__Imm1_0__imm_95_4, AMFBS_None, { MCK_Imm }, },
3903 { 314 /* bleu */, SP::BPICC, Convert__Imm1_1__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3904 { 314 /* bleu */, SP::BPXCC, Convert__Imm1_1__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3905 { 314 /* bleu */, SP::BPXCC, Convert__Imm1_1__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3906 { 314 /* bleu */, SP::BCONDA, Convert__Imm1_1__imm_95_4, AMFBS_None, { MCK_a, MCK_Imm }, },
3907 { 314 /* bleu */, SP::BPICC, Convert__Imm1_1__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3908 { 314 /* bleu */, SP::BPICCA, Convert__Imm1_2__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3909 { 314 /* bleu */, SP::BPXCCA, Convert__Imm1_2__imm_95_4, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3910 { 314 /* bleu */, SP::BPXCCA, Convert__Imm1_2__imm_95_4, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3911 { 314 /* bleu */, SP::BPICCA, Convert__Imm1_2__imm_95_4, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3912 { 314 /* bleu */, SP::BPICCNT, Convert__Imm1_2__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3913 { 314 /* bleu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_4, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3914 { 314 /* bleu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_4, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3915 { 314 /* bleu */, SP::BPICCNT, Convert__Imm1_2__imm_95_4, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3916 { 314 /* bleu */, SP::BPICC, Convert__Imm1_2__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3917 { 314 /* bleu */, SP::BPXCC, Convert__Imm1_2__imm_95_4, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3918 { 314 /* bleu */, SP::BPXCC, Convert__Imm1_2__imm_95_4, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3919 { 314 /* bleu */, SP::BPICC, Convert__Imm1_2__imm_95_4, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3920 { 314 /* bleu */, SP::BPICCANT, Convert__Imm1_3__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3921 { 314 /* bleu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_4, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3922 { 314 /* bleu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_4, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3923 { 314 /* bleu */, SP::BPICCANT, Convert__Imm1_3__imm_95_4, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3924 { 314 /* bleu */, SP::BPICCA, Convert__Imm1_3__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3925 { 314 /* bleu */, SP::BPXCCA, Convert__Imm1_3__imm_95_4, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3926 { 314 /* bleu */, SP::BPXCCA, Convert__Imm1_3__imm_95_4, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3927 { 314 /* bleu */, SP::BPICCA, Convert__Imm1_3__imm_95_4, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3928 { 319 /* blt */, SP::BCOND, Convert__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
3929 { 319 /* blt */, SP::BPICC, Convert__Imm1_1__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3930 { 319 /* blt */, SP::BPXCC, Convert__Imm1_1__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3931 { 319 /* blt */, SP::BPXCC, Convert__Imm1_1__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3932 { 319 /* blt */, SP::BCONDA, Convert__Imm1_1__imm_95_3, AMFBS_None, { MCK_a, MCK_Imm }, },
3933 { 319 /* blt */, SP::BPICC, Convert__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3934 { 319 /* blt */, SP::BPICCA, Convert__Imm1_2__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3935 { 319 /* blt */, SP::BPXCCA, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3936 { 319 /* blt */, SP::BPXCCA, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3937 { 319 /* blt */, SP::BPICCA, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3938 { 319 /* blt */, SP::BPICCNT, Convert__Imm1_2__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3939 { 319 /* blt */, SP::BPXCCNT, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3940 { 319 /* blt */, SP::BPXCCNT, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3941 { 319 /* blt */, SP::BPICCNT, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3942 { 319 /* blt */, SP::BPICC, Convert__Imm1_2__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3943 { 319 /* blt */, SP::BPXCC, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3944 { 319 /* blt */, SP::BPXCC, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3945 { 319 /* blt */, SP::BPICC, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3946 { 319 /* blt */, SP::BPICCANT, Convert__Imm1_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3947 { 319 /* blt */, SP::BPXCCANT, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3948 { 319 /* blt */, SP::BPXCCANT, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3949 { 319 /* blt */, SP::BPICCANT, Convert__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3950 { 319 /* blt */, SP::BPICCA, Convert__Imm1_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3951 { 319 /* blt */, SP::BPXCCA, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3952 { 319 /* blt */, SP::BPXCCA, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3953 { 319 /* blt */, SP::BPICCA, Convert__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3954 { 323 /* blu */, SP::BCOND, Convert__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
3955 { 323 /* blu */, SP::BPICC, Convert__Imm1_1__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3956 { 323 /* blu */, SP::BPXCC, Convert__Imm1_1__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3957 { 323 /* blu */, SP::BPXCC, Convert__Imm1_1__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3958 { 323 /* blu */, SP::BCONDA, Convert__Imm1_1__imm_95_5, AMFBS_None, { MCK_a, MCK_Imm }, },
3959 { 323 /* blu */, SP::BPICC, Convert__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3960 { 323 /* blu */, SP::BPICCA, Convert__Imm1_2__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3961 { 323 /* blu */, SP::BPXCCA, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3962 { 323 /* blu */, SP::BPXCCA, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3963 { 323 /* blu */, SP::BPICCA, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3964 { 323 /* blu */, SP::BPICCNT, Convert__Imm1_2__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3965 { 323 /* blu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3966 { 323 /* blu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3967 { 323 /* blu */, SP::BPICCNT, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3968 { 323 /* blu */, SP::BPICC, Convert__Imm1_2__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3969 { 323 /* blu */, SP::BPXCC, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3970 { 323 /* blu */, SP::BPXCC, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3971 { 323 /* blu */, SP::BPICC, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3972 { 323 /* blu */, SP::BPICCANT, Convert__Imm1_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3973 { 323 /* blu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3974 { 323 /* blu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3975 { 323 /* blu */, SP::BPICCANT, Convert__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3976 { 323 /* blu */, SP::BPICCA, Convert__Imm1_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3977 { 323 /* blu */, SP::BPXCCA, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3978 { 323 /* blu */, SP::BPXCCA, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3979 { 323 /* blu */, SP::BPICCA, Convert__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3980 { 327 /* bmask */, SP::BMASK, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3981 { 333 /* bn */, SP::BCOND, Convert__Imm1_0__imm_95_0, AMFBS_None, { MCK_Imm }, },
3982 { 333 /* bn */, SP::BPICC, Convert__Imm1_1__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
3983 { 333 /* bn */, SP::BPXCC, Convert__Imm1_1__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
3984 { 333 /* bn */, SP::BPXCC, Convert__Imm1_1__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3985 { 333 /* bn */, SP::BCONDA, Convert__Imm1_1__imm_95_0, AMFBS_None, { MCK_a, MCK_Imm }, },
3986 { 333 /* bn */, SP::BPICC, Convert__Imm1_1__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3987 { 333 /* bn */, SP::BPICCA, Convert__Imm1_2__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3988 { 333 /* bn */, SP::BPXCCA, Convert__Imm1_2__imm_95_0, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
3989 { 333 /* bn */, SP::BPXCCA, Convert__Imm1_2__imm_95_0, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3990 { 333 /* bn */, SP::BPICCA, Convert__Imm1_2__imm_95_0, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3991 { 333 /* bn */, SP::BPICCNT, Convert__Imm1_2__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3992 { 333 /* bn */, SP::BPXCCNT, Convert__Imm1_2__imm_95_0, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
3993 { 333 /* bn */, SP::BPXCCNT, Convert__Imm1_2__imm_95_0, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3994 { 333 /* bn */, SP::BPICCNT, Convert__Imm1_2__imm_95_0, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3995 { 333 /* bn */, SP::BPICC, Convert__Imm1_2__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3996 { 333 /* bn */, SP::BPXCC, Convert__Imm1_2__imm_95_0, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
3997 { 333 /* bn */, SP::BPXCC, Convert__Imm1_2__imm_95_0, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3998 { 333 /* bn */, SP::BPICC, Convert__Imm1_2__imm_95_0, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3999 { 333 /* bn */, SP::BPICCANT, Convert__Imm1_3__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4000 { 333 /* bn */, SP::BPXCCANT, Convert__Imm1_3__imm_95_0, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4001 { 333 /* bn */, SP::BPXCCANT, Convert__Imm1_3__imm_95_0, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4002 { 333 /* bn */, SP::BPICCANT, Convert__Imm1_3__imm_95_0, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
4003 { 333 /* bn */, SP::BPICCA, Convert__Imm1_3__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4004 { 333 /* bn */, SP::BPXCCA, Convert__Imm1_3__imm_95_0, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4005 { 333 /* bn */, SP::BPXCCA, Convert__Imm1_3__imm_95_0, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4006 { 333 /* bn */, SP::BPICCA, Convert__Imm1_3__imm_95_0, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
4007 { 336 /* bne */, SP::BCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
4008 { 336 /* bne */, SP::BPICC, Convert__Imm1_1__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
4009 { 336 /* bne */, SP::BPXCC, Convert__Imm1_1__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
4010 { 336 /* bne */, SP::BPXCC, Convert__Imm1_1__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
4011 { 336 /* bne */, SP::BCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
4012 { 336 /* bne */, SP::BPICC, Convert__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4013 { 336 /* bne */, SP::BPICCA, Convert__Imm1_2__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4014 { 336 /* bne */, SP::BPXCCA, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4015 { 336 /* bne */, SP::BPXCCA, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
4016 { 336 /* bne */, SP::BPICCA, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
4017 { 336 /* bne */, SP::BPICCNT, Convert__Imm1_2__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4018 { 336 /* bne */, SP::BPXCCNT, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4019 { 336 /* bne */, SP::BPXCCNT, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4020 { 336 /* bne */, SP::BPICCNT, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
4021 { 336 /* bne */, SP::BPICC, Convert__Imm1_2__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4022 { 336 /* bne */, SP::BPXCC, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4023 { 336 /* bne */, SP::BPXCC, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4024 { 336 /* bne */, SP::BPICC, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
4025 { 336 /* bne */, SP::BPICCANT, Convert__Imm1_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4026 { 336 /* bne */, SP::BPXCCANT, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4027 { 336 /* bne */, SP::BPXCCANT, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4028 { 336 /* bne */, SP::BPICCANT, Convert__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
4029 { 336 /* bne */, SP::BPICCA, Convert__Imm1_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4030 { 336 /* bne */, SP::BPXCCA, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4031 { 336 /* bne */, SP::BPXCCA, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4032 { 336 /* bne */, SP::BPICCA, Convert__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
4033 { 340 /* bneg */, SP::BCOND, Convert__Imm1_0__imm_95_6, AMFBS_None, { MCK_Imm }, },
4034 { 340 /* bneg */, SP::BPICC, Convert__Imm1_1__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
4035 { 340 /* bneg */, SP::BPXCC, Convert__Imm1_1__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
4036 { 340 /* bneg */, SP::BPXCC, Convert__Imm1_1__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
4037 { 340 /* bneg */, SP::BCONDA, Convert__Imm1_1__imm_95_6, AMFBS_None, { MCK_a, MCK_Imm }, },
4038 { 340 /* bneg */, SP::BPICC, Convert__Imm1_1__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4039 { 340 /* bneg */, SP::BPICCA, Convert__Imm1_2__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4040 { 340 /* bneg */, SP::BPXCCA, Convert__Imm1_2__imm_95_6, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4041 { 340 /* bneg */, SP::BPXCCA, Convert__Imm1_2__imm_95_6, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
4042 { 340 /* bneg */, SP::BPICCA, Convert__Imm1_2__imm_95_6, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
4043 { 340 /* bneg */, SP::BPICCNT, Convert__Imm1_2__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4044 { 340 /* bneg */, SP::BPXCCNT, Convert__Imm1_2__imm_95_6, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4045 { 340 /* bneg */, SP::BPXCCNT, Convert__Imm1_2__imm_95_6, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4046 { 340 /* bneg */, SP::BPICCNT, Convert__Imm1_2__imm_95_6, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
4047 { 340 /* bneg */, SP::BPICC, Convert__Imm1_2__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4048 { 340 /* bneg */, SP::BPXCC, Convert__Imm1_2__imm_95_6, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4049 { 340 /* bneg */, SP::BPXCC, Convert__Imm1_2__imm_95_6, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4050 { 340 /* bneg */, SP::BPICC, Convert__Imm1_2__imm_95_6, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
4051 { 340 /* bneg */, SP::BPICCANT, Convert__Imm1_3__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4052 { 340 /* bneg */, SP::BPXCCANT, Convert__Imm1_3__imm_95_6, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4053 { 340 /* bneg */, SP::BPXCCANT, Convert__Imm1_3__imm_95_6, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4054 { 340 /* bneg */, SP::BPICCANT, Convert__Imm1_3__imm_95_6, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
4055 { 340 /* bneg */, SP::BPICCA, Convert__Imm1_3__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4056 { 340 /* bneg */, SP::BPXCCA, Convert__Imm1_3__imm_95_6, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4057 { 340 /* bneg */, SP::BPXCCA, Convert__Imm1_3__imm_95_6, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4058 { 340 /* bneg */, SP::BPICCA, Convert__Imm1_3__imm_95_6, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
4059 { 345 /* bnz */, SP::BCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
4060 { 345 /* bnz */, SP::BPICC, Convert__Imm1_1__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
4061 { 345 /* bnz */, SP::BPXCC, Convert__Imm1_1__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
4062 { 345 /* bnz */, SP::BPXCC, Convert__Imm1_1__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
4063 { 345 /* bnz */, SP::BCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
4064 { 345 /* bnz */, SP::BPICC, Convert__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4065 { 345 /* bnz */, SP::BPICCA, Convert__Imm1_2__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4066 { 345 /* bnz */, SP::BPXCCA, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4067 { 345 /* bnz */, SP::BPXCCA, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
4068 { 345 /* bnz */, SP::BPICCA, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
4069 { 345 /* bnz */, SP::BPICCNT, Convert__Imm1_2__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4070 { 345 /* bnz */, SP::BPXCCNT, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4071 { 345 /* bnz */, SP::BPXCCNT, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4072 { 345 /* bnz */, SP::BPICCNT, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
4073 { 345 /* bnz */, SP::BPICC, Convert__Imm1_2__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4074 { 345 /* bnz */, SP::BPXCC, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4075 { 345 /* bnz */, SP::BPXCC, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4076 { 345 /* bnz */, SP::BPICC, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
4077 { 345 /* bnz */, SP::BPICCANT, Convert__Imm1_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4078 { 345 /* bnz */, SP::BPXCCANT, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4079 { 345 /* bnz */, SP::BPXCCANT, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4080 { 345 /* bnz */, SP::BPICCANT, Convert__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
4081 { 345 /* bnz */, SP::BPICCA, Convert__Imm1_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4082 { 345 /* bnz */, SP::BPXCCA, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4083 { 345 /* bnz */, SP::BPXCCA, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4084 { 345 /* bnz */, SP::BPICCA, Convert__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
4085 { 349 /* bpos */, SP::BCOND, Convert__Imm1_0__imm_95_14, AMFBS_None, { MCK_Imm }, },
4086 { 349 /* bpos */, SP::BPICC, Convert__Imm1_1__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
4087 { 349 /* bpos */, SP::BPXCC, Convert__Imm1_1__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
4088 { 349 /* bpos */, SP::BPXCC, Convert__Imm1_1__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
4089 { 349 /* bpos */, SP::BCONDA, Convert__Imm1_1__imm_95_14, AMFBS_None, { MCK_a, MCK_Imm }, },
4090 { 349 /* bpos */, SP::BPICC, Convert__Imm1_1__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4091 { 349 /* bpos */, SP::BPICCA, Convert__Imm1_2__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4092 { 349 /* bpos */, SP::BPXCCA, Convert__Imm1_2__imm_95_14, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4093 { 349 /* bpos */, SP::BPXCCA, Convert__Imm1_2__imm_95_14, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
4094 { 349 /* bpos */, SP::BPICCA, Convert__Imm1_2__imm_95_14, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
4095 { 349 /* bpos */, SP::BPICCNT, Convert__Imm1_2__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4096 { 349 /* bpos */, SP::BPXCCNT, Convert__Imm1_2__imm_95_14, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4097 { 349 /* bpos */, SP::BPXCCNT, Convert__Imm1_2__imm_95_14, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4098 { 349 /* bpos */, SP::BPICCNT, Convert__Imm1_2__imm_95_14, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
4099 { 349 /* bpos */, SP::BPICC, Convert__Imm1_2__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4100 { 349 /* bpos */, SP::BPXCC, Convert__Imm1_2__imm_95_14, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4101 { 349 /* bpos */, SP::BPXCC, Convert__Imm1_2__imm_95_14, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4102 { 349 /* bpos */, SP::BPICC, Convert__Imm1_2__imm_95_14, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
4103 { 349 /* bpos */, SP::BPICCANT, Convert__Imm1_3__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4104 { 349 /* bpos */, SP::BPXCCANT, Convert__Imm1_3__imm_95_14, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4105 { 349 /* bpos */, SP::BPXCCANT, Convert__Imm1_3__imm_95_14, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4106 { 349 /* bpos */, SP::BPICCANT, Convert__Imm1_3__imm_95_14, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
4107 { 349 /* bpos */, SP::BPICCA, Convert__Imm1_3__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4108 { 349 /* bpos */, SP::BPXCCA, Convert__Imm1_3__imm_95_14, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4109 { 349 /* bpos */, SP::BPXCCA, Convert__Imm1_3__imm_95_14, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4110 { 349 /* bpos */, SP::BPICCA, Convert__Imm1_3__imm_95_14, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
4111 { 354 /* br */, SP::BPR, Convert__Imm1_2__Imm1_0__Reg1_1, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_Imm }, },
4112 { 354 /* br */, SP::BPRA, Convert__Imm1_3__Imm1_0__Reg1_2, AMFBS_Is64Bit, { MCK_Imm, MCK_a, MCK_IntRegs, MCK_Imm }, },
4113 { 354 /* br */, SP::BPRNT, Convert__Imm1_3__Imm1_0__Reg1_2, AMFBS_Is64Bit, { MCK_Imm, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4114 { 354 /* br */, SP::BPRANT, Convert__Imm1_4__Imm1_0__Reg1_3, AMFBS_Is64Bit, { MCK_Imm, MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4115 { 357 /* bre */, SP::BPR, Convert__Imm1_1__imm_95_1__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
4116 { 357 /* bre */, SP::BPRA, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
4117 { 357 /* bre */, SP::BPRNT, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
4118 { 357 /* bre */, SP::BPR, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
4119 { 357 /* bre */, SP::BPRANT, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4120 { 357 /* bre */, SP::BPRA, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
4121 { 361 /* brgez */, SP::BPR, Convert__Imm1_1__imm_95_7__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
4122 { 361 /* brgez */, SP::BPRA, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
4123 { 361 /* brgez */, SP::BPRNT, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
4124 { 361 /* brgez */, SP::BPR, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
4125 { 361 /* brgez */, SP::BPRANT, Convert__Imm1_3__imm_95_7__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4126 { 361 /* brgez */, SP::BPRA, Convert__Imm1_3__imm_95_7__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
4127 { 367 /* brgz */, SP::BPR, Convert__Imm1_1__imm_95_6__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
4128 { 367 /* brgz */, SP::BPRA, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
4129 { 367 /* brgz */, SP::BPRNT, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
4130 { 367 /* brgz */, SP::BPR, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
4131 { 367 /* brgz */, SP::BPRANT, Convert__Imm1_3__imm_95_6__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4132 { 367 /* brgz */, SP::BPRA, Convert__Imm1_3__imm_95_6__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
4133 { 372 /* brlez */, SP::BPR, Convert__Imm1_1__imm_95_2__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
4134 { 372 /* brlez */, SP::BPRA, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
4135 { 372 /* brlez */, SP::BPRNT, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
4136 { 372 /* brlez */, SP::BPR, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
4137 { 372 /* brlez */, SP::BPRANT, Convert__Imm1_3__imm_95_2__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4138 { 372 /* brlez */, SP::BPRA, Convert__Imm1_3__imm_95_2__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
4139 { 378 /* brlz */, SP::BPR, Convert__Imm1_1__imm_95_3__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
4140 { 378 /* brlz */, SP::BPRA, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
4141 { 378 /* brlz */, SP::BPRNT, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
4142 { 378 /* brlz */, SP::BPR, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
4143 { 378 /* brlz */, SP::BPRANT, Convert__Imm1_3__imm_95_3__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4144 { 378 /* brlz */, SP::BPRA, Convert__Imm1_3__imm_95_3__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
4145 { 383 /* brne */, SP::BPR, Convert__Imm1_1__imm_95_5__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
4146 { 383 /* brne */, SP::BPRA, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
4147 { 383 /* brne */, SP::BPRNT, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
4148 { 383 /* brne */, SP::BPR, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
4149 { 383 /* brne */, SP::BPRANT, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4150 { 383 /* brne */, SP::BPRA, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
4151 { 388 /* brnz */, SP::BPR, Convert__Imm1_1__imm_95_5__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
4152 { 388 /* brnz */, SP::BPRA, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
4153 { 388 /* brnz */, SP::BPRNT, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
4154 { 388 /* brnz */, SP::BPR, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
4155 { 388 /* brnz */, SP::BPRANT, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4156 { 388 /* brnz */, SP::BPRA, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
4157 { 393 /* brz */, SP::BPR, Convert__Imm1_1__imm_95_1__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
4158 { 393 /* brz */, SP::BPRA, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
4159 { 393 /* brz */, SP::BPRNT, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
4160 { 393 /* brz */, SP::BPR, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
4161 { 393 /* brz */, SP::BPRANT, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
4162 { 393 /* brz */, SP::BPRA, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
4163 { 397 /* bset */, SP::ORrr, Convert__Reg1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
4164 { 397 /* bset */, SP::ORri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4165 { 402 /* bshuffle */, SP::BSHUFFLE, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4166 { 411 /* btog */, SP::XORrr, Convert__Reg1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
4167 { 411 /* btog */, SP::XORri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4168 { 416 /* btst */, SP::ANDCCrr, Convert__regG0__Reg1_1__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
4169 { 416 /* btst */, SP::ANDCCri, Convert__regG0__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4170 { 421 /* bvc */, SP::BCOND, Convert__Imm1_0__imm_95_15, AMFBS_None, { MCK_Imm }, },
4171 { 421 /* bvc */, SP::BPICC, Convert__Imm1_1__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
4172 { 421 /* bvc */, SP::BPXCC, Convert__Imm1_1__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
4173 { 421 /* bvc */, SP::BPXCC, Convert__Imm1_1__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
4174 { 421 /* bvc */, SP::BCONDA, Convert__Imm1_1__imm_95_15, AMFBS_None, { MCK_a, MCK_Imm }, },
4175 { 421 /* bvc */, SP::BPICC, Convert__Imm1_1__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4176 { 421 /* bvc */, SP::BPICCA, Convert__Imm1_2__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4177 { 421 /* bvc */, SP::BPXCCA, Convert__Imm1_2__imm_95_15, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4178 { 421 /* bvc */, SP::BPXCCA, Convert__Imm1_2__imm_95_15, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
4179 { 421 /* bvc */, SP::BPICCA, Convert__Imm1_2__imm_95_15, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
4180 { 421 /* bvc */, SP::BPICCNT, Convert__Imm1_2__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4181 { 421 /* bvc */, SP::BPXCCNT, Convert__Imm1_2__imm_95_15, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4182 { 421 /* bvc */, SP::BPXCCNT, Convert__Imm1_2__imm_95_15, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4183 { 421 /* bvc */, SP::BPICCNT, Convert__Imm1_2__imm_95_15, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
4184 { 421 /* bvc */, SP::BPICC, Convert__Imm1_2__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4185 { 421 /* bvc */, SP::BPXCC, Convert__Imm1_2__imm_95_15, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4186 { 421 /* bvc */, SP::BPXCC, Convert__Imm1_2__imm_95_15, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4187 { 421 /* bvc */, SP::BPICC, Convert__Imm1_2__imm_95_15, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
4188 { 421 /* bvc */, SP::BPICCANT, Convert__Imm1_3__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4189 { 421 /* bvc */, SP::BPXCCANT, Convert__Imm1_3__imm_95_15, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4190 { 421 /* bvc */, SP::BPXCCANT, Convert__Imm1_3__imm_95_15, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4191 { 421 /* bvc */, SP::BPICCANT, Convert__Imm1_3__imm_95_15, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
4192 { 421 /* bvc */, SP::BPICCA, Convert__Imm1_3__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4193 { 421 /* bvc */, SP::BPXCCA, Convert__Imm1_3__imm_95_15, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4194 { 421 /* bvc */, SP::BPXCCA, Convert__Imm1_3__imm_95_15, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4195 { 421 /* bvc */, SP::BPICCA, Convert__Imm1_3__imm_95_15, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
4196 { 425 /* bvs */, SP::BCOND, Convert__Imm1_0__imm_95_7, AMFBS_None, { MCK_Imm }, },
4197 { 425 /* bvs */, SP::BPICC, Convert__Imm1_1__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
4198 { 425 /* bvs */, SP::BPXCC, Convert__Imm1_1__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
4199 { 425 /* bvs */, SP::BPXCC, Convert__Imm1_1__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
4200 { 425 /* bvs */, SP::BCONDA, Convert__Imm1_1__imm_95_7, AMFBS_None, { MCK_a, MCK_Imm }, },
4201 { 425 /* bvs */, SP::BPICC, Convert__Imm1_1__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4202 { 425 /* bvs */, SP::BPICCA, Convert__Imm1_2__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4203 { 425 /* bvs */, SP::BPXCCA, Convert__Imm1_2__imm_95_7, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4204 { 425 /* bvs */, SP::BPXCCA, Convert__Imm1_2__imm_95_7, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
4205 { 425 /* bvs */, SP::BPICCA, Convert__Imm1_2__imm_95_7, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
4206 { 425 /* bvs */, SP::BPICCNT, Convert__Imm1_2__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4207 { 425 /* bvs */, SP::BPXCCNT, Convert__Imm1_2__imm_95_7, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4208 { 425 /* bvs */, SP::BPXCCNT, Convert__Imm1_2__imm_95_7, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4209 { 425 /* bvs */, SP::BPICCNT, Convert__Imm1_2__imm_95_7, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
4210 { 425 /* bvs */, SP::BPICC, Convert__Imm1_2__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4211 { 425 /* bvs */, SP::BPXCC, Convert__Imm1_2__imm_95_7, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4212 { 425 /* bvs */, SP::BPXCC, Convert__Imm1_2__imm_95_7, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4213 { 425 /* bvs */, SP::BPICC, Convert__Imm1_2__imm_95_7, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
4214 { 425 /* bvs */, SP::BPICCANT, Convert__Imm1_3__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4215 { 425 /* bvs */, SP::BPXCCANT, Convert__Imm1_3__imm_95_7, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4216 { 425 /* bvs */, SP::BPXCCANT, Convert__Imm1_3__imm_95_7, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4217 { 425 /* bvs */, SP::BPICCANT, Convert__Imm1_3__imm_95_7, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
4218 { 425 /* bvs */, SP::BPICCA, Convert__Imm1_3__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4219 { 425 /* bvs */, SP::BPXCCA, Convert__Imm1_3__imm_95_7, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4220 { 425 /* bvs */, SP::BPXCCA, Convert__Imm1_3__imm_95_7, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4221 { 425 /* bvs */, SP::BPICCA, Convert__Imm1_3__imm_95_7, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
4222 { 429 /* bz */, SP::BCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
4223 { 429 /* bz */, SP::BPICC, Convert__Imm1_1__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
4224 { 429 /* bz */, SP::BPXCC, Convert__Imm1_1__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
4225 { 429 /* bz */, SP::BPXCC, Convert__Imm1_1__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
4226 { 429 /* bz */, SP::BCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
4227 { 429 /* bz */, SP::BPICC, Convert__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4228 { 429 /* bz */, SP::BPICCA, Convert__Imm1_2__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4229 { 429 /* bz */, SP::BPXCCA, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK__PCT_ncc, MCK_Imm }, },
4230 { 429 /* bz */, SP::BPXCCA, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
4231 { 429 /* bz */, SP::BPICCA, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
4232 { 429 /* bz */, SP::BPICCNT, Convert__Imm1_2__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4233 { 429 /* bz */, SP::BPXCCNT, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4234 { 429 /* bz */, SP::BPXCCNT, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4235 { 429 /* bz */, SP::BPICCNT, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
4236 { 429 /* bz */, SP::BPICC, Convert__Imm1_2__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4237 { 429 /* bz */, SP::BPXCC, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4238 { 429 /* bz */, SP::BPXCC, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4239 { 429 /* bz */, SP::BPICC, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
4240 { 429 /* bz */, SP::BPICCANT, Convert__Imm1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4241 { 429 /* bz */, SP::BPXCCANT, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_ncc, MCK_Imm }, },
4242 { 429 /* bz */, SP::BPXCCANT, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
4243 { 429 /* bz */, SP::BPICCANT, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
4244 { 429 /* bz */, SP::BPICCA, Convert__Imm1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4245 { 429 /* bz */, SP::BPXCCA, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_ncc, MCK_Imm }, },
4246 { 429 /* bz */, SP::BPXCCA, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
4247 { 429 /* bz */, SP::BPICCA, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
4248 { 432 /* call */, SP::CALL, Convert__CallTarget1_0, AMFBS_None, { MCK_CallTarget }, },
4249 { 432 /* call */, SP::JMPLri, Convert__regO7__MEMri2_0, AMFBS_None, { MCK_MEMri }, },
4250 { 432 /* call */, SP::JMPLrr, Convert__regO7__MEMrr2_0, AMFBS_None, { MCK_MEMrr }, },
4251 { 432 /* call */, SP::CALLi, Convert__CallTarget1_0__Imm1_1, AMFBS_None, { MCK_CallTarget, MCK_Imm }, },
4252 { 432 /* call */, SP::TLS_CALL, Convert__CallTarget1_0__TailRelocSymCall_TLS1_1, AMFBS_None, { MCK_CallTarget, MCK_TailRelocSymCall_TLS }, },
4253 { 432 /* call */, SP::CALLrii, Convert__MEMri2_0__Imm1_1, AMFBS_None, { MCK_MEMri, MCK_Imm }, },
4254 { 432 /* call */, SP::CALLrri, Convert__MEMrr2_0__Imm1_1, AMFBS_None, { MCK_MEMrr, MCK_Imm }, },
4255 { 437 /* camellia_f */, SP::CAMELLIA_F, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4256 { 448 /* camellia_fl */, SP::CAMELLIA_FL, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4257 { 460 /* camellia_fli */, SP::CAMELLIA_FLI, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4258 { 473 /* cas */, SP::CASArr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_128, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
4259 { 477 /* casa */, SP::CASAri, Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK__PCT_asi, MCK_IntRegs, MCK_IntRegs }, },
4260 { 477 /* casa */, SP::CASArr, Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1__ASITag1_3, AMFBS_HasCASA, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_ASITag, MCK_IntRegs, MCK_IntRegs }, },
4261 { 482 /* casl */, SP::CASArr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_136, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
4262 { 487 /* casx */, SP::CASXArr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_128, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
4263 { 492 /* casxa */, SP::CASXAri, Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1, AMFBS_Is64Bit_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK__PCT_asi, MCK_IntRegs, MCK_IntRegs }, },
4264 { 492 /* casxa */, SP::CASXArr, Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1__ASITag1_3, AMFBS_Is64Bit_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_ASITag, MCK_IntRegs, MCK_IntRegs }, },
4265 { 498 /* casxl */, SP::CASXArr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_136, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
4266 { 504 /* cb */, SP::CPBCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
4267 { 504 /* cb */, SP::CPBCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
4268 { 504 /* cb */, SP::CPBCOND, Convert__Imm1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Imm }, },
4269 { 504 /* cb */, SP::CPBCONDA, Convert__Imm1_2__Imm1_0, AMFBS_None, { MCK_Imm, MCK_a, MCK_Imm }, },
4270 { 507 /* cb0 */, SP::CPBCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
4271 { 507 /* cb0 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
4272 { 511 /* cb01 */, SP::CPBCOND, Convert__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
4273 { 511 /* cb01 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_13, AMFBS_None, { MCK_a, MCK_Imm }, },
4274 { 516 /* cb012 */, SP::CPBCOND, Convert__Imm1_0__imm_95_15, AMFBS_None, { MCK_Imm }, },
4275 { 516 /* cb012 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_15, AMFBS_None, { MCK_a, MCK_Imm }, },
4276 { 522 /* cb013 */, SP::CPBCOND, Convert__Imm1_0__imm_95_14, AMFBS_None, { MCK_Imm }, },
4277 { 522 /* cb013 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_14, AMFBS_None, { MCK_a, MCK_Imm }, },
4278 { 528 /* cb02 */, SP::CPBCOND, Convert__Imm1_0__imm_95_11, AMFBS_None, { MCK_Imm }, },
4279 { 528 /* cb02 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_11, AMFBS_None, { MCK_a, MCK_Imm }, },
4280 { 533 /* cb023 */, SP::CPBCOND, Convert__Imm1_0__imm_95_12, AMFBS_None, { MCK_Imm }, },
4281 { 533 /* cb023 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_12, AMFBS_None, { MCK_a, MCK_Imm }, },
4282 { 539 /* cb03 */, SP::CPBCOND, Convert__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
4283 { 539 /* cb03 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_10, AMFBS_None, { MCK_a, MCK_Imm }, },
4284 { 544 /* cb1 */, SP::CPBCOND, Convert__Imm1_0__imm_95_4, AMFBS_None, { MCK_Imm }, },
4285 { 544 /* cb1 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_4, AMFBS_None, { MCK_a, MCK_Imm }, },
4286 { 548 /* cb12 */, SP::CPBCOND, Convert__Imm1_0__imm_95_2, AMFBS_None, { MCK_Imm }, },
4287 { 548 /* cb12 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_2, AMFBS_None, { MCK_a, MCK_Imm }, },
4288 { 553 /* cb123 */, SP::CPBCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
4289 { 553 /* cb123 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
4290 { 559 /* cb13 */, SP::CPBCOND, Convert__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
4291 { 559 /* cb13 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_3, AMFBS_None, { MCK_a, MCK_Imm }, },
4292 { 564 /* cb2 */, SP::CPBCOND, Convert__Imm1_0__imm_95_6, AMFBS_None, { MCK_Imm }, },
4293 { 564 /* cb2 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_6, AMFBS_None, { MCK_a, MCK_Imm }, },
4294 { 568 /* cb23 */, SP::CPBCOND, Convert__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
4295 { 568 /* cb23 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_5, AMFBS_None, { MCK_a, MCK_Imm }, },
4296 { 573 /* cb3 */, SP::CPBCOND, Convert__Imm1_0__imm_95_7, AMFBS_None, { MCK_Imm }, },
4297 { 573 /* cb3 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_7, AMFBS_None, { MCK_a, MCK_Imm }, },
4298 { 577 /* cba */, SP::CPBCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
4299 { 577 /* cba */, SP::CPBCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
4300 { 581 /* cbn */, SP::CPBCOND, Convert__Imm1_0__imm_95_0, AMFBS_None, { MCK_Imm }, },
4301 { 581 /* cbn */, SP::CPBCONDA, Convert__Imm1_1__imm_95_0, AMFBS_None, { MCK_a, MCK_Imm }, },
4302 { 585 /* clr */, SP::ORrr, Convert__Reg1_0__regG0__regG0, AMFBS_None, { MCK_IntRegs }, },
4303 { 585 /* clr */, SP::STri, Convert__MEMri2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_ }, },
4304 { 585 /* clr */, SP::STrr, Convert__MEMrr2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
4305 { 589 /* clrb */, SP::STBri, Convert__MEMri2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_ }, },
4306 { 589 /* clrb */, SP::STBrr, Convert__MEMrr2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
4307 { 594 /* clrh */, SP::STHri, Convert__MEMri2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_ }, },
4308 { 594 /* clrh */, SP::STHrr, Convert__MEMrr2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
4309 { 599 /* clrx */, SP::STXri, Convert__MEMri2_1__regG0, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_ }, },
4310 { 599 /* clrx */, SP::STXrr, Convert__MEMrr2_1__regG0, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
4311 { 604 /* cmask16 */, SP::CMASK16, Convert__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs }, },
4312 { 612 /* cmask32 */, SP::CMASK32, Convert__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs }, },
4313 { 620 /* cmask8 */, SP::CMASK8, Convert__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs }, },
4314 { 627 /* cmp */, SP::SUBCCrr, Convert__regG0__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
4315 { 627 /* cmp */, SP::SUBCCri, Convert__regG0__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm }, },
4316 { 631 /* crc32c */, SP::CRC32C, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4317 { 638 /* cwb */, SP::CWBCONDrr, Convert__Imm1_3__Imm1_0__Reg1_1__Reg1_2, AMFBS_HasOSA2011, { MCK_Imm, MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4318 { 638 /* cwb */, SP::CWBCONDri, Convert__Imm1_3__Imm1_0__Reg1_1__Imm1_2, AMFBS_HasOSA2011, { MCK_Imm, MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4319 { 642 /* cwbcc */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4320 { 642 /* cwbcc */, SP::CWBCONDri, Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4321 { 648 /* cwbcs */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4322 { 648 /* cwbcs */, SP::CWBCONDri, Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4323 { 654 /* cwbe */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_1__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4324 { 654 /* cwbe */, SP::CWBCONDri, Convert__Imm1_2__imm_95_1__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4325 { 659 /* cwbg */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_10__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4326 { 659 /* cwbg */, SP::CWBCONDri, Convert__Imm1_2__imm_95_10__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4327 { 664 /* cwbge */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_11__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4328 { 664 /* cwbge */, SP::CWBCONDri, Convert__Imm1_2__imm_95_11__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4329 { 670 /* cwbgeu */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4330 { 670 /* cwbgeu */, SP::CWBCONDri, Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4331 { 677 /* cwbgu */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_12__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4332 { 677 /* cwbgu */, SP::CWBCONDri, Convert__Imm1_2__imm_95_12__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4333 { 683 /* cwbl */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_3__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4334 { 683 /* cwbl */, SP::CWBCONDri, Convert__Imm1_2__imm_95_3__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4335 { 688 /* cwble */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_2__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4336 { 688 /* cwble */, SP::CWBCONDri, Convert__Imm1_2__imm_95_2__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4337 { 694 /* cwbleu */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_4__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4338 { 694 /* cwbleu */, SP::CWBCONDri, Convert__Imm1_2__imm_95_4__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4339 { 701 /* cwblu */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4340 { 701 /* cwblu */, SP::CWBCONDri, Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4341 { 707 /* cwbne */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_9__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4342 { 707 /* cwbne */, SP::CWBCONDri, Convert__Imm1_2__imm_95_9__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4343 { 713 /* cwbneg */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_6__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4344 { 713 /* cwbneg */, SP::CWBCONDri, Convert__Imm1_2__imm_95_6__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4345 { 720 /* cwbpos */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_14__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4346 { 720 /* cwbpos */, SP::CWBCONDri, Convert__Imm1_2__imm_95_14__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4347 { 727 /* cwbvc */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_15__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4348 { 727 /* cwbvc */, SP::CWBCONDri, Convert__Imm1_2__imm_95_15__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4349 { 733 /* cwbvs */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_7__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4350 { 733 /* cwbvs */, SP::CWBCONDri, Convert__Imm1_2__imm_95_7__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4351 { 739 /* cxb */, SP::CXBCONDrr, Convert__Imm1_3__Imm1_0__Reg1_1__Reg1_2, AMFBS_HasOSA2011, { MCK_Imm, MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4352 { 739 /* cxb */, SP::CXBCONDri, Convert__Imm1_3__Imm1_0__Reg1_1__Imm1_2, AMFBS_HasOSA2011, { MCK_Imm, MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4353 { 743 /* cxbcc */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4354 { 743 /* cxbcc */, SP::CXBCONDri, Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4355 { 749 /* cxbcs */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4356 { 749 /* cxbcs */, SP::CXBCONDri, Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4357 { 755 /* cxbe */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_1__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4358 { 755 /* cxbe */, SP::CXBCONDri, Convert__Imm1_2__imm_95_1__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4359 { 760 /* cxbg */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_10__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4360 { 760 /* cxbg */, SP::CXBCONDri, Convert__Imm1_2__imm_95_10__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4361 { 765 /* cxbge */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_11__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4362 { 765 /* cxbge */, SP::CXBCONDri, Convert__Imm1_2__imm_95_11__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4363 { 771 /* cxbgeu */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4364 { 771 /* cxbgeu */, SP::CXBCONDri, Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4365 { 778 /* cxbgu */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_12__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4366 { 778 /* cxbgu */, SP::CXBCONDri, Convert__Imm1_2__imm_95_12__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4367 { 784 /* cxbl */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_3__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4368 { 784 /* cxbl */, SP::CXBCONDri, Convert__Imm1_2__imm_95_3__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4369 { 789 /* cxble */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_2__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4370 { 789 /* cxble */, SP::CXBCONDri, Convert__Imm1_2__imm_95_2__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4371 { 795 /* cxbleu */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_4__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4372 { 795 /* cxbleu */, SP::CXBCONDri, Convert__Imm1_2__imm_95_4__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4373 { 802 /* cxblu */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4374 { 802 /* cxblu */, SP::CXBCONDri, Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4375 { 808 /* cxbne */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_9__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4376 { 808 /* cxbne */, SP::CXBCONDri, Convert__Imm1_2__imm_95_9__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4377 { 814 /* cxbneg */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_6__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4378 { 814 /* cxbneg */, SP::CXBCONDri, Convert__Imm1_2__imm_95_6__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4379 { 821 /* cxbpos */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_14__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4380 { 821 /* cxbpos */, SP::CXBCONDri, Convert__Imm1_2__imm_95_14__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4381 { 828 /* cxbvc */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_15__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4382 { 828 /* cxbvc */, SP::CXBCONDri, Convert__Imm1_2__imm_95_15__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4383 { 834 /* cxbvs */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_7__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
4384 { 834 /* cxbvs */, SP::CXBCONDri, Convert__Imm1_2__imm_95_7__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
4385 { 840 /* dec */, SP::SUBri, Convert__Reg1_0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
4386 { 840 /* dec */, SP::SUBri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4387 { 844 /* deccc */, SP::SUBCCri, Convert__Reg1_0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
4388 { 844 /* deccc */, SP::SUBCCri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4389 { 850 /* des_iip */, SP::DES_IIP, Convert__Reg1_1__Reg1_0, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs }, },
4390 { 858 /* des_ip */, SP::DES_IP, Convert__Reg1_1__Reg1_0, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs }, },
4391 { 865 /* des_kexpand */, SP::DES_KEXPAND, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_Imm, MCK_DFPRegs }, },
4392 { 877 /* des_round */, SP::DES_ROUND, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasCrypto, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4393 { 887 /* done */, SP::DONE, Convert_NoOperands, AMFBS_HasV9, { }, },
4394 { 892 /* edge16 */, SP::EDGE16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4395 { 899 /* edge16l */, SP::EDGE16L, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4396 { 907 /* edge16ln */, SP::EDGE16LN, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4397 { 916 /* edge16n */, SP::EDGE16N, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4398 { 924 /* edge32 */, SP::EDGE32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4399 { 931 /* edge32l */, SP::EDGE32L, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4400 { 939 /* edge32ln */, SP::EDGE32LN, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4401 { 948 /* edge32n */, SP::EDGE32N, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4402 { 956 /* edge8 */, SP::EDGE8, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4403 { 962 /* edge8l */, SP::EDGE8L, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4404 { 969 /* edge8ln */, SP::EDGE8LN, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4405 { 977 /* edge8n */, SP::EDGE8N, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4406 { 984 /* fabsd */, SP::FABSD, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_DFPRegs, MCK_DFPRegs }, },
4407 { 990 /* fabsq */, SP::FABSQ, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK_QFPRegs }, },
4408 { 996 /* fabss */, SP::FABSS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4409 { 1002 /* faddd */, SP::FADDD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4410 { 1008 /* faddq */, SP::FADDQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4411 { 1014 /* fadds */, SP::FADDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4412 { 1020 /* faligndata */, SP::FALIGNADATA, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4413 { 1031 /* fand */, SP::FAND, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4414 { 1036 /* fandnot1 */, SP::FANDNOT1, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4415 { 1045 /* fandnot1s */, SP::FANDNOT1S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4416 { 1055 /* fandnot2 */, SP::FANDNOT2, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4417 { 1064 /* fandnot2s */, SP::FANDNOT2S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4418 { 1074 /* fands */, SP::FANDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4419 { 1080 /* fb */, SP::FBCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
4420 { 1080 /* fb */, SP::FBCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
4421 { 1080 /* fb */, SP::BPFCC, Convert__Imm1_1__imm_95_8__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4422 { 1080 /* fb */, SP::FBCOND, Convert__Imm1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Imm }, },
4423 { 1080 /* fb */, SP::BPFCCA, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4424 { 1080 /* fb */, SP::BPFCCNT, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4425 { 1080 /* fb */, SP::BPFCC, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4426 { 1080 /* fb */, SP::FBCONDA, Convert__Imm1_2__Imm1_0, AMFBS_None, { MCK_Imm, MCK_a, MCK_Imm }, },
4427 { 1080 /* fb */, SP::FBCOND_V9, Convert__Imm1_2__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_Imm }, },
4428 { 1080 /* fb */, SP::BPFCC, Convert__Imm1_2__Imm1_0__Reg1_1, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_Imm }, },
4429 { 1080 /* fb */, SP::BPFCCANT, Convert__Imm1_3__imm_95_8__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4430 { 1080 /* fb */, SP::BPFCCA, Convert__Imm1_3__imm_95_8__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4431 { 1080 /* fb */, SP::FBCONDA_V9, Convert__Imm1_3__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_FCC0, MCK_Imm }, },
4432 { 1080 /* fb */, SP::BPFCCA, Convert__Imm1_3__Imm1_0__Reg1_2, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_FCCRegs, MCK_Imm }, },
4433 { 1080 /* fb */, SP::BPFCCNT, Convert__Imm1_3__Imm1_0__Reg1_2, AMFBS_HasV9, { MCK_Imm, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4434 { 1080 /* fb */, SP::BPFCCANT, Convert__Imm1_4__Imm1_0__Reg1_3, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4435 { 1083 /* fba */, SP::FBCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
4436 { 1083 /* fba */, SP::FBCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
4437 { 1083 /* fba */, SP::BPFCC, Convert__Imm1_1__imm_95_8__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4438 { 1083 /* fba */, SP::BPFCCA, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4439 { 1083 /* fba */, SP::BPFCCNT, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4440 { 1083 /* fba */, SP::BPFCC, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4441 { 1083 /* fba */, SP::BPFCCANT, Convert__Imm1_3__imm_95_8__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4442 { 1083 /* fba */, SP::BPFCCA, Convert__Imm1_3__imm_95_8__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4443 { 1087 /* fbe */, SP::FBCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
4444 { 1087 /* fbe */, SP::FBCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
4445 { 1087 /* fbe */, SP::BPFCC, Convert__Imm1_1__imm_95_9__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4446 { 1087 /* fbe */, SP::BPFCCA, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4447 { 1087 /* fbe */, SP::BPFCCNT, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4448 { 1087 /* fbe */, SP::BPFCC, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4449 { 1087 /* fbe */, SP::BPFCCANT, Convert__Imm1_3__imm_95_9__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4450 { 1087 /* fbe */, SP::BPFCCA, Convert__Imm1_3__imm_95_9__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4451 { 1091 /* fbg */, SP::FBCOND, Convert__Imm1_0__imm_95_6, AMFBS_None, { MCK_Imm }, },
4452 { 1091 /* fbg */, SP::FBCONDA, Convert__Imm1_1__imm_95_6, AMFBS_None, { MCK_a, MCK_Imm }, },
4453 { 1091 /* fbg */, SP::BPFCC, Convert__Imm1_1__imm_95_6__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4454 { 1091 /* fbg */, SP::BPFCCA, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4455 { 1091 /* fbg */, SP::BPFCCNT, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4456 { 1091 /* fbg */, SP::BPFCC, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4457 { 1091 /* fbg */, SP::BPFCCANT, Convert__Imm1_3__imm_95_6__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4458 { 1091 /* fbg */, SP::BPFCCA, Convert__Imm1_3__imm_95_6__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4459 { 1095 /* fbge */, SP::FBCOND, Convert__Imm1_0__imm_95_11, AMFBS_None, { MCK_Imm }, },
4460 { 1095 /* fbge */, SP::FBCONDA, Convert__Imm1_1__imm_95_11, AMFBS_None, { MCK_a, MCK_Imm }, },
4461 { 1095 /* fbge */, SP::BPFCC, Convert__Imm1_1__imm_95_11__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4462 { 1095 /* fbge */, SP::BPFCCA, Convert__Imm1_2__imm_95_11__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4463 { 1095 /* fbge */, SP::BPFCCNT, Convert__Imm1_2__imm_95_11__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4464 { 1095 /* fbge */, SP::BPFCC, Convert__Imm1_2__imm_95_11__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4465 { 1095 /* fbge */, SP::BPFCCANT, Convert__Imm1_3__imm_95_11__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4466 { 1095 /* fbge */, SP::BPFCCA, Convert__Imm1_3__imm_95_11__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4467 { 1100 /* fbl */, SP::FBCOND, Convert__Imm1_0__imm_95_4, AMFBS_None, { MCK_Imm }, },
4468 { 1100 /* fbl */, SP::FBCONDA, Convert__Imm1_1__imm_95_4, AMFBS_None, { MCK_a, MCK_Imm }, },
4469 { 1100 /* fbl */, SP::BPFCC, Convert__Imm1_1__imm_95_4__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4470 { 1100 /* fbl */, SP::BPFCCA, Convert__Imm1_2__imm_95_4__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4471 { 1100 /* fbl */, SP::BPFCCNT, Convert__Imm1_2__imm_95_4__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4472 { 1100 /* fbl */, SP::BPFCC, Convert__Imm1_2__imm_95_4__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4473 { 1100 /* fbl */, SP::BPFCCANT, Convert__Imm1_3__imm_95_4__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4474 { 1100 /* fbl */, SP::BPFCCA, Convert__Imm1_3__imm_95_4__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4475 { 1104 /* fble */, SP::FBCOND, Convert__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
4476 { 1104 /* fble */, SP::FBCONDA, Convert__Imm1_1__imm_95_13, AMFBS_None, { MCK_a, MCK_Imm }, },
4477 { 1104 /* fble */, SP::BPFCC, Convert__Imm1_1__imm_95_13__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4478 { 1104 /* fble */, SP::BPFCCA, Convert__Imm1_2__imm_95_13__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4479 { 1104 /* fble */, SP::BPFCCNT, Convert__Imm1_2__imm_95_13__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4480 { 1104 /* fble */, SP::BPFCC, Convert__Imm1_2__imm_95_13__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4481 { 1104 /* fble */, SP::BPFCCANT, Convert__Imm1_3__imm_95_13__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4482 { 1104 /* fble */, SP::BPFCCA, Convert__Imm1_3__imm_95_13__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4483 { 1109 /* fblg */, SP::FBCOND, Convert__Imm1_0__imm_95_2, AMFBS_None, { MCK_Imm }, },
4484 { 1109 /* fblg */, SP::FBCONDA, Convert__Imm1_1__imm_95_2, AMFBS_None, { MCK_a, MCK_Imm }, },
4485 { 1109 /* fblg */, SP::BPFCC, Convert__Imm1_1__imm_95_2__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4486 { 1109 /* fblg */, SP::BPFCCA, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4487 { 1109 /* fblg */, SP::BPFCCNT, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4488 { 1109 /* fblg */, SP::BPFCC, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4489 { 1109 /* fblg */, SP::BPFCCANT, Convert__Imm1_3__imm_95_2__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4490 { 1109 /* fblg */, SP::BPFCCA, Convert__Imm1_3__imm_95_2__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4491 { 1114 /* fbn */, SP::FBCOND, Convert__Imm1_0__imm_95_0, AMFBS_None, { MCK_Imm }, },
4492 { 1114 /* fbn */, SP::FBCONDA, Convert__Imm1_1__imm_95_0, AMFBS_None, { MCK_a, MCK_Imm }, },
4493 { 1114 /* fbn */, SP::BPFCC, Convert__Imm1_1__imm_95_0__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4494 { 1114 /* fbn */, SP::BPFCCA, Convert__Imm1_2__imm_95_0__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4495 { 1114 /* fbn */, SP::BPFCCNT, Convert__Imm1_2__imm_95_0__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4496 { 1114 /* fbn */, SP::BPFCC, Convert__Imm1_2__imm_95_0__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4497 { 1114 /* fbn */, SP::BPFCCANT, Convert__Imm1_3__imm_95_0__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4498 { 1114 /* fbn */, SP::BPFCCA, Convert__Imm1_3__imm_95_0__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4499 { 1118 /* fbne */, SP::FBCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
4500 { 1118 /* fbne */, SP::FBCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
4501 { 1118 /* fbne */, SP::BPFCC, Convert__Imm1_1__imm_95_1__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4502 { 1118 /* fbne */, SP::BPFCCA, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4503 { 1118 /* fbne */, SP::BPFCCNT, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4504 { 1118 /* fbne */, SP::BPFCC, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4505 { 1118 /* fbne */, SP::BPFCCANT, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4506 { 1118 /* fbne */, SP::BPFCCA, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4507 { 1123 /* fbnz */, SP::FBCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
4508 { 1123 /* fbnz */, SP::FBCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
4509 { 1123 /* fbnz */, SP::BPFCC, Convert__Imm1_1__imm_95_1__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4510 { 1123 /* fbnz */, SP::BPFCCA, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4511 { 1123 /* fbnz */, SP::BPFCCNT, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4512 { 1123 /* fbnz */, SP::BPFCC, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4513 { 1123 /* fbnz */, SP::BPFCCANT, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4514 { 1123 /* fbnz */, SP::BPFCCA, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4515 { 1128 /* fbo */, SP::FBCOND, Convert__Imm1_0__imm_95_15, AMFBS_None, { MCK_Imm }, },
4516 { 1128 /* fbo */, SP::FBCONDA, Convert__Imm1_1__imm_95_15, AMFBS_None, { MCK_a, MCK_Imm }, },
4517 { 1128 /* fbo */, SP::BPFCC, Convert__Imm1_1__imm_95_15__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4518 { 1128 /* fbo */, SP::BPFCCA, Convert__Imm1_2__imm_95_15__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4519 { 1128 /* fbo */, SP::BPFCCNT, Convert__Imm1_2__imm_95_15__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4520 { 1128 /* fbo */, SP::BPFCC, Convert__Imm1_2__imm_95_15__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4521 { 1128 /* fbo */, SP::BPFCCANT, Convert__Imm1_3__imm_95_15__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4522 { 1128 /* fbo */, SP::BPFCCA, Convert__Imm1_3__imm_95_15__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4523 { 1132 /* fbu */, SP::FBCOND, Convert__Imm1_0__imm_95_7, AMFBS_None, { MCK_Imm }, },
4524 { 1132 /* fbu */, SP::FBCONDA, Convert__Imm1_1__imm_95_7, AMFBS_None, { MCK_a, MCK_Imm }, },
4525 { 1132 /* fbu */, SP::BPFCC, Convert__Imm1_1__imm_95_7__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4526 { 1132 /* fbu */, SP::BPFCCA, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4527 { 1132 /* fbu */, SP::BPFCCNT, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4528 { 1132 /* fbu */, SP::BPFCC, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4529 { 1132 /* fbu */, SP::BPFCCANT, Convert__Imm1_3__imm_95_7__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4530 { 1132 /* fbu */, SP::BPFCCA, Convert__Imm1_3__imm_95_7__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4531 { 1136 /* fbue */, SP::FBCOND, Convert__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
4532 { 1136 /* fbue */, SP::FBCONDA, Convert__Imm1_1__imm_95_10, AMFBS_None, { MCK_a, MCK_Imm }, },
4533 { 1136 /* fbue */, SP::BPFCC, Convert__Imm1_1__imm_95_10__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4534 { 1136 /* fbue */, SP::BPFCCA, Convert__Imm1_2__imm_95_10__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4535 { 1136 /* fbue */, SP::BPFCCNT, Convert__Imm1_2__imm_95_10__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4536 { 1136 /* fbue */, SP::BPFCC, Convert__Imm1_2__imm_95_10__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4537 { 1136 /* fbue */, SP::BPFCCANT, Convert__Imm1_3__imm_95_10__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4538 { 1136 /* fbue */, SP::BPFCCA, Convert__Imm1_3__imm_95_10__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4539 { 1141 /* fbug */, SP::FBCOND, Convert__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
4540 { 1141 /* fbug */, SP::FBCONDA, Convert__Imm1_1__imm_95_5, AMFBS_None, { MCK_a, MCK_Imm }, },
4541 { 1141 /* fbug */, SP::BPFCC, Convert__Imm1_1__imm_95_5__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4542 { 1141 /* fbug */, SP::BPFCCA, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4543 { 1141 /* fbug */, SP::BPFCCNT, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4544 { 1141 /* fbug */, SP::BPFCC, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4545 { 1141 /* fbug */, SP::BPFCCANT, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4546 { 1141 /* fbug */, SP::BPFCCA, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4547 { 1146 /* fbuge */, SP::FBCOND, Convert__Imm1_0__imm_95_12, AMFBS_None, { MCK_Imm }, },
4548 { 1146 /* fbuge */, SP::FBCONDA, Convert__Imm1_1__imm_95_12, AMFBS_None, { MCK_a, MCK_Imm }, },
4549 { 1146 /* fbuge */, SP::BPFCC, Convert__Imm1_1__imm_95_12__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4550 { 1146 /* fbuge */, SP::BPFCCA, Convert__Imm1_2__imm_95_12__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4551 { 1146 /* fbuge */, SP::BPFCCNT, Convert__Imm1_2__imm_95_12__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4552 { 1146 /* fbuge */, SP::BPFCC, Convert__Imm1_2__imm_95_12__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4553 { 1146 /* fbuge */, SP::BPFCCANT, Convert__Imm1_3__imm_95_12__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4554 { 1146 /* fbuge */, SP::BPFCCA, Convert__Imm1_3__imm_95_12__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4555 { 1152 /* fbul */, SP::FBCOND, Convert__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
4556 { 1152 /* fbul */, SP::FBCONDA, Convert__Imm1_1__imm_95_3, AMFBS_None, { MCK_a, MCK_Imm }, },
4557 { 1152 /* fbul */, SP::BPFCC, Convert__Imm1_1__imm_95_3__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4558 { 1152 /* fbul */, SP::BPFCCA, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4559 { 1152 /* fbul */, SP::BPFCCNT, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4560 { 1152 /* fbul */, SP::BPFCC, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4561 { 1152 /* fbul */, SP::BPFCCANT, Convert__Imm1_3__imm_95_3__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4562 { 1152 /* fbul */, SP::BPFCCA, Convert__Imm1_3__imm_95_3__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4563 { 1157 /* fbule */, SP::FBCOND, Convert__Imm1_0__imm_95_14, AMFBS_None, { MCK_Imm }, },
4564 { 1157 /* fbule */, SP::FBCONDA, Convert__Imm1_1__imm_95_14, AMFBS_None, { MCK_a, MCK_Imm }, },
4565 { 1157 /* fbule */, SP::BPFCC, Convert__Imm1_1__imm_95_14__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4566 { 1157 /* fbule */, SP::BPFCCA, Convert__Imm1_2__imm_95_14__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4567 { 1157 /* fbule */, SP::BPFCCNT, Convert__Imm1_2__imm_95_14__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4568 { 1157 /* fbule */, SP::BPFCC, Convert__Imm1_2__imm_95_14__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4569 { 1157 /* fbule */, SP::BPFCCANT, Convert__Imm1_3__imm_95_14__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4570 { 1157 /* fbule */, SP::BPFCCA, Convert__Imm1_3__imm_95_14__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4571 { 1163 /* fbz */, SP::FBCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
4572 { 1163 /* fbz */, SP::FBCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
4573 { 1163 /* fbz */, SP::BPFCC, Convert__Imm1_1__imm_95_9__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4574 { 1163 /* fbz */, SP::BPFCCA, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4575 { 1163 /* fbz */, SP::BPFCCNT, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4576 { 1163 /* fbz */, SP::BPFCC, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4577 { 1163 /* fbz */, SP::BPFCCANT, Convert__Imm1_3__imm_95_9__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4578 { 1163 /* fbz */, SP::BPFCCA, Convert__Imm1_3__imm_95_9__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4579 { 1167 /* fchksm16 */, SP::FCHKSM16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4580 { 1176 /* fcmpd */, SP::V9FCMPD, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs }, },
4581 { 1176 /* fcmpd */, SP::V9FCMPD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4582 { 1182 /* fcmped */, SP::V9FCMPED, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs }, },
4583 { 1182 /* fcmped */, SP::V9FCMPED, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4584 { 1189 /* fcmpeq */, SP::V9FCMPEQ, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs }, },
4585 { 1189 /* fcmpeq */, SP::V9FCMPEQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4586 { 1196 /* fcmpeq16 */, SP::FCMPEQ16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4587 { 1205 /* fcmpeq32 */, SP::FCMPEQ32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4588 { 1214 /* fcmpes */, SP::V9FCMPES, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4589 { 1214 /* fcmpes */, SP::V9FCMPES, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4590 { 1221 /* fcmpgt16 */, SP::FCMPGT16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4591 { 1230 /* fcmpgt32 */, SP::FCMPGT32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4592 { 1239 /* fcmple16 */, SP::FCMPLE16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4593 { 1248 /* fcmple32 */, SP::FCMPLE32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4594 { 1257 /* fcmpne16 */, SP::FCMPNE16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4595 { 1266 /* fcmpne32 */, SP::FCMPNE32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4596 { 1275 /* fcmpq */, SP::V9FCMPQ, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs }, },
4597 { 1275 /* fcmpq */, SP::V9FCMPQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4598 { 1281 /* fcmps */, SP::V9FCMPS, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4599 { 1281 /* fcmps */, SP::V9FCMPS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4600 { 1287 /* fdivd */, SP::FDIVD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4601 { 1293 /* fdivq */, SP::FDIVQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4602 { 1299 /* fdivs */, SP::FDIVS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4603 { 1305 /* fdmulq */, SP::FDMULQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_QFPRegs }, },
4604 { 1312 /* fdtoi */, SP::FDTOI, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK_FPRegs }, },
4605 { 1318 /* fdtoq */, SP::FDTOQ, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK_QFPRegs }, },
4606 { 1324 /* fdtos */, SP::FDTOS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK_FPRegs }, },
4607 { 1330 /* fdtox */, SP::FDTOX, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_DFPRegs, MCK_DFPRegs }, },
4608 { 1336 /* fexpand */, SP::FEXPAND, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_DFPRegs }, },
4609 { 1344 /* fhaddd */, SP::FHADDD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4610 { 1351 /* fhadds */, SP::FHADDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4611 { 1358 /* fhsubd */, SP::FHSUBD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4612 { 1365 /* fhsubs */, SP::FHSUBS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4613 { 1372 /* fitod */, SP::FITOD, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_DFPRegs }, },
4614 { 1378 /* fitoq */, SP::FITOQ, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_QFPRegs }, },
4615 { 1384 /* fitos */, SP::FITOS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4616 { 1390 /* flcmpd */, SP::FLCMPD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVIS3, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4617 { 1397 /* flcmps */, SP::FLCMPS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVIS3, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4618 { 1404 /* flush */, SP::FLUSH, Convert_NoOperands, AMFBS_None, { }, },
4619 { 1404 /* flush */, SP::FLUSH, Convert_NoOperands, AMFBS_None, { MCK_G0 }, },
4620 { 1404 /* flush */, SP::FLUSHri, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, },
4621 { 1404 /* flush */, SP::FLUSHrr, Convert__MEMrr2_0, AMFBS_None, { MCK_MEMrr }, },
4622 { 1410 /* flushw */, SP::FLUSHW, Convert_NoOperands, AMFBS_HasV9, { }, },
4623 { 1417 /* fmaddd */, SP::FMADDD, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4624 { 1424 /* fmadds */, SP::FMADDS, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4625 { 1431 /* fmean16 */, SP::FMEAN16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4626 { 1439 /* fmovd */, SP::FMOVD, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_DFPRegs, MCK_DFPRegs }, },
4627 { 1439 /* fmovd */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4628 { 1439 /* fmovd */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4629 { 1439 /* fmovd */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4630 { 1439 /* fmovd */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4631 { 1439 /* fmovd */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4632 { 1439 /* fmovd */, SP::FMOVD_XCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4633 { 1439 /* fmovd */, SP::FMOVD_FCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_DFPRegs, MCK_DFPRegs }, },
4634 { 1439 /* fmovd */, SP::FMOVD_ICC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4635 { 1439 /* fmovd */, SP::V9FMOVD_FCC, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4636 { 1445 /* fmovda */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4637 { 1445 /* fmovda */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4638 { 1445 /* fmovda */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4639 { 1445 /* fmovda */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4640 { 1445 /* fmovda */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4641 { 1452 /* fmovdcc */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4642 { 1452 /* fmovdcc */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4643 { 1452 /* fmovdcc */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4644 { 1452 /* fmovdcc */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4645 { 1460 /* fmovdcs */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4646 { 1460 /* fmovdcs */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4647 { 1460 /* fmovdcs */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4648 { 1460 /* fmovdcs */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4649 { 1468 /* fmovde */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4650 { 1468 /* fmovde */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4651 { 1468 /* fmovde */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4652 { 1468 /* fmovde */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4653 { 1468 /* fmovde */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4654 { 1475 /* fmovdeq */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4655 { 1475 /* fmovdeq */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4656 { 1475 /* fmovdeq */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4657 { 1475 /* fmovdeq */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4658 { 1483 /* fmovdg */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4659 { 1483 /* fmovdg */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4660 { 1483 /* fmovdg */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4661 { 1483 /* fmovdg */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4662 { 1483 /* fmovdg */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4663 { 1490 /* fmovdge */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4664 { 1490 /* fmovdge */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4665 { 1490 /* fmovdge */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4666 { 1490 /* fmovdge */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4667 { 1490 /* fmovdge */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4668 { 1498 /* fmovdgeu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4669 { 1498 /* fmovdgeu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4670 { 1498 /* fmovdgeu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4671 { 1498 /* fmovdgeu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4672 { 1507 /* fmovdgt */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4673 { 1507 /* fmovdgt */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4674 { 1507 /* fmovdgt */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4675 { 1507 /* fmovdgt */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4676 { 1515 /* fmovdgu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4677 { 1515 /* fmovdgu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4678 { 1515 /* fmovdgu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4679 { 1515 /* fmovdgu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4680 { 1523 /* fmovdl */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4681 { 1523 /* fmovdl */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4682 { 1523 /* fmovdl */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4683 { 1523 /* fmovdl */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4684 { 1523 /* fmovdl */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4685 { 1530 /* fmovdle */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4686 { 1530 /* fmovdle */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4687 { 1530 /* fmovdle */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4688 { 1530 /* fmovdle */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4689 { 1530 /* fmovdle */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4690 { 1538 /* fmovdleu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4691 { 1538 /* fmovdleu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4692 { 1538 /* fmovdleu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4693 { 1538 /* fmovdleu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4694 { 1547 /* fmovdlg */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4695 { 1555 /* fmovdlt */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4696 { 1555 /* fmovdlt */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4697 { 1555 /* fmovdlt */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4698 { 1555 /* fmovdlt */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4699 { 1563 /* fmovdlu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4700 { 1563 /* fmovdlu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4701 { 1563 /* fmovdlu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4702 { 1563 /* fmovdlu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4703 { 1571 /* fmovdn */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4704 { 1571 /* fmovdn */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4705 { 1571 /* fmovdn */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4706 { 1571 /* fmovdn */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4707 { 1571 /* fmovdn */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4708 { 1578 /* fmovdne */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4709 { 1578 /* fmovdne */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4710 { 1578 /* fmovdne */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4711 { 1578 /* fmovdne */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4712 { 1578 /* fmovdne */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4713 { 1586 /* fmovdneg */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4714 { 1586 /* fmovdneg */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4715 { 1586 /* fmovdneg */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4716 { 1586 /* fmovdneg */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4717 { 1595 /* fmovdnz */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4718 { 1595 /* fmovdnz */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4719 { 1595 /* fmovdnz */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4720 { 1595 /* fmovdnz */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4721 { 1595 /* fmovdnz */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4722 { 1603 /* fmovdo */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4723 { 1610 /* fmovdpos */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4724 { 1610 /* fmovdpos */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4725 { 1610 /* fmovdpos */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4726 { 1610 /* fmovdpos */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4727 { 1619 /* fmovdu */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4728 { 1626 /* fmovdue */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4729 { 1634 /* fmovdug */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4730 { 1642 /* fmovduge */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4731 { 1651 /* fmovdul */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4732 { 1659 /* fmovdule */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4733 { 1668 /* fmovdvc */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4734 { 1668 /* fmovdvc */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4735 { 1668 /* fmovdvc */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4736 { 1668 /* fmovdvc */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4737 { 1676 /* fmovdvs */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4738 { 1676 /* fmovdvs */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4739 { 1676 /* fmovdvs */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4740 { 1676 /* fmovdvs */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4741 { 1684 /* fmovdz */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4742 { 1684 /* fmovdz */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_DFPRegs, MCK_DFPRegs }, },
4743 { 1684 /* fmovdz */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4744 { 1684 /* fmovdz */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4745 { 1684 /* fmovdz */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4746 { 1691 /* fmovq */, SP::FMOVQ, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK_QFPRegs }, },
4747 { 1691 /* fmovq */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4748 { 1691 /* fmovq */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4749 { 1691 /* fmovq */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4750 { 1691 /* fmovq */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4751 { 1691 /* fmovq */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4752 { 1691 /* fmovq */, SP::FMOVQ_XCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4753 { 1691 /* fmovq */, SP::FMOVQ_FCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_QFPRegs, MCK_QFPRegs }, },
4754 { 1691 /* fmovq */, SP::FMOVQ_ICC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4755 { 1691 /* fmovq */, SP::V9FMOVQ_FCC, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4756 { 1697 /* fmovqa */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4757 { 1697 /* fmovqa */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4758 { 1697 /* fmovqa */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4759 { 1697 /* fmovqa */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4760 { 1697 /* fmovqa */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4761 { 1704 /* fmovqcc */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4762 { 1704 /* fmovqcc */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4763 { 1704 /* fmovqcc */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4764 { 1704 /* fmovqcc */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4765 { 1712 /* fmovqcs */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4766 { 1712 /* fmovqcs */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4767 { 1712 /* fmovqcs */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4768 { 1712 /* fmovqcs */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4769 { 1720 /* fmovqe */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4770 { 1720 /* fmovqe */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4771 { 1720 /* fmovqe */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4772 { 1720 /* fmovqe */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4773 { 1720 /* fmovqe */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4774 { 1727 /* fmovqeq */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4775 { 1727 /* fmovqeq */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4776 { 1727 /* fmovqeq */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4777 { 1727 /* fmovqeq */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4778 { 1735 /* fmovqg */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4779 { 1735 /* fmovqg */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4780 { 1735 /* fmovqg */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4781 { 1735 /* fmovqg */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4782 { 1735 /* fmovqg */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4783 { 1742 /* fmovqge */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4784 { 1742 /* fmovqge */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4785 { 1742 /* fmovqge */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4786 { 1742 /* fmovqge */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4787 { 1742 /* fmovqge */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4788 { 1750 /* fmovqgeu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4789 { 1750 /* fmovqgeu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4790 { 1750 /* fmovqgeu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4791 { 1750 /* fmovqgeu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4792 { 1759 /* fmovqgt */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4793 { 1759 /* fmovqgt */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4794 { 1759 /* fmovqgt */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4795 { 1759 /* fmovqgt */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4796 { 1767 /* fmovqgu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4797 { 1767 /* fmovqgu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4798 { 1767 /* fmovqgu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4799 { 1767 /* fmovqgu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4800 { 1775 /* fmovql */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4801 { 1775 /* fmovql */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4802 { 1775 /* fmovql */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4803 { 1775 /* fmovql */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4804 { 1775 /* fmovql */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4805 { 1782 /* fmovqle */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4806 { 1782 /* fmovqle */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4807 { 1782 /* fmovqle */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4808 { 1782 /* fmovqle */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4809 { 1782 /* fmovqle */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4810 { 1790 /* fmovqleu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4811 { 1790 /* fmovqleu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4812 { 1790 /* fmovqleu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4813 { 1790 /* fmovqleu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4814 { 1799 /* fmovqlg */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4815 { 1807 /* fmovqlt */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4816 { 1807 /* fmovqlt */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4817 { 1807 /* fmovqlt */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4818 { 1807 /* fmovqlt */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4819 { 1815 /* fmovqlu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4820 { 1815 /* fmovqlu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4821 { 1815 /* fmovqlu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4822 { 1815 /* fmovqlu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4823 { 1823 /* fmovqn */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4824 { 1823 /* fmovqn */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4825 { 1823 /* fmovqn */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4826 { 1823 /* fmovqn */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4827 { 1823 /* fmovqn */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4828 { 1830 /* fmovqne */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4829 { 1830 /* fmovqne */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4830 { 1830 /* fmovqne */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4831 { 1830 /* fmovqne */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4832 { 1830 /* fmovqne */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4833 { 1838 /* fmovqneg */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4834 { 1838 /* fmovqneg */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4835 { 1838 /* fmovqneg */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4836 { 1838 /* fmovqneg */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4837 { 1847 /* fmovqnz */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4838 { 1847 /* fmovqnz */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4839 { 1847 /* fmovqnz */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4840 { 1847 /* fmovqnz */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4841 { 1847 /* fmovqnz */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4842 { 1855 /* fmovqo */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4843 { 1862 /* fmovqpos */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4844 { 1862 /* fmovqpos */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4845 { 1862 /* fmovqpos */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4846 { 1862 /* fmovqpos */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4847 { 1871 /* fmovqu */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4848 { 1878 /* fmovque */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4849 { 1886 /* fmovqug */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4850 { 1894 /* fmovquge */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4851 { 1903 /* fmovqul */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4852 { 1911 /* fmovqule */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4853 { 1920 /* fmovqvc */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4854 { 1920 /* fmovqvc */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4855 { 1920 /* fmovqvc */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4856 { 1920 /* fmovqvc */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4857 { 1928 /* fmovqvs */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4858 { 1928 /* fmovqvs */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4859 { 1928 /* fmovqvs */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4860 { 1928 /* fmovqvs */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4861 { 1936 /* fmovqz */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4862 { 1936 /* fmovqz */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_QFPRegs, MCK_QFPRegs }, },
4863 { 1936 /* fmovqz */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4864 { 1936 /* fmovqz */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4865 { 1936 /* fmovqz */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4866 { 1943 /* fmovrd */, SP::FMOVRD, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4867 { 1950 /* fmovrde */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4868 { 1958 /* fmovrdgez */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4869 { 1968 /* fmovrdgz */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4870 { 1977 /* fmovrdlez */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4871 { 1987 /* fmovrdlz */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4872 { 1996 /* fmovrdne */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4873 { 2005 /* fmovrdnz */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4874 { 2014 /* fmovrdz */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4875 { 2022 /* fmovrq */, SP::FMOVRQ, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4876 { 2029 /* fmovrqe */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4877 { 2037 /* fmovrqgez */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4878 { 2047 /* fmovrqgz */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4879 { 2056 /* fmovrqlez */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4880 { 2066 /* fmovrqlz */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4881 { 2075 /* fmovrqne */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4882 { 2084 /* fmovrqnz */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4883 { 2093 /* fmovrqz */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4884 { 2101 /* fmovrs */, SP::FMOVRS, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4885 { 2108 /* fmovrse */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4886 { 2116 /* fmovrsgez */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4887 { 2126 /* fmovrsgz */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4888 { 2135 /* fmovrslez */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4889 { 2145 /* fmovrslz */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4890 { 2154 /* fmovrsne */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4891 { 2163 /* fmovrsnz */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4892 { 2172 /* fmovrsz */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4893 { 2180 /* fmovs */, SP::FMOVS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4894 { 2180 /* fmovs */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4895 { 2180 /* fmovs */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4896 { 2180 /* fmovs */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4897 { 2180 /* fmovs */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4898 { 2180 /* fmovs */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4899 { 2180 /* fmovs */, SP::FMOVS_XCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4900 { 2180 /* fmovs */, SP::FMOVS_FCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_FPRegs, MCK_FPRegs }, },
4901 { 2180 /* fmovs */, SP::FMOVS_ICC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4902 { 2180 /* fmovs */, SP::V9FMOVS_FCC, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4903 { 2186 /* fmovsa */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4904 { 2186 /* fmovsa */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4905 { 2186 /* fmovsa */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4906 { 2186 /* fmovsa */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4907 { 2186 /* fmovsa */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4908 { 2193 /* fmovscc */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4909 { 2193 /* fmovscc */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4910 { 2193 /* fmovscc */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4911 { 2193 /* fmovscc */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4912 { 2201 /* fmovscs */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4913 { 2201 /* fmovscs */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4914 { 2201 /* fmovscs */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4915 { 2201 /* fmovscs */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4916 { 2209 /* fmovse */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4917 { 2209 /* fmovse */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4918 { 2209 /* fmovse */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4919 { 2209 /* fmovse */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4920 { 2209 /* fmovse */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4921 { 2216 /* fmovseq */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4922 { 2216 /* fmovseq */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4923 { 2216 /* fmovseq */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4924 { 2216 /* fmovseq */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4925 { 2224 /* fmovsg */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4926 { 2224 /* fmovsg */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4927 { 2224 /* fmovsg */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4928 { 2224 /* fmovsg */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4929 { 2224 /* fmovsg */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4930 { 2231 /* fmovsge */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4931 { 2231 /* fmovsge */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4932 { 2231 /* fmovsge */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4933 { 2231 /* fmovsge */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4934 { 2231 /* fmovsge */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4935 { 2239 /* fmovsgeu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4936 { 2239 /* fmovsgeu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4937 { 2239 /* fmovsgeu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4938 { 2239 /* fmovsgeu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4939 { 2248 /* fmovsgt */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4940 { 2248 /* fmovsgt */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4941 { 2248 /* fmovsgt */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4942 { 2248 /* fmovsgt */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4943 { 2256 /* fmovsgu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4944 { 2256 /* fmovsgu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4945 { 2256 /* fmovsgu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4946 { 2256 /* fmovsgu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4947 { 2264 /* fmovsl */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4948 { 2264 /* fmovsl */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4949 { 2264 /* fmovsl */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4950 { 2264 /* fmovsl */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4951 { 2264 /* fmovsl */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4952 { 2271 /* fmovsle */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4953 { 2271 /* fmovsle */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4954 { 2271 /* fmovsle */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4955 { 2271 /* fmovsle */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4956 { 2271 /* fmovsle */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4957 { 2279 /* fmovsleu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4958 { 2279 /* fmovsleu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4959 { 2279 /* fmovsleu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4960 { 2279 /* fmovsleu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4961 { 2288 /* fmovslg */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4962 { 2296 /* fmovslt */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4963 { 2296 /* fmovslt */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4964 { 2296 /* fmovslt */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4965 { 2296 /* fmovslt */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4966 { 2304 /* fmovslu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4967 { 2304 /* fmovslu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4968 { 2304 /* fmovslu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4969 { 2304 /* fmovslu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4970 { 2312 /* fmovsn */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4971 { 2312 /* fmovsn */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4972 { 2312 /* fmovsn */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4973 { 2312 /* fmovsn */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4974 { 2312 /* fmovsn */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4975 { 2319 /* fmovsne */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4976 { 2319 /* fmovsne */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4977 { 2319 /* fmovsne */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4978 { 2319 /* fmovsne */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4979 { 2319 /* fmovsne */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4980 { 2327 /* fmovsneg */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4981 { 2327 /* fmovsneg */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4982 { 2327 /* fmovsneg */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4983 { 2327 /* fmovsneg */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4984 { 2336 /* fmovsnz */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4985 { 2336 /* fmovsnz */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4986 { 2336 /* fmovsnz */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4987 { 2336 /* fmovsnz */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4988 { 2336 /* fmovsnz */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4989 { 2344 /* fmovso */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4990 { 2351 /* fmovspos */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4991 { 2351 /* fmovspos */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
4992 { 2351 /* fmovspos */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4993 { 2351 /* fmovspos */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4994 { 2360 /* fmovsu */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4995 { 2367 /* fmovsue */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4996 { 2375 /* fmovsug */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4997 { 2383 /* fmovsuge */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4998 { 2392 /* fmovsul */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4999 { 2400 /* fmovsule */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
5000 { 2409 /* fmovsvc */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
5001 { 2409 /* fmovsvc */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
5002 { 2409 /* fmovsvc */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
5003 { 2409 /* fmovsvc */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
5004 { 2417 /* fmovsvs */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
5005 { 2417 /* fmovsvs */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
5006 { 2417 /* fmovsvs */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
5007 { 2417 /* fmovsvs */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
5008 { 2425 /* fmovsz */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
5009 { 2425 /* fmovsz */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_FPRegs, MCK_FPRegs }, },
5010 { 2425 /* fmovsz */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
5011 { 2425 /* fmovsz */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
5012 { 2425 /* fmovsz */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
5013 { 2432 /* fmsubd */, SP::FMSUBD, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5014 { 2439 /* fmsubs */, SP::FMSUBS, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5015 { 2446 /* fmul8sux16 */, SP::FMUL8SUX16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5016 { 2457 /* fmul8ulx16 */, SP::FMUL8ULX16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5017 { 2468 /* fmul8x16 */, SP::FMUL8X16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5018 { 2477 /* fmul8x16al */, SP::FMUL8X16AL, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
5019 { 2488 /* fmul8x16au */, SP::FMUL8X16AU, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
5020 { 2499 /* fmuld */, SP::FMULD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5021 { 2505 /* fmuld8sux16 */, SP::FMULD8SUX16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
5022 { 2517 /* fmuld8ulx16 */, SP::FMULD8ULX16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
5023 { 2529 /* fmulq */, SP::FMULQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
5024 { 2535 /* fmuls */, SP::FMULS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5025 { 2541 /* fnaddd */, SP::FNADDD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5026 { 2548 /* fnadds */, SP::FNADDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5027 { 2555 /* fnand */, SP::FNAND, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5028 { 2561 /* fnands */, SP::FNANDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5029 { 2568 /* fnegd */, SP::FNEGD, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_DFPRegs, MCK_DFPRegs }, },
5030 { 2574 /* fnegq */, SP::FNEGQ, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK_QFPRegs }, },
5031 { 2580 /* fnegs */, SP::FNEGS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
5032 { 2586 /* fnhaddd */, SP::FNHADDD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5033 { 2594 /* fnhadds */, SP::FNHADDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5034 { 2602 /* fnmaddd */, SP::FNMADDD, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5035 { 2610 /* fnmadds */, SP::FNMADDS, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5036 { 2618 /* fnmsubd */, SP::FNMSUBD, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5037 { 2626 /* fnmsubs */, SP::FNMSUBS, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5038 { 2634 /* fnmuld */, SP::FNMULD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5039 { 2641 /* fnmuls */, SP::FNMULS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5040 { 2648 /* fnor */, SP::FNOR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5041 { 2653 /* fnors */, SP::FNORS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5042 { 2659 /* fnot1 */, SP::FNOT1, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
5043 { 2665 /* fnot1s */, SP::FNOT1S, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
5044 { 2672 /* fnot2 */, SP::FNOT2, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
5045 { 2678 /* fnot2s */, SP::FNOT2S, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
5046 { 2685 /* fnsmuld */, SP::FNSMULD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
5047 { 2693 /* fone */, SP::FONE, Convert__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs }, },
5048 { 2698 /* fones */, SP::FONES, Convert__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs }, },
5049 { 2704 /* for */, SP::FOR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5050 { 2708 /* fornot1 */, SP::FORNOT1, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5051 { 2716 /* fornot1s */, SP::FORNOT1S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5052 { 2725 /* fornot2 */, SP::FORNOT2, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5053 { 2733 /* fornot2s */, SP::FORNOT2S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5054 { 2742 /* fors */, SP::FORS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5055 { 2747 /* fpack16 */, SP::FPACK16, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
5056 { 2755 /* fpack32 */, SP::FPACK32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5057 { 2763 /* fpackfix */, SP::FPACKFIX, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_FPRegs }, },
5058 { 2772 /* fpadd16 */, SP::FPADD16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5059 { 2780 /* fpadd16s */, SP::FPADD16S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5060 { 2789 /* fpadd32 */, SP::FPADD32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5061 { 2797 /* fpadd32s */, SP::FPADD32S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5062 { 2806 /* fpadd64 */, SP::FPADD64, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5063 { 2814 /* fpmaddx */, SP::FPMADDX, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasOSA2011, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5064 { 2822 /* fpmaddxhi */, SP::FPMADDXHI, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasOSA2011, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5065 { 2832 /* fpmerge */, SP::FPMERGE, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
5066 { 2840 /* fpsub16 */, SP::FPSUB16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5067 { 2848 /* fpsub16s */, SP::FPSUB16S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5068 { 2857 /* fpsub32 */, SP::FPSUB32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5069 { 2865 /* fpsub32s */, SP::FPSUB32S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5070 { 2874 /* fqtod */, SP::FQTOD, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_QFPRegs, MCK_DFPRegs }, },
5071 { 2880 /* fqtoi */, SP::FQTOI, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_QFPRegs, MCK_FPRegs }, },
5072 { 2886 /* fqtos */, SP::FQTOS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_QFPRegs, MCK_FPRegs }, },
5073 { 2892 /* fqtox */, SP::FQTOX, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_QFPRegs, MCK_DFPRegs }, },
5074 { 2898 /* fslas16 */, SP::FSLAS16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5075 { 2906 /* fslas32 */, SP::FSLAS32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5076 { 2914 /* fsll16 */, SP::FSLL16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5077 { 2921 /* fsll32 */, SP::FSLL32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5078 { 2928 /* fsmuld */, SP::FSMULD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
5079 { 2935 /* fsqrtd */, SP::FSQRTD, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs }, },
5080 { 2942 /* fsqrtq */, SP::FSQRTQ, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs }, },
5081 { 2949 /* fsqrts */, SP::FSQRTS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
5082 { 2956 /* fsra16 */, SP::FSRA16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5083 { 2963 /* fsra32 */, SP::FSRA32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5084 { 2970 /* fsrc1 */, SP::FSRC1, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
5085 { 2976 /* fsrc1s */, SP::FSRC1S, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
5086 { 2983 /* fsrc2 */, SP::FSRC2, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
5087 { 2989 /* fsrc2s */, SP::FSRC2S, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
5088 { 2996 /* fsrl16 */, SP::FSRL16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5089 { 3003 /* fsrl32 */, SP::FSRL32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5090 { 3010 /* fstod */, SP::FSTOD, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_DFPRegs }, },
5091 { 3016 /* fstoi */, SP::FSTOI, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
5092 { 3022 /* fstoq */, SP::FSTOQ, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_QFPRegs }, },
5093 { 3028 /* fstox */, SP::FSTOX, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_FPRegs, MCK_DFPRegs }, },
5094 { 3034 /* fsubd */, SP::FSUBD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5095 { 3040 /* fsubq */, SP::FSUBQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
5096 { 3046 /* fsubs */, SP::FSUBS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5097 { 3052 /* fxnor */, SP::FXNOR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5098 { 3058 /* fxnors */, SP::FXNORS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5099 { 3065 /* fxor */, SP::FXOR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5100 { 3070 /* fxors */, SP::FXORS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
5101 { 3076 /* fxtod */, SP::FXTOD, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_DFPRegs, MCK_DFPRegs }, },
5102 { 3082 /* fxtoq */, SP::FXTOQ, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_DFPRegs, MCK_QFPRegs }, },
5103 { 3088 /* fxtos */, SP::FXTOS, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_DFPRegs, MCK_FPRegs }, },
5104 { 3094 /* fzero */, SP::FZERO, Convert__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs }, },
5105 { 3100 /* fzeros */, SP::FZEROS, Convert__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs }, },
5106 { 3107 /* inc */, SP::ADDri, Convert__Reg1_0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
5107 { 3107 /* inc */, SP::ADDri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
5108 { 3111 /* inccc */, SP::ADDCCri, Convert__Reg1_0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
5109 { 3111 /* inccc */, SP::ADDCCri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
5110 { 3117 /* invalw */, SP::INVALW, Convert_NoOperands, AMFBS_HasUA2005, { }, },
5111 { 3124 /* jmp */, SP::JMPLri, Convert__regG0__MEMri2_0, AMFBS_None, { MCK_MEMri }, },
5112 { 3124 /* jmp */, SP::JMPLrr, Convert__regG0__MEMrr2_0, AMFBS_None, { MCK_MEMrr }, },
5113 { 3128 /* jmpl */, SP::JMPLri, Convert__Reg1_1__MEMri2_0, AMFBS_None, { MCK_MEMri, MCK_IntRegs }, },
5114 { 3128 /* jmpl */, SP::JMPLrr, Convert__Reg1_1__MEMrr2_0, AMFBS_None, { MCK_MEMrr, MCK_IntRegs }, },
5115 { 3133 /* ld */, SP::LDCSRri, Convert__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_CPSR }, },
5116 { 3133 /* ld */, SP::LDFSRri, Convert__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_FSR }, },
5117 { 3133 /* ld */, SP::LDCri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_CoprocRegs }, },
5118 { 3133 /* ld */, SP::LDFri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_FPRegs }, },
5119 { 3133 /* ld */, SP::LDri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
5120 { 3133 /* ld */, SP::LDCSRrr, Convert__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_CPSR }, },
5121 { 3133 /* ld */, SP::LDFSRrr, Convert__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_FSR }, },
5122 { 3133 /* ld */, SP::LDCrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_CoprocRegs }, },
5123 { 3133 /* ld */, SP::LDFrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_FPRegs }, },
5124 { 3133 /* ld */, SP::LDrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
5125 { 3133 /* ld */, SP::GDOP_LDrr, Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_GOT1_4, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs, MCK_TailRelocSymLoad_GOT }, },
5126 { 3133 /* ld */, SP::TLS_LDrr, Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_TLS1_4, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs, MCK_TailRelocSymLoad_TLS }, },
5127 { 3136 /* lda */, SP::LDFAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_FPRegs }, },
5128 { 3136 /* lda */, SP::LDAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
5129 { 3136 /* lda */, SP::LDFArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_FPRegs }, },
5130 { 3136 /* lda */, SP::LDArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
5131 { 3140 /* ldd */, SP::LDDCri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_CoprocPair }, },
5132 { 3140 /* ldd */, SP::LDDri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntPair }, },
5133 { 3140 /* ldd */, SP::LDDFri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_DFPRegs }, },
5134 { 3140 /* ldd */, SP::LDDCrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_CoprocPair }, },
5135 { 3140 /* ldd */, SP::LDDrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntPair }, },
5136 { 3140 /* ldd */, SP::LDDFrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_DFPRegs }, },
5137 { 3144 /* ldda */, SP::LDDAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntPair }, },
5138 { 3144 /* ldda */, SP::LDDFAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_DFPRegs }, },
5139 { 3144 /* ldda */, SP::LDDArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntPair }, },
5140 { 3144 /* ldda */, SP::LDDFArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_DFPRegs }, },
5141 { 3149 /* ldq */, SP::LDQFri, Convert__Reg1_3__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK_QFPRegs }, },
5142 { 3149 /* ldq */, SP::LDQFrr, Convert__Reg1_3__MEMrr2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_QFPRegs }, },
5143 { 3153 /* ldqa */, SP::LDQFAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_QFPRegs }, },
5144 { 3153 /* ldqa */, SP::LDQFArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_QFPRegs }, },
5145 { 3158 /* ldsb */, SP::LDSBri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
5146 { 3158 /* ldsb */, SP::LDSBrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
5147 { 3163 /* ldsba */, SP::LDSBAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
5148 { 3163 /* ldsba */, SP::LDSBArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
5149 { 3169 /* ldsh */, SP::LDSHri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
5150 { 3169 /* ldsh */, SP::LDSHrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
5151 { 3174 /* ldsha */, SP::LDSHAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
5152 { 3174 /* ldsha */, SP::LDSHArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
5153 { 3180 /* ldstub */, SP::LDSTUBri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
5154 { 3180 /* ldstub */, SP::LDSTUBrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
5155 { 3187 /* ldstuba */, SP::LDSTUBAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
5156 { 3187 /* ldstuba */, SP::LDSTUBArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
5157 { 3195 /* ldsw */, SP::LDSWri, Convert__Reg1_3__MEMri2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
5158 { 3195 /* ldsw */, SP::LDSWrr, Convert__Reg1_3__MEMrr2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
5159 { 3200 /* ldswa */, SP::LDSWAri, Convert__Reg1_4__MEMri2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
5160 { 3200 /* ldswa */, SP::LDSWArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
5161 { 3206 /* ldub */, SP::LDUBri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
5162 { 3206 /* ldub */, SP::LDUBrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
5163 { 3211 /* lduba */, SP::LDUBAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
5164 { 3211 /* lduba */, SP::LDUBArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
5165 { 3217 /* lduh */, SP::LDUHri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
5166 { 3217 /* lduh */, SP::LDUHrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
5167 { 3222 /* lduha */, SP::LDUHAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
5168 { 3222 /* lduha */, SP::LDUHArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
5169 { 3228 /* ldx */, SP::LDXFSRri, Convert__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK_FSR }, },
5170 { 3228 /* ldx */, SP::LDXri, Convert__Reg1_3__MEMri2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
5171 { 3228 /* ldx */, SP::LDXFSRrr, Convert__MEMrr2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_FSR }, },
5172 { 3228 /* ldx */, SP::LDXrr, Convert__Reg1_3__MEMrr2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
5173 { 3228 /* ldx */, SP::GDOP_LDXrr, Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_GOT1_4, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs, MCK_TailRelocSymLoad_GOT }, },
5174 { 3228 /* ldx */, SP::TLS_LDXrr, Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_TLS1_4, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs, MCK_TailRelocSymLoad_TLS }, },
5175 { 3232 /* ldxa */, SP::LDXAri, Convert__Reg1_4__MEMri2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
5176 { 3232 /* ldxa */, SP::LDXArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
5177 { 3237 /* lzcnt */, SP::LZCNT, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs }, },
5178 { 3243 /* md5 */, SP::MD5, Convert_NoOperands, AMFBS_HasCrypto, { }, },
5179 { 3247 /* membar */, SP::MEMBARi, Convert__MembarTag1_0, AMFBS_HasV9, { MCK_MembarTag }, },
5180 { 3254 /* montmul */, SP::MONTMUL, Convert__Imm1_0, AMFBS_HasCrypto, { MCK_Imm }, },
5181 { 3262 /* montsqr */, SP::MONTSQR, Convert__Imm1_0, AMFBS_HasCrypto, { MCK_Imm }, },
5182 { 3270 /* mov */, SP::RDPSR, Convert__Reg1_1, AMFBS_None, { MCK_PSR, MCK_IntRegs }, },
5183 { 3270 /* mov */, SP::RDTBR, Convert__Reg1_1, AMFBS_None, { MCK_TBR, MCK_IntRegs }, },
5184 { 3270 /* mov */, SP::RDWIM, Convert__Reg1_1, AMFBS_None, { MCK_WIM, MCK_IntRegs }, },
5185 { 3270 /* mov */, SP::WRPSRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_PSR }, },
5186 { 3270 /* mov */, SP::WRTBRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_TBR }, },
5187 { 3270 /* mov */, SP::WRWIMrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_WIM }, },
5188 { 3270 /* mov */, SP::ORrr, Convert__Reg1_1__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
5189 { 3270 /* mov */, SP::WRASRrr, Convert__Reg1_1__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_ASRRegs }, },
5190 { 3270 /* mov */, SP::RDASR, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_ASRRegs, MCK_IntRegs }, },
5191 { 3270 /* mov */, SP::WRPSRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_PSR }, },
5192 { 3270 /* mov */, SP::WRTBRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_TBR }, },
5193 { 3270 /* mov */, SP::WRWIMri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_WIM }, },
5194 { 3270 /* mov */, SP::ORri, Convert__Reg1_1__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
5195 { 3270 /* mov */, SP::WRASRri, Convert__Reg1_1__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_ASRRegs }, },
5196 { 3270 /* mov */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5197 { 3270 /* mov */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5198 { 3270 /* mov */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5199 { 3270 /* mov */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5200 { 3270 /* mov */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5201 { 3270 /* mov */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5202 { 3270 /* mov */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5203 { 3270 /* mov */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5204 { 3270 /* mov */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5205 { 3270 /* mov */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5206 { 3270 /* mov */, SP::MOVXCCrr, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5207 { 3270 /* mov */, SP::MOVXCCri, Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5208 { 3270 /* mov */, SP::MOVFCCrr, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_IntRegs, MCK_IntRegs }, },
5209 { 3270 /* mov */, SP::MOVFCCri, Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_Imm, MCK_IntRegs }, },
5210 { 3270 /* mov */, SP::MOVICCrr, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5211 { 3270 /* mov */, SP::MOVICCri, Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5212 { 3270 /* mov */, SP::V9MOVFCCrr, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5213 { 3270 /* mov */, SP::V9MOVFCCri, Convert__Reg1_3__Reg1_1__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5214 { 3274 /* mova */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5215 { 3274 /* mova */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5216 { 3274 /* mova */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5217 { 3274 /* mova */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5218 { 3274 /* mova */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5219 { 3274 /* mova */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5220 { 3274 /* mova */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5221 { 3274 /* mova */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5222 { 3274 /* mova */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5223 { 3274 /* mova */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5224 { 3279 /* movcc */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5225 { 3279 /* movcc */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5226 { 3279 /* movcc */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5227 { 3279 /* movcc */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5228 { 3279 /* movcc */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5229 { 3279 /* movcc */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5230 { 3279 /* movcc */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5231 { 3279 /* movcc */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5232 { 3285 /* movcs */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5233 { 3285 /* movcs */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5234 { 3285 /* movcs */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5235 { 3285 /* movcs */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5236 { 3285 /* movcs */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5237 { 3285 /* movcs */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5238 { 3285 /* movcs */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5239 { 3285 /* movcs */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5240 { 3291 /* movdtox */, SP::MOVDTOX, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_IntRegs }, },
5241 { 3299 /* move */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5242 { 3299 /* move */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5243 { 3299 /* move */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5244 { 3299 /* move */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5245 { 3299 /* move */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5246 { 3299 /* move */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5247 { 3299 /* move */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5248 { 3299 /* move */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5249 { 3299 /* move */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5250 { 3299 /* move */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5251 { 3304 /* moveq */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5252 { 3304 /* moveq */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5253 { 3304 /* moveq */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5254 { 3304 /* moveq */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5255 { 3304 /* moveq */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5256 { 3304 /* moveq */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5257 { 3304 /* moveq */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5258 { 3304 /* moveq */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5259 { 3310 /* movg */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5260 { 3310 /* movg */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5261 { 3310 /* movg */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5262 { 3310 /* movg */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5263 { 3310 /* movg */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5264 { 3310 /* movg */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5265 { 3310 /* movg */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5266 { 3310 /* movg */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5267 { 3310 /* movg */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5268 { 3310 /* movg */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5269 { 3315 /* movge */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5270 { 3315 /* movge */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5271 { 3315 /* movge */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5272 { 3315 /* movge */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5273 { 3315 /* movge */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5274 { 3315 /* movge */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5275 { 3315 /* movge */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5276 { 3315 /* movge */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5277 { 3315 /* movge */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5278 { 3315 /* movge */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5279 { 3321 /* movgeu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5280 { 3321 /* movgeu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5281 { 3321 /* movgeu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5282 { 3321 /* movgeu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5283 { 3321 /* movgeu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5284 { 3321 /* movgeu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5285 { 3321 /* movgeu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5286 { 3321 /* movgeu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5287 { 3328 /* movgt */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5288 { 3328 /* movgt */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5289 { 3328 /* movgt */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5290 { 3328 /* movgt */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5291 { 3328 /* movgt */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5292 { 3328 /* movgt */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5293 { 3328 /* movgt */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5294 { 3328 /* movgt */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5295 { 3334 /* movgu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5296 { 3334 /* movgu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5297 { 3334 /* movgu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5298 { 3334 /* movgu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5299 { 3334 /* movgu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5300 { 3334 /* movgu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5301 { 3334 /* movgu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5302 { 3334 /* movgu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5303 { 3340 /* movl */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5304 { 3340 /* movl */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5305 { 3340 /* movl */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5306 { 3340 /* movl */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5307 { 3340 /* movl */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5308 { 3340 /* movl */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5309 { 3340 /* movl */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5310 { 3340 /* movl */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5311 { 3340 /* movl */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5312 { 3340 /* movl */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5313 { 3345 /* movle */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5314 { 3345 /* movle */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5315 { 3345 /* movle */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5316 { 3345 /* movle */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5317 { 3345 /* movle */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5318 { 3345 /* movle */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5319 { 3345 /* movle */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5320 { 3345 /* movle */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5321 { 3345 /* movle */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5322 { 3345 /* movle */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5323 { 3351 /* movleu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5324 { 3351 /* movleu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5325 { 3351 /* movleu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5326 { 3351 /* movleu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5327 { 3351 /* movleu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5328 { 3351 /* movleu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5329 { 3351 /* movleu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5330 { 3351 /* movleu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5331 { 3358 /* movlg */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5332 { 3358 /* movlg */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5333 { 3364 /* movlt */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5334 { 3364 /* movlt */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5335 { 3364 /* movlt */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5336 { 3364 /* movlt */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5337 { 3364 /* movlt */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5338 { 3364 /* movlt */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5339 { 3364 /* movlt */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5340 { 3364 /* movlt */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5341 { 3370 /* movlu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5342 { 3370 /* movlu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5343 { 3370 /* movlu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5344 { 3370 /* movlu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5345 { 3370 /* movlu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5346 { 3370 /* movlu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5347 { 3370 /* movlu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5348 { 3370 /* movlu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5349 { 3376 /* movn */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5350 { 3376 /* movn */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5351 { 3376 /* movn */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5352 { 3376 /* movn */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5353 { 3376 /* movn */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5354 { 3376 /* movn */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5355 { 3376 /* movn */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5356 { 3376 /* movn */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5357 { 3376 /* movn */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5358 { 3376 /* movn */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5359 { 3381 /* movne */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5360 { 3381 /* movne */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5361 { 3381 /* movne */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5362 { 3381 /* movne */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5363 { 3381 /* movne */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5364 { 3381 /* movne */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5365 { 3381 /* movne */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5366 { 3381 /* movne */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5367 { 3381 /* movne */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5368 { 3381 /* movne */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5369 { 3387 /* movneg */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5370 { 3387 /* movneg */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5371 { 3387 /* movneg */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5372 { 3387 /* movneg */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5373 { 3387 /* movneg */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5374 { 3387 /* movneg */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5375 { 3387 /* movneg */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5376 { 3387 /* movneg */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5377 { 3394 /* movnz */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5378 { 3394 /* movnz */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5379 { 3394 /* movnz */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5380 { 3394 /* movnz */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5381 { 3394 /* movnz */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5382 { 3394 /* movnz */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5383 { 3394 /* movnz */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5384 { 3394 /* movnz */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5385 { 3394 /* movnz */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5386 { 3394 /* movnz */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5387 { 3400 /* movo */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5388 { 3400 /* movo */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5389 { 3405 /* movpos */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5390 { 3405 /* movpos */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5391 { 3405 /* movpos */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5392 { 3405 /* movpos */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5393 { 3405 /* movpos */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5394 { 3405 /* movpos */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5395 { 3405 /* movpos */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5396 { 3405 /* movpos */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5397 { 3412 /* movr */, SP::MOVRrr, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5398 { 3412 /* movr */, SP::MOVRri, Convert__Reg1_3__Reg1_1__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5399 { 3417 /* movre */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5400 { 3417 /* movre */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5401 { 3423 /* movrgez */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5402 { 3423 /* movrgez */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5403 { 3431 /* movrgz */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5404 { 3431 /* movrgz */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5405 { 3438 /* movrlez */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5406 { 3438 /* movrlez */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5407 { 3446 /* movrlz */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5408 { 3446 /* movrlz */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5409 { 3453 /* movrne */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5410 { 3453 /* movrne */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5411 { 3460 /* movrnz */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5412 { 3460 /* movrnz */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5413 { 3467 /* movrz */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5414 { 3467 /* movrz */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5415 { 3473 /* movstosw */, SP::MOVSTOSW, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_FPRegs, MCK_IntRegs }, },
5416 { 3482 /* movstouw */, SP::MOVSTOUW, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_FPRegs, MCK_IntRegs }, },
5417 { 3491 /* movu */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5418 { 3491 /* movu */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5419 { 3496 /* movue */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5420 { 3496 /* movue */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5421 { 3502 /* movug */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5422 { 3502 /* movug */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5423 { 3508 /* movuge */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5424 { 3508 /* movuge */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5425 { 3515 /* movul */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5426 { 3515 /* movul */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5427 { 3521 /* movule */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5428 { 3521 /* movule */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5429 { 3528 /* movvc */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5430 { 3528 /* movvc */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5431 { 3528 /* movvc */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5432 { 3528 /* movvc */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5433 { 3528 /* movvc */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5434 { 3528 /* movvc */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5435 { 3528 /* movvc */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5436 { 3528 /* movvc */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5437 { 3534 /* movvs */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5438 { 3534 /* movvs */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5439 { 3534 /* movvs */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5440 { 3534 /* movvs */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5441 { 3534 /* movvs */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5442 { 3534 /* movvs */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5443 { 3534 /* movvs */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5444 { 3534 /* movvs */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5445 { 3540 /* movwtos */, SP::MOVWTOS, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs, MCK_FPRegs }, },
5446 { 3548 /* movxtod */, SP::MOVXTOD, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs, MCK_DFPRegs }, },
5447 { 3556 /* movz */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5448 { 3556 /* movz */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK_IntRegs }, },
5449 { 3556 /* movz */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is32Bit_HasV9, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5450 { 3556 /* movz */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_ncc, MCK_Imm, MCK_IntRegs }, },
5451 { 3556 /* movz */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
5452 { 3556 /* movz */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
5453 { 3556 /* movz */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
5454 { 3556 /* movz */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
5455 { 3556 /* movz */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
5456 { 3556 /* movz */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
5457 { 3561 /* mpmul */, SP::MPMUL, Convert__Imm1_0, AMFBS_HasCrypto, { MCK_Imm }, },
5458 { 3567 /* mulscc */, SP::MULSCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5459 { 3567 /* mulscc */, SP::MULSCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5460 { 3574 /* mulx */, SP::MULXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5461 { 3574 /* mulx */, SP::MULXri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5462 { 3579 /* neg */, SP::SUBrr, Convert__Reg1_0__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs }, },
5463 { 3579 /* neg */, SP::SUBrr, Convert__Reg1_1__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
5464 { 3583 /* nop */, SP::NOP, Convert_NoOperands, AMFBS_None, { }, },
5465 { 3587 /* normalw */, SP::NORMALW, Convert_NoOperands, AMFBS_HasUA2005, { }, },
5466 { 3595 /* not */, SP::XNORrr, Convert__Reg1_0__Reg1_0__regG0, AMFBS_None, { MCK_IntRegs }, },
5467 { 3595 /* not */, SP::XNORrr, Convert__Reg1_1__Reg1_0__regG0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
5468 { 3599 /* or */, SP::ORrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5469 { 3599 /* or */, SP::ORri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5470 { 3599 /* or */, SP::ORri, Convert__Reg1_2__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK_IntRegs }, },
5471 { 3602 /* orcc */, SP::ORCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5472 { 3602 /* orcc */, SP::ORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5473 { 3607 /* orn */, SP::ORNrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5474 { 3607 /* orn */, SP::ORNri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5475 { 3611 /* orncc */, SP::ORNCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5476 { 3611 /* orncc */, SP::ORNCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5477 { 3617 /* otherw */, SP::OTHERW, Convert_NoOperands, AMFBS_HasUA2005, { }, },
5478 { 3624 /* pause */, SP::WRASRrr, Convert__regASR27__regG0__Reg1_0, AMFBS_HasOSA2011, { MCK_IntRegs }, },
5479 { 3624 /* pause */, SP::WRASRri, Convert__regASR27__regG0__Imm1_0, AMFBS_HasOSA2011, { MCK_Imm }, },
5480 { 3630 /* pdist */, SP::PDIST, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
5481 { 3636 /* pdistn */, SP::PDISTN, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
5482 { 3643 /* popc */, SP::POPCrr, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_IntRegs, MCK_IntRegs }, },
5483 { 3648 /* prefetch */, SP::PREFETCHi, Convert__MEMri2_1__PrefetchTag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK_PrefetchTag }, },
5484 { 3648 /* prefetch */, SP::PREFETCHr, Convert__MEMrr2_1__PrefetchTag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_PrefetchTag }, },
5485 { 3657 /* prefetcha */, SP::PREFETCHAi, Convert__MEMri2_1__PrefetchTag1_4, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_PrefetchTag }, },
5486 { 3657 /* prefetcha */, SP::PREFETCHAr, Convert__MEMrr2_1__ASITag1_3__PrefetchTag1_4, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_PrefetchTag }, },
5487 { 3667 /* pwr */, SP::PWRPSRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_PSR }, },
5488 { 3667 /* pwr */, SP::PWRPSRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_PSR }, },
5489 { 3667 /* pwr */, SP::PWRPSRrr, Convert__Reg1_0__Reg1_1, AMFBS_HasPWRPSR, { MCK_IntRegs, MCK_IntRegs, MCK_PSR }, },
5490 { 3667 /* pwr */, SP::PWRPSRri, Convert__Reg1_0__Imm1_1, AMFBS_HasPWRPSR, { MCK_IntRegs, MCK_Imm, MCK_PSR }, },
5491 { 3671 /* rd */, SP::RDPSR, Convert__Reg1_1, AMFBS_None, { MCK_PSR, MCK_IntRegs }, },
5492 { 3671 /* rd */, SP::RDTBR, Convert__Reg1_1, AMFBS_None, { MCK_TBR, MCK_IntRegs }, },
5493 { 3671 /* rd */, SP::RDWIM, Convert__Reg1_1, AMFBS_None, { MCK_WIM, MCK_IntRegs }, },
5494 { 3671 /* rd */, SP::RDASR, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_ASRRegs, MCK_IntRegs }, },
5495 { 3674 /* rdpr */, SP::RDFQ, Convert__Reg1_1, AMFBS_HasV9, { MCK_FQ, MCK_IntRegs }, },
5496 { 3674 /* rdpr */, SP::RDPR, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_PRRegs, MCK_IntRegs }, },
5497 { 3679 /* restore */, SP::RESTORErr, Convert__regG0__regG0__regG0, AMFBS_None, { }, },
5498 { 3679 /* restore */, SP::RESTORErr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5499 { 3679 /* restore */, SP::RESTOREri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5500 { 3687 /* restored */, SP::RESTORED, Convert_NoOperands, AMFBS_HasV9, { }, },
5501 { 3696 /* ret */, SP::RET, Convert__imm_95_8, AMFBS_None, { }, },
5502 { 3700 /* retl */, SP::RETL, Convert__imm_95_8, AMFBS_None, { }, },
5503 { 3705 /* retry */, SP::RETRY, Convert_NoOperands, AMFBS_HasV9, { }, },
5504 { 3711 /* rett */, SP::RETTri, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, },
5505 { 3711 /* rett */, SP::RETTrr, Convert__MEMrr2_0, AMFBS_None, { MCK_MEMrr }, },
5506 { 3716 /* save */, SP::SAVErr, Convert__regG0__regG0__regG0, AMFBS_None, { }, },
5507 { 3716 /* save */, SP::SAVErr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5508 { 3716 /* save */, SP::SAVEri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5509 { 3721 /* saved */, SP::SAVED, Convert_NoOperands, AMFBS_HasV9, { }, },
5510 { 3727 /* sdiv */, SP::SDIVrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5511 { 3727 /* sdiv */, SP::SDIVri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5512 { 3732 /* sdivcc */, SP::SDIVCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5513 { 3732 /* sdivcc */, SP::SDIVCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5514 { 3739 /* sdivx */, SP::SDIVXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5515 { 3739 /* sdivx */, SP::SDIVXri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5516 { 3745 /* set */, SP::SET, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
5517 { 3749 /* sethi */, SP::SETHIi, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
5518 { 3755 /* setsw */, SP::SETSW, Convert__Reg1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_IntRegs }, },
5519 { 3761 /* setx */, SP::SETX, Convert__Reg1_2__Imm1_0__Reg1_1, AMFBS_Is64Bit_HasV9, { MCK_Imm, MCK_IntRegs, MCK_IntRegs }, },
5520 { 3766 /* sha1 */, SP::SHA1, Convert_NoOperands, AMFBS_HasCrypto, { }, },
5521 { 3771 /* sha256 */, SP::SHA256, Convert_NoOperands, AMFBS_HasCrypto, { }, },
5522 { 3778 /* sha512 */, SP::SHA512, Convert_NoOperands, AMFBS_HasCrypto, { }, },
5523 { 3785 /* shutdown */, SP::SHUTDOWN, Convert_NoOperands, AMFBS_HasVIS, { }, },
5524 { 3794 /* siam */, SP::SIAM, Convert__Imm1_0, AMFBS_HasVIS2, { MCK_Imm }, },
5525 { 3799 /* signx */, SP::SRArr, Convert__Reg1_0__Reg1_0__regG0, AMFBS_HasV9, { MCK_IntRegs }, },
5526 { 3799 /* signx */, SP::SRArr, Convert__Reg1_1__Reg1_0__regG0, AMFBS_HasV9, { MCK_IntRegs, MCK_IntRegs }, },
5527 { 3805 /* sir */, SP::SIR, Convert__imm_95_0, AMFBS_None, { }, },
5528 { 3805 /* sir */, SP::SIR, Convert__Imm1_0, AMFBS_HasV9, { MCK_Imm }, },
5529 { 3809 /* sll */, SP::SLLrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5530 { 3809 /* sll */, SP::SLLri, Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1, AMFBS_None, { MCK_IntRegs, MCK_ShiftAmtImm5, MCK_IntRegs }, },
5531 { 3813 /* sllx */, SP::SLLXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5532 { 3813 /* sllx */, SP::SLLXri, Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_ShiftAmtImm6, MCK_IntRegs }, },
5533 { 3818 /* smac */, SP::SMACrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5534 { 3818 /* smac */, SP::SMACri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5535 { 3823 /* smul */, SP::SMULrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5536 { 3823 /* smul */, SP::SMULri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5537 { 3828 /* smulcc */, SP::SMULCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5538 { 3828 /* smulcc */, SP::SMULCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5539 { 3835 /* sra */, SP::SRArr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5540 { 3835 /* sra */, SP::SRAri, Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1, AMFBS_None, { MCK_IntRegs, MCK_ShiftAmtImm5, MCK_IntRegs }, },
5541 { 3839 /* srax */, SP::SRAXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5542 { 3839 /* srax */, SP::SRAXri, Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_ShiftAmtImm6, MCK_IntRegs }, },
5543 { 3844 /* srl */, SP::SRLrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5544 { 3844 /* srl */, SP::SRLri, Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1, AMFBS_None, { MCK_IntRegs, MCK_ShiftAmtImm5, MCK_IntRegs }, },
5545 { 3848 /* srlx */, SP::SRLXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5546 { 3848 /* srlx */, SP::SRLXri, Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_ShiftAmtImm6, MCK_IntRegs }, },
5547 { 3853 /* st */, SP::STCSRri, Convert__MEMri2_2, AMFBS_None, { MCK_CPSR, MCK__91_, MCK_MEMri, MCK__93_ }, },
5548 { 3853 /* st */, SP::STCSRrr, Convert__MEMrr2_2, AMFBS_None, { MCK_CPSR, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5549 { 3853 /* st */, SP::STFSRri, Convert__MEMri2_2, AMFBS_None, { MCK_FSR, MCK__91_, MCK_MEMri, MCK__93_ }, },
5550 { 3853 /* st */, SP::STFSRrr, Convert__MEMrr2_2, AMFBS_None, { MCK_FSR, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5551 { 3853 /* st */, SP::STCri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_CoprocRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
5552 { 3853 /* st */, SP::STCrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_CoprocRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5553 { 3853 /* st */, SP::STFri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
5554 { 3853 /* st */, SP::STFrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5555 { 3853 /* st */, SP::STri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
5556 { 3853 /* st */, SP::STrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5557 { 3856 /* sta */, SP::STFAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_FPRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
5558 { 3856 /* sta */, SP::STFArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_HasV9, { MCK_FPRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
5559 { 3856 /* sta */, SP::STAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
5560 { 3856 /* sta */, SP::STArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
5561 { 3860 /* stb */, SP::STBri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
5562 { 3860 /* stb */, SP::STBrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5563 { 3864 /* stba */, SP::STBAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
5564 { 3864 /* stba */, SP::STBArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
5565 { 3869 /* stbar */, SP::STBAR, Convert_NoOperands, AMFBS_None, { }, },
5566 { 3875 /* std */, SP::STDCQri, Convert__MEMri2_2, AMFBS_None, { MCK_CPQ, MCK__91_, MCK_MEMri, MCK__93_ }, },
5567 { 3875 /* std */, SP::STDCQrr, Convert__MEMrr2_2, AMFBS_None, { MCK_CPQ, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5568 { 3875 /* std */, SP::STDFQri, Convert__MEMri2_2, AMFBS_None, { MCK_FQ, MCK__91_, MCK_MEMri, MCK__93_ }, },
5569 { 3875 /* std */, SP::STDFQrr, Convert__MEMrr2_2, AMFBS_None, { MCK_FQ, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5570 { 3875 /* std */, SP::STDCri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_CoprocPair, MCK__91_, MCK_MEMri, MCK__93_ }, },
5571 { 3875 /* std */, SP::STDCrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_CoprocPair, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5572 { 3875 /* std */, SP::STDri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_IntPair, MCK__91_, MCK_MEMri, MCK__93_ }, },
5573 { 3875 /* std */, SP::STDrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_IntPair, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5574 { 3875 /* std */, SP::STDFri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
5575 { 3875 /* std */, SP::STDFrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5576 { 3879 /* stda */, SP::STDAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_IntPair, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
5577 { 3879 /* stda */, SP::STDArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_None, { MCK_IntPair, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
5578 { 3879 /* stda */, SP::STDFAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_DFPRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
5579 { 3879 /* stda */, SP::STDFArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_HasV9, { MCK_DFPRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
5580 { 3884 /* sth */, SP::STHri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
5581 { 3884 /* sth */, SP::STHrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5582 { 3888 /* stha */, SP::STHAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
5583 { 3888 /* stha */, SP::STHArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
5584 { 3893 /* stq */, SP::STQFri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
5585 { 3893 /* stq */, SP::STQFrr, Convert__MEMrr2_2__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5586 { 3897 /* stqa */, SP::STQFAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
5587 { 3897 /* stqa */, SP::STQFArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
5588 { 3902 /* stx */, SP::STXFSRri, Convert__MEMri2_2, AMFBS_HasV9, { MCK_FSR, MCK__91_, MCK_MEMri, MCK__93_ }, },
5589 { 3902 /* stx */, SP::STXFSRrr, Convert__MEMrr2_2, AMFBS_HasV9, { MCK_FSR, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5590 { 3902 /* stx */, SP::STXri, Convert__MEMri2_2__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
5591 { 3902 /* stx */, SP::STXrr, Convert__MEMrr2_2__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
5592 { 3906 /* stxa */, SP::STXAri, Convert__MEMri2_2__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
5593 { 3906 /* stxa */, SP::STXArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_Is64Bit, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
5594 { 3911 /* sub */, SP::SUBrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5595 { 3911 /* sub */, SP::SUBri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5596 { 3915 /* subcc */, SP::SUBCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5597 { 3915 /* subcc */, SP::SUBCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5598 { 3921 /* subx */, SP::SUBCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5599 { 3921 /* subx */, SP::SUBCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5600 { 3926 /* subxcc */, SP::SUBErr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5601 { 3926 /* subxcc */, SP::SUBEri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5602 { 3933 /* swap */, SP::SWAPri, Convert__Reg1_3__MEMri2_1__Tie0_1_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
5603 { 3933 /* swap */, SP::SWAPrr, Convert__Reg1_3__MEMrr2_1__Tie0_1_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
5604 { 3938 /* swapa */, SP::SWAPAri, Convert__Reg1_4__MEMri2_1__Tie0_1_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
5605 { 3938 /* swapa */, SP::SWAPArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3__Tie0_1_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
5606 { 3944 /* t */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_8, AMFBS_None, { MCK_IntRegs }, },
5607 { 3944 /* t */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
5608 { 3944 /* t */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5609 { 3944 /* t */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5610 { 3944 /* t */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5611 { 3944 /* t */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5612 { 3944 /* t */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5613 { 3944 /* t */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5614 { 3944 /* t */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5615 { 3944 /* t */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5616 { 3944 /* t */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_8, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5617 { 3944 /* t */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_8, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5618 { 3944 /* t */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5619 { 3944 /* t */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5620 { 3944 /* t */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5621 { 3944 /* t */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5622 { 3944 /* t */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5623 { 3944 /* t */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5624 { 3944 /* t */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5625 { 3944 /* t */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5626 { 3944 /* t */, SP::TRAPrr, Convert__Reg1_1__Reg1_3__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5627 { 3944 /* t */, SP::TRAPri, Convert__Reg1_1__Imm1_3__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5628 { 3944 /* t */, SP::TXCCrr, Convert__Reg1_2__Reg1_4__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5629 { 3944 /* t */, SP::TXCCri, Convert__Reg1_2__Imm1_4__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5630 { 3944 /* t */, SP::TICCrr, Convert__Reg1_2__Reg1_4__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5631 { 3944 /* t */, SP::TICCri, Convert__Reg1_2__Imm1_4__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5632 { 3946 /* ta */, SP::TA1, Convert_NoOperands, AMFBS_None, { MCK_1 }, },
5633 { 3946 /* ta */, SP::TA3, Convert_NoOperands, AMFBS_None, { MCK_3 }, },
5634 { 3946 /* ta */, SP::TA5, Convert_NoOperands, AMFBS_None, { MCK_5 }, },
5635 { 3946 /* ta */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_8, AMFBS_None, { MCK_IntRegs }, },
5636 { 3946 /* ta */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
5637 { 3946 /* ta */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5638 { 3946 /* ta */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5639 { 3946 /* ta */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5640 { 3946 /* ta */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5641 { 3946 /* ta */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5642 { 3946 /* ta */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5643 { 3946 /* ta */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5644 { 3946 /* ta */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5645 { 3946 /* ta */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_8, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5646 { 3946 /* ta */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_8, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5647 { 3946 /* ta */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5648 { 3946 /* ta */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5649 { 3946 /* ta */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5650 { 3946 /* ta */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5651 { 3946 /* ta */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5652 { 3946 /* ta */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5653 { 3946 /* ta */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5654 { 3946 /* ta */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5655 { 3949 /* taddcc */, SP::TADDCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5656 { 3949 /* taddcc */, SP::TADDCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5657 { 3956 /* taddcctv */, SP::TADDCCTVrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5658 { 3956 /* taddcctv */, SP::TADDCCTVri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5659 { 3965 /* tcc */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_13, AMFBS_None, { MCK_IntRegs }, },
5660 { 3965 /* tcc */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
5661 { 3965 /* tcc */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5662 { 3965 /* tcc */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5663 { 3965 /* tcc */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5664 { 3965 /* tcc */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5665 { 3965 /* tcc */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5666 { 3965 /* tcc */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5667 { 3965 /* tcc */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5668 { 3965 /* tcc */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5669 { 3965 /* tcc */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_13, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5670 { 3965 /* tcc */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_13, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5671 { 3965 /* tcc */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5672 { 3965 /* tcc */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5673 { 3965 /* tcc */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5674 { 3965 /* tcc */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5675 { 3965 /* tcc */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5676 { 3965 /* tcc */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5677 { 3965 /* tcc */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5678 { 3965 /* tcc */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5679 { 3969 /* tcs */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_5, AMFBS_None, { MCK_IntRegs }, },
5680 { 3969 /* tcs */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
5681 { 3969 /* tcs */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5682 { 3969 /* tcs */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5683 { 3969 /* tcs */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5684 { 3969 /* tcs */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5685 { 3969 /* tcs */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5686 { 3969 /* tcs */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5687 { 3969 /* tcs */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5688 { 3969 /* tcs */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5689 { 3969 /* tcs */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_5, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5690 { 3969 /* tcs */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_5, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5691 { 3969 /* tcs */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5692 { 3969 /* tcs */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5693 { 3969 /* tcs */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5694 { 3969 /* tcs */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5695 { 3969 /* tcs */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5696 { 3969 /* tcs */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5697 { 3969 /* tcs */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5698 { 3969 /* tcs */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5699 { 3973 /* te */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
5700 { 3973 /* te */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
5701 { 3973 /* te */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5702 { 3973 /* te */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5703 { 3973 /* te */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5704 { 3973 /* te */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5705 { 3973 /* te */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5706 { 3973 /* te */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5707 { 3973 /* te */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5708 { 3973 /* te */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5709 { 3973 /* te */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5710 { 3973 /* te */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5711 { 3973 /* te */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5712 { 3973 /* te */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5713 { 3973 /* te */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5714 { 3973 /* te */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5715 { 3973 /* te */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5716 { 3973 /* te */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5717 { 3973 /* te */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5718 { 3973 /* te */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5719 { 3976 /* teq */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
5720 { 3976 /* teq */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
5721 { 3976 /* teq */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5722 { 3976 /* teq */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5723 { 3976 /* teq */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5724 { 3976 /* teq */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5725 { 3976 /* teq */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5726 { 3976 /* teq */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5727 { 3976 /* teq */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5728 { 3976 /* teq */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5729 { 3976 /* teq */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5730 { 3976 /* teq */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5731 { 3976 /* teq */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5732 { 3976 /* teq */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5733 { 3976 /* teq */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5734 { 3976 /* teq */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5735 { 3976 /* teq */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5736 { 3976 /* teq */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5737 { 3976 /* teq */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5738 { 3976 /* teq */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5739 { 3980 /* tg */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_10, AMFBS_None, { MCK_IntRegs }, },
5740 { 3980 /* tg */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
5741 { 3980 /* tg */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5742 { 3980 /* tg */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5743 { 3980 /* tg */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5744 { 3980 /* tg */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5745 { 3980 /* tg */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5746 { 3980 /* tg */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5747 { 3980 /* tg */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5748 { 3980 /* tg */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5749 { 3980 /* tg */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_10, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5750 { 3980 /* tg */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_10, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5751 { 3980 /* tg */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5752 { 3980 /* tg */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5753 { 3980 /* tg */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5754 { 3980 /* tg */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5755 { 3980 /* tg */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5756 { 3980 /* tg */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5757 { 3980 /* tg */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5758 { 3980 /* tg */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5759 { 3983 /* tge */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_11, AMFBS_None, { MCK_IntRegs }, },
5760 { 3983 /* tge */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_11, AMFBS_None, { MCK_Imm }, },
5761 { 3983 /* tge */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5762 { 3983 /* tge */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_11, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5763 { 3983 /* tge */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5764 { 3983 /* tge */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_11, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5765 { 3983 /* tge */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_11, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5766 { 3983 /* tge */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_11, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5767 { 3983 /* tge */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5768 { 3983 /* tge */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5769 { 3983 /* tge */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_11, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5770 { 3983 /* tge */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_11, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5771 { 3983 /* tge */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5772 { 3983 /* tge */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_11, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5773 { 3983 /* tge */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_11, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5774 { 3983 /* tge */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_11, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5775 { 3983 /* tge */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_11, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5776 { 3983 /* tge */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_11, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5777 { 3983 /* tge */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5778 { 3983 /* tge */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5779 { 3987 /* tgeu */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_13, AMFBS_None, { MCK_IntRegs }, },
5780 { 3987 /* tgeu */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
5781 { 3987 /* tgeu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5782 { 3987 /* tgeu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5783 { 3987 /* tgeu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5784 { 3987 /* tgeu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5785 { 3987 /* tgeu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5786 { 3987 /* tgeu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5787 { 3987 /* tgeu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5788 { 3987 /* tgeu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5789 { 3987 /* tgeu */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_13, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5790 { 3987 /* tgeu */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_13, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5791 { 3987 /* tgeu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5792 { 3987 /* tgeu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5793 { 3987 /* tgeu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5794 { 3987 /* tgeu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5795 { 3987 /* tgeu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5796 { 3987 /* tgeu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5797 { 3987 /* tgeu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5798 { 3987 /* tgeu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5799 { 3992 /* tgt */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_10, AMFBS_None, { MCK_IntRegs }, },
5800 { 3992 /* tgt */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
5801 { 3992 /* tgt */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5802 { 3992 /* tgt */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5803 { 3992 /* tgt */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5804 { 3992 /* tgt */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5805 { 3992 /* tgt */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5806 { 3992 /* tgt */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5807 { 3992 /* tgt */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5808 { 3992 /* tgt */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5809 { 3992 /* tgt */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_10, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5810 { 3992 /* tgt */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_10, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5811 { 3992 /* tgt */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5812 { 3992 /* tgt */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5813 { 3992 /* tgt */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5814 { 3992 /* tgt */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5815 { 3992 /* tgt */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5816 { 3992 /* tgt */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5817 { 3992 /* tgt */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5818 { 3992 /* tgt */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5819 { 3996 /* tgu */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_12, AMFBS_None, { MCK_IntRegs }, },
5820 { 3996 /* tgu */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_12, AMFBS_None, { MCK_Imm }, },
5821 { 3996 /* tgu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5822 { 3996 /* tgu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_12, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5823 { 3996 /* tgu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5824 { 3996 /* tgu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_12, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5825 { 3996 /* tgu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_12, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5826 { 3996 /* tgu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_12, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5827 { 3996 /* tgu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5828 { 3996 /* tgu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5829 { 3996 /* tgu */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_12, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5830 { 3996 /* tgu */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_12, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5831 { 3996 /* tgu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5832 { 3996 /* tgu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_12, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5833 { 3996 /* tgu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_12, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5834 { 3996 /* tgu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_12, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5835 { 3996 /* tgu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_12, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5836 { 3996 /* tgu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_12, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5837 { 3996 /* tgu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5838 { 3996 /* tgu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5839 { 4000 /* tl */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_3, AMFBS_None, { MCK_IntRegs }, },
5840 { 4000 /* tl */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
5841 { 4000 /* tl */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5842 { 4000 /* tl */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5843 { 4000 /* tl */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5844 { 4000 /* tl */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5845 { 4000 /* tl */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5846 { 4000 /* tl */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5847 { 4000 /* tl */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5848 { 4000 /* tl */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5849 { 4000 /* tl */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_3, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5850 { 4000 /* tl */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_3, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5851 { 4000 /* tl */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5852 { 4000 /* tl */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5853 { 4000 /* tl */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5854 { 4000 /* tl */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5855 { 4000 /* tl */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5856 { 4000 /* tl */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5857 { 4000 /* tl */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5858 { 4000 /* tl */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5859 { 4003 /* tle */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_2, AMFBS_None, { MCK_IntRegs }, },
5860 { 4003 /* tle */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_2, AMFBS_None, { MCK_Imm }, },
5861 { 4003 /* tle */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5862 { 4003 /* tle */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_2, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5863 { 4003 /* tle */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5864 { 4003 /* tle */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_2, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5865 { 4003 /* tle */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_2, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5866 { 4003 /* tle */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_2, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5867 { 4003 /* tle */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5868 { 4003 /* tle */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5869 { 4003 /* tle */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_2, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5870 { 4003 /* tle */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_2, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5871 { 4003 /* tle */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5872 { 4003 /* tle */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_2, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5873 { 4003 /* tle */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_2, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5874 { 4003 /* tle */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_2, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5875 { 4003 /* tle */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_2, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5876 { 4003 /* tle */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_2, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5877 { 4003 /* tle */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5878 { 4003 /* tle */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5879 { 4007 /* tleu */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_4, AMFBS_None, { MCK_IntRegs }, },
5880 { 4007 /* tleu */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_4, AMFBS_None, { MCK_Imm }, },
5881 { 4007 /* tleu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5882 { 4007 /* tleu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_4, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5883 { 4007 /* tleu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5884 { 4007 /* tleu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_4, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5885 { 4007 /* tleu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_4, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5886 { 4007 /* tleu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_4, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5887 { 4007 /* tleu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5888 { 4007 /* tleu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5889 { 4007 /* tleu */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_4, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5890 { 4007 /* tleu */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_4, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5891 { 4007 /* tleu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5892 { 4007 /* tleu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_4, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5893 { 4007 /* tleu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_4, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5894 { 4007 /* tleu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_4, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5895 { 4007 /* tleu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_4, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5896 { 4007 /* tleu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_4, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5897 { 4007 /* tleu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5898 { 4007 /* tleu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5899 { 4012 /* tlt */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_3, AMFBS_None, { MCK_IntRegs }, },
5900 { 4012 /* tlt */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
5901 { 4012 /* tlt */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5902 { 4012 /* tlt */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5903 { 4012 /* tlt */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5904 { 4012 /* tlt */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5905 { 4012 /* tlt */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5906 { 4012 /* tlt */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5907 { 4012 /* tlt */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5908 { 4012 /* tlt */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5909 { 4012 /* tlt */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_3, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5910 { 4012 /* tlt */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_3, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5911 { 4012 /* tlt */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5912 { 4012 /* tlt */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5913 { 4012 /* tlt */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5914 { 4012 /* tlt */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5915 { 4012 /* tlt */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5916 { 4012 /* tlt */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5917 { 4012 /* tlt */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5918 { 4012 /* tlt */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5919 { 4016 /* tlu */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_5, AMFBS_None, { MCK_IntRegs }, },
5920 { 4016 /* tlu */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
5921 { 4016 /* tlu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5922 { 4016 /* tlu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5923 { 4016 /* tlu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5924 { 4016 /* tlu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5925 { 4016 /* tlu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5926 { 4016 /* tlu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5927 { 4016 /* tlu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5928 { 4016 /* tlu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5929 { 4016 /* tlu */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_5, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5930 { 4016 /* tlu */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_5, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5931 { 4016 /* tlu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5932 { 4016 /* tlu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5933 { 4016 /* tlu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5934 { 4016 /* tlu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5935 { 4016 /* tlu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5936 { 4016 /* tlu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5937 { 4016 /* tlu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5938 { 4016 /* tlu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5939 { 4020 /* tn */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_0, AMFBS_None, { MCK_IntRegs }, },
5940 { 4020 /* tn */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_0, AMFBS_None, { MCK_Imm }, },
5941 { 4020 /* tn */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5942 { 4020 /* tn */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_0, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5943 { 4020 /* tn */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5944 { 4020 /* tn */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_0, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5945 { 4020 /* tn */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_0, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5946 { 4020 /* tn */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_0, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5947 { 4020 /* tn */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5948 { 4020 /* tn */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5949 { 4020 /* tn */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5950 { 4020 /* tn */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5951 { 4020 /* tn */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5952 { 4020 /* tn */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_0, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5953 { 4020 /* tn */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_0, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5954 { 4020 /* tn */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_0, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5955 { 4020 /* tn */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_0, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5956 { 4020 /* tn */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_0, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5957 { 4020 /* tn */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5958 { 4020 /* tn */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5959 { 4023 /* tne */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_9, AMFBS_None, { MCK_IntRegs }, },
5960 { 4023 /* tne */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
5961 { 4023 /* tne */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5962 { 4023 /* tne */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5963 { 4023 /* tne */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5964 { 4023 /* tne */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5965 { 4023 /* tne */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5966 { 4023 /* tne */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5967 { 4023 /* tne */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5968 { 4023 /* tne */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5969 { 4023 /* tne */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_9, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5970 { 4023 /* tne */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_9, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5971 { 4023 /* tne */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5972 { 4023 /* tne */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5973 { 4023 /* tne */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5974 { 4023 /* tne */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5975 { 4023 /* tne */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5976 { 4023 /* tne */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5977 { 4023 /* tne */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5978 { 4023 /* tne */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5979 { 4027 /* tneg */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_6, AMFBS_None, { MCK_IntRegs }, },
5980 { 4027 /* tneg */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_6, AMFBS_None, { MCK_Imm }, },
5981 { 4027 /* tneg */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5982 { 4027 /* tneg */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_6, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
5983 { 4027 /* tneg */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
5984 { 4027 /* tneg */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_6, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
5985 { 4027 /* tneg */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_6, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5986 { 4027 /* tneg */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_6, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5987 { 4027 /* tneg */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5988 { 4027 /* tneg */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5989 { 4027 /* tneg */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_6, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5990 { 4027 /* tneg */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_6, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5991 { 4027 /* tneg */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5992 { 4027 /* tneg */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_6, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5993 { 4027 /* tneg */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_6, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5994 { 4027 /* tneg */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_6, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5995 { 4027 /* tneg */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_6, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5996 { 4027 /* tneg */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_6, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5997 { 4027 /* tneg */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5998 { 4027 /* tneg */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5999 { 4032 /* tnz */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_9, AMFBS_None, { MCK_IntRegs }, },
6000 { 4032 /* tnz */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
6001 { 4032 /* tnz */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6002 { 4032 /* tnz */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6003 { 4032 /* tnz */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
6004 { 4032 /* tnz */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
6005 { 4032 /* tnz */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
6006 { 4032 /* tnz */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
6007 { 4032 /* tnz */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
6008 { 4032 /* tnz */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
6009 { 4032 /* tnz */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_9, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6010 { 4032 /* tnz */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_9, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
6011 { 4032 /* tnz */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6012 { 4032 /* tnz */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6013 { 4032 /* tnz */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6014 { 4032 /* tnz */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6015 { 4032 /* tnz */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6016 { 4032 /* tnz */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6017 { 4032 /* tnz */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6018 { 4032 /* tnz */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6019 { 4036 /* tpos */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_14, AMFBS_None, { MCK_IntRegs }, },
6020 { 4036 /* tpos */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_14, AMFBS_None, { MCK_Imm }, },
6021 { 4036 /* tpos */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6022 { 4036 /* tpos */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_14, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6023 { 4036 /* tpos */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
6024 { 4036 /* tpos */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_14, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
6025 { 4036 /* tpos */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_14, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
6026 { 4036 /* tpos */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_14, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
6027 { 4036 /* tpos */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
6028 { 4036 /* tpos */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
6029 { 4036 /* tpos */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_14, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6030 { 4036 /* tpos */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_14, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
6031 { 4036 /* tpos */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6032 { 4036 /* tpos */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_14, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6033 { 4036 /* tpos */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_14, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6034 { 4036 /* tpos */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_14, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6035 { 4036 /* tpos */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_14, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6036 { 4036 /* tpos */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_14, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6037 { 4036 /* tpos */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6038 { 4036 /* tpos */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6039 { 4041 /* tst */, SP::ORCCrr, Convert__regG0__Reg1_0__regG0, AMFBS_None, { MCK_IntRegs }, },
6040 { 4045 /* tsubcc */, SP::TSUBCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6041 { 4045 /* tsubcc */, SP::TSUBCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6042 { 4052 /* tsubcctv */, SP::TSUBCCTVrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6043 { 4052 /* tsubcctv */, SP::TSUBCCTVri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6044 { 4061 /* tvc */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_15, AMFBS_None, { MCK_IntRegs }, },
6045 { 4061 /* tvc */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_15, AMFBS_None, { MCK_Imm }, },
6046 { 4061 /* tvc */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6047 { 4061 /* tvc */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_15, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6048 { 4061 /* tvc */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
6049 { 4061 /* tvc */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_15, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
6050 { 4061 /* tvc */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_15, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
6051 { 4061 /* tvc */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_15, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
6052 { 4061 /* tvc */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
6053 { 4061 /* tvc */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
6054 { 4061 /* tvc */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_15, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6055 { 4061 /* tvc */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_15, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
6056 { 4061 /* tvc */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6057 { 4061 /* tvc */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_15, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6058 { 4061 /* tvc */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_15, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6059 { 4061 /* tvc */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_15, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6060 { 4061 /* tvc */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_15, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6061 { 4061 /* tvc */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_15, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6062 { 4061 /* tvc */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6063 { 4061 /* tvc */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6064 { 4065 /* tvs */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_7, AMFBS_None, { MCK_IntRegs }, },
6065 { 4065 /* tvs */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_7, AMFBS_None, { MCK_Imm }, },
6066 { 4065 /* tvs */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6067 { 4065 /* tvs */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_7, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6068 { 4065 /* tvs */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
6069 { 4065 /* tvs */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_7, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
6070 { 4065 /* tvs */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_7, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
6071 { 4065 /* tvs */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_7, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
6072 { 4065 /* tvs */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
6073 { 4065 /* tvs */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
6074 { 4065 /* tvs */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_7, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6075 { 4065 /* tvs */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_7, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
6076 { 4065 /* tvs */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6077 { 4065 /* tvs */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_7, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6078 { 4065 /* tvs */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_7, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6079 { 4065 /* tvs */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_7, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6080 { 4065 /* tvs */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_7, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6081 { 4065 /* tvs */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_7, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6082 { 4065 /* tvs */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6083 { 4065 /* tvs */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6084 { 4069 /* tz */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
6085 { 4069 /* tz */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
6086 { 4069 /* tz */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6087 { 4069 /* tz */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs }, },
6088 { 4069 /* tz */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_Imm }, },
6089 { 4069 /* tz */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_Imm }, },
6090 { 4069 /* tz */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
6091 { 4069 /* tz */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
6092 { 4069 /* tz */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
6093 { 4069 /* tz */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
6094 { 4069 /* tz */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6095 { 4069 /* tz */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
6096 { 4069 /* tz */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6097 { 4069 /* tz */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6098 { 4069 /* tz */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9_Is32Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6099 { 4069 /* tz */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9_Is64Bit, { MCK__PCT_ncc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6100 { 4069 /* tz */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6101 { 4069 /* tz */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6102 { 4069 /* tz */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
6103 { 4069 /* tz */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
6104 { 4072 /* udiv */, SP::UDIVrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6105 { 4072 /* udiv */, SP::UDIVri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6106 { 4077 /* udivcc */, SP::UDIVCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6107 { 4077 /* udivcc */, SP::UDIVCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6108 { 4084 /* udivx */, SP::UDIVXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6109 { 4084 /* udivx */, SP::UDIVXri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6110 { 4090 /* umac */, SP::UMACrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6111 { 4090 /* umac */, SP::UMACri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6112 { 4095 /* umul */, SP::UMULrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6113 { 4095 /* umul */, SP::UMULri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6114 { 4100 /* umulcc */, SP::UMULCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6115 { 4100 /* umulcc */, SP::UMULCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6116 { 4107 /* umulxhi */, SP::UMULXHI, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6117 { 4115 /* unimp */, SP::UNIMP, Convert__imm_95_0, AMFBS_None, { }, },
6118 { 4115 /* unimp */, SP::UNIMP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
6119 { 4121 /* wr */, SP::WRPSRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_PSR }, },
6120 { 4121 /* wr */, SP::WRTBRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_TBR }, },
6121 { 4121 /* wr */, SP::WRWIMrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_WIM }, },
6122 { 4121 /* wr */, SP::WRASRrr, Convert__Reg1_1__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_ASRRegs }, },
6123 { 4121 /* wr */, SP::WRPSRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_PSR }, },
6124 { 4121 /* wr */, SP::WRTBRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_TBR }, },
6125 { 4121 /* wr */, SP::WRWIMri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_WIM }, },
6126 { 4121 /* wr */, SP::WRASRri, Convert__Reg1_1__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_ASRRegs }, },
6127 { 4121 /* wr */, SP::WRPSRrr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_PSR }, },
6128 { 4121 /* wr */, SP::WRTBRrr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_TBR }, },
6129 { 4121 /* wr */, SP::WRWIMrr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_WIM }, },
6130 { 4121 /* wr */, SP::WRASRrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_ASRRegs }, },
6131 { 4121 /* wr */, SP::WRPSRri, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_PSR }, },
6132 { 4121 /* wr */, SP::WRTBRri, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_TBR }, },
6133 { 4121 /* wr */, SP::WRWIMri, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_WIM }, },
6134 { 4121 /* wr */, SP::WRASRri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_ASRRegs }, },
6135 { 4124 /* wrpr */, SP::WRPRrr, Convert__Reg1_1__Reg1_0__regG0, AMFBS_HasV9, { MCK_IntRegs, MCK_PRRegs }, },
6136 { 4124 /* wrpr */, SP::WRPRri, Convert__Reg1_1__regG0__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_PRRegs }, },
6137 { 4124 /* wrpr */, SP::WRPRrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasV9, { MCK_IntRegs, MCK_IntRegs, MCK_PRRegs }, },
6138 { 4124 /* wrpr */, SP::WRPRri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_HasV9, { MCK_IntRegs, MCK_Imm, MCK_PRRegs }, },
6139 { 4129 /* xmulx */, SP::XMULX, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6140 { 4135 /* xmulxhi */, SP::XMULXHI, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6141 { 4143 /* xnor */, SP::XNORrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6142 { 4143 /* xnor */, SP::XNORri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6143 { 4148 /* xnorcc */, SP::XNORCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6144 { 4148 /* xnorcc */, SP::XNORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6145 { 4155 /* xor */, SP::XORrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6146 { 4155 /* xor */, SP::XORri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6147 { 4159 /* xorcc */, SP::XORCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
6148 { 4159 /* xorcc */, SP::XORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
6149};
6150
6151#include "llvm/Support/Debug.h"
6152#include "llvm/Support/Format.h"
6153
6154unsigned SparcAsmParser::
6155MatchInstructionImpl(const OperandVector &Operands,
6156 MCInst &Inst,
6157 uint64_t &ErrorInfo,
6158 FeatureBitset &MissingFeatures,
6159 bool matchingInlineAsm, unsigned VariantID) {
6160 // Eliminate obvious mismatches.
6161 if (Operands.size() > 7) {
6162 ErrorInfo = 7;
6163 return Match_InvalidOperand;
6164 }
6165
6166 // Get the current feature set.
6167 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
6168
6169 // Get the instruction mnemonic, which is the first token.
6170 StringRef Mnemonic = ((SparcOperand &)*Operands[0]).getToken();
6171
6172 // Process all MnemonicAliases to remap the mnemonic.
6173 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
6174
6175 // Some state to try to produce better error messages.
6176 bool HadMatchOtherThanFeatures = false;
6177 bool HadMatchOtherThanPredicate = false;
6178 unsigned RetCode = Match_InvalidOperand;
6179 MissingFeatures.set();
6180 // Set ErrorInfo to the operand that mismatches if it is
6181 // wrong for all instances of the instruction.
6182 ErrorInfo = ~0ULL;
6183 // Find the appropriate table for this asm variant.
6184 const MatchEntry *Start, *End;
6185 switch (VariantID) {
6186 default: llvm_unreachable("invalid variant!");
6187 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
6188 }
6189 // Search the table.
6190 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
6191
6192 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
6193 std::distance(MnemonicRange.first, MnemonicRange.second) <<
6194 " encodings with mnemonic '" << Mnemonic << "'\n");
6195
6196 // Return a more specific error code if no mnemonics match.
6197 if (MnemonicRange.first == MnemonicRange.second)
6198 return Match_MnemonicFail;
6199
6200 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
6201 it != ie; ++it) {
6202 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
6203 bool HasRequiredFeatures =
6204 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
6205 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
6206 << MII.getName(it->Opcode) << "\n");
6207 // equal_range guarantees that instruction mnemonic matches.
6208 assert(Mnemonic == it->getMnemonic());
6209 bool OperandsValid = true;
6210 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 6; ++FormalIdx) {
6211 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
6212 DEBUG_WITH_TYPE("asm-matcher",
6213 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
6214 << " against actual operand at index " << ActualIdx);
6215 if (ActualIdx < Operands.size())
6216 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
6217 Operands[ActualIdx]->print(dbgs(), *getContext().getAsmInfo()); dbgs() << "): ");
6218 else
6219 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
6220 if (ActualIdx >= Operands.size()) {
6221 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
6222 if (Formal == InvalidMatchClass) {
6223 break;
6224 }
6225 if (isSubclass(Formal, OptionalMatchClass)) {
6226 continue;
6227 }
6228 OperandsValid = false;
6229 ErrorInfo = ActualIdx;
6230 break;
6231 }
6232 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
6233 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
6234 if (Diag == Match_Success) {
6235 DEBUG_WITH_TYPE("asm-matcher",
6236 dbgs() << "match success using generic matcher\n");
6237 ++ActualIdx;
6238 continue;
6239 }
6240 // If the generic handler indicates an invalid operand
6241 // failure, check for a special case.
6242 if (Diag != Match_Success) {
6243 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
6244 if (TargetDiag == Match_Success) {
6245 DEBUG_WITH_TYPE("asm-matcher",
6246 dbgs() << "match success using target matcher\n");
6247 ++ActualIdx;
6248 continue;
6249 }
6250 // If the target matcher returned a specific error code use
6251 // that, else use the one from the generic matcher.
6252 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
6253 Diag = TargetDiag;
6254 }
6255 // If current formal operand wasn't matched and it is optional
6256 // then try to match next formal operand
6257 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
6258 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
6259 continue;
6260 }
6261 // If this operand is broken for all of the instances of this
6262 // mnemonic, keep track of it so we can report loc info.
6263 // If we already had a match that only failed due to a
6264 // target predicate, that diagnostic is preferred.
6265 if (!HadMatchOtherThanPredicate &&
6266 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
6267 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
6268 RetCode = Diag;
6269 ErrorInfo = ActualIdx;
6270 }
6271 // Otherwise, just reject this instance of the mnemonic.
6272 OperandsValid = false;
6273 break;
6274 }
6275
6276 if (!OperandsValid) {
6277 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
6278 "operand mismatches, ignoring "
6279 "this opcode\n");
6280 continue;
6281 }
6282 if (!HasRequiredFeatures) {
6283 HadMatchOtherThanFeatures = true;
6284 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
6285 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
6286 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
6287 if (NewMissingFeatures[I])
6288 dbgs() << ' ' << I;
6289 dbgs() << "\n");
6290 if (NewMissingFeatures.count() <=
6291 MissingFeatures.count())
6292 MissingFeatures = NewMissingFeatures;
6293 continue;
6294 }
6295
6296 Inst.clear();
6297
6298 Inst.setOpcode(it->Opcode);
6299 // We have a potential match but have not rendered the operands.
6300 // Check the target predicate to handle any context sensitive
6301 // constraints.
6302 // For example, Ties that are referenced multiple times must be
6303 // checked here to ensure the input is the same for each match
6304 // constraints. If we leave it any later the ties will have been
6305 // canonicalized
6306 unsigned MatchResult;
6307 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
6308 Inst.clear();
6309 DEBUG_WITH_TYPE(
6310 "asm-matcher",
6311 dbgs() << "Early target match predicate failed with diag code "
6312 << MatchResult << "\n");
6313 RetCode = MatchResult;
6314 HadMatchOtherThanPredicate = true;
6315 continue;
6316 }
6317
6318 if (matchingInlineAsm) {
6319 convertToMapAndConstraints(it->ConvertFn, Operands);
6320 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
6321 ErrorInfo))
6322 return Match_InvalidTiedOperand;
6323
6324 return Match_Success;
6325 }
6326
6327 // We have selected a definite instruction, convert the parsed
6328 // operands into the appropriate MCInst.
6329 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
6330
6331 // We have a potential match. Check the target predicate to
6332 // handle any context sensitive constraints.
6333 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
6334 DEBUG_WITH_TYPE("asm-matcher",
6335 dbgs() << "Target match predicate failed with diag code "
6336 << MatchResult << "\n");
6337 Inst.clear();
6338 RetCode = MatchResult;
6339 HadMatchOtherThanPredicate = true;
6340 continue;
6341 }
6342
6343 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
6344 ErrorInfo))
6345 return Match_InvalidTiedOperand;
6346
6347 DEBUG_WITH_TYPE(
6348 "asm-matcher",
6349 dbgs() << "Opcode result: complete match, selecting this opcode\n");
6350 return Match_Success;
6351 }
6352
6353 // Okay, we had no match. Try to return a useful error code.
6354 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
6355 return RetCode;
6356
6357 ErrorInfo = 0;
6358 return Match_MissingFeature;
6359}
6360
6361namespace {
6362 struct OperandMatchEntry {
6363 uint16_t Mnemonic;
6364 uint8_t OperandMask;
6365 uint8_t Class;
6366 uint8_t RequiredFeaturesIdx;
6367
6368 StringRef getMnemonic() const {
6369 return StringRef(MnemonicTable + Mnemonic + 1,
6370 MnemonicTable[Mnemonic]);
6371 }
6372 };
6373
6374 // Predicate for searching for an opcode.
6375 struct LessOpcodeOperand {
6376 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
6377 return LHS.getMnemonic() < RHS;
6378 }
6379 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
6380 return LHS < RHS.getMnemonic();
6381 }
6382 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
6383 return LHS.getMnemonic() < RHS.getMnemonic();
6384 }
6385 };
6386} // end anonymous namespace
6387
6388static const OperandMatchEntry OperandMatchTable[180] = {
6389 /* Operand List Mnemonic, Mask, Operand Class, Features */
6390 { 0 /* add */, 8 /* 3 */, MCK_TailRelocSymAdd_TLS, AMFBS_None },
6391 { 432 /* call */, 1 /* 0 */, MCK_CallTarget, AMFBS_None },
6392 { 432 /* call */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
6393 { 432 /* call */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
6394 { 432 /* call */, 1 /* 0 */, MCK_CallTarget, AMFBS_None },
6395 { 432 /* call */, 1 /* 0 */, MCK_CallTarget, AMFBS_None },
6396 { 432 /* call */, 2 /* 1 */, MCK_TailRelocSymCall_TLS, AMFBS_None },
6397 { 432 /* call */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
6398 { 432 /* call */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
6399 { 477 /* casa */, 8 /* 3 */, MCK_ASITag, AMFBS_HasCASA },
6400 { 492 /* casxa */, 8 /* 3 */, MCK_ASITag, AMFBS_Is64Bit_HasV9 },
6401 { 585 /* clr */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6402 { 585 /* clr */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6403 { 589 /* clrb */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6404 { 589 /* clrb */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6405 { 594 /* clrh */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6406 { 594 /* clrh */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6407 { 599 /* clrx */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6408 { 599 /* clrx */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
6409 { 1404 /* flush */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
6410 { 1404 /* flush */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
6411 { 3124 /* jmp */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
6412 { 3124 /* jmp */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
6413 { 3128 /* jmpl */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
6414 { 3128 /* jmpl */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
6415 { 3133 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6416 { 3133 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6417 { 3133 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6418 { 3133 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6419 { 3133 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6420 { 3133 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6421 { 3133 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6422 { 3133 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6423 { 3133 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6424 { 3133 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6425 { 3133 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6426 { 3133 /* ld */, 16 /* 4 */, MCK_TailRelocSymLoad_GOT, AMFBS_None },
6427 { 3133 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6428 { 3133 /* ld */, 16 /* 4 */, MCK_TailRelocSymLoad_TLS, AMFBS_None },
6429 { 3136 /* lda */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6430 { 3136 /* lda */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6431 { 3136 /* lda */, 8 /* 3 */, MCK_ASITag, AMFBS_HasV9 },
6432 { 3136 /* lda */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
6433 { 3136 /* lda */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
6434 { 3136 /* lda */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6435 { 3140 /* ldd */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6436 { 3140 /* ldd */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6437 { 3140 /* ldd */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6438 { 3140 /* ldd */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6439 { 3140 /* ldd */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6440 { 3140 /* ldd */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6441 { 3144 /* ldda */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6442 { 3144 /* ldda */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6443 { 3144 /* ldda */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
6444 { 3144 /* ldda */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6445 { 3144 /* ldda */, 8 /* 3 */, MCK_ASITag, AMFBS_HasV9 },
6446 { 3144 /* ldda */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
6447 { 3149 /* ldq */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6448 { 3149 /* ldq */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
6449 { 3153 /* ldqa */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6450 { 3153 /* ldqa */, 8 /* 3 */, MCK_ASITag, AMFBS_HasV9 },
6451 { 3153 /* ldqa */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
6452 { 3158 /* ldsb */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6453 { 3158 /* ldsb */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6454 { 3163 /* ldsba */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6455 { 3163 /* ldsba */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
6456 { 3163 /* ldsba */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6457 { 3169 /* ldsh */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6458 { 3169 /* ldsh */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6459 { 3174 /* ldsha */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6460 { 3174 /* ldsha */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
6461 { 3174 /* ldsha */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6462 { 3180 /* ldstub */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6463 { 3180 /* ldstub */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6464 { 3187 /* ldstuba */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6465 { 3187 /* ldstuba */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
6466 { 3187 /* ldstuba */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6467 { 3195 /* ldsw */, 2 /* 1 */, MCK_MEMri, AMFBS_Is64Bit },
6468 { 3195 /* ldsw */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
6469 { 3200 /* ldswa */, 2 /* 1 */, MCK_MEMri, AMFBS_Is64Bit },
6470 { 3200 /* ldswa */, 8 /* 3 */, MCK_ASITag, AMFBS_Is64Bit },
6471 { 3200 /* ldswa */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
6472 { 3206 /* ldub */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6473 { 3206 /* ldub */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6474 { 3211 /* lduba */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6475 { 3211 /* lduba */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
6476 { 3211 /* lduba */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6477 { 3217 /* lduh */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6478 { 3217 /* lduh */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6479 { 3222 /* lduha */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6480 { 3222 /* lduha */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
6481 { 3222 /* lduha */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6482 { 3228 /* ldx */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6483 { 3228 /* ldx */, 2 /* 1 */, MCK_MEMri, AMFBS_Is64Bit },
6484 { 3228 /* ldx */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
6485 { 3228 /* ldx */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
6486 { 3228 /* ldx */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
6487 { 3228 /* ldx */, 16 /* 4 */, MCK_TailRelocSymLoad_GOT, AMFBS_Is64Bit },
6488 { 3228 /* ldx */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
6489 { 3228 /* ldx */, 16 /* 4 */, MCK_TailRelocSymLoad_TLS, AMFBS_Is64Bit },
6490 { 3232 /* ldxa */, 2 /* 1 */, MCK_MEMri, AMFBS_Is64Bit },
6491 { 3232 /* ldxa */, 8 /* 3 */, MCK_ASITag, AMFBS_Is64Bit },
6492 { 3232 /* ldxa */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
6493 { 3247 /* membar */, 1 /* 0 */, MCK_MembarTag, AMFBS_HasV9 },
6494 { 3648 /* prefetch */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6495 { 3648 /* prefetch */, 8 /* 3 */, MCK_PrefetchTag, AMFBS_HasV9 },
6496 { 3648 /* prefetch */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
6497 { 3648 /* prefetch */, 8 /* 3 */, MCK_PrefetchTag, AMFBS_HasV9 },
6498 { 3657 /* prefetcha */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6499 { 3657 /* prefetcha */, 16 /* 4 */, MCK_PrefetchTag, AMFBS_HasV9 },
6500 { 3657 /* prefetcha */, 8 /* 3 */, MCK_ASITag, AMFBS_HasV9 },
6501 { 3657 /* prefetcha */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
6502 { 3657 /* prefetcha */, 16 /* 4 */, MCK_PrefetchTag, AMFBS_HasV9 },
6503 { 3711 /* rett */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
6504 { 3711 /* rett */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
6505 { 3809 /* sll */, 2 /* 1 */, MCK_ShiftAmtImm5, AMFBS_None },
6506 { 3813 /* sllx */, 2 /* 1 */, MCK_ShiftAmtImm6, AMFBS_Is64Bit },
6507 { 3835 /* sra */, 2 /* 1 */, MCK_ShiftAmtImm5, AMFBS_None },
6508 { 3839 /* srax */, 2 /* 1 */, MCK_ShiftAmtImm6, AMFBS_Is64Bit },
6509 { 3844 /* srl */, 2 /* 1 */, MCK_ShiftAmtImm5, AMFBS_None },
6510 { 3848 /* srlx */, 2 /* 1 */, MCK_ShiftAmtImm6, AMFBS_Is64Bit },
6511 { 3853 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6512 { 3853 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6513 { 3853 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6514 { 3853 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6515 { 3853 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6516 { 3853 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6517 { 3853 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6518 { 3853 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6519 { 3853 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6520 { 3853 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6521 { 3856 /* sta */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
6522 { 3856 /* sta */, 16 /* 4 */, MCK_ASITag, AMFBS_HasV9 },
6523 { 3856 /* sta */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
6524 { 3856 /* sta */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
6525 { 3856 /* sta */, 16 /* 4 */, MCK_ASITag, AMFBS_None },
6526 { 3856 /* sta */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6527 { 3860 /* stb */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6528 { 3860 /* stb */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6529 { 3864 /* stba */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
6530 { 3864 /* stba */, 16 /* 4 */, MCK_ASITag, AMFBS_None },
6531 { 3864 /* stba */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6532 { 3875 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6533 { 3875 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6534 { 3875 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6535 { 3875 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6536 { 3875 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6537 { 3875 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6538 { 3875 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6539 { 3875 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6540 { 3875 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6541 { 3875 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6542 { 3879 /* stda */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
6543 { 3879 /* stda */, 16 /* 4 */, MCK_ASITag, AMFBS_None },
6544 { 3879 /* stda */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6545 { 3879 /* stda */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
6546 { 3879 /* stda */, 16 /* 4 */, MCK_ASITag, AMFBS_HasV9 },
6547 { 3879 /* stda */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
6548 { 3884 /* sth */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
6549 { 3884 /* sth */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6550 { 3888 /* stha */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
6551 { 3888 /* stha */, 16 /* 4 */, MCK_ASITag, AMFBS_None },
6552 { 3888 /* stha */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
6553 { 3893 /* stq */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
6554 { 3893 /* stq */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
6555 { 3897 /* stqa */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
6556 { 3897 /* stqa */, 16 /* 4 */, MCK_ASITag, AMFBS_HasV9 },
6557 { 3897 /* stqa */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
6558 { 3902 /* stx */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
6559 { 3902 /* stx */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
6560 { 3902 /* stx */, 4 /* 2 */, MCK_MEMri, AMFBS_Is64Bit },
6561 { 3902 /* stx */, 4 /* 2 */, MCK_MEMrr, AMFBS_Is64Bit },
6562 { 3906 /* stxa */, 4 /* 2 */, MCK_MEMri, AMFBS_Is64Bit },
6563 { 3906 /* stxa */, 16 /* 4 */, MCK_ASITag, AMFBS_Is64Bit },
6564 { 3906 /* stxa */, 4 /* 2 */, MCK_MEMrr, AMFBS_Is64Bit },
6565 { 3933 /* swap */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
6566 { 3933 /* swap */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6567 { 3938 /* swapa */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
6568 { 3938 /* swapa */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
6569 { 3938 /* swapa */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
6570};
6571
6572ParseStatus SparcAsmParser::
6573tryCustomParseOperand(OperandVector &Operands,
6574 unsigned MCK) {
6575
6576 switch(MCK) {
6577 case MCK_ASITag:
6578 return parseASITag(Operands);
6579 case MCK_CallTarget:
6580 return parseCallTarget(Operands);
6581 case MCK_MEMri:
6582 return parseMEMOperand(Operands);
6583 case MCK_MEMrr:
6584 return parseMEMOperand(Operands);
6585 case MCK_MembarTag:
6586 return parseMembarTag(Operands);
6587 case MCK_PrefetchTag:
6588 return parsePrefetchTag(Operands);
6589 case MCK_ShiftAmtImm5:
6590 return parseShiftAmtImm<5>(Operands);
6591 case MCK_ShiftAmtImm6:
6592 return parseShiftAmtImm<6>(Operands);
6593 case MCK_TailRelocSymLoad_GOT:
6594 return parseTailRelocSym<TailRelocKind::Load_GOT>(Operands);
6595 case MCK_TailRelocSymAdd_TLS:
6596 return parseTailRelocSym<TailRelocKind::Add_TLS>(Operands);
6597 case MCK_TailRelocSymLoad_TLS:
6598 return parseTailRelocSym<TailRelocKind::Load_TLS>(Operands);
6599 case MCK_TailRelocSymCall_TLS:
6600 return parseTailRelocSym<TailRelocKind::Call_TLS>(Operands);
6601 default:
6602 return ParseStatus::NoMatch;
6603 }
6604 return ParseStatus::NoMatch;
6605}
6606
6607ParseStatus SparcAsmParser::
6608MatchOperandParserImpl(OperandVector &Operands,
6609 StringRef Mnemonic,
6610 bool ParseForAllFeatures) {
6611 // Get the current feature set.
6612 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
6613
6614 // Get the next operand index.
6615 unsigned NextOpNum = Operands.size() - 1;
6616 // Search the table.
6617 auto MnemonicRange =
6618 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
6619 Mnemonic, LessOpcodeOperand());
6620
6621 if (MnemonicRange.first == MnemonicRange.second)
6622 return ParseStatus::NoMatch;
6623
6624 for (const OperandMatchEntry *it = MnemonicRange.first,
6625 *ie = MnemonicRange.second; it != ie; ++it) {
6626 // equal_range guarantees that instruction mnemonic matches.
6627 assert(Mnemonic == it->getMnemonic());
6628
6629 // check if the available features match
6630 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
6631 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
6632 continue;
6633
6634 // check if the operand in question has a custom parser.
6635 if (!(it->OperandMask & (1 << NextOpNum)))
6636 continue;
6637
6638 // call custom parse method to handle the operand
6639 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
6640 if (!Result.isNoMatch())
6641 return Result;
6642 }
6643
6644 // Okay, we had no match.
6645 return ParseStatus::NoMatch;
6646}
6647
6648#endif // GET_MATCHER_IMPLEMENTATION
6649
6650
6651#ifdef GET_MNEMONIC_SPELL_CHECKER
6652#undef GET_MNEMONIC_SPELL_CHECKER
6653
6654static std::string SparcMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
6655 const unsigned MaxEditDist = 2;
6656 std::vector<StringRef> Candidates;
6657 StringRef Prev = "";
6658
6659 // Find the appropriate table for this asm variant.
6660 const MatchEntry *Start, *End;
6661 switch (VariantID) {
6662 default: llvm_unreachable("invalid variant!");
6663 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
6664 }
6665
6666 for (auto I = Start; I < End; I++) {
6667 // Ignore unsupported instructions.
6668 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
6669 if ((FBS & RequiredFeatures) != RequiredFeatures)
6670 continue;
6671
6672 StringRef T = I->getMnemonic();
6673 // Avoid recomputing the edit distance for the same string.
6674 if (T == Prev)
6675 continue;
6676
6677 Prev = T;
6678 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
6679 if (Dist <= MaxEditDist)
6680 Candidates.push_back(T);
6681 }
6682
6683 if (Candidates.empty())
6684 return "";
6685
6686 std::string Res = ", did you mean: ";
6687 unsigned i = 0;
6688 for (; i < Candidates.size() - 1; i++)
6689 Res += Candidates[i].str() + ", ";
6690 return Res + Candidates[i].str() + "?";
6691}
6692
6693#endif // GET_MNEMONIC_SPELL_CHECKER
6694
6695
6696#ifdef GET_MNEMONIC_CHECKER
6697#undef GET_MNEMONIC_CHECKER
6698
6699static bool SparcCheckMnemonic(StringRef Mnemonic,
6700 const FeatureBitset &AvailableFeatures,
6701 unsigned VariantID) {
6702 // Process all MnemonicAliases to remap the mnemonic.
6703 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
6704
6705 // Find the appropriate table for this asm variant.
6706 const MatchEntry *Start, *End;
6707 switch (VariantID) {
6708 default: llvm_unreachable("invalid variant!");
6709 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
6710 }
6711
6712 // Search the table.
6713 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
6714
6715 if (MnemonicRange.first == MnemonicRange.second)
6716 return false;
6717
6718 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
6719 it != ie; ++it) {
6720 const FeatureBitset &RequiredFeatures =
6721 FeatureBitsets[it->RequiredFeaturesIdx];
6722 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
6723 return true;
6724 }
6725 return false;
6726}
6727
6728#endif // GET_MNEMONIC_CHECKER
6729
6730