1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SP {
13
14 enum {
15 PHI = 0, // Target.td:1200
16 INLINEASM = 1, // Target.td:1206
17 INLINEASM_BR = 2, // Target.td:1212
18 CFI_INSTRUCTION = 3, // Target.td:1221
19 EH_LABEL = 4, // Target.td:1230
20 GC_LABEL = 5, // Target.td:1239
21 ANNOTATION_LABEL = 6, // Target.td:1248
22 KILL = 7, // Target.td:1256
23 EXTRACT_SUBREG = 8, // Target.td:1263
24 INSERT_SUBREG = 9, // Target.td:1269
25 IMPLICIT_DEF = 10, // Target.td:1276
26 INIT_UNDEF = 11, // Target.td:1285
27 SUBREG_TO_REG = 12, // Target.td:1292
28 COPY_TO_REGCLASS = 13, // Target.td:1298
29 DBG_VALUE = 14, // Target.td:1305
30 DBG_VALUE_LIST = 15, // Target.td:1312
31 DBG_INSTR_REF = 16, // Target.td:1319
32 DBG_PHI = 17, // Target.td:1326
33 DBG_LABEL = 18, // Target.td:1333
34 REG_SEQUENCE = 19, // Target.td:1340
35 COPY = 20, // Target.td:1347
36 COPY_LANEMASK = 21, // Target.td:1355
37 BUNDLE = 22, // Target.td:1362
38 LIFETIME_START = 23, // Target.td:1368
39 LIFETIME_END = 24, // Target.td:1375
40 PSEUDO_PROBE = 25, // Target.td:1382
41 ARITH_FENCE = 26, // Target.td:1389
42 STACKMAP = 27, // Target.td:1398
43 FENTRY_CALL = 28, // Target.td:1533
44 PATCHPOINT = 29, // Target.td:1406
45 LOAD_STACK_GUARD = 30, // Target.td:1424
46 PREALLOCATED_SETUP = 31, // Target.td:1432
47 PREALLOCATED_ARG = 32, // Target.td:1438
48 STATEPOINT = 33, // Target.td:1415
49 LOCAL_ESCAPE = 34, // Target.td:1444
50 FAULTING_OP = 35, // Target.td:1453
51 PATCHABLE_OP = 36, // Target.td:1473
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1481
53 PATCHABLE_RET = 38, // Target.td:1488
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1497
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1505
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1513
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1523
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1543
59 FAKE_USE = 44, // Target.td:1463
60 MEMBARRIER = 45, // Target.td:1549
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1557
62 RELOC_NONE = 47, // Target.td:1565
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1576
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1572
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1580
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1584
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1472
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484
96 G_INSERT = 81, // GenericOpcodes.td:1492
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1502
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448
145 G_FENCE = 130, // GenericOpcodes.td:1450
146 G_PREFETCH = 131, // GenericOpcodes.td:1457
147 G_BRCOND = 132, // GenericOpcodes.td:1592
148 G_BRINDIRECT = 133, // GenericOpcodes.td:1601
149 G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624
150 G_INTRINSIC = 135, // GenericOpcodes.td:1544
151 G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551
152 G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560
153 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568
154 G_ANYEXT = 139, // GenericOpcodes.td:44
155 G_TRUNC = 140, // GenericOpcodes.td:83
156 G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90
157 G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97
158 G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104
159 G_CONSTANT = 144, // GenericOpcodes.td:165
160 G_FCONSTANT = 145, // GenericOpcodes.td:172
161 G_VASTART = 146, // GenericOpcodes.td:178
162 G_VAARG = 147, // GenericOpcodes.td:185
163 G_SEXT = 148, // GenericOpcodes.td:52
164 G_SEXT_INREG = 149, // GenericOpcodes.td:66
165 G_ZEXT = 150, // GenericOpcodes.td:74
166 G_SHL = 151, // GenericOpcodes.td:396
167 G_LSHR = 152, // GenericOpcodes.td:403
168 G_ASHR = 153, // GenericOpcodes.td:410
169 G_FSHL = 154, // GenericOpcodes.td:462
170 G_FSHR = 155, // GenericOpcodes.td:470
171 G_ROTR = 156, // GenericOpcodes.td:477
172 G_ROTL = 157, // GenericOpcodes.td:484
173 G_ICMP = 158, // GenericOpcodes.td:491
174 G_FCMP = 159, // GenericOpcodes.td:498
175 G_SCMP = 160, // GenericOpcodes.td:505
176 G_UCMP = 161, // GenericOpcodes.td:512
177 G_SELECT = 162, // GenericOpcodes.td:519
178 G_UADDO = 163, // GenericOpcodes.td:584
179 G_UADDE = 164, // GenericOpcodes.td:592
180 G_USUBO = 165, // GenericOpcodes.td:614
181 G_USUBE = 166, // GenericOpcodes.td:620
182 G_SADDO = 167, // GenericOpcodes.td:599
183 G_SADDE = 168, // GenericOpcodes.td:607
184 G_SSUBO = 169, // GenericOpcodes.td:627
185 G_SSUBE = 170, // GenericOpcodes.td:634
186 G_UMULO = 171, // GenericOpcodes.td:641
187 G_SMULO = 172, // GenericOpcodes.td:649
188 G_UMULH = 173, // GenericOpcodes.td:658
189 G_SMULH = 174, // GenericOpcodes.td:667
190 G_UADDSAT = 175, // GenericOpcodes.td:679
191 G_SADDSAT = 176, // GenericOpcodes.td:687
192 G_USUBSAT = 177, // GenericOpcodes.td:695
193 G_SSUBSAT = 178, // GenericOpcodes.td:703
194 G_USHLSAT = 179, // GenericOpcodes.td:711
195 G_SSHLSAT = 180, // GenericOpcodes.td:719
196 G_SMULFIX = 181, // GenericOpcodes.td:731
197 G_UMULFIX = 182, // GenericOpcodes.td:738
198 G_SMULFIXSAT = 183, // GenericOpcodes.td:748
199 G_UMULFIXSAT = 184, // GenericOpcodes.td:755
200 G_SDIVFIX = 185, // GenericOpcodes.td:766
201 G_UDIVFIX = 186, // GenericOpcodes.td:773
202 G_SDIVFIXSAT = 187, // GenericOpcodes.td:783
203 G_UDIVFIXSAT = 188, // GenericOpcodes.td:790
204 G_FADD = 189, // GenericOpcodes.td:963
205 G_FSUB = 190, // GenericOpcodes.td:971
206 G_FMUL = 191, // GenericOpcodes.td:979
207 G_FMA = 192, // GenericOpcodes.td:988
208 G_FMAD = 193, // GenericOpcodes.td:997
209 G_FDIV = 194, // GenericOpcodes.td:1005
210 G_FREM = 195, // GenericOpcodes.td:1012
211 G_FMODF = 196, // GenericOpcodes.td:1019
212 G_FPOW = 197, // GenericOpcodes.td:1026
213 G_FPOWI = 198, // GenericOpcodes.td:1033
214 G_FEXP = 199, // GenericOpcodes.td:1040
215 G_FEXP2 = 200, // GenericOpcodes.td:1047
216 G_FEXP10 = 201, // GenericOpcodes.td:1054
217 G_FLOG = 202, // GenericOpcodes.td:1061
218 G_FLOG2 = 203, // GenericOpcodes.td:1068
219 G_FLOG10 = 204, // GenericOpcodes.td:1075
220 G_FLDEXP = 205, // GenericOpcodes.td:1082
221 G_FFREXP = 206, // GenericOpcodes.td:1089
222 G_FNEG = 207, // GenericOpcodes.td:801
223 G_FPEXT = 208, // GenericOpcodes.td:807
224 G_FPTRUNC = 209, // GenericOpcodes.td:813
225 G_FPTOSI = 210, // GenericOpcodes.td:819
226 G_FPTOUI = 211, // GenericOpcodes.td:825
227 G_SITOFP = 212, // GenericOpcodes.td:831
228 G_UITOFP = 213, // GenericOpcodes.td:837
229 G_FPTOSI_SAT = 214, // GenericOpcodes.td:843
230 G_FPTOUI_SAT = 215, // GenericOpcodes.td:849
231 G_FABS = 216, // GenericOpcodes.td:855
232 G_FCOPYSIGN = 217, // GenericOpcodes.td:861
233 G_IS_FPCLASS = 218, // GenericOpcodes.td:874
234 G_FCANONICALIZE = 219, // GenericOpcodes.td:867
235 G_FMINNUM = 220, // GenericOpcodes.td:887
236 G_FMAXNUM = 221, // GenericOpcodes.td:894
237 G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912
238 G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919
239 G_FMINIMUM = 224, // GenericOpcodes.td:929
240 G_FMAXIMUM = 225, // GenericOpcodes.td:936
241 G_FMINIMUMNUM = 226, // GenericOpcodes.td:944
242 G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951
243 G_GET_FPENV = 228, // GenericOpcodes.td:1219
244 G_SET_FPENV = 229, // GenericOpcodes.td:1226
245 G_RESET_FPENV = 230, // GenericOpcodes.td:1233
246 G_GET_FPMODE = 231, // GenericOpcodes.td:1240
247 G_SET_FPMODE = 232, // GenericOpcodes.td:1247
248 G_RESET_FPMODE = 233, // GenericOpcodes.td:1254
249 G_GET_ROUNDING = 234, // GenericOpcodes.td:1311
250 G_SET_ROUNDING = 235, // GenericOpcodes.td:1317
251 G_PTR_ADD = 236, // GenericOpcodes.td:526
252 G_PTRMASK = 237, // GenericOpcodes.td:534
253 G_SMIN = 238, // GenericOpcodes.td:541
254 G_SMAX = 239, // GenericOpcodes.td:549
255 G_UMIN = 240, // GenericOpcodes.td:557
256 G_UMAX = 241, // GenericOpcodes.td:565
257 G_ABS = 242, // GenericOpcodes.td:573
258 G_LROUND = 243, // GenericOpcodes.td:283
259 G_LLROUND = 244, // GenericOpcodes.td:289
260 G_BR = 245, // GenericOpcodes.td:1582
261 G_BRJT = 246, // GenericOpcodes.td:1612
262 G_VSCALE = 247, // GenericOpcodes.td:1512
263 G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656
264 G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663
265 G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670
266 G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677
267 G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687
268 G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694
269 G_STEP_VECTOR = 254, // GenericOpcodes.td:1701
270 G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708
271 G_CTTZ = 256, // GenericOpcodes.td:205
272 G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211
273 G_CTLZ = 258, // GenericOpcodes.td:193
274 G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199
275 G_CTLS = 260, // GenericOpcodes.td:217
276 G_CTPOP = 261, // GenericOpcodes.td:223
277 G_BSWAP = 262, // GenericOpcodes.td:229
278 G_BITREVERSE = 263, // GenericOpcodes.td:235
279 G_FCEIL = 264, // GenericOpcodes.td:1096
280 G_FCOS = 265, // GenericOpcodes.td:1103
281 G_FSIN = 266, // GenericOpcodes.td:1110
282 G_FSINCOS = 267, // GenericOpcodes.td:1117
283 G_FTAN = 268, // GenericOpcodes.td:1124
284 G_FACOS = 269, // GenericOpcodes.td:1131
285 G_FASIN = 270, // GenericOpcodes.td:1138
286 G_FATAN = 271, // GenericOpcodes.td:1145
287 G_FATAN2 = 272, // GenericOpcodes.td:1152
288 G_FCOSH = 273, // GenericOpcodes.td:1159
289 G_FSINH = 274, // GenericOpcodes.td:1166
290 G_FTANH = 275, // GenericOpcodes.td:1173
291 G_FSQRT = 276, // GenericOpcodes.td:1183
292 G_FFLOOR = 277, // GenericOpcodes.td:1190
293 G_FRINT = 278, // GenericOpcodes.td:1197
294 G_FNEARBYINT = 279, // GenericOpcodes.td:1204
295 G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241
296 G_BLOCK_ADDR = 281, // GenericOpcodes.td:247
297 G_JUMP_TABLE = 282, // GenericOpcodes.td:253
298 G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259
299 G_STACKSAVE = 284, // GenericOpcodes.td:265
300 G_STACKRESTORE = 285, // GenericOpcodes.td:271
301 G_STRICT_FADD = 286, // GenericOpcodes.td:1758
302 G_STRICT_FSUB = 287, // GenericOpcodes.td:1759
303 G_STRICT_FMUL = 288, // GenericOpcodes.td:1760
304 G_STRICT_FDIV = 289, // GenericOpcodes.td:1761
305 G_STRICT_FREM = 290, // GenericOpcodes.td:1762
306 G_STRICT_FMA = 291, // GenericOpcodes.td:1763
307 G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764
308 G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765
309 G_READ_REGISTER = 294, // GenericOpcodes.td:1631
310 G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641
311 G_MEMCPY = 296, // GenericOpcodes.td:1771
312 G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779
313 G_MEMMOVE = 298, // GenericOpcodes.td:1787
314 G_MEMSET = 299, // GenericOpcodes.td:1795
315 G_BZERO = 300, // GenericOpcodes.td:1802
316 G_TRAP = 301, // GenericOpcodes.td:1812
317 G_DEBUGTRAP = 302, // GenericOpcodes.td:1819
318 G_UBSANTRAP = 303, // GenericOpcodes.td:1825
319 G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724
320 G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730
321 G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736
322 G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737
323 G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739
324 G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740
325 G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744
328 G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745
329 G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752
336 G_SBFX = 321, // GenericOpcodes.td:1837
337 G_UBFX = 322, // GenericOpcodes.td:1845
338 ADJCALLSTACKDOWN = 323, // SparcInstrInfo.td:591
339 ADJCALLSTACKUP = 324, // SparcInstrInfo.td:594
340 GETPCX = 325, // SparcInstrInfo.td:587
341 SELECT_CC_DFP_FCC = 326, // SparcInstrInfo.td:667
342 SELECT_CC_DFP_ICC = 327, // SparcInstrInfo.td:624
343 SELECT_CC_DFP_XCC = 328, // SparcInstrInfo.td:645
344 SELECT_CC_FP_FCC = 329, // SparcInstrInfo.td:663
345 SELECT_CC_FP_ICC = 330, // SparcInstrInfo.td:619
346 SELECT_CC_FP_XCC = 331, // SparcInstrInfo.td:640
347 SELECT_CC_Int_FCC = 332, // SparcInstrInfo.td:658
348 SELECT_CC_Int_ICC = 333, // SparcInstrInfo.td:615
349 SELECT_CC_Int_XCC = 334, // SparcInstrInfo.td:636
350 SELECT_CC_QFP_FCC = 335, // SparcInstrInfo.td:671
351 SELECT_CC_QFP_ICC = 336, // SparcInstrInfo.td:629
352 SELECT_CC_QFP_XCC = 337, // SparcInstrInfo.td:650
353 SET = 338, // SparcInstrAliases.td:562
354 SETSW = 339, // SparcInstrAliases.td:566
355 SETX = 340, // SparcInstrAliases.td:570
356 V8BAR = 341, // SparcInstrInfo.td:583
357 ADDCCri = 342, // SparcInstrInfo.td:478
358 ADDCCrr = 343, // SparcInstrInfo.td:473
359 ADDCri = 344, // SparcInstrInfo.td:492
360 ADDCrr = 345, // SparcInstrInfo.td:488
361 ADDEri = 346, // SparcInstrInfo.td:478
362 ADDErr = 347, // SparcInstrInfo.td:473
363 ADDXC = 348, // SparcInstrVIS.td:185
364 ADDXCCC = 349, // SparcInstrVIS.td:188
365 ADDri = 350, // SparcInstrInfo.td:478
366 ADDrr = 351, // SparcInstrInfo.td:473
367 AES_DROUND01 = 352, // SparcInstrCrypto.td:23
368 AES_DROUND01_LAST = 353, // SparcInstrCrypto.td:27
369 AES_DROUND23 = 354, // SparcInstrCrypto.td:24
370 AES_DROUND23_LAST = 355, // SparcInstrCrypto.td:28
371 AES_EROUND01 = 356, // SparcInstrCrypto.td:21
372 AES_EROUND01_LAST = 357, // SparcInstrCrypto.td:25
373 AES_EROUND23 = 358, // SparcInstrCrypto.td:22
374 AES_EROUND23_LAST = 359, // SparcInstrCrypto.td:26
375 AES_KEXPAND0 = 360, // SparcInstrCrypto.td:29
376 AES_KEXPAND1 = 361, // SparcInstrCrypto.td:32
377 AES_KEXPAND2 = 362, // SparcInstrCrypto.td:33
378 ALIGNADDR = 363, // SparcInstrVIS.td:96
379 ALIGNADDRL = 364, // SparcInstrVIS.td:97
380 ALLCLEAN = 365, // SparcInstrUAOSA.td:39
381 ANDCCri = 366, // SparcInstrInfo.td:492
382 ANDCCrr = 367, // SparcInstrInfo.td:488
383 ANDNCCri = 368, // SparcInstrInfo.td:492
384 ANDNCCrr = 369, // SparcInstrInfo.td:488
385 ANDNri = 370, // SparcInstrInfo.td:852
386 ANDNrr = 371, // SparcInstrInfo.td:848
387 ANDri = 372, // SparcInstrInfo.td:478
388 ANDrr = 373, // SparcInstrInfo.td:473
389 ARRAY16 = 374, // SparcInstrVIS.td:154
390 ARRAY32 = 375, // SparcInstrVIS.td:155
391 ARRAY8 = 376, // SparcInstrVIS.td:153
392 BA = 377, // SparcInstrInfo.td:965
393 BCOND = 378, // SparcInstrInfo.td:1014
394 BCONDA = 379, // SparcInstrInfo.td:1017
395 BINDri = 380, // SparcInstrInfo.td:1007
396 BINDrr = 381, // SparcInstrInfo.td:1003
397 BMASK = 382, // SparcInstrVIS.td:165
398 BPFCC = 383, // SparcInstrInfo.td:1038
399 BPFCCA = 384, // SparcInstrInfo.td:1041
400 BPFCCANT = 385, // SparcInstrInfo.td:1047
401 BPFCCNT = 386, // SparcInstrInfo.td:1044
402 BPICC = 387, // SparcInstrInfo.td:979
403 BPICCA = 388, // SparcInstrInfo.td:983
404 BPICCANT = 389, // SparcInstrInfo.td:991
405 BPICCNT = 390, // SparcInstrInfo.td:987
406 BPR = 391, // SparcInstr64Bit.td:325
407 BPRA = 392, // SparcInstr64Bit.td:327
408 BPRANT = 393, // SparcInstr64Bit.td:331
409 BPRNT = 394, // SparcInstr64Bit.td:329
410 BPXCC = 395, // SparcInstrInfo.td:979
411 BPXCCA = 396, // SparcInstrInfo.td:983
412 BPXCCANT = 397, // SparcInstrInfo.td:991
413 BPXCCNT = 398, // SparcInstrInfo.td:987
414 BSHUFFLE = 399, // SparcInstrVIS.td:166
415 CALL = 400, // SparcInstrInfo.td:1100
416 CALLi = 401, // SparcInstrInfo.td:1112
417 CALLri = 402, // SparcInstrInfo.td:1127
418 CALLrii = 403, // SparcInstrInfo.td:1138
419 CALLrr = 404, // SparcInstrInfo.td:1122
420 CALLrri = 405, // SparcInstrInfo.td:1135
421 CAMELLIA_F = 406, // SparcInstrCrypto.td:37
422 CAMELLIA_FL = 407, // SparcInstrCrypto.td:38
423 CAMELLIA_FLI = 408, // SparcInstrCrypto.td:41
424 CASAri = 409, // SparcInstrInfo.td:1800
425 CASArr = 410, // SparcInstrInfo.td:1792
426 CASXAri = 411, // SparcInstr64Bit.td:442
427 CASXArr = 412, // SparcInstr64Bit.td:435
428 CMASK16 = 413, // SparcInstrVIS.td:193
429 CMASK32 = 414, // SparcInstrVIS.td:195
430 CMASK8 = 415, // SparcInstrVIS.td:191
431 CPBCOND = 416, // SparcInstrInfo.td:1090
432 CPBCONDA = 417, // SparcInstrInfo.td:1093
433 CRC32C = 418, // SparcInstrCrypto.td:45
434 CWBCONDri = 419, // SparcInstrUAOSA.td:31
435 CWBCONDrr = 420, // SparcInstrUAOSA.td:28
436 CXBCONDri = 421, // SparcInstrUAOSA.td:31
437 CXBCONDrr = 422, // SparcInstrUAOSA.td:28
438 DES_IIP = 423, // SparcInstrCrypto.td:54
439 DES_IP = 424, // SparcInstrCrypto.td:51
440 DES_KEXPAND = 425, // SparcInstrCrypto.td:58
441 DES_ROUND = 426, // SparcInstrCrypto.td:49
442 DONE = 427, // SparcInstrInfo.td:1854
443 EDGE16 = 428, // SparcInstrVIS.td:146
444 EDGE16L = 429, // SparcInstrVIS.td:147
445 EDGE16LN = 430, // SparcInstrVIS.td:175
446 EDGE16N = 431, // SparcInstrVIS.td:174
447 EDGE32 = 432, // SparcInstrVIS.td:148
448 EDGE32L = 433, // SparcInstrVIS.td:149
449 EDGE32LN = 434, // SparcInstrVIS.td:177
450 EDGE32N = 435, // SparcInstrVIS.td:176
451 EDGE8 = 436, // SparcInstrVIS.td:144
452 EDGE8L = 437, // SparcInstrVIS.td:145
453 EDGE8LN = 438, // SparcInstrVIS.td:173
454 EDGE8N = 439, // SparcInstrVIS.td:172
455 FABSD = 440, // SparcInstrInfo.td:1708
456 FABSQ = 441, // SparcInstrInfo.td:1713
457 FABSS = 442, // SparcInstrInfo.td:1393
458 FADDD = 443, // SparcInstrInfo.td:1428
459 FADDQ = 444, // SparcInstrInfo.td:1433
460 FADDS = 445, // SparcInstrInfo.td:1423
461 FALIGNADATA = 446, // SparcInstrVIS.td:98
462 FAND = 447, // SparcInstrVIS.td:116
463 FANDNOT1 = 448, // SparcInstrVIS.td:129
464 FANDNOT1S = 449, // SparcInstrVIS.td:130
465 FANDNOT2 = 450, // SparcInstrVIS.td:131
466 FANDNOT2S = 451, // SparcInstrVIS.td:132
467 FANDS = 452, // SparcInstrVIS.td:117
468 FBCOND = 453, // SparcInstrInfo.td:1054
469 FBCONDA = 454, // SparcInstrInfo.td:1057
470 FBCONDA_V9 = 455, // SparcInstrInfo.td:1068
471 FBCOND_V9 = 456, // SparcInstrInfo.td:1064
472 FCHKSM16 = 457, // SparcInstrVIS.td:200
473 FCMPD = 458, // SparcInstrInfo.td:1519
474 FCMPD_V9 = 459, // SparcInstrInfo.td:1544
475 FCMPEQ16 = 460, // SparcInstrVIS.td:140
476 FCMPEQ32 = 461, // SparcInstrVIS.td:141
477 FCMPGT16 = 462, // SparcInstrVIS.td:134
478 FCMPGT32 = 463, // SparcInstrVIS.td:135
479 FCMPLE16 = 464, // SparcInstrVIS.td:136
480 FCMPLE32 = 465, // SparcInstrVIS.td:137
481 FCMPNE16 = 466, // SparcInstrVIS.td:138
482 FCMPNE32 = 467, // SparcInstrVIS.td:139
483 FCMPQ = 468, // SparcInstrInfo.td:1524
484 FCMPQ_V9 = 469, // SparcInstrInfo.td:1549
485 FCMPS = 470, // SparcInstrInfo.td:1514
486 FCMPS_V9 = 471, // SparcInstrInfo.td:1539
487 FDIVD = 472, // SparcInstrInfo.td:1495
488 FDIVQ = 473, // SparcInstrInfo.td:1500
489 FDIVS = 474, // SparcInstrInfo.td:1490
490 FDMULQ = 475, // SparcInstrInfo.td:1481
491 FDTOI = 476, // SparcInstrInfo.td:1341
492 FDTOQ = 477, // SparcInstrInfo.td:1368
493 FDTOS = 478, // SparcInstrInfo.td:1363
494 FDTOX = 479, // SparcInstr64Bit.td:399
495 FEXPAND = 480, // SparcInstrVIS.td:72
496 FHADDD = 481, // SparcInstrVIS.td:205
497 FHADDS = 482, // SparcInstrVIS.td:202
498 FHSUBD = 483, // SparcInstrVIS.td:211
499 FHSUBS = 484, // SparcInstrVIS.td:208
500 FITOD = 485, // SparcInstrInfo.td:1324
501 FITOQ = 486, // SparcInstrInfo.td:1329
502 FITOS = 487, // SparcInstrInfo.td:1319
503 FLCMPD = 488, // SparcInstrVIS.td:217
504 FLCMPS = 489, // SparcInstrVIS.td:214
505 FLUSH = 490, // SparcInstrInfo.td:1313
506 FLUSHW = 491, // SparcInstrInfo.td:601
507 FLUSHri = 492, // SparcInstrInfo.td:1306
508 FLUSHrr = 493, // SparcInstrInfo.td:1304
509 FMADDD = 494, // SparcInstrUAOSA.td:49
510 FMADDS = 495, // SparcInstrUAOSA.td:48
511 FMEAN16 = 496, // SparcInstrVIS.td:221
512 FMOVD = 497, // SparcInstrInfo.td:1692
513 FMOVD_FCC = 498, // SparcInstrInfo.td:1675
514 FMOVD_ICC = 499, // SparcInstrInfo.td:1656
515 FMOVD_XCC = 500, // SparcInstr64Bit.td:308
516 FMOVQ = 501, // SparcInstrInfo.td:1696
517 FMOVQ_FCC = 502, // SparcInstrInfo.td:1681
518 FMOVQ_ICC = 503, // SparcInstrInfo.td:1662
519 FMOVQ_XCC = 504, // SparcInstr64Bit.td:314
520 FMOVRD = 505, // SparcInstr64Bit.td:364
521 FMOVRQ = 506, // SparcInstr64Bit.td:369
522 FMOVRS = 507, // SparcInstr64Bit.td:360
523 FMOVS = 508, // SparcInstrInfo.td:1385
524 FMOVS_FCC = 509, // SparcInstrInfo.td:1670
525 FMOVS_ICC = 510, // SparcInstrInfo.td:1651
526 FMOVS_XCC = 511, // SparcInstr64Bit.td:303
527 FMSUBD = 512, // SparcInstrUAOSA.td:51
528 FMSUBS = 513, // SparcInstrUAOSA.td:50
529 FMUL8SUX16 = 514, // SparcInstrVIS.td:87
530 FMUL8ULX16 = 515, // SparcInstrVIS.td:88
531 FMUL8X16 = 516, // SparcInstrVIS.td:78
532 FMUL8X16AL = 517, // SparcInstrVIS.td:84
533 FMUL8X16AU = 518, // SparcInstrVIS.td:81
534 FMULD = 519, // SparcInstrInfo.td:1463
535 FMULD8SUX16 = 520, // SparcInstrVIS.td:89
536 FMULD8ULX16 = 521, // SparcInstrVIS.td:92
537 FMULQ = 522, // SparcInstrInfo.td:1468
538 FMULS = 523, // SparcInstrInfo.td:1457
539 FNADDD = 524, // SparcInstrVIS.td:226
540 FNADDS = 525, // SparcInstrVIS.td:223
541 FNAND = 526, // SparcInstrVIS.td:118
542 FNANDS = 527, // SparcInstrVIS.td:119
543 FNEGD = 528, // SparcInstrInfo.td:1699
544 FNEGQ = 529, // SparcInstrInfo.td:1704
545 FNEGS = 530, // SparcInstrInfo.td:1388
546 FNHADDD = 531, // SparcInstrVIS.td:232
547 FNHADDS = 532, // SparcInstrVIS.td:229
548 FNMADDD = 533, // SparcInstrUAOSA.td:54
549 FNMADDS = 534, // SparcInstrUAOSA.td:53
550 FNMSUBD = 535, // SparcInstrUAOSA.td:56
551 FNMSUBS = 536, // SparcInstrUAOSA.td:55
552 FNMULD = 537, // SparcInstrVIS.td:239
553 FNMULS = 538, // SparcInstrVIS.td:236
554 FNOR = 539, // SparcInstrVIS.td:114
555 FNORS = 540, // SparcInstrVIS.td:115
556 FNOT1 = 541, // SparcInstrVIS.td:108
557 FNOT1S = 542, // SparcInstrVIS.td:109
558 FNOT2 = 543, // SparcInstrVIS.td:110
559 FNOT2S = 544, // SparcInstrVIS.td:111
560 FNSMULD = 545, // SparcInstrVIS.td:242
561 FONE = 546, // SparcInstrVIS.td:102
562 FONES = 547, // SparcInstrVIS.td:103
563 FOR = 548, // SparcInstrVIS.td:112
564 FORNOT1 = 549, // SparcInstrVIS.td:125
565 FORNOT1S = 550, // SparcInstrVIS.td:126
566 FORNOT2 = 551, // SparcInstrVIS.td:127
567 FORNOT2S = 552, // SparcInstrVIS.td:128
568 FORS = 553, // SparcInstrVIS.td:113
569 FPACK16 = 554, // SparcInstrVIS.td:66
570 FPACK32 = 555, // SparcInstrVIS.td:67
571 FPACKFIX = 556, // SparcInstrVIS.td:69
572 FPADD16 = 557, // SparcInstrVIS.td:57
573 FPADD16S = 558, // SparcInstrVIS.td:58
574 FPADD32 = 559, // SparcInstrVIS.td:59
575 FPADD32S = 560, // SparcInstrVIS.td:60
576 FPADD64 = 561, // SparcInstrVIS.td:246
577 FPMADDX = 562, // SparcInstrUAOSA.td:66
578 FPMADDXHI = 563, // SparcInstrUAOSA.td:67
579 FPMERGE = 564, // SparcInstrVIS.td:74
580 FPSUB16 = 565, // SparcInstrVIS.td:61
581 FPSUB16S = 566, // SparcInstrVIS.td:62
582 FPSUB32 = 567, // SparcInstrVIS.td:63
583 FPSUB32S = 568, // SparcInstrVIS.td:64
584 FQTOD = 569, // SparcInstrInfo.td:1378
585 FQTOI = 570, // SparcInstrInfo.td:1346
586 FQTOS = 571, // SparcInstrInfo.td:1373
587 FQTOX = 572, // SparcInstr64Bit.td:404
588 FSLAS16 = 573, // SparcInstrVIS.td:252
589 FSLAS32 = 574, // SparcInstrVIS.td:254
590 FSLL16 = 575, // SparcInstrVIS.td:248
591 FSLL32 = 576, // SparcInstrVIS.td:250
592 FSMULD = 577, // SparcInstrInfo.td:1474
593 FSQRTD = 578, // SparcInstrInfo.td:1409
594 FSQRTQ = 579, // SparcInstrInfo.td:1414
595 FSQRTS = 580, // SparcInstrInfo.td:1404
596 FSRA16 = 581, // SparcInstrVIS.td:253
597 FSRA32 = 582, // SparcInstrVIS.td:255
598 FSRC1 = 583, // SparcInstrVIS.td:104
599 FSRC1S = 584, // SparcInstrVIS.td:105
600 FSRC2 = 585, // SparcInstrVIS.td:106
601 FSRC2S = 586, // SparcInstrVIS.td:107
602 FSRL16 = 587, // SparcInstrVIS.td:249
603 FSRL32 = 588, // SparcInstrVIS.td:251
604 FSTOD = 589, // SparcInstrInfo.td:1353
605 FSTOI = 590, // SparcInstrInfo.td:1336
606 FSTOQ = 591, // SparcInstrInfo.td:1358
607 FSTOX = 592, // SparcInstr64Bit.td:395
608 FSUBD = 593, // SparcInstrInfo.td:1444
609 FSUBQ = 594, // SparcInstrInfo.td:1449
610 FSUBS = 595, // SparcInstrInfo.td:1439
611 FXNOR = 596, // SparcInstrVIS.td:122
612 FXNORS = 597, // SparcInstrVIS.td:123
613 FXOR = 598, // SparcInstrVIS.td:120
614 FXORS = 599, // SparcInstrVIS.td:121
615 FXTOD = 600, // SparcInstr64Bit.td:385
616 FXTOQ = 601, // SparcInstr64Bit.td:390
617 FXTOS = 602, // SparcInstr64Bit.td:381
618 FZERO = 603, // SparcInstrVIS.td:100
619 FZEROS = 604, // SparcInstrVIS.td:101
620 GDOP_LDXrr = 605, // SparcInstr64Bit.td:216
621 GDOP_LDrr = 606, // SparcInstrInfo.td:727
622 INVALW = 607, // SparcInstrUAOSA.td:40
623 JMPLri = 608, // SparcInstrInfo.td:1153
624 JMPLrr = 609, // SparcInstrInfo.td:1148
625 LDAri = 610, // SparcInstrInfo.td:521
626 LDArr = 611, // SparcInstrInfo.td:516
627 LDCSRri = 612, // SparcInstrInfo.td:706
628 LDCSRrr = 613, // SparcInstrInfo.td:704
629 LDCri = 614, // SparcInstrInfo.td:506
630 LDCrr = 615, // SparcInstrInfo.td:501
631 LDDAri = 616, // SparcInstrInfo.td:521
632 LDDArr = 617, // SparcInstrInfo.td:516
633 LDDCri = 618, // SparcInstrInfo.td:506
634 LDDCrr = 619, // SparcInstrInfo.td:501
635 LDDFAri = 620, // SparcInstrInfo.td:521
636 LDDFArr = 621, // SparcInstrInfo.td:516
637 LDDFri = 622, // SparcInstrInfo.td:506
638 LDDFrr = 623, // SparcInstrInfo.td:501
639 LDDri = 624, // SparcInstrInfo.td:506
640 LDDrr = 625, // SparcInstrInfo.td:501
641 LDFAri = 626, // SparcInstrInfo.td:521
642 LDFArr = 627, // SparcInstrInfo.td:516
643 LDFSRri = 628, // SparcInstrInfo.td:715
644 LDFSRrr = 629, // SparcInstrInfo.td:713
645 LDFri = 630, // SparcInstrInfo.td:506
646 LDFrr = 631, // SparcInstrInfo.td:501
647 LDQFAri = 632, // SparcInstrInfo.td:521
648 LDQFArr = 633, // SparcInstrInfo.td:516
649 LDQFri = 634, // SparcInstrInfo.td:506
650 LDQFrr = 635, // SparcInstrInfo.td:501
651 LDSBAri = 636, // SparcInstrInfo.td:521
652 LDSBArr = 637, // SparcInstrInfo.td:516
653 LDSBri = 638, // SparcInstrInfo.td:506
654 LDSBrr = 639, // SparcInstrInfo.td:501
655 LDSHAri = 640, // SparcInstrInfo.td:521
656 LDSHArr = 641, // SparcInstrInfo.td:516
657 LDSHri = 642, // SparcInstrInfo.td:506
658 LDSHrr = 643, // SparcInstrInfo.td:501
659 LDSTUBAri = 644, // SparcInstrInfo.td:806
660 LDSTUBArr = 645, // SparcInstrInfo.td:802
661 LDSTUBri = 646, // SparcInstrInfo.td:800
662 LDSTUBrr = 647, // SparcInstrInfo.td:798
663 LDSWAri = 648, // SparcInstrInfo.td:521
664 LDSWArr = 649, // SparcInstrInfo.td:516
665 LDSWri = 650, // SparcInstrInfo.td:506
666 LDSWrr = 651, // SparcInstrInfo.td:501
667 LDUBAri = 652, // SparcInstrInfo.td:521
668 LDUBArr = 653, // SparcInstrInfo.td:516
669 LDUBri = 654, // SparcInstrInfo.td:506
670 LDUBrr = 655, // SparcInstrInfo.td:501
671 LDUHAri = 656, // SparcInstrInfo.td:521
672 LDUHArr = 657, // SparcInstrInfo.td:516
673 LDUHri = 658, // SparcInstrInfo.td:506
674 LDUHrr = 659, // SparcInstrInfo.td:501
675 LDXAri = 660, // SparcInstrInfo.td:521
676 LDXArr = 661, // SparcInstrInfo.td:516
677 LDXFSRri = 662, // SparcInstrInfo.td:721
678 LDXFSRrr = 663, // SparcInstrInfo.td:719
679 LDXri = 664, // SparcInstrInfo.td:506
680 LDXrr = 665, // SparcInstrInfo.td:501
681 LDri = 666, // SparcInstrInfo.td:506
682 LDrr = 667, // SparcInstrInfo.td:501
683 LZCNT = 668, // SparcInstrVIS.td:258
684 MD5 = 669, // SparcInstrCrypto.td:65
685 MEMBARi = 670, // SparcInstrInfo.td:1782
686 MONTMUL = 671, // SparcInstrCrypto.td:95
687 MONTSQR = 672, // SparcInstrCrypto.td:96
688 MOVDTOX = 673, // SparcInstrVIS.td:266
689 MOVFCCri = 674, // SparcInstrInfo.td:1642
690 MOVFCCrr = 675, // SparcInstrInfo.td:1637
691 MOVICCri = 676, // SparcInstrInfo.td:1628
692 MOVICCrr = 677, // SparcInstrInfo.td:1622
693 MOVRri = 678, // SparcInstr64Bit.td:352
694 MOVRrr = 679, // SparcInstr64Bit.td:347
695 MOVSTOSW = 680, // SparcInstrVIS.td:262
696 MOVSTOUW = 681, // SparcInstrVIS.td:264
697 MOVWTOS = 682, // SparcInstrVIS.td:268
698 MOVXCCri = 683, // SparcInstr64Bit.td:295
699 MOVXCCrr = 684, // SparcInstr64Bit.td:290
700 MOVXTOD = 685, // SparcInstrVIS.td:270
701 MPMUL = 686, // SparcInstrCrypto.td:94
702 MULSCCri = 687, // SparcInstrInfo.td:492
703 MULSCCrr = 688, // SparcInstrInfo.td:488
704 MULXri = 689, // SparcInstrInfo.td:478
705 MULXrr = 690, // SparcInstrInfo.td:473
706 NOP = 691, // SparcInstrInfo.td:843
707 NORMALW = 692, // SparcInstrUAOSA.td:41
708 ORCCri = 693, // SparcInstrInfo.td:492
709 ORCCrr = 694, // SparcInstrInfo.td:488
710 ORNCCri = 695, // SparcInstrInfo.td:492
711 ORNCCrr = 696, // SparcInstrInfo.td:488
712 ORNri = 697, // SparcInstrInfo.td:862
713 ORNrr = 698, // SparcInstrInfo.td:858
714 ORri = 699, // SparcInstrInfo.td:478
715 ORrr = 700, // SparcInstrInfo.td:473
716 OTHERW = 701, // SparcInstrUAOSA.td:42
717 PDIST = 702, // SparcInstrVIS.td:151
718 PDISTN = 703, // SparcInstrVIS.td:274
719 POPCrr = 704, // SparcInstrInfo.td:1775
720 PREFETCHAi = 705, // SparcInstrInfo.td:1878
721 PREFETCHAr = 706, // SparcInstrInfo.td:1874
722 PREFETCHi = 707, // SparcInstrInfo.td:1871
723 PREFETCHr = 708, // SparcInstrInfo.td:1868
724 PWRPSRri = 709, // SparcInstrInfo.td:1835
725 PWRPSRrr = 710, // SparcInstrInfo.td:1832
726 RDASR = 711, // SparcInstrInfo.td:1232
727 RDFQ = 712, // SparcInstrInfo.td:1897
728 RDPR = 713, // SparcInstrInfo.td:1888
729 RDPSR = 714, // SparcInstrInfo.td:1239
730 RDTBR = 715, // SparcInstrInfo.td:1249
731 RDWIM = 716, // SparcInstrInfo.td:1244
732 RESTORED = 717, // SparcInstrInfo.td:1863
733 RESTOREri = 718, // SparcInstrInfo.td:492
734 RESTORErr = 719, // SparcInstrInfo.td:488
735 RET = 720, // SparcInstrInfo.td:1172
736 RETL = 721, // SparcInstrInfo.td:1165
737 RETRY = 722, // SparcInstrInfo.td:1857
738 RETTri = 723, // SparcInstrInfo.td:1187
739 RETTrr = 724, // SparcInstrInfo.td:1182
740 SAVED = 725, // SparcInstrInfo.td:1860
741 SAVEri = 726, // SparcInstrInfo.td:492
742 SAVErr = 727, // SparcInstrInfo.td:488
743 SDIVCCri = 728, // SparcInstrInfo.td:492
744 SDIVCCrr = 729, // SparcInstrInfo.td:488
745 SDIVXri = 730, // SparcInstrInfo.td:478
746 SDIVXrr = 731, // SparcInstrInfo.td:473
747 SDIVri = 732, // SparcInstrInfo.td:492
748 SDIVrr = 733, // SparcInstrInfo.td:488
749 SETHIi = 734, // SparcInstrInfo.td:834
750 SHA1 = 735, // SparcInstrCrypto.td:68
751 SHA256 = 736, // SparcInstrCrypto.td:71
752 SHA512 = 737, // SparcInstrCrypto.td:75
753 SHUTDOWN = 738, // SparcInstrVIS.td:157
754 SIAM = 739, // SparcInstrVIS.td:169
755 SIR = 740, // SparcInstrInfo.td:1786
756 SLLXri = 741, // SparcInstrFormats.td:299
757 SLLXrr = 742, // SparcInstrFormats.td:295
758 SLLri = 743, // SparcInstrFormats.td:299
759 SLLrr = 744, // SparcInstrFormats.td:295
760 SMACri = 745, // SparcInstrInfo.td:1813
761 SMACrr = 746, // SparcInstrInfo.td:1808
762 SMULCCri = 747, // SparcInstrInfo.td:492
763 SMULCCrr = 748, // SparcInstrInfo.td:488
764 SMULri = 749, // SparcInstrInfo.td:478
765 SMULrr = 750, // SparcInstrInfo.td:473
766 SRAXri = 751, // SparcInstrFormats.td:299
767 SRAXrr = 752, // SparcInstrFormats.td:295
768 SRAri = 753, // SparcInstrFormats.td:299
769 SRArr = 754, // SparcInstrFormats.td:295
770 SRLXri = 755, // SparcInstrFormats.td:299
771 SRLXrr = 756, // SparcInstrFormats.td:295
772 SRLri = 757, // SparcInstrFormats.td:299
773 SRLrr = 758, // SparcInstrFormats.td:295
774 STAri = 759, // SparcInstrInfo.td:559
775 STArr = 760, // SparcInstrInfo.td:553
776 STBAR = 761, // SparcInstrInfo.td:1294
777 STBAri = 762, // SparcInstrInfo.td:559
778 STBArr = 763, // SparcInstrInfo.td:553
779 STBri = 764, // SparcInstrInfo.td:542
780 STBrr = 765, // SparcInstrInfo.td:537
781 STCSRri = 766, // SparcInstrInfo.td:762
782 STCSRrr = 767, // SparcInstrInfo.td:760
783 STCri = 768, // SparcInstrInfo.td:542
784 STCrr = 769, // SparcInstrInfo.td:537
785 STDAri = 770, // SparcInstrInfo.td:559
786 STDArr = 771, // SparcInstrInfo.td:553
787 STDCQri = 772, // SparcInstrInfo.td:768
788 STDCQrr = 773, // SparcInstrInfo.td:766
789 STDCri = 774, // SparcInstrInfo.td:542
790 STDCrr = 775, // SparcInstrInfo.td:537
791 STDFAri = 776, // SparcInstrInfo.td:559
792 STDFArr = 777, // SparcInstrInfo.td:553
793 STDFQri = 778, // SparcInstrInfo.td:783
794 STDFQrr = 779, // SparcInstrInfo.td:781
795 STDFri = 780, // SparcInstrInfo.td:542
796 STDFrr = 781, // SparcInstrInfo.td:537
797 STDri = 782, // SparcInstrInfo.td:542
798 STDrr = 783, // SparcInstrInfo.td:537
799 STFAri = 784, // SparcInstrInfo.td:559
800 STFArr = 785, // SparcInstrInfo.td:553
801 STFSRri = 786, // SparcInstrInfo.td:777
802 STFSRrr = 787, // SparcInstrInfo.td:775
803 STFri = 788, // SparcInstrInfo.td:542
804 STFrr = 789, // SparcInstrInfo.td:537
805 STHAri = 790, // SparcInstrInfo.td:559
806 STHArr = 791, // SparcInstrInfo.td:553
807 STHri = 792, // SparcInstrInfo.td:542
808 STHrr = 793, // SparcInstrInfo.td:537
809 STQFAri = 794, // SparcInstrInfo.td:559
810 STQFArr = 795, // SparcInstrInfo.td:553
811 STQFri = 796, // SparcInstrInfo.td:542
812 STQFrr = 797, // SparcInstrInfo.td:537
813 STXAri = 798, // SparcInstrInfo.td:559
814 STXArr = 799, // SparcInstrInfo.td:553
815 STXFSRri = 800, // SparcInstrInfo.td:790
816 STXFSRrr = 801, // SparcInstrInfo.td:788
817 STXri = 802, // SparcInstrInfo.td:542
818 STXrr = 803, // SparcInstrInfo.td:537
819 STri = 804, // SparcInstrInfo.td:542
820 STrr = 805, // SparcInstrInfo.td:537
821 SUBCCri = 806, // SparcInstrInfo.td:478
822 SUBCCrr = 807, // SparcInstrInfo.td:473
823 SUBCri = 808, // SparcInstrInfo.td:492
824 SUBCrr = 809, // SparcInstrInfo.td:488
825 SUBEri = 810, // SparcInstrInfo.td:478
826 SUBErr = 811, // SparcInstrInfo.td:473
827 SUBri = 812, // SparcInstrInfo.td:478
828 SUBrr = 813, // SparcInstrInfo.td:473
829 SWAPAri = 814, // SparcInstrInfo.td:826
830 SWAPArr = 815, // SparcInstrInfo.td:821
831 SWAPri = 816, // SparcInstrInfo.td:817
832 SWAPrr = 817, // SparcInstrInfo.td:813
833 TA1 = 818, // SparcInstrInfo.td:1228
834 TA3 = 819, // SparcInstrInfo.td:605
835 TA5 = 820, // SparcInstrInfo.td:1225
836 TADDCCTVri = 821, // SparcInstrInfo.td:492
837 TADDCCTVrr = 822, // SparcInstrInfo.td:488
838 TADDCCri = 823, // SparcInstrInfo.td:492
839 TADDCCrr = 824, // SparcInstrInfo.td:488
840 TAIL_CALL = 825, // SparcInstrInfo.td:1594
841 TAIL_CALLri = 826, // SparcInstrInfo.td:1608
842 TICCri = 827, // SparcInstrInfo.td:1214
843 TICCrr = 828, // SparcInstrInfo.td:1210
844 TLS_ADDrr = 829, // SparcInstrInfo.td:1560
845 TLS_CALL = 830, // SparcInstrInfo.td:1577
846 TLS_LDXrr = 831, // SparcInstr64Bit.td:210
847 TLS_LDrr = 832, // SparcInstrInfo.td:1568
848 TRAPri = 833, // SparcInstrInfo.td:1203
849 TRAPrr = 834, // SparcInstrInfo.td:1199
850 TSUBCCTVri = 835, // SparcInstrInfo.td:492
851 TSUBCCTVrr = 836, // SparcInstrInfo.td:488
852 TSUBCCri = 837, // SparcInstrInfo.td:492
853 TSUBCCrr = 838, // SparcInstrInfo.td:488
854 TXCCri = 839, // SparcInstrInfo.td:1214
855 TXCCrr = 840, // SparcInstrInfo.td:1210
856 UDIVCCri = 841, // SparcInstrInfo.td:492
857 UDIVCCrr = 842, // SparcInstrInfo.td:488
858 UDIVXri = 843, // SparcInstrInfo.td:478
859 UDIVXrr = 844, // SparcInstrInfo.td:473
860 UDIVri = 845, // SparcInstrInfo.td:492
861 UDIVrr = 846, // SparcInstrInfo.td:488
862 UMACri = 847, // SparcInstrInfo.td:1823
863 UMACrr = 848, // SparcInstrInfo.td:1818
864 UMULCCri = 849, // SparcInstrInfo.td:492
865 UMULCCrr = 850, // SparcInstrInfo.td:488
866 UMULXHI = 851, // SparcInstrVIS.td:276
867 UMULri = 852, // SparcInstrInfo.td:478
868 UMULrr = 853, // SparcInstrInfo.td:473
869 UNIMP = 854, // SparcInstrInfo.td:1299
870 V9FCMPD = 855, // SparcInstrInfo.td:1723
871 V9FCMPED = 856, // SparcInstrInfo.td:1735
872 V9FCMPEQ = 857, // SparcInstrInfo.td:1738
873 V9FCMPES = 858, // SparcInstrInfo.td:1732
874 V9FCMPQ = 859, // SparcInstrInfo.td:1726
875 V9FCMPS = 860, // SparcInstrInfo.td:1720
876 V9FMOVD_FCC = 861, // SparcInstrInfo.td:1759
877 V9FMOVQ_FCC = 862, // SparcInstrInfo.td:1764
878 V9FMOVS_FCC = 863, // SparcInstrInfo.td:1755
879 V9MOVFCCri = 864, // SparcInstrInfo.td:1751
880 V9MOVFCCrr = 865, // SparcInstrInfo.td:1747
881 WRASRri = 866, // SparcInstrInfo.td:1258
882 WRASRrr = 867, // SparcInstrInfo.td:1255
883 WRPRri = 868, // SparcInstrInfo.td:1907
884 WRPRrr = 869, // SparcInstrInfo.td:1904
885 WRPSRri = 870, // SparcInstrInfo.td:1268
886 WRPSRrr = 871, // SparcInstrInfo.td:1265
887 WRTBRri = 872, // SparcInstrInfo.td:1286
888 WRTBRrr = 873, // SparcInstrInfo.td:1283
889 WRWIMri = 874, // SparcInstrInfo.td:1277
890 WRWIMrr = 875, // SparcInstrInfo.td:1274
891 XMULX = 876, // SparcInstrVIS.td:277
892 XMULXHI = 877, // SparcInstrVIS.td:278
893 XNORCCri = 878, // SparcInstrInfo.td:492
894 XNORCCrr = 879, // SparcInstrInfo.td:488
895 XNORri = 880, // SparcInstrInfo.td:871
896 XNORrr = 881, // SparcInstrInfo.td:867
897 XORCCri = 882, // SparcInstrInfo.td:492
898 XORCCrr = 883, // SparcInstrInfo.td:488
899 XORri = 884, // SparcInstrInfo.td:478
900 XORrr = 885, // SparcInstrInfo.td:473
901 INSTRUCTION_LIST_END = 886
902 };
903 enum RegClassByHwModeUses : uint16_t {
904 sparc_ptr_rc,
905 };
906
907} // namespace llvm::SP
908
909#endif // GET_INSTRINFO_ENUM
910
911#ifdef GET_INSTRINFO_SCHED_ENUM
912#undef GET_INSTRINFO_SCHED_ENUM
913
914namespace llvm::SP::Sched {
915
916 enum {
917 NoInstrModel = 0,
918 IIC_iu_instr = 1,
919 IIC_fpu_normal_instr = 2,
920 IIC_jmp_or_call = 3,
921 IIC_fpu_abs = 4,
922 IIC_fpu_fast_instr = 5,
923 IIC_fpu_divd = 6,
924 IIC_fpu_divs = 7,
925 IIC_fpu_muld = 8,
926 IIC_fpu_muls = 9,
927 IIC_fpu_negs = 10,
928 IIC_fpu_sqrtd = 11,
929 IIC_fpu_sqrts = 12,
930 IIC_fpu_stod = 13,
931 IIC_ldd = 14,
932 IIC_iu_or_fpu_instr = 15,
933 IIC_iu_div = 16,
934 IIC_smac_umac = 17,
935 IIC_iu_smul = 18,
936 IIC_st = 19,
937 IIC_std = 20,
938 IIC_iu_umul = 21,
939 SCHED_LIST_END = 22
940 };
941
942} // namespace llvm::SP::Sched
943
944#endif // GET_INSTRINFO_SCHED_ENUM
945
946#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
947
948namespace llvm {
949
950struct SparcInstrTable {
951 MCInstrDesc Insts[886];
952 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
953 MCPhysReg ImplicitOps[218];
954 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
955 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
956 MCOperandInfo OperandInfo[579];
957};
958} // namespace llvm
959
960#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
961
962#ifdef GET_INSTRINFO_MC_DESC
963#undef GET_INSTRINFO_MC_DESC
964
965namespace llvm {
966
967static_assert((sizeof SparcInstrTable::ImplicitOps + sizeof SparcInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
968static constexpr unsigned SparcOpInfoBase = (sizeof SparcInstrTable::ImplicitOps + sizeof SparcInstrTable::Padding) / sizeof(MCOperandInfo);
969
970extern const SparcInstrTable SparcDescs = {
971 {
972 { 885, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // XORrr
973 { 884, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0, 0x0ULL }, // XORri
974 { 883, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XORCCrr
975 { 882, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XORCCri
976 { 881, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // XNORrr
977 { 880, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XNORri
978 { 879, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XNORCCrr
979 { 878, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XNORCCri
980 { 877, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XMULXHI
981 { 876, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XMULX
982 { 875, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 421, 141, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRWIMrr
983 { 874, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 171, 141, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRWIMri
984 { 873, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 421, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRTBRrr
985 { 872, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 171, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRTBRri
986 { 871, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 421, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPSRrr
987 { 870, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 171, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPSRri
988 { 869, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 576, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPRrr
989 { 868, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 573, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPRri
990 { 867, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 570, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRASRrr
991 { 866, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 567, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRASRri
992 { 865, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 562, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9MOVFCCrr
993 { 864, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 557, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9MOVFCCri
994 { 863, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 552, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FMOVS_FCC
995 { 862, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 547, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FMOVQ_FCC
996 { 861, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 542, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FMOVD_FCC
997 { 860, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 272, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPS
998 { 859, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPQ
999 { 858, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 272, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPES
1000 { 857, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 539, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPEQ
1001 { 856, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 269, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPED
1002 { 855, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 269, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPD
1003 { 854, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UNIMP
1004 { 853, 3, 1, 4, 21, 0, 1, SparcOpInfoBase + 179, 215, 0, 0x0ULL }, // UMULrr
1005 { 852, 3, 1, 4, 21, 0, 1, SparcOpInfoBase + 176, 215, 0, 0x0ULL }, // UMULri
1006 { 851, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0, 0x0ULL }, // UMULXHI
1007 { 850, 3, 1, 4, 21, 0, 2, SparcOpInfoBase + 179, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMULCCrr
1008 { 849, 3, 1, 4, 21, 0, 2, SparcOpInfoBase + 176, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMULCCri
1009 { 848, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 179, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMACrr
1010 { 847, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 176, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMACri
1011 { 846, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 179, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVrr
1012 { 845, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 176, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVri
1013 { 844, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVXrr
1014 { 843, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 418, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVXri
1015 { 842, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 179, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVCCrr
1016 { 841, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 176, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVCCri
1017 { 840, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 444, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TXCCrr
1018 { 839, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 532, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TXCCri
1019 { 838, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCrr
1020 { 837, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCri
1021 { 836, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCTVrr
1022 { 835, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCTVri
1023 { 834, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 444, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAPrr
1024 { 833, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 532, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAPri
1025 { 832, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // TLS_LDrr
1026 { 831, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // TLS_LDXrr
1027 { 830, 2, 0, 4, 3, 1, 0, SparcOpInfoBase + 193, 217, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // TLS_CALL
1028 { 829, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 535, 0, 0, 0x0ULL }, // TLS_ADDrr
1029 { 828, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 444, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TICCrr
1030 { 827, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 532, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TICCri
1031 { 826, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // TAIL_CALLri
1032 { 825, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 192, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // TAIL_CALL
1033 { 824, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCrr
1034 { 823, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCri
1035 { 822, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCTVrr
1036 { 821, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCTVri
1037 { 820, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TA5
1038 { 819, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TA3
1039 { 818, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TA1
1040 { 817, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 528, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // SWAPrr
1041 { 816, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // SWAPri
1042 { 815, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 523, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWAPArr
1043 { 814, 4, 1, 4, 1, 1, 0, SparcOpInfoBase + 519, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWAPAri
1044 { 813, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // SUBrr
1045 { 812, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0, 0x0ULL }, // SUBri
1046 { 811, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 179, 5, 0, 0x0ULL }, // SUBErr
1047 { 810, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 176, 5, 0, 0x0ULL }, // SUBEri
1048 { 809, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SUBCrr
1049 { 808, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SUBCri
1050 { 807, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBCCrr
1051 { 806, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBCCri
1052 { 805, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 454, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STrr
1053 { 804, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 447, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STri
1054 { 803, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 516, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STXrr
1055 { 802, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 509, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STXri
1056 { 801, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 197, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXFSRrr
1057 { 800, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 195, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXFSRri
1058 { 799, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 512, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXArr
1059 { 798, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 509, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXAri
1060 { 797, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 506, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STQFrr
1061 { 796, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 499, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STQFri
1062 { 795, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 502, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STQFArr
1063 { 794, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 499, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STQFAri
1064 { 793, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 454, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STHrr
1065 { 792, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 447, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STHri
1066 { 791, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 450, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STHArr
1067 { 790, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 447, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STHAri
1068 { 789, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 496, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STFrr
1069 { 788, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 489, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STFri
1070 { 787, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 197, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFSRrr
1071 { 786, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 195, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFSRri
1072 { 785, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 492, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFArr
1073 { 784, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 489, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFAri
1074 { 783, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 486, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDrr
1075 { 782, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 463, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDri
1076 { 781, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 483, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDFrr
1077 { 780, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 476, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDFri
1078 { 779, 2, 0, 4, 20, 0, 1, SparcOpInfoBase + 197, 139, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFQrr
1079 { 778, 2, 0, 4, 20, 0, 1, SparcOpInfoBase + 195, 139, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFQri
1080 { 777, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 479, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFArr
1081 { 776, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 476, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFAri
1082 { 775, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 473, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDCrr
1083 { 774, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 470, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDCri
1084 { 773, 2, 0, 4, 20, 1, 0, SparcOpInfoBase + 197, 216, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDCQrr
1085 { 772, 2, 0, 4, 20, 1, 0, SparcOpInfoBase + 195, 216, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDCQri
1086 { 771, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 466, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDArr
1087 { 770, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 463, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDAri
1088 { 769, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 460, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STCrr
1089 { 768, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 457, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STCri
1090 { 767, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 197, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STCSRrr
1091 { 766, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 195, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STCSRri
1092 { 765, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 454, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STBrr
1093 { 764, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 447, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STBri
1094 { 763, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 450, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STBArr
1095 { 762, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 447, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STBAri
1096 { 761, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STBAR
1097 { 760, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 450, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STArr
1098 { 759, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 447, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STAri
1099 { 758, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // SRLrr
1100 { 757, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 444, 0, 0, 0x0ULL }, // SRLri
1101 { 756, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 441, 0, 0, 0x0ULL }, // SRLXrr
1102 { 755, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 438, 0, 0, 0x0ULL }, // SRLXri
1103 { 754, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // SRArr
1104 { 753, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 444, 0, 0, 0x0ULL }, // SRAri
1105 { 752, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 441, 0, 0, 0x0ULL }, // SRAXrr
1106 { 751, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 438, 0, 0, 0x0ULL }, // SRAXri
1107 { 750, 3, 1, 4, 18, 0, 1, SparcOpInfoBase + 179, 215, 0, 0x0ULL }, // SMULrr
1108 { 749, 3, 1, 4, 18, 0, 1, SparcOpInfoBase + 176, 215, 0, 0x0ULL }, // SMULri
1109 { 748, 3, 1, 4, 18, 0, 2, SparcOpInfoBase + 179, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMULCCrr
1110 { 747, 3, 1, 4, 18, 0, 2, SparcOpInfoBase + 176, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMULCCri
1111 { 746, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 179, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMACrr
1112 { 745, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 176, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMACri
1113 { 744, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // SLLrr
1114 { 743, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 444, 0, 0, 0x0ULL }, // SLLri
1115 { 742, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 441, 0, 0, 0x0ULL }, // SLLXrr
1116 { 741, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 438, 0, 0, 0x0ULL }, // SLLXri
1117 { 740, 1, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SIR
1118 { 739, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SIAM
1119 { 738, 0, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHUTDOWN
1120 { 737, 0, 0, 4, 0, 24, 8, SparcOpInfoBase + 1, 177, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHA512
1121 { 736, 0, 0, 4, 0, 12, 4, SparcOpInfoBase + 1, 161, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHA256
1122 { 735, 0, 0, 4, 0, 11, 3, SparcOpInfoBase + 1, 147, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHA1
1123 { 734, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 171, 0, 0, 0x0ULL }, // SETHIi
1124 { 733, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 179, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVrr
1125 { 732, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 176, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVri
1126 { 731, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVXrr
1127 { 730, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 418, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVXri
1128 { 729, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 179, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVCCrr
1129 { 728, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 176, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVCCri
1130 { 727, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SAVErr
1131 { 726, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SAVEri
1132 { 725, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SAVED
1133 { 724, 2, 0, 4, 3, 0, 0, SparcOpInfoBase + 197, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RETTrr
1134 { 723, 2, 0, 4, 3, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RETTri
1135 { 722, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RETRY
1136 { 721, 1, 0, 4, 3, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // RETL
1137 { 720, 1, 0, 4, 3, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RET
1138 { 719, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RESTORErr
1139 { 718, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RESTOREri
1140 { 717, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RESTORED
1141 { 716, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 435, 141, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDWIM
1142 { 715, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 435, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDTBR
1143 { 714, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 435, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDPSR
1144 { 713, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 436, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDPR
1145 { 712, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 435, 139, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDFQ
1146 { 711, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 433, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDASR
1147 { 710, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 421, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PWRPSRrr
1148 { 709, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 171, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PWRPSRri
1149 { 708, 3, 0, 4, 1, 0, 0, SparcOpInfoBase + 430, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHr
1150 { 707, 3, 0, 4, 1, 0, 0, SparcOpInfoBase + 423, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHi
1151 { 706, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 426, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHAr
1152 { 705, 3, 0, 4, 1, 1, 0, SparcOpInfoBase + 423, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHAi
1153 { 704, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 421, 0, 0, 0x0ULL }, // POPCrr
1154 { 703, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 255, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PDISTN
1155 { 702, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PDIST
1156 { 701, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // OTHERW
1157 { 700, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // ORrr
1158 { 699, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0, 0x0ULL }, // ORri
1159 { 698, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // ORNrr
1160 { 697, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORNri
1161 { 696, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORNCCrr
1162 { 695, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORNCCri
1163 { 694, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORCCrr
1164 { 693, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORCCri
1165 { 692, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NORMALW
1166 { 691, 0, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NOP
1167 { 690, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 182, 0, 0, 0x0ULL }, // MULXrr
1168 { 689, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 418, 0, 0, 0x0ULL }, // MULXri
1169 { 688, 3, 1, 4, 1, 2, 2, SparcOpInfoBase + 179, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULSCCrr
1170 { 687, 3, 1, 4, 1, 2, 2, SparcOpInfoBase + 176, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULSCCri
1171 { 686, 1, 0, 4, 0, 52, 52, SparcOpInfoBase + 1, 30, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MPMUL
1172 { 685, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 416, 0, 0, 0x0ULL }, // MOVXTOD
1173 { 684, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 398, 4, 0, 0x0ULL }, // MOVXCCrr
1174 { 683, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 394, 4, 0, 0x0ULL }, // MOVXCCri
1175 { 682, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 414, 0, 0, 0x0ULL }, // MOVWTOS
1176 { 681, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 412, 0, 0, 0x0ULL }, // MOVSTOUW
1177 { 680, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 412, 0, 0, 0x0ULL }, // MOVSTOSW
1178 { 679, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 407, 0, 0, 0x0ULL }, // MOVRrr
1179 { 678, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 402, 0, 0, 0x0ULL }, // MOVRri
1180 { 677, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 398, 4, 0, 0x0ULL }, // MOVICCrr
1181 { 676, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 394, 4, 0, 0x0ULL }, // MOVICCri
1182 { 675, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 398, 3, 0, 0x0ULL }, // MOVFCCrr
1183 { 674, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 394, 3, 0, 0x0ULL }, // MOVFCCri
1184 { 673, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 392, 0, 0, 0x0ULL }, // MOVDTOX
1185 { 672, 1, 0, 4, 0, 52, 52, SparcOpInfoBase + 1, 30, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MONTSQR
1186 { 671, 1, 0, 4, 0, 52, 52, SparcOpInfoBase + 1, 30, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MONTMUL
1187 { 670, 1, 0, 4, 1, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARi
1188 { 669, 0, 0, 4, 0, 10, 8, SparcOpInfoBase + 1, 12, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MD5
1189 { 668, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 390, 0, 0, 0x0ULL }, // LZCNT
1190 { 667, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 329, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDrr
1191 { 666, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 326, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDri
1192 { 665, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 387, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDXrr
1193 { 664, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 384, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDXri
1194 { 663, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 197, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXFSRrr
1195 { 662, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 195, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXFSRri
1196 { 661, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXArr
1197 { 660, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 384, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXAri
1198 { 659, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 329, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUHrr
1199 { 658, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 326, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUHri
1200 { 657, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUHArr
1201 { 656, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 326, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUHAri
1202 { 655, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 329, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUBrr
1203 { 654, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 326, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUBri
1204 { 653, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUBArr
1205 { 652, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 326, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUBAri
1206 { 651, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 387, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSWrr
1207 { 650, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 384, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSWri
1208 { 649, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSWArr
1209 { 648, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 384, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSWAri
1210 { 647, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 329, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBrr
1211 { 646, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 326, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBri
1212 { 645, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBArr
1213 { 644, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 326, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBAri
1214 { 643, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 329, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSHrr
1215 { 642, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 326, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSHri
1216 { 641, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSHArr
1217 { 640, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 326, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSHAri
1218 { 639, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 329, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSBrr
1219 { 638, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 326, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSBri
1220 { 637, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSBArr
1221 { 636, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 326, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSBAri
1222 { 635, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 381, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDQFrr
1223 { 634, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 374, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDQFri
1224 { 633, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 377, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDQFArr
1225 { 632, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 374, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDQFAri
1226 { 631, 3, 1, 4, 15, 0, 0, SparcOpInfoBase + 371, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDFrr
1227 { 630, 3, 1, 4, 15, 0, 0, SparcOpInfoBase + 364, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDFri
1228 { 629, 2, 0, 4, 15, 0, 1, SparcOpInfoBase + 197, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFSRrr
1229 { 628, 2, 0, 4, 15, 0, 1, SparcOpInfoBase + 195, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFSRri
1230 { 627, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 367, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFArr
1231 { 626, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 364, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFAri
1232 { 625, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 361, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDrr
1233 { 624, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 338, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDri
1234 { 623, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 358, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDFrr
1235 { 622, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 351, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDFri
1236 { 621, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 354, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDFArr
1237 { 620, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 351, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDFAri
1238 { 619, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 348, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDCrr
1239 { 618, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 345, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDCri
1240 { 617, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 341, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDArr
1241 { 616, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 338, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDAri
1242 { 615, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 335, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDCrr
1243 { 614, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 332, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDCri
1244 { 613, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 197, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDCSRrr
1245 { 612, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 195, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDCSRri
1246 { 611, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDArr
1247 { 610, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 326, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDAri
1248 { 609, 3, 1, 4, 3, 0, 0, SparcOpInfoBase + 329, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JMPLrr
1249 { 608, 3, 1, 4, 3, 0, 0, SparcOpInfoBase + 326, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JMPLri
1250 { 607, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INVALW
1251 { 606, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // GDOP_LDrr
1252 { 605, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // GDOP_LDXrr
1253 { 604, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 313, 0, 0, 0x0ULL }, // FZEROS
1254 { 603, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 312, 0, 0, 0x0ULL }, // FZERO
1255 { 602, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 261, 0, 0, 0x0ULL }, // FXTOS
1256 { 601, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 263, 0, 0, 0x0ULL }, // FXTOQ
1257 { 600, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0, 0x0ULL }, // FXTOD
1258 { 599, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXORS
1259 { 598, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXOR
1260 { 597, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXNORS
1261 { 596, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXNOR
1262 { 595, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 252, 0, 0, 0x0ULL }, // FSUBS
1263 { 594, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 249, 0, 0, 0x0ULL }, // FSUBQ
1264 { 593, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 189, 0, 0, 0x0ULL }, // FSUBD
1265 { 592, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 265, 0, 0, 0x0ULL }, // FSTOX
1266 { 591, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 267, 0, 0, 0x0ULL }, // FSTOQ
1267 { 590, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 247, 0, 0, 0x0ULL }, // FSTOI
1268 { 589, 2, 1, 4, 13, 0, 0, SparcOpInfoBase + 265, 0, 0, 0x0ULL }, // FSTOD
1269 { 588, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRL32
1270 { 587, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRL16
1271 { 586, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 247, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC2S
1272 { 585, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC2
1273 { 584, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 247, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC1S
1274 { 583, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC1
1275 { 582, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRA32
1276 { 581, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRA16
1277 { 580, 2, 1, 4, 12, 0, 0, SparcOpInfoBase + 247, 0, 0, 0x0ULL }, // FSQRTS
1278 { 579, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FSQRTQ
1279 { 578, 2, 1, 4, 11, 0, 0, SparcOpInfoBase + 240, 0, 0, 0x0ULL }, // FSQRTD
1280 { 577, 3, 1, 4, 8, 0, 0, SparcOpInfoBase + 309, 0, 0, 0x0ULL }, // FSMULD
1281 { 576, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLL32
1282 { 575, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLL16
1283 { 574, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLAS32
1284 { 573, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLAS16
1285 { 572, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 314, 0, 0, 0x0ULL }, // FQTOX
1286 { 571, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 316, 0, 0, 0x0ULL }, // FQTOS
1287 { 570, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 316, 0, 0, 0x0ULL }, // FQTOI
1288 { 569, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 314, 0, 0, 0x0ULL }, // FQTOD
1289 { 568, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB32S
1290 { 567, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB32
1291 { 566, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB16S
1292 { 565, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB16
1293 { 564, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPMERGE
1294 { 563, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPMADDXHI
1295 { 562, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPMADDX
1296 { 561, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD64
1297 { 560, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD32S
1298 { 559, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD32
1299 { 558, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD16S
1300 { 557, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD16
1301 { 556, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 261, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPACKFIX
1302 { 555, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPACK32
1303 { 554, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPACK16
1304 { 553, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORS
1305 { 552, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT2S
1306 { 551, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT2
1307 { 550, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT1S
1308 { 549, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT1
1309 { 548, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FOR
1310 { 547, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 313, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FONES
1311 { 546, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 312, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FONE
1312 { 545, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0, 0x0ULL }, // FNSMULD
1313 { 544, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 247, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT2S
1314 { 543, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT2
1315 { 542, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 247, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT1S
1316 { 541, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT1
1317 { 540, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNORS
1318 { 539, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOR
1319 { 538, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0, 0x0ULL }, // FNMULS
1320 { 537, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0, 0x0ULL }, // FNMULD
1321 { 536, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 275, 0, 0, 0x0ULL }, // FNMSUBS
1322 { 535, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FNMSUBD
1323 { 534, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 275, 0, 0, 0x0ULL }, // FNMADDS
1324 { 533, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FNMADDD
1325 { 532, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0, 0x0ULL }, // FNHADDS
1326 { 531, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0, 0x0ULL }, // FNHADDD
1327 { 530, 2, 1, 4, 10, 0, 0, SparcOpInfoBase + 247, 0, 0, 0x0ULL }, // FNEGS
1328 { 529, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FNEGQ
1329 { 528, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0, 0x0ULL }, // FNEGD
1330 { 527, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNANDS
1331 { 526, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNAND
1332 { 525, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0, 0x0ULL }, // FNADDS
1333 { 524, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0, 0x0ULL }, // FNADDD
1334 { 523, 3, 1, 4, 9, 0, 0, SparcOpInfoBase + 252, 0, 0, 0x0ULL }, // FMULS
1335 { 522, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 249, 0, 0, 0x0ULL }, // FMULQ
1336 { 521, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMULD8ULX16
1337 { 520, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMULD8SUX16
1338 { 519, 3, 1, 4, 8, 0, 0, SparcOpInfoBase + 189, 0, 0, 0x0ULL }, // FMULD
1339 { 518, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8X16AU
1340 { 517, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8X16AL
1341 { 516, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 306, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8X16
1342 { 515, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8ULX16
1343 { 514, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8SUX16
1344 { 513, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 275, 0, 0, 0x0ULL }, // FMSUBS
1345 { 512, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FMSUBD
1346 { 511, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 302, 4, 0, 0x0ULL }, // FMOVS_XCC
1347 { 510, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 302, 4, 0, 0x0ULL }, // FMOVS_ICC
1348 { 509, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 302, 3, 0, 0x0ULL }, // FMOVS_FCC
1349 { 508, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 247, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMOVS
1350 { 507, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 297, 0, 0, 0x0ULL }, // FMOVRS
1351 { 506, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 292, 0, 0, 0x0ULL }, // FMOVRQ
1352 { 505, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 287, 0, 0, 0x0ULL }, // FMOVRD
1353 { 504, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 283, 4, 0, 0x0ULL }, // FMOVQ_XCC
1354 { 503, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 283, 4, 0, 0x0ULL }, // FMOVQ_ICC
1355 { 502, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 283, 3, 0, 0x0ULL }, // FMOVQ_FCC
1356 { 501, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMOVQ
1357 { 500, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 279, 4, 0, 0x0ULL }, // FMOVD_XCC
1358 { 499, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 279, 4, 0, 0x0ULL }, // FMOVD_ICC
1359 { 498, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 279, 3, 0, 0x0ULL }, // FMOVD_FCC
1360 { 497, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMOVD
1361 { 496, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMEAN16
1362 { 495, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 275, 0, 0, 0x0ULL }, // FMADDS
1363 { 494, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FMADDD
1364 { 493, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 197, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSHrr
1365 { 492, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSHri
1366 { 491, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSHW
1367 { 490, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSH
1368 { 489, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 272, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLCMPS
1369 { 488, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 269, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLCMPD
1370 { 487, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 247, 0, 0, 0x0ULL }, // FITOS
1371 { 486, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 267, 0, 0, 0x0ULL }, // FITOQ
1372 { 485, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 265, 0, 0, 0x0ULL }, // FITOD
1373 { 484, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0, 0x0ULL }, // FHSUBS
1374 { 483, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0, 0x0ULL }, // FHSUBD
1375 { 482, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0, 0x0ULL }, // FHADDS
1376 { 481, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0, 0x0ULL }, // FHADDD
1377 { 480, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 265, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FEXPAND
1378 { 479, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0, 0x0ULL }, // FDTOX
1379 { 478, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 261, 0, 0, 0x0ULL }, // FDTOS
1380 { 477, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 263, 0, 0, 0x0ULL }, // FDTOQ
1381 { 476, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 261, 0, 0, 0x0ULL }, // FDTOI
1382 { 475, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 258, 0, 0, 0x0ULL }, // FDMULQ
1383 { 474, 3, 1, 4, 7, 0, 0, SparcOpInfoBase + 252, 0, 0, 0x0ULL }, // FDIVS
1384 { 473, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 249, 0, 0, 0x0ULL }, // FDIVQ
1385 { 472, 3, 1, 4, 6, 0, 0, SparcOpInfoBase + 189, 0, 0, 0x0ULL }, // FDIVD
1386 { 471, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 247, 3, 0, 0x0ULL }, // FCMPS_V9
1387 { 470, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 247, 3, 0, 0x0ULL }, // FCMPS
1388 { 469, 2, 0, 4, 0, 0, 1, SparcOpInfoBase + 245, 3, 0, 0x0ULL }, // FCMPQ_V9
1389 { 468, 2, 0, 4, 0, 0, 1, SparcOpInfoBase + 245, 3, 0, 0x0ULL }, // FCMPQ
1390 { 467, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 255, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPNE32
1391 { 466, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 255, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPNE16
1392 { 465, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 255, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPLE32
1393 { 464, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 255, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPLE16
1394 { 463, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 255, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPGT32
1395 { 462, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 255, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPGT16
1396 { 461, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 255, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPEQ32
1397 { 460, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 255, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPEQ16
1398 { 459, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 240, 3, 0, 0x0ULL }, // FCMPD_V9
1399 { 458, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 240, 3, 0, 0x0ULL }, // FCMPD
1400 { 457, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCHKSM16
1401 { 456, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 193, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // FBCOND_V9
1402 { 455, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 193, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // FBCONDA_V9
1403 { 454, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 193, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FBCONDA
1404 { 453, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 193, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // FBCOND
1405 { 452, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDS
1406 { 451, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT2S
1407 { 450, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT2
1408 { 449, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 252, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT1S
1409 { 448, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT1
1410 { 447, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAND
1411 { 446, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FALIGNADATA
1412 { 445, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 252, 0, 0, 0x0ULL }, // FADDS
1413 { 444, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 249, 0, 0, 0x0ULL }, // FADDQ
1414 { 443, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 189, 0, 0, 0x0ULL }, // FADDD
1415 { 442, 2, 1, 4, 4, 0, 0, SparcOpInfoBase + 247, 0, 0, 0x0ULL }, // FABSS
1416 { 441, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FABSQ
1417 { 440, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0, 0x0ULL }, // FABSD
1418 { 439, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8N
1419 { 438, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8LN
1420 { 437, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8L
1421 { 436, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8
1422 { 435, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32N
1423 { 434, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32LN
1424 { 433, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32L
1425 { 432, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32
1426 { 431, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16N
1427 { 430, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16LN
1428 { 429, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16L
1429 { 428, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16
1430 { 427, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DONE
1431 { 426, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_ROUND
1432 { 425, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 242, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_KEXPAND
1433 { 424, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_IP
1434 { 423, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_IIP
1435 { 422, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CXBCONDrr
1436 { 421, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 232, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CXBCONDri
1437 { 420, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CWBCONDrr
1438 { 419, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 232, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CWBCONDri
1439 { 418, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CRC32C
1440 { 417, 2, 0, 4, 0, 0, 0, SparcOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CPBCONDA
1441 { 416, 2, 0, 4, 0, 0, 0, SparcOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // CPBCOND
1442 { 415, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 231, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMASK8
1443 { 414, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 231, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMASK32
1444 { 413, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 231, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMASK16
1445 { 412, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 226, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // CASXArr
1446 { 411, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 222, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CASXAri
1447 { 410, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 217, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // CASArr
1448 { 409, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 213, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CASAri
1449 { 408, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CAMELLIA_FLI
1450 { 407, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CAMELLIA_FL
1451 { 406, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CAMELLIA_F
1452 { 405, 3, 0, 4, 1, 1, 1, SparcOpInfoBase + 210, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CALLrri
1453 { 404, 2, 0, 4, 3, 1, 1, SparcOpInfoBase + 197, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // CALLrr
1454 { 403, 3, 0, 4, 1, 1, 1, SparcOpInfoBase + 207, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CALLrii
1455 { 402, 2, 0, 4, 3, 1, 1, SparcOpInfoBase + 195, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // CALLri
1456 { 401, 2, 0, 4, 0, 1, 1, SparcOpInfoBase + 205, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CALLi
1457 { 400, 1, 0, 4, 3, 1, 1, SparcOpInfoBase + 192, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // CALL
1458 { 399, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BSHUFFLE
1459 { 398, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPXCCNT
1460 { 397, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPXCCANT
1461 { 396, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPXCCA
1462 { 395, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BPXCC
1463 { 394, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 202, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPRNT
1464 { 393, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 202, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPRANT
1465 { 392, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 202, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPRA
1466 { 391, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 202, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BPR
1467 { 390, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPICCNT
1468 { 389, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPICCANT
1469 { 388, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPICCA
1470 { 387, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BPICC
1471 { 386, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 199, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCCNT
1472 { 385, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 199, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCCANT
1473 { 384, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 199, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCCA
1474 { 383, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 199, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCC
1475 { 382, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BMASK
1476 { 381, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 197, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BINDrr
1477 { 380, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BINDri
1478 { 379, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BCONDA
1479 { 378, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BCOND
1480 { 377, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 192, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BA
1481 { 376, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ARRAY8
1482 { 375, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ARRAY32
1483 { 374, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ARRAY16
1484 { 373, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // ANDrr
1485 { 372, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0, 0x0ULL }, // ANDri
1486 { 371, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // ANDNrr
1487 { 370, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDNri
1488 { 369, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDNCCrr
1489 { 368, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDNCCri
1490 { 367, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDCCrr
1491 { 366, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDCCri
1492 { 365, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALLCLEAN
1493 { 364, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALIGNADDRL
1494 { 363, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 182, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALIGNADDR
1495 { 362, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_KEXPAND2
1496 { 361, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 155, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_KEXPAND1
1497 { 360, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_KEXPAND0
1498 { 359, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND23_LAST
1499 { 358, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND23
1500 { 357, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND01_LAST
1501 { 356, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND01
1502 { 355, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND23_LAST
1503 { 354, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND23
1504 { 353, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND01_LAST
1505 { 352, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND01
1506 { 351, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 179, 0, 0, 0x0ULL }, // ADDrr
1507 { 350, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 176, 0, 0, 0x0ULL }, // ADDri
1508 { 349, 3, 1, 4, 0, 1, 1, SparcOpInfoBase + 182, 5, 0, 0x0ULL }, // ADDXCCC
1509 { 348, 3, 1, 4, 0, 1, 0, SparcOpInfoBase + 182, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDXC
1510 { 347, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 179, 5, 0, 0x0ULL }, // ADDErr
1511 { 346, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 176, 5, 0, 0x0ULL }, // ADDEri
1512 { 345, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 179, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDCrr
1513 { 344, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 176, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDCri
1514 { 343, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 179, 4, 0, 0x0ULL }, // ADDCCrr
1515 { 342, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 176, 4, 0, 0x0ULL }, // ADDCCri
1516 { 341, 0, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V8BAR
1517 { 340, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 173, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SETX
1518 { 339, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 171, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SETSW
1519 { 338, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 171, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SET
1520 { 337, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 167, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_QFP_XCC
1521 { 336, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 167, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_QFP_ICC
1522 { 335, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 167, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_QFP_FCC
1523 { 334, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 163, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_Int_XCC
1524 { 333, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 163, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_Int_ICC
1525 { 332, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 163, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_Int_FCC
1526 { 331, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 159, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_FP_XCC
1527 { 330, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 159, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_FP_ICC
1528 { 329, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 159, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_FP_FCC
1529 { 328, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 155, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_DFP_XCC
1530 { 327, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 155, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_DFP_ICC
1531 { 326, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 155, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_DFP_FCC
1532 { 325, 1, 1, 4, 0, 0, 1, SparcOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // GETPCX
1533 { 324, 2, 0, 4, 0, 1, 1, SparcOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ADJCALLSTACKUP
1534 { 323, 2, 0, 4, 0, 1, 1, SparcOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ADJCALLSTACKDOWN
1535 { 322, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX
1536 { 321, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX
1537 { 320, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN
1538 { 319, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX
1539 { 318, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN
1540 { 317, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX
1541 { 316, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR
1542 { 315, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR
1543 { 314, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND
1544 { 313, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL
1545 { 312, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD
1546 { 311, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1547 { 310, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1548 { 309, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN
1549 { 308, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX
1550 { 307, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL
1551 { 306, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD
1552 { 305, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1553 { 304, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1554 { 303, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP
1555 { 302, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP
1556 { 301, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP
1557 { 300, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO
1558 { 299, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET
1559 { 298, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE
1560 { 297, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE
1561 { 296, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY
1562 { 295, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 145, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1563 { 294, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1564 { 293, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP
1565 { 292, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT
1566 { 291, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA
1567 { 290, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM
1568 { 289, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV
1569 { 288, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL
1570 { 287, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB
1571 { 286, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD
1572 { 285, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE
1573 { 284, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE
1574 { 283, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC
1575 { 282, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE
1576 { 281, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR
1577 { 280, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST
1578 { 279, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT
1579 { 278, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT
1580 { 277, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR
1581 { 276, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT
1582 { 275, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH
1583 { 274, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH
1584 { 273, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH
1585 { 272, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2
1586 { 271, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN
1587 { 270, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN
1588 { 269, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS
1589 { 268, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN
1590 { 267, 3, 2, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS
1591 { 266, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN
1592 { 265, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS
1593 { 264, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL
1594 { 263, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE
1595 { 262, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP
1596 { 261, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP
1597 { 260, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS
1598 { 259, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
1599 { 258, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ
1600 { 257, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
1601 { 256, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ
1602 { 255, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS
1603 { 254, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR
1604 { 253, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR
1605 { 252, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR
1606 { 251, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1607 { 250, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT
1608 { 249, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1609 { 248, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR
1610 { 247, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE
1611 { 246, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 127, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT
1612 { 245, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR
1613 { 244, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND
1614 { 243, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND
1615 { 242, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS
1616 { 241, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX
1617 { 240, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN
1618 { 239, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX
1619 { 238, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN
1620 { 237, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK
1621 { 236, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD
1622 { 235, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING
1623 { 234, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING
1624 { 233, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE
1625 { 232, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE
1626 { 231, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE
1627 { 230, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV
1628 { 229, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV
1629 { 228, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV
1630 { 227, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM
1631 { 226, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM
1632 { 225, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM
1633 { 224, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM
1634 { 223, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE
1635 { 222, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE
1636 { 221, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM
1637 { 220, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM
1638 { 219, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE
1639 { 218, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS
1640 { 217, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN
1641 { 216, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS
1642 { 215, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT
1643 { 214, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT
1644 { 213, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP
1645 { 212, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP
1646 { 211, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI
1647 { 210, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI
1648 { 209, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC
1649 { 208, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT
1650 { 207, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG
1651 { 206, 3, 2, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP
1652 { 205, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP
1653 { 204, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10
1654 { 203, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2
1655 { 202, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG
1656 { 201, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10
1657 { 200, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2
1658 { 199, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP
1659 { 198, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI
1660 { 197, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW
1661 { 196, 3, 2, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF
1662 { 195, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM
1663 { 194, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV
1664 { 193, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD
1665 { 192, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA
1666 { 191, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL
1667 { 190, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB
1668 { 189, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD
1669 { 188, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT
1670 { 187, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT
1671 { 186, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX
1672 { 185, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX
1673 { 184, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT
1674 { 183, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT
1675 { 182, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX
1676 { 181, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX
1677 { 180, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT
1678 { 179, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT
1679 { 178, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT
1680 { 177, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT
1681 { 176, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT
1682 { 175, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT
1683 { 174, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH
1684 { 173, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH
1685 { 172, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO
1686 { 171, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO
1687 { 170, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE
1688 { 169, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO
1689 { 168, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE
1690 { 167, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO
1691 { 166, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE
1692 { 165, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO
1693 { 164, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE
1694 { 163, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO
1695 { 162, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT
1696 { 161, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP
1697 { 160, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP
1698 { 159, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP
1699 { 158, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP
1700 { 157, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL
1701 { 156, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR
1702 { 155, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR
1703 { 154, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL
1704 { 153, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR
1705 { 152, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR
1706 { 151, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL
1707 { 150, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT
1708 { 149, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG
1709 { 148, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT
1710 { 147, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG
1711 { 146, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART
1712 { 145, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT
1713 { 144, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT
1714 { 143, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U
1715 { 142, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U
1716 { 141, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S
1717 { 140, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC
1718 { 139, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT
1719 { 138, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1720 { 137, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1721 { 136, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1722 { 135, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC
1723 { 134, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START
1724 { 133, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT
1725 { 132, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND
1726 { 131, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH
1727 { 130, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 24, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE
1728 { 129, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1729 { 128, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1730 { 127, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1731 { 126, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1732 { 125, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1733 { 124, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1734 { 123, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN
1735 { 122, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX
1736 { 121, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB
1737 { 120, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD
1738 { 119, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN
1739 { 118, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX
1740 { 117, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN
1741 { 116, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX
1742 { 115, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR
1743 { 114, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR
1744 { 113, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND
1745 { 112, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND
1746 { 111, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB
1747 { 110, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD
1748 { 109, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG
1749 { 108, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG
1750 { 107, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 85, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1751 { 106, 5, 1, 0, 0, 0, 0, SparcOpInfoBase + 80, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE
1752 { 105, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE
1753 { 104, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1754 { 103, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD
1755 { 102, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD
1756 { 101, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD
1757 { 100, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD
1758 { 99, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD
1759 { 98, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER
1760 { 97, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER
1761 { 96, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1762 { 95, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT
1763 { 94, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT
1764 { 93, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND
1765 { 92, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC
1766 { 91, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1767 { 90, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1768 { 89, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE
1769 { 88, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST
1770 { 87, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR
1771 { 86, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT
1772 { 85, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS
1773 { 84, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1774 { 83, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR
1775 { 82, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES
1776 { 81, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT
1777 { 80, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES
1778 { 79, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT
1779 { 78, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL
1780 { 77, 5, 1, 0, 0, 0, 0, SparcOpInfoBase + 56, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1781 { 76, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE
1782 { 75, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX
1783 { 74, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI
1784 { 73, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF
1785 { 72, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL
1786 { 71, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR
1787 { 70, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL
1788 { 69, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR
1789 { 68, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU
1790 { 67, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS
1791 { 66, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR
1792 { 65, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR
1793 { 64, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND
1794 { 63, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM
1795 { 62, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM
1796 { 61, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM
1797 { 60, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM
1798 { 59, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV
1799 { 58, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV
1800 { 57, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL
1801 { 56, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB
1802 { 55, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD
1803 { 54, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN
1804 { 53, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT
1805 { 52, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT
1806 { 51, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1807 { 50, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1808 { 49, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1809 { 48, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1810 { 47, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE
1811 { 46, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1812 { 45, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER
1813 { 44, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE
1814 { 43, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1815 { 42, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 40, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17133
1816 { 41, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 38, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17132
1817 { 40, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL
1818 { 39, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1819 { 38, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET
1820 { 37, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1821 { 36, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP
1822 { 35, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP
1823 { 34, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE
1824 { 33, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT
1825 { 32, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 33, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17131
1826 { 31, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP
1827 { 30, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_14301
1828 { 29, 6, 1, 0, 0, 0, 0, SparcOpInfoBase + 26, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT
1829 { 28, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL
1830 { 27, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP
1831 { 26, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE
1832 { 25, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE
1833 { 24, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END
1834 { 23, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START
1835 { 22, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE
1836 { 21, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK
1837 { 20, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY
1838 { 19, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE
1839 { 18, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL
1840 { 17, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI
1841 { 16, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF
1842 { 15, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST
1843 { 14, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE
1844 { 13, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS
1845 { 12, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG
1846 { 11, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF
1847 { 10, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF
1848 { 9, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG
1849 { 8, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG
1850 { 7, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL
1851 { 6, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL
1852 { 5, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL
1853 { 4, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL
1854 { 3, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION
1855 { 2, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR
1856 { 1, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM
1857 { 0, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI
1858 }, {
1859 /* 0 */
1860 /* 0 */ SP::O6, SP::O6,
1861 /* 2 */ SP::O7,
1862 /* 3 */ SP::FCC0,
1863 /* 4 */ SP::ICC,
1864 /* 5 */ SP::ICC, SP::ICC,
1865 /* 7 */ SP::O6, SP::O7,
1866 /* 9 */ SP::ASR3,
1867 /* 10 */ SP::CPSR,
1868 /* 11 */ SP::FSR,
1869 /* 12 */ SP::D0, SP::D1, SP::D2, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7,
1870 /* 30 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5,
1871 /* 134 */ SP::Y, SP::ICC, SP::Y, SP::ICC,
1872 /* 138 */ SP::PSR,
1873 /* 139 */ SP::FQ,
1874 /* 140 */ SP::TBR,
1875 /* 141 */ SP::WIM,
1876 /* 142 */ SP::Y, SP::Y, SP::ICC,
1877 /* 145 */ SP::Y, SP::Y,
1878 /* 147 */ SP::D0, SP::D1, SP::D2, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D0, SP::D1, SP::D2,
1879 /* 161 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D0, SP::D1, SP::D2, SP::D3,
1880 /* 177 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7,
1881 /* 209 */ SP::Y, SP::ASR18, SP::Y, SP::ASR18,
1882 /* 213 */ SP::Y, SP::ICC,
1883 /* 215 */ SP::Y,
1884 /* 216 */ SP::CPQ,
1885 /* 217 */ SP::O6,
1886 }, {
1887 0
1888 }, {
1889 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1890 /* 1 */
1891 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1892 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1893 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1894 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1895 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1896 /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1897 /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1898 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1899 /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1900 /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1901 /* 32 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
1902 /* 33 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1903 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1904 /* 38 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1905 /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1906 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1907 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1908 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1909 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1910 /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1911 /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1912 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1913 /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1914 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1915 /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1916 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1917 /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1918 /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1919 /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1920 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1921 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1922 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1923 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1924 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1925 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1926 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1927 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1928 /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1929 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1930 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1931 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1932 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1933 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1934 /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1935 /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1936 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1937 /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1938 /* 155 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1939 /* 159 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1940 /* 163 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1941 /* 167 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1942 /* 171 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1943 /* 173 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1944 /* 176 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1945 /* 179 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1946 /* 182 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1947 /* 185 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1948 /* 189 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1949 /* 192 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },
1950 /* 193 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1951 /* 195 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1952 /* 197 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
1953 /* 199 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1954 /* 202 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1955 /* 205 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1956 /* 207 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1957 /* 210 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1958 /* 213 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1959 /* 217 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1960 /* 222 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1961 /* 226 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1962 /* 231 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1963 /* 232 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1964 /* 236 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1965 /* 240 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1966 /* 242 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1967 /* 245 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1968 /* 247 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1969 /* 249 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1970 /* 252 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1971 /* 255 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1972 /* 258 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1973 /* 261 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1974 /* 263 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1975 /* 265 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1976 /* 267 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1977 /* 269 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1978 /* 272 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1979 /* 275 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1980 /* 279 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1981 /* 283 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1982 /* 287 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1983 /* 292 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1984 /* 297 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1985 /* 302 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1986 /* 306 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1987 /* 309 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1988 /* 312 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1989 /* 313 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1990 /* 314 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1991 /* 316 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1992 /* 318 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1993 /* 322 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1994 /* 326 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1995 /* 329 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
1996 /* 332 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1997 /* 335 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
1998 /* 338 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1999 /* 341 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2000 /* 345 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2001 /* 348 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2002 /* 351 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2003 /* 354 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2004 /* 358 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2005 /* 361 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2006 /* 364 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2007 /* 367 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2008 /* 371 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2009 /* 374 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2010 /* 377 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2011 /* 381 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2012 /* 384 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2013 /* 387 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2014 /* 390 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2015 /* 392 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2016 /* 394 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2017 /* 398 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2018 /* 402 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2019 /* 407 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2020 /* 412 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2021 /* 414 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2022 /* 416 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2023 /* 418 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
2024 /* 421 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2025 /* 423 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2026 /* 426 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2027 /* 430 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2028 /* 433 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2029 /* 435 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2030 /* 436 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2031 /* 438 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2032 /* 441 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2033 /* 444 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2034 /* 447 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2035 /* 450 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2036 /* 454 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2037 /* 457 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2038 /* 460 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2039 /* 463 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2040 /* 466 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2041 /* 470 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2042 /* 473 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2043 /* 476 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2044 /* 479 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2045 /* 483 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2046 /* 486 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2047 /* 489 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2048 /* 492 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2049 /* 496 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2050 /* 499 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2051 /* 502 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2052 /* 506 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2053 /* 509 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2054 /* 512 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2055 /* 516 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2056 /* 519 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
2057 /* 523 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
2058 /* 528 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
2059 /* 532 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2060 /* 535 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2061 /* 539 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2062 /* 542 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2063 /* 547 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2064 /* 552 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2065 /* 557 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2066 /* 562 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2067 /* 567 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
2068 /* 570 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2069 /* 573 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
2070 /* 576 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2071 }
2072};
2073
2074
2075#ifdef __GNUC__
2076#pragma GCC diagnostic push
2077#pragma GCC diagnostic ignored "-Woverlength-strings"
2078#endif
2079extern const char SparcInstrNameData[] = {
2080 /* 0 */ "G_FLOG10\000"
2081 /* 9 */ "G_FEXP10\000"
2082 /* 18 */ "AES_KEXPAND0\000"
2083 /* 31 */ "AES_DROUND01\000"
2084 /* 44 */ "AES_EROUND01\000"
2085 /* 57 */ "SHA1\000"
2086 /* 62 */ "TA1\000"
2087 /* 66 */ "FSRC1\000"
2088 /* 72 */ "AES_KEXPAND1\000"
2089 /* 85 */ "FANDNOT1\000"
2090 /* 94 */ "FNOT1\000"
2091 /* 100 */ "FORNOT1\000"
2092 /* 108 */ "SHA512\000"
2093 /* 115 */ "FSRA32\000"
2094 /* 122 */ "FPSUB32\000"
2095 /* 130 */ "FPADD32\000"
2096 /* 138 */ "EDGE32\000"
2097 /* 145 */ "FCMPLE32\000"
2098 /* 154 */ "FCMPNE32\000"
2099 /* 163 */ "FPACK32\000"
2100 /* 171 */ "CMASK32\000"
2101 /* 179 */ "FSLL32\000"
2102 /* 186 */ "FSRL32\000"
2103 /* 193 */ "FCMPEQ32\000"
2104 /* 202 */ "FSLAS32\000"
2105 /* 210 */ "FCMPGT32\000"
2106 /* 219 */ "ARRAY32\000"
2107 /* 227 */ "FSRC2\000"
2108 /* 233 */ "AES_KEXPAND2\000"
2109 /* 246 */ "G_FLOG2\000"
2110 /* 254 */ "G_FATAN2\000"
2111 /* 263 */ "G_FEXP2\000"
2112 /* 271 */ "FANDNOT2\000"
2113 /* 280 */ "FNOT2\000"
2114 /* 286 */ "FORNOT2\000"
2115 /* 294 */ "AES_DROUND23\000"
2116 /* 307 */ "AES_EROUND23\000"
2117 /* 320 */ "TA3\000"
2118 /* 324 */ "FPADD64\000"
2119 /* 332 */ "TA5\000"
2120 /* 336 */ "MD5\000"
2121 /* 340 */ "FSRA16\000"
2122 /* 347 */ "FPSUB16\000"
2123 /* 355 */ "FPADD16\000"
2124 /* 363 */ "EDGE16\000"
2125 /* 370 */ "FCMPLE16\000"
2126 /* 379 */ "FCMPNE16\000"
2127 /* 388 */ "FPACK16\000"
2128 /* 396 */ "CMASK16\000"
2129 /* 404 */ "FSLL16\000"
2130 /* 411 */ "FSRL16\000"
2131 /* 418 */ "FCHKSM16\000"
2132 /* 427 */ "FMEAN16\000"
2133 /* 435 */ "FCMPEQ16\000"
2134 /* 444 */ "FSLAS16\000"
2135 /* 452 */ "FCMPGT16\000"
2136 /* 461 */ "FMUL8X16\000"
2137 /* 470 */ "FMULD8ULX16\000"
2138 /* 482 */ "FMUL8ULX16\000"
2139 /* 493 */ "FMULD8SUX16\000"
2140 /* 505 */ "FMUL8SUX16\000"
2141 /* 516 */ "ARRAY16\000"
2142 /* 524 */ "SHA256\000"
2143 /* 531 */ "EDGE8\000"
2144 /* 537 */ "CMASK8\000"
2145 /* 544 */ "ARRAY8\000"
2146 /* 551 */ "FBCONDA_V9\000"
2147 /* 562 */ "FBCOND_V9\000"
2148 /* 572 */ "FCMPD_V9\000"
2149 /* 581 */ "FCMPQ_V9\000"
2150 /* 590 */ "FCMPS_V9\000"
2151 /* 599 */ "BA\000"
2152 /* 602 */ "BPFCCA\000"
2153 /* 609 */ "BPICCA\000"
2154 /* 616 */ "BPXCCA\000"
2155 /* 623 */ "FBCONDA\000"
2156 /* 631 */ "CPBCONDA\000"
2157 /* 640 */ "G_FMA\000"
2158 /* 646 */ "G_STRICT_FMA\000"
2159 /* 659 */ "BPRA\000"
2160 /* 664 */ "FALIGNADATA\000"
2161 /* 676 */ "G_FSUB\000"
2162 /* 683 */ "G_STRICT_FSUB\000"
2163 /* 697 */ "G_ATOMICRMW_FSUB\000"
2164 /* 714 */ "G_SUB\000"
2165 /* 720 */ "G_ATOMICRMW_SUB\000"
2166 /* 736 */ "CRC32C\000"
2167 /* 743 */ "ADDXCCC\000"
2168 /* 751 */ "BPFCC\000"
2169 /* 757 */ "V9FMOVD_FCC\000"
2170 /* 769 */ "SELECT_CC_DFP_FCC\000"
2171 /* 787 */ "SELECT_CC_QFP_FCC\000"
2172 /* 805 */ "SELECT_CC_FP_FCC\000"
2173 /* 822 */ "V9FMOVQ_FCC\000"
2174 /* 834 */ "V9FMOVS_FCC\000"
2175 /* 846 */ "SELECT_CC_Int_FCC\000"
2176 /* 864 */ "BPICC\000"
2177 /* 870 */ "FMOVD_ICC\000"
2178 /* 880 */ "SELECT_CC_DFP_ICC\000"
2179 /* 898 */ "SELECT_CC_QFP_ICC\000"
2180 /* 916 */ "SELECT_CC_FP_ICC\000"
2181 /* 933 */ "FMOVQ_ICC\000"
2182 /* 943 */ "FMOVS_ICC\000"
2183 /* 953 */ "SELECT_CC_Int_ICC\000"
2184 /* 971 */ "BPXCC\000"
2185 /* 977 */ "FMOVD_XCC\000"
2186 /* 987 */ "SELECT_CC_DFP_XCC\000"
2187 /* 1005 */ "SELECT_CC_QFP_XCC\000"
2188 /* 1023 */ "SELECT_CC_FP_XCC\000"
2189 /* 1040 */ "FMOVQ_XCC\000"
2190 /* 1050 */ "FMOVS_XCC\000"
2191 /* 1060 */ "SELECT_CC_Int_XCC\000"
2192 /* 1078 */ "G_INTRINSIC\000"
2193 /* 1090 */ "G_FPTRUNC\000"
2194 /* 1100 */ "G_INTRINSIC_TRUNC\000"
2195 /* 1118 */ "G_TRUNC\000"
2196 /* 1126 */ "G_BUILD_VECTOR_TRUNC\000"
2197 /* 1147 */ "G_DYN_STACKALLOC\000"
2198 /* 1164 */ "ADDXC\000"
2199 /* 1170 */ "G_FMAD\000"
2200 /* 1177 */ "G_INDEXED_SEXTLOAD\000"
2201 /* 1196 */ "G_SEXTLOAD\000"
2202 /* 1207 */ "G_INDEXED_ZEXTLOAD\000"
2203 /* 1226 */ "G_ZEXTLOAD\000"
2204 /* 1237 */ "G_INDEXED_LOAD\000"
2205 /* 1252 */ "G_LOAD\000"
2206 /* 1259 */ "FSUBD\000"
2207 /* 1265 */ "FHSUBD\000"
2208 /* 1272 */ "FMSUBD\000"
2209 /* 1279 */ "FNMSUBD\000"
2210 /* 1287 */ "G_VECREDUCE_FADD\000"
2211 /* 1304 */ "G_FADD\000"
2212 /* 1311 */ "G_VECREDUCE_SEQ_FADD\000"
2213 /* 1332 */ "G_STRICT_FADD\000"
2214 /* 1346 */ "G_ATOMICRMW_FADD\000"
2215 /* 1363 */ "G_VECREDUCE_ADD\000"
2216 /* 1379 */ "G_ADD\000"
2217 /* 1385 */ "G_PTR_ADD\000"
2218 /* 1395 */ "G_ATOMICRMW_ADD\000"
2219 /* 1411 */ "FADDD\000"
2220 /* 1417 */ "FHADDD\000"
2221 /* 1424 */ "FNHADDD\000"
2222 /* 1432 */ "FMADDD\000"
2223 /* 1439 */ "FNMADDD\000"
2224 /* 1447 */ "FNADDD\000"
2225 /* 1454 */ "V9FCMPED\000"
2226 /* 1463 */ "RESTORED\000"
2227 /* 1472 */ "SAVED\000"
2228 /* 1478 */ "FNEGD\000"
2229 /* 1484 */ "FMULD\000"
2230 /* 1490 */ "FNMULD\000"
2231 /* 1497 */ "FSMULD\000"
2232 /* 1504 */ "FNSMULD\000"
2233 /* 1512 */ "FAND\000"
2234 /* 1517 */ "FNAND\000"
2235 /* 1523 */ "G_ATOMICRMW_NAND\000"
2236 /* 1540 */ "FEXPAND\000"
2237 /* 1548 */ "DES_KEXPAND\000"
2238 /* 1560 */ "G_VECREDUCE_AND\000"
2239 /* 1576 */ "G_AND\000"
2240 /* 1582 */ "G_ATOMICRMW_AND\000"
2241 /* 1598 */ "LIFETIME_END\000"
2242 /* 1611 */ "FBCOND\000"
2243 /* 1618 */ "CPBCOND\000"
2244 /* 1626 */ "G_BRCOND\000"
2245 /* 1635 */ "G_ATOMICRMW_USUB_COND\000"
2246 /* 1657 */ "G_LLROUND\000"
2247 /* 1667 */ "G_LROUND\000"
2248 /* 1676 */ "G_INTRINSIC_ROUND\000"
2249 /* 1694 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
2250 /* 1720 */ "DES_ROUND\000"
2251 /* 1730 */ "FITOD\000"
2252 /* 1736 */ "FQTOD\000"
2253 /* 1742 */ "FSTOD\000"
2254 /* 1748 */ "FXTOD\000"
2255 /* 1754 */ "MOVXTOD\000"
2256 /* 1762 */ "V9FCMPD\000"
2257 /* 1770 */ "FLCMPD\000"
2258 /* 1777 */ "LOAD_STACK_GUARD\000"
2259 /* 1794 */ "FMOVRD\000"
2260 /* 1801 */ "FABSD\000"
2261 /* 1807 */ "FSQRTD\000"
2262 /* 1814 */ "FDIVD\000"
2263 /* 1820 */ "FMOVD\000"
2264 /* 1826 */ "PSEUDO_PROBE\000"
2265 /* 1839 */ "G_SSUBE\000"
2266 /* 1847 */ "G_USUBE\000"
2267 /* 1855 */ "G_FENCE\000"
2268 /* 1863 */ "ARITH_FENCE\000"
2269 /* 1875 */ "REG_SEQUENCE\000"
2270 /* 1888 */ "G_SADDE\000"
2271 /* 1896 */ "G_UADDE\000"
2272 /* 1904 */ "G_GET_FPMODE\000"
2273 /* 1917 */ "G_RESET_FPMODE\000"
2274 /* 1932 */ "G_SET_FPMODE\000"
2275 /* 1945 */ "G_FMINNUM_IEEE\000"
2276 /* 1960 */ "G_FMAXNUM_IEEE\000"
2277 /* 1975 */ "FPMERGE\000"
2278 /* 1983 */ "G_VSCALE\000"
2279 /* 1992 */ "G_JUMP_TABLE\000"
2280 /* 2005 */ "BUNDLE\000"
2281 /* 2012 */ "BSHUFFLE\000"
2282 /* 2021 */ "G_MEMCPY_INLINE\000"
2283 /* 2037 */ "DONE\000"
2284 /* 2042 */ "FONE\000"
2285 /* 2047 */ "RELOC_NONE\000"
2286 /* 2058 */ "LOCAL_ESCAPE\000"
2287 /* 2071 */ "G_STACKRESTORE\000"
2288 /* 2086 */ "G_INDEXED_STORE\000"
2289 /* 2102 */ "G_STORE\000"
2290 /* 2110 */ "G_BITREVERSE\000"
2291 /* 2123 */ "FAKE_USE\000"
2292 /* 2132 */ "DBG_VALUE\000"
2293 /* 2142 */ "G_GLOBAL_VALUE\000"
2294 /* 2157 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2295 /* 2180 */ "CONVERGENCECTRL_GLUE\000"
2296 /* 2201 */ "G_STACKSAVE\000"
2297 /* 2213 */ "G_MEMMOVE\000"
2298 /* 2223 */ "G_FREEZE\000"
2299 /* 2232 */ "G_FCANONICALIZE\000"
2300 /* 2248 */ "G_FMODF\000"
2301 /* 2256 */ "G_CTLZ_ZERO_UNDEF\000"
2302 /* 2274 */ "G_CTTZ_ZERO_UNDEF\000"
2303 /* 2292 */ "INIT_UNDEF\000"
2304 /* 2303 */ "G_IMPLICIT_DEF\000"
2305 /* 2318 */ "DBG_INSTR_REF\000"
2306 /* 2332 */ "CAMELLIA_F\000"
2307 /* 2343 */ "G_FNEG\000"
2308 /* 2350 */ "EXTRACT_SUBREG\000"
2309 /* 2365 */ "INSERT_SUBREG\000"
2310 /* 2379 */ "G_SEXT_INREG\000"
2311 /* 2392 */ "SUBREG_TO_REG\000"
2312 /* 2406 */ "G_ATOMIC_CMPXCHG\000"
2313 /* 2423 */ "G_ATOMICRMW_XCHG\000"
2314 /* 2440 */ "G_GET_ROUNDING\000"
2315 /* 2455 */ "G_SET_ROUNDING\000"
2316 /* 2470 */ "G_FLOG\000"
2317 /* 2477 */ "G_VAARG\000"
2318 /* 2485 */ "PREALLOCATED_ARG\000"
2319 /* 2502 */ "G_PREFETCH\000"
2320 /* 2513 */ "G_SMULH\000"
2321 /* 2521 */ "G_UMULH\000"
2322 /* 2529 */ "G_FTANH\000"
2323 /* 2537 */ "G_FSINH\000"
2324 /* 2545 */ "G_FCOSH\000"
2325 /* 2553 */ "FLUSH\000"
2326 /* 2559 */ "DBG_PHI\000"
2327 /* 2567 */ "FPMADDXHI\000"
2328 /* 2577 */ "UMULXHI\000"
2329 /* 2585 */ "XMULXHI\000"
2330 /* 2593 */ "CAMELLIA_FLI\000"
2331 /* 2606 */ "FDTOI\000"
2332 /* 2612 */ "FQTOI\000"
2333 /* 2618 */ "FSTOI\000"
2334 /* 2624 */ "G_FPTOSI\000"
2335 /* 2633 */ "G_FPTOUI\000"
2336 /* 2642 */ "G_FPOWI\000"
2337 /* 2650 */ "BMASK\000"
2338 /* 2656 */ "COPY_LANEMASK\000"
2339 /* 2670 */ "G_PTRMASK\000"
2340 /* 2680 */ "EDGE32L\000"
2341 /* 2688 */ "EDGE16L\000"
2342 /* 2696 */ "EDGE8L\000"
2343 /* 2703 */ "FMUL8X16AL\000"
2344 /* 2714 */ "GC_LABEL\000"
2345 /* 2723 */ "DBG_LABEL\000"
2346 /* 2733 */ "EH_LABEL\000"
2347 /* 2742 */ "ANNOTATION_LABEL\000"
2348 /* 2759 */ "ICALL_BRANCH_FUNNEL\000"
2349 /* 2779 */ "CAMELLIA_FL\000"
2350 /* 2791 */ "G_FSHL\000"
2351 /* 2798 */ "G_SHL\000"
2352 /* 2804 */ "G_FCEIL\000"
2353 /* 2812 */ "G_SAVGCEIL\000"
2354 /* 2823 */ "G_UAVGCEIL\000"
2355 /* 2834 */ "PATCHABLE_TAIL_CALL\000"
2356 /* 2854 */ "TLS_CALL\000"
2357 /* 2863 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2358 /* 2890 */ "PATCHABLE_EVENT_CALL\000"
2359 /* 2911 */ "FENTRY_CALL\000"
2360 /* 2923 */ "KILL\000"
2361 /* 2928 */ "G_CONSTANT_POOL\000"
2362 /* 2944 */ "ALIGNADDRL\000"
2363 /* 2955 */ "RETL\000"
2364 /* 2960 */ "G_ROTL\000"
2365 /* 2967 */ "G_VECREDUCE_FMUL\000"
2366 /* 2984 */ "G_FMUL\000"
2367 /* 2991 */ "G_VECREDUCE_SEQ_FMUL\000"
2368 /* 3012 */ "G_STRICT_FMUL\000"
2369 /* 3026 */ "MPMUL\000"
2370 /* 3032 */ "MONTMUL\000"
2371 /* 3040 */ "G_VECREDUCE_MUL\000"
2372 /* 3056 */ "G_MUL\000"
2373 /* 3062 */ "SIAM\000"
2374 /* 3067 */ "G_FREM\000"
2375 /* 3074 */ "G_STRICT_FREM\000"
2376 /* 3088 */ "G_SREM\000"
2377 /* 3095 */ "G_UREM\000"
2378 /* 3102 */ "G_SDIVREM\000"
2379 /* 3112 */ "G_UDIVREM\000"
2380 /* 3122 */ "RDWIM\000"
2381 /* 3128 */ "INLINEASM\000"
2382 /* 3138 */ "G_VECREDUCE_FMINIMUM\000"
2383 /* 3159 */ "G_FMINIMUM\000"
2384 /* 3170 */ "G_ATOMICRMW_FMINIMUM\000"
2385 /* 3191 */ "G_VECREDUCE_FMAXIMUM\000"
2386 /* 3212 */ "G_FMAXIMUM\000"
2387 /* 3223 */ "G_ATOMICRMW_FMAXIMUM\000"
2388 /* 3244 */ "G_FMINIMUMNUM\000"
2389 /* 3258 */ "G_FMAXIMUMNUM\000"
2390 /* 3272 */ "G_FMINNUM\000"
2391 /* 3282 */ "G_FMAXNUM\000"
2392 /* 3292 */ "EDGE32N\000"
2393 /* 3300 */ "EDGE16N\000"
2394 /* 3308 */ "EDGE8N\000"
2395 /* 3315 */ "ALLCLEAN\000"
2396 /* 3324 */ "G_FATAN\000"
2397 /* 3332 */ "G_FTAN\000"
2398 /* 3339 */ "G_INTRINSIC_ROUNDEVEN\000"
2399 /* 3361 */ "G_ASSERT_ALIGN\000"
2400 /* 3376 */ "G_FCOPYSIGN\000"
2401 /* 3388 */ "G_VECREDUCE_FMIN\000"
2402 /* 3405 */ "G_ATOMICRMW_FMIN\000"
2403 /* 3422 */ "G_VECREDUCE_SMIN\000"
2404 /* 3439 */ "G_SMIN\000"
2405 /* 3446 */ "G_VECREDUCE_UMIN\000"
2406 /* 3463 */ "G_UMIN\000"
2407 /* 3470 */ "G_ATOMICRMW_UMIN\000"
2408 /* 3487 */ "G_ATOMICRMW_MIN\000"
2409 /* 3503 */ "G_FASIN\000"
2410 /* 3511 */ "G_FSIN\000"
2411 /* 3518 */ "EDGE32LN\000"
2412 /* 3527 */ "EDGE16LN\000"
2413 /* 3536 */ "EDGE8LN\000"
2414 /* 3544 */ "CFI_INSTRUCTION\000"
2415 /* 3560 */ "PDISTN\000"
2416 /* 3567 */ "ADJCALLSTACKDOWN\000"
2417 /* 3584 */ "SHUTDOWN\000"
2418 /* 3593 */ "G_SSUBO\000"
2419 /* 3601 */ "G_USUBO\000"
2420 /* 3609 */ "G_SADDO\000"
2421 /* 3617 */ "G_UADDO\000"
2422 /* 3625 */ "JUMP_TABLE_DEBUG_INFO\000"
2423 /* 3647 */ "G_SMULO\000"
2424 /* 3655 */ "G_UMULO\000"
2425 /* 3663 */ "G_BZERO\000"
2426 /* 3671 */ "FZERO\000"
2427 /* 3677 */ "STACKMAP\000"
2428 /* 3686 */ "G_DEBUGTRAP\000"
2429 /* 3698 */ "G_UBSANTRAP\000"
2430 /* 3710 */ "G_TRAP\000"
2431 /* 3717 */ "G_ATOMICRMW_UDEC_WRAP\000"
2432 /* 3739 */ "G_ATOMICRMW_UINC_WRAP\000"
2433 /* 3761 */ "G_BSWAP\000"
2434 /* 3769 */ "G_SITOFP\000"
2435 /* 3778 */ "G_UITOFP\000"
2436 /* 3787 */ "DES_IIP\000"
2437 /* 3795 */ "DES_IP\000"
2438 /* 3802 */ "G_FCMP\000"
2439 /* 3809 */ "G_ICMP\000"
2440 /* 3816 */ "G_SCMP\000"
2441 /* 3823 */ "G_UCMP\000"
2442 /* 3830 */ "UNIMP\000"
2443 /* 3836 */ "NOP\000"
2444 /* 3840 */ "CONVERGENCECTRL_LOOP\000"
2445 /* 3861 */ "G_CTPOP\000"
2446 /* 3869 */ "PATCHABLE_OP\000"
2447 /* 3882 */ "FAULTING_OP\000"
2448 /* 3894 */ "ADJCALLSTACKUP\000"
2449 /* 3909 */ "PREALLOCATED_SETUP\000"
2450 /* 3928 */ "G_FLDEXP\000"
2451 /* 3937 */ "G_STRICT_FLDEXP\000"
2452 /* 3953 */ "G_FEXP\000"
2453 /* 3960 */ "G_FFREXP\000"
2454 /* 3969 */ "FSUBQ\000"
2455 /* 3975 */ "FADDQ\000"
2456 /* 3981 */ "V9FCMPEQ\000"
2457 /* 3990 */ "RDFQ\000"
2458 /* 3995 */ "FNEGQ\000"
2459 /* 4001 */ "FDMULQ\000"
2460 /* 4008 */ "FMULQ\000"
2461 /* 4014 */ "FDTOQ\000"
2462 /* 4020 */ "FITOQ\000"
2463 /* 4026 */ "FSTOQ\000"
2464 /* 4032 */ "FXTOQ\000"
2465 /* 4038 */ "V9FCMPQ\000"
2466 /* 4046 */ "FMOVRQ\000"
2467 /* 4053 */ "FABSQ\000"
2468 /* 4059 */ "FSQRTQ\000"
2469 /* 4066 */ "FDIVQ\000"
2470 /* 4072 */ "FMOVQ\000"
2471 /* 4078 */ "V8BAR\000"
2472 /* 4084 */ "STBAR\000"
2473 /* 4090 */ "RDTBR\000"
2474 /* 4096 */ "G_BR\000"
2475 /* 4101 */ "INLINEASM_BR\000"
2476 /* 4114 */ "ALIGNADDR\000"
2477 /* 4124 */ "G_BLOCK_ADDR\000"
2478 /* 4137 */ "MEMBARRIER\000"
2479 /* 4148 */ "G_CONSTANT_FOLD_BARRIER\000"
2480 /* 4172 */ "PATCHABLE_FUNCTION_ENTER\000"
2481 /* 4197 */ "G_READCYCLECOUNTER\000"
2482 /* 4216 */ "G_READSTEADYCOUNTER\000"
2483 /* 4236 */ "G_READ_REGISTER\000"
2484 /* 4252 */ "G_WRITE_REGISTER\000"
2485 /* 4269 */ "G_ASHR\000"
2486 /* 4276 */ "G_FSHR\000"
2487 /* 4283 */ "G_LSHR\000"
2488 /* 4290 */ "SIR\000"
2489 /* 4294 */ "FOR\000"
2490 /* 4298 */ "CONVERGENCECTRL_ANCHOR\000"
2491 /* 4321 */ "FNOR\000"
2492 /* 4326 */ "FXNOR\000"
2493 /* 4332 */ "G_FFLOOR\000"
2494 /* 4341 */ "G_SAVGFLOOR\000"
2495 /* 4353 */ "G_UAVGFLOOR\000"
2496 /* 4365 */ "G_EXTRACT_SUBVECTOR\000"
2497 /* 4385 */ "G_INSERT_SUBVECTOR\000"
2498 /* 4404 */ "G_BUILD_VECTOR\000"
2499 /* 4419 */ "G_SHUFFLE_VECTOR\000"
2500 /* 4436 */ "G_STEP_VECTOR\000"
2501 /* 4450 */ "G_SPLAT_VECTOR\000"
2502 /* 4465 */ "FXOR\000"
2503 /* 4470 */ "G_VECREDUCE_XOR\000"
2504 /* 4486 */ "G_XOR\000"
2505 /* 4492 */ "G_ATOMICRMW_XOR\000"
2506 /* 4508 */ "G_VECREDUCE_OR\000"
2507 /* 4523 */ "G_OR\000"
2508 /* 4528 */ "G_ATOMICRMW_OR\000"
2509 /* 4543 */ "BPR\000"
2510 /* 4547 */ "RDPR\000"
2511 /* 4552 */ "MONTSQR\000"
2512 /* 4560 */ "RDASR\000"
2513 /* 4566 */ "RDPSR\000"
2514 /* 4572 */ "G_ROTR\000"
2515 /* 4579 */ "G_INTTOPTR\000"
2516 /* 4590 */ "FSRC1S\000"
2517 /* 4597 */ "FANDNOT1S\000"
2518 /* 4607 */ "FNOT1S\000"
2519 /* 4614 */ "FORNOT1S\000"
2520 /* 4623 */ "FPSUB32S\000"
2521 /* 4632 */ "FPADD32S\000"
2522 /* 4641 */ "FSRC2S\000"
2523 /* 4648 */ "FANDNOT2S\000"
2524 /* 4658 */ "FNOT2S\000"
2525 /* 4665 */ "FORNOT2S\000"
2526 /* 4674 */ "FPSUB16S\000"
2527 /* 4683 */ "FPADD16S\000"
2528 /* 4692 */ "G_FABS\000"
2529 /* 4699 */ "G_ABS\000"
2530 /* 4705 */ "FSUBS\000"
2531 /* 4711 */ "FHSUBS\000"
2532 /* 4718 */ "FMSUBS\000"
2533 /* 4725 */ "FNMSUBS\000"
2534 /* 4733 */ "G_ABDS\000"
2535 /* 4740 */ "FADDS\000"
2536 /* 4746 */ "FHADDS\000"
2537 /* 4753 */ "FNHADDS\000"
2538 /* 4761 */ "FMADDS\000"
2539 /* 4768 */ "FNMADDS\000"
2540 /* 4776 */ "FNADDS\000"
2541 /* 4783 */ "FANDS\000"
2542 /* 4789 */ "FNANDS\000"
2543 /* 4796 */ "FONES\000"
2544 /* 4802 */ "V9FCMPES\000"
2545 /* 4811 */ "G_UNMERGE_VALUES\000"
2546 /* 4828 */ "G_MERGE_VALUES\000"
2547 /* 4843 */ "FNEGS\000"
2548 /* 4849 */ "G_CTLS\000"
2549 /* 4856 */ "FMULS\000"
2550 /* 4862 */ "FNMULS\000"
2551 /* 4869 */ "G_FACOS\000"
2552 /* 4877 */ "G_FCOS\000"
2553 /* 4884 */ "G_FSINCOS\000"
2554 /* 4894 */ "FZEROS\000"
2555 /* 4901 */ "FDTOS\000"
2556 /* 4907 */ "FITOS\000"
2557 /* 4913 */ "FQTOS\000"
2558 /* 4919 */ "MOVWTOS\000"
2559 /* 4927 */ "FXTOS\000"
2560 /* 4933 */ "V9FCMPS\000"
2561 /* 4941 */ "FLCMPS\000"
2562 /* 4948 */ "FORS\000"
2563 /* 4953 */ "FNORS\000"
2564 /* 4959 */ "FXNORS\000"
2565 /* 4966 */ "G_CONCAT_VECTORS\000"
2566 /* 4983 */ "FXORS\000"
2567 /* 4989 */ "FMOVRS\000"
2568 /* 4996 */ "COPY_TO_REGCLASS\000"
2569 /* 5013 */ "G_IS_FPCLASS\000"
2570 /* 5026 */ "FABSS\000"
2571 /* 5032 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2572 /* 5062 */ "G_VECTOR_COMPRESS\000"
2573 /* 5080 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2574 /* 5107 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2575 /* 5145 */ "FSQRTS\000"
2576 /* 5152 */ "FDIVS\000"
2577 /* 5158 */ "FMOVS\000"
2578 /* 5164 */ "G_TRUNC_SSAT_S\000"
2579 /* 5179 */ "G_SSUBSAT\000"
2580 /* 5189 */ "G_USUBSAT\000"
2581 /* 5199 */ "G_SADDSAT\000"
2582 /* 5209 */ "G_UADDSAT\000"
2583 /* 5219 */ "G_SSHLSAT\000"
2584 /* 5229 */ "G_USHLSAT\000"
2585 /* 5239 */ "G_SMULFIXSAT\000"
2586 /* 5252 */ "G_UMULFIXSAT\000"
2587 /* 5265 */ "G_SDIVFIXSAT\000"
2588 /* 5278 */ "G_UDIVFIXSAT\000"
2589 /* 5291 */ "G_ATOMICRMW_USUB_SAT\000"
2590 /* 5312 */ "G_FPTOSI_SAT\000"
2591 /* 5325 */ "G_FPTOUI_SAT\000"
2592 /* 5338 */ "G_EXTRACT\000"
2593 /* 5348 */ "G_SELECT\000"
2594 /* 5357 */ "G_BRINDIRECT\000"
2595 /* 5370 */ "PATCHABLE_RET\000"
2596 /* 5384 */ "G_MEMSET\000"
2597 /* 5393 */ "PATCHABLE_FUNCTION_EXIT\000"
2598 /* 5417 */ "G_BRJT\000"
2599 /* 5424 */ "G_EXTRACT_VECTOR_ELT\000"
2600 /* 5445 */ "G_INSERT_VECTOR_ELT\000"
2601 /* 5465 */ "BPFCCANT\000"
2602 /* 5474 */ "BPICCANT\000"
2603 /* 5483 */ "BPXCCANT\000"
2604 /* 5492 */ "BPRANT\000"
2605 /* 5499 */ "G_FCONSTANT\000"
2606 /* 5511 */ "G_CONSTANT\000"
2607 /* 5522 */ "BPFCCNT\000"
2608 /* 5530 */ "BPICCNT\000"
2609 /* 5538 */ "BPXCCNT\000"
2610 /* 5546 */ "LZCNT\000"
2611 /* 5552 */ "G_INTRINSIC_CONVERGENT\000"
2612 /* 5575 */ "STATEPOINT\000"
2613 /* 5586 */ "PATCHPOINT\000"
2614 /* 5597 */ "G_PTRTOINT\000"
2615 /* 5608 */ "G_FRINT\000"
2616 /* 5616 */ "G_INTRINSIC_LLRINT\000"
2617 /* 5635 */ "G_INTRINSIC_LRINT\000"
2618 /* 5653 */ "G_FNEARBYINT\000"
2619 /* 5666 */ "BPRNT\000"
2620 /* 5672 */ "G_VASTART\000"
2621 /* 5682 */ "LIFETIME_START\000"
2622 /* 5697 */ "G_INVOKE_REGION_START\000"
2623 /* 5719 */ "G_INSERT\000"
2624 /* 5728 */ "G_FSQRT\000"
2625 /* 5736 */ "G_STRICT_FSQRT\000"
2626 /* 5751 */ "G_BITCAST\000"
2627 /* 5761 */ "G_ADDRSPACE_CAST\000"
2628 /* 5778 */ "AES_DROUND01_LAST\000"
2629 /* 5796 */ "AES_EROUND01_LAST\000"
2630 /* 5814 */ "AES_DROUND23_LAST\000"
2631 /* 5832 */ "AES_EROUND23_LAST\000"
2632 /* 5850 */ "PDIST\000"
2633 /* 5856 */ "DBG_VALUE_LIST\000"
2634 /* 5871 */ "G_FPEXT\000"
2635 /* 5879 */ "G_SEXT\000"
2636 /* 5886 */ "G_ASSERT_SEXT\000"
2637 /* 5900 */ "G_ANYEXT\000"
2638 /* 5909 */ "G_ZEXT\000"
2639 /* 5916 */ "G_ASSERT_ZEXT\000"
2640 /* 5930 */ "FMUL8X16AU\000"
2641 /* 5941 */ "G_ABDU\000"
2642 /* 5948 */ "G_TRUNC_SSAT_U\000"
2643 /* 5963 */ "G_TRUNC_USAT_U\000"
2644 /* 5978 */ "G_FDIV\000"
2645 /* 5985 */ "G_STRICT_FDIV\000"
2646 /* 5999 */ "G_SDIV\000"
2647 /* 6006 */ "G_UDIV\000"
2648 /* 6013 */ "G_GET_FPENV\000"
2649 /* 6025 */ "G_RESET_FPENV\000"
2650 /* 6039 */ "G_SET_FPENV\000"
2651 /* 6051 */ "FLUSHW\000"
2652 /* 6058 */ "NORMALW\000"
2653 /* 6066 */ "INVALW\000"
2654 /* 6073 */ "G_FPOW\000"
2655 /* 6080 */ "OTHERW\000"
2656 /* 6087 */ "MOVSTOSW\000"
2657 /* 6096 */ "SETSW\000"
2658 /* 6102 */ "MOVSTOUW\000"
2659 /* 6111 */ "G_VECREDUCE_FMAX\000"
2660 /* 6128 */ "G_ATOMICRMW_FMAX\000"
2661 /* 6145 */ "G_VECREDUCE_SMAX\000"
2662 /* 6162 */ "G_SMAX\000"
2663 /* 6169 */ "G_VECREDUCE_UMAX\000"
2664 /* 6186 */ "G_UMAX\000"
2665 /* 6193 */ "G_ATOMICRMW_UMAX\000"
2666 /* 6210 */ "G_ATOMICRMW_MAX\000"
2667 /* 6226 */ "GETPCX\000"
2668 /* 6233 */ "FPMADDX\000"
2669 /* 6241 */ "G_FRAME_INDEX\000"
2670 /* 6255 */ "G_SBFX\000"
2671 /* 6262 */ "G_UBFX\000"
2672 /* 6269 */ "FPACKFIX\000"
2673 /* 6278 */ "G_SMULFIX\000"
2674 /* 6288 */ "G_UMULFIX\000"
2675 /* 6298 */ "G_SDIVFIX\000"
2676 /* 6308 */ "G_UDIVFIX\000"
2677 /* 6318 */ "XMULX\000"
2678 /* 6324 */ "FDTOX\000"
2679 /* 6330 */ "MOVDTOX\000"
2680 /* 6338 */ "FQTOX\000"
2681 /* 6344 */ "FSTOX\000"
2682 /* 6350 */ "SETX\000"
2683 /* 6355 */ "G_MEMCPY\000"
2684 /* 6364 */ "COPY\000"
2685 /* 6369 */ "RETRY\000"
2686 /* 6375 */ "CONVERGENCECTRL_ENTRY\000"
2687 /* 6397 */ "G_CTLZ\000"
2688 /* 6404 */ "G_CTTZ\000"
2689 /* 6411 */ "PREFETCHAi\000"
2690 /* 6422 */ "PREFETCHi\000"
2691 /* 6432 */ "SETHIi\000"
2692 /* 6439 */ "CALLi\000"
2693 /* 6445 */ "MEMBARi\000"
2694 /* 6453 */ "CALLrii\000"
2695 /* 6461 */ "LDSBAri\000"
2696 /* 6469 */ "STBAri\000"
2697 /* 6476 */ "LDUBAri\000"
2698 /* 6484 */ "LDSTUBAri\000"
2699 /* 6494 */ "LDDAri\000"
2700 /* 6501 */ "LDAri\000"
2701 /* 6507 */ "STDAri\000"
2702 /* 6514 */ "LDDFAri\000"
2703 /* 6522 */ "LDFAri\000"
2704 /* 6529 */ "STDFAri\000"
2705 /* 6537 */ "LDQFAri\000"
2706 /* 6545 */ "STQFAri\000"
2707 /* 6553 */ "STFAri\000"
2708 /* 6560 */ "LDSHAri\000"
2709 /* 6568 */ "STHAri\000"
2710 /* 6575 */ "LDUHAri\000"
2711 /* 6583 */ "SWAPAri\000"
2712 /* 6591 */ "SRAri\000"
2713 /* 6597 */ "CASAri\000"
2714 /* 6604 */ "STAri\000"
2715 /* 6610 */ "LDSWAri\000"
2716 /* 6618 */ "LDXAri\000"
2717 /* 6625 */ "CASXAri\000"
2718 /* 6633 */ "STXAri\000"
2719 /* 6640 */ "LDSBri\000"
2720 /* 6647 */ "STBri\000"
2721 /* 6653 */ "LDUBri\000"
2722 /* 6660 */ "SUBri\000"
2723 /* 6666 */ "LDSTUBri\000"
2724 /* 6675 */ "SMACri\000"
2725 /* 6682 */ "UMACri\000"
2726 /* 6689 */ "SUBCri\000"
2727 /* 6696 */ "TSUBCCri\000"
2728 /* 6705 */ "TADDCCri\000"
2729 /* 6714 */ "ANDCCri\000"
2730 /* 6722 */ "V9MOVFCCri\000"
2731 /* 6733 */ "TICCri\000"
2732 /* 6740 */ "MOVICCri\000"
2733 /* 6749 */ "SMULCCri\000"
2734 /* 6758 */ "UMULCCri\000"
2735 /* 6767 */ "ANDNCCri\000"
2736 /* 6776 */ "ORNCCri\000"
2737 /* 6784 */ "XNORCCri\000"
2738 /* 6793 */ "XORCCri\000"
2739 /* 6801 */ "MULSCCri\000"
2740 /* 6810 */ "SDIVCCri\000"
2741 /* 6819 */ "UDIVCCri\000"
2742 /* 6828 */ "TXCCri\000"
2743 /* 6835 */ "MOVXCCri\000"
2744 /* 6844 */ "ADDCri\000"
2745 /* 6851 */ "LDDCri\000"
2746 /* 6858 */ "LDCri\000"
2747 /* 6864 */ "STDCri\000"
2748 /* 6871 */ "STCri\000"
2749 /* 6877 */ "ADDri\000"
2750 /* 6883 */ "LDDri\000"
2751 /* 6889 */ "LDri\000"
2752 /* 6894 */ "ANDri\000"
2753 /* 6900 */ "BINDri\000"
2754 /* 6907 */ "CWBCONDri\000"
2755 /* 6917 */ "CXBCONDri\000"
2756 /* 6927 */ "STDri\000"
2757 /* 6933 */ "SUBEri\000"
2758 /* 6940 */ "ADDEri\000"
2759 /* 6947 */ "RESTOREri\000"
2760 /* 6957 */ "SAVEri\000"
2761 /* 6964 */ "LDDFri\000"
2762 /* 6971 */ "LDFri\000"
2763 /* 6977 */ "STDFri\000"
2764 /* 6984 */ "LDQFri\000"
2765 /* 6991 */ "STQFri\000"
2766 /* 6998 */ "STFri\000"
2767 /* 7004 */ "LDSHri\000"
2768 /* 7011 */ "FLUSHri\000"
2769 /* 7019 */ "STHri\000"
2770 /* 7025 */ "LDUHri\000"
2771 /* 7032 */ "TAIL_CALLri\000"
2772 /* 7044 */ "SLLri\000"
2773 /* 7050 */ "JMPLri\000"
2774 /* 7057 */ "SRLri\000"
2775 /* 7063 */ "SMULri\000"
2776 /* 7070 */ "UMULri\000"
2777 /* 7077 */ "WRWIMri\000"
2778 /* 7085 */ "ANDNri\000"
2779 /* 7092 */ "ORNri\000"
2780 /* 7098 */ "TRAPri\000"
2781 /* 7105 */ "SWAPri\000"
2782 /* 7112 */ "STDCQri\000"
2783 /* 7120 */ "STDFQri\000"
2784 /* 7128 */ "WRTBRri\000"
2785 /* 7136 */ "XNORri\000"
2786 /* 7143 */ "XORri\000"
2787 /* 7149 */ "WRPRri\000"
2788 /* 7156 */ "WRASRri\000"
2789 /* 7164 */ "LDCSRri\000"
2790 /* 7172 */ "STCSRri\000"
2791 /* 7180 */ "LDFSRri\000"
2792 /* 7188 */ "STFSRri\000"
2793 /* 7196 */ "LDXFSRri\000"
2794 /* 7205 */ "STXFSRri\000"
2795 /* 7214 */ "PWRPSRri\000"
2796 /* 7223 */ "MOVRri\000"
2797 /* 7230 */ "STri\000"
2798 /* 7235 */ "RETTri\000"
2799 /* 7242 */ "SDIVri\000"
2800 /* 7249 */ "UDIVri\000"
2801 /* 7256 */ "TSUBCCTVri\000"
2802 /* 7267 */ "TADDCCTVri\000"
2803 /* 7278 */ "LDSWri\000"
2804 /* 7285 */ "SRAXri\000"
2805 /* 7292 */ "LDXri\000"
2806 /* 7298 */ "SLLXri\000"
2807 /* 7305 */ "SRLXri\000"
2808 /* 7312 */ "MULXri\000"
2809 /* 7319 */ "STXri\000"
2810 /* 7325 */ "SDIVXri\000"
2811 /* 7333 */ "UDIVXri\000"
2812 /* 7341 */ "CALLrri\000"
2813 /* 7349 */ "PREFETCHAr\000"
2814 /* 7360 */ "PREFETCHr\000"
2815 /* 7370 */ "LDSBArr\000"
2816 /* 7378 */ "STBArr\000"
2817 /* 7385 */ "LDUBArr\000"
2818 /* 7393 */ "LDSTUBArr\000"
2819 /* 7403 */ "LDDArr\000"
2820 /* 7410 */ "LDArr\000"
2821 /* 7416 */ "STDArr\000"
2822 /* 7423 */ "LDDFArr\000"
2823 /* 7431 */ "LDFArr\000"
2824 /* 7438 */ "STDFArr\000"
2825 /* 7446 */ "LDQFArr\000"
2826 /* 7454 */ "STQFArr\000"
2827 /* 7462 */ "STFArr\000"
2828 /* 7469 */ "LDSHArr\000"
2829 /* 7477 */ "STHArr\000"
2830 /* 7484 */ "LDUHArr\000"
2831 /* 7492 */ "SWAPArr\000"
2832 /* 7500 */ "SRArr\000"
2833 /* 7506 */ "CASArr\000"
2834 /* 7513 */ "STArr\000"
2835 /* 7519 */ "LDSWArr\000"
2836 /* 7527 */ "LDXArr\000"
2837 /* 7534 */ "CASXArr\000"
2838 /* 7542 */ "STXArr\000"
2839 /* 7549 */ "LDSBrr\000"
2840 /* 7556 */ "STBrr\000"
2841 /* 7562 */ "LDUBrr\000"
2842 /* 7569 */ "SUBrr\000"
2843 /* 7575 */ "LDSTUBrr\000"
2844 /* 7584 */ "SMACrr\000"
2845 /* 7591 */ "UMACrr\000"
2846 /* 7598 */ "SUBCrr\000"
2847 /* 7605 */ "TSUBCCrr\000"
2848 /* 7614 */ "TADDCCrr\000"
2849 /* 7623 */ "ANDCCrr\000"
2850 /* 7631 */ "V9MOVFCCrr\000"
2851 /* 7642 */ "TICCrr\000"
2852 /* 7649 */ "MOVICCrr\000"
2853 /* 7658 */ "SMULCCrr\000"
2854 /* 7667 */ "UMULCCrr\000"
2855 /* 7676 */ "ANDNCCrr\000"
2856 /* 7685 */ "ORNCCrr\000"
2857 /* 7693 */ "XNORCCrr\000"
2858 /* 7702 */ "XORCCrr\000"
2859 /* 7710 */ "MULSCCrr\000"
2860 /* 7719 */ "SDIVCCrr\000"
2861 /* 7728 */ "UDIVCCrr\000"
2862 /* 7737 */ "TXCCrr\000"
2863 /* 7744 */ "MOVXCCrr\000"
2864 /* 7753 */ "ADDCrr\000"
2865 /* 7760 */ "LDDCrr\000"
2866 /* 7767 */ "LDCrr\000"
2867 /* 7773 */ "STDCrr\000"
2868 /* 7780 */ "POPCrr\000"
2869 /* 7787 */ "STCrr\000"
2870 /* 7793 */ "TLS_ADDrr\000"
2871 /* 7803 */ "LDDrr\000"
2872 /* 7809 */ "GDOP_LDrr\000"
2873 /* 7819 */ "TLS_LDrr\000"
2874 /* 7828 */ "ANDrr\000"
2875 /* 7834 */ "BINDrr\000"
2876 /* 7841 */ "CWBCONDrr\000"
2877 /* 7851 */ "CXBCONDrr\000"
2878 /* 7861 */ "STDrr\000"
2879 /* 7867 */ "SUBErr\000"
2880 /* 7874 */ "ADDErr\000"
2881 /* 7881 */ "RESTORErr\000"
2882 /* 7891 */ "SAVErr\000"
2883 /* 7898 */ "LDDFrr\000"
2884 /* 7905 */ "LDFrr\000"
2885 /* 7911 */ "STDFrr\000"
2886 /* 7918 */ "LDQFrr\000"
2887 /* 7925 */ "STQFrr\000"
2888 /* 7932 */ "STFrr\000"
2889 /* 7938 */ "LDSHrr\000"
2890 /* 7945 */ "FLUSHrr\000"
2891 /* 7953 */ "STHrr\000"
2892 /* 7959 */ "LDUHrr\000"
2893 /* 7966 */ "CALLrr\000"
2894 /* 7973 */ "SLLrr\000"
2895 /* 7979 */ "JMPLrr\000"
2896 /* 7986 */ "SRLrr\000"
2897 /* 7992 */ "SMULrr\000"
2898 /* 7999 */ "UMULrr\000"
2899 /* 8006 */ "WRWIMrr\000"
2900 /* 8014 */ "ANDNrr\000"
2901 /* 8021 */ "ORNrr\000"
2902 /* 8027 */ "TRAPrr\000"
2903 /* 8034 */ "SWAPrr\000"
2904 /* 8041 */ "STDCQrr\000"
2905 /* 8049 */ "STDFQrr\000"
2906 /* 8057 */ "WRTBRrr\000"
2907 /* 8065 */ "XNORrr\000"
2908 /* 8072 */ "XORrr\000"
2909 /* 8078 */ "WRPRrr\000"
2910 /* 8085 */ "WRASRrr\000"
2911 /* 8093 */ "LDCSRrr\000"
2912 /* 8101 */ "STCSRrr\000"
2913 /* 8109 */ "LDFSRrr\000"
2914 /* 8117 */ "STFSRrr\000"
2915 /* 8125 */ "LDXFSRrr\000"
2916 /* 8134 */ "STXFSRrr\000"
2917 /* 8143 */ "PWRPSRrr\000"
2918 /* 8152 */ "MOVRrr\000"
2919 /* 8159 */ "STrr\000"
2920 /* 8164 */ "RETTrr\000"
2921 /* 8171 */ "SDIVrr\000"
2922 /* 8178 */ "UDIVrr\000"
2923 /* 8185 */ "TSUBCCTVrr\000"
2924 /* 8196 */ "TADDCCTVrr\000"
2925 /* 8207 */ "LDSWrr\000"
2926 /* 8214 */ "SRAXrr\000"
2927 /* 8221 */ "GDOP_LDXrr\000"
2928 /* 8232 */ "TLS_LDXrr\000"
2929 /* 8242 */ "SLLXrr\000"
2930 /* 8249 */ "SRLXrr\000"
2931 /* 8256 */ "MULXrr\000"
2932 /* 8263 */ "STXrr\000"
2933 /* 8269 */ "SDIVXrr\000"
2934 /* 8277 */ "UDIVXrr\000"
2935};
2936#ifdef __GNUC__
2937#pragma GCC diagnostic pop
2938#endif
2939
2940extern const unsigned SparcInstrNameIndices[] = {
2941 2563U, 3128U, 4101U, 3544U, 2733U, 2714U, 2742U, 2923U,
2942 2350U, 2365U, 2305U, 2292U, 2392U, 4996U, 2132U, 5856U,
2943 2318U, 2559U, 2723U, 1875U, 6364U, 2656U, 2005U, 5682U,
2944 1598U, 1826U, 1863U, 3677U, 2911U, 5586U, 1777U, 3909U,
2945 2485U, 5575U, 2058U, 3882U, 3869U, 4172U, 5370U, 5393U,
2946 2834U, 2890U, 2863U, 2759U, 2123U, 4137U, 3625U, 2047U,
2947 6375U, 4298U, 3840U, 2180U, 5886U, 5916U, 3361U, 1379U,
2948 714U, 3056U, 5999U, 6006U, 3088U, 3095U, 3102U, 3112U,
2949 1576U, 4523U, 4486U, 4733U, 5941U, 4353U, 2823U, 4341U,
2950 2812U, 2303U, 2561U, 6241U, 2142U, 2157U, 2928U, 5338U,
2951 4811U, 5719U, 4828U, 4404U, 1126U, 4966U, 5597U, 4579U,
2952 5751U, 2223U, 4148U, 1694U, 1100U, 1676U, 5635U, 5616U,
2953 3339U, 4197U, 4216U, 1252U, 1196U, 1226U, 1237U, 1177U,
2954 1207U, 2102U, 2086U, 5032U, 2406U, 2423U, 1395U, 720U,
2955 1582U, 1523U, 4528U, 4492U, 6210U, 3487U, 6193U, 3470U,
2956 1346U, 697U, 6128U, 3405U, 3223U, 3170U, 3739U, 3717U,
2957 1635U, 5291U, 1855U, 2502U, 1626U, 5357U, 5697U, 1078U,
2958 5080U, 5552U, 5107U, 5900U, 1118U, 5164U, 5948U, 5963U,
2959 5511U, 5499U, 5672U, 2477U, 5879U, 2379U, 5909U, 2798U,
2960 4283U, 4269U, 2791U, 4276U, 4572U, 2960U, 3809U, 3802U,
2961 3816U, 3823U, 5348U, 3617U, 1896U, 3601U, 1847U, 3609U,
2962 1888U, 3593U, 1839U, 3655U, 3647U, 2521U, 2513U, 5209U,
2963 5199U, 5189U, 5179U, 5229U, 5219U, 6278U, 6288U, 5239U,
2964 5252U, 6298U, 6308U, 5265U, 5278U, 1304U, 676U, 2984U,
2965 640U, 1170U, 5978U, 3067U, 2248U, 6073U, 2642U, 3953U,
2966 263U, 9U, 2470U, 246U, 0U, 3928U, 3960U, 2343U,
2967 5871U, 1090U, 2624U, 2633U, 3769U, 3778U, 5312U, 5325U,
2968 4692U, 3376U, 5013U, 2232U, 3272U, 3282U, 1945U, 1960U,
2969 3159U, 3212U, 3244U, 3258U, 6013U, 6039U, 6025U, 1904U,
2970 1932U, 1917U, 2440U, 2455U, 1385U, 2670U, 3439U, 6162U,
2971 3463U, 6186U, 4699U, 1667U, 1657U, 4096U, 5417U, 1983U,
2972 4385U, 4365U, 5445U, 5424U, 4419U, 4450U, 4436U, 5062U,
2973 6404U, 2274U, 6397U, 2256U, 4849U, 3861U, 3761U, 2110U,
2974 2804U, 4877U, 3511U, 4884U, 3332U, 4869U, 3503U, 3324U,
2975 254U, 2545U, 2537U, 2529U, 5728U, 4332U, 5608U, 5653U,
2976 5761U, 4124U, 1992U, 1147U, 2201U, 2071U, 1332U, 683U,
2977 3012U, 5985U, 3074U, 646U, 5736U, 3937U, 4236U, 4252U,
2978 6355U, 2021U, 2213U, 5384U, 3663U, 3710U, 3686U, 3698U,
2979 1311U, 2991U, 1287U, 2967U, 6111U, 3388U, 3191U, 3138U,
2980 1363U, 3040U, 1560U, 4508U, 4470U, 6145U, 3422U, 6169U,
2981 3446U, 6255U, 6262U, 3567U, 3894U, 6226U, 769U, 880U,
2982 987U, 805U, 916U, 1023U, 846U, 953U, 1060U, 787U,
2983 898U, 1005U, 5389U, 6096U, 6350U, 4078U, 6706U, 7615U,
2984 6844U, 7753U, 6940U, 7874U, 1164U, 743U, 6877U, 7797U,
2985 31U, 5778U, 294U, 5814U, 44U, 5796U, 307U, 5832U,
2986 18U, 72U, 233U, 4114U, 2944U, 3315U, 6714U, 7623U,
2987 6767U, 7676U, 7085U, 8014U, 6894U, 7828U, 516U, 219U,
2988 544U, 599U, 1612U, 624U, 6900U, 7834U, 2650U, 751U,
2989 602U, 5465U, 5522U, 864U, 609U, 5474U, 5530U, 4543U,
2990 659U, 5492U, 5666U, 971U, 616U, 5483U, 5538U, 2012U,
2991 2849U, 6439U, 7037U, 6453U, 7966U, 7341U, 2332U, 2779U,
2992 2593U, 6597U, 7506U, 6625U, 7534U, 396U, 171U, 537U,
2993 1618U, 631U, 736U, 6907U, 7841U, 6917U, 7851U, 3787U,
2994 3795U, 1548U, 1720U, 2037U, 363U, 2688U, 3527U, 3300U,
2995 138U, 2680U, 3518U, 3292U, 531U, 2696U, 3536U, 3308U,
2996 1801U, 4053U, 5026U, 1411U, 3975U, 4740U, 664U, 1512U,
2997 85U, 4597U, 271U, 4648U, 4783U, 1611U, 623U, 551U,
2998 562U, 418U, 1764U, 572U, 435U, 193U, 452U, 210U,
2999 370U, 145U, 379U, 154U, 4040U, 581U, 4935U, 590U,
3000 1814U, 4066U, 5152U, 4001U, 2606U, 4014U, 4901U, 6324U,
3001 1540U, 1417U, 4746U, 1265U, 4711U, 1730U, 4020U, 4907U,
3002 1770U, 4941U, 2553U, 6051U, 7011U, 7945U, 1432U, 4761U,
3003 427U, 1820U, 759U, 870U, 977U, 4072U, 824U, 933U,
3004 1040U, 1794U, 4046U, 4989U, 5158U, 836U, 943U, 1050U,
3005 1272U, 4718U, 505U, 482U, 461U, 2703U, 5930U, 1484U,
3006 493U, 470U, 4008U, 4856U, 1447U, 4776U, 1517U, 4789U,
3007 1478U, 3995U, 4843U, 1424U, 4753U, 1439U, 4768U, 1279U,
3008 4725U, 1490U, 4862U, 4321U, 4953U, 94U, 4607U, 280U,
3009 4658U, 1504U, 2042U, 4796U, 4294U, 100U, 4614U, 286U,
3010 4665U, 4948U, 388U, 163U, 6269U, 355U, 4683U, 130U,
3011 4632U, 324U, 6233U, 2567U, 1975U, 347U, 4674U, 122U,
3012 4623U, 1736U, 2612U, 4913U, 6338U, 444U, 202U, 404U,
3013 179U, 1497U, 1807U, 4059U, 5145U, 340U, 115U, 66U,
3014 4590U, 227U, 4641U, 411U, 186U, 1742U, 2618U, 4026U,
3015 6344U, 1259U, 3969U, 4705U, 4326U, 4959U, 4465U, 4983U,
3016 1748U, 4032U, 4927U, 3671U, 4894U, 8221U, 7809U, 6066U,
3017 7050U, 7979U, 6501U, 7410U, 7164U, 8093U, 6858U, 7767U,
3018 6494U, 7403U, 6851U, 7760U, 6514U, 7423U, 6964U, 7898U,
3019 6883U, 7803U, 6522U, 7431U, 7180U, 8109U, 6971U, 7905U,
3020 6537U, 7446U, 6984U, 7918U, 6461U, 7370U, 6640U, 7549U,
3021 6560U, 7469U, 7004U, 7938U, 6484U, 7393U, 6666U, 7575U,
3022 6610U, 7519U, 7278U, 8207U, 6476U, 7385U, 6653U, 7562U,
3023 6575U, 7484U, 7025U, 7959U, 6618U, 7527U, 7196U, 8125U,
3024 7292U, 8226U, 6889U, 7814U, 5546U, 336U, 6445U, 3032U,
3025 4552U, 6330U, 6724U, 7633U, 6740U, 7649U, 7223U, 8152U,
3026 6087U, 6102U, 4919U, 6835U, 7744U, 1754U, 3026U, 6801U,
3027 7710U, 7312U, 8256U, 3836U, 6058U, 6786U, 7695U, 6776U,
3028 7685U, 7092U, 8021U, 7138U, 8067U, 6080U, 5850U, 3560U,
3029 7780U, 6411U, 7349U, 6422U, 7360U, 7214U, 8143U, 4560U,
3030 3990U, 4547U, 4566U, 4090U, 3122U, 1463U, 6947U, 7881U,
3031 5380U, 2955U, 6369U, 7235U, 8164U, 1472U, 6957U, 7891U,
3032 6810U, 7719U, 7325U, 8269U, 7242U, 8171U, 6432U, 57U,
3033 524U, 108U, 3584U, 3062U, 4290U, 7298U, 8242U, 7044U,
3034 7973U, 6675U, 7584U, 6749U, 7658U, 7063U, 7992U, 7285U,
3035 8214U, 6591U, 7500U, 7305U, 8249U, 7057U, 7986U, 6604U,
3036 7513U, 4084U, 6469U, 7378U, 6647U, 7556U, 7172U, 8101U,
3037 6871U, 7787U, 6507U, 7416U, 7112U, 8041U, 6864U, 7773U,
3038 6529U, 7438U, 7120U, 8049U, 6977U, 7911U, 6927U, 7861U,
3039 6553U, 7462U, 7188U, 8117U, 6998U, 7932U, 6568U, 7477U,
3040 7019U, 7953U, 6545U, 7454U, 6991U, 7925U, 6633U, 7542U,
3041 7205U, 8134U, 7319U, 8263U, 7230U, 8159U, 6697U, 7606U,
3042 6689U, 7598U, 6933U, 7867U, 6660U, 7569U, 6583U, 7492U,
3043 7105U, 8034U, 62U, 320U, 332U, 7267U, 8196U, 6705U,
3044 7614U, 2844U, 7032U, 6733U, 7642U, 7793U, 2854U, 8232U,
3045 7819U, 7098U, 8027U, 7256U, 8185U, 6696U, 7605U, 6828U,
3046 7737U, 6819U, 7728U, 7333U, 8277U, 7249U, 8178U, 6682U,
3047 7591U, 6758U, 7667U, 2577U, 7070U, 7999U, 3830U, 1762U,
3048 1454U, 3981U, 4802U, 4038U, 4933U, 757U, 822U, 834U,
3049 6722U, 7631U, 7156U, 8085U, 7149U, 8078U, 7215U, 8144U,
3050 7128U, 8057U, 7077U, 8006U, 6318U, 2585U, 6784U, 7693U,
3051 7136U, 8065U, 6793U, 7702U, 7143U, 8072U,
3052};
3053
3054extern const int16_t SparcRegClassByHwModeTables[2][1] = {
3055 { // DefaultMode
3056 SP::IntRegsRegClassID, // sparc_ptr_rc
3057 },
3058 { // SPARC64
3059 SP::I64RegsRegClassID, // sparc_ptr_rc
3060 },
3061};
3062
3063static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
3064 II->InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 886, &SparcRegClassByHwModeTables[0][0], 1);
3065}
3066
3067
3068} // namespace llvm
3069
3070#endif // GET_INSTRINFO_MC_DESC
3071
3072#ifdef GET_INSTRINFO_HEADER
3073#undef GET_INSTRINFO_HEADER
3074
3075namespace llvm {
3076
3077struct SparcGenInstrInfo : public TargetInstrInfo {
3078 explicit SparcGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
3079 ~SparcGenInstrInfo() override = default;
3080};
3081extern const int16_t SparcRegClassByHwModeTables[2][1];
3082
3083} // namespace llvm
3084
3085namespace llvm::SP {
3086
3087
3088} // namespace llvm::SP
3089
3090#endif // GET_INSTRINFO_HEADER
3091
3092#ifdef GET_INSTRINFO_HELPER_DECLS
3093#undef GET_INSTRINFO_HELPER_DECLS
3094
3095
3096#endif // GET_INSTRINFO_HELPER_DECLS
3097
3098#ifdef GET_INSTRINFO_HELPERS
3099#undef GET_INSTRINFO_HELPERS
3100
3101
3102#endif // GET_INSTRINFO_HELPERS
3103
3104#ifdef GET_INSTRINFO_CTOR_DTOR
3105#undef GET_INSTRINFO_CTOR_DTOR
3106
3107namespace llvm {
3108
3109extern const SparcInstrTable SparcDescs;
3110extern const unsigned SparcInstrNameIndices[];
3111extern const char SparcInstrNameData[];
3112SparcGenInstrInfo::SparcGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
3113 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, SparcRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) {
3114 InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 886, &SparcRegClassByHwModeTables[0][0], 1);
3115}
3116
3117} // namespace llvm
3118
3119#endif // GET_INSTRINFO_CTOR_DTOR
3120
3121#ifdef GET_INSTRINFO_MC_HELPER_DECLS
3122#undef GET_INSTRINFO_MC_HELPER_DECLS
3123
3124namespace llvm {
3125
3126class MCInst;
3127class FeatureBitset;
3128
3129namespace Sparc_MC {
3130
3131void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
3132
3133} // namespace Sparc_MC
3134
3135} // namespace llvm
3136
3137#endif // GET_INSTRINFO_MC_HELPER_DECLS
3138
3139#ifdef GET_INSTRINFO_MC_HELPERS
3140#undef GET_INSTRINFO_MC_HELPERS
3141
3142namespace llvm::Sparc_MC {
3143
3144
3145} // namespace llvm::Sparc_MC
3146
3147#endif // GET_INSTRINFO_MC_HELPERS
3148
3149#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3150 defined(GET_AVAILABLE_OPCODE_CHECKER)
3151#define GET_COMPUTE_FEATURES
3152#endif
3153#ifdef GET_COMPUTE_FEATURES
3154#undef GET_COMPUTE_FEATURES
3155
3156namespace llvm::Sparc_MC {
3157
3158// Bits for subtarget features that participate in instruction matching.
3159enum SubtargetFeatureBits : uint8_t {
3160 Feature_Is32BitBit = 10,
3161 Feature_Is64BitBit = 11,
3162 Feature_UseSoftMulDivBit = 12,
3163 Feature_HasV9Bit = 6,
3164 Feature_HasVISBit = 7,
3165 Feature_HasVIS2Bit = 8,
3166 Feature_HasVIS3Bit = 9,
3167 Feature_HasUA2005Bit = 4,
3168 Feature_HasUA2007Bit = 5,
3169 Feature_HasOSA2011Bit = 2,
3170 Feature_HasCryptoBit = 1,
3171 Feature_HasCASABit = 0,
3172 Feature_HasPWRPSRBit = 3,
3173};
3174
3175inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3176 FeatureBitset Features;
3177 if (!FB[Sparc::Feature64Bit])
3178 Features.set(Feature_Is32BitBit);
3179 if (FB[Sparc::Feature64Bit])
3180 Features.set(Feature_Is64BitBit);
3181 if (FB[Sparc::FeatureSoftMulDiv])
3182 Features.set(Feature_UseSoftMulDivBit);
3183 if (FB[Sparc::FeatureV9])
3184 Features.set(Feature_HasV9Bit);
3185 if (FB[Sparc::FeatureVIS])
3186 Features.set(Feature_HasVISBit);
3187 if (FB[Sparc::FeatureVIS2])
3188 Features.set(Feature_HasVIS2Bit);
3189 if (FB[Sparc::FeatureVIS3])
3190 Features.set(Feature_HasVIS3Bit);
3191 if (FB[Sparc::FeatureUA2005])
3192 Features.set(Feature_HasUA2005Bit);
3193 if (FB[Sparc::FeatureUA2007])
3194 Features.set(Feature_HasUA2007Bit);
3195 if (FB[Sparc::FeatureOSA2011])
3196 Features.set(Feature_HasOSA2011Bit);
3197 if (FB[Sparc::FeatureCrypto])
3198 Features.set(Feature_HasCryptoBit);
3199 if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
3200 Features.set(Feature_HasCASABit);
3201 if (FB[Sparc::FeaturePWRPSR])
3202 Features.set(Feature_HasPWRPSRBit);
3203 return Features;
3204}
3205
3206inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3207 enum : uint8_t {
3208 CEFBS_None,
3209 CEFBS_HasCASA,
3210 CEFBS_HasCrypto,
3211 CEFBS_HasOSA2011,
3212 CEFBS_HasPWRPSR,
3213 CEFBS_HasUA2005,
3214 CEFBS_HasUA2007,
3215 CEFBS_HasV9,
3216 CEFBS_HasVIS,
3217 CEFBS_HasVIS2,
3218 CEFBS_HasVIS3,
3219 CEFBS_Is64Bit,
3220 CEFBS_Is64Bit_HasV9,
3221 };
3222
3223 static constexpr FeatureBitset FeatureBitsets[] = {
3224 {}, // CEFBS_None
3225 {Feature_HasCASABit, },
3226 {Feature_HasCryptoBit, },
3227 {Feature_HasOSA2011Bit, },
3228 {Feature_HasPWRPSRBit, },
3229 {Feature_HasUA2005Bit, },
3230 {Feature_HasUA2007Bit, },
3231 {Feature_HasV9Bit, },
3232 {Feature_HasVISBit, },
3233 {Feature_HasVIS2Bit, },
3234 {Feature_HasVIS3Bit, },
3235 {Feature_Is64BitBit, },
3236 {Feature_Is64BitBit, Feature_HasV9Bit, },
3237 };
3238 static constexpr uint8_t RequiredFeaturesRefs[] = {
3239 CEFBS_None, // PHI
3240 CEFBS_None, // INLINEASM
3241 CEFBS_None, // INLINEASM_BR
3242 CEFBS_None, // CFI_INSTRUCTION
3243 CEFBS_None, // EH_LABEL
3244 CEFBS_None, // GC_LABEL
3245 CEFBS_None, // ANNOTATION_LABEL
3246 CEFBS_None, // KILL
3247 CEFBS_None, // EXTRACT_SUBREG
3248 CEFBS_None, // INSERT_SUBREG
3249 CEFBS_None, // IMPLICIT_DEF
3250 CEFBS_None, // INIT_UNDEF
3251 CEFBS_None, // SUBREG_TO_REG
3252 CEFBS_None, // COPY_TO_REGCLASS
3253 CEFBS_None, // DBG_VALUE
3254 CEFBS_None, // DBG_VALUE_LIST
3255 CEFBS_None, // DBG_INSTR_REF
3256 CEFBS_None, // DBG_PHI
3257 CEFBS_None, // DBG_LABEL
3258 CEFBS_None, // REG_SEQUENCE
3259 CEFBS_None, // COPY
3260 CEFBS_None, // COPY_LANEMASK
3261 CEFBS_None, // BUNDLE
3262 CEFBS_None, // LIFETIME_START
3263 CEFBS_None, // LIFETIME_END
3264 CEFBS_None, // PSEUDO_PROBE
3265 CEFBS_None, // ARITH_FENCE
3266 CEFBS_None, // STACKMAP
3267 CEFBS_None, // FENTRY_CALL
3268 CEFBS_None, // PATCHPOINT
3269 CEFBS_None, // LOAD_STACK_GUARD
3270 CEFBS_None, // PREALLOCATED_SETUP
3271 CEFBS_None, // PREALLOCATED_ARG
3272 CEFBS_None, // STATEPOINT
3273 CEFBS_None, // LOCAL_ESCAPE
3274 CEFBS_None, // FAULTING_OP
3275 CEFBS_None, // PATCHABLE_OP
3276 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
3277 CEFBS_None, // PATCHABLE_RET
3278 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
3279 CEFBS_None, // PATCHABLE_TAIL_CALL
3280 CEFBS_None, // PATCHABLE_EVENT_CALL
3281 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
3282 CEFBS_None, // ICALL_BRANCH_FUNNEL
3283 CEFBS_None, // FAKE_USE
3284 CEFBS_None, // MEMBARRIER
3285 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
3286 CEFBS_None, // RELOC_NONE
3287 CEFBS_None, // CONVERGENCECTRL_ENTRY
3288 CEFBS_None, // CONVERGENCECTRL_ANCHOR
3289 CEFBS_None, // CONVERGENCECTRL_LOOP
3290 CEFBS_None, // CONVERGENCECTRL_GLUE
3291 CEFBS_None, // G_ASSERT_SEXT
3292 CEFBS_None, // G_ASSERT_ZEXT
3293 CEFBS_None, // G_ASSERT_ALIGN
3294 CEFBS_None, // G_ADD
3295 CEFBS_None, // G_SUB
3296 CEFBS_None, // G_MUL
3297 CEFBS_None, // G_SDIV
3298 CEFBS_None, // G_UDIV
3299 CEFBS_None, // G_SREM
3300 CEFBS_None, // G_UREM
3301 CEFBS_None, // G_SDIVREM
3302 CEFBS_None, // G_UDIVREM
3303 CEFBS_None, // G_AND
3304 CEFBS_None, // G_OR
3305 CEFBS_None, // G_XOR
3306 CEFBS_None, // G_ABDS
3307 CEFBS_None, // G_ABDU
3308 CEFBS_None, // G_UAVGFLOOR
3309 CEFBS_None, // G_UAVGCEIL
3310 CEFBS_None, // G_SAVGFLOOR
3311 CEFBS_None, // G_SAVGCEIL
3312 CEFBS_None, // G_IMPLICIT_DEF
3313 CEFBS_None, // G_PHI
3314 CEFBS_None, // G_FRAME_INDEX
3315 CEFBS_None, // G_GLOBAL_VALUE
3316 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3317 CEFBS_None, // G_CONSTANT_POOL
3318 CEFBS_None, // G_EXTRACT
3319 CEFBS_None, // G_UNMERGE_VALUES
3320 CEFBS_None, // G_INSERT
3321 CEFBS_None, // G_MERGE_VALUES
3322 CEFBS_None, // G_BUILD_VECTOR
3323 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3324 CEFBS_None, // G_CONCAT_VECTORS
3325 CEFBS_None, // G_PTRTOINT
3326 CEFBS_None, // G_INTTOPTR
3327 CEFBS_None, // G_BITCAST
3328 CEFBS_None, // G_FREEZE
3329 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3330 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3331 CEFBS_None, // G_INTRINSIC_TRUNC
3332 CEFBS_None, // G_INTRINSIC_ROUND
3333 CEFBS_None, // G_INTRINSIC_LRINT
3334 CEFBS_None, // G_INTRINSIC_LLRINT
3335 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3336 CEFBS_None, // G_READCYCLECOUNTER
3337 CEFBS_None, // G_READSTEADYCOUNTER
3338 CEFBS_None, // G_LOAD
3339 CEFBS_None, // G_SEXTLOAD
3340 CEFBS_None, // G_ZEXTLOAD
3341 CEFBS_None, // G_INDEXED_LOAD
3342 CEFBS_None, // G_INDEXED_SEXTLOAD
3343 CEFBS_None, // G_INDEXED_ZEXTLOAD
3344 CEFBS_None, // G_STORE
3345 CEFBS_None, // G_INDEXED_STORE
3346 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3347 CEFBS_None, // G_ATOMIC_CMPXCHG
3348 CEFBS_None, // G_ATOMICRMW_XCHG
3349 CEFBS_None, // G_ATOMICRMW_ADD
3350 CEFBS_None, // G_ATOMICRMW_SUB
3351 CEFBS_None, // G_ATOMICRMW_AND
3352 CEFBS_None, // G_ATOMICRMW_NAND
3353 CEFBS_None, // G_ATOMICRMW_OR
3354 CEFBS_None, // G_ATOMICRMW_XOR
3355 CEFBS_None, // G_ATOMICRMW_MAX
3356 CEFBS_None, // G_ATOMICRMW_MIN
3357 CEFBS_None, // G_ATOMICRMW_UMAX
3358 CEFBS_None, // G_ATOMICRMW_UMIN
3359 CEFBS_None, // G_ATOMICRMW_FADD
3360 CEFBS_None, // G_ATOMICRMW_FSUB
3361 CEFBS_None, // G_ATOMICRMW_FMAX
3362 CEFBS_None, // G_ATOMICRMW_FMIN
3363 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3364 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3365 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3366 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3367 CEFBS_None, // G_ATOMICRMW_USUB_COND
3368 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3369 CEFBS_None, // G_FENCE
3370 CEFBS_None, // G_PREFETCH
3371 CEFBS_None, // G_BRCOND
3372 CEFBS_None, // G_BRINDIRECT
3373 CEFBS_None, // G_INVOKE_REGION_START
3374 CEFBS_None, // G_INTRINSIC
3375 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3376 CEFBS_None, // G_INTRINSIC_CONVERGENT
3377 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3378 CEFBS_None, // G_ANYEXT
3379 CEFBS_None, // G_TRUNC
3380 CEFBS_None, // G_TRUNC_SSAT_S
3381 CEFBS_None, // G_TRUNC_SSAT_U
3382 CEFBS_None, // G_TRUNC_USAT_U
3383 CEFBS_None, // G_CONSTANT
3384 CEFBS_None, // G_FCONSTANT
3385 CEFBS_None, // G_VASTART
3386 CEFBS_None, // G_VAARG
3387 CEFBS_None, // G_SEXT
3388 CEFBS_None, // G_SEXT_INREG
3389 CEFBS_None, // G_ZEXT
3390 CEFBS_None, // G_SHL
3391 CEFBS_None, // G_LSHR
3392 CEFBS_None, // G_ASHR
3393 CEFBS_None, // G_FSHL
3394 CEFBS_None, // G_FSHR
3395 CEFBS_None, // G_ROTR
3396 CEFBS_None, // G_ROTL
3397 CEFBS_None, // G_ICMP
3398 CEFBS_None, // G_FCMP
3399 CEFBS_None, // G_SCMP
3400 CEFBS_None, // G_UCMP
3401 CEFBS_None, // G_SELECT
3402 CEFBS_None, // G_UADDO
3403 CEFBS_None, // G_UADDE
3404 CEFBS_None, // G_USUBO
3405 CEFBS_None, // G_USUBE
3406 CEFBS_None, // G_SADDO
3407 CEFBS_None, // G_SADDE
3408 CEFBS_None, // G_SSUBO
3409 CEFBS_None, // G_SSUBE
3410 CEFBS_None, // G_UMULO
3411 CEFBS_None, // G_SMULO
3412 CEFBS_None, // G_UMULH
3413 CEFBS_None, // G_SMULH
3414 CEFBS_None, // G_UADDSAT
3415 CEFBS_None, // G_SADDSAT
3416 CEFBS_None, // G_USUBSAT
3417 CEFBS_None, // G_SSUBSAT
3418 CEFBS_None, // G_USHLSAT
3419 CEFBS_None, // G_SSHLSAT
3420 CEFBS_None, // G_SMULFIX
3421 CEFBS_None, // G_UMULFIX
3422 CEFBS_None, // G_SMULFIXSAT
3423 CEFBS_None, // G_UMULFIXSAT
3424 CEFBS_None, // G_SDIVFIX
3425 CEFBS_None, // G_UDIVFIX
3426 CEFBS_None, // G_SDIVFIXSAT
3427 CEFBS_None, // G_UDIVFIXSAT
3428 CEFBS_None, // G_FADD
3429 CEFBS_None, // G_FSUB
3430 CEFBS_None, // G_FMUL
3431 CEFBS_None, // G_FMA
3432 CEFBS_None, // G_FMAD
3433 CEFBS_None, // G_FDIV
3434 CEFBS_None, // G_FREM
3435 CEFBS_None, // G_FMODF
3436 CEFBS_None, // G_FPOW
3437 CEFBS_None, // G_FPOWI
3438 CEFBS_None, // G_FEXP
3439 CEFBS_None, // G_FEXP2
3440 CEFBS_None, // G_FEXP10
3441 CEFBS_None, // G_FLOG
3442 CEFBS_None, // G_FLOG2
3443 CEFBS_None, // G_FLOG10
3444 CEFBS_None, // G_FLDEXP
3445 CEFBS_None, // G_FFREXP
3446 CEFBS_None, // G_FNEG
3447 CEFBS_None, // G_FPEXT
3448 CEFBS_None, // G_FPTRUNC
3449 CEFBS_None, // G_FPTOSI
3450 CEFBS_None, // G_FPTOUI
3451 CEFBS_None, // G_SITOFP
3452 CEFBS_None, // G_UITOFP
3453 CEFBS_None, // G_FPTOSI_SAT
3454 CEFBS_None, // G_FPTOUI_SAT
3455 CEFBS_None, // G_FABS
3456 CEFBS_None, // G_FCOPYSIGN
3457 CEFBS_None, // G_IS_FPCLASS
3458 CEFBS_None, // G_FCANONICALIZE
3459 CEFBS_None, // G_FMINNUM
3460 CEFBS_None, // G_FMAXNUM
3461 CEFBS_None, // G_FMINNUM_IEEE
3462 CEFBS_None, // G_FMAXNUM_IEEE
3463 CEFBS_None, // G_FMINIMUM
3464 CEFBS_None, // G_FMAXIMUM
3465 CEFBS_None, // G_FMINIMUMNUM
3466 CEFBS_None, // G_FMAXIMUMNUM
3467 CEFBS_None, // G_GET_FPENV
3468 CEFBS_None, // G_SET_FPENV
3469 CEFBS_None, // G_RESET_FPENV
3470 CEFBS_None, // G_GET_FPMODE
3471 CEFBS_None, // G_SET_FPMODE
3472 CEFBS_None, // G_RESET_FPMODE
3473 CEFBS_None, // G_GET_ROUNDING
3474 CEFBS_None, // G_SET_ROUNDING
3475 CEFBS_None, // G_PTR_ADD
3476 CEFBS_None, // G_PTRMASK
3477 CEFBS_None, // G_SMIN
3478 CEFBS_None, // G_SMAX
3479 CEFBS_None, // G_UMIN
3480 CEFBS_None, // G_UMAX
3481 CEFBS_None, // G_ABS
3482 CEFBS_None, // G_LROUND
3483 CEFBS_None, // G_LLROUND
3484 CEFBS_None, // G_BR
3485 CEFBS_None, // G_BRJT
3486 CEFBS_None, // G_VSCALE
3487 CEFBS_None, // G_INSERT_SUBVECTOR
3488 CEFBS_None, // G_EXTRACT_SUBVECTOR
3489 CEFBS_None, // G_INSERT_VECTOR_ELT
3490 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3491 CEFBS_None, // G_SHUFFLE_VECTOR
3492 CEFBS_None, // G_SPLAT_VECTOR
3493 CEFBS_None, // G_STEP_VECTOR
3494 CEFBS_None, // G_VECTOR_COMPRESS
3495 CEFBS_None, // G_CTTZ
3496 CEFBS_None, // G_CTTZ_ZERO_UNDEF
3497 CEFBS_None, // G_CTLZ
3498 CEFBS_None, // G_CTLZ_ZERO_UNDEF
3499 CEFBS_None, // G_CTLS
3500 CEFBS_None, // G_CTPOP
3501 CEFBS_None, // G_BSWAP
3502 CEFBS_None, // G_BITREVERSE
3503 CEFBS_None, // G_FCEIL
3504 CEFBS_None, // G_FCOS
3505 CEFBS_None, // G_FSIN
3506 CEFBS_None, // G_FSINCOS
3507 CEFBS_None, // G_FTAN
3508 CEFBS_None, // G_FACOS
3509 CEFBS_None, // G_FASIN
3510 CEFBS_None, // G_FATAN
3511 CEFBS_None, // G_FATAN2
3512 CEFBS_None, // G_FCOSH
3513 CEFBS_None, // G_FSINH
3514 CEFBS_None, // G_FTANH
3515 CEFBS_None, // G_FSQRT
3516 CEFBS_None, // G_FFLOOR
3517 CEFBS_None, // G_FRINT
3518 CEFBS_None, // G_FNEARBYINT
3519 CEFBS_None, // G_ADDRSPACE_CAST
3520 CEFBS_None, // G_BLOCK_ADDR
3521 CEFBS_None, // G_JUMP_TABLE
3522 CEFBS_None, // G_DYN_STACKALLOC
3523 CEFBS_None, // G_STACKSAVE
3524 CEFBS_None, // G_STACKRESTORE
3525 CEFBS_None, // G_STRICT_FADD
3526 CEFBS_None, // G_STRICT_FSUB
3527 CEFBS_None, // G_STRICT_FMUL
3528 CEFBS_None, // G_STRICT_FDIV
3529 CEFBS_None, // G_STRICT_FREM
3530 CEFBS_None, // G_STRICT_FMA
3531 CEFBS_None, // G_STRICT_FSQRT
3532 CEFBS_None, // G_STRICT_FLDEXP
3533 CEFBS_None, // G_READ_REGISTER
3534 CEFBS_None, // G_WRITE_REGISTER
3535 CEFBS_None, // G_MEMCPY
3536 CEFBS_None, // G_MEMCPY_INLINE
3537 CEFBS_None, // G_MEMMOVE
3538 CEFBS_None, // G_MEMSET
3539 CEFBS_None, // G_BZERO
3540 CEFBS_None, // G_TRAP
3541 CEFBS_None, // G_DEBUGTRAP
3542 CEFBS_None, // G_UBSANTRAP
3543 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3544 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3545 CEFBS_None, // G_VECREDUCE_FADD
3546 CEFBS_None, // G_VECREDUCE_FMUL
3547 CEFBS_None, // G_VECREDUCE_FMAX
3548 CEFBS_None, // G_VECREDUCE_FMIN
3549 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3550 CEFBS_None, // G_VECREDUCE_FMINIMUM
3551 CEFBS_None, // G_VECREDUCE_ADD
3552 CEFBS_None, // G_VECREDUCE_MUL
3553 CEFBS_None, // G_VECREDUCE_AND
3554 CEFBS_None, // G_VECREDUCE_OR
3555 CEFBS_None, // G_VECREDUCE_XOR
3556 CEFBS_None, // G_VECREDUCE_SMAX
3557 CEFBS_None, // G_VECREDUCE_SMIN
3558 CEFBS_None, // G_VECREDUCE_UMAX
3559 CEFBS_None, // G_VECREDUCE_UMIN
3560 CEFBS_None, // G_SBFX
3561 CEFBS_None, // G_UBFX
3562 CEFBS_None, // ADJCALLSTACKDOWN
3563 CEFBS_None, // ADJCALLSTACKUP
3564 CEFBS_None, // GETPCX
3565 CEFBS_None, // SELECT_CC_DFP_FCC
3566 CEFBS_None, // SELECT_CC_DFP_ICC
3567 CEFBS_None, // SELECT_CC_DFP_XCC
3568 CEFBS_None, // SELECT_CC_FP_FCC
3569 CEFBS_None, // SELECT_CC_FP_ICC
3570 CEFBS_None, // SELECT_CC_FP_XCC
3571 CEFBS_None, // SELECT_CC_Int_FCC
3572 CEFBS_None, // SELECT_CC_Int_ICC
3573 CEFBS_None, // SELECT_CC_Int_XCC
3574 CEFBS_None, // SELECT_CC_QFP_FCC
3575 CEFBS_None, // SELECT_CC_QFP_ICC
3576 CEFBS_None, // SELECT_CC_QFP_XCC
3577 CEFBS_None, // SET
3578 CEFBS_HasV9, // SETSW
3579 CEFBS_Is64Bit_HasV9, // SETX
3580 CEFBS_None, // V8BAR
3581 CEFBS_None, // ADDCCri
3582 CEFBS_None, // ADDCCrr
3583 CEFBS_None, // ADDCri
3584 CEFBS_None, // ADDCrr
3585 CEFBS_None, // ADDEri
3586 CEFBS_None, // ADDErr
3587 CEFBS_HasVIS3, // ADDXC
3588 CEFBS_HasVIS3, // ADDXCCC
3589 CEFBS_None, // ADDri
3590 CEFBS_None, // ADDrr
3591 CEFBS_HasCrypto, // AES_DROUND01
3592 CEFBS_HasCrypto, // AES_DROUND01_LAST
3593 CEFBS_HasCrypto, // AES_DROUND23
3594 CEFBS_HasCrypto, // AES_DROUND23_LAST
3595 CEFBS_HasCrypto, // AES_EROUND01
3596 CEFBS_HasCrypto, // AES_EROUND01_LAST
3597 CEFBS_HasCrypto, // AES_EROUND23
3598 CEFBS_HasCrypto, // AES_EROUND23_LAST
3599 CEFBS_HasCrypto, // AES_KEXPAND0
3600 CEFBS_HasCrypto, // AES_KEXPAND1
3601 CEFBS_HasCrypto, // AES_KEXPAND2
3602 CEFBS_HasVIS, // ALIGNADDR
3603 CEFBS_HasVIS, // ALIGNADDRL
3604 CEFBS_HasUA2005, // ALLCLEAN
3605 CEFBS_None, // ANDCCri
3606 CEFBS_None, // ANDCCrr
3607 CEFBS_None, // ANDNCCri
3608 CEFBS_None, // ANDNCCrr
3609 CEFBS_None, // ANDNri
3610 CEFBS_None, // ANDNrr
3611 CEFBS_None, // ANDri
3612 CEFBS_None, // ANDrr
3613 CEFBS_HasVIS, // ARRAY16
3614 CEFBS_HasVIS, // ARRAY32
3615 CEFBS_HasVIS, // ARRAY8
3616 CEFBS_None, // BA
3617 CEFBS_None, // BCOND
3618 CEFBS_None, // BCONDA
3619 CEFBS_None, // BINDri
3620 CEFBS_None, // BINDrr
3621 CEFBS_HasVIS2, // BMASK
3622 CEFBS_HasV9, // BPFCC
3623 CEFBS_HasV9, // BPFCCA
3624 CEFBS_HasV9, // BPFCCANT
3625 CEFBS_HasV9, // BPFCCNT
3626 CEFBS_HasV9, // BPICC
3627 CEFBS_HasV9, // BPICCA
3628 CEFBS_HasV9, // BPICCANT
3629 CEFBS_HasV9, // BPICCNT
3630 CEFBS_Is64Bit, // BPR
3631 CEFBS_Is64Bit, // BPRA
3632 CEFBS_Is64Bit, // BPRANT
3633 CEFBS_Is64Bit, // BPRNT
3634 CEFBS_Is64Bit, // BPXCC
3635 CEFBS_Is64Bit, // BPXCCA
3636 CEFBS_Is64Bit, // BPXCCANT
3637 CEFBS_Is64Bit, // BPXCCNT
3638 CEFBS_HasVIS2, // BSHUFFLE
3639 CEFBS_None, // CALL
3640 CEFBS_None, // CALLi
3641 CEFBS_None, // CALLri
3642 CEFBS_None, // CALLrii
3643 CEFBS_None, // CALLrr
3644 CEFBS_None, // CALLrri
3645 CEFBS_HasCrypto, // CAMELLIA_F
3646 CEFBS_HasCrypto, // CAMELLIA_FL
3647 CEFBS_HasCrypto, // CAMELLIA_FLI
3648 CEFBS_HasV9, // CASAri
3649 CEFBS_HasCASA, // CASArr
3650 CEFBS_Is64Bit_HasV9, // CASXAri
3651 CEFBS_Is64Bit_HasV9, // CASXArr
3652 CEFBS_HasVIS3, // CMASK16
3653 CEFBS_HasVIS3, // CMASK32
3654 CEFBS_HasVIS3, // CMASK8
3655 CEFBS_None, // CPBCOND
3656 CEFBS_None, // CPBCONDA
3657 CEFBS_HasCrypto, // CRC32C
3658 CEFBS_HasOSA2011, // CWBCONDri
3659 CEFBS_HasOSA2011, // CWBCONDrr
3660 CEFBS_HasOSA2011, // CXBCONDri
3661 CEFBS_HasOSA2011, // CXBCONDrr
3662 CEFBS_HasCrypto, // DES_IIP
3663 CEFBS_HasCrypto, // DES_IP
3664 CEFBS_HasCrypto, // DES_KEXPAND
3665 CEFBS_HasCrypto, // DES_ROUND
3666 CEFBS_HasV9, // DONE
3667 CEFBS_HasVIS, // EDGE16
3668 CEFBS_HasVIS, // EDGE16L
3669 CEFBS_HasVIS2, // EDGE16LN
3670 CEFBS_HasVIS2, // EDGE16N
3671 CEFBS_HasVIS, // EDGE32
3672 CEFBS_HasVIS, // EDGE32L
3673 CEFBS_HasVIS2, // EDGE32LN
3674 CEFBS_HasVIS2, // EDGE32N
3675 CEFBS_HasVIS, // EDGE8
3676 CEFBS_HasVIS, // EDGE8L
3677 CEFBS_HasVIS2, // EDGE8LN
3678 CEFBS_HasVIS2, // EDGE8N
3679 CEFBS_HasV9, // FABSD
3680 CEFBS_HasV9, // FABSQ
3681 CEFBS_None, // FABSS
3682 CEFBS_None, // FADDD
3683 CEFBS_None, // FADDQ
3684 CEFBS_None, // FADDS
3685 CEFBS_HasVIS, // FALIGNADATA
3686 CEFBS_HasVIS, // FAND
3687 CEFBS_HasVIS, // FANDNOT1
3688 CEFBS_HasVIS, // FANDNOT1S
3689 CEFBS_HasVIS, // FANDNOT2
3690 CEFBS_HasVIS, // FANDNOT2S
3691 CEFBS_HasVIS, // FANDS
3692 CEFBS_None, // FBCOND
3693 CEFBS_None, // FBCONDA
3694 CEFBS_HasV9, // FBCONDA_V9
3695 CEFBS_HasV9, // FBCOND_V9
3696 CEFBS_HasVIS3, // FCHKSM16
3697 CEFBS_None, // FCMPD
3698 CEFBS_HasV9, // FCMPD_V9
3699 CEFBS_HasVIS, // FCMPEQ16
3700 CEFBS_HasVIS, // FCMPEQ32
3701 CEFBS_HasVIS, // FCMPGT16
3702 CEFBS_HasVIS, // FCMPGT32
3703 CEFBS_HasVIS, // FCMPLE16
3704 CEFBS_HasVIS, // FCMPLE32
3705 CEFBS_HasVIS, // FCMPNE16
3706 CEFBS_HasVIS, // FCMPNE32
3707 CEFBS_None, // FCMPQ
3708 CEFBS_HasV9, // FCMPQ_V9
3709 CEFBS_None, // FCMPS
3710 CEFBS_HasV9, // FCMPS_V9
3711 CEFBS_None, // FDIVD
3712 CEFBS_None, // FDIVQ
3713 CEFBS_None, // FDIVS
3714 CEFBS_None, // FDMULQ
3715 CEFBS_None, // FDTOI
3716 CEFBS_None, // FDTOQ
3717 CEFBS_None, // FDTOS
3718 CEFBS_Is64Bit, // FDTOX
3719 CEFBS_HasVIS, // FEXPAND
3720 CEFBS_HasVIS3, // FHADDD
3721 CEFBS_HasVIS3, // FHADDS
3722 CEFBS_HasVIS3, // FHSUBD
3723 CEFBS_HasVIS3, // FHSUBS
3724 CEFBS_None, // FITOD
3725 CEFBS_None, // FITOQ
3726 CEFBS_None, // FITOS
3727 CEFBS_HasVIS3, // FLCMPD
3728 CEFBS_HasVIS3, // FLCMPS
3729 CEFBS_None, // FLUSH
3730 CEFBS_HasV9, // FLUSHW
3731 CEFBS_None, // FLUSHri
3732 CEFBS_None, // FLUSHrr
3733 CEFBS_HasUA2007, // FMADDD
3734 CEFBS_HasUA2007, // FMADDS
3735 CEFBS_HasVIS3, // FMEAN16
3736 CEFBS_HasV9, // FMOVD
3737 CEFBS_HasV9, // FMOVD_FCC
3738 CEFBS_HasV9, // FMOVD_ICC
3739 CEFBS_Is64Bit, // FMOVD_XCC
3740 CEFBS_HasV9, // FMOVQ
3741 CEFBS_HasV9, // FMOVQ_FCC
3742 CEFBS_HasV9, // FMOVQ_ICC
3743 CEFBS_Is64Bit, // FMOVQ_XCC
3744 CEFBS_Is64Bit, // FMOVRD
3745 CEFBS_None, // FMOVRQ
3746 CEFBS_Is64Bit, // FMOVRS
3747 CEFBS_None, // FMOVS
3748 CEFBS_HasV9, // FMOVS_FCC
3749 CEFBS_HasV9, // FMOVS_ICC
3750 CEFBS_Is64Bit, // FMOVS_XCC
3751 CEFBS_HasUA2007, // FMSUBD
3752 CEFBS_HasUA2007, // FMSUBS
3753 CEFBS_HasVIS, // FMUL8SUX16
3754 CEFBS_HasVIS, // FMUL8ULX16
3755 CEFBS_HasVIS, // FMUL8X16
3756 CEFBS_HasVIS, // FMUL8X16AL
3757 CEFBS_HasVIS, // FMUL8X16AU
3758 CEFBS_None, // FMULD
3759 CEFBS_HasVIS, // FMULD8SUX16
3760 CEFBS_HasVIS, // FMULD8ULX16
3761 CEFBS_None, // FMULQ
3762 CEFBS_None, // FMULS
3763 CEFBS_HasVIS3, // FNADDD
3764 CEFBS_HasVIS3, // FNADDS
3765 CEFBS_HasVIS, // FNAND
3766 CEFBS_HasVIS, // FNANDS
3767 CEFBS_HasV9, // FNEGD
3768 CEFBS_HasV9, // FNEGQ
3769 CEFBS_None, // FNEGS
3770 CEFBS_HasVIS3, // FNHADDD
3771 CEFBS_HasVIS3, // FNHADDS
3772 CEFBS_HasUA2007, // FNMADDD
3773 CEFBS_HasUA2007, // FNMADDS
3774 CEFBS_HasUA2007, // FNMSUBD
3775 CEFBS_HasUA2007, // FNMSUBS
3776 CEFBS_HasVIS3, // FNMULD
3777 CEFBS_HasVIS3, // FNMULS
3778 CEFBS_HasVIS, // FNOR
3779 CEFBS_HasVIS, // FNORS
3780 CEFBS_HasVIS, // FNOT1
3781 CEFBS_HasVIS, // FNOT1S
3782 CEFBS_HasVIS, // FNOT2
3783 CEFBS_HasVIS, // FNOT2S
3784 CEFBS_HasVIS3, // FNSMULD
3785 CEFBS_HasVIS, // FONE
3786 CEFBS_HasVIS, // FONES
3787 CEFBS_HasVIS, // FOR
3788 CEFBS_HasVIS, // FORNOT1
3789 CEFBS_HasVIS, // FORNOT1S
3790 CEFBS_HasVIS, // FORNOT2
3791 CEFBS_HasVIS, // FORNOT2S
3792 CEFBS_HasVIS, // FORS
3793 CEFBS_HasVIS, // FPACK16
3794 CEFBS_HasVIS, // FPACK32
3795 CEFBS_HasVIS, // FPACKFIX
3796 CEFBS_HasVIS, // FPADD16
3797 CEFBS_HasVIS, // FPADD16S
3798 CEFBS_HasVIS, // FPADD32
3799 CEFBS_HasVIS, // FPADD32S
3800 CEFBS_HasVIS3, // FPADD64
3801 CEFBS_HasOSA2011, // FPMADDX
3802 CEFBS_HasOSA2011, // FPMADDXHI
3803 CEFBS_HasVIS, // FPMERGE
3804 CEFBS_HasVIS, // FPSUB16
3805 CEFBS_HasVIS, // FPSUB16S
3806 CEFBS_HasVIS, // FPSUB32
3807 CEFBS_HasVIS, // FPSUB32S
3808 CEFBS_None, // FQTOD
3809 CEFBS_None, // FQTOI
3810 CEFBS_None, // FQTOS
3811 CEFBS_Is64Bit, // FQTOX
3812 CEFBS_HasVIS3, // FSLAS16
3813 CEFBS_HasVIS3, // FSLAS32
3814 CEFBS_HasVIS3, // FSLL16
3815 CEFBS_HasVIS3, // FSLL32
3816 CEFBS_None, // FSMULD
3817 CEFBS_None, // FSQRTD
3818 CEFBS_None, // FSQRTQ
3819 CEFBS_None, // FSQRTS
3820 CEFBS_HasVIS3, // FSRA16
3821 CEFBS_HasVIS3, // FSRA32
3822 CEFBS_HasVIS, // FSRC1
3823 CEFBS_HasVIS, // FSRC1S
3824 CEFBS_HasVIS, // FSRC2
3825 CEFBS_HasVIS, // FSRC2S
3826 CEFBS_HasVIS3, // FSRL16
3827 CEFBS_HasVIS3, // FSRL32
3828 CEFBS_None, // FSTOD
3829 CEFBS_None, // FSTOI
3830 CEFBS_None, // FSTOQ
3831 CEFBS_Is64Bit, // FSTOX
3832 CEFBS_None, // FSUBD
3833 CEFBS_None, // FSUBQ
3834 CEFBS_None, // FSUBS
3835 CEFBS_HasVIS, // FXNOR
3836 CEFBS_HasVIS, // FXNORS
3837 CEFBS_HasVIS, // FXOR
3838 CEFBS_HasVIS, // FXORS
3839 CEFBS_Is64Bit, // FXTOD
3840 CEFBS_Is64Bit, // FXTOQ
3841 CEFBS_Is64Bit, // FXTOS
3842 CEFBS_HasVIS, // FZERO
3843 CEFBS_HasVIS, // FZEROS
3844 CEFBS_Is64Bit, // GDOP_LDXrr
3845 CEFBS_None, // GDOP_LDrr
3846 CEFBS_HasUA2005, // INVALW
3847 CEFBS_None, // JMPLri
3848 CEFBS_None, // JMPLrr
3849 CEFBS_HasV9, // LDAri
3850 CEFBS_None, // LDArr
3851 CEFBS_None, // LDCSRri
3852 CEFBS_None, // LDCSRrr
3853 CEFBS_None, // LDCri
3854 CEFBS_None, // LDCrr
3855 CEFBS_HasV9, // LDDAri
3856 CEFBS_None, // LDDArr
3857 CEFBS_None, // LDDCri
3858 CEFBS_None, // LDDCrr
3859 CEFBS_HasV9, // LDDFAri
3860 CEFBS_HasV9, // LDDFArr
3861 CEFBS_None, // LDDFri
3862 CEFBS_None, // LDDFrr
3863 CEFBS_None, // LDDri
3864 CEFBS_None, // LDDrr
3865 CEFBS_HasV9, // LDFAri
3866 CEFBS_HasV9, // LDFArr
3867 CEFBS_None, // LDFSRri
3868 CEFBS_None, // LDFSRrr
3869 CEFBS_None, // LDFri
3870 CEFBS_None, // LDFrr
3871 CEFBS_HasV9, // LDQFAri
3872 CEFBS_HasV9, // LDQFArr
3873 CEFBS_HasV9, // LDQFri
3874 CEFBS_HasV9, // LDQFrr
3875 CEFBS_HasV9, // LDSBAri
3876 CEFBS_None, // LDSBArr
3877 CEFBS_None, // LDSBri
3878 CEFBS_None, // LDSBrr
3879 CEFBS_HasV9, // LDSHAri
3880 CEFBS_None, // LDSHArr
3881 CEFBS_None, // LDSHri
3882 CEFBS_None, // LDSHrr
3883 CEFBS_HasV9, // LDSTUBAri
3884 CEFBS_None, // LDSTUBArr
3885 CEFBS_None, // LDSTUBri
3886 CEFBS_None, // LDSTUBrr
3887 CEFBS_Is64Bit, // LDSWAri
3888 CEFBS_Is64Bit, // LDSWArr
3889 CEFBS_Is64Bit, // LDSWri
3890 CEFBS_Is64Bit, // LDSWrr
3891 CEFBS_HasV9, // LDUBAri
3892 CEFBS_None, // LDUBArr
3893 CEFBS_None, // LDUBri
3894 CEFBS_None, // LDUBrr
3895 CEFBS_HasV9, // LDUHAri
3896 CEFBS_None, // LDUHArr
3897 CEFBS_None, // LDUHri
3898 CEFBS_None, // LDUHrr
3899 CEFBS_Is64Bit, // LDXAri
3900 CEFBS_Is64Bit, // LDXArr
3901 CEFBS_HasV9, // LDXFSRri
3902 CEFBS_HasV9, // LDXFSRrr
3903 CEFBS_Is64Bit, // LDXri
3904 CEFBS_Is64Bit, // LDXrr
3905 CEFBS_None, // LDri
3906 CEFBS_None, // LDrr
3907 CEFBS_HasVIS3, // LZCNT
3908 CEFBS_HasCrypto, // MD5
3909 CEFBS_HasV9, // MEMBARi
3910 CEFBS_HasCrypto, // MONTMUL
3911 CEFBS_HasCrypto, // MONTSQR
3912 CEFBS_HasVIS3, // MOVDTOX
3913 CEFBS_HasV9, // MOVFCCri
3914 CEFBS_HasV9, // MOVFCCrr
3915 CEFBS_HasV9, // MOVICCri
3916 CEFBS_HasV9, // MOVICCrr
3917 CEFBS_Is64Bit, // MOVRri
3918 CEFBS_Is64Bit, // MOVRrr
3919 CEFBS_HasVIS3, // MOVSTOSW
3920 CEFBS_HasVIS3, // MOVSTOUW
3921 CEFBS_HasVIS3, // MOVWTOS
3922 CEFBS_Is64Bit, // MOVXCCri
3923 CEFBS_Is64Bit, // MOVXCCrr
3924 CEFBS_HasVIS3, // MOVXTOD
3925 CEFBS_HasCrypto, // MPMUL
3926 CEFBS_None, // MULSCCri
3927 CEFBS_None, // MULSCCrr
3928 CEFBS_Is64Bit, // MULXri
3929 CEFBS_Is64Bit, // MULXrr
3930 CEFBS_None, // NOP
3931 CEFBS_HasUA2005, // NORMALW
3932 CEFBS_None, // ORCCri
3933 CEFBS_None, // ORCCrr
3934 CEFBS_None, // ORNCCri
3935 CEFBS_None, // ORNCCrr
3936 CEFBS_None, // ORNri
3937 CEFBS_None, // ORNrr
3938 CEFBS_None, // ORri
3939 CEFBS_None, // ORrr
3940 CEFBS_HasUA2005, // OTHERW
3941 CEFBS_HasVIS, // PDIST
3942 CEFBS_HasVIS3, // PDISTN
3943 CEFBS_HasV9, // POPCrr
3944 CEFBS_HasV9, // PREFETCHAi
3945 CEFBS_HasV9, // PREFETCHAr
3946 CEFBS_HasV9, // PREFETCHi
3947 CEFBS_HasV9, // PREFETCHr
3948 CEFBS_HasPWRPSR, // PWRPSRri
3949 CEFBS_HasPWRPSR, // PWRPSRrr
3950 CEFBS_None, // RDASR
3951 CEFBS_HasV9, // RDFQ
3952 CEFBS_HasV9, // RDPR
3953 CEFBS_None, // RDPSR
3954 CEFBS_None, // RDTBR
3955 CEFBS_None, // RDWIM
3956 CEFBS_HasV9, // RESTORED
3957 CEFBS_None, // RESTOREri
3958 CEFBS_None, // RESTORErr
3959 CEFBS_None, // RET
3960 CEFBS_None, // RETL
3961 CEFBS_HasV9, // RETRY
3962 CEFBS_None, // RETTri
3963 CEFBS_None, // RETTrr
3964 CEFBS_HasV9, // SAVED
3965 CEFBS_None, // SAVEri
3966 CEFBS_None, // SAVErr
3967 CEFBS_None, // SDIVCCri
3968 CEFBS_None, // SDIVCCrr
3969 CEFBS_Is64Bit, // SDIVXri
3970 CEFBS_Is64Bit, // SDIVXrr
3971 CEFBS_None, // SDIVri
3972 CEFBS_None, // SDIVrr
3973 CEFBS_None, // SETHIi
3974 CEFBS_HasCrypto, // SHA1
3975 CEFBS_HasCrypto, // SHA256
3976 CEFBS_HasCrypto, // SHA512
3977 CEFBS_HasVIS, // SHUTDOWN
3978 CEFBS_HasVIS2, // SIAM
3979 CEFBS_HasV9, // SIR
3980 CEFBS_Is64Bit, // SLLXri
3981 CEFBS_Is64Bit, // SLLXrr
3982 CEFBS_None, // SLLri
3983 CEFBS_None, // SLLrr
3984 CEFBS_None, // SMACri
3985 CEFBS_None, // SMACrr
3986 CEFBS_None, // SMULCCri
3987 CEFBS_None, // SMULCCrr
3988 CEFBS_None, // SMULri
3989 CEFBS_None, // SMULrr
3990 CEFBS_Is64Bit, // SRAXri
3991 CEFBS_Is64Bit, // SRAXrr
3992 CEFBS_None, // SRAri
3993 CEFBS_None, // SRArr
3994 CEFBS_Is64Bit, // SRLXri
3995 CEFBS_Is64Bit, // SRLXrr
3996 CEFBS_None, // SRLri
3997 CEFBS_None, // SRLrr
3998 CEFBS_HasV9, // STAri
3999 CEFBS_None, // STArr
4000 CEFBS_None, // STBAR
4001 CEFBS_HasV9, // STBAri
4002 CEFBS_None, // STBArr
4003 CEFBS_None, // STBri
4004 CEFBS_None, // STBrr
4005 CEFBS_None, // STCSRri
4006 CEFBS_None, // STCSRrr
4007 CEFBS_None, // STCri
4008 CEFBS_None, // STCrr
4009 CEFBS_HasV9, // STDAri
4010 CEFBS_None, // STDArr
4011 CEFBS_None, // STDCQri
4012 CEFBS_None, // STDCQrr
4013 CEFBS_None, // STDCri
4014 CEFBS_None, // STDCrr
4015 CEFBS_HasV9, // STDFAri
4016 CEFBS_HasV9, // STDFArr
4017 CEFBS_None, // STDFQri
4018 CEFBS_None, // STDFQrr
4019 CEFBS_None, // STDFri
4020 CEFBS_None, // STDFrr
4021 CEFBS_None, // STDri
4022 CEFBS_None, // STDrr
4023 CEFBS_HasV9, // STFAri
4024 CEFBS_HasV9, // STFArr
4025 CEFBS_None, // STFSRri
4026 CEFBS_None, // STFSRrr
4027 CEFBS_None, // STFri
4028 CEFBS_None, // STFrr
4029 CEFBS_HasV9, // STHAri
4030 CEFBS_None, // STHArr
4031 CEFBS_None, // STHri
4032 CEFBS_None, // STHrr
4033 CEFBS_HasV9, // STQFAri
4034 CEFBS_HasV9, // STQFArr
4035 CEFBS_HasV9, // STQFri
4036 CEFBS_HasV9, // STQFrr
4037 CEFBS_Is64Bit, // STXAri
4038 CEFBS_Is64Bit, // STXArr
4039 CEFBS_HasV9, // STXFSRri
4040 CEFBS_HasV9, // STXFSRrr
4041 CEFBS_Is64Bit, // STXri
4042 CEFBS_Is64Bit, // STXrr
4043 CEFBS_None, // STri
4044 CEFBS_None, // STrr
4045 CEFBS_None, // SUBCCri
4046 CEFBS_None, // SUBCCrr
4047 CEFBS_None, // SUBCri
4048 CEFBS_None, // SUBCrr
4049 CEFBS_None, // SUBEri
4050 CEFBS_None, // SUBErr
4051 CEFBS_None, // SUBri
4052 CEFBS_None, // SUBrr
4053 CEFBS_HasV9, // SWAPAri
4054 CEFBS_None, // SWAPArr
4055 CEFBS_None, // SWAPri
4056 CEFBS_None, // SWAPrr
4057 CEFBS_None, // TA1
4058 CEFBS_None, // TA3
4059 CEFBS_None, // TA5
4060 CEFBS_None, // TADDCCTVri
4061 CEFBS_None, // TADDCCTVrr
4062 CEFBS_None, // TADDCCri
4063 CEFBS_None, // TADDCCrr
4064 CEFBS_None, // TAIL_CALL
4065 CEFBS_None, // TAIL_CALLri
4066 CEFBS_HasV9, // TICCri
4067 CEFBS_HasV9, // TICCrr
4068 CEFBS_None, // TLS_ADDrr
4069 CEFBS_None, // TLS_CALL
4070 CEFBS_Is64Bit, // TLS_LDXrr
4071 CEFBS_None, // TLS_LDrr
4072 CEFBS_None, // TRAPri
4073 CEFBS_None, // TRAPrr
4074 CEFBS_None, // TSUBCCTVri
4075 CEFBS_None, // TSUBCCTVrr
4076 CEFBS_None, // TSUBCCri
4077 CEFBS_None, // TSUBCCrr
4078 CEFBS_Is64Bit, // TXCCri
4079 CEFBS_Is64Bit, // TXCCrr
4080 CEFBS_None, // UDIVCCri
4081 CEFBS_None, // UDIVCCrr
4082 CEFBS_Is64Bit, // UDIVXri
4083 CEFBS_Is64Bit, // UDIVXrr
4084 CEFBS_None, // UDIVri
4085 CEFBS_None, // UDIVrr
4086 CEFBS_None, // UMACri
4087 CEFBS_None, // UMACrr
4088 CEFBS_None, // UMULCCri
4089 CEFBS_None, // UMULCCrr
4090 CEFBS_HasVIS3, // UMULXHI
4091 CEFBS_None, // UMULri
4092 CEFBS_None, // UMULrr
4093 CEFBS_None, // UNIMP
4094 CEFBS_None, // V9FCMPD
4095 CEFBS_None, // V9FCMPED
4096 CEFBS_None, // V9FCMPEQ
4097 CEFBS_None, // V9FCMPES
4098 CEFBS_None, // V9FCMPQ
4099 CEFBS_None, // V9FCMPS
4100 CEFBS_HasV9, // V9FMOVD_FCC
4101 CEFBS_HasV9, // V9FMOVQ_FCC
4102 CEFBS_HasV9, // V9FMOVS_FCC
4103 CEFBS_HasV9, // V9MOVFCCri
4104 CEFBS_HasV9, // V9MOVFCCrr
4105 CEFBS_None, // WRASRri
4106 CEFBS_None, // WRASRrr
4107 CEFBS_HasV9, // WRPRri
4108 CEFBS_HasV9, // WRPRrr
4109 CEFBS_None, // WRPSRri
4110 CEFBS_None, // WRPSRrr
4111 CEFBS_None, // WRTBRri
4112 CEFBS_None, // WRTBRrr
4113 CEFBS_None, // WRWIMri
4114 CEFBS_None, // WRWIMrr
4115 CEFBS_HasVIS3, // XMULX
4116 CEFBS_HasVIS3, // XMULXHI
4117 CEFBS_None, // XNORCCri
4118 CEFBS_None, // XNORCCrr
4119 CEFBS_None, // XNORri
4120 CEFBS_None, // XNORrr
4121 CEFBS_None, // XORCCri
4122 CEFBS_None, // XORCCrr
4123 CEFBS_None, // XORri
4124 CEFBS_None, // XORrr
4125 };
4126
4127 assert(Opcode < 886);
4128 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
4129}
4130
4131
4132} // namespace llvm::Sparc_MC
4133
4134#endif // GET_COMPUTE_FEATURES
4135
4136#ifdef GET_AVAILABLE_OPCODE_CHECKER
4137#undef GET_AVAILABLE_OPCODE_CHECKER
4138
4139namespace llvm::Sparc_MC {
4140
4141bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
4142 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4143 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4144 FeatureBitset MissingFeatures =
4145 (AvailableFeatures & RequiredFeatures) ^
4146 RequiredFeatures;
4147 return !MissingFeatures.any();
4148}
4149
4150} // namespace llvm::Sparc_MC
4151
4152#endif // GET_AVAILABLE_OPCODE_CHECKER
4153
4154#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
4155#undef ENABLE_INSTR_PREDICATE_VERIFIER
4156
4157#include <sstream>
4158
4159namespace llvm::Sparc_MC {
4160
4161#ifndef NDEBUG
4162static const char *SubtargetFeatureNames[] = {
4163 "Feature_HasCASA",
4164 "Feature_HasCrypto",
4165 "Feature_HasOSA2011",
4166 "Feature_HasPWRPSR",
4167 "Feature_HasUA2005",
4168 "Feature_HasUA2007",
4169 "Feature_HasV9",
4170 "Feature_HasVIS",
4171 "Feature_HasVIS2",
4172 "Feature_HasVIS3",
4173 "Feature_Is32Bit",
4174 "Feature_Is64Bit",
4175 "Feature_UseSoftMulDiv",
4176 nullptr
4177};
4178
4179#endif // NDEBUG
4180
4181void verifyInstructionPredicates(
4182 unsigned Opcode, const FeatureBitset &Features) {
4183#ifndef NDEBUG
4184 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4185 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4186 FeatureBitset MissingFeatures =
4187 (AvailableFeatures & RequiredFeatures) ^
4188 RequiredFeatures;
4189 if (MissingFeatures.any()) {
4190 std::ostringstream Msg;
4191 Msg << "Attempting to emit " << &SparcInstrNameData[SparcInstrNameIndices[Opcode]]
4192 << " instruction but the ";
4193 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
4194 if (MissingFeatures.test(i))
4195 Msg << SubtargetFeatureNames[i] << " ";
4196 Msg << "predicate(s) are not met";
4197 report_fatal_error(Msg.str().c_str());
4198 }
4199#endif // NDEBUG
4200}
4201
4202} // namespace llvm::Sparc_MC
4203
4204#endif // ENABLE_INSTR_PREDICATE_VERIFIER
4205
4206