1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SP {
13
14 enum {
15 PHI = 0, // Target.td:1301
16 INLINEASM = 1, // Target.td:1307
17 INLINEASM_BR = 2, // Target.td:1313
18 CFI_INSTRUCTION = 3, // Target.td:1322
19 EH_LABEL = 4, // Target.td:1331
20 GC_LABEL = 5, // Target.td:1340
21 ANNOTATION_LABEL = 6, // Target.td:1349
22 KILL = 7, // Target.td:1357
23 EXTRACT_SUBREG = 8, // Target.td:1364
24 INSERT_SUBREG = 9, // Target.td:1370
25 IMPLICIT_DEF = 10, // Target.td:1377
26 INIT_UNDEF = 11, // Target.td:1386
27 SUBREG_TO_REG = 12, // Target.td:1393
28 COPY_TO_REGCLASS = 13, // Target.td:1399
29 DBG_VALUE = 14, // Target.td:1406
30 DBG_VALUE_LIST = 15, // Target.td:1413
31 DBG_INSTR_REF = 16, // Target.td:1420
32 DBG_PHI = 17, // Target.td:1427
33 DBG_LABEL = 18, // Target.td:1434
34 REG_SEQUENCE = 19, // Target.td:1441
35 COPY = 20, // Target.td:1448
36 COPY_LANEMASK = 21, // Target.td:1456
37 BUNDLE = 22, // Target.td:1463
38 LIFETIME_START = 23, // Target.td:1469
39 LIFETIME_END = 24, // Target.td:1476
40 PSEUDO_PROBE = 25, // Target.td:1483
41 ARITH_FENCE = 26, // Target.td:1490
42 STACKMAP = 27, // Target.td:1499
43 FENTRY_CALL = 28, // Target.td:1634
44 PATCHPOINT = 29, // Target.td:1507
45 LOAD_STACK_GUARD = 30, // Target.td:1525
46 PREALLOCATED_SETUP = 31, // Target.td:1533
47 PREALLOCATED_ARG = 32, // Target.td:1539
48 STATEPOINT = 33, // Target.td:1516
49 LOCAL_ESCAPE = 34, // Target.td:1545
50 FAULTING_OP = 35, // Target.td:1554
51 PATCHABLE_OP = 36, // Target.td:1574
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1582
53 PATCHABLE_RET = 38, // Target.td:1589
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1598
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1606
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1614
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1624
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1644
59 FAKE_USE = 44, // Target.td:1564
60 MEMBARRIER = 45, // Target.td:1650
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1658
62 RELOC_NONE = 47, // Target.td:1666
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1678
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1674
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1682
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1686
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1867
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1859
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1874
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1474
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1486
96 G_INSERT = 81, // GenericOpcodes.td:1494
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1504
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1523
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1532
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1539
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1881
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_FMAXIMUMNUM = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_FMINIMUMNUM = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_UINC_WRAP = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_UDEC_WRAP = 129, // GenericOpcodes.td:1448
145 G_ATOMICRMW_USUB_COND = 130, // GenericOpcodes.td:1449
146 G_ATOMICRMW_USUB_SAT = 131, // GenericOpcodes.td:1450
147 G_FENCE = 132, // GenericOpcodes.td:1452
148 G_PREFETCH = 133, // GenericOpcodes.td:1459
149 G_BRCOND = 134, // GenericOpcodes.td:1594
150 G_BRINDIRECT = 135, // GenericOpcodes.td:1603
151 G_INVOKE_REGION_START = 136, // GenericOpcodes.td:1626
152 G_INTRINSIC = 137, // GenericOpcodes.td:1546
153 G_INTRINSIC_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1553
154 G_INTRINSIC_CONVERGENT = 139, // GenericOpcodes.td:1562
155 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1570
156 G_ANYEXT = 141, // GenericOpcodes.td:44
157 G_TRUNC = 142, // GenericOpcodes.td:83
158 G_TRUNC_SSAT_S = 143, // GenericOpcodes.td:90
159 G_TRUNC_SSAT_U = 144, // GenericOpcodes.td:97
160 G_TRUNC_USAT_U = 145, // GenericOpcodes.td:104
161 G_CONSTANT = 146, // GenericOpcodes.td:165
162 G_FCONSTANT = 147, // GenericOpcodes.td:172
163 G_VASTART = 148, // GenericOpcodes.td:178
164 G_VAARG = 149, // GenericOpcodes.td:185
165 G_SEXT = 150, // GenericOpcodes.td:52
166 G_SEXT_INREG = 151, // GenericOpcodes.td:66
167 G_ZEXT = 152, // GenericOpcodes.td:74
168 G_SHL = 153, // GenericOpcodes.td:396
169 G_LSHR = 154, // GenericOpcodes.td:403
170 G_ASHR = 155, // GenericOpcodes.td:410
171 G_FSHL = 156, // GenericOpcodes.td:462
172 G_FSHR = 157, // GenericOpcodes.td:470
173 G_ROTR = 158, // GenericOpcodes.td:477
174 G_ROTL = 159, // GenericOpcodes.td:484
175 G_ICMP = 160, // GenericOpcodes.td:491
176 G_FCMP = 161, // GenericOpcodes.td:498
177 G_SCMP = 162, // GenericOpcodes.td:505
178 G_UCMP = 163, // GenericOpcodes.td:512
179 G_SELECT = 164, // GenericOpcodes.td:519
180 G_UADDO = 165, // GenericOpcodes.td:584
181 G_UADDE = 166, // GenericOpcodes.td:592
182 G_USUBO = 167, // GenericOpcodes.td:614
183 G_USUBE = 168, // GenericOpcodes.td:620
184 G_SADDO = 169, // GenericOpcodes.td:599
185 G_SADDE = 170, // GenericOpcodes.td:607
186 G_SSUBO = 171, // GenericOpcodes.td:627
187 G_SSUBE = 172, // GenericOpcodes.td:634
188 G_UMULO = 173, // GenericOpcodes.td:641
189 G_SMULO = 174, // GenericOpcodes.td:649
190 G_UMULH = 175, // GenericOpcodes.td:658
191 G_SMULH = 176, // GenericOpcodes.td:667
192 G_UADDSAT = 177, // GenericOpcodes.td:679
193 G_SADDSAT = 178, // GenericOpcodes.td:687
194 G_USUBSAT = 179, // GenericOpcodes.td:695
195 G_SSUBSAT = 180, // GenericOpcodes.td:703
196 G_USHLSAT = 181, // GenericOpcodes.td:711
197 G_SSHLSAT = 182, // GenericOpcodes.td:719
198 G_SMULFIX = 183, // GenericOpcodes.td:731
199 G_UMULFIX = 184, // GenericOpcodes.td:738
200 G_SMULFIXSAT = 185, // GenericOpcodes.td:748
201 G_UMULFIXSAT = 186, // GenericOpcodes.td:755
202 G_SDIVFIX = 187, // GenericOpcodes.td:766
203 G_UDIVFIX = 188, // GenericOpcodes.td:773
204 G_SDIVFIXSAT = 189, // GenericOpcodes.td:783
205 G_UDIVFIXSAT = 190, // GenericOpcodes.td:790
206 G_FADD = 191, // GenericOpcodes.td:963
207 G_FSUB = 192, // GenericOpcodes.td:971
208 G_FMUL = 193, // GenericOpcodes.td:979
209 G_FMA = 194, // GenericOpcodes.td:988
210 G_FMAD = 195, // GenericOpcodes.td:997
211 G_FDIV = 196, // GenericOpcodes.td:1005
212 G_FREM = 197, // GenericOpcodes.td:1012
213 G_FMODF = 198, // GenericOpcodes.td:1019
214 G_FPOW = 199, // GenericOpcodes.td:1026
215 G_FPOWI = 200, // GenericOpcodes.td:1033
216 G_FEXP = 201, // GenericOpcodes.td:1040
217 G_FEXP2 = 202, // GenericOpcodes.td:1047
218 G_FEXP10 = 203, // GenericOpcodes.td:1054
219 G_FLOG = 204, // GenericOpcodes.td:1061
220 G_FLOG2 = 205, // GenericOpcodes.td:1068
221 G_FLOG10 = 206, // GenericOpcodes.td:1075
222 G_FLDEXP = 207, // GenericOpcodes.td:1082
223 G_FFREXP = 208, // GenericOpcodes.td:1089
224 G_FNEG = 209, // GenericOpcodes.td:801
225 G_FPEXT = 210, // GenericOpcodes.td:807
226 G_FPTRUNC = 211, // GenericOpcodes.td:813
227 G_FPTOSI = 212, // GenericOpcodes.td:819
228 G_FPTOUI = 213, // GenericOpcodes.td:825
229 G_SITOFP = 214, // GenericOpcodes.td:831
230 G_UITOFP = 215, // GenericOpcodes.td:837
231 G_FPTOSI_SAT = 216, // GenericOpcodes.td:843
232 G_FPTOUI_SAT = 217, // GenericOpcodes.td:849
233 G_FABS = 218, // GenericOpcodes.td:855
234 G_FCOPYSIGN = 219, // GenericOpcodes.td:861
235 G_IS_FPCLASS = 220, // GenericOpcodes.td:874
236 G_FCANONICALIZE = 221, // GenericOpcodes.td:867
237 G_FMINNUM = 222, // GenericOpcodes.td:887
238 G_FMAXNUM = 223, // GenericOpcodes.td:894
239 G_FMINNUM_IEEE = 224, // GenericOpcodes.td:912
240 G_FMAXNUM_IEEE = 225, // GenericOpcodes.td:919
241 G_FMINIMUM = 226, // GenericOpcodes.td:929
242 G_FMAXIMUM = 227, // GenericOpcodes.td:936
243 G_FMINIMUMNUM = 228, // GenericOpcodes.td:944
244 G_FMAXIMUMNUM = 229, // GenericOpcodes.td:951
245 G_GET_FPENV = 230, // GenericOpcodes.td:1219
246 G_SET_FPENV = 231, // GenericOpcodes.td:1226
247 G_RESET_FPENV = 232, // GenericOpcodes.td:1233
248 G_GET_FPMODE = 233, // GenericOpcodes.td:1240
249 G_SET_FPMODE = 234, // GenericOpcodes.td:1247
250 G_RESET_FPMODE = 235, // GenericOpcodes.td:1254
251 G_GET_ROUNDING = 236, // GenericOpcodes.td:1311
252 G_SET_ROUNDING = 237, // GenericOpcodes.td:1317
253 G_PTR_ADD = 238, // GenericOpcodes.td:526
254 G_PTRMASK = 239, // GenericOpcodes.td:534
255 G_SMIN = 240, // GenericOpcodes.td:541
256 G_SMAX = 241, // GenericOpcodes.td:549
257 G_UMIN = 242, // GenericOpcodes.td:557
258 G_UMAX = 243, // GenericOpcodes.td:565
259 G_ABS = 244, // GenericOpcodes.td:573
260 G_LROUND = 245, // GenericOpcodes.td:283
261 G_LLROUND = 246, // GenericOpcodes.td:289
262 G_BR = 247, // GenericOpcodes.td:1584
263 G_BRJT = 248, // GenericOpcodes.td:1614
264 G_VSCALE = 249, // GenericOpcodes.td:1514
265 G_INSERT_SUBVECTOR = 250, // GenericOpcodes.td:1658
266 G_EXTRACT_SUBVECTOR = 251, // GenericOpcodes.td:1665
267 G_INSERT_VECTOR_ELT = 252, // GenericOpcodes.td:1672
268 G_EXTRACT_VECTOR_ELT = 253, // GenericOpcodes.td:1679
269 G_SHUFFLE_VECTOR = 254, // GenericOpcodes.td:1689
270 G_SPLAT_VECTOR = 255, // GenericOpcodes.td:1696
271 G_STEP_VECTOR = 256, // GenericOpcodes.td:1703
272 G_VECTOR_COMPRESS = 257, // GenericOpcodes.td:1710
273 G_CTTZ = 258, // GenericOpcodes.td:205
274 G_CTTZ_ZERO_UNDEF = 259, // GenericOpcodes.td:211
275 G_CTLZ = 260, // GenericOpcodes.td:193
276 G_CTLZ_ZERO_UNDEF = 261, // GenericOpcodes.td:199
277 G_CTLS = 262, // GenericOpcodes.td:217
278 G_CTPOP = 263, // GenericOpcodes.td:223
279 G_BSWAP = 264, // GenericOpcodes.td:229
280 G_BITREVERSE = 265, // GenericOpcodes.td:235
281 G_FCEIL = 266, // GenericOpcodes.td:1096
282 G_FCOS = 267, // GenericOpcodes.td:1103
283 G_FSIN = 268, // GenericOpcodes.td:1110
284 G_FSINCOS = 269, // GenericOpcodes.td:1117
285 G_FTAN = 270, // GenericOpcodes.td:1124
286 G_FACOS = 271, // GenericOpcodes.td:1131
287 G_FASIN = 272, // GenericOpcodes.td:1138
288 G_FATAN = 273, // GenericOpcodes.td:1145
289 G_FATAN2 = 274, // GenericOpcodes.td:1152
290 G_FCOSH = 275, // GenericOpcodes.td:1159
291 G_FSINH = 276, // GenericOpcodes.td:1166
292 G_FTANH = 277, // GenericOpcodes.td:1173
293 G_FSQRT = 278, // GenericOpcodes.td:1183
294 G_FFLOOR = 279, // GenericOpcodes.td:1190
295 G_FRINT = 280, // GenericOpcodes.td:1197
296 G_FNEARBYINT = 281, // GenericOpcodes.td:1204
297 G_ADDRSPACE_CAST = 282, // GenericOpcodes.td:241
298 G_BLOCK_ADDR = 283, // GenericOpcodes.td:247
299 G_JUMP_TABLE = 284, // GenericOpcodes.td:253
300 G_DYN_STACKALLOC = 285, // GenericOpcodes.td:259
301 G_STACKSAVE = 286, // GenericOpcodes.td:265
302 G_STACKRESTORE = 287, // GenericOpcodes.td:271
303 G_STRICT_FADD = 288, // GenericOpcodes.td:1760
304 G_STRICT_FSUB = 289, // GenericOpcodes.td:1761
305 G_STRICT_FMUL = 290, // GenericOpcodes.td:1762
306 G_STRICT_FDIV = 291, // GenericOpcodes.td:1763
307 G_STRICT_FREM = 292, // GenericOpcodes.td:1764
308 G_STRICT_FMA = 293, // GenericOpcodes.td:1765
309 G_STRICT_FSQRT = 294, // GenericOpcodes.td:1766
310 G_STRICT_FLDEXP = 295, // GenericOpcodes.td:1767
311 G_READ_REGISTER = 296, // GenericOpcodes.td:1633
312 G_WRITE_REGISTER = 297, // GenericOpcodes.td:1643
313 G_MEMCPY = 298, // GenericOpcodes.td:1773
314 G_MEMCPY_INLINE = 299, // GenericOpcodes.td:1781
315 G_MEMMOVE = 300, // GenericOpcodes.td:1789
316 G_MEMSET = 301, // GenericOpcodes.td:1797
317 G_BZERO = 302, // GenericOpcodes.td:1804
318 G_TRAP = 303, // GenericOpcodes.td:1814
319 G_DEBUGTRAP = 304, // GenericOpcodes.td:1821
320 G_UBSANTRAP = 305, // GenericOpcodes.td:1827
321 G_VECREDUCE_SEQ_FADD = 306, // GenericOpcodes.td:1726
322 G_VECREDUCE_SEQ_FMUL = 307, // GenericOpcodes.td:1732
323 G_VECREDUCE_FADD = 308, // GenericOpcodes.td:1738
324 G_VECREDUCE_FMUL = 309, // GenericOpcodes.td:1739
325 G_VECREDUCE_FMAX = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMIN = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_FMAXIMUM = 312, // GenericOpcodes.td:1743
328 G_VECREDUCE_FMINIMUM = 313, // GenericOpcodes.td:1744
329 G_VECREDUCE_ADD = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_MUL = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_AND = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_OR = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_XOR = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_SMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_SMIN = 320, // GenericOpcodes.td:1752
336 G_VECREDUCE_UMAX = 321, // GenericOpcodes.td:1753
337 G_VECREDUCE_UMIN = 322, // GenericOpcodes.td:1754
338 G_SBFX = 323, // GenericOpcodes.td:1839
339 G_UBFX = 324, // GenericOpcodes.td:1847
340 ADJCALLSTACKDOWN = 325, // SparcInstrInfo.td:591
341 ADJCALLSTACKUP = 326, // SparcInstrInfo.td:594
342 GETPCX = 327, // SparcInstrInfo.td:587
343 SELECT_CC_DFP_FCC = 328, // SparcInstrInfo.td:667
344 SELECT_CC_DFP_ICC = 329, // SparcInstrInfo.td:624
345 SELECT_CC_DFP_XCC = 330, // SparcInstrInfo.td:645
346 SELECT_CC_FP_FCC = 331, // SparcInstrInfo.td:663
347 SELECT_CC_FP_ICC = 332, // SparcInstrInfo.td:619
348 SELECT_CC_FP_XCC = 333, // SparcInstrInfo.td:640
349 SELECT_CC_Int_FCC = 334, // SparcInstrInfo.td:658
350 SELECT_CC_Int_ICC = 335, // SparcInstrInfo.td:615
351 SELECT_CC_Int_XCC = 336, // SparcInstrInfo.td:636
352 SELECT_CC_QFP_FCC = 337, // SparcInstrInfo.td:671
353 SELECT_CC_QFP_ICC = 338, // SparcInstrInfo.td:629
354 SELECT_CC_QFP_XCC = 339, // SparcInstrInfo.td:650
355 SET = 340, // SparcInstrAliases.td:562
356 SETSW = 341, // SparcInstrAliases.td:566
357 SETX = 342, // SparcInstrAliases.td:570
358 V8BAR = 343, // SparcInstrInfo.td:583
359 ADDCCri = 344, // SparcInstrInfo.td:478
360 ADDCCrr = 345, // SparcInstrInfo.td:473
361 ADDCri = 346, // SparcInstrInfo.td:492
362 ADDCrr = 347, // SparcInstrInfo.td:488
363 ADDEri = 348, // SparcInstrInfo.td:478
364 ADDErr = 349, // SparcInstrInfo.td:473
365 ADDXC = 350, // SparcInstrVIS.td:185
366 ADDXCCC = 351, // SparcInstrVIS.td:188
367 ADDri = 352, // SparcInstrInfo.td:478
368 ADDrr = 353, // SparcInstrInfo.td:473
369 AES_DROUND01 = 354, // SparcInstrCrypto.td:23
370 AES_DROUND01_LAST = 355, // SparcInstrCrypto.td:27
371 AES_DROUND23 = 356, // SparcInstrCrypto.td:24
372 AES_DROUND23_LAST = 357, // SparcInstrCrypto.td:28
373 AES_EROUND01 = 358, // SparcInstrCrypto.td:21
374 AES_EROUND01_LAST = 359, // SparcInstrCrypto.td:25
375 AES_EROUND23 = 360, // SparcInstrCrypto.td:22
376 AES_EROUND23_LAST = 361, // SparcInstrCrypto.td:26
377 AES_KEXPAND0 = 362, // SparcInstrCrypto.td:29
378 AES_KEXPAND1 = 363, // SparcInstrCrypto.td:32
379 AES_KEXPAND2 = 364, // SparcInstrCrypto.td:33
380 ALIGNADDR = 365, // SparcInstrVIS.td:96
381 ALIGNADDRL = 366, // SparcInstrVIS.td:97
382 ALLCLEAN = 367, // SparcInstrUAOSA.td:39
383 ANDCCri = 368, // SparcInstrInfo.td:492
384 ANDCCrr = 369, // SparcInstrInfo.td:488
385 ANDNCCri = 370, // SparcInstrInfo.td:492
386 ANDNCCrr = 371, // SparcInstrInfo.td:488
387 ANDNri = 372, // SparcInstrInfo.td:852
388 ANDNrr = 373, // SparcInstrInfo.td:848
389 ANDri = 374, // SparcInstrInfo.td:478
390 ANDrr = 375, // SparcInstrInfo.td:473
391 ARRAY16 = 376, // SparcInstrVIS.td:154
392 ARRAY32 = 377, // SparcInstrVIS.td:155
393 ARRAY8 = 378, // SparcInstrVIS.td:153
394 BA = 379, // SparcInstrInfo.td:965
395 BCOND = 380, // SparcInstrInfo.td:1014
396 BCONDA = 381, // SparcInstrInfo.td:1017
397 BINDri = 382, // SparcInstrInfo.td:1007
398 BINDrr = 383, // SparcInstrInfo.td:1003
399 BMASK = 384, // SparcInstrVIS.td:165
400 BPFCC = 385, // SparcInstrInfo.td:1038
401 BPFCCA = 386, // SparcInstrInfo.td:1041
402 BPFCCANT = 387, // SparcInstrInfo.td:1047
403 BPFCCNT = 388, // SparcInstrInfo.td:1044
404 BPICC = 389, // SparcInstrInfo.td:979
405 BPICCA = 390, // SparcInstrInfo.td:983
406 BPICCANT = 391, // SparcInstrInfo.td:991
407 BPICCNT = 392, // SparcInstrInfo.td:987
408 BPR = 393, // SparcInstr64Bit.td:325
409 BPRA = 394, // SparcInstr64Bit.td:327
410 BPRANT = 395, // SparcInstr64Bit.td:331
411 BPRNT = 396, // SparcInstr64Bit.td:329
412 BPXCC = 397, // SparcInstrInfo.td:979
413 BPXCCA = 398, // SparcInstrInfo.td:983
414 BPXCCANT = 399, // SparcInstrInfo.td:991
415 BPXCCNT = 400, // SparcInstrInfo.td:987
416 BSHUFFLE = 401, // SparcInstrVIS.td:166
417 CALL = 402, // SparcInstrInfo.td:1100
418 CALLi = 403, // SparcInstrInfo.td:1112
419 CALLri = 404, // SparcInstrInfo.td:1127
420 CALLrii = 405, // SparcInstrInfo.td:1138
421 CALLrr = 406, // SparcInstrInfo.td:1122
422 CALLrri = 407, // SparcInstrInfo.td:1135
423 CAMELLIA_F = 408, // SparcInstrCrypto.td:37
424 CAMELLIA_FL = 409, // SparcInstrCrypto.td:38
425 CAMELLIA_FLI = 410, // SparcInstrCrypto.td:41
426 CASAri = 411, // SparcInstrInfo.td:1800
427 CASArr = 412, // SparcInstrInfo.td:1792
428 CASXAri = 413, // SparcInstr64Bit.td:442
429 CASXArr = 414, // SparcInstr64Bit.td:435
430 CMASK16 = 415, // SparcInstrVIS.td:193
431 CMASK32 = 416, // SparcInstrVIS.td:195
432 CMASK8 = 417, // SparcInstrVIS.td:191
433 CPBCOND = 418, // SparcInstrInfo.td:1090
434 CPBCONDA = 419, // SparcInstrInfo.td:1093
435 CRC32C = 420, // SparcInstrCrypto.td:45
436 CWBCONDri = 421, // SparcInstrUAOSA.td:31
437 CWBCONDrr = 422, // SparcInstrUAOSA.td:28
438 CXBCONDri = 423, // SparcInstrUAOSA.td:31
439 CXBCONDrr = 424, // SparcInstrUAOSA.td:28
440 DES_IIP = 425, // SparcInstrCrypto.td:54
441 DES_IP = 426, // SparcInstrCrypto.td:51
442 DES_KEXPAND = 427, // SparcInstrCrypto.td:58
443 DES_ROUND = 428, // SparcInstrCrypto.td:49
444 DONE = 429, // SparcInstrInfo.td:1854
445 EDGE16 = 430, // SparcInstrVIS.td:146
446 EDGE16L = 431, // SparcInstrVIS.td:147
447 EDGE16LN = 432, // SparcInstrVIS.td:175
448 EDGE16N = 433, // SparcInstrVIS.td:174
449 EDGE32 = 434, // SparcInstrVIS.td:148
450 EDGE32L = 435, // SparcInstrVIS.td:149
451 EDGE32LN = 436, // SparcInstrVIS.td:177
452 EDGE32N = 437, // SparcInstrVIS.td:176
453 EDGE8 = 438, // SparcInstrVIS.td:144
454 EDGE8L = 439, // SparcInstrVIS.td:145
455 EDGE8LN = 440, // SparcInstrVIS.td:173
456 EDGE8N = 441, // SparcInstrVIS.td:172
457 FABSD = 442, // SparcInstrInfo.td:1708
458 FABSQ = 443, // SparcInstrInfo.td:1713
459 FABSS = 444, // SparcInstrInfo.td:1393
460 FADDD = 445, // SparcInstrInfo.td:1428
461 FADDQ = 446, // SparcInstrInfo.td:1433
462 FADDS = 447, // SparcInstrInfo.td:1423
463 FALIGNADATA = 448, // SparcInstrVIS.td:98
464 FAND = 449, // SparcInstrVIS.td:116
465 FANDNOT1 = 450, // SparcInstrVIS.td:129
466 FANDNOT1S = 451, // SparcInstrVIS.td:130
467 FANDNOT2 = 452, // SparcInstrVIS.td:131
468 FANDNOT2S = 453, // SparcInstrVIS.td:132
469 FANDS = 454, // SparcInstrVIS.td:117
470 FBCOND = 455, // SparcInstrInfo.td:1054
471 FBCONDA = 456, // SparcInstrInfo.td:1057
472 FBCONDA_V9 = 457, // SparcInstrInfo.td:1068
473 FBCOND_V9 = 458, // SparcInstrInfo.td:1064
474 FCHKSM16 = 459, // SparcInstrVIS.td:200
475 FCMPD = 460, // SparcInstrInfo.td:1519
476 FCMPD_V9 = 461, // SparcInstrInfo.td:1544
477 FCMPEQ16 = 462, // SparcInstrVIS.td:140
478 FCMPEQ32 = 463, // SparcInstrVIS.td:141
479 FCMPGT16 = 464, // SparcInstrVIS.td:134
480 FCMPGT32 = 465, // SparcInstrVIS.td:135
481 FCMPLE16 = 466, // SparcInstrVIS.td:136
482 FCMPLE32 = 467, // SparcInstrVIS.td:137
483 FCMPNE16 = 468, // SparcInstrVIS.td:138
484 FCMPNE32 = 469, // SparcInstrVIS.td:139
485 FCMPQ = 470, // SparcInstrInfo.td:1524
486 FCMPQ_V9 = 471, // SparcInstrInfo.td:1549
487 FCMPS = 472, // SparcInstrInfo.td:1514
488 FCMPS_V9 = 473, // SparcInstrInfo.td:1539
489 FDIVD = 474, // SparcInstrInfo.td:1495
490 FDIVQ = 475, // SparcInstrInfo.td:1500
491 FDIVS = 476, // SparcInstrInfo.td:1490
492 FDMULQ = 477, // SparcInstrInfo.td:1481
493 FDTOI = 478, // SparcInstrInfo.td:1341
494 FDTOQ = 479, // SparcInstrInfo.td:1368
495 FDTOS = 480, // SparcInstrInfo.td:1363
496 FDTOX = 481, // SparcInstr64Bit.td:399
497 FEXPAND = 482, // SparcInstrVIS.td:72
498 FHADDD = 483, // SparcInstrVIS.td:205
499 FHADDS = 484, // SparcInstrVIS.td:202
500 FHSUBD = 485, // SparcInstrVIS.td:211
501 FHSUBS = 486, // SparcInstrVIS.td:208
502 FITOD = 487, // SparcInstrInfo.td:1324
503 FITOQ = 488, // SparcInstrInfo.td:1329
504 FITOS = 489, // SparcInstrInfo.td:1319
505 FLCMPD = 490, // SparcInstrVIS.td:217
506 FLCMPS = 491, // SparcInstrVIS.td:214
507 FLUSH = 492, // SparcInstrInfo.td:1313
508 FLUSHW = 493, // SparcInstrInfo.td:601
509 FLUSHri = 494, // SparcInstrInfo.td:1306
510 FLUSHrr = 495, // SparcInstrInfo.td:1304
511 FMADDD = 496, // SparcInstrUAOSA.td:49
512 FMADDS = 497, // SparcInstrUAOSA.td:48
513 FMEAN16 = 498, // SparcInstrVIS.td:221
514 FMOVD = 499, // SparcInstrInfo.td:1692
515 FMOVD_FCC = 500, // SparcInstrInfo.td:1675
516 FMOVD_ICC = 501, // SparcInstrInfo.td:1656
517 FMOVD_XCC = 502, // SparcInstr64Bit.td:308
518 FMOVQ = 503, // SparcInstrInfo.td:1696
519 FMOVQ_FCC = 504, // SparcInstrInfo.td:1681
520 FMOVQ_ICC = 505, // SparcInstrInfo.td:1662
521 FMOVQ_XCC = 506, // SparcInstr64Bit.td:314
522 FMOVRD = 507, // SparcInstr64Bit.td:364
523 FMOVRQ = 508, // SparcInstr64Bit.td:369
524 FMOVRS = 509, // SparcInstr64Bit.td:360
525 FMOVS = 510, // SparcInstrInfo.td:1385
526 FMOVS_FCC = 511, // SparcInstrInfo.td:1670
527 FMOVS_ICC = 512, // SparcInstrInfo.td:1651
528 FMOVS_XCC = 513, // SparcInstr64Bit.td:303
529 FMSUBD = 514, // SparcInstrUAOSA.td:51
530 FMSUBS = 515, // SparcInstrUAOSA.td:50
531 FMUL8SUX16 = 516, // SparcInstrVIS.td:87
532 FMUL8ULX16 = 517, // SparcInstrVIS.td:88
533 FMUL8X16 = 518, // SparcInstrVIS.td:78
534 FMUL8X16AL = 519, // SparcInstrVIS.td:84
535 FMUL8X16AU = 520, // SparcInstrVIS.td:81
536 FMULD = 521, // SparcInstrInfo.td:1463
537 FMULD8SUX16 = 522, // SparcInstrVIS.td:89
538 FMULD8ULX16 = 523, // SparcInstrVIS.td:92
539 FMULQ = 524, // SparcInstrInfo.td:1468
540 FMULS = 525, // SparcInstrInfo.td:1457
541 FNADDD = 526, // SparcInstrVIS.td:226
542 FNADDS = 527, // SparcInstrVIS.td:223
543 FNAND = 528, // SparcInstrVIS.td:118
544 FNANDS = 529, // SparcInstrVIS.td:119
545 FNEGD = 530, // SparcInstrInfo.td:1699
546 FNEGQ = 531, // SparcInstrInfo.td:1704
547 FNEGS = 532, // SparcInstrInfo.td:1388
548 FNHADDD = 533, // SparcInstrVIS.td:232
549 FNHADDS = 534, // SparcInstrVIS.td:229
550 FNMADDD = 535, // SparcInstrUAOSA.td:54
551 FNMADDS = 536, // SparcInstrUAOSA.td:53
552 FNMSUBD = 537, // SparcInstrUAOSA.td:56
553 FNMSUBS = 538, // SparcInstrUAOSA.td:55
554 FNMULD = 539, // SparcInstrVIS.td:239
555 FNMULS = 540, // SparcInstrVIS.td:236
556 FNOR = 541, // SparcInstrVIS.td:114
557 FNORS = 542, // SparcInstrVIS.td:115
558 FNOT1 = 543, // SparcInstrVIS.td:108
559 FNOT1S = 544, // SparcInstrVIS.td:109
560 FNOT2 = 545, // SparcInstrVIS.td:110
561 FNOT2S = 546, // SparcInstrVIS.td:111
562 FNSMULD = 547, // SparcInstrVIS.td:242
563 FONE = 548, // SparcInstrVIS.td:102
564 FONES = 549, // SparcInstrVIS.td:103
565 FOR = 550, // SparcInstrVIS.td:112
566 FORNOT1 = 551, // SparcInstrVIS.td:125
567 FORNOT1S = 552, // SparcInstrVIS.td:126
568 FORNOT2 = 553, // SparcInstrVIS.td:127
569 FORNOT2S = 554, // SparcInstrVIS.td:128
570 FORS = 555, // SparcInstrVIS.td:113
571 FPACK16 = 556, // SparcInstrVIS.td:66
572 FPACK32 = 557, // SparcInstrVIS.td:67
573 FPACKFIX = 558, // SparcInstrVIS.td:69
574 FPADD16 = 559, // SparcInstrVIS.td:57
575 FPADD16S = 560, // SparcInstrVIS.td:58
576 FPADD32 = 561, // SparcInstrVIS.td:59
577 FPADD32S = 562, // SparcInstrVIS.td:60
578 FPADD64 = 563, // SparcInstrVIS.td:246
579 FPMADDX = 564, // SparcInstrUAOSA.td:66
580 FPMADDXHI = 565, // SparcInstrUAOSA.td:67
581 FPMERGE = 566, // SparcInstrVIS.td:74
582 FPSUB16 = 567, // SparcInstrVIS.td:61
583 FPSUB16S = 568, // SparcInstrVIS.td:62
584 FPSUB32 = 569, // SparcInstrVIS.td:63
585 FPSUB32S = 570, // SparcInstrVIS.td:64
586 FQTOD = 571, // SparcInstrInfo.td:1378
587 FQTOI = 572, // SparcInstrInfo.td:1346
588 FQTOS = 573, // SparcInstrInfo.td:1373
589 FQTOX = 574, // SparcInstr64Bit.td:404
590 FSLAS16 = 575, // SparcInstrVIS.td:252
591 FSLAS32 = 576, // SparcInstrVIS.td:254
592 FSLL16 = 577, // SparcInstrVIS.td:248
593 FSLL32 = 578, // SparcInstrVIS.td:250
594 FSMULD = 579, // SparcInstrInfo.td:1474
595 FSQRTD = 580, // SparcInstrInfo.td:1409
596 FSQRTQ = 581, // SparcInstrInfo.td:1414
597 FSQRTS = 582, // SparcInstrInfo.td:1404
598 FSRA16 = 583, // SparcInstrVIS.td:253
599 FSRA32 = 584, // SparcInstrVIS.td:255
600 FSRC1 = 585, // SparcInstrVIS.td:104
601 FSRC1S = 586, // SparcInstrVIS.td:105
602 FSRC2 = 587, // SparcInstrVIS.td:106
603 FSRC2S = 588, // SparcInstrVIS.td:107
604 FSRL16 = 589, // SparcInstrVIS.td:249
605 FSRL32 = 590, // SparcInstrVIS.td:251
606 FSTOD = 591, // SparcInstrInfo.td:1353
607 FSTOI = 592, // SparcInstrInfo.td:1336
608 FSTOQ = 593, // SparcInstrInfo.td:1358
609 FSTOX = 594, // SparcInstr64Bit.td:395
610 FSUBD = 595, // SparcInstrInfo.td:1444
611 FSUBQ = 596, // SparcInstrInfo.td:1449
612 FSUBS = 597, // SparcInstrInfo.td:1439
613 FXNOR = 598, // SparcInstrVIS.td:122
614 FXNORS = 599, // SparcInstrVIS.td:123
615 FXOR = 600, // SparcInstrVIS.td:120
616 FXORS = 601, // SparcInstrVIS.td:121
617 FXTOD = 602, // SparcInstr64Bit.td:385
618 FXTOQ = 603, // SparcInstr64Bit.td:390
619 FXTOS = 604, // SparcInstr64Bit.td:381
620 FZERO = 605, // SparcInstrVIS.td:100
621 FZEROS = 606, // SparcInstrVIS.td:101
622 GDOP_LDXrr = 607, // SparcInstr64Bit.td:216
623 GDOP_LDrr = 608, // SparcInstrInfo.td:727
624 INVALW = 609, // SparcInstrUAOSA.td:40
625 JMPLri = 610, // SparcInstrInfo.td:1153
626 JMPLrr = 611, // SparcInstrInfo.td:1148
627 LDAri = 612, // SparcInstrInfo.td:521
628 LDArr = 613, // SparcInstrInfo.td:516
629 LDCSRri = 614, // SparcInstrInfo.td:706
630 LDCSRrr = 615, // SparcInstrInfo.td:704
631 LDCri = 616, // SparcInstrInfo.td:506
632 LDCrr = 617, // SparcInstrInfo.td:501
633 LDDAri = 618, // SparcInstrInfo.td:521
634 LDDArr = 619, // SparcInstrInfo.td:516
635 LDDCri = 620, // SparcInstrInfo.td:506
636 LDDCrr = 621, // SparcInstrInfo.td:501
637 LDDFAri = 622, // SparcInstrInfo.td:521
638 LDDFArr = 623, // SparcInstrInfo.td:516
639 LDDFri = 624, // SparcInstrInfo.td:506
640 LDDFrr = 625, // SparcInstrInfo.td:501
641 LDDri = 626, // SparcInstrInfo.td:506
642 LDDrr = 627, // SparcInstrInfo.td:501
643 LDFAri = 628, // SparcInstrInfo.td:521
644 LDFArr = 629, // SparcInstrInfo.td:516
645 LDFSRri = 630, // SparcInstrInfo.td:715
646 LDFSRrr = 631, // SparcInstrInfo.td:713
647 LDFri = 632, // SparcInstrInfo.td:506
648 LDFrr = 633, // SparcInstrInfo.td:501
649 LDQFAri = 634, // SparcInstrInfo.td:521
650 LDQFArr = 635, // SparcInstrInfo.td:516
651 LDQFri = 636, // SparcInstrInfo.td:506
652 LDQFrr = 637, // SparcInstrInfo.td:501
653 LDSBAri = 638, // SparcInstrInfo.td:521
654 LDSBArr = 639, // SparcInstrInfo.td:516
655 LDSBri = 640, // SparcInstrInfo.td:506
656 LDSBrr = 641, // SparcInstrInfo.td:501
657 LDSHAri = 642, // SparcInstrInfo.td:521
658 LDSHArr = 643, // SparcInstrInfo.td:516
659 LDSHri = 644, // SparcInstrInfo.td:506
660 LDSHrr = 645, // SparcInstrInfo.td:501
661 LDSTUBAri = 646, // SparcInstrInfo.td:806
662 LDSTUBArr = 647, // SparcInstrInfo.td:802
663 LDSTUBri = 648, // SparcInstrInfo.td:800
664 LDSTUBrr = 649, // SparcInstrInfo.td:798
665 LDSWAri = 650, // SparcInstrInfo.td:521
666 LDSWArr = 651, // SparcInstrInfo.td:516
667 LDSWri = 652, // SparcInstrInfo.td:506
668 LDSWrr = 653, // SparcInstrInfo.td:501
669 LDUBAri = 654, // SparcInstrInfo.td:521
670 LDUBArr = 655, // SparcInstrInfo.td:516
671 LDUBri = 656, // SparcInstrInfo.td:506
672 LDUBrr = 657, // SparcInstrInfo.td:501
673 LDUHAri = 658, // SparcInstrInfo.td:521
674 LDUHArr = 659, // SparcInstrInfo.td:516
675 LDUHri = 660, // SparcInstrInfo.td:506
676 LDUHrr = 661, // SparcInstrInfo.td:501
677 LDXAri = 662, // SparcInstrInfo.td:521
678 LDXArr = 663, // SparcInstrInfo.td:516
679 LDXFSRri = 664, // SparcInstrInfo.td:721
680 LDXFSRrr = 665, // SparcInstrInfo.td:719
681 LDXri = 666, // SparcInstrInfo.td:506
682 LDXrr = 667, // SparcInstrInfo.td:501
683 LDri = 668, // SparcInstrInfo.td:506
684 LDrr = 669, // SparcInstrInfo.td:501
685 LZCNT = 670, // SparcInstrVIS.td:258
686 MD5 = 671, // SparcInstrCrypto.td:65
687 MEMBARi = 672, // SparcInstrInfo.td:1782
688 MONTMUL = 673, // SparcInstrCrypto.td:95
689 MONTSQR = 674, // SparcInstrCrypto.td:96
690 MOVDTOX = 675, // SparcInstrVIS.td:266
691 MOVFCCri = 676, // SparcInstrInfo.td:1642
692 MOVFCCrr = 677, // SparcInstrInfo.td:1637
693 MOVICCri = 678, // SparcInstrInfo.td:1628
694 MOVICCrr = 679, // SparcInstrInfo.td:1622
695 MOVRri = 680, // SparcInstr64Bit.td:352
696 MOVRrr = 681, // SparcInstr64Bit.td:347
697 MOVSTOSW = 682, // SparcInstrVIS.td:262
698 MOVSTOUW = 683, // SparcInstrVIS.td:264
699 MOVWTOS = 684, // SparcInstrVIS.td:268
700 MOVXCCri = 685, // SparcInstr64Bit.td:295
701 MOVXCCrr = 686, // SparcInstr64Bit.td:290
702 MOVXTOD = 687, // SparcInstrVIS.td:270
703 MPMUL = 688, // SparcInstrCrypto.td:94
704 MULSCCri = 689, // SparcInstrInfo.td:492
705 MULSCCrr = 690, // SparcInstrInfo.td:488
706 MULXri = 691, // SparcInstrInfo.td:478
707 MULXrr = 692, // SparcInstrInfo.td:473
708 NOP = 693, // SparcInstrInfo.td:843
709 NORMALW = 694, // SparcInstrUAOSA.td:41
710 ORCCri = 695, // SparcInstrInfo.td:492
711 ORCCrr = 696, // SparcInstrInfo.td:488
712 ORNCCri = 697, // SparcInstrInfo.td:492
713 ORNCCrr = 698, // SparcInstrInfo.td:488
714 ORNri = 699, // SparcInstrInfo.td:862
715 ORNrr = 700, // SparcInstrInfo.td:858
716 ORri = 701, // SparcInstrInfo.td:478
717 ORrr = 702, // SparcInstrInfo.td:473
718 OTHERW = 703, // SparcInstrUAOSA.td:42
719 PDIST = 704, // SparcInstrVIS.td:151
720 PDISTN = 705, // SparcInstrVIS.td:274
721 POPCrr = 706, // SparcInstrInfo.td:1775
722 PREFETCHAi = 707, // SparcInstrInfo.td:1878
723 PREFETCHAr = 708, // SparcInstrInfo.td:1874
724 PREFETCHi = 709, // SparcInstrInfo.td:1871
725 PREFETCHr = 710, // SparcInstrInfo.td:1868
726 PWRPSRri = 711, // SparcInstrInfo.td:1835
727 PWRPSRrr = 712, // SparcInstrInfo.td:1832
728 RDASR = 713, // SparcInstrInfo.td:1232
729 RDFQ = 714, // SparcInstrInfo.td:1897
730 RDPR = 715, // SparcInstrInfo.td:1888
731 RDPSR = 716, // SparcInstrInfo.td:1239
732 RDTBR = 717, // SparcInstrInfo.td:1249
733 RDWIM = 718, // SparcInstrInfo.td:1244
734 RESTORED = 719, // SparcInstrInfo.td:1863
735 RESTOREri = 720, // SparcInstrInfo.td:492
736 RESTORErr = 721, // SparcInstrInfo.td:488
737 RET = 722, // SparcInstrInfo.td:1172
738 RETL = 723, // SparcInstrInfo.td:1165
739 RETRY = 724, // SparcInstrInfo.td:1857
740 RETTri = 725, // SparcInstrInfo.td:1187
741 RETTrr = 726, // SparcInstrInfo.td:1182
742 SAVED = 727, // SparcInstrInfo.td:1860
743 SAVEri = 728, // SparcInstrInfo.td:492
744 SAVErr = 729, // SparcInstrInfo.td:488
745 SDIVCCri = 730, // SparcInstrInfo.td:492
746 SDIVCCrr = 731, // SparcInstrInfo.td:488
747 SDIVXri = 732, // SparcInstrInfo.td:478
748 SDIVXrr = 733, // SparcInstrInfo.td:473
749 SDIVri = 734, // SparcInstrInfo.td:492
750 SDIVrr = 735, // SparcInstrInfo.td:488
751 SETHIi = 736, // SparcInstrInfo.td:834
752 SHA1 = 737, // SparcInstrCrypto.td:68
753 SHA256 = 738, // SparcInstrCrypto.td:71
754 SHA512 = 739, // SparcInstrCrypto.td:75
755 SHUTDOWN = 740, // SparcInstrVIS.td:157
756 SIAM = 741, // SparcInstrVIS.td:169
757 SIR = 742, // SparcInstrInfo.td:1786
758 SLLXri = 743, // SparcInstrFormats.td:299
759 SLLXrr = 744, // SparcInstrFormats.td:295
760 SLLri = 745, // SparcInstrFormats.td:299
761 SLLrr = 746, // SparcInstrFormats.td:295
762 SMACri = 747, // SparcInstrInfo.td:1813
763 SMACrr = 748, // SparcInstrInfo.td:1808
764 SMULCCri = 749, // SparcInstrInfo.td:492
765 SMULCCrr = 750, // SparcInstrInfo.td:488
766 SMULri = 751, // SparcInstrInfo.td:478
767 SMULrr = 752, // SparcInstrInfo.td:473
768 SRAXri = 753, // SparcInstrFormats.td:299
769 SRAXrr = 754, // SparcInstrFormats.td:295
770 SRAri = 755, // SparcInstrFormats.td:299
771 SRArr = 756, // SparcInstrFormats.td:295
772 SRLXri = 757, // SparcInstrFormats.td:299
773 SRLXrr = 758, // SparcInstrFormats.td:295
774 SRLri = 759, // SparcInstrFormats.td:299
775 SRLrr = 760, // SparcInstrFormats.td:295
776 STAri = 761, // SparcInstrInfo.td:559
777 STArr = 762, // SparcInstrInfo.td:553
778 STBAR = 763, // SparcInstrInfo.td:1294
779 STBAri = 764, // SparcInstrInfo.td:559
780 STBArr = 765, // SparcInstrInfo.td:553
781 STBri = 766, // SparcInstrInfo.td:542
782 STBrr = 767, // SparcInstrInfo.td:537
783 STCSRri = 768, // SparcInstrInfo.td:762
784 STCSRrr = 769, // SparcInstrInfo.td:760
785 STCri = 770, // SparcInstrInfo.td:542
786 STCrr = 771, // SparcInstrInfo.td:537
787 STDAri = 772, // SparcInstrInfo.td:559
788 STDArr = 773, // SparcInstrInfo.td:553
789 STDCQri = 774, // SparcInstrInfo.td:768
790 STDCQrr = 775, // SparcInstrInfo.td:766
791 STDCri = 776, // SparcInstrInfo.td:542
792 STDCrr = 777, // SparcInstrInfo.td:537
793 STDFAri = 778, // SparcInstrInfo.td:559
794 STDFArr = 779, // SparcInstrInfo.td:553
795 STDFQri = 780, // SparcInstrInfo.td:783
796 STDFQrr = 781, // SparcInstrInfo.td:781
797 STDFri = 782, // SparcInstrInfo.td:542
798 STDFrr = 783, // SparcInstrInfo.td:537
799 STDri = 784, // SparcInstrInfo.td:542
800 STDrr = 785, // SparcInstrInfo.td:537
801 STFAri = 786, // SparcInstrInfo.td:559
802 STFArr = 787, // SparcInstrInfo.td:553
803 STFSRri = 788, // SparcInstrInfo.td:777
804 STFSRrr = 789, // SparcInstrInfo.td:775
805 STFri = 790, // SparcInstrInfo.td:542
806 STFrr = 791, // SparcInstrInfo.td:537
807 STHAri = 792, // SparcInstrInfo.td:559
808 STHArr = 793, // SparcInstrInfo.td:553
809 STHri = 794, // SparcInstrInfo.td:542
810 STHrr = 795, // SparcInstrInfo.td:537
811 STQFAri = 796, // SparcInstrInfo.td:559
812 STQFArr = 797, // SparcInstrInfo.td:553
813 STQFri = 798, // SparcInstrInfo.td:542
814 STQFrr = 799, // SparcInstrInfo.td:537
815 STXAri = 800, // SparcInstrInfo.td:559
816 STXArr = 801, // SparcInstrInfo.td:553
817 STXFSRri = 802, // SparcInstrInfo.td:790
818 STXFSRrr = 803, // SparcInstrInfo.td:788
819 STXri = 804, // SparcInstrInfo.td:542
820 STXrr = 805, // SparcInstrInfo.td:537
821 STri = 806, // SparcInstrInfo.td:542
822 STrr = 807, // SparcInstrInfo.td:537
823 SUBCCri = 808, // SparcInstrInfo.td:478
824 SUBCCrr = 809, // SparcInstrInfo.td:473
825 SUBCri = 810, // SparcInstrInfo.td:492
826 SUBCrr = 811, // SparcInstrInfo.td:488
827 SUBEri = 812, // SparcInstrInfo.td:478
828 SUBErr = 813, // SparcInstrInfo.td:473
829 SUBri = 814, // SparcInstrInfo.td:478
830 SUBrr = 815, // SparcInstrInfo.td:473
831 SWAPAri = 816, // SparcInstrInfo.td:826
832 SWAPArr = 817, // SparcInstrInfo.td:821
833 SWAPri = 818, // SparcInstrInfo.td:817
834 SWAPrr = 819, // SparcInstrInfo.td:813
835 TA1 = 820, // SparcInstrInfo.td:1228
836 TA3 = 821, // SparcInstrInfo.td:605
837 TA5 = 822, // SparcInstrInfo.td:1225
838 TADDCCTVri = 823, // SparcInstrInfo.td:492
839 TADDCCTVrr = 824, // SparcInstrInfo.td:488
840 TADDCCri = 825, // SparcInstrInfo.td:492
841 TADDCCrr = 826, // SparcInstrInfo.td:488
842 TAIL_CALL = 827, // SparcInstrInfo.td:1594
843 TAIL_CALLri = 828, // SparcInstrInfo.td:1608
844 TICCri = 829, // SparcInstrInfo.td:1214
845 TICCrr = 830, // SparcInstrInfo.td:1210
846 TLS_ADDrr = 831, // SparcInstrInfo.td:1560
847 TLS_CALL = 832, // SparcInstrInfo.td:1577
848 TLS_LDXrr = 833, // SparcInstr64Bit.td:210
849 TLS_LDrr = 834, // SparcInstrInfo.td:1568
850 TRAPri = 835, // SparcInstrInfo.td:1203
851 TRAPrr = 836, // SparcInstrInfo.td:1199
852 TSUBCCTVri = 837, // SparcInstrInfo.td:492
853 TSUBCCTVrr = 838, // SparcInstrInfo.td:488
854 TSUBCCri = 839, // SparcInstrInfo.td:492
855 TSUBCCrr = 840, // SparcInstrInfo.td:488
856 TXCCri = 841, // SparcInstrInfo.td:1214
857 TXCCrr = 842, // SparcInstrInfo.td:1210
858 UDIVCCri = 843, // SparcInstrInfo.td:492
859 UDIVCCrr = 844, // SparcInstrInfo.td:488
860 UDIVXri = 845, // SparcInstrInfo.td:478
861 UDIVXrr = 846, // SparcInstrInfo.td:473
862 UDIVri = 847, // SparcInstrInfo.td:492
863 UDIVrr = 848, // SparcInstrInfo.td:488
864 UMACri = 849, // SparcInstrInfo.td:1823
865 UMACrr = 850, // SparcInstrInfo.td:1818
866 UMULCCri = 851, // SparcInstrInfo.td:492
867 UMULCCrr = 852, // SparcInstrInfo.td:488
868 UMULXHI = 853, // SparcInstrVIS.td:276
869 UMULri = 854, // SparcInstrInfo.td:478
870 UMULrr = 855, // SparcInstrInfo.td:473
871 UNIMP = 856, // SparcInstrInfo.td:1299
872 V9FCMPD = 857, // SparcInstrInfo.td:1723
873 V9FCMPED = 858, // SparcInstrInfo.td:1735
874 V9FCMPEQ = 859, // SparcInstrInfo.td:1738
875 V9FCMPES = 860, // SparcInstrInfo.td:1732
876 V9FCMPQ = 861, // SparcInstrInfo.td:1726
877 V9FCMPS = 862, // SparcInstrInfo.td:1720
878 V9FMOVD_FCC = 863, // SparcInstrInfo.td:1759
879 V9FMOVQ_FCC = 864, // SparcInstrInfo.td:1764
880 V9FMOVS_FCC = 865, // SparcInstrInfo.td:1755
881 V9MOVFCCri = 866, // SparcInstrInfo.td:1751
882 V9MOVFCCrr = 867, // SparcInstrInfo.td:1747
883 WRASRri = 868, // SparcInstrInfo.td:1258
884 WRASRrr = 869, // SparcInstrInfo.td:1255
885 WRPRri = 870, // SparcInstrInfo.td:1907
886 WRPRrr = 871, // SparcInstrInfo.td:1904
887 WRPSRri = 872, // SparcInstrInfo.td:1268
888 WRPSRrr = 873, // SparcInstrInfo.td:1265
889 WRTBRri = 874, // SparcInstrInfo.td:1286
890 WRTBRrr = 875, // SparcInstrInfo.td:1283
891 WRWIMri = 876, // SparcInstrInfo.td:1277
892 WRWIMrr = 877, // SparcInstrInfo.td:1274
893 XMULX = 878, // SparcInstrVIS.td:277
894 XMULXHI = 879, // SparcInstrVIS.td:278
895 XNORCCri = 880, // SparcInstrInfo.td:492
896 XNORCCrr = 881, // SparcInstrInfo.td:488
897 XNORri = 882, // SparcInstrInfo.td:871
898 XNORrr = 883, // SparcInstrInfo.td:867
899 XORCCri = 884, // SparcInstrInfo.td:492
900 XORCCrr = 885, // SparcInstrInfo.td:488
901 XORri = 886, // SparcInstrInfo.td:478
902 XORrr = 887, // SparcInstrInfo.td:473
903 INSTRUCTION_LIST_END = 888
904 };
905 enum RegClassByHwModeUses : uint16_t {
906 sparc_ptr_rc,
907 };
908
909} // namespace llvm::SP
910
911#endif // GET_INSTRINFO_ENUM
912
913#ifdef GET_INSTRINFO_SCHED_ENUM
914#undef GET_INSTRINFO_SCHED_ENUM
915
916namespace llvm::SP::Sched {
917
918 enum {
919 NoInstrModel = 0,
920 IIC_iu_instr = 1,
921 IIC_fpu_normal_instr = 2,
922 IIC_jmp_or_call = 3,
923 IIC_fpu_abs = 4,
924 IIC_fpu_fast_instr = 5,
925 IIC_fpu_divd = 6,
926 IIC_fpu_divs = 7,
927 IIC_fpu_muld = 8,
928 IIC_fpu_muls = 9,
929 IIC_fpu_negs = 10,
930 IIC_fpu_sqrtd = 11,
931 IIC_fpu_sqrts = 12,
932 IIC_fpu_stod = 13,
933 IIC_ldd = 14,
934 IIC_iu_or_fpu_instr = 15,
935 IIC_iu_div = 16,
936 IIC_smac_umac = 17,
937 IIC_iu_smul = 18,
938 IIC_st = 19,
939 IIC_std = 20,
940 IIC_iu_umul = 21,
941 SCHED_LIST_END = 22
942 };
943
944} // namespace llvm::SP::Sched
945
946#endif // GET_INSTRINFO_SCHED_ENUM
947
948#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
949
950namespace llvm {
951
952struct SparcInstrTable {
953 MCInstrDesc Insts[888];
954 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
955 MCPhysReg ImplicitOps[218];
956 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
957 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
958 MCOperandInfo OperandInfo[575];
959};
960} // namespace llvm
961
962#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
963
964#ifdef GET_INSTRINFO_MC_DESC
965#undef GET_INSTRINFO_MC_DESC
966
967namespace llvm {
968
969static_assert((sizeof SparcInstrTable::ImplicitOps + sizeof SparcInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
970static constexpr unsigned SparcOpInfoBase = (sizeof SparcInstrTable::ImplicitOps + sizeof SparcInstrTable::Padding) / sizeof(MCOperandInfo);
971
972extern const SparcInstrTable SparcDescs = {
973 {
974 { 887, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // XORrr
975 { 886, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // XORri
976 { 885, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XORCCrr
977 { 884, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XORCCri
978 { 883, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // XNORrr
979 { 882, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XNORri
980 { 881, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XNORCCrr
981 { 880, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XNORCCri
982 { 879, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XMULXHI
983 { 878, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XMULX
984 { 877, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 417, 141, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRWIMrr
985 { 876, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 167, 141, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRWIMri
986 { 875, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 417, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRTBRrr
987 { 874, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 167, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRTBRri
988 { 873, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 417, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPSRrr
989 { 872, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 167, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPSRri
990 { 871, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 572, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPRrr
991 { 870, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 569, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPRri
992 { 869, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 566, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRASRrr
993 { 868, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 563, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRASRri
994 { 867, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 558, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9MOVFCCrr
995 { 866, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 553, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9MOVFCCri
996 { 865, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 548, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FMOVS_FCC
997 { 864, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 543, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FMOVQ_FCC
998 { 863, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 538, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FMOVD_FCC
999 { 862, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 268, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPS
1000 { 861, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 535, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPQ
1001 { 860, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 268, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPES
1002 { 859, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 535, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPEQ
1003 { 858, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 265, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPED
1004 { 857, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 265, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPD
1005 { 856, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UNIMP
1006 { 855, 3, 1, 4, 21, 0, 1, SparcOpInfoBase + 175, 215, 0, 0x0ULL }, // UMULrr
1007 { 854, 3, 1, 4, 21, 0, 1, SparcOpInfoBase + 172, 215, 0, 0x0ULL }, // UMULri
1008 { 853, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0, 0x0ULL }, // UMULXHI
1009 { 852, 3, 1, 4, 21, 0, 2, SparcOpInfoBase + 175, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMULCCrr
1010 { 851, 3, 1, 4, 21, 0, 2, SparcOpInfoBase + 172, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMULCCri
1011 { 850, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 175, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMACrr
1012 { 849, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 172, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMACri
1013 { 848, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 175, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVrr
1014 { 847, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 172, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVri
1015 { 846, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVXrr
1016 { 845, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 414, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVXri
1017 { 844, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 175, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVCCrr
1018 { 843, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 172, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVCCri
1019 { 842, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 440, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TXCCrr
1020 { 841, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 528, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TXCCri
1021 { 840, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCrr
1022 { 839, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCri
1023 { 838, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCTVrr
1024 { 837, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCTVri
1025 { 836, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 440, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAPrr
1026 { 835, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 528, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAPri
1027 { 834, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // TLS_LDrr
1028 { 833, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // TLS_LDXrr
1029 { 832, 2, 0, 4, 3, 1, 0, SparcOpInfoBase + 189, 217, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // TLS_CALL
1030 { 831, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 531, 0, 0, 0x0ULL }, // TLS_ADDrr
1031 { 830, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 440, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TICCrr
1032 { 829, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 528, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TICCri
1033 { 828, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 191, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // TAIL_CALLri
1034 { 827, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 188, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // TAIL_CALL
1035 { 826, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCrr
1036 { 825, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCri
1037 { 824, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCTVrr
1038 { 823, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCTVri
1039 { 822, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TA5
1040 { 821, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TA3
1041 { 820, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TA1
1042 { 819, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 524, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // SWAPrr
1043 { 818, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 515, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // SWAPri
1044 { 817, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 519, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWAPArr
1045 { 816, 4, 1, 4, 1, 1, 0, SparcOpInfoBase + 515, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWAPAri
1046 { 815, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // SUBrr
1047 { 814, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // SUBri
1048 { 813, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 175, 5, 0, 0x0ULL }, // SUBErr
1049 { 812, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 172, 5, 0, 0x0ULL }, // SUBEri
1050 { 811, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SUBCrr
1051 { 810, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SUBCri
1052 { 809, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBCCrr
1053 { 808, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBCCri
1054 { 807, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 450, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STrr
1055 { 806, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 443, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STri
1056 { 805, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 512, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STXrr
1057 { 804, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 505, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STXri
1058 { 803, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXFSRrr
1059 { 802, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 191, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXFSRri
1060 { 801, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 508, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXArr
1061 { 800, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 505, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXAri
1062 { 799, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 502, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STQFrr
1063 { 798, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 495, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STQFri
1064 { 797, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 498, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STQFArr
1065 { 796, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 495, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STQFAri
1066 { 795, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 450, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STHrr
1067 { 794, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 443, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STHri
1068 { 793, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STHArr
1069 { 792, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 443, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STHAri
1070 { 791, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 492, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STFrr
1071 { 790, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 485, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STFri
1072 { 789, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 193, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFSRrr
1073 { 788, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 191, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFSRri
1074 { 787, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 488, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFArr
1075 { 786, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 485, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFAri
1076 { 785, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 482, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDrr
1077 { 784, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 459, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDri
1078 { 783, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 479, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDFrr
1079 { 782, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 472, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDFri
1080 { 781, 2, 0, 4, 20, 0, 1, SparcOpInfoBase + 193, 139, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFQrr
1081 { 780, 2, 0, 4, 20, 0, 1, SparcOpInfoBase + 191, 139, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFQri
1082 { 779, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 475, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFArr
1083 { 778, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 472, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFAri
1084 { 777, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 469, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDCrr
1085 { 776, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 466, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDCri
1086 { 775, 2, 0, 4, 20, 1, 0, SparcOpInfoBase + 193, 216, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDCQrr
1087 { 774, 2, 0, 4, 20, 1, 0, SparcOpInfoBase + 191, 216, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDCQri
1088 { 773, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 462, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDArr
1089 { 772, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 459, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDAri
1090 { 771, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 456, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STCrr
1091 { 770, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 453, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STCri
1092 { 769, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 193, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STCSRrr
1093 { 768, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 191, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STCSRri
1094 { 767, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 450, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STBrr
1095 { 766, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 443, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STBri
1096 { 765, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STBArr
1097 { 764, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 443, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STBAri
1098 { 763, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STBAR
1099 { 762, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STArr
1100 { 761, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 443, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STAri
1101 { 760, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // SRLrr
1102 { 759, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 440, 0, 0, 0x0ULL }, // SRLri
1103 { 758, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 437, 0, 0, 0x0ULL }, // SRLXrr
1104 { 757, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 434, 0, 0, 0x0ULL }, // SRLXri
1105 { 756, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // SRArr
1106 { 755, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 440, 0, 0, 0x0ULL }, // SRAri
1107 { 754, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 437, 0, 0, 0x0ULL }, // SRAXrr
1108 { 753, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 434, 0, 0, 0x0ULL }, // SRAXri
1109 { 752, 3, 1, 4, 18, 0, 1, SparcOpInfoBase + 175, 215, 0, 0x0ULL }, // SMULrr
1110 { 751, 3, 1, 4, 18, 0, 1, SparcOpInfoBase + 172, 215, 0, 0x0ULL }, // SMULri
1111 { 750, 3, 1, 4, 18, 0, 2, SparcOpInfoBase + 175, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMULCCrr
1112 { 749, 3, 1, 4, 18, 0, 2, SparcOpInfoBase + 172, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMULCCri
1113 { 748, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 175, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMACrr
1114 { 747, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 172, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMACri
1115 { 746, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // SLLrr
1116 { 745, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 440, 0, 0, 0x0ULL }, // SLLri
1117 { 744, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 437, 0, 0, 0x0ULL }, // SLLXrr
1118 { 743, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 434, 0, 0, 0x0ULL }, // SLLXri
1119 { 742, 1, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SIR
1120 { 741, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SIAM
1121 { 740, 0, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHUTDOWN
1122 { 739, 0, 0, 4, 0, 24, 8, SparcOpInfoBase + 1, 177, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHA512
1123 { 738, 0, 0, 4, 0, 12, 4, SparcOpInfoBase + 1, 161, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHA256
1124 { 737, 0, 0, 4, 0, 11, 3, SparcOpInfoBase + 1, 147, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHA1
1125 { 736, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 167, 0, 0, 0x0ULL }, // SETHIi
1126 { 735, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 175, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVrr
1127 { 734, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 172, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVri
1128 { 733, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVXrr
1129 { 732, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 414, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVXri
1130 { 731, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 175, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVCCrr
1131 { 730, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 172, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVCCri
1132 { 729, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SAVErr
1133 { 728, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SAVEri
1134 { 727, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SAVED
1135 { 726, 2, 0, 4, 3, 0, 0, SparcOpInfoBase + 193, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RETTrr
1136 { 725, 2, 0, 4, 3, 0, 0, SparcOpInfoBase + 191, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RETTri
1137 { 724, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RETRY
1138 { 723, 1, 0, 4, 3, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // RETL
1139 { 722, 1, 0, 4, 3, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RET
1140 { 721, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RESTORErr
1141 { 720, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RESTOREri
1142 { 719, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RESTORED
1143 { 718, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 431, 141, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDWIM
1144 { 717, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 431, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDTBR
1145 { 716, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 431, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDPSR
1146 { 715, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 432, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDPR
1147 { 714, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 431, 139, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDFQ
1148 { 713, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 429, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDASR
1149 { 712, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 417, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PWRPSRrr
1150 { 711, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 167, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PWRPSRri
1151 { 710, 3, 0, 4, 1, 0, 0, SparcOpInfoBase + 426, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHr
1152 { 709, 3, 0, 4, 1, 0, 0, SparcOpInfoBase + 419, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHi
1153 { 708, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 422, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHAr
1154 { 707, 3, 0, 4, 1, 1, 0, SparcOpInfoBase + 419, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHAi
1155 { 706, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 417, 0, 0, 0x0ULL }, // POPCrr
1156 { 705, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PDISTN
1157 { 704, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PDIST
1158 { 703, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // OTHERW
1159 { 702, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ORrr
1160 { 701, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // ORri
1161 { 700, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ORNrr
1162 { 699, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORNri
1163 { 698, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORNCCrr
1164 { 697, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORNCCri
1165 { 696, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORCCrr
1166 { 695, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORCCri
1167 { 694, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NORMALW
1168 { 693, 0, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NOP
1169 { 692, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 178, 0, 0, 0x0ULL }, // MULXrr
1170 { 691, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 414, 0, 0, 0x0ULL }, // MULXri
1171 { 690, 3, 1, 4, 1, 2, 2, SparcOpInfoBase + 175, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULSCCrr
1172 { 689, 3, 1, 4, 1, 2, 2, SparcOpInfoBase + 172, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULSCCri
1173 { 688, 1, 0, 4, 0, 52, 52, SparcOpInfoBase + 1, 30, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MPMUL
1174 { 687, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 412, 0, 0, 0x0ULL }, // MOVXTOD
1175 { 686, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 394, 4, 0, 0x0ULL }, // MOVXCCrr
1176 { 685, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 390, 4, 0, 0x0ULL }, // MOVXCCri
1177 { 684, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 410, 0, 0, 0x0ULL }, // MOVWTOS
1178 { 683, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 408, 0, 0, 0x0ULL }, // MOVSTOUW
1179 { 682, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 408, 0, 0, 0x0ULL }, // MOVSTOSW
1180 { 681, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 403, 0, 0, 0x0ULL }, // MOVRrr
1181 { 680, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 398, 0, 0, 0x0ULL }, // MOVRri
1182 { 679, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 394, 4, 0, 0x0ULL }, // MOVICCrr
1183 { 678, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 390, 4, 0, 0x0ULL }, // MOVICCri
1184 { 677, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 394, 3, 0, 0x0ULL }, // MOVFCCrr
1185 { 676, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 390, 3, 0, 0x0ULL }, // MOVFCCri
1186 { 675, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 388, 0, 0, 0x0ULL }, // MOVDTOX
1187 { 674, 1, 0, 4, 0, 52, 52, SparcOpInfoBase + 1, 30, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MONTSQR
1188 { 673, 1, 0, 4, 0, 52, 52, SparcOpInfoBase + 1, 30, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MONTMUL
1189 { 672, 1, 0, 4, 1, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARi
1190 { 671, 0, 0, 4, 0, 10, 8, SparcOpInfoBase + 1, 12, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MD5
1191 { 670, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 386, 0, 0, 0x0ULL }, // LZCNT
1192 { 669, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDrr
1193 { 668, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDri
1194 { 667, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 383, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDXrr
1195 { 666, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 380, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDXri
1196 { 665, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 193, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXFSRrr
1197 { 664, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 191, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXFSRri
1198 { 663, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 314, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXArr
1199 { 662, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 380, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXAri
1200 { 661, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUHrr
1201 { 660, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUHri
1202 { 659, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUHArr
1203 { 658, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUHAri
1204 { 657, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUBrr
1205 { 656, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUBri
1206 { 655, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUBArr
1207 { 654, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUBAri
1208 { 653, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 383, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSWrr
1209 { 652, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 380, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSWri
1210 { 651, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 314, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSWArr
1211 { 650, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 380, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSWAri
1212 { 649, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBrr
1213 { 648, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBri
1214 { 647, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBArr
1215 { 646, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBAri
1216 { 645, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSHrr
1217 { 644, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSHri
1218 { 643, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSHArr
1219 { 642, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSHAri
1220 { 641, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSBrr
1221 { 640, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSBri
1222 { 639, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSBArr
1223 { 638, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSBAri
1224 { 637, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 377, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDQFrr
1225 { 636, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 370, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDQFri
1226 { 635, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 373, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDQFArr
1227 { 634, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 370, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDQFAri
1228 { 633, 3, 1, 4, 15, 0, 0, SparcOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDFrr
1229 { 632, 3, 1, 4, 15, 0, 0, SparcOpInfoBase + 360, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDFri
1230 { 631, 2, 0, 4, 15, 0, 1, SparcOpInfoBase + 193, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFSRrr
1231 { 630, 2, 0, 4, 15, 0, 1, SparcOpInfoBase + 191, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFSRri
1232 { 629, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 363, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFArr
1233 { 628, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 360, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFAri
1234 { 627, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 357, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDrr
1235 { 626, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 334, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDri
1236 { 625, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 354, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDFrr
1237 { 624, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 347, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDFri
1238 { 623, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 350, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDFArr
1239 { 622, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 347, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDFAri
1240 { 621, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 344, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDCrr
1241 { 620, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 341, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDCri
1242 { 619, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 337, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDArr
1243 { 618, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 334, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDAri
1244 { 617, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 331, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDCrr
1245 { 616, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 328, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDCri
1246 { 615, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 193, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDCSRrr
1247 { 614, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 191, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDCSRri
1248 { 613, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDArr
1249 { 612, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDAri
1250 { 611, 3, 1, 4, 3, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JMPLrr
1251 { 610, 3, 1, 4, 3, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JMPLri
1252 { 609, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INVALW
1253 { 608, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // GDOP_LDrr
1254 { 607, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 314, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // GDOP_LDXrr
1255 { 606, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0, 0x0ULL }, // FZEROS
1256 { 605, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 308, 0, 0, 0x0ULL }, // FZERO
1257 { 604, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 257, 0, 0, 0x0ULL }, // FXTOS
1258 { 603, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 259, 0, 0, 0x0ULL }, // FXTOQ
1259 { 602, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FXTOD
1260 { 601, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXORS
1261 { 600, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXOR
1262 { 599, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXNORS
1263 { 598, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXNOR
1264 { 597, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FSUBS
1265 { 596, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FSUBQ
1266 { 595, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FSUBD
1267 { 594, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 261, 0, 0, 0x0ULL }, // FSTOX
1268 { 593, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 263, 0, 0, 0x0ULL }, // FSTOQ
1269 { 592, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FSTOI
1270 { 591, 2, 1, 4, 13, 0, 0, SparcOpInfoBase + 261, 0, 0, 0x0ULL }, // FSTOD
1271 { 590, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRL32
1272 { 589, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRL16
1273 { 588, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC2S
1274 { 587, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC2
1275 { 586, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC1S
1276 { 585, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC1
1277 { 584, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRA32
1278 { 583, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRA16
1279 { 582, 2, 1, 4, 12, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FSQRTS
1280 { 581, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 241, 0, 0, 0x0ULL }, // FSQRTQ
1281 { 580, 2, 1, 4, 11, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FSQRTD
1282 { 579, 3, 1, 4, 8, 0, 0, SparcOpInfoBase + 305, 0, 0, 0x0ULL }, // FSMULD
1283 { 578, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLL32
1284 { 577, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLL16
1285 { 576, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLAS32
1286 { 575, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLAS16
1287 { 574, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 310, 0, 0, 0x0ULL }, // FQTOX
1288 { 573, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 312, 0, 0, 0x0ULL }, // FQTOS
1289 { 572, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 312, 0, 0, 0x0ULL }, // FQTOI
1290 { 571, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 310, 0, 0, 0x0ULL }, // FQTOD
1291 { 570, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB32S
1292 { 569, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB32
1293 { 568, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB16S
1294 { 567, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB16
1295 { 566, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPMERGE
1296 { 565, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPMADDXHI
1297 { 564, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPMADDX
1298 { 563, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD64
1299 { 562, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD32S
1300 { 561, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD32
1301 { 560, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD16S
1302 { 559, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD16
1303 { 558, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 257, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPACKFIX
1304 { 557, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPACK32
1305 { 556, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPACK16
1306 { 555, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORS
1307 { 554, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT2S
1308 { 553, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT2
1309 { 552, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT1S
1310 { 551, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT1
1311 { 550, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FOR
1312 { 549, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FONES
1313 { 548, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 308, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FONE
1314 { 547, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0, 0x0ULL }, // FNSMULD
1315 { 546, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT2S
1316 { 545, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT2
1317 { 544, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT1S
1318 { 543, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT1
1319 { 542, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNORS
1320 { 541, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOR
1321 { 540, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FNMULS
1322 { 539, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FNMULD
1323 { 538, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 271, 0, 0, 0x0ULL }, // FNMSUBS
1324 { 537, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0, 0x0ULL }, // FNMSUBD
1325 { 536, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 271, 0, 0, 0x0ULL }, // FNMADDS
1326 { 535, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0, 0x0ULL }, // FNMADDD
1327 { 534, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FNHADDS
1328 { 533, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FNHADDD
1329 { 532, 2, 1, 4, 10, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FNEGS
1330 { 531, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 241, 0, 0, 0x0ULL }, // FNEGQ
1331 { 530, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FNEGD
1332 { 529, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNANDS
1333 { 528, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNAND
1334 { 527, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FNADDS
1335 { 526, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FNADDD
1336 { 525, 3, 1, 4, 9, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FMULS
1337 { 524, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FMULQ
1338 { 523, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMULD8ULX16
1339 { 522, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMULD8SUX16
1340 { 521, 3, 1, 4, 8, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FMULD
1341 { 520, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8X16AU
1342 { 519, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8X16AL
1343 { 518, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 302, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8X16
1344 { 517, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8ULX16
1345 { 516, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8SUX16
1346 { 515, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 271, 0, 0, 0x0ULL }, // FMSUBS
1347 { 514, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0, 0x0ULL }, // FMSUBD
1348 { 513, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 298, 4, 0, 0x0ULL }, // FMOVS_XCC
1349 { 512, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 298, 4, 0, 0x0ULL }, // FMOVS_ICC
1350 { 511, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 298, 3, 0, 0x0ULL }, // FMOVS_FCC
1351 { 510, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMOVS
1352 { 509, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 293, 0, 0, 0x0ULL }, // FMOVRS
1353 { 508, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 288, 0, 0, 0x0ULL }, // FMOVRQ
1354 { 507, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 283, 0, 0, 0x0ULL }, // FMOVRD
1355 { 506, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 279, 4, 0, 0x0ULL }, // FMOVQ_XCC
1356 { 505, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 279, 4, 0, 0x0ULL }, // FMOVQ_ICC
1357 { 504, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 279, 3, 0, 0x0ULL }, // FMOVQ_FCC
1358 { 503, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMOVQ
1359 { 502, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 275, 4, 0, 0x0ULL }, // FMOVD_XCC
1360 { 501, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 275, 4, 0, 0x0ULL }, // FMOVD_ICC
1361 { 500, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 275, 3, 0, 0x0ULL }, // FMOVD_FCC
1362 { 499, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMOVD
1363 { 498, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMEAN16
1364 { 497, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 271, 0, 0, 0x0ULL }, // FMADDS
1365 { 496, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0, 0x0ULL }, // FMADDD
1366 { 495, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 193, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSHrr
1367 { 494, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 191, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSHri
1368 { 493, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSHW
1369 { 492, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSH
1370 { 491, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 268, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLCMPS
1371 { 490, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 265, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLCMPD
1372 { 489, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FITOS
1373 { 488, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 263, 0, 0, 0x0ULL }, // FITOQ
1374 { 487, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 261, 0, 0, 0x0ULL }, // FITOD
1375 { 486, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FHSUBS
1376 { 485, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FHSUBD
1377 { 484, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FHADDS
1378 { 483, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FHADDD
1379 { 482, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 261, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FEXPAND
1380 { 481, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FDTOX
1381 { 480, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 257, 0, 0, 0x0ULL }, // FDTOS
1382 { 479, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 259, 0, 0, 0x0ULL }, // FDTOQ
1383 { 478, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 257, 0, 0, 0x0ULL }, // FDTOI
1384 { 477, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 254, 0, 0, 0x0ULL }, // FDMULQ
1385 { 476, 3, 1, 4, 7, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FDIVS
1386 { 475, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FDIVQ
1387 { 474, 3, 1, 4, 6, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FDIVD
1388 { 473, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 243, 3, 0, 0x0ULL }, // FCMPS_V9
1389 { 472, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 243, 3, 0, 0x0ULL }, // FCMPS
1390 { 471, 2, 0, 4, 0, 0, 1, SparcOpInfoBase + 241, 3, 0, 0x0ULL }, // FCMPQ_V9
1391 { 470, 2, 0, 4, 0, 0, 1, SparcOpInfoBase + 241, 3, 0, 0x0ULL }, // FCMPQ
1392 { 469, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPNE32
1393 { 468, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPNE16
1394 { 467, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPLE32
1395 { 466, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPLE16
1396 { 465, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPGT32
1397 { 464, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPGT16
1398 { 463, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPEQ32
1399 { 462, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPEQ16
1400 { 461, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 236, 3, 0, 0x0ULL }, // FCMPD_V9
1401 { 460, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 236, 3, 0, 0x0ULL }, // FCMPD
1402 { 459, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCHKSM16
1403 { 458, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // FBCOND_V9
1404 { 457, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // FBCONDA_V9
1405 { 456, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FBCONDA
1406 { 455, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // FBCOND
1407 { 454, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDS
1408 { 453, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT2S
1409 { 452, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT2
1410 { 451, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT1S
1411 { 450, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT1
1412 { 449, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAND
1413 { 448, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FALIGNADATA
1414 { 447, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FADDS
1415 { 446, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FADDQ
1416 { 445, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FADDD
1417 { 444, 2, 1, 4, 4, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FABSS
1418 { 443, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 241, 0, 0, 0x0ULL }, // FABSQ
1419 { 442, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FABSD
1420 { 441, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8N
1421 { 440, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8LN
1422 { 439, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8L
1423 { 438, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8
1424 { 437, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32N
1425 { 436, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32LN
1426 { 435, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32L
1427 { 434, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32
1428 { 433, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16N
1429 { 432, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16LN
1430 { 431, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16L
1431 { 430, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16
1432 { 429, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DONE
1433 { 428, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_ROUND
1434 { 427, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 238, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_KEXPAND
1435 { 426, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_IP
1436 { 425, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_IIP
1437 { 424, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 232, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CXBCONDrr
1438 { 423, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 228, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CXBCONDri
1439 { 422, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 232, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CWBCONDrr
1440 { 421, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 228, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CWBCONDri
1441 { 420, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CRC32C
1442 { 419, 2, 0, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CPBCONDA
1443 { 418, 2, 0, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // CPBCOND
1444 { 417, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 227, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMASK8
1445 { 416, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 227, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMASK32
1446 { 415, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 227, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMASK16
1447 { 414, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 222, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // CASXArr
1448 { 413, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 218, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CASXAri
1449 { 412, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 213, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // CASArr
1450 { 411, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 209, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CASAri
1451 { 410, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CAMELLIA_FLI
1452 { 409, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CAMELLIA_FL
1453 { 408, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CAMELLIA_F
1454 { 407, 3, 0, 4, 1, 1, 1, SparcOpInfoBase + 206, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CALLrri
1455 { 406, 2, 0, 4, 3, 1, 1, SparcOpInfoBase + 193, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // CALLrr
1456 { 405, 3, 0, 4, 1, 1, 1, SparcOpInfoBase + 203, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CALLrii
1457 { 404, 2, 0, 4, 3, 1, 1, SparcOpInfoBase + 191, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // CALLri
1458 { 403, 2, 0, 4, 0, 1, 1, SparcOpInfoBase + 201, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CALLi
1459 { 402, 1, 0, 4, 3, 1, 1, SparcOpInfoBase + 188, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // CALL
1460 { 401, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BSHUFFLE
1461 { 400, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPXCCNT
1462 { 399, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPXCCANT
1463 { 398, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPXCCA
1464 { 397, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BPXCC
1465 { 396, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 198, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPRNT
1466 { 395, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 198, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPRANT
1467 { 394, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 198, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPRA
1468 { 393, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 198, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BPR
1469 { 392, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPICCNT
1470 { 391, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPICCANT
1471 { 390, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPICCA
1472 { 389, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BPICC
1473 { 388, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCCNT
1474 { 387, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCCANT
1475 { 386, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCCA
1476 { 385, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCC
1477 { 384, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BMASK
1478 { 383, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BINDrr
1479 { 382, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 191, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BINDri
1480 { 381, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BCONDA
1481 { 380, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BCOND
1482 { 379, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 188, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BA
1483 { 378, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ARRAY8
1484 { 377, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ARRAY32
1485 { 376, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ARRAY16
1486 { 375, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ANDrr
1487 { 374, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // ANDri
1488 { 373, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ANDNrr
1489 { 372, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDNri
1490 { 371, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDNCCrr
1491 { 370, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDNCCri
1492 { 369, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDCCrr
1493 { 368, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDCCri
1494 { 367, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALLCLEAN
1495 { 366, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALIGNADDRL
1496 { 365, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALIGNADDR
1497 { 364, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_KEXPAND2
1498 { 363, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 151, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_KEXPAND1
1499 { 362, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_KEXPAND0
1500 { 361, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND23_LAST
1501 { 360, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND23
1502 { 359, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND01_LAST
1503 { 358, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND01
1504 { 357, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND23_LAST
1505 { 356, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND23
1506 { 355, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND01_LAST
1507 { 354, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND01
1508 { 353, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ADDrr
1509 { 352, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // ADDri
1510 { 351, 3, 1, 4, 0, 1, 1, SparcOpInfoBase + 178, 5, 0, 0x0ULL }, // ADDXCCC
1511 { 350, 3, 1, 4, 0, 1, 0, SparcOpInfoBase + 178, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDXC
1512 { 349, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 175, 5, 0, 0x0ULL }, // ADDErr
1513 { 348, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 172, 5, 0, 0x0ULL }, // ADDEri
1514 { 347, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDCrr
1515 { 346, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDCri
1516 { 345, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0, 0x0ULL }, // ADDCCrr
1517 { 344, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0, 0x0ULL }, // ADDCCri
1518 { 343, 0, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V8BAR
1519 { 342, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 169, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SETX
1520 { 341, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 167, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SETSW
1521 { 340, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 167, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SET
1522 { 339, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 163, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_QFP_XCC
1523 { 338, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 163, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_QFP_ICC
1524 { 337, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 163, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_QFP_FCC
1525 { 336, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 159, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_Int_XCC
1526 { 335, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 159, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_Int_ICC
1527 { 334, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 159, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_Int_FCC
1528 { 333, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 155, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_FP_XCC
1529 { 332, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 155, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_FP_ICC
1530 { 331, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 155, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_FP_FCC
1531 { 330, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 151, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_DFP_XCC
1532 { 329, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 151, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_DFP_ICC
1533 { 328, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 151, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_DFP_FCC
1534 { 327, 1, 1, 4, 0, 0, 1, SparcOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // GETPCX
1535 { 326, 2, 0, 4, 0, 1, 1, SparcOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ADJCALLSTACKUP
1536 { 325, 2, 0, 4, 0, 1, 1, SparcOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ADJCALLSTACKDOWN
1537 { 324, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX
1538 { 323, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX
1539 { 322, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN
1540 { 321, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX
1541 { 320, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN
1542 { 319, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX
1543 { 318, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR
1544 { 317, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR
1545 { 316, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND
1546 { 315, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL
1547 { 314, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD
1548 { 313, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1549 { 312, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1550 { 311, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN
1551 { 310, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX
1552 { 309, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL
1553 { 308, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD
1554 { 307, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1555 { 306, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1556 { 305, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP
1557 { 304, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP
1558 { 303, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP
1559 { 302, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO
1560 { 301, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET
1561 { 300, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE
1562 { 299, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE
1563 { 298, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY
1564 { 297, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1565 { 296, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1566 { 295, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP
1567 { 294, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT
1568 { 293, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA
1569 { 292, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM
1570 { 291, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV
1571 { 290, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL
1572 { 289, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB
1573 { 288, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD
1574 { 287, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE
1575 { 286, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE
1576 { 285, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC
1577 { 284, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE
1578 { 283, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR
1579 { 282, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST
1580 { 281, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT
1581 { 280, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT
1582 { 279, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR
1583 { 278, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT
1584 { 277, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH
1585 { 276, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH
1586 { 275, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH
1587 { 274, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2
1588 { 273, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN
1589 { 272, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN
1590 { 271, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS
1591 { 270, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN
1592 { 269, 3, 2, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS
1593 { 268, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN
1594 { 267, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS
1595 { 266, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL
1596 { 265, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE
1597 { 264, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP
1598 { 263, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP
1599 { 262, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS
1600 { 261, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
1601 { 260, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ
1602 { 259, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
1603 { 258, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ
1604 { 257, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS
1605 { 256, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR
1606 { 255, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR
1607 { 254, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR
1608 { 253, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1609 { 252, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT
1610 { 251, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1611 { 250, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR
1612 { 249, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE
1613 { 248, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT
1614 { 247, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR
1615 { 246, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND
1616 { 245, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND
1617 { 244, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS
1618 { 243, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX
1619 { 242, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN
1620 { 241, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX
1621 { 240, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN
1622 { 239, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK
1623 { 238, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD
1624 { 237, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING
1625 { 236, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING
1626 { 235, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE
1627 { 234, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE
1628 { 233, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE
1629 { 232, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV
1630 { 231, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV
1631 { 230, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV
1632 { 229, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM
1633 { 228, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM
1634 { 227, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM
1635 { 226, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM
1636 { 225, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE
1637 { 224, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE
1638 { 223, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM
1639 { 222, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM
1640 { 221, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE
1641 { 220, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS
1642 { 219, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN
1643 { 218, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS
1644 { 217, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT
1645 { 216, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT
1646 { 215, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP
1647 { 214, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP
1648 { 213, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI
1649 { 212, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI
1650 { 211, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC
1651 { 210, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT
1652 { 209, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG
1653 { 208, 3, 2, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP
1654 { 207, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP
1655 { 206, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10
1656 { 205, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2
1657 { 204, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG
1658 { 203, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10
1659 { 202, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2
1660 { 201, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP
1661 { 200, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI
1662 { 199, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW
1663 { 198, 3, 2, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF
1664 { 197, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM
1665 { 196, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV
1666 { 195, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD
1667 { 194, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA
1668 { 193, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL
1669 { 192, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB
1670 { 191, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD
1671 { 190, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT
1672 { 189, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT
1673 { 188, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX
1674 { 187, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX
1675 { 186, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT
1676 { 185, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT
1677 { 184, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX
1678 { 183, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX
1679 { 182, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT
1680 { 181, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT
1681 { 180, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT
1682 { 179, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT
1683 { 178, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT
1684 { 177, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT
1685 { 176, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH
1686 { 175, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH
1687 { 174, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO
1688 { 173, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO
1689 { 172, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE
1690 { 171, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO
1691 { 170, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE
1692 { 169, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO
1693 { 168, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE
1694 { 167, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO
1695 { 166, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE
1696 { 165, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO
1697 { 164, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT
1698 { 163, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP
1699 { 162, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP
1700 { 161, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP
1701 { 160, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP
1702 { 159, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL
1703 { 158, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR
1704 { 157, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR
1705 { 156, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL
1706 { 155, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR
1707 { 154, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR
1708 { 153, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL
1709 { 152, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT
1710 { 151, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG
1711 { 150, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT
1712 { 149, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG
1713 { 148, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART
1714 { 147, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT
1715 { 146, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT
1716 { 145, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U
1717 { 144, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U
1718 { 143, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S
1719 { 142, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC
1720 { 141, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT
1721 { 140, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1722 { 139, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1723 { 138, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1724 { 137, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC
1725 { 136, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START
1726 { 135, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT
1727 { 134, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND
1728 { 133, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH
1729 { 132, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE
1730 { 131, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1731 { 130, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1732 { 129, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1733 { 128, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1734 { 127, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1735 { 126, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1736 { 125, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1737 { 124, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1738 { 123, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN
1739 { 122, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX
1740 { 121, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB
1741 { 120, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD
1742 { 119, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN
1743 { 118, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX
1744 { 117, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN
1745 { 116, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX
1746 { 115, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR
1747 { 114, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR
1748 { 113, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND
1749 { 112, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND
1750 { 111, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB
1751 { 110, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD
1752 { 109, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG
1753 { 108, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG
1754 { 107, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1755 { 106, 5, 1, 0, 0, 0, 0, SparcOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE
1756 { 105, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE
1757 { 104, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1758 { 103, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD
1759 { 102, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD
1760 { 101, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD
1761 { 100, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD
1762 { 99, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD
1763 { 98, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER
1764 { 97, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER
1765 { 96, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1766 { 95, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT
1767 { 94, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT
1768 { 93, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND
1769 { 92, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC
1770 { 91, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1771 { 90, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1772 { 89, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE
1773 { 88, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST
1774 { 87, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR
1775 { 86, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT
1776 { 85, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS
1777 { 84, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1778 { 83, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR
1779 { 82, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES
1780 { 81, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT
1781 { 80, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES
1782 { 79, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT
1783 { 78, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL
1784 { 77, 5, 1, 0, 0, 0, 0, SparcOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1785 { 76, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE
1786 { 75, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX
1787 { 74, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI
1788 { 73, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF
1789 { 72, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL
1790 { 71, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR
1791 { 70, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL
1792 { 69, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR
1793 { 68, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU
1794 { 67, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS
1795 { 66, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR
1796 { 65, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR
1797 { 64, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND
1798 { 63, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM
1799 { 62, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM
1800 { 61, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM
1801 { 60, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM
1802 { 59, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV
1803 { 58, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV
1804 { 57, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL
1805 { 56, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB
1806 { 55, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD
1807 { 54, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN
1808 { 53, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT
1809 { 52, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT
1810 { 51, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1811 { 50, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1812 { 49, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1813 { 48, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1814 { 47, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE
1815 { 46, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1816 { 45, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER
1817 { 44, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE
1818 { 43, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1819 { 42, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_16375
1820 { 41, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_16374
1821 { 40, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL
1822 { 39, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1823 { 38, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET
1824 { 37, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1825 { 36, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP
1826 { 35, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP
1827 { 34, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE
1828 { 33, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT
1829 { 32, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_16373
1830 { 31, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP
1831 { 30, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_13542
1832 { 29, 6, 1, 0, 0, 0, 0, SparcOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT
1833 { 28, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL
1834 { 27, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP
1835 { 26, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE
1836 { 25, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE
1837 { 24, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END
1838 { 23, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START
1839 { 22, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE
1840 { 21, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK
1841 { 20, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY
1842 { 19, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE
1843 { 18, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL
1844 { 17, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI
1845 { 16, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF
1846 { 15, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST
1847 { 14, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE
1848 { 13, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS
1849 { 12, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG
1850 { 11, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF
1851 { 10, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF
1852 { 9, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG
1853 { 8, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG
1854 { 7, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL
1855 { 6, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL
1856 { 5, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL
1857 { 4, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL
1858 { 3, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION
1859 { 2, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR
1860 { 1, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM
1861 { 0, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI
1862 }, {
1863 /* 0 */
1864 /* 0 */ SP::O6, SP::O6,
1865 /* 2 */ SP::O7,
1866 /* 3 */ SP::FCC0,
1867 /* 4 */ SP::ICC,
1868 /* 5 */ SP::ICC, SP::ICC,
1869 /* 7 */ SP::O6, SP::O7,
1870 /* 9 */ SP::ASR3,
1871 /* 10 */ SP::CPSR,
1872 /* 11 */ SP::FSR,
1873 /* 12 */ SP::D0, SP::D1, SP::D2, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7,
1874 /* 30 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5,
1875 /* 134 */ SP::Y, SP::ICC, SP::Y, SP::ICC,
1876 /* 138 */ SP::PSR,
1877 /* 139 */ SP::FQ,
1878 /* 140 */ SP::TBR,
1879 /* 141 */ SP::WIM,
1880 /* 142 */ SP::Y, SP::Y, SP::ICC,
1881 /* 145 */ SP::Y, SP::Y,
1882 /* 147 */ SP::D0, SP::D1, SP::D2, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D0, SP::D1, SP::D2,
1883 /* 161 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D0, SP::D1, SP::D2, SP::D3,
1884 /* 177 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7,
1885 /* 209 */ SP::Y, SP::ASR18, SP::Y, SP::ASR18,
1886 /* 213 */ SP::Y, SP::ICC,
1887 /* 215 */ SP::Y,
1888 /* 216 */ SP::CPQ,
1889 /* 217 */ SP::O6,
1890 }, {
1891 0
1892 }, {
1893 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1894 /* 1 */
1895 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1896 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1897 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1898 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1899 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1900 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1901 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1902 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1903 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1904 /* 28 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
1905 /* 29 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1906 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1907 /* 34 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1908 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1909 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1910 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1911 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1912 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1913 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1914 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1915 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1916 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1917 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1918 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1919 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1920 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1921 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1922 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1923 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1924 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1925 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1926 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1927 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1928 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1929 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1930 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1931 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1932 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1933 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1934 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1935 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1936 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1937 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1938 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1939 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1940 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1941 /* 151 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1942 /* 155 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1943 /* 159 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1944 /* 163 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1945 /* 167 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1946 /* 169 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1947 /* 172 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1948 /* 175 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1949 /* 178 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1950 /* 181 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1951 /* 185 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1952 /* 188 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },
1953 /* 189 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1954 /* 191 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1955 /* 193 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
1956 /* 195 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1957 /* 198 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1958 /* 201 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1959 /* 203 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1960 /* 206 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1961 /* 209 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1962 /* 213 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1963 /* 218 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1964 /* 222 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1965 /* 227 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1966 /* 228 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1967 /* 232 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1968 /* 236 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1969 /* 238 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1970 /* 241 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1971 /* 243 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1972 /* 245 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1973 /* 248 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1974 /* 251 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1975 /* 254 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1976 /* 257 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1977 /* 259 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1978 /* 261 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1979 /* 263 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1980 /* 265 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1981 /* 268 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1982 /* 271 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1983 /* 275 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1984 /* 279 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1985 /* 283 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1986 /* 288 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1987 /* 293 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1988 /* 298 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1989 /* 302 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1990 /* 305 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1991 /* 308 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1992 /* 309 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1993 /* 310 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1994 /* 312 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1995 /* 314 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1996 /* 318 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1997 /* 322 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1998 /* 325 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
1999 /* 328 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2000 /* 331 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2001 /* 334 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2002 /* 337 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2003 /* 341 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2004 /* 344 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2005 /* 347 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2006 /* 350 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2007 /* 354 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2008 /* 357 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2009 /* 360 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2010 /* 363 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2011 /* 367 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2012 /* 370 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2013 /* 373 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2014 /* 377 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2015 /* 380 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2016 /* 383 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2017 /* 386 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2018 /* 388 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2019 /* 390 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2020 /* 394 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2021 /* 398 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2022 /* 403 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2023 /* 408 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2024 /* 410 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2025 /* 412 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2026 /* 414 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
2027 /* 417 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2028 /* 419 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2029 /* 422 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2030 /* 426 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2031 /* 429 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2032 /* 431 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2033 /* 432 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2034 /* 434 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2035 /* 437 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2036 /* 440 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2037 /* 443 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2038 /* 446 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2039 /* 450 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2040 /* 453 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2041 /* 456 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2042 /* 459 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2043 /* 462 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2044 /* 466 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2045 /* 469 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2046 /* 472 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2047 /* 475 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2048 /* 479 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2049 /* 482 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2050 /* 485 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2051 /* 488 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2052 /* 492 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2053 /* 495 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2054 /* 498 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2055 /* 502 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2056 /* 505 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2057 /* 508 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2058 /* 512 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2059 /* 515 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
2060 /* 519 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
2061 /* 524 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
2062 /* 528 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2063 /* 531 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2064 /* 535 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2065 /* 538 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2066 /* 543 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2067 /* 548 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2068 /* 553 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2069 /* 558 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2070 /* 563 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
2071 /* 566 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2072 /* 569 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
2073 /* 572 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2074 }
2075};
2076
2077
2078#ifdef __GNUC__
2079#pragma GCC diagnostic push
2080#pragma GCC diagnostic ignored "-Woverlength-strings"
2081#endif
2082extern const char SparcInstrNameData[] = {
2083 /* 0 */ "G_FLOG10\000"
2084 /* 9 */ "G_FEXP10\000"
2085 /* 18 */ "AES_KEXPAND0\000"
2086 /* 31 */ "AES_DROUND01\000"
2087 /* 44 */ "AES_EROUND01\000"
2088 /* 57 */ "SHA1\000"
2089 /* 62 */ "TA1\000"
2090 /* 66 */ "FSRC1\000"
2091 /* 72 */ "AES_KEXPAND1\000"
2092 /* 85 */ "FANDNOT1\000"
2093 /* 94 */ "FNOT1\000"
2094 /* 100 */ "FORNOT1\000"
2095 /* 108 */ "SHA512\000"
2096 /* 115 */ "FSRA32\000"
2097 /* 122 */ "FPSUB32\000"
2098 /* 130 */ "FPADD32\000"
2099 /* 138 */ "EDGE32\000"
2100 /* 145 */ "FCMPLE32\000"
2101 /* 154 */ "FCMPNE32\000"
2102 /* 163 */ "FPACK32\000"
2103 /* 171 */ "CMASK32\000"
2104 /* 179 */ "FSLL32\000"
2105 /* 186 */ "FSRL32\000"
2106 /* 193 */ "FCMPEQ32\000"
2107 /* 202 */ "FSLAS32\000"
2108 /* 210 */ "FCMPGT32\000"
2109 /* 219 */ "ARRAY32\000"
2110 /* 227 */ "FSRC2\000"
2111 /* 233 */ "AES_KEXPAND2\000"
2112 /* 246 */ "G_FLOG2\000"
2113 /* 254 */ "G_FATAN2\000"
2114 /* 263 */ "G_FEXP2\000"
2115 /* 271 */ "FANDNOT2\000"
2116 /* 280 */ "FNOT2\000"
2117 /* 286 */ "FORNOT2\000"
2118 /* 294 */ "AES_DROUND23\000"
2119 /* 307 */ "AES_EROUND23\000"
2120 /* 320 */ "TA3\000"
2121 /* 324 */ "FPADD64\000"
2122 /* 332 */ "TA5\000"
2123 /* 336 */ "MD5\000"
2124 /* 340 */ "FSRA16\000"
2125 /* 347 */ "FPSUB16\000"
2126 /* 355 */ "FPADD16\000"
2127 /* 363 */ "EDGE16\000"
2128 /* 370 */ "FCMPLE16\000"
2129 /* 379 */ "FCMPNE16\000"
2130 /* 388 */ "FPACK16\000"
2131 /* 396 */ "CMASK16\000"
2132 /* 404 */ "FSLL16\000"
2133 /* 411 */ "FSRL16\000"
2134 /* 418 */ "FCHKSM16\000"
2135 /* 427 */ "FMEAN16\000"
2136 /* 435 */ "FCMPEQ16\000"
2137 /* 444 */ "FSLAS16\000"
2138 /* 452 */ "FCMPGT16\000"
2139 /* 461 */ "FMUL8X16\000"
2140 /* 470 */ "FMULD8ULX16\000"
2141 /* 482 */ "FMUL8ULX16\000"
2142 /* 493 */ "FMULD8SUX16\000"
2143 /* 505 */ "FMUL8SUX16\000"
2144 /* 516 */ "ARRAY16\000"
2145 /* 524 */ "SHA256\000"
2146 /* 531 */ "EDGE8\000"
2147 /* 537 */ "CMASK8\000"
2148 /* 544 */ "ARRAY8\000"
2149 /* 551 */ "FBCONDA_V9\000"
2150 /* 562 */ "FBCOND_V9\000"
2151 /* 572 */ "FCMPD_V9\000"
2152 /* 581 */ "FCMPQ_V9\000"
2153 /* 590 */ "FCMPS_V9\000"
2154 /* 599 */ "BA\000"
2155 /* 602 */ "BPFCCA\000"
2156 /* 609 */ "BPICCA\000"
2157 /* 616 */ "BPXCCA\000"
2158 /* 623 */ "FBCONDA\000"
2159 /* 631 */ "CPBCONDA\000"
2160 /* 640 */ "G_FMA\000"
2161 /* 646 */ "G_STRICT_FMA\000"
2162 /* 659 */ "BPRA\000"
2163 /* 664 */ "FALIGNADATA\000"
2164 /* 676 */ "G_FSUB\000"
2165 /* 683 */ "G_STRICT_FSUB\000"
2166 /* 697 */ "G_ATOMICRMW_FSUB\000"
2167 /* 714 */ "G_SUB\000"
2168 /* 720 */ "G_ATOMICRMW_SUB\000"
2169 /* 736 */ "CRC32C\000"
2170 /* 743 */ "ADDXCCC\000"
2171 /* 751 */ "BPFCC\000"
2172 /* 757 */ "V9FMOVD_FCC\000"
2173 /* 769 */ "SELECT_CC_DFP_FCC\000"
2174 /* 787 */ "SELECT_CC_QFP_FCC\000"
2175 /* 805 */ "SELECT_CC_FP_FCC\000"
2176 /* 822 */ "V9FMOVQ_FCC\000"
2177 /* 834 */ "V9FMOVS_FCC\000"
2178 /* 846 */ "SELECT_CC_Int_FCC\000"
2179 /* 864 */ "BPICC\000"
2180 /* 870 */ "FMOVD_ICC\000"
2181 /* 880 */ "SELECT_CC_DFP_ICC\000"
2182 /* 898 */ "SELECT_CC_QFP_ICC\000"
2183 /* 916 */ "SELECT_CC_FP_ICC\000"
2184 /* 933 */ "FMOVQ_ICC\000"
2185 /* 943 */ "FMOVS_ICC\000"
2186 /* 953 */ "SELECT_CC_Int_ICC\000"
2187 /* 971 */ "BPXCC\000"
2188 /* 977 */ "FMOVD_XCC\000"
2189 /* 987 */ "SELECT_CC_DFP_XCC\000"
2190 /* 1005 */ "SELECT_CC_QFP_XCC\000"
2191 /* 1023 */ "SELECT_CC_FP_XCC\000"
2192 /* 1040 */ "FMOVQ_XCC\000"
2193 /* 1050 */ "FMOVS_XCC\000"
2194 /* 1060 */ "SELECT_CC_Int_XCC\000"
2195 /* 1078 */ "G_INTRINSIC\000"
2196 /* 1090 */ "G_FPTRUNC\000"
2197 /* 1100 */ "G_INTRINSIC_TRUNC\000"
2198 /* 1118 */ "G_TRUNC\000"
2199 /* 1126 */ "G_BUILD_VECTOR_TRUNC\000"
2200 /* 1147 */ "G_DYN_STACKALLOC\000"
2201 /* 1164 */ "ADDXC\000"
2202 /* 1170 */ "G_FMAD\000"
2203 /* 1177 */ "G_INDEXED_SEXTLOAD\000"
2204 /* 1196 */ "G_SEXTLOAD\000"
2205 /* 1207 */ "G_INDEXED_ZEXTLOAD\000"
2206 /* 1226 */ "G_ZEXTLOAD\000"
2207 /* 1237 */ "G_INDEXED_LOAD\000"
2208 /* 1252 */ "G_LOAD\000"
2209 /* 1259 */ "FSUBD\000"
2210 /* 1265 */ "FHSUBD\000"
2211 /* 1272 */ "FMSUBD\000"
2212 /* 1279 */ "FNMSUBD\000"
2213 /* 1287 */ "G_VECREDUCE_FADD\000"
2214 /* 1304 */ "G_FADD\000"
2215 /* 1311 */ "G_VECREDUCE_SEQ_FADD\000"
2216 /* 1332 */ "G_STRICT_FADD\000"
2217 /* 1346 */ "G_ATOMICRMW_FADD\000"
2218 /* 1363 */ "G_VECREDUCE_ADD\000"
2219 /* 1379 */ "G_ADD\000"
2220 /* 1385 */ "G_PTR_ADD\000"
2221 /* 1395 */ "G_ATOMICRMW_ADD\000"
2222 /* 1411 */ "FADDD\000"
2223 /* 1417 */ "FHADDD\000"
2224 /* 1424 */ "FNHADDD\000"
2225 /* 1432 */ "FMADDD\000"
2226 /* 1439 */ "FNMADDD\000"
2227 /* 1447 */ "FNADDD\000"
2228 /* 1454 */ "V9FCMPED\000"
2229 /* 1463 */ "RESTORED\000"
2230 /* 1472 */ "SAVED\000"
2231 /* 1478 */ "FNEGD\000"
2232 /* 1484 */ "FMULD\000"
2233 /* 1490 */ "FNMULD\000"
2234 /* 1497 */ "FSMULD\000"
2235 /* 1504 */ "FNSMULD\000"
2236 /* 1512 */ "FAND\000"
2237 /* 1517 */ "FNAND\000"
2238 /* 1523 */ "G_ATOMICRMW_NAND\000"
2239 /* 1540 */ "FEXPAND\000"
2240 /* 1548 */ "DES_KEXPAND\000"
2241 /* 1560 */ "G_VECREDUCE_AND\000"
2242 /* 1576 */ "G_AND\000"
2243 /* 1582 */ "G_ATOMICRMW_AND\000"
2244 /* 1598 */ "LIFETIME_END\000"
2245 /* 1611 */ "FBCOND\000"
2246 /* 1618 */ "CPBCOND\000"
2247 /* 1626 */ "G_BRCOND\000"
2248 /* 1635 */ "G_ATOMICRMW_USUB_COND\000"
2249 /* 1657 */ "G_LLROUND\000"
2250 /* 1667 */ "G_LROUND\000"
2251 /* 1676 */ "G_INTRINSIC_ROUND\000"
2252 /* 1694 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
2253 /* 1720 */ "DES_ROUND\000"
2254 /* 1730 */ "FITOD\000"
2255 /* 1736 */ "FQTOD\000"
2256 /* 1742 */ "FSTOD\000"
2257 /* 1748 */ "FXTOD\000"
2258 /* 1754 */ "MOVXTOD\000"
2259 /* 1762 */ "V9FCMPD\000"
2260 /* 1770 */ "FLCMPD\000"
2261 /* 1777 */ "LOAD_STACK_GUARD\000"
2262 /* 1794 */ "FMOVRD\000"
2263 /* 1801 */ "FABSD\000"
2264 /* 1807 */ "FSQRTD\000"
2265 /* 1814 */ "FDIVD\000"
2266 /* 1820 */ "FMOVD\000"
2267 /* 1826 */ "PSEUDO_PROBE\000"
2268 /* 1839 */ "G_SSUBE\000"
2269 /* 1847 */ "G_USUBE\000"
2270 /* 1855 */ "G_FENCE\000"
2271 /* 1863 */ "ARITH_FENCE\000"
2272 /* 1875 */ "REG_SEQUENCE\000"
2273 /* 1888 */ "G_SADDE\000"
2274 /* 1896 */ "G_UADDE\000"
2275 /* 1904 */ "G_GET_FPMODE\000"
2276 /* 1917 */ "G_RESET_FPMODE\000"
2277 /* 1932 */ "G_SET_FPMODE\000"
2278 /* 1945 */ "G_FMINNUM_IEEE\000"
2279 /* 1960 */ "G_FMAXNUM_IEEE\000"
2280 /* 1975 */ "FPMERGE\000"
2281 /* 1983 */ "G_VSCALE\000"
2282 /* 1992 */ "G_JUMP_TABLE\000"
2283 /* 2005 */ "BUNDLE\000"
2284 /* 2012 */ "BSHUFFLE\000"
2285 /* 2021 */ "G_MEMCPY_INLINE\000"
2286 /* 2037 */ "DONE\000"
2287 /* 2042 */ "FONE\000"
2288 /* 2047 */ "RELOC_NONE\000"
2289 /* 2058 */ "LOCAL_ESCAPE\000"
2290 /* 2071 */ "G_STACKRESTORE\000"
2291 /* 2086 */ "G_INDEXED_STORE\000"
2292 /* 2102 */ "G_STORE\000"
2293 /* 2110 */ "G_BITREVERSE\000"
2294 /* 2123 */ "FAKE_USE\000"
2295 /* 2132 */ "DBG_VALUE\000"
2296 /* 2142 */ "G_GLOBAL_VALUE\000"
2297 /* 2157 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2298 /* 2180 */ "CONVERGENCECTRL_GLUE\000"
2299 /* 2201 */ "G_STACKSAVE\000"
2300 /* 2213 */ "G_MEMMOVE\000"
2301 /* 2223 */ "G_FREEZE\000"
2302 /* 2232 */ "G_FCANONICALIZE\000"
2303 /* 2248 */ "G_FMODF\000"
2304 /* 2256 */ "G_CTLZ_ZERO_UNDEF\000"
2305 /* 2274 */ "G_CTTZ_ZERO_UNDEF\000"
2306 /* 2292 */ "INIT_UNDEF\000"
2307 /* 2303 */ "G_IMPLICIT_DEF\000"
2308 /* 2318 */ "DBG_INSTR_REF\000"
2309 /* 2332 */ "CAMELLIA_F\000"
2310 /* 2343 */ "G_FNEG\000"
2311 /* 2350 */ "EXTRACT_SUBREG\000"
2312 /* 2365 */ "INSERT_SUBREG\000"
2313 /* 2379 */ "G_SEXT_INREG\000"
2314 /* 2392 */ "SUBREG_TO_REG\000"
2315 /* 2406 */ "G_ATOMIC_CMPXCHG\000"
2316 /* 2423 */ "G_ATOMICRMW_XCHG\000"
2317 /* 2440 */ "G_GET_ROUNDING\000"
2318 /* 2455 */ "G_SET_ROUNDING\000"
2319 /* 2470 */ "G_FLOG\000"
2320 /* 2477 */ "G_VAARG\000"
2321 /* 2485 */ "PREALLOCATED_ARG\000"
2322 /* 2502 */ "G_PREFETCH\000"
2323 /* 2513 */ "G_SMULH\000"
2324 /* 2521 */ "G_UMULH\000"
2325 /* 2529 */ "G_FTANH\000"
2326 /* 2537 */ "G_FSINH\000"
2327 /* 2545 */ "G_FCOSH\000"
2328 /* 2553 */ "FLUSH\000"
2329 /* 2559 */ "DBG_PHI\000"
2330 /* 2567 */ "FPMADDXHI\000"
2331 /* 2577 */ "UMULXHI\000"
2332 /* 2585 */ "XMULXHI\000"
2333 /* 2593 */ "CAMELLIA_FLI\000"
2334 /* 2606 */ "FDTOI\000"
2335 /* 2612 */ "FQTOI\000"
2336 /* 2618 */ "FSTOI\000"
2337 /* 2624 */ "G_FPTOSI\000"
2338 /* 2633 */ "G_FPTOUI\000"
2339 /* 2642 */ "G_FPOWI\000"
2340 /* 2650 */ "BMASK\000"
2341 /* 2656 */ "COPY_LANEMASK\000"
2342 /* 2670 */ "G_PTRMASK\000"
2343 /* 2680 */ "EDGE32L\000"
2344 /* 2688 */ "EDGE16L\000"
2345 /* 2696 */ "EDGE8L\000"
2346 /* 2703 */ "FMUL8X16AL\000"
2347 /* 2714 */ "GC_LABEL\000"
2348 /* 2723 */ "DBG_LABEL\000"
2349 /* 2733 */ "EH_LABEL\000"
2350 /* 2742 */ "ANNOTATION_LABEL\000"
2351 /* 2759 */ "ICALL_BRANCH_FUNNEL\000"
2352 /* 2779 */ "CAMELLIA_FL\000"
2353 /* 2791 */ "G_FSHL\000"
2354 /* 2798 */ "G_SHL\000"
2355 /* 2804 */ "G_FCEIL\000"
2356 /* 2812 */ "G_SAVGCEIL\000"
2357 /* 2823 */ "G_UAVGCEIL\000"
2358 /* 2834 */ "PATCHABLE_TAIL_CALL\000"
2359 /* 2854 */ "TLS_CALL\000"
2360 /* 2863 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2361 /* 2890 */ "PATCHABLE_EVENT_CALL\000"
2362 /* 2911 */ "FENTRY_CALL\000"
2363 /* 2923 */ "KILL\000"
2364 /* 2928 */ "G_CONSTANT_POOL\000"
2365 /* 2944 */ "ALIGNADDRL\000"
2366 /* 2955 */ "RETL\000"
2367 /* 2960 */ "G_ROTL\000"
2368 /* 2967 */ "G_VECREDUCE_FMUL\000"
2369 /* 2984 */ "G_FMUL\000"
2370 /* 2991 */ "G_VECREDUCE_SEQ_FMUL\000"
2371 /* 3012 */ "G_STRICT_FMUL\000"
2372 /* 3026 */ "MPMUL\000"
2373 /* 3032 */ "MONTMUL\000"
2374 /* 3040 */ "G_VECREDUCE_MUL\000"
2375 /* 3056 */ "G_MUL\000"
2376 /* 3062 */ "SIAM\000"
2377 /* 3067 */ "G_FREM\000"
2378 /* 3074 */ "G_STRICT_FREM\000"
2379 /* 3088 */ "G_SREM\000"
2380 /* 3095 */ "G_UREM\000"
2381 /* 3102 */ "G_SDIVREM\000"
2382 /* 3112 */ "G_UDIVREM\000"
2383 /* 3122 */ "RDWIM\000"
2384 /* 3128 */ "INLINEASM\000"
2385 /* 3138 */ "G_VECREDUCE_FMINIMUM\000"
2386 /* 3159 */ "G_FMINIMUM\000"
2387 /* 3170 */ "G_ATOMICRMW_FMINIMUM\000"
2388 /* 3191 */ "G_VECREDUCE_FMAXIMUM\000"
2389 /* 3212 */ "G_FMAXIMUM\000"
2390 /* 3223 */ "G_ATOMICRMW_FMAXIMUM\000"
2391 /* 3244 */ "G_FMINIMUMNUM\000"
2392 /* 3258 */ "G_ATOMICRMW_FMINIMUMNUM\000"
2393 /* 3282 */ "G_FMAXIMUMNUM\000"
2394 /* 3296 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
2395 /* 3320 */ "G_FMINNUM\000"
2396 /* 3330 */ "G_FMAXNUM\000"
2397 /* 3340 */ "EDGE32N\000"
2398 /* 3348 */ "EDGE16N\000"
2399 /* 3356 */ "EDGE8N\000"
2400 /* 3363 */ "ALLCLEAN\000"
2401 /* 3372 */ "G_FATAN\000"
2402 /* 3380 */ "G_FTAN\000"
2403 /* 3387 */ "G_INTRINSIC_ROUNDEVEN\000"
2404 /* 3409 */ "G_ASSERT_ALIGN\000"
2405 /* 3424 */ "G_FCOPYSIGN\000"
2406 /* 3436 */ "G_VECREDUCE_FMIN\000"
2407 /* 3453 */ "G_ATOMICRMW_FMIN\000"
2408 /* 3470 */ "G_VECREDUCE_SMIN\000"
2409 /* 3487 */ "G_SMIN\000"
2410 /* 3494 */ "G_VECREDUCE_UMIN\000"
2411 /* 3511 */ "G_UMIN\000"
2412 /* 3518 */ "G_ATOMICRMW_UMIN\000"
2413 /* 3535 */ "G_ATOMICRMW_MIN\000"
2414 /* 3551 */ "G_FASIN\000"
2415 /* 3559 */ "G_FSIN\000"
2416 /* 3566 */ "EDGE32LN\000"
2417 /* 3575 */ "EDGE16LN\000"
2418 /* 3584 */ "EDGE8LN\000"
2419 /* 3592 */ "CFI_INSTRUCTION\000"
2420 /* 3608 */ "PDISTN\000"
2421 /* 3615 */ "ADJCALLSTACKDOWN\000"
2422 /* 3632 */ "SHUTDOWN\000"
2423 /* 3641 */ "G_SSUBO\000"
2424 /* 3649 */ "G_USUBO\000"
2425 /* 3657 */ "G_SADDO\000"
2426 /* 3665 */ "G_UADDO\000"
2427 /* 3673 */ "JUMP_TABLE_DEBUG_INFO\000"
2428 /* 3695 */ "G_SMULO\000"
2429 /* 3703 */ "G_UMULO\000"
2430 /* 3711 */ "G_BZERO\000"
2431 /* 3719 */ "FZERO\000"
2432 /* 3725 */ "STACKMAP\000"
2433 /* 3734 */ "G_DEBUGTRAP\000"
2434 /* 3746 */ "G_UBSANTRAP\000"
2435 /* 3758 */ "G_TRAP\000"
2436 /* 3765 */ "G_ATOMICRMW_UDEC_WRAP\000"
2437 /* 3787 */ "G_ATOMICRMW_UINC_WRAP\000"
2438 /* 3809 */ "G_BSWAP\000"
2439 /* 3817 */ "G_SITOFP\000"
2440 /* 3826 */ "G_UITOFP\000"
2441 /* 3835 */ "DES_IIP\000"
2442 /* 3843 */ "DES_IP\000"
2443 /* 3850 */ "G_FCMP\000"
2444 /* 3857 */ "G_ICMP\000"
2445 /* 3864 */ "G_SCMP\000"
2446 /* 3871 */ "G_UCMP\000"
2447 /* 3878 */ "UNIMP\000"
2448 /* 3884 */ "NOP\000"
2449 /* 3888 */ "CONVERGENCECTRL_LOOP\000"
2450 /* 3909 */ "G_CTPOP\000"
2451 /* 3917 */ "PATCHABLE_OP\000"
2452 /* 3930 */ "FAULTING_OP\000"
2453 /* 3942 */ "ADJCALLSTACKUP\000"
2454 /* 3957 */ "PREALLOCATED_SETUP\000"
2455 /* 3976 */ "G_FLDEXP\000"
2456 /* 3985 */ "G_STRICT_FLDEXP\000"
2457 /* 4001 */ "G_FEXP\000"
2458 /* 4008 */ "G_FFREXP\000"
2459 /* 4017 */ "FSUBQ\000"
2460 /* 4023 */ "FADDQ\000"
2461 /* 4029 */ "V9FCMPEQ\000"
2462 /* 4038 */ "RDFQ\000"
2463 /* 4043 */ "FNEGQ\000"
2464 /* 4049 */ "FDMULQ\000"
2465 /* 4056 */ "FMULQ\000"
2466 /* 4062 */ "FDTOQ\000"
2467 /* 4068 */ "FITOQ\000"
2468 /* 4074 */ "FSTOQ\000"
2469 /* 4080 */ "FXTOQ\000"
2470 /* 4086 */ "V9FCMPQ\000"
2471 /* 4094 */ "FMOVRQ\000"
2472 /* 4101 */ "FABSQ\000"
2473 /* 4107 */ "FSQRTQ\000"
2474 /* 4114 */ "FDIVQ\000"
2475 /* 4120 */ "FMOVQ\000"
2476 /* 4126 */ "V8BAR\000"
2477 /* 4132 */ "STBAR\000"
2478 /* 4138 */ "RDTBR\000"
2479 /* 4144 */ "G_BR\000"
2480 /* 4149 */ "INLINEASM_BR\000"
2481 /* 4162 */ "ALIGNADDR\000"
2482 /* 4172 */ "G_BLOCK_ADDR\000"
2483 /* 4185 */ "MEMBARRIER\000"
2484 /* 4196 */ "G_CONSTANT_FOLD_BARRIER\000"
2485 /* 4220 */ "PATCHABLE_FUNCTION_ENTER\000"
2486 /* 4245 */ "G_READCYCLECOUNTER\000"
2487 /* 4264 */ "G_READSTEADYCOUNTER\000"
2488 /* 4284 */ "G_READ_REGISTER\000"
2489 /* 4300 */ "G_WRITE_REGISTER\000"
2490 /* 4317 */ "G_ASHR\000"
2491 /* 4324 */ "G_FSHR\000"
2492 /* 4331 */ "G_LSHR\000"
2493 /* 4338 */ "SIR\000"
2494 /* 4342 */ "FOR\000"
2495 /* 4346 */ "CONVERGENCECTRL_ANCHOR\000"
2496 /* 4369 */ "FNOR\000"
2497 /* 4374 */ "FXNOR\000"
2498 /* 4380 */ "G_FFLOOR\000"
2499 /* 4389 */ "G_SAVGFLOOR\000"
2500 /* 4401 */ "G_UAVGFLOOR\000"
2501 /* 4413 */ "G_EXTRACT_SUBVECTOR\000"
2502 /* 4433 */ "G_INSERT_SUBVECTOR\000"
2503 /* 4452 */ "G_BUILD_VECTOR\000"
2504 /* 4467 */ "G_SHUFFLE_VECTOR\000"
2505 /* 4484 */ "G_STEP_VECTOR\000"
2506 /* 4498 */ "G_SPLAT_VECTOR\000"
2507 /* 4513 */ "FXOR\000"
2508 /* 4518 */ "G_VECREDUCE_XOR\000"
2509 /* 4534 */ "G_XOR\000"
2510 /* 4540 */ "G_ATOMICRMW_XOR\000"
2511 /* 4556 */ "G_VECREDUCE_OR\000"
2512 /* 4571 */ "G_OR\000"
2513 /* 4576 */ "G_ATOMICRMW_OR\000"
2514 /* 4591 */ "BPR\000"
2515 /* 4595 */ "RDPR\000"
2516 /* 4600 */ "MONTSQR\000"
2517 /* 4608 */ "RDASR\000"
2518 /* 4614 */ "RDPSR\000"
2519 /* 4620 */ "G_ROTR\000"
2520 /* 4627 */ "G_INTTOPTR\000"
2521 /* 4638 */ "FSRC1S\000"
2522 /* 4645 */ "FANDNOT1S\000"
2523 /* 4655 */ "FNOT1S\000"
2524 /* 4662 */ "FORNOT1S\000"
2525 /* 4671 */ "FPSUB32S\000"
2526 /* 4680 */ "FPADD32S\000"
2527 /* 4689 */ "FSRC2S\000"
2528 /* 4696 */ "FANDNOT2S\000"
2529 /* 4706 */ "FNOT2S\000"
2530 /* 4713 */ "FORNOT2S\000"
2531 /* 4722 */ "FPSUB16S\000"
2532 /* 4731 */ "FPADD16S\000"
2533 /* 4740 */ "G_FABS\000"
2534 /* 4747 */ "G_ABS\000"
2535 /* 4753 */ "FSUBS\000"
2536 /* 4759 */ "FHSUBS\000"
2537 /* 4766 */ "FMSUBS\000"
2538 /* 4773 */ "FNMSUBS\000"
2539 /* 4781 */ "G_ABDS\000"
2540 /* 4788 */ "FADDS\000"
2541 /* 4794 */ "FHADDS\000"
2542 /* 4801 */ "FNHADDS\000"
2543 /* 4809 */ "FMADDS\000"
2544 /* 4816 */ "FNMADDS\000"
2545 /* 4824 */ "FNADDS\000"
2546 /* 4831 */ "FANDS\000"
2547 /* 4837 */ "FNANDS\000"
2548 /* 4844 */ "FONES\000"
2549 /* 4850 */ "V9FCMPES\000"
2550 /* 4859 */ "G_UNMERGE_VALUES\000"
2551 /* 4876 */ "G_MERGE_VALUES\000"
2552 /* 4891 */ "FNEGS\000"
2553 /* 4897 */ "G_CTLS\000"
2554 /* 4904 */ "FMULS\000"
2555 /* 4910 */ "FNMULS\000"
2556 /* 4917 */ "G_FACOS\000"
2557 /* 4925 */ "G_FCOS\000"
2558 /* 4932 */ "G_FSINCOS\000"
2559 /* 4942 */ "FZEROS\000"
2560 /* 4949 */ "FDTOS\000"
2561 /* 4955 */ "FITOS\000"
2562 /* 4961 */ "FQTOS\000"
2563 /* 4967 */ "MOVWTOS\000"
2564 /* 4975 */ "FXTOS\000"
2565 /* 4981 */ "V9FCMPS\000"
2566 /* 4989 */ "FLCMPS\000"
2567 /* 4996 */ "FORS\000"
2568 /* 5001 */ "FNORS\000"
2569 /* 5007 */ "FXNORS\000"
2570 /* 5014 */ "G_CONCAT_VECTORS\000"
2571 /* 5031 */ "FXORS\000"
2572 /* 5037 */ "FMOVRS\000"
2573 /* 5044 */ "COPY_TO_REGCLASS\000"
2574 /* 5061 */ "G_IS_FPCLASS\000"
2575 /* 5074 */ "FABSS\000"
2576 /* 5080 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2577 /* 5110 */ "G_VECTOR_COMPRESS\000"
2578 /* 5128 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2579 /* 5155 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2580 /* 5193 */ "FSQRTS\000"
2581 /* 5200 */ "FDIVS\000"
2582 /* 5206 */ "FMOVS\000"
2583 /* 5212 */ "G_TRUNC_SSAT_S\000"
2584 /* 5227 */ "G_SSUBSAT\000"
2585 /* 5237 */ "G_USUBSAT\000"
2586 /* 5247 */ "G_SADDSAT\000"
2587 /* 5257 */ "G_UADDSAT\000"
2588 /* 5267 */ "G_SSHLSAT\000"
2589 /* 5277 */ "G_USHLSAT\000"
2590 /* 5287 */ "G_SMULFIXSAT\000"
2591 /* 5300 */ "G_UMULFIXSAT\000"
2592 /* 5313 */ "G_SDIVFIXSAT\000"
2593 /* 5326 */ "G_UDIVFIXSAT\000"
2594 /* 5339 */ "G_ATOMICRMW_USUB_SAT\000"
2595 /* 5360 */ "G_FPTOSI_SAT\000"
2596 /* 5373 */ "G_FPTOUI_SAT\000"
2597 /* 5386 */ "G_EXTRACT\000"
2598 /* 5396 */ "G_SELECT\000"
2599 /* 5405 */ "G_BRINDIRECT\000"
2600 /* 5418 */ "PATCHABLE_RET\000"
2601 /* 5432 */ "G_MEMSET\000"
2602 /* 5441 */ "PATCHABLE_FUNCTION_EXIT\000"
2603 /* 5465 */ "G_BRJT\000"
2604 /* 5472 */ "G_EXTRACT_VECTOR_ELT\000"
2605 /* 5493 */ "G_INSERT_VECTOR_ELT\000"
2606 /* 5513 */ "BPFCCANT\000"
2607 /* 5522 */ "BPICCANT\000"
2608 /* 5531 */ "BPXCCANT\000"
2609 /* 5540 */ "BPRANT\000"
2610 /* 5547 */ "G_FCONSTANT\000"
2611 /* 5559 */ "G_CONSTANT\000"
2612 /* 5570 */ "BPFCCNT\000"
2613 /* 5578 */ "BPICCNT\000"
2614 /* 5586 */ "BPXCCNT\000"
2615 /* 5594 */ "LZCNT\000"
2616 /* 5600 */ "G_INTRINSIC_CONVERGENT\000"
2617 /* 5623 */ "STATEPOINT\000"
2618 /* 5634 */ "PATCHPOINT\000"
2619 /* 5645 */ "G_PTRTOINT\000"
2620 /* 5656 */ "G_FRINT\000"
2621 /* 5664 */ "G_INTRINSIC_LLRINT\000"
2622 /* 5683 */ "G_INTRINSIC_LRINT\000"
2623 /* 5701 */ "G_FNEARBYINT\000"
2624 /* 5714 */ "BPRNT\000"
2625 /* 5720 */ "G_VASTART\000"
2626 /* 5730 */ "LIFETIME_START\000"
2627 /* 5745 */ "G_INVOKE_REGION_START\000"
2628 /* 5767 */ "G_INSERT\000"
2629 /* 5776 */ "G_FSQRT\000"
2630 /* 5784 */ "G_STRICT_FSQRT\000"
2631 /* 5799 */ "G_BITCAST\000"
2632 /* 5809 */ "G_ADDRSPACE_CAST\000"
2633 /* 5826 */ "AES_DROUND01_LAST\000"
2634 /* 5844 */ "AES_EROUND01_LAST\000"
2635 /* 5862 */ "AES_DROUND23_LAST\000"
2636 /* 5880 */ "AES_EROUND23_LAST\000"
2637 /* 5898 */ "PDIST\000"
2638 /* 5904 */ "DBG_VALUE_LIST\000"
2639 /* 5919 */ "G_FPEXT\000"
2640 /* 5927 */ "G_SEXT\000"
2641 /* 5934 */ "G_ASSERT_SEXT\000"
2642 /* 5948 */ "G_ANYEXT\000"
2643 /* 5957 */ "G_ZEXT\000"
2644 /* 5964 */ "G_ASSERT_ZEXT\000"
2645 /* 5978 */ "FMUL8X16AU\000"
2646 /* 5989 */ "G_ABDU\000"
2647 /* 5996 */ "G_TRUNC_SSAT_U\000"
2648 /* 6011 */ "G_TRUNC_USAT_U\000"
2649 /* 6026 */ "G_FDIV\000"
2650 /* 6033 */ "G_STRICT_FDIV\000"
2651 /* 6047 */ "G_SDIV\000"
2652 /* 6054 */ "G_UDIV\000"
2653 /* 6061 */ "G_GET_FPENV\000"
2654 /* 6073 */ "G_RESET_FPENV\000"
2655 /* 6087 */ "G_SET_FPENV\000"
2656 /* 6099 */ "FLUSHW\000"
2657 /* 6106 */ "NORMALW\000"
2658 /* 6114 */ "INVALW\000"
2659 /* 6121 */ "G_FPOW\000"
2660 /* 6128 */ "OTHERW\000"
2661 /* 6135 */ "MOVSTOSW\000"
2662 /* 6144 */ "SETSW\000"
2663 /* 6150 */ "MOVSTOUW\000"
2664 /* 6159 */ "G_VECREDUCE_FMAX\000"
2665 /* 6176 */ "G_ATOMICRMW_FMAX\000"
2666 /* 6193 */ "G_VECREDUCE_SMAX\000"
2667 /* 6210 */ "G_SMAX\000"
2668 /* 6217 */ "G_VECREDUCE_UMAX\000"
2669 /* 6234 */ "G_UMAX\000"
2670 /* 6241 */ "G_ATOMICRMW_UMAX\000"
2671 /* 6258 */ "G_ATOMICRMW_MAX\000"
2672 /* 6274 */ "GETPCX\000"
2673 /* 6281 */ "FPMADDX\000"
2674 /* 6289 */ "G_FRAME_INDEX\000"
2675 /* 6303 */ "G_SBFX\000"
2676 /* 6310 */ "G_UBFX\000"
2677 /* 6317 */ "FPACKFIX\000"
2678 /* 6326 */ "G_SMULFIX\000"
2679 /* 6336 */ "G_UMULFIX\000"
2680 /* 6346 */ "G_SDIVFIX\000"
2681 /* 6356 */ "G_UDIVFIX\000"
2682 /* 6366 */ "XMULX\000"
2683 /* 6372 */ "FDTOX\000"
2684 /* 6378 */ "MOVDTOX\000"
2685 /* 6386 */ "FQTOX\000"
2686 /* 6392 */ "FSTOX\000"
2687 /* 6398 */ "SETX\000"
2688 /* 6403 */ "G_MEMCPY\000"
2689 /* 6412 */ "COPY\000"
2690 /* 6417 */ "RETRY\000"
2691 /* 6423 */ "CONVERGENCECTRL_ENTRY\000"
2692 /* 6445 */ "G_CTLZ\000"
2693 /* 6452 */ "G_CTTZ\000"
2694 /* 6459 */ "PREFETCHAi\000"
2695 /* 6470 */ "PREFETCHi\000"
2696 /* 6480 */ "SETHIi\000"
2697 /* 6487 */ "CALLi\000"
2698 /* 6493 */ "MEMBARi\000"
2699 /* 6501 */ "CALLrii\000"
2700 /* 6509 */ "LDSBAri\000"
2701 /* 6517 */ "STBAri\000"
2702 /* 6524 */ "LDUBAri\000"
2703 /* 6532 */ "LDSTUBAri\000"
2704 /* 6542 */ "LDDAri\000"
2705 /* 6549 */ "LDAri\000"
2706 /* 6555 */ "STDAri\000"
2707 /* 6562 */ "LDDFAri\000"
2708 /* 6570 */ "LDFAri\000"
2709 /* 6577 */ "STDFAri\000"
2710 /* 6585 */ "LDQFAri\000"
2711 /* 6593 */ "STQFAri\000"
2712 /* 6601 */ "STFAri\000"
2713 /* 6608 */ "LDSHAri\000"
2714 /* 6616 */ "STHAri\000"
2715 /* 6623 */ "LDUHAri\000"
2716 /* 6631 */ "SWAPAri\000"
2717 /* 6639 */ "SRAri\000"
2718 /* 6645 */ "CASAri\000"
2719 /* 6652 */ "STAri\000"
2720 /* 6658 */ "LDSWAri\000"
2721 /* 6666 */ "LDXAri\000"
2722 /* 6673 */ "CASXAri\000"
2723 /* 6681 */ "STXAri\000"
2724 /* 6688 */ "LDSBri\000"
2725 /* 6695 */ "STBri\000"
2726 /* 6701 */ "LDUBri\000"
2727 /* 6708 */ "SUBri\000"
2728 /* 6714 */ "LDSTUBri\000"
2729 /* 6723 */ "SMACri\000"
2730 /* 6730 */ "UMACri\000"
2731 /* 6737 */ "SUBCri\000"
2732 /* 6744 */ "TSUBCCri\000"
2733 /* 6753 */ "TADDCCri\000"
2734 /* 6762 */ "ANDCCri\000"
2735 /* 6770 */ "V9MOVFCCri\000"
2736 /* 6781 */ "TICCri\000"
2737 /* 6788 */ "MOVICCri\000"
2738 /* 6797 */ "SMULCCri\000"
2739 /* 6806 */ "UMULCCri\000"
2740 /* 6815 */ "ANDNCCri\000"
2741 /* 6824 */ "ORNCCri\000"
2742 /* 6832 */ "XNORCCri\000"
2743 /* 6841 */ "XORCCri\000"
2744 /* 6849 */ "MULSCCri\000"
2745 /* 6858 */ "SDIVCCri\000"
2746 /* 6867 */ "UDIVCCri\000"
2747 /* 6876 */ "TXCCri\000"
2748 /* 6883 */ "MOVXCCri\000"
2749 /* 6892 */ "ADDCri\000"
2750 /* 6899 */ "LDDCri\000"
2751 /* 6906 */ "LDCri\000"
2752 /* 6912 */ "STDCri\000"
2753 /* 6919 */ "STCri\000"
2754 /* 6925 */ "ADDri\000"
2755 /* 6931 */ "LDDri\000"
2756 /* 6937 */ "LDri\000"
2757 /* 6942 */ "ANDri\000"
2758 /* 6948 */ "BINDri\000"
2759 /* 6955 */ "CWBCONDri\000"
2760 /* 6965 */ "CXBCONDri\000"
2761 /* 6975 */ "STDri\000"
2762 /* 6981 */ "SUBEri\000"
2763 /* 6988 */ "ADDEri\000"
2764 /* 6995 */ "RESTOREri\000"
2765 /* 7005 */ "SAVEri\000"
2766 /* 7012 */ "LDDFri\000"
2767 /* 7019 */ "LDFri\000"
2768 /* 7025 */ "STDFri\000"
2769 /* 7032 */ "LDQFri\000"
2770 /* 7039 */ "STQFri\000"
2771 /* 7046 */ "STFri\000"
2772 /* 7052 */ "LDSHri\000"
2773 /* 7059 */ "FLUSHri\000"
2774 /* 7067 */ "STHri\000"
2775 /* 7073 */ "LDUHri\000"
2776 /* 7080 */ "TAIL_CALLri\000"
2777 /* 7092 */ "SLLri\000"
2778 /* 7098 */ "JMPLri\000"
2779 /* 7105 */ "SRLri\000"
2780 /* 7111 */ "SMULri\000"
2781 /* 7118 */ "UMULri\000"
2782 /* 7125 */ "WRWIMri\000"
2783 /* 7133 */ "ANDNri\000"
2784 /* 7140 */ "ORNri\000"
2785 /* 7146 */ "TRAPri\000"
2786 /* 7153 */ "SWAPri\000"
2787 /* 7160 */ "STDCQri\000"
2788 /* 7168 */ "STDFQri\000"
2789 /* 7176 */ "WRTBRri\000"
2790 /* 7184 */ "XNORri\000"
2791 /* 7191 */ "XORri\000"
2792 /* 7197 */ "WRPRri\000"
2793 /* 7204 */ "WRASRri\000"
2794 /* 7212 */ "LDCSRri\000"
2795 /* 7220 */ "STCSRri\000"
2796 /* 7228 */ "LDFSRri\000"
2797 /* 7236 */ "STFSRri\000"
2798 /* 7244 */ "LDXFSRri\000"
2799 /* 7253 */ "STXFSRri\000"
2800 /* 7262 */ "PWRPSRri\000"
2801 /* 7271 */ "MOVRri\000"
2802 /* 7278 */ "STri\000"
2803 /* 7283 */ "RETTri\000"
2804 /* 7290 */ "SDIVri\000"
2805 /* 7297 */ "UDIVri\000"
2806 /* 7304 */ "TSUBCCTVri\000"
2807 /* 7315 */ "TADDCCTVri\000"
2808 /* 7326 */ "LDSWri\000"
2809 /* 7333 */ "SRAXri\000"
2810 /* 7340 */ "LDXri\000"
2811 /* 7346 */ "SLLXri\000"
2812 /* 7353 */ "SRLXri\000"
2813 /* 7360 */ "MULXri\000"
2814 /* 7367 */ "STXri\000"
2815 /* 7373 */ "SDIVXri\000"
2816 /* 7381 */ "UDIVXri\000"
2817 /* 7389 */ "CALLrri\000"
2818 /* 7397 */ "PREFETCHAr\000"
2819 /* 7408 */ "PREFETCHr\000"
2820 /* 7418 */ "LDSBArr\000"
2821 /* 7426 */ "STBArr\000"
2822 /* 7433 */ "LDUBArr\000"
2823 /* 7441 */ "LDSTUBArr\000"
2824 /* 7451 */ "LDDArr\000"
2825 /* 7458 */ "LDArr\000"
2826 /* 7464 */ "STDArr\000"
2827 /* 7471 */ "LDDFArr\000"
2828 /* 7479 */ "LDFArr\000"
2829 /* 7486 */ "STDFArr\000"
2830 /* 7494 */ "LDQFArr\000"
2831 /* 7502 */ "STQFArr\000"
2832 /* 7510 */ "STFArr\000"
2833 /* 7517 */ "LDSHArr\000"
2834 /* 7525 */ "STHArr\000"
2835 /* 7532 */ "LDUHArr\000"
2836 /* 7540 */ "SWAPArr\000"
2837 /* 7548 */ "SRArr\000"
2838 /* 7554 */ "CASArr\000"
2839 /* 7561 */ "STArr\000"
2840 /* 7567 */ "LDSWArr\000"
2841 /* 7575 */ "LDXArr\000"
2842 /* 7582 */ "CASXArr\000"
2843 /* 7590 */ "STXArr\000"
2844 /* 7597 */ "LDSBrr\000"
2845 /* 7604 */ "STBrr\000"
2846 /* 7610 */ "LDUBrr\000"
2847 /* 7617 */ "SUBrr\000"
2848 /* 7623 */ "LDSTUBrr\000"
2849 /* 7632 */ "SMACrr\000"
2850 /* 7639 */ "UMACrr\000"
2851 /* 7646 */ "SUBCrr\000"
2852 /* 7653 */ "TSUBCCrr\000"
2853 /* 7662 */ "TADDCCrr\000"
2854 /* 7671 */ "ANDCCrr\000"
2855 /* 7679 */ "V9MOVFCCrr\000"
2856 /* 7690 */ "TICCrr\000"
2857 /* 7697 */ "MOVICCrr\000"
2858 /* 7706 */ "SMULCCrr\000"
2859 /* 7715 */ "UMULCCrr\000"
2860 /* 7724 */ "ANDNCCrr\000"
2861 /* 7733 */ "ORNCCrr\000"
2862 /* 7741 */ "XNORCCrr\000"
2863 /* 7750 */ "XORCCrr\000"
2864 /* 7758 */ "MULSCCrr\000"
2865 /* 7767 */ "SDIVCCrr\000"
2866 /* 7776 */ "UDIVCCrr\000"
2867 /* 7785 */ "TXCCrr\000"
2868 /* 7792 */ "MOVXCCrr\000"
2869 /* 7801 */ "ADDCrr\000"
2870 /* 7808 */ "LDDCrr\000"
2871 /* 7815 */ "LDCrr\000"
2872 /* 7821 */ "STDCrr\000"
2873 /* 7828 */ "POPCrr\000"
2874 /* 7835 */ "STCrr\000"
2875 /* 7841 */ "TLS_ADDrr\000"
2876 /* 7851 */ "LDDrr\000"
2877 /* 7857 */ "GDOP_LDrr\000"
2878 /* 7867 */ "TLS_LDrr\000"
2879 /* 7876 */ "ANDrr\000"
2880 /* 7882 */ "BINDrr\000"
2881 /* 7889 */ "CWBCONDrr\000"
2882 /* 7899 */ "CXBCONDrr\000"
2883 /* 7909 */ "STDrr\000"
2884 /* 7915 */ "SUBErr\000"
2885 /* 7922 */ "ADDErr\000"
2886 /* 7929 */ "RESTORErr\000"
2887 /* 7939 */ "SAVErr\000"
2888 /* 7946 */ "LDDFrr\000"
2889 /* 7953 */ "LDFrr\000"
2890 /* 7959 */ "STDFrr\000"
2891 /* 7966 */ "LDQFrr\000"
2892 /* 7973 */ "STQFrr\000"
2893 /* 7980 */ "STFrr\000"
2894 /* 7986 */ "LDSHrr\000"
2895 /* 7993 */ "FLUSHrr\000"
2896 /* 8001 */ "STHrr\000"
2897 /* 8007 */ "LDUHrr\000"
2898 /* 8014 */ "CALLrr\000"
2899 /* 8021 */ "SLLrr\000"
2900 /* 8027 */ "JMPLrr\000"
2901 /* 8034 */ "SRLrr\000"
2902 /* 8040 */ "SMULrr\000"
2903 /* 8047 */ "UMULrr\000"
2904 /* 8054 */ "WRWIMrr\000"
2905 /* 8062 */ "ANDNrr\000"
2906 /* 8069 */ "ORNrr\000"
2907 /* 8075 */ "TRAPrr\000"
2908 /* 8082 */ "SWAPrr\000"
2909 /* 8089 */ "STDCQrr\000"
2910 /* 8097 */ "STDFQrr\000"
2911 /* 8105 */ "WRTBRrr\000"
2912 /* 8113 */ "XNORrr\000"
2913 /* 8120 */ "XORrr\000"
2914 /* 8126 */ "WRPRrr\000"
2915 /* 8133 */ "WRASRrr\000"
2916 /* 8141 */ "LDCSRrr\000"
2917 /* 8149 */ "STCSRrr\000"
2918 /* 8157 */ "LDFSRrr\000"
2919 /* 8165 */ "STFSRrr\000"
2920 /* 8173 */ "LDXFSRrr\000"
2921 /* 8182 */ "STXFSRrr\000"
2922 /* 8191 */ "PWRPSRrr\000"
2923 /* 8200 */ "MOVRrr\000"
2924 /* 8207 */ "STrr\000"
2925 /* 8212 */ "RETTrr\000"
2926 /* 8219 */ "SDIVrr\000"
2927 /* 8226 */ "UDIVrr\000"
2928 /* 8233 */ "TSUBCCTVrr\000"
2929 /* 8244 */ "TADDCCTVrr\000"
2930 /* 8255 */ "LDSWrr\000"
2931 /* 8262 */ "SRAXrr\000"
2932 /* 8269 */ "GDOP_LDXrr\000"
2933 /* 8280 */ "TLS_LDXrr\000"
2934 /* 8290 */ "SLLXrr\000"
2935 /* 8297 */ "SRLXrr\000"
2936 /* 8304 */ "MULXrr\000"
2937 /* 8311 */ "STXrr\000"
2938 /* 8317 */ "SDIVXrr\000"
2939 /* 8325 */ "UDIVXrr\000"
2940};
2941#ifdef __GNUC__
2942#pragma GCC diagnostic pop
2943#endif
2944
2945extern const unsigned SparcInstrNameIndices[] = {
2946 2563U, 3128U, 4149U, 3592U, 2733U, 2714U, 2742U, 2923U,
2947 2350U, 2365U, 2305U, 2292U, 2392U, 5044U, 2132U, 5904U,
2948 2318U, 2559U, 2723U, 1875U, 6412U, 2656U, 2005U, 5730U,
2949 1598U, 1826U, 1863U, 3725U, 2911U, 5634U, 1777U, 3957U,
2950 2485U, 5623U, 2058U, 3930U, 3917U, 4220U, 5418U, 5441U,
2951 2834U, 2890U, 2863U, 2759U, 2123U, 4185U, 3673U, 2047U,
2952 6423U, 4346U, 3888U, 2180U, 5934U, 5964U, 3409U, 1379U,
2953 714U, 3056U, 6047U, 6054U, 3088U, 3095U, 3102U, 3112U,
2954 1576U, 4571U, 4534U, 4781U, 5989U, 4401U, 2823U, 4389U,
2955 2812U, 2303U, 2561U, 6289U, 2142U, 2157U, 2928U, 5386U,
2956 4859U, 5767U, 4876U, 4452U, 1126U, 5014U, 5645U, 4627U,
2957 5799U, 2223U, 4196U, 1694U, 1100U, 1676U, 5683U, 5664U,
2958 3387U, 4245U, 4264U, 1252U, 1196U, 1226U, 1237U, 1177U,
2959 1207U, 2102U, 2086U, 5080U, 2406U, 2423U, 1395U, 720U,
2960 1582U, 1523U, 4576U, 4540U, 6258U, 3535U, 6241U, 3518U,
2961 1346U, 697U, 6176U, 3453U, 3223U, 3170U, 3296U, 3258U,
2962 3787U, 3765U, 1635U, 5339U, 1855U, 2502U, 1626U, 5405U,
2963 5745U, 1078U, 5128U, 5600U, 5155U, 5948U, 1118U, 5212U,
2964 5996U, 6011U, 5559U, 5547U, 5720U, 2477U, 5927U, 2379U,
2965 5957U, 2798U, 4331U, 4317U, 2791U, 4324U, 4620U, 2960U,
2966 3857U, 3850U, 3864U, 3871U, 5396U, 3665U, 1896U, 3649U,
2967 1847U, 3657U, 1888U, 3641U, 1839U, 3703U, 3695U, 2521U,
2968 2513U, 5257U, 5247U, 5237U, 5227U, 5277U, 5267U, 6326U,
2969 6336U, 5287U, 5300U, 6346U, 6356U, 5313U, 5326U, 1304U,
2970 676U, 2984U, 640U, 1170U, 6026U, 3067U, 2248U, 6121U,
2971 2642U, 4001U, 263U, 9U, 2470U, 246U, 0U, 3976U,
2972 4008U, 2343U, 5919U, 1090U, 2624U, 2633U, 3817U, 3826U,
2973 5360U, 5373U, 4740U, 3424U, 5061U, 2232U, 3320U, 3330U,
2974 1945U, 1960U, 3159U, 3212U, 3244U, 3282U, 6061U, 6087U,
2975 6073U, 1904U, 1932U, 1917U, 2440U, 2455U, 1385U, 2670U,
2976 3487U, 6210U, 3511U, 6234U, 4747U, 1667U, 1657U, 4144U,
2977 5465U, 1983U, 4433U, 4413U, 5493U, 5472U, 4467U, 4498U,
2978 4484U, 5110U, 6452U, 2274U, 6445U, 2256U, 4897U, 3909U,
2979 3809U, 2110U, 2804U, 4925U, 3559U, 4932U, 3380U, 4917U,
2980 3551U, 3372U, 254U, 2545U, 2537U, 2529U, 5776U, 4380U,
2981 5656U, 5701U, 5809U, 4172U, 1992U, 1147U, 2201U, 2071U,
2982 1332U, 683U, 3012U, 6033U, 3074U, 646U, 5784U, 3985U,
2983 4284U, 4300U, 6403U, 2021U, 2213U, 5432U, 3711U, 3758U,
2984 3734U, 3746U, 1311U, 2991U, 1287U, 2967U, 6159U, 3436U,
2985 3191U, 3138U, 1363U, 3040U, 1560U, 4556U, 4518U, 6193U,
2986 3470U, 6217U, 3494U, 6303U, 6310U, 3615U, 3942U, 6274U,
2987 769U, 880U, 987U, 805U, 916U, 1023U, 846U, 953U,
2988 1060U, 787U, 898U, 1005U, 5437U, 6144U, 6398U, 4126U,
2989 6754U, 7663U, 6892U, 7801U, 6988U, 7922U, 1164U, 743U,
2990 6925U, 7845U, 31U, 5826U, 294U, 5862U, 44U, 5844U,
2991 307U, 5880U, 18U, 72U, 233U, 4162U, 2944U, 3363U,
2992 6762U, 7671U, 6815U, 7724U, 7133U, 8062U, 6942U, 7876U,
2993 516U, 219U, 544U, 599U, 1612U, 624U, 6948U, 7882U,
2994 2650U, 751U, 602U, 5513U, 5570U, 864U, 609U, 5522U,
2995 5578U, 4591U, 659U, 5540U, 5714U, 971U, 616U, 5531U,
2996 5586U, 2012U, 2849U, 6487U, 7085U, 6501U, 8014U, 7389U,
2997 2332U, 2779U, 2593U, 6645U, 7554U, 6673U, 7582U, 396U,
2998 171U, 537U, 1618U, 631U, 736U, 6955U, 7889U, 6965U,
2999 7899U, 3835U, 3843U, 1548U, 1720U, 2037U, 363U, 2688U,
3000 3575U, 3348U, 138U, 2680U, 3566U, 3340U, 531U, 2696U,
3001 3584U, 3356U, 1801U, 4101U, 5074U, 1411U, 4023U, 4788U,
3002 664U, 1512U, 85U, 4645U, 271U, 4696U, 4831U, 1611U,
3003 623U, 551U, 562U, 418U, 1764U, 572U, 435U, 193U,
3004 452U, 210U, 370U, 145U, 379U, 154U, 4088U, 581U,
3005 4983U, 590U, 1814U, 4114U, 5200U, 4049U, 2606U, 4062U,
3006 4949U, 6372U, 1540U, 1417U, 4794U, 1265U, 4759U, 1730U,
3007 4068U, 4955U, 1770U, 4989U, 2553U, 6099U, 7059U, 7993U,
3008 1432U, 4809U, 427U, 1820U, 759U, 870U, 977U, 4120U,
3009 824U, 933U, 1040U, 1794U, 4094U, 5037U, 5206U, 836U,
3010 943U, 1050U, 1272U, 4766U, 505U, 482U, 461U, 2703U,
3011 5978U, 1484U, 493U, 470U, 4056U, 4904U, 1447U, 4824U,
3012 1517U, 4837U, 1478U, 4043U, 4891U, 1424U, 4801U, 1439U,
3013 4816U, 1279U, 4773U, 1490U, 4910U, 4369U, 5001U, 94U,
3014 4655U, 280U, 4706U, 1504U, 2042U, 4844U, 4342U, 100U,
3015 4662U, 286U, 4713U, 4996U, 388U, 163U, 6317U, 355U,
3016 4731U, 130U, 4680U, 324U, 6281U, 2567U, 1975U, 347U,
3017 4722U, 122U, 4671U, 1736U, 2612U, 4961U, 6386U, 444U,
3018 202U, 404U, 179U, 1497U, 1807U, 4107U, 5193U, 340U,
3019 115U, 66U, 4638U, 227U, 4689U, 411U, 186U, 1742U,
3020 2618U, 4074U, 6392U, 1259U, 4017U, 4753U, 4374U, 5007U,
3021 4513U, 5031U, 1748U, 4080U, 4975U, 3719U, 4942U, 8269U,
3022 7857U, 6114U, 7098U, 8027U, 6549U, 7458U, 7212U, 8141U,
3023 6906U, 7815U, 6542U, 7451U, 6899U, 7808U, 6562U, 7471U,
3024 7012U, 7946U, 6931U, 7851U, 6570U, 7479U, 7228U, 8157U,
3025 7019U, 7953U, 6585U, 7494U, 7032U, 7966U, 6509U, 7418U,
3026 6688U, 7597U, 6608U, 7517U, 7052U, 7986U, 6532U, 7441U,
3027 6714U, 7623U, 6658U, 7567U, 7326U, 8255U, 6524U, 7433U,
3028 6701U, 7610U, 6623U, 7532U, 7073U, 8007U, 6666U, 7575U,
3029 7244U, 8173U, 7340U, 8274U, 6937U, 7862U, 5594U, 336U,
3030 6493U, 3032U, 4600U, 6378U, 6772U, 7681U, 6788U, 7697U,
3031 7271U, 8200U, 6135U, 6150U, 4967U, 6883U, 7792U, 1754U,
3032 3026U, 6849U, 7758U, 7360U, 8304U, 3884U, 6106U, 6834U,
3033 7743U, 6824U, 7733U, 7140U, 8069U, 7186U, 8115U, 6128U,
3034 5898U, 3608U, 7828U, 6459U, 7397U, 6470U, 7408U, 7262U,
3035 8191U, 4608U, 4038U, 4595U, 4614U, 4138U, 3122U, 1463U,
3036 6995U, 7929U, 5428U, 2955U, 6417U, 7283U, 8212U, 1472U,
3037 7005U, 7939U, 6858U, 7767U, 7373U, 8317U, 7290U, 8219U,
3038 6480U, 57U, 524U, 108U, 3632U, 3062U, 4338U, 7346U,
3039 8290U, 7092U, 8021U, 6723U, 7632U, 6797U, 7706U, 7111U,
3040 8040U, 7333U, 8262U, 6639U, 7548U, 7353U, 8297U, 7105U,
3041 8034U, 6652U, 7561U, 4132U, 6517U, 7426U, 6695U, 7604U,
3042 7220U, 8149U, 6919U, 7835U, 6555U, 7464U, 7160U, 8089U,
3043 6912U, 7821U, 6577U, 7486U, 7168U, 8097U, 7025U, 7959U,
3044 6975U, 7909U, 6601U, 7510U, 7236U, 8165U, 7046U, 7980U,
3045 6616U, 7525U, 7067U, 8001U, 6593U, 7502U, 7039U, 7973U,
3046 6681U, 7590U, 7253U, 8182U, 7367U, 8311U, 7278U, 8207U,
3047 6745U, 7654U, 6737U, 7646U, 6981U, 7915U, 6708U, 7617U,
3048 6631U, 7540U, 7153U, 8082U, 62U, 320U, 332U, 7315U,
3049 8244U, 6753U, 7662U, 2844U, 7080U, 6781U, 7690U, 7841U,
3050 2854U, 8280U, 7867U, 7146U, 8075U, 7304U, 8233U, 6744U,
3051 7653U, 6876U, 7785U, 6867U, 7776U, 7381U, 8325U, 7297U,
3052 8226U, 6730U, 7639U, 6806U, 7715U, 2577U, 7118U, 8047U,
3053 3878U, 1762U, 1454U, 4029U, 4850U, 4086U, 4981U, 757U,
3054 822U, 834U, 6770U, 7679U, 7204U, 8133U, 7197U, 8126U,
3055 7263U, 8192U, 7176U, 8105U, 7125U, 8054U, 6366U, 2585U,
3056 6832U, 7741U, 7184U, 8113U, 6841U, 7750U, 7191U, 8120U,
3057};
3058
3059extern const int16_t SparcRegClassByHwModeTables[2][1] = {
3060 { // DefaultMode
3061 SP::IntRegsRegClassID, // sparc_ptr_rc
3062 },
3063 { // SPARC64
3064 SP::I64RegsRegClassID, // sparc_ptr_rc
3065 },
3066};
3067
3068static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
3069 II->InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 888, &SparcRegClassByHwModeTables[0][0], 1);
3070}
3071
3072
3073} // namespace llvm
3074
3075#endif // GET_INSTRINFO_MC_DESC
3076
3077#ifdef GET_INSTRINFO_HEADER
3078#undef GET_INSTRINFO_HEADER
3079
3080namespace llvm {
3081
3082struct SparcGenInstrInfo : public TargetInstrInfo {
3083 explicit SparcGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
3084 ~SparcGenInstrInfo() override = default;
3085};
3086extern const int16_t SparcRegClassByHwModeTables[2][1];
3087
3088} // namespace llvm
3089
3090namespace llvm::SP {
3091
3092
3093} // namespace llvm::SP
3094
3095#endif // GET_INSTRINFO_HEADER
3096
3097#ifdef GET_INSTRINFO_HELPER_DECLS
3098#undef GET_INSTRINFO_HELPER_DECLS
3099
3100
3101#endif // GET_INSTRINFO_HELPER_DECLS
3102
3103#ifdef GET_INSTRINFO_HELPERS
3104#undef GET_INSTRINFO_HELPERS
3105
3106
3107#endif // GET_INSTRINFO_HELPERS
3108
3109#ifdef GET_INSTRINFO_CTOR_DTOR
3110#undef GET_INSTRINFO_CTOR_DTOR
3111
3112namespace llvm {
3113
3114extern const SparcInstrTable SparcDescs;
3115extern const unsigned SparcInstrNameIndices[];
3116extern const char SparcInstrNameData[];
3117SparcGenInstrInfo::SparcGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
3118 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, SparcRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) {
3119 InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 888, &SparcRegClassByHwModeTables[0][0], 1);
3120}
3121
3122} // namespace llvm
3123
3124#endif // GET_INSTRINFO_CTOR_DTOR
3125
3126#ifdef GET_INSTRINFO_MC_HELPER_DECLS
3127#undef GET_INSTRINFO_MC_HELPER_DECLS
3128
3129namespace llvm {
3130
3131class MCInst;
3132class FeatureBitset;
3133
3134namespace Sparc_MC {
3135
3136void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
3137
3138} // namespace Sparc_MC
3139
3140} // namespace llvm
3141
3142#endif // GET_INSTRINFO_MC_HELPER_DECLS
3143
3144#ifdef GET_INSTRINFO_MC_HELPERS
3145#undef GET_INSTRINFO_MC_HELPERS
3146
3147namespace llvm::Sparc_MC {
3148
3149
3150} // namespace llvm::Sparc_MC
3151
3152#endif // GET_INSTRINFO_MC_HELPERS
3153
3154#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3155 defined(GET_AVAILABLE_OPCODE_CHECKER)
3156#define GET_COMPUTE_FEATURES
3157#endif
3158#ifdef GET_COMPUTE_FEATURES
3159#undef GET_COMPUTE_FEATURES
3160
3161namespace llvm::Sparc_MC {
3162
3163// Bits for subtarget features that participate in instruction matching.
3164enum SubtargetFeatureBits : uint8_t {
3165 Feature_Is32BitBit = 10,
3166 Feature_Is64BitBit = 11,
3167 Feature_UseSoftMulDivBit = 12,
3168 Feature_HasV9Bit = 6,
3169 Feature_HasVISBit = 7,
3170 Feature_HasVIS2Bit = 8,
3171 Feature_HasVIS3Bit = 9,
3172 Feature_HasUA2005Bit = 4,
3173 Feature_HasUA2007Bit = 5,
3174 Feature_HasOSA2011Bit = 2,
3175 Feature_HasCryptoBit = 1,
3176 Feature_HasCASABit = 0,
3177 Feature_HasPWRPSRBit = 3,
3178};
3179
3180inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3181 FeatureBitset Features;
3182 if (!FB[Sparc::Feature64Bit])
3183 Features.set(Feature_Is32BitBit);
3184 if (FB[Sparc::Feature64Bit])
3185 Features.set(Feature_Is64BitBit);
3186 if (FB[Sparc::FeatureSoftMulDiv])
3187 Features.set(Feature_UseSoftMulDivBit);
3188 if (FB[Sparc::FeatureV9])
3189 Features.set(Feature_HasV9Bit);
3190 if (FB[Sparc::FeatureVIS])
3191 Features.set(Feature_HasVISBit);
3192 if (FB[Sparc::FeatureVIS2])
3193 Features.set(Feature_HasVIS2Bit);
3194 if (FB[Sparc::FeatureVIS3])
3195 Features.set(Feature_HasVIS3Bit);
3196 if (FB[Sparc::FeatureUA2005])
3197 Features.set(Feature_HasUA2005Bit);
3198 if (FB[Sparc::FeatureUA2007])
3199 Features.set(Feature_HasUA2007Bit);
3200 if (FB[Sparc::FeatureOSA2011])
3201 Features.set(Feature_HasOSA2011Bit);
3202 if (FB[Sparc::FeatureCrypto])
3203 Features.set(Feature_HasCryptoBit);
3204 if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
3205 Features.set(Feature_HasCASABit);
3206 if (FB[Sparc::FeaturePWRPSR])
3207 Features.set(Feature_HasPWRPSRBit);
3208 return Features;
3209}
3210
3211inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3212 enum : uint8_t {
3213 CEFBS_None,
3214 CEFBS_HasCASA,
3215 CEFBS_HasCrypto,
3216 CEFBS_HasOSA2011,
3217 CEFBS_HasPWRPSR,
3218 CEFBS_HasUA2005,
3219 CEFBS_HasUA2007,
3220 CEFBS_HasV9,
3221 CEFBS_HasVIS,
3222 CEFBS_HasVIS2,
3223 CEFBS_HasVIS3,
3224 CEFBS_Is64Bit,
3225 CEFBS_Is64Bit_HasV9,
3226 };
3227
3228 static constexpr FeatureBitset FeatureBitsets[] = {
3229 {}, // CEFBS_None
3230 {Feature_HasCASABit, },
3231 {Feature_HasCryptoBit, },
3232 {Feature_HasOSA2011Bit, },
3233 {Feature_HasPWRPSRBit, },
3234 {Feature_HasUA2005Bit, },
3235 {Feature_HasUA2007Bit, },
3236 {Feature_HasV9Bit, },
3237 {Feature_HasVISBit, },
3238 {Feature_HasVIS2Bit, },
3239 {Feature_HasVIS3Bit, },
3240 {Feature_Is64BitBit, },
3241 {Feature_Is64BitBit, Feature_HasV9Bit, },
3242 };
3243 static constexpr uint8_t RequiredFeaturesRefs[] = {
3244 CEFBS_None, // PHI
3245 CEFBS_None, // INLINEASM
3246 CEFBS_None, // INLINEASM_BR
3247 CEFBS_None, // CFI_INSTRUCTION
3248 CEFBS_None, // EH_LABEL
3249 CEFBS_None, // GC_LABEL
3250 CEFBS_None, // ANNOTATION_LABEL
3251 CEFBS_None, // KILL
3252 CEFBS_None, // EXTRACT_SUBREG
3253 CEFBS_None, // INSERT_SUBREG
3254 CEFBS_None, // IMPLICIT_DEF
3255 CEFBS_None, // INIT_UNDEF
3256 CEFBS_None, // SUBREG_TO_REG
3257 CEFBS_None, // COPY_TO_REGCLASS
3258 CEFBS_None, // DBG_VALUE
3259 CEFBS_None, // DBG_VALUE_LIST
3260 CEFBS_None, // DBG_INSTR_REF
3261 CEFBS_None, // DBG_PHI
3262 CEFBS_None, // DBG_LABEL
3263 CEFBS_None, // REG_SEQUENCE
3264 CEFBS_None, // COPY
3265 CEFBS_None, // COPY_LANEMASK
3266 CEFBS_None, // BUNDLE
3267 CEFBS_None, // LIFETIME_START
3268 CEFBS_None, // LIFETIME_END
3269 CEFBS_None, // PSEUDO_PROBE
3270 CEFBS_None, // ARITH_FENCE
3271 CEFBS_None, // STACKMAP
3272 CEFBS_None, // FENTRY_CALL
3273 CEFBS_None, // PATCHPOINT
3274 CEFBS_None, // LOAD_STACK_GUARD
3275 CEFBS_None, // PREALLOCATED_SETUP
3276 CEFBS_None, // PREALLOCATED_ARG
3277 CEFBS_None, // STATEPOINT
3278 CEFBS_None, // LOCAL_ESCAPE
3279 CEFBS_None, // FAULTING_OP
3280 CEFBS_None, // PATCHABLE_OP
3281 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
3282 CEFBS_None, // PATCHABLE_RET
3283 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
3284 CEFBS_None, // PATCHABLE_TAIL_CALL
3285 CEFBS_None, // PATCHABLE_EVENT_CALL
3286 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
3287 CEFBS_None, // ICALL_BRANCH_FUNNEL
3288 CEFBS_None, // FAKE_USE
3289 CEFBS_None, // MEMBARRIER
3290 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
3291 CEFBS_None, // RELOC_NONE
3292 CEFBS_None, // CONVERGENCECTRL_ENTRY
3293 CEFBS_None, // CONVERGENCECTRL_ANCHOR
3294 CEFBS_None, // CONVERGENCECTRL_LOOP
3295 CEFBS_None, // CONVERGENCECTRL_GLUE
3296 CEFBS_None, // G_ASSERT_SEXT
3297 CEFBS_None, // G_ASSERT_ZEXT
3298 CEFBS_None, // G_ASSERT_ALIGN
3299 CEFBS_None, // G_ADD
3300 CEFBS_None, // G_SUB
3301 CEFBS_None, // G_MUL
3302 CEFBS_None, // G_SDIV
3303 CEFBS_None, // G_UDIV
3304 CEFBS_None, // G_SREM
3305 CEFBS_None, // G_UREM
3306 CEFBS_None, // G_SDIVREM
3307 CEFBS_None, // G_UDIVREM
3308 CEFBS_None, // G_AND
3309 CEFBS_None, // G_OR
3310 CEFBS_None, // G_XOR
3311 CEFBS_None, // G_ABDS
3312 CEFBS_None, // G_ABDU
3313 CEFBS_None, // G_UAVGFLOOR
3314 CEFBS_None, // G_UAVGCEIL
3315 CEFBS_None, // G_SAVGFLOOR
3316 CEFBS_None, // G_SAVGCEIL
3317 CEFBS_None, // G_IMPLICIT_DEF
3318 CEFBS_None, // G_PHI
3319 CEFBS_None, // G_FRAME_INDEX
3320 CEFBS_None, // G_GLOBAL_VALUE
3321 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3322 CEFBS_None, // G_CONSTANT_POOL
3323 CEFBS_None, // G_EXTRACT
3324 CEFBS_None, // G_UNMERGE_VALUES
3325 CEFBS_None, // G_INSERT
3326 CEFBS_None, // G_MERGE_VALUES
3327 CEFBS_None, // G_BUILD_VECTOR
3328 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3329 CEFBS_None, // G_CONCAT_VECTORS
3330 CEFBS_None, // G_PTRTOINT
3331 CEFBS_None, // G_INTTOPTR
3332 CEFBS_None, // G_BITCAST
3333 CEFBS_None, // G_FREEZE
3334 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3335 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3336 CEFBS_None, // G_INTRINSIC_TRUNC
3337 CEFBS_None, // G_INTRINSIC_ROUND
3338 CEFBS_None, // G_INTRINSIC_LRINT
3339 CEFBS_None, // G_INTRINSIC_LLRINT
3340 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3341 CEFBS_None, // G_READCYCLECOUNTER
3342 CEFBS_None, // G_READSTEADYCOUNTER
3343 CEFBS_None, // G_LOAD
3344 CEFBS_None, // G_SEXTLOAD
3345 CEFBS_None, // G_ZEXTLOAD
3346 CEFBS_None, // G_INDEXED_LOAD
3347 CEFBS_None, // G_INDEXED_SEXTLOAD
3348 CEFBS_None, // G_INDEXED_ZEXTLOAD
3349 CEFBS_None, // G_STORE
3350 CEFBS_None, // G_INDEXED_STORE
3351 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3352 CEFBS_None, // G_ATOMIC_CMPXCHG
3353 CEFBS_None, // G_ATOMICRMW_XCHG
3354 CEFBS_None, // G_ATOMICRMW_ADD
3355 CEFBS_None, // G_ATOMICRMW_SUB
3356 CEFBS_None, // G_ATOMICRMW_AND
3357 CEFBS_None, // G_ATOMICRMW_NAND
3358 CEFBS_None, // G_ATOMICRMW_OR
3359 CEFBS_None, // G_ATOMICRMW_XOR
3360 CEFBS_None, // G_ATOMICRMW_MAX
3361 CEFBS_None, // G_ATOMICRMW_MIN
3362 CEFBS_None, // G_ATOMICRMW_UMAX
3363 CEFBS_None, // G_ATOMICRMW_UMIN
3364 CEFBS_None, // G_ATOMICRMW_FADD
3365 CEFBS_None, // G_ATOMICRMW_FSUB
3366 CEFBS_None, // G_ATOMICRMW_FMAX
3367 CEFBS_None, // G_ATOMICRMW_FMIN
3368 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3369 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3370 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
3371 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
3372 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3373 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3374 CEFBS_None, // G_ATOMICRMW_USUB_COND
3375 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3376 CEFBS_None, // G_FENCE
3377 CEFBS_None, // G_PREFETCH
3378 CEFBS_None, // G_BRCOND
3379 CEFBS_None, // G_BRINDIRECT
3380 CEFBS_None, // G_INVOKE_REGION_START
3381 CEFBS_None, // G_INTRINSIC
3382 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3383 CEFBS_None, // G_INTRINSIC_CONVERGENT
3384 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3385 CEFBS_None, // G_ANYEXT
3386 CEFBS_None, // G_TRUNC
3387 CEFBS_None, // G_TRUNC_SSAT_S
3388 CEFBS_None, // G_TRUNC_SSAT_U
3389 CEFBS_None, // G_TRUNC_USAT_U
3390 CEFBS_None, // G_CONSTANT
3391 CEFBS_None, // G_FCONSTANT
3392 CEFBS_None, // G_VASTART
3393 CEFBS_None, // G_VAARG
3394 CEFBS_None, // G_SEXT
3395 CEFBS_None, // G_SEXT_INREG
3396 CEFBS_None, // G_ZEXT
3397 CEFBS_None, // G_SHL
3398 CEFBS_None, // G_LSHR
3399 CEFBS_None, // G_ASHR
3400 CEFBS_None, // G_FSHL
3401 CEFBS_None, // G_FSHR
3402 CEFBS_None, // G_ROTR
3403 CEFBS_None, // G_ROTL
3404 CEFBS_None, // G_ICMP
3405 CEFBS_None, // G_FCMP
3406 CEFBS_None, // G_SCMP
3407 CEFBS_None, // G_UCMP
3408 CEFBS_None, // G_SELECT
3409 CEFBS_None, // G_UADDO
3410 CEFBS_None, // G_UADDE
3411 CEFBS_None, // G_USUBO
3412 CEFBS_None, // G_USUBE
3413 CEFBS_None, // G_SADDO
3414 CEFBS_None, // G_SADDE
3415 CEFBS_None, // G_SSUBO
3416 CEFBS_None, // G_SSUBE
3417 CEFBS_None, // G_UMULO
3418 CEFBS_None, // G_SMULO
3419 CEFBS_None, // G_UMULH
3420 CEFBS_None, // G_SMULH
3421 CEFBS_None, // G_UADDSAT
3422 CEFBS_None, // G_SADDSAT
3423 CEFBS_None, // G_USUBSAT
3424 CEFBS_None, // G_SSUBSAT
3425 CEFBS_None, // G_USHLSAT
3426 CEFBS_None, // G_SSHLSAT
3427 CEFBS_None, // G_SMULFIX
3428 CEFBS_None, // G_UMULFIX
3429 CEFBS_None, // G_SMULFIXSAT
3430 CEFBS_None, // G_UMULFIXSAT
3431 CEFBS_None, // G_SDIVFIX
3432 CEFBS_None, // G_UDIVFIX
3433 CEFBS_None, // G_SDIVFIXSAT
3434 CEFBS_None, // G_UDIVFIXSAT
3435 CEFBS_None, // G_FADD
3436 CEFBS_None, // G_FSUB
3437 CEFBS_None, // G_FMUL
3438 CEFBS_None, // G_FMA
3439 CEFBS_None, // G_FMAD
3440 CEFBS_None, // G_FDIV
3441 CEFBS_None, // G_FREM
3442 CEFBS_None, // G_FMODF
3443 CEFBS_None, // G_FPOW
3444 CEFBS_None, // G_FPOWI
3445 CEFBS_None, // G_FEXP
3446 CEFBS_None, // G_FEXP2
3447 CEFBS_None, // G_FEXP10
3448 CEFBS_None, // G_FLOG
3449 CEFBS_None, // G_FLOG2
3450 CEFBS_None, // G_FLOG10
3451 CEFBS_None, // G_FLDEXP
3452 CEFBS_None, // G_FFREXP
3453 CEFBS_None, // G_FNEG
3454 CEFBS_None, // G_FPEXT
3455 CEFBS_None, // G_FPTRUNC
3456 CEFBS_None, // G_FPTOSI
3457 CEFBS_None, // G_FPTOUI
3458 CEFBS_None, // G_SITOFP
3459 CEFBS_None, // G_UITOFP
3460 CEFBS_None, // G_FPTOSI_SAT
3461 CEFBS_None, // G_FPTOUI_SAT
3462 CEFBS_None, // G_FABS
3463 CEFBS_None, // G_FCOPYSIGN
3464 CEFBS_None, // G_IS_FPCLASS
3465 CEFBS_None, // G_FCANONICALIZE
3466 CEFBS_None, // G_FMINNUM
3467 CEFBS_None, // G_FMAXNUM
3468 CEFBS_None, // G_FMINNUM_IEEE
3469 CEFBS_None, // G_FMAXNUM_IEEE
3470 CEFBS_None, // G_FMINIMUM
3471 CEFBS_None, // G_FMAXIMUM
3472 CEFBS_None, // G_FMINIMUMNUM
3473 CEFBS_None, // G_FMAXIMUMNUM
3474 CEFBS_None, // G_GET_FPENV
3475 CEFBS_None, // G_SET_FPENV
3476 CEFBS_None, // G_RESET_FPENV
3477 CEFBS_None, // G_GET_FPMODE
3478 CEFBS_None, // G_SET_FPMODE
3479 CEFBS_None, // G_RESET_FPMODE
3480 CEFBS_None, // G_GET_ROUNDING
3481 CEFBS_None, // G_SET_ROUNDING
3482 CEFBS_None, // G_PTR_ADD
3483 CEFBS_None, // G_PTRMASK
3484 CEFBS_None, // G_SMIN
3485 CEFBS_None, // G_SMAX
3486 CEFBS_None, // G_UMIN
3487 CEFBS_None, // G_UMAX
3488 CEFBS_None, // G_ABS
3489 CEFBS_None, // G_LROUND
3490 CEFBS_None, // G_LLROUND
3491 CEFBS_None, // G_BR
3492 CEFBS_None, // G_BRJT
3493 CEFBS_None, // G_VSCALE
3494 CEFBS_None, // G_INSERT_SUBVECTOR
3495 CEFBS_None, // G_EXTRACT_SUBVECTOR
3496 CEFBS_None, // G_INSERT_VECTOR_ELT
3497 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3498 CEFBS_None, // G_SHUFFLE_VECTOR
3499 CEFBS_None, // G_SPLAT_VECTOR
3500 CEFBS_None, // G_STEP_VECTOR
3501 CEFBS_None, // G_VECTOR_COMPRESS
3502 CEFBS_None, // G_CTTZ
3503 CEFBS_None, // G_CTTZ_ZERO_UNDEF
3504 CEFBS_None, // G_CTLZ
3505 CEFBS_None, // G_CTLZ_ZERO_UNDEF
3506 CEFBS_None, // G_CTLS
3507 CEFBS_None, // G_CTPOP
3508 CEFBS_None, // G_BSWAP
3509 CEFBS_None, // G_BITREVERSE
3510 CEFBS_None, // G_FCEIL
3511 CEFBS_None, // G_FCOS
3512 CEFBS_None, // G_FSIN
3513 CEFBS_None, // G_FSINCOS
3514 CEFBS_None, // G_FTAN
3515 CEFBS_None, // G_FACOS
3516 CEFBS_None, // G_FASIN
3517 CEFBS_None, // G_FATAN
3518 CEFBS_None, // G_FATAN2
3519 CEFBS_None, // G_FCOSH
3520 CEFBS_None, // G_FSINH
3521 CEFBS_None, // G_FTANH
3522 CEFBS_None, // G_FSQRT
3523 CEFBS_None, // G_FFLOOR
3524 CEFBS_None, // G_FRINT
3525 CEFBS_None, // G_FNEARBYINT
3526 CEFBS_None, // G_ADDRSPACE_CAST
3527 CEFBS_None, // G_BLOCK_ADDR
3528 CEFBS_None, // G_JUMP_TABLE
3529 CEFBS_None, // G_DYN_STACKALLOC
3530 CEFBS_None, // G_STACKSAVE
3531 CEFBS_None, // G_STACKRESTORE
3532 CEFBS_None, // G_STRICT_FADD
3533 CEFBS_None, // G_STRICT_FSUB
3534 CEFBS_None, // G_STRICT_FMUL
3535 CEFBS_None, // G_STRICT_FDIV
3536 CEFBS_None, // G_STRICT_FREM
3537 CEFBS_None, // G_STRICT_FMA
3538 CEFBS_None, // G_STRICT_FSQRT
3539 CEFBS_None, // G_STRICT_FLDEXP
3540 CEFBS_None, // G_READ_REGISTER
3541 CEFBS_None, // G_WRITE_REGISTER
3542 CEFBS_None, // G_MEMCPY
3543 CEFBS_None, // G_MEMCPY_INLINE
3544 CEFBS_None, // G_MEMMOVE
3545 CEFBS_None, // G_MEMSET
3546 CEFBS_None, // G_BZERO
3547 CEFBS_None, // G_TRAP
3548 CEFBS_None, // G_DEBUGTRAP
3549 CEFBS_None, // G_UBSANTRAP
3550 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3551 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3552 CEFBS_None, // G_VECREDUCE_FADD
3553 CEFBS_None, // G_VECREDUCE_FMUL
3554 CEFBS_None, // G_VECREDUCE_FMAX
3555 CEFBS_None, // G_VECREDUCE_FMIN
3556 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3557 CEFBS_None, // G_VECREDUCE_FMINIMUM
3558 CEFBS_None, // G_VECREDUCE_ADD
3559 CEFBS_None, // G_VECREDUCE_MUL
3560 CEFBS_None, // G_VECREDUCE_AND
3561 CEFBS_None, // G_VECREDUCE_OR
3562 CEFBS_None, // G_VECREDUCE_XOR
3563 CEFBS_None, // G_VECREDUCE_SMAX
3564 CEFBS_None, // G_VECREDUCE_SMIN
3565 CEFBS_None, // G_VECREDUCE_UMAX
3566 CEFBS_None, // G_VECREDUCE_UMIN
3567 CEFBS_None, // G_SBFX
3568 CEFBS_None, // G_UBFX
3569 CEFBS_None, // ADJCALLSTACKDOWN
3570 CEFBS_None, // ADJCALLSTACKUP
3571 CEFBS_None, // GETPCX
3572 CEFBS_None, // SELECT_CC_DFP_FCC
3573 CEFBS_None, // SELECT_CC_DFP_ICC
3574 CEFBS_None, // SELECT_CC_DFP_XCC
3575 CEFBS_None, // SELECT_CC_FP_FCC
3576 CEFBS_None, // SELECT_CC_FP_ICC
3577 CEFBS_None, // SELECT_CC_FP_XCC
3578 CEFBS_None, // SELECT_CC_Int_FCC
3579 CEFBS_None, // SELECT_CC_Int_ICC
3580 CEFBS_None, // SELECT_CC_Int_XCC
3581 CEFBS_None, // SELECT_CC_QFP_FCC
3582 CEFBS_None, // SELECT_CC_QFP_ICC
3583 CEFBS_None, // SELECT_CC_QFP_XCC
3584 CEFBS_None, // SET
3585 CEFBS_HasV9, // SETSW
3586 CEFBS_Is64Bit_HasV9, // SETX
3587 CEFBS_None, // V8BAR
3588 CEFBS_None, // ADDCCri
3589 CEFBS_None, // ADDCCrr
3590 CEFBS_None, // ADDCri
3591 CEFBS_None, // ADDCrr
3592 CEFBS_None, // ADDEri
3593 CEFBS_None, // ADDErr
3594 CEFBS_HasVIS3, // ADDXC
3595 CEFBS_HasVIS3, // ADDXCCC
3596 CEFBS_None, // ADDri
3597 CEFBS_None, // ADDrr
3598 CEFBS_HasCrypto, // AES_DROUND01
3599 CEFBS_HasCrypto, // AES_DROUND01_LAST
3600 CEFBS_HasCrypto, // AES_DROUND23
3601 CEFBS_HasCrypto, // AES_DROUND23_LAST
3602 CEFBS_HasCrypto, // AES_EROUND01
3603 CEFBS_HasCrypto, // AES_EROUND01_LAST
3604 CEFBS_HasCrypto, // AES_EROUND23
3605 CEFBS_HasCrypto, // AES_EROUND23_LAST
3606 CEFBS_HasCrypto, // AES_KEXPAND0
3607 CEFBS_HasCrypto, // AES_KEXPAND1
3608 CEFBS_HasCrypto, // AES_KEXPAND2
3609 CEFBS_HasVIS, // ALIGNADDR
3610 CEFBS_HasVIS, // ALIGNADDRL
3611 CEFBS_HasUA2005, // ALLCLEAN
3612 CEFBS_None, // ANDCCri
3613 CEFBS_None, // ANDCCrr
3614 CEFBS_None, // ANDNCCri
3615 CEFBS_None, // ANDNCCrr
3616 CEFBS_None, // ANDNri
3617 CEFBS_None, // ANDNrr
3618 CEFBS_None, // ANDri
3619 CEFBS_None, // ANDrr
3620 CEFBS_HasVIS, // ARRAY16
3621 CEFBS_HasVIS, // ARRAY32
3622 CEFBS_HasVIS, // ARRAY8
3623 CEFBS_None, // BA
3624 CEFBS_None, // BCOND
3625 CEFBS_None, // BCONDA
3626 CEFBS_None, // BINDri
3627 CEFBS_None, // BINDrr
3628 CEFBS_HasVIS2, // BMASK
3629 CEFBS_HasV9, // BPFCC
3630 CEFBS_HasV9, // BPFCCA
3631 CEFBS_HasV9, // BPFCCANT
3632 CEFBS_HasV9, // BPFCCNT
3633 CEFBS_HasV9, // BPICC
3634 CEFBS_HasV9, // BPICCA
3635 CEFBS_HasV9, // BPICCANT
3636 CEFBS_HasV9, // BPICCNT
3637 CEFBS_Is64Bit, // BPR
3638 CEFBS_Is64Bit, // BPRA
3639 CEFBS_Is64Bit, // BPRANT
3640 CEFBS_Is64Bit, // BPRNT
3641 CEFBS_Is64Bit, // BPXCC
3642 CEFBS_Is64Bit, // BPXCCA
3643 CEFBS_Is64Bit, // BPXCCANT
3644 CEFBS_Is64Bit, // BPXCCNT
3645 CEFBS_HasVIS2, // BSHUFFLE
3646 CEFBS_None, // CALL
3647 CEFBS_None, // CALLi
3648 CEFBS_None, // CALLri
3649 CEFBS_None, // CALLrii
3650 CEFBS_None, // CALLrr
3651 CEFBS_None, // CALLrri
3652 CEFBS_HasCrypto, // CAMELLIA_F
3653 CEFBS_HasCrypto, // CAMELLIA_FL
3654 CEFBS_HasCrypto, // CAMELLIA_FLI
3655 CEFBS_HasV9, // CASAri
3656 CEFBS_HasCASA, // CASArr
3657 CEFBS_Is64Bit_HasV9, // CASXAri
3658 CEFBS_Is64Bit_HasV9, // CASXArr
3659 CEFBS_HasVIS3, // CMASK16
3660 CEFBS_HasVIS3, // CMASK32
3661 CEFBS_HasVIS3, // CMASK8
3662 CEFBS_None, // CPBCOND
3663 CEFBS_None, // CPBCONDA
3664 CEFBS_HasCrypto, // CRC32C
3665 CEFBS_HasOSA2011, // CWBCONDri
3666 CEFBS_HasOSA2011, // CWBCONDrr
3667 CEFBS_HasOSA2011, // CXBCONDri
3668 CEFBS_HasOSA2011, // CXBCONDrr
3669 CEFBS_HasCrypto, // DES_IIP
3670 CEFBS_HasCrypto, // DES_IP
3671 CEFBS_HasCrypto, // DES_KEXPAND
3672 CEFBS_HasCrypto, // DES_ROUND
3673 CEFBS_HasV9, // DONE
3674 CEFBS_HasVIS, // EDGE16
3675 CEFBS_HasVIS, // EDGE16L
3676 CEFBS_HasVIS2, // EDGE16LN
3677 CEFBS_HasVIS2, // EDGE16N
3678 CEFBS_HasVIS, // EDGE32
3679 CEFBS_HasVIS, // EDGE32L
3680 CEFBS_HasVIS2, // EDGE32LN
3681 CEFBS_HasVIS2, // EDGE32N
3682 CEFBS_HasVIS, // EDGE8
3683 CEFBS_HasVIS, // EDGE8L
3684 CEFBS_HasVIS2, // EDGE8LN
3685 CEFBS_HasVIS2, // EDGE8N
3686 CEFBS_HasV9, // FABSD
3687 CEFBS_HasV9, // FABSQ
3688 CEFBS_None, // FABSS
3689 CEFBS_None, // FADDD
3690 CEFBS_None, // FADDQ
3691 CEFBS_None, // FADDS
3692 CEFBS_HasVIS, // FALIGNADATA
3693 CEFBS_HasVIS, // FAND
3694 CEFBS_HasVIS, // FANDNOT1
3695 CEFBS_HasVIS, // FANDNOT1S
3696 CEFBS_HasVIS, // FANDNOT2
3697 CEFBS_HasVIS, // FANDNOT2S
3698 CEFBS_HasVIS, // FANDS
3699 CEFBS_None, // FBCOND
3700 CEFBS_None, // FBCONDA
3701 CEFBS_HasV9, // FBCONDA_V9
3702 CEFBS_HasV9, // FBCOND_V9
3703 CEFBS_HasVIS3, // FCHKSM16
3704 CEFBS_None, // FCMPD
3705 CEFBS_HasV9, // FCMPD_V9
3706 CEFBS_HasVIS, // FCMPEQ16
3707 CEFBS_HasVIS, // FCMPEQ32
3708 CEFBS_HasVIS, // FCMPGT16
3709 CEFBS_HasVIS, // FCMPGT32
3710 CEFBS_HasVIS, // FCMPLE16
3711 CEFBS_HasVIS, // FCMPLE32
3712 CEFBS_HasVIS, // FCMPNE16
3713 CEFBS_HasVIS, // FCMPNE32
3714 CEFBS_None, // FCMPQ
3715 CEFBS_HasV9, // FCMPQ_V9
3716 CEFBS_None, // FCMPS
3717 CEFBS_HasV9, // FCMPS_V9
3718 CEFBS_None, // FDIVD
3719 CEFBS_None, // FDIVQ
3720 CEFBS_None, // FDIVS
3721 CEFBS_None, // FDMULQ
3722 CEFBS_None, // FDTOI
3723 CEFBS_None, // FDTOQ
3724 CEFBS_None, // FDTOS
3725 CEFBS_Is64Bit, // FDTOX
3726 CEFBS_HasVIS, // FEXPAND
3727 CEFBS_HasVIS3, // FHADDD
3728 CEFBS_HasVIS3, // FHADDS
3729 CEFBS_HasVIS3, // FHSUBD
3730 CEFBS_HasVIS3, // FHSUBS
3731 CEFBS_None, // FITOD
3732 CEFBS_None, // FITOQ
3733 CEFBS_None, // FITOS
3734 CEFBS_HasVIS3, // FLCMPD
3735 CEFBS_HasVIS3, // FLCMPS
3736 CEFBS_None, // FLUSH
3737 CEFBS_HasV9, // FLUSHW
3738 CEFBS_None, // FLUSHri
3739 CEFBS_None, // FLUSHrr
3740 CEFBS_HasUA2007, // FMADDD
3741 CEFBS_HasUA2007, // FMADDS
3742 CEFBS_HasVIS3, // FMEAN16
3743 CEFBS_HasV9, // FMOVD
3744 CEFBS_HasV9, // FMOVD_FCC
3745 CEFBS_HasV9, // FMOVD_ICC
3746 CEFBS_Is64Bit, // FMOVD_XCC
3747 CEFBS_HasV9, // FMOVQ
3748 CEFBS_HasV9, // FMOVQ_FCC
3749 CEFBS_HasV9, // FMOVQ_ICC
3750 CEFBS_Is64Bit, // FMOVQ_XCC
3751 CEFBS_Is64Bit, // FMOVRD
3752 CEFBS_None, // FMOVRQ
3753 CEFBS_Is64Bit, // FMOVRS
3754 CEFBS_None, // FMOVS
3755 CEFBS_HasV9, // FMOVS_FCC
3756 CEFBS_HasV9, // FMOVS_ICC
3757 CEFBS_Is64Bit, // FMOVS_XCC
3758 CEFBS_HasUA2007, // FMSUBD
3759 CEFBS_HasUA2007, // FMSUBS
3760 CEFBS_HasVIS, // FMUL8SUX16
3761 CEFBS_HasVIS, // FMUL8ULX16
3762 CEFBS_HasVIS, // FMUL8X16
3763 CEFBS_HasVIS, // FMUL8X16AL
3764 CEFBS_HasVIS, // FMUL8X16AU
3765 CEFBS_None, // FMULD
3766 CEFBS_HasVIS, // FMULD8SUX16
3767 CEFBS_HasVIS, // FMULD8ULX16
3768 CEFBS_None, // FMULQ
3769 CEFBS_None, // FMULS
3770 CEFBS_HasVIS3, // FNADDD
3771 CEFBS_HasVIS3, // FNADDS
3772 CEFBS_HasVIS, // FNAND
3773 CEFBS_HasVIS, // FNANDS
3774 CEFBS_HasV9, // FNEGD
3775 CEFBS_HasV9, // FNEGQ
3776 CEFBS_None, // FNEGS
3777 CEFBS_HasVIS3, // FNHADDD
3778 CEFBS_HasVIS3, // FNHADDS
3779 CEFBS_HasUA2007, // FNMADDD
3780 CEFBS_HasUA2007, // FNMADDS
3781 CEFBS_HasUA2007, // FNMSUBD
3782 CEFBS_HasUA2007, // FNMSUBS
3783 CEFBS_HasVIS3, // FNMULD
3784 CEFBS_HasVIS3, // FNMULS
3785 CEFBS_HasVIS, // FNOR
3786 CEFBS_HasVIS, // FNORS
3787 CEFBS_HasVIS, // FNOT1
3788 CEFBS_HasVIS, // FNOT1S
3789 CEFBS_HasVIS, // FNOT2
3790 CEFBS_HasVIS, // FNOT2S
3791 CEFBS_HasVIS3, // FNSMULD
3792 CEFBS_HasVIS, // FONE
3793 CEFBS_HasVIS, // FONES
3794 CEFBS_HasVIS, // FOR
3795 CEFBS_HasVIS, // FORNOT1
3796 CEFBS_HasVIS, // FORNOT1S
3797 CEFBS_HasVIS, // FORNOT2
3798 CEFBS_HasVIS, // FORNOT2S
3799 CEFBS_HasVIS, // FORS
3800 CEFBS_HasVIS, // FPACK16
3801 CEFBS_HasVIS, // FPACK32
3802 CEFBS_HasVIS, // FPACKFIX
3803 CEFBS_HasVIS, // FPADD16
3804 CEFBS_HasVIS, // FPADD16S
3805 CEFBS_HasVIS, // FPADD32
3806 CEFBS_HasVIS, // FPADD32S
3807 CEFBS_HasVIS3, // FPADD64
3808 CEFBS_HasOSA2011, // FPMADDX
3809 CEFBS_HasOSA2011, // FPMADDXHI
3810 CEFBS_HasVIS, // FPMERGE
3811 CEFBS_HasVIS, // FPSUB16
3812 CEFBS_HasVIS, // FPSUB16S
3813 CEFBS_HasVIS, // FPSUB32
3814 CEFBS_HasVIS, // FPSUB32S
3815 CEFBS_None, // FQTOD
3816 CEFBS_None, // FQTOI
3817 CEFBS_None, // FQTOS
3818 CEFBS_Is64Bit, // FQTOX
3819 CEFBS_HasVIS3, // FSLAS16
3820 CEFBS_HasVIS3, // FSLAS32
3821 CEFBS_HasVIS3, // FSLL16
3822 CEFBS_HasVIS3, // FSLL32
3823 CEFBS_None, // FSMULD
3824 CEFBS_None, // FSQRTD
3825 CEFBS_None, // FSQRTQ
3826 CEFBS_None, // FSQRTS
3827 CEFBS_HasVIS3, // FSRA16
3828 CEFBS_HasVIS3, // FSRA32
3829 CEFBS_HasVIS, // FSRC1
3830 CEFBS_HasVIS, // FSRC1S
3831 CEFBS_HasVIS, // FSRC2
3832 CEFBS_HasVIS, // FSRC2S
3833 CEFBS_HasVIS3, // FSRL16
3834 CEFBS_HasVIS3, // FSRL32
3835 CEFBS_None, // FSTOD
3836 CEFBS_None, // FSTOI
3837 CEFBS_None, // FSTOQ
3838 CEFBS_Is64Bit, // FSTOX
3839 CEFBS_None, // FSUBD
3840 CEFBS_None, // FSUBQ
3841 CEFBS_None, // FSUBS
3842 CEFBS_HasVIS, // FXNOR
3843 CEFBS_HasVIS, // FXNORS
3844 CEFBS_HasVIS, // FXOR
3845 CEFBS_HasVIS, // FXORS
3846 CEFBS_Is64Bit, // FXTOD
3847 CEFBS_Is64Bit, // FXTOQ
3848 CEFBS_Is64Bit, // FXTOS
3849 CEFBS_HasVIS, // FZERO
3850 CEFBS_HasVIS, // FZEROS
3851 CEFBS_Is64Bit, // GDOP_LDXrr
3852 CEFBS_None, // GDOP_LDrr
3853 CEFBS_HasUA2005, // INVALW
3854 CEFBS_None, // JMPLri
3855 CEFBS_None, // JMPLrr
3856 CEFBS_HasV9, // LDAri
3857 CEFBS_None, // LDArr
3858 CEFBS_None, // LDCSRri
3859 CEFBS_None, // LDCSRrr
3860 CEFBS_None, // LDCri
3861 CEFBS_None, // LDCrr
3862 CEFBS_HasV9, // LDDAri
3863 CEFBS_None, // LDDArr
3864 CEFBS_None, // LDDCri
3865 CEFBS_None, // LDDCrr
3866 CEFBS_HasV9, // LDDFAri
3867 CEFBS_HasV9, // LDDFArr
3868 CEFBS_None, // LDDFri
3869 CEFBS_None, // LDDFrr
3870 CEFBS_None, // LDDri
3871 CEFBS_None, // LDDrr
3872 CEFBS_HasV9, // LDFAri
3873 CEFBS_HasV9, // LDFArr
3874 CEFBS_None, // LDFSRri
3875 CEFBS_None, // LDFSRrr
3876 CEFBS_None, // LDFri
3877 CEFBS_None, // LDFrr
3878 CEFBS_HasV9, // LDQFAri
3879 CEFBS_HasV9, // LDQFArr
3880 CEFBS_HasV9, // LDQFri
3881 CEFBS_HasV9, // LDQFrr
3882 CEFBS_HasV9, // LDSBAri
3883 CEFBS_None, // LDSBArr
3884 CEFBS_None, // LDSBri
3885 CEFBS_None, // LDSBrr
3886 CEFBS_HasV9, // LDSHAri
3887 CEFBS_None, // LDSHArr
3888 CEFBS_None, // LDSHri
3889 CEFBS_None, // LDSHrr
3890 CEFBS_HasV9, // LDSTUBAri
3891 CEFBS_None, // LDSTUBArr
3892 CEFBS_None, // LDSTUBri
3893 CEFBS_None, // LDSTUBrr
3894 CEFBS_Is64Bit, // LDSWAri
3895 CEFBS_Is64Bit, // LDSWArr
3896 CEFBS_Is64Bit, // LDSWri
3897 CEFBS_Is64Bit, // LDSWrr
3898 CEFBS_HasV9, // LDUBAri
3899 CEFBS_None, // LDUBArr
3900 CEFBS_None, // LDUBri
3901 CEFBS_None, // LDUBrr
3902 CEFBS_HasV9, // LDUHAri
3903 CEFBS_None, // LDUHArr
3904 CEFBS_None, // LDUHri
3905 CEFBS_None, // LDUHrr
3906 CEFBS_Is64Bit, // LDXAri
3907 CEFBS_Is64Bit, // LDXArr
3908 CEFBS_HasV9, // LDXFSRri
3909 CEFBS_HasV9, // LDXFSRrr
3910 CEFBS_Is64Bit, // LDXri
3911 CEFBS_Is64Bit, // LDXrr
3912 CEFBS_None, // LDri
3913 CEFBS_None, // LDrr
3914 CEFBS_HasVIS3, // LZCNT
3915 CEFBS_HasCrypto, // MD5
3916 CEFBS_HasV9, // MEMBARi
3917 CEFBS_HasCrypto, // MONTMUL
3918 CEFBS_HasCrypto, // MONTSQR
3919 CEFBS_HasVIS3, // MOVDTOX
3920 CEFBS_HasV9, // MOVFCCri
3921 CEFBS_HasV9, // MOVFCCrr
3922 CEFBS_HasV9, // MOVICCri
3923 CEFBS_HasV9, // MOVICCrr
3924 CEFBS_Is64Bit, // MOVRri
3925 CEFBS_Is64Bit, // MOVRrr
3926 CEFBS_HasVIS3, // MOVSTOSW
3927 CEFBS_HasVIS3, // MOVSTOUW
3928 CEFBS_HasVIS3, // MOVWTOS
3929 CEFBS_Is64Bit, // MOVXCCri
3930 CEFBS_Is64Bit, // MOVXCCrr
3931 CEFBS_HasVIS3, // MOVXTOD
3932 CEFBS_HasCrypto, // MPMUL
3933 CEFBS_None, // MULSCCri
3934 CEFBS_None, // MULSCCrr
3935 CEFBS_Is64Bit, // MULXri
3936 CEFBS_Is64Bit, // MULXrr
3937 CEFBS_None, // NOP
3938 CEFBS_HasUA2005, // NORMALW
3939 CEFBS_None, // ORCCri
3940 CEFBS_None, // ORCCrr
3941 CEFBS_None, // ORNCCri
3942 CEFBS_None, // ORNCCrr
3943 CEFBS_None, // ORNri
3944 CEFBS_None, // ORNrr
3945 CEFBS_None, // ORri
3946 CEFBS_None, // ORrr
3947 CEFBS_HasUA2005, // OTHERW
3948 CEFBS_HasVIS, // PDIST
3949 CEFBS_HasVIS3, // PDISTN
3950 CEFBS_HasV9, // POPCrr
3951 CEFBS_HasV9, // PREFETCHAi
3952 CEFBS_HasV9, // PREFETCHAr
3953 CEFBS_HasV9, // PREFETCHi
3954 CEFBS_HasV9, // PREFETCHr
3955 CEFBS_HasPWRPSR, // PWRPSRri
3956 CEFBS_HasPWRPSR, // PWRPSRrr
3957 CEFBS_None, // RDASR
3958 CEFBS_HasV9, // RDFQ
3959 CEFBS_HasV9, // RDPR
3960 CEFBS_None, // RDPSR
3961 CEFBS_None, // RDTBR
3962 CEFBS_None, // RDWIM
3963 CEFBS_HasV9, // RESTORED
3964 CEFBS_None, // RESTOREri
3965 CEFBS_None, // RESTORErr
3966 CEFBS_None, // RET
3967 CEFBS_None, // RETL
3968 CEFBS_HasV9, // RETRY
3969 CEFBS_None, // RETTri
3970 CEFBS_None, // RETTrr
3971 CEFBS_HasV9, // SAVED
3972 CEFBS_None, // SAVEri
3973 CEFBS_None, // SAVErr
3974 CEFBS_None, // SDIVCCri
3975 CEFBS_None, // SDIVCCrr
3976 CEFBS_Is64Bit, // SDIVXri
3977 CEFBS_Is64Bit, // SDIVXrr
3978 CEFBS_None, // SDIVri
3979 CEFBS_None, // SDIVrr
3980 CEFBS_None, // SETHIi
3981 CEFBS_HasCrypto, // SHA1
3982 CEFBS_HasCrypto, // SHA256
3983 CEFBS_HasCrypto, // SHA512
3984 CEFBS_HasVIS, // SHUTDOWN
3985 CEFBS_HasVIS2, // SIAM
3986 CEFBS_HasV9, // SIR
3987 CEFBS_Is64Bit, // SLLXri
3988 CEFBS_Is64Bit, // SLLXrr
3989 CEFBS_None, // SLLri
3990 CEFBS_None, // SLLrr
3991 CEFBS_None, // SMACri
3992 CEFBS_None, // SMACrr
3993 CEFBS_None, // SMULCCri
3994 CEFBS_None, // SMULCCrr
3995 CEFBS_None, // SMULri
3996 CEFBS_None, // SMULrr
3997 CEFBS_Is64Bit, // SRAXri
3998 CEFBS_Is64Bit, // SRAXrr
3999 CEFBS_None, // SRAri
4000 CEFBS_None, // SRArr
4001 CEFBS_Is64Bit, // SRLXri
4002 CEFBS_Is64Bit, // SRLXrr
4003 CEFBS_None, // SRLri
4004 CEFBS_None, // SRLrr
4005 CEFBS_HasV9, // STAri
4006 CEFBS_None, // STArr
4007 CEFBS_None, // STBAR
4008 CEFBS_HasV9, // STBAri
4009 CEFBS_None, // STBArr
4010 CEFBS_None, // STBri
4011 CEFBS_None, // STBrr
4012 CEFBS_None, // STCSRri
4013 CEFBS_None, // STCSRrr
4014 CEFBS_None, // STCri
4015 CEFBS_None, // STCrr
4016 CEFBS_HasV9, // STDAri
4017 CEFBS_None, // STDArr
4018 CEFBS_None, // STDCQri
4019 CEFBS_None, // STDCQrr
4020 CEFBS_None, // STDCri
4021 CEFBS_None, // STDCrr
4022 CEFBS_HasV9, // STDFAri
4023 CEFBS_HasV9, // STDFArr
4024 CEFBS_None, // STDFQri
4025 CEFBS_None, // STDFQrr
4026 CEFBS_None, // STDFri
4027 CEFBS_None, // STDFrr
4028 CEFBS_None, // STDri
4029 CEFBS_None, // STDrr
4030 CEFBS_HasV9, // STFAri
4031 CEFBS_HasV9, // STFArr
4032 CEFBS_None, // STFSRri
4033 CEFBS_None, // STFSRrr
4034 CEFBS_None, // STFri
4035 CEFBS_None, // STFrr
4036 CEFBS_HasV9, // STHAri
4037 CEFBS_None, // STHArr
4038 CEFBS_None, // STHri
4039 CEFBS_None, // STHrr
4040 CEFBS_HasV9, // STQFAri
4041 CEFBS_HasV9, // STQFArr
4042 CEFBS_HasV9, // STQFri
4043 CEFBS_HasV9, // STQFrr
4044 CEFBS_Is64Bit, // STXAri
4045 CEFBS_Is64Bit, // STXArr
4046 CEFBS_HasV9, // STXFSRri
4047 CEFBS_HasV9, // STXFSRrr
4048 CEFBS_Is64Bit, // STXri
4049 CEFBS_Is64Bit, // STXrr
4050 CEFBS_None, // STri
4051 CEFBS_None, // STrr
4052 CEFBS_None, // SUBCCri
4053 CEFBS_None, // SUBCCrr
4054 CEFBS_None, // SUBCri
4055 CEFBS_None, // SUBCrr
4056 CEFBS_None, // SUBEri
4057 CEFBS_None, // SUBErr
4058 CEFBS_None, // SUBri
4059 CEFBS_None, // SUBrr
4060 CEFBS_HasV9, // SWAPAri
4061 CEFBS_None, // SWAPArr
4062 CEFBS_None, // SWAPri
4063 CEFBS_None, // SWAPrr
4064 CEFBS_None, // TA1
4065 CEFBS_None, // TA3
4066 CEFBS_None, // TA5
4067 CEFBS_None, // TADDCCTVri
4068 CEFBS_None, // TADDCCTVrr
4069 CEFBS_None, // TADDCCri
4070 CEFBS_None, // TADDCCrr
4071 CEFBS_None, // TAIL_CALL
4072 CEFBS_None, // TAIL_CALLri
4073 CEFBS_HasV9, // TICCri
4074 CEFBS_HasV9, // TICCrr
4075 CEFBS_None, // TLS_ADDrr
4076 CEFBS_None, // TLS_CALL
4077 CEFBS_Is64Bit, // TLS_LDXrr
4078 CEFBS_None, // TLS_LDrr
4079 CEFBS_None, // TRAPri
4080 CEFBS_None, // TRAPrr
4081 CEFBS_None, // TSUBCCTVri
4082 CEFBS_None, // TSUBCCTVrr
4083 CEFBS_None, // TSUBCCri
4084 CEFBS_None, // TSUBCCrr
4085 CEFBS_Is64Bit, // TXCCri
4086 CEFBS_Is64Bit, // TXCCrr
4087 CEFBS_None, // UDIVCCri
4088 CEFBS_None, // UDIVCCrr
4089 CEFBS_Is64Bit, // UDIVXri
4090 CEFBS_Is64Bit, // UDIVXrr
4091 CEFBS_None, // UDIVri
4092 CEFBS_None, // UDIVrr
4093 CEFBS_None, // UMACri
4094 CEFBS_None, // UMACrr
4095 CEFBS_None, // UMULCCri
4096 CEFBS_None, // UMULCCrr
4097 CEFBS_HasVIS3, // UMULXHI
4098 CEFBS_None, // UMULri
4099 CEFBS_None, // UMULrr
4100 CEFBS_None, // UNIMP
4101 CEFBS_None, // V9FCMPD
4102 CEFBS_None, // V9FCMPED
4103 CEFBS_None, // V9FCMPEQ
4104 CEFBS_None, // V9FCMPES
4105 CEFBS_None, // V9FCMPQ
4106 CEFBS_None, // V9FCMPS
4107 CEFBS_HasV9, // V9FMOVD_FCC
4108 CEFBS_HasV9, // V9FMOVQ_FCC
4109 CEFBS_HasV9, // V9FMOVS_FCC
4110 CEFBS_HasV9, // V9MOVFCCri
4111 CEFBS_HasV9, // V9MOVFCCrr
4112 CEFBS_None, // WRASRri
4113 CEFBS_None, // WRASRrr
4114 CEFBS_HasV9, // WRPRri
4115 CEFBS_HasV9, // WRPRrr
4116 CEFBS_None, // WRPSRri
4117 CEFBS_None, // WRPSRrr
4118 CEFBS_None, // WRTBRri
4119 CEFBS_None, // WRTBRrr
4120 CEFBS_None, // WRWIMri
4121 CEFBS_None, // WRWIMrr
4122 CEFBS_HasVIS3, // XMULX
4123 CEFBS_HasVIS3, // XMULXHI
4124 CEFBS_None, // XNORCCri
4125 CEFBS_None, // XNORCCrr
4126 CEFBS_None, // XNORri
4127 CEFBS_None, // XNORrr
4128 CEFBS_None, // XORCCri
4129 CEFBS_None, // XORCCrr
4130 CEFBS_None, // XORri
4131 CEFBS_None, // XORrr
4132 };
4133
4134 assert(Opcode < 888);
4135 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
4136}
4137
4138
4139} // namespace llvm::Sparc_MC
4140
4141#endif // GET_COMPUTE_FEATURES
4142
4143#ifdef GET_AVAILABLE_OPCODE_CHECKER
4144#undef GET_AVAILABLE_OPCODE_CHECKER
4145
4146namespace llvm::Sparc_MC {
4147
4148bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
4149 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4150 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4151 FeatureBitset MissingFeatures =
4152 (AvailableFeatures & RequiredFeatures) ^
4153 RequiredFeatures;
4154 return !MissingFeatures.any();
4155}
4156
4157} // namespace llvm::Sparc_MC
4158
4159#endif // GET_AVAILABLE_OPCODE_CHECKER
4160
4161#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
4162#undef ENABLE_INSTR_PREDICATE_VERIFIER
4163
4164#include <sstream>
4165
4166namespace llvm::Sparc_MC {
4167
4168#ifndef NDEBUG
4169static const char *SubtargetFeatureNames[] = {
4170 "Feature_HasCASA",
4171 "Feature_HasCrypto",
4172 "Feature_HasOSA2011",
4173 "Feature_HasPWRPSR",
4174 "Feature_HasUA2005",
4175 "Feature_HasUA2007",
4176 "Feature_HasV9",
4177 "Feature_HasVIS",
4178 "Feature_HasVIS2",
4179 "Feature_HasVIS3",
4180 "Feature_Is32Bit",
4181 "Feature_Is64Bit",
4182 "Feature_UseSoftMulDiv",
4183 nullptr
4184};
4185
4186#endif // NDEBUG
4187
4188void verifyInstructionPredicates(
4189 unsigned Opcode, const FeatureBitset &Features) {
4190#ifndef NDEBUG
4191 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4192 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4193 FeatureBitset MissingFeatures =
4194 (AvailableFeatures & RequiredFeatures) ^
4195 RequiredFeatures;
4196 if (MissingFeatures.any()) {
4197 std::ostringstream Msg;
4198 Msg << "Attempting to emit " << &SparcInstrNameData[SparcInstrNameIndices[Opcode]]
4199 << " instruction but the ";
4200 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
4201 if (MissingFeatures.test(i))
4202 Msg << SubtargetFeatureNames[i] << " ";
4203 Msg << "predicate(s) are not met";
4204 report_fatal_error(Msg.str().c_str());
4205 }
4206#endif // NDEBUG
4207}
4208
4209} // namespace llvm::Sparc_MC
4210
4211#endif // ENABLE_INSTR_PREDICATE_VERIFIER
4212
4213