1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::SP {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1530
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543
96 G_INSERT = 81, // GenericOpcodes.td:1552
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1562
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330
114 G_LOAD = 99, // GenericOpcodes.td:1357
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1366
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1374
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1383
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410
121 G_STORE = 106, // GenericOpcodes.td:1418
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1436
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1508
150 G_PREFETCH = 135, // GenericOpcodes.td:1515
151 G_BRCOND = 136, // GenericOpcodes.td:1655
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1664
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687
154 G_INTRINSIC = 139, // GenericOpcodes.td:1607
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:609
183 G_UADDE = 168, // GenericOpcodes.td:617
184 G_USUBO = 169, // GenericOpcodes.td:639
185 G_USUBE = 170, // GenericOpcodes.td:645
186 G_SADDO = 171, // GenericOpcodes.td:624
187 G_SADDE = 172, // GenericOpcodes.td:632
188 G_SSUBO = 173, // GenericOpcodes.td:652
189 G_SSUBE = 174, // GenericOpcodes.td:659
190 G_UMULO = 175, // GenericOpcodes.td:666
191 G_SMULO = 176, // GenericOpcodes.td:674
192 G_UMULH = 177, // GenericOpcodes.td:683
193 G_SMULH = 178, // GenericOpcodes.td:692
194 G_UADDSAT = 179, // GenericOpcodes.td:704
195 G_SADDSAT = 180, // GenericOpcodes.td:712
196 G_USUBSAT = 181, // GenericOpcodes.td:720
197 G_SSUBSAT = 182, // GenericOpcodes.td:728
198 G_USHLSAT = 183, // GenericOpcodes.td:736
199 G_SSHLSAT = 184, // GenericOpcodes.td:744
200 G_SMULFIX = 185, // GenericOpcodes.td:756
201 G_UMULFIX = 186, // GenericOpcodes.td:763
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:773
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:780
204 G_SDIVFIX = 189, // GenericOpcodes.td:791
205 G_UDIVFIX = 190, // GenericOpcodes.td:798
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:808
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:815
208 G_FADD = 193, // GenericOpcodes.td:988
209 G_FSUB = 194, // GenericOpcodes.td:996
210 G_FMUL = 195, // GenericOpcodes.td:1004
211 G_FMA = 196, // GenericOpcodes.td:1013
212 G_FMAD = 197, // GenericOpcodes.td:1022
213 G_FDIV = 198, // GenericOpcodes.td:1030
214 G_FREM = 199, // GenericOpcodes.td:1037
215 G_FMODF = 200, // GenericOpcodes.td:1044
216 G_FPOW = 201, // GenericOpcodes.td:1051
217 G_FPOWI = 202, // GenericOpcodes.td:1058
218 G_FEXP = 203, // GenericOpcodes.td:1065
219 G_FEXP2 = 204, // GenericOpcodes.td:1072
220 G_FEXP10 = 205, // GenericOpcodes.td:1079
221 G_FLOG = 206, // GenericOpcodes.td:1086
222 G_FLOG2 = 207, // GenericOpcodes.td:1093
223 G_FLOG10 = 208, // GenericOpcodes.td:1100
224 G_FLDEXP = 209, // GenericOpcodes.td:1107
225 G_FFREXP = 210, // GenericOpcodes.td:1114
226 G_FNEG = 211, // GenericOpcodes.td:826
227 G_FPEXT = 212, // GenericOpcodes.td:832
228 G_FPTRUNC = 213, // GenericOpcodes.td:838
229 G_FPTOSI = 214, // GenericOpcodes.td:844
230 G_FPTOUI = 215, // GenericOpcodes.td:850
231 G_SITOFP = 216, // GenericOpcodes.td:856
232 G_UITOFP = 217, // GenericOpcodes.td:862
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:868
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:874
235 G_FABS = 220, // GenericOpcodes.td:880
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:886
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:899
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:892
239 G_FMINNUM = 224, // GenericOpcodes.td:912
240 G_FMAXNUM = 225, // GenericOpcodes.td:919
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944
243 G_FMINIMUM = 228, // GenericOpcodes.td:954
244 G_FMAXIMUM = 229, // GenericOpcodes.td:961
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:969
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976
247 G_GET_FPENV = 232, // GenericOpcodes.td:1244
248 G_SET_FPENV = 233, // GenericOpcodes.td:1251
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1258
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1265
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1272
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1279
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1336
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1342
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1645
265 G_BRJT = 250, // GenericOpcodes.td:1675
266 G_VSCALE = 251, // GenericOpcodes.td:1573
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1770
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_FCEIL = 270, // GenericOpcodes.td:1121
286 G_FCOS = 271, // GenericOpcodes.td:1128
287 G_FSIN = 272, // GenericOpcodes.td:1135
288 G_FSINCOS = 273, // GenericOpcodes.td:1142
289 G_FTAN = 274, // GenericOpcodes.td:1149
290 G_FACOS = 275, // GenericOpcodes.td:1156
291 G_FASIN = 276, // GenericOpcodes.td:1163
292 G_FATAN = 277, // GenericOpcodes.td:1170
293 G_FATAN2 = 278, // GenericOpcodes.td:1177
294 G_FCOSH = 279, // GenericOpcodes.td:1184
295 G_FSINH = 280, // GenericOpcodes.td:1191
296 G_FTANH = 281, // GenericOpcodes.td:1198
297 G_FSQRT = 282, // GenericOpcodes.td:1208
298 G_FFLOOR = 283, // GenericOpcodes.td:1215
299 G_FRINT = 284, // GenericOpcodes.td:1222
300 G_FNEARBYINT = 285, // GenericOpcodes.td:1229
301 G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248
302 G_BLOCK_ADDR = 287, // GenericOpcodes.td:254
303 G_JUMP_TABLE = 288, // GenericOpcodes.td:260
304 G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266
305 G_STACKSAVE = 290, // GenericOpcodes.td:272
306 G_STACKRESTORE = 291, // GenericOpcodes.td:278
307 G_STRICT_FADD = 292, // GenericOpcodes.td:1829
308 G_STRICT_FSUB = 293, // GenericOpcodes.td:1830
309 G_STRICT_FMUL = 294, // GenericOpcodes.td:1831
310 G_STRICT_FDIV = 295, // GenericOpcodes.td:1832
311 G_STRICT_FREM = 296, // GenericOpcodes.td:1833
312 G_STRICT_FMA = 297, // GenericOpcodes.td:1834
313 G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835
314 G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836
315 G_STRICT_FCMP = 300, // GenericOpcodes.td:1837
316 G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838
317 G_READ_REGISTER = 302, // GenericOpcodes.td:1694
318 G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704
319 G_MEMCPY = 304, // GenericOpcodes.td:1844
320 G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852
321 G_MEMMOVE = 306, // GenericOpcodes.td:1860
322 G_MEMSET = 307, // GenericOpcodes.td:1868
323 G_BZERO = 308, // GenericOpcodes.td:1875
324 G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882
325 G_TRAP = 310, // GenericOpcodes.td:1892
326 G_DEBUGTRAP = 311, // GenericOpcodes.td:1899
327 G_UBSANTRAP = 312, // GenericOpcodes.td:1905
328 G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793
329 G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799
330 G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805
331 G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806
332 G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808
333 G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809
334 G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810
335 G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811
336 G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812
337 G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813
338 G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815
339 G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816
340 G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817
341 G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818
342 G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819
343 G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820
344 G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821
345 G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822
346 G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823
347 G_SBFX = 332, // GenericOpcodes.td:1917
348 G_UBFX = 333, // GenericOpcodes.td:1925
349 ADJCALLSTACKDOWN = 334, // SparcInstrInfo.td:613
350 ADJCALLSTACKUP = 335, // SparcInstrInfo.td:616
351 GETPCX = 336, // SparcInstrInfo.td:609
352 SELECT_CC_DFP_FCC = 337, // SparcInstrInfo.td:689
353 SELECT_CC_DFP_ICC = 338, // SparcInstrInfo.td:646
354 SELECT_CC_DFP_XCC = 339, // SparcInstrInfo.td:667
355 SELECT_CC_FP_FCC = 340, // SparcInstrInfo.td:685
356 SELECT_CC_FP_ICC = 341, // SparcInstrInfo.td:641
357 SELECT_CC_FP_XCC = 342, // SparcInstrInfo.td:662
358 SELECT_CC_Int_FCC = 343, // SparcInstrInfo.td:680
359 SELECT_CC_Int_ICC = 344, // SparcInstrInfo.td:637
360 SELECT_CC_Int_XCC = 345, // SparcInstrInfo.td:658
361 SELECT_CC_QFP_FCC = 346, // SparcInstrInfo.td:693
362 SELECT_CC_QFP_ICC = 347, // SparcInstrInfo.td:651
363 SELECT_CC_QFP_XCC = 348, // SparcInstrInfo.td:672
364 SET = 349, // SparcInstrAliases.td:562
365 SETSW = 350, // SparcInstrAliases.td:566
366 SETX = 351, // SparcInstrAliases.td:570
367 V8BAR = 352, // SparcInstrInfo.td:605
368 ADDCCri = 353, // SparcInstrInfo.td:502
369 ADDCCrr = 354, // SparcInstrInfo.td:497
370 ADDCri = 355, // SparcInstrInfo.td:516
371 ADDCrr = 356, // SparcInstrInfo.td:512
372 ADDEri = 357, // SparcInstrInfo.td:502
373 ADDErr = 358, // SparcInstrInfo.td:497
374 ADDXC = 359, // SparcInstrVIS.td:185
375 ADDXCCC = 360, // SparcInstrVIS.td:188
376 ADDri = 361, // SparcInstrInfo.td:502
377 ADDrr = 362, // SparcInstrInfo.td:497
378 AES_DROUND01 = 363, // SparcInstrCrypto.td:23
379 AES_DROUND01_LAST = 364, // SparcInstrCrypto.td:27
380 AES_DROUND23 = 365, // SparcInstrCrypto.td:24
381 AES_DROUND23_LAST = 366, // SparcInstrCrypto.td:28
382 AES_EROUND01 = 367, // SparcInstrCrypto.td:21
383 AES_EROUND01_LAST = 368, // SparcInstrCrypto.td:25
384 AES_EROUND23 = 369, // SparcInstrCrypto.td:22
385 AES_EROUND23_LAST = 370, // SparcInstrCrypto.td:26
386 AES_KEXPAND0 = 371, // SparcInstrCrypto.td:29
387 AES_KEXPAND1 = 372, // SparcInstrCrypto.td:32
388 AES_KEXPAND2 = 373, // SparcInstrCrypto.td:33
389 ALIGNADDR = 374, // SparcInstrVIS.td:96
390 ALIGNADDRL = 375, // SparcInstrVIS.td:97
391 ALLCLEAN = 376, // SparcInstrUAOSA.td:39
392 ANDCCri = 377, // SparcInstrInfo.td:516
393 ANDCCrr = 378, // SparcInstrInfo.td:512
394 ANDNCCri = 379, // SparcInstrInfo.td:516
395 ANDNCCrr = 380, // SparcInstrInfo.td:512
396 ANDNri = 381, // SparcInstrInfo.td:874
397 ANDNrr = 382, // SparcInstrInfo.td:870
398 ANDri = 383, // SparcInstrInfo.td:502
399 ANDrr = 384, // SparcInstrInfo.td:497
400 ARRAY16 = 385, // SparcInstrVIS.td:154
401 ARRAY32 = 386, // SparcInstrVIS.td:155
402 ARRAY8 = 387, // SparcInstrVIS.td:153
403 BA = 388, // SparcInstrInfo.td:987
404 BCOND = 389, // SparcInstrInfo.td:1036
405 BCONDA = 390, // SparcInstrInfo.td:1039
406 BINDri = 391, // SparcInstrInfo.td:1029
407 BINDrr = 392, // SparcInstrInfo.td:1025
408 BMASK = 393, // SparcInstrVIS.td:165
409 BPFCC = 394, // SparcInstrInfo.td:1060
410 BPFCCA = 395, // SparcInstrInfo.td:1063
411 BPFCCANT = 396, // SparcInstrInfo.td:1069
412 BPFCCNT = 397, // SparcInstrInfo.td:1066
413 BPICC = 398, // SparcInstrInfo.td:1001
414 BPICCA = 399, // SparcInstrInfo.td:1005
415 BPICCANT = 400, // SparcInstrInfo.td:1013
416 BPICCNT = 401, // SparcInstrInfo.td:1009
417 BPR = 402, // SparcInstr64Bit.td:334
418 BPRA = 403, // SparcInstr64Bit.td:336
419 BPRANT = 404, // SparcInstr64Bit.td:340
420 BPRNT = 405, // SparcInstr64Bit.td:338
421 BPXCC = 406, // SparcInstrInfo.td:1001
422 BPXCCA = 407, // SparcInstrInfo.td:1005
423 BPXCCANT = 408, // SparcInstrInfo.td:1013
424 BPXCCNT = 409, // SparcInstrInfo.td:1009
425 BSHUFFLE = 410, // SparcInstrVIS.td:166
426 CALL = 411, // SparcInstrInfo.td:1122
427 CALLi = 412, // SparcInstrInfo.td:1134
428 CALLri = 413, // SparcInstrInfo.td:1149
429 CALLrii = 414, // SparcInstrInfo.td:1160
430 CALLrr = 415, // SparcInstrInfo.td:1144
431 CALLrri = 416, // SparcInstrInfo.td:1157
432 CAMELLIA_F = 417, // SparcInstrCrypto.td:37
433 CAMELLIA_FL = 418, // SparcInstrCrypto.td:38
434 CAMELLIA_FLI = 419, // SparcInstrCrypto.td:41
435 CASAri = 420, // SparcInstrInfo.td:1822
436 CASArr = 421, // SparcInstrInfo.td:1814
437 CASXAri = 422, // SparcInstr64Bit.td:452
438 CASXArr = 423, // SparcInstr64Bit.td:445
439 CMASK16 = 424, // SparcInstrVIS.td:193
440 CMASK32 = 425, // SparcInstrVIS.td:195
441 CMASK8 = 426, // SparcInstrVIS.td:191
442 CPBCOND = 427, // SparcInstrInfo.td:1112
443 CPBCONDA = 428, // SparcInstrInfo.td:1115
444 CRC32C = 429, // SparcInstrCrypto.td:45
445 CWBCONDri = 430, // SparcInstrUAOSA.td:31
446 CWBCONDrr = 431, // SparcInstrUAOSA.td:28
447 CXBCONDri = 432, // SparcInstrUAOSA.td:31
448 CXBCONDrr = 433, // SparcInstrUAOSA.td:28
449 DES_IIP = 434, // SparcInstrCrypto.td:54
450 DES_IP = 435, // SparcInstrCrypto.td:51
451 DES_KEXPAND = 436, // SparcInstrCrypto.td:58
452 DES_ROUND = 437, // SparcInstrCrypto.td:49
453 DONE = 438, // SparcInstrInfo.td:1876
454 EDGE16 = 439, // SparcInstrVIS.td:146
455 EDGE16L = 440, // SparcInstrVIS.td:147
456 EDGE16LN = 441, // SparcInstrVIS.td:175
457 EDGE16N = 442, // SparcInstrVIS.td:174
458 EDGE32 = 443, // SparcInstrVIS.td:148
459 EDGE32L = 444, // SparcInstrVIS.td:149
460 EDGE32LN = 445, // SparcInstrVIS.td:177
461 EDGE32N = 446, // SparcInstrVIS.td:176
462 EDGE8 = 447, // SparcInstrVIS.td:144
463 EDGE8L = 448, // SparcInstrVIS.td:145
464 EDGE8LN = 449, // SparcInstrVIS.td:173
465 EDGE8N = 450, // SparcInstrVIS.td:172
466 FABSD = 451, // SparcInstrInfo.td:1730
467 FABSQ = 452, // SparcInstrInfo.td:1735
468 FABSS = 453, // SparcInstrInfo.td:1415
469 FADDD = 454, // SparcInstrInfo.td:1450
470 FADDQ = 455, // SparcInstrInfo.td:1455
471 FADDS = 456, // SparcInstrInfo.td:1445
472 FALIGNADATA = 457, // SparcInstrVIS.td:98
473 FAND = 458, // SparcInstrVIS.td:116
474 FANDNOT1 = 459, // SparcInstrVIS.td:129
475 FANDNOT1S = 460, // SparcInstrVIS.td:130
476 FANDNOT2 = 461, // SparcInstrVIS.td:131
477 FANDNOT2S = 462, // SparcInstrVIS.td:132
478 FANDS = 463, // SparcInstrVIS.td:117
479 FBCOND = 464, // SparcInstrInfo.td:1076
480 FBCONDA = 465, // SparcInstrInfo.td:1079
481 FBCONDA_V9 = 466, // SparcInstrInfo.td:1090
482 FBCOND_V9 = 467, // SparcInstrInfo.td:1086
483 FCHKSM16 = 468, // SparcInstrVIS.td:200
484 FCMPD = 469, // SparcInstrInfo.td:1541
485 FCMPD_V9 = 470, // SparcInstrInfo.td:1566
486 FCMPEQ16 = 471, // SparcInstrVIS.td:140
487 FCMPEQ32 = 472, // SparcInstrVIS.td:141
488 FCMPGT16 = 473, // SparcInstrVIS.td:134
489 FCMPGT32 = 474, // SparcInstrVIS.td:135
490 FCMPLE16 = 475, // SparcInstrVIS.td:136
491 FCMPLE32 = 476, // SparcInstrVIS.td:137
492 FCMPNE16 = 477, // SparcInstrVIS.td:138
493 FCMPNE32 = 478, // SparcInstrVIS.td:139
494 FCMPQ = 479, // SparcInstrInfo.td:1546
495 FCMPQ_V9 = 480, // SparcInstrInfo.td:1571
496 FCMPS = 481, // SparcInstrInfo.td:1536
497 FCMPS_V9 = 482, // SparcInstrInfo.td:1561
498 FDIVD = 483, // SparcInstrInfo.td:1517
499 FDIVQ = 484, // SparcInstrInfo.td:1522
500 FDIVS = 485, // SparcInstrInfo.td:1512
501 FDMULQ = 486, // SparcInstrInfo.td:1503
502 FDTOI = 487, // SparcInstrInfo.td:1363
503 FDTOQ = 488, // SparcInstrInfo.td:1390
504 FDTOS = 489, // SparcInstrInfo.td:1385
505 FDTOX = 490, // SparcInstr64Bit.td:408
506 FEXPAND = 491, // SparcInstrVIS.td:72
507 FHADDD = 492, // SparcInstrVIS.td:205
508 FHADDS = 493, // SparcInstrVIS.td:202
509 FHSUBD = 494, // SparcInstrVIS.td:211
510 FHSUBS = 495, // SparcInstrVIS.td:208
511 FITOD = 496, // SparcInstrInfo.td:1346
512 FITOQ = 497, // SparcInstrInfo.td:1351
513 FITOS = 498, // SparcInstrInfo.td:1341
514 FLCMPD = 499, // SparcInstrVIS.td:217
515 FLCMPS = 500, // SparcInstrVIS.td:214
516 FLUSH = 501, // SparcInstrInfo.td:1335
517 FLUSHW = 502, // SparcInstrInfo.td:623
518 FLUSHri = 503, // SparcInstrInfo.td:1328
519 FLUSHrr = 504, // SparcInstrInfo.td:1326
520 FMADDD = 505, // SparcInstrUAOSA.td:49
521 FMADDS = 506, // SparcInstrUAOSA.td:48
522 FMEAN16 = 507, // SparcInstrVIS.td:221
523 FMOVD = 508, // SparcInstrInfo.td:1714
524 FMOVD_FCC = 509, // SparcInstrInfo.td:1697
525 FMOVD_ICC = 510, // SparcInstrInfo.td:1678
526 FMOVD_XCC = 511, // SparcInstr64Bit.td:315
527 FMOVQ = 512, // SparcInstrInfo.td:1718
528 FMOVQ_FCC = 513, // SparcInstrInfo.td:1703
529 FMOVQ_ICC = 514, // SparcInstrInfo.td:1684
530 FMOVQ_XCC = 515, // SparcInstr64Bit.td:321
531 FMOVRD = 516, // SparcInstr64Bit.td:373
532 FMOVRQ = 517, // SparcInstr64Bit.td:378
533 FMOVRS = 518, // SparcInstr64Bit.td:369
534 FMOVS = 519, // SparcInstrInfo.td:1407
535 FMOVS_FCC = 520, // SparcInstrInfo.td:1692
536 FMOVS_ICC = 521, // SparcInstrInfo.td:1673
537 FMOVS_XCC = 522, // SparcInstr64Bit.td:310
538 FMSUBD = 523, // SparcInstrUAOSA.td:51
539 FMSUBS = 524, // SparcInstrUAOSA.td:50
540 FMUL8SUX16 = 525, // SparcInstrVIS.td:87
541 FMUL8ULX16 = 526, // SparcInstrVIS.td:88
542 FMUL8X16 = 527, // SparcInstrVIS.td:78
543 FMUL8X16AL = 528, // SparcInstrVIS.td:84
544 FMUL8X16AU = 529, // SparcInstrVIS.td:81
545 FMULD = 530, // SparcInstrInfo.td:1485
546 FMULD8SUX16 = 531, // SparcInstrVIS.td:89
547 FMULD8ULX16 = 532, // SparcInstrVIS.td:92
548 FMULQ = 533, // SparcInstrInfo.td:1490
549 FMULS = 534, // SparcInstrInfo.td:1479
550 FNADDD = 535, // SparcInstrVIS.td:226
551 FNADDS = 536, // SparcInstrVIS.td:223
552 FNAND = 537, // SparcInstrVIS.td:118
553 FNANDS = 538, // SparcInstrVIS.td:119
554 FNEGD = 539, // SparcInstrInfo.td:1721
555 FNEGQ = 540, // SparcInstrInfo.td:1726
556 FNEGS = 541, // SparcInstrInfo.td:1410
557 FNHADDD = 542, // SparcInstrVIS.td:232
558 FNHADDS = 543, // SparcInstrVIS.td:229
559 FNMADDD = 544, // SparcInstrUAOSA.td:54
560 FNMADDS = 545, // SparcInstrUAOSA.td:53
561 FNMSUBD = 546, // SparcInstrUAOSA.td:56
562 FNMSUBS = 547, // SparcInstrUAOSA.td:55
563 FNMULD = 548, // SparcInstrVIS.td:239
564 FNMULS = 549, // SparcInstrVIS.td:236
565 FNOR = 550, // SparcInstrVIS.td:114
566 FNORS = 551, // SparcInstrVIS.td:115
567 FNOT1 = 552, // SparcInstrVIS.td:108
568 FNOT1S = 553, // SparcInstrVIS.td:109
569 FNOT2 = 554, // SparcInstrVIS.td:110
570 FNOT2S = 555, // SparcInstrVIS.td:111
571 FNSMULD = 556, // SparcInstrVIS.td:242
572 FONE = 557, // SparcInstrVIS.td:102
573 FONES = 558, // SparcInstrVIS.td:103
574 FOR = 559, // SparcInstrVIS.td:112
575 FORNOT1 = 560, // SparcInstrVIS.td:125
576 FORNOT1S = 561, // SparcInstrVIS.td:126
577 FORNOT2 = 562, // SparcInstrVIS.td:127
578 FORNOT2S = 563, // SparcInstrVIS.td:128
579 FORS = 564, // SparcInstrVIS.td:113
580 FPACK16 = 565, // SparcInstrVIS.td:66
581 FPACK32 = 566, // SparcInstrVIS.td:67
582 FPACKFIX = 567, // SparcInstrVIS.td:69
583 FPADD16 = 568, // SparcInstrVIS.td:57
584 FPADD16S = 569, // SparcInstrVIS.td:58
585 FPADD32 = 570, // SparcInstrVIS.td:59
586 FPADD32S = 571, // SparcInstrVIS.td:60
587 FPADD64 = 572, // SparcInstrVIS.td:246
588 FPMADDX = 573, // SparcInstrUAOSA.td:66
589 FPMADDXHI = 574, // SparcInstrUAOSA.td:67
590 FPMERGE = 575, // SparcInstrVIS.td:74
591 FPSUB16 = 576, // SparcInstrVIS.td:61
592 FPSUB16S = 577, // SparcInstrVIS.td:62
593 FPSUB32 = 578, // SparcInstrVIS.td:63
594 FPSUB32S = 579, // SparcInstrVIS.td:64
595 FQTOD = 580, // SparcInstrInfo.td:1400
596 FQTOI = 581, // SparcInstrInfo.td:1368
597 FQTOS = 582, // SparcInstrInfo.td:1395
598 FQTOX = 583, // SparcInstr64Bit.td:413
599 FSLAS16 = 584, // SparcInstrVIS.td:252
600 FSLAS32 = 585, // SparcInstrVIS.td:254
601 FSLL16 = 586, // SparcInstrVIS.td:248
602 FSLL32 = 587, // SparcInstrVIS.td:250
603 FSMULD = 588, // SparcInstrInfo.td:1496
604 FSQRTD = 589, // SparcInstrInfo.td:1431
605 FSQRTQ = 590, // SparcInstrInfo.td:1436
606 FSQRTS = 591, // SparcInstrInfo.td:1426
607 FSRA16 = 592, // SparcInstrVIS.td:253
608 FSRA32 = 593, // SparcInstrVIS.td:255
609 FSRC1 = 594, // SparcInstrVIS.td:104
610 FSRC1S = 595, // SparcInstrVIS.td:105
611 FSRC2 = 596, // SparcInstrVIS.td:106
612 FSRC2S = 597, // SparcInstrVIS.td:107
613 FSRL16 = 598, // SparcInstrVIS.td:249
614 FSRL32 = 599, // SparcInstrVIS.td:251
615 FSTOD = 600, // SparcInstrInfo.td:1375
616 FSTOI = 601, // SparcInstrInfo.td:1358
617 FSTOQ = 602, // SparcInstrInfo.td:1380
618 FSTOX = 603, // SparcInstr64Bit.td:404
619 FSUBD = 604, // SparcInstrInfo.td:1466
620 FSUBQ = 605, // SparcInstrInfo.td:1471
621 FSUBS = 606, // SparcInstrInfo.td:1461
622 FXNOR = 607, // SparcInstrVIS.td:122
623 FXNORS = 608, // SparcInstrVIS.td:123
624 FXOR = 609, // SparcInstrVIS.td:120
625 FXORS = 610, // SparcInstrVIS.td:121
626 FXTOD = 611, // SparcInstr64Bit.td:394
627 FXTOQ = 612, // SparcInstr64Bit.td:399
628 FXTOS = 613, // SparcInstr64Bit.td:390
629 FZERO = 614, // SparcInstrVIS.td:100
630 FZEROS = 615, // SparcInstrVIS.td:101
631 GDOP_LDXrr = 616, // SparcInstr64Bit.td:219
632 GDOP_LDrr = 617, // SparcInstrInfo.td:749
633 INVALW = 618, // SparcInstrUAOSA.td:40
634 JMPLri = 619, // SparcInstrInfo.td:1175
635 JMPLrr = 620, // SparcInstrInfo.td:1170
636 LDAri = 621, // SparcInstrInfo.td:545
637 LDArr = 622, // SparcInstrInfo.td:540
638 LDCSRri = 623, // SparcInstrInfo.td:728
639 LDCSRrr = 624, // SparcInstrInfo.td:726
640 LDCri = 625, // SparcInstrInfo.td:530
641 LDCrr = 626, // SparcInstrInfo.td:525
642 LDDAri = 627, // SparcInstrInfo.td:545
643 LDDArr = 628, // SparcInstrInfo.td:540
644 LDDCri = 629, // SparcInstrInfo.td:530
645 LDDCrr = 630, // SparcInstrInfo.td:525
646 LDDFAri = 631, // SparcInstrInfo.td:545
647 LDDFArr = 632, // SparcInstrInfo.td:540
648 LDDFri = 633, // SparcInstrInfo.td:530
649 LDDFrr = 634, // SparcInstrInfo.td:525
650 LDDri = 635, // SparcInstrInfo.td:530
651 LDDrr = 636, // SparcInstrInfo.td:525
652 LDFAri = 637, // SparcInstrInfo.td:545
653 LDFArr = 638, // SparcInstrInfo.td:540
654 LDFSRri = 639, // SparcInstrInfo.td:737
655 LDFSRrr = 640, // SparcInstrInfo.td:735
656 LDFri = 641, // SparcInstrInfo.td:530
657 LDFrr = 642, // SparcInstrInfo.td:525
658 LDQFAri = 643, // SparcInstrInfo.td:545
659 LDQFArr = 644, // SparcInstrInfo.td:540
660 LDQFri = 645, // SparcInstrInfo.td:530
661 LDQFrr = 646, // SparcInstrInfo.td:525
662 LDSBAri = 647, // SparcInstrInfo.td:545
663 LDSBArr = 648, // SparcInstrInfo.td:540
664 LDSBri = 649, // SparcInstrInfo.td:530
665 LDSBrr = 650, // SparcInstrInfo.td:525
666 LDSHAri = 651, // SparcInstrInfo.td:545
667 LDSHArr = 652, // SparcInstrInfo.td:540
668 LDSHri = 653, // SparcInstrInfo.td:530
669 LDSHrr = 654, // SparcInstrInfo.td:525
670 LDSTUBAri = 655, // SparcInstrInfo.td:828
671 LDSTUBArr = 656, // SparcInstrInfo.td:824
672 LDSTUBri = 657, // SparcInstrInfo.td:822
673 LDSTUBrr = 658, // SparcInstrInfo.td:820
674 LDSWAri = 659, // SparcInstrInfo.td:545
675 LDSWArr = 660, // SparcInstrInfo.td:540
676 LDSWri = 661, // SparcInstrInfo.td:530
677 LDSWrr = 662, // SparcInstrInfo.td:525
678 LDUBAri = 663, // SparcInstrInfo.td:545
679 LDUBArr = 664, // SparcInstrInfo.td:540
680 LDUBri = 665, // SparcInstrInfo.td:530
681 LDUBrr = 666, // SparcInstrInfo.td:525
682 LDUHAri = 667, // SparcInstrInfo.td:545
683 LDUHArr = 668, // SparcInstrInfo.td:540
684 LDUHri = 669, // SparcInstrInfo.td:530
685 LDUHrr = 670, // SparcInstrInfo.td:525
686 LDXAri = 671, // SparcInstrInfo.td:545
687 LDXArr = 672, // SparcInstrInfo.td:540
688 LDXFSRri = 673, // SparcInstrInfo.td:743
689 LDXFSRrr = 674, // SparcInstrInfo.td:741
690 LDXri = 675, // SparcInstrInfo.td:530
691 LDXrr = 676, // SparcInstrInfo.td:525
692 LDri = 677, // SparcInstrInfo.td:530
693 LDrr = 678, // SparcInstrInfo.td:525
694 LZCNT = 679, // SparcInstrVIS.td:258
695 MD5 = 680, // SparcInstrCrypto.td:65
696 MEMBARi = 681, // SparcInstrInfo.td:1804
697 MONTMUL = 682, // SparcInstrCrypto.td:95
698 MONTSQR = 683, // SparcInstrCrypto.td:96
699 MOVDTOX = 684, // SparcInstrVIS.td:266
700 MOVFCCri = 685, // SparcInstrInfo.td:1664
701 MOVFCCrr = 686, // SparcInstrInfo.td:1659
702 MOVICCri = 687, // SparcInstrInfo.td:1650
703 MOVICCrr = 688, // SparcInstrInfo.td:1644
704 MOVRri = 689, // SparcInstr64Bit.td:361
705 MOVRrr = 690, // SparcInstr64Bit.td:356
706 MOVSTOSW = 691, // SparcInstrVIS.td:262
707 MOVSTOUW = 692, // SparcInstrVIS.td:264
708 MOVWTOS = 693, // SparcInstrVIS.td:268
709 MOVXCCri = 694, // SparcInstr64Bit.td:302
710 MOVXCCrr = 695, // SparcInstr64Bit.td:297
711 MOVXTOD = 696, // SparcInstrVIS.td:270
712 MPMUL = 697, // SparcInstrCrypto.td:94
713 MULSCCri = 698, // SparcInstrInfo.td:516
714 MULSCCrr = 699, // SparcInstrInfo.td:512
715 MULXri = 700, // SparcInstrInfo.td:502
716 MULXrr = 701, // SparcInstrInfo.td:497
717 NOP = 702, // SparcInstrInfo.td:865
718 NORMALW = 703, // SparcInstrUAOSA.td:41
719 ORCCri = 704, // SparcInstrInfo.td:516
720 ORCCrr = 705, // SparcInstrInfo.td:512
721 ORNCCri = 706, // SparcInstrInfo.td:516
722 ORNCCrr = 707, // SparcInstrInfo.td:512
723 ORNri = 708, // SparcInstrInfo.td:884
724 ORNrr = 709, // SparcInstrInfo.td:880
725 ORri = 710, // SparcInstrInfo.td:502
726 ORrr = 711, // SparcInstrInfo.td:497
727 OTHERW = 712, // SparcInstrUAOSA.td:42
728 PDIST = 713, // SparcInstrVIS.td:151
729 PDISTN = 714, // SparcInstrVIS.td:274
730 POPCrr = 715, // SparcInstrInfo.td:1797
731 PREFETCHAi = 716, // SparcInstrInfo.td:1900
732 PREFETCHAr = 717, // SparcInstrInfo.td:1896
733 PREFETCHi = 718, // SparcInstrInfo.td:1893
734 PREFETCHr = 719, // SparcInstrInfo.td:1890
735 PWRPSRri = 720, // SparcInstrInfo.td:1857
736 PWRPSRrr = 721, // SparcInstrInfo.td:1854
737 RDASR = 722, // SparcInstrInfo.td:1254
738 RDFQ = 723, // SparcInstrInfo.td:1919
739 RDPR = 724, // SparcInstrInfo.td:1910
740 RDPSR = 725, // SparcInstrInfo.td:1261
741 RDTBR = 726, // SparcInstrInfo.td:1271
742 RDWIM = 727, // SparcInstrInfo.td:1266
743 RESTORED = 728, // SparcInstrInfo.td:1885
744 RESTOREri = 729, // SparcInstrInfo.td:516
745 RESTORErr = 730, // SparcInstrInfo.td:512
746 RET = 731, // SparcInstrInfo.td:1194
747 RETL = 732, // SparcInstrInfo.td:1187
748 RETRY = 733, // SparcInstrInfo.td:1879
749 RETTri = 734, // SparcInstrInfo.td:1209
750 RETTrr = 735, // SparcInstrInfo.td:1204
751 SAVED = 736, // SparcInstrInfo.td:1882
752 SAVEri = 737, // SparcInstrInfo.td:516
753 SAVErr = 738, // SparcInstrInfo.td:512
754 SDIVCCri = 739, // SparcInstrInfo.td:516
755 SDIVCCrr = 740, // SparcInstrInfo.td:512
756 SDIVXri = 741, // SparcInstrInfo.td:502
757 SDIVXrr = 742, // SparcInstrInfo.td:497
758 SDIVri = 743, // SparcInstrInfo.td:516
759 SDIVrr = 744, // SparcInstrInfo.td:512
760 SETHIi = 745, // SparcInstrInfo.td:856
761 SHA1 = 746, // SparcInstrCrypto.td:68
762 SHA256 = 747, // SparcInstrCrypto.td:71
763 SHA512 = 748, // SparcInstrCrypto.td:75
764 SHUTDOWN = 749, // SparcInstrVIS.td:157
765 SIAM = 750, // SparcInstrVIS.td:169
766 SIR = 751, // SparcInstrInfo.td:1808
767 SLLXri = 752, // SparcInstrFormats.td:299
768 SLLXrr = 753, // SparcInstrFormats.td:295
769 SLLri = 754, // SparcInstrFormats.td:299
770 SLLrr = 755, // SparcInstrFormats.td:295
771 SMACri = 756, // SparcInstrInfo.td:1835
772 SMACrr = 757, // SparcInstrInfo.td:1830
773 SMULCCri = 758, // SparcInstrInfo.td:516
774 SMULCCrr = 759, // SparcInstrInfo.td:512
775 SMULri = 760, // SparcInstrInfo.td:502
776 SMULrr = 761, // SparcInstrInfo.td:497
777 SRAXri = 762, // SparcInstrFormats.td:299
778 SRAXrr = 763, // SparcInstrFormats.td:295
779 SRAri = 764, // SparcInstrFormats.td:299
780 SRArr = 765, // SparcInstrFormats.td:295
781 SRLXri = 766, // SparcInstrFormats.td:299
782 SRLXrr = 767, // SparcInstrFormats.td:295
783 SRLri = 768, // SparcInstrFormats.td:299
784 SRLrr = 769, // SparcInstrFormats.td:295
785 STAri = 770, // SparcInstrInfo.td:581
786 STArr = 771, // SparcInstrInfo.td:575
787 STBAR = 772, // SparcInstrInfo.td:1316
788 STBAri = 773, // SparcInstrInfo.td:581
789 STBArr = 774, // SparcInstrInfo.td:575
790 STBri = 775, // SparcInstrInfo.td:566
791 STBrr = 776, // SparcInstrInfo.td:561
792 STCSRri = 777, // SparcInstrInfo.td:784
793 STCSRrr = 778, // SparcInstrInfo.td:782
794 STCri = 779, // SparcInstrInfo.td:566
795 STCrr = 780, // SparcInstrInfo.td:561
796 STDAri = 781, // SparcInstrInfo.td:581
797 STDArr = 782, // SparcInstrInfo.td:575
798 STDCQri = 783, // SparcInstrInfo.td:790
799 STDCQrr = 784, // SparcInstrInfo.td:788
800 STDCri = 785, // SparcInstrInfo.td:566
801 STDCrr = 786, // SparcInstrInfo.td:561
802 STDFAri = 787, // SparcInstrInfo.td:581
803 STDFArr = 788, // SparcInstrInfo.td:575
804 STDFQri = 789, // SparcInstrInfo.td:805
805 STDFQrr = 790, // SparcInstrInfo.td:803
806 STDFri = 791, // SparcInstrInfo.td:566
807 STDFrr = 792, // SparcInstrInfo.td:561
808 STDri = 793, // SparcInstrInfo.td:566
809 STDrr = 794, // SparcInstrInfo.td:561
810 STFAri = 795, // SparcInstrInfo.td:581
811 STFArr = 796, // SparcInstrInfo.td:575
812 STFSRri = 797, // SparcInstrInfo.td:799
813 STFSRrr = 798, // SparcInstrInfo.td:797
814 STFri = 799, // SparcInstrInfo.td:566
815 STFrr = 800, // SparcInstrInfo.td:561
816 STHAri = 801, // SparcInstrInfo.td:581
817 STHArr = 802, // SparcInstrInfo.td:575
818 STHri = 803, // SparcInstrInfo.td:566
819 STHrr = 804, // SparcInstrInfo.td:561
820 STQFAri = 805, // SparcInstrInfo.td:581
821 STQFArr = 806, // SparcInstrInfo.td:575
822 STQFri = 807, // SparcInstrInfo.td:566
823 STQFrr = 808, // SparcInstrInfo.td:561
824 STXAri = 809, // SparcInstrInfo.td:581
825 STXArr = 810, // SparcInstrInfo.td:575
826 STXFSRri = 811, // SparcInstrInfo.td:812
827 STXFSRrr = 812, // SparcInstrInfo.td:810
828 STXri = 813, // SparcInstrInfo.td:566
829 STXrr = 814, // SparcInstrInfo.td:561
830 STri = 815, // SparcInstrInfo.td:566
831 STrr = 816, // SparcInstrInfo.td:561
832 SUBCCri = 817, // SparcInstrInfo.td:502
833 SUBCCrr = 818, // SparcInstrInfo.td:497
834 SUBCri = 819, // SparcInstrInfo.td:516
835 SUBCrr = 820, // SparcInstrInfo.td:512
836 SUBEri = 821, // SparcInstrInfo.td:502
837 SUBErr = 822, // SparcInstrInfo.td:497
838 SUBri = 823, // SparcInstrInfo.td:502
839 SUBrr = 824, // SparcInstrInfo.td:497
840 SWAPAri = 825, // SparcInstrInfo.td:848
841 SWAPArr = 826, // SparcInstrInfo.td:843
842 SWAPri = 827, // SparcInstrInfo.td:839
843 SWAPrr = 828, // SparcInstrInfo.td:835
844 TA1 = 829, // SparcInstrInfo.td:1250
845 TA3 = 830, // SparcInstrInfo.td:627
846 TA5 = 831, // SparcInstrInfo.td:1247
847 TADDCCTVri = 832, // SparcInstrInfo.td:516
848 TADDCCTVrr = 833, // SparcInstrInfo.td:512
849 TADDCCri = 834, // SparcInstrInfo.td:516
850 TADDCCrr = 835, // SparcInstrInfo.td:512
851 TAIL_CALL = 836, // SparcInstrInfo.td:1616
852 TAIL_CALLri = 837, // SparcInstrInfo.td:1630
853 TICCri = 838, // SparcInstrInfo.td:1236
854 TICCrr = 839, // SparcInstrInfo.td:1232
855 TLS_ADDrr = 840, // SparcInstrInfo.td:1582
856 TLS_CALL = 841, // SparcInstrInfo.td:1599
857 TLS_LDXrr = 842, // SparcInstr64Bit.td:213
858 TLS_LDrr = 843, // SparcInstrInfo.td:1590
859 TRAPri = 844, // SparcInstrInfo.td:1225
860 TRAPrr = 845, // SparcInstrInfo.td:1221
861 TSUBCCTVri = 846, // SparcInstrInfo.td:516
862 TSUBCCTVrr = 847, // SparcInstrInfo.td:512
863 TSUBCCri = 848, // SparcInstrInfo.td:516
864 TSUBCCrr = 849, // SparcInstrInfo.td:512
865 TXCCri = 850, // SparcInstrInfo.td:1236
866 TXCCrr = 851, // SparcInstrInfo.td:1232
867 UDIVCCri = 852, // SparcInstrInfo.td:516
868 UDIVCCrr = 853, // SparcInstrInfo.td:512
869 UDIVXri = 854, // SparcInstrInfo.td:502
870 UDIVXrr = 855, // SparcInstrInfo.td:497
871 UDIVri = 856, // SparcInstrInfo.td:516
872 UDIVrr = 857, // SparcInstrInfo.td:512
873 UMACri = 858, // SparcInstrInfo.td:1845
874 UMACrr = 859, // SparcInstrInfo.td:1840
875 UMULCCri = 860, // SparcInstrInfo.td:516
876 UMULCCrr = 861, // SparcInstrInfo.td:512
877 UMULXHI = 862, // SparcInstrVIS.td:276
878 UMULri = 863, // SparcInstrInfo.td:502
879 UMULrr = 864, // SparcInstrInfo.td:497
880 UNIMP = 865, // SparcInstrInfo.td:1321
881 V9FCMPD = 866, // SparcInstrInfo.td:1745
882 V9FCMPED = 867, // SparcInstrInfo.td:1757
883 V9FCMPEQ = 868, // SparcInstrInfo.td:1760
884 V9FCMPES = 869, // SparcInstrInfo.td:1754
885 V9FCMPQ = 870, // SparcInstrInfo.td:1748
886 V9FCMPS = 871, // SparcInstrInfo.td:1742
887 V9FMOVD_FCC = 872, // SparcInstrInfo.td:1781
888 V9FMOVQ_FCC = 873, // SparcInstrInfo.td:1786
889 V9FMOVS_FCC = 874, // SparcInstrInfo.td:1777
890 V9MOVFCCri = 875, // SparcInstrInfo.td:1773
891 V9MOVFCCrr = 876, // SparcInstrInfo.td:1769
892 WRASRri = 877, // SparcInstrInfo.td:1280
893 WRASRrr = 878, // SparcInstrInfo.td:1277
894 WRPRri = 879, // SparcInstrInfo.td:1929
895 WRPRrr = 880, // SparcInstrInfo.td:1926
896 WRPSRri = 881, // SparcInstrInfo.td:1290
897 WRPSRrr = 882, // SparcInstrInfo.td:1287
898 WRTBRri = 883, // SparcInstrInfo.td:1308
899 WRTBRrr = 884, // SparcInstrInfo.td:1305
900 WRWIMri = 885, // SparcInstrInfo.td:1299
901 WRWIMrr = 886, // SparcInstrInfo.td:1296
902 XMULX = 887, // SparcInstrVIS.td:277
903 XMULXHI = 888, // SparcInstrVIS.td:278
904 XNORCCri = 889, // SparcInstrInfo.td:516
905 XNORCCrr = 890, // SparcInstrInfo.td:512
906 XNORri = 891, // SparcInstrInfo.td:893
907 XNORrr = 892, // SparcInstrInfo.td:889
908 XORCCri = 893, // SparcInstrInfo.td:516
909 XORCCrr = 894, // SparcInstrInfo.td:512
910 XORri = 895, // SparcInstrInfo.td:502
911 XORrr = 896, // SparcInstrInfo.td:497
912 INSTRUCTION_LIST_END = 897
913 };
914 enum RegClassByHwModeUses : uint16_t {
915 sparc_ptr_rc,
916 };
917
918} // namespace llvm::SP
919
920#endif // GET_INSTRINFO_ENUM
921
922#ifdef GET_INSTRINFO_SCHED_ENUM
923#undef GET_INSTRINFO_SCHED_ENUM
924
925namespace llvm::SP::Sched {
926
927 enum {
928 NoInstrModel = 0,
929 IIC_iu_instr = 1,
930 IIC_fpu_normal_instr = 2,
931 IIC_jmp_or_call = 3,
932 IIC_fpu_abs = 4,
933 IIC_fpu_fast_instr = 5,
934 IIC_fpu_divd = 6,
935 IIC_fpu_divs = 7,
936 IIC_fpu_muld = 8,
937 IIC_fpu_muls = 9,
938 IIC_fpu_negs = 10,
939 IIC_fpu_sqrtd = 11,
940 IIC_fpu_sqrts = 12,
941 IIC_fpu_stod = 13,
942 IIC_ldd = 14,
943 IIC_iu_or_fpu_instr = 15,
944 IIC_iu_div = 16,
945 IIC_smac_umac = 17,
946 IIC_iu_smul = 18,
947 IIC_st = 19,
948 IIC_std = 20,
949 IIC_iu_umul = 21,
950 SCHED_LIST_END = 22
951 };
952
953} // namespace llvm::SP::Sched
954
955#endif // GET_INSTRINFO_SCHED_ENUM
956
957#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
958
959namespace llvm {
960
961struct SparcInstrTable {
962 MCInstrDesc Insts[897];
963 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
964 MCPhysReg ImplicitOps[218];
965 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
966 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
967 MCOperandInfo OperandInfo[575];
968};
969} // namespace llvm
970
971#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
972
973#ifdef GET_INSTRINFO_MC_DESC
974#undef GET_INSTRINFO_MC_DESC
975
976namespace llvm {
977
978static_assert((sizeof SparcInstrTable::ImplicitOps + sizeof SparcInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
979static constexpr unsigned SparcOpInfoBase = (sizeof SparcInstrTable::ImplicitOps + sizeof SparcInstrTable::Padding) / sizeof(MCOperandInfo);
980
981extern const SparcInstrTable SparcDescs = {
982 {
983 { 896, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // XORrr
984 { 895, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // XORri
985 { 894, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XORCCrr
986 { 893, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XORCCri
987 { 892, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // XNORrr
988 { 891, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XNORri
989 { 890, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XNORCCrr
990 { 889, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XNORCCri
991 { 888, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XMULXHI
992 { 887, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // XMULX
993 { 886, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 417, 141, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRWIMrr
994 { 885, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 167, 141, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRWIMri
995 { 884, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 417, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRTBRrr
996 { 883, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 167, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRTBRri
997 { 882, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 417, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPSRrr
998 { 881, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 167, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPSRri
999 { 880, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 572, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPRrr
1000 { 879, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 569, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRPRri
1001 { 878, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 566, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRASRrr
1002 { 877, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 563, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WRASRri
1003 { 876, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 558, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9MOVFCCrr
1004 { 875, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 553, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9MOVFCCri
1005 { 874, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 548, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FMOVS_FCC
1006 { 873, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 543, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FMOVQ_FCC
1007 { 872, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 538, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FMOVD_FCC
1008 { 871, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 268, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPS
1009 { 870, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 535, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPQ
1010 { 869, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 268, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPES
1011 { 868, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 535, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPEQ
1012 { 867, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 265, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPED
1013 { 866, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 265, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V9FCMPD
1014 { 865, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UNIMP
1015 { 864, 3, 1, 4, 21, 0, 1, SparcOpInfoBase + 175, 215, 0, 0x0ULL }, // UMULrr
1016 { 863, 3, 1, 4, 21, 0, 1, SparcOpInfoBase + 172, 215, 0, 0x0ULL }, // UMULri
1017 { 862, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0, 0x0ULL }, // UMULXHI
1018 { 861, 3, 1, 4, 21, 0, 2, SparcOpInfoBase + 175, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMULCCrr
1019 { 860, 3, 1, 4, 21, 0, 2, SparcOpInfoBase + 172, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMULCCri
1020 { 859, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 175, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMACrr
1021 { 858, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 172, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UMACri
1022 { 857, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 175, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVrr
1023 { 856, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 172, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVri
1024 { 855, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVXrr
1025 { 854, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 414, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVXri
1026 { 853, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 175, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVCCrr
1027 { 852, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 172, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // UDIVCCri
1028 { 851, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 440, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TXCCrr
1029 { 850, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 528, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TXCCri
1030 { 849, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCrr
1031 { 848, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCri
1032 { 847, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCTVrr
1033 { 846, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TSUBCCTVri
1034 { 845, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 440, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAPrr
1035 { 844, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 528, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TRAPri
1036 { 843, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // TLS_LDrr
1037 { 842, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // TLS_LDXrr
1038 { 841, 2, 0, 4, 3, 1, 0, SparcOpInfoBase + 189, 217, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // TLS_CALL
1039 { 840, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 531, 0, 0, 0x0ULL }, // TLS_ADDrr
1040 { 839, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 440, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TICCrr
1041 { 838, 3, 0, 4, 0, 1, 0, SparcOpInfoBase + 528, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TICCri
1042 { 837, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 191, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // TAIL_CALLri
1043 { 836, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 188, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // TAIL_CALL
1044 { 835, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCrr
1045 { 834, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCri
1046 { 833, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCTVrr
1047 { 832, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TADDCCTVri
1048 { 831, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TA5
1049 { 830, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TA3
1050 { 829, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TA1
1051 { 828, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 524, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // SWAPrr
1052 { 827, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 515, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // SWAPri
1053 { 826, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 519, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWAPArr
1054 { 825, 4, 1, 4, 1, 1, 0, SparcOpInfoBase + 515, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SWAPAri
1055 { 824, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // SUBrr
1056 { 823, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // SUBri
1057 { 822, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 175, 5, 0, 0x0ULL }, // SUBErr
1058 { 821, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 172, 5, 0, 0x0ULL }, // SUBEri
1059 { 820, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SUBCrr
1060 { 819, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SUBCri
1061 { 818, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBCCrr
1062 { 817, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBCCri
1063 { 816, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 450, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STrr
1064 { 815, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 443, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STri
1065 { 814, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 512, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STXrr
1066 { 813, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 505, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STXri
1067 { 812, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 193, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXFSRrr
1068 { 811, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 191, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXFSRri
1069 { 810, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 508, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STXArr
1070 { 809, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 505, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STXAri
1071 { 808, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 502, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STQFrr
1072 { 807, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 495, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STQFri
1073 { 806, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 498, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STQFArr
1074 { 805, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 495, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STQFAri
1075 { 804, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 450, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STHrr
1076 { 803, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 443, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STHri
1077 { 802, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 446, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STHArr
1078 { 801, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 443, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STHAri
1079 { 800, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 492, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STFrr
1080 { 799, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 485, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STFri
1081 { 798, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 193, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFSRrr
1082 { 797, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 191, 11, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFSRri
1083 { 796, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 488, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFArr
1084 { 795, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 485, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STFAri
1085 { 794, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 482, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDrr
1086 { 793, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 459, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDri
1087 { 792, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 479, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDFrr
1088 { 791, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 472, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDFri
1089 { 790, 2, 0, 4, 20, 0, 1, SparcOpInfoBase + 193, 139, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFQrr
1090 { 789, 2, 0, 4, 20, 0, 1, SparcOpInfoBase + 191, 139, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFQri
1091 { 788, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 475, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFArr
1092 { 787, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 472, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDFAri
1093 { 786, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 469, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDCrr
1094 { 785, 3, 0, 4, 20, 0, 0, SparcOpInfoBase + 466, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STDCri
1095 { 784, 2, 0, 4, 20, 1, 0, SparcOpInfoBase + 193, 216, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDCQrr
1096 { 783, 2, 0, 4, 20, 1, 0, SparcOpInfoBase + 191, 216, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDCQri
1097 { 782, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 462, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDArr
1098 { 781, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 459, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STDAri
1099 { 780, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 456, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STCrr
1100 { 779, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 453, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STCri
1101 { 778, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 193, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STCSRrr
1102 { 777, 2, 0, 4, 19, 1, 0, SparcOpInfoBase + 191, 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STCSRri
1103 { 776, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 450, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STBrr
1104 { 775, 3, 0, 4, 19, 0, 0, SparcOpInfoBase + 443, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STBri
1105 { 774, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 446, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STBArr
1106 { 773, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 443, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STBAri
1107 { 772, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STBAR
1108 { 771, 4, 0, 4, 19, 0, 0, SparcOpInfoBase + 446, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // STArr
1109 { 770, 3, 0, 4, 19, 1, 0, SparcOpInfoBase + 443, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STAri
1110 { 769, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // SRLrr
1111 { 768, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 440, 0, 0, 0x0ULL }, // SRLri
1112 { 767, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 437, 0, 0, 0x0ULL }, // SRLXrr
1113 { 766, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 434, 0, 0, 0x0ULL }, // SRLXri
1114 { 765, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // SRArr
1115 { 764, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 440, 0, 0, 0x0ULL }, // SRAri
1116 { 763, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 437, 0, 0, 0x0ULL }, // SRAXrr
1117 { 762, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 434, 0, 0, 0x0ULL }, // SRAXri
1118 { 761, 3, 1, 4, 18, 0, 1, SparcOpInfoBase + 175, 215, 0, 0x0ULL }, // SMULrr
1119 { 760, 3, 1, 4, 18, 0, 1, SparcOpInfoBase + 172, 215, 0, 0x0ULL }, // SMULri
1120 { 759, 3, 1, 4, 18, 0, 2, SparcOpInfoBase + 175, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMULCCrr
1121 { 758, 3, 1, 4, 18, 0, 2, SparcOpInfoBase + 172, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMULCCri
1122 { 757, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 175, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMACrr
1123 { 756, 3, 1, 4, 17, 2, 2, SparcOpInfoBase + 172, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SMACri
1124 { 755, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // SLLrr
1125 { 754, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 440, 0, 0, 0x0ULL }, // SLLri
1126 { 753, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 437, 0, 0, 0x0ULL }, // SLLXrr
1127 { 752, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 434, 0, 0, 0x0ULL }, // SLLXri
1128 { 751, 1, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SIR
1129 { 750, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SIAM
1130 { 749, 0, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHUTDOWN
1131 { 748, 0, 0, 4, 0, 24, 8, SparcOpInfoBase + 1, 177, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHA512
1132 { 747, 0, 0, 4, 0, 12, 4, SparcOpInfoBase + 1, 161, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHA256
1133 { 746, 0, 0, 4, 0, 11, 3, SparcOpInfoBase + 1, 147, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SHA1
1134 { 745, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 167, 0, 0, 0x0ULL }, // SETHIi
1135 { 744, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 175, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVrr
1136 { 743, 3, 1, 4, 16, 1, 1, SparcOpInfoBase + 172, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVri
1137 { 742, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVXrr
1138 { 741, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 414, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVXri
1139 { 740, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 175, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVCCrr
1140 { 739, 3, 1, 4, 16, 1, 2, SparcOpInfoBase + 172, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SDIVCCri
1141 { 738, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SAVErr
1142 { 737, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SAVEri
1143 { 736, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SAVED
1144 { 735, 2, 0, 4, 3, 0, 0, SparcOpInfoBase + 193, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RETTrr
1145 { 734, 2, 0, 4, 3, 0, 0, SparcOpInfoBase + 191, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RETTri
1146 { 733, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RETRY
1147 { 732, 1, 0, 4, 3, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // RETL
1148 { 731, 1, 0, 4, 3, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RET
1149 { 730, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RESTORErr
1150 { 729, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RESTOREri
1151 { 728, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RESTORED
1152 { 727, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 431, 141, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDWIM
1153 { 726, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 431, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDTBR
1154 { 725, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 431, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDPSR
1155 { 724, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 432, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDPR
1156 { 723, 1, 1, 4, 1, 1, 0, SparcOpInfoBase + 431, 139, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDFQ
1157 { 722, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 429, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RDASR
1158 { 721, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 417, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PWRPSRrr
1159 { 720, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 167, 138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PWRPSRri
1160 { 719, 3, 0, 4, 1, 0, 0, SparcOpInfoBase + 426, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHr
1161 { 718, 3, 0, 4, 1, 0, 0, SparcOpInfoBase + 419, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHi
1162 { 717, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 422, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHAr
1163 { 716, 3, 0, 4, 1, 1, 0, SparcOpInfoBase + 419, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREFETCHAi
1164 { 715, 2, 1, 4, 1, 0, 0, SparcOpInfoBase + 417, 0, 0, 0x0ULL }, // POPCrr
1165 { 714, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PDISTN
1166 { 713, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PDIST
1167 { 712, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // OTHERW
1168 { 711, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ORrr
1169 { 710, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // ORri
1170 { 709, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ORNrr
1171 { 708, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORNri
1172 { 707, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORNCCrr
1173 { 706, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORNCCri
1174 { 705, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORCCrr
1175 { 704, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ORCCri
1176 { 703, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NORMALW
1177 { 702, 0, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // NOP
1178 { 701, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 178, 0, 0, 0x0ULL }, // MULXrr
1179 { 700, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 414, 0, 0, 0x0ULL }, // MULXri
1180 { 699, 3, 1, 4, 1, 2, 2, SparcOpInfoBase + 175, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULSCCrr
1181 { 698, 3, 1, 4, 1, 2, 2, SparcOpInfoBase + 172, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MULSCCri
1182 { 697, 1, 0, 4, 0, 52, 52, SparcOpInfoBase + 1, 30, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MPMUL
1183 { 696, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 412, 0, 0, 0x0ULL }, // MOVXTOD
1184 { 695, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 394, 4, 0, 0x0ULL }, // MOVXCCrr
1185 { 694, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 390, 4, 0, 0x0ULL }, // MOVXCCri
1186 { 693, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 410, 0, 0, 0x0ULL }, // MOVWTOS
1187 { 692, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 408, 0, 0, 0x0ULL }, // MOVSTOUW
1188 { 691, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 408, 0, 0, 0x0ULL }, // MOVSTOSW
1189 { 690, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 403, 0, 0, 0x0ULL }, // MOVRrr
1190 { 689, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 398, 0, 0, 0x0ULL }, // MOVRri
1191 { 688, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 394, 4, 0, 0x0ULL }, // MOVICCrr
1192 { 687, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 390, 4, 0, 0x0ULL }, // MOVICCri
1193 { 686, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 394, 3, 0, 0x0ULL }, // MOVFCCrr
1194 { 685, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 390, 3, 0, 0x0ULL }, // MOVFCCri
1195 { 684, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 388, 0, 0, 0x0ULL }, // MOVDTOX
1196 { 683, 1, 0, 4, 0, 52, 52, SparcOpInfoBase + 1, 30, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MONTSQR
1197 { 682, 1, 0, 4, 0, 52, 52, SparcOpInfoBase + 1, 30, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MONTMUL
1198 { 681, 1, 0, 4, 1, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARi
1199 { 680, 0, 0, 4, 0, 10, 8, SparcOpInfoBase + 1, 12, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MD5
1200 { 679, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 386, 0, 0, 0x0ULL }, // LZCNT
1201 { 678, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDrr
1202 { 677, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDri
1203 { 676, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 383, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDXrr
1204 { 675, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 380, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDXri
1205 { 674, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 193, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXFSRrr
1206 { 673, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 191, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXFSRri
1207 { 672, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 314, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDXArr
1208 { 671, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 380, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDXAri
1209 { 670, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUHrr
1210 { 669, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUHri
1211 { 668, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUHArr
1212 { 667, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUHAri
1213 { 666, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUBrr
1214 { 665, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDUBri
1215 { 664, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUBArr
1216 { 663, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDUBAri
1217 { 662, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 383, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSWrr
1218 { 661, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 380, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSWri
1219 { 660, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 314, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSWArr
1220 { 659, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 380, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSWAri
1221 { 658, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBrr
1222 { 657, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBri
1223 { 656, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBArr
1224 { 655, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSTUBAri
1225 { 654, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSHrr
1226 { 653, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSHri
1227 { 652, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSHArr
1228 { 651, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSHAri
1229 { 650, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSBrr
1230 { 649, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDSBri
1231 { 648, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSBArr
1232 { 647, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDSBAri
1233 { 646, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 377, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDQFrr
1234 { 645, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 370, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDQFri
1235 { 644, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 373, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDQFArr
1236 { 643, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 370, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDQFAri
1237 { 642, 3, 1, 4, 15, 0, 0, SparcOpInfoBase + 367, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDFrr
1238 { 641, 3, 1, 4, 15, 0, 0, SparcOpInfoBase + 360, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDFri
1239 { 640, 2, 0, 4, 15, 0, 1, SparcOpInfoBase + 193, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFSRrr
1240 { 639, 2, 0, 4, 15, 0, 1, SparcOpInfoBase + 191, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFSRri
1241 { 638, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 363, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFArr
1242 { 637, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 360, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDFAri
1243 { 636, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 357, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDrr
1244 { 635, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 334, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDri
1245 { 634, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 354, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDFrr
1246 { 633, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 347, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDFri
1247 { 632, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 350, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDFArr
1248 { 631, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 347, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDFAri
1249 { 630, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 344, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDCrr
1250 { 629, 3, 1, 4, 14, 0, 0, SparcOpInfoBase + 341, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDDCri
1251 { 628, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 337, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDArr
1252 { 627, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 334, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDDAri
1253 { 626, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 331, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDCrr
1254 { 625, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 328, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDCri
1255 { 624, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 193, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDCSRrr
1256 { 623, 2, 0, 4, 1, 0, 1, SparcOpInfoBase + 191, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDCSRri
1257 { 622, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // LDArr
1258 { 621, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 322, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDAri
1259 { 620, 3, 1, 4, 3, 0, 0, SparcOpInfoBase + 325, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JMPLrr
1260 { 619, 3, 1, 4, 3, 0, 0, SparcOpInfoBase + 322, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JMPLri
1261 { 618, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INVALW
1262 { 617, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 318, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // GDOP_LDrr
1263 { 616, 4, 1, 4, 1, 0, 0, SparcOpInfoBase + 314, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // GDOP_LDXrr
1264 { 615, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0, 0x0ULL }, // FZEROS
1265 { 614, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 308, 0, 0, 0x0ULL }, // FZERO
1266 { 613, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 257, 0, 0, 0x0ULL }, // FXTOS
1267 { 612, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 259, 0, 0, 0x0ULL }, // FXTOQ
1268 { 611, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FXTOD
1269 { 610, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXORS
1270 { 609, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXOR
1271 { 608, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXNORS
1272 { 607, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FXNOR
1273 { 606, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FSUBS
1274 { 605, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FSUBQ
1275 { 604, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FSUBD
1276 { 603, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 261, 0, 0, 0x0ULL }, // FSTOX
1277 { 602, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 263, 0, 0, 0x0ULL }, // FSTOQ
1278 { 601, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FSTOI
1279 { 600, 2, 1, 4, 13, 0, 0, SparcOpInfoBase + 261, 0, 0, 0x0ULL }, // FSTOD
1280 { 599, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRL32
1281 { 598, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRL16
1282 { 597, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC2S
1283 { 596, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC2
1284 { 595, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC1S
1285 { 594, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRC1
1286 { 593, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRA32
1287 { 592, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSRA16
1288 { 591, 2, 1, 4, 12, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FSQRTS
1289 { 590, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 241, 0, 0, 0x0ULL }, // FSQRTQ
1290 { 589, 2, 1, 4, 11, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FSQRTD
1291 { 588, 3, 1, 4, 8, 0, 0, SparcOpInfoBase + 305, 0, 0, 0x0ULL }, // FSMULD
1292 { 587, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLL32
1293 { 586, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLL16
1294 { 585, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLAS32
1295 { 584, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FSLAS16
1296 { 583, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 310, 0, 0, 0x0ULL }, // FQTOX
1297 { 582, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 312, 0, 0, 0x0ULL }, // FQTOS
1298 { 581, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 312, 0, 0, 0x0ULL }, // FQTOI
1299 { 580, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 310, 0, 0, 0x0ULL }, // FQTOD
1300 { 579, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB32S
1301 { 578, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB32
1302 { 577, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB16S
1303 { 576, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPSUB16
1304 { 575, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPMERGE
1305 { 574, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPMADDXHI
1306 { 573, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPMADDX
1307 { 572, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD64
1308 { 571, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD32S
1309 { 570, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD32
1310 { 569, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD16S
1311 { 568, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPADD16
1312 { 567, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 257, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPACKFIX
1313 { 566, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPACK32
1314 { 565, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FPACK16
1315 { 564, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORS
1316 { 563, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT2S
1317 { 562, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT2
1318 { 561, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT1S
1319 { 560, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FORNOT1
1320 { 559, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FOR
1321 { 558, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 309, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FONES
1322 { 557, 1, 1, 4, 0, 0, 0, SparcOpInfoBase + 308, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FONE
1323 { 556, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0, 0x0ULL }, // FNSMULD
1324 { 555, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT2S
1325 { 554, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT2
1326 { 553, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT1S
1327 { 552, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOT1
1328 { 551, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNORS
1329 { 550, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNOR
1330 { 549, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FNMULS
1331 { 548, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FNMULD
1332 { 547, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 271, 0, 0, 0x0ULL }, // FNMSUBS
1333 { 546, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0, 0x0ULL }, // FNMSUBD
1334 { 545, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 271, 0, 0, 0x0ULL }, // FNMADDS
1335 { 544, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0, 0x0ULL }, // FNMADDD
1336 { 543, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FNHADDS
1337 { 542, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FNHADDD
1338 { 541, 2, 1, 4, 10, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FNEGS
1339 { 540, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 241, 0, 0, 0x0ULL }, // FNEGQ
1340 { 539, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FNEGD
1341 { 538, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNANDS
1342 { 537, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FNAND
1343 { 536, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FNADDS
1344 { 535, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FNADDD
1345 { 534, 3, 1, 4, 9, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FMULS
1346 { 533, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FMULQ
1347 { 532, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMULD8ULX16
1348 { 531, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMULD8SUX16
1349 { 530, 3, 1, 4, 8, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FMULD
1350 { 529, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8X16AU
1351 { 528, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 305, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8X16AL
1352 { 527, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 302, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8X16
1353 { 526, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8ULX16
1354 { 525, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMUL8SUX16
1355 { 524, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 271, 0, 0, 0x0ULL }, // FMSUBS
1356 { 523, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0, 0x0ULL }, // FMSUBD
1357 { 522, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 298, 4, 0, 0x0ULL }, // FMOVS_XCC
1358 { 521, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 298, 4, 0, 0x0ULL }, // FMOVS_ICC
1359 { 520, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 298, 3, 0, 0x0ULL }, // FMOVS_FCC
1360 { 519, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 243, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMOVS
1361 { 518, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 293, 0, 0, 0x0ULL }, // FMOVRS
1362 { 517, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 288, 0, 0, 0x0ULL }, // FMOVRQ
1363 { 516, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 283, 0, 0, 0x0ULL }, // FMOVRD
1364 { 515, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 279, 4, 0, 0x0ULL }, // FMOVQ_XCC
1365 { 514, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 279, 4, 0, 0x0ULL }, // FMOVQ_ICC
1366 { 513, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 279, 3, 0, 0x0ULL }, // FMOVQ_FCC
1367 { 512, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 241, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMOVQ
1368 { 511, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 275, 4, 0, 0x0ULL }, // FMOVD_XCC
1369 { 510, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 275, 4, 0, 0x0ULL }, // FMOVD_ICC
1370 { 509, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 275, 3, 0, 0x0ULL }, // FMOVD_FCC
1371 { 508, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMOVD
1372 { 507, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FMEAN16
1373 { 506, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 271, 0, 0, 0x0ULL }, // FMADDS
1374 { 505, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0, 0x0ULL }, // FMADDD
1375 { 504, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 193, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSHrr
1376 { 503, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 191, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSHri
1377 { 502, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSHW
1378 { 501, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLUSH
1379 { 500, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 268, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLCMPS
1380 { 499, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 265, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FLCMPD
1381 { 498, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FITOS
1382 { 497, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 263, 0, 0, 0x0ULL }, // FITOQ
1383 { 496, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 261, 0, 0, 0x0ULL }, // FITOD
1384 { 495, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FHSUBS
1385 { 494, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FHSUBD
1386 { 493, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FHADDS
1387 { 492, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FHADDD
1388 { 491, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 261, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FEXPAND
1389 { 490, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FDTOX
1390 { 489, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 257, 0, 0, 0x0ULL }, // FDTOS
1391 { 488, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 259, 0, 0, 0x0ULL }, // FDTOQ
1392 { 487, 2, 1, 4, 5, 0, 0, SparcOpInfoBase + 257, 0, 0, 0x0ULL }, // FDTOI
1393 { 486, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 254, 0, 0, 0x0ULL }, // FDMULQ
1394 { 485, 3, 1, 4, 7, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FDIVS
1395 { 484, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FDIVQ
1396 { 483, 3, 1, 4, 6, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FDIVD
1397 { 482, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 243, 3, 0, 0x0ULL }, // FCMPS_V9
1398 { 481, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 243, 3, 0, 0x0ULL }, // FCMPS
1399 { 480, 2, 0, 4, 0, 0, 1, SparcOpInfoBase + 241, 3, 0, 0x0ULL }, // FCMPQ_V9
1400 { 479, 2, 0, 4, 0, 0, 1, SparcOpInfoBase + 241, 3, 0, 0x0ULL }, // FCMPQ
1401 { 478, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPNE32
1402 { 477, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPNE16
1403 { 476, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPLE32
1404 { 475, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPLE16
1405 { 474, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPGT32
1406 { 473, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPGT16
1407 { 472, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPEQ32
1408 { 471, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 251, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCMPEQ16
1409 { 470, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 236, 3, 0, 0x0ULL }, // FCMPD_V9
1410 { 469, 2, 0, 4, 5, 0, 1, SparcOpInfoBase + 236, 3, 0, 0x0ULL }, // FCMPD
1411 { 468, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FCHKSM16
1412 { 467, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // FBCOND_V9
1413 { 466, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // FBCONDA_V9
1414 { 465, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FBCONDA
1415 { 464, 2, 0, 4, 2, 1, 0, SparcOpInfoBase + 189, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // FBCOND
1416 { 463, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDS
1417 { 462, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT2S
1418 { 461, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT2
1419 { 460, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 248, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT1S
1420 { 459, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FANDNOT1
1421 { 458, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAND
1422 { 457, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FALIGNADATA
1423 { 456, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 248, 0, 0, 0x0ULL }, // FADDS
1424 { 455, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 245, 0, 0, 0x0ULL }, // FADDQ
1425 { 454, 3, 1, 4, 5, 0, 0, SparcOpInfoBase + 185, 0, 0, 0x0ULL }, // FADDD
1426 { 453, 2, 1, 4, 4, 0, 0, SparcOpInfoBase + 243, 0, 0, 0x0ULL }, // FABSS
1427 { 452, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 241, 0, 0, 0x0ULL }, // FABSQ
1428 { 451, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0, 0x0ULL }, // FABSD
1429 { 450, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8N
1430 { 449, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8LN
1431 { 448, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8L
1432 { 447, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE8
1433 { 446, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32N
1434 { 445, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32LN
1435 { 444, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32L
1436 { 443, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE32
1437 { 442, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16N
1438 { 441, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16LN
1439 { 440, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16L
1440 { 439, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // EDGE16
1441 { 438, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DONE
1442 { 437, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_ROUND
1443 { 436, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 238, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_KEXPAND
1444 { 435, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_IP
1445 { 434, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // DES_IIP
1446 { 433, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 232, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CXBCONDrr
1447 { 432, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 228, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CXBCONDri
1448 { 431, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 232, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CWBCONDrr
1449 { 430, 4, 0, 4, 0, 0, 0, SparcOpInfoBase + 228, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CWBCONDri
1450 { 429, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CRC32C
1451 { 428, 2, 0, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CPBCONDA
1452 { 427, 2, 0, 4, 0, 0, 0, SparcOpInfoBase + 189, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // CPBCOND
1453 { 426, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 227, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMASK8
1454 { 425, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 227, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMASK32
1455 { 424, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 227, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMASK16
1456 { 423, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 222, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // CASXArr
1457 { 422, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 218, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CASXAri
1458 { 421, 5, 1, 4, 0, 0, 0, SparcOpInfoBase + 213, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // CASArr
1459 { 420, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 209, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CASAri
1460 { 419, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CAMELLIA_FLI
1461 { 418, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CAMELLIA_FL
1462 { 417, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CAMELLIA_F
1463 { 416, 3, 0, 4, 1, 1, 1, SparcOpInfoBase + 206, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CALLrri
1464 { 415, 2, 0, 4, 3, 1, 1, SparcOpInfoBase + 193, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // CALLrr
1465 { 414, 3, 0, 4, 1, 1, 1, SparcOpInfoBase + 203, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CALLrii
1466 { 413, 2, 0, 4, 3, 1, 1, SparcOpInfoBase + 191, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // CALLri
1467 { 412, 2, 0, 4, 0, 1, 1, SparcOpInfoBase + 201, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CALLi
1468 { 411, 1, 0, 4, 3, 1, 1, SparcOpInfoBase + 188, 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // CALL
1469 { 410, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BSHUFFLE
1470 { 409, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPXCCNT
1471 { 408, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPXCCANT
1472 { 407, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPXCCA
1473 { 406, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BPXCC
1474 { 405, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 198, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPRNT
1475 { 404, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 198, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPRANT
1476 { 403, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 198, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPRA
1477 { 402, 3, 0, 4, 0, 0, 0, SparcOpInfoBase + 198, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BPR
1478 { 401, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPICCNT
1479 { 400, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPICCANT
1480 { 399, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPICCA
1481 { 398, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BPICC
1482 { 397, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCCNT
1483 { 396, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCCANT
1484 { 395, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCCA
1485 { 394, 3, 0, 4, 2, 0, 0, SparcOpInfoBase + 195, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BPFCC
1486 { 393, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BMASK
1487 { 392, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 193, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BINDrr
1488 { 391, 2, 0, 4, 1, 0, 0, SparcOpInfoBase + 191, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BINDri
1489 { 390, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BCONDA
1490 { 389, 2, 0, 4, 1, 1, 0, SparcOpInfoBase + 189, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BCOND
1491 { 388, 1, 0, 4, 0, 0, 0, SparcOpInfoBase + 188, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // BA
1492 { 387, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ARRAY8
1493 { 386, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ARRAY32
1494 { 385, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ARRAY16
1495 { 384, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ANDrr
1496 { 383, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // ANDri
1497 { 382, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ANDNrr
1498 { 381, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDNri
1499 { 380, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDNCCrr
1500 { 379, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDNCCri
1501 { 378, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDCCrr
1502 { 377, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ANDCCri
1503 { 376, 0, 0, 4, 1, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALLCLEAN
1504 { 375, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALIGNADDRL
1505 { 374, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 178, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALIGNADDR
1506 { 373, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_KEXPAND2
1507 { 372, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 151, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_KEXPAND1
1508 { 371, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 185, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_KEXPAND0
1509 { 370, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND23_LAST
1510 { 369, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND23
1511 { 368, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND01_LAST
1512 { 367, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_EROUND01
1513 { 366, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND23_LAST
1514 { 365, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND23
1515 { 364, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND01_LAST
1516 { 363, 4, 1, 4, 0, 0, 0, SparcOpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // AES_DROUND01
1517 { 362, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 175, 0, 0, 0x0ULL }, // ADDrr
1518 { 361, 3, 1, 4, 1, 0, 0, SparcOpInfoBase + 172, 0, 0, 0x0ULL }, // ADDri
1519 { 360, 3, 1, 4, 0, 1, 1, SparcOpInfoBase + 178, 5, 0, 0x0ULL }, // ADDXCCC
1520 { 359, 3, 1, 4, 0, 1, 0, SparcOpInfoBase + 178, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDXC
1521 { 358, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 175, 5, 0, 0x0ULL }, // ADDErr
1522 { 357, 3, 1, 4, 1, 1, 1, SparcOpInfoBase + 172, 5, 0, 0x0ULL }, // ADDEri
1523 { 356, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 175, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDCrr
1524 { 355, 3, 1, 4, 1, 1, 0, SparcOpInfoBase + 172, 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADDCri
1525 { 354, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 175, 4, 0, 0x0ULL }, // ADDCCrr
1526 { 353, 3, 1, 4, 1, 0, 1, SparcOpInfoBase + 172, 4, 0, 0x0ULL }, // ADDCCri
1527 { 352, 0, 0, 4, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // V8BAR
1528 { 351, 3, 1, 4, 0, 0, 0, SparcOpInfoBase + 169, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SETX
1529 { 350, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 167, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SETSW
1530 { 349, 2, 1, 4, 0, 0, 0, SparcOpInfoBase + 167, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SET
1531 { 348, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 163, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_QFP_XCC
1532 { 347, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 163, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_QFP_ICC
1533 { 346, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 163, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_QFP_FCC
1534 { 345, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 159, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_Int_XCC
1535 { 344, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 159, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_Int_ICC
1536 { 343, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 159, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_Int_FCC
1537 { 342, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 155, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_FP_XCC
1538 { 341, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 155, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_FP_ICC
1539 { 340, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 155, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_FP_FCC
1540 { 339, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 151, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_DFP_XCC
1541 { 338, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 151, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_DFP_ICC
1542 { 337, 4, 1, 4, 0, 1, 0, SparcOpInfoBase + 151, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // SELECT_CC_DFP_FCC
1543 { 336, 1, 1, 4, 0, 0, 1, SparcOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // GETPCX
1544 { 335, 2, 0, 4, 0, 1, 1, SparcOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ADJCALLSTACKUP
1545 { 334, 2, 0, 4, 0, 1, 1, SparcOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // ADJCALLSTACKDOWN
1546 { 333, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX
1547 { 332, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX
1548 { 331, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN
1549 { 330, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX
1550 { 329, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN
1551 { 328, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX
1552 { 327, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR
1553 { 326, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR
1554 { 325, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND
1555 { 324, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL
1556 { 323, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD
1557 { 322, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1558 { 321, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1559 { 320, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1560 { 319, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1561 { 318, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN
1562 { 317, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX
1563 { 316, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL
1564 { 315, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD
1565 { 314, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1566 { 313, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1567 { 312, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP
1568 { 311, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP
1569 { 310, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP
1570 { 309, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET_INLINE
1571 { 308, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO
1572 { 307, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET
1573 { 306, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE
1574 { 305, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE
1575 { 304, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY
1576 { 303, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1577 { 302, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1578 { 301, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMPS
1579 { 300, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMP
1580 { 299, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP
1581 { 298, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT
1582 { 297, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA
1583 { 296, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM
1584 { 295, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV
1585 { 294, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL
1586 { 293, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB
1587 { 292, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD
1588 { 291, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE
1589 { 290, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE
1590 { 289, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC
1591 { 288, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE
1592 { 287, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR
1593 { 286, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST
1594 { 285, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT
1595 { 284, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT
1596 { 283, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR
1597 { 282, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT
1598 { 281, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH
1599 { 280, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH
1600 { 279, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH
1601 { 278, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2
1602 { 277, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN
1603 { 276, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN
1604 { 275, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS
1605 { 274, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN
1606 { 273, 3, 2, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS
1607 { 272, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN
1608 { 271, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS
1609 { 270, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL
1610 { 269, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMULH
1611 { 268, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMUL
1612 { 267, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE
1613 { 266, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP
1614 { 265, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP
1615 { 264, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS
1616 { 263, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_POISON
1617 { 262, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ
1618 { 261, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_POISON
1619 { 260, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ
1620 { 259, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS
1621 { 258, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR
1622 { 257, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR
1623 { 256, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR
1624 { 255, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1625 { 254, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT
1626 { 253, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1627 { 252, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR
1628 { 251, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE
1629 { 250, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT
1630 { 249, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR
1631 { 248, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND
1632 { 247, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND
1633 { 246, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS
1634 { 245, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX
1635 { 244, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN
1636 { 243, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX
1637 { 242, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN
1638 { 241, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK
1639 { 240, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD
1640 { 239, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING
1641 { 238, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING
1642 { 237, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE
1643 { 236, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE
1644 { 235, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE
1645 { 234, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV
1646 { 233, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV
1647 { 232, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV
1648 { 231, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM
1649 { 230, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM
1650 { 229, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM
1651 { 228, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM
1652 { 227, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE
1653 { 226, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE
1654 { 225, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM
1655 { 224, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM
1656 { 223, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE
1657 { 222, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS
1658 { 221, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN
1659 { 220, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS
1660 { 219, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT
1661 { 218, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT
1662 { 217, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP
1663 { 216, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP
1664 { 215, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI
1665 { 214, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI
1666 { 213, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC
1667 { 212, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT
1668 { 211, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG
1669 { 210, 3, 2, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP
1670 { 209, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP
1671 { 208, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10
1672 { 207, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2
1673 { 206, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG
1674 { 205, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10
1675 { 204, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2
1676 { 203, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP
1677 { 202, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI
1678 { 201, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW
1679 { 200, 3, 2, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF
1680 { 199, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM
1681 { 198, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV
1682 { 197, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD
1683 { 196, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA
1684 { 195, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL
1685 { 194, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB
1686 { 193, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD
1687 { 192, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT
1688 { 191, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT
1689 { 190, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX
1690 { 189, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX
1691 { 188, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT
1692 { 187, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT
1693 { 186, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX
1694 { 185, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX
1695 { 184, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT
1696 { 183, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT
1697 { 182, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT
1698 { 181, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT
1699 { 180, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT
1700 { 179, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT
1701 { 178, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH
1702 { 177, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH
1703 { 176, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO
1704 { 175, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO
1705 { 174, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE
1706 { 173, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO
1707 { 172, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE
1708 { 171, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO
1709 { 170, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE
1710 { 169, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO
1711 { 168, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE
1712 { 167, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO
1713 { 166, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT
1714 { 165, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP
1715 { 164, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP
1716 { 163, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP
1717 { 162, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP
1718 { 161, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL
1719 { 160, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR
1720 { 159, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR
1721 { 158, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL
1722 { 157, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR
1723 { 156, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR
1724 { 155, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL
1725 { 154, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT
1726 { 153, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG
1727 { 152, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT
1728 { 151, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG
1729 { 150, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART
1730 { 149, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT
1731 { 148, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT
1732 { 147, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U
1733 { 146, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U
1734 { 145, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S
1735 { 144, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC
1736 { 143, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT
1737 { 142, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1738 { 141, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1739 { 140, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1740 { 139, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC
1741 { 138, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START
1742 { 137, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT
1743 { 136, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND
1744 { 135, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH
1745 { 134, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE
1746 { 133, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1747 { 132, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1748 { 131, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1749 { 130, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1750 { 129, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1751 { 128, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1752 { 127, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1753 { 126, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1754 { 125, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN
1755 { 124, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX
1756 { 123, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB
1757 { 122, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD
1758 { 121, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN
1759 { 120, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX
1760 { 119, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN
1761 { 118, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX
1762 { 117, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR
1763 { 116, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR
1764 { 115, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND
1765 { 114, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND
1766 { 113, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB
1767 { 112, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD
1768 { 111, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG
1769 { 110, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG
1770 { 109, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1771 { 108, 5, 1, 0, 0, 0, 0, SparcOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE
1772 { 107, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_FPTRUNCSTORE
1773 { 106, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE
1774 { 105, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1775 { 104, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD
1776 { 103, 5, 2, 0, 0, 0, 0, SparcOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD
1777 { 102, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_FPEXTLOAD
1778 { 101, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD
1779 { 100, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD
1780 { 99, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD
1781 { 98, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER
1782 { 97, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER
1783 { 96, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1784 { 95, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT
1785 { 94, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT
1786 { 93, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND
1787 { 92, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC
1788 { 91, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1789 { 90, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1790 { 89, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE
1791 { 88, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST
1792 { 87, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR
1793 { 86, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT
1794 { 85, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS
1795 { 84, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1796 { 83, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR
1797 { 82, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES
1798 { 81, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT
1799 { 80, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES
1800 { 79, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT
1801 { 78, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL
1802 { 77, 5, 1, 0, 0, 0, 0, SparcOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1803 { 76, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE
1804 { 75, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX
1805 { 74, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI
1806 { 73, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF
1807 { 72, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL
1808 { 71, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR
1809 { 70, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL
1810 { 69, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR
1811 { 68, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU
1812 { 67, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS
1813 { 66, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR
1814 { 65, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR
1815 { 64, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND
1816 { 63, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM
1817 { 62, 4, 2, 0, 0, 0, 0, SparcOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM
1818 { 61, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM
1819 { 60, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM
1820 { 59, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV
1821 { 58, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV
1822 { 57, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL
1823 { 56, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB
1824 { 55, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD
1825 { 54, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN
1826 { 53, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT
1827 { 52, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT
1828 { 51, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1829 { 50, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1830 { 49, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1831 { 48, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1832 { 47, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE
1833 { 46, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1834 { 45, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER
1835 { 44, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE
1836 { 43, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1837 { 42, 3, 0, 0, 0, 0, 0, SparcOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17211
1838 { 41, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17210
1839 { 40, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL
1840 { 39, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1841 { 38, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET
1842 { 37, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1843 { 36, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP
1844 { 35, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP
1845 { 34, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE
1846 { 33, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT
1847 { 32, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_17209
1848 { 31, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP
1849 { 30, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_14348
1850 { 29, 6, 1, 0, 0, 0, 0, SparcOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT
1851 { 28, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL
1852 { 27, 2, 0, 0, 0, 0, 0, SparcOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP
1853 { 26, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE
1854 { 25, 4, 0, 0, 0, 0, 0, SparcOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE
1855 { 24, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END
1856 { 23, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START
1857 { 22, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE
1858 { 21, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK
1859 { 20, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY
1860 { 19, 2, 1, 0, 0, 0, 0, SparcOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE
1861 { 18, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL
1862 { 17, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI
1863 { 16, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF
1864 { 15, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST
1865 { 14, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE
1866 { 13, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS
1867 { 12, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG
1868 { 11, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF
1869 { 10, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF
1870 { 9, 4, 1, 0, 0, 0, 0, SparcOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG
1871 { 8, 3, 1, 0, 0, 0, 0, SparcOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG
1872 { 7, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL
1873 { 6, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL
1874 { 5, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL
1875 { 4, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL
1876 { 3, 1, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION
1877 { 2, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR
1878 { 1, 0, 0, 0, 0, 0, 0, SparcOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM
1879 { 0, 1, 1, 0, 0, 0, 0, SparcOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI
1880 }, {
1881 /* 0 */
1882 /* 0 */ SP::O6, SP::O6,
1883 /* 2 */ SP::O7,
1884 /* 3 */ SP::FCC0,
1885 /* 4 */ SP::ICC,
1886 /* 5 */ SP::ICC, SP::ICC,
1887 /* 7 */ SP::O6, SP::O7,
1888 /* 9 */ SP::ASR3,
1889 /* 10 */ SP::CPSR,
1890 /* 11 */ SP::FSR,
1891 /* 12 */ SP::D0, SP::D1, SP::D2, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7,
1892 /* 30 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5,
1893 /* 134 */ SP::Y, SP::ICC, SP::Y, SP::ICC,
1894 /* 138 */ SP::PSR,
1895 /* 139 */ SP::FQ,
1896 /* 140 */ SP::TBR,
1897 /* 141 */ SP::WIM,
1898 /* 142 */ SP::Y, SP::Y, SP::ICC,
1899 /* 145 */ SP::Y, SP::Y,
1900 /* 147 */ SP::D0, SP::D1, SP::D2, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D0, SP::D1, SP::D2,
1901 /* 161 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D0, SP::D1, SP::D2, SP::D3,
1902 /* 177 */ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7,
1903 /* 209 */ SP::Y, SP::ASR18, SP::Y, SP::ASR18,
1904 /* 213 */ SP::Y, SP::ICC,
1905 /* 215 */ SP::Y,
1906 /* 216 */ SP::CPQ,
1907 /* 217 */ SP::O6,
1908 }, {
1909 0
1910 }, {
1911 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1912 /* 1 */
1913 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1914 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1915 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1916 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1917 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1918 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1919 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1920 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1921 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1922 /* 28 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
1923 /* 29 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1924 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1925 /* 34 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1926 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1927 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1928 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1929 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1930 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1931 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1932 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1933 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1934 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1935 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1936 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1937 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1938 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1939 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1940 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1941 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1942 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1943 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1944 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1945 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1946 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1947 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1948 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1949 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1950 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1951 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1952 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1953 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1954 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1955 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1956 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1957 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1958 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1959 /* 151 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1960 /* 155 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1961 /* 159 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1962 /* 163 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1963 /* 167 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1964 /* 169 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1965 /* 172 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1966 /* 175 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1967 /* 178 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1968 /* 181 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1969 /* 185 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1970 /* 188 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },
1971 /* 189 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1972 /* 191 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1973 /* 193 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
1974 /* 195 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1975 /* 198 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1976 /* 201 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1977 /* 203 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1978 /* 206 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1979 /* 209 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1980 /* 213 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1981 /* 218 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1982 /* 222 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1983 /* 227 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1984 /* 228 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1985 /* 232 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1986 /* 236 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1987 /* 238 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1988 /* 241 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1989 /* 243 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1990 /* 245 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1991 /* 248 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1992 /* 251 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1993 /* 254 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1994 /* 257 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1995 /* 259 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1996 /* 261 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1997 /* 263 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1998 /* 265 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1999 /* 268 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2000 /* 271 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2001 /* 275 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2002 /* 279 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2003 /* 283 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2004 /* 288 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2005 /* 293 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2006 /* 298 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2007 /* 302 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2008 /* 305 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2009 /* 308 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2010 /* 309 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2011 /* 310 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2012 /* 312 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2013 /* 314 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2014 /* 318 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2015 /* 322 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2016 /* 325 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2017 /* 328 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2018 /* 331 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2019 /* 334 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2020 /* 337 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2021 /* 341 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2022 /* 344 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2023 /* 347 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2024 /* 350 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2025 /* 354 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2026 /* 357 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2027 /* 360 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2028 /* 363 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2029 /* 367 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2030 /* 370 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2031 /* 373 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2032 /* 377 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2033 /* 380 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2034 /* 383 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 },
2035 /* 386 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2036 /* 388 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2037 /* 390 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2038 /* 394 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2039 /* 398 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2040 /* 403 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2041 /* 408 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2042 /* 410 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2043 /* 412 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2044 /* 414 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
2045 /* 417 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2046 /* 419 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2047 /* 422 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2048 /* 426 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2049 /* 429 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2050 /* 431 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2051 /* 432 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2052 /* 434 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2053 /* 437 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2054 /* 440 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2055 /* 443 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2056 /* 446 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2057 /* 450 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2058 /* 453 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2059 /* 456 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2060 /* 459 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2061 /* 462 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2062 /* 466 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2063 /* 469 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2064 /* 472 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2065 /* 475 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2066 /* 479 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2067 /* 482 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2068 /* 485 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2069 /* 488 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2070 /* 492 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2071 /* 495 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2072 /* 498 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2073 /* 502 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2074 /* 505 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2075 /* 508 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2076 /* 512 */ { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2077 /* 515 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
2078 /* 519 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
2079 /* 524 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::sparc_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
2080 /* 528 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2081 /* 531 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2082 /* 535 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2083 /* 538 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2084 /* 543 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2085 /* 548 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2086 /* 553 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2087 /* 558 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
2088 /* 563 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
2089 /* 566 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2090 /* 569 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
2091 /* 572 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
2092 }
2093};
2094
2095
2096#ifdef __GNUC__
2097#pragma GCC diagnostic push
2098#pragma GCC diagnostic ignored "-Woverlength-strings"
2099#endif
2100extern const char SparcInstrNameData[] = {
2101 /* 0 */ "G_FLOG10\000"
2102 /* 9 */ "G_FEXP10\000"
2103 /* 18 */ "AES_KEXPAND0\000"
2104 /* 31 */ "AES_DROUND01\000"
2105 /* 44 */ "AES_EROUND01\000"
2106 /* 57 */ "SHA1\000"
2107 /* 62 */ "TA1\000"
2108 /* 66 */ "FSRC1\000"
2109 /* 72 */ "AES_KEXPAND1\000"
2110 /* 85 */ "FANDNOT1\000"
2111 /* 94 */ "FNOT1\000"
2112 /* 100 */ "FORNOT1\000"
2113 /* 108 */ "SHA512\000"
2114 /* 115 */ "FSRA32\000"
2115 /* 122 */ "FPSUB32\000"
2116 /* 130 */ "FPADD32\000"
2117 /* 138 */ "EDGE32\000"
2118 /* 145 */ "FCMPLE32\000"
2119 /* 154 */ "FCMPNE32\000"
2120 /* 163 */ "FPACK32\000"
2121 /* 171 */ "CMASK32\000"
2122 /* 179 */ "FSLL32\000"
2123 /* 186 */ "FSRL32\000"
2124 /* 193 */ "FCMPEQ32\000"
2125 /* 202 */ "FSLAS32\000"
2126 /* 210 */ "FCMPGT32\000"
2127 /* 219 */ "ARRAY32\000"
2128 /* 227 */ "FSRC2\000"
2129 /* 233 */ "AES_KEXPAND2\000"
2130 /* 246 */ "G_FLOG2\000"
2131 /* 254 */ "G_FATAN2\000"
2132 /* 263 */ "G_FEXP2\000"
2133 /* 271 */ "FANDNOT2\000"
2134 /* 280 */ "FNOT2\000"
2135 /* 286 */ "FORNOT2\000"
2136 /* 294 */ "AES_DROUND23\000"
2137 /* 307 */ "AES_EROUND23\000"
2138 /* 320 */ "TA3\000"
2139 /* 324 */ "FPADD64\000"
2140 /* 332 */ "TA5\000"
2141 /* 336 */ "MD5\000"
2142 /* 340 */ "FSRA16\000"
2143 /* 347 */ "FPSUB16\000"
2144 /* 355 */ "FPADD16\000"
2145 /* 363 */ "EDGE16\000"
2146 /* 370 */ "FCMPLE16\000"
2147 /* 379 */ "FCMPNE16\000"
2148 /* 388 */ "FPACK16\000"
2149 /* 396 */ "CMASK16\000"
2150 /* 404 */ "FSLL16\000"
2151 /* 411 */ "FSRL16\000"
2152 /* 418 */ "FCHKSM16\000"
2153 /* 427 */ "FMEAN16\000"
2154 /* 435 */ "FCMPEQ16\000"
2155 /* 444 */ "FSLAS16\000"
2156 /* 452 */ "FCMPGT16\000"
2157 /* 461 */ "FMUL8X16\000"
2158 /* 470 */ "FMULD8ULX16\000"
2159 /* 482 */ "FMUL8ULX16\000"
2160 /* 493 */ "FMULD8SUX16\000"
2161 /* 505 */ "FMUL8SUX16\000"
2162 /* 516 */ "ARRAY16\000"
2163 /* 524 */ "SHA256\000"
2164 /* 531 */ "EDGE8\000"
2165 /* 537 */ "CMASK8\000"
2166 /* 544 */ "ARRAY8\000"
2167 /* 551 */ "FBCONDA_V9\000"
2168 /* 562 */ "FBCOND_V9\000"
2169 /* 572 */ "FCMPD_V9\000"
2170 /* 581 */ "FCMPQ_V9\000"
2171 /* 590 */ "FCMPS_V9\000"
2172 /* 599 */ "BA\000"
2173 /* 602 */ "BPFCCA\000"
2174 /* 609 */ "BPICCA\000"
2175 /* 616 */ "BPXCCA\000"
2176 /* 623 */ "FBCONDA\000"
2177 /* 631 */ "CPBCONDA\000"
2178 /* 640 */ "G_FMA\000"
2179 /* 646 */ "G_STRICT_FMA\000"
2180 /* 659 */ "BPRA\000"
2181 /* 664 */ "FALIGNADATA\000"
2182 /* 676 */ "G_FSUB\000"
2183 /* 683 */ "G_STRICT_FSUB\000"
2184 /* 697 */ "G_ATOMICRMW_FSUB\000"
2185 /* 714 */ "G_SUB\000"
2186 /* 720 */ "G_ATOMICRMW_SUB\000"
2187 /* 736 */ "CRC32C\000"
2188 /* 743 */ "ADDXCCC\000"
2189 /* 751 */ "BPFCC\000"
2190 /* 757 */ "V9FMOVD_FCC\000"
2191 /* 769 */ "SELECT_CC_DFP_FCC\000"
2192 /* 787 */ "SELECT_CC_QFP_FCC\000"
2193 /* 805 */ "SELECT_CC_FP_FCC\000"
2194 /* 822 */ "V9FMOVQ_FCC\000"
2195 /* 834 */ "V9FMOVS_FCC\000"
2196 /* 846 */ "SELECT_CC_Int_FCC\000"
2197 /* 864 */ "BPICC\000"
2198 /* 870 */ "FMOVD_ICC\000"
2199 /* 880 */ "SELECT_CC_DFP_ICC\000"
2200 /* 898 */ "SELECT_CC_QFP_ICC\000"
2201 /* 916 */ "SELECT_CC_FP_ICC\000"
2202 /* 933 */ "FMOVQ_ICC\000"
2203 /* 943 */ "FMOVS_ICC\000"
2204 /* 953 */ "SELECT_CC_Int_ICC\000"
2205 /* 971 */ "BPXCC\000"
2206 /* 977 */ "FMOVD_XCC\000"
2207 /* 987 */ "SELECT_CC_DFP_XCC\000"
2208 /* 1005 */ "SELECT_CC_QFP_XCC\000"
2209 /* 1023 */ "SELECT_CC_FP_XCC\000"
2210 /* 1040 */ "FMOVQ_XCC\000"
2211 /* 1050 */ "FMOVS_XCC\000"
2212 /* 1060 */ "SELECT_CC_Int_XCC\000"
2213 /* 1078 */ "G_INTRINSIC\000"
2214 /* 1090 */ "G_FPTRUNC\000"
2215 /* 1100 */ "G_INTRINSIC_TRUNC\000"
2216 /* 1118 */ "G_TRUNC\000"
2217 /* 1126 */ "G_BUILD_VECTOR_TRUNC\000"
2218 /* 1147 */ "G_DYN_STACKALLOC\000"
2219 /* 1164 */ "ADDXC\000"
2220 /* 1170 */ "G_FMAD\000"
2221 /* 1177 */ "G_FPEXTLOAD\000"
2222 /* 1189 */ "G_INDEXED_SEXTLOAD\000"
2223 /* 1208 */ "G_SEXTLOAD\000"
2224 /* 1219 */ "G_INDEXED_ZEXTLOAD\000"
2225 /* 1238 */ "G_ZEXTLOAD\000"
2226 /* 1249 */ "G_INDEXED_LOAD\000"
2227 /* 1264 */ "G_LOAD\000"
2228 /* 1271 */ "FSUBD\000"
2229 /* 1277 */ "FHSUBD\000"
2230 /* 1284 */ "FMSUBD\000"
2231 /* 1291 */ "FNMSUBD\000"
2232 /* 1299 */ "G_VECREDUCE_FADD\000"
2233 /* 1316 */ "G_FADD\000"
2234 /* 1323 */ "G_VECREDUCE_SEQ_FADD\000"
2235 /* 1344 */ "G_STRICT_FADD\000"
2236 /* 1358 */ "G_ATOMICRMW_FADD\000"
2237 /* 1375 */ "G_VECREDUCE_ADD\000"
2238 /* 1391 */ "G_ADD\000"
2239 /* 1397 */ "G_PTR_ADD\000"
2240 /* 1407 */ "G_ATOMICRMW_ADD\000"
2241 /* 1423 */ "FADDD\000"
2242 /* 1429 */ "FHADDD\000"
2243 /* 1436 */ "FNHADDD\000"
2244 /* 1444 */ "FMADDD\000"
2245 /* 1451 */ "FNMADDD\000"
2246 /* 1459 */ "FNADDD\000"
2247 /* 1466 */ "V9FCMPED\000"
2248 /* 1475 */ "RESTORED\000"
2249 /* 1484 */ "SAVED\000"
2250 /* 1490 */ "FNEGD\000"
2251 /* 1496 */ "FMULD\000"
2252 /* 1502 */ "FNMULD\000"
2253 /* 1509 */ "FSMULD\000"
2254 /* 1516 */ "FNSMULD\000"
2255 /* 1524 */ "FAND\000"
2256 /* 1529 */ "FNAND\000"
2257 /* 1535 */ "G_ATOMICRMW_NAND\000"
2258 /* 1552 */ "FEXPAND\000"
2259 /* 1560 */ "DES_KEXPAND\000"
2260 /* 1572 */ "G_VECREDUCE_AND\000"
2261 /* 1588 */ "G_AND\000"
2262 /* 1594 */ "G_ATOMICRMW_AND\000"
2263 /* 1610 */ "LIFETIME_END\000"
2264 /* 1623 */ "FBCOND\000"
2265 /* 1630 */ "CPBCOND\000"
2266 /* 1638 */ "G_BRCOND\000"
2267 /* 1647 */ "G_ATOMICRMW_USUB_COND\000"
2268 /* 1669 */ "G_LLROUND\000"
2269 /* 1679 */ "G_LROUND\000"
2270 /* 1688 */ "G_INTRINSIC_ROUND\000"
2271 /* 1706 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
2272 /* 1732 */ "DES_ROUND\000"
2273 /* 1742 */ "FITOD\000"
2274 /* 1748 */ "FQTOD\000"
2275 /* 1754 */ "FSTOD\000"
2276 /* 1760 */ "FXTOD\000"
2277 /* 1766 */ "MOVXTOD\000"
2278 /* 1774 */ "V9FCMPD\000"
2279 /* 1782 */ "FLCMPD\000"
2280 /* 1789 */ "LOAD_STACK_GUARD\000"
2281 /* 1806 */ "FMOVRD\000"
2282 /* 1813 */ "FABSD\000"
2283 /* 1819 */ "FSQRTD\000"
2284 /* 1826 */ "FDIVD\000"
2285 /* 1832 */ "FMOVD\000"
2286 /* 1838 */ "PSEUDO_PROBE\000"
2287 /* 1851 */ "G_SSUBE\000"
2288 /* 1859 */ "G_USUBE\000"
2289 /* 1867 */ "G_FENCE\000"
2290 /* 1875 */ "ARITH_FENCE\000"
2291 /* 1887 */ "REG_SEQUENCE\000"
2292 /* 1900 */ "G_SADDE\000"
2293 /* 1908 */ "G_UADDE\000"
2294 /* 1916 */ "G_GET_FPMODE\000"
2295 /* 1929 */ "G_RESET_FPMODE\000"
2296 /* 1944 */ "G_SET_FPMODE\000"
2297 /* 1957 */ "G_FMINNUM_IEEE\000"
2298 /* 1972 */ "G_FMAXNUM_IEEE\000"
2299 /* 1987 */ "FPMERGE\000"
2300 /* 1995 */ "G_VSCALE\000"
2301 /* 2004 */ "G_JUMP_TABLE\000"
2302 /* 2017 */ "BUNDLE\000"
2303 /* 2024 */ "BSHUFFLE\000"
2304 /* 2033 */ "G_MEMSET_INLINE\000"
2305 /* 2049 */ "G_MEMCPY_INLINE\000"
2306 /* 2065 */ "DONE\000"
2307 /* 2070 */ "FONE\000"
2308 /* 2075 */ "RELOC_NONE\000"
2309 /* 2086 */ "LOCAL_ESCAPE\000"
2310 /* 2099 */ "G_FPTRUNCSTORE\000"
2311 /* 2114 */ "G_STACKRESTORE\000"
2312 /* 2129 */ "G_INDEXED_STORE\000"
2313 /* 2145 */ "G_STORE\000"
2314 /* 2153 */ "G_BITREVERSE\000"
2315 /* 2166 */ "FAKE_USE\000"
2316 /* 2175 */ "DBG_VALUE\000"
2317 /* 2185 */ "G_GLOBAL_VALUE\000"
2318 /* 2200 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2319 /* 2223 */ "CONVERGENCECTRL_GLUE\000"
2320 /* 2244 */ "G_STACKSAVE\000"
2321 /* 2256 */ "G_MEMMOVE\000"
2322 /* 2266 */ "G_FREEZE\000"
2323 /* 2275 */ "G_FCANONICALIZE\000"
2324 /* 2291 */ "G_FMODF\000"
2325 /* 2299 */ "INIT_UNDEF\000"
2326 /* 2310 */ "G_IMPLICIT_DEF\000"
2327 /* 2325 */ "DBG_INSTR_REF\000"
2328 /* 2339 */ "CAMELLIA_F\000"
2329 /* 2350 */ "G_FNEG\000"
2330 /* 2357 */ "EXTRACT_SUBREG\000"
2331 /* 2372 */ "INSERT_SUBREG\000"
2332 /* 2386 */ "G_SEXT_INREG\000"
2333 /* 2399 */ "SUBREG_TO_REG\000"
2334 /* 2413 */ "G_ATOMIC_CMPXCHG\000"
2335 /* 2430 */ "G_ATOMICRMW_XCHG\000"
2336 /* 2447 */ "G_GET_ROUNDING\000"
2337 /* 2462 */ "G_SET_ROUNDING\000"
2338 /* 2477 */ "G_FLOG\000"
2339 /* 2484 */ "G_VAARG\000"
2340 /* 2492 */ "PREALLOCATED_ARG\000"
2341 /* 2509 */ "G_PREFETCH\000"
2342 /* 2520 */ "G_CLMULH\000"
2343 /* 2529 */ "G_SMULH\000"
2344 /* 2537 */ "G_UMULH\000"
2345 /* 2545 */ "G_FTANH\000"
2346 /* 2553 */ "G_FSINH\000"
2347 /* 2561 */ "G_FCOSH\000"
2348 /* 2569 */ "FLUSH\000"
2349 /* 2575 */ "DBG_PHI\000"
2350 /* 2583 */ "FPMADDXHI\000"
2351 /* 2593 */ "UMULXHI\000"
2352 /* 2601 */ "XMULXHI\000"
2353 /* 2609 */ "CAMELLIA_FLI\000"
2354 /* 2622 */ "FDTOI\000"
2355 /* 2628 */ "FQTOI\000"
2356 /* 2634 */ "FSTOI\000"
2357 /* 2640 */ "G_FPTOSI\000"
2358 /* 2649 */ "G_FPTOUI\000"
2359 /* 2658 */ "G_FPOWI\000"
2360 /* 2666 */ "BMASK\000"
2361 /* 2672 */ "COPY_LANEMASK\000"
2362 /* 2686 */ "G_PTRMASK\000"
2363 /* 2696 */ "EDGE32L\000"
2364 /* 2704 */ "EDGE16L\000"
2365 /* 2712 */ "EDGE8L\000"
2366 /* 2719 */ "FMUL8X16AL\000"
2367 /* 2730 */ "GC_LABEL\000"
2368 /* 2739 */ "DBG_LABEL\000"
2369 /* 2749 */ "EH_LABEL\000"
2370 /* 2758 */ "ANNOTATION_LABEL\000"
2371 /* 2775 */ "ICALL_BRANCH_FUNNEL\000"
2372 /* 2795 */ "CAMELLIA_FL\000"
2373 /* 2807 */ "G_FSHL\000"
2374 /* 2814 */ "G_SHL\000"
2375 /* 2820 */ "G_FCEIL\000"
2376 /* 2828 */ "G_SAVGCEIL\000"
2377 /* 2839 */ "G_UAVGCEIL\000"
2378 /* 2850 */ "PATCHABLE_TAIL_CALL\000"
2379 /* 2870 */ "TLS_CALL\000"
2380 /* 2879 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2381 /* 2906 */ "PATCHABLE_EVENT_CALL\000"
2382 /* 2927 */ "FENTRY_CALL\000"
2383 /* 2939 */ "KILL\000"
2384 /* 2944 */ "G_CONSTANT_POOL\000"
2385 /* 2960 */ "ALIGNADDRL\000"
2386 /* 2971 */ "RETL\000"
2387 /* 2976 */ "G_ROTL\000"
2388 /* 2983 */ "G_VECREDUCE_FMUL\000"
2389 /* 3000 */ "G_FMUL\000"
2390 /* 3007 */ "G_VECREDUCE_SEQ_FMUL\000"
2391 /* 3028 */ "G_STRICT_FMUL\000"
2392 /* 3042 */ "G_CLMUL\000"
2393 /* 3050 */ "MPMUL\000"
2394 /* 3056 */ "MONTMUL\000"
2395 /* 3064 */ "G_VECREDUCE_MUL\000"
2396 /* 3080 */ "G_MUL\000"
2397 /* 3086 */ "SIAM\000"
2398 /* 3091 */ "G_FREM\000"
2399 /* 3098 */ "G_STRICT_FREM\000"
2400 /* 3112 */ "G_SREM\000"
2401 /* 3119 */ "G_UREM\000"
2402 /* 3126 */ "G_SDIVREM\000"
2403 /* 3136 */ "G_UDIVREM\000"
2404 /* 3146 */ "RDWIM\000"
2405 /* 3152 */ "INLINEASM\000"
2406 /* 3162 */ "G_VECREDUCE_FMINIMUM\000"
2407 /* 3183 */ "G_FMINIMUM\000"
2408 /* 3194 */ "G_ATOMICRMW_FMINIMUM\000"
2409 /* 3215 */ "G_VECREDUCE_FMAXIMUM\000"
2410 /* 3236 */ "G_FMAXIMUM\000"
2411 /* 3247 */ "G_ATOMICRMW_FMAXIMUM\000"
2412 /* 3268 */ "G_VECREDUCE_FMINIMUMNUM\000"
2413 /* 3292 */ "G_FMINIMUMNUM\000"
2414 /* 3306 */ "G_ATOMICRMW_FMINIMUMNUM\000"
2415 /* 3330 */ "G_VECREDUCE_FMAXIMUMNUM\000"
2416 /* 3354 */ "G_FMAXIMUMNUM\000"
2417 /* 3368 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
2418 /* 3392 */ "G_FMINNUM\000"
2419 /* 3402 */ "G_FMAXNUM\000"
2420 /* 3412 */ "EDGE32N\000"
2421 /* 3420 */ "EDGE16N\000"
2422 /* 3428 */ "EDGE8N\000"
2423 /* 3435 */ "ALLCLEAN\000"
2424 /* 3444 */ "G_FATAN\000"
2425 /* 3452 */ "G_FTAN\000"
2426 /* 3459 */ "G_INTRINSIC_ROUNDEVEN\000"
2427 /* 3481 */ "G_ASSERT_ALIGN\000"
2428 /* 3496 */ "G_FCOPYSIGN\000"
2429 /* 3508 */ "G_VECREDUCE_FMIN\000"
2430 /* 3525 */ "G_ATOMICRMW_FMIN\000"
2431 /* 3542 */ "G_VECREDUCE_SMIN\000"
2432 /* 3559 */ "G_SMIN\000"
2433 /* 3566 */ "G_VECREDUCE_UMIN\000"
2434 /* 3583 */ "G_UMIN\000"
2435 /* 3590 */ "G_ATOMICRMW_UMIN\000"
2436 /* 3607 */ "G_ATOMICRMW_MIN\000"
2437 /* 3623 */ "G_FASIN\000"
2438 /* 3631 */ "G_FSIN\000"
2439 /* 3638 */ "EDGE32LN\000"
2440 /* 3647 */ "EDGE16LN\000"
2441 /* 3656 */ "EDGE8LN\000"
2442 /* 3664 */ "CFI_INSTRUCTION\000"
2443 /* 3680 */ "G_CTLZ_ZERO_POISON\000"
2444 /* 3699 */ "G_CTTZ_ZERO_POISON\000"
2445 /* 3718 */ "PDISTN\000"
2446 /* 3725 */ "ADJCALLSTACKDOWN\000"
2447 /* 3742 */ "SHUTDOWN\000"
2448 /* 3751 */ "G_SSUBO\000"
2449 /* 3759 */ "G_USUBO\000"
2450 /* 3767 */ "G_SADDO\000"
2451 /* 3775 */ "G_UADDO\000"
2452 /* 3783 */ "JUMP_TABLE_DEBUG_INFO\000"
2453 /* 3805 */ "G_SMULO\000"
2454 /* 3813 */ "G_UMULO\000"
2455 /* 3821 */ "G_BZERO\000"
2456 /* 3829 */ "FZERO\000"
2457 /* 3835 */ "STACKMAP\000"
2458 /* 3844 */ "G_DEBUGTRAP\000"
2459 /* 3856 */ "G_UBSANTRAP\000"
2460 /* 3868 */ "G_TRAP\000"
2461 /* 3875 */ "G_ATOMICRMW_UDEC_WRAP\000"
2462 /* 3897 */ "G_ATOMICRMW_UINC_WRAP\000"
2463 /* 3919 */ "G_BSWAP\000"
2464 /* 3927 */ "G_SITOFP\000"
2465 /* 3936 */ "G_UITOFP\000"
2466 /* 3945 */ "DES_IIP\000"
2467 /* 3953 */ "DES_IP\000"
2468 /* 3960 */ "G_FCMP\000"
2469 /* 3967 */ "G_STRICT_FCMP\000"
2470 /* 3981 */ "G_ICMP\000"
2471 /* 3988 */ "G_SCMP\000"
2472 /* 3995 */ "G_UCMP\000"
2473 /* 4002 */ "UNIMP\000"
2474 /* 4008 */ "NOP\000"
2475 /* 4012 */ "CONVERGENCECTRL_LOOP\000"
2476 /* 4033 */ "G_CTPOP\000"
2477 /* 4041 */ "PATCHABLE_OP\000"
2478 /* 4054 */ "FAULTING_OP\000"
2479 /* 4066 */ "ADJCALLSTACKUP\000"
2480 /* 4081 */ "PREALLOCATED_SETUP\000"
2481 /* 4100 */ "G_FLDEXP\000"
2482 /* 4109 */ "G_STRICT_FLDEXP\000"
2483 /* 4125 */ "G_FEXP\000"
2484 /* 4132 */ "G_FFREXP\000"
2485 /* 4141 */ "FSUBQ\000"
2486 /* 4147 */ "FADDQ\000"
2487 /* 4153 */ "V9FCMPEQ\000"
2488 /* 4162 */ "RDFQ\000"
2489 /* 4167 */ "FNEGQ\000"
2490 /* 4173 */ "FDMULQ\000"
2491 /* 4180 */ "FMULQ\000"
2492 /* 4186 */ "FDTOQ\000"
2493 /* 4192 */ "FITOQ\000"
2494 /* 4198 */ "FSTOQ\000"
2495 /* 4204 */ "FXTOQ\000"
2496 /* 4210 */ "V9FCMPQ\000"
2497 /* 4218 */ "FMOVRQ\000"
2498 /* 4225 */ "FABSQ\000"
2499 /* 4231 */ "FSQRTQ\000"
2500 /* 4238 */ "FDIVQ\000"
2501 /* 4244 */ "FMOVQ\000"
2502 /* 4250 */ "V8BAR\000"
2503 /* 4256 */ "STBAR\000"
2504 /* 4262 */ "RDTBR\000"
2505 /* 4268 */ "G_BR\000"
2506 /* 4273 */ "INLINEASM_BR\000"
2507 /* 4286 */ "ALIGNADDR\000"
2508 /* 4296 */ "G_BLOCK_ADDR\000"
2509 /* 4309 */ "MEMBARRIER\000"
2510 /* 4320 */ "G_CONSTANT_FOLD_BARRIER\000"
2511 /* 4344 */ "PATCHABLE_FUNCTION_ENTER\000"
2512 /* 4369 */ "G_READCYCLECOUNTER\000"
2513 /* 4388 */ "G_READSTEADYCOUNTER\000"
2514 /* 4408 */ "G_READ_REGISTER\000"
2515 /* 4424 */ "G_WRITE_REGISTER\000"
2516 /* 4441 */ "G_ASHR\000"
2517 /* 4448 */ "G_FSHR\000"
2518 /* 4455 */ "G_LSHR\000"
2519 /* 4462 */ "SIR\000"
2520 /* 4466 */ "FOR\000"
2521 /* 4470 */ "CONVERGENCECTRL_ANCHOR\000"
2522 /* 4493 */ "FNOR\000"
2523 /* 4498 */ "FXNOR\000"
2524 /* 4504 */ "G_FFLOOR\000"
2525 /* 4513 */ "G_SAVGFLOOR\000"
2526 /* 4525 */ "G_UAVGFLOOR\000"
2527 /* 4537 */ "G_EXTRACT_SUBVECTOR\000"
2528 /* 4557 */ "G_INSERT_SUBVECTOR\000"
2529 /* 4576 */ "G_BUILD_VECTOR\000"
2530 /* 4591 */ "G_SHUFFLE_VECTOR\000"
2531 /* 4608 */ "G_STEP_VECTOR\000"
2532 /* 4622 */ "G_SPLAT_VECTOR\000"
2533 /* 4637 */ "FXOR\000"
2534 /* 4642 */ "G_VECREDUCE_XOR\000"
2535 /* 4658 */ "G_XOR\000"
2536 /* 4664 */ "G_ATOMICRMW_XOR\000"
2537 /* 4680 */ "G_VECREDUCE_OR\000"
2538 /* 4695 */ "G_OR\000"
2539 /* 4700 */ "G_ATOMICRMW_OR\000"
2540 /* 4715 */ "BPR\000"
2541 /* 4719 */ "RDPR\000"
2542 /* 4724 */ "MONTSQR\000"
2543 /* 4732 */ "RDASR\000"
2544 /* 4738 */ "RDPSR\000"
2545 /* 4744 */ "G_ROTR\000"
2546 /* 4751 */ "G_INTTOPTR\000"
2547 /* 4762 */ "FSRC1S\000"
2548 /* 4769 */ "FANDNOT1S\000"
2549 /* 4779 */ "FNOT1S\000"
2550 /* 4786 */ "FORNOT1S\000"
2551 /* 4795 */ "FPSUB32S\000"
2552 /* 4804 */ "FPADD32S\000"
2553 /* 4813 */ "FSRC2S\000"
2554 /* 4820 */ "FANDNOT2S\000"
2555 /* 4830 */ "FNOT2S\000"
2556 /* 4837 */ "FORNOT2S\000"
2557 /* 4846 */ "FPSUB16S\000"
2558 /* 4855 */ "FPADD16S\000"
2559 /* 4864 */ "G_FABS\000"
2560 /* 4871 */ "G_ABS\000"
2561 /* 4877 */ "FSUBS\000"
2562 /* 4883 */ "FHSUBS\000"
2563 /* 4890 */ "FMSUBS\000"
2564 /* 4897 */ "FNMSUBS\000"
2565 /* 4905 */ "G_ABDS\000"
2566 /* 4912 */ "FADDS\000"
2567 /* 4918 */ "FHADDS\000"
2568 /* 4925 */ "FNHADDS\000"
2569 /* 4933 */ "FMADDS\000"
2570 /* 4940 */ "FNMADDS\000"
2571 /* 4948 */ "FNADDS\000"
2572 /* 4955 */ "FANDS\000"
2573 /* 4961 */ "FNANDS\000"
2574 /* 4968 */ "FONES\000"
2575 /* 4974 */ "V9FCMPES\000"
2576 /* 4983 */ "G_UNMERGE_VALUES\000"
2577 /* 5000 */ "G_MERGE_VALUES\000"
2578 /* 5015 */ "FNEGS\000"
2579 /* 5021 */ "G_CTLS\000"
2580 /* 5028 */ "FMULS\000"
2581 /* 5034 */ "FNMULS\000"
2582 /* 5041 */ "G_FACOS\000"
2583 /* 5049 */ "G_FCOS\000"
2584 /* 5056 */ "G_FSINCOS\000"
2585 /* 5066 */ "FZEROS\000"
2586 /* 5073 */ "FDTOS\000"
2587 /* 5079 */ "FITOS\000"
2588 /* 5085 */ "FQTOS\000"
2589 /* 5091 */ "MOVWTOS\000"
2590 /* 5099 */ "FXTOS\000"
2591 /* 5105 */ "V9FCMPS\000"
2592 /* 5113 */ "G_STRICT_FCMPS\000"
2593 /* 5128 */ "FLCMPS\000"
2594 /* 5135 */ "FORS\000"
2595 /* 5140 */ "FNORS\000"
2596 /* 5146 */ "FXNORS\000"
2597 /* 5153 */ "G_CONCAT_VECTORS\000"
2598 /* 5170 */ "FXORS\000"
2599 /* 5176 */ "FMOVRS\000"
2600 /* 5183 */ "COPY_TO_REGCLASS\000"
2601 /* 5200 */ "G_IS_FPCLASS\000"
2602 /* 5213 */ "FABSS\000"
2603 /* 5219 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2604 /* 5249 */ "G_VECTOR_COMPRESS\000"
2605 /* 5267 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2606 /* 5294 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2607 /* 5332 */ "FSQRTS\000"
2608 /* 5339 */ "FDIVS\000"
2609 /* 5345 */ "FMOVS\000"
2610 /* 5351 */ "G_TRUNC_SSAT_S\000"
2611 /* 5366 */ "G_SSUBSAT\000"
2612 /* 5376 */ "G_USUBSAT\000"
2613 /* 5386 */ "G_SADDSAT\000"
2614 /* 5396 */ "G_UADDSAT\000"
2615 /* 5406 */ "G_SSHLSAT\000"
2616 /* 5416 */ "G_USHLSAT\000"
2617 /* 5426 */ "G_SMULFIXSAT\000"
2618 /* 5439 */ "G_UMULFIXSAT\000"
2619 /* 5452 */ "G_SDIVFIXSAT\000"
2620 /* 5465 */ "G_UDIVFIXSAT\000"
2621 /* 5478 */ "G_ATOMICRMW_USUB_SAT\000"
2622 /* 5499 */ "G_FPTOSI_SAT\000"
2623 /* 5512 */ "G_FPTOUI_SAT\000"
2624 /* 5525 */ "G_EXTRACT\000"
2625 /* 5535 */ "G_SELECT\000"
2626 /* 5544 */ "G_BRINDIRECT\000"
2627 /* 5557 */ "PATCHABLE_RET\000"
2628 /* 5571 */ "G_MEMSET\000"
2629 /* 5580 */ "PATCHABLE_FUNCTION_EXIT\000"
2630 /* 5604 */ "G_BRJT\000"
2631 /* 5611 */ "G_EXTRACT_VECTOR_ELT\000"
2632 /* 5632 */ "G_INSERT_VECTOR_ELT\000"
2633 /* 5652 */ "BPFCCANT\000"
2634 /* 5661 */ "BPICCANT\000"
2635 /* 5670 */ "BPXCCANT\000"
2636 /* 5679 */ "BPRANT\000"
2637 /* 5686 */ "G_FCONSTANT\000"
2638 /* 5698 */ "G_CONSTANT\000"
2639 /* 5709 */ "BPFCCNT\000"
2640 /* 5717 */ "BPICCNT\000"
2641 /* 5725 */ "BPXCCNT\000"
2642 /* 5733 */ "LZCNT\000"
2643 /* 5739 */ "G_INTRINSIC_CONVERGENT\000"
2644 /* 5762 */ "STATEPOINT\000"
2645 /* 5773 */ "PATCHPOINT\000"
2646 /* 5784 */ "G_PTRTOINT\000"
2647 /* 5795 */ "G_FRINT\000"
2648 /* 5803 */ "G_INTRINSIC_LLRINT\000"
2649 /* 5822 */ "G_INTRINSIC_LRINT\000"
2650 /* 5840 */ "G_FNEARBYINT\000"
2651 /* 5853 */ "BPRNT\000"
2652 /* 5859 */ "G_VASTART\000"
2653 /* 5869 */ "LIFETIME_START\000"
2654 /* 5884 */ "G_INVOKE_REGION_START\000"
2655 /* 5906 */ "G_INSERT\000"
2656 /* 5915 */ "G_FSQRT\000"
2657 /* 5923 */ "G_STRICT_FSQRT\000"
2658 /* 5938 */ "G_BITCAST\000"
2659 /* 5948 */ "G_ADDRSPACE_CAST\000"
2660 /* 5965 */ "AES_DROUND01_LAST\000"
2661 /* 5983 */ "AES_EROUND01_LAST\000"
2662 /* 6001 */ "AES_DROUND23_LAST\000"
2663 /* 6019 */ "AES_EROUND23_LAST\000"
2664 /* 6037 */ "PDIST\000"
2665 /* 6043 */ "DBG_VALUE_LIST\000"
2666 /* 6058 */ "G_FPEXT\000"
2667 /* 6066 */ "G_SEXT\000"
2668 /* 6073 */ "G_ASSERT_SEXT\000"
2669 /* 6087 */ "G_ANYEXT\000"
2670 /* 6096 */ "G_ZEXT\000"
2671 /* 6103 */ "G_ASSERT_ZEXT\000"
2672 /* 6117 */ "FMUL8X16AU\000"
2673 /* 6128 */ "G_ABDU\000"
2674 /* 6135 */ "G_TRUNC_SSAT_U\000"
2675 /* 6150 */ "G_TRUNC_USAT_U\000"
2676 /* 6165 */ "G_FDIV\000"
2677 /* 6172 */ "G_STRICT_FDIV\000"
2678 /* 6186 */ "G_SDIV\000"
2679 /* 6193 */ "G_UDIV\000"
2680 /* 6200 */ "G_GET_FPENV\000"
2681 /* 6212 */ "G_RESET_FPENV\000"
2682 /* 6226 */ "G_SET_FPENV\000"
2683 /* 6238 */ "FLUSHW\000"
2684 /* 6245 */ "NORMALW\000"
2685 /* 6253 */ "INVALW\000"
2686 /* 6260 */ "G_FPOW\000"
2687 /* 6267 */ "OTHERW\000"
2688 /* 6274 */ "MOVSTOSW\000"
2689 /* 6283 */ "SETSW\000"
2690 /* 6289 */ "MOVSTOUW\000"
2691 /* 6298 */ "G_VECREDUCE_FMAX\000"
2692 /* 6315 */ "G_ATOMICRMW_FMAX\000"
2693 /* 6332 */ "G_VECREDUCE_SMAX\000"
2694 /* 6349 */ "G_SMAX\000"
2695 /* 6356 */ "G_VECREDUCE_UMAX\000"
2696 /* 6373 */ "G_UMAX\000"
2697 /* 6380 */ "G_ATOMICRMW_UMAX\000"
2698 /* 6397 */ "G_ATOMICRMW_MAX\000"
2699 /* 6413 */ "GETPCX\000"
2700 /* 6420 */ "FPMADDX\000"
2701 /* 6428 */ "G_FRAME_INDEX\000"
2702 /* 6442 */ "G_SBFX\000"
2703 /* 6449 */ "G_UBFX\000"
2704 /* 6456 */ "FPACKFIX\000"
2705 /* 6465 */ "G_SMULFIX\000"
2706 /* 6475 */ "G_UMULFIX\000"
2707 /* 6485 */ "G_SDIVFIX\000"
2708 /* 6495 */ "G_UDIVFIX\000"
2709 /* 6505 */ "XMULX\000"
2710 /* 6511 */ "FDTOX\000"
2711 /* 6517 */ "MOVDTOX\000"
2712 /* 6525 */ "FQTOX\000"
2713 /* 6531 */ "FSTOX\000"
2714 /* 6537 */ "SETX\000"
2715 /* 6542 */ "G_MEMCPY\000"
2716 /* 6551 */ "COPY\000"
2717 /* 6556 */ "RETRY\000"
2718 /* 6562 */ "CONVERGENCECTRL_ENTRY\000"
2719 /* 6584 */ "G_CTLZ\000"
2720 /* 6591 */ "G_CTTZ\000"
2721 /* 6598 */ "PREFETCHAi\000"
2722 /* 6609 */ "PREFETCHi\000"
2723 /* 6619 */ "SETHIi\000"
2724 /* 6626 */ "CALLi\000"
2725 /* 6632 */ "MEMBARi\000"
2726 /* 6640 */ "CALLrii\000"
2727 /* 6648 */ "LDSBAri\000"
2728 /* 6656 */ "STBAri\000"
2729 /* 6663 */ "LDUBAri\000"
2730 /* 6671 */ "LDSTUBAri\000"
2731 /* 6681 */ "LDDAri\000"
2732 /* 6688 */ "LDAri\000"
2733 /* 6694 */ "STDAri\000"
2734 /* 6701 */ "LDDFAri\000"
2735 /* 6709 */ "LDFAri\000"
2736 /* 6716 */ "STDFAri\000"
2737 /* 6724 */ "LDQFAri\000"
2738 /* 6732 */ "STQFAri\000"
2739 /* 6740 */ "STFAri\000"
2740 /* 6747 */ "LDSHAri\000"
2741 /* 6755 */ "STHAri\000"
2742 /* 6762 */ "LDUHAri\000"
2743 /* 6770 */ "SWAPAri\000"
2744 /* 6778 */ "SRAri\000"
2745 /* 6784 */ "CASAri\000"
2746 /* 6791 */ "STAri\000"
2747 /* 6797 */ "LDSWAri\000"
2748 /* 6805 */ "LDXAri\000"
2749 /* 6812 */ "CASXAri\000"
2750 /* 6820 */ "STXAri\000"
2751 /* 6827 */ "LDSBri\000"
2752 /* 6834 */ "STBri\000"
2753 /* 6840 */ "LDUBri\000"
2754 /* 6847 */ "SUBri\000"
2755 /* 6853 */ "LDSTUBri\000"
2756 /* 6862 */ "SMACri\000"
2757 /* 6869 */ "UMACri\000"
2758 /* 6876 */ "SUBCri\000"
2759 /* 6883 */ "TSUBCCri\000"
2760 /* 6892 */ "TADDCCri\000"
2761 /* 6901 */ "ANDCCri\000"
2762 /* 6909 */ "V9MOVFCCri\000"
2763 /* 6920 */ "TICCri\000"
2764 /* 6927 */ "MOVICCri\000"
2765 /* 6936 */ "SMULCCri\000"
2766 /* 6945 */ "UMULCCri\000"
2767 /* 6954 */ "ANDNCCri\000"
2768 /* 6963 */ "ORNCCri\000"
2769 /* 6971 */ "XNORCCri\000"
2770 /* 6980 */ "XORCCri\000"
2771 /* 6988 */ "MULSCCri\000"
2772 /* 6997 */ "SDIVCCri\000"
2773 /* 7006 */ "UDIVCCri\000"
2774 /* 7015 */ "TXCCri\000"
2775 /* 7022 */ "MOVXCCri\000"
2776 /* 7031 */ "ADDCri\000"
2777 /* 7038 */ "LDDCri\000"
2778 /* 7045 */ "LDCri\000"
2779 /* 7051 */ "STDCri\000"
2780 /* 7058 */ "STCri\000"
2781 /* 7064 */ "ADDri\000"
2782 /* 7070 */ "LDDri\000"
2783 /* 7076 */ "LDri\000"
2784 /* 7081 */ "ANDri\000"
2785 /* 7087 */ "BINDri\000"
2786 /* 7094 */ "CWBCONDri\000"
2787 /* 7104 */ "CXBCONDri\000"
2788 /* 7114 */ "STDri\000"
2789 /* 7120 */ "SUBEri\000"
2790 /* 7127 */ "ADDEri\000"
2791 /* 7134 */ "RESTOREri\000"
2792 /* 7144 */ "SAVEri\000"
2793 /* 7151 */ "LDDFri\000"
2794 /* 7158 */ "LDFri\000"
2795 /* 7164 */ "STDFri\000"
2796 /* 7171 */ "LDQFri\000"
2797 /* 7178 */ "STQFri\000"
2798 /* 7185 */ "STFri\000"
2799 /* 7191 */ "LDSHri\000"
2800 /* 7198 */ "FLUSHri\000"
2801 /* 7206 */ "STHri\000"
2802 /* 7212 */ "LDUHri\000"
2803 /* 7219 */ "TAIL_CALLri\000"
2804 /* 7231 */ "SLLri\000"
2805 /* 7237 */ "JMPLri\000"
2806 /* 7244 */ "SRLri\000"
2807 /* 7250 */ "SMULri\000"
2808 /* 7257 */ "UMULri\000"
2809 /* 7264 */ "WRWIMri\000"
2810 /* 7272 */ "ANDNri\000"
2811 /* 7279 */ "ORNri\000"
2812 /* 7285 */ "TRAPri\000"
2813 /* 7292 */ "SWAPri\000"
2814 /* 7299 */ "STDCQri\000"
2815 /* 7307 */ "STDFQri\000"
2816 /* 7315 */ "WRTBRri\000"
2817 /* 7323 */ "XNORri\000"
2818 /* 7330 */ "XORri\000"
2819 /* 7336 */ "WRPRri\000"
2820 /* 7343 */ "WRASRri\000"
2821 /* 7351 */ "LDCSRri\000"
2822 /* 7359 */ "STCSRri\000"
2823 /* 7367 */ "LDFSRri\000"
2824 /* 7375 */ "STFSRri\000"
2825 /* 7383 */ "LDXFSRri\000"
2826 /* 7392 */ "STXFSRri\000"
2827 /* 7401 */ "PWRPSRri\000"
2828 /* 7410 */ "MOVRri\000"
2829 /* 7417 */ "STri\000"
2830 /* 7422 */ "RETTri\000"
2831 /* 7429 */ "SDIVri\000"
2832 /* 7436 */ "UDIVri\000"
2833 /* 7443 */ "TSUBCCTVri\000"
2834 /* 7454 */ "TADDCCTVri\000"
2835 /* 7465 */ "LDSWri\000"
2836 /* 7472 */ "SRAXri\000"
2837 /* 7479 */ "LDXri\000"
2838 /* 7485 */ "SLLXri\000"
2839 /* 7492 */ "SRLXri\000"
2840 /* 7499 */ "MULXri\000"
2841 /* 7506 */ "STXri\000"
2842 /* 7512 */ "SDIVXri\000"
2843 /* 7520 */ "UDIVXri\000"
2844 /* 7528 */ "CALLrri\000"
2845 /* 7536 */ "PREFETCHAr\000"
2846 /* 7547 */ "PREFETCHr\000"
2847 /* 7557 */ "LDSBArr\000"
2848 /* 7565 */ "STBArr\000"
2849 /* 7572 */ "LDUBArr\000"
2850 /* 7580 */ "LDSTUBArr\000"
2851 /* 7590 */ "LDDArr\000"
2852 /* 7597 */ "LDArr\000"
2853 /* 7603 */ "STDArr\000"
2854 /* 7610 */ "LDDFArr\000"
2855 /* 7618 */ "LDFArr\000"
2856 /* 7625 */ "STDFArr\000"
2857 /* 7633 */ "LDQFArr\000"
2858 /* 7641 */ "STQFArr\000"
2859 /* 7649 */ "STFArr\000"
2860 /* 7656 */ "LDSHArr\000"
2861 /* 7664 */ "STHArr\000"
2862 /* 7671 */ "LDUHArr\000"
2863 /* 7679 */ "SWAPArr\000"
2864 /* 7687 */ "SRArr\000"
2865 /* 7693 */ "CASArr\000"
2866 /* 7700 */ "STArr\000"
2867 /* 7706 */ "LDSWArr\000"
2868 /* 7714 */ "LDXArr\000"
2869 /* 7721 */ "CASXArr\000"
2870 /* 7729 */ "STXArr\000"
2871 /* 7736 */ "LDSBrr\000"
2872 /* 7743 */ "STBrr\000"
2873 /* 7749 */ "LDUBrr\000"
2874 /* 7756 */ "SUBrr\000"
2875 /* 7762 */ "LDSTUBrr\000"
2876 /* 7771 */ "SMACrr\000"
2877 /* 7778 */ "UMACrr\000"
2878 /* 7785 */ "SUBCrr\000"
2879 /* 7792 */ "TSUBCCrr\000"
2880 /* 7801 */ "TADDCCrr\000"
2881 /* 7810 */ "ANDCCrr\000"
2882 /* 7818 */ "V9MOVFCCrr\000"
2883 /* 7829 */ "TICCrr\000"
2884 /* 7836 */ "MOVICCrr\000"
2885 /* 7845 */ "SMULCCrr\000"
2886 /* 7854 */ "UMULCCrr\000"
2887 /* 7863 */ "ANDNCCrr\000"
2888 /* 7872 */ "ORNCCrr\000"
2889 /* 7880 */ "XNORCCrr\000"
2890 /* 7889 */ "XORCCrr\000"
2891 /* 7897 */ "MULSCCrr\000"
2892 /* 7906 */ "SDIVCCrr\000"
2893 /* 7915 */ "UDIVCCrr\000"
2894 /* 7924 */ "TXCCrr\000"
2895 /* 7931 */ "MOVXCCrr\000"
2896 /* 7940 */ "ADDCrr\000"
2897 /* 7947 */ "LDDCrr\000"
2898 /* 7954 */ "LDCrr\000"
2899 /* 7960 */ "STDCrr\000"
2900 /* 7967 */ "POPCrr\000"
2901 /* 7974 */ "STCrr\000"
2902 /* 7980 */ "TLS_ADDrr\000"
2903 /* 7990 */ "LDDrr\000"
2904 /* 7996 */ "GDOP_LDrr\000"
2905 /* 8006 */ "TLS_LDrr\000"
2906 /* 8015 */ "ANDrr\000"
2907 /* 8021 */ "BINDrr\000"
2908 /* 8028 */ "CWBCONDrr\000"
2909 /* 8038 */ "CXBCONDrr\000"
2910 /* 8048 */ "STDrr\000"
2911 /* 8054 */ "SUBErr\000"
2912 /* 8061 */ "ADDErr\000"
2913 /* 8068 */ "RESTORErr\000"
2914 /* 8078 */ "SAVErr\000"
2915 /* 8085 */ "LDDFrr\000"
2916 /* 8092 */ "LDFrr\000"
2917 /* 8098 */ "STDFrr\000"
2918 /* 8105 */ "LDQFrr\000"
2919 /* 8112 */ "STQFrr\000"
2920 /* 8119 */ "STFrr\000"
2921 /* 8125 */ "LDSHrr\000"
2922 /* 8132 */ "FLUSHrr\000"
2923 /* 8140 */ "STHrr\000"
2924 /* 8146 */ "LDUHrr\000"
2925 /* 8153 */ "CALLrr\000"
2926 /* 8160 */ "SLLrr\000"
2927 /* 8166 */ "JMPLrr\000"
2928 /* 8173 */ "SRLrr\000"
2929 /* 8179 */ "SMULrr\000"
2930 /* 8186 */ "UMULrr\000"
2931 /* 8193 */ "WRWIMrr\000"
2932 /* 8201 */ "ANDNrr\000"
2933 /* 8208 */ "ORNrr\000"
2934 /* 8214 */ "TRAPrr\000"
2935 /* 8221 */ "SWAPrr\000"
2936 /* 8228 */ "STDCQrr\000"
2937 /* 8236 */ "STDFQrr\000"
2938 /* 8244 */ "WRTBRrr\000"
2939 /* 8252 */ "XNORrr\000"
2940 /* 8259 */ "XORrr\000"
2941 /* 8265 */ "WRPRrr\000"
2942 /* 8272 */ "WRASRrr\000"
2943 /* 8280 */ "LDCSRrr\000"
2944 /* 8288 */ "STCSRrr\000"
2945 /* 8296 */ "LDFSRrr\000"
2946 /* 8304 */ "STFSRrr\000"
2947 /* 8312 */ "LDXFSRrr\000"
2948 /* 8321 */ "STXFSRrr\000"
2949 /* 8330 */ "PWRPSRrr\000"
2950 /* 8339 */ "MOVRrr\000"
2951 /* 8346 */ "STrr\000"
2952 /* 8351 */ "RETTrr\000"
2953 /* 8358 */ "SDIVrr\000"
2954 /* 8365 */ "UDIVrr\000"
2955 /* 8372 */ "TSUBCCTVrr\000"
2956 /* 8383 */ "TADDCCTVrr\000"
2957 /* 8394 */ "LDSWrr\000"
2958 /* 8401 */ "SRAXrr\000"
2959 /* 8408 */ "GDOP_LDXrr\000"
2960 /* 8419 */ "TLS_LDXrr\000"
2961 /* 8429 */ "SLLXrr\000"
2962 /* 8436 */ "SRLXrr\000"
2963 /* 8443 */ "MULXrr\000"
2964 /* 8450 */ "STXrr\000"
2965 /* 8456 */ "SDIVXrr\000"
2966 /* 8464 */ "UDIVXrr\000"
2967};
2968#ifdef __GNUC__
2969#pragma GCC diagnostic pop
2970#endif
2971
2972extern const unsigned SparcInstrNameIndices[] = {
2973 2579U, 3152U, 4273U, 3664U, 2749U, 2730U, 2758U, 2939U,
2974 2357U, 2372U, 2312U, 2299U, 2399U, 5183U, 2175U, 6043U,
2975 2325U, 2575U, 2739U, 1887U, 6551U, 2672U, 2017U, 5869U,
2976 1610U, 1838U, 1875U, 3835U, 2927U, 5773U, 1789U, 4081U,
2977 2492U, 5762U, 2086U, 4054U, 4041U, 4344U, 5557U, 5580U,
2978 2850U, 2906U, 2879U, 2775U, 2166U, 4309U, 3783U, 2075U,
2979 6562U, 4470U, 4012U, 2223U, 6073U, 6103U, 3481U, 1391U,
2980 714U, 3080U, 6186U, 6193U, 3112U, 3119U, 3126U, 3136U,
2981 1588U, 4695U, 4658U, 4905U, 6128U, 4525U, 2839U, 4513U,
2982 2828U, 2310U, 2577U, 6428U, 2185U, 2200U, 2944U, 5525U,
2983 4983U, 5906U, 5000U, 4576U, 1126U, 5153U, 5784U, 4751U,
2984 5938U, 2266U, 4320U, 1706U, 1100U, 1688U, 5822U, 5803U,
2985 3459U, 4369U, 4388U, 1264U, 1208U, 1238U, 1177U, 1249U,
2986 1189U, 1219U, 2145U, 2099U, 2129U, 5219U, 2413U, 2430U,
2987 1407U, 720U, 1594U, 1535U, 4700U, 4664U, 6397U, 3607U,
2988 6380U, 3590U, 1358U, 697U, 6315U, 3525U, 3247U, 3194U,
2989 3368U, 3306U, 3897U, 3875U, 1647U, 5478U, 1867U, 2509U,
2990 1638U, 5544U, 5884U, 1078U, 5267U, 5739U, 5294U, 6087U,
2991 1118U, 5351U, 6135U, 6150U, 5698U, 5686U, 5859U, 2484U,
2992 6066U, 2386U, 6096U, 2814U, 4455U, 4441U, 2807U, 4448U,
2993 4744U, 2976U, 3981U, 3960U, 3988U, 3995U, 5535U, 3775U,
2994 1908U, 3759U, 1859U, 3767U, 1900U, 3751U, 1851U, 3813U,
2995 3805U, 2537U, 2529U, 5396U, 5386U, 5376U, 5366U, 5416U,
2996 5406U, 6465U, 6475U, 5426U, 5439U, 6485U, 6495U, 5452U,
2997 5465U, 1316U, 676U, 3000U, 640U, 1170U, 6165U, 3091U,
2998 2291U, 6260U, 2658U, 4125U, 263U, 9U, 2477U, 246U,
2999 0U, 4100U, 4132U, 2350U, 6058U, 1090U, 2640U, 2649U,
3000 3927U, 3936U, 5499U, 5512U, 4864U, 3496U, 5200U, 2275U,
3001 3392U, 3402U, 1957U, 1972U, 3183U, 3236U, 3292U, 3354U,
3002 6200U, 6226U, 6212U, 1916U, 1944U, 1929U, 2447U, 2462U,
3003 1397U, 2686U, 3559U, 6349U, 3583U, 6373U, 4871U, 1679U,
3004 1669U, 4268U, 5604U, 1995U, 4557U, 4537U, 5632U, 5611U,
3005 4591U, 4622U, 4608U, 5249U, 6591U, 3699U, 6584U, 3680U,
3006 5021U, 4033U, 3919U, 2153U, 3042U, 2520U, 2820U, 5049U,
3007 3631U, 5056U, 3452U, 5041U, 3623U, 3444U, 254U, 2561U,
3008 2553U, 2545U, 5915U, 4504U, 5795U, 5840U, 5948U, 4296U,
3009 2004U, 1147U, 2244U, 2114U, 1344U, 683U, 3028U, 6172U,
3010 3098U, 646U, 5923U, 4109U, 3967U, 5113U, 4408U, 4424U,
3011 6542U, 2049U, 2256U, 5571U, 3821U, 2033U, 3868U, 3844U,
3012 3856U, 1323U, 3007U, 1299U, 2983U, 6298U, 3508U, 3215U,
3013 3162U, 3330U, 3268U, 1375U, 3064U, 1572U, 4680U, 4642U,
3014 6332U, 3542U, 6356U, 3566U, 6442U, 6449U, 3725U, 4066U,
3015 6413U, 769U, 880U, 987U, 805U, 916U, 1023U, 846U,
3016 953U, 1060U, 787U, 898U, 1005U, 5576U, 6283U, 6537U,
3017 4250U, 6893U, 7802U, 7031U, 7940U, 7127U, 8061U, 1164U,
3018 743U, 7064U, 7984U, 31U, 5965U, 294U, 6001U, 44U,
3019 5983U, 307U, 6019U, 18U, 72U, 233U, 4286U, 2960U,
3020 3435U, 6901U, 7810U, 6954U, 7863U, 7272U, 8201U, 7081U,
3021 8015U, 516U, 219U, 544U, 599U, 1624U, 624U, 7087U,
3022 8021U, 2666U, 751U, 602U, 5652U, 5709U, 864U, 609U,
3023 5661U, 5717U, 4715U, 659U, 5679U, 5853U, 971U, 616U,
3024 5670U, 5725U, 2024U, 2865U, 6626U, 7224U, 6640U, 8153U,
3025 7528U, 2339U, 2795U, 2609U, 6784U, 7693U, 6812U, 7721U,
3026 396U, 171U, 537U, 1630U, 631U, 736U, 7094U, 8028U,
3027 7104U, 8038U, 3945U, 3953U, 1560U, 1732U, 2065U, 363U,
3028 2704U, 3647U, 3420U, 138U, 2696U, 3638U, 3412U, 531U,
3029 2712U, 3656U, 3428U, 1813U, 4225U, 5213U, 1423U, 4147U,
3030 4912U, 664U, 1524U, 85U, 4769U, 271U, 4820U, 4955U,
3031 1623U, 623U, 551U, 562U, 418U, 1776U, 572U, 435U,
3032 193U, 452U, 210U, 370U, 145U, 379U, 154U, 4212U,
3033 581U, 5107U, 590U, 1826U, 4238U, 5339U, 4173U, 2622U,
3034 4186U, 5073U, 6511U, 1552U, 1429U, 4918U, 1277U, 4883U,
3035 1742U, 4192U, 5079U, 1782U, 5128U, 2569U, 6238U, 7198U,
3036 8132U, 1444U, 4933U, 427U, 1832U, 759U, 870U, 977U,
3037 4244U, 824U, 933U, 1040U, 1806U, 4218U, 5176U, 5345U,
3038 836U, 943U, 1050U, 1284U, 4890U, 505U, 482U, 461U,
3039 2719U, 6117U, 1496U, 493U, 470U, 4180U, 5028U, 1459U,
3040 4948U, 1529U, 4961U, 1490U, 4167U, 5015U, 1436U, 4925U,
3041 1451U, 4940U, 1291U, 4897U, 1502U, 5034U, 4493U, 5140U,
3042 94U, 4779U, 280U, 4830U, 1516U, 2070U, 4968U, 4466U,
3043 100U, 4786U, 286U, 4837U, 5135U, 388U, 163U, 6456U,
3044 355U, 4855U, 130U, 4804U, 324U, 6420U, 2583U, 1987U,
3045 347U, 4846U, 122U, 4795U, 1748U, 2628U, 5085U, 6525U,
3046 444U, 202U, 404U, 179U, 1509U, 1819U, 4231U, 5332U,
3047 340U, 115U, 66U, 4762U, 227U, 4813U, 411U, 186U,
3048 1754U, 2634U, 4198U, 6531U, 1271U, 4141U, 4877U, 4498U,
3049 5146U, 4637U, 5170U, 1760U, 4204U, 5099U, 3829U, 5066U,
3050 8408U, 7996U, 6253U, 7237U, 8166U, 6688U, 7597U, 7351U,
3051 8280U, 7045U, 7954U, 6681U, 7590U, 7038U, 7947U, 6701U,
3052 7610U, 7151U, 8085U, 7070U, 7990U, 6709U, 7618U, 7367U,
3053 8296U, 7158U, 8092U, 6724U, 7633U, 7171U, 8105U, 6648U,
3054 7557U, 6827U, 7736U, 6747U, 7656U, 7191U, 8125U, 6671U,
3055 7580U, 6853U, 7762U, 6797U, 7706U, 7465U, 8394U, 6663U,
3056 7572U, 6840U, 7749U, 6762U, 7671U, 7212U, 8146U, 6805U,
3057 7714U, 7383U, 8312U, 7479U, 8413U, 7076U, 8001U, 5733U,
3058 336U, 6632U, 3056U, 4724U, 6517U, 6911U, 7820U, 6927U,
3059 7836U, 7410U, 8339U, 6274U, 6289U, 5091U, 7022U, 7931U,
3060 1766U, 3050U, 6988U, 7897U, 7499U, 8443U, 4008U, 6245U,
3061 6973U, 7882U, 6963U, 7872U, 7279U, 8208U, 7325U, 8254U,
3062 6267U, 6037U, 3718U, 7967U, 6598U, 7536U, 6609U, 7547U,
3063 7401U, 8330U, 4732U, 4162U, 4719U, 4738U, 4262U, 3146U,
3064 1475U, 7134U, 8068U, 5567U, 2971U, 6556U, 7422U, 8351U,
3065 1484U, 7144U, 8078U, 6997U, 7906U, 7512U, 8456U, 7429U,
3066 8358U, 6619U, 57U, 524U, 108U, 3742U, 3086U, 4462U,
3067 7485U, 8429U, 7231U, 8160U, 6862U, 7771U, 6936U, 7845U,
3068 7250U, 8179U, 7472U, 8401U, 6778U, 7687U, 7492U, 8436U,
3069 7244U, 8173U, 6791U, 7700U, 4256U, 6656U, 7565U, 6834U,
3070 7743U, 7359U, 8288U, 7058U, 7974U, 6694U, 7603U, 7299U,
3071 8228U, 7051U, 7960U, 6716U, 7625U, 7307U, 8236U, 7164U,
3072 8098U, 7114U, 8048U, 6740U, 7649U, 7375U, 8304U, 7185U,
3073 8119U, 6755U, 7664U, 7206U, 8140U, 6732U, 7641U, 7178U,
3074 8112U, 6820U, 7729U, 7392U, 8321U, 7506U, 8450U, 7417U,
3075 8346U, 6884U, 7793U, 6876U, 7785U, 7120U, 8054U, 6847U,
3076 7756U, 6770U, 7679U, 7292U, 8221U, 62U, 320U, 332U,
3077 7454U, 8383U, 6892U, 7801U, 2860U, 7219U, 6920U, 7829U,
3078 7980U, 2870U, 8419U, 8006U, 7285U, 8214U, 7443U, 8372U,
3079 6883U, 7792U, 7015U, 7924U, 7006U, 7915U, 7520U, 8464U,
3080 7436U, 8365U, 6869U, 7778U, 6945U, 7854U, 2593U, 7257U,
3081 8186U, 4002U, 1774U, 1466U, 4153U, 4974U, 4210U, 5105U,
3082 757U, 822U, 834U, 6909U, 7818U, 7343U, 8272U, 7336U,
3083 8265U, 7402U, 8331U, 7315U, 8244U, 7264U, 8193U, 6505U,
3084 2601U, 6971U, 7880U, 7323U, 8252U, 6980U, 7889U, 7330U,
3085 8259U,
3086};
3087
3088extern const int16_t SparcRegClassByHwModeTables[2][1] = {
3089 { // DefaultMode
3090 SP::IntRegsRegClassID, // sparc_ptr_rc
3091 },
3092 { // SPARC64
3093 SP::I64RegsRegClassID, // sparc_ptr_rc
3094 },
3095};
3096
3097static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
3098 II->InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 897, &SparcRegClassByHwModeTables[0][0], 1);
3099}
3100
3101
3102} // namespace llvm
3103
3104#endif // GET_INSTRINFO_MC_DESC
3105
3106#ifdef GET_INSTRINFO_HEADER
3107#undef GET_INSTRINFO_HEADER
3108
3109namespace llvm {
3110
3111struct SparcGenInstrInfo : public TargetInstrInfo {
3112 explicit SparcGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
3113 ~SparcGenInstrInfo() override = default;
3114};
3115extern const int16_t SparcRegClassByHwModeTables[2][1];
3116
3117} // namespace llvm
3118
3119namespace llvm::SP {
3120
3121
3122} // namespace llvm::SP
3123
3124#endif // GET_INSTRINFO_HEADER
3125
3126#ifdef GET_INSTRINFO_HELPER_DECLS
3127#undef GET_INSTRINFO_HELPER_DECLS
3128
3129
3130#endif // GET_INSTRINFO_HELPER_DECLS
3131
3132#ifdef GET_INSTRINFO_HELPERS
3133#undef GET_INSTRINFO_HELPERS
3134
3135
3136#endif // GET_INSTRINFO_HELPERS
3137
3138#ifdef GET_INSTRINFO_CTOR_DTOR
3139#undef GET_INSTRINFO_CTOR_DTOR
3140
3141namespace llvm {
3142
3143extern const SparcInstrTable SparcDescs;
3144extern const unsigned SparcInstrNameIndices[];
3145extern const char SparcInstrNameData[];
3146SparcGenInstrInfo::SparcGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
3147 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, SparcRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) {
3148 InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 897, &SparcRegClassByHwModeTables[0][0], 1);
3149}
3150
3151} // namespace llvm
3152
3153#endif // GET_INSTRINFO_CTOR_DTOR
3154
3155#ifdef GET_INSTRINFO_MC_HELPER_DECLS
3156#undef GET_INSTRINFO_MC_HELPER_DECLS
3157
3158namespace llvm {
3159
3160class MCInst;
3161class FeatureBitset;
3162
3163extern const int16_t SparcRegClassByHwModeTables[2][1];
3164
3165namespace Sparc_MC {
3166
3167void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
3168
3169} // namespace Sparc_MC
3170
3171} // namespace llvm
3172
3173#endif // GET_INSTRINFO_MC_HELPER_DECLS
3174
3175#ifdef GET_INSTRINFO_MC_HELPERS
3176#undef GET_INSTRINFO_MC_HELPERS
3177
3178namespace llvm::Sparc_MC {
3179
3180
3181} // namespace llvm::Sparc_MC
3182
3183#endif // GET_INSTRINFO_MC_HELPERS
3184
3185#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3186 defined(GET_AVAILABLE_OPCODE_CHECKER)
3187#define GET_COMPUTE_FEATURES
3188#endif
3189#ifdef GET_COMPUTE_FEATURES
3190#undef GET_COMPUTE_FEATURES
3191
3192namespace llvm::Sparc_MC {
3193
3194// Bits for subtarget features that participate in instruction matching.
3195enum SubtargetFeatureBits : uint8_t {
3196 Feature_Is32BitBit = 10,
3197 Feature_Is64BitBit = 11,
3198 Feature_UseSoftMulDivBit = 12,
3199 Feature_HasV9Bit = 6,
3200 Feature_HasVISBit = 7,
3201 Feature_HasVIS2Bit = 8,
3202 Feature_HasVIS3Bit = 9,
3203 Feature_HasUA2005Bit = 4,
3204 Feature_HasUA2007Bit = 5,
3205 Feature_HasOSA2011Bit = 2,
3206 Feature_HasCryptoBit = 1,
3207 Feature_HasCASABit = 0,
3208 Feature_HasPWRPSRBit = 3,
3209};
3210
3211inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3212 FeatureBitset Features;
3213 if (!(FB[Sparc::Feature64Bit]))
3214 Features.set(Feature_Is32BitBit);
3215 if (FB[Sparc::Feature64Bit])
3216 Features.set(Feature_Is64BitBit);
3217 if (FB[Sparc::FeatureSoftMulDiv])
3218 Features.set(Feature_UseSoftMulDivBit);
3219 if (FB[Sparc::FeatureV9])
3220 Features.set(Feature_HasV9Bit);
3221 if (FB[Sparc::FeatureVIS])
3222 Features.set(Feature_HasVISBit);
3223 if (FB[Sparc::FeatureVIS2])
3224 Features.set(Feature_HasVIS2Bit);
3225 if (FB[Sparc::FeatureVIS3])
3226 Features.set(Feature_HasVIS3Bit);
3227 if (FB[Sparc::FeatureUA2005])
3228 Features.set(Feature_HasUA2005Bit);
3229 if (FB[Sparc::FeatureUA2007])
3230 Features.set(Feature_HasUA2007Bit);
3231 if (FB[Sparc::FeatureOSA2011])
3232 Features.set(Feature_HasOSA2011Bit);
3233 if (FB[Sparc::FeatureCrypto])
3234 Features.set(Feature_HasCryptoBit);
3235 if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
3236 Features.set(Feature_HasCASABit);
3237 if (FB[Sparc::FeaturePWRPSR])
3238 Features.set(Feature_HasPWRPSRBit);
3239 return Features;
3240}
3241
3242inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3243 enum : uint8_t {
3244 CEFBS_None,
3245 CEFBS_HasCASA,
3246 CEFBS_HasCrypto,
3247 CEFBS_HasOSA2011,
3248 CEFBS_HasPWRPSR,
3249 CEFBS_HasUA2005,
3250 CEFBS_HasUA2007,
3251 CEFBS_HasV9,
3252 CEFBS_HasVIS,
3253 CEFBS_HasVIS2,
3254 CEFBS_HasVIS3,
3255 CEFBS_Is64Bit,
3256 CEFBS_Is64Bit_HasV9,
3257 };
3258
3259 static constexpr FeatureBitset FeatureBitsets[] = {
3260 {}, // CEFBS_None
3261 {Feature_HasCASABit, },
3262 {Feature_HasCryptoBit, },
3263 {Feature_HasOSA2011Bit, },
3264 {Feature_HasPWRPSRBit, },
3265 {Feature_HasUA2005Bit, },
3266 {Feature_HasUA2007Bit, },
3267 {Feature_HasV9Bit, },
3268 {Feature_HasVISBit, },
3269 {Feature_HasVIS2Bit, },
3270 {Feature_HasVIS3Bit, },
3271 {Feature_Is64BitBit, },
3272 {Feature_Is64BitBit, Feature_HasV9Bit, },
3273 };
3274 static constexpr uint8_t RequiredFeaturesRefs[] = {
3275 CEFBS_None, // PHI
3276 CEFBS_None, // INLINEASM
3277 CEFBS_None, // INLINEASM_BR
3278 CEFBS_None, // CFI_INSTRUCTION
3279 CEFBS_None, // EH_LABEL
3280 CEFBS_None, // GC_LABEL
3281 CEFBS_None, // ANNOTATION_LABEL
3282 CEFBS_None, // KILL
3283 CEFBS_None, // EXTRACT_SUBREG
3284 CEFBS_None, // INSERT_SUBREG
3285 CEFBS_None, // IMPLICIT_DEF
3286 CEFBS_None, // INIT_UNDEF
3287 CEFBS_None, // SUBREG_TO_REG
3288 CEFBS_None, // COPY_TO_REGCLASS
3289 CEFBS_None, // DBG_VALUE
3290 CEFBS_None, // DBG_VALUE_LIST
3291 CEFBS_None, // DBG_INSTR_REF
3292 CEFBS_None, // DBG_PHI
3293 CEFBS_None, // DBG_LABEL
3294 CEFBS_None, // REG_SEQUENCE
3295 CEFBS_None, // COPY
3296 CEFBS_None, // COPY_LANEMASK
3297 CEFBS_None, // BUNDLE
3298 CEFBS_None, // LIFETIME_START
3299 CEFBS_None, // LIFETIME_END
3300 CEFBS_None, // PSEUDO_PROBE
3301 CEFBS_None, // ARITH_FENCE
3302 CEFBS_None, // STACKMAP
3303 CEFBS_None, // FENTRY_CALL
3304 CEFBS_None, // PATCHPOINT
3305 CEFBS_None, // LOAD_STACK_GUARD
3306 CEFBS_None, // PREALLOCATED_SETUP
3307 CEFBS_None, // PREALLOCATED_ARG
3308 CEFBS_None, // STATEPOINT
3309 CEFBS_None, // LOCAL_ESCAPE
3310 CEFBS_None, // FAULTING_OP
3311 CEFBS_None, // PATCHABLE_OP
3312 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
3313 CEFBS_None, // PATCHABLE_RET
3314 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
3315 CEFBS_None, // PATCHABLE_TAIL_CALL
3316 CEFBS_None, // PATCHABLE_EVENT_CALL
3317 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
3318 CEFBS_None, // ICALL_BRANCH_FUNNEL
3319 CEFBS_None, // FAKE_USE
3320 CEFBS_None, // MEMBARRIER
3321 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
3322 CEFBS_None, // RELOC_NONE
3323 CEFBS_None, // CONVERGENCECTRL_ENTRY
3324 CEFBS_None, // CONVERGENCECTRL_ANCHOR
3325 CEFBS_None, // CONVERGENCECTRL_LOOP
3326 CEFBS_None, // CONVERGENCECTRL_GLUE
3327 CEFBS_None, // G_ASSERT_SEXT
3328 CEFBS_None, // G_ASSERT_ZEXT
3329 CEFBS_None, // G_ASSERT_ALIGN
3330 CEFBS_None, // G_ADD
3331 CEFBS_None, // G_SUB
3332 CEFBS_None, // G_MUL
3333 CEFBS_None, // G_SDIV
3334 CEFBS_None, // G_UDIV
3335 CEFBS_None, // G_SREM
3336 CEFBS_None, // G_UREM
3337 CEFBS_None, // G_SDIVREM
3338 CEFBS_None, // G_UDIVREM
3339 CEFBS_None, // G_AND
3340 CEFBS_None, // G_OR
3341 CEFBS_None, // G_XOR
3342 CEFBS_None, // G_ABDS
3343 CEFBS_None, // G_ABDU
3344 CEFBS_None, // G_UAVGFLOOR
3345 CEFBS_None, // G_UAVGCEIL
3346 CEFBS_None, // G_SAVGFLOOR
3347 CEFBS_None, // G_SAVGCEIL
3348 CEFBS_None, // G_IMPLICIT_DEF
3349 CEFBS_None, // G_PHI
3350 CEFBS_None, // G_FRAME_INDEX
3351 CEFBS_None, // G_GLOBAL_VALUE
3352 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
3353 CEFBS_None, // G_CONSTANT_POOL
3354 CEFBS_None, // G_EXTRACT
3355 CEFBS_None, // G_UNMERGE_VALUES
3356 CEFBS_None, // G_INSERT
3357 CEFBS_None, // G_MERGE_VALUES
3358 CEFBS_None, // G_BUILD_VECTOR
3359 CEFBS_None, // G_BUILD_VECTOR_TRUNC
3360 CEFBS_None, // G_CONCAT_VECTORS
3361 CEFBS_None, // G_PTRTOINT
3362 CEFBS_None, // G_INTTOPTR
3363 CEFBS_None, // G_BITCAST
3364 CEFBS_None, // G_FREEZE
3365 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
3366 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
3367 CEFBS_None, // G_INTRINSIC_TRUNC
3368 CEFBS_None, // G_INTRINSIC_ROUND
3369 CEFBS_None, // G_INTRINSIC_LRINT
3370 CEFBS_None, // G_INTRINSIC_LLRINT
3371 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
3372 CEFBS_None, // G_READCYCLECOUNTER
3373 CEFBS_None, // G_READSTEADYCOUNTER
3374 CEFBS_None, // G_LOAD
3375 CEFBS_None, // G_SEXTLOAD
3376 CEFBS_None, // G_ZEXTLOAD
3377 CEFBS_None, // G_FPEXTLOAD
3378 CEFBS_None, // G_INDEXED_LOAD
3379 CEFBS_None, // G_INDEXED_SEXTLOAD
3380 CEFBS_None, // G_INDEXED_ZEXTLOAD
3381 CEFBS_None, // G_STORE
3382 CEFBS_None, // G_FPTRUNCSTORE
3383 CEFBS_None, // G_INDEXED_STORE
3384 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3385 CEFBS_None, // G_ATOMIC_CMPXCHG
3386 CEFBS_None, // G_ATOMICRMW_XCHG
3387 CEFBS_None, // G_ATOMICRMW_ADD
3388 CEFBS_None, // G_ATOMICRMW_SUB
3389 CEFBS_None, // G_ATOMICRMW_AND
3390 CEFBS_None, // G_ATOMICRMW_NAND
3391 CEFBS_None, // G_ATOMICRMW_OR
3392 CEFBS_None, // G_ATOMICRMW_XOR
3393 CEFBS_None, // G_ATOMICRMW_MAX
3394 CEFBS_None, // G_ATOMICRMW_MIN
3395 CEFBS_None, // G_ATOMICRMW_UMAX
3396 CEFBS_None, // G_ATOMICRMW_UMIN
3397 CEFBS_None, // G_ATOMICRMW_FADD
3398 CEFBS_None, // G_ATOMICRMW_FSUB
3399 CEFBS_None, // G_ATOMICRMW_FMAX
3400 CEFBS_None, // G_ATOMICRMW_FMIN
3401 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
3402 CEFBS_None, // G_ATOMICRMW_FMINIMUM
3403 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
3404 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
3405 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
3406 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
3407 CEFBS_None, // G_ATOMICRMW_USUB_COND
3408 CEFBS_None, // G_ATOMICRMW_USUB_SAT
3409 CEFBS_None, // G_FENCE
3410 CEFBS_None, // G_PREFETCH
3411 CEFBS_None, // G_BRCOND
3412 CEFBS_None, // G_BRINDIRECT
3413 CEFBS_None, // G_INVOKE_REGION_START
3414 CEFBS_None, // G_INTRINSIC
3415 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
3416 CEFBS_None, // G_INTRINSIC_CONVERGENT
3417 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3418 CEFBS_None, // G_ANYEXT
3419 CEFBS_None, // G_TRUNC
3420 CEFBS_None, // G_TRUNC_SSAT_S
3421 CEFBS_None, // G_TRUNC_SSAT_U
3422 CEFBS_None, // G_TRUNC_USAT_U
3423 CEFBS_None, // G_CONSTANT
3424 CEFBS_None, // G_FCONSTANT
3425 CEFBS_None, // G_VASTART
3426 CEFBS_None, // G_VAARG
3427 CEFBS_None, // G_SEXT
3428 CEFBS_None, // G_SEXT_INREG
3429 CEFBS_None, // G_ZEXT
3430 CEFBS_None, // G_SHL
3431 CEFBS_None, // G_LSHR
3432 CEFBS_None, // G_ASHR
3433 CEFBS_None, // G_FSHL
3434 CEFBS_None, // G_FSHR
3435 CEFBS_None, // G_ROTR
3436 CEFBS_None, // G_ROTL
3437 CEFBS_None, // G_ICMP
3438 CEFBS_None, // G_FCMP
3439 CEFBS_None, // G_SCMP
3440 CEFBS_None, // G_UCMP
3441 CEFBS_None, // G_SELECT
3442 CEFBS_None, // G_UADDO
3443 CEFBS_None, // G_UADDE
3444 CEFBS_None, // G_USUBO
3445 CEFBS_None, // G_USUBE
3446 CEFBS_None, // G_SADDO
3447 CEFBS_None, // G_SADDE
3448 CEFBS_None, // G_SSUBO
3449 CEFBS_None, // G_SSUBE
3450 CEFBS_None, // G_UMULO
3451 CEFBS_None, // G_SMULO
3452 CEFBS_None, // G_UMULH
3453 CEFBS_None, // G_SMULH
3454 CEFBS_None, // G_UADDSAT
3455 CEFBS_None, // G_SADDSAT
3456 CEFBS_None, // G_USUBSAT
3457 CEFBS_None, // G_SSUBSAT
3458 CEFBS_None, // G_USHLSAT
3459 CEFBS_None, // G_SSHLSAT
3460 CEFBS_None, // G_SMULFIX
3461 CEFBS_None, // G_UMULFIX
3462 CEFBS_None, // G_SMULFIXSAT
3463 CEFBS_None, // G_UMULFIXSAT
3464 CEFBS_None, // G_SDIVFIX
3465 CEFBS_None, // G_UDIVFIX
3466 CEFBS_None, // G_SDIVFIXSAT
3467 CEFBS_None, // G_UDIVFIXSAT
3468 CEFBS_None, // G_FADD
3469 CEFBS_None, // G_FSUB
3470 CEFBS_None, // G_FMUL
3471 CEFBS_None, // G_FMA
3472 CEFBS_None, // G_FMAD
3473 CEFBS_None, // G_FDIV
3474 CEFBS_None, // G_FREM
3475 CEFBS_None, // G_FMODF
3476 CEFBS_None, // G_FPOW
3477 CEFBS_None, // G_FPOWI
3478 CEFBS_None, // G_FEXP
3479 CEFBS_None, // G_FEXP2
3480 CEFBS_None, // G_FEXP10
3481 CEFBS_None, // G_FLOG
3482 CEFBS_None, // G_FLOG2
3483 CEFBS_None, // G_FLOG10
3484 CEFBS_None, // G_FLDEXP
3485 CEFBS_None, // G_FFREXP
3486 CEFBS_None, // G_FNEG
3487 CEFBS_None, // G_FPEXT
3488 CEFBS_None, // G_FPTRUNC
3489 CEFBS_None, // G_FPTOSI
3490 CEFBS_None, // G_FPTOUI
3491 CEFBS_None, // G_SITOFP
3492 CEFBS_None, // G_UITOFP
3493 CEFBS_None, // G_FPTOSI_SAT
3494 CEFBS_None, // G_FPTOUI_SAT
3495 CEFBS_None, // G_FABS
3496 CEFBS_None, // G_FCOPYSIGN
3497 CEFBS_None, // G_IS_FPCLASS
3498 CEFBS_None, // G_FCANONICALIZE
3499 CEFBS_None, // G_FMINNUM
3500 CEFBS_None, // G_FMAXNUM
3501 CEFBS_None, // G_FMINNUM_IEEE
3502 CEFBS_None, // G_FMAXNUM_IEEE
3503 CEFBS_None, // G_FMINIMUM
3504 CEFBS_None, // G_FMAXIMUM
3505 CEFBS_None, // G_FMINIMUMNUM
3506 CEFBS_None, // G_FMAXIMUMNUM
3507 CEFBS_None, // G_GET_FPENV
3508 CEFBS_None, // G_SET_FPENV
3509 CEFBS_None, // G_RESET_FPENV
3510 CEFBS_None, // G_GET_FPMODE
3511 CEFBS_None, // G_SET_FPMODE
3512 CEFBS_None, // G_RESET_FPMODE
3513 CEFBS_None, // G_GET_ROUNDING
3514 CEFBS_None, // G_SET_ROUNDING
3515 CEFBS_None, // G_PTR_ADD
3516 CEFBS_None, // G_PTRMASK
3517 CEFBS_None, // G_SMIN
3518 CEFBS_None, // G_SMAX
3519 CEFBS_None, // G_UMIN
3520 CEFBS_None, // G_UMAX
3521 CEFBS_None, // G_ABS
3522 CEFBS_None, // G_LROUND
3523 CEFBS_None, // G_LLROUND
3524 CEFBS_None, // G_BR
3525 CEFBS_None, // G_BRJT
3526 CEFBS_None, // G_VSCALE
3527 CEFBS_None, // G_INSERT_SUBVECTOR
3528 CEFBS_None, // G_EXTRACT_SUBVECTOR
3529 CEFBS_None, // G_INSERT_VECTOR_ELT
3530 CEFBS_None, // G_EXTRACT_VECTOR_ELT
3531 CEFBS_None, // G_SHUFFLE_VECTOR
3532 CEFBS_None, // G_SPLAT_VECTOR
3533 CEFBS_None, // G_STEP_VECTOR
3534 CEFBS_None, // G_VECTOR_COMPRESS
3535 CEFBS_None, // G_CTTZ
3536 CEFBS_None, // G_CTTZ_ZERO_POISON
3537 CEFBS_None, // G_CTLZ
3538 CEFBS_None, // G_CTLZ_ZERO_POISON
3539 CEFBS_None, // G_CTLS
3540 CEFBS_None, // G_CTPOP
3541 CEFBS_None, // G_BSWAP
3542 CEFBS_None, // G_BITREVERSE
3543 CEFBS_None, // G_CLMUL
3544 CEFBS_None, // G_CLMULH
3545 CEFBS_None, // G_FCEIL
3546 CEFBS_None, // G_FCOS
3547 CEFBS_None, // G_FSIN
3548 CEFBS_None, // G_FSINCOS
3549 CEFBS_None, // G_FTAN
3550 CEFBS_None, // G_FACOS
3551 CEFBS_None, // G_FASIN
3552 CEFBS_None, // G_FATAN
3553 CEFBS_None, // G_FATAN2
3554 CEFBS_None, // G_FCOSH
3555 CEFBS_None, // G_FSINH
3556 CEFBS_None, // G_FTANH
3557 CEFBS_None, // G_FSQRT
3558 CEFBS_None, // G_FFLOOR
3559 CEFBS_None, // G_FRINT
3560 CEFBS_None, // G_FNEARBYINT
3561 CEFBS_None, // G_ADDRSPACE_CAST
3562 CEFBS_None, // G_BLOCK_ADDR
3563 CEFBS_None, // G_JUMP_TABLE
3564 CEFBS_None, // G_DYN_STACKALLOC
3565 CEFBS_None, // G_STACKSAVE
3566 CEFBS_None, // G_STACKRESTORE
3567 CEFBS_None, // G_STRICT_FADD
3568 CEFBS_None, // G_STRICT_FSUB
3569 CEFBS_None, // G_STRICT_FMUL
3570 CEFBS_None, // G_STRICT_FDIV
3571 CEFBS_None, // G_STRICT_FREM
3572 CEFBS_None, // G_STRICT_FMA
3573 CEFBS_None, // G_STRICT_FSQRT
3574 CEFBS_None, // G_STRICT_FLDEXP
3575 CEFBS_None, // G_STRICT_FCMP
3576 CEFBS_None, // G_STRICT_FCMPS
3577 CEFBS_None, // G_READ_REGISTER
3578 CEFBS_None, // G_WRITE_REGISTER
3579 CEFBS_None, // G_MEMCPY
3580 CEFBS_None, // G_MEMCPY_INLINE
3581 CEFBS_None, // G_MEMMOVE
3582 CEFBS_None, // G_MEMSET
3583 CEFBS_None, // G_BZERO
3584 CEFBS_None, // G_MEMSET_INLINE
3585 CEFBS_None, // G_TRAP
3586 CEFBS_None, // G_DEBUGTRAP
3587 CEFBS_None, // G_UBSANTRAP
3588 CEFBS_None, // G_VECREDUCE_SEQ_FADD
3589 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
3590 CEFBS_None, // G_VECREDUCE_FADD
3591 CEFBS_None, // G_VECREDUCE_FMUL
3592 CEFBS_None, // G_VECREDUCE_FMAX
3593 CEFBS_None, // G_VECREDUCE_FMIN
3594 CEFBS_None, // G_VECREDUCE_FMAXIMUM
3595 CEFBS_None, // G_VECREDUCE_FMINIMUM
3596 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
3597 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
3598 CEFBS_None, // G_VECREDUCE_ADD
3599 CEFBS_None, // G_VECREDUCE_MUL
3600 CEFBS_None, // G_VECREDUCE_AND
3601 CEFBS_None, // G_VECREDUCE_OR
3602 CEFBS_None, // G_VECREDUCE_XOR
3603 CEFBS_None, // G_VECREDUCE_SMAX
3604 CEFBS_None, // G_VECREDUCE_SMIN
3605 CEFBS_None, // G_VECREDUCE_UMAX
3606 CEFBS_None, // G_VECREDUCE_UMIN
3607 CEFBS_None, // G_SBFX
3608 CEFBS_None, // G_UBFX
3609 CEFBS_None, // ADJCALLSTACKDOWN
3610 CEFBS_None, // ADJCALLSTACKUP
3611 CEFBS_None, // GETPCX
3612 CEFBS_None, // SELECT_CC_DFP_FCC
3613 CEFBS_None, // SELECT_CC_DFP_ICC
3614 CEFBS_None, // SELECT_CC_DFP_XCC
3615 CEFBS_None, // SELECT_CC_FP_FCC
3616 CEFBS_None, // SELECT_CC_FP_ICC
3617 CEFBS_None, // SELECT_CC_FP_XCC
3618 CEFBS_None, // SELECT_CC_Int_FCC
3619 CEFBS_None, // SELECT_CC_Int_ICC
3620 CEFBS_None, // SELECT_CC_Int_XCC
3621 CEFBS_None, // SELECT_CC_QFP_FCC
3622 CEFBS_None, // SELECT_CC_QFP_ICC
3623 CEFBS_None, // SELECT_CC_QFP_XCC
3624 CEFBS_None, // SET
3625 CEFBS_HasV9, // SETSW
3626 CEFBS_Is64Bit_HasV9, // SETX
3627 CEFBS_None, // V8BAR
3628 CEFBS_None, // ADDCCri
3629 CEFBS_None, // ADDCCrr
3630 CEFBS_None, // ADDCri
3631 CEFBS_None, // ADDCrr
3632 CEFBS_None, // ADDEri
3633 CEFBS_None, // ADDErr
3634 CEFBS_HasVIS3, // ADDXC
3635 CEFBS_HasVIS3, // ADDXCCC
3636 CEFBS_None, // ADDri
3637 CEFBS_None, // ADDrr
3638 CEFBS_HasCrypto, // AES_DROUND01
3639 CEFBS_HasCrypto, // AES_DROUND01_LAST
3640 CEFBS_HasCrypto, // AES_DROUND23
3641 CEFBS_HasCrypto, // AES_DROUND23_LAST
3642 CEFBS_HasCrypto, // AES_EROUND01
3643 CEFBS_HasCrypto, // AES_EROUND01_LAST
3644 CEFBS_HasCrypto, // AES_EROUND23
3645 CEFBS_HasCrypto, // AES_EROUND23_LAST
3646 CEFBS_HasCrypto, // AES_KEXPAND0
3647 CEFBS_HasCrypto, // AES_KEXPAND1
3648 CEFBS_HasCrypto, // AES_KEXPAND2
3649 CEFBS_HasVIS, // ALIGNADDR
3650 CEFBS_HasVIS, // ALIGNADDRL
3651 CEFBS_HasUA2005, // ALLCLEAN
3652 CEFBS_None, // ANDCCri
3653 CEFBS_None, // ANDCCrr
3654 CEFBS_None, // ANDNCCri
3655 CEFBS_None, // ANDNCCrr
3656 CEFBS_None, // ANDNri
3657 CEFBS_None, // ANDNrr
3658 CEFBS_None, // ANDri
3659 CEFBS_None, // ANDrr
3660 CEFBS_HasVIS, // ARRAY16
3661 CEFBS_HasVIS, // ARRAY32
3662 CEFBS_HasVIS, // ARRAY8
3663 CEFBS_None, // BA
3664 CEFBS_None, // BCOND
3665 CEFBS_None, // BCONDA
3666 CEFBS_None, // BINDri
3667 CEFBS_None, // BINDrr
3668 CEFBS_HasVIS2, // BMASK
3669 CEFBS_HasV9, // BPFCC
3670 CEFBS_HasV9, // BPFCCA
3671 CEFBS_HasV9, // BPFCCANT
3672 CEFBS_HasV9, // BPFCCNT
3673 CEFBS_HasV9, // BPICC
3674 CEFBS_HasV9, // BPICCA
3675 CEFBS_HasV9, // BPICCANT
3676 CEFBS_HasV9, // BPICCNT
3677 CEFBS_HasV9, // BPR
3678 CEFBS_HasV9, // BPRA
3679 CEFBS_HasV9, // BPRANT
3680 CEFBS_HasV9, // BPRNT
3681 CEFBS_Is64Bit, // BPXCC
3682 CEFBS_Is64Bit, // BPXCCA
3683 CEFBS_Is64Bit, // BPXCCANT
3684 CEFBS_Is64Bit, // BPXCCNT
3685 CEFBS_HasVIS2, // BSHUFFLE
3686 CEFBS_None, // CALL
3687 CEFBS_None, // CALLi
3688 CEFBS_None, // CALLri
3689 CEFBS_None, // CALLrii
3690 CEFBS_None, // CALLrr
3691 CEFBS_None, // CALLrri
3692 CEFBS_HasCrypto, // CAMELLIA_F
3693 CEFBS_HasCrypto, // CAMELLIA_FL
3694 CEFBS_HasCrypto, // CAMELLIA_FLI
3695 CEFBS_HasV9, // CASAri
3696 CEFBS_HasCASA, // CASArr
3697 CEFBS_HasV9, // CASXAri
3698 CEFBS_HasV9, // CASXArr
3699 CEFBS_HasVIS3, // CMASK16
3700 CEFBS_HasVIS3, // CMASK32
3701 CEFBS_HasVIS3, // CMASK8
3702 CEFBS_None, // CPBCOND
3703 CEFBS_None, // CPBCONDA
3704 CEFBS_HasCrypto, // CRC32C
3705 CEFBS_HasOSA2011, // CWBCONDri
3706 CEFBS_HasOSA2011, // CWBCONDrr
3707 CEFBS_HasOSA2011, // CXBCONDri
3708 CEFBS_HasOSA2011, // CXBCONDrr
3709 CEFBS_HasCrypto, // DES_IIP
3710 CEFBS_HasCrypto, // DES_IP
3711 CEFBS_HasCrypto, // DES_KEXPAND
3712 CEFBS_HasCrypto, // DES_ROUND
3713 CEFBS_HasV9, // DONE
3714 CEFBS_HasVIS, // EDGE16
3715 CEFBS_HasVIS, // EDGE16L
3716 CEFBS_HasVIS2, // EDGE16LN
3717 CEFBS_HasVIS2, // EDGE16N
3718 CEFBS_HasVIS, // EDGE32
3719 CEFBS_HasVIS, // EDGE32L
3720 CEFBS_HasVIS2, // EDGE32LN
3721 CEFBS_HasVIS2, // EDGE32N
3722 CEFBS_HasVIS, // EDGE8
3723 CEFBS_HasVIS, // EDGE8L
3724 CEFBS_HasVIS2, // EDGE8LN
3725 CEFBS_HasVIS2, // EDGE8N
3726 CEFBS_HasV9, // FABSD
3727 CEFBS_HasV9, // FABSQ
3728 CEFBS_None, // FABSS
3729 CEFBS_None, // FADDD
3730 CEFBS_None, // FADDQ
3731 CEFBS_None, // FADDS
3732 CEFBS_HasVIS, // FALIGNADATA
3733 CEFBS_HasVIS, // FAND
3734 CEFBS_HasVIS, // FANDNOT1
3735 CEFBS_HasVIS, // FANDNOT1S
3736 CEFBS_HasVIS, // FANDNOT2
3737 CEFBS_HasVIS, // FANDNOT2S
3738 CEFBS_HasVIS, // FANDS
3739 CEFBS_None, // FBCOND
3740 CEFBS_None, // FBCONDA
3741 CEFBS_HasV9, // FBCONDA_V9
3742 CEFBS_HasV9, // FBCOND_V9
3743 CEFBS_HasVIS3, // FCHKSM16
3744 CEFBS_None, // FCMPD
3745 CEFBS_HasV9, // FCMPD_V9
3746 CEFBS_HasVIS, // FCMPEQ16
3747 CEFBS_HasVIS, // FCMPEQ32
3748 CEFBS_HasVIS, // FCMPGT16
3749 CEFBS_HasVIS, // FCMPGT32
3750 CEFBS_HasVIS, // FCMPLE16
3751 CEFBS_HasVIS, // FCMPLE32
3752 CEFBS_HasVIS, // FCMPNE16
3753 CEFBS_HasVIS, // FCMPNE32
3754 CEFBS_None, // FCMPQ
3755 CEFBS_HasV9, // FCMPQ_V9
3756 CEFBS_None, // FCMPS
3757 CEFBS_HasV9, // FCMPS_V9
3758 CEFBS_None, // FDIVD
3759 CEFBS_None, // FDIVQ
3760 CEFBS_None, // FDIVS
3761 CEFBS_None, // FDMULQ
3762 CEFBS_None, // FDTOI
3763 CEFBS_None, // FDTOQ
3764 CEFBS_None, // FDTOS
3765 CEFBS_HasV9, // FDTOX
3766 CEFBS_HasVIS, // FEXPAND
3767 CEFBS_HasVIS3, // FHADDD
3768 CEFBS_HasVIS3, // FHADDS
3769 CEFBS_HasVIS3, // FHSUBD
3770 CEFBS_HasVIS3, // FHSUBS
3771 CEFBS_None, // FITOD
3772 CEFBS_None, // FITOQ
3773 CEFBS_None, // FITOS
3774 CEFBS_HasVIS3, // FLCMPD
3775 CEFBS_HasVIS3, // FLCMPS
3776 CEFBS_None, // FLUSH
3777 CEFBS_HasV9, // FLUSHW
3778 CEFBS_None, // FLUSHri
3779 CEFBS_None, // FLUSHrr
3780 CEFBS_HasUA2007, // FMADDD
3781 CEFBS_HasUA2007, // FMADDS
3782 CEFBS_HasVIS3, // FMEAN16
3783 CEFBS_HasV9, // FMOVD
3784 CEFBS_HasV9, // FMOVD_FCC
3785 CEFBS_HasV9, // FMOVD_ICC
3786 CEFBS_Is64Bit, // FMOVD_XCC
3787 CEFBS_HasV9, // FMOVQ
3788 CEFBS_HasV9, // FMOVQ_FCC
3789 CEFBS_HasV9, // FMOVQ_ICC
3790 CEFBS_Is64Bit, // FMOVQ_XCC
3791 CEFBS_HasV9, // FMOVRD
3792 CEFBS_HasV9, // FMOVRQ
3793 CEFBS_HasV9, // FMOVRS
3794 CEFBS_None, // FMOVS
3795 CEFBS_HasV9, // FMOVS_FCC
3796 CEFBS_HasV9, // FMOVS_ICC
3797 CEFBS_Is64Bit, // FMOVS_XCC
3798 CEFBS_HasUA2007, // FMSUBD
3799 CEFBS_HasUA2007, // FMSUBS
3800 CEFBS_HasVIS, // FMUL8SUX16
3801 CEFBS_HasVIS, // FMUL8ULX16
3802 CEFBS_HasVIS, // FMUL8X16
3803 CEFBS_HasVIS, // FMUL8X16AL
3804 CEFBS_HasVIS, // FMUL8X16AU
3805 CEFBS_None, // FMULD
3806 CEFBS_HasVIS, // FMULD8SUX16
3807 CEFBS_HasVIS, // FMULD8ULX16
3808 CEFBS_None, // FMULQ
3809 CEFBS_None, // FMULS
3810 CEFBS_HasVIS3, // FNADDD
3811 CEFBS_HasVIS3, // FNADDS
3812 CEFBS_HasVIS, // FNAND
3813 CEFBS_HasVIS, // FNANDS
3814 CEFBS_HasV9, // FNEGD
3815 CEFBS_HasV9, // FNEGQ
3816 CEFBS_None, // FNEGS
3817 CEFBS_HasVIS3, // FNHADDD
3818 CEFBS_HasVIS3, // FNHADDS
3819 CEFBS_HasUA2007, // FNMADDD
3820 CEFBS_HasUA2007, // FNMADDS
3821 CEFBS_HasUA2007, // FNMSUBD
3822 CEFBS_HasUA2007, // FNMSUBS
3823 CEFBS_HasVIS3, // FNMULD
3824 CEFBS_HasVIS3, // FNMULS
3825 CEFBS_HasVIS, // FNOR
3826 CEFBS_HasVIS, // FNORS
3827 CEFBS_HasVIS, // FNOT1
3828 CEFBS_HasVIS, // FNOT1S
3829 CEFBS_HasVIS, // FNOT2
3830 CEFBS_HasVIS, // FNOT2S
3831 CEFBS_HasVIS3, // FNSMULD
3832 CEFBS_HasVIS, // FONE
3833 CEFBS_HasVIS, // FONES
3834 CEFBS_HasVIS, // FOR
3835 CEFBS_HasVIS, // FORNOT1
3836 CEFBS_HasVIS, // FORNOT1S
3837 CEFBS_HasVIS, // FORNOT2
3838 CEFBS_HasVIS, // FORNOT2S
3839 CEFBS_HasVIS, // FORS
3840 CEFBS_HasVIS, // FPACK16
3841 CEFBS_HasVIS, // FPACK32
3842 CEFBS_HasVIS, // FPACKFIX
3843 CEFBS_HasVIS, // FPADD16
3844 CEFBS_HasVIS, // FPADD16S
3845 CEFBS_HasVIS, // FPADD32
3846 CEFBS_HasVIS, // FPADD32S
3847 CEFBS_HasVIS3, // FPADD64
3848 CEFBS_HasOSA2011, // FPMADDX
3849 CEFBS_HasOSA2011, // FPMADDXHI
3850 CEFBS_HasVIS, // FPMERGE
3851 CEFBS_HasVIS, // FPSUB16
3852 CEFBS_HasVIS, // FPSUB16S
3853 CEFBS_HasVIS, // FPSUB32
3854 CEFBS_HasVIS, // FPSUB32S
3855 CEFBS_None, // FQTOD
3856 CEFBS_None, // FQTOI
3857 CEFBS_None, // FQTOS
3858 CEFBS_HasV9, // FQTOX
3859 CEFBS_HasVIS3, // FSLAS16
3860 CEFBS_HasVIS3, // FSLAS32
3861 CEFBS_HasVIS3, // FSLL16
3862 CEFBS_HasVIS3, // FSLL32
3863 CEFBS_None, // FSMULD
3864 CEFBS_None, // FSQRTD
3865 CEFBS_None, // FSQRTQ
3866 CEFBS_None, // FSQRTS
3867 CEFBS_HasVIS3, // FSRA16
3868 CEFBS_HasVIS3, // FSRA32
3869 CEFBS_HasVIS, // FSRC1
3870 CEFBS_HasVIS, // FSRC1S
3871 CEFBS_HasVIS, // FSRC2
3872 CEFBS_HasVIS, // FSRC2S
3873 CEFBS_HasVIS3, // FSRL16
3874 CEFBS_HasVIS3, // FSRL32
3875 CEFBS_None, // FSTOD
3876 CEFBS_None, // FSTOI
3877 CEFBS_None, // FSTOQ
3878 CEFBS_HasV9, // FSTOX
3879 CEFBS_None, // FSUBD
3880 CEFBS_None, // FSUBQ
3881 CEFBS_None, // FSUBS
3882 CEFBS_HasVIS, // FXNOR
3883 CEFBS_HasVIS, // FXNORS
3884 CEFBS_HasVIS, // FXOR
3885 CEFBS_HasVIS, // FXORS
3886 CEFBS_HasV9, // FXTOD
3887 CEFBS_HasV9, // FXTOQ
3888 CEFBS_HasV9, // FXTOS
3889 CEFBS_HasVIS, // FZERO
3890 CEFBS_HasVIS, // FZEROS
3891 CEFBS_HasV9, // GDOP_LDXrr
3892 CEFBS_None, // GDOP_LDrr
3893 CEFBS_HasUA2005, // INVALW
3894 CEFBS_None, // JMPLri
3895 CEFBS_None, // JMPLrr
3896 CEFBS_HasV9, // LDAri
3897 CEFBS_None, // LDArr
3898 CEFBS_None, // LDCSRri
3899 CEFBS_None, // LDCSRrr
3900 CEFBS_None, // LDCri
3901 CEFBS_None, // LDCrr
3902 CEFBS_HasV9, // LDDAri
3903 CEFBS_None, // LDDArr
3904 CEFBS_None, // LDDCri
3905 CEFBS_None, // LDDCrr
3906 CEFBS_HasV9, // LDDFAri
3907 CEFBS_HasV9, // LDDFArr
3908 CEFBS_None, // LDDFri
3909 CEFBS_None, // LDDFrr
3910 CEFBS_None, // LDDri
3911 CEFBS_None, // LDDrr
3912 CEFBS_HasV9, // LDFAri
3913 CEFBS_HasV9, // LDFArr
3914 CEFBS_None, // LDFSRri
3915 CEFBS_None, // LDFSRrr
3916 CEFBS_None, // LDFri
3917 CEFBS_None, // LDFrr
3918 CEFBS_HasV9, // LDQFAri
3919 CEFBS_HasV9, // LDQFArr
3920 CEFBS_HasV9, // LDQFri
3921 CEFBS_HasV9, // LDQFrr
3922 CEFBS_HasV9, // LDSBAri
3923 CEFBS_None, // LDSBArr
3924 CEFBS_None, // LDSBri
3925 CEFBS_None, // LDSBrr
3926 CEFBS_HasV9, // LDSHAri
3927 CEFBS_None, // LDSHArr
3928 CEFBS_None, // LDSHri
3929 CEFBS_None, // LDSHrr
3930 CEFBS_HasV9, // LDSTUBAri
3931 CEFBS_None, // LDSTUBArr
3932 CEFBS_None, // LDSTUBri
3933 CEFBS_None, // LDSTUBrr
3934 CEFBS_HasV9, // LDSWAri
3935 CEFBS_HasV9, // LDSWArr
3936 CEFBS_HasV9, // LDSWri
3937 CEFBS_HasV9, // LDSWrr
3938 CEFBS_HasV9, // LDUBAri
3939 CEFBS_None, // LDUBArr
3940 CEFBS_None, // LDUBri
3941 CEFBS_None, // LDUBrr
3942 CEFBS_HasV9, // LDUHAri
3943 CEFBS_None, // LDUHArr
3944 CEFBS_None, // LDUHri
3945 CEFBS_None, // LDUHrr
3946 CEFBS_HasV9, // LDXAri
3947 CEFBS_HasV9, // LDXArr
3948 CEFBS_HasV9, // LDXFSRri
3949 CEFBS_HasV9, // LDXFSRrr
3950 CEFBS_HasV9, // LDXri
3951 CEFBS_HasV9, // LDXrr
3952 CEFBS_None, // LDri
3953 CEFBS_None, // LDrr
3954 CEFBS_HasVIS3, // LZCNT
3955 CEFBS_HasCrypto, // MD5
3956 CEFBS_HasV9, // MEMBARi
3957 CEFBS_HasCrypto, // MONTMUL
3958 CEFBS_HasCrypto, // MONTSQR
3959 CEFBS_HasVIS3, // MOVDTOX
3960 CEFBS_HasV9, // MOVFCCri
3961 CEFBS_HasV9, // MOVFCCrr
3962 CEFBS_HasV9, // MOVICCri
3963 CEFBS_HasV9, // MOVICCrr
3964 CEFBS_HasV9, // MOVRri
3965 CEFBS_HasV9, // MOVRrr
3966 CEFBS_HasVIS3, // MOVSTOSW
3967 CEFBS_HasVIS3, // MOVSTOUW
3968 CEFBS_HasVIS3, // MOVWTOS
3969 CEFBS_Is64Bit, // MOVXCCri
3970 CEFBS_Is64Bit, // MOVXCCrr
3971 CEFBS_HasVIS3, // MOVXTOD
3972 CEFBS_HasCrypto, // MPMUL
3973 CEFBS_None, // MULSCCri
3974 CEFBS_None, // MULSCCrr
3975 CEFBS_HasV9, // MULXri
3976 CEFBS_HasV9, // MULXrr
3977 CEFBS_None, // NOP
3978 CEFBS_HasUA2005, // NORMALW
3979 CEFBS_None, // ORCCri
3980 CEFBS_None, // ORCCrr
3981 CEFBS_None, // ORNCCri
3982 CEFBS_None, // ORNCCrr
3983 CEFBS_None, // ORNri
3984 CEFBS_None, // ORNrr
3985 CEFBS_None, // ORri
3986 CEFBS_None, // ORrr
3987 CEFBS_HasUA2005, // OTHERW
3988 CEFBS_HasVIS, // PDIST
3989 CEFBS_HasVIS3, // PDISTN
3990 CEFBS_HasV9, // POPCrr
3991 CEFBS_HasV9, // PREFETCHAi
3992 CEFBS_HasV9, // PREFETCHAr
3993 CEFBS_HasV9, // PREFETCHi
3994 CEFBS_HasV9, // PREFETCHr
3995 CEFBS_HasPWRPSR, // PWRPSRri
3996 CEFBS_HasPWRPSR, // PWRPSRrr
3997 CEFBS_None, // RDASR
3998 CEFBS_HasV9, // RDFQ
3999 CEFBS_HasV9, // RDPR
4000 CEFBS_None, // RDPSR
4001 CEFBS_None, // RDTBR
4002 CEFBS_None, // RDWIM
4003 CEFBS_HasV9, // RESTORED
4004 CEFBS_None, // RESTOREri
4005 CEFBS_None, // RESTORErr
4006 CEFBS_None, // RET
4007 CEFBS_None, // RETL
4008 CEFBS_HasV9, // RETRY
4009 CEFBS_None, // RETTri
4010 CEFBS_None, // RETTrr
4011 CEFBS_HasV9, // SAVED
4012 CEFBS_None, // SAVEri
4013 CEFBS_None, // SAVErr
4014 CEFBS_None, // SDIVCCri
4015 CEFBS_None, // SDIVCCrr
4016 CEFBS_HasV9, // SDIVXri
4017 CEFBS_HasV9, // SDIVXrr
4018 CEFBS_None, // SDIVri
4019 CEFBS_None, // SDIVrr
4020 CEFBS_None, // SETHIi
4021 CEFBS_HasCrypto, // SHA1
4022 CEFBS_HasCrypto, // SHA256
4023 CEFBS_HasCrypto, // SHA512
4024 CEFBS_HasVIS, // SHUTDOWN
4025 CEFBS_HasVIS2, // SIAM
4026 CEFBS_HasV9, // SIR
4027 CEFBS_HasV9, // SLLXri
4028 CEFBS_HasV9, // SLLXrr
4029 CEFBS_None, // SLLri
4030 CEFBS_None, // SLLrr
4031 CEFBS_None, // SMACri
4032 CEFBS_None, // SMACrr
4033 CEFBS_None, // SMULCCri
4034 CEFBS_None, // SMULCCrr
4035 CEFBS_None, // SMULri
4036 CEFBS_None, // SMULrr
4037 CEFBS_HasV9, // SRAXri
4038 CEFBS_HasV9, // SRAXrr
4039 CEFBS_None, // SRAri
4040 CEFBS_None, // SRArr
4041 CEFBS_HasV9, // SRLXri
4042 CEFBS_HasV9, // SRLXrr
4043 CEFBS_None, // SRLri
4044 CEFBS_None, // SRLrr
4045 CEFBS_HasV9, // STAri
4046 CEFBS_None, // STArr
4047 CEFBS_None, // STBAR
4048 CEFBS_HasV9, // STBAri
4049 CEFBS_None, // STBArr
4050 CEFBS_None, // STBri
4051 CEFBS_None, // STBrr
4052 CEFBS_None, // STCSRri
4053 CEFBS_None, // STCSRrr
4054 CEFBS_None, // STCri
4055 CEFBS_None, // STCrr
4056 CEFBS_HasV9, // STDAri
4057 CEFBS_None, // STDArr
4058 CEFBS_None, // STDCQri
4059 CEFBS_None, // STDCQrr
4060 CEFBS_None, // STDCri
4061 CEFBS_None, // STDCrr
4062 CEFBS_HasV9, // STDFAri
4063 CEFBS_HasV9, // STDFArr
4064 CEFBS_None, // STDFQri
4065 CEFBS_None, // STDFQrr
4066 CEFBS_None, // STDFri
4067 CEFBS_None, // STDFrr
4068 CEFBS_None, // STDri
4069 CEFBS_None, // STDrr
4070 CEFBS_HasV9, // STFAri
4071 CEFBS_HasV9, // STFArr
4072 CEFBS_None, // STFSRri
4073 CEFBS_None, // STFSRrr
4074 CEFBS_None, // STFri
4075 CEFBS_None, // STFrr
4076 CEFBS_HasV9, // STHAri
4077 CEFBS_None, // STHArr
4078 CEFBS_None, // STHri
4079 CEFBS_None, // STHrr
4080 CEFBS_HasV9, // STQFAri
4081 CEFBS_HasV9, // STQFArr
4082 CEFBS_HasV9, // STQFri
4083 CEFBS_HasV9, // STQFrr
4084 CEFBS_HasV9, // STXAri
4085 CEFBS_HasV9, // STXArr
4086 CEFBS_HasV9, // STXFSRri
4087 CEFBS_HasV9, // STXFSRrr
4088 CEFBS_HasV9, // STXri
4089 CEFBS_HasV9, // STXrr
4090 CEFBS_None, // STri
4091 CEFBS_None, // STrr
4092 CEFBS_None, // SUBCCri
4093 CEFBS_None, // SUBCCrr
4094 CEFBS_None, // SUBCri
4095 CEFBS_None, // SUBCrr
4096 CEFBS_None, // SUBEri
4097 CEFBS_None, // SUBErr
4098 CEFBS_None, // SUBri
4099 CEFBS_None, // SUBrr
4100 CEFBS_HasV9, // SWAPAri
4101 CEFBS_None, // SWAPArr
4102 CEFBS_None, // SWAPri
4103 CEFBS_None, // SWAPrr
4104 CEFBS_None, // TA1
4105 CEFBS_None, // TA3
4106 CEFBS_None, // TA5
4107 CEFBS_None, // TADDCCTVri
4108 CEFBS_None, // TADDCCTVrr
4109 CEFBS_None, // TADDCCri
4110 CEFBS_None, // TADDCCrr
4111 CEFBS_None, // TAIL_CALL
4112 CEFBS_None, // TAIL_CALLri
4113 CEFBS_HasV9, // TICCri
4114 CEFBS_HasV9, // TICCrr
4115 CEFBS_None, // TLS_ADDrr
4116 CEFBS_None, // TLS_CALL
4117 CEFBS_HasV9, // TLS_LDXrr
4118 CEFBS_None, // TLS_LDrr
4119 CEFBS_None, // TRAPri
4120 CEFBS_None, // TRAPrr
4121 CEFBS_None, // TSUBCCTVri
4122 CEFBS_None, // TSUBCCTVrr
4123 CEFBS_None, // TSUBCCri
4124 CEFBS_None, // TSUBCCrr
4125 CEFBS_Is64Bit, // TXCCri
4126 CEFBS_Is64Bit, // TXCCrr
4127 CEFBS_None, // UDIVCCri
4128 CEFBS_None, // UDIVCCrr
4129 CEFBS_HasV9, // UDIVXri
4130 CEFBS_HasV9, // UDIVXrr
4131 CEFBS_None, // UDIVri
4132 CEFBS_None, // UDIVrr
4133 CEFBS_None, // UMACri
4134 CEFBS_None, // UMACrr
4135 CEFBS_None, // UMULCCri
4136 CEFBS_None, // UMULCCrr
4137 CEFBS_HasVIS3, // UMULXHI
4138 CEFBS_None, // UMULri
4139 CEFBS_None, // UMULrr
4140 CEFBS_None, // UNIMP
4141 CEFBS_None, // V9FCMPD
4142 CEFBS_None, // V9FCMPED
4143 CEFBS_None, // V9FCMPEQ
4144 CEFBS_None, // V9FCMPES
4145 CEFBS_None, // V9FCMPQ
4146 CEFBS_None, // V9FCMPS
4147 CEFBS_HasV9, // V9FMOVD_FCC
4148 CEFBS_HasV9, // V9FMOVQ_FCC
4149 CEFBS_HasV9, // V9FMOVS_FCC
4150 CEFBS_HasV9, // V9MOVFCCri
4151 CEFBS_HasV9, // V9MOVFCCrr
4152 CEFBS_None, // WRASRri
4153 CEFBS_None, // WRASRrr
4154 CEFBS_HasV9, // WRPRri
4155 CEFBS_HasV9, // WRPRrr
4156 CEFBS_None, // WRPSRri
4157 CEFBS_None, // WRPSRrr
4158 CEFBS_None, // WRTBRri
4159 CEFBS_None, // WRTBRrr
4160 CEFBS_None, // WRWIMri
4161 CEFBS_None, // WRWIMrr
4162 CEFBS_HasVIS3, // XMULX
4163 CEFBS_HasVIS3, // XMULXHI
4164 CEFBS_None, // XNORCCri
4165 CEFBS_None, // XNORCCrr
4166 CEFBS_None, // XNORri
4167 CEFBS_None, // XNORrr
4168 CEFBS_None, // XORCCri
4169 CEFBS_None, // XORCCrr
4170 CEFBS_None, // XORri
4171 CEFBS_None, // XORrr
4172 };
4173
4174 assert(Opcode < 897);
4175 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
4176}
4177
4178
4179} // namespace llvm::Sparc_MC
4180
4181#endif // GET_COMPUTE_FEATURES
4182
4183#ifdef GET_AVAILABLE_OPCODE_CHECKER
4184#undef GET_AVAILABLE_OPCODE_CHECKER
4185
4186namespace llvm::Sparc_MC {
4187
4188bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
4189 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4190 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4191 FeatureBitset MissingFeatures =
4192 (AvailableFeatures & RequiredFeatures) ^
4193 RequiredFeatures;
4194 return !MissingFeatures.any();
4195}
4196
4197} // namespace llvm::Sparc_MC
4198
4199#endif // GET_AVAILABLE_OPCODE_CHECKER
4200
4201#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
4202#undef ENABLE_INSTR_PREDICATE_VERIFIER
4203
4204#include <sstream>
4205
4206namespace llvm::Sparc_MC {
4207
4208#ifndef NDEBUG
4209static const char *SubtargetFeatureNames[] = {
4210 "Feature_HasCASA",
4211 "Feature_HasCrypto",
4212 "Feature_HasOSA2011",
4213 "Feature_HasPWRPSR",
4214 "Feature_HasUA2005",
4215 "Feature_HasUA2007",
4216 "Feature_HasV9",
4217 "Feature_HasVIS",
4218 "Feature_HasVIS2",
4219 "Feature_HasVIS3",
4220 "Feature_Is32Bit",
4221 "Feature_Is64Bit",
4222 "Feature_UseSoftMulDiv",
4223 nullptr
4224};
4225
4226#endif // NDEBUG
4227
4228void verifyInstructionPredicates(
4229 unsigned Opcode, const FeatureBitset &Features) {
4230#ifndef NDEBUG
4231 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4232 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4233 FeatureBitset MissingFeatures =
4234 (AvailableFeatures & RequiredFeatures) ^
4235 RequiredFeatures;
4236 if (MissingFeatures.any()) {
4237 std::ostringstream Msg;
4238 Msg << "Attempting to emit " << &SparcInstrNameData[SparcInstrNameIndices[Opcode]]
4239 << " instruction but the ";
4240 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
4241 if (MissingFeatures.test(i))
4242 Msg << SubtargetFeatureNames[i] << " ";
4243 Msg << "predicate(s) are not met";
4244 report_fatal_error(Msg.str().c_str());
4245 }
4246#endif // NDEBUG
4247}
4248
4249} // namespace llvm::Sparc_MC
4250
4251#endif // ENABLE_INSTR_PREDICATE_VERIFIER
4252
4253