1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass SparcMCRegisterClasses[];
13
14namespace SP {
15enum : unsigned {
16 NoRegister,
17 CANRESTORE = 1,
18 CANSAVE = 2,
19 CLEANWIN = 3,
20 CPQ = 4,
21 CPSR = 5,
22 CWP = 6,
23 FQ = 7,
24 FSR = 8,
25 GL = 9,
26 ICC = 10,
27 OTHERWIN = 11,
28 PIL = 12,
29 PSR = 13,
30 PSTATE = 14,
31 TBA = 15,
32 TBR = 16,
33 TICK = 17,
34 TL = 18,
35 TNPC = 19,
36 TPC = 20,
37 TSTATE = 21,
38 TT = 22,
39 VER = 23,
40 WIM = 24,
41 WSTATE = 25,
42 Y = 26,
43 ASR1 = 27,
44 ASR2 = 28,
45 ASR3 = 29,
46 ASR4 = 30,
47 ASR5 = 31,
48 ASR6 = 32,
49 ASR7 = 33,
50 ASR8 = 34,
51 ASR9 = 35,
52 ASR10 = 36,
53 ASR11 = 37,
54 ASR12 = 38,
55 ASR13 = 39,
56 ASR14 = 40,
57 ASR15 = 41,
58 ASR16 = 42,
59 ASR17 = 43,
60 ASR18 = 44,
61 ASR19 = 45,
62 ASR20 = 46,
63 ASR21 = 47,
64 ASR22 = 48,
65 ASR23 = 49,
66 ASR24 = 50,
67 ASR25 = 51,
68 ASR26 = 52,
69 ASR27 = 53,
70 ASR28 = 54,
71 ASR29 = 55,
72 ASR30 = 56,
73 ASR31 = 57,
74 C0 = 58,
75 C1 = 59,
76 C2 = 60,
77 C3 = 61,
78 C4 = 62,
79 C5 = 63,
80 C6 = 64,
81 C7 = 65,
82 C8 = 66,
83 C9 = 67,
84 C10 = 68,
85 C11 = 69,
86 C12 = 70,
87 C13 = 71,
88 C14 = 72,
89 C15 = 73,
90 C16 = 74,
91 C17 = 75,
92 C18 = 76,
93 C19 = 77,
94 C20 = 78,
95 C21 = 79,
96 C22 = 80,
97 C23 = 81,
98 C24 = 82,
99 C25 = 83,
100 C26 = 84,
101 C27 = 85,
102 C28 = 86,
103 C29 = 87,
104 C30 = 88,
105 C31 = 89,
106 D0 = 90,
107 D1 = 91,
108 D2 = 92,
109 D3 = 93,
110 D4 = 94,
111 D5 = 95,
112 D6 = 96,
113 D7 = 97,
114 D8 = 98,
115 D9 = 99,
116 D10 = 100,
117 D11 = 101,
118 D12 = 102,
119 D13 = 103,
120 D14 = 104,
121 D15 = 105,
122 D16 = 106,
123 D17 = 107,
124 D18 = 108,
125 D19 = 109,
126 D20 = 110,
127 D21 = 111,
128 D22 = 112,
129 D23 = 113,
130 D24 = 114,
131 D25 = 115,
132 D26 = 116,
133 D27 = 117,
134 D28 = 118,
135 D29 = 119,
136 D30 = 120,
137 D31 = 121,
138 F0 = 122,
139 F1 = 123,
140 F2 = 124,
141 F3 = 125,
142 F4 = 126,
143 F5 = 127,
144 F6 = 128,
145 F7 = 129,
146 F8 = 130,
147 F9 = 131,
148 F10 = 132,
149 F11 = 133,
150 F12 = 134,
151 F13 = 135,
152 F14 = 136,
153 F15 = 137,
154 F16 = 138,
155 F17 = 139,
156 F18 = 140,
157 F19 = 141,
158 F20 = 142,
159 F21 = 143,
160 F22 = 144,
161 F23 = 145,
162 F24 = 146,
163 F25 = 147,
164 F26 = 148,
165 F27 = 149,
166 F28 = 150,
167 F29 = 151,
168 F30 = 152,
169 F31 = 153,
170 FCC0 = 154,
171 FCC1 = 155,
172 FCC2 = 156,
173 FCC3 = 157,
174 G0 = 158,
175 G1 = 159,
176 G2 = 160,
177 G3 = 161,
178 G4 = 162,
179 G5 = 163,
180 G6 = 164,
181 G7 = 165,
182 I0 = 166,
183 I1 = 167,
184 I2 = 168,
185 I3 = 169,
186 I4 = 170,
187 I5 = 171,
188 I6 = 172,
189 I7 = 173,
190 L0 = 174,
191 L1 = 175,
192 L2 = 176,
193 L3 = 177,
194 L4 = 178,
195 L5 = 179,
196 L6 = 180,
197 L7 = 181,
198 O0 = 182,
199 O1 = 183,
200 O2 = 184,
201 O3 = 185,
202 O4 = 186,
203 O5 = 187,
204 O6 = 188,
205 O7 = 189,
206 Q0 = 190,
207 Q1 = 191,
208 Q2 = 192,
209 Q3 = 193,
210 Q4 = 194,
211 Q5 = 195,
212 Q6 = 196,
213 Q7 = 197,
214 Q8 = 198,
215 Q9 = 199,
216 Q10 = 200,
217 Q11 = 201,
218 Q12 = 202,
219 Q13 = 203,
220 Q14 = 204,
221 Q15 = 205,
222 C0_C1 = 206,
223 C2_C3 = 207,
224 C4_C5 = 208,
225 C6_C7 = 209,
226 C8_C9 = 210,
227 C10_C11 = 211,
228 C12_C13 = 212,
229 C14_C15 = 213,
230 C16_C17 = 214,
231 C18_C19 = 215,
232 C20_C21 = 216,
233 C22_C23 = 217,
234 C24_C25 = 218,
235 C26_C27 = 219,
236 C28_C29 = 220,
237 C30_C31 = 221,
238 G0_G1 = 222,
239 G2_G3 = 223,
240 G4_G5 = 224,
241 G6_G7 = 225,
242 I0_I1 = 226,
243 I2_I3 = 227,
244 I4_I5 = 228,
245 I6_I7 = 229,
246 L0_L1 = 230,
247 L2_L3 = 231,
248 L4_L5 = 232,
249 L6_L7 = 233,
250 O0_O1 = 234,
251 O2_O3 = 235,
252 O4_O5 = 236,
253 O6_O7 = 237,
254 NUM_TARGET_REGS // 238
255};
256} // end namespace SP
257
258// Register classes
259
260namespace SP {
261enum {
262 FCCRegsRegClassID = 0,
263 ASRRegsRegClassID = 1,
264 CoprocRegsRegClassID = 2,
265 FPRegsRegClassID = 3,
266 IntRegsRegClassID = 4,
267 GPRIncomingArgRegClassID = 5,
268 GPROutgoingArgRegClassID = 6,
269 DFPRegsRegClassID = 7,
270 I64RegsRegClassID = 8,
271 PRRegsRegClassID = 9,
272 CoprocPairRegClassID = 10,
273 IntPairRegClassID = 11,
274 LowDFPRegsRegClassID = 12,
275 I64Regs_and_GPRIncomingArgRegClassID = 13,
276 I64Regs_and_GPROutgoingArgRegClassID = 14,
277 IntPair_with_sub_even_in_GPRIncomingArgRegClassID = 15,
278 IntPair_with_sub_even_in_GPROutgoingArgRegClassID = 16,
279 PRRegs_and_ASRRegsRegClassID = 17,
280 QFPRegsRegClassID = 18,
281 LowQFPRegsRegClassID = 19,
282
283};
284} // end namespace SP
285
286
287// Register alternate name indices
288
289namespace SP {
290enum {
291 NoRegAltName, // 0
292 RegNamesStateReg, // 1
293 NUM_TARGET_REG_ALT_NAMES = 2
294};
295} // end namespace SP
296
297
298// Subregister indices
299
300namespace SP {
301enum : uint16_t {
302 NoSubRegister,
303 sub_even, // 1
304 sub_even64, // 2
305 sub_odd, // 3
306 sub_odd64, // 4
307 sub_odd64_then_sub_even, // 5
308 sub_odd64_then_sub_odd, // 6
309 NUM_TARGET_SUBREGS
310};
311} // end namespace SP
312
313// Register pressure sets enum.
314namespace SP {
315enum RegisterPressureSets {
316 PRRegs_and_ASRRegs = 0,
317 FCCRegs = 1,
318 GPRIncomingArg = 2,
319 GPROutgoingArg = 3,
320 PRRegs = 4,
321 FPRegs = 5,
322 IntRegs = 6,
323 DFPRegs = 7,
324};
325} // end namespace SP
326
327} // end namespace llvm
328
329