1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass SparcMCRegisterClasses[];
13
14namespace SP {
15
16enum : unsigned {
17 NoRegister,
18 CANRESTORE = 1,
19 CANSAVE = 2,
20 CLEANWIN = 3,
21 CPQ = 4,
22 CPSR = 5,
23 CWP = 6,
24 FQ = 7,
25 FSR = 8,
26 GL = 9,
27 ICC = 10,
28 OTHERWIN = 11,
29 PIL = 12,
30 PSR = 13,
31 PSTATE = 14,
32 TBA = 15,
33 TBR = 16,
34 TICK = 17,
35 TL = 18,
36 TNPC = 19,
37 TPC = 20,
38 TSTATE = 21,
39 TT = 22,
40 VER = 23,
41 WIM = 24,
42 WSTATE = 25,
43 Y = 26,
44 ASR1 = 27,
45 ASR2 = 28,
46 ASR3 = 29,
47 ASR4 = 30,
48 ASR5 = 31,
49 ASR6 = 32,
50 ASR7 = 33,
51 ASR8 = 34,
52 ASR9 = 35,
53 ASR10 = 36,
54 ASR11 = 37,
55 ASR12 = 38,
56 ASR13 = 39,
57 ASR14 = 40,
58 ASR15 = 41,
59 ASR16 = 42,
60 ASR17 = 43,
61 ASR18 = 44,
62 ASR19 = 45,
63 ASR20 = 46,
64 ASR21 = 47,
65 ASR22 = 48,
66 ASR23 = 49,
67 ASR24 = 50,
68 ASR25 = 51,
69 ASR26 = 52,
70 ASR27 = 53,
71 ASR28 = 54,
72 ASR29 = 55,
73 ASR30 = 56,
74 ASR31 = 57,
75 C0 = 58,
76 C1 = 59,
77 C2 = 60,
78 C3 = 61,
79 C4 = 62,
80 C5 = 63,
81 C6 = 64,
82 C7 = 65,
83 C8 = 66,
84 C9 = 67,
85 C10 = 68,
86 C11 = 69,
87 C12 = 70,
88 C13 = 71,
89 C14 = 72,
90 C15 = 73,
91 C16 = 74,
92 C17 = 75,
93 C18 = 76,
94 C19 = 77,
95 C20 = 78,
96 C21 = 79,
97 C22 = 80,
98 C23 = 81,
99 C24 = 82,
100 C25 = 83,
101 C26 = 84,
102 C27 = 85,
103 C28 = 86,
104 C29 = 87,
105 C30 = 88,
106 C31 = 89,
107 D0 = 90,
108 D1 = 91,
109 D2 = 92,
110 D3 = 93,
111 D4 = 94,
112 D5 = 95,
113 D6 = 96,
114 D7 = 97,
115 D8 = 98,
116 D9 = 99,
117 D10 = 100,
118 D11 = 101,
119 D12 = 102,
120 D13 = 103,
121 D14 = 104,
122 D15 = 105,
123 D16 = 106,
124 D17 = 107,
125 D18 = 108,
126 D19 = 109,
127 D20 = 110,
128 D21 = 111,
129 D22 = 112,
130 D23 = 113,
131 D24 = 114,
132 D25 = 115,
133 D26 = 116,
134 D27 = 117,
135 D28 = 118,
136 D29 = 119,
137 D30 = 120,
138 D31 = 121,
139 F0 = 122,
140 F1 = 123,
141 F2 = 124,
142 F3 = 125,
143 F4 = 126,
144 F5 = 127,
145 F6 = 128,
146 F7 = 129,
147 F8 = 130,
148 F9 = 131,
149 F10 = 132,
150 F11 = 133,
151 F12 = 134,
152 F13 = 135,
153 F14 = 136,
154 F15 = 137,
155 F16 = 138,
156 F17 = 139,
157 F18 = 140,
158 F19 = 141,
159 F20 = 142,
160 F21 = 143,
161 F22 = 144,
162 F23 = 145,
163 F24 = 146,
164 F25 = 147,
165 F26 = 148,
166 F27 = 149,
167 F28 = 150,
168 F29 = 151,
169 F30 = 152,
170 F31 = 153,
171 FCC0 = 154,
172 FCC1 = 155,
173 FCC2 = 156,
174 FCC3 = 157,
175 G0 = 158,
176 G1 = 159,
177 G2 = 160,
178 G3 = 161,
179 G4 = 162,
180 G5 = 163,
181 G6 = 164,
182 G7 = 165,
183 I0 = 166,
184 I1 = 167,
185 I2 = 168,
186 I3 = 169,
187 I4 = 170,
188 I5 = 171,
189 I6 = 172,
190 I7 = 173,
191 L0 = 174,
192 L1 = 175,
193 L2 = 176,
194 L3 = 177,
195 L4 = 178,
196 L5 = 179,
197 L6 = 180,
198 L7 = 181,
199 O0 = 182,
200 O1 = 183,
201 O2 = 184,
202 O3 = 185,
203 O4 = 186,
204 O5 = 187,
205 O6 = 188,
206 O7 = 189,
207 Q0 = 190,
208 Q1 = 191,
209 Q2 = 192,
210 Q3 = 193,
211 Q4 = 194,
212 Q5 = 195,
213 Q6 = 196,
214 Q7 = 197,
215 Q8 = 198,
216 Q9 = 199,
217 Q10 = 200,
218 Q11 = 201,
219 Q12 = 202,
220 Q13 = 203,
221 Q14 = 204,
222 Q15 = 205,
223 C0_C1 = 206,
224 C2_C3 = 207,
225 C4_C5 = 208,
226 C6_C7 = 209,
227 C8_C9 = 210,
228 C10_C11 = 211,
229 C12_C13 = 212,
230 C14_C15 = 213,
231 C16_C17 = 214,
232 C18_C19 = 215,
233 C20_C21 = 216,
234 C22_C23 = 217,
235 C24_C25 = 218,
236 C26_C27 = 219,
237 C28_C29 = 220,
238 C30_C31 = 221,
239 G0_G1 = 222,
240 G2_G3 = 223,
241 G4_G5 = 224,
242 G6_G7 = 225,
243 I0_I1 = 226,
244 I2_I3 = 227,
245 I4_I5 = 228,
246 I6_I7 = 229,
247 L0_L1 = 230,
248 L2_L3 = 231,
249 L4_L5 = 232,
250 L6_L7 = 233,
251 O0_O1 = 234,
252 O2_O3 = 235,
253 O4_O5 = 236,
254 O6_O7 = 237,
255 NUM_TARGET_REGS // 238
256};
257
258} // namespace SP
259
260// Register classes
261
262namespace SP {
263
264enum {
265 FCCRegsRegClassID = 0,
266 ASRRegsRegClassID = 1,
267 CoprocRegsRegClassID = 2,
268 FPRegsRegClassID = 3,
269 IntRegsRegClassID = 4,
270 GPRIncomingArgRegClassID = 5,
271 GPROutgoingArgRegClassID = 6,
272 DFPRegsRegClassID = 7,
273 I64RegsRegClassID = 8,
274 PRRegsRegClassID = 9,
275 CoprocPairRegClassID = 10,
276 IntPairRegClassID = 11,
277 LowDFPRegsRegClassID = 12,
278 I64Regs_and_GPRIncomingArgRegClassID = 13,
279 I64Regs_and_GPROutgoingArgRegClassID = 14,
280 IntPair_with_sub_even_in_GPRIncomingArgRegClassID = 15,
281 IntPair_with_sub_even_in_GPROutgoingArgRegClassID = 16,
282 PRRegs_and_ASRRegsRegClassID = 17,
283 QFPRegsRegClassID = 18,
284 LowQFPRegsRegClassID = 19,
285
286};
287
288} // namespace SP
289
290// Register alternate name indices
291
292namespace SP {
293
294enum {
295 NoRegAltName, // 0
296 RegNamesStateReg, // 1
297 NUM_TARGET_REG_ALT_NAMES = 2
298};
299
300} // namespace SP
301
302// Subregister indices
303
304namespace SP {
305
306enum : uint16_t {
307 NoSubRegister,
308 sub_even, // 1
309 sub_even64, // 2
310 sub_odd, // 3
311 sub_odd64, // 4
312 sub_odd64_then_sub_even, // 5
313 sub_odd64_then_sub_odd, // 6
314 NUM_TARGET_SUBREGS
315};
316
317} // namespace SP
318// Register pressure sets enum.
319namespace SP {
320
321enum RegisterPressureSets {
322 PRRegs_and_ASRRegs = 0,
323 FCCRegs = 1,
324 GPRIncomingArg = 2,
325 GPROutgoingArg = 3,
326 PRRegs = 4,
327 FPRegs = 5,
328 IntRegs = 6,
329 DFPRegs = 7,
330};
331
332} // namespace SP
333
334} // namespace llvm
335