1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace Sparc {
15
16enum {
17 DetectRoundChange = 0,
18 Feature64Bit = 1,
19 FeatureCrypto = 2,
20 FeatureHardQuad = 3,
21 FeatureLeon = 4,
22 FeatureNoFMULS = 5,
23 FeatureNoFSMULD = 6,
24 FeatureOSA2011 = 7,
25 FeaturePWRPSR = 8,
26 FeatureReserveG1 = 9,
27 FeatureReserveG2 = 10,
28 FeatureReserveG3 = 11,
29 FeatureReserveG4 = 12,
30 FeatureReserveG5 = 13,
31 FeatureReserveG6 = 14,
32 FeatureReserveG7 = 15,
33 FeatureReserveI0 = 16,
34 FeatureReserveI1 = 17,
35 FeatureReserveI2 = 18,
36 FeatureReserveI3 = 19,
37 FeatureReserveI4 = 20,
38 FeatureReserveI5 = 21,
39 FeatureReserveL0 = 22,
40 FeatureReserveL1 = 23,
41 FeatureReserveL2 = 24,
42 FeatureReserveL3 = 25,
43 FeatureReserveL4 = 26,
44 FeatureReserveL5 = 27,
45 FeatureReserveL6 = 28,
46 FeatureReserveL7 = 29,
47 FeatureReserveO0 = 30,
48 FeatureReserveO1 = 31,
49 FeatureReserveO2 = 32,
50 FeatureReserveO3 = 33,
51 FeatureReserveO4 = 34,
52 FeatureReserveO5 = 35,
53 FeatureSoftFloat = 36,
54 FeatureSoftMulDiv = 37,
55 FeatureUA2005 = 38,
56 FeatureUA2007 = 39,
57 FeatureV8Deprecated = 40,
58 FeatureV8Plus = 41,
59 FeatureV9 = 42,
60 FeatureVIS = 43,
61 FeatureVIS2 = 44,
62 FeatureVIS3 = 45,
63 FixAllFDIVSQRT = 46,
64 FixTN0009 = 47,
65 FixTN0010 = 48,
66 FixTN0011 = 49,
67 FixTN0012 = 50,
68 FixTN0013 = 51,
69 InsertNOPLoad = 52,
70 LeonCASA = 53,
71 LeonCycleCounter = 54,
72 TuneNoPredictor = 55,
73 TuneSlowRDPC = 56,
74 UMACSMACSupport = 57,
75 UsePopc = 58,
76 NumSubtargetFeatures = 59
77};
78
79} // namespace Sparc
80
81} // namespace llvm
82
83#endif // GET_SUBTARGETINFO_ENUM
84
85#ifdef GET_SUBTARGETINFO_MACRO
86
87GET_SUBTARGETINFO_MACRO(DetectRoundChange, false, detectRoundChange)
88GET_SUBTARGETINFO_MACRO(FixAllFDIVSQRT, false, fixAllFDIVSQRT)
89GET_SUBTARGETINFO_MACRO(FixTN0009, false, fixTN0009)
90GET_SUBTARGETINFO_MACRO(FixTN0010, false, fixTN0010)
91GET_SUBTARGETINFO_MACRO(FixTN0011, false, fixTN0011)
92GET_SUBTARGETINFO_MACRO(FixTN0012, false, fixTN0012)
93GET_SUBTARGETINFO_MACRO(FixTN0013, false, fixTN0013)
94GET_SUBTARGETINFO_MACRO(HasHardQuad, false, hasHardQuad)
95GET_SUBTARGETINFO_MACRO(HasLeonCasa, false, hasLeonCasa)
96GET_SUBTARGETINFO_MACRO(HasLeonCycleCounter, false, hasLeonCycleCounter)
97GET_SUBTARGETINFO_MACRO(HasNoFMULS, false, hasNoFMULS)
98GET_SUBTARGETINFO_MACRO(HasNoFSMULD, false, hasNoFSMULD)
99GET_SUBTARGETINFO_MACRO(HasNoPredictor, false, hasNoPredictor)
100GET_SUBTARGETINFO_MACRO(HasPWRPSR, false, hasPWRPSR)
101GET_SUBTARGETINFO_MACRO(HasSlowRDPC, false, hasSlowRDPC)
102GET_SUBTARGETINFO_MACRO(HasUmacSmac, false, hasUmacSmac)
103GET_SUBTARGETINFO_MACRO(InsertNOPLoad, false, insertNOPLoad)
104GET_SUBTARGETINFO_MACRO(Is64Bit, false, is64Bit)
105GET_SUBTARGETINFO_MACRO(IsCrypto, false, isCrypto)
106GET_SUBTARGETINFO_MACRO(IsLeon, false, isLeon)
107GET_SUBTARGETINFO_MACRO(IsOSA2011, false, isOSA2011)
108GET_SUBTARGETINFO_MACRO(IsUA2005, false, isUA2005)
109GET_SUBTARGETINFO_MACRO(IsUA2007, false, isUA2007)
110GET_SUBTARGETINFO_MACRO(IsV8Plus, false, isV8Plus)
111GET_SUBTARGETINFO_MACRO(IsV9, false, isV9)
112GET_SUBTARGETINFO_MACRO(IsVIS, false, isVIS)
113GET_SUBTARGETINFO_MACRO(IsVIS2, false, isVIS2)
114GET_SUBTARGETINFO_MACRO(IsVIS3, false, isVIS3)
115GET_SUBTARGETINFO_MACRO(UsePopc, false, usePopc)
116GET_SUBTARGETINFO_MACRO(UseSoftFloat, false, useSoftFloat)
117GET_SUBTARGETINFO_MACRO(UseSoftMulDiv, false, useSoftMulDiv)
118GET_SUBTARGETINFO_MACRO(UseV8DeprecatedInsts, false, useV8DeprecatedInsts)
119
120#undef GET_SUBTARGETINFO_MACRO
121#endif // GET_SUBTARGETINFO_MACRO
122
123#ifdef GET_SUBTARGETINFO_MC_DESC
124#undef GET_SUBTARGETINFO_MC_DESC
125
126namespace llvm {
127
128// Sorted (by key) array of values for CPU features.
129extern const llvm::SubtargetFeatureKV SparcFeatureKV[] = {
130 { "64bit", "Enable 64-bit mode", Sparc::Feature64Bit, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
131 { "crypto", "Enable cryptographic extensions", Sparc::FeatureCrypto, { { { 0x80ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
132 { "deprecated-v8", "Enable deprecated V8 instructions in V9 mode", Sparc::FeatureV8Deprecated, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
133 { "detectroundchange", "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", Sparc::DetectRoundChange, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
134 { "fix-tn0009", "Enable workaround for errata described in GRLIB-TN-0009", Sparc::FixTN0009, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
135 { "fix-tn0010", "Enable workaround for errata described in GRLIB-TN-0010", Sparc::FixTN0010, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
136 { "fix-tn0011", "Enable workaround for errata described in GRLIB-TN-0011", Sparc::FixTN0011, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
137 { "fix-tn0012", "Enable workaround for errata described in GRLIB-TN-0012", Sparc::FixTN0012, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
138 { "fix-tn0013", "Enable workaround for errata described in GRLIB-TN-0013", Sparc::FixTN0013, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
139 { "fixallfdivsqrt", "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store", Sparc::FixAllFDIVSQRT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
140 { "hard-quad-float", "Enable quad-word floating point instructions", Sparc::FeatureHardQuad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
141 { "hasleoncasa", "Enable CASA instruction for LEON3 and LEON4 processors", Sparc::LeonCASA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
142 { "hasumacsmac", "Enable UMAC and SMAC for LEON3 and LEON4 processors", Sparc::UMACSMACSupport, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
143 { "insertnopload", "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", Sparc::InsertNOPLoad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
144 { "leon", "Enable LEON extensions", Sparc::FeatureLeon, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
145 { "leoncyclecounter", "Use the Leon cycle counter register", Sparc::LeonCycleCounter, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
146 { "leonpwrpsr", "Enable the PWRPSR instruction", Sparc::FeaturePWRPSR, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
147 { "no-fmuls", "Disable the fmuls instruction.", Sparc::FeatureNoFMULS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
148 { "no-fsmuld", "Disable the fsmuld instruction.", Sparc::FeatureNoFSMULD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
149 { "no-predictor", "Processor has no branch predictor, branches stall execution", Sparc::TuneNoPredictor, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
150 { "osa2011", "Enable Oracle SPARC Architecture 2011 extensions", Sparc::FeatureOSA2011, { { { 0x3c0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
151 { "popc", "Use the popc (population count) instruction", Sparc::UsePopc, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
152 { "reserve-g1", "Reserve G1, making it unavailable as a GPR", Sparc::FeatureReserveG1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
153 { "reserve-g2", "Reserve G2, making it unavailable as a GPR", Sparc::FeatureReserveG2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
154 { "reserve-g3", "Reserve G3, making it unavailable as a GPR", Sparc::FeatureReserveG3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
155 { "reserve-g4", "Reserve G4, making it unavailable as a GPR", Sparc::FeatureReserveG4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
156 { "reserve-g5", "Reserve G5, making it unavailable as a GPR", Sparc::FeatureReserveG5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
157 { "reserve-g6", "Reserve G6, making it unavailable as a GPR", Sparc::FeatureReserveG6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
158 { "reserve-g7", "Reserve G7, making it unavailable as a GPR", Sparc::FeatureReserveG7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
159 { "reserve-i0", "Reserve I0, making it unavailable as a GPR", Sparc::FeatureReserveI0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
160 { "reserve-i1", "Reserve I1, making it unavailable as a GPR", Sparc::FeatureReserveI1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
161 { "reserve-i2", "Reserve I2, making it unavailable as a GPR", Sparc::FeatureReserveI2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
162 { "reserve-i3", "Reserve I3, making it unavailable as a GPR", Sparc::FeatureReserveI3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
163 { "reserve-i4", "Reserve I4, making it unavailable as a GPR", Sparc::FeatureReserveI4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
164 { "reserve-i5", "Reserve I5, making it unavailable as a GPR", Sparc::FeatureReserveI5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
165 { "reserve-l0", "Reserve L0, making it unavailable as a GPR", Sparc::FeatureReserveL0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
166 { "reserve-l1", "Reserve L1, making it unavailable as a GPR", Sparc::FeatureReserveL1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
167 { "reserve-l2", "Reserve L2, making it unavailable as a GPR", Sparc::FeatureReserveL2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
168 { "reserve-l3", "Reserve L3, making it unavailable as a GPR", Sparc::FeatureReserveL3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
169 { "reserve-l4", "Reserve L4, making it unavailable as a GPR", Sparc::FeatureReserveL4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
170 { "reserve-l5", "Reserve L5, making it unavailable as a GPR", Sparc::FeatureReserveL5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
171 { "reserve-l6", "Reserve L6, making it unavailable as a GPR", Sparc::FeatureReserveL6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
172 { "reserve-l7", "Reserve L7, making it unavailable as a GPR", Sparc::FeatureReserveL7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
173 { "reserve-o0", "Reserve O0, making it unavailable as a GPR", Sparc::FeatureReserveO0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
174 { "reserve-o1", "Reserve O1, making it unavailable as a GPR", Sparc::FeatureReserveO1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
175 { "reserve-o2", "Reserve O2, making it unavailable as a GPR", Sparc::FeatureReserveO2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
176 { "reserve-o3", "Reserve O3, making it unavailable as a GPR", Sparc::FeatureReserveO3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
177 { "reserve-o4", "Reserve O4, making it unavailable as a GPR", Sparc::FeatureReserveO4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
178 { "reserve-o5", "Reserve O5, making it unavailable as a GPR", Sparc::FeatureReserveO5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
179 { "slow-rdpc", "rd %pc, %XX is slow", Sparc::TuneSlowRDPC, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
180 { "soft-float", "Use software emulation for floating point", Sparc::FeatureSoftFloat, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
181 { "soft-mul-div", "Use software emulation for integer multiply and divide", Sparc::FeatureSoftMulDiv, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
182 { "ua2005", "Enable UltraSPARC Architecture 2005 extensions", Sparc::FeatureUA2005, { { { 0x1c0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
183 { "ua2007", "Enable UltraSPARC Architecture 2007 extensions", Sparc::FeatureUA2007, { { { 0x1c0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
184 { "v8plus", "Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code", Sparc::FeatureV8Plus, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
185 { "v9", "Enable SPARC-V9 instructions", Sparc::FeatureV9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
186 { "vis", "Enable UltraSPARC Visual Instruction Set extensions", Sparc::FeatureVIS, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
187 { "vis2", "Enable Visual Instruction Set extensions II", Sparc::FeatureVIS2, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
188 { "vis3", "Enable Visual Instruction Set extensions III", Sparc::FeatureVIS3, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
189};
190
191#ifdef DBGFIELD
192#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
193#endif
194#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
195#define DBGFIELD(x) x,
196#define DBGVAL_OR_NULLPTR(x) x
197#else
198#define DBGFIELD(x)
199#define DBGVAL_OR_NULLPTR(x) nullptr
200#endif
201
202// Functional units for "LEON2Itineraries"
203namespace LEON2ItinerariesFU {
204
205 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
206 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
207
208} // namespace LEON2ItinerariesFU
209
210// Functional units for "LEON3Itineraries"
211namespace LEON3ItinerariesFU {
212
213 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
214 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
215
216} // namespace LEON3ItinerariesFU
217
218// Functional units for "LEON4Itineraries"
219namespace LEON4ItinerariesFU {
220
221 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
222 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
223
224} // namespace LEON4ItinerariesFU
225
226extern const llvm::InstrStage SparcStages[] = {
227 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
228 { 1, LEON2ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
229 { 1, LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
230 { 1, LEON2ItinerariesFU::LEONIU | LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
231 { 1, LEON3ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
232 { 1, LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
233 { 1, LEON3ItinerariesFU::LEONIU | LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
234 { 1, LEON4ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
235 { 1, LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 8
236 { 1, LEON4ItinerariesFU::LEONIU | LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 9
237 { 0, 0, 0, llvm::InstrStage::Required } // End stages
238};
239extern const unsigned SparcOperandCycles[] = {
240 0, // No itinerary
241 1, 1, // 1-2
242 7, 1, // 3-4
243 2, 1, // 5-6
244 2, 1, // 7-8
245 7, 1, // 9-10
246 36, 1, // 11-12
247 20, 1, // 13-14
248 21, 1, // 15-16
249 16, 1, // 17-18
250 2, 1, // 19-20
251 65, 1, // 21-22
252 37, 1, // 23-24
253 2, 1, // 25-26
254 2, 1, // 27-28
255 1, 1, // 29-30
256 35, 1, // 31-32
257 5, 1, // 33-34
258 2, 1, // 35-36
259 3, 1, // 37-38
260 5, 1, // 39-40
261 1, 1, // 41-42
262 7, 1, // 43-44
263 3, 1, // 45-46
264 2, 1, // 47-48
265 4, 1, // 49-50
266 17, 1, // 51-52
267 16, 1, // 53-54
268 4, 1, // 55-56
269 4, 1, // 57-58
270 2, 1, // 59-60
271 25, 1, // 61-62
272 24, 1, // 63-64
273 4, 1, // 65-66
274 2, 1, // 67-68
275 1, 1, // 69-70
276 35, 1, // 71-72
277 2, 1, // 73-74
278 1, 1, // 75-76
279 4, 1, // 77-78
280 5, 1, // 79-80
281 4, 1, // 81-82
282 1, 1, // 83-84
283 7, 1, // 85-86
284 3, 1, // 87-88
285 2, 1, // 89-90
286 4, 1, // 91-92
287 17, 1, // 93-94
288 16, 1, // 95-96
289 4, 1, // 97-98
290 4, 1, // 99-100
291 2, 1, // 101-102
292 25, 1, // 103-104
293 24, 1, // 105-106
294 4, 1, // 107-108
295 1, 1, // 109-110
296 1, 1, // 111-112
297 35, 1, // 113-114
298 2, 1, // 115-116
299 1, 1, // 117-118
300 1, 1, // 119-120
301 1, 1, // 121-122
302 4, 1, // 123-124
303 0 // End operand cycles
304};
305extern const unsigned SparcForwardingPaths[] = {
306 0, // No itinerary
307 0, 0, // 1-2
308 0, 0, // 3-4
309 0, 0, // 5-6
310 0, 0, // 7-8
311 0, 0, // 9-10
312 0, 0, // 11-12
313 0, 0, // 13-14
314 0, 0, // 15-16
315 0, 0, // 17-18
316 0, 0, // 19-20
317 0, 0, // 21-22
318 0, 0, // 23-24
319 0, 0, // 25-26
320 0, 0, // 27-28
321 0, 0, // 29-30
322 0, 0, // 31-32
323 0, 0, // 33-34
324 0, 0, // 35-36
325 0, 0, // 37-38
326 0, 0, // 39-40
327 0, 0, // 41-42
328 0, 0, // 43-44
329 0, 0, // 45-46
330 0, 0, // 47-48
331 0, 0, // 49-50
332 0, 0, // 51-52
333 0, 0, // 53-54
334 0, 0, // 55-56
335 0, 0, // 57-58
336 0, 0, // 59-60
337 0, 0, // 61-62
338 0, 0, // 63-64
339 0, 0, // 65-66
340 0, 0, // 67-68
341 0, 0, // 69-70
342 0, 0, // 71-72
343 0, 0, // 73-74
344 0, 0, // 75-76
345 0, 0, // 77-78
346 0, 0, // 79-80
347 0, 0, // 81-82
348 0, 0, // 83-84
349 0, 0, // 85-86
350 0, 0, // 87-88
351 0, 0, // 89-90
352 0, 0, // 91-92
353 0, 0, // 93-94
354 0, 0, // 95-96
355 0, 0, // 97-98
356 0, 0, // 99-100
357 0, 0, // 101-102
358 0, 0, // 103-104
359 0, 0, // 105-106
360 0, 0, // 107-108
361 0, 0, // 109-110
362 0, 0, // 111-112
363 0, 0, // 113-114
364 0, 0, // 115-116
365 0, 0, // 117-118
366 0, 0, // 119-120
367 0, 0, // 121-122
368 0, 0, // 123-124
369 0 // End bypass tables
370};
371
372static constexpr llvm::InstrItinerary LEON2Itineraries[] = {
373 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
374 { 1, 1, 2, 1, 3 }, // 1 IIC_iu_instr
375 { 1, 2, 3, 3, 5 }, // 2 IIC_fpu_normal_instr
376 { 1, 3, 4, 5, 7 }, // 3 IIC_jmp_or_call
377 { 1, 2, 3, 7, 9 }, // 4 IIC_fpu_abs
378 { 1, 2, 3, 9, 11 }, // 5 IIC_fpu_fast_instr
379 { 1, 2, 3, 11, 13 }, // 6 IIC_fpu_divd
380 { 1, 2, 3, 13, 15 }, // 7 IIC_fpu_divs
381 { 1, 2, 3, 15, 17 }, // 8 IIC_fpu_muld
382 { 1, 2, 3, 17, 19 }, // 9 IIC_fpu_muls
383 { 1, 2, 3, 19, 21 }, // 10 IIC_fpu_negs
384 { 1, 2, 3, 21, 23 }, // 11 IIC_fpu_sqrtd
385 { 1, 2, 3, 23, 25 }, // 12 IIC_fpu_sqrts
386 { 1, 2, 3, 25, 27 }, // 13 IIC_fpu_stod
387 { 1, 3, 4, 27, 29 }, // 14 IIC_ldd
388 { 1, 3, 4, 29, 31 }, // 15 IIC_iu_or_fpu_instr
389 { 1, 1, 2, 31, 33 }, // 16 IIC_iu_div
390 { 0, 0, 0, 0, 0 }, // 17 IIC_smac_umac
391 { 1, 1, 2, 33, 35 }, // 18 IIC_iu_smul
392 { 1, 3, 4, 35, 37 }, // 19 IIC_st
393 { 1, 3, 4, 37, 39 }, // 20 IIC_std
394 { 1, 1, 2, 39, 41 }, // 21 IIC_iu_umul
395 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
396};
397
398static constexpr llvm::InstrItinerary LEON3Itineraries[] = {
399 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
400 { 1, 4, 5, 41, 43 }, // 1 IIC_iu_instr
401 { 1, 5, 6, 43, 45 }, // 2 IIC_fpu_normal_instr
402 { 1, 6, 7, 45, 47 }, // 3 IIC_jmp_or_call
403 { 1, 5, 6, 47, 49 }, // 4 IIC_fpu_abs
404 { 1, 5, 6, 49, 51 }, // 5 IIC_fpu_fast_instr
405 { 1, 5, 6, 51, 53 }, // 6 IIC_fpu_divd
406 { 1, 5, 6, 53, 55 }, // 7 IIC_fpu_divs
407 { 1, 5, 6, 55, 57 }, // 8 IIC_fpu_muld
408 { 1, 5, 6, 57, 59 }, // 9 IIC_fpu_muls
409 { 1, 5, 6, 59, 61 }, // 10 IIC_fpu_negs
410 { 1, 5, 6, 61, 63 }, // 11 IIC_fpu_sqrtd
411 { 1, 5, 6, 63, 65 }, // 12 IIC_fpu_sqrts
412 { 1, 5, 6, 65, 67 }, // 13 IIC_fpu_stod
413 { 1, 6, 7, 67, 69 }, // 14 IIC_ldd
414 { 1, 6, 7, 69, 71 }, // 15 IIC_iu_or_fpu_instr
415 { 1, 4, 5, 71, 73 }, // 16 IIC_iu_div
416 { 1, 4, 5, 73, 75 }, // 17 IIC_smac_umac
417 { 1, 4, 5, 75, 77 }, // 18 IIC_iu_smul
418 { 1, 6, 7, 77, 79 }, // 19 IIC_st
419 { 1, 6, 7, 79, 81 }, // 20 IIC_std
420 { 1, 4, 5, 81, 83 }, // 21 IIC_iu_umul
421 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
422};
423
424static constexpr llvm::InstrItinerary LEON4Itineraries[] = {
425 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
426 { 1, 7, 8, 83, 85 }, // 1 IIC_iu_instr
427 { 1, 8, 9, 85, 87 }, // 2 IIC_fpu_normal_instr
428 { 1, 9, 10, 87, 89 }, // 3 IIC_jmp_or_call
429 { 1, 8, 9, 89, 91 }, // 4 IIC_fpu_abs
430 { 1, 8, 9, 91, 93 }, // 5 IIC_fpu_fast_instr
431 { 1, 8, 9, 93, 95 }, // 6 IIC_fpu_divd
432 { 1, 8, 9, 95, 97 }, // 7 IIC_fpu_divs
433 { 1, 8, 9, 97, 99 }, // 8 IIC_fpu_muld
434 { 1, 8, 9, 99, 101 }, // 9 IIC_fpu_muls
435 { 1, 8, 9, 101, 103 }, // 10 IIC_fpu_negs
436 { 1, 8, 9, 103, 105 }, // 11 IIC_fpu_sqrtd
437 { 1, 8, 9, 105, 107 }, // 12 IIC_fpu_sqrts
438 { 1, 8, 9, 107, 109 }, // 13 IIC_fpu_stod
439 { 1, 9, 10, 109, 111 }, // 14 IIC_ldd
440 { 1, 9, 10, 111, 113 }, // 15 IIC_iu_or_fpu_instr
441 { 1, 7, 8, 113, 115 }, // 16 IIC_iu_div
442 { 1, 7, 8, 115, 117 }, // 17 IIC_smac_umac
443 { 1, 7, 8, 117, 119 }, // 18 IIC_iu_smul
444 { 1, 9, 10, 119, 121 }, // 19 IIC_st
445 { 1, 9, 10, 121, 123 }, // 20 IIC_std
446 { 1, 7, 8, 123, 125 }, // 21 IIC_iu_umul
447 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
448};
449
450// ===============================================================
451// Data tables for the new per-operand machine model.
452
453// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
454extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[] = {
455 { 0, 0, 0 }, // Invalid
456}; // SparcWriteProcResTable
457
458// {Cycles, WriteResourceID}
459extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[] = {
460 { 0, 0}, // Invalid
461}; // SparcWriteLatencyTable
462
463// {UseIdx, WriteResourceID, Cycles}
464extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[] = {
465 {0, 0, 0}, // Invalid
466}; // SparcReadAdvanceTable
467
468#ifdef __GNUC__
469#pragma GCC diagnostic push
470#pragma GCC diagnostic ignored "-Woverlength-strings"
471#endif
472static constexpr char SparcSchedClassNamesStorage[] =
473 "\0"
474 "InvalidSchedClass\0"
475 ;
476#ifdef __GNUC__
477#pragma GCC diagnostic pop
478#endif
479
480static constexpr llvm::StringTable
481SparcSchedClassNames = SparcSchedClassNamesStorage;
482
483static const llvm::MCSchedModel NoSchedModel = {
484 MCSchedModel::DefaultIssueWidth,
485 MCSchedModel::DefaultMicroOpBufferSize,
486 MCSchedModel::DefaultLoopMicroOpBufferSize,
487 MCSchedModel::DefaultLoadLatency,
488 MCSchedModel::DefaultHighLatency,
489 MCSchedModel::DefaultMispredictPenalty,
490 false, // PostRAScheduler
491 false, // CompleteModel
492 false, // EnableIntervals
493 0, // Processor ID
494 nullptr, nullptr, 0, 0, // No instruction-level machine model.
495 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
496 nullptr, // No Itinerary
497 nullptr // No extra processor descriptor
498};
499
500static const llvm::MCSchedModel LEON2ItinerariesModel = {
501 MCSchedModel::DefaultIssueWidth,
502 MCSchedModel::DefaultMicroOpBufferSize,
503 MCSchedModel::DefaultLoopMicroOpBufferSize,
504 MCSchedModel::DefaultLoadLatency,
505 MCSchedModel::DefaultHighLatency,
506 MCSchedModel::DefaultMispredictPenalty,
507 false, // PostRAScheduler
508 false, // CompleteModel
509 false, // EnableIntervals
510 1, // Processor ID
511 nullptr, nullptr, 0, 0, // No instruction-level machine model.
512 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
513 LEON2Itineraries,
514 nullptr // No extra processor descriptor
515};
516
517static const llvm::MCSchedModel LEON3ItinerariesModel = {
518 MCSchedModel::DefaultIssueWidth,
519 MCSchedModel::DefaultMicroOpBufferSize,
520 MCSchedModel::DefaultLoopMicroOpBufferSize,
521 MCSchedModel::DefaultLoadLatency,
522 MCSchedModel::DefaultHighLatency,
523 MCSchedModel::DefaultMispredictPenalty,
524 false, // PostRAScheduler
525 false, // CompleteModel
526 false, // EnableIntervals
527 2, // Processor ID
528 nullptr, nullptr, 0, 0, // No instruction-level machine model.
529 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
530 LEON3Itineraries,
531 nullptr // No extra processor descriptor
532};
533
534static const llvm::MCSchedModel LEON4ItinerariesModel = {
535 MCSchedModel::DefaultIssueWidth,
536 MCSchedModel::DefaultMicroOpBufferSize,
537 MCSchedModel::DefaultLoopMicroOpBufferSize,
538 MCSchedModel::DefaultLoadLatency,
539 MCSchedModel::DefaultHighLatency,
540 MCSchedModel::DefaultMispredictPenalty,
541 false, // PostRAScheduler
542 false, // CompleteModel
543 false, // EnableIntervals
544 3, // Processor ID
545 nullptr, nullptr, 0, 0, // No instruction-level machine model.
546 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
547 LEON4Itineraries,
548 nullptr // No extra processor descriptor
549};
550
551#undef DBGFIELD
552
553#undef DBGVAL_OR_NULLPTR
554
555// Sorted (by key) array of values for CPU subtype.
556extern const llvm::SubtargetSubTypeKV SparcSubTypeKV[] = {
557 { "at697e", { { { 0x10000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
558 { "at697f", { { { 0x10000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
559 { "f934", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
560 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
561 { "gr712rc", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
562 { "gr740", { { { 0x260000000000110ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON4ItinerariesModel },
563 { "hypersparc", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
564 { "leon2", { { { 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
565 { "leon3", { { { 0x200000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
566 { "leon4", { { { 0x220000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON4ItinerariesModel },
567 { "ma2080", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
568 { "ma2085", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
569 { "ma2100", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
570 { "ma2150", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
571 { "ma2155", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
572 { "ma2450", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
573 { "ma2455", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
574 { "ma2480", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
575 { "ma2485", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
576 { "ma2x5x", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
577 { "ma2x8x", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
578 { "myriad2", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
579 { "myriad2.1", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
580 { "myriad2.2", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
581 { "myriad2.3", { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
582 { "niagara", { { { 0x1d4000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
583 { "niagara2", { { { 0x4001d4000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
584 { "niagara3", { { { 0x4003dc000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
585 { "niagara4", { { { 0x4003dc000000084ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
586 { "sparclet", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
587 { "sparclite", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
588 { "sparclite86x", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
589 { "supersparc", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
590 { "tsc701", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
591 { "ultrasparc", { { { 0xd0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
592 { "ultrasparc3", { { { 0x1d0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
593 { "ut699", { { { 0x10400000000070ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
594 { "v7", { { { 0x2000000040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
595 { "v8", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
596 { "v9", { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
597};
598
599// Sorted array of names of CPU subtypes, including aliases.
600extern const llvm::StringRef SparcNames[] = {
601"at697e",
602"at697f",
603"f934",
604"generic",
605"gr712rc",
606"gr740",
607"hypersparc",
608"leon2",
609"leon3",
610"leon4",
611"ma2080",
612"ma2085",
613"ma2100",
614"ma2150",
615"ma2155",
616"ma2450",
617"ma2455",
618"ma2480",
619"ma2485",
620"ma2x5x",
621"ma2x8x",
622"myriad2",
623"myriad2.1",
624"myriad2.2",
625"myriad2.3",
626"niagara",
627"niagara2",
628"niagara3",
629"niagara4",
630"sparclet",
631"sparclite",
632"sparclite86x",
633"supersparc",
634"tsc701",
635"ultrasparc",
636"ultrasparc3",
637"ut699",
638"v7",
639"v8",
640"v9"};
641
642namespace Sparc_MC {
643
644unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
645 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
646 // Don't know how to resolve this scheduling class.
647 return 0;
648}
649
650} // namespace Sparc_MC
651struct SparcGenMCSubtargetInfo : public MCSubtargetInfo {
652 SparcGenMCSubtargetInfo(const Triple &TT,
653 StringRef CPU, StringRef TuneCPU, StringRef FS,
654 ArrayRef<StringRef> PN,
655 ArrayRef<SubtargetFeatureKV> PF,
656 ArrayRef<SubtargetSubTypeKV> PD,
657 const MCWriteProcResEntry *WPR,
658 const MCWriteLatencyEntry *WL,
659 const MCReadAdvanceEntry *RA, const InstrStage *IS,
660 const unsigned *OC, const unsigned *FP) :
661 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
662 WPR, WL, RA, IS, OC, FP) { }
663
664 unsigned resolveVariantSchedClass(unsigned SchedClass,
665 const MCInst *MI, const MCInstrInfo *MCII,
666 unsigned CPUID) const final {
667 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
668 }
669 unsigned getHwModeSet() const final;
670 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
671};
672unsigned SparcGenMCSubtargetInfo::getHwModeSet() const {
673 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
674 // Collect HwModes and store them as a bit set.
675 unsigned Modes = 0;
676 if (FB[Sparc::Feature64Bit]) Modes |= (1 << 0);
677 return Modes;
678}
679unsigned SparcGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
680 unsigned Modes = getHwModeSet();
681
682 if (!Modes)
683 return Modes;
684
685 switch (type) {
686 case HwMode_Default:
687 return llvm::countr_zero(Modes) + 1;
688 case HwMode_ValueType:
689 Modes &= 0;
690 if (!Modes)
691 return Modes;
692 if (!llvm::has_single_bit<unsigned>(Modes))
693 llvm_unreachable("Two or more HwModes for ValueType were found!");
694 return llvm::countr_zero(Modes) + 1;
695 case HwMode_RegInfo:
696 Modes &= 1;
697 if (!Modes)
698 return Modes;
699 if (!llvm::has_single_bit<unsigned>(Modes))
700 llvm_unreachable("Two or more HwModes for RegInfo were found!");
701 return llvm::countr_zero(Modes) + 1;
702 case HwMode_EncodingInfo:
703 Modes &= 0;
704 if (!Modes)
705 return Modes;
706 if (!llvm::has_single_bit<unsigned>(Modes))
707 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
708 return llvm::countr_zero(Modes) + 1;
709 }
710 llvm_unreachable("unexpected HwModeType");
711 return 0; // should not get here
712}
713
714static inline MCSubtargetInfo *createSparcMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
715 return new SparcGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, SparcNames, SparcFeatureKV, SparcSubTypeKV,
716 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
717 SparcStages, SparcOperandCycles, SparcForwardingPaths);
718}
719
720
721} // namespace llvm
722
723#endif // GET_SUBTARGETINFO_MC_DESC
724
725#ifdef GET_SUBTARGETINFO_TARGET_DESC
726#undef GET_SUBTARGETINFO_TARGET_DESC
727
728#include "llvm/ADT/BitmaskEnum.h"
729#include "llvm/Support/Debug.h"
730#include "llvm/Support/raw_ostream.h"
731
732// ParseSubtargetFeatures - Parses features string setting specified
733// subtarget options.
734void llvm::SparcSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
735 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
736 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
737 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
738 InitMCProcessorInfo(CPU, TuneCPU, FS);
739 const FeatureBitset &Bits = getFeatureBits();
740 if (Bits[Sparc::DetectRoundChange]) DetectRoundChange = true;
741 if (Bits[Sparc::Feature64Bit]) Is64Bit = true;
742 if (Bits[Sparc::FeatureCrypto]) IsCrypto = true;
743 if (Bits[Sparc::FeatureHardQuad]) HasHardQuad = true;
744 if (Bits[Sparc::FeatureLeon]) IsLeon = true;
745 if (Bits[Sparc::FeatureNoFMULS]) HasNoFMULS = true;
746 if (Bits[Sparc::FeatureNoFSMULD]) HasNoFSMULD = true;
747 if (Bits[Sparc::FeatureOSA2011]) IsOSA2011 = true;
748 if (Bits[Sparc::FeaturePWRPSR]) HasPWRPSR = true;
749 if (Bits[Sparc::FeatureReserveG1]) ReserveRegister[1 + SP::G0] = true;
750 if (Bits[Sparc::FeatureReserveG2]) ReserveRegister[2 + SP::G0] = true;
751 if (Bits[Sparc::FeatureReserveG3]) ReserveRegister[3 + SP::G0] = true;
752 if (Bits[Sparc::FeatureReserveG4]) ReserveRegister[4 + SP::G0] = true;
753 if (Bits[Sparc::FeatureReserveG5]) ReserveRegister[5 + SP::G0] = true;
754 if (Bits[Sparc::FeatureReserveG6]) ReserveRegister[6 + SP::G0] = true;
755 if (Bits[Sparc::FeatureReserveG7]) ReserveRegister[7 + SP::G0] = true;
756 if (Bits[Sparc::FeatureReserveI0]) ReserveRegister[0 + SP::I0] = true;
757 if (Bits[Sparc::FeatureReserveI1]) ReserveRegister[1 + SP::I0] = true;
758 if (Bits[Sparc::FeatureReserveI2]) ReserveRegister[2 + SP::I0] = true;
759 if (Bits[Sparc::FeatureReserveI3]) ReserveRegister[3 + SP::I0] = true;
760 if (Bits[Sparc::FeatureReserveI4]) ReserveRegister[4 + SP::I0] = true;
761 if (Bits[Sparc::FeatureReserveI5]) ReserveRegister[5 + SP::I0] = true;
762 if (Bits[Sparc::FeatureReserveL0]) ReserveRegister[0 + SP::L0] = true;
763 if (Bits[Sparc::FeatureReserveL1]) ReserveRegister[1 + SP::L0] = true;
764 if (Bits[Sparc::FeatureReserveL2]) ReserveRegister[2 + SP::L0] = true;
765 if (Bits[Sparc::FeatureReserveL3]) ReserveRegister[3 + SP::L0] = true;
766 if (Bits[Sparc::FeatureReserveL4]) ReserveRegister[4 + SP::L0] = true;
767 if (Bits[Sparc::FeatureReserveL5]) ReserveRegister[5 + SP::L0] = true;
768 if (Bits[Sparc::FeatureReserveL6]) ReserveRegister[6 + SP::L0] = true;
769 if (Bits[Sparc::FeatureReserveL7]) ReserveRegister[7 + SP::L0] = true;
770 if (Bits[Sparc::FeatureReserveO0]) ReserveRegister[0 + SP::O0] = true;
771 if (Bits[Sparc::FeatureReserveO1]) ReserveRegister[1 + SP::O0] = true;
772 if (Bits[Sparc::FeatureReserveO2]) ReserveRegister[2 + SP::O0] = true;
773 if (Bits[Sparc::FeatureReserveO3]) ReserveRegister[3 + SP::O0] = true;
774 if (Bits[Sparc::FeatureReserveO4]) ReserveRegister[4 + SP::O0] = true;
775 if (Bits[Sparc::FeatureReserveO5]) ReserveRegister[5 + SP::O0] = true;
776 if (Bits[Sparc::FeatureSoftFloat]) UseSoftFloat = true;
777 if (Bits[Sparc::FeatureSoftMulDiv]) UseSoftMulDiv = true;
778 if (Bits[Sparc::FeatureUA2005]) IsUA2005 = true;
779 if (Bits[Sparc::FeatureUA2007]) IsUA2007 = true;
780 if (Bits[Sparc::FeatureV8Deprecated]) UseV8DeprecatedInsts = true;
781 if (Bits[Sparc::FeatureV8Plus]) IsV8Plus = true;
782 if (Bits[Sparc::FeatureV9]) IsV9 = true;
783 if (Bits[Sparc::FeatureVIS]) IsVIS = true;
784 if (Bits[Sparc::FeatureVIS2]) IsVIS2 = true;
785 if (Bits[Sparc::FeatureVIS3]) IsVIS3 = true;
786 if (Bits[Sparc::FixAllFDIVSQRT]) FixAllFDIVSQRT = true;
787 if (Bits[Sparc::FixTN0009]) FixTN0009 = true;
788 if (Bits[Sparc::FixTN0010]) FixTN0010 = true;
789 if (Bits[Sparc::FixTN0011]) FixTN0011 = true;
790 if (Bits[Sparc::FixTN0012]) FixTN0012 = true;
791 if (Bits[Sparc::FixTN0013]) FixTN0013 = true;
792 if (Bits[Sparc::InsertNOPLoad]) InsertNOPLoad = true;
793 if (Bits[Sparc::LeonCASA]) HasLeonCasa = true;
794 if (Bits[Sparc::LeonCycleCounter]) HasLeonCycleCounter = true;
795 if (Bits[Sparc::TuneNoPredictor]) HasNoPredictor = true;
796 if (Bits[Sparc::TuneSlowRDPC]) HasSlowRDPC = true;
797 if (Bits[Sparc::UMACSMACSupport]) HasUmacSmac = true;
798 if (Bits[Sparc::UsePopc]) UsePopc = true;
799}
800
801#endif // GET_SUBTARGETINFO_TARGET_DESC
802
803#ifdef GET_SUBTARGETINFO_HEADER
804#undef GET_SUBTARGETINFO_HEADER
805
806namespace llvm {
807
808class DFAPacketizer;
809namespace Sparc_MC {
810
811unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
812
813} // namespace Sparc_MC
814struct SparcGenSubtargetInfo : public TargetSubtargetInfo {
815 explicit SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
816public:
817 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
818 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
819 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
820 enum class SparcHwModeBits : unsigned {
821 DefaultMode = 0,
822 SPARC64 = (1 << 0),
823
824 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/SPARC64),
825 };
826 unsigned getHwModeSet() const final;
827 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
828};
829
830} // namespace llvm
831
832#endif // GET_SUBTARGETINFO_HEADER
833
834#ifdef GET_SUBTARGETINFO_CTOR
835#undef GET_SUBTARGETINFO_CTOR
836
837#include "llvm/CodeGen/TargetSchedule.h"
838
839namespace llvm {
840
841extern const llvm::StringRef SparcNames[];
842extern const llvm::SubtargetFeatureKV SparcFeatureKV[];
843extern const llvm::SubtargetSubTypeKV SparcSubTypeKV[];
844extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[];
845extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[];
846extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[];
847extern const llvm::InstrStage SparcStages[];
848extern const unsigned SparcOperandCycles[];
849extern const unsigned SparcForwardingPaths[];
850SparcGenSubtargetInfo::SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
851 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(SparcNames, 40), ArrayRef(SparcFeatureKV, 59), ArrayRef(SparcSubTypeKV, 40),
852 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
853 SparcStages, SparcOperandCycles, SparcForwardingPaths) {}
854
855unsigned SparcGenSubtargetInfo
856::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
857 report_fatal_error("Expected a variant SchedClass");
858} // SparcGenSubtargetInfo::resolveSchedClass
859
860unsigned SparcGenSubtargetInfo
861::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
862 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
863} // SparcGenSubtargetInfo::resolveVariantSchedClass
864
865unsigned SparcGenSubtargetInfo::getHwModeSet() const {
866 [[maybe_unused]] const auto *Subtarget =
867 static_cast<const SparcSubtarget *>(this);
868 // Collect HwModes and store them as a bit set.
869 unsigned Modes = 0;
870 if ((Subtarget->is64Bit())) Modes |= (1 << 0);
871 return Modes;
872}
873unsigned SparcGenSubtargetInfo::getHwMode(enum HwModeType type) const {
874 unsigned Modes = getHwModeSet();
875
876 if (!Modes)
877 return Modes;
878
879 switch (type) {
880 case HwMode_Default:
881 return llvm::countr_zero(Modes) + 1;
882 case HwMode_ValueType:
883 Modes &= 0;
884 if (!Modes)
885 return Modes;
886 if (!llvm::has_single_bit<unsigned>(Modes))
887 llvm_unreachable("Two or more HwModes for ValueType were found!");
888 return llvm::countr_zero(Modes) + 1;
889 case HwMode_RegInfo:
890 Modes &= 1;
891 if (!Modes)
892 return Modes;
893 if (!llvm::has_single_bit<unsigned>(Modes))
894 llvm_unreachable("Two or more HwModes for RegInfo were found!");
895 return llvm::countr_zero(Modes) + 1;
896 case HwMode_EncodingInfo:
897 Modes &= 0;
898 if (!Modes)
899 return Modes;
900 if (!llvm::has_single_bit<unsigned>(Modes))
901 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
902 return llvm::countr_zero(Modes) + 1;
903 }
904 llvm_unreachable("unexpected HwModeType");
905 return 0; // should not get here
906}
907
908} // namespace llvm
909
910#endif // GET_SUBTARGETINFO_CTOR
911
912#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
913#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
914
915
916#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
917
918#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
919#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
920
921
922#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
923
924