1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace Sparc {
15
16enum {
17 DetectRoundChange = 0,
18 Feature64Bit = 1,
19 FeatureCrypto = 2,
20 FeatureHardQuad = 3,
21 FeatureLeon = 4,
22 FeatureNoFMULS = 5,
23 FeatureNoFSMULD = 6,
24 FeatureOSA2011 = 7,
25 FeaturePWRPSR = 8,
26 FeatureReserveG1 = 9,
27 FeatureReserveG2 = 10,
28 FeatureReserveG3 = 11,
29 FeatureReserveG4 = 12,
30 FeatureReserveG5 = 13,
31 FeatureReserveG6 = 14,
32 FeatureReserveG7 = 15,
33 FeatureReserveI0 = 16,
34 FeatureReserveI1 = 17,
35 FeatureReserveI2 = 18,
36 FeatureReserveI3 = 19,
37 FeatureReserveI4 = 20,
38 FeatureReserveI5 = 21,
39 FeatureReserveL0 = 22,
40 FeatureReserveL1 = 23,
41 FeatureReserveL2 = 24,
42 FeatureReserveL3 = 25,
43 FeatureReserveL4 = 26,
44 FeatureReserveL5 = 27,
45 FeatureReserveL6 = 28,
46 FeatureReserveL7 = 29,
47 FeatureReserveO0 = 30,
48 FeatureReserveO1 = 31,
49 FeatureReserveO2 = 32,
50 FeatureReserveO3 = 33,
51 FeatureReserveO4 = 34,
52 FeatureReserveO5 = 35,
53 FeatureSoftFloat = 36,
54 FeatureSoftMulDiv = 37,
55 FeatureUA2005 = 38,
56 FeatureUA2007 = 39,
57 FeatureV8Deprecated = 40,
58 FeatureV8Plus = 41,
59 FeatureV9 = 42,
60 FeatureVIS = 43,
61 FeatureVIS2 = 44,
62 FeatureVIS3 = 45,
63 FixAllFDIVSQRT = 46,
64 FixTN0009 = 47,
65 FixTN0010 = 48,
66 FixTN0011 = 49,
67 FixTN0012 = 50,
68 FixTN0013 = 51,
69 InsertNOPLoad = 52,
70 LeonCASA = 53,
71 LeonCycleCounter = 54,
72 TuneNoPredictor = 55,
73 TuneSlowRDPC = 56,
74 UMACSMACSupport = 57,
75 UsePopc = 58,
76 NumSubtargetFeatures = 59
77};
78
79} // namespace Sparc
80
81} // namespace llvm
82
83#endif // GET_SUBTARGETINFO_ENUM
84
85#ifdef GET_SUBTARGETINFO_MACRO
86
87GET_SUBTARGETINFO_MACRO(DetectRoundChange, false, detectRoundChange)
88GET_SUBTARGETINFO_MACRO(FixAllFDIVSQRT, false, fixAllFDIVSQRT)
89GET_SUBTARGETINFO_MACRO(FixTN0009, false, fixTN0009)
90GET_SUBTARGETINFO_MACRO(FixTN0010, false, fixTN0010)
91GET_SUBTARGETINFO_MACRO(FixTN0011, false, fixTN0011)
92GET_SUBTARGETINFO_MACRO(FixTN0012, false, fixTN0012)
93GET_SUBTARGETINFO_MACRO(FixTN0013, false, fixTN0013)
94GET_SUBTARGETINFO_MACRO(HasHardQuad, false, hasHardQuad)
95GET_SUBTARGETINFO_MACRO(HasLeonCasa, false, hasLeonCasa)
96GET_SUBTARGETINFO_MACRO(HasLeonCycleCounter, false, hasLeonCycleCounter)
97GET_SUBTARGETINFO_MACRO(HasNoFMULS, false, hasNoFMULS)
98GET_SUBTARGETINFO_MACRO(HasNoFSMULD, false, hasNoFSMULD)
99GET_SUBTARGETINFO_MACRO(HasNoPredictor, false, hasNoPredictor)
100GET_SUBTARGETINFO_MACRO(HasPWRPSR, false, hasPWRPSR)
101GET_SUBTARGETINFO_MACRO(HasSlowRDPC, false, hasSlowRDPC)
102GET_SUBTARGETINFO_MACRO(HasUmacSmac, false, hasUmacSmac)
103GET_SUBTARGETINFO_MACRO(InsertNOPLoad, false, insertNOPLoad)
104GET_SUBTARGETINFO_MACRO(Is64Bit, false, is64Bit)
105GET_SUBTARGETINFO_MACRO(IsCrypto, false, isCrypto)
106GET_SUBTARGETINFO_MACRO(IsLeon, false, isLeon)
107GET_SUBTARGETINFO_MACRO(IsOSA2011, false, isOSA2011)
108GET_SUBTARGETINFO_MACRO(IsUA2005, false, isUA2005)
109GET_SUBTARGETINFO_MACRO(IsUA2007, false, isUA2007)
110GET_SUBTARGETINFO_MACRO(IsV8Plus, false, isV8Plus)
111GET_SUBTARGETINFO_MACRO(IsV9, false, isV9)
112GET_SUBTARGETINFO_MACRO(IsVIS, false, isVIS)
113GET_SUBTARGETINFO_MACRO(IsVIS2, false, isVIS2)
114GET_SUBTARGETINFO_MACRO(IsVIS3, false, isVIS3)
115GET_SUBTARGETINFO_MACRO(UsePopc, false, usePopc)
116GET_SUBTARGETINFO_MACRO(UseSoftFloat, false, useSoftFloat)
117GET_SUBTARGETINFO_MACRO(UseSoftMulDiv, false, useSoftMulDiv)
118GET_SUBTARGETINFO_MACRO(UseV8DeprecatedInsts, false, useV8DeprecatedInsts)
119
120#undef GET_SUBTARGETINFO_MACRO
121#endif // GET_SUBTARGETINFO_MACRO
122
123#ifdef GET_SUBTARGETINFO_MC_DESC
124#undef GET_SUBTARGETINFO_MC_DESC
125
126namespace llvm {
127
128// Sorted (by key) array of values for CPU features.
129extern const llvm::SubtargetFeatureKVStorage< 59, 3417> SparcFeatureKVStorage = {
130 {
131 { sizeof(SubtargetFeatureKV) * 59 + 1, sizeof(SubtargetFeatureKV) * 59 + 7, Sparc::Feature64Bit, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
132 { sizeof(SubtargetFeatureKV) * 58 + 26, sizeof(SubtargetFeatureKV) * 58 + 33, Sparc::FeatureCrypto, { { { 0x80ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
133 { sizeof(SubtargetFeatureKV) * 57 + 65, sizeof(SubtargetFeatureKV) * 57 + 79, Sparc::FeatureV8Deprecated, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
134 { sizeof(SubtargetFeatureKV) * 56 + 124, sizeof(SubtargetFeatureKV) * 56 + 142, Sparc::DetectRoundChange, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
135 { sizeof(SubtargetFeatureKV) * 55 + 253, sizeof(SubtargetFeatureKV) * 55 + 264, Sparc::FixTN0009, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
136 { sizeof(SubtargetFeatureKV) * 54 + 320, sizeof(SubtargetFeatureKV) * 54 + 331, Sparc::FixTN0010, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
137 { sizeof(SubtargetFeatureKV) * 53 + 387, sizeof(SubtargetFeatureKV) * 53 + 398, Sparc::FixTN0011, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
138 { sizeof(SubtargetFeatureKV) * 52 + 454, sizeof(SubtargetFeatureKV) * 52 + 465, Sparc::FixTN0012, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
139 { sizeof(SubtargetFeatureKV) * 51 + 521, sizeof(SubtargetFeatureKV) * 51 + 532, Sparc::FixTN0013, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
140 { sizeof(SubtargetFeatureKV) * 50 + 588, sizeof(SubtargetFeatureKV) * 50 + 603, Sparc::FixAllFDIVSQRT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
141 { sizeof(SubtargetFeatureKV) * 49 + 699, sizeof(SubtargetFeatureKV) * 49 + 715, Sparc::FeatureHardQuad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
142 { sizeof(SubtargetFeatureKV) * 48 + 760, sizeof(SubtargetFeatureKV) * 48 + 772, Sparc::LeonCASA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
143 { sizeof(SubtargetFeatureKV) * 47 + 827, sizeof(SubtargetFeatureKV) * 47 + 839, Sparc::UMACSMACSupport, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
144 { sizeof(SubtargetFeatureKV) * 46 + 891, sizeof(SubtargetFeatureKV) * 46 + 905, Sparc::InsertNOPLoad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
145 { sizeof(SubtargetFeatureKV) * 45 + 1051, sizeof(SubtargetFeatureKV) * 45 + 1056, Sparc::FeatureLeon, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
146 { sizeof(SubtargetFeatureKV) * 44 + 1079, sizeof(SubtargetFeatureKV) * 44 + 1096, Sparc::LeonCycleCounter, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
147 { sizeof(SubtargetFeatureKV) * 43 + 1132, sizeof(SubtargetFeatureKV) * 43 + 1143, Sparc::FeaturePWRPSR, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
148 { sizeof(SubtargetFeatureKV) * 42 + 1173, sizeof(SubtargetFeatureKV) * 42 + 1182, Sparc::FeatureNoFMULS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
149 { sizeof(SubtargetFeatureKV) * 41 + 1213, sizeof(SubtargetFeatureKV) * 41 + 1223, Sparc::FeatureNoFSMULD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
150 { sizeof(SubtargetFeatureKV) * 40 + 1255, sizeof(SubtargetFeatureKV) * 40 + 1268, Sparc::TuneNoPredictor, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
151 { sizeof(SubtargetFeatureKV) * 39 + 1328, sizeof(SubtargetFeatureKV) * 39 + 1336, Sparc::FeatureOSA2011, { { { 0x3c0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
152 { sizeof(SubtargetFeatureKV) * 38 + 1385, sizeof(SubtargetFeatureKV) * 38 + 1390, Sparc::UsePopc, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
153 { sizeof(SubtargetFeatureKV) * 37 + 1434, sizeof(SubtargetFeatureKV) * 37 + 1445, Sparc::FeatureReserveG1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
154 { sizeof(SubtargetFeatureKV) * 36 + 1488, sizeof(SubtargetFeatureKV) * 36 + 1499, Sparc::FeatureReserveG2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
155 { sizeof(SubtargetFeatureKV) * 35 + 1542, sizeof(SubtargetFeatureKV) * 35 + 1553, Sparc::FeatureReserveG3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
156 { sizeof(SubtargetFeatureKV) * 34 + 1596, sizeof(SubtargetFeatureKV) * 34 + 1607, Sparc::FeatureReserveG4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
157 { sizeof(SubtargetFeatureKV) * 33 + 1650, sizeof(SubtargetFeatureKV) * 33 + 1661, Sparc::FeatureReserveG5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
158 { sizeof(SubtargetFeatureKV) * 32 + 1704, sizeof(SubtargetFeatureKV) * 32 + 1715, Sparc::FeatureReserveG6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
159 { sizeof(SubtargetFeatureKV) * 31 + 1758, sizeof(SubtargetFeatureKV) * 31 + 1769, Sparc::FeatureReserveG7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
160 { sizeof(SubtargetFeatureKV) * 30 + 1812, sizeof(SubtargetFeatureKV) * 30 + 1823, Sparc::FeatureReserveI0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
161 { sizeof(SubtargetFeatureKV) * 29 + 1866, sizeof(SubtargetFeatureKV) * 29 + 1877, Sparc::FeatureReserveI1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
162 { sizeof(SubtargetFeatureKV) * 28 + 1920, sizeof(SubtargetFeatureKV) * 28 + 1931, Sparc::FeatureReserveI2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
163 { sizeof(SubtargetFeatureKV) * 27 + 1974, sizeof(SubtargetFeatureKV) * 27 + 1985, Sparc::FeatureReserveI3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
164 { sizeof(SubtargetFeatureKV) * 26 + 2028, sizeof(SubtargetFeatureKV) * 26 + 2039, Sparc::FeatureReserveI4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
165 { sizeof(SubtargetFeatureKV) * 25 + 2082, sizeof(SubtargetFeatureKV) * 25 + 2093, Sparc::FeatureReserveI5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
166 { sizeof(SubtargetFeatureKV) * 24 + 2136, sizeof(SubtargetFeatureKV) * 24 + 2147, Sparc::FeatureReserveL0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
167 { sizeof(SubtargetFeatureKV) * 23 + 2190, sizeof(SubtargetFeatureKV) * 23 + 2201, Sparc::FeatureReserveL1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
168 { sizeof(SubtargetFeatureKV) * 22 + 2244, sizeof(SubtargetFeatureKV) * 22 + 2255, Sparc::FeatureReserveL2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
169 { sizeof(SubtargetFeatureKV) * 21 + 2298, sizeof(SubtargetFeatureKV) * 21 + 2309, Sparc::FeatureReserveL3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
170 { sizeof(SubtargetFeatureKV) * 20 + 2352, sizeof(SubtargetFeatureKV) * 20 + 2363, Sparc::FeatureReserveL4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
171 { sizeof(SubtargetFeatureKV) * 19 + 2406, sizeof(SubtargetFeatureKV) * 19 + 2417, Sparc::FeatureReserveL5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
172 { sizeof(SubtargetFeatureKV) * 18 + 2460, sizeof(SubtargetFeatureKV) * 18 + 2471, Sparc::FeatureReserveL6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
173 { sizeof(SubtargetFeatureKV) * 17 + 2514, sizeof(SubtargetFeatureKV) * 17 + 2525, Sparc::FeatureReserveL7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
174 { sizeof(SubtargetFeatureKV) * 16 + 2568, sizeof(SubtargetFeatureKV) * 16 + 2579, Sparc::FeatureReserveO0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
175 { sizeof(SubtargetFeatureKV) * 15 + 2622, sizeof(SubtargetFeatureKV) * 15 + 2633, Sparc::FeatureReserveO1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
176 { sizeof(SubtargetFeatureKV) * 14 + 2676, sizeof(SubtargetFeatureKV) * 14 + 2687, Sparc::FeatureReserveO2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
177 { sizeof(SubtargetFeatureKV) * 13 + 2730, sizeof(SubtargetFeatureKV) * 13 + 2741, Sparc::FeatureReserveO3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
178 { sizeof(SubtargetFeatureKV) * 12 + 2784, sizeof(SubtargetFeatureKV) * 12 + 2795, Sparc::FeatureReserveO4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
179 { sizeof(SubtargetFeatureKV) * 11 + 2838, sizeof(SubtargetFeatureKV) * 11 + 2849, Sparc::FeatureReserveO5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
180 { sizeof(SubtargetFeatureKV) * 10 + 2892, sizeof(SubtargetFeatureKV) * 10 + 2902, Sparc::TuneSlowRDPC, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
181 { sizeof(SubtargetFeatureKV) * 9 + 2922, sizeof(SubtargetFeatureKV) * 9 + 2933, Sparc::FeatureSoftFloat, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
182 { sizeof(SubtargetFeatureKV) * 8 + 2975, sizeof(SubtargetFeatureKV) * 8 + 2988, Sparc::FeatureSoftMulDiv, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
183 { sizeof(SubtargetFeatureKV) * 7 + 3043, sizeof(SubtargetFeatureKV) * 7 + 3050, Sparc::FeatureUA2005, { { { 0x1c0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
184 { sizeof(SubtargetFeatureKV) * 6 + 3097, sizeof(SubtargetFeatureKV) * 6 + 3104, Sparc::FeatureUA2007, { { { 0x1c0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
185 { sizeof(SubtargetFeatureKV) * 5 + 3151, sizeof(SubtargetFeatureKV) * 5 + 3158, Sparc::FeatureV8Plus, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
186 { sizeof(SubtargetFeatureKV) * 4 + 3229, sizeof(SubtargetFeatureKV) * 4 + 3232, Sparc::FeatureV9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
187 { sizeof(SubtargetFeatureKV) * 3 + 3261, sizeof(SubtargetFeatureKV) * 3 + 3265, Sparc::FeatureVIS, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
188 { sizeof(SubtargetFeatureKV) * 2 + 3317, sizeof(SubtargetFeatureKV) * 2 + 3322, Sparc::FeatureVIS2, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
189 { sizeof(SubtargetFeatureKV) * 1 + 3366, sizeof(SubtargetFeatureKV) * 1 + 3371, Sparc::FeatureVIS3, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
190 },
191 "\000" "64bit\000Enable 64-bit mode\000crypto\000Enable cryptographic ex"
192 "tensions\000deprecated-v8\000Enable deprecated V8 instructions in V9 mo"
193 "de\000detectroundchange\000LEON3 erratum detection: Detects any roundin"
194 "g mode change request: use only the round-to-nearest rounding mode\000f"
195 "ix-tn0009\000Enable workaround for errata described in GRLIB-TN-0009\000"
196 "fix-tn0010\000Enable workaround for errata described in GRLIB-TN-0010\000"
197 "fix-tn0011\000Enable workaround for errata described in GRLIB-TN-0011\000"
198 "fix-tn0012\000Enable workaround for errata described in GRLIB-TN-0012\000"
199 "fix-tn0013\000Enable workaround for errata described in GRLIB-TN-0013\000"
200 "fixallfdivsqrt\000LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instr"
201 "uctions with NOPs and floating-point store\000hard-quad-float\000Enable"
202 " quad-word floating point instructions\000hasleoncasa\000Enable CASA in"
203 "struction for LEON3 and LEON4 processors\000hasumacsmac\000Enable UMAC "
204 "and SMAC for LEON3 and LEON4 processors\000insertnopload\000LEON3 errat"
205 "um fix: Insert a NOP instruction after every single-cycle load instruct"
206 "ion when the next instruction is another load/store instruction\000leon"
207 "\000Enable LEON extensions\000leoncyclecounter\000Use the Leon cycle co"
208 "unter register\000leonpwrpsr\000Enable the PWRPSR instruction\000no-fmu"
209 "ls\000Disable the fmuls instruction.\000no-fsmuld\000Disable the fsmuld"
210 " instruction.\000no-predictor\000Processor has no branch predictor, bra"
211 "nches stall execution\000osa2011\000Enable Oracle SPARC Architecture 20"
212 "11 extensions\000popc\000Use the popc (population count) instruction\000"
213 "reserve-g1\000Reserve G1, making it unavailable as a GPR\000reserve-g2\000"
214 "Reserve G2, making it unavailable as a GPR\000reserve-g3\000Reserve G3,"
215 " making it unavailable as a GPR\000reserve-g4\000Reserve G4, making it "
216 "unavailable as a GPR\000reserve-g5\000Reserve G5, making it unavailable"
217 " as a GPR\000reserve-g6\000Reserve G6, making it unavailable as a GPR\000"
218 "reserve-g7\000Reserve G7, making it unavailable as a GPR\000reserve-i0\000"
219 "Reserve I0, making it unavailable as a GPR\000reserve-i1\000Reserve I1,"
220 " making it unavailable as a GPR\000reserve-i2\000Reserve I2, making it "
221 "unavailable as a GPR\000reserve-i3\000Reserve I3, making it unavailable"
222 " as a GPR\000reserve-i4\000Reserve I4, making it unavailable as a GPR\000"
223 "reserve-i5\000Reserve I5, making it unavailable as a GPR\000reserve-l0\000"
224 "Reserve L0, making it unavailable as a GPR\000reserve-l1\000Reserve L1,"
225 " making it unavailable as a GPR\000reserve-l2\000Reserve L2, making it "
226 "unavailable as a GPR\000reserve-l3\000Reserve L3, making it unavailable"
227 " as a GPR\000reserve-l4\000Reserve L4, making it unavailable as a GPR\000"
228 "reserve-l5\000Reserve L5, making it unavailable as a GPR\000reserve-l6\000"
229 "Reserve L6, making it unavailable as a GPR\000reserve-l7\000Reserve L7,"
230 " making it unavailable as a GPR\000reserve-o0\000Reserve O0, making it "
231 "unavailable as a GPR\000reserve-o1\000Reserve O1, making it unavailable"
232 " as a GPR\000reserve-o2\000Reserve O2, making it unavailable as a GPR\000"
233 "reserve-o3\000Reserve O3, making it unavailable as a GPR\000reserve-o4\000"
234 "Reserve O4, making it unavailable as a GPR\000reserve-o5\000Reserve O5,"
235 " making it unavailable as a GPR\000slow-rdpc\000rd %pc, %XX is slow\000"
236 "soft-float\000Use software emulation for floating point\000soft-mul-div"
237 "\000Use software emulation for integer multiply and divide\000ua2005\000"
238 "Enable UltraSPARC Architecture 2005 extensions\000ua2007\000Enable Ultr"
239 "aSPARC Architecture 2007 extensions\000v8plus\000Enable V8+ mode, allow"
240 "ing use of 64-bit V9 instructions in 32-bit code\000v9\000Enable SPARC-"
241 "V9 instructions\000vis\000Enable UltraSPARC Visual Instruction Set exte"
242 "nsions\000vis2\000Enable Visual Instruction Set extensions II\000vis3\000"
243 "Enable Visual Instruction Set extensions III\000"};
244
245#ifdef DBGFIELD
246#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
247#endif
248#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
249#define DBGFIELD(x) x,
250#define DBGVAL_OR_NULLPTR(x) x
251#else
252#define DBGFIELD(x)
253#define DBGVAL_OR_NULLPTR(x) nullptr
254#endif
255
256// Functional units for "LEON2Itineraries"
257namespace LEON2ItinerariesFU {
258
259 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
260 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
261
262} // namespace LEON2ItinerariesFU
263
264// Functional units for "LEON3Itineraries"
265namespace LEON3ItinerariesFU {
266
267 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
268 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
269
270} // namespace LEON3ItinerariesFU
271
272// Functional units for "LEON4Itineraries"
273namespace LEON4ItinerariesFU {
274
275 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
276 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
277
278} // namespace LEON4ItinerariesFU
279
280extern const llvm::InstrStage SparcStages[] = {
281 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
282 { 1, LEON2ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
283 { 1, LEON2ItinerariesFU::LEONIU | LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
284 { 1, LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
285 { 1, LEON3ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
286 { 1, LEON3ItinerariesFU::LEONIU | LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
287 { 1, LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
288 { 1, LEON4ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
289 { 1, LEON4ItinerariesFU::LEONIU | LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 8
290 { 1, LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 9
291 { 0, 0, 0, llvm::InstrStage::Required } // End stages
292};
293extern const unsigned SparcOperandCycles[] = {
294 0, // No itinerary
295 1, 1, // 1-2
296 1, 1, // 3-4
297 2, 1, // 5-6
298 7, 1, // 7-8
299 2, 1, // 9-10
300 3, 1, // 11-12
301 2, 1, // 13-14
302 7, 1, // 15-16
303 7, 1, // 17-18
304 7, 1, // 19-20
305 36, 1, // 21-22
306 20, 1, // 23-24
307 2, 1, // 25-26
308 21, 1, // 27-28
309 16, 1, // 29-30
310 2, 1, // 31-32
311 65, 1, // 33-34
312 37, 1, // 35-36
313 2, 1, // 37-38
314 2, 1, // 39-40
315 2, 1, // 41-42
316 1, 1, // 43-44
317 1, 1, // 45-46
318 35, 1, // 47-48
319 5, 1, // 49-50
320 2, 1, // 51-52
321 3, 1, // 53-54
322 3, 1, // 55-56
323 2, 1, // 57-58
324 5, 1, // 59-60
325 1, 1, // 61-62
326 1, 1, // 63-64
327 3, 1, // 65-66
328 7, 1, // 67-68
329 3, 1, // 69-70
330 3, 1, // 71-72
331 2, 1, // 73-74
332 4, 1, // 75-76
333 7, 1, // 77-78
334 4, 1, // 79-80
335 17, 1, // 81-82
336 16, 1, // 83-84
337 2, 1, // 85-86
338 4, 1, // 87-88
339 4, 1, // 89-90
340 2, 1, // 91-92
341 25, 1, // 93-94
342 24, 1, // 95-96
343 4, 1, // 97-98
344 2, 1, // 99-100
345 2, 1, // 101-102
346 1, 1, // 103-104
347 1, 1, // 105-106
348 35, 1, // 107-108
349 2, 1, // 109-110
350 1, 1, // 111-112
351 4, 1, // 113-114
352 5, 1, // 115-116
353 5, 1, // 117-118
354 4, 1, // 119-120
355 4, 1, // 121-122
356 1, 1, // 123-124
357 1, 1, // 125-126
358 3, 1, // 127-128
359 7, 1, // 129-130
360 3, 1, // 131-132
361 3, 1, // 133-134
362 2, 1, // 135-136
363 4, 1, // 137-138
364 7, 1, // 139-140
365 4, 1, // 141-142
366 17, 1, // 143-144
367 16, 1, // 145-146
368 2, 1, // 147-148
369 4, 1, // 149-150
370 4, 1, // 151-152
371 2, 1, // 153-154
372 25, 1, // 155-156
373 24, 1, // 157-158
374 4, 1, // 159-160
375 1, 1, // 161-162
376 1, 1, // 163-164
377 1, 1, // 165-166
378 1, 1, // 167-168
379 35, 1, // 169-170
380 2, 1, // 171-172
381 1, 1, // 173-174
382 1, 1, // 175-176
383 1, 1, // 177-178
384 1, 1, // 179-180
385 1, 1, // 181-182
386 4, 1, // 183-184
387 0 // End operand cycles
388};
389extern const unsigned SparcForwardingPaths[] = {
390 0, // No itinerary
391 0, 0, // 1-2
392 0, 0, // 3-4
393 0, 0, // 5-6
394 0, 0, // 7-8
395 0, 0, // 9-10
396 0, 0, // 11-12
397 0, 0, // 13-14
398 0, 0, // 15-16
399 0, 0, // 17-18
400 0, 0, // 19-20
401 0, 0, // 21-22
402 0, 0, // 23-24
403 0, 0, // 25-26
404 0, 0, // 27-28
405 0, 0, // 29-30
406 0, 0, // 31-32
407 0, 0, // 33-34
408 0, 0, // 35-36
409 0, 0, // 37-38
410 0, 0, // 39-40
411 0, 0, // 41-42
412 0, 0, // 43-44
413 0, 0, // 45-46
414 0, 0, // 47-48
415 0, 0, // 49-50
416 0, 0, // 51-52
417 0, 0, // 53-54
418 0, 0, // 55-56
419 0, 0, // 57-58
420 0, 0, // 59-60
421 0, 0, // 61-62
422 0, 0, // 63-64
423 0, 0, // 65-66
424 0, 0, // 67-68
425 0, 0, // 69-70
426 0, 0, // 71-72
427 0, 0, // 73-74
428 0, 0, // 75-76
429 0, 0, // 77-78
430 0, 0, // 79-80
431 0, 0, // 81-82
432 0, 0, // 83-84
433 0, 0, // 85-86
434 0, 0, // 87-88
435 0, 0, // 89-90
436 0, 0, // 91-92
437 0, 0, // 93-94
438 0, 0, // 95-96
439 0, 0, // 97-98
440 0, 0, // 99-100
441 0, 0, // 101-102
442 0, 0, // 103-104
443 0, 0, // 105-106
444 0, 0, // 107-108
445 0, 0, // 109-110
446 0, 0, // 111-112
447 0, 0, // 113-114
448 0, 0, // 115-116
449 0, 0, // 117-118
450 0, 0, // 119-120
451 0, 0, // 121-122
452 0, 0, // 123-124
453 0, 0, // 125-126
454 0, 0, // 127-128
455 0, 0, // 129-130
456 0, 0, // 131-132
457 0, 0, // 133-134
458 0, 0, // 135-136
459 0, 0, // 137-138
460 0, 0, // 139-140
461 0, 0, // 141-142
462 0, 0, // 143-144
463 0, 0, // 145-146
464 0, 0, // 147-148
465 0, 0, // 149-150
466 0, 0, // 151-152
467 0, 0, // 153-154
468 0, 0, // 155-156
469 0, 0, // 157-158
470 0, 0, // 159-160
471 0, 0, // 161-162
472 0, 0, // 163-164
473 0, 0, // 165-166
474 0, 0, // 167-168
475 0, 0, // 169-170
476 0, 0, // 171-172
477 0, 0, // 173-174
478 0, 0, // 175-176
479 0, 0, // 177-178
480 0, 0, // 179-180
481 0, 0, // 181-182
482 0, 0, // 183-184
483 0 // End bypass tables
484};
485
486static constexpr llvm::InstrItinerary LEON2Itineraries[] = {
487 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
488 { 1, 1, 2, 1, 3 }, // 1 IIC_iu_instr
489 { 1, 1, 2, 3, 5 }, // 2 IIC_branch
490 { 1, 2, 3, 5, 7 }, // 3 IIC_jmp
491 { 1, 3, 4, 7, 9 }, // 4 IIC_fpu_normal_instr
492 { 1, 2, 3, 9, 11 }, // 5 IIC_call
493 { 1, 2, 3, 11, 13 }, // 6 IIC_atomic
494 { 1, 3, 4, 13, 15 }, // 7 IIC_fpu_abs
495 { 1, 3, 4, 15, 17 }, // 8 IIC_fpu_fast_instr
496 { 1, 3, 4, 17, 19 }, // 9 IIC_fp_branch
497 { 1, 3, 4, 19, 21 }, // 10 IIC_fpu_cmp
498 { 1, 3, 4, 21, 23 }, // 11 IIC_fpu_divd
499 { 1, 3, 4, 23, 25 }, // 12 IIC_fpu_divs
500 { 1, 3, 4, 25, 27 }, // 13 IIC_fpu_movs
501 { 1, 3, 4, 27, 29 }, // 14 IIC_fpu_muld
502 { 1, 3, 4, 29, 31 }, // 15 IIC_fpu_muls
503 { 1, 3, 4, 31, 33 }, // 16 IIC_fpu_negs
504 { 1, 3, 4, 33, 35 }, // 17 IIC_fpu_sqrtd
505 { 1, 3, 4, 35, 37 }, // 18 IIC_fpu_sqrts
506 { 1, 3, 4, 37, 39 }, // 19 IIC_fpu_stod
507 { 1, 2, 3, 39, 41 }, // 20 IIC_ldd
508 { 1, 2, 3, 41, 43 }, // 21 IIC_fpu_ldd
509 { 1, 2, 3, 43, 45 }, // 22 IIC_fpu_ld
510 { 1, 1, 2, 45, 47 }, // 23 IIC_ld
511 { 1, 1, 2, 47, 49 }, // 24 IIC_iu_div
512 { 0, 0, 0, 0, 0 }, // 25 IIC_smac_umac
513 { 1, 1, 2, 49, 51 }, // 26 IIC_iu_smul
514 { 1, 2, 3, 51, 53 }, // 27 IIC_st
515 { 1, 2, 3, 53, 55 }, // 28 IIC_std
516 { 1, 2, 3, 55, 57 }, // 29 IIC_fpu_std
517 { 1, 2, 3, 57, 59 }, // 30 IIC_fpu_st
518 { 1, 1, 2, 59, 61 }, // 31 IIC_iu_umul
519 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
520};
521
522static constexpr llvm::InstrItinerary LEON3Itineraries[] = {
523 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
524 { 1, 4, 5, 61, 63 }, // 1 IIC_iu_instr
525 { 1, 4, 5, 63, 65 }, // 2 IIC_branch
526 { 1, 5, 6, 65, 67 }, // 3 IIC_jmp
527 { 1, 6, 7, 67, 69 }, // 4 IIC_fpu_normal_instr
528 { 1, 5, 6, 69, 71 }, // 5 IIC_call
529 { 1, 5, 6, 71, 73 }, // 6 IIC_atomic
530 { 1, 6, 7, 73, 75 }, // 7 IIC_fpu_abs
531 { 1, 6, 7, 75, 77 }, // 8 IIC_fpu_fast_instr
532 { 1, 6, 7, 77, 79 }, // 9 IIC_fp_branch
533 { 1, 6, 7, 79, 81 }, // 10 IIC_fpu_cmp
534 { 1, 6, 7, 81, 83 }, // 11 IIC_fpu_divd
535 { 1, 6, 7, 83, 85 }, // 12 IIC_fpu_divs
536 { 1, 6, 7, 85, 87 }, // 13 IIC_fpu_movs
537 { 1, 6, 7, 87, 89 }, // 14 IIC_fpu_muld
538 { 1, 6, 7, 89, 91 }, // 15 IIC_fpu_muls
539 { 1, 6, 7, 91, 93 }, // 16 IIC_fpu_negs
540 { 1, 6, 7, 93, 95 }, // 17 IIC_fpu_sqrtd
541 { 1, 6, 7, 95, 97 }, // 18 IIC_fpu_sqrts
542 { 1, 6, 7, 97, 99 }, // 19 IIC_fpu_stod
543 { 1, 5, 6, 99, 101 }, // 20 IIC_ldd
544 { 1, 5, 6, 101, 103 }, // 21 IIC_fpu_ldd
545 { 1, 5, 6, 103, 105 }, // 22 IIC_fpu_ld
546 { 1, 4, 5, 105, 107 }, // 23 IIC_ld
547 { 1, 4, 5, 107, 109 }, // 24 IIC_iu_div
548 { 1, 4, 5, 109, 111 }, // 25 IIC_smac_umac
549 { 1, 4, 5, 111, 113 }, // 26 IIC_iu_smul
550 { 1, 5, 6, 113, 115 }, // 27 IIC_st
551 { 1, 5, 6, 115, 117 }, // 28 IIC_std
552 { 1, 5, 6, 117, 119 }, // 29 IIC_fpu_std
553 { 1, 5, 6, 119, 121 }, // 30 IIC_fpu_st
554 { 1, 4, 5, 121, 123 }, // 31 IIC_iu_umul
555 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
556};
557
558static constexpr llvm::InstrItinerary LEON4Itineraries[] = {
559 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
560 { 1, 7, 8, 123, 125 }, // 1 IIC_iu_instr
561 { 1, 7, 8, 125, 127 }, // 2 IIC_branch
562 { 1, 8, 9, 127, 129 }, // 3 IIC_jmp
563 { 1, 9, 10, 129, 131 }, // 4 IIC_fpu_normal_instr
564 { 1, 8, 9, 131, 133 }, // 5 IIC_call
565 { 1, 8, 9, 133, 135 }, // 6 IIC_atomic
566 { 1, 9, 10, 135, 137 }, // 7 IIC_fpu_abs
567 { 1, 9, 10, 137, 139 }, // 8 IIC_fpu_fast_instr
568 { 1, 9, 10, 139, 141 }, // 9 IIC_fp_branch
569 { 1, 9, 10, 141, 143 }, // 10 IIC_fpu_cmp
570 { 1, 9, 10, 143, 145 }, // 11 IIC_fpu_divd
571 { 1, 9, 10, 145, 147 }, // 12 IIC_fpu_divs
572 { 1, 9, 10, 147, 149 }, // 13 IIC_fpu_movs
573 { 1, 9, 10, 149, 151 }, // 14 IIC_fpu_muld
574 { 1, 9, 10, 151, 153 }, // 15 IIC_fpu_muls
575 { 1, 9, 10, 153, 155 }, // 16 IIC_fpu_negs
576 { 1, 9, 10, 155, 157 }, // 17 IIC_fpu_sqrtd
577 { 1, 9, 10, 157, 159 }, // 18 IIC_fpu_sqrts
578 { 1, 9, 10, 159, 161 }, // 19 IIC_fpu_stod
579 { 1, 8, 9, 161, 163 }, // 20 IIC_ldd
580 { 1, 8, 9, 163, 165 }, // 21 IIC_fpu_ldd
581 { 1, 8, 9, 165, 167 }, // 22 IIC_fpu_ld
582 { 1, 8, 9, 167, 169 }, // 23 IIC_ld
583 { 1, 7, 8, 169, 171 }, // 24 IIC_iu_div
584 { 1, 7, 8, 171, 173 }, // 25 IIC_smac_umac
585 { 1, 7, 8, 173, 175 }, // 26 IIC_iu_smul
586 { 1, 8, 9, 175, 177 }, // 27 IIC_st
587 { 1, 8, 9, 177, 179 }, // 28 IIC_std
588 { 1, 8, 9, 179, 181 }, // 29 IIC_fpu_std
589 { 1, 8, 9, 181, 183 }, // 30 IIC_fpu_st
590 { 1, 7, 8, 183, 185 }, // 31 IIC_iu_umul
591 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
592};
593
594// ===============================================================
595// Data tables for the new per-operand machine model.
596
597static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
598static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
599
600// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
601extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[] = {
602 { 0, 0, 0 }, // Invalid
603}; // SparcWriteProcResTable
604
605// {Cycles, WriteResourceID}
606extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[] = {
607 { 0, 0}, // Invalid
608}; // SparcWriteLatencyTable
609
610// {UseIdx, WriteResourceID, Cycles}
611extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[] = {
612 {0, 0, 0}, // Invalid
613}; // SparcReadAdvanceTable
614
615#ifdef __GNUC__
616#pragma GCC diagnostic push
617#pragma GCC diagnostic ignored "-Woverlength-strings"
618#endif
619static constexpr char SparcSchedClassNamesStorage[] =
620 "\0"
621 "InvalidSchedClass\0"
622 ;
623#ifdef __GNUC__
624#pragma GCC diagnostic pop
625#endif
626
627static constexpr llvm::StringTable
628SparcSchedClassNames = SparcSchedClassNamesStorage;
629
630extern const llvm::MCSchedModel SparcSchedModels[] = {
631{ // NoSchedModel
632 MCSchedModel::DefaultIssueWidth,
633 MCSchedModel::DefaultMicroOpBufferSize,
634 MCSchedModel::DefaultLoopMicroOpBufferSize,
635 MCSchedModel::DefaultLoadLatency,
636 MCSchedModel::DefaultHighLatency,
637 MCSchedModel::DefaultMispredictPenalty,
638 false, // PostRAScheduler
639 false, // CompleteModel
640 false, // EnableIntervals
641 0, // Processor ID
642 nullptr, nullptr, 0, 0, // No instruction-level machine model.
643 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
644 nullptr, // No Itinerary
645 nullptr // No extra processor descriptor
646 },
647{ // LEON2ItinerariesModel
648 MCSchedModel::DefaultIssueWidth,
649 MCSchedModel::DefaultMicroOpBufferSize,
650 MCSchedModel::DefaultLoopMicroOpBufferSize,
651 MCSchedModel::DefaultLoadLatency,
652 MCSchedModel::DefaultHighLatency,
653 MCSchedModel::DefaultMispredictPenalty,
654 false, // PostRAScheduler
655 false, // CompleteModel
656 false, // EnableIntervals
657 1, // Processor ID
658 nullptr, nullptr, 0, 0, // No instruction-level machine model.
659 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
660 LEON2Itineraries,
661 nullptr // No extra processor descriptor
662 },
663{ // LEON3ItinerariesModel
664 MCSchedModel::DefaultIssueWidth,
665 MCSchedModel::DefaultMicroOpBufferSize,
666 MCSchedModel::DefaultLoopMicroOpBufferSize,
667 MCSchedModel::DefaultLoadLatency,
668 MCSchedModel::DefaultHighLatency,
669 MCSchedModel::DefaultMispredictPenalty,
670 false, // PostRAScheduler
671 false, // CompleteModel
672 false, // EnableIntervals
673 2, // Processor ID
674 nullptr, nullptr, 0, 0, // No instruction-level machine model.
675 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
676 LEON3Itineraries,
677 nullptr // No extra processor descriptor
678 },
679{ // LEON4ItinerariesModel
680 MCSchedModel::DefaultIssueWidth,
681 MCSchedModel::DefaultMicroOpBufferSize,
682 MCSchedModel::DefaultLoopMicroOpBufferSize,
683 MCSchedModel::DefaultLoadLatency,
684 MCSchedModel::DefaultHighLatency,
685 MCSchedModel::DefaultMispredictPenalty,
686 false, // PostRAScheduler
687 false, // CompleteModel
688 false, // EnableIntervals
689 3, // Processor ID
690 nullptr, nullptr, 0, 0, // No instruction-level machine model.
691 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
692 LEON4Itineraries,
693 nullptr // No extra processor descriptor
694 },
695};
696
697#undef DBGFIELD
698
699#undef DBGVAL_OR_NULLPTR
700
701static constexpr size_t SparcCPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 0>);
702// Sorted (by key) array of values for CPU subtype.
703extern const llvm::SubtargetSubTypeKVStorage< 41, 0, 316> SparcSubTypeKVStorage = {
704 {
705 { sizeof(SubtargetSubTypeKV) * 41 + SparcCPUAliasArraySize + 1, { { { 0x10000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
706 { sizeof(SubtargetSubTypeKV) * 40 + SparcCPUAliasArraySize + 8, { { { 0x10000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
707 { sizeof(SubtargetSubTypeKV) * 39 + SparcCPUAliasArraySize + 15, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
708 { sizeof(SubtargetSubTypeKV) * 38 + SparcCPUAliasArraySize + 20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
709 { sizeof(SubtargetSubTypeKV) * 37 + SparcCPUAliasArraySize + 28, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 },
710 { sizeof(SubtargetSubTypeKV) * 36 + SparcCPUAliasArraySize + 36, { { { 0x260000000000110ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 3 },
711 { sizeof(SubtargetSubTypeKV) * 35 + SparcCPUAliasArraySize + 42, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
712 { sizeof(SubtargetSubTypeKV) * 34 + SparcCPUAliasArraySize + 53, { { { 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
713 { sizeof(SubtargetSubTypeKV) * 33 + SparcCPUAliasArraySize + 59, { { { 0x220000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 },
714 { sizeof(SubtargetSubTypeKV) * 32 + SparcCPUAliasArraySize + 65, { { { 0x220000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 3 },
715 { sizeof(SubtargetSubTypeKV) * 31 + SparcCPUAliasArraySize + 71, { { { 0x60000000000110ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
716 { sizeof(SubtargetSubTypeKV) * 30 + SparcCPUAliasArraySize + 77, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
717 { sizeof(SubtargetSubTypeKV) * 29 + SparcCPUAliasArraySize + 84, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
718 { sizeof(SubtargetSubTypeKV) * 28 + SparcCPUAliasArraySize + 91, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
719 { sizeof(SubtargetSubTypeKV) * 27 + SparcCPUAliasArraySize + 98, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
720 { sizeof(SubtargetSubTypeKV) * 26 + SparcCPUAliasArraySize + 105, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
721 { sizeof(SubtargetSubTypeKV) * 25 + SparcCPUAliasArraySize + 112, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
722 { sizeof(SubtargetSubTypeKV) * 24 + SparcCPUAliasArraySize + 119, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
723 { sizeof(SubtargetSubTypeKV) * 23 + SparcCPUAliasArraySize + 126, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
724 { sizeof(SubtargetSubTypeKV) * 22 + SparcCPUAliasArraySize + 133, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
725 { sizeof(SubtargetSubTypeKV) * 21 + SparcCPUAliasArraySize + 140, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
726 { sizeof(SubtargetSubTypeKV) * 20 + SparcCPUAliasArraySize + 147, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
727 { sizeof(SubtargetSubTypeKV) * 19 + SparcCPUAliasArraySize + 154, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
728 { sizeof(SubtargetSubTypeKV) * 18 + SparcCPUAliasArraySize + 162, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
729 { sizeof(SubtargetSubTypeKV) * 17 + SparcCPUAliasArraySize + 172, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
730 { sizeof(SubtargetSubTypeKV) * 16 + SparcCPUAliasArraySize + 182, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
731 { sizeof(SubtargetSubTypeKV) * 15 + SparcCPUAliasArraySize + 192, { { { 0x1d4000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
732 { sizeof(SubtargetSubTypeKV) * 14 + SparcCPUAliasArraySize + 200, { { { 0x4001d4000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
733 { sizeof(SubtargetSubTypeKV) * 13 + SparcCPUAliasArraySize + 209, { { { 0x4003dc000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
734 { sizeof(SubtargetSubTypeKV) * 12 + SparcCPUAliasArraySize + 218, { { { 0x4003dc000000084ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
735 { sizeof(SubtargetSubTypeKV) * 11 + SparcCPUAliasArraySize + 227, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
736 { sizeof(SubtargetSubTypeKV) * 10 + SparcCPUAliasArraySize + 236, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
737 { sizeof(SubtargetSubTypeKV) * 9 + SparcCPUAliasArraySize + 246, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
738 { sizeof(SubtargetSubTypeKV) * 8 + SparcCPUAliasArraySize + 259, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
739 { sizeof(SubtargetSubTypeKV) * 7 + SparcCPUAliasArraySize + 270, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
740 { sizeof(SubtargetSubTypeKV) * 6 + SparcCPUAliasArraySize + 277, { { { 0xd0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
741 { sizeof(SubtargetSubTypeKV) * 5 + SparcCPUAliasArraySize + 288, { { { 0x1d0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
742 { sizeof(SubtargetSubTypeKV) * 4 + SparcCPUAliasArraySize + 300, { { { 0x10400000000070ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 },
743 { sizeof(SubtargetSubTypeKV) * 3 + SparcCPUAliasArraySize + 306, { { { 0x2000000040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
744 { sizeof(SubtargetSubTypeKV) * 2 + SparcCPUAliasArraySize + 309, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
745 { sizeof(SubtargetSubTypeKV) * 1 + SparcCPUAliasArraySize + 312, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
746 },
747 { {
748 } },
749 "\000at697e\000at697f\000f934\000generic\000gr712rc\000gr740\000hyperspa"
750 "rc\000leon2\000leon3\000leon4\000leon5\000ma2080\000ma2085\000ma2100\000"
751 "ma2150\000ma2155\000ma2450\000ma2455\000ma2480\000ma2485\000ma2x5x\000m"
752 "a2x8x\000myriad2\000myriad2.1\000myriad2.2\000myriad2.3\000niagara\000n"
753 "iagara2\000niagara3\000niagara4\000sparclet\000sparclite\000sparclite86"
754 "x\000supersparc\000tsc701\000ultrasparc\000ultrasparc3\000ut699\000v7\000"
755 "v8\000v9\000"};
756
757namespace Sparc_MC {
758
759unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
760 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
761 // Don't know how to resolve this scheduling class.
762 return 0;
763}
764
765} // namespace Sparc_MC
766struct SparcGenMCSubtargetInfo : public MCSubtargetInfo {
767 SparcGenMCSubtargetInfo(const Triple &TT,
768 StringRef CPU, StringRef TuneCPU, StringRef FS,
769 StringTable PN,
770 ArrayRef<SubtargetFeatureKV> PF,
771 ArrayRef<SubtargetSubTypeKV> PD,
772 ArrayRef<SubtargetSubTypeAliasKV> PA,
773 const MCSchedModel *PSM,
774 const MCWriteProcResEntry *WPR,
775 const MCWriteLatencyEntry *WL,
776 const MCReadAdvanceEntry *RA, const InstrStage *IS,
777 const unsigned *OC, const unsigned *FP) :
778 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
779 WPR, WL, RA, IS, OC, FP) { }
780
781 unsigned resolveVariantSchedClass(unsigned SchedClass,
782 const MCInst *MI, const MCInstrInfo *MCII,
783 unsigned CPUID) const final {
784 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
785 }
786 unsigned getHwModeSet() const final;
787 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
788};
789unsigned SparcGenMCSubtargetInfo::getHwModeSet() const {
790 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
791 // Collect HwModes and store them as a bit set.
792 unsigned Modes = 0;
793 if (FB[Sparc::Feature64Bit]) Modes |= (1 << 0);
794 return Modes;
795}
796unsigned SparcGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
797 unsigned Modes = getHwModeSet();
798
799 if (!Modes)
800 return Modes;
801
802 switch (type) {
803 case HwMode_Default:
804 return llvm::countr_zero(Modes) + 1;
805 case HwMode_ValueType:
806 // No HwMode for ValueType.
807 return 0;
808 case HwMode_RegInfo:
809 Modes &= 1;
810 if (!Modes)
811 return Modes;
812 if (!llvm::has_single_bit<unsigned>(Modes))
813 llvm_unreachable("Two or more HwModes for RegInfo were found!");
814 return llvm::countr_zero(Modes) + 1;
815 case HwMode_EncodingInfo:
816 // No HwMode for EncodingInfo.
817 return 0;
818 }
819 llvm_unreachable("unexpected HwModeType");
820 return 0; // should not get here
821}
822
823static inline MCSubtargetInfo *createSparcMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
824 return new SparcGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(SparcSubTypeKVStorage.Strings), SparcFeatureKVStorage.Features, SparcSubTypeKVStorage.SubTypes, ArrayRef(SparcSubTypeKVStorage.Aliases).take_front(0), SparcSchedModels,
825 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
826 SparcStages, SparcOperandCycles, SparcForwardingPaths);
827}
828
829
830} // namespace llvm
831
832#endif // GET_SUBTARGETINFO_MC_DESC
833
834#ifdef GET_SUBTARGETINFO_TARGET_DESC
835#undef GET_SUBTARGETINFO_TARGET_DESC
836
837#include "llvm/ADT/BitmaskEnum.h"
838#include "llvm/Support/Debug.h"
839#include "llvm/Support/raw_ostream.h"
840
841// ParseSubtargetFeatures - Parses features string setting specified
842// subtarget options.
843void llvm::SparcSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
844 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
845 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
846 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
847 InitMCProcessorInfo(CPU, TuneCPU, FS);
848 const FeatureBitset &Bits = getFeatureBits();
849 if (Bits[Sparc::DetectRoundChange]) DetectRoundChange = true;
850 if (Bits[Sparc::Feature64Bit]) Is64Bit = true;
851 if (Bits[Sparc::FeatureCrypto]) IsCrypto = true;
852 if (Bits[Sparc::FeatureHardQuad]) HasHardQuad = true;
853 if (Bits[Sparc::FeatureLeon]) IsLeon = true;
854 if (Bits[Sparc::FeatureNoFMULS]) HasNoFMULS = true;
855 if (Bits[Sparc::FeatureNoFSMULD]) HasNoFSMULD = true;
856 if (Bits[Sparc::FeatureOSA2011]) IsOSA2011 = true;
857 if (Bits[Sparc::FeaturePWRPSR]) HasPWRPSR = true;
858 if (Bits[Sparc::FeatureReserveG1]) ReserveRegister[1 + SP::G0] = true;
859 if (Bits[Sparc::FeatureReserveG2]) ReserveRegister[2 + SP::G0] = true;
860 if (Bits[Sparc::FeatureReserveG3]) ReserveRegister[3 + SP::G0] = true;
861 if (Bits[Sparc::FeatureReserveG4]) ReserveRegister[4 + SP::G0] = true;
862 if (Bits[Sparc::FeatureReserveG5]) ReserveRegister[5 + SP::G0] = true;
863 if (Bits[Sparc::FeatureReserveG6]) ReserveRegister[6 + SP::G0] = true;
864 if (Bits[Sparc::FeatureReserveG7]) ReserveRegister[7 + SP::G0] = true;
865 if (Bits[Sparc::FeatureReserveI0]) ReserveRegister[0 + SP::I0] = true;
866 if (Bits[Sparc::FeatureReserveI1]) ReserveRegister[1 + SP::I0] = true;
867 if (Bits[Sparc::FeatureReserveI2]) ReserveRegister[2 + SP::I0] = true;
868 if (Bits[Sparc::FeatureReserveI3]) ReserveRegister[3 + SP::I0] = true;
869 if (Bits[Sparc::FeatureReserveI4]) ReserveRegister[4 + SP::I0] = true;
870 if (Bits[Sparc::FeatureReserveI5]) ReserveRegister[5 + SP::I0] = true;
871 if (Bits[Sparc::FeatureReserveL0]) ReserveRegister[0 + SP::L0] = true;
872 if (Bits[Sparc::FeatureReserveL1]) ReserveRegister[1 + SP::L0] = true;
873 if (Bits[Sparc::FeatureReserveL2]) ReserveRegister[2 + SP::L0] = true;
874 if (Bits[Sparc::FeatureReserveL3]) ReserveRegister[3 + SP::L0] = true;
875 if (Bits[Sparc::FeatureReserveL4]) ReserveRegister[4 + SP::L0] = true;
876 if (Bits[Sparc::FeatureReserveL5]) ReserveRegister[5 + SP::L0] = true;
877 if (Bits[Sparc::FeatureReserveL6]) ReserveRegister[6 + SP::L0] = true;
878 if (Bits[Sparc::FeatureReserveL7]) ReserveRegister[7 + SP::L0] = true;
879 if (Bits[Sparc::FeatureReserveO0]) ReserveRegister[0 + SP::O0] = true;
880 if (Bits[Sparc::FeatureReserveO1]) ReserveRegister[1 + SP::O0] = true;
881 if (Bits[Sparc::FeatureReserveO2]) ReserveRegister[2 + SP::O0] = true;
882 if (Bits[Sparc::FeatureReserveO3]) ReserveRegister[3 + SP::O0] = true;
883 if (Bits[Sparc::FeatureReserveO4]) ReserveRegister[4 + SP::O0] = true;
884 if (Bits[Sparc::FeatureReserveO5]) ReserveRegister[5 + SP::O0] = true;
885 if (Bits[Sparc::FeatureSoftFloat]) UseSoftFloat = true;
886 if (Bits[Sparc::FeatureSoftMulDiv]) UseSoftMulDiv = true;
887 if (Bits[Sparc::FeatureUA2005]) IsUA2005 = true;
888 if (Bits[Sparc::FeatureUA2007]) IsUA2007 = true;
889 if (Bits[Sparc::FeatureV8Deprecated]) UseV8DeprecatedInsts = true;
890 if (Bits[Sparc::FeatureV8Plus]) IsV8Plus = true;
891 if (Bits[Sparc::FeatureV9]) IsV9 = true;
892 if (Bits[Sparc::FeatureVIS]) IsVIS = true;
893 if (Bits[Sparc::FeatureVIS2]) IsVIS2 = true;
894 if (Bits[Sparc::FeatureVIS3]) IsVIS3 = true;
895 if (Bits[Sparc::FixAllFDIVSQRT]) FixAllFDIVSQRT = true;
896 if (Bits[Sparc::FixTN0009]) FixTN0009 = true;
897 if (Bits[Sparc::FixTN0010]) FixTN0010 = true;
898 if (Bits[Sparc::FixTN0011]) FixTN0011 = true;
899 if (Bits[Sparc::FixTN0012]) FixTN0012 = true;
900 if (Bits[Sparc::FixTN0013]) FixTN0013 = true;
901 if (Bits[Sparc::InsertNOPLoad]) InsertNOPLoad = true;
902 if (Bits[Sparc::LeonCASA]) HasLeonCasa = true;
903 if (Bits[Sparc::LeonCycleCounter]) HasLeonCycleCounter = true;
904 if (Bits[Sparc::TuneNoPredictor]) HasNoPredictor = true;
905 if (Bits[Sparc::TuneSlowRDPC]) HasSlowRDPC = true;
906 if (Bits[Sparc::UMACSMACSupport]) HasUmacSmac = true;
907 if (Bits[Sparc::UsePopc]) UsePopc = true;
908}
909
910#endif // GET_SUBTARGETINFO_TARGET_DESC
911
912#ifdef GET_SUBTARGETINFO_HEADER
913#undef GET_SUBTARGETINFO_HEADER
914
915namespace llvm {
916
917class DFAPacketizer;
918namespace Sparc_MC {
919
920unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
921
922} // namespace Sparc_MC
923struct SparcGenSubtargetInfo : public TargetSubtargetInfo {
924 explicit SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
925public:
926 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
927 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
928 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
929 enum class SparcHwModeBits : unsigned {
930 DefaultMode = 0,
931 SPARC64 = (1 << 0),
932
933 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/SPARC64),
934 };
935 unsigned getHwModeSet() const final;
936 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
937 const FeatureBitset &getInlineIgnoreFeatures() const override;
938 const FeatureBitset &getInlineInverseFeatures() const override;
939 const FeatureBitset &getInlineMustMatchFeatures() const override;
940};
941
942} // namespace llvm
943
944#endif // GET_SUBTARGETINFO_HEADER
945
946#ifdef GET_SUBTARGETINFO_CTOR
947#undef GET_SUBTARGETINFO_CTOR
948
949#include "llvm/CodeGen/TargetSchedule.h"
950
951namespace llvm {
952
953extern const llvm::StringRef SparcNames[];
954extern const llvm::SubtargetFeatureKVStorage<59, 3417> SparcFeatureKVStorage;
955extern const llvm::SubtargetSubTypeKVStorage<41, 0, 316> SparcSubTypeKVStorage;
956extern const llvm::MCSchedModel SparcSchedModels[];
957extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[];
958extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[];
959extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[];
960extern const llvm::InstrStage SparcStages[];
961extern const unsigned SparcOperandCycles[];
962extern const unsigned SparcForwardingPaths[];
963SparcGenSubtargetInfo::SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
964 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(SparcSubTypeKVStorage.Strings), ArrayRef(SparcFeatureKVStorage.Features), ArrayRef(SparcSubTypeKVStorage.SubTypes), ArrayRef(SparcSubTypeKVStorage.Aliases).take_front(0), SparcSchedModels,
965 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
966 SparcStages, SparcOperandCycles, SparcForwardingPaths) {}
967
968unsigned SparcGenSubtargetInfo
969::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
970 report_fatal_error("Expected a variant SchedClass");
971} // SparcGenSubtargetInfo::resolveSchedClass
972
973unsigned SparcGenSubtargetInfo
974::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
975 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
976} // SparcGenSubtargetInfo::resolveVariantSchedClass
977
978unsigned SparcGenSubtargetInfo::getHwModeSet() const {
979 [[maybe_unused]] const auto *Subtarget =
980 static_cast<const SparcSubtarget *>(this);
981 // Collect HwModes and store them as a bit set.
982 unsigned Modes = 0;
983 if ((Subtarget->is64Bit())) Modes |= (1 << 0);
984 return Modes;
985}
986unsigned SparcGenSubtargetInfo::getHwMode(enum HwModeType type) const {
987 unsigned Modes = getHwModeSet();
988
989 if (!Modes)
990 return Modes;
991
992 switch (type) {
993 case HwMode_Default:
994 return llvm::countr_zero(Modes) + 1;
995 case HwMode_ValueType:
996 // No HwMode for ValueType.
997 return 0;
998 case HwMode_RegInfo:
999 Modes &= 1;
1000 if (!Modes)
1001 return Modes;
1002 if (!llvm::has_single_bit<unsigned>(Modes))
1003 llvm_unreachable("Two or more HwModes for RegInfo were found!");
1004 return llvm::countr_zero(Modes) + 1;
1005 case HwMode_EncodingInfo:
1006 // No HwMode for EncodingInfo.
1007 return 0;
1008 }
1009 llvm_unreachable("unexpected HwModeType");
1010 return 0; // should not get here
1011}
1012const FeatureBitset &SparcGenSubtargetInfo::getInlineIgnoreFeatures() const {
1013 static constexpr FeatureBitset Features = {
1014 };
1015 return Features;
1016}
1017
1018const FeatureBitset &SparcGenSubtargetInfo::getInlineInverseFeatures() const {
1019 static constexpr FeatureBitset Features = {
1020 };
1021 return Features;
1022}
1023
1024const FeatureBitset &SparcGenSubtargetInfo::getInlineMustMatchFeatures() const {
1025 static constexpr FeatureBitset Features = {
1026 };
1027 return Features;
1028}
1029
1030
1031} // namespace llvm
1032
1033#endif // GET_SUBTARGETINFO_CTOR
1034
1035#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
1036#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
1037
1038
1039#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
1040
1041#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
1042#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
1043
1044
1045#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
1046
1047