1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace Sparc {
15
16enum {
17 DetectRoundChange = 0,
18 Feature64Bit = 1,
19 FeatureCrypto = 2,
20 FeatureHardQuad = 3,
21 FeatureLeon = 4,
22 FeatureNoFMULS = 5,
23 FeatureNoFSMULD = 6,
24 FeatureOSA2011 = 7,
25 FeaturePWRPSR = 8,
26 FeatureReserveG1 = 9,
27 FeatureReserveG2 = 10,
28 FeatureReserveG3 = 11,
29 FeatureReserveG4 = 12,
30 FeatureReserveG5 = 13,
31 FeatureReserveG6 = 14,
32 FeatureReserveG7 = 15,
33 FeatureReserveI0 = 16,
34 FeatureReserveI1 = 17,
35 FeatureReserveI2 = 18,
36 FeatureReserveI3 = 19,
37 FeatureReserveI4 = 20,
38 FeatureReserveI5 = 21,
39 FeatureReserveL0 = 22,
40 FeatureReserveL1 = 23,
41 FeatureReserveL2 = 24,
42 FeatureReserveL3 = 25,
43 FeatureReserveL4 = 26,
44 FeatureReserveL5 = 27,
45 FeatureReserveL6 = 28,
46 FeatureReserveL7 = 29,
47 FeatureReserveO0 = 30,
48 FeatureReserveO1 = 31,
49 FeatureReserveO2 = 32,
50 FeatureReserveO3 = 33,
51 FeatureReserveO4 = 34,
52 FeatureReserveO5 = 35,
53 FeatureSoftFloat = 36,
54 FeatureSoftMulDiv = 37,
55 FeatureUA2005 = 38,
56 FeatureUA2007 = 39,
57 FeatureV8Deprecated = 40,
58 FeatureV8Plus = 41,
59 FeatureV9 = 42,
60 FeatureVIS = 43,
61 FeatureVIS2 = 44,
62 FeatureVIS3 = 45,
63 FixAllFDIVSQRT = 46,
64 FixTN0009 = 47,
65 FixTN0010 = 48,
66 FixTN0011 = 49,
67 FixTN0012 = 50,
68 FixTN0013 = 51,
69 InsertNOPLoad = 52,
70 LeonCASA = 53,
71 LeonCycleCounter = 54,
72 TuneNoPredictor = 55,
73 TuneSlowRDPC = 56,
74 UMACSMACSupport = 57,
75 UsePopc = 58,
76 NumSubtargetFeatures = 59
77};
78
79} // namespace Sparc
80
81} // namespace llvm
82
83#endif // GET_SUBTARGETINFO_ENUM
84
85#ifdef GET_SUBTARGETINFO_MACRO
86
87GET_SUBTARGETINFO_MACRO(DetectRoundChange, false, detectRoundChange)
88GET_SUBTARGETINFO_MACRO(FixAllFDIVSQRT, false, fixAllFDIVSQRT)
89GET_SUBTARGETINFO_MACRO(FixTN0009, false, fixTN0009)
90GET_SUBTARGETINFO_MACRO(FixTN0010, false, fixTN0010)
91GET_SUBTARGETINFO_MACRO(FixTN0011, false, fixTN0011)
92GET_SUBTARGETINFO_MACRO(FixTN0012, false, fixTN0012)
93GET_SUBTARGETINFO_MACRO(FixTN0013, false, fixTN0013)
94GET_SUBTARGETINFO_MACRO(HasHardQuad, false, hasHardQuad)
95GET_SUBTARGETINFO_MACRO(HasLeonCasa, false, hasLeonCasa)
96GET_SUBTARGETINFO_MACRO(HasLeonCycleCounter, false, hasLeonCycleCounter)
97GET_SUBTARGETINFO_MACRO(HasNoFMULS, false, hasNoFMULS)
98GET_SUBTARGETINFO_MACRO(HasNoFSMULD, false, hasNoFSMULD)
99GET_SUBTARGETINFO_MACRO(HasNoPredictor, false, hasNoPredictor)
100GET_SUBTARGETINFO_MACRO(HasPWRPSR, false, hasPWRPSR)
101GET_SUBTARGETINFO_MACRO(HasSlowRDPC, false, hasSlowRDPC)
102GET_SUBTARGETINFO_MACRO(HasUmacSmac, false, hasUmacSmac)
103GET_SUBTARGETINFO_MACRO(InsertNOPLoad, false, insertNOPLoad)
104GET_SUBTARGETINFO_MACRO(Is64Bit, false, is64Bit)
105GET_SUBTARGETINFO_MACRO(IsCrypto, false, isCrypto)
106GET_SUBTARGETINFO_MACRO(IsLeon, false, isLeon)
107GET_SUBTARGETINFO_MACRO(IsOSA2011, false, isOSA2011)
108GET_SUBTARGETINFO_MACRO(IsUA2005, false, isUA2005)
109GET_SUBTARGETINFO_MACRO(IsUA2007, false, isUA2007)
110GET_SUBTARGETINFO_MACRO(IsV8Plus, false, isV8Plus)
111GET_SUBTARGETINFO_MACRO(IsV9, false, isV9)
112GET_SUBTARGETINFO_MACRO(IsVIS, false, isVIS)
113GET_SUBTARGETINFO_MACRO(IsVIS2, false, isVIS2)
114GET_SUBTARGETINFO_MACRO(IsVIS3, false, isVIS3)
115GET_SUBTARGETINFO_MACRO(UsePopc, false, usePopc)
116GET_SUBTARGETINFO_MACRO(UseSoftFloat, false, useSoftFloat)
117GET_SUBTARGETINFO_MACRO(UseSoftMulDiv, false, useSoftMulDiv)
118GET_SUBTARGETINFO_MACRO(UseV8DeprecatedInsts, false, useV8DeprecatedInsts)
119
120#undef GET_SUBTARGETINFO_MACRO
121#endif // GET_SUBTARGETINFO_MACRO
122
123#ifdef GET_SUBTARGETINFO_MC_DESC
124#undef GET_SUBTARGETINFO_MC_DESC
125
126namespace llvm {
127
128// Sorted (by key) array of values for CPU features.
129extern const llvm::SubtargetFeatureKVStorage< 59, 3417> SparcFeatureKVStorage = {
130 {
131 { sizeof(SubtargetFeatureKV) * 59 + 1, sizeof(SubtargetFeatureKV) * 59 + 7, Sparc::Feature64Bit, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
132 { sizeof(SubtargetFeatureKV) * 58 + 26, sizeof(SubtargetFeatureKV) * 58 + 33, Sparc::FeatureCrypto, { { { 0x80ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
133 { sizeof(SubtargetFeatureKV) * 57 + 65, sizeof(SubtargetFeatureKV) * 57 + 79, Sparc::FeatureV8Deprecated, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
134 { sizeof(SubtargetFeatureKV) * 56 + 124, sizeof(SubtargetFeatureKV) * 56 + 142, Sparc::DetectRoundChange, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
135 { sizeof(SubtargetFeatureKV) * 55 + 253, sizeof(SubtargetFeatureKV) * 55 + 264, Sparc::FixTN0009, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
136 { sizeof(SubtargetFeatureKV) * 54 + 320, sizeof(SubtargetFeatureKV) * 54 + 331, Sparc::FixTN0010, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
137 { sizeof(SubtargetFeatureKV) * 53 + 387, sizeof(SubtargetFeatureKV) * 53 + 398, Sparc::FixTN0011, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
138 { sizeof(SubtargetFeatureKV) * 52 + 454, sizeof(SubtargetFeatureKV) * 52 + 465, Sparc::FixTN0012, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
139 { sizeof(SubtargetFeatureKV) * 51 + 521, sizeof(SubtargetFeatureKV) * 51 + 532, Sparc::FixTN0013, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
140 { sizeof(SubtargetFeatureKV) * 50 + 588, sizeof(SubtargetFeatureKV) * 50 + 603, Sparc::FixAllFDIVSQRT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
141 { sizeof(SubtargetFeatureKV) * 49 + 699, sizeof(SubtargetFeatureKV) * 49 + 715, Sparc::FeatureHardQuad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
142 { sizeof(SubtargetFeatureKV) * 48 + 760, sizeof(SubtargetFeatureKV) * 48 + 772, Sparc::LeonCASA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
143 { sizeof(SubtargetFeatureKV) * 47 + 827, sizeof(SubtargetFeatureKV) * 47 + 839, Sparc::UMACSMACSupport, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
144 { sizeof(SubtargetFeatureKV) * 46 + 891, sizeof(SubtargetFeatureKV) * 46 + 905, Sparc::InsertNOPLoad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
145 { sizeof(SubtargetFeatureKV) * 45 + 1051, sizeof(SubtargetFeatureKV) * 45 + 1056, Sparc::FeatureLeon, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
146 { sizeof(SubtargetFeatureKV) * 44 + 1079, sizeof(SubtargetFeatureKV) * 44 + 1096, Sparc::LeonCycleCounter, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
147 { sizeof(SubtargetFeatureKV) * 43 + 1132, sizeof(SubtargetFeatureKV) * 43 + 1143, Sparc::FeaturePWRPSR, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
148 { sizeof(SubtargetFeatureKV) * 42 + 1173, sizeof(SubtargetFeatureKV) * 42 + 1182, Sparc::FeatureNoFMULS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
149 { sizeof(SubtargetFeatureKV) * 41 + 1213, sizeof(SubtargetFeatureKV) * 41 + 1223, Sparc::FeatureNoFSMULD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
150 { sizeof(SubtargetFeatureKV) * 40 + 1255, sizeof(SubtargetFeatureKV) * 40 + 1268, Sparc::TuneNoPredictor, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
151 { sizeof(SubtargetFeatureKV) * 39 + 1328, sizeof(SubtargetFeatureKV) * 39 + 1336, Sparc::FeatureOSA2011, { { { 0x3c0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
152 { sizeof(SubtargetFeatureKV) * 38 + 1385, sizeof(SubtargetFeatureKV) * 38 + 1390, Sparc::UsePopc, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
153 { sizeof(SubtargetFeatureKV) * 37 + 1434, sizeof(SubtargetFeatureKV) * 37 + 1445, Sparc::FeatureReserveG1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
154 { sizeof(SubtargetFeatureKV) * 36 + 1488, sizeof(SubtargetFeatureKV) * 36 + 1499, Sparc::FeatureReserveG2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
155 { sizeof(SubtargetFeatureKV) * 35 + 1542, sizeof(SubtargetFeatureKV) * 35 + 1553, Sparc::FeatureReserveG3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
156 { sizeof(SubtargetFeatureKV) * 34 + 1596, sizeof(SubtargetFeatureKV) * 34 + 1607, Sparc::FeatureReserveG4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
157 { sizeof(SubtargetFeatureKV) * 33 + 1650, sizeof(SubtargetFeatureKV) * 33 + 1661, Sparc::FeatureReserveG5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
158 { sizeof(SubtargetFeatureKV) * 32 + 1704, sizeof(SubtargetFeatureKV) * 32 + 1715, Sparc::FeatureReserveG6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
159 { sizeof(SubtargetFeatureKV) * 31 + 1758, sizeof(SubtargetFeatureKV) * 31 + 1769, Sparc::FeatureReserveG7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
160 { sizeof(SubtargetFeatureKV) * 30 + 1812, sizeof(SubtargetFeatureKV) * 30 + 1823, Sparc::FeatureReserveI0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
161 { sizeof(SubtargetFeatureKV) * 29 + 1866, sizeof(SubtargetFeatureKV) * 29 + 1877, Sparc::FeatureReserveI1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
162 { sizeof(SubtargetFeatureKV) * 28 + 1920, sizeof(SubtargetFeatureKV) * 28 + 1931, Sparc::FeatureReserveI2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
163 { sizeof(SubtargetFeatureKV) * 27 + 1974, sizeof(SubtargetFeatureKV) * 27 + 1985, Sparc::FeatureReserveI3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
164 { sizeof(SubtargetFeatureKV) * 26 + 2028, sizeof(SubtargetFeatureKV) * 26 + 2039, Sparc::FeatureReserveI4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
165 { sizeof(SubtargetFeatureKV) * 25 + 2082, sizeof(SubtargetFeatureKV) * 25 + 2093, Sparc::FeatureReserveI5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
166 { sizeof(SubtargetFeatureKV) * 24 + 2136, sizeof(SubtargetFeatureKV) * 24 + 2147, Sparc::FeatureReserveL0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
167 { sizeof(SubtargetFeatureKV) * 23 + 2190, sizeof(SubtargetFeatureKV) * 23 + 2201, Sparc::FeatureReserveL1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
168 { sizeof(SubtargetFeatureKV) * 22 + 2244, sizeof(SubtargetFeatureKV) * 22 + 2255, Sparc::FeatureReserveL2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
169 { sizeof(SubtargetFeatureKV) * 21 + 2298, sizeof(SubtargetFeatureKV) * 21 + 2309, Sparc::FeatureReserveL3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
170 { sizeof(SubtargetFeatureKV) * 20 + 2352, sizeof(SubtargetFeatureKV) * 20 + 2363, Sparc::FeatureReserveL4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
171 { sizeof(SubtargetFeatureKV) * 19 + 2406, sizeof(SubtargetFeatureKV) * 19 + 2417, Sparc::FeatureReserveL5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
172 { sizeof(SubtargetFeatureKV) * 18 + 2460, sizeof(SubtargetFeatureKV) * 18 + 2471, Sparc::FeatureReserveL6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
173 { sizeof(SubtargetFeatureKV) * 17 + 2514, sizeof(SubtargetFeatureKV) * 17 + 2525, Sparc::FeatureReserveL7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
174 { sizeof(SubtargetFeatureKV) * 16 + 2568, sizeof(SubtargetFeatureKV) * 16 + 2579, Sparc::FeatureReserveO0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
175 { sizeof(SubtargetFeatureKV) * 15 + 2622, sizeof(SubtargetFeatureKV) * 15 + 2633, Sparc::FeatureReserveO1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
176 { sizeof(SubtargetFeatureKV) * 14 + 2676, sizeof(SubtargetFeatureKV) * 14 + 2687, Sparc::FeatureReserveO2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
177 { sizeof(SubtargetFeatureKV) * 13 + 2730, sizeof(SubtargetFeatureKV) * 13 + 2741, Sparc::FeatureReserveO3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
178 { sizeof(SubtargetFeatureKV) * 12 + 2784, sizeof(SubtargetFeatureKV) * 12 + 2795, Sparc::FeatureReserveO4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
179 { sizeof(SubtargetFeatureKV) * 11 + 2838, sizeof(SubtargetFeatureKV) * 11 + 2849, Sparc::FeatureReserveO5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
180 { sizeof(SubtargetFeatureKV) * 10 + 2892, sizeof(SubtargetFeatureKV) * 10 + 2902, Sparc::TuneSlowRDPC, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
181 { sizeof(SubtargetFeatureKV) * 9 + 2922, sizeof(SubtargetFeatureKV) * 9 + 2933, Sparc::FeatureSoftFloat, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
182 { sizeof(SubtargetFeatureKV) * 8 + 2975, sizeof(SubtargetFeatureKV) * 8 + 2988, Sparc::FeatureSoftMulDiv, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
183 { sizeof(SubtargetFeatureKV) * 7 + 3043, sizeof(SubtargetFeatureKV) * 7 + 3050, Sparc::FeatureUA2005, { { { 0x1c0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
184 { sizeof(SubtargetFeatureKV) * 6 + 3097, sizeof(SubtargetFeatureKV) * 6 + 3104, Sparc::FeatureUA2007, { { { 0x1c0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
185 { sizeof(SubtargetFeatureKV) * 5 + 3151, sizeof(SubtargetFeatureKV) * 5 + 3158, Sparc::FeatureV8Plus, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
186 { sizeof(SubtargetFeatureKV) * 4 + 3229, sizeof(SubtargetFeatureKV) * 4 + 3232, Sparc::FeatureV9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
187 { sizeof(SubtargetFeatureKV) * 3 + 3261, sizeof(SubtargetFeatureKV) * 3 + 3265, Sparc::FeatureVIS, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
188 { sizeof(SubtargetFeatureKV) * 2 + 3317, sizeof(SubtargetFeatureKV) * 2 + 3322, Sparc::FeatureVIS2, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
189 { sizeof(SubtargetFeatureKV) * 1 + 3366, sizeof(SubtargetFeatureKV) * 1 + 3371, Sparc::FeatureVIS3, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
190 },
191 "\000" "64bit\000Enable 64-bit mode\000crypto\000Enable cryptographic ex"
192 "tensions\000deprecated-v8\000Enable deprecated V8 instructions in V9 mo"
193 "de\000detectroundchange\000LEON3 erratum detection: Detects any roundin"
194 "g mode change request: use only the round-to-nearest rounding mode\000f"
195 "ix-tn0009\000Enable workaround for errata described in GRLIB-TN-0009\000"
196 "fix-tn0010\000Enable workaround for errata described in GRLIB-TN-0010\000"
197 "fix-tn0011\000Enable workaround for errata described in GRLIB-TN-0011\000"
198 "fix-tn0012\000Enable workaround for errata described in GRLIB-TN-0012\000"
199 "fix-tn0013\000Enable workaround for errata described in GRLIB-TN-0013\000"
200 "fixallfdivsqrt\000LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instr"
201 "uctions with NOPs and floating-point store\000hard-quad-float\000Enable"
202 " quad-word floating point instructions\000hasleoncasa\000Enable CASA in"
203 "struction for LEON3 and LEON4 processors\000hasumacsmac\000Enable UMAC "
204 "and SMAC for LEON3 and LEON4 processors\000insertnopload\000LEON3 errat"
205 "um fix: Insert a NOP instruction after every single-cycle load instruct"
206 "ion when the next instruction is another load/store instruction\000leon"
207 "\000Enable LEON extensions\000leoncyclecounter\000Use the Leon cycle co"
208 "unter register\000leonpwrpsr\000Enable the PWRPSR instruction\000no-fmu"
209 "ls\000Disable the fmuls instruction.\000no-fsmuld\000Disable the fsmuld"
210 " instruction.\000no-predictor\000Processor has no branch predictor, bra"
211 "nches stall execution\000osa2011\000Enable Oracle SPARC Architecture 20"
212 "11 extensions\000popc\000Use the popc (population count) instruction\000"
213 "reserve-g1\000Reserve G1, making it unavailable as a GPR\000reserve-g2\000"
214 "Reserve G2, making it unavailable as a GPR\000reserve-g3\000Reserve G3,"
215 " making it unavailable as a GPR\000reserve-g4\000Reserve G4, making it "
216 "unavailable as a GPR\000reserve-g5\000Reserve G5, making it unavailable"
217 " as a GPR\000reserve-g6\000Reserve G6, making it unavailable as a GPR\000"
218 "reserve-g7\000Reserve G7, making it unavailable as a GPR\000reserve-i0\000"
219 "Reserve I0, making it unavailable as a GPR\000reserve-i1\000Reserve I1,"
220 " making it unavailable as a GPR\000reserve-i2\000Reserve I2, making it "
221 "unavailable as a GPR\000reserve-i3\000Reserve I3, making it unavailable"
222 " as a GPR\000reserve-i4\000Reserve I4, making it unavailable as a GPR\000"
223 "reserve-i5\000Reserve I5, making it unavailable as a GPR\000reserve-l0\000"
224 "Reserve L0, making it unavailable as a GPR\000reserve-l1\000Reserve L1,"
225 " making it unavailable as a GPR\000reserve-l2\000Reserve L2, making it "
226 "unavailable as a GPR\000reserve-l3\000Reserve L3, making it unavailable"
227 " as a GPR\000reserve-l4\000Reserve L4, making it unavailable as a GPR\000"
228 "reserve-l5\000Reserve L5, making it unavailable as a GPR\000reserve-l6\000"
229 "Reserve L6, making it unavailable as a GPR\000reserve-l7\000Reserve L7,"
230 " making it unavailable as a GPR\000reserve-o0\000Reserve O0, making it "
231 "unavailable as a GPR\000reserve-o1\000Reserve O1, making it unavailable"
232 " as a GPR\000reserve-o2\000Reserve O2, making it unavailable as a GPR\000"
233 "reserve-o3\000Reserve O3, making it unavailable as a GPR\000reserve-o4\000"
234 "Reserve O4, making it unavailable as a GPR\000reserve-o5\000Reserve O5,"
235 " making it unavailable as a GPR\000slow-rdpc\000rd %pc, %XX is slow\000"
236 "soft-float\000Use software emulation for floating point\000soft-mul-div"
237 "\000Use software emulation for integer multiply and divide\000ua2005\000"
238 "Enable UltraSPARC Architecture 2005 extensions\000ua2007\000Enable Ultr"
239 "aSPARC Architecture 2007 extensions\000v8plus\000Enable V8+ mode, allow"
240 "ing use of 64-bit V9 instructions in 32-bit code\000v9\000Enable SPARC-"
241 "V9 instructions\000vis\000Enable UltraSPARC Visual Instruction Set exte"
242 "nsions\000vis2\000Enable Visual Instruction Set extensions II\000vis3\000"
243 "Enable Visual Instruction Set extensions III\000"};
244
245#ifdef DBGFIELD
246#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
247#endif
248#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
249#define DBGFIELD(x) x,
250#define DBGVAL_OR_NULLPTR(x) x
251#else
252#define DBGFIELD(x)
253#define DBGVAL_OR_NULLPTR(x) nullptr
254#endif
255
256// Functional units for "LEON2Itineraries"
257namespace LEON2ItinerariesFU {
258
259 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
260 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
261
262} // namespace LEON2ItinerariesFU
263
264// Functional units for "LEON3Itineraries"
265namespace LEON3ItinerariesFU {
266
267 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
268 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
269
270} // namespace LEON3ItinerariesFU
271
272// Functional units for "LEON4Itineraries"
273namespace LEON4ItinerariesFU {
274
275 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
276 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
277
278} // namespace LEON4ItinerariesFU
279
280extern const llvm::InstrStage SparcStages[] = {
281 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
282 { 1, LEON2ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
283 { 1, LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
284 { 1, LEON2ItinerariesFU::LEONIU | LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
285 { 1, LEON3ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
286 { 1, LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
287 { 1, LEON3ItinerariesFU::LEONIU | LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
288 { 1, LEON4ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
289 { 1, LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 8
290 { 1, LEON4ItinerariesFU::LEONIU | LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 9
291 { 0, 0, 0, llvm::InstrStage::Required } // End stages
292};
293extern const unsigned SparcOperandCycles[] = {
294 0, // No itinerary
295 1, 1, // 1-2
296 7, 1, // 3-4
297 2, 1, // 5-6
298 2, 1, // 7-8
299 7, 1, // 9-10
300 36, 1, // 11-12
301 20, 1, // 13-14
302 21, 1, // 15-16
303 16, 1, // 17-18
304 2, 1, // 19-20
305 65, 1, // 21-22
306 37, 1, // 23-24
307 2, 1, // 25-26
308 2, 1, // 27-28
309 1, 1, // 29-30
310 35, 1, // 31-32
311 5, 1, // 33-34
312 2, 1, // 35-36
313 3, 1, // 37-38
314 5, 1, // 39-40
315 1, 1, // 41-42
316 7, 1, // 43-44
317 3, 1, // 45-46
318 2, 1, // 47-48
319 4, 1, // 49-50
320 17, 1, // 51-52
321 16, 1, // 53-54
322 4, 1, // 55-56
323 4, 1, // 57-58
324 2, 1, // 59-60
325 25, 1, // 61-62
326 24, 1, // 63-64
327 4, 1, // 65-66
328 2, 1, // 67-68
329 1, 1, // 69-70
330 35, 1, // 71-72
331 2, 1, // 73-74
332 1, 1, // 75-76
333 4, 1, // 77-78
334 5, 1, // 79-80
335 4, 1, // 81-82
336 1, 1, // 83-84
337 7, 1, // 85-86
338 3, 1, // 87-88
339 2, 1, // 89-90
340 4, 1, // 91-92
341 17, 1, // 93-94
342 16, 1, // 95-96
343 4, 1, // 97-98
344 4, 1, // 99-100
345 2, 1, // 101-102
346 25, 1, // 103-104
347 24, 1, // 105-106
348 4, 1, // 107-108
349 1, 1, // 109-110
350 1, 1, // 111-112
351 35, 1, // 113-114
352 2, 1, // 115-116
353 1, 1, // 117-118
354 1, 1, // 119-120
355 1, 1, // 121-122
356 4, 1, // 123-124
357 0 // End operand cycles
358};
359extern const unsigned SparcForwardingPaths[] = {
360 0, // No itinerary
361 0, 0, // 1-2
362 0, 0, // 3-4
363 0, 0, // 5-6
364 0, 0, // 7-8
365 0, 0, // 9-10
366 0, 0, // 11-12
367 0, 0, // 13-14
368 0, 0, // 15-16
369 0, 0, // 17-18
370 0, 0, // 19-20
371 0, 0, // 21-22
372 0, 0, // 23-24
373 0, 0, // 25-26
374 0, 0, // 27-28
375 0, 0, // 29-30
376 0, 0, // 31-32
377 0, 0, // 33-34
378 0, 0, // 35-36
379 0, 0, // 37-38
380 0, 0, // 39-40
381 0, 0, // 41-42
382 0, 0, // 43-44
383 0, 0, // 45-46
384 0, 0, // 47-48
385 0, 0, // 49-50
386 0, 0, // 51-52
387 0, 0, // 53-54
388 0, 0, // 55-56
389 0, 0, // 57-58
390 0, 0, // 59-60
391 0, 0, // 61-62
392 0, 0, // 63-64
393 0, 0, // 65-66
394 0, 0, // 67-68
395 0, 0, // 69-70
396 0, 0, // 71-72
397 0, 0, // 73-74
398 0, 0, // 75-76
399 0, 0, // 77-78
400 0, 0, // 79-80
401 0, 0, // 81-82
402 0, 0, // 83-84
403 0, 0, // 85-86
404 0, 0, // 87-88
405 0, 0, // 89-90
406 0, 0, // 91-92
407 0, 0, // 93-94
408 0, 0, // 95-96
409 0, 0, // 97-98
410 0, 0, // 99-100
411 0, 0, // 101-102
412 0, 0, // 103-104
413 0, 0, // 105-106
414 0, 0, // 107-108
415 0, 0, // 109-110
416 0, 0, // 111-112
417 0, 0, // 113-114
418 0, 0, // 115-116
419 0, 0, // 117-118
420 0, 0, // 119-120
421 0, 0, // 121-122
422 0, 0, // 123-124
423 0 // End bypass tables
424};
425
426static constexpr llvm::InstrItinerary LEON2Itineraries[] = {
427 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
428 { 1, 1, 2, 1, 3 }, // 1 IIC_iu_instr
429 { 1, 2, 3, 3, 5 }, // 2 IIC_fpu_normal_instr
430 { 1, 3, 4, 5, 7 }, // 3 IIC_jmp_or_call
431 { 1, 2, 3, 7, 9 }, // 4 IIC_fpu_abs
432 { 1, 2, 3, 9, 11 }, // 5 IIC_fpu_fast_instr
433 { 1, 2, 3, 11, 13 }, // 6 IIC_fpu_divd
434 { 1, 2, 3, 13, 15 }, // 7 IIC_fpu_divs
435 { 1, 2, 3, 15, 17 }, // 8 IIC_fpu_muld
436 { 1, 2, 3, 17, 19 }, // 9 IIC_fpu_muls
437 { 1, 2, 3, 19, 21 }, // 10 IIC_fpu_negs
438 { 1, 2, 3, 21, 23 }, // 11 IIC_fpu_sqrtd
439 { 1, 2, 3, 23, 25 }, // 12 IIC_fpu_sqrts
440 { 1, 2, 3, 25, 27 }, // 13 IIC_fpu_stod
441 { 1, 3, 4, 27, 29 }, // 14 IIC_ldd
442 { 1, 3, 4, 29, 31 }, // 15 IIC_iu_or_fpu_instr
443 { 1, 1, 2, 31, 33 }, // 16 IIC_iu_div
444 { 0, 0, 0, 0, 0 }, // 17 IIC_smac_umac
445 { 1, 1, 2, 33, 35 }, // 18 IIC_iu_smul
446 { 1, 3, 4, 35, 37 }, // 19 IIC_st
447 { 1, 3, 4, 37, 39 }, // 20 IIC_std
448 { 1, 1, 2, 39, 41 }, // 21 IIC_iu_umul
449 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
450};
451
452static constexpr llvm::InstrItinerary LEON3Itineraries[] = {
453 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
454 { 1, 4, 5, 41, 43 }, // 1 IIC_iu_instr
455 { 1, 5, 6, 43, 45 }, // 2 IIC_fpu_normal_instr
456 { 1, 6, 7, 45, 47 }, // 3 IIC_jmp_or_call
457 { 1, 5, 6, 47, 49 }, // 4 IIC_fpu_abs
458 { 1, 5, 6, 49, 51 }, // 5 IIC_fpu_fast_instr
459 { 1, 5, 6, 51, 53 }, // 6 IIC_fpu_divd
460 { 1, 5, 6, 53, 55 }, // 7 IIC_fpu_divs
461 { 1, 5, 6, 55, 57 }, // 8 IIC_fpu_muld
462 { 1, 5, 6, 57, 59 }, // 9 IIC_fpu_muls
463 { 1, 5, 6, 59, 61 }, // 10 IIC_fpu_negs
464 { 1, 5, 6, 61, 63 }, // 11 IIC_fpu_sqrtd
465 { 1, 5, 6, 63, 65 }, // 12 IIC_fpu_sqrts
466 { 1, 5, 6, 65, 67 }, // 13 IIC_fpu_stod
467 { 1, 6, 7, 67, 69 }, // 14 IIC_ldd
468 { 1, 6, 7, 69, 71 }, // 15 IIC_iu_or_fpu_instr
469 { 1, 4, 5, 71, 73 }, // 16 IIC_iu_div
470 { 1, 4, 5, 73, 75 }, // 17 IIC_smac_umac
471 { 1, 4, 5, 75, 77 }, // 18 IIC_iu_smul
472 { 1, 6, 7, 77, 79 }, // 19 IIC_st
473 { 1, 6, 7, 79, 81 }, // 20 IIC_std
474 { 1, 4, 5, 81, 83 }, // 21 IIC_iu_umul
475 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
476};
477
478static constexpr llvm::InstrItinerary LEON4Itineraries[] = {
479 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
480 { 1, 7, 8, 83, 85 }, // 1 IIC_iu_instr
481 { 1, 8, 9, 85, 87 }, // 2 IIC_fpu_normal_instr
482 { 1, 9, 10, 87, 89 }, // 3 IIC_jmp_or_call
483 { 1, 8, 9, 89, 91 }, // 4 IIC_fpu_abs
484 { 1, 8, 9, 91, 93 }, // 5 IIC_fpu_fast_instr
485 { 1, 8, 9, 93, 95 }, // 6 IIC_fpu_divd
486 { 1, 8, 9, 95, 97 }, // 7 IIC_fpu_divs
487 { 1, 8, 9, 97, 99 }, // 8 IIC_fpu_muld
488 { 1, 8, 9, 99, 101 }, // 9 IIC_fpu_muls
489 { 1, 8, 9, 101, 103 }, // 10 IIC_fpu_negs
490 { 1, 8, 9, 103, 105 }, // 11 IIC_fpu_sqrtd
491 { 1, 8, 9, 105, 107 }, // 12 IIC_fpu_sqrts
492 { 1, 8, 9, 107, 109 }, // 13 IIC_fpu_stod
493 { 1, 9, 10, 109, 111 }, // 14 IIC_ldd
494 { 1, 9, 10, 111, 113 }, // 15 IIC_iu_or_fpu_instr
495 { 1, 7, 8, 113, 115 }, // 16 IIC_iu_div
496 { 1, 7, 8, 115, 117 }, // 17 IIC_smac_umac
497 { 1, 7, 8, 117, 119 }, // 18 IIC_iu_smul
498 { 1, 9, 10, 119, 121 }, // 19 IIC_st
499 { 1, 9, 10, 121, 123 }, // 20 IIC_std
500 { 1, 7, 8, 123, 125 }, // 21 IIC_iu_umul
501 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
502};
503
504// ===============================================================
505// Data tables for the new per-operand machine model.
506
507static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
508static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
509
510// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
511extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[] = {
512 { 0, 0, 0 }, // Invalid
513}; // SparcWriteProcResTable
514
515// {Cycles, WriteResourceID}
516extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[] = {
517 { 0, 0}, // Invalid
518}; // SparcWriteLatencyTable
519
520// {UseIdx, WriteResourceID, Cycles}
521extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[] = {
522 {0, 0, 0}, // Invalid
523}; // SparcReadAdvanceTable
524
525#ifdef __GNUC__
526#pragma GCC diagnostic push
527#pragma GCC diagnostic ignored "-Woverlength-strings"
528#endif
529static constexpr char SparcSchedClassNamesStorage[] =
530 "\0"
531 "InvalidSchedClass\0"
532 ;
533#ifdef __GNUC__
534#pragma GCC diagnostic pop
535#endif
536
537static constexpr llvm::StringTable
538SparcSchedClassNames = SparcSchedClassNamesStorage;
539
540extern const llvm::MCSchedModel SparcSchedModels[] = {
541{ // NoSchedModel
542 MCSchedModel::DefaultIssueWidth,
543 MCSchedModel::DefaultMicroOpBufferSize,
544 MCSchedModel::DefaultLoopMicroOpBufferSize,
545 MCSchedModel::DefaultLoadLatency,
546 MCSchedModel::DefaultHighLatency,
547 MCSchedModel::DefaultMispredictPenalty,
548 false, // PostRAScheduler
549 false, // CompleteModel
550 false, // EnableIntervals
551 0, // Processor ID
552 nullptr, nullptr, 0, 0, // No instruction-level machine model.
553 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
554 nullptr, // No Itinerary
555 nullptr // No extra processor descriptor
556 },
557{ // LEON2ItinerariesModel
558 MCSchedModel::DefaultIssueWidth,
559 MCSchedModel::DefaultMicroOpBufferSize,
560 MCSchedModel::DefaultLoopMicroOpBufferSize,
561 MCSchedModel::DefaultLoadLatency,
562 MCSchedModel::DefaultHighLatency,
563 MCSchedModel::DefaultMispredictPenalty,
564 false, // PostRAScheduler
565 false, // CompleteModel
566 false, // EnableIntervals
567 1, // Processor ID
568 nullptr, nullptr, 0, 0, // No instruction-level machine model.
569 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
570 LEON2Itineraries,
571 nullptr // No extra processor descriptor
572 },
573{ // LEON3ItinerariesModel
574 MCSchedModel::DefaultIssueWidth,
575 MCSchedModel::DefaultMicroOpBufferSize,
576 MCSchedModel::DefaultLoopMicroOpBufferSize,
577 MCSchedModel::DefaultLoadLatency,
578 MCSchedModel::DefaultHighLatency,
579 MCSchedModel::DefaultMispredictPenalty,
580 false, // PostRAScheduler
581 false, // CompleteModel
582 false, // EnableIntervals
583 2, // Processor ID
584 nullptr, nullptr, 0, 0, // No instruction-level machine model.
585 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
586 LEON3Itineraries,
587 nullptr // No extra processor descriptor
588 },
589{ // LEON4ItinerariesModel
590 MCSchedModel::DefaultIssueWidth,
591 MCSchedModel::DefaultMicroOpBufferSize,
592 MCSchedModel::DefaultLoopMicroOpBufferSize,
593 MCSchedModel::DefaultLoadLatency,
594 MCSchedModel::DefaultHighLatency,
595 MCSchedModel::DefaultMispredictPenalty,
596 false, // PostRAScheduler
597 false, // CompleteModel
598 false, // EnableIntervals
599 3, // Processor ID
600 nullptr, nullptr, 0, 0, // No instruction-level machine model.
601 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
602 LEON4Itineraries,
603 nullptr // No extra processor descriptor
604 },
605};
606
607#undef DBGFIELD
608
609#undef DBGVAL_OR_NULLPTR
610
611// Sorted (by key) array of values for CPU subtype.
612extern const llvm::SubtargetSubTypeKVStorage< 40, 310> SparcSubTypeKVStorage = {
613 {
614 { sizeof(SubtargetSubTypeKV) * 40 + 1, { { { 0x10000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
615 { sizeof(SubtargetSubTypeKV) * 39 + 8, { { { 0x10000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
616 { sizeof(SubtargetSubTypeKV) * 38 + 15, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
617 { sizeof(SubtargetSubTypeKV) * 37 + 20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
618 { sizeof(SubtargetSubTypeKV) * 36 + 28, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 },
619 { sizeof(SubtargetSubTypeKV) * 35 + 36, { { { 0x260000000000110ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 3 },
620 { sizeof(SubtargetSubTypeKV) * 34 + 42, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
621 { sizeof(SubtargetSubTypeKV) * 33 + 53, { { { 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
622 { sizeof(SubtargetSubTypeKV) * 32 + 59, { { { 0x220000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 },
623 { sizeof(SubtargetSubTypeKV) * 31 + 65, { { { 0x220000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 3 },
624 { sizeof(SubtargetSubTypeKV) * 30 + 71, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
625 { sizeof(SubtargetSubTypeKV) * 29 + 78, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
626 { sizeof(SubtargetSubTypeKV) * 28 + 85, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
627 { sizeof(SubtargetSubTypeKV) * 27 + 92, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
628 { sizeof(SubtargetSubTypeKV) * 26 + 99, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
629 { sizeof(SubtargetSubTypeKV) * 25 + 106, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
630 { sizeof(SubtargetSubTypeKV) * 24 + 113, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
631 { sizeof(SubtargetSubTypeKV) * 23 + 120, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
632 { sizeof(SubtargetSubTypeKV) * 22 + 127, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
633 { sizeof(SubtargetSubTypeKV) * 21 + 134, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
634 { sizeof(SubtargetSubTypeKV) * 20 + 141, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
635 { sizeof(SubtargetSubTypeKV) * 19 + 148, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
636 { sizeof(SubtargetSubTypeKV) * 18 + 156, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
637 { sizeof(SubtargetSubTypeKV) * 17 + 166, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
638 { sizeof(SubtargetSubTypeKV) * 16 + 176, { { { 0x20000000000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
639 { sizeof(SubtargetSubTypeKV) * 15 + 186, { { { 0x1d4000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
640 { sizeof(SubtargetSubTypeKV) * 14 + 194, { { { 0x4001d4000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
641 { sizeof(SubtargetSubTypeKV) * 13 + 203, { { { 0x4003dc000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
642 { sizeof(SubtargetSubTypeKV) * 12 + 212, { { { 0x4003dc000000084ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
643 { sizeof(SubtargetSubTypeKV) * 11 + 221, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
644 { sizeof(SubtargetSubTypeKV) * 10 + 230, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
645 { sizeof(SubtargetSubTypeKV) * 9 + 240, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
646 { sizeof(SubtargetSubTypeKV) * 8 + 253, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
647 { sizeof(SubtargetSubTypeKV) * 7 + 264, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
648 { sizeof(SubtargetSubTypeKV) * 6 + 271, { { { 0xd0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
649 { sizeof(SubtargetSubTypeKV) * 5 + 282, { { { 0x1d0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
650 { sizeof(SubtargetSubTypeKV) * 4 + 294, { { { 0x10400000000070ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 },
651 { sizeof(SubtargetSubTypeKV) * 3 + 300, { { { 0x2000000040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
652 { sizeof(SubtargetSubTypeKV) * 2 + 303, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
653 { sizeof(SubtargetSubTypeKV) * 1 + 306, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
654 },
655 "\000at697e\000at697f\000f934\000generic\000gr712rc\000gr740\000hyperspa"
656 "rc\000leon2\000leon3\000leon4\000ma2080\000ma2085\000ma2100\000ma2150\000"
657 "ma2155\000ma2450\000ma2455\000ma2480\000ma2485\000ma2x5x\000ma2x8x\000m"
658 "yriad2\000myriad2.1\000myriad2.2\000myriad2.3\000niagara\000niagara2\000"
659 "niagara3\000niagara4\000sparclet\000sparclite\000sparclite86x\000supers"
660 "parc\000tsc701\000ultrasparc\000ultrasparc3\000ut699\000v7\000v8\000v9\000"};
661
662namespace Sparc_MC {
663
664unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
665 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
666 // Don't know how to resolve this scheduling class.
667 return 0;
668}
669
670} // namespace Sparc_MC
671struct SparcGenMCSubtargetInfo : public MCSubtargetInfo {
672 SparcGenMCSubtargetInfo(const Triple &TT,
673 StringRef CPU, StringRef TuneCPU, StringRef FS,
674 StringTable PN,
675 ArrayRef<SubtargetFeatureKV> PF,
676 ArrayRef<SubtargetSubTypeKV> PD,
677 const MCSchedModel *PSM,
678 const MCWriteProcResEntry *WPR,
679 const MCWriteLatencyEntry *WL,
680 const MCReadAdvanceEntry *RA, const InstrStage *IS,
681 const unsigned *OC, const unsigned *FP) :
682 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
683 WPR, WL, RA, IS, OC, FP) { }
684
685 unsigned resolveVariantSchedClass(unsigned SchedClass,
686 const MCInst *MI, const MCInstrInfo *MCII,
687 unsigned CPUID) const final {
688 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
689 }
690 unsigned getHwModeSet() const final;
691 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
692};
693unsigned SparcGenMCSubtargetInfo::getHwModeSet() const {
694 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
695 // Collect HwModes and store them as a bit set.
696 unsigned Modes = 0;
697 if (FB[Sparc::Feature64Bit]) Modes |= (1 << 0);
698 return Modes;
699}
700unsigned SparcGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
701 unsigned Modes = getHwModeSet();
702
703 if (!Modes)
704 return Modes;
705
706 switch (type) {
707 case HwMode_Default:
708 return llvm::countr_zero(Modes) + 1;
709 case HwMode_ValueType:
710 // No HwMode for ValueType.
711 return 0;
712 case HwMode_RegInfo:
713 Modes &= 1;
714 if (!Modes)
715 return Modes;
716 if (!llvm::has_single_bit<unsigned>(Modes))
717 llvm_unreachable("Two or more HwModes for RegInfo were found!");
718 return llvm::countr_zero(Modes) + 1;
719 case HwMode_EncodingInfo:
720 // No HwMode for EncodingInfo.
721 return 0;
722 }
723 llvm_unreachable("unexpected HwModeType");
724 return 0; // should not get here
725}
726
727static inline MCSubtargetInfo *createSparcMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
728 return new SparcGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(SparcSubTypeKVStorage.Strings), SparcFeatureKVStorage.Features, SparcSubTypeKVStorage.SubTypes, SparcSchedModels,
729 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
730 SparcStages, SparcOperandCycles, SparcForwardingPaths);
731}
732
733
734} // namespace llvm
735
736#endif // GET_SUBTARGETINFO_MC_DESC
737
738#ifdef GET_SUBTARGETINFO_TARGET_DESC
739#undef GET_SUBTARGETINFO_TARGET_DESC
740
741#include "llvm/ADT/BitmaskEnum.h"
742#include "llvm/Support/Debug.h"
743#include "llvm/Support/raw_ostream.h"
744
745// ParseSubtargetFeatures - Parses features string setting specified
746// subtarget options.
747void llvm::SparcSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
748 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
749 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
750 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
751 InitMCProcessorInfo(CPU, TuneCPU, FS);
752 const FeatureBitset &Bits = getFeatureBits();
753 if (Bits[Sparc::DetectRoundChange]) DetectRoundChange = true;
754 if (Bits[Sparc::Feature64Bit]) Is64Bit = true;
755 if (Bits[Sparc::FeatureCrypto]) IsCrypto = true;
756 if (Bits[Sparc::FeatureHardQuad]) HasHardQuad = true;
757 if (Bits[Sparc::FeatureLeon]) IsLeon = true;
758 if (Bits[Sparc::FeatureNoFMULS]) HasNoFMULS = true;
759 if (Bits[Sparc::FeatureNoFSMULD]) HasNoFSMULD = true;
760 if (Bits[Sparc::FeatureOSA2011]) IsOSA2011 = true;
761 if (Bits[Sparc::FeaturePWRPSR]) HasPWRPSR = true;
762 if (Bits[Sparc::FeatureReserveG1]) ReserveRegister[1 + SP::G0] = true;
763 if (Bits[Sparc::FeatureReserveG2]) ReserveRegister[2 + SP::G0] = true;
764 if (Bits[Sparc::FeatureReserveG3]) ReserveRegister[3 + SP::G0] = true;
765 if (Bits[Sparc::FeatureReserveG4]) ReserveRegister[4 + SP::G0] = true;
766 if (Bits[Sparc::FeatureReserveG5]) ReserveRegister[5 + SP::G0] = true;
767 if (Bits[Sparc::FeatureReserveG6]) ReserveRegister[6 + SP::G0] = true;
768 if (Bits[Sparc::FeatureReserveG7]) ReserveRegister[7 + SP::G0] = true;
769 if (Bits[Sparc::FeatureReserveI0]) ReserveRegister[0 + SP::I0] = true;
770 if (Bits[Sparc::FeatureReserveI1]) ReserveRegister[1 + SP::I0] = true;
771 if (Bits[Sparc::FeatureReserveI2]) ReserveRegister[2 + SP::I0] = true;
772 if (Bits[Sparc::FeatureReserveI3]) ReserveRegister[3 + SP::I0] = true;
773 if (Bits[Sparc::FeatureReserveI4]) ReserveRegister[4 + SP::I0] = true;
774 if (Bits[Sparc::FeatureReserveI5]) ReserveRegister[5 + SP::I0] = true;
775 if (Bits[Sparc::FeatureReserveL0]) ReserveRegister[0 + SP::L0] = true;
776 if (Bits[Sparc::FeatureReserveL1]) ReserveRegister[1 + SP::L0] = true;
777 if (Bits[Sparc::FeatureReserveL2]) ReserveRegister[2 + SP::L0] = true;
778 if (Bits[Sparc::FeatureReserveL3]) ReserveRegister[3 + SP::L0] = true;
779 if (Bits[Sparc::FeatureReserveL4]) ReserveRegister[4 + SP::L0] = true;
780 if (Bits[Sparc::FeatureReserveL5]) ReserveRegister[5 + SP::L0] = true;
781 if (Bits[Sparc::FeatureReserveL6]) ReserveRegister[6 + SP::L0] = true;
782 if (Bits[Sparc::FeatureReserveL7]) ReserveRegister[7 + SP::L0] = true;
783 if (Bits[Sparc::FeatureReserveO0]) ReserveRegister[0 + SP::O0] = true;
784 if (Bits[Sparc::FeatureReserveO1]) ReserveRegister[1 + SP::O0] = true;
785 if (Bits[Sparc::FeatureReserveO2]) ReserveRegister[2 + SP::O0] = true;
786 if (Bits[Sparc::FeatureReserveO3]) ReserveRegister[3 + SP::O0] = true;
787 if (Bits[Sparc::FeatureReserveO4]) ReserveRegister[4 + SP::O0] = true;
788 if (Bits[Sparc::FeatureReserveO5]) ReserveRegister[5 + SP::O0] = true;
789 if (Bits[Sparc::FeatureSoftFloat]) UseSoftFloat = true;
790 if (Bits[Sparc::FeatureSoftMulDiv]) UseSoftMulDiv = true;
791 if (Bits[Sparc::FeatureUA2005]) IsUA2005 = true;
792 if (Bits[Sparc::FeatureUA2007]) IsUA2007 = true;
793 if (Bits[Sparc::FeatureV8Deprecated]) UseV8DeprecatedInsts = true;
794 if (Bits[Sparc::FeatureV8Plus]) IsV8Plus = true;
795 if (Bits[Sparc::FeatureV9]) IsV9 = true;
796 if (Bits[Sparc::FeatureVIS]) IsVIS = true;
797 if (Bits[Sparc::FeatureVIS2]) IsVIS2 = true;
798 if (Bits[Sparc::FeatureVIS3]) IsVIS3 = true;
799 if (Bits[Sparc::FixAllFDIVSQRT]) FixAllFDIVSQRT = true;
800 if (Bits[Sparc::FixTN0009]) FixTN0009 = true;
801 if (Bits[Sparc::FixTN0010]) FixTN0010 = true;
802 if (Bits[Sparc::FixTN0011]) FixTN0011 = true;
803 if (Bits[Sparc::FixTN0012]) FixTN0012 = true;
804 if (Bits[Sparc::FixTN0013]) FixTN0013 = true;
805 if (Bits[Sparc::InsertNOPLoad]) InsertNOPLoad = true;
806 if (Bits[Sparc::LeonCASA]) HasLeonCasa = true;
807 if (Bits[Sparc::LeonCycleCounter]) HasLeonCycleCounter = true;
808 if (Bits[Sparc::TuneNoPredictor]) HasNoPredictor = true;
809 if (Bits[Sparc::TuneSlowRDPC]) HasSlowRDPC = true;
810 if (Bits[Sparc::UMACSMACSupport]) HasUmacSmac = true;
811 if (Bits[Sparc::UsePopc]) UsePopc = true;
812}
813
814#endif // GET_SUBTARGETINFO_TARGET_DESC
815
816#ifdef GET_SUBTARGETINFO_HEADER
817#undef GET_SUBTARGETINFO_HEADER
818
819namespace llvm {
820
821class DFAPacketizer;
822namespace Sparc_MC {
823
824unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
825
826} // namespace Sparc_MC
827struct SparcGenSubtargetInfo : public TargetSubtargetInfo {
828 explicit SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
829public:
830 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
831 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
832 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
833 enum class SparcHwModeBits : unsigned {
834 DefaultMode = 0,
835 SPARC64 = (1 << 0),
836
837 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/SPARC64),
838 };
839 unsigned getHwModeSet() const final;
840 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
841 const FeatureBitset &getInlineIgnoreFeatures() const override;
842 const FeatureBitset &getInlineInverseFeatures() const override;
843 const FeatureBitset &getInlineMustMatchFeatures() const override;
844};
845
846} // namespace llvm
847
848#endif // GET_SUBTARGETINFO_HEADER
849
850#ifdef GET_SUBTARGETINFO_CTOR
851#undef GET_SUBTARGETINFO_CTOR
852
853#include "llvm/CodeGen/TargetSchedule.h"
854
855namespace llvm {
856
857extern const llvm::StringRef SparcNames[];
858extern const llvm::SubtargetFeatureKVStorage<59, 3417> SparcFeatureKVStorage;
859extern const llvm::SubtargetSubTypeKVStorage<40, 310> SparcSubTypeKVStorage;
860extern const llvm::MCSchedModel SparcSchedModels[];
861extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[];
862extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[];
863extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[];
864extern const llvm::InstrStage SparcStages[];
865extern const unsigned SparcOperandCycles[];
866extern const unsigned SparcForwardingPaths[];
867SparcGenSubtargetInfo::SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
868 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(SparcSubTypeKVStorage.Strings), ArrayRef(SparcFeatureKVStorage.Features), ArrayRef(SparcSubTypeKVStorage.SubTypes), SparcSchedModels,
869 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
870 SparcStages, SparcOperandCycles, SparcForwardingPaths) {}
871
872unsigned SparcGenSubtargetInfo
873::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
874 report_fatal_error("Expected a variant SchedClass");
875} // SparcGenSubtargetInfo::resolveSchedClass
876
877unsigned SparcGenSubtargetInfo
878::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
879 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
880} // SparcGenSubtargetInfo::resolveVariantSchedClass
881
882unsigned SparcGenSubtargetInfo::getHwModeSet() const {
883 [[maybe_unused]] const auto *Subtarget =
884 static_cast<const SparcSubtarget *>(this);
885 // Collect HwModes and store them as a bit set.
886 unsigned Modes = 0;
887 if ((Subtarget->is64Bit())) Modes |= (1 << 0);
888 return Modes;
889}
890unsigned SparcGenSubtargetInfo::getHwMode(enum HwModeType type) const {
891 unsigned Modes = getHwModeSet();
892
893 if (!Modes)
894 return Modes;
895
896 switch (type) {
897 case HwMode_Default:
898 return llvm::countr_zero(Modes) + 1;
899 case HwMode_ValueType:
900 // No HwMode for ValueType.
901 return 0;
902 case HwMode_RegInfo:
903 Modes &= 1;
904 if (!Modes)
905 return Modes;
906 if (!llvm::has_single_bit<unsigned>(Modes))
907 llvm_unreachable("Two or more HwModes for RegInfo were found!");
908 return llvm::countr_zero(Modes) + 1;
909 case HwMode_EncodingInfo:
910 // No HwMode for EncodingInfo.
911 return 0;
912 }
913 llvm_unreachable("unexpected HwModeType");
914 return 0; // should not get here
915}
916const FeatureBitset &SparcGenSubtargetInfo::getInlineIgnoreFeatures() const {
917 static constexpr FeatureBitset Features = {
918 };
919 return Features;
920}
921
922const FeatureBitset &SparcGenSubtargetInfo::getInlineInverseFeatures() const {
923 static constexpr FeatureBitset Features = {
924 };
925 return Features;
926}
927
928const FeatureBitset &SparcGenSubtargetInfo::getInlineMustMatchFeatures() const {
929 static constexpr FeatureBitset Features = {
930 };
931 return Features;
932}
933
934
935} // namespace llvm
936
937#endif // GET_SUBTARGETINFO_CTOR
938
939#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
940#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
941
942
943#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
944
945#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
946#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
947
948
949#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
950
951