| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Machine Code Emitter *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | uint64_t SystemZMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| 10 | SmallVectorImpl<MCFixup> &Fixups, |
| 11 | const MCSubtargetInfo &STI) const { |
| 12 | static const uint64_t InstBits[] = { |
| 13 | UINT64_C(1509949440), // A |
| 14 | UINT64_C(1778384896), // AD |
| 15 | UINT64_C(260584255782938), // ADB |
| 16 | UINT64_C(3004825600), // ADBR |
| 17 | UINT64_C(10752), // ADR |
| 18 | UINT64_C(3016884224), // ADTR |
| 19 | UINT64_C(3016884224), // ADTRA |
| 20 | UINT64_C(2046820352), // AE |
| 21 | UINT64_C(260584255782922), // AEB |
| 22 | UINT64_C(3003777024), // AEBR |
| 23 | UINT64_C(14848), // AER |
| 24 | UINT64_C(213343910494208), // AFI |
| 25 | UINT64_C(249589139505160), // AG |
| 26 | UINT64_C(249589139505176), // AGF |
| 27 | UINT64_C(213339615526912), // AGFI |
| 28 | UINT64_C(3105357824), // AGFR |
| 29 | UINT64_C(249589139505208), // AGH |
| 30 | UINT64_C(2802515968), // AGHI |
| 31 | UINT64_C(259484744155353), // AGHIK |
| 32 | UINT64_C(3104309248), // AGR |
| 33 | UINT64_C(3118989312), // AGRK |
| 34 | UINT64_C(258385232527482), // AGSI |
| 35 | UINT64_C(1241513984), // AH |
| 36 | UINT64_C(3116892160), // AHHHR |
| 37 | UINT64_C(3117940736), // AHHLR |
| 38 | UINT64_C(2802450432), // AHI |
| 39 | UINT64_C(259484744155352), // AHIK |
| 40 | UINT64_C(249589139505274), // AHY |
| 41 | UINT64_C(224334731804672), // AIH |
| 42 | UINT64_C(1577058304), // AL |
| 43 | UINT64_C(249589139505304), // ALC |
| 44 | UINT64_C(249589139505288), // ALCG |
| 45 | UINT64_C(3112697856), // ALCGR |
| 46 | UINT64_C(3113746432), // ALCR |
| 47 | UINT64_C(213352500428800), // ALFI |
| 48 | UINT64_C(249589139505162), // ALG |
| 49 | UINT64_C(249589139505178), // ALGF |
| 50 | UINT64_C(213348205461504), // ALGFI |
| 51 | UINT64_C(3105488896), // ALGFR |
| 52 | UINT64_C(259484744155355), // ALGHSIK |
| 53 | UINT64_C(3104440320), // ALGR |
| 54 | UINT64_C(3119120384), // ALGRK |
| 55 | UINT64_C(258385232527486), // ALGSI |
| 56 | UINT64_C(3117023232), // ALHHHR |
| 57 | UINT64_C(3118071808), // ALHHLR |
| 58 | UINT64_C(259484744155354), // ALHSIK |
| 59 | UINT64_C(7680), // ALR |
| 60 | UINT64_C(3120168960), // ALRK |
| 61 | UINT64_C(258385232527470), // ALSI |
| 62 | UINT64_C(224343321739264), // ALSIH |
| 63 | UINT64_C(224347616706560), // ALSIHN |
| 64 | UINT64_C(249589139505246), // ALY |
| 65 | UINT64_C(274877906944000), // AP |
| 66 | UINT64_C(6656), // AR |
| 67 | UINT64_C(3120037888), // ARK |
| 68 | UINT64_C(258385232527466), // ASI |
| 69 | UINT64_C(2113929216), // AU |
| 70 | UINT64_C(15872), // AUR |
| 71 | UINT64_C(1845493760), // AW |
| 72 | UINT64_C(11776), // AWR |
| 73 | UINT64_C(3007971328), // AXBR |
| 74 | UINT64_C(13824), // AXR |
| 75 | UINT64_C(3017408512), // AXTR |
| 76 | UINT64_C(3017408512), // AXTRA |
| 77 | UINT64_C(249589139505242), // AY |
| 78 | UINT64_C(1206910976), // B |
| 79 | UINT64_C(2990538752), // BAKR |
| 80 | UINT64_C(1157627904), // BAL |
| 81 | UINT64_C(1280), // BALR |
| 82 | UINT64_C(1291845632), // BAS |
| 83 | UINT64_C(3328), // BASR |
| 84 | UINT64_C(3072), // BASSM |
| 85 | UINT64_C(1199570944), // BAsmE |
| 86 | UINT64_C(1193279488), // BAsmH |
| 87 | UINT64_C(1201668096), // BAsmHE |
| 88 | UINT64_C(1195376640), // BAsmL |
| 89 | UINT64_C(1203765248), // BAsmLE |
| 90 | UINT64_C(1197473792), // BAsmLH |
| 91 | UINT64_C(1195376640), // BAsmM |
| 92 | UINT64_C(1198522368), // BAsmNE |
| 93 | UINT64_C(1204813824), // BAsmNH |
| 94 | UINT64_C(1196425216), // BAsmNHE |
| 95 | UINT64_C(1202716672), // BAsmNL |
| 96 | UINT64_C(1194328064), // BAsmNLE |
| 97 | UINT64_C(1200619520), // BAsmNLH |
| 98 | UINT64_C(1202716672), // BAsmNM |
| 99 | UINT64_C(1205862400), // BAsmNO |
| 100 | UINT64_C(1204813824), // BAsmNP |
| 101 | UINT64_C(1198522368), // BAsmNZ |
| 102 | UINT64_C(1192230912), // BAsmO |
| 103 | UINT64_C(1193279488), // BAsmP |
| 104 | UINT64_C(1199570944), // BAsmZ |
| 105 | UINT64_C(1191182336), // BC |
| 106 | UINT64_C(1191182336), // BCAsm |
| 107 | UINT64_C(1792), // BCR |
| 108 | UINT64_C(1792), // BCRAsm |
| 109 | UINT64_C(1174405120), // BCT |
| 110 | UINT64_C(249589139505222), // BCTG |
| 111 | UINT64_C(3108372480), // BCTGR |
| 112 | UINT64_C(1536), // BCTR |
| 113 | UINT64_C(3110928384), // BDEPG |
| 114 | UINT64_C(3110862848), // BEXTG |
| 115 | UINT64_C(250619931656263), // BI |
| 116 | UINT64_C(250138895319111), // BIAsmE |
| 117 | UINT64_C(249726578458695), // BIAsmH |
| 118 | UINT64_C(250276334272583), // BIAsmHE |
| 119 | UINT64_C(249864017412167), // BIAsmL |
| 120 | UINT64_C(250413773226055), // BIAsmLE |
| 121 | UINT64_C(250001456365639), // BIAsmLH |
| 122 | UINT64_C(249864017412167), // BIAsmM |
| 123 | UINT64_C(250070175842375), // BIAsmNE |
| 124 | UINT64_C(250482492702791), // BIAsmNH |
| 125 | UINT64_C(249932736888903), // BIAsmNHE |
| 126 | UINT64_C(250345053749319), // BIAsmNL |
| 127 | UINT64_C(249795297935431), // BIAsmNLE |
| 128 | UINT64_C(250207614795847), // BIAsmNLH |
| 129 | UINT64_C(250345053749319), // BIAsmNM |
| 130 | UINT64_C(250551212179527), // BIAsmNO |
| 131 | UINT64_C(250482492702791), // BIAsmNP |
| 132 | UINT64_C(250070175842375), // BIAsmNZ |
| 133 | UINT64_C(249657858981959), // BIAsmO |
| 134 | UINT64_C(249726578458695), // BIAsmP |
| 135 | UINT64_C(250138895319111), // BIAsmZ |
| 136 | UINT64_C(249589139505223), // BIC |
| 137 | UINT64_C(249589139505223), // BICAsm |
| 138 | UINT64_C(218802813927424), // BPP |
| 139 | UINT64_C(216603790671872), // BPRP |
| 140 | UINT64_C(2032), // BR |
| 141 | UINT64_C(2802122752), // BRAS |
| 142 | UINT64_C(211127707369472), // BRASL |
| 143 | UINT64_C(1920), // BRAsmE |
| 144 | UINT64_C(1824), // BRAsmH |
| 145 | UINT64_C(1952), // BRAsmHE |
| 146 | UINT64_C(1856), // BRAsmL |
| 147 | UINT64_C(1984), // BRAsmLE |
| 148 | UINT64_C(1888), // BRAsmLH |
| 149 | UINT64_C(1856), // BRAsmM |
| 150 | UINT64_C(1904), // BRAsmNE |
| 151 | UINT64_C(2000), // BRAsmNH |
| 152 | UINT64_C(1872), // BRAsmNHE |
| 153 | UINT64_C(1968), // BRAsmNL |
| 154 | UINT64_C(1840), // BRAsmNLE |
| 155 | UINT64_C(1936), // BRAsmNLH |
| 156 | UINT64_C(1968), // BRAsmNM |
| 157 | UINT64_C(2016), // BRAsmNO |
| 158 | UINT64_C(2000), // BRAsmNP |
| 159 | UINT64_C(1904), // BRAsmNZ |
| 160 | UINT64_C(1808), // BRAsmO |
| 161 | UINT64_C(1824), // BRAsmP |
| 162 | UINT64_C(1920), // BRAsmZ |
| 163 | UINT64_C(2802057216), // BRC |
| 164 | UINT64_C(2802057216), // BRCAsm |
| 165 | UINT64_C(211123412402176), // BRCL |
| 166 | UINT64_C(211123412402176), // BRCLAsm |
| 167 | UINT64_C(2802188288), // BRCT |
| 168 | UINT64_C(2802253824), // BRCTG |
| 169 | UINT64_C(224326141870080), // BRCTH |
| 170 | UINT64_C(2214592512), // BRXH |
| 171 | UINT64_C(259484744155204), // BRXHG |
| 172 | UINT64_C(2231369728), // BRXLE |
| 173 | UINT64_C(259484744155205), // BRXLG |
| 174 | UINT64_C(2992242688), // BSA |
| 175 | UINT64_C(2992111616), // BSG |
| 176 | UINT64_C(2816), // BSM |
| 177 | UINT64_C(2248146944), // BXH |
| 178 | UINT64_C(258385232527428), // BXHG |
| 179 | UINT64_C(2264924160), // BXLE |
| 180 | UINT64_C(258385232527429), // BXLEG |
| 181 | UINT64_C(1493172224), // C |
| 182 | UINT64_C(219928095358976), // CAL |
| 183 | UINT64_C(219932390326272), // CALG |
| 184 | UINT64_C(219966750064640), // CALGF |
| 185 | UINT64_C(1761607680), // CD |
| 186 | UINT64_C(260584255782937), // CDB |
| 187 | UINT64_C(3004760064), // CDBR |
| 188 | UINT64_C(3012886528), // CDFBR |
| 189 | UINT64_C(3012886528), // CDFBRA |
| 190 | UINT64_C(3014983680), // CDFR |
| 191 | UINT64_C(3109093376), // CDFTR |
| 192 | UINT64_C(3013935104), // CDGBR |
| 193 | UINT64_C(3013935104), // CDGBRA |
| 194 | UINT64_C(3016032256), // CDGR |
| 195 | UINT64_C(3018915840), // CDGTR |
| 196 | UINT64_C(3018915840), // CDGTRA |
| 197 | UINT64_C(3012624384), // CDLFBR |
| 198 | UINT64_C(3109224448), // CDLFTR |
| 199 | UINT64_C(3013672960), // CDLGBR |
| 200 | UINT64_C(3109158912), // CDLGTR |
| 201 | UINT64_C(260584255783086), // CDPT |
| 202 | UINT64_C(10496), // CDR |
| 203 | UINT64_C(3137339392), // CDS |
| 204 | UINT64_C(258385232527422), // CDSG |
| 205 | UINT64_C(3019046912), // CDSTR |
| 206 | UINT64_C(258385232527409), // CDSY |
| 207 | UINT64_C(3018063872), // CDTR |
| 208 | UINT64_C(3018981376), // CDUTR |
| 209 | UINT64_C(260584255783082), // CDZT |
| 210 | UINT64_C(2030043136), // CE |
| 211 | UINT64_C(260584255782921), // CEB |
| 212 | UINT64_C(3003711488), // CEBR |
| 213 | UINT64_C(3019112448), // CEDTR |
| 214 | UINT64_C(3012820992), // CEFBR |
| 215 | UINT64_C(3012820992), // CEFBRA |
| 216 | UINT64_C(3014918144), // CEFR |
| 217 | UINT64_C(3013869568), // CEGBR |
| 218 | UINT64_C(3013869568), // CEGBRA |
| 219 | UINT64_C(3015966720), // CEGR |
| 220 | UINT64_C(3012558848), // CELFBR |
| 221 | UINT64_C(3013607424), // CELGBR |
| 222 | UINT64_C(14592), // CER |
| 223 | UINT64_C(3019636736), // CEXTR |
| 224 | UINT64_C(2988048384), // CFC |
| 225 | UINT64_C(3013148672), // CFDBR |
| 226 | UINT64_C(3013148672), // CFDBRA |
| 227 | UINT64_C(3015245824), // CFDR |
| 228 | UINT64_C(3108044800), // CFDTR |
| 229 | UINT64_C(3013083136), // CFEBR |
| 230 | UINT64_C(3013083136), // CFEBRA |
| 231 | UINT64_C(3015180288), // CFER |
| 232 | UINT64_C(213361090363392), // CFI |
| 233 | UINT64_C(3013214208), // CFXBR |
| 234 | UINT64_C(3013214208), // CFXBRA |
| 235 | UINT64_C(3015311360), // CFXR |
| 236 | UINT64_C(3108569088), // CFXTR |
| 237 | UINT64_C(249589139505184), // CG |
| 238 | UINT64_C(3014197248), // CGDBR |
| 239 | UINT64_C(3014197248), // CGDBRA |
| 240 | UINT64_C(3016294400), // CGDR |
| 241 | UINT64_C(3017867264), // CGDTR |
| 242 | UINT64_C(3017867264), // CGDTRA |
| 243 | UINT64_C(3014131712), // CGEBR |
| 244 | UINT64_C(3014131712), // CGEBRA |
| 245 | UINT64_C(3016228864), // CGER |
| 246 | UINT64_C(249589139505200), // CGF |
| 247 | UINT64_C(213356795396096), // CGFI |
| 248 | UINT64_C(3106930688), // CGFR |
| 249 | UINT64_C(217754841907200), // CGFRL |
| 250 | UINT64_C(249589139505204), // CGH |
| 251 | UINT64_C(2802778112), // CGHI |
| 252 | UINT64_C(217720482168832), // CGHRL |
| 253 | UINT64_C(252166119882752), // CGHSI |
| 254 | UINT64_C(259484744155388), // CGIB |
| 255 | UINT64_C(259484744155388), // CGIBAsm |
| 256 | UINT64_C(259519103893756), // CGIBAsmE |
| 257 | UINT64_C(259493334089980), // CGIBAsmH |
| 258 | UINT64_C(259527693828348), // CGIBAsmHE |
| 259 | UINT64_C(259501924024572), // CGIBAsmL |
| 260 | UINT64_C(259536283762940), // CGIBAsmLE |
| 261 | UINT64_C(259510513959164), // CGIBAsmLH |
| 262 | UINT64_C(259510513959164), // CGIBAsmNE |
| 263 | UINT64_C(259536283762940), // CGIBAsmNH |
| 264 | UINT64_C(259501924024572), // CGIBAsmNHE |
| 265 | UINT64_C(259527693828348), // CGIBAsmNL |
| 266 | UINT64_C(259493334089980), // CGIBAsmNLE |
| 267 | UINT64_C(259519103893756), // CGIBAsmNLH |
| 268 | UINT64_C(259484744155260), // CGIJ |
| 269 | UINT64_C(259484744155260), // CGIJAsm |
| 270 | UINT64_C(259519103893628), // CGIJAsmE |
| 271 | UINT64_C(259493334089852), // CGIJAsmH |
| 272 | UINT64_C(259527693828220), // CGIJAsmHE |
| 273 | UINT64_C(259501924024444), // CGIJAsmL |
| 274 | UINT64_C(259536283762812), // CGIJAsmLE |
| 275 | UINT64_C(259510513959036), // CGIJAsmLH |
| 276 | UINT64_C(259510513959036), // CGIJAsmNE |
| 277 | UINT64_C(259536283762812), // CGIJAsmNH |
| 278 | UINT64_C(259501924024444), // CGIJAsmNHE |
| 279 | UINT64_C(259527693828220), // CGIJAsmNL |
| 280 | UINT64_C(259493334089852), // CGIJAsmNLE |
| 281 | UINT64_C(259519103893628), // CGIJAsmNLH |
| 282 | UINT64_C(259484744155248), // CGIT |
| 283 | UINT64_C(259484744155248), // CGITAsm |
| 284 | UINT64_C(259484744188016), // CGITAsmE |
| 285 | UINT64_C(259484744163440), // CGITAsmH |
| 286 | UINT64_C(259484744196208), // CGITAsmHE |
| 287 | UINT64_C(259484744171632), // CGITAsmL |
| 288 | UINT64_C(259484744204400), // CGITAsmLE |
| 289 | UINT64_C(259484744179824), // CGITAsmLH |
| 290 | UINT64_C(259484744179824), // CGITAsmNE |
| 291 | UINT64_C(259484744204400), // CGITAsmNH |
| 292 | UINT64_C(259484744171632), // CGITAsmNHE |
| 293 | UINT64_C(259484744196208), // CGITAsmNL |
| 294 | UINT64_C(259484744163440), // CGITAsmNLE |
| 295 | UINT64_C(259484744188016), // CGITAsmNLH |
| 296 | UINT64_C(3105882112), // CGR |
| 297 | UINT64_C(259484744155364), // CGRB |
| 298 | UINT64_C(259484744155364), // CGRBAsm |
| 299 | UINT64_C(259484744188132), // CGRBAsmE |
| 300 | UINT64_C(259484744163556), // CGRBAsmH |
| 301 | UINT64_C(259484744196324), // CGRBAsmHE |
| 302 | UINT64_C(259484744171748), // CGRBAsmL |
| 303 | UINT64_C(259484744204516), // CGRBAsmLE |
| 304 | UINT64_C(259484744179940), // CGRBAsmLH |
| 305 | UINT64_C(259484744179940), // CGRBAsmNE |
| 306 | UINT64_C(259484744204516), // CGRBAsmNH |
| 307 | UINT64_C(259484744171748), // CGRBAsmNHE |
| 308 | UINT64_C(259484744196324), // CGRBAsmNL |
| 309 | UINT64_C(259484744163556), // CGRBAsmNLE |
| 310 | UINT64_C(259484744188132), // CGRBAsmNLH |
| 311 | UINT64_C(259484744155236), // CGRJ |
| 312 | UINT64_C(259484744155236), // CGRJAsm |
| 313 | UINT64_C(259484744188004), // CGRJAsmE |
| 314 | UINT64_C(259484744163428), // CGRJAsmH |
| 315 | UINT64_C(259484744196196), // CGRJAsmHE |
| 316 | UINT64_C(259484744171620), // CGRJAsmL |
| 317 | UINT64_C(259484744204388), // CGRJAsmLE |
| 318 | UINT64_C(259484744179812), // CGRJAsmLH |
| 319 | UINT64_C(259484744179812), // CGRJAsmNE |
| 320 | UINT64_C(259484744204388), // CGRJAsmNH |
| 321 | UINT64_C(259484744171620), // CGRJAsmNHE |
| 322 | UINT64_C(259484744196196), // CGRJAsmNL |
| 323 | UINT64_C(259484744163428), // CGRJAsmNLE |
| 324 | UINT64_C(259484744188004), // CGRJAsmNLH |
| 325 | UINT64_C(217737662038016), // CGRL |
| 326 | UINT64_C(3110076416), // CGRT |
| 327 | UINT64_C(3110076416), // CGRTAsm |
| 328 | UINT64_C(3110109184), // CGRTAsmE |
| 329 | UINT64_C(3110084608), // CGRTAsmH |
| 330 | UINT64_C(3110117376), // CGRTAsmHE |
| 331 | UINT64_C(3110092800), // CGRTAsmL |
| 332 | UINT64_C(3110125568), // CGRTAsmLE |
| 333 | UINT64_C(3110100992), // CGRTAsmLH |
| 334 | UINT64_C(3110100992), // CGRTAsmNE |
| 335 | UINT64_C(3110125568), // CGRTAsmNH |
| 336 | UINT64_C(3110092800), // CGRTAsmNHE |
| 337 | UINT64_C(3110117376), // CGRTAsmNL |
| 338 | UINT64_C(3110084608), // CGRTAsmNLE |
| 339 | UINT64_C(3110109184), // CGRTAsmNLH |
| 340 | UINT64_C(3014262784), // CGXBR |
| 341 | UINT64_C(3014262784), // CGXBRA |
| 342 | UINT64_C(3016359936), // CGXR |
| 343 | UINT64_C(3018391552), // CGXTR |
| 344 | UINT64_C(3018391552), // CGXTRA |
| 345 | UINT64_C(1224736768), // CH |
| 346 | UINT64_C(249589139505357), // CHF |
| 347 | UINT64_C(3117219840), // CHHR |
| 348 | UINT64_C(252148940013568), // CHHSI |
| 349 | UINT64_C(2802712576), // CHI |
| 350 | UINT64_C(3118268416), // CHLR |
| 351 | UINT64_C(217724777136128), // CHRL |
| 352 | UINT64_C(252183299751936), // CHSI |
| 353 | UINT64_C(249589139505273), // CHY |
| 354 | UINT64_C(259484744155390), // CIB |
| 355 | UINT64_C(259484744155390), // CIBAsm |
| 356 | UINT64_C(259519103893758), // CIBAsmE |
| 357 | UINT64_C(259493334089982), // CIBAsmH |
| 358 | UINT64_C(259527693828350), // CIBAsmHE |
| 359 | UINT64_C(259501924024574), // CIBAsmL |
| 360 | UINT64_C(259536283762942), // CIBAsmLE |
| 361 | UINT64_C(259510513959166), // CIBAsmLH |
| 362 | UINT64_C(259510513959166), // CIBAsmNE |
| 363 | UINT64_C(259536283762942), // CIBAsmNH |
| 364 | UINT64_C(259501924024574), // CIBAsmNHE |
| 365 | UINT64_C(259527693828350), // CIBAsmNL |
| 366 | UINT64_C(259493334089982), // CIBAsmNLE |
| 367 | UINT64_C(259519103893758), // CIBAsmNLH |
| 368 | UINT64_C(224356206641152), // CIH |
| 369 | UINT64_C(259484744155262), // CIJ |
| 370 | UINT64_C(259484744155262), // CIJAsm |
| 371 | UINT64_C(259519103893630), // CIJAsmE |
| 372 | UINT64_C(259493334089854), // CIJAsmH |
| 373 | UINT64_C(259527693828222), // CIJAsmHE |
| 374 | UINT64_C(259501924024446), // CIJAsmL |
| 375 | UINT64_C(259536283762814), // CIJAsmLE |
| 376 | UINT64_C(259510513959038), // CIJAsmLH |
| 377 | UINT64_C(259510513959038), // CIJAsmNE |
| 378 | UINT64_C(259536283762814), // CIJAsmNH |
| 379 | UINT64_C(259501924024446), // CIJAsmNHE |
| 380 | UINT64_C(259527693828222), // CIJAsmNL |
| 381 | UINT64_C(259493334089854), // CIJAsmNLE |
| 382 | UINT64_C(259519103893630), // CIJAsmNLH |
| 383 | UINT64_C(259484744155250), // CIT |
| 384 | UINT64_C(259484744155250), // CITAsm |
| 385 | UINT64_C(259484744188018), // CITAsmE |
| 386 | UINT64_C(259484744163442), // CITAsmH |
| 387 | UINT64_C(259484744196210), // CITAsmHE |
| 388 | UINT64_C(259484744171634), // CITAsmL |
| 389 | UINT64_C(259484744204402), // CITAsmLE |
| 390 | UINT64_C(259484744179826), // CITAsmLH |
| 391 | UINT64_C(259484744179826), // CITAsmNE |
| 392 | UINT64_C(259484744204402), // CITAsmNH |
| 393 | UINT64_C(259484744171634), // CITAsmNHE |
| 394 | UINT64_C(259484744196210), // CITAsmNL |
| 395 | UINT64_C(259484744163442), // CITAsmNLE |
| 396 | UINT64_C(259484744188018), // CITAsmNLH |
| 397 | UINT64_C(2990604288), // CKSM |
| 398 | UINT64_C(1426063360), // CL |
| 399 | UINT64_C(234195976716288), // CLC |
| 400 | UINT64_C(3840), // CLCL |
| 401 | UINT64_C(2835349504), // CLCLE |
| 402 | UINT64_C(258385232527503), // CLCLU |
| 403 | UINT64_C(3013410816), // CLFDBR |
| 404 | UINT64_C(3108175872), // CLFDTR |
| 405 | UINT64_C(3013345280), // CLFEBR |
| 406 | UINT64_C(252187594719232), // CLFHSI |
| 407 | UINT64_C(213369680297984), // CLFI |
| 408 | UINT64_C(259484744155251), // CLFIT |
| 409 | UINT64_C(259484744155251), // CLFITAsm |
| 410 | UINT64_C(259484744188019), // CLFITAsmE |
| 411 | UINT64_C(259484744163443), // CLFITAsmH |
| 412 | UINT64_C(259484744196211), // CLFITAsmHE |
| 413 | UINT64_C(259484744171635), // CLFITAsmL |
| 414 | UINT64_C(259484744204403), // CLFITAsmLE |
| 415 | UINT64_C(259484744179827), // CLFITAsmLH |
| 416 | UINT64_C(259484744179827), // CLFITAsmNE |
| 417 | UINT64_C(259484744204403), // CLFITAsmNH |
| 418 | UINT64_C(259484744171635), // CLFITAsmNHE |
| 419 | UINT64_C(259484744196211), // CLFITAsmNL |
| 420 | UINT64_C(259484744163443), // CLFITAsmNLE |
| 421 | UINT64_C(259484744188019), // CLFITAsmNLH |
| 422 | UINT64_C(3013476352), // CLFXBR |
| 423 | UINT64_C(3108700160), // CLFXTR |
| 424 | UINT64_C(249589139505185), // CLG |
| 425 | UINT64_C(3014459392), // CLGDBR |
| 426 | UINT64_C(3108110336), // CLGDTR |
| 427 | UINT64_C(3014393856), // CLGEBR |
| 428 | UINT64_C(249589139505201), // CLGF |
| 429 | UINT64_C(213365385330688), // CLGFI |
| 430 | UINT64_C(3106996224), // CLGFR |
| 431 | UINT64_C(217763431841792), // CLGFRL |
| 432 | UINT64_C(217729072103424), // CLGHRL |
| 433 | UINT64_C(252170414850048), // CLGHSI |
| 434 | UINT64_C(259484744155389), // CLGIB |
| 435 | UINT64_C(259484744155389), // CLGIBAsm |
| 436 | UINT64_C(259519103893757), // CLGIBAsmE |
| 437 | UINT64_C(259493334089981), // CLGIBAsmH |
| 438 | UINT64_C(259527693828349), // CLGIBAsmHE |
| 439 | UINT64_C(259501924024573), // CLGIBAsmL |
| 440 | UINT64_C(259536283762941), // CLGIBAsmLE |
| 441 | UINT64_C(259510513959165), // CLGIBAsmLH |
| 442 | UINT64_C(259510513959165), // CLGIBAsmNE |
| 443 | UINT64_C(259536283762941), // CLGIBAsmNH |
| 444 | UINT64_C(259501924024573), // CLGIBAsmNHE |
| 445 | UINT64_C(259527693828349), // CLGIBAsmNL |
| 446 | UINT64_C(259493334089981), // CLGIBAsmNLE |
| 447 | UINT64_C(259519103893757), // CLGIBAsmNLH |
| 448 | UINT64_C(259484744155261), // CLGIJ |
| 449 | UINT64_C(259484744155261), // CLGIJAsm |
| 450 | UINT64_C(259519103893629), // CLGIJAsmE |
| 451 | UINT64_C(259493334089853), // CLGIJAsmH |
| 452 | UINT64_C(259527693828221), // CLGIJAsmHE |
| 453 | UINT64_C(259501924024445), // CLGIJAsmL |
| 454 | UINT64_C(259536283762813), // CLGIJAsmLE |
| 455 | UINT64_C(259510513959037), // CLGIJAsmLH |
| 456 | UINT64_C(259510513959037), // CLGIJAsmNE |
| 457 | UINT64_C(259536283762813), // CLGIJAsmNH |
| 458 | UINT64_C(259501924024445), // CLGIJAsmNHE |
| 459 | UINT64_C(259527693828221), // CLGIJAsmNL |
| 460 | UINT64_C(259493334089853), // CLGIJAsmNLE |
| 461 | UINT64_C(259519103893629), // CLGIJAsmNLH |
| 462 | UINT64_C(259484744155249), // CLGIT |
| 463 | UINT64_C(259484744155249), // CLGITAsm |
| 464 | UINT64_C(259484744188017), // CLGITAsmE |
| 465 | UINT64_C(259484744163441), // CLGITAsmH |
| 466 | UINT64_C(259484744196209), // CLGITAsmHE |
| 467 | UINT64_C(259484744171633), // CLGITAsmL |
| 468 | UINT64_C(259484744204401), // CLGITAsmLE |
| 469 | UINT64_C(259484744179825), // CLGITAsmLH |
| 470 | UINT64_C(259484744179825), // CLGITAsmNE |
| 471 | UINT64_C(259484744204401), // CLGITAsmNH |
| 472 | UINT64_C(259484744171633), // CLGITAsmNHE |
| 473 | UINT64_C(259484744196209), // CLGITAsmNL |
| 474 | UINT64_C(259484744163441), // CLGITAsmNLE |
| 475 | UINT64_C(259484744188017), // CLGITAsmNLH |
| 476 | UINT64_C(3105947648), // CLGR |
| 477 | UINT64_C(259484744155365), // CLGRB |
| 478 | UINT64_C(259484744155365), // CLGRBAsm |
| 479 | UINT64_C(259484744188133), // CLGRBAsmE |
| 480 | UINT64_C(259484744163557), // CLGRBAsmH |
| 481 | UINT64_C(259484744196325), // CLGRBAsmHE |
| 482 | UINT64_C(259484744171749), // CLGRBAsmL |
| 483 | UINT64_C(259484744204517), // CLGRBAsmLE |
| 484 | UINT64_C(259484744179941), // CLGRBAsmLH |
| 485 | UINT64_C(259484744179941), // CLGRBAsmNE |
| 486 | UINT64_C(259484744204517), // CLGRBAsmNH |
| 487 | UINT64_C(259484744171749), // CLGRBAsmNHE |
| 488 | UINT64_C(259484744196325), // CLGRBAsmNL |
| 489 | UINT64_C(259484744163557), // CLGRBAsmNLE |
| 490 | UINT64_C(259484744188133), // CLGRBAsmNLH |
| 491 | UINT64_C(259484744155237), // CLGRJ |
| 492 | UINT64_C(259484744155237), // CLGRJAsm |
| 493 | UINT64_C(259484744188005), // CLGRJAsmE |
| 494 | UINT64_C(259484744163429), // CLGRJAsmH |
| 495 | UINT64_C(259484744196197), // CLGRJAsmHE |
| 496 | UINT64_C(259484744171621), // CLGRJAsmL |
| 497 | UINT64_C(259484744204389), // CLGRJAsmLE |
| 498 | UINT64_C(259484744179813), // CLGRJAsmLH |
| 499 | UINT64_C(259484744179813), // CLGRJAsmNE |
| 500 | UINT64_C(259484744204389), // CLGRJAsmNH |
| 501 | UINT64_C(259484744171621), // CLGRJAsmNHE |
| 502 | UINT64_C(259484744196197), // CLGRJAsmNL |
| 503 | UINT64_C(259484744163429), // CLGRJAsmNLE |
| 504 | UINT64_C(259484744188005), // CLGRJAsmNLH |
| 505 | UINT64_C(217746251972608), // CLGRL |
| 506 | UINT64_C(3110141952), // CLGRT |
| 507 | UINT64_C(3110141952), // CLGRTAsm |
| 508 | UINT64_C(3110174720), // CLGRTAsmE |
| 509 | UINT64_C(3110150144), // CLGRTAsmH |
| 510 | UINT64_C(3110182912), // CLGRTAsmHE |
| 511 | UINT64_C(3110158336), // CLGRTAsmL |
| 512 | UINT64_C(3110191104), // CLGRTAsmLE |
| 513 | UINT64_C(3110166528), // CLGRTAsmLH |
| 514 | UINT64_C(3110166528), // CLGRTAsmNE |
| 515 | UINT64_C(3110191104), // CLGRTAsmNH |
| 516 | UINT64_C(3110158336), // CLGRTAsmNHE |
| 517 | UINT64_C(3110182912), // CLGRTAsmNL |
| 518 | UINT64_C(3110150144), // CLGRTAsmNLE |
| 519 | UINT64_C(3110174720), // CLGRTAsmNLH |
| 520 | UINT64_C(258385232527403), // CLGT |
| 521 | UINT64_C(258385232527403), // CLGTAsm |
| 522 | UINT64_C(258419592265771), // CLGTAsmE |
| 523 | UINT64_C(258393822461995), // CLGTAsmH |
| 524 | UINT64_C(258428182200363), // CLGTAsmHE |
| 525 | UINT64_C(258402412396587), // CLGTAsmL |
| 526 | UINT64_C(258436772134955), // CLGTAsmLE |
| 527 | UINT64_C(258411002331179), // CLGTAsmLH |
| 528 | UINT64_C(258411002331179), // CLGTAsmNE |
| 529 | UINT64_C(258436772134955), // CLGTAsmNH |
| 530 | UINT64_C(258402412396587), // CLGTAsmNHE |
| 531 | UINT64_C(258428182200363), // CLGTAsmNL |
| 532 | UINT64_C(258393822461995), // CLGTAsmNLE |
| 533 | UINT64_C(258419592265771), // CLGTAsmNLH |
| 534 | UINT64_C(3014524928), // CLGXBR |
| 535 | UINT64_C(3108634624), // CLGXTR |
| 536 | UINT64_C(249589139505359), // CLHF |
| 537 | UINT64_C(3117350912), // CLHHR |
| 538 | UINT64_C(252153234980864), // CLHHSI |
| 539 | UINT64_C(3118399488), // CLHLR |
| 540 | UINT64_C(217733367070720), // CLHRL |
| 541 | UINT64_C(2499805184), // CLI |
| 542 | UINT64_C(259484744155391), // CLIB |
| 543 | UINT64_C(259484744155391), // CLIBAsm |
| 544 | UINT64_C(259519103893759), // CLIBAsmE |
| 545 | UINT64_C(259493334089983), // CLIBAsmH |
| 546 | UINT64_C(259527693828351), // CLIBAsmHE |
| 547 | UINT64_C(259501924024575), // CLIBAsmL |
| 548 | UINT64_C(259536283762943), // CLIBAsmLE |
| 549 | UINT64_C(259510513959167), // CLIBAsmLH |
| 550 | UINT64_C(259510513959167), // CLIBAsmNE |
| 551 | UINT64_C(259536283762943), // CLIBAsmNH |
| 552 | UINT64_C(259501924024575), // CLIBAsmNHE |
| 553 | UINT64_C(259527693828351), // CLIBAsmNL |
| 554 | UINT64_C(259493334089983), // CLIBAsmNLE |
| 555 | UINT64_C(259519103893759), // CLIBAsmNLH |
| 556 | UINT64_C(224364796575744), // CLIH |
| 557 | UINT64_C(259484744155263), // CLIJ |
| 558 | UINT64_C(259484744155263), // CLIJAsm |
| 559 | UINT64_C(259519103893631), // CLIJAsmE |
| 560 | UINT64_C(259493334089855), // CLIJAsmH |
| 561 | UINT64_C(259527693828223), // CLIJAsmHE |
| 562 | UINT64_C(259501924024447), // CLIJAsmL |
| 563 | UINT64_C(259536283762815), // CLIJAsmLE |
| 564 | UINT64_C(259510513959039), // CLIJAsmLH |
| 565 | UINT64_C(259510513959039), // CLIJAsmNE |
| 566 | UINT64_C(259536283762815), // CLIJAsmNH |
| 567 | UINT64_C(259501924024447), // CLIJAsmNHE |
| 568 | UINT64_C(259527693828223), // CLIJAsmNL |
| 569 | UINT64_C(259493334089855), // CLIJAsmNLE |
| 570 | UINT64_C(259519103893631), // CLIJAsmNLH |
| 571 | UINT64_C(258385232527445), // CLIY |
| 572 | UINT64_C(3170893824), // CLM |
| 573 | UINT64_C(258385232527392), // CLMH |
| 574 | UINT64_C(258385232527393), // CLMY |
| 575 | UINT64_C(5376), // CLR |
| 576 | UINT64_C(259484744155383), // CLRB |
| 577 | UINT64_C(259484744155383), // CLRBAsm |
| 578 | UINT64_C(259484744188151), // CLRBAsmE |
| 579 | UINT64_C(259484744163575), // CLRBAsmH |
| 580 | UINT64_C(259484744196343), // CLRBAsmHE |
| 581 | UINT64_C(259484744171767), // CLRBAsmL |
| 582 | UINT64_C(259484744204535), // CLRBAsmLE |
| 583 | UINT64_C(259484744179959), // CLRBAsmLH |
| 584 | UINT64_C(259484744179959), // CLRBAsmNE |
| 585 | UINT64_C(259484744204535), // CLRBAsmNH |
| 586 | UINT64_C(259484744171767), // CLRBAsmNHE |
| 587 | UINT64_C(259484744196343), // CLRBAsmNL |
| 588 | UINT64_C(259484744163575), // CLRBAsmNLE |
| 589 | UINT64_C(259484744188151), // CLRBAsmNLH |
| 590 | UINT64_C(259484744155255), // CLRJ |
| 591 | UINT64_C(259484744155255), // CLRJAsm |
| 592 | UINT64_C(259484744188023), // CLRJAsmE |
| 593 | UINT64_C(259484744163447), // CLRJAsmH |
| 594 | UINT64_C(259484744196215), // CLRJAsmHE |
| 595 | UINT64_C(259484744171639), // CLRJAsmL |
| 596 | UINT64_C(259484744204407), // CLRJAsmLE |
| 597 | UINT64_C(259484744179831), // CLRJAsmLH |
| 598 | UINT64_C(259484744179831), // CLRJAsmNE |
| 599 | UINT64_C(259484744204407), // CLRJAsmNH |
| 600 | UINT64_C(259484744171639), // CLRJAsmNHE |
| 601 | UINT64_C(259484744196215), // CLRJAsmNL |
| 602 | UINT64_C(259484744163447), // CLRJAsmNLE |
| 603 | UINT64_C(259484744188023), // CLRJAsmNLH |
| 604 | UINT64_C(217767726809088), // CLRL |
| 605 | UINT64_C(3111321600), // CLRT |
| 606 | UINT64_C(3111321600), // CLRTAsm |
| 607 | UINT64_C(3111354368), // CLRTAsmE |
| 608 | UINT64_C(3111329792), // CLRTAsmH |
| 609 | UINT64_C(3111362560), // CLRTAsmHE |
| 610 | UINT64_C(3111337984), // CLRTAsmL |
| 611 | UINT64_C(3111370752), // CLRTAsmLE |
| 612 | UINT64_C(3111346176), // CLRTAsmLH |
| 613 | UINT64_C(3111346176), // CLRTAsmNE |
| 614 | UINT64_C(3111370752), // CLRTAsmNH |
| 615 | UINT64_C(3111337984), // CLRTAsmNHE |
| 616 | UINT64_C(3111362560), // CLRTAsmNL |
| 617 | UINT64_C(3111329792), // CLRTAsmNLE |
| 618 | UINT64_C(3111354368), // CLRTAsmNLH |
| 619 | UINT64_C(2992439296), // CLST |
| 620 | UINT64_C(258385232527395), // CLT |
| 621 | UINT64_C(258385232527395), // CLTAsm |
| 622 | UINT64_C(258419592265763), // CLTAsmE |
| 623 | UINT64_C(258393822461987), // CLTAsmH |
| 624 | UINT64_C(258428182200355), // CLTAsmHE |
| 625 | UINT64_C(258402412396579), // CLTAsmL |
| 626 | UINT64_C(258436772134947), // CLTAsmLE |
| 627 | UINT64_C(258411002331171), // CLTAsmLH |
| 628 | UINT64_C(258411002331171), // CLTAsmNE |
| 629 | UINT64_C(258436772134947), // CLTAsmNH |
| 630 | UINT64_C(258402412396579), // CLTAsmNHE |
| 631 | UINT64_C(258428182200355), // CLTAsmNL |
| 632 | UINT64_C(258393822461987), // CLTAsmNLE |
| 633 | UINT64_C(258419592265763), // CLTAsmNLH |
| 634 | UINT64_C(249589139505237), // CLY |
| 635 | UINT64_C(3110600704), // CLZG |
| 636 | UINT64_C(2992832512), // CMPSC |
| 637 | UINT64_C(273778395316224), // CP |
| 638 | UINT64_C(260584255783084), // CPDT |
| 639 | UINT64_C(3010592768), // CPSDRdd |
| 640 | UINT64_C(3010592768), // CPSDRdh |
| 641 | UINT64_C(3010592768), // CPSDRds |
| 642 | UINT64_C(3010592768), // CPSDRhd |
| 643 | UINT64_C(3010592768), // CPSDRhh |
| 644 | UINT64_C(3010592768), // CPSDRhs |
| 645 | UINT64_C(3010592768), // CPSDRsd |
| 646 | UINT64_C(3010592768), // CPSDRsh |
| 647 | UINT64_C(3010592768), // CPSDRss |
| 648 | UINT64_C(260584255783085), // CPXT |
| 649 | UINT64_C(2991390720), // CPYA |
| 650 | UINT64_C(6400), // CR |
| 651 | UINT64_C(259484744155382), // CRB |
| 652 | UINT64_C(259484744155382), // CRBAsm |
| 653 | UINT64_C(259484744188150), // CRBAsmE |
| 654 | UINT64_C(259484744163574), // CRBAsmH |
| 655 | UINT64_C(259484744196342), // CRBAsmHE |
| 656 | UINT64_C(259484744171766), // CRBAsmL |
| 657 | UINT64_C(259484744204534), // CRBAsmLE |
| 658 | UINT64_C(259484744179958), // CRBAsmLH |
| 659 | UINT64_C(259484744179958), // CRBAsmNE |
| 660 | UINT64_C(259484744204534), // CRBAsmNH |
| 661 | UINT64_C(259484744171766), // CRBAsmNHE |
| 662 | UINT64_C(259484744196342), // CRBAsmNL |
| 663 | UINT64_C(259484744163574), // CRBAsmNLE |
| 664 | UINT64_C(259484744188150), // CRBAsmNLH |
| 665 | UINT64_C(3113156608), // CRDTE |
| 666 | UINT64_C(3113156608), // CRDTEOpt |
| 667 | UINT64_C(259484744155254), // CRJ |
| 668 | UINT64_C(259484744155254), // CRJAsm |
| 669 | UINT64_C(259484744188022), // CRJAsmE |
| 670 | UINT64_C(259484744163446), // CRJAsmH |
| 671 | UINT64_C(259484744196214), // CRJAsmHE |
| 672 | UINT64_C(259484744171638), // CRJAsmL |
| 673 | UINT64_C(259484744204406), // CRJAsmLE |
| 674 | UINT64_C(259484744179830), // CRJAsmLH |
| 675 | UINT64_C(259484744179830), // CRJAsmNE |
| 676 | UINT64_C(259484744204406), // CRJAsmNH |
| 677 | UINT64_C(259484744171638), // CRJAsmNHE |
| 678 | UINT64_C(259484744196214), // CRJAsmNL |
| 679 | UINT64_C(259484744163446), // CRJAsmNLE |
| 680 | UINT64_C(259484744188022), // CRJAsmNLH |
| 681 | UINT64_C(217759136874496), // CRL |
| 682 | UINT64_C(3111256064), // CRT |
| 683 | UINT64_C(3111256064), // CRTAsm |
| 684 | UINT64_C(3111288832), // CRTAsmE |
| 685 | UINT64_C(3111264256), // CRTAsmH |
| 686 | UINT64_C(3111297024), // CRTAsmHE |
| 687 | UINT64_C(3111272448), // CRTAsmL |
| 688 | UINT64_C(3111305216), // CRTAsmLE |
| 689 | UINT64_C(3111280640), // CRTAsmLH |
| 690 | UINT64_C(3111280640), // CRTAsmNE |
| 691 | UINT64_C(3111305216), // CRTAsmNH |
| 692 | UINT64_C(3111272448), // CRTAsmNHE |
| 693 | UINT64_C(3111297024), // CRTAsmNL |
| 694 | UINT64_C(3111264256), // CRTAsmNLE |
| 695 | UINT64_C(3111288832), // CRTAsmNLH |
| 696 | UINT64_C(3120562176), // CS |
| 697 | UINT64_C(2989490176), // CSCH |
| 698 | UINT64_C(3017998336), // CSDTR |
| 699 | UINT64_C(258385232527408), // CSG |
| 700 | UINT64_C(2991587328), // CSP |
| 701 | UINT64_C(3112828928), // CSPG |
| 702 | UINT64_C(219910915489792), // CSST |
| 703 | UINT64_C(3018522624), // CSXTR |
| 704 | UINT64_C(258385232527380), // CSY |
| 705 | UINT64_C(3110666240), // CTZG |
| 706 | UINT64_C(2997288960), // CU12 |
| 707 | UINT64_C(2997288960), // CU12Opt |
| 708 | UINT64_C(3115319296), // CU14 |
| 709 | UINT64_C(3115319296), // CU14Opt |
| 710 | UINT64_C(2997223424), // CU21 |
| 711 | UINT64_C(2997223424), // CU21Opt |
| 712 | UINT64_C(3115384832), // CU24 |
| 713 | UINT64_C(3115384832), // CU24Opt |
| 714 | UINT64_C(3115450368), // CU41 |
| 715 | UINT64_C(3115515904), // CU42 |
| 716 | UINT64_C(3017932800), // CUDTR |
| 717 | UINT64_C(2992046080), // CUSE |
| 718 | UINT64_C(2997288960), // CUTFU |
| 719 | UINT64_C(2997288960), // CUTFUOpt |
| 720 | UINT64_C(2997223424), // CUUTF |
| 721 | UINT64_C(2997223424), // CUUTFOpt |
| 722 | UINT64_C(3018457088), // CUXTR |
| 723 | UINT64_C(1325400064), // CVB |
| 724 | UINT64_C(249589139505166), // CVBG |
| 725 | UINT64_C(249589139505158), // CVBY |
| 726 | UINT64_C(1308622848), // CVD |
| 727 | UINT64_C(249589139505198), // CVDG |
| 728 | UINT64_C(249589139505190), // CVDY |
| 729 | UINT64_C(3007905792), // CXBR |
| 730 | UINT64_C(3012952064), // CXFBR |
| 731 | UINT64_C(3012952064), // CXFBRA |
| 732 | UINT64_C(3015049216), // CXFR |
| 733 | UINT64_C(3109617664), // CXFTR |
| 734 | UINT64_C(3014000640), // CXGBR |
| 735 | UINT64_C(3014000640), // CXGBRA |
| 736 | UINT64_C(3016097792), // CXGR |
| 737 | UINT64_C(3019440128), // CXGTR |
| 738 | UINT64_C(3019440128), // CXGTRA |
| 739 | UINT64_C(3012689920), // CXLFBR |
| 740 | UINT64_C(3109748736), // CXLFTR |
| 741 | UINT64_C(3013738496), // CXLGBR |
| 742 | UINT64_C(3109683200), // CXLGTR |
| 743 | UINT64_C(260584255783087), // CXPT |
| 744 | UINT64_C(3010002944), // CXR |
| 745 | UINT64_C(3019571200), // CXSTR |
| 746 | UINT64_C(3018588160), // CXTR |
| 747 | UINT64_C(3019505664), // CXUTR |
| 748 | UINT64_C(260584255783083), // CXZT |
| 749 | UINT64_C(249589139505241), // CY |
| 750 | UINT64_C(260584255783080), // CZDT |
| 751 | UINT64_C(260584255783081), // CZXT |
| 752 | UINT64_C(1560281088), // D |
| 753 | UINT64_C(1828716544), // DD |
| 754 | UINT64_C(260584255782941), // DDB |
| 755 | UINT64_C(3005022208), // DDBR |
| 756 | UINT64_C(11520), // DDR |
| 757 | UINT64_C(3016818688), // DDTR |
| 758 | UINT64_C(3016818688), // DDTRA |
| 759 | UINT64_C(2097152000), // DE |
| 760 | UINT64_C(260584255782925), // DEB |
| 761 | UINT64_C(3003973632), // DEBR |
| 762 | UINT64_C(15616), // DER |
| 763 | UINT64_C(3107520512), // DFLTCC |
| 764 | UINT64_C(2197815296), // DIAG |
| 765 | UINT64_C(3009085440), // DIDBR |
| 766 | UINT64_C(3008561152), // DIEBR |
| 767 | UINT64_C(249589139505303), // DL |
| 768 | UINT64_C(249589139505287), // DLG |
| 769 | UINT64_C(3112632320), // DLGR |
| 770 | UINT64_C(3113680896), // DLR |
| 771 | UINT64_C(278176441827328), // DP |
| 772 | UINT64_C(7424), // DR |
| 773 | UINT64_C(249589139505165), // DSG |
| 774 | UINT64_C(249589139505181), // DSGF |
| 775 | UINT64_C(3105685504), // DSGFR |
| 776 | UINT64_C(3104636928), // DSGR |
| 777 | UINT64_C(3008167936), // DXBR |
| 778 | UINT64_C(2989293568), // DXR |
| 779 | UINT64_C(3017342976), // DXTR |
| 780 | UINT64_C(3017342976), // DXTRA |
| 781 | UINT64_C(2991521792), // EAR |
| 782 | UINT64_C(258385232527436), // ECAG |
| 783 | UINT64_C(3001286656), // ECCTR |
| 784 | UINT64_C(3001876480), // ECPGA |
| 785 | UINT64_C(219906620522496), // ECTG |
| 786 | UINT64_C(244091581366272), // ED |
| 787 | UINT64_C(245191092994048), // EDMK |
| 788 | UINT64_C(3018129408), // EEDTR |
| 789 | UINT64_C(3018653696), // EEXTR |
| 790 | UINT64_C(3012296704), // EFPC |
| 791 | UINT64_C(3113877504), // EPAIR |
| 792 | UINT64_C(2988834816), // EPAR |
| 793 | UINT64_C(3001352192), // EPCTR |
| 794 | UINT64_C(3113025536), // EPSW |
| 795 | UINT64_C(2991128576), // EREG |
| 796 | UINT64_C(3104702464), // EREGG |
| 797 | UINT64_C(3113943040), // ESAIR |
| 798 | UINT64_C(2988900352), // ESAR |
| 799 | UINT64_C(3018260480), // ESDTR |
| 800 | UINT64_C(3114074112), // ESEA |
| 801 | UINT64_C(2991194112), // ESTA |
| 802 | UINT64_C(3018784768), // ESXTR |
| 803 | UINT64_C(3001810944), // ETND |
| 804 | UINT64_C(1140850688), // EX |
| 805 | UINT64_C(217703302299648), // EXRL |
| 806 | UINT64_C(3009347584), // FIDBR |
| 807 | UINT64_C(3009347584), // FIDBRA |
| 808 | UINT64_C(3011444736), // FIDR |
| 809 | UINT64_C(3017211904), // FIDTR |
| 810 | UINT64_C(3008823296), // FIEBR |
| 811 | UINT64_C(3008823296), // FIEBRA |
| 812 | UINT64_C(3010920448), // FIER |
| 813 | UINT64_C(3007774720), // FIXBR |
| 814 | UINT64_C(3007774720), // FIXBRA |
| 815 | UINT64_C(3009871872), // FIXR |
| 816 | UINT64_C(3017736192), // FIXTR |
| 817 | UINT64_C(3112370176), // FLOGR |
| 818 | UINT64_C(9216), // HDR |
| 819 | UINT64_C(13312), // HER |
| 820 | UINT64_C(2989555712), // HSCH |
| 821 | UINT64_C(2988703744), // IAC |
| 822 | UINT64_C(1124073472), // IC |
| 823 | UINT64_C(1124073472), // IC32 |
| 824 | UINT64_C(249589139505267), // IC32Y |
| 825 | UINT64_C(3204448256), // ICM |
| 826 | UINT64_C(258385232527488), // ICMH |
| 827 | UINT64_C(258385232527489), // ICMY |
| 828 | UINT64_C(249589139505267), // ICY |
| 829 | UINT64_C(3113091072), // IDTE |
| 830 | UINT64_C(3113091072), // IDTEOpt |
| 831 | UINT64_C(3019243520), // IEDTR |
| 832 | UINT64_C(3019767808), // IEXTR |
| 833 | UINT64_C(211140592271360), // IIHF |
| 834 | UINT64_C(2768240640), // IIHH |
| 835 | UINT64_C(2768306176), // IIHL |
| 836 | UINT64_C(211144887238656), // IILF |
| 837 | UINT64_C(2768371712), // IILH |
| 838 | UINT64_C(2768437248), // IILL |
| 839 | UINT64_C(2987065344), // IPK |
| 840 | UINT64_C(2988572672), // IPM |
| 841 | UINT64_C(2988507136), // IPTE |
| 842 | UINT64_C(2988507136), // IPTEOpt |
| 843 | UINT64_C(2988507136), // IPTEOptOpt |
| 844 | UINT64_C(3115057152), // IRBM |
| 845 | UINT64_C(2989031424), // ISKE |
| 846 | UINT64_C(2988638208), // IVSK |
| 847 | UINT64_C(0), // InsnE |
| 848 | UINT64_C(0), // InsnI |
| 849 | UINT64_C(0), // InsnIE |
| 850 | UINT64_C(0), // InsnMII |
| 851 | UINT64_C(0), // InsnRI |
| 852 | UINT64_C(0), // InsnRIE |
| 853 | UINT64_C(0), // InsnRIEa |
| 854 | UINT64_C(0), // InsnRIEb |
| 855 | UINT64_C(0), // InsnRIEc |
| 856 | UINT64_C(0), // InsnRIEd |
| 857 | UINT64_C(0), // InsnRIEe |
| 858 | UINT64_C(0), // InsnRIEf |
| 859 | UINT64_C(0), // InsnRIEg |
| 860 | UINT64_C(0), // InsnRIL |
| 861 | UINT64_C(0), // InsnRILU |
| 862 | UINT64_C(0), // InsnRILa |
| 863 | UINT64_C(0), // InsnRILb |
| 864 | UINT64_C(0), // InsnRILc |
| 865 | UINT64_C(0), // InsnRIS |
| 866 | UINT64_C(0), // InsnRIa |
| 867 | UINT64_C(0), // InsnRIb |
| 868 | UINT64_C(0), // InsnRIc |
| 869 | UINT64_C(0), // InsnRR |
| 870 | UINT64_C(0), // InsnRRD |
| 871 | UINT64_C(0), // InsnRRE |
| 872 | UINT64_C(0), // InsnRRF |
| 873 | UINT64_C(0), // InsnRRFa |
| 874 | UINT64_C(0), // InsnRRFb |
| 875 | UINT64_C(0), // InsnRRFc |
| 876 | UINT64_C(0), // InsnRRFd |
| 877 | UINT64_C(0), // InsnRRFe |
| 878 | UINT64_C(0), // InsnRRS |
| 879 | UINT64_C(0), // InsnRS |
| 880 | UINT64_C(0), // InsnRSE |
| 881 | UINT64_C(0), // InsnRSI |
| 882 | UINT64_C(0), // InsnRSLa |
| 883 | UINT64_C(0), // InsnRSLb |
| 884 | UINT64_C(0), // InsnRSY |
| 885 | UINT64_C(0), // InsnRSYa |
| 886 | UINT64_C(0), // InsnRSYb |
| 887 | UINT64_C(0), // InsnRSa |
| 888 | UINT64_C(0), // InsnRSb |
| 889 | UINT64_C(0), // InsnRX |
| 890 | UINT64_C(0), // InsnRXE |
| 891 | UINT64_C(0), // InsnRXF |
| 892 | UINT64_C(0), // InsnRXY |
| 893 | UINT64_C(0), // InsnRXYa |
| 894 | UINT64_C(0), // InsnRXYb |
| 895 | UINT64_C(0), // InsnRXYc |
| 896 | UINT64_C(0), // InsnRXa |
| 897 | UINT64_C(0), // InsnRXb |
| 898 | UINT64_C(0), // InsnS |
| 899 | UINT64_C(0), // InsnSI |
| 900 | UINT64_C(0), // InsnSIL |
| 901 | UINT64_C(0), // InsnSIY |
| 902 | UINT64_C(0), // InsnSMI |
| 903 | UINT64_C(0), // InsnSS |
| 904 | UINT64_C(0), // InsnSSE |
| 905 | UINT64_C(0), // InsnSSF |
| 906 | UINT64_C(0), // InsnSSa |
| 907 | UINT64_C(0), // InsnSSb |
| 908 | UINT64_C(0), // InsnSSc |
| 909 | UINT64_C(0), // InsnSSd |
| 910 | UINT64_C(0), // InsnSSe |
| 911 | UINT64_C(0), // InsnSSf |
| 912 | UINT64_C(0), // InsnVRI |
| 913 | UINT64_C(0), // InsnVRIa |
| 914 | UINT64_C(0), // InsnVRIb |
| 915 | UINT64_C(0), // InsnVRIc |
| 916 | UINT64_C(0), // InsnVRId |
| 917 | UINT64_C(0), // InsnVRIe |
| 918 | UINT64_C(0), // InsnVRIf |
| 919 | UINT64_C(0), // InsnVRIg |
| 920 | UINT64_C(0), // InsnVRIh |
| 921 | UINT64_C(0), // InsnVRIi |
| 922 | UINT64_C(0), // InsnVRIj |
| 923 | UINT64_C(0), // InsnVRIk |
| 924 | UINT64_C(0), // InsnVRIl |
| 925 | UINT64_C(0), // InsnVRR |
| 926 | UINT64_C(0), // InsnVRRa |
| 927 | UINT64_C(0), // InsnVRRb |
| 928 | UINT64_C(0), // InsnVRRc |
| 929 | UINT64_C(0), // InsnVRRd |
| 930 | UINT64_C(0), // InsnVRRe |
| 931 | UINT64_C(0), // InsnVRRf |
| 932 | UINT64_C(0), // InsnVRRg |
| 933 | UINT64_C(0), // InsnVRRh |
| 934 | UINT64_C(0), // InsnVRRi |
| 935 | UINT64_C(0), // InsnVRRj |
| 936 | UINT64_C(0), // InsnVRRk |
| 937 | UINT64_C(0), // InsnVRS |
| 938 | UINT64_C(0), // InsnVRSa |
| 939 | UINT64_C(0), // InsnVRSb |
| 940 | UINT64_C(0), // InsnVRSc |
| 941 | UINT64_C(0), // InsnVRSd |
| 942 | UINT64_C(0), // InsnVRV |
| 943 | UINT64_C(0), // InsnVRX |
| 944 | UINT64_C(0), // InsnVSI |
| 945 | UINT64_C(2817785856), // J |
| 946 | UINT64_C(2810445824), // JAsmE |
| 947 | UINT64_C(2804154368), // JAsmH |
| 948 | UINT64_C(2812542976), // JAsmHE |
| 949 | UINT64_C(2806251520), // JAsmL |
| 950 | UINT64_C(2814640128), // JAsmLE |
| 951 | UINT64_C(2808348672), // JAsmLH |
| 952 | UINT64_C(2806251520), // JAsmM |
| 953 | UINT64_C(2809397248), // JAsmNE |
| 954 | UINT64_C(2815688704), // JAsmNH |
| 955 | UINT64_C(2807300096), // JAsmNHE |
| 956 | UINT64_C(2813591552), // JAsmNL |
| 957 | UINT64_C(2805202944), // JAsmNLE |
| 958 | UINT64_C(2811494400), // JAsmNLH |
| 959 | UINT64_C(2813591552), // JAsmNM |
| 960 | UINT64_C(2816737280), // JAsmNO |
| 961 | UINT64_C(2815688704), // JAsmNP |
| 962 | UINT64_C(2809397248), // JAsmNZ |
| 963 | UINT64_C(2803105792), // JAsmO |
| 964 | UINT64_C(2804154368), // JAsmP |
| 965 | UINT64_C(2810445824), // JAsmZ |
| 966 | UINT64_C(212154204553216), // JG |
| 967 | UINT64_C(211673168216064), // JGAsmE |
| 968 | UINT64_C(211260851355648), // JGAsmH |
| 969 | UINT64_C(211810607169536), // JGAsmHE |
| 970 | UINT64_C(211398290309120), // JGAsmL |
| 971 | UINT64_C(211948046123008), // JGAsmLE |
| 972 | UINT64_C(211535729262592), // JGAsmLH |
| 973 | UINT64_C(211398290309120), // JGAsmM |
| 974 | UINT64_C(211604448739328), // JGAsmNE |
| 975 | UINT64_C(212016765599744), // JGAsmNH |
| 976 | UINT64_C(211467009785856), // JGAsmNHE |
| 977 | UINT64_C(211879326646272), // JGAsmNL |
| 978 | UINT64_C(211329570832384), // JGAsmNLE |
| 979 | UINT64_C(211741887692800), // JGAsmNLH |
| 980 | UINT64_C(211879326646272), // JGAsmNM |
| 981 | UINT64_C(212085485076480), // JGAsmNO |
| 982 | UINT64_C(212016765599744), // JGAsmNP |
| 983 | UINT64_C(211604448739328), // JGAsmNZ |
| 984 | UINT64_C(211192131878912), // JGAsmO |
| 985 | UINT64_C(211260851355648), // JGAsmP |
| 986 | UINT64_C(211673168216064), // JGAsmZ |
| 987 | UINT64_C(211123412402176), // JGNOP |
| 988 | UINT64_C(2802057216), // JNOP |
| 989 | UINT64_C(260584255782936), // KDB |
| 990 | UINT64_C(3004694528), // KDBR |
| 991 | UINT64_C(3107586048), // KDSA |
| 992 | UINT64_C(3017801728), // KDTR |
| 993 | UINT64_C(260584255782920), // KEB |
| 994 | UINT64_C(3003645952), // KEBR |
| 995 | UINT64_C(3107848192), // KIMD |
| 996 | UINT64_C(3107848192), // KIMDOpt |
| 997 | UINT64_C(3107913728), // KLMD |
| 998 | UINT64_C(3107913728), // KLMDOpt |
| 999 | UINT64_C(3106799616), // KM |
| 1000 | UINT64_C(3106471936), // KMA |
| 1001 | UINT64_C(3105751040), // KMAC |
| 1002 | UINT64_C(3106865152), // KMC |
| 1003 | UINT64_C(3106734080), // KMCTR |
| 1004 | UINT64_C(3106537472), // KMF |
| 1005 | UINT64_C(3106603008), // KMO |
| 1006 | UINT64_C(3007840256), // KXBR |
| 1007 | UINT64_C(3018326016), // KXTR |
| 1008 | UINT64_C(1476395008), // L |
| 1009 | UINT64_C(1090519040), // LA |
| 1010 | UINT64_C(258385232527608), // LAA |
| 1011 | UINT64_C(258385232527592), // LAAG |
| 1012 | UINT64_C(258385232527610), // LAAL |
| 1013 | UINT64_C(258385232527594), // LAALG |
| 1014 | UINT64_C(1358954496), // LAE |
| 1015 | UINT64_C(249589139505269), // LAEY |
| 1016 | UINT64_C(2583691264), // LAM |
| 1017 | UINT64_C(258385232527514), // LAMY |
| 1018 | UINT64_C(258385232527604), // LAN |
| 1019 | UINT64_C(258385232527588), // LANG |
| 1020 | UINT64_C(258385232527606), // LAO |
| 1021 | UINT64_C(258385232527590), // LAOG |
| 1022 | UINT64_C(211106232532992), // LARL |
| 1023 | UINT64_C(251788162760704), // LASP |
| 1024 | UINT64_C(249589139505311), // LAT |
| 1025 | UINT64_C(258385232527607), // LAX |
| 1026 | UINT64_C(258385232527591), // LAXG |
| 1027 | UINT64_C(249589139505265), // LAY |
| 1028 | UINT64_C(249589139505270), // LB |
| 1029 | UINT64_C(2986344448), // LBEAR |
| 1030 | UINT64_C(249589139505344), // LBH |
| 1031 | UINT64_C(3106275328), // LBR |
| 1032 | UINT64_C(253987186016295), // LCBB |
| 1033 | UINT64_C(2994995200), // LCCTL |
| 1034 | UINT64_C(3004366848), // LCDBR |
| 1035 | UINT64_C(3010658304), // LCDFR |
| 1036 | UINT64_C(3010658304), // LCDFR_16 |
| 1037 | UINT64_C(3010658304), // LCDFR_32 |
| 1038 | UINT64_C(8960), // LCDR |
| 1039 | UINT64_C(3003318272), // LCEBR |
| 1040 | UINT64_C(13056), // LCER |
| 1041 | UINT64_C(3105030144), // LCGFR |
| 1042 | UINT64_C(3103981568), // LCGR |
| 1043 | UINT64_C(4864), // LCR |
| 1044 | UINT64_C(3070230528), // LCTL |
| 1045 | UINT64_C(258385232527407), // LCTLG |
| 1046 | UINT64_C(3007512576), // LCXBR |
| 1047 | UINT64_C(3009609728), // LCXR |
| 1048 | UINT64_C(1744830464), // LD |
| 1049 | UINT64_C(260584255782948), // LDE |
| 1050 | UINT64_C(260584255782948), // LDE32 |
| 1051 | UINT64_C(260584255782916), // LDEB |
| 1052 | UINT64_C(3003383808), // LDEBR |
| 1053 | UINT64_C(3005480960), // LDER |
| 1054 | UINT64_C(3017015296), // LDETR |
| 1055 | UINT64_C(3015770112), // LDGR |
| 1056 | UINT64_C(10240), // LDR |
| 1057 | UINT64_C(10240), // LDR16 |
| 1058 | UINT64_C(10240), // LDR32 |
| 1059 | UINT64_C(3007643648), // LDXBR |
| 1060 | UINT64_C(3007643648), // LDXBRA |
| 1061 | UINT64_C(9472), // LDXR |
| 1062 | UINT64_C(3017605120), // LDXTR |
| 1063 | UINT64_C(260584255783013), // LDY |
| 1064 | UINT64_C(2013265920), // LE |
| 1065 | UINT64_C(2013265920), // LE16 |
| 1066 | UINT64_C(260584255783012), // LE16Y |
| 1067 | UINT64_C(3007578112), // LEDBR |
| 1068 | UINT64_C(3007578112), // LEDBRA |
| 1069 | UINT64_C(13568), // LEDR |
| 1070 | UINT64_C(3017080832), // LEDTR |
| 1071 | UINT64_C(14336), // LER |
| 1072 | UINT64_C(14336), // LER16 |
| 1073 | UINT64_C(3007709184), // LEXBR |
| 1074 | UINT64_C(3007709184), // LEXBRA |
| 1075 | UINT64_C(3009806336), // LEXR |
| 1076 | UINT64_C(260584255783012), // LEY |
| 1077 | UINT64_C(2998730752), // LFAS |
| 1078 | UINT64_C(249589139505354), // LFH |
| 1079 | UINT64_C(249589139505352), // LFHAT |
| 1080 | UINT64_C(2996633600), // LFPC |
| 1081 | UINT64_C(249589139505156), // LG |
| 1082 | UINT64_C(249589139505285), // LGAT |
| 1083 | UINT64_C(249589139505271), // LGB |
| 1084 | UINT64_C(3104178176), // LGBR |
| 1085 | UINT64_C(3016556544), // LGDR |
| 1086 | UINT64_C(249589139505172), // LGF |
| 1087 | UINT64_C(211110527500288), // LGFI |
| 1088 | UINT64_C(3105095680), // LGFR |
| 1089 | UINT64_C(215555818651648), // LGFRL |
| 1090 | UINT64_C(249589139505228), // LGG |
| 1091 | UINT64_C(249589139505173), // LGH |
| 1092 | UINT64_C(2802384896), // LGHI |
| 1093 | UINT64_C(3104243712), // LGHR |
| 1094 | UINT64_C(215521458913280), // LGHRL |
| 1095 | UINT64_C(3104047104), // LGR |
| 1096 | UINT64_C(215538638782464), // LGRL |
| 1097 | UINT64_C(249589139505229), // LGSC |
| 1098 | UINT64_C(1207959552), // LH |
| 1099 | UINT64_C(249589139505348), // LHH |
| 1100 | UINT64_C(2802319360), // LHI |
| 1101 | UINT64_C(3106340864), // LHR |
| 1102 | UINT64_C(215525753880576), // LHRL |
| 1103 | UINT64_C(249589139505272), // LHY |
| 1104 | UINT64_C(249589139505300), // LLC |
| 1105 | UINT64_C(249589139505346), // LLCH |
| 1106 | UINT64_C(3113484288), // LLCR |
| 1107 | UINT64_C(249589139505296), // LLGC |
| 1108 | UINT64_C(3112435712), // LLGCR |
| 1109 | UINT64_C(249589139505174), // LLGF |
| 1110 | UINT64_C(249589139505309), // LLGFAT |
| 1111 | UINT64_C(3105226752), // LLGFR |
| 1112 | UINT64_C(215564408586240), // LLGFRL |
| 1113 | UINT64_C(249589139505224), // LLGFSG |
| 1114 | UINT64_C(249589139505297), // LLGH |
| 1115 | UINT64_C(3112501248), // LLGHR |
| 1116 | UINT64_C(215530048847872), // LLGHRL |
| 1117 | UINT64_C(249589139505175), // LLGT |
| 1118 | UINT64_C(249589139505308), // LLGTAT |
| 1119 | UINT64_C(3105292288), // LLGTR |
| 1120 | UINT64_C(249589139505301), // LLH |
| 1121 | UINT64_C(249589139505350), // LLHH |
| 1122 | UINT64_C(3113549824), // LLHR |
| 1123 | UINT64_C(215512868978688), // LLHRL |
| 1124 | UINT64_C(211166362075136), // LLIHF |
| 1125 | UINT64_C(2769027072), // LLIHH |
| 1126 | UINT64_C(2769092608), // LLIHL |
| 1127 | UINT64_C(211170657042432), // LLILF |
| 1128 | UINT64_C(2769158144), // LLILH |
| 1129 | UINT64_C(2769223680), // LLILL |
| 1130 | UINT64_C(249589139505249), // LLXAB |
| 1131 | UINT64_C(249589139505253), // LLXAF |
| 1132 | UINT64_C(249589139505255), // LLXAG |
| 1133 | UINT64_C(249589139505251), // LLXAH |
| 1134 | UINT64_C(249589139505257), // LLXAQ |
| 1135 | UINT64_C(249589139505210), // LLZRGF |
| 1136 | UINT64_C(2550136832), // LM |
| 1137 | UINT64_C(262783279038464), // LMD |
| 1138 | UINT64_C(258385232527364), // LMG |
| 1139 | UINT64_C(258385232527510), // LMH |
| 1140 | UINT64_C(258385232527512), // LMY |
| 1141 | UINT64_C(3004235776), // LNDBR |
| 1142 | UINT64_C(3010527232), // LNDFR |
| 1143 | UINT64_C(3010527232), // LNDFR_16 |
| 1144 | UINT64_C(3010527232), // LNDFR_32 |
| 1145 | UINT64_C(8448), // LNDR |
| 1146 | UINT64_C(3003187200), // LNEBR |
| 1147 | UINT64_C(12544), // LNER |
| 1148 | UINT64_C(3104899072), // LNGFR |
| 1149 | UINT64_C(3103850496), // LNGR |
| 1150 | UINT64_C(4352), // LNR |
| 1151 | UINT64_C(3007381504), // LNXBR |
| 1152 | UINT64_C(3009478656), // LNXR |
| 1153 | UINT64_C(258385232527602), // LOC |
| 1154 | UINT64_C(258385232527602), // LOCAsm |
| 1155 | UINT64_C(258419592265970), // LOCAsmE |
| 1156 | UINT64_C(258393822462194), // LOCAsmH |
| 1157 | UINT64_C(258428182200562), // LOCAsmHE |
| 1158 | UINT64_C(258402412396786), // LOCAsmL |
| 1159 | UINT64_C(258436772135154), // LOCAsmLE |
| 1160 | UINT64_C(258411002331378), // LOCAsmLH |
| 1161 | UINT64_C(258402412396786), // LOCAsmM |
| 1162 | UINT64_C(258415297298674), // LOCAsmNE |
| 1163 | UINT64_C(258441067102450), // LOCAsmNH |
| 1164 | UINT64_C(258406707364082), // LOCAsmNHE |
| 1165 | UINT64_C(258432477167858), // LOCAsmNL |
| 1166 | UINT64_C(258398117429490), // LOCAsmNLE |
| 1167 | UINT64_C(258423887233266), // LOCAsmNLH |
| 1168 | UINT64_C(258432477167858), // LOCAsmNM |
| 1169 | UINT64_C(258445362069746), // LOCAsmNO |
| 1170 | UINT64_C(258441067102450), // LOCAsmNP |
| 1171 | UINT64_C(258415297298674), // LOCAsmNZ |
| 1172 | UINT64_C(258389527494898), // LOCAsmO |
| 1173 | UINT64_C(258393822462194), // LOCAsmP |
| 1174 | UINT64_C(258419592265970), // LOCAsmZ |
| 1175 | UINT64_C(258385232527584), // LOCFH |
| 1176 | UINT64_C(258385232527584), // LOCFHAsm |
| 1177 | UINT64_C(258419592265952), // LOCFHAsmE |
| 1178 | UINT64_C(258393822462176), // LOCFHAsmH |
| 1179 | UINT64_C(258428182200544), // LOCFHAsmHE |
| 1180 | UINT64_C(258402412396768), // LOCFHAsmL |
| 1181 | UINT64_C(258436772135136), // LOCFHAsmLE |
| 1182 | UINT64_C(258411002331360), // LOCFHAsmLH |
| 1183 | UINT64_C(258402412396768), // LOCFHAsmM |
| 1184 | UINT64_C(258415297298656), // LOCFHAsmNE |
| 1185 | UINT64_C(258441067102432), // LOCFHAsmNH |
| 1186 | UINT64_C(258406707364064), // LOCFHAsmNHE |
| 1187 | UINT64_C(258432477167840), // LOCFHAsmNL |
| 1188 | UINT64_C(258398117429472), // LOCFHAsmNLE |
| 1189 | UINT64_C(258423887233248), // LOCFHAsmNLH |
| 1190 | UINT64_C(258432477167840), // LOCFHAsmNM |
| 1191 | UINT64_C(258445362069728), // LOCFHAsmNO |
| 1192 | UINT64_C(258441067102432), // LOCFHAsmNP |
| 1193 | UINT64_C(258415297298656), // LOCFHAsmNZ |
| 1194 | UINT64_C(258389527494880), // LOCFHAsmO |
| 1195 | UINT64_C(258393822462176), // LOCFHAsmP |
| 1196 | UINT64_C(258419592265952), // LOCFHAsmZ |
| 1197 | UINT64_C(3118465024), // LOCFHR |
| 1198 | UINT64_C(3118465024), // LOCFHRAsm |
| 1199 | UINT64_C(3118497792), // LOCFHRAsmE |
| 1200 | UINT64_C(3118473216), // LOCFHRAsmH |
| 1201 | UINT64_C(3118505984), // LOCFHRAsmHE |
| 1202 | UINT64_C(3118481408), // LOCFHRAsmL |
| 1203 | UINT64_C(3118514176), // LOCFHRAsmLE |
| 1204 | UINT64_C(3118489600), // LOCFHRAsmLH |
| 1205 | UINT64_C(3118481408), // LOCFHRAsmM |
| 1206 | UINT64_C(3118493696), // LOCFHRAsmNE |
| 1207 | UINT64_C(3118518272), // LOCFHRAsmNH |
| 1208 | UINT64_C(3118485504), // LOCFHRAsmNHE |
| 1209 | UINT64_C(3118510080), // LOCFHRAsmNL |
| 1210 | UINT64_C(3118477312), // LOCFHRAsmNLE |
| 1211 | UINT64_C(3118501888), // LOCFHRAsmNLH |
| 1212 | UINT64_C(3118510080), // LOCFHRAsmNM |
| 1213 | UINT64_C(3118522368), // LOCFHRAsmNO |
| 1214 | UINT64_C(3118518272), // LOCFHRAsmNP |
| 1215 | UINT64_C(3118493696), // LOCFHRAsmNZ |
| 1216 | UINT64_C(3118469120), // LOCFHRAsmO |
| 1217 | UINT64_C(3118473216), // LOCFHRAsmP |
| 1218 | UINT64_C(3118497792), // LOCFHRAsmZ |
| 1219 | UINT64_C(258385232527586), // LOCG |
| 1220 | UINT64_C(258385232527586), // LOCGAsm |
| 1221 | UINT64_C(258419592265954), // LOCGAsmE |
| 1222 | UINT64_C(258393822462178), // LOCGAsmH |
| 1223 | UINT64_C(258428182200546), // LOCGAsmHE |
| 1224 | UINT64_C(258402412396770), // LOCGAsmL |
| 1225 | UINT64_C(258436772135138), // LOCGAsmLE |
| 1226 | UINT64_C(258411002331362), // LOCGAsmLH |
| 1227 | UINT64_C(258402412396770), // LOCGAsmM |
| 1228 | UINT64_C(258415297298658), // LOCGAsmNE |
| 1229 | UINT64_C(258441067102434), // LOCGAsmNH |
| 1230 | UINT64_C(258406707364066), // LOCGAsmNHE |
| 1231 | UINT64_C(258432477167842), // LOCGAsmNL |
| 1232 | UINT64_C(258398117429474), // LOCGAsmNLE |
| 1233 | UINT64_C(258423887233250), // LOCGAsmNLH |
| 1234 | UINT64_C(258432477167842), // LOCGAsmNM |
| 1235 | UINT64_C(258445362069730), // LOCGAsmNO |
| 1236 | UINT64_C(258441067102434), // LOCGAsmNP |
| 1237 | UINT64_C(258415297298658), // LOCGAsmNZ |
| 1238 | UINT64_C(258389527494882), // LOCGAsmO |
| 1239 | UINT64_C(258393822462178), // LOCGAsmP |
| 1240 | UINT64_C(258419592265954), // LOCGAsmZ |
| 1241 | UINT64_C(259484744155206), // LOCGHI |
| 1242 | UINT64_C(259484744155206), // LOCGHIAsm |
| 1243 | UINT64_C(259519103893574), // LOCGHIAsmE |
| 1244 | UINT64_C(259493334089798), // LOCGHIAsmH |
| 1245 | UINT64_C(259527693828166), // LOCGHIAsmHE |
| 1246 | UINT64_C(259501924024390), // LOCGHIAsmL |
| 1247 | UINT64_C(259536283762758), // LOCGHIAsmLE |
| 1248 | UINT64_C(259510513958982), // LOCGHIAsmLH |
| 1249 | UINT64_C(259501924024390), // LOCGHIAsmM |
| 1250 | UINT64_C(259514808926278), // LOCGHIAsmNE |
| 1251 | UINT64_C(259540578730054), // LOCGHIAsmNH |
| 1252 | UINT64_C(259506218991686), // LOCGHIAsmNHE |
| 1253 | UINT64_C(259531988795462), // LOCGHIAsmNL |
| 1254 | UINT64_C(259497629057094), // LOCGHIAsmNLE |
| 1255 | UINT64_C(259523398860870), // LOCGHIAsmNLH |
| 1256 | UINT64_C(259531988795462), // LOCGHIAsmNM |
| 1257 | UINT64_C(259544873697350), // LOCGHIAsmNO |
| 1258 | UINT64_C(259540578730054), // LOCGHIAsmNP |
| 1259 | UINT64_C(259514808926278), // LOCGHIAsmNZ |
| 1260 | UINT64_C(259489039122502), // LOCGHIAsmO |
| 1261 | UINT64_C(259493334089798), // LOCGHIAsmP |
| 1262 | UINT64_C(259519103893574), // LOCGHIAsmZ |
| 1263 | UINT64_C(3118596096), // LOCGR |
| 1264 | UINT64_C(3118596096), // LOCGRAsm |
| 1265 | UINT64_C(3118628864), // LOCGRAsmE |
| 1266 | UINT64_C(3118604288), // LOCGRAsmH |
| 1267 | UINT64_C(3118637056), // LOCGRAsmHE |
| 1268 | UINT64_C(3118612480), // LOCGRAsmL |
| 1269 | UINT64_C(3118645248), // LOCGRAsmLE |
| 1270 | UINT64_C(3118620672), // LOCGRAsmLH |
| 1271 | UINT64_C(3118612480), // LOCGRAsmM |
| 1272 | UINT64_C(3118624768), // LOCGRAsmNE |
| 1273 | UINT64_C(3118649344), // LOCGRAsmNH |
| 1274 | UINT64_C(3118616576), // LOCGRAsmNHE |
| 1275 | UINT64_C(3118641152), // LOCGRAsmNL |
| 1276 | UINT64_C(3118608384), // LOCGRAsmNLE |
| 1277 | UINT64_C(3118632960), // LOCGRAsmNLH |
| 1278 | UINT64_C(3118641152), // LOCGRAsmNM |
| 1279 | UINT64_C(3118653440), // LOCGRAsmNO |
| 1280 | UINT64_C(3118649344), // LOCGRAsmNP |
| 1281 | UINT64_C(3118624768), // LOCGRAsmNZ |
| 1282 | UINT64_C(3118600192), // LOCGRAsmO |
| 1283 | UINT64_C(3118604288), // LOCGRAsmP |
| 1284 | UINT64_C(3118628864), // LOCGRAsmZ |
| 1285 | UINT64_C(259484744155214), // LOCHHI |
| 1286 | UINT64_C(259484744155214), // LOCHHIAsm |
| 1287 | UINT64_C(259519103893582), // LOCHHIAsmE |
| 1288 | UINT64_C(259493334089806), // LOCHHIAsmH |
| 1289 | UINT64_C(259527693828174), // LOCHHIAsmHE |
| 1290 | UINT64_C(259501924024398), // LOCHHIAsmL |
| 1291 | UINT64_C(259536283762766), // LOCHHIAsmLE |
| 1292 | UINT64_C(259510513958990), // LOCHHIAsmLH |
| 1293 | UINT64_C(259501924024398), // LOCHHIAsmM |
| 1294 | UINT64_C(259514808926286), // LOCHHIAsmNE |
| 1295 | UINT64_C(259540578730062), // LOCHHIAsmNH |
| 1296 | UINT64_C(259506218991694), // LOCHHIAsmNHE |
| 1297 | UINT64_C(259531988795470), // LOCHHIAsmNL |
| 1298 | UINT64_C(259497629057102), // LOCHHIAsmNLE |
| 1299 | UINT64_C(259523398860878), // LOCHHIAsmNLH |
| 1300 | UINT64_C(259531988795470), // LOCHHIAsmNM |
| 1301 | UINT64_C(259544873697358), // LOCHHIAsmNO |
| 1302 | UINT64_C(259540578730062), // LOCHHIAsmNP |
| 1303 | UINT64_C(259514808926286), // LOCHHIAsmNZ |
| 1304 | UINT64_C(259489039122510), // LOCHHIAsmO |
| 1305 | UINT64_C(259493334089806), // LOCHHIAsmP |
| 1306 | UINT64_C(259519103893582), // LOCHHIAsmZ |
| 1307 | UINT64_C(259484744155202), // LOCHI |
| 1308 | UINT64_C(259484744155202), // LOCHIAsm |
| 1309 | UINT64_C(259519103893570), // LOCHIAsmE |
| 1310 | UINT64_C(259493334089794), // LOCHIAsmH |
| 1311 | UINT64_C(259527693828162), // LOCHIAsmHE |
| 1312 | UINT64_C(259501924024386), // LOCHIAsmL |
| 1313 | UINT64_C(259536283762754), // LOCHIAsmLE |
| 1314 | UINT64_C(259510513958978), // LOCHIAsmLH |
| 1315 | UINT64_C(259501924024386), // LOCHIAsmM |
| 1316 | UINT64_C(259514808926274), // LOCHIAsmNE |
| 1317 | UINT64_C(259540578730050), // LOCHIAsmNH |
| 1318 | UINT64_C(259506218991682), // LOCHIAsmNHE |
| 1319 | UINT64_C(259531988795458), // LOCHIAsmNL |
| 1320 | UINT64_C(259497629057090), // LOCHIAsmNLE |
| 1321 | UINT64_C(259523398860866), // LOCHIAsmNLH |
| 1322 | UINT64_C(259531988795458), // LOCHIAsmNM |
| 1323 | UINT64_C(259544873697346), // LOCHIAsmNO |
| 1324 | UINT64_C(259540578730050), // LOCHIAsmNP |
| 1325 | UINT64_C(259514808926274), // LOCHIAsmNZ |
| 1326 | UINT64_C(259489039122498), // LOCHIAsmO |
| 1327 | UINT64_C(259493334089794), // LOCHIAsmP |
| 1328 | UINT64_C(259519103893570), // LOCHIAsmZ |
| 1329 | UINT64_C(3119644672), // LOCR |
| 1330 | UINT64_C(3119644672), // LOCRAsm |
| 1331 | UINT64_C(3119677440), // LOCRAsmE |
| 1332 | UINT64_C(3119652864), // LOCRAsmH |
| 1333 | UINT64_C(3119685632), // LOCRAsmHE |
| 1334 | UINT64_C(3119661056), // LOCRAsmL |
| 1335 | UINT64_C(3119693824), // LOCRAsmLE |
| 1336 | UINT64_C(3119669248), // LOCRAsmLH |
| 1337 | UINT64_C(3119661056), // LOCRAsmM |
| 1338 | UINT64_C(3119673344), // LOCRAsmNE |
| 1339 | UINT64_C(3119697920), // LOCRAsmNH |
| 1340 | UINT64_C(3119665152), // LOCRAsmNHE |
| 1341 | UINT64_C(3119689728), // LOCRAsmNL |
| 1342 | UINT64_C(3119656960), // LOCRAsmNLE |
| 1343 | UINT64_C(3119681536), // LOCRAsmNLH |
| 1344 | UINT64_C(3119689728), // LOCRAsmNM |
| 1345 | UINT64_C(3119702016), // LOCRAsmNO |
| 1346 | UINT64_C(3119697920), // LOCRAsmNP |
| 1347 | UINT64_C(3119673344), // LOCRAsmNZ |
| 1348 | UINT64_C(3119648768), // LOCRAsmO |
| 1349 | UINT64_C(3119652864), // LOCRAsmP |
| 1350 | UINT64_C(3119677440), // LOCRAsmZ |
| 1351 | UINT64_C(2995060736), // LPCTL |
| 1352 | UINT64_C(219919505424384), // LPD |
| 1353 | UINT64_C(3004170240), // LPDBR |
| 1354 | UINT64_C(3010461696), // LPDFR |
| 1355 | UINT64_C(3010461696), // LPDFR_16 |
| 1356 | UINT64_C(3010461696), // LPDFR_32 |
| 1357 | UINT64_C(219923800391680), // LPDG |
| 1358 | UINT64_C(8192), // LPDR |
| 1359 | UINT64_C(3003121664), // LPEBR |
| 1360 | UINT64_C(12288), // LPER |
| 1361 | UINT64_C(3104833536), // LPGFR |
| 1362 | UINT64_C(3103784960), // LPGR |
| 1363 | UINT64_C(2994733056), // LPP |
| 1364 | UINT64_C(249589139505295), // LPQ |
| 1365 | UINT64_C(4096), // LPR |
| 1366 | UINT64_C(2181038080), // LPSW |
| 1367 | UINT64_C(2998009856), // LPSWE |
| 1368 | UINT64_C(258385232527473), // LPSWEY |
| 1369 | UINT64_C(3114926080), // LPTEA |
| 1370 | UINT64_C(3007315968), // LPXBR |
| 1371 | UINT64_C(3009413120), // LPXR |
| 1372 | UINT64_C(6144), // LR |
| 1373 | UINT64_C(2969567232), // LRA |
| 1374 | UINT64_C(249589139505155), // LRAG |
| 1375 | UINT64_C(249589139505171), // LRAY |
| 1376 | UINT64_C(9472), // LRDR |
| 1377 | UINT64_C(13568), // LRER |
| 1378 | UINT64_C(215560113618944), // LRL |
| 1379 | UINT64_C(249589139505182), // LRV |
| 1380 | UINT64_C(249589139505167), // LRVG |
| 1381 | UINT64_C(3104768000), // LRVGR |
| 1382 | UINT64_C(249589139505183), // LRVH |
| 1383 | UINT64_C(3105816576), // LRVR |
| 1384 | UINT64_C(2995191808), // LSCTL |
| 1385 | UINT64_C(249589139505170), // LT |
| 1386 | UINT64_C(3004301312), // LTDBR |
| 1387 | UINT64_C(8704), // LTDR |
| 1388 | UINT64_C(3017146368), // LTDTR |
| 1389 | UINT64_C(3003252736), // LTEBR |
| 1390 | UINT64_C(12800), // LTER |
| 1391 | UINT64_C(249589139505154), // LTG |
| 1392 | UINT64_C(249589139505202), // LTGF |
| 1393 | UINT64_C(3104964608), // LTGFR |
| 1394 | UINT64_C(3103916032), // LTGR |
| 1395 | UINT64_C(4608), // LTR |
| 1396 | UINT64_C(3007447040), // LTXBR |
| 1397 | UINT64_C(3009544192), // LTXR |
| 1398 | UINT64_C(3017670656), // LTXTR |
| 1399 | UINT64_C(2991259648), // LURA |
| 1400 | UINT64_C(3104112640), // LURAG |
| 1401 | UINT64_C(249589139505248), // LXAB |
| 1402 | UINT64_C(249589139505252), // LXAF |
| 1403 | UINT64_C(249589139505254), // LXAG |
| 1404 | UINT64_C(249589139505250), // LXAH |
| 1405 | UINT64_C(249589139505256), // LXAQ |
| 1406 | UINT64_C(260584255782949), // LXD |
| 1407 | UINT64_C(260584255782917), // LXDB |
| 1408 | UINT64_C(3003449344), // LXDBR |
| 1409 | UINT64_C(3005546496), // LXDR |
| 1410 | UINT64_C(3017539584), // LXDTR |
| 1411 | UINT64_C(260584255782950), // LXE |
| 1412 | UINT64_C(260584255782918), // LXEB |
| 1413 | UINT64_C(3003514880), // LXEBR |
| 1414 | UINT64_C(3005612032), // LXER |
| 1415 | UINT64_C(3009740800), // LXR |
| 1416 | UINT64_C(249589139505240), // LY |
| 1417 | UINT64_C(3010789376), // LZDR |
| 1418 | UINT64_C(3010723840), // LZER |
| 1419 | UINT64_C(3010723840), // LZER_16 |
| 1420 | UINT64_C(249589139505211), // LZRF |
| 1421 | UINT64_C(249589139505194), // LZRG |
| 1422 | UINT64_C(3010854912), // LZXR |
| 1423 | UINT64_C(1543503872), // M |
| 1424 | UINT64_C(260584255782974), // MAD |
| 1425 | UINT64_C(260584255782942), // MADB |
| 1426 | UINT64_C(3005087744), // MADBR |
| 1427 | UINT64_C(3007184896), // MADR |
| 1428 | UINT64_C(260584255782958), // MAE |
| 1429 | UINT64_C(260584255782926), // MAEB |
| 1430 | UINT64_C(3004039168), // MAEBR |
| 1431 | UINT64_C(3006136320), // MAER |
| 1432 | UINT64_C(260584255782970), // MAY |
| 1433 | UINT64_C(260584255782972), // MAYH |
| 1434 | UINT64_C(3007053824), // MAYHR |
| 1435 | UINT64_C(260584255782968), // MAYL |
| 1436 | UINT64_C(3006791680), // MAYLR |
| 1437 | UINT64_C(3006922752), // MAYR |
| 1438 | UINT64_C(2936012800), // MC |
| 1439 | UINT64_C(1811939328), // MD |
| 1440 | UINT64_C(260584255782940), // MDB |
| 1441 | UINT64_C(3004956672), // MDBR |
| 1442 | UINT64_C(2080374784), // MDE |
| 1443 | UINT64_C(260584255782924), // MDEB |
| 1444 | UINT64_C(3003908096), // MDEBR |
| 1445 | UINT64_C(15360), // MDER |
| 1446 | UINT64_C(11264), // MDR |
| 1447 | UINT64_C(3016753152), // MDTR |
| 1448 | UINT64_C(3016753152), // MDTRA |
| 1449 | UINT64_C(2080374784), // ME |
| 1450 | UINT64_C(260584255782967), // MEE |
| 1451 | UINT64_C(260584255782935), // MEEB |
| 1452 | UINT64_C(3004628992), // MEEBR |
| 1453 | UINT64_C(3006726144), // MEER |
| 1454 | UINT64_C(15360), // MER |
| 1455 | UINT64_C(249589139505244), // MFY |
| 1456 | UINT64_C(249589139505284), // MG |
| 1457 | UINT64_C(249589139505212), // MGH |
| 1458 | UINT64_C(2802647040), // MGHI |
| 1459 | UINT64_C(3119251456), // MGRK |
| 1460 | UINT64_C(1275068416), // MH |
| 1461 | UINT64_C(2802581504), // MHI |
| 1462 | UINT64_C(249589139505276), // MHY |
| 1463 | UINT64_C(249589139505302), // ML |
| 1464 | UINT64_C(249589139505286), // MLG |
| 1465 | UINT64_C(3112566784), // MLGR |
| 1466 | UINT64_C(3113615360), // MLR |
| 1467 | UINT64_C(277076930199552), // MP |
| 1468 | UINT64_C(7168), // MR |
| 1469 | UINT64_C(1895825408), // MS |
| 1470 | UINT64_C(249589139505235), // MSC |
| 1471 | UINT64_C(2989621248), // MSCH |
| 1472 | UINT64_C(260584255782975), // MSD |
| 1473 | UINT64_C(260584255782943), // MSDB |
| 1474 | UINT64_C(3005153280), // MSDBR |
| 1475 | UINT64_C(3007250432), // MSDR |
| 1476 | UINT64_C(260584255782959), // MSE |
| 1477 | UINT64_C(260584255782927), // MSEB |
| 1478 | UINT64_C(3004104704), // MSEBR |
| 1479 | UINT64_C(3006201856), // MSER |
| 1480 | UINT64_C(213309550755840), // MSFI |
| 1481 | UINT64_C(249589139505164), // MSG |
| 1482 | UINT64_C(249589139505283), // MSGC |
| 1483 | UINT64_C(249589139505180), // MSGF |
| 1484 | UINT64_C(213305255788544), // MSGFI |
| 1485 | UINT64_C(3105619968), // MSGFR |
| 1486 | UINT64_C(3104571392), // MSGR |
| 1487 | UINT64_C(3119316992), // MSGRKC |
| 1488 | UINT64_C(2991718400), // MSR |
| 1489 | UINT64_C(3120365568), // MSRKC |
| 1490 | UINT64_C(2990997504), // MSTA |
| 1491 | UINT64_C(249589139505233), // MSY |
| 1492 | UINT64_C(230897441832960), // MVC |
| 1493 | UINT64_C(251852587270144), // MVCDK |
| 1494 | UINT64_C(255086697644032), // MVCIN |
| 1495 | UINT64_C(238594023227392), // MVCK |
| 1496 | UINT64_C(3584), // MVCL |
| 1497 | UINT64_C(2818572288), // MVCLE |
| 1498 | UINT64_C(258385232527502), // MVCLU |
| 1499 | UINT64_C(219902325555200), // MVCOS |
| 1500 | UINT64_C(239693534855168), // MVCP |
| 1501 | UINT64_C(251831112433664), // MVCRL |
| 1502 | UINT64_C(240793046482944), // MVCS |
| 1503 | UINT64_C(251848292302848), // MVCSK |
| 1504 | UINT64_C(252097400406016), // MVGHI |
| 1505 | UINT64_C(252080220536832), // MVHHI |
| 1506 | UINT64_C(252114580275200), // MVHI |
| 1507 | UINT64_C(2449473536), // MVI |
| 1508 | UINT64_C(258385232527442), // MVIY |
| 1509 | UINT64_C(229797930205184), // MVN |
| 1510 | UINT64_C(264982302294016), // MVO |
| 1511 | UINT64_C(2991849472), // MVPG |
| 1512 | UINT64_C(2991915008), // MVST |
| 1513 | UINT64_C(231996953460736), // MVZ |
| 1514 | UINT64_C(3008102400), // MXBR |
| 1515 | UINT64_C(1728053248), // MXD |
| 1516 | UINT64_C(260584255782919), // MXDB |
| 1517 | UINT64_C(3003580416), // MXDBR |
| 1518 | UINT64_C(9984), // MXDR |
| 1519 | UINT64_C(9728), // MXR |
| 1520 | UINT64_C(3017277440), // MXTR |
| 1521 | UINT64_C(3017277440), // MXTRA |
| 1522 | UINT64_C(260584255782971), // MY |
| 1523 | UINT64_C(260584255782973), // MYH |
| 1524 | UINT64_C(3007119360), // MYHR |
| 1525 | UINT64_C(260584255782969), // MYL |
| 1526 | UINT64_C(3006857216), // MYLR |
| 1527 | UINT64_C(3006988288), // MYR |
| 1528 | UINT64_C(1409286144), // N |
| 1529 | UINT64_C(233096465088512), // NC |
| 1530 | UINT64_C(3118792704), // NCGRK |
| 1531 | UINT64_C(3119841280), // NCRK |
| 1532 | UINT64_C(249589139505280), // NG |
| 1533 | UINT64_C(3112173568), // NGR |
| 1534 | UINT64_C(3118727168), // NGRK |
| 1535 | UINT64_C(2483027968), // NI |
| 1536 | UINT64_C(3002728448), // NIAI |
| 1537 | UINT64_C(211149182205952), // NIHF |
| 1538 | UINT64_C(2768502784), // NIHH |
| 1539 | UINT64_C(2768568320), // NIHL |
| 1540 | UINT64_C(211153477173248), // NILF |
| 1541 | UINT64_C(2768633856), // NILH |
| 1542 | UINT64_C(2768699392), // NILL |
| 1543 | UINT64_C(258385232527444), // NIY |
| 1544 | UINT64_C(3110338560), // NNGRK |
| 1545 | UINT64_C(3107651584), // NNPA |
| 1546 | UINT64_C(3111387136), // NNRK |
| 1547 | UINT64_C(3110469632), // NOGRK |
| 1548 | UINT64_C(1191182336), // NOP |
| 1549 | UINT64_C(1191182336), // NOPOpt |
| 1550 | UINT64_C(1792), // NOPR |
| 1551 | UINT64_C(1792), // NOPROpt |
| 1552 | UINT64_C(3111518208), // NORK |
| 1553 | UINT64_C(3110469632), // NOTGR |
| 1554 | UINT64_C(3111518208), // NOTR |
| 1555 | UINT64_C(5120), // NR |
| 1556 | UINT64_C(3119775744), // NRK |
| 1557 | UINT64_C(249589139505189), // NTSTG |
| 1558 | UINT64_C(3110535168), // NXGRK |
| 1559 | UINT64_C(3111583744), // NXRK |
| 1560 | UINT64_C(249589139505236), // NY |
| 1561 | UINT64_C(1442840576), // O |
| 1562 | UINT64_C(235295488344064), // OC |
| 1563 | UINT64_C(3110404096), // OCGRK |
| 1564 | UINT64_C(3111452672), // OCRK |
| 1565 | UINT64_C(249589139505281), // OG |
| 1566 | UINT64_C(3112239104), // OGR |
| 1567 | UINT64_C(3118858240), // OGRK |
| 1568 | UINT64_C(2516582400), // OI |
| 1569 | UINT64_C(211157772140544), // OIHF |
| 1570 | UINT64_C(2768764928), // OIHH |
| 1571 | UINT64_C(2768830464), // OIHL |
| 1572 | UINT64_C(211162067107840), // OILF |
| 1573 | UINT64_C(2768896000), // OILH |
| 1574 | UINT64_C(2768961536), // OILL |
| 1575 | UINT64_C(258385232527446), // OIY |
| 1576 | UINT64_C(5632), // OR |
| 1577 | UINT64_C(3119906816), // ORK |
| 1578 | UINT64_C(249589139505238), // OY |
| 1579 | UINT64_C(266081813921792), // PACK |
| 1580 | UINT64_C(2991063040), // PALB |
| 1581 | UINT64_C(2987917312), // PC |
| 1582 | UINT64_C(3106668544), // PCC |
| 1583 | UINT64_C(3106406400), // PCKMO |
| 1584 | UINT64_C(258385232527382), // PFCR |
| 1585 | UINT64_C(249589139505206), // PFD |
| 1586 | UINT64_C(217711892234240), // PFDRL |
| 1587 | UINT64_C(3115253760), // PFMF |
| 1588 | UINT64_C(266), // PFPO |
| 1589 | UINT64_C(2989359104), // PGIN |
| 1590 | UINT64_C(2989424640), // PGOUT |
| 1591 | UINT64_C(256186209271808), // PKA |
| 1592 | UINT64_C(247390116249600), // PKU |
| 1593 | UINT64_C(261683767410688), // PLO |
| 1594 | UINT64_C(3118530560), // POPCNT |
| 1595 | UINT64_C(3118530560), // POPCNTOpt |
| 1596 | UINT64_C(3001548800), // PPA |
| 1597 | UINT64_C(3107717120), // PPNO |
| 1598 | UINT64_C(257), // PR |
| 1599 | UINT64_C(3107717120), // PRNO |
| 1600 | UINT64_C(2988965888), // PT |
| 1601 | UINT64_C(3114401792), // PTF |
| 1602 | UINT64_C(260), // PTFF |
| 1603 | UINT64_C(3114139648), // PTI |
| 1604 | UINT64_C(2987196416), // PTLB |
| 1605 | UINT64_C(3019177984), // QADTR |
| 1606 | UINT64_C(3019702272), // QAXTR |
| 1607 | UINT64_C(2995650560), // QCTRI |
| 1608 | UINT64_C(2995716096), // QPACI |
| 1609 | UINT64_C(2995126272), // QSI |
| 1610 | UINT64_C(2990211072), // RCHP |
| 1611 | UINT64_C(3112894464), // RDP |
| 1612 | UINT64_C(3112894464), // RDPOpt |
| 1613 | UINT64_C(259484744155221), // RISBG |
| 1614 | UINT64_C(259484744155221), // RISBG32 |
| 1615 | UINT64_C(259484744155221), // RISBG32Opt |
| 1616 | UINT64_C(259484744155225), // RISBGN |
| 1617 | UINT64_C(259484744155225), // RISBGNOpt |
| 1618 | UINT64_C(259484752543833), // RISBGNZ |
| 1619 | UINT64_C(259484752543833), // RISBGNZOpt |
| 1620 | UINT64_C(259484744155221), // RISBGOpt |
| 1621 | UINT64_C(259484752543829), // RISBGZ |
| 1622 | UINT64_C(259484752543829), // RISBGZOpt |
| 1623 | UINT64_C(259484744155229), // RISBHG |
| 1624 | UINT64_C(259484744155229), // RISBHGOpt |
| 1625 | UINT64_C(259484744155217), // RISBLG |
| 1626 | UINT64_C(259484744155217), // RISBLGOpt |
| 1627 | UINT64_C(258385232527389), // RLL |
| 1628 | UINT64_C(258385232527388), // RLLG |
| 1629 | UINT64_C(259484744155220), // RNSBG |
| 1630 | UINT64_C(259484744155220), // RNSBGOpt |
| 1631 | UINT64_C(259484744155222), // ROSBG |
| 1632 | UINT64_C(259484744155222), // ROSBGOpt |
| 1633 | UINT64_C(2994143232), // RP |
| 1634 | UINT64_C(2989096960), // RRBE |
| 1635 | UINT64_C(3115188224), // RRBM |
| 1636 | UINT64_C(3019309056), // RRDTR |
| 1637 | UINT64_C(3019833344), // RRXTR |
| 1638 | UINT64_C(2990014464), // RSCH |
| 1639 | UINT64_C(259484744155223), // RXSBG |
| 1640 | UINT64_C(259484744155223), // RXSBGOpt |
| 1641 | UINT64_C(1526726656), // S |
| 1642 | UINT64_C(2987982848), // SAC |
| 1643 | UINT64_C(2994274304), // SACF |
| 1644 | UINT64_C(2989948928), // SAL |
| 1645 | UINT64_C(268), // SAM24 |
| 1646 | UINT64_C(269), // SAM31 |
| 1647 | UINT64_C(270), // SAM64 |
| 1648 | UINT64_C(2991456256), // SAR |
| 1649 | UINT64_C(3001024512), // SCCTR |
| 1650 | UINT64_C(2990276608), // SCHM |
| 1651 | UINT64_C(2986606592), // SCK |
| 1652 | UINT64_C(2986737664), // SCKC |
| 1653 | UINT64_C(263), // SCKPF |
| 1654 | UINT64_C(1795162112), // SD |
| 1655 | UINT64_C(260584255782939), // SDB |
| 1656 | UINT64_C(3004891136), // SDBR |
| 1657 | UINT64_C(11008), // SDR |
| 1658 | UINT64_C(3016949760), // SDTR |
| 1659 | UINT64_C(3016949760), // SDTRA |
| 1660 | UINT64_C(2063597568), // SE |
| 1661 | UINT64_C(260584255782923), // SEB |
| 1662 | UINT64_C(3003842560), // SEBR |
| 1663 | UINT64_C(3116367872), // SELFHR |
| 1664 | UINT64_C(3116367872), // SELFHRAsm |
| 1665 | UINT64_C(3116369920), // SELFHRAsmE |
| 1666 | UINT64_C(3116368384), // SELFHRAsmH |
| 1667 | UINT64_C(3116370432), // SELFHRAsmHE |
| 1668 | UINT64_C(3116368896), // SELFHRAsmL |
| 1669 | UINT64_C(3116370944), // SELFHRAsmLE |
| 1670 | UINT64_C(3116369408), // SELFHRAsmLH |
| 1671 | UINT64_C(3116368896), // SELFHRAsmM |
| 1672 | UINT64_C(3116369664), // SELFHRAsmNE |
| 1673 | UINT64_C(3116371200), // SELFHRAsmNH |
| 1674 | UINT64_C(3116369152), // SELFHRAsmNHE |
| 1675 | UINT64_C(3116370688), // SELFHRAsmNL |
| 1676 | UINT64_C(3116368640), // SELFHRAsmNLE |
| 1677 | UINT64_C(3116370176), // SELFHRAsmNLH |
| 1678 | UINT64_C(3116370688), // SELFHRAsmNM |
| 1679 | UINT64_C(3116371456), // SELFHRAsmNO |
| 1680 | UINT64_C(3116371200), // SELFHRAsmNP |
| 1681 | UINT64_C(3116369664), // SELFHRAsmNZ |
| 1682 | UINT64_C(3116368128), // SELFHRAsmO |
| 1683 | UINT64_C(3116368384), // SELFHRAsmP |
| 1684 | UINT64_C(3116369920), // SELFHRAsmZ |
| 1685 | UINT64_C(3118661632), // SELGR |
| 1686 | UINT64_C(3118661632), // SELGRAsm |
| 1687 | UINT64_C(3118663680), // SELGRAsmE |
| 1688 | UINT64_C(3118662144), // SELGRAsmH |
| 1689 | UINT64_C(3118664192), // SELGRAsmHE |
| 1690 | UINT64_C(3118662656), // SELGRAsmL |
| 1691 | UINT64_C(3118664704), // SELGRAsmLE |
| 1692 | UINT64_C(3118663168), // SELGRAsmLH |
| 1693 | UINT64_C(3118662656), // SELGRAsmM |
| 1694 | UINT64_C(3118663424), // SELGRAsmNE |
| 1695 | UINT64_C(3118664960), // SELGRAsmNH |
| 1696 | UINT64_C(3118662912), // SELGRAsmNHE |
| 1697 | UINT64_C(3118664448), // SELGRAsmNL |
| 1698 | UINT64_C(3118662400), // SELGRAsmNLE |
| 1699 | UINT64_C(3118663936), // SELGRAsmNLH |
| 1700 | UINT64_C(3118664448), // SELGRAsmNM |
| 1701 | UINT64_C(3118665216), // SELGRAsmNO |
| 1702 | UINT64_C(3118664960), // SELGRAsmNP |
| 1703 | UINT64_C(3118663424), // SELGRAsmNZ |
| 1704 | UINT64_C(3118661888), // SELGRAsmO |
| 1705 | UINT64_C(3118662144), // SELGRAsmP |
| 1706 | UINT64_C(3118663680), // SELGRAsmZ |
| 1707 | UINT64_C(3119513600), // SELR |
| 1708 | UINT64_C(3119513600), // SELRAsm |
| 1709 | UINT64_C(3119515648), // SELRAsmE |
| 1710 | UINT64_C(3119514112), // SELRAsmH |
| 1711 | UINT64_C(3119516160), // SELRAsmHE |
| 1712 | UINT64_C(3119514624), // SELRAsmL |
| 1713 | UINT64_C(3119516672), // SELRAsmLE |
| 1714 | UINT64_C(3119515136), // SELRAsmLH |
| 1715 | UINT64_C(3119514624), // SELRAsmM |
| 1716 | UINT64_C(3119515392), // SELRAsmNE |
| 1717 | UINT64_C(3119516928), // SELRAsmNH |
| 1718 | UINT64_C(3119514880), // SELRAsmNHE |
| 1719 | UINT64_C(3119516416), // SELRAsmNL |
| 1720 | UINT64_C(3119514368), // SELRAsmNLE |
| 1721 | UINT64_C(3119515904), // SELRAsmNLH |
| 1722 | UINT64_C(3119516416), // SELRAsmNM |
| 1723 | UINT64_C(3119517184), // SELRAsmNO |
| 1724 | UINT64_C(3119516928), // SELRAsmNP |
| 1725 | UINT64_C(3119515392), // SELRAsmNZ |
| 1726 | UINT64_C(3119513856), // SELRAsmO |
| 1727 | UINT64_C(3119514112), // SELRAsmP |
| 1728 | UINT64_C(3119515648), // SELRAsmZ |
| 1729 | UINT64_C(15104), // SER |
| 1730 | UINT64_C(3011837952), // SFASR |
| 1731 | UINT64_C(3011772416), // SFPC |
| 1732 | UINT64_C(249589139505161), // SG |
| 1733 | UINT64_C(249589139505177), // SGF |
| 1734 | UINT64_C(3105423360), // SGFR |
| 1735 | UINT64_C(249589139505209), // SGH |
| 1736 | UINT64_C(3104374784), // SGR |
| 1737 | UINT64_C(3119054848), // SGRK |
| 1738 | UINT64_C(1258291200), // SH |
| 1739 | UINT64_C(3116957696), // SHHHR |
| 1740 | UINT64_C(3118006272), // SHHLR |
| 1741 | UINT64_C(249589139505275), // SHY |
| 1742 | UINT64_C(2987655168), // SIE |
| 1743 | UINT64_C(2993946624), // SIGA |
| 1744 | UINT64_C(2919235584), // SIGP |
| 1745 | UINT64_C(1593835520), // SL |
| 1746 | UINT64_C(2332033024), // SLA |
| 1747 | UINT64_C(258385232527371), // SLAG |
| 1748 | UINT64_C(258385232527581), // SLAK |
| 1749 | UINT64_C(249589139505305), // SLB |
| 1750 | UINT64_C(249589139505289), // SLBG |
| 1751 | UINT64_C(3112763392), // SLBGR |
| 1752 | UINT64_C(3113811968), // SLBR |
| 1753 | UINT64_C(2399141888), // SLDA |
| 1754 | UINT64_C(2365587456), // SLDL |
| 1755 | UINT64_C(260584255782976), // SLDT |
| 1756 | UINT64_C(213326730625024), // SLFI |
| 1757 | UINT64_C(249589139505163), // SLG |
| 1758 | UINT64_C(249589139505179), // SLGF |
| 1759 | UINT64_C(213322435657728), // SLGFI |
| 1760 | UINT64_C(3105554432), // SLGFR |
| 1761 | UINT64_C(3104505856), // SLGR |
| 1762 | UINT64_C(3119185920), // SLGRK |
| 1763 | UINT64_C(3117088768), // SLHHHR |
| 1764 | UINT64_C(3118137344), // SLHHLR |
| 1765 | UINT64_C(2298478592), // SLL |
| 1766 | UINT64_C(258385232527373), // SLLG |
| 1767 | UINT64_C(258385232527583), // SLLK |
| 1768 | UINT64_C(7936), // SLR |
| 1769 | UINT64_C(3120234496), // SLRK |
| 1770 | UINT64_C(260584255782984), // SLXT |
| 1771 | UINT64_C(249589139505247), // SLY |
| 1772 | UINT64_C(3107454976), // SORTL |
| 1773 | UINT64_C(275977418571776), // SP |
| 1774 | UINT64_C(3001090048), // SPCTR |
| 1775 | UINT64_C(2986999808), // SPKA |
| 1776 | UINT64_C(1024), // SPM |
| 1777 | UINT64_C(2986868736), // SPT |
| 1778 | UINT64_C(2987393024), // SPX |
| 1779 | UINT64_C(260584255782965), // SQD |
| 1780 | UINT64_C(260584255782933), // SQDB |
| 1781 | UINT64_C(3004497920), // SQDBR |
| 1782 | UINT64_C(2990800896), // SQDR |
| 1783 | UINT64_C(260584255782964), // SQE |
| 1784 | UINT64_C(260584255782932), // SQEB |
| 1785 | UINT64_C(3004432384), // SQEBR |
| 1786 | UINT64_C(2990866432), // SQER |
| 1787 | UINT64_C(3004563456), // SQXBR |
| 1788 | UINT64_C(3006660608), // SQXR |
| 1789 | UINT64_C(6912), // SR |
| 1790 | UINT64_C(2315255808), // SRA |
| 1791 | UINT64_C(258385232527370), // SRAG |
| 1792 | UINT64_C(258385232527580), // SRAK |
| 1793 | UINT64_C(2382364672), // SRDA |
| 1794 | UINT64_C(2348810240), // SRDL |
| 1795 | UINT64_C(260584255782977), // SRDT |
| 1796 | UINT64_C(3120103424), // SRK |
| 1797 | UINT64_C(2281701376), // SRL |
| 1798 | UINT64_C(258385232527372), // SRLG |
| 1799 | UINT64_C(258385232527582), // SRLK |
| 1800 | UINT64_C(2996371456), // SRNM |
| 1801 | UINT64_C(2998403072), // SRNMB |
| 1802 | UINT64_C(2998468608), // SRNMT |
| 1803 | UINT64_C(263882790666240), // SRP |
| 1804 | UINT64_C(2992504832), // SRST |
| 1805 | UINT64_C(3116236800), // SRSTU |
| 1806 | UINT64_C(260584255782985), // SRXT |
| 1807 | UINT64_C(3114205184), // SSAIR |
| 1808 | UINT64_C(2988769280), // SSAR |
| 1809 | UINT64_C(2989686784), // SSCH |
| 1810 | UINT64_C(2989162496), // SSKE |
| 1811 | UINT64_C(2989162496), // SSKEOpt |
| 1812 | UINT64_C(2147483648), // SSM |
| 1813 | UINT64_C(1342177280), // ST |
| 1814 | UINT64_C(2600468480), // STAM |
| 1815 | UINT64_C(258385232527515), // STAMY |
| 1816 | UINT64_C(2987524096), // STAP |
| 1817 | UINT64_C(2986409984), // STBEAR |
| 1818 | UINT64_C(1107296256), // STC |
| 1819 | UINT64_C(249589139505347), // STCH |
| 1820 | UINT64_C(2986672128), // STCK |
| 1821 | UINT64_C(2986803200), // STCKC |
| 1822 | UINT64_C(2994208768), // STCKE |
| 1823 | UINT64_C(2994470912), // STCKF |
| 1824 | UINT64_C(3187671040), // STCM |
| 1825 | UINT64_C(258385232527404), // STCMH |
| 1826 | UINT64_C(258385232527405), // STCMY |
| 1827 | UINT64_C(2990145536), // STCPS |
| 1828 | UINT64_C(2990080000), // STCRW |
| 1829 | UINT64_C(258385232527397), // STCTG |
| 1830 | UINT64_C(3053453312), // STCTL |
| 1831 | UINT64_C(249589139505266), // STCY |
| 1832 | UINT64_C(1610612736), // STD |
| 1833 | UINT64_C(260584255783015), // STDY |
| 1834 | UINT64_C(1879048192), // STE |
| 1835 | UINT64_C(1879048192), // STE16 |
| 1836 | UINT64_C(260584255783014), // STE16Y |
| 1837 | UINT64_C(260584255783014), // STEY |
| 1838 | UINT64_C(249589139505355), // STFH |
| 1839 | UINT64_C(2997944320), // STFL |
| 1840 | UINT64_C(2997878784), // STFLE |
| 1841 | UINT64_C(2996568064), // STFPC |
| 1842 | UINT64_C(249589139505188), // STG |
| 1843 | UINT64_C(215551523684352), // STGRL |
| 1844 | UINT64_C(249589139505225), // STGSC |
| 1845 | UINT64_C(1073741824), // STH |
| 1846 | UINT64_C(249589139505351), // STHH |
| 1847 | UINT64_C(215534343815168), // STHRL |
| 1848 | UINT64_C(249589139505264), // STHY |
| 1849 | UINT64_C(2986475520), // STIDP |
| 1850 | UINT64_C(2415919104), // STM |
| 1851 | UINT64_C(258385232527396), // STMG |
| 1852 | UINT64_C(258385232527398), // STMH |
| 1853 | UINT64_C(258385232527504), // STMY |
| 1854 | UINT64_C(2885681152), // STNSM |
| 1855 | UINT64_C(258385232527603), // STOC |
| 1856 | UINT64_C(258385232527603), // STOCAsm |
| 1857 | UINT64_C(258419592265971), // STOCAsmE |
| 1858 | UINT64_C(258393822462195), // STOCAsmH |
| 1859 | UINT64_C(258428182200563), // STOCAsmHE |
| 1860 | UINT64_C(258402412396787), // STOCAsmL |
| 1861 | UINT64_C(258436772135155), // STOCAsmLE |
| 1862 | UINT64_C(258411002331379), // STOCAsmLH |
| 1863 | UINT64_C(258402412396787), // STOCAsmM |
| 1864 | UINT64_C(258415297298675), // STOCAsmNE |
| 1865 | UINT64_C(258441067102451), // STOCAsmNH |
| 1866 | UINT64_C(258406707364083), // STOCAsmNHE |
| 1867 | UINT64_C(258432477167859), // STOCAsmNL |
| 1868 | UINT64_C(258398117429491), // STOCAsmNLE |
| 1869 | UINT64_C(258423887233267), // STOCAsmNLH |
| 1870 | UINT64_C(258432477167859), // STOCAsmNM |
| 1871 | UINT64_C(258445362069747), // STOCAsmNO |
| 1872 | UINT64_C(258441067102451), // STOCAsmNP |
| 1873 | UINT64_C(258415297298675), // STOCAsmNZ |
| 1874 | UINT64_C(258389527494899), // STOCAsmO |
| 1875 | UINT64_C(258393822462195), // STOCAsmP |
| 1876 | UINT64_C(258419592265971), // STOCAsmZ |
| 1877 | UINT64_C(258385232527585), // STOCFH |
| 1878 | UINT64_C(258385232527585), // STOCFHAsm |
| 1879 | UINT64_C(258419592265953), // STOCFHAsmE |
| 1880 | UINT64_C(258393822462177), // STOCFHAsmH |
| 1881 | UINT64_C(258428182200545), // STOCFHAsmHE |
| 1882 | UINT64_C(258402412396769), // STOCFHAsmL |
| 1883 | UINT64_C(258436772135137), // STOCFHAsmLE |
| 1884 | UINT64_C(258411002331361), // STOCFHAsmLH |
| 1885 | UINT64_C(258402412396769), // STOCFHAsmM |
| 1886 | UINT64_C(258415297298657), // STOCFHAsmNE |
| 1887 | UINT64_C(258441067102433), // STOCFHAsmNH |
| 1888 | UINT64_C(258406707364065), // STOCFHAsmNHE |
| 1889 | UINT64_C(258432477167841), // STOCFHAsmNL |
| 1890 | UINT64_C(258398117429473), // STOCFHAsmNLE |
| 1891 | UINT64_C(258423887233249), // STOCFHAsmNLH |
| 1892 | UINT64_C(258432477167841), // STOCFHAsmNM |
| 1893 | UINT64_C(258445362069729), // STOCFHAsmNO |
| 1894 | UINT64_C(258441067102433), // STOCFHAsmNP |
| 1895 | UINT64_C(258415297298657), // STOCFHAsmNZ |
| 1896 | UINT64_C(258389527494881), // STOCFHAsmO |
| 1897 | UINT64_C(258393822462177), // STOCFHAsmP |
| 1898 | UINT64_C(258419592265953), // STOCFHAsmZ |
| 1899 | UINT64_C(258385232527587), // STOCG |
| 1900 | UINT64_C(258385232527587), // STOCGAsm |
| 1901 | UINT64_C(258419592265955), // STOCGAsmE |
| 1902 | UINT64_C(258393822462179), // STOCGAsmH |
| 1903 | UINT64_C(258428182200547), // STOCGAsmHE |
| 1904 | UINT64_C(258402412396771), // STOCGAsmL |
| 1905 | UINT64_C(258436772135139), // STOCGAsmLE |
| 1906 | UINT64_C(258411002331363), // STOCGAsmLH |
| 1907 | UINT64_C(258402412396771), // STOCGAsmM |
| 1908 | UINT64_C(258415297298659), // STOCGAsmNE |
| 1909 | UINT64_C(258441067102435), // STOCGAsmNH |
| 1910 | UINT64_C(258406707364067), // STOCGAsmNHE |
| 1911 | UINT64_C(258432477167843), // STOCGAsmNL |
| 1912 | UINT64_C(258398117429475), // STOCGAsmNLE |
| 1913 | UINT64_C(258423887233251), // STOCGAsmNLH |
| 1914 | UINT64_C(258432477167843), // STOCGAsmNM |
| 1915 | UINT64_C(258445362069731), // STOCGAsmNO |
| 1916 | UINT64_C(258441067102435), // STOCGAsmNP |
| 1917 | UINT64_C(258415297298659), // STOCGAsmNZ |
| 1918 | UINT64_C(258389527494883), // STOCGAsmO |
| 1919 | UINT64_C(258393822462179), // STOCGAsmP |
| 1920 | UINT64_C(258419592265955), // STOCGAsmZ |
| 1921 | UINT64_C(2902458368), // STOSM |
| 1922 | UINT64_C(249589139505294), // STPQ |
| 1923 | UINT64_C(2986934272), // STPT |
| 1924 | UINT64_C(2987458560), // STPX |
| 1925 | UINT64_C(251796752695296), // STRAG |
| 1926 | UINT64_C(215568703553536), // STRL |
| 1927 | UINT64_C(249589139505214), // STRV |
| 1928 | UINT64_C(249589139505199), // STRVG |
| 1929 | UINT64_C(249589139505215), // STRVH |
| 1930 | UINT64_C(2989752320), // STSCH |
| 1931 | UINT64_C(2994536448), // STSI |
| 1932 | UINT64_C(2990931968), // STURA |
| 1933 | UINT64_C(3106209792), // STURG |
| 1934 | UINT64_C(249589139505232), // STY |
| 1935 | UINT64_C(2130706432), // SU |
| 1936 | UINT64_C(16128), // SUR |
| 1937 | UINT64_C(2560), // SVC |
| 1938 | UINT64_C(1862270976), // SW |
| 1939 | UINT64_C(12032), // SWR |
| 1940 | UINT64_C(3008036864), // SXBR |
| 1941 | UINT64_C(14080), // SXR |
| 1942 | UINT64_C(3017474048), // SXTR |
| 1943 | UINT64_C(3017474048), // SXTRA |
| 1944 | UINT64_C(249589139505243), // SY |
| 1945 | UINT64_C(3002859520), // TABORT |
| 1946 | UINT64_C(267), // TAM |
| 1947 | UINT64_C(2991325184), // TAR |
| 1948 | UINT64_C(2989228032), // TB |
| 1949 | UINT64_C(3008430080), // TBDR |
| 1950 | UINT64_C(3008364544), // TBEDR |
| 1951 | UINT64_C(252200479621120), // TBEGIN |
| 1952 | UINT64_C(252204774588416), // TBEGINC |
| 1953 | UINT64_C(260584255782929), // TCDB |
| 1954 | UINT64_C(260584255782928), // TCEB |
| 1955 | UINT64_C(260584255782930), // TCXB |
| 1956 | UINT64_C(260584255782996), // TDCDT |
| 1957 | UINT64_C(260584255782992), // TDCET |
| 1958 | UINT64_C(260584255783000), // TDCXT |
| 1959 | UINT64_C(260584255782997), // TDGDT |
| 1960 | UINT64_C(260584255782993), // TDGET |
| 1961 | UINT64_C(260584255783001), // TDGXT |
| 1962 | UINT64_C(3002597376), // TEND |
| 1963 | UINT64_C(3008888832), // THDER |
| 1964 | UINT64_C(3008954368), // THDR |
| 1965 | UINT64_C(2432696320), // TM |
| 1966 | UINT64_C(2801926144), // TMHH |
| 1967 | UINT64_C(2801991680), // TMHL |
| 1968 | UINT64_C(2801795072), // TMLH |
| 1969 | UINT64_C(2801860608), // TMLL |
| 1970 | UINT64_C(258385232527441), // TMY |
| 1971 | UINT64_C(258385232527552), // TP |
| 1972 | UINT64_C(3114336256), // TPEI |
| 1973 | UINT64_C(2989883392), // TPI |
| 1974 | UINT64_C(251792457728000), // TPROT |
| 1975 | UINT64_C(241892558110720), // TR |
| 1976 | UINT64_C(2566914048), // TRACE |
| 1977 | UINT64_C(258385232527375), // TRACG |
| 1978 | UINT64_C(511), // TRAP2 |
| 1979 | UINT64_C(3003056128), // TRAP4 |
| 1980 | UINT64_C(2997157888), // TRE |
| 1981 | UINT64_C(3113418752), // TROO |
| 1982 | UINT64_C(3113418752), // TROOOpt |
| 1983 | UINT64_C(3113353216), // TROT |
| 1984 | UINT64_C(3113353216), // TROTOpt |
| 1985 | UINT64_C(242992069738496), // TRT |
| 1986 | UINT64_C(3116302336), // TRTE |
| 1987 | UINT64_C(3116302336), // TRTEOpt |
| 1988 | UINT64_C(3113287680), // TRTO |
| 1989 | UINT64_C(3113287680), // TRTOOpt |
| 1990 | UINT64_C(228698418577408), // TRTR |
| 1991 | UINT64_C(3116171264), // TRTRE |
| 1992 | UINT64_C(3116171264), // TRTREOpt |
| 1993 | UINT64_C(3113222144), // TRTT |
| 1994 | UINT64_C(3113222144), // TRTTOpt |
| 1995 | UINT64_C(2466250752), // TS |
| 1996 | UINT64_C(2989817856), // TSCH |
| 1997 | UINT64_C(267181325549568), // UNPK |
| 1998 | UINT64_C(257285720899584), // UNPKA |
| 1999 | UINT64_C(248489627877376), // UNPKU |
| 2000 | UINT64_C(258), // UPT |
| 2001 | UINT64_C(253987186016499), // VA |
| 2002 | UINT64_C(253987186016499), // VAB |
| 2003 | UINT64_C(253987186016443), // VAC |
| 2004 | UINT64_C(253987186016497), // VACC |
| 2005 | UINT64_C(253987186016497), // VACCB |
| 2006 | UINT64_C(253987186016441), // VACCC |
| 2007 | UINT64_C(253987253125305), // VACCCQ |
| 2008 | UINT64_C(253987186024689), // VACCF |
| 2009 | UINT64_C(253987186028785), // VACCG |
| 2010 | UINT64_C(253987186020593), // VACCH |
| 2011 | UINT64_C(253987186032881), // VACCQ |
| 2012 | UINT64_C(253987253125307), // VACQ |
| 2013 | UINT64_C(253987186024691), // VAF |
| 2014 | UINT64_C(253987186028787), // VAG |
| 2015 | UINT64_C(253987186020595), // VAH |
| 2016 | UINT64_C(252887674388593), // VAP |
| 2017 | UINT64_C(253987186032883), // VAQ |
| 2018 | UINT64_C(253987186016498), // VAVG |
| 2019 | UINT64_C(253987186016498), // VAVGB |
| 2020 | UINT64_C(253987186024690), // VAVGF |
| 2021 | UINT64_C(253987186028786), // VAVGG |
| 2022 | UINT64_C(253987186020594), // VAVGH |
| 2023 | UINT64_C(253987186016496), // VAVGL |
| 2024 | UINT64_C(253987186016496), // VAVGLB |
| 2025 | UINT64_C(253987186024688), // VAVGLF |
| 2026 | UINT64_C(253987186028784), // VAVGLG |
| 2027 | UINT64_C(253987186020592), // VAVGLH |
| 2028 | UINT64_C(253987186032880), // VAVGLQ |
| 2029 | UINT64_C(253987186032882), // VAVGQ |
| 2030 | UINT64_C(253987186016393), // VBLEND |
| 2031 | UINT64_C(253987186016393), // VBLENDB |
| 2032 | UINT64_C(253987219570825), // VBLENDF |
| 2033 | UINT64_C(253987236348041), // VBLENDG |
| 2034 | UINT64_C(253987202793609), // VBLENDH |
| 2035 | UINT64_C(253987253125257), // VBLENDQ |
| 2036 | UINT64_C(253987186016389), // VBPERM |
| 2037 | UINT64_C(253987186016451), // VCDG |
| 2038 | UINT64_C(253987186028739), // VCDGB |
| 2039 | UINT64_C(253987186016449), // VCDLG |
| 2040 | UINT64_C(253987186028737), // VCDLGB |
| 2041 | UINT64_C(253987186024643), // VCEFB |
| 2042 | UINT64_C(253987186024641), // VCELFB |
| 2043 | UINT64_C(253987186016504), // VCEQ |
| 2044 | UINT64_C(253987186016504), // VCEQB |
| 2045 | UINT64_C(253987187065080), // VCEQBS |
| 2046 | UINT64_C(253987186024696), // VCEQF |
| 2047 | UINT64_C(253987187073272), // VCEQFS |
| 2048 | UINT64_C(253987186028792), // VCEQG |
| 2049 | UINT64_C(253987187077368), // VCEQGS |
| 2050 | UINT64_C(253987186020600), // VCEQH |
| 2051 | UINT64_C(253987187069176), // VCEQHS |
| 2052 | UINT64_C(253987186032888), // VCEQQ |
| 2053 | UINT64_C(253987187081464), // VCEQQS |
| 2054 | UINT64_C(253987186024642), // VCFEB |
| 2055 | UINT64_C(252887674388573), // VCFN |
| 2056 | UINT64_C(253987186016449), // VCFPL |
| 2057 | UINT64_C(253987186016451), // VCFPS |
| 2058 | UINT64_C(253987186016450), // VCGD |
| 2059 | UINT64_C(253987186028738), // VCGDB |
| 2060 | UINT64_C(253987186016507), // VCH |
| 2061 | UINT64_C(253987186016507), // VCHB |
| 2062 | UINT64_C(253987187065083), // VCHBS |
| 2063 | UINT64_C(253987186024699), // VCHF |
| 2064 | UINT64_C(253987187073275), // VCHFS |
| 2065 | UINT64_C(253987186028795), // VCHG |
| 2066 | UINT64_C(253987187077371), // VCHGS |
| 2067 | UINT64_C(253987186020603), // VCHH |
| 2068 | UINT64_C(253987187069179), // VCHHS |
| 2069 | UINT64_C(253987186016505), // VCHL |
| 2070 | UINT64_C(253987186016505), // VCHLB |
| 2071 | UINT64_C(253987187065081), // VCHLBS |
| 2072 | UINT64_C(253987186024697), // VCHLF |
| 2073 | UINT64_C(253987187073273), // VCHLFS |
| 2074 | UINT64_C(253987186028793), // VCHLG |
| 2075 | UINT64_C(253987187077369), // VCHLGS |
| 2076 | UINT64_C(253987186020601), // VCHLH |
| 2077 | UINT64_C(253987187069177), // VCHLHS |
| 2078 | UINT64_C(253987186032889), // VCHLQ |
| 2079 | UINT64_C(253987187081465), // VCHLQS |
| 2080 | UINT64_C(253987186032891), // VCHQ |
| 2081 | UINT64_C(253987187081467), // VCHQS |
| 2082 | UINT64_C(253987186016358), // VCKSM |
| 2083 | UINT64_C(253987186024640), // VCLFEB |
| 2084 | UINT64_C(252887674388566), // VCLFNH |
| 2085 | UINT64_C(252887674388574), // VCLFNL |
| 2086 | UINT64_C(253987186016448), // VCLFP |
| 2087 | UINT64_C(253987186016448), // VCLGD |
| 2088 | UINT64_C(253987186028736), // VCLGDB |
| 2089 | UINT64_C(253987186016339), // VCLZ |
| 2090 | UINT64_C(253987186016339), // VCLZB |
| 2091 | UINT64_C(252887674388561), // VCLZDP |
| 2092 | UINT64_C(253987186024531), // VCLZF |
| 2093 | UINT64_C(253987186028627), // VCLZG |
| 2094 | UINT64_C(253987186020435), // VCLZH |
| 2095 | UINT64_C(253987186032723), // VCLZQ |
| 2096 | UINT64_C(252887674388565), // VCNF |
| 2097 | UINT64_C(252887674388599), // VCP |
| 2098 | UINT64_C(252887674388597), // VCRNF |
| 2099 | UINT64_C(253987186016450), // VCSFP |
| 2100 | UINT64_C(252887674388605), // VCSPH |
| 2101 | UINT64_C(253987186016338), // VCTZ |
| 2102 | UINT64_C(253987186016338), // VCTZB |
| 2103 | UINT64_C(253987186024530), // VCTZF |
| 2104 | UINT64_C(253987186028626), // VCTZG |
| 2105 | UINT64_C(253987186020434), // VCTZH |
| 2106 | UINT64_C(253987186032722), // VCTZQ |
| 2107 | UINT64_C(252887674388560), // VCVB |
| 2108 | UINT64_C(252887674388562), // VCVBG |
| 2109 | UINT64_C(252887674388562), // VCVBGOpt |
| 2110 | UINT64_C(252887674388560), // VCVBOpt |
| 2111 | UINT64_C(252887674388558), // VCVBQ |
| 2112 | UINT64_C(252887674388568), // VCVD |
| 2113 | UINT64_C(252887674388570), // VCVDG |
| 2114 | UINT64_C(252887674388554), // VCVDQ |
| 2115 | UINT64_C(253987186016434), // VD |
| 2116 | UINT64_C(253987186024626), // VDF |
| 2117 | UINT64_C(253987186028722), // VDG |
| 2118 | UINT64_C(253987186016432), // VDL |
| 2119 | UINT64_C(253987186024624), // VDLF |
| 2120 | UINT64_C(253987186028720), // VDLG |
| 2121 | UINT64_C(253987186032816), // VDLQ |
| 2122 | UINT64_C(252887674388602), // VDP |
| 2123 | UINT64_C(253987186032818), // VDQ |
| 2124 | UINT64_C(253987186016475), // VEC |
| 2125 | UINT64_C(253987186016475), // VECB |
| 2126 | UINT64_C(253987186024667), // VECF |
| 2127 | UINT64_C(253987186028763), // VECG |
| 2128 | UINT64_C(253987186020571), // VECH |
| 2129 | UINT64_C(253987186016473), // VECL |
| 2130 | UINT64_C(253987186016473), // VECLB |
| 2131 | UINT64_C(253987186024665), // VECLF |
| 2132 | UINT64_C(253987186028761), // VECLG |
| 2133 | UINT64_C(253987186020569), // VECLH |
| 2134 | UINT64_C(253987186032857), // VECLQ |
| 2135 | UINT64_C(253987186032859), // VECQ |
| 2136 | UINT64_C(253987186016370), // VERIM |
| 2137 | UINT64_C(253987186016370), // VERIMB |
| 2138 | UINT64_C(253987186024562), // VERIMF |
| 2139 | UINT64_C(253987186028658), // VERIMG |
| 2140 | UINT64_C(253987186020466), // VERIMH |
| 2141 | UINT64_C(253987186016307), // VERLL |
| 2142 | UINT64_C(253987186016307), // VERLLB |
| 2143 | UINT64_C(253987186024499), // VERLLF |
| 2144 | UINT64_C(253987186028595), // VERLLG |
| 2145 | UINT64_C(253987186020403), // VERLLH |
| 2146 | UINT64_C(253987186016371), // VERLLV |
| 2147 | UINT64_C(253987186016371), // VERLLVB |
| 2148 | UINT64_C(253987186024563), // VERLLVF |
| 2149 | UINT64_C(253987186028659), // VERLLVG |
| 2150 | UINT64_C(253987186020467), // VERLLVH |
| 2151 | UINT64_C(253987186016304), // VESL |
| 2152 | UINT64_C(253987186016304), // VESLB |
| 2153 | UINT64_C(253987186024496), // VESLF |
| 2154 | UINT64_C(253987186028592), // VESLG |
| 2155 | UINT64_C(253987186020400), // VESLH |
| 2156 | UINT64_C(253987186016368), // VESLV |
| 2157 | UINT64_C(253987186016368), // VESLVB |
| 2158 | UINT64_C(253987186024560), // VESLVF |
| 2159 | UINT64_C(253987186028656), // VESLVG |
| 2160 | UINT64_C(253987186020464), // VESLVH |
| 2161 | UINT64_C(253987186016314), // VESRA |
| 2162 | UINT64_C(253987186016314), // VESRAB |
| 2163 | UINT64_C(253987186024506), // VESRAF |
| 2164 | UINT64_C(253987186028602), // VESRAG |
| 2165 | UINT64_C(253987186020410), // VESRAH |
| 2166 | UINT64_C(253987186016378), // VESRAV |
| 2167 | UINT64_C(253987186016378), // VESRAVB |
| 2168 | UINT64_C(253987186024570), // VESRAVF |
| 2169 | UINT64_C(253987186028666), // VESRAVG |
| 2170 | UINT64_C(253987186020474), // VESRAVH |
| 2171 | UINT64_C(253987186016312), // VESRL |
| 2172 | UINT64_C(253987186016312), // VESRLB |
| 2173 | UINT64_C(253987186024504), // VESRLF |
| 2174 | UINT64_C(253987186028600), // VESRLG |
| 2175 | UINT64_C(253987186020408), // VESRLH |
| 2176 | UINT64_C(253987186016376), // VESRLV |
| 2177 | UINT64_C(253987186016376), // VESRLVB |
| 2178 | UINT64_C(253987186024568), // VESRLVF |
| 2179 | UINT64_C(253987186028664), // VESRLVG |
| 2180 | UINT64_C(253987186020472), // VESRLVH |
| 2181 | UINT64_C(253987186016392), // VEVAL |
| 2182 | UINT64_C(253987186016483), // VFA |
| 2183 | UINT64_C(253987186028771), // VFADB |
| 2184 | UINT64_C(253987186016386), // VFAE |
| 2185 | UINT64_C(253987186016386), // VFAEB |
| 2186 | UINT64_C(253987187064962), // VFAEBS |
| 2187 | UINT64_C(253987186024578), // VFAEF |
| 2188 | UINT64_C(253987187073154), // VFAEFS |
| 2189 | UINT64_C(253987186020482), // VFAEH |
| 2190 | UINT64_C(253987187069058), // VFAEHS |
| 2191 | UINT64_C(253987188113538), // VFAEZB |
| 2192 | UINT64_C(253987189162114), // VFAEZBS |
| 2193 | UINT64_C(253987188121730), // VFAEZF |
| 2194 | UINT64_C(253987189170306), // VFAEZFS |
| 2195 | UINT64_C(253987188117634), // VFAEZH |
| 2196 | UINT64_C(253987189166210), // VFAEZHS |
| 2197 | UINT64_C(253987186024675), // VFASB |
| 2198 | UINT64_C(253987186016488), // VFCE |
| 2199 | UINT64_C(253987186028776), // VFCEDB |
| 2200 | UINT64_C(253987187077352), // VFCEDBS |
| 2201 | UINT64_C(253987186024680), // VFCESB |
| 2202 | UINT64_C(253987187073256), // VFCESBS |
| 2203 | UINT64_C(253987186016491), // VFCH |
| 2204 | UINT64_C(253987186028779), // VFCHDB |
| 2205 | UINT64_C(253987187077355), // VFCHDBS |
| 2206 | UINT64_C(253987186016490), // VFCHE |
| 2207 | UINT64_C(253987186028778), // VFCHEDB |
| 2208 | UINT64_C(253987187077354), // VFCHEDBS |
| 2209 | UINT64_C(253987186024682), // VFCHESB |
| 2210 | UINT64_C(253987187073258), // VFCHESBS |
| 2211 | UINT64_C(253987186024683), // VFCHSB |
| 2212 | UINT64_C(253987187073259), // VFCHSBS |
| 2213 | UINT64_C(253987186016485), // VFD |
| 2214 | UINT64_C(253987186028773), // VFDDB |
| 2215 | UINT64_C(253987186024677), // VFDSB |
| 2216 | UINT64_C(253987186016384), // VFEE |
| 2217 | UINT64_C(253987186016384), // VFEEB |
| 2218 | UINT64_C(253987187064960), // VFEEBS |
| 2219 | UINT64_C(253987186024576), // VFEEF |
| 2220 | UINT64_C(253987187073152), // VFEEFS |
| 2221 | UINT64_C(253987186020480), // VFEEH |
| 2222 | UINT64_C(253987187069056), // VFEEHS |
| 2223 | UINT64_C(253987188113536), // VFEEZB |
| 2224 | UINT64_C(253987189162112), // VFEEZBS |
| 2225 | UINT64_C(253987188121728), // VFEEZF |
| 2226 | UINT64_C(253987189170304), // VFEEZFS |
| 2227 | UINT64_C(253987188117632), // VFEEZH |
| 2228 | UINT64_C(253987189166208), // VFEEZHS |
| 2229 | UINT64_C(253987186016385), // VFENE |
| 2230 | UINT64_C(253987186016385), // VFENEB |
| 2231 | UINT64_C(253987187064961), // VFENEBS |
| 2232 | UINT64_C(253987186024577), // VFENEF |
| 2233 | UINT64_C(253987187073153), // VFENEFS |
| 2234 | UINT64_C(253987186020481), // VFENEH |
| 2235 | UINT64_C(253987187069057), // VFENEHS |
| 2236 | UINT64_C(253987188113537), // VFENEZB |
| 2237 | UINT64_C(253987189162113), // VFENEZBS |
| 2238 | UINT64_C(253987188121729), // VFENEZF |
| 2239 | UINT64_C(253987189170305), // VFENEZFS |
| 2240 | UINT64_C(253987188117633), // VFENEZH |
| 2241 | UINT64_C(253987189166209), // VFENEZHS |
| 2242 | UINT64_C(253987186016455), // VFI |
| 2243 | UINT64_C(253987186028743), // VFIDB |
| 2244 | UINT64_C(253987186024647), // VFISB |
| 2245 | UINT64_C(253987186290920), // VFKEDB |
| 2246 | UINT64_C(253987187339496), // VFKEDBS |
| 2247 | UINT64_C(253987186286824), // VFKESB |
| 2248 | UINT64_C(253987187335400), // VFKESBS |
| 2249 | UINT64_C(253987186290923), // VFKHDB |
| 2250 | UINT64_C(253987187339499), // VFKHDBS |
| 2251 | UINT64_C(253987186290922), // VFKHEDB |
| 2252 | UINT64_C(253987187339498), // VFKHEDBS |
| 2253 | UINT64_C(253987186286826), // VFKHESB |
| 2254 | UINT64_C(253987187335402), // VFKHESBS |
| 2255 | UINT64_C(253987186286827), // VFKHSB |
| 2256 | UINT64_C(253987187335403), // VFKHSBS |
| 2257 | UINT64_C(253987186028748), // VFLCDB |
| 2258 | UINT64_C(253987186024652), // VFLCSB |
| 2259 | UINT64_C(253987186016452), // VFLL |
| 2260 | UINT64_C(253987186024644), // VFLLS |
| 2261 | UINT64_C(253987187077324), // VFLNDB |
| 2262 | UINT64_C(253987187073228), // VFLNSB |
| 2263 | UINT64_C(253987188125900), // VFLPDB |
| 2264 | UINT64_C(253987188121804), // VFLPSB |
| 2265 | UINT64_C(253987186016453), // VFLR |
| 2266 | UINT64_C(253987186028741), // VFLRD |
| 2267 | UINT64_C(253987186016487), // VFM |
| 2268 | UINT64_C(253987186016399), // VFMA |
| 2269 | UINT64_C(253987236348047), // VFMADB |
| 2270 | UINT64_C(253987219570831), // VFMASB |
| 2271 | UINT64_C(253987186016495), // VFMAX |
| 2272 | UINT64_C(253987186028783), // VFMAXDB |
| 2273 | UINT64_C(253987186024687), // VFMAXSB |
| 2274 | UINT64_C(253987186028775), // VFMDB |
| 2275 | UINT64_C(253987186016494), // VFMIN |
| 2276 | UINT64_C(253987186028782), // VFMINDB |
| 2277 | UINT64_C(253987186024686), // VFMINSB |
| 2278 | UINT64_C(253987186016398), // VFMS |
| 2279 | UINT64_C(253987186024679), // VFMSB |
| 2280 | UINT64_C(253987236348046), // VFMSDB |
| 2281 | UINT64_C(253987219570830), // VFMSSB |
| 2282 | UINT64_C(253987186016415), // VFNMA |
| 2283 | UINT64_C(253987236348063), // VFNMADB |
| 2284 | UINT64_C(253987219570847), // VFNMASB |
| 2285 | UINT64_C(253987186016414), // VFNMS |
| 2286 | UINT64_C(253987236348062), // VFNMSDB |
| 2287 | UINT64_C(253987219570846), // VFNMSSB |
| 2288 | UINT64_C(253987186016460), // VFPSO |
| 2289 | UINT64_C(253987186028748), // VFPSODB |
| 2290 | UINT64_C(253987186024652), // VFPSOSB |
| 2291 | UINT64_C(253987186016482), // VFS |
| 2292 | UINT64_C(253987186028770), // VFSDB |
| 2293 | UINT64_C(253987186016462), // VFSQ |
| 2294 | UINT64_C(253987186028750), // VFSQDB |
| 2295 | UINT64_C(253987186024654), // VFSQSB |
| 2296 | UINT64_C(253987186024674), // VFSSB |
| 2297 | UINT64_C(253987186016330), // VFTCI |
| 2298 | UINT64_C(253987186028618), // VFTCIDB |
| 2299 | UINT64_C(253987186024522), // VFTCISB |
| 2300 | UINT64_C(253987186016324), // VGBM |
| 2301 | UINT64_C(253987186016275), // VGEF |
| 2302 | UINT64_C(253987186016274), // VGEG |
| 2303 | UINT64_C(253987186016340), // VGEM |
| 2304 | UINT64_C(253987186016340), // VGEMB |
| 2305 | UINT64_C(253987186024532), // VGEMF |
| 2306 | UINT64_C(253987186028628), // VGEMG |
| 2307 | UINT64_C(253987186020436), // VGEMH |
| 2308 | UINT64_C(253987186032724), // VGEMQ |
| 2309 | UINT64_C(253987186016436), // VGFM |
| 2310 | UINT64_C(253987186016444), // VGFMA |
| 2311 | UINT64_C(253987186016444), // VGFMAB |
| 2312 | UINT64_C(253987219570876), // VGFMAF |
| 2313 | UINT64_C(253987236348092), // VGFMAG |
| 2314 | UINT64_C(253987202793660), // VGFMAH |
| 2315 | UINT64_C(253987186016436), // VGFMB |
| 2316 | UINT64_C(253987186024628), // VGFMF |
| 2317 | UINT64_C(253987186028724), // VGFMG |
| 2318 | UINT64_C(253987186020532), // VGFMH |
| 2319 | UINT64_C(253987186016326), // VGM |
| 2320 | UINT64_C(253987186016326), // VGMB |
| 2321 | UINT64_C(253987186024518), // VGMF |
| 2322 | UINT64_C(253987186028614), // VGMG |
| 2323 | UINT64_C(253987186020422), // VGMH |
| 2324 | UINT64_C(253987186016348), // VISTR |
| 2325 | UINT64_C(253987186016348), // VISTRB |
| 2326 | UINT64_C(253987187064924), // VISTRBS |
| 2327 | UINT64_C(253987186024540), // VISTRF |
| 2328 | UINT64_C(253987187073116), // VISTRFS |
| 2329 | UINT64_C(253987186020444), // VISTRH |
| 2330 | UINT64_C(253987187069020), // VISTRHS |
| 2331 | UINT64_C(253987186016262), // VL |
| 2332 | UINT64_C(253987186016262), // VLAlign |
| 2333 | UINT64_C(253987186016263), // VLBB |
| 2334 | UINT64_C(252887674388486), // VLBR |
| 2335 | UINT64_C(252887674396678), // VLBRF |
| 2336 | UINT64_C(252887674400774), // VLBRG |
| 2337 | UINT64_C(252887674392582), // VLBRH |
| 2338 | UINT64_C(252887674404870), // VLBRQ |
| 2339 | UINT64_C(252887674388485), // VLBRREP |
| 2340 | UINT64_C(252887674396677), // VLBRREPF |
| 2341 | UINT64_C(252887674400773), // VLBRREPG |
| 2342 | UINT64_C(252887674392581), // VLBRREPH |
| 2343 | UINT64_C(253987186016478), // VLC |
| 2344 | UINT64_C(253987186016478), // VLCB |
| 2345 | UINT64_C(253987186024670), // VLCF |
| 2346 | UINT64_C(253987186028766), // VLCG |
| 2347 | UINT64_C(253987186020574), // VLCH |
| 2348 | UINT64_C(253987186032862), // VLCQ |
| 2349 | UINT64_C(253987186016452), // VLDE |
| 2350 | UINT64_C(253987186024644), // VLDEB |
| 2351 | UINT64_C(253987186016256), // VLEB |
| 2352 | UINT64_C(252887674388483), // VLEBRF |
| 2353 | UINT64_C(252887674388482), // VLEBRG |
| 2354 | UINT64_C(252887674388481), // VLEBRH |
| 2355 | UINT64_C(253987186016453), // VLED |
| 2356 | UINT64_C(253987186028741), // VLEDB |
| 2357 | UINT64_C(253987186016259), // VLEF |
| 2358 | UINT64_C(253987186016258), // VLEG |
| 2359 | UINT64_C(253987186016257), // VLEH |
| 2360 | UINT64_C(253987186016320), // VLEIB |
| 2361 | UINT64_C(253987186016323), // VLEIF |
| 2362 | UINT64_C(253987186016322), // VLEIG |
| 2363 | UINT64_C(253987186016321), // VLEIH |
| 2364 | UINT64_C(252887674388487), // VLER |
| 2365 | UINT64_C(252887674396679), // VLERF |
| 2366 | UINT64_C(252887674400775), // VLERG |
| 2367 | UINT64_C(252887674392583), // VLERH |
| 2368 | UINT64_C(253987186016289), // VLGV |
| 2369 | UINT64_C(253987186016289), // VLGVB |
| 2370 | UINT64_C(253987186024481), // VLGVF |
| 2371 | UINT64_C(253987186028577), // VLGVG |
| 2372 | UINT64_C(253987186020385), // VLGVH |
| 2373 | UINT64_C(252887674388553), // VLIP |
| 2374 | UINT64_C(253987186016311), // VLL |
| 2375 | UINT64_C(252887674388484), // VLLEBRZ |
| 2376 | UINT64_C(252887674413060), // VLLEBRZE |
| 2377 | UINT64_C(252887674396676), // VLLEBRZF |
| 2378 | UINT64_C(252887674400772), // VLLEBRZG |
| 2379 | UINT64_C(252887674392580), // VLLEBRZH |
| 2380 | UINT64_C(253987186016260), // VLLEZ |
| 2381 | UINT64_C(253987186016260), // VLLEZB |
| 2382 | UINT64_C(253987186024452), // VLLEZF |
| 2383 | UINT64_C(253987186028548), // VLLEZG |
| 2384 | UINT64_C(253987186020356), // VLLEZH |
| 2385 | UINT64_C(253987186040836), // VLLEZLF |
| 2386 | UINT64_C(253987186016310), // VLM |
| 2387 | UINT64_C(253987186016310), // VLMAlign |
| 2388 | UINT64_C(253987186016479), // VLP |
| 2389 | UINT64_C(253987186016479), // VLPB |
| 2390 | UINT64_C(253987186024671), // VLPF |
| 2391 | UINT64_C(253987186028767), // VLPG |
| 2392 | UINT64_C(253987186020575), // VLPH |
| 2393 | UINT64_C(253987186032863), // VLPQ |
| 2394 | UINT64_C(253987186016342), // VLR |
| 2395 | UINT64_C(253987186016261), // VLREP |
| 2396 | UINT64_C(253987186016261), // VLREPB |
| 2397 | UINT64_C(253987186024453), // VLREPF |
| 2398 | UINT64_C(253987186028549), // VLREPG |
| 2399 | UINT64_C(253987186020357), // VLREPH |
| 2400 | UINT64_C(252887674388533), // VLRL |
| 2401 | UINT64_C(252887674388535), // VLRLR |
| 2402 | UINT64_C(253987186016290), // VLVG |
| 2403 | UINT64_C(253987186016290), // VLVGB |
| 2404 | UINT64_C(253987186024482), // VLVGF |
| 2405 | UINT64_C(253987186028578), // VLVGG |
| 2406 | UINT64_C(253987186020386), // VLVGH |
| 2407 | UINT64_C(253987186016354), // VLVGP |
| 2408 | UINT64_C(253987186016430), // VMAE |
| 2409 | UINT64_C(253987186016430), // VMAEB |
| 2410 | UINT64_C(253987219570862), // VMAEF |
| 2411 | UINT64_C(253987236348078), // VMAEG |
| 2412 | UINT64_C(253987202793646), // VMAEH |
| 2413 | UINT64_C(253987186016427), // VMAH |
| 2414 | UINT64_C(253987186016427), // VMAHB |
| 2415 | UINT64_C(253987219570859), // VMAHF |
| 2416 | UINT64_C(253987236348075), // VMAHG |
| 2417 | UINT64_C(253987202793643), // VMAHH |
| 2418 | UINT64_C(253987253125291), // VMAHQ |
| 2419 | UINT64_C(253987186016426), // VMAL |
| 2420 | UINT64_C(253987186016426), // VMALB |
| 2421 | UINT64_C(253987186016428), // VMALE |
| 2422 | UINT64_C(253987186016428), // VMALEB |
| 2423 | UINT64_C(253987219570860), // VMALEF |
| 2424 | UINT64_C(253987236348076), // VMALEG |
| 2425 | UINT64_C(253987202793644), // VMALEH |
| 2426 | UINT64_C(253987219570858), // VMALF |
| 2427 | UINT64_C(253987236348074), // VMALG |
| 2428 | UINT64_C(253987186016425), // VMALH |
| 2429 | UINT64_C(253987186016425), // VMALHB |
| 2430 | UINT64_C(253987219570857), // VMALHF |
| 2431 | UINT64_C(253987236348073), // VMALHG |
| 2432 | UINT64_C(253987202793641), // VMALHH |
| 2433 | UINT64_C(253987253125289), // VMALHQ |
| 2434 | UINT64_C(253987202793642), // VMALHW |
| 2435 | UINT64_C(253987186016429), // VMALO |
| 2436 | UINT64_C(253987186016429), // VMALOB |
| 2437 | UINT64_C(253987219570861), // VMALOF |
| 2438 | UINT64_C(253987236348077), // VMALOG |
| 2439 | UINT64_C(253987202793645), // VMALOH |
| 2440 | UINT64_C(253987253125290), // VMALQ |
| 2441 | UINT64_C(253987186016431), // VMAO |
| 2442 | UINT64_C(253987186016431), // VMAOB |
| 2443 | UINT64_C(253987219570863), // VMAOF |
| 2444 | UINT64_C(253987236348079), // VMAOG |
| 2445 | UINT64_C(253987202793647), // VMAOH |
| 2446 | UINT64_C(253987186016422), // VME |
| 2447 | UINT64_C(253987186016422), // VMEB |
| 2448 | UINT64_C(253987186024614), // VMEF |
| 2449 | UINT64_C(253987186028710), // VMEG |
| 2450 | UINT64_C(253987186020518), // VMEH |
| 2451 | UINT64_C(253987186016419), // VMH |
| 2452 | UINT64_C(253987186016419), // VMHB |
| 2453 | UINT64_C(253987186024611), // VMHF |
| 2454 | UINT64_C(253987186028707), // VMHG |
| 2455 | UINT64_C(253987186020515), // VMHH |
| 2456 | UINT64_C(253987186032803), // VMHQ |
| 2457 | UINT64_C(253987186016418), // VML |
| 2458 | UINT64_C(253987186016418), // VMLB |
| 2459 | UINT64_C(253987186016420), // VMLE |
| 2460 | UINT64_C(253987186016420), // VMLEB |
| 2461 | UINT64_C(253987186024612), // VMLEF |
| 2462 | UINT64_C(253987186028708), // VMLEG |
| 2463 | UINT64_C(253987186020516), // VMLEH |
| 2464 | UINT64_C(253987186024610), // VMLF |
| 2465 | UINT64_C(253987186028706), // VMLG |
| 2466 | UINT64_C(253987186016417), // VMLH |
| 2467 | UINT64_C(253987186016417), // VMLHB |
| 2468 | UINT64_C(253987186024609), // VMLHF |
| 2469 | UINT64_C(253987186028705), // VMLHG |
| 2470 | UINT64_C(253987186020513), // VMLHH |
| 2471 | UINT64_C(253987186032801), // VMLHQ |
| 2472 | UINT64_C(253987186020514), // VMLHW |
| 2473 | UINT64_C(253987186016421), // VMLO |
| 2474 | UINT64_C(253987186016421), // VMLOB |
| 2475 | UINT64_C(253987186024613), // VMLOF |
| 2476 | UINT64_C(253987186028709), // VMLOG |
| 2477 | UINT64_C(253987186020517), // VMLOH |
| 2478 | UINT64_C(253987186032802), // VMLQ |
| 2479 | UINT64_C(253987186016510), // VMN |
| 2480 | UINT64_C(253987186016510), // VMNB |
| 2481 | UINT64_C(253987186024702), // VMNF |
| 2482 | UINT64_C(253987186028798), // VMNG |
| 2483 | UINT64_C(253987186020606), // VMNH |
| 2484 | UINT64_C(253987186016508), // VMNL |
| 2485 | UINT64_C(253987186016508), // VMNLB |
| 2486 | UINT64_C(253987186024700), // VMNLF |
| 2487 | UINT64_C(253987186028796), // VMNLG |
| 2488 | UINT64_C(253987186020604), // VMNLH |
| 2489 | UINT64_C(253987186032892), // VMNLQ |
| 2490 | UINT64_C(253987186032894), // VMNQ |
| 2491 | UINT64_C(253987186016423), // VMO |
| 2492 | UINT64_C(253987186016423), // VMOB |
| 2493 | UINT64_C(253987186024615), // VMOF |
| 2494 | UINT64_C(253987186028711), // VMOG |
| 2495 | UINT64_C(253987186020519), // VMOH |
| 2496 | UINT64_C(252887674388600), // VMP |
| 2497 | UINT64_C(253987186016353), // VMRH |
| 2498 | UINT64_C(253987186016353), // VMRHB |
| 2499 | UINT64_C(253987186024545), // VMRHF |
| 2500 | UINT64_C(253987186028641), // VMRHG |
| 2501 | UINT64_C(253987186020449), // VMRHH |
| 2502 | UINT64_C(253987186016352), // VMRL |
| 2503 | UINT64_C(253987186016352), // VMRLB |
| 2504 | UINT64_C(253987186024544), // VMRLF |
| 2505 | UINT64_C(253987186028640), // VMRLG |
| 2506 | UINT64_C(253987186020448), // VMRLH |
| 2507 | UINT64_C(253987186016440), // VMSL |
| 2508 | UINT64_C(253987236348088), // VMSLG |
| 2509 | UINT64_C(252887674388601), // VMSP |
| 2510 | UINT64_C(253987186016511), // VMX |
| 2511 | UINT64_C(253987186016511), // VMXB |
| 2512 | UINT64_C(253987186024703), // VMXF |
| 2513 | UINT64_C(253987186028799), // VMXG |
| 2514 | UINT64_C(253987186020607), // VMXH |
| 2515 | UINT64_C(253987186016509), // VMXL |
| 2516 | UINT64_C(253987186016509), // VMXLB |
| 2517 | UINT64_C(253987186024701), // VMXLF |
| 2518 | UINT64_C(253987186028797), // VMXLG |
| 2519 | UINT64_C(253987186020605), // VMXLH |
| 2520 | UINT64_C(253987186032893), // VMXLQ |
| 2521 | UINT64_C(253987186032895), // VMXQ |
| 2522 | UINT64_C(253987186016360), // VN |
| 2523 | UINT64_C(253987186016361), // VNC |
| 2524 | UINT64_C(253987186016366), // VNN |
| 2525 | UINT64_C(253987186016363), // VNO |
| 2526 | UINT64_C(253987186016364), // VNX |
| 2527 | UINT64_C(253987186016362), // VO |
| 2528 | UINT64_C(253987186016367), // VOC |
| 2529 | UINT64_C(253991480918084), // VONE |
| 2530 | UINT64_C(253987186016388), // VPDI |
| 2531 | UINT64_C(253987186016396), // VPERM |
| 2532 | UINT64_C(253987186016404), // VPK |
| 2533 | UINT64_C(253987186024596), // VPKF |
| 2534 | UINT64_C(253987186028692), // VPKG |
| 2535 | UINT64_C(253987186020500), // VPKH |
| 2536 | UINT64_C(253987186016405), // VPKLS |
| 2537 | UINT64_C(253987186024597), // VPKLSF |
| 2538 | UINT64_C(253987187073173), // VPKLSFS |
| 2539 | UINT64_C(253987186028693), // VPKLSG |
| 2540 | UINT64_C(253987187077269), // VPKLSGS |
| 2541 | UINT64_C(253987186020501), // VPKLSH |
| 2542 | UINT64_C(253987187069077), // VPKLSHS |
| 2543 | UINT64_C(253987186016407), // VPKS |
| 2544 | UINT64_C(253987186024599), // VPKSF |
| 2545 | UINT64_C(253987187073175), // VPKSFS |
| 2546 | UINT64_C(253987186028695), // VPKSG |
| 2547 | UINT64_C(253987187077271), // VPKSGS |
| 2548 | UINT64_C(253987186020503), // VPKSH |
| 2549 | UINT64_C(253987187069079), // VPKSHS |
| 2550 | UINT64_C(252887674388532), // VPKZ |
| 2551 | UINT64_C(252887674388592), // VPKZR |
| 2552 | UINT64_C(253987186016336), // VPOPCT |
| 2553 | UINT64_C(253987186016336), // VPOPCTB |
| 2554 | UINT64_C(253987186024528), // VPOPCTF |
| 2555 | UINT64_C(253987186028624), // VPOPCTG |
| 2556 | UINT64_C(253987186020432), // VPOPCTH |
| 2557 | UINT64_C(252887674388571), // VPSOP |
| 2558 | UINT64_C(253987186016435), // VR |
| 2559 | UINT64_C(253987186016333), // VREP |
| 2560 | UINT64_C(253987186016333), // VREPB |
| 2561 | UINT64_C(253987186024525), // VREPF |
| 2562 | UINT64_C(253987186028621), // VREPG |
| 2563 | UINT64_C(253987186020429), // VREPH |
| 2564 | UINT64_C(253987186016325), // VREPI |
| 2565 | UINT64_C(253987186016325), // VREPIB |
| 2566 | UINT64_C(253987186024517), // VREPIF |
| 2567 | UINT64_C(253987186028613), // VREPIG |
| 2568 | UINT64_C(253987186020421), // VREPIH |
| 2569 | UINT64_C(253987186024627), // VRF |
| 2570 | UINT64_C(253987186028723), // VRG |
| 2571 | UINT64_C(253987186016433), // VRL |
| 2572 | UINT64_C(253987186024625), // VRLF |
| 2573 | UINT64_C(253987186028721), // VRLG |
| 2574 | UINT64_C(253987186032817), // VRLQ |
| 2575 | UINT64_C(252887674388603), // VRP |
| 2576 | UINT64_C(253987186032819), // VRQ |
| 2577 | UINT64_C(253987186016503), // VS |
| 2578 | UINT64_C(253987186016503), // VSB |
| 2579 | UINT64_C(253987186016445), // VSBCBI |
| 2580 | UINT64_C(253987253125309), // VSBCBIQ |
| 2581 | UINT64_C(253987186016447), // VSBI |
| 2582 | UINT64_C(253987253125311), // VSBIQ |
| 2583 | UINT64_C(253987186016501), // VSCBI |
| 2584 | UINT64_C(253987186016501), // VSCBIB |
| 2585 | UINT64_C(253987186024693), // VSCBIF |
| 2586 | UINT64_C(253987186028789), // VSCBIG |
| 2587 | UINT64_C(253987186020597), // VSCBIH |
| 2588 | UINT64_C(253987186032885), // VSCBIQ |
| 2589 | UINT64_C(253987186016283), // VSCEF |
| 2590 | UINT64_C(253987186016282), // VSCEG |
| 2591 | UINT64_C(252887674400884), // VSCHDP |
| 2592 | UINT64_C(252887674388596), // VSCHP |
| 2593 | UINT64_C(252887674396788), // VSCHSP |
| 2594 | UINT64_C(252887674404980), // VSCHXP |
| 2595 | UINT64_C(252887674388604), // VSCSHP |
| 2596 | UINT64_C(252887674388606), // VSDP |
| 2597 | UINT64_C(253987186016351), // VSEG |
| 2598 | UINT64_C(253987186016351), // VSEGB |
| 2599 | UINT64_C(253987186024543), // VSEGF |
| 2600 | UINT64_C(253987186020447), // VSEGH |
| 2601 | UINT64_C(253987186016397), // VSEL |
| 2602 | UINT64_C(253987186024695), // VSF |
| 2603 | UINT64_C(253987186028791), // VSG |
| 2604 | UINT64_C(253987186020599), // VSH |
| 2605 | UINT64_C(253987186016372), // VSL |
| 2606 | UINT64_C(253987186016373), // VSLB |
| 2607 | UINT64_C(253987186016390), // VSLD |
| 2608 | UINT64_C(253987186016375), // VSLDB |
| 2609 | UINT64_C(252887674388595), // VSP |
| 2610 | UINT64_C(253987186032887), // VSQ |
| 2611 | UINT64_C(253987186016382), // VSRA |
| 2612 | UINT64_C(253987186016383), // VSRAB |
| 2613 | UINT64_C(253987186016391), // VSRD |
| 2614 | UINT64_C(253987186016380), // VSRL |
| 2615 | UINT64_C(253987186016381), // VSRLB |
| 2616 | UINT64_C(252887674388569), // VSRP |
| 2617 | UINT64_C(252887674388594), // VSRPR |
| 2618 | UINT64_C(253987186016270), // VST |
| 2619 | UINT64_C(253987186016270), // VSTAlign |
| 2620 | UINT64_C(252887674388494), // VSTBR |
| 2621 | UINT64_C(252887674396686), // VSTBRF |
| 2622 | UINT64_C(252887674400782), // VSTBRG |
| 2623 | UINT64_C(252887674392590), // VSTBRH |
| 2624 | UINT64_C(252887674404878), // VSTBRQ |
| 2625 | UINT64_C(253987186016264), // VSTEB |
| 2626 | UINT64_C(252887674388491), // VSTEBRF |
| 2627 | UINT64_C(252887674388490), // VSTEBRG |
| 2628 | UINT64_C(252887674388489), // VSTEBRH |
| 2629 | UINT64_C(253987186016267), // VSTEF |
| 2630 | UINT64_C(253987186016266), // VSTEG |
| 2631 | UINT64_C(253987186016265), // VSTEH |
| 2632 | UINT64_C(252887674388495), // VSTER |
| 2633 | UINT64_C(252887674396687), // VSTERF |
| 2634 | UINT64_C(252887674400783), // VSTERG |
| 2635 | UINT64_C(252887674392591), // VSTERH |
| 2636 | UINT64_C(253987186016319), // VSTL |
| 2637 | UINT64_C(253987186016318), // VSTM |
| 2638 | UINT64_C(253987186016318), // VSTMAlign |
| 2639 | UINT64_C(253987186016394), // VSTRC |
| 2640 | UINT64_C(253987186016394), // VSTRCB |
| 2641 | UINT64_C(253987187064970), // VSTRCBS |
| 2642 | UINT64_C(253987219570826), // VSTRCF |
| 2643 | UINT64_C(253987220619402), // VSTRCFS |
| 2644 | UINT64_C(253987202793610), // VSTRCH |
| 2645 | UINT64_C(253987203842186), // VSTRCHS |
| 2646 | UINT64_C(253987188113546), // VSTRCZB |
| 2647 | UINT64_C(253987189162122), // VSTRCZBS |
| 2648 | UINT64_C(253987221667978), // VSTRCZF |
| 2649 | UINT64_C(253987222716554), // VSTRCZFS |
| 2650 | UINT64_C(253987204890762), // VSTRCZH |
| 2651 | UINT64_C(253987205939338), // VSTRCZHS |
| 2652 | UINT64_C(252887674388541), // VSTRL |
| 2653 | UINT64_C(252887674388543), // VSTRLR |
| 2654 | UINT64_C(253987186016395), // VSTRS |
| 2655 | UINT64_C(253987186016395), // VSTRSB |
| 2656 | UINT64_C(253987219570827), // VSTRSF |
| 2657 | UINT64_C(253987202793611), // VSTRSH |
| 2658 | UINT64_C(253987188113547), // VSTRSZB |
| 2659 | UINT64_C(253987221667979), // VSTRSZF |
| 2660 | UINT64_C(253987204890763), // VSTRSZH |
| 2661 | UINT64_C(253987186016356), // VSUM |
| 2662 | UINT64_C(253987186016356), // VSUMB |
| 2663 | UINT64_C(253987186016357), // VSUMG |
| 2664 | UINT64_C(253987186024549), // VSUMGF |
| 2665 | UINT64_C(253987186020453), // VSUMGH |
| 2666 | UINT64_C(253987186020452), // VSUMH |
| 2667 | UINT64_C(253987186016359), // VSUMQ |
| 2668 | UINT64_C(253987186024551), // VSUMQF |
| 2669 | UINT64_C(253987186028647), // VSUMQG |
| 2670 | UINT64_C(253987186016472), // VTM |
| 2671 | UINT64_C(252887674388575), // VTP |
| 2672 | UINT64_C(252887674388575), // VTPOpt |
| 2673 | UINT64_C(252887674388607), // VTZ |
| 2674 | UINT64_C(253987186016471), // VUPH |
| 2675 | UINT64_C(253987186016471), // VUPHB |
| 2676 | UINT64_C(253987186024663), // VUPHF |
| 2677 | UINT64_C(253987186028759), // VUPHG |
| 2678 | UINT64_C(253987186020567), // VUPHH |
| 2679 | UINT64_C(252887674388540), // VUPKZ |
| 2680 | UINT64_C(252887674388564), // VUPKZH |
| 2681 | UINT64_C(252887674388572), // VUPKZL |
| 2682 | UINT64_C(253987186016470), // VUPL |
| 2683 | UINT64_C(253987186016470), // VUPLB |
| 2684 | UINT64_C(253987186024662), // VUPLF |
| 2685 | UINT64_C(253987186028758), // VUPLG |
| 2686 | UINT64_C(253987186016469), // VUPLH |
| 2687 | UINT64_C(253987186016469), // VUPLHB |
| 2688 | UINT64_C(253987186024661), // VUPLHF |
| 2689 | UINT64_C(253987186028757), // VUPLHG |
| 2690 | UINT64_C(253987186020565), // VUPLHH |
| 2691 | UINT64_C(253987186020566), // VUPLHW |
| 2692 | UINT64_C(253987186016468), // VUPLL |
| 2693 | UINT64_C(253987186016468), // VUPLLB |
| 2694 | UINT64_C(253987186024660), // VUPLLF |
| 2695 | UINT64_C(253987186028756), // VUPLLG |
| 2696 | UINT64_C(253987186020564), // VUPLLH |
| 2697 | UINT64_C(253987186016365), // VX |
| 2698 | UINT64_C(253987186016324), // VZERO |
| 2699 | UINT64_C(253987186553027), // WCDGB |
| 2700 | UINT64_C(253987186553025), // WCDLGB |
| 2701 | UINT64_C(253987186548931), // WCEFB |
| 2702 | UINT64_C(253987186548929), // WCELFB |
| 2703 | UINT64_C(253987186548930), // WCFEB |
| 2704 | UINT64_C(253987186553026), // WCGDB |
| 2705 | UINT64_C(253987186548928), // WCLFEB |
| 2706 | UINT64_C(253987186553024), // WCLGDB |
| 2707 | UINT64_C(253987186553059), // WFADB |
| 2708 | UINT64_C(253987186548963), // WFASB |
| 2709 | UINT64_C(253987186557155), // WFAXB |
| 2710 | UINT64_C(253987186016459), // WFC |
| 2711 | UINT64_C(253987186028747), // WFCDB |
| 2712 | UINT64_C(253987186553064), // WFCEDB |
| 2713 | UINT64_C(253987187601640), // WFCEDBS |
| 2714 | UINT64_C(253987186548968), // WFCESB |
| 2715 | UINT64_C(253987187597544), // WFCESBS |
| 2716 | UINT64_C(253987186557160), // WFCEXB |
| 2717 | UINT64_C(253987187605736), // WFCEXBS |
| 2718 | UINT64_C(253987186553067), // WFCHDB |
| 2719 | UINT64_C(253987187601643), // WFCHDBS |
| 2720 | UINT64_C(253987186553066), // WFCHEDB |
| 2721 | UINT64_C(253987187601642), // WFCHEDBS |
| 2722 | UINT64_C(253987186548970), // WFCHESB |
| 2723 | UINT64_C(253987187597546), // WFCHESBS |
| 2724 | UINT64_C(253987186557162), // WFCHEXB |
| 2725 | UINT64_C(253987187605738), // WFCHEXBS |
| 2726 | UINT64_C(253987186548971), // WFCHSB |
| 2727 | UINT64_C(253987187597547), // WFCHSBS |
| 2728 | UINT64_C(253987186557163), // WFCHXB |
| 2729 | UINT64_C(253987187605739), // WFCHXBS |
| 2730 | UINT64_C(253987186024651), // WFCSB |
| 2731 | UINT64_C(253987186032843), // WFCXB |
| 2732 | UINT64_C(253987186553061), // WFDDB |
| 2733 | UINT64_C(253987186548965), // WFDSB |
| 2734 | UINT64_C(253987186557157), // WFDXB |
| 2735 | UINT64_C(253987186553031), // WFIDB |
| 2736 | UINT64_C(253987186548935), // WFISB |
| 2737 | UINT64_C(253987186557127), // WFIXB |
| 2738 | UINT64_C(253987186016458), // WFK |
| 2739 | UINT64_C(253987186028746), // WFKDB |
| 2740 | UINT64_C(253987186815208), // WFKEDB |
| 2741 | UINT64_C(253987187863784), // WFKEDBS |
| 2742 | UINT64_C(253987186811112), // WFKESB |
| 2743 | UINT64_C(253987187859688), // WFKESBS |
| 2744 | UINT64_C(253987186819304), // WFKEXB |
| 2745 | UINT64_C(253987187867880), // WFKEXBS |
| 2746 | UINT64_C(253987186815211), // WFKHDB |
| 2747 | UINT64_C(253987187863787), // WFKHDBS |
| 2748 | UINT64_C(253987186815210), // WFKHEDB |
| 2749 | UINT64_C(253987187863786), // WFKHEDBS |
| 2750 | UINT64_C(253987186811114), // WFKHESB |
| 2751 | UINT64_C(253987187859690), // WFKHESBS |
| 2752 | UINT64_C(253987186819306), // WFKHEXB |
| 2753 | UINT64_C(253987187867882), // WFKHEXBS |
| 2754 | UINT64_C(253987186811115), // WFKHSB |
| 2755 | UINT64_C(253987187859691), // WFKHSBS |
| 2756 | UINT64_C(253987186819307), // WFKHXB |
| 2757 | UINT64_C(253987187867883), // WFKHXBS |
| 2758 | UINT64_C(253987186024650), // WFKSB |
| 2759 | UINT64_C(253987186032842), // WFKXB |
| 2760 | UINT64_C(253987186553036), // WFLCDB |
| 2761 | UINT64_C(253987186548940), // WFLCSB |
| 2762 | UINT64_C(253987186557132), // WFLCXB |
| 2763 | UINT64_C(253987186553028), // WFLLD |
| 2764 | UINT64_C(253987186548932), // WFLLS |
| 2765 | UINT64_C(253987187601612), // WFLNDB |
| 2766 | UINT64_C(253987187597516), // WFLNSB |
| 2767 | UINT64_C(253987187605708), // WFLNXB |
| 2768 | UINT64_C(253987188650188), // WFLPDB |
| 2769 | UINT64_C(253987188646092), // WFLPSB |
| 2770 | UINT64_C(253987188654284), // WFLPXB |
| 2771 | UINT64_C(253987186553029), // WFLRD |
| 2772 | UINT64_C(253987186557125), // WFLRX |
| 2773 | UINT64_C(253987236872335), // WFMADB |
| 2774 | UINT64_C(253987220095119), // WFMASB |
| 2775 | UINT64_C(253987253649551), // WFMAXB |
| 2776 | UINT64_C(253987186553071), // WFMAXDB |
| 2777 | UINT64_C(253987186548975), // WFMAXSB |
| 2778 | UINT64_C(253987186557167), // WFMAXXB |
| 2779 | UINT64_C(253987186553063), // WFMDB |
| 2780 | UINT64_C(253987186553070), // WFMINDB |
| 2781 | UINT64_C(253987186548974), // WFMINSB |
| 2782 | UINT64_C(253987186557166), // WFMINXB |
| 2783 | UINT64_C(253987186548967), // WFMSB |
| 2784 | UINT64_C(253987236872334), // WFMSDB |
| 2785 | UINT64_C(253987220095118), // WFMSSB |
| 2786 | UINT64_C(253987253649550), // WFMSXB |
| 2787 | UINT64_C(253987186557159), // WFMXB |
| 2788 | UINT64_C(253987236872351), // WFNMADB |
| 2789 | UINT64_C(253987220095135), // WFNMASB |
| 2790 | UINT64_C(253987253649567), // WFNMAXB |
| 2791 | UINT64_C(253987236872350), // WFNMSDB |
| 2792 | UINT64_C(253987220095134), // WFNMSSB |
| 2793 | UINT64_C(253987253649566), // WFNMSXB |
| 2794 | UINT64_C(253987186553036), // WFPSODB |
| 2795 | UINT64_C(253987186548940), // WFPSOSB |
| 2796 | UINT64_C(253987186557132), // WFPSOXB |
| 2797 | UINT64_C(253987186553058), // WFSDB |
| 2798 | UINT64_C(253987186553038), // WFSQDB |
| 2799 | UINT64_C(253987186548942), // WFSQSB |
| 2800 | UINT64_C(253987186557134), // WFSQXB |
| 2801 | UINT64_C(253987186548962), // WFSSB |
| 2802 | UINT64_C(253987186557154), // WFSXB |
| 2803 | UINT64_C(253987186552906), // WFTCIDB |
| 2804 | UINT64_C(253987186548810), // WFTCISB |
| 2805 | UINT64_C(253987186557002), // WFTCIXB |
| 2806 | UINT64_C(253987186548932), // WLDEB |
| 2807 | UINT64_C(253987186553029), // WLEDB |
| 2808 | UINT64_C(1459617792), // X |
| 2809 | UINT64_C(236394999971840), // XC |
| 2810 | UINT64_C(249589139505282), // XG |
| 2811 | UINT64_C(3112304640), // XGR |
| 2812 | UINT64_C(3118923776), // XGRK |
| 2813 | UINT64_C(2533359616), // XI |
| 2814 | UINT64_C(211132002336768), // XIHF |
| 2815 | UINT64_C(211136297304064), // XILF |
| 2816 | UINT64_C(258385232527447), // XIY |
| 2817 | UINT64_C(5888), // XR |
| 2818 | UINT64_C(3119972352), // XRK |
| 2819 | UINT64_C(2994077696), // XSCH |
| 2820 | UINT64_C(249589139505239), // XY |
| 2821 | UINT64_C(272678883688448), // ZAP |
| 2822 | }; |
| 2823 | constexpr unsigned FirstSupportedOpcode = 577; |
| 2824 | |
| 2825 | const unsigned opcode = MI.getOpcode(); |
| 2826 | if (opcode < FirstSupportedOpcode) |
| 2827 | reportUnsupportedInst(Inst: MI); |
| 2828 | unsigned TableIndex = opcode - FirstSupportedOpcode; |
| 2829 | uint64_t Value = InstBits[TableIndex]; |
| 2830 | uint64_t op = 0; |
| 2831 | (void)op; // suppress warning |
| 2832 | switch (opcode) { |
| 2833 | case SystemZ::CSCH: |
| 2834 | case SystemZ::HSCH: |
| 2835 | case SystemZ::IPK: |
| 2836 | case SystemZ::NNPA: |
| 2837 | case SystemZ::NOPOpt: |
| 2838 | case SystemZ::NOPROpt: |
| 2839 | case SystemZ::PALB: |
| 2840 | case SystemZ::PCC: |
| 2841 | case SystemZ::PCKMO: |
| 2842 | case SystemZ::PFPO: |
| 2843 | case SystemZ::PR: |
| 2844 | case SystemZ::PTFF: |
| 2845 | case SystemZ::PTLB: |
| 2846 | case SystemZ::RCHP: |
| 2847 | case SystemZ::RSCH: |
| 2848 | case SystemZ::SAL: |
| 2849 | case SystemZ::SAM24: |
| 2850 | case SystemZ::SAM31: |
| 2851 | case SystemZ::SAM64: |
| 2852 | case SystemZ::SCHM: |
| 2853 | case SystemZ::SCKPF: |
| 2854 | case SystemZ::TAM: |
| 2855 | case SystemZ::TEND: |
| 2856 | case SystemZ::TRAP2: |
| 2857 | case SystemZ::UPT: |
| 2858 | case SystemZ::XSCH: { |
| 2859 | break; |
| 2860 | } |
| 2861 | case SystemZ::CLI: |
| 2862 | case SystemZ::MC: |
| 2863 | case SystemZ::MVI: |
| 2864 | case SystemZ::NI: |
| 2865 | case SystemZ::OI: |
| 2866 | case SystemZ::STNSM: |
| 2867 | case SystemZ::STOSM: |
| 2868 | case SystemZ::TM: |
| 2869 | case SystemZ::XI: { |
| 2870 | // op: B1 |
| 2871 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2872 | Value |= (op & 0xf) << 12; |
| 2873 | // op: D1 |
| 2874 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 2875 | Value |= (op & 0xfff); |
| 2876 | // op: I2 |
| 2877 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 2, Fixups, STI); |
| 2878 | Value |= (op & 0xff) << 16; |
| 2879 | break; |
| 2880 | } |
| 2881 | case SystemZ::LPSWEY: { |
| 2882 | // op: B1 |
| 2883 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2884 | Value |= (op & 0xf) << 28; |
| 2885 | // op: D1 |
| 2886 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 1, Fixups, STI); |
| 2887 | Value |= (op & 0xfff) << 16; |
| 2888 | Value |= (op & 0xff000) >> 4; |
| 2889 | break; |
| 2890 | } |
| 2891 | case SystemZ::AGSI: |
| 2892 | case SystemZ::ALGSI: |
| 2893 | case SystemZ::ALSI: |
| 2894 | case SystemZ::ASI: { |
| 2895 | // op: B1 |
| 2896 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2897 | Value |= (op & 0xf) << 28; |
| 2898 | // op: D1 |
| 2899 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 1, Fixups, STI); |
| 2900 | Value |= (op & 0xfff) << 16; |
| 2901 | Value |= (op & 0xff000) >> 4; |
| 2902 | // op: I2 |
| 2903 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, OpNum: 2, Fixups, STI); |
| 2904 | Value |= (op & 0xff) << 32; |
| 2905 | break; |
| 2906 | } |
| 2907 | case SystemZ::CLIY: |
| 2908 | case SystemZ::MVIY: |
| 2909 | case SystemZ::NIY: |
| 2910 | case SystemZ::OIY: |
| 2911 | case SystemZ::TMY: |
| 2912 | case SystemZ::XIY: { |
| 2913 | // op: B1 |
| 2914 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2915 | Value |= (op & 0xf) << 28; |
| 2916 | // op: D1 |
| 2917 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 1, Fixups, STI); |
| 2918 | Value |= (op & 0xfff) << 16; |
| 2919 | Value |= (op & 0xff000) >> 4; |
| 2920 | // op: I2 |
| 2921 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 2, Fixups, STI); |
| 2922 | Value |= (op & 0xff) << 32; |
| 2923 | break; |
| 2924 | } |
| 2925 | case SystemZ::LASP: |
| 2926 | case SystemZ::MVCDK: |
| 2927 | case SystemZ::MVCRL: |
| 2928 | case SystemZ::MVCSK: |
| 2929 | case SystemZ::STRAG: |
| 2930 | case SystemZ::TPROT: { |
| 2931 | // op: B1 |
| 2932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2933 | Value |= (op & 0xf) << 28; |
| 2934 | // op: D1 |
| 2935 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 2936 | Value |= (op & 0xfff) << 16; |
| 2937 | // op: B2 |
| 2938 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2939 | Value |= (op & 0xf) << 12; |
| 2940 | // op: D2 |
| 2941 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 2942 | Value |= (op & 0xfff); |
| 2943 | break; |
| 2944 | } |
| 2945 | case SystemZ::PKA: |
| 2946 | case SystemZ::PKU: { |
| 2947 | // op: B1 |
| 2948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2949 | Value |= (op & 0xf) << 28; |
| 2950 | // op: D1 |
| 2951 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 2952 | Value |= (op & 0xfff) << 16; |
| 2953 | // op: B2 |
| 2954 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2955 | Value |= (op & 0xf) << 12; |
| 2956 | // op: D2 |
| 2957 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 2958 | Value |= (op & 0xfff); |
| 2959 | // op: L2 |
| 2960 | op = getLenEncoding<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 2961 | Value |= (op & 0xff) << 32; |
| 2962 | break; |
| 2963 | } |
| 2964 | case SystemZ::CSST: |
| 2965 | case SystemZ::ECTG: |
| 2966 | case SystemZ::MVCOS: { |
| 2967 | // op: B1 |
| 2968 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2969 | Value |= (op & 0xf) << 28; |
| 2970 | // op: D1 |
| 2971 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 2972 | Value |= (op & 0xfff) << 16; |
| 2973 | // op: B2 |
| 2974 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2975 | Value |= (op & 0xf) << 12; |
| 2976 | // op: D2 |
| 2977 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 2978 | Value |= (op & 0xfff); |
| 2979 | // op: R3 |
| 2980 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 2981 | Value |= (op & 0xf) << 36; |
| 2982 | break; |
| 2983 | } |
| 2984 | case SystemZ::CGHSI: |
| 2985 | case SystemZ::CHHSI: |
| 2986 | case SystemZ::CHSI: |
| 2987 | case SystemZ::MVGHI: |
| 2988 | case SystemZ::MVHHI: |
| 2989 | case SystemZ::MVHI: { |
| 2990 | // op: B1 |
| 2991 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2992 | Value |= (op & 0xf) << 28; |
| 2993 | // op: D1 |
| 2994 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 2995 | Value |= (op & 0xfff) << 16; |
| 2996 | // op: I2 |
| 2997 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 2998 | Value |= (op & 0xffff); |
| 2999 | break; |
| 3000 | } |
| 3001 | case SystemZ::CLFHSI: |
| 3002 | case SystemZ::CLGHSI: |
| 3003 | case SystemZ::CLHHSI: |
| 3004 | case SystemZ::TBEGIN: |
| 3005 | case SystemZ::TBEGINC: { |
| 3006 | // op: B1 |
| 3007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3008 | Value |= (op & 0xf) << 28; |
| 3009 | // op: D1 |
| 3010 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 3011 | Value |= (op & 0xfff) << 16; |
| 3012 | // op: I2 |
| 3013 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 2, Fixups, STI); |
| 3014 | Value |= (op & 0xffff); |
| 3015 | break; |
| 3016 | } |
| 3017 | case SystemZ::TP: { |
| 3018 | // op: B1 |
| 3019 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3020 | Value |= (op & 0xf) << 28; |
| 3021 | // op: D1 |
| 3022 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 3023 | Value |= (op & 0xfff) << 16; |
| 3024 | // op: L1 |
| 3025 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 3026 | Value |= (op & 0xf) << 36; |
| 3027 | break; |
| 3028 | } |
| 3029 | case SystemZ::SRP: { |
| 3030 | // op: B1 |
| 3031 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3032 | Value |= (op & 0xf) << 28; |
| 3033 | // op: D1 |
| 3034 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 3035 | Value |= (op & 0xfff) << 16; |
| 3036 | // op: L1 |
| 3037 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 3038 | Value |= (op & 0xf) << 36; |
| 3039 | // op: B2 |
| 3040 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3041 | Value |= (op & 0xf) << 12; |
| 3042 | // op: D2 |
| 3043 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 3044 | Value |= (op & 0xfff); |
| 3045 | // op: I3 |
| 3046 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 3047 | Value |= (op & 0xf) << 32; |
| 3048 | break; |
| 3049 | } |
| 3050 | case SystemZ::AP: |
| 3051 | case SystemZ::CP: |
| 3052 | case SystemZ::DP: |
| 3053 | case SystemZ::MP: |
| 3054 | case SystemZ::MVO: |
| 3055 | case SystemZ::PACK: |
| 3056 | case SystemZ::SP: |
| 3057 | case SystemZ::UNPK: |
| 3058 | case SystemZ::ZAP: { |
| 3059 | // op: B1 |
| 3060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3061 | Value |= (op & 0xf) << 28; |
| 3062 | // op: D1 |
| 3063 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 3064 | Value |= (op & 0xfff) << 16; |
| 3065 | // op: L1 |
| 3066 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 3067 | Value |= (op & 0xf) << 36; |
| 3068 | // op: B2 |
| 3069 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3070 | Value |= (op & 0xf) << 12; |
| 3071 | // op: D2 |
| 3072 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 3073 | Value |= (op & 0xfff); |
| 3074 | // op: L2 |
| 3075 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 3076 | Value |= (op & 0xf) << 32; |
| 3077 | break; |
| 3078 | } |
| 3079 | case SystemZ::CLC: |
| 3080 | case SystemZ::ED: |
| 3081 | case SystemZ::EDMK: |
| 3082 | case SystemZ::MVC: |
| 3083 | case SystemZ::MVCIN: |
| 3084 | case SystemZ::MVN: |
| 3085 | case SystemZ::MVZ: |
| 3086 | case SystemZ::NC: |
| 3087 | case SystemZ::OC: |
| 3088 | case SystemZ::TR: |
| 3089 | case SystemZ::TRT: |
| 3090 | case SystemZ::TRTR: |
| 3091 | case SystemZ::UNPKA: |
| 3092 | case SystemZ::UNPKU: |
| 3093 | case SystemZ::XC: { |
| 3094 | // op: B1 |
| 3095 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3096 | Value |= (op & 0xf) << 28; |
| 3097 | // op: D1 |
| 3098 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 3099 | Value |= (op & 0xfff) << 16; |
| 3100 | // op: L1 |
| 3101 | op = getLenEncoding<SystemZ::FK_390_U8Imm>(MI, OpNum: 2, Fixups, STI); |
| 3102 | Value |= (op & 0xff) << 32; |
| 3103 | // op: B2 |
| 3104 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3105 | Value |= (op & 0xf) << 12; |
| 3106 | // op: D2 |
| 3107 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 3108 | Value |= (op & 0xfff); |
| 3109 | break; |
| 3110 | } |
| 3111 | case SystemZ::CAL: |
| 3112 | case SystemZ::CALG: |
| 3113 | case SystemZ::CALGF: |
| 3114 | case SystemZ::LPD: |
| 3115 | case SystemZ::LPDG: { |
| 3116 | // op: B1 |
| 3117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3118 | Value |= (op & 0xf) << 28; |
| 3119 | // op: D1 |
| 3120 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 3121 | Value |= (op & 0xfff) << 16; |
| 3122 | // op: B2 |
| 3123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3124 | Value |= (op & 0xf) << 12; |
| 3125 | // op: D2 |
| 3126 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 3127 | Value |= (op & 0xfff); |
| 3128 | // op: R3 |
| 3129 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3130 | Value |= (op & 0xf) << 36; |
| 3131 | break; |
| 3132 | } |
| 3133 | case SystemZ::CFC: |
| 3134 | case SystemZ::LBEAR: |
| 3135 | case SystemZ::LCCTL: |
| 3136 | case SystemZ::LFAS: |
| 3137 | case SystemZ::LFPC: |
| 3138 | case SystemZ::LPCTL: |
| 3139 | case SystemZ::LPP: |
| 3140 | case SystemZ::LPSW: |
| 3141 | case SystemZ::LPSWE: |
| 3142 | case SystemZ::LSCTL: |
| 3143 | case SystemZ::MSCH: |
| 3144 | case SystemZ::PC: |
| 3145 | case SystemZ::QCTRI: |
| 3146 | case SystemZ::QPACI: |
| 3147 | case SystemZ::QSI: |
| 3148 | case SystemZ::RP: |
| 3149 | case SystemZ::SAC: |
| 3150 | case SystemZ::SACF: |
| 3151 | case SystemZ::SCK: |
| 3152 | case SystemZ::SCKC: |
| 3153 | case SystemZ::SIE: |
| 3154 | case SystemZ::SIGA: |
| 3155 | case SystemZ::SPKA: |
| 3156 | case SystemZ::SPT: |
| 3157 | case SystemZ::SPX: |
| 3158 | case SystemZ::SRNM: |
| 3159 | case SystemZ::SRNMB: |
| 3160 | case SystemZ::SRNMT: |
| 3161 | case SystemZ::SSCH: |
| 3162 | case SystemZ::SSM: |
| 3163 | case SystemZ::STAP: |
| 3164 | case SystemZ::STBEAR: |
| 3165 | case SystemZ::STCK: |
| 3166 | case SystemZ::STCKC: |
| 3167 | case SystemZ::STCKE: |
| 3168 | case SystemZ::STCKF: |
| 3169 | case SystemZ::STCPS: |
| 3170 | case SystemZ::STCRW: |
| 3171 | case SystemZ::STFL: |
| 3172 | case SystemZ::STFLE: |
| 3173 | case SystemZ::STFPC: |
| 3174 | case SystemZ::STIDP: |
| 3175 | case SystemZ::STPT: |
| 3176 | case SystemZ::STPX: |
| 3177 | case SystemZ::STSCH: |
| 3178 | case SystemZ::STSI: |
| 3179 | case SystemZ::TABORT: |
| 3180 | case SystemZ::TPI: |
| 3181 | case SystemZ::TRAP4: |
| 3182 | case SystemZ::TS: |
| 3183 | case SystemZ::TSCH: { |
| 3184 | // op: B2 |
| 3185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3186 | Value |= (op & 0xf) << 12; |
| 3187 | // op: D2 |
| 3188 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 3189 | Value |= (op & 0xfff); |
| 3190 | break; |
| 3191 | } |
| 3192 | case SystemZ::NIAI: { |
| 3193 | // op: I1 |
| 3194 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 0, Fixups, STI); |
| 3195 | Value |= (op & 0xf) << 4; |
| 3196 | // op: I2 |
| 3197 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 3198 | Value |= (op & 0xf); |
| 3199 | break; |
| 3200 | } |
| 3201 | case SystemZ::SVC: { |
| 3202 | // op: I1 |
| 3203 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 0, Fixups, STI); |
| 3204 | Value |= (op & 0xff); |
| 3205 | break; |
| 3206 | } |
| 3207 | case SystemZ::BRCAsm: { |
| 3208 | // op: M1 |
| 3209 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 0, Fixups, STI); |
| 3210 | Value |= (op & 0xf) << 20; |
| 3211 | // op: RI2 |
| 3212 | op = getPC16DBLEncoding(MI, OpNum: 1, Fixups, STI); |
| 3213 | Value |= (op & 0xffff); |
| 3214 | break; |
| 3215 | } |
| 3216 | case SystemZ::BCAsm: { |
| 3217 | // op: M1 |
| 3218 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 0, Fixups, STI); |
| 3219 | Value |= (op & 0xf) << 20; |
| 3220 | // op: X2 |
| 3221 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3222 | Value |= (op & 0xf) << 16; |
| 3223 | // op: B2 |
| 3224 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3225 | Value |= (op & 0xf) << 12; |
| 3226 | // op: D2 |
| 3227 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 3228 | Value |= (op & 0xfff); |
| 3229 | break; |
| 3230 | } |
| 3231 | case SystemZ::BPRP: { |
| 3232 | // op: M1 |
| 3233 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 0, Fixups, STI); |
| 3234 | Value |= (op & 0xf) << 36; |
| 3235 | // op: RI2 |
| 3236 | op = getPC12DBLBPPEncoding(MI, OpNum: 1, Fixups, STI); |
| 3237 | Value |= (op & 0xfff) << 24; |
| 3238 | // op: RI3 |
| 3239 | op = getPC24DBLBPPEncoding(MI, OpNum: 2, Fixups, STI); |
| 3240 | Value |= (op & 0xffffff); |
| 3241 | break; |
| 3242 | } |
| 3243 | case SystemZ::BPP: { |
| 3244 | // op: M1 |
| 3245 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 0, Fixups, STI); |
| 3246 | Value |= (op & 0xf) << 36; |
| 3247 | // op: RI2 |
| 3248 | op = getPC16DBLBPPEncoding(MI, OpNum: 1, Fixups, STI); |
| 3249 | Value |= (op & 0xffff); |
| 3250 | // op: B3 |
| 3251 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3252 | Value |= (op & 0xf) << 28; |
| 3253 | // op: D3 |
| 3254 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3255 | Value |= (op & 0xfff) << 16; |
| 3256 | break; |
| 3257 | } |
| 3258 | case SystemZ::BRCLAsm: |
| 3259 | case SystemZ::PFDRL: { |
| 3260 | // op: M1 |
| 3261 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 0, Fixups, STI); |
| 3262 | Value |= (op & 0xf) << 36; |
| 3263 | // op: RI2 |
| 3264 | op = getPC32DBLEncoding(MI, OpNum: 1, Fixups, STI); |
| 3265 | Value |= (op & 0xffffffff); |
| 3266 | break; |
| 3267 | } |
| 3268 | case SystemZ::BICAsm: |
| 3269 | case SystemZ::PFD: { |
| 3270 | // op: M1 |
| 3271 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 0, Fixups, STI); |
| 3272 | Value |= (op & 0xf) << 36; |
| 3273 | // op: X2 |
| 3274 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3275 | Value |= (op & 0xf) << 32; |
| 3276 | // op: B2 |
| 3277 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3278 | Value |= (op & 0xf) << 28; |
| 3279 | // op: D2 |
| 3280 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 2, Fixups, STI); |
| 3281 | Value |= (op & 0xfff) << 16; |
| 3282 | Value |= (op & 0xff000) >> 4; |
| 3283 | break; |
| 3284 | } |
| 3285 | case SystemZ::BRC: { |
| 3286 | // op: M1 |
| 3287 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3288 | Value |= (op & 0xf) << 20; |
| 3289 | // op: RI2 |
| 3290 | op = getPC16DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 3291 | Value |= (op & 0xffff); |
| 3292 | break; |
| 3293 | } |
| 3294 | case SystemZ::BC: { |
| 3295 | // op: M1 |
| 3296 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3297 | Value |= (op & 0xf) << 20; |
| 3298 | // op: X2 |
| 3299 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3300 | Value |= (op & 0xf) << 16; |
| 3301 | // op: B2 |
| 3302 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3303 | Value |= (op & 0xf) << 12; |
| 3304 | // op: D2 |
| 3305 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3306 | Value |= (op & 0xfff); |
| 3307 | break; |
| 3308 | } |
| 3309 | case SystemZ::BRCL: { |
| 3310 | // op: M1 |
| 3311 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3312 | Value |= (op & 0xf) << 36; |
| 3313 | // op: RI2 |
| 3314 | op = getPC32DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 3315 | Value |= (op & 0xffffffff); |
| 3316 | break; |
| 3317 | } |
| 3318 | case SystemZ::BIC: { |
| 3319 | // op: M1 |
| 3320 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3321 | Value |= (op & 0xf) << 36; |
| 3322 | // op: X2 |
| 3323 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3324 | Value |= (op & 0xf) << 32; |
| 3325 | // op: B2 |
| 3326 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3327 | Value |= (op & 0xf) << 28; |
| 3328 | // op: D2 |
| 3329 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 3330 | Value |= (op & 0xfff) << 16; |
| 3331 | Value |= (op & 0xff000) >> 4; |
| 3332 | break; |
| 3333 | } |
| 3334 | case SystemZ::BCRAsm: { |
| 3335 | // op: R1 |
| 3336 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 0, Fixups, STI); |
| 3337 | Value |= (op & 0xf) << 4; |
| 3338 | // op: R2 |
| 3339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3340 | Value |= (op & 0xf); |
| 3341 | break; |
| 3342 | } |
| 3343 | case SystemZ::CDPT: |
| 3344 | case SystemZ::CDZT: |
| 3345 | case SystemZ::CPDT: |
| 3346 | case SystemZ::CPXT: |
| 3347 | case SystemZ::CXPT: |
| 3348 | case SystemZ::CXZT: |
| 3349 | case SystemZ::CZDT: |
| 3350 | case SystemZ::CZXT: { |
| 3351 | // op: R1 |
| 3352 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3353 | Value |= (op & 0xf) << 12; |
| 3354 | // op: B2 |
| 3355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3356 | Value |= (op & 0xf) << 28; |
| 3357 | // op: D2 |
| 3358 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 3359 | Value |= (op & 0xfff) << 16; |
| 3360 | // op: L2 |
| 3361 | op = getLenEncoding<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 3362 | Value |= (op & 0xff) << 32; |
| 3363 | // op: M3 |
| 3364 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 3365 | Value |= (op & 0xf) << 8; |
| 3366 | break; |
| 3367 | } |
| 3368 | case SystemZ::MY: |
| 3369 | case SystemZ::MYH: |
| 3370 | case SystemZ::MYL: |
| 3371 | case SystemZ::SLDT: |
| 3372 | case SystemZ::SLXT: |
| 3373 | case SystemZ::SRDT: |
| 3374 | case SystemZ::SRXT: { |
| 3375 | // op: R1 |
| 3376 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3377 | Value |= (op & 0xf) << 12; |
| 3378 | // op: R3 |
| 3379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3380 | Value |= (op & 0xf) << 36; |
| 3381 | // op: X2 |
| 3382 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3383 | Value |= (op & 0xf) << 32; |
| 3384 | // op: B2 |
| 3385 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3386 | Value |= (op & 0xf) << 28; |
| 3387 | // op: D2 |
| 3388 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3389 | Value |= (op & 0xfff) << 16; |
| 3390 | break; |
| 3391 | } |
| 3392 | case SystemZ::MYHR: |
| 3393 | case SystemZ::MYLR: |
| 3394 | case SystemZ::MYR: { |
| 3395 | // op: R1 |
| 3396 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3397 | Value |= (op & 0xf) << 12; |
| 3398 | // op: R3 |
| 3399 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3400 | Value |= (op & 0xf) << 4; |
| 3401 | // op: R2 |
| 3402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3403 | Value |= (op & 0xf); |
| 3404 | break; |
| 3405 | } |
| 3406 | case SystemZ::MAD: |
| 3407 | case SystemZ::MADB: |
| 3408 | case SystemZ::MAE: |
| 3409 | case SystemZ::MAEB: |
| 3410 | case SystemZ::MAY: |
| 3411 | case SystemZ::MAYH: |
| 3412 | case SystemZ::MAYL: |
| 3413 | case SystemZ::MSD: |
| 3414 | case SystemZ::MSDB: |
| 3415 | case SystemZ::MSE: |
| 3416 | case SystemZ::MSEB: { |
| 3417 | // op: R1 |
| 3418 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3419 | Value |= (op & 0xf) << 12; |
| 3420 | // op: R3 |
| 3421 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3422 | Value |= (op & 0xf) << 36; |
| 3423 | // op: X2 |
| 3424 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 3425 | Value |= (op & 0xf) << 32; |
| 3426 | // op: B2 |
| 3427 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3428 | Value |= (op & 0xf) << 28; |
| 3429 | // op: D2 |
| 3430 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 3431 | Value |= (op & 0xfff) << 16; |
| 3432 | break; |
| 3433 | } |
| 3434 | case SystemZ::MADBR: |
| 3435 | case SystemZ::MADR: |
| 3436 | case SystemZ::MAEBR: |
| 3437 | case SystemZ::MAER: |
| 3438 | case SystemZ::MAYHR: |
| 3439 | case SystemZ::MAYLR: |
| 3440 | case SystemZ::MAYR: |
| 3441 | case SystemZ::MSDBR: |
| 3442 | case SystemZ::MSDR: |
| 3443 | case SystemZ::MSEBR: |
| 3444 | case SystemZ::MSER: { |
| 3445 | // op: R1 |
| 3446 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3447 | Value |= (op & 0xf) << 12; |
| 3448 | // op: R3 |
| 3449 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3450 | Value |= (op & 0xf) << 4; |
| 3451 | // op: R2 |
| 3452 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3453 | Value |= (op & 0xf); |
| 3454 | break; |
| 3455 | } |
| 3456 | case SystemZ::SLA: |
| 3457 | case SystemZ::SLDA: |
| 3458 | case SystemZ::SLDL: |
| 3459 | case SystemZ::SLL: |
| 3460 | case SystemZ::SRA: |
| 3461 | case SystemZ::SRDA: |
| 3462 | case SystemZ::SRDL: |
| 3463 | case SystemZ::SRL: { |
| 3464 | // op: R1 |
| 3465 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3466 | Value |= (op & 0xf) << 20; |
| 3467 | // op: B2 |
| 3468 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3469 | Value |= (op & 0xf) << 12; |
| 3470 | // op: D2 |
| 3471 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3472 | Value |= (op & 0xfff); |
| 3473 | break; |
| 3474 | } |
| 3475 | case SystemZ::CGHI: |
| 3476 | case SystemZ::CHI: |
| 3477 | case SystemZ::LGHI: |
| 3478 | case SystemZ::LHI: { |
| 3479 | // op: R1 |
| 3480 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3481 | Value |= (op & 0xf) << 20; |
| 3482 | // op: I2 |
| 3483 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 1, Fixups, STI); |
| 3484 | Value |= (op & 0xffff); |
| 3485 | break; |
| 3486 | } |
| 3487 | case SystemZ::AGHI: |
| 3488 | case SystemZ::AHI: |
| 3489 | case SystemZ::MGHI: |
| 3490 | case SystemZ::MHI: { |
| 3491 | // op: R1 |
| 3492 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3493 | Value |= (op & 0xf) << 20; |
| 3494 | // op: I2 |
| 3495 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 3496 | Value |= (op & 0xffff); |
| 3497 | break; |
| 3498 | } |
| 3499 | case SystemZ::LLIHH: |
| 3500 | case SystemZ::LLIHL: |
| 3501 | case SystemZ::LLILH: |
| 3502 | case SystemZ::LLILL: |
| 3503 | case SystemZ::TMHH: |
| 3504 | case SystemZ::TMHL: |
| 3505 | case SystemZ::TMLH: |
| 3506 | case SystemZ::TMLL: { |
| 3507 | // op: R1 |
| 3508 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3509 | Value |= (op & 0xf) << 20; |
| 3510 | // op: I2 |
| 3511 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 1, Fixups, STI); |
| 3512 | Value |= (op & 0xffff); |
| 3513 | break; |
| 3514 | } |
| 3515 | case SystemZ::IIHH: |
| 3516 | case SystemZ::IIHL: |
| 3517 | case SystemZ::IILH: |
| 3518 | case SystemZ::IILL: |
| 3519 | case SystemZ::NIHH: |
| 3520 | case SystemZ::NIHL: |
| 3521 | case SystemZ::NILH: |
| 3522 | case SystemZ::NILL: |
| 3523 | case SystemZ::OIHH: |
| 3524 | case SystemZ::OIHL: |
| 3525 | case SystemZ::OILH: |
| 3526 | case SystemZ::OILL: { |
| 3527 | // op: R1 |
| 3528 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3529 | Value |= (op & 0xf) << 20; |
| 3530 | // op: I2 |
| 3531 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 2, Fixups, STI); |
| 3532 | Value |= (op & 0xffff); |
| 3533 | break; |
| 3534 | } |
| 3535 | case SystemZ::CLM: |
| 3536 | case SystemZ::STCM: { |
| 3537 | // op: R1 |
| 3538 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3539 | Value |= (op & 0xf) << 20; |
| 3540 | // op: M3 |
| 3541 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 3542 | Value |= (op & 0xf) << 16; |
| 3543 | // op: B2 |
| 3544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3545 | Value |= (op & 0xf) << 12; |
| 3546 | // op: D2 |
| 3547 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3548 | Value |= (op & 0xfff); |
| 3549 | break; |
| 3550 | } |
| 3551 | case SystemZ::ICM: { |
| 3552 | // op: R1 |
| 3553 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3554 | Value |= (op & 0xf) << 20; |
| 3555 | // op: M3 |
| 3556 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 3557 | Value |= (op & 0xf) << 16; |
| 3558 | // op: B2 |
| 3559 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3560 | Value |= (op & 0xf) << 12; |
| 3561 | // op: D2 |
| 3562 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 3563 | Value |= (op & 0xfff); |
| 3564 | break; |
| 3565 | } |
| 3566 | case SystemZ::DIAG: |
| 3567 | case SystemZ::LAM: |
| 3568 | case SystemZ::LCTL: |
| 3569 | case SystemZ::LM: |
| 3570 | case SystemZ::SIGP: |
| 3571 | case SystemZ::STAM: |
| 3572 | case SystemZ::STCTL: |
| 3573 | case SystemZ::STM: |
| 3574 | case SystemZ::TRACE: { |
| 3575 | // op: R1 |
| 3576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3577 | Value |= (op & 0xf) << 20; |
| 3578 | // op: R3 |
| 3579 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3580 | Value |= (op & 0xf) << 16; |
| 3581 | // op: B2 |
| 3582 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3583 | Value |= (op & 0xf) << 12; |
| 3584 | // op: D2 |
| 3585 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3586 | Value |= (op & 0xfff); |
| 3587 | break; |
| 3588 | } |
| 3589 | case SystemZ::CLCLE: |
| 3590 | case SystemZ::MVCLE: { |
| 3591 | // op: R1 |
| 3592 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3593 | Value |= (op & 0xf) << 20; |
| 3594 | // op: R3 |
| 3595 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3596 | Value |= (op & 0xf) << 16; |
| 3597 | // op: B2 |
| 3598 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3599 | Value |= (op & 0xf) << 12; |
| 3600 | // op: D2 |
| 3601 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 5, Fixups, STI); |
| 3602 | Value |= (op & 0xfff); |
| 3603 | break; |
| 3604 | } |
| 3605 | case SystemZ::BXH: |
| 3606 | case SystemZ::BXLE: |
| 3607 | case SystemZ::CDS: |
| 3608 | case SystemZ::CS: { |
| 3609 | // op: R1 |
| 3610 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3611 | Value |= (op & 0xf) << 20; |
| 3612 | // op: R3 |
| 3613 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3614 | Value |= (op & 0xf) << 16; |
| 3615 | // op: B2 |
| 3616 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3617 | Value |= (op & 0xf) << 12; |
| 3618 | // op: D2 |
| 3619 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 3620 | Value |= (op & 0xfff); |
| 3621 | break; |
| 3622 | } |
| 3623 | case SystemZ::BRXH: |
| 3624 | case SystemZ::BRXLE: { |
| 3625 | // op: R1 |
| 3626 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3627 | Value |= (op & 0xf) << 20; |
| 3628 | // op: R3 |
| 3629 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3630 | Value |= (op & 0xf) << 16; |
| 3631 | // op: RI2 |
| 3632 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 3633 | Value |= (op & 0xffff); |
| 3634 | break; |
| 3635 | } |
| 3636 | case SystemZ::BRCT: |
| 3637 | case SystemZ::BRCTG: { |
| 3638 | // op: R1 |
| 3639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3640 | Value |= (op & 0xf) << 20; |
| 3641 | // op: RI2 |
| 3642 | op = getPC16DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 3643 | Value |= (op & 0xffff); |
| 3644 | break; |
| 3645 | } |
| 3646 | case SystemZ::BRAS: { |
| 3647 | // op: R1 |
| 3648 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3649 | Value |= (op & 0xf) << 20; |
| 3650 | // op: RI2 |
| 3651 | op = getPC16DBLTLSEncoding(MI, OpNum: 1, Fixups, STI); |
| 3652 | Value |= (op & 0xffff); |
| 3653 | break; |
| 3654 | } |
| 3655 | case SystemZ::BAL: |
| 3656 | case SystemZ::BAS: |
| 3657 | case SystemZ::C: |
| 3658 | case SystemZ::CD: |
| 3659 | case SystemZ::CE: |
| 3660 | case SystemZ::CH: |
| 3661 | case SystemZ::CL: |
| 3662 | case SystemZ::CVD: |
| 3663 | case SystemZ::EX: |
| 3664 | case SystemZ::L: |
| 3665 | case SystemZ::LA: |
| 3666 | case SystemZ::LAE: |
| 3667 | case SystemZ::LD: |
| 3668 | case SystemZ::LE: |
| 3669 | case SystemZ::LE16: |
| 3670 | case SystemZ::LH: |
| 3671 | case SystemZ::LRA: |
| 3672 | case SystemZ::ST: |
| 3673 | case SystemZ::STC: |
| 3674 | case SystemZ::STD: |
| 3675 | case SystemZ::STE: |
| 3676 | case SystemZ::STE16: |
| 3677 | case SystemZ::STH: { |
| 3678 | // op: R1 |
| 3679 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3680 | Value |= (op & 0xf) << 20; |
| 3681 | // op: X2 |
| 3682 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3683 | Value |= (op & 0xf) << 16; |
| 3684 | // op: B2 |
| 3685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3686 | Value |= (op & 0xf) << 12; |
| 3687 | // op: D2 |
| 3688 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 3689 | Value |= (op & 0xfff); |
| 3690 | break; |
| 3691 | } |
| 3692 | case SystemZ::A: |
| 3693 | case SystemZ::AD: |
| 3694 | case SystemZ::AE: |
| 3695 | case SystemZ::AH: |
| 3696 | case SystemZ::AL: |
| 3697 | case SystemZ::AU: |
| 3698 | case SystemZ::AW: |
| 3699 | case SystemZ::BCT: |
| 3700 | case SystemZ::CVB: |
| 3701 | case SystemZ::D: |
| 3702 | case SystemZ::DD: |
| 3703 | case SystemZ::DE: |
| 3704 | case SystemZ::IC: |
| 3705 | case SystemZ::IC32: |
| 3706 | case SystemZ::M: |
| 3707 | case SystemZ::MD: |
| 3708 | case SystemZ::MDE: |
| 3709 | case SystemZ::ME: |
| 3710 | case SystemZ::MH: |
| 3711 | case SystemZ::MS: |
| 3712 | case SystemZ::MXD: |
| 3713 | case SystemZ::N: |
| 3714 | case SystemZ::O: |
| 3715 | case SystemZ::S: |
| 3716 | case SystemZ::SD: |
| 3717 | case SystemZ::SE: |
| 3718 | case SystemZ::SH: |
| 3719 | case SystemZ::SL: |
| 3720 | case SystemZ::SU: |
| 3721 | case SystemZ::SW: |
| 3722 | case SystemZ::X: { |
| 3723 | // op: R1 |
| 3724 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3725 | Value |= (op & 0xf) << 20; |
| 3726 | // op: X2 |
| 3727 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3728 | Value |= (op & 0xf) << 16; |
| 3729 | // op: B2 |
| 3730 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3731 | Value |= (op & 0xf) << 12; |
| 3732 | // op: D2 |
| 3733 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3734 | Value |= (op & 0xfff); |
| 3735 | break; |
| 3736 | } |
| 3737 | case SystemZ::CLGTAsmE: |
| 3738 | case SystemZ::CLGTAsmH: |
| 3739 | case SystemZ::CLGTAsmHE: |
| 3740 | case SystemZ::CLGTAsmL: |
| 3741 | case SystemZ::CLGTAsmLE: |
| 3742 | case SystemZ::CLGTAsmLH: |
| 3743 | case SystemZ::CLGTAsmNE: |
| 3744 | case SystemZ::CLGTAsmNH: |
| 3745 | case SystemZ::CLGTAsmNHE: |
| 3746 | case SystemZ::CLGTAsmNL: |
| 3747 | case SystemZ::CLGTAsmNLE: |
| 3748 | case SystemZ::CLGTAsmNLH: |
| 3749 | case SystemZ::CLTAsmE: |
| 3750 | case SystemZ::CLTAsmH: |
| 3751 | case SystemZ::CLTAsmHE: |
| 3752 | case SystemZ::CLTAsmL: |
| 3753 | case SystemZ::CLTAsmLE: |
| 3754 | case SystemZ::CLTAsmLH: |
| 3755 | case SystemZ::CLTAsmNE: |
| 3756 | case SystemZ::CLTAsmNH: |
| 3757 | case SystemZ::CLTAsmNHE: |
| 3758 | case SystemZ::CLTAsmNL: |
| 3759 | case SystemZ::CLTAsmNLE: |
| 3760 | case SystemZ::CLTAsmNLH: |
| 3761 | case SystemZ::STOCAsmE: |
| 3762 | case SystemZ::STOCAsmH: |
| 3763 | case SystemZ::STOCAsmHE: |
| 3764 | case SystemZ::STOCAsmL: |
| 3765 | case SystemZ::STOCAsmLE: |
| 3766 | case SystemZ::STOCAsmLH: |
| 3767 | case SystemZ::STOCAsmM: |
| 3768 | case SystemZ::STOCAsmNE: |
| 3769 | case SystemZ::STOCAsmNH: |
| 3770 | case SystemZ::STOCAsmNHE: |
| 3771 | case SystemZ::STOCAsmNL: |
| 3772 | case SystemZ::STOCAsmNLE: |
| 3773 | case SystemZ::STOCAsmNLH: |
| 3774 | case SystemZ::STOCAsmNM: |
| 3775 | case SystemZ::STOCAsmNO: |
| 3776 | case SystemZ::STOCAsmNP: |
| 3777 | case SystemZ::STOCAsmNZ: |
| 3778 | case SystemZ::STOCAsmO: |
| 3779 | case SystemZ::STOCAsmP: |
| 3780 | case SystemZ::STOCAsmZ: |
| 3781 | case SystemZ::STOCFHAsmE: |
| 3782 | case SystemZ::STOCFHAsmH: |
| 3783 | case SystemZ::STOCFHAsmHE: |
| 3784 | case SystemZ::STOCFHAsmL: |
| 3785 | case SystemZ::STOCFHAsmLE: |
| 3786 | case SystemZ::STOCFHAsmLH: |
| 3787 | case SystemZ::STOCFHAsmM: |
| 3788 | case SystemZ::STOCFHAsmNE: |
| 3789 | case SystemZ::STOCFHAsmNH: |
| 3790 | case SystemZ::STOCFHAsmNHE: |
| 3791 | case SystemZ::STOCFHAsmNL: |
| 3792 | case SystemZ::STOCFHAsmNLE: |
| 3793 | case SystemZ::STOCFHAsmNLH: |
| 3794 | case SystemZ::STOCFHAsmNM: |
| 3795 | case SystemZ::STOCFHAsmNO: |
| 3796 | case SystemZ::STOCFHAsmNP: |
| 3797 | case SystemZ::STOCFHAsmNZ: |
| 3798 | case SystemZ::STOCFHAsmO: |
| 3799 | case SystemZ::STOCFHAsmP: |
| 3800 | case SystemZ::STOCFHAsmZ: |
| 3801 | case SystemZ::STOCGAsmE: |
| 3802 | case SystemZ::STOCGAsmH: |
| 3803 | case SystemZ::STOCGAsmHE: |
| 3804 | case SystemZ::STOCGAsmL: |
| 3805 | case SystemZ::STOCGAsmLE: |
| 3806 | case SystemZ::STOCGAsmLH: |
| 3807 | case SystemZ::STOCGAsmM: |
| 3808 | case SystemZ::STOCGAsmNE: |
| 3809 | case SystemZ::STOCGAsmNH: |
| 3810 | case SystemZ::STOCGAsmNHE: |
| 3811 | case SystemZ::STOCGAsmNL: |
| 3812 | case SystemZ::STOCGAsmNLE: |
| 3813 | case SystemZ::STOCGAsmNLH: |
| 3814 | case SystemZ::STOCGAsmNM: |
| 3815 | case SystemZ::STOCGAsmNO: |
| 3816 | case SystemZ::STOCGAsmNP: |
| 3817 | case SystemZ::STOCGAsmNZ: |
| 3818 | case SystemZ::STOCGAsmO: |
| 3819 | case SystemZ::STOCGAsmP: |
| 3820 | case SystemZ::STOCGAsmZ: { |
| 3821 | // op: R1 |
| 3822 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3823 | Value |= (op & 0xf) << 36; |
| 3824 | // op: B2 |
| 3825 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3826 | Value |= (op & 0xf) << 28; |
| 3827 | // op: D2 |
| 3828 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 2, Fixups, STI); |
| 3829 | Value |= (op & 0xfff) << 16; |
| 3830 | Value |= (op & 0xff000) >> 4; |
| 3831 | break; |
| 3832 | } |
| 3833 | case SystemZ::PLO: { |
| 3834 | // op: R1 |
| 3835 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3836 | Value |= (op & 0xf) << 36; |
| 3837 | // op: B2 |
| 3838 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3839 | Value |= (op & 0xf) << 28; |
| 3840 | // op: D2 |
| 3841 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 3842 | Value |= (op & 0xfff) << 16; |
| 3843 | // op: R3 |
| 3844 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3845 | Value |= (op & 0xf) << 32; |
| 3846 | // op: B4 |
| 3847 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3848 | Value |= (op & 0xf) << 12; |
| 3849 | // op: D4 |
| 3850 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 5, Fixups, STI); |
| 3851 | Value |= (op & 0xfff); |
| 3852 | break; |
| 3853 | } |
| 3854 | case SystemZ::LOCAsmE: |
| 3855 | case SystemZ::LOCAsmH: |
| 3856 | case SystemZ::LOCAsmHE: |
| 3857 | case SystemZ::LOCAsmL: |
| 3858 | case SystemZ::LOCAsmLE: |
| 3859 | case SystemZ::LOCAsmLH: |
| 3860 | case SystemZ::LOCAsmM: |
| 3861 | case SystemZ::LOCAsmNE: |
| 3862 | case SystemZ::LOCAsmNH: |
| 3863 | case SystemZ::LOCAsmNHE: |
| 3864 | case SystemZ::LOCAsmNL: |
| 3865 | case SystemZ::LOCAsmNLE: |
| 3866 | case SystemZ::LOCAsmNLH: |
| 3867 | case SystemZ::LOCAsmNM: |
| 3868 | case SystemZ::LOCAsmNO: |
| 3869 | case SystemZ::LOCAsmNP: |
| 3870 | case SystemZ::LOCAsmNZ: |
| 3871 | case SystemZ::LOCAsmO: |
| 3872 | case SystemZ::LOCAsmP: |
| 3873 | case SystemZ::LOCAsmZ: |
| 3874 | case SystemZ::LOCFHAsmE: |
| 3875 | case SystemZ::LOCFHAsmH: |
| 3876 | case SystemZ::LOCFHAsmHE: |
| 3877 | case SystemZ::LOCFHAsmL: |
| 3878 | case SystemZ::LOCFHAsmLE: |
| 3879 | case SystemZ::LOCFHAsmLH: |
| 3880 | case SystemZ::LOCFHAsmM: |
| 3881 | case SystemZ::LOCFHAsmNE: |
| 3882 | case SystemZ::LOCFHAsmNH: |
| 3883 | case SystemZ::LOCFHAsmNHE: |
| 3884 | case SystemZ::LOCFHAsmNL: |
| 3885 | case SystemZ::LOCFHAsmNLE: |
| 3886 | case SystemZ::LOCFHAsmNLH: |
| 3887 | case SystemZ::LOCFHAsmNM: |
| 3888 | case SystemZ::LOCFHAsmNO: |
| 3889 | case SystemZ::LOCFHAsmNP: |
| 3890 | case SystemZ::LOCFHAsmNZ: |
| 3891 | case SystemZ::LOCFHAsmO: |
| 3892 | case SystemZ::LOCFHAsmP: |
| 3893 | case SystemZ::LOCFHAsmZ: |
| 3894 | case SystemZ::LOCGAsmE: |
| 3895 | case SystemZ::LOCGAsmH: |
| 3896 | case SystemZ::LOCGAsmHE: |
| 3897 | case SystemZ::LOCGAsmL: |
| 3898 | case SystemZ::LOCGAsmLE: |
| 3899 | case SystemZ::LOCGAsmLH: |
| 3900 | case SystemZ::LOCGAsmM: |
| 3901 | case SystemZ::LOCGAsmNE: |
| 3902 | case SystemZ::LOCGAsmNH: |
| 3903 | case SystemZ::LOCGAsmNHE: |
| 3904 | case SystemZ::LOCGAsmNL: |
| 3905 | case SystemZ::LOCGAsmNLE: |
| 3906 | case SystemZ::LOCGAsmNLH: |
| 3907 | case SystemZ::LOCGAsmNM: |
| 3908 | case SystemZ::LOCGAsmNO: |
| 3909 | case SystemZ::LOCGAsmNP: |
| 3910 | case SystemZ::LOCGAsmNZ: |
| 3911 | case SystemZ::LOCGAsmO: |
| 3912 | case SystemZ::LOCGAsmP: |
| 3913 | case SystemZ::LOCGAsmZ: { |
| 3914 | // op: R1 |
| 3915 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3916 | Value |= (op & 0xf) << 36; |
| 3917 | // op: B2 |
| 3918 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3919 | Value |= (op & 0xf) << 28; |
| 3920 | // op: D2 |
| 3921 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 3922 | Value |= (op & 0xfff) << 16; |
| 3923 | Value |= (op & 0xff000) >> 4; |
| 3924 | break; |
| 3925 | } |
| 3926 | case SystemZ::LMD: { |
| 3927 | // op: R1 |
| 3928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3929 | Value |= (op & 0xf) << 36; |
| 3930 | // op: B2 |
| 3931 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3932 | Value |= (op & 0xf) << 28; |
| 3933 | // op: D2 |
| 3934 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3935 | Value |= (op & 0xfff) << 16; |
| 3936 | // op: R3 |
| 3937 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3938 | Value |= (op & 0xf) << 32; |
| 3939 | // op: B4 |
| 3940 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3941 | Value |= (op & 0xf) << 12; |
| 3942 | // op: D4 |
| 3943 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 5, Fixups, STI); |
| 3944 | Value |= (op & 0xfff); |
| 3945 | break; |
| 3946 | } |
| 3947 | case SystemZ::VLGVB: |
| 3948 | case SystemZ::VLGVF: |
| 3949 | case SystemZ::VLGVG: |
| 3950 | case SystemZ::VLGVH: { |
| 3951 | // op: R1 |
| 3952 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3953 | Value |= (op & 0xf) << 36; |
| 3954 | // op: B2 |
| 3955 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3956 | Value |= (op & 0xf) << 28; |
| 3957 | // op: D2 |
| 3958 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3959 | Value |= (op & 0xfff) << 16; |
| 3960 | // op: V3 |
| 3961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3962 | Value |= (op & 0xf) << 32; |
| 3963 | Value |= (op & 0x10) << 6; |
| 3964 | break; |
| 3965 | } |
| 3966 | case SystemZ::VLGV: { |
| 3967 | // op: R1 |
| 3968 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3969 | Value |= (op & 0xf) << 36; |
| 3970 | // op: B2 |
| 3971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3972 | Value |= (op & 0xf) << 28; |
| 3973 | // op: D2 |
| 3974 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 3975 | Value |= (op & 0xfff) << 16; |
| 3976 | // op: V3 |
| 3977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3978 | Value |= (op & 0xf) << 32; |
| 3979 | Value |= (op & 0x10) << 6; |
| 3980 | // op: M4 |
| 3981 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 3982 | Value |= (op & 0xf) << 12; |
| 3983 | break; |
| 3984 | } |
| 3985 | case SystemZ::CGITAsmE: |
| 3986 | case SystemZ::CGITAsmH: |
| 3987 | case SystemZ::CGITAsmHE: |
| 3988 | case SystemZ::CGITAsmL: |
| 3989 | case SystemZ::CGITAsmLE: |
| 3990 | case SystemZ::CGITAsmLH: |
| 3991 | case SystemZ::CGITAsmNE: |
| 3992 | case SystemZ::CGITAsmNH: |
| 3993 | case SystemZ::CGITAsmNHE: |
| 3994 | case SystemZ::CGITAsmNL: |
| 3995 | case SystemZ::CGITAsmNLE: |
| 3996 | case SystemZ::CGITAsmNLH: |
| 3997 | case SystemZ::CITAsmE: |
| 3998 | case SystemZ::CITAsmH: |
| 3999 | case SystemZ::CITAsmHE: |
| 4000 | case SystemZ::CITAsmL: |
| 4001 | case SystemZ::CITAsmLE: |
| 4002 | case SystemZ::CITAsmLH: |
| 4003 | case SystemZ::CITAsmNE: |
| 4004 | case SystemZ::CITAsmNH: |
| 4005 | case SystemZ::CITAsmNHE: |
| 4006 | case SystemZ::CITAsmNL: |
| 4007 | case SystemZ::CITAsmNLE: |
| 4008 | case SystemZ::CITAsmNLH: { |
| 4009 | // op: R1 |
| 4010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4011 | Value |= (op & 0xf) << 36; |
| 4012 | // op: I2 |
| 4013 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 1, Fixups, STI); |
| 4014 | Value |= (op & 0xffff) << 16; |
| 4015 | break; |
| 4016 | } |
| 4017 | case SystemZ::CGITAsm: |
| 4018 | case SystemZ::CITAsm: { |
| 4019 | // op: R1 |
| 4020 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4021 | Value |= (op & 0xf) << 36; |
| 4022 | // op: I2 |
| 4023 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 1, Fixups, STI); |
| 4024 | Value |= (op & 0xffff) << 16; |
| 4025 | // op: M3 |
| 4026 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 4027 | Value |= (op & 0xf) << 12; |
| 4028 | break; |
| 4029 | } |
| 4030 | case SystemZ::CGIT: |
| 4031 | case SystemZ::CIT: { |
| 4032 | // op: R1 |
| 4033 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4034 | Value |= (op & 0xf) << 36; |
| 4035 | // op: I2 |
| 4036 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 1, Fixups, STI); |
| 4037 | Value |= (op & 0xffff) << 16; |
| 4038 | // op: M3 |
| 4039 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4040 | Value |= (op & 0xf) << 12; |
| 4041 | break; |
| 4042 | } |
| 4043 | case SystemZ::LOCGHIAsmE: |
| 4044 | case SystemZ::LOCGHIAsmH: |
| 4045 | case SystemZ::LOCGHIAsmHE: |
| 4046 | case SystemZ::LOCGHIAsmL: |
| 4047 | case SystemZ::LOCGHIAsmLE: |
| 4048 | case SystemZ::LOCGHIAsmLH: |
| 4049 | case SystemZ::LOCGHIAsmM: |
| 4050 | case SystemZ::LOCGHIAsmNE: |
| 4051 | case SystemZ::LOCGHIAsmNH: |
| 4052 | case SystemZ::LOCGHIAsmNHE: |
| 4053 | case SystemZ::LOCGHIAsmNL: |
| 4054 | case SystemZ::LOCGHIAsmNLE: |
| 4055 | case SystemZ::LOCGHIAsmNLH: |
| 4056 | case SystemZ::LOCGHIAsmNM: |
| 4057 | case SystemZ::LOCGHIAsmNO: |
| 4058 | case SystemZ::LOCGHIAsmNP: |
| 4059 | case SystemZ::LOCGHIAsmNZ: |
| 4060 | case SystemZ::LOCGHIAsmO: |
| 4061 | case SystemZ::LOCGHIAsmP: |
| 4062 | case SystemZ::LOCGHIAsmZ: |
| 4063 | case SystemZ::LOCHHIAsmE: |
| 4064 | case SystemZ::LOCHHIAsmH: |
| 4065 | case SystemZ::LOCHHIAsmHE: |
| 4066 | case SystemZ::LOCHHIAsmL: |
| 4067 | case SystemZ::LOCHHIAsmLE: |
| 4068 | case SystemZ::LOCHHIAsmLH: |
| 4069 | case SystemZ::LOCHHIAsmM: |
| 4070 | case SystemZ::LOCHHIAsmNE: |
| 4071 | case SystemZ::LOCHHIAsmNH: |
| 4072 | case SystemZ::LOCHHIAsmNHE: |
| 4073 | case SystemZ::LOCHHIAsmNL: |
| 4074 | case SystemZ::LOCHHIAsmNLE: |
| 4075 | case SystemZ::LOCHHIAsmNLH: |
| 4076 | case SystemZ::LOCHHIAsmNM: |
| 4077 | case SystemZ::LOCHHIAsmNO: |
| 4078 | case SystemZ::LOCHHIAsmNP: |
| 4079 | case SystemZ::LOCHHIAsmNZ: |
| 4080 | case SystemZ::LOCHHIAsmO: |
| 4081 | case SystemZ::LOCHHIAsmP: |
| 4082 | case SystemZ::LOCHHIAsmZ: |
| 4083 | case SystemZ::LOCHIAsmE: |
| 4084 | case SystemZ::LOCHIAsmH: |
| 4085 | case SystemZ::LOCHIAsmHE: |
| 4086 | case SystemZ::LOCHIAsmL: |
| 4087 | case SystemZ::LOCHIAsmLE: |
| 4088 | case SystemZ::LOCHIAsmLH: |
| 4089 | case SystemZ::LOCHIAsmM: |
| 4090 | case SystemZ::LOCHIAsmNE: |
| 4091 | case SystemZ::LOCHIAsmNH: |
| 4092 | case SystemZ::LOCHIAsmNHE: |
| 4093 | case SystemZ::LOCHIAsmNL: |
| 4094 | case SystemZ::LOCHIAsmNLE: |
| 4095 | case SystemZ::LOCHIAsmNLH: |
| 4096 | case SystemZ::LOCHIAsmNM: |
| 4097 | case SystemZ::LOCHIAsmNO: |
| 4098 | case SystemZ::LOCHIAsmNP: |
| 4099 | case SystemZ::LOCHIAsmNZ: |
| 4100 | case SystemZ::LOCHIAsmO: |
| 4101 | case SystemZ::LOCHIAsmP: |
| 4102 | case SystemZ::LOCHIAsmZ: { |
| 4103 | // op: R1 |
| 4104 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4105 | Value |= (op & 0xf) << 36; |
| 4106 | // op: I2 |
| 4107 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 4108 | Value |= (op & 0xffff) << 16; |
| 4109 | break; |
| 4110 | } |
| 4111 | case SystemZ::CFI: |
| 4112 | case SystemZ::CGFI: |
| 4113 | case SystemZ::CIH: |
| 4114 | case SystemZ::LGFI: { |
| 4115 | // op: R1 |
| 4116 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4117 | Value |= (op & 0xf) << 36; |
| 4118 | // op: I2 |
| 4119 | op = getImmOpValue<SystemZ::FK_390_S32Imm>(MI, OpNum: 1, Fixups, STI); |
| 4120 | Value |= (op & 0xffffffff); |
| 4121 | break; |
| 4122 | } |
| 4123 | case SystemZ::AFI: |
| 4124 | case SystemZ::AGFI: |
| 4125 | case SystemZ::AIH: |
| 4126 | case SystemZ::ALSIH: |
| 4127 | case SystemZ::ALSIHN: |
| 4128 | case SystemZ::MSFI: |
| 4129 | case SystemZ::MSGFI: { |
| 4130 | // op: R1 |
| 4131 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4132 | Value |= (op & 0xf) << 36; |
| 4133 | // op: I2 |
| 4134 | op = getImmOpValue<SystemZ::FK_390_S32Imm>(MI, OpNum: 2, Fixups, STI); |
| 4135 | Value |= (op & 0xffffffff); |
| 4136 | break; |
| 4137 | } |
| 4138 | case SystemZ::CGIBAsmE: |
| 4139 | case SystemZ::CGIBAsmH: |
| 4140 | case SystemZ::CGIBAsmHE: |
| 4141 | case SystemZ::CGIBAsmL: |
| 4142 | case SystemZ::CGIBAsmLE: |
| 4143 | case SystemZ::CGIBAsmLH: |
| 4144 | case SystemZ::CGIBAsmNE: |
| 4145 | case SystemZ::CGIBAsmNH: |
| 4146 | case SystemZ::CGIBAsmNHE: |
| 4147 | case SystemZ::CGIBAsmNL: |
| 4148 | case SystemZ::CGIBAsmNLE: |
| 4149 | case SystemZ::CGIBAsmNLH: |
| 4150 | case SystemZ::CIBAsmE: |
| 4151 | case SystemZ::CIBAsmH: |
| 4152 | case SystemZ::CIBAsmHE: |
| 4153 | case SystemZ::CIBAsmL: |
| 4154 | case SystemZ::CIBAsmLE: |
| 4155 | case SystemZ::CIBAsmLH: |
| 4156 | case SystemZ::CIBAsmNE: |
| 4157 | case SystemZ::CIBAsmNH: |
| 4158 | case SystemZ::CIBAsmNHE: |
| 4159 | case SystemZ::CIBAsmNL: |
| 4160 | case SystemZ::CIBAsmNLE: |
| 4161 | case SystemZ::CIBAsmNLH: { |
| 4162 | // op: R1 |
| 4163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4164 | Value |= (op & 0xf) << 36; |
| 4165 | // op: I2 |
| 4166 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4167 | Value |= (op & 0xff) << 8; |
| 4168 | // op: B4 |
| 4169 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4170 | Value |= (op & 0xf) << 28; |
| 4171 | // op: D4 |
| 4172 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 4173 | Value |= (op & 0xfff) << 16; |
| 4174 | break; |
| 4175 | } |
| 4176 | case SystemZ::CGIBAsm: |
| 4177 | case SystemZ::CIBAsm: { |
| 4178 | // op: R1 |
| 4179 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4180 | Value |= (op & 0xf) << 36; |
| 4181 | // op: I2 |
| 4182 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4183 | Value |= (op & 0xff) << 8; |
| 4184 | // op: M3 |
| 4185 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 4186 | Value |= (op & 0xf) << 32; |
| 4187 | // op: B4 |
| 4188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4189 | Value |= (op & 0xf) << 28; |
| 4190 | // op: D4 |
| 4191 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 4192 | Value |= (op & 0xfff) << 16; |
| 4193 | break; |
| 4194 | } |
| 4195 | case SystemZ::CGIJAsm: |
| 4196 | case SystemZ::CIJAsm: { |
| 4197 | // op: R1 |
| 4198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4199 | Value |= (op & 0xf) << 36; |
| 4200 | // op: I2 |
| 4201 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4202 | Value |= (op & 0xff) << 8; |
| 4203 | // op: M3 |
| 4204 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 4205 | Value |= (op & 0xf) << 32; |
| 4206 | // op: RI4 |
| 4207 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 4208 | Value |= (op & 0xffff) << 16; |
| 4209 | break; |
| 4210 | } |
| 4211 | case SystemZ::CGIB: |
| 4212 | case SystemZ::CIB: { |
| 4213 | // op: R1 |
| 4214 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4215 | Value |= (op & 0xf) << 36; |
| 4216 | // op: I2 |
| 4217 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4218 | Value |= (op & 0xff) << 8; |
| 4219 | // op: M3 |
| 4220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4221 | Value |= (op & 0xf) << 32; |
| 4222 | // op: B4 |
| 4223 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4224 | Value |= (op & 0xf) << 28; |
| 4225 | // op: D4 |
| 4226 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 4227 | Value |= (op & 0xfff) << 16; |
| 4228 | break; |
| 4229 | } |
| 4230 | case SystemZ::CGIJ: |
| 4231 | case SystemZ::CIJ: { |
| 4232 | // op: R1 |
| 4233 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4234 | Value |= (op & 0xf) << 36; |
| 4235 | // op: I2 |
| 4236 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4237 | Value |= (op & 0xff) << 8; |
| 4238 | // op: M3 |
| 4239 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4240 | Value |= (op & 0xf) << 32; |
| 4241 | // op: RI4 |
| 4242 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 4243 | Value |= (op & 0xffff) << 16; |
| 4244 | break; |
| 4245 | } |
| 4246 | case SystemZ::CGIJAsmE: |
| 4247 | case SystemZ::CGIJAsmH: |
| 4248 | case SystemZ::CGIJAsmHE: |
| 4249 | case SystemZ::CGIJAsmL: |
| 4250 | case SystemZ::CGIJAsmLE: |
| 4251 | case SystemZ::CGIJAsmLH: |
| 4252 | case SystemZ::CGIJAsmNE: |
| 4253 | case SystemZ::CGIJAsmNH: |
| 4254 | case SystemZ::CGIJAsmNHE: |
| 4255 | case SystemZ::CGIJAsmNL: |
| 4256 | case SystemZ::CGIJAsmNLE: |
| 4257 | case SystemZ::CGIJAsmNLH: |
| 4258 | case SystemZ::CIJAsmE: |
| 4259 | case SystemZ::CIJAsmH: |
| 4260 | case SystemZ::CIJAsmHE: |
| 4261 | case SystemZ::CIJAsmL: |
| 4262 | case SystemZ::CIJAsmLE: |
| 4263 | case SystemZ::CIJAsmLH: |
| 4264 | case SystemZ::CIJAsmNE: |
| 4265 | case SystemZ::CIJAsmNH: |
| 4266 | case SystemZ::CIJAsmNHE: |
| 4267 | case SystemZ::CIJAsmNL: |
| 4268 | case SystemZ::CIJAsmNLE: |
| 4269 | case SystemZ::CIJAsmNLH: { |
| 4270 | // op: R1 |
| 4271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4272 | Value |= (op & 0xf) << 36; |
| 4273 | // op: I2 |
| 4274 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4275 | Value |= (op & 0xff) << 8; |
| 4276 | // op: RI4 |
| 4277 | op = getPC16DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 4278 | Value |= (op & 0xffff) << 16; |
| 4279 | break; |
| 4280 | } |
| 4281 | case SystemZ::CLFITAsmE: |
| 4282 | case SystemZ::CLFITAsmH: |
| 4283 | case SystemZ::CLFITAsmHE: |
| 4284 | case SystemZ::CLFITAsmL: |
| 4285 | case SystemZ::CLFITAsmLE: |
| 4286 | case SystemZ::CLFITAsmLH: |
| 4287 | case SystemZ::CLFITAsmNE: |
| 4288 | case SystemZ::CLFITAsmNH: |
| 4289 | case SystemZ::CLFITAsmNHE: |
| 4290 | case SystemZ::CLFITAsmNL: |
| 4291 | case SystemZ::CLFITAsmNLE: |
| 4292 | case SystemZ::CLFITAsmNLH: |
| 4293 | case SystemZ::CLGITAsmE: |
| 4294 | case SystemZ::CLGITAsmH: |
| 4295 | case SystemZ::CLGITAsmHE: |
| 4296 | case SystemZ::CLGITAsmL: |
| 4297 | case SystemZ::CLGITAsmLE: |
| 4298 | case SystemZ::CLGITAsmLH: |
| 4299 | case SystemZ::CLGITAsmNE: |
| 4300 | case SystemZ::CLGITAsmNH: |
| 4301 | case SystemZ::CLGITAsmNHE: |
| 4302 | case SystemZ::CLGITAsmNL: |
| 4303 | case SystemZ::CLGITAsmNLE: |
| 4304 | case SystemZ::CLGITAsmNLH: { |
| 4305 | // op: R1 |
| 4306 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4307 | Value |= (op & 0xf) << 36; |
| 4308 | // op: I2 |
| 4309 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 1, Fixups, STI); |
| 4310 | Value |= (op & 0xffff) << 16; |
| 4311 | break; |
| 4312 | } |
| 4313 | case SystemZ::CLFITAsm: |
| 4314 | case SystemZ::CLGITAsm: { |
| 4315 | // op: R1 |
| 4316 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4317 | Value |= (op & 0xf) << 36; |
| 4318 | // op: I2 |
| 4319 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 1, Fixups, STI); |
| 4320 | Value |= (op & 0xffff) << 16; |
| 4321 | // op: M3 |
| 4322 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 4323 | Value |= (op & 0xf) << 12; |
| 4324 | break; |
| 4325 | } |
| 4326 | case SystemZ::CLFIT: |
| 4327 | case SystemZ::CLGIT: { |
| 4328 | // op: R1 |
| 4329 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4330 | Value |= (op & 0xf) << 36; |
| 4331 | // op: I2 |
| 4332 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 1, Fixups, STI); |
| 4333 | Value |= (op & 0xffff) << 16; |
| 4334 | // op: M3 |
| 4335 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4336 | Value |= (op & 0xf) << 12; |
| 4337 | break; |
| 4338 | } |
| 4339 | case SystemZ::CLFI: |
| 4340 | case SystemZ::CLGFI: |
| 4341 | case SystemZ::CLIH: |
| 4342 | case SystemZ::IIHF: |
| 4343 | case SystemZ::IILF: |
| 4344 | case SystemZ::LLIHF: |
| 4345 | case SystemZ::LLILF: { |
| 4346 | // op: R1 |
| 4347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4348 | Value |= (op & 0xf) << 36; |
| 4349 | // op: I2 |
| 4350 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 1, Fixups, STI); |
| 4351 | Value |= (op & 0xffffffff); |
| 4352 | break; |
| 4353 | } |
| 4354 | case SystemZ::ALFI: |
| 4355 | case SystemZ::ALGFI: |
| 4356 | case SystemZ::NIHF: |
| 4357 | case SystemZ::NILF: |
| 4358 | case SystemZ::OIHF: |
| 4359 | case SystemZ::OILF: |
| 4360 | case SystemZ::SLFI: |
| 4361 | case SystemZ::SLGFI: |
| 4362 | case SystemZ::XIHF: |
| 4363 | case SystemZ::XILF: { |
| 4364 | // op: R1 |
| 4365 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4366 | Value |= (op & 0xf) << 36; |
| 4367 | // op: I2 |
| 4368 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 2, Fixups, STI); |
| 4369 | Value |= (op & 0xffffffff); |
| 4370 | break; |
| 4371 | } |
| 4372 | case SystemZ::CLGIBAsmE: |
| 4373 | case SystemZ::CLGIBAsmH: |
| 4374 | case SystemZ::CLGIBAsmHE: |
| 4375 | case SystemZ::CLGIBAsmL: |
| 4376 | case SystemZ::CLGIBAsmLE: |
| 4377 | case SystemZ::CLGIBAsmLH: |
| 4378 | case SystemZ::CLGIBAsmNE: |
| 4379 | case SystemZ::CLGIBAsmNH: |
| 4380 | case SystemZ::CLGIBAsmNHE: |
| 4381 | case SystemZ::CLGIBAsmNL: |
| 4382 | case SystemZ::CLGIBAsmNLE: |
| 4383 | case SystemZ::CLGIBAsmNLH: |
| 4384 | case SystemZ::CLIBAsmE: |
| 4385 | case SystemZ::CLIBAsmH: |
| 4386 | case SystemZ::CLIBAsmHE: |
| 4387 | case SystemZ::CLIBAsmL: |
| 4388 | case SystemZ::CLIBAsmLE: |
| 4389 | case SystemZ::CLIBAsmLH: |
| 4390 | case SystemZ::CLIBAsmNE: |
| 4391 | case SystemZ::CLIBAsmNH: |
| 4392 | case SystemZ::CLIBAsmNHE: |
| 4393 | case SystemZ::CLIBAsmNL: |
| 4394 | case SystemZ::CLIBAsmNLE: |
| 4395 | case SystemZ::CLIBAsmNLH: { |
| 4396 | // op: R1 |
| 4397 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4398 | Value |= (op & 0xf) << 36; |
| 4399 | // op: I2 |
| 4400 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4401 | Value |= (op & 0xff) << 8; |
| 4402 | // op: B4 |
| 4403 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4404 | Value |= (op & 0xf) << 28; |
| 4405 | // op: D4 |
| 4406 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 4407 | Value |= (op & 0xfff) << 16; |
| 4408 | break; |
| 4409 | } |
| 4410 | case SystemZ::CLGIBAsm: |
| 4411 | case SystemZ::CLIBAsm: { |
| 4412 | // op: R1 |
| 4413 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4414 | Value |= (op & 0xf) << 36; |
| 4415 | // op: I2 |
| 4416 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4417 | Value |= (op & 0xff) << 8; |
| 4418 | // op: M3 |
| 4419 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 4420 | Value |= (op & 0xf) << 32; |
| 4421 | // op: B4 |
| 4422 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4423 | Value |= (op & 0xf) << 28; |
| 4424 | // op: D4 |
| 4425 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 4426 | Value |= (op & 0xfff) << 16; |
| 4427 | break; |
| 4428 | } |
| 4429 | case SystemZ::CLGIJAsm: |
| 4430 | case SystemZ::CLIJAsm: { |
| 4431 | // op: R1 |
| 4432 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4433 | Value |= (op & 0xf) << 36; |
| 4434 | // op: I2 |
| 4435 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4436 | Value |= (op & 0xff) << 8; |
| 4437 | // op: M3 |
| 4438 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 4439 | Value |= (op & 0xf) << 32; |
| 4440 | // op: RI4 |
| 4441 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 4442 | Value |= (op & 0xffff) << 16; |
| 4443 | break; |
| 4444 | } |
| 4445 | case SystemZ::CLGIB: |
| 4446 | case SystemZ::CLIB: { |
| 4447 | // op: R1 |
| 4448 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4449 | Value |= (op & 0xf) << 36; |
| 4450 | // op: I2 |
| 4451 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4452 | Value |= (op & 0xff) << 8; |
| 4453 | // op: M3 |
| 4454 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4455 | Value |= (op & 0xf) << 32; |
| 4456 | // op: B4 |
| 4457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4458 | Value |= (op & 0xf) << 28; |
| 4459 | // op: D4 |
| 4460 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 4461 | Value |= (op & 0xfff) << 16; |
| 4462 | break; |
| 4463 | } |
| 4464 | case SystemZ::CLGIJ: |
| 4465 | case SystemZ::CLIJ: { |
| 4466 | // op: R1 |
| 4467 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4468 | Value |= (op & 0xf) << 36; |
| 4469 | // op: I2 |
| 4470 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4471 | Value |= (op & 0xff) << 8; |
| 4472 | // op: M3 |
| 4473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4474 | Value |= (op & 0xf) << 32; |
| 4475 | // op: RI4 |
| 4476 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 4477 | Value |= (op & 0xffff) << 16; |
| 4478 | break; |
| 4479 | } |
| 4480 | case SystemZ::CLGIJAsmE: |
| 4481 | case SystemZ::CLGIJAsmH: |
| 4482 | case SystemZ::CLGIJAsmHE: |
| 4483 | case SystemZ::CLGIJAsmL: |
| 4484 | case SystemZ::CLGIJAsmLE: |
| 4485 | case SystemZ::CLGIJAsmLH: |
| 4486 | case SystemZ::CLGIJAsmNE: |
| 4487 | case SystemZ::CLGIJAsmNH: |
| 4488 | case SystemZ::CLGIJAsmNHE: |
| 4489 | case SystemZ::CLGIJAsmNL: |
| 4490 | case SystemZ::CLGIJAsmNLE: |
| 4491 | case SystemZ::CLGIJAsmNLH: |
| 4492 | case SystemZ::CLIJAsmE: |
| 4493 | case SystemZ::CLIJAsmH: |
| 4494 | case SystemZ::CLIJAsmHE: |
| 4495 | case SystemZ::CLIJAsmL: |
| 4496 | case SystemZ::CLIJAsmLE: |
| 4497 | case SystemZ::CLIJAsmLH: |
| 4498 | case SystemZ::CLIJAsmNE: |
| 4499 | case SystemZ::CLIJAsmNH: |
| 4500 | case SystemZ::CLIJAsmNHE: |
| 4501 | case SystemZ::CLIJAsmNL: |
| 4502 | case SystemZ::CLIJAsmNLE: |
| 4503 | case SystemZ::CLIJAsmNLH: { |
| 4504 | // op: R1 |
| 4505 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4506 | Value |= (op & 0xf) << 36; |
| 4507 | // op: I2 |
| 4508 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 1, Fixups, STI); |
| 4509 | Value |= (op & 0xff) << 8; |
| 4510 | // op: RI4 |
| 4511 | op = getPC16DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 4512 | Value |= (op & 0xffff) << 16; |
| 4513 | break; |
| 4514 | } |
| 4515 | case SystemZ::CLMH: |
| 4516 | case SystemZ::CLMY: |
| 4517 | case SystemZ::STCMH: |
| 4518 | case SystemZ::STCMY: { |
| 4519 | // op: R1 |
| 4520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4521 | Value |= (op & 0xf) << 36; |
| 4522 | // op: M3 |
| 4523 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 4524 | Value |= (op & 0xf) << 32; |
| 4525 | // op: B2 |
| 4526 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4527 | Value |= (op & 0xf) << 28; |
| 4528 | // op: D2 |
| 4529 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 4530 | Value |= (op & 0xfff) << 16; |
| 4531 | Value |= (op & 0xff000) >> 4; |
| 4532 | break; |
| 4533 | } |
| 4534 | case SystemZ::ICMH: |
| 4535 | case SystemZ::ICMY: { |
| 4536 | // op: R1 |
| 4537 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4538 | Value |= (op & 0xf) << 36; |
| 4539 | // op: M3 |
| 4540 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 4541 | Value |= (op & 0xf) << 32; |
| 4542 | // op: B2 |
| 4543 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4544 | Value |= (op & 0xf) << 28; |
| 4545 | // op: D2 |
| 4546 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 4, Fixups, STI); |
| 4547 | Value |= (op & 0xfff) << 16; |
| 4548 | Value |= (op & 0xff000) >> 4; |
| 4549 | break; |
| 4550 | } |
| 4551 | case SystemZ::CLGTAsm: |
| 4552 | case SystemZ::CLTAsm: |
| 4553 | case SystemZ::STOCAsm: |
| 4554 | case SystemZ::STOCFHAsm: |
| 4555 | case SystemZ::STOCGAsm: { |
| 4556 | // op: R1 |
| 4557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4558 | Value |= (op & 0xf) << 36; |
| 4559 | // op: M3 |
| 4560 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 4561 | Value |= (op & 0xf) << 32; |
| 4562 | // op: B2 |
| 4563 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4564 | Value |= (op & 0xf) << 28; |
| 4565 | // op: D2 |
| 4566 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 2, Fixups, STI); |
| 4567 | Value |= (op & 0xfff) << 16; |
| 4568 | Value |= (op & 0xff000) >> 4; |
| 4569 | break; |
| 4570 | } |
| 4571 | case SystemZ::LOCGHIAsm: |
| 4572 | case SystemZ::LOCHHIAsm: |
| 4573 | case SystemZ::LOCHIAsm: { |
| 4574 | // op: R1 |
| 4575 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4576 | Value |= (op & 0xf) << 36; |
| 4577 | // op: M3 |
| 4578 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 4579 | Value |= (op & 0xf) << 32; |
| 4580 | // op: I2 |
| 4581 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 4582 | Value |= (op & 0xffff) << 16; |
| 4583 | break; |
| 4584 | } |
| 4585 | case SystemZ::LOCAsm: |
| 4586 | case SystemZ::LOCFHAsm: |
| 4587 | case SystemZ::LOCGAsm: { |
| 4588 | // op: R1 |
| 4589 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4590 | Value |= (op & 0xf) << 36; |
| 4591 | // op: M3 |
| 4592 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 4593 | Value |= (op & 0xf) << 32; |
| 4594 | // op: B2 |
| 4595 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4596 | Value |= (op & 0xf) << 28; |
| 4597 | // op: D2 |
| 4598 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 4599 | Value |= (op & 0xfff) << 16; |
| 4600 | Value |= (op & 0xff000) >> 4; |
| 4601 | break; |
| 4602 | } |
| 4603 | case SystemZ::CLGT: |
| 4604 | case SystemZ::CLT: { |
| 4605 | // op: R1 |
| 4606 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4607 | Value |= (op & 0xf) << 36; |
| 4608 | // op: M3 |
| 4609 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4610 | Value |= (op & 0xf) << 32; |
| 4611 | // op: B2 |
| 4612 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4613 | Value |= (op & 0xf) << 28; |
| 4614 | // op: D2 |
| 4615 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 2, Fixups, STI); |
| 4616 | Value |= (op & 0xfff) << 16; |
| 4617 | Value |= (op & 0xff000) >> 4; |
| 4618 | break; |
| 4619 | } |
| 4620 | case SystemZ::STOC: |
| 4621 | case SystemZ::STOCFH: |
| 4622 | case SystemZ::STOCG: { |
| 4623 | // op: R1 |
| 4624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4625 | Value |= (op & 0xf) << 36; |
| 4626 | // op: M3 |
| 4627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4628 | Value |= (op & 0xf) << 32; |
| 4629 | // op: B2 |
| 4630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4631 | Value |= (op & 0xf) << 28; |
| 4632 | // op: D2 |
| 4633 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 2, Fixups, STI); |
| 4634 | Value |= (op & 0xfff) << 16; |
| 4635 | Value |= (op & 0xff000) >> 4; |
| 4636 | break; |
| 4637 | } |
| 4638 | case SystemZ::LOCGHI: |
| 4639 | case SystemZ::LOCHHI: |
| 4640 | case SystemZ::LOCHI: { |
| 4641 | // op: R1 |
| 4642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4643 | Value |= (op & 0xf) << 36; |
| 4644 | // op: M3 |
| 4645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4646 | Value |= (op & 0xf) << 32; |
| 4647 | // op: I2 |
| 4648 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 4649 | Value |= (op & 0xffff) << 16; |
| 4650 | break; |
| 4651 | } |
| 4652 | case SystemZ::LOC: |
| 4653 | case SystemZ::LOCFH: |
| 4654 | case SystemZ::LOCG: { |
| 4655 | // op: R1 |
| 4656 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4657 | Value |= (op & 0xf) << 36; |
| 4658 | // op: M3 |
| 4659 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 4660 | Value |= (op & 0xf) << 32; |
| 4661 | // op: B2 |
| 4662 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4663 | Value |= (op & 0xf) << 28; |
| 4664 | // op: D2 |
| 4665 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 4666 | Value |= (op & 0xfff) << 16; |
| 4667 | Value |= (op & 0xff000) >> 4; |
| 4668 | break; |
| 4669 | } |
| 4670 | case SystemZ::CGRBAsmE: |
| 4671 | case SystemZ::CGRBAsmH: |
| 4672 | case SystemZ::CGRBAsmHE: |
| 4673 | case SystemZ::CGRBAsmL: |
| 4674 | case SystemZ::CGRBAsmLE: |
| 4675 | case SystemZ::CGRBAsmLH: |
| 4676 | case SystemZ::CGRBAsmNE: |
| 4677 | case SystemZ::CGRBAsmNH: |
| 4678 | case SystemZ::CGRBAsmNHE: |
| 4679 | case SystemZ::CGRBAsmNL: |
| 4680 | case SystemZ::CGRBAsmNLE: |
| 4681 | case SystemZ::CGRBAsmNLH: |
| 4682 | case SystemZ::CLGRBAsmE: |
| 4683 | case SystemZ::CLGRBAsmH: |
| 4684 | case SystemZ::CLGRBAsmHE: |
| 4685 | case SystemZ::CLGRBAsmL: |
| 4686 | case SystemZ::CLGRBAsmLE: |
| 4687 | case SystemZ::CLGRBAsmLH: |
| 4688 | case SystemZ::CLGRBAsmNE: |
| 4689 | case SystemZ::CLGRBAsmNH: |
| 4690 | case SystemZ::CLGRBAsmNHE: |
| 4691 | case SystemZ::CLGRBAsmNL: |
| 4692 | case SystemZ::CLGRBAsmNLE: |
| 4693 | case SystemZ::CLGRBAsmNLH: |
| 4694 | case SystemZ::CLRBAsmE: |
| 4695 | case SystemZ::CLRBAsmH: |
| 4696 | case SystemZ::CLRBAsmHE: |
| 4697 | case SystemZ::CLRBAsmL: |
| 4698 | case SystemZ::CLRBAsmLE: |
| 4699 | case SystemZ::CLRBAsmLH: |
| 4700 | case SystemZ::CLRBAsmNE: |
| 4701 | case SystemZ::CLRBAsmNH: |
| 4702 | case SystemZ::CLRBAsmNHE: |
| 4703 | case SystemZ::CLRBAsmNL: |
| 4704 | case SystemZ::CLRBAsmNLE: |
| 4705 | case SystemZ::CLRBAsmNLH: |
| 4706 | case SystemZ::CRBAsmE: |
| 4707 | case SystemZ::CRBAsmH: |
| 4708 | case SystemZ::CRBAsmHE: |
| 4709 | case SystemZ::CRBAsmL: |
| 4710 | case SystemZ::CRBAsmLE: |
| 4711 | case SystemZ::CRBAsmLH: |
| 4712 | case SystemZ::CRBAsmNE: |
| 4713 | case SystemZ::CRBAsmNH: |
| 4714 | case SystemZ::CRBAsmNHE: |
| 4715 | case SystemZ::CRBAsmNL: |
| 4716 | case SystemZ::CRBAsmNLE: |
| 4717 | case SystemZ::CRBAsmNLH: { |
| 4718 | // op: R1 |
| 4719 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4720 | Value |= (op & 0xf) << 36; |
| 4721 | // op: R2 |
| 4722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4723 | Value |= (op & 0xf) << 32; |
| 4724 | // op: B4 |
| 4725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4726 | Value |= (op & 0xf) << 28; |
| 4727 | // op: D4 |
| 4728 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 4729 | Value |= (op & 0xfff) << 16; |
| 4730 | break; |
| 4731 | } |
| 4732 | case SystemZ::CGRBAsm: |
| 4733 | case SystemZ::CLGRBAsm: |
| 4734 | case SystemZ::CLRBAsm: |
| 4735 | case SystemZ::CRBAsm: { |
| 4736 | // op: R1 |
| 4737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4738 | Value |= (op & 0xf) << 36; |
| 4739 | // op: R2 |
| 4740 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4741 | Value |= (op & 0xf) << 32; |
| 4742 | // op: M3 |
| 4743 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 4744 | Value |= (op & 0xf) << 12; |
| 4745 | // op: B4 |
| 4746 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4747 | Value |= (op & 0xf) << 28; |
| 4748 | // op: D4 |
| 4749 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 4750 | Value |= (op & 0xfff) << 16; |
| 4751 | break; |
| 4752 | } |
| 4753 | case SystemZ::CGRJAsm: |
| 4754 | case SystemZ::CLGRJAsm: |
| 4755 | case SystemZ::CLRJAsm: |
| 4756 | case SystemZ::CRJAsm: { |
| 4757 | // op: R1 |
| 4758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4759 | Value |= (op & 0xf) << 36; |
| 4760 | // op: R2 |
| 4761 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4762 | Value |= (op & 0xf) << 32; |
| 4763 | // op: M3 |
| 4764 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 4765 | Value |= (op & 0xf) << 12; |
| 4766 | // op: RI4 |
| 4767 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 4768 | Value |= (op & 0xffff) << 16; |
| 4769 | break; |
| 4770 | } |
| 4771 | case SystemZ::CGRB: |
| 4772 | case SystemZ::CLGRB: |
| 4773 | case SystemZ::CLRB: |
| 4774 | case SystemZ::CRB: { |
| 4775 | // op: R1 |
| 4776 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4777 | Value |= (op & 0xf) << 36; |
| 4778 | // op: R2 |
| 4779 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4780 | Value |= (op & 0xf) << 32; |
| 4781 | // op: M3 |
| 4782 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4783 | Value |= (op & 0xf) << 12; |
| 4784 | // op: B4 |
| 4785 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4786 | Value |= (op & 0xf) << 28; |
| 4787 | // op: D4 |
| 4788 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 4789 | Value |= (op & 0xfff) << 16; |
| 4790 | break; |
| 4791 | } |
| 4792 | case SystemZ::CGRJ: |
| 4793 | case SystemZ::CLGRJ: |
| 4794 | case SystemZ::CLRJ: |
| 4795 | case SystemZ::CRJ: { |
| 4796 | // op: R1 |
| 4797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4798 | Value |= (op & 0xf) << 36; |
| 4799 | // op: R2 |
| 4800 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4801 | Value |= (op & 0xf) << 32; |
| 4802 | // op: M3 |
| 4803 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4804 | Value |= (op & 0xf) << 12; |
| 4805 | // op: RI4 |
| 4806 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 4807 | Value |= (op & 0xffff) << 16; |
| 4808 | break; |
| 4809 | } |
| 4810 | case SystemZ::CGRJAsmE: |
| 4811 | case SystemZ::CGRJAsmH: |
| 4812 | case SystemZ::CGRJAsmHE: |
| 4813 | case SystemZ::CGRJAsmL: |
| 4814 | case SystemZ::CGRJAsmLE: |
| 4815 | case SystemZ::CGRJAsmLH: |
| 4816 | case SystemZ::CGRJAsmNE: |
| 4817 | case SystemZ::CGRJAsmNH: |
| 4818 | case SystemZ::CGRJAsmNHE: |
| 4819 | case SystemZ::CGRJAsmNL: |
| 4820 | case SystemZ::CGRJAsmNLE: |
| 4821 | case SystemZ::CGRJAsmNLH: |
| 4822 | case SystemZ::CLGRJAsmE: |
| 4823 | case SystemZ::CLGRJAsmH: |
| 4824 | case SystemZ::CLGRJAsmHE: |
| 4825 | case SystemZ::CLGRJAsmL: |
| 4826 | case SystemZ::CLGRJAsmLE: |
| 4827 | case SystemZ::CLGRJAsmLH: |
| 4828 | case SystemZ::CLGRJAsmNE: |
| 4829 | case SystemZ::CLGRJAsmNH: |
| 4830 | case SystemZ::CLGRJAsmNHE: |
| 4831 | case SystemZ::CLGRJAsmNL: |
| 4832 | case SystemZ::CLGRJAsmNLE: |
| 4833 | case SystemZ::CLGRJAsmNLH: |
| 4834 | case SystemZ::CLRJAsmE: |
| 4835 | case SystemZ::CLRJAsmH: |
| 4836 | case SystemZ::CLRJAsmHE: |
| 4837 | case SystemZ::CLRJAsmL: |
| 4838 | case SystemZ::CLRJAsmLE: |
| 4839 | case SystemZ::CLRJAsmLH: |
| 4840 | case SystemZ::CLRJAsmNE: |
| 4841 | case SystemZ::CLRJAsmNH: |
| 4842 | case SystemZ::CLRJAsmNHE: |
| 4843 | case SystemZ::CLRJAsmNL: |
| 4844 | case SystemZ::CLRJAsmNLE: |
| 4845 | case SystemZ::CLRJAsmNLH: |
| 4846 | case SystemZ::CRJAsmE: |
| 4847 | case SystemZ::CRJAsmH: |
| 4848 | case SystemZ::CRJAsmHE: |
| 4849 | case SystemZ::CRJAsmL: |
| 4850 | case SystemZ::CRJAsmLE: |
| 4851 | case SystemZ::CRJAsmLH: |
| 4852 | case SystemZ::CRJAsmNE: |
| 4853 | case SystemZ::CRJAsmNH: |
| 4854 | case SystemZ::CRJAsmNHE: |
| 4855 | case SystemZ::CRJAsmNL: |
| 4856 | case SystemZ::CRJAsmNLE: |
| 4857 | case SystemZ::CRJAsmNLH: { |
| 4858 | // op: R1 |
| 4859 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4860 | Value |= (op & 0xf) << 36; |
| 4861 | // op: R2 |
| 4862 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4863 | Value |= (op & 0xf) << 32; |
| 4864 | // op: RI4 |
| 4865 | op = getPC16DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 4866 | Value |= (op & 0xffff) << 16; |
| 4867 | break; |
| 4868 | } |
| 4869 | case SystemZ::RISBGNZOpt: |
| 4870 | case SystemZ::RISBGZOpt: { |
| 4871 | // op: R1 |
| 4872 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4873 | Value |= (op & 0xf) << 36; |
| 4874 | // op: R2 |
| 4875 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4876 | Value |= (op & 0xf) << 32; |
| 4877 | // op: I3 |
| 4878 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 4879 | Value |= (op & 0xff) << 24; |
| 4880 | // op: I4 |
| 4881 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 4882 | Value |= (op & 0x7f) << 16; |
| 4883 | break; |
| 4884 | } |
| 4885 | case SystemZ::RISBGNZ: |
| 4886 | case SystemZ::RISBGZ: { |
| 4887 | // op: R1 |
| 4888 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4889 | Value |= (op & 0xf) << 36; |
| 4890 | // op: R2 |
| 4891 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4892 | Value |= (op & 0xf) << 32; |
| 4893 | // op: I3 |
| 4894 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 4895 | Value |= (op & 0xff) << 24; |
| 4896 | // op: I4 |
| 4897 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 4898 | Value |= (op & 0x7f) << 16; |
| 4899 | // op: I5 |
| 4900 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 5, Fixups, STI); |
| 4901 | Value |= (op & 0xff) << 8; |
| 4902 | break; |
| 4903 | } |
| 4904 | case SystemZ::RISBG32Opt: |
| 4905 | case SystemZ::RISBGNOpt: |
| 4906 | case SystemZ::RISBGOpt: |
| 4907 | case SystemZ::RISBHGOpt: |
| 4908 | case SystemZ::RISBLGOpt: |
| 4909 | case SystemZ::RNSBGOpt: |
| 4910 | case SystemZ::ROSBGOpt: |
| 4911 | case SystemZ::RXSBGOpt: { |
| 4912 | // op: R1 |
| 4913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4914 | Value |= (op & 0xf) << 36; |
| 4915 | // op: R2 |
| 4916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4917 | Value |= (op & 0xf) << 32; |
| 4918 | // op: I3 |
| 4919 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 4920 | Value |= (op & 0xff) << 24; |
| 4921 | // op: I4 |
| 4922 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 4923 | Value |= (op & 0xff) << 16; |
| 4924 | break; |
| 4925 | } |
| 4926 | case SystemZ::RISBG: |
| 4927 | case SystemZ::RISBG32: |
| 4928 | case SystemZ::RISBGN: |
| 4929 | case SystemZ::RISBHG: |
| 4930 | case SystemZ::RISBLG: |
| 4931 | case SystemZ::RNSBG: |
| 4932 | case SystemZ::ROSBG: |
| 4933 | case SystemZ::RXSBG: { |
| 4934 | // op: R1 |
| 4935 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4936 | Value |= (op & 0xf) << 36; |
| 4937 | // op: R2 |
| 4938 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4939 | Value |= (op & 0xf) << 32; |
| 4940 | // op: I3 |
| 4941 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 4942 | Value |= (op & 0xff) << 24; |
| 4943 | // op: I4 |
| 4944 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 4945 | Value |= (op & 0xff) << 16; |
| 4946 | // op: I5 |
| 4947 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 5, Fixups, STI); |
| 4948 | Value |= (op & 0xff) << 8; |
| 4949 | break; |
| 4950 | } |
| 4951 | case SystemZ::ECAG: |
| 4952 | case SystemZ::LAA: |
| 4953 | case SystemZ::LAAG: |
| 4954 | case SystemZ::LAAL: |
| 4955 | case SystemZ::LAALG: |
| 4956 | case SystemZ::LAMY: |
| 4957 | case SystemZ::LAN: |
| 4958 | case SystemZ::LANG: |
| 4959 | case SystemZ::LAO: |
| 4960 | case SystemZ::LAOG: |
| 4961 | case SystemZ::LAX: |
| 4962 | case SystemZ::LAXG: |
| 4963 | case SystemZ::LCTLG: |
| 4964 | case SystemZ::LMG: |
| 4965 | case SystemZ::LMH: |
| 4966 | case SystemZ::LMY: |
| 4967 | case SystemZ::PFCR: |
| 4968 | case SystemZ::RLL: |
| 4969 | case SystemZ::RLLG: |
| 4970 | case SystemZ::SLAG: |
| 4971 | case SystemZ::SLAK: |
| 4972 | case SystemZ::SLLG: |
| 4973 | case SystemZ::SLLK: |
| 4974 | case SystemZ::SRAG: |
| 4975 | case SystemZ::SRAK: |
| 4976 | case SystemZ::SRLG: |
| 4977 | case SystemZ::SRLK: |
| 4978 | case SystemZ::STAMY: |
| 4979 | case SystemZ::STCTG: |
| 4980 | case SystemZ::STMG: |
| 4981 | case SystemZ::STMH: |
| 4982 | case SystemZ::STMY: |
| 4983 | case SystemZ::TRACG: { |
| 4984 | // op: R1 |
| 4985 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4986 | Value |= (op & 0xf) << 36; |
| 4987 | // op: R3 |
| 4988 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4989 | Value |= (op & 0xf) << 32; |
| 4990 | // op: B2 |
| 4991 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4992 | Value |= (op & 0xf) << 28; |
| 4993 | // op: D2 |
| 4994 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 4995 | Value |= (op & 0xfff) << 16; |
| 4996 | Value |= (op & 0xff000) >> 4; |
| 4997 | break; |
| 4998 | } |
| 4999 | case SystemZ::CLCLU: |
| 5000 | case SystemZ::MVCLU: { |
| 5001 | // op: R1 |
| 5002 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5003 | Value |= (op & 0xf) << 36; |
| 5004 | // op: R3 |
| 5005 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5006 | Value |= (op & 0xf) << 32; |
| 5007 | // op: B2 |
| 5008 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5009 | Value |= (op & 0xf) << 28; |
| 5010 | // op: D2 |
| 5011 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 5, Fixups, STI); |
| 5012 | Value |= (op & 0xfff) << 16; |
| 5013 | Value |= (op & 0xff000) >> 4; |
| 5014 | break; |
| 5015 | } |
| 5016 | case SystemZ::AGHIK: |
| 5017 | case SystemZ::AHIK: |
| 5018 | case SystemZ::ALGHSIK: |
| 5019 | case SystemZ::ALHSIK: { |
| 5020 | // op: R1 |
| 5021 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5022 | Value |= (op & 0xf) << 36; |
| 5023 | // op: R3 |
| 5024 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5025 | Value |= (op & 0xf) << 32; |
| 5026 | // op: I2 |
| 5027 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 5028 | Value |= (op & 0xffff) << 16; |
| 5029 | break; |
| 5030 | } |
| 5031 | case SystemZ::BXHG: |
| 5032 | case SystemZ::BXLEG: |
| 5033 | case SystemZ::CDSG: |
| 5034 | case SystemZ::CDSY: |
| 5035 | case SystemZ::CSG: |
| 5036 | case SystemZ::CSY: { |
| 5037 | // op: R1 |
| 5038 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5039 | Value |= (op & 0xf) << 36; |
| 5040 | // op: R3 |
| 5041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5042 | Value |= (op & 0xf) << 32; |
| 5043 | // op: B2 |
| 5044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5045 | Value |= (op & 0xf) << 28; |
| 5046 | // op: D2 |
| 5047 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 4, Fixups, STI); |
| 5048 | Value |= (op & 0xfff) << 16; |
| 5049 | Value |= (op & 0xff000) >> 4; |
| 5050 | break; |
| 5051 | } |
| 5052 | case SystemZ::BRXHG: |
| 5053 | case SystemZ::BRXLG: { |
| 5054 | // op: R1 |
| 5055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5056 | Value |= (op & 0xf) << 36; |
| 5057 | // op: R3 |
| 5058 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5059 | Value |= (op & 0xf) << 32; |
| 5060 | // op: RI2 |
| 5061 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 5062 | Value |= (op & 0xffff) << 16; |
| 5063 | break; |
| 5064 | } |
| 5065 | case SystemZ::CGFRL: |
| 5066 | case SystemZ::CGHRL: |
| 5067 | case SystemZ::CGRL: |
| 5068 | case SystemZ::CHRL: |
| 5069 | case SystemZ::CLGFRL: |
| 5070 | case SystemZ::CLGHRL: |
| 5071 | case SystemZ::CLGRL: |
| 5072 | case SystemZ::CLHRL: |
| 5073 | case SystemZ::CLRL: |
| 5074 | case SystemZ::CRL: |
| 5075 | case SystemZ::EXRL: |
| 5076 | case SystemZ::LARL: |
| 5077 | case SystemZ::LGFRL: |
| 5078 | case SystemZ::LGHRL: |
| 5079 | case SystemZ::LGRL: |
| 5080 | case SystemZ::LHRL: |
| 5081 | case SystemZ::LLGFRL: |
| 5082 | case SystemZ::LLGHRL: |
| 5083 | case SystemZ::LLHRL: |
| 5084 | case SystemZ::LRL: |
| 5085 | case SystemZ::STGRL: |
| 5086 | case SystemZ::STHRL: |
| 5087 | case SystemZ::STRL: { |
| 5088 | // op: R1 |
| 5089 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5090 | Value |= (op & 0xf) << 36; |
| 5091 | // op: RI2 |
| 5092 | op = getPC32DBLEncoding(MI, OpNum: 1, Fixups, STI); |
| 5093 | Value |= (op & 0xffffffff); |
| 5094 | break; |
| 5095 | } |
| 5096 | case SystemZ::BRCTH: { |
| 5097 | // op: R1 |
| 5098 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5099 | Value |= (op & 0xf) << 36; |
| 5100 | // op: RI2 |
| 5101 | op = getPC32DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 5102 | Value |= (op & 0xffffffff); |
| 5103 | break; |
| 5104 | } |
| 5105 | case SystemZ::BRASL: { |
| 5106 | // op: R1 |
| 5107 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5108 | Value |= (op & 0xf) << 36; |
| 5109 | // op: RI2 |
| 5110 | op = getPC32DBLTLSEncoding(MI, OpNum: 1, Fixups, STI); |
| 5111 | Value |= (op & 0xffffffff); |
| 5112 | break; |
| 5113 | } |
| 5114 | case SystemZ::VCVB: |
| 5115 | case SystemZ::VCVBG: { |
| 5116 | // op: R1 |
| 5117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5118 | Value |= (op & 0xf) << 36; |
| 5119 | // op: V2 |
| 5120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5121 | Value |= (op & 0xf) << 32; |
| 5122 | Value |= (op & 0x10) << 6; |
| 5123 | // op: M3 |
| 5124 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 5125 | Value |= (op & 0xf) << 20; |
| 5126 | break; |
| 5127 | } |
| 5128 | case SystemZ::VCVBGOpt: |
| 5129 | case SystemZ::VCVBOpt: { |
| 5130 | // op: R1 |
| 5131 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5132 | Value |= (op & 0xf) << 36; |
| 5133 | // op: V2 |
| 5134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5135 | Value |= (op & 0xf) << 32; |
| 5136 | Value |= (op & 0x10) << 6; |
| 5137 | // op: M3 |
| 5138 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 5139 | Value |= (op & 0xf) << 20; |
| 5140 | // op: M4 |
| 5141 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 5142 | Value |= (op & 0xf) << 16; |
| 5143 | break; |
| 5144 | } |
| 5145 | case SystemZ::CG: |
| 5146 | case SystemZ::CGF: |
| 5147 | case SystemZ::CGH: |
| 5148 | case SystemZ::CHF: |
| 5149 | case SystemZ::CHY: |
| 5150 | case SystemZ::CLG: |
| 5151 | case SystemZ::CLGF: |
| 5152 | case SystemZ::CLHF: |
| 5153 | case SystemZ::CLY: |
| 5154 | case SystemZ::CVDG: |
| 5155 | case SystemZ::CVDY: |
| 5156 | case SystemZ::CY: |
| 5157 | case SystemZ::LAEY: |
| 5158 | case SystemZ::LAT: |
| 5159 | case SystemZ::LAY: |
| 5160 | case SystemZ::LB: |
| 5161 | case SystemZ::LBH: |
| 5162 | case SystemZ::LDY: |
| 5163 | case SystemZ::LE16Y: |
| 5164 | case SystemZ::LEY: |
| 5165 | case SystemZ::LFH: |
| 5166 | case SystemZ::LFHAT: |
| 5167 | case SystemZ::LG: |
| 5168 | case SystemZ::LGAT: |
| 5169 | case SystemZ::LGB: |
| 5170 | case SystemZ::LGF: |
| 5171 | case SystemZ::LGG: |
| 5172 | case SystemZ::LGH: |
| 5173 | case SystemZ::LGSC: |
| 5174 | case SystemZ::LHH: |
| 5175 | case SystemZ::LHY: |
| 5176 | case SystemZ::LLC: |
| 5177 | case SystemZ::LLCH: |
| 5178 | case SystemZ::LLGC: |
| 5179 | case SystemZ::LLGF: |
| 5180 | case SystemZ::LLGFAT: |
| 5181 | case SystemZ::LLGFSG: |
| 5182 | case SystemZ::LLGH: |
| 5183 | case SystemZ::LLGT: |
| 5184 | case SystemZ::LLGTAT: |
| 5185 | case SystemZ::LLH: |
| 5186 | case SystemZ::LLHH: |
| 5187 | case SystemZ::LLXAB: |
| 5188 | case SystemZ::LLXAF: |
| 5189 | case SystemZ::LLXAG: |
| 5190 | case SystemZ::LLXAH: |
| 5191 | case SystemZ::LLXAQ: |
| 5192 | case SystemZ::LLZRGF: |
| 5193 | case SystemZ::LPQ: |
| 5194 | case SystemZ::LRAG: |
| 5195 | case SystemZ::LRAY: |
| 5196 | case SystemZ::LRV: |
| 5197 | case SystemZ::LRVG: |
| 5198 | case SystemZ::LRVH: |
| 5199 | case SystemZ::LT: |
| 5200 | case SystemZ::LTG: |
| 5201 | case SystemZ::LTGF: |
| 5202 | case SystemZ::LXAB: |
| 5203 | case SystemZ::LXAF: |
| 5204 | case SystemZ::LXAG: |
| 5205 | case SystemZ::LXAH: |
| 5206 | case SystemZ::LXAQ: |
| 5207 | case SystemZ::LY: |
| 5208 | case SystemZ::LZRF: |
| 5209 | case SystemZ::LZRG: |
| 5210 | case SystemZ::NTSTG: |
| 5211 | case SystemZ::STCH: |
| 5212 | case SystemZ::STCY: |
| 5213 | case SystemZ::STDY: |
| 5214 | case SystemZ::STE16Y: |
| 5215 | case SystemZ::STEY: |
| 5216 | case SystemZ::STFH: |
| 5217 | case SystemZ::STG: |
| 5218 | case SystemZ::STGSC: |
| 5219 | case SystemZ::STHH: |
| 5220 | case SystemZ::STHY: |
| 5221 | case SystemZ::STPQ: |
| 5222 | case SystemZ::STRV: |
| 5223 | case SystemZ::STRVG: |
| 5224 | case SystemZ::STRVH: |
| 5225 | case SystemZ::STY: { |
| 5226 | // op: R1 |
| 5227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5228 | Value |= (op & 0xf) << 36; |
| 5229 | // op: X2 |
| 5230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5231 | Value |= (op & 0xf) << 32; |
| 5232 | // op: B2 |
| 5233 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5234 | Value |= (op & 0xf) << 28; |
| 5235 | // op: D2 |
| 5236 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 2, Fixups, STI); |
| 5237 | Value |= (op & 0xfff) << 16; |
| 5238 | Value |= (op & 0xff000) >> 4; |
| 5239 | break; |
| 5240 | } |
| 5241 | case SystemZ::CDB: |
| 5242 | case SystemZ::CEB: |
| 5243 | case SystemZ::KDB: |
| 5244 | case SystemZ::KEB: |
| 5245 | case SystemZ::LDE: |
| 5246 | case SystemZ::LDE32: |
| 5247 | case SystemZ::LDEB: |
| 5248 | case SystemZ::LXD: |
| 5249 | case SystemZ::LXDB: |
| 5250 | case SystemZ::LXE: |
| 5251 | case SystemZ::LXEB: |
| 5252 | case SystemZ::SQD: |
| 5253 | case SystemZ::SQDB: |
| 5254 | case SystemZ::SQE: |
| 5255 | case SystemZ::SQEB: |
| 5256 | case SystemZ::TCDB: |
| 5257 | case SystemZ::TCEB: |
| 5258 | case SystemZ::TCXB: |
| 5259 | case SystemZ::TDCDT: |
| 5260 | case SystemZ::TDCET: |
| 5261 | case SystemZ::TDCXT: |
| 5262 | case SystemZ::TDGDT: |
| 5263 | case SystemZ::TDGET: |
| 5264 | case SystemZ::TDGXT: { |
| 5265 | // op: R1 |
| 5266 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5267 | Value |= (op & 0xf) << 36; |
| 5268 | // op: X2 |
| 5269 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5270 | Value |= (op & 0xf) << 32; |
| 5271 | // op: B2 |
| 5272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5273 | Value |= (op & 0xf) << 28; |
| 5274 | // op: D2 |
| 5275 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 5276 | Value |= (op & 0xfff) << 16; |
| 5277 | break; |
| 5278 | } |
| 5279 | case SystemZ::LCBB: { |
| 5280 | // op: R1 |
| 5281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5282 | Value |= (op & 0xf) << 36; |
| 5283 | // op: X2 |
| 5284 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5285 | Value |= (op & 0xf) << 32; |
| 5286 | // op: B2 |
| 5287 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5288 | Value |= (op & 0xf) << 28; |
| 5289 | // op: D2 |
| 5290 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 5291 | Value |= (op & 0xfff) << 16; |
| 5292 | // op: M3 |
| 5293 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 5294 | Value |= (op & 0xf) << 12; |
| 5295 | break; |
| 5296 | } |
| 5297 | case SystemZ::AG: |
| 5298 | case SystemZ::AGF: |
| 5299 | case SystemZ::AGH: |
| 5300 | case SystemZ::AHY: |
| 5301 | case SystemZ::ALC: |
| 5302 | case SystemZ::ALCG: |
| 5303 | case SystemZ::ALG: |
| 5304 | case SystemZ::ALGF: |
| 5305 | case SystemZ::ALY: |
| 5306 | case SystemZ::AY: |
| 5307 | case SystemZ::BCTG: |
| 5308 | case SystemZ::CVBG: |
| 5309 | case SystemZ::CVBY: |
| 5310 | case SystemZ::DL: |
| 5311 | case SystemZ::DLG: |
| 5312 | case SystemZ::DSG: |
| 5313 | case SystemZ::DSGF: |
| 5314 | case SystemZ::IC32Y: |
| 5315 | case SystemZ::ICY: |
| 5316 | case SystemZ::MFY: |
| 5317 | case SystemZ::MG: |
| 5318 | case SystemZ::MGH: |
| 5319 | case SystemZ::MHY: |
| 5320 | case SystemZ::ML: |
| 5321 | case SystemZ::MLG: |
| 5322 | case SystemZ::MSC: |
| 5323 | case SystemZ::MSG: |
| 5324 | case SystemZ::MSGC: |
| 5325 | case SystemZ::MSGF: |
| 5326 | case SystemZ::MSY: |
| 5327 | case SystemZ::NG: |
| 5328 | case SystemZ::NY: |
| 5329 | case SystemZ::OG: |
| 5330 | case SystemZ::OY: |
| 5331 | case SystemZ::SG: |
| 5332 | case SystemZ::SGF: |
| 5333 | case SystemZ::SGH: |
| 5334 | case SystemZ::SHY: |
| 5335 | case SystemZ::SLB: |
| 5336 | case SystemZ::SLBG: |
| 5337 | case SystemZ::SLG: |
| 5338 | case SystemZ::SLGF: |
| 5339 | case SystemZ::SLY: |
| 5340 | case SystemZ::SY: |
| 5341 | case SystemZ::XG: |
| 5342 | case SystemZ::XY: { |
| 5343 | // op: R1 |
| 5344 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5345 | Value |= (op & 0xf) << 36; |
| 5346 | // op: X2 |
| 5347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5348 | Value |= (op & 0xf) << 32; |
| 5349 | // op: B2 |
| 5350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5351 | Value |= (op & 0xf) << 28; |
| 5352 | // op: D2 |
| 5353 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 5354 | Value |= (op & 0xfff) << 16; |
| 5355 | Value |= (op & 0xff000) >> 4; |
| 5356 | break; |
| 5357 | } |
| 5358 | case SystemZ::ADB: |
| 5359 | case SystemZ::AEB: |
| 5360 | case SystemZ::DDB: |
| 5361 | case SystemZ::DEB: |
| 5362 | case SystemZ::MDB: |
| 5363 | case SystemZ::MDEB: |
| 5364 | case SystemZ::MEE: |
| 5365 | case SystemZ::MEEB: |
| 5366 | case SystemZ::MXDB: |
| 5367 | case SystemZ::SDB: |
| 5368 | case SystemZ::SEB: { |
| 5369 | // op: R1 |
| 5370 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5371 | Value |= (op & 0xf) << 36; |
| 5372 | // op: X2 |
| 5373 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5374 | Value |= (op & 0xf) << 32; |
| 5375 | // op: B2 |
| 5376 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5377 | Value |= (op & 0xf) << 28; |
| 5378 | // op: D2 |
| 5379 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 5380 | Value |= (op & 0xfff) << 16; |
| 5381 | break; |
| 5382 | } |
| 5383 | case SystemZ::EFPC: |
| 5384 | case SystemZ::EPAIR: |
| 5385 | case SystemZ::EPAR: |
| 5386 | case SystemZ::ESAIR: |
| 5387 | case SystemZ::ESAR: |
| 5388 | case SystemZ::ESEA: |
| 5389 | case SystemZ::ETND: |
| 5390 | case SystemZ::IAC: |
| 5391 | case SystemZ::IPM: |
| 5392 | case SystemZ::LZDR: |
| 5393 | case SystemZ::LZER: |
| 5394 | case SystemZ::LZER_16: |
| 5395 | case SystemZ::LZXR: |
| 5396 | case SystemZ::MSTA: |
| 5397 | case SystemZ::PTF: |
| 5398 | case SystemZ::SFASR: |
| 5399 | case SystemZ::SFPC: |
| 5400 | case SystemZ::SPM: |
| 5401 | case SystemZ::SSAIR: |
| 5402 | case SystemZ::SSAR: { |
| 5403 | // op: R1 |
| 5404 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5405 | Value |= (op & 0xf) << 4; |
| 5406 | break; |
| 5407 | } |
| 5408 | case SystemZ::NOTGR: |
| 5409 | case SystemZ::NOTR: { |
| 5410 | // op: R1 |
| 5411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5412 | Value |= (op & 0xf) << 4; |
| 5413 | // op: R2 |
| 5414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5415 | Value |= (op & 0xf) << 12; |
| 5416 | Value |= (op & 0xf); |
| 5417 | break; |
| 5418 | } |
| 5419 | case SystemZ::BAKR: |
| 5420 | case SystemZ::BALR: |
| 5421 | case SystemZ::BASR: |
| 5422 | case SystemZ::BASSM: |
| 5423 | case SystemZ::BSA: |
| 5424 | case SystemZ::BSG: |
| 5425 | case SystemZ::BSM: |
| 5426 | case SystemZ::CDBR: |
| 5427 | case SystemZ::CDFBR: |
| 5428 | case SystemZ::CDFR: |
| 5429 | case SystemZ::CDGBR: |
| 5430 | case SystemZ::CDGR: |
| 5431 | case SystemZ::CDGTR: |
| 5432 | case SystemZ::CDR: |
| 5433 | case SystemZ::CDSTR: |
| 5434 | case SystemZ::CDTR: |
| 5435 | case SystemZ::CDUTR: |
| 5436 | case SystemZ::CEBR: |
| 5437 | case SystemZ::CEDTR: |
| 5438 | case SystemZ::CEFBR: |
| 5439 | case SystemZ::CEFR: |
| 5440 | case SystemZ::CEGBR: |
| 5441 | case SystemZ::CEGR: |
| 5442 | case SystemZ::CER: |
| 5443 | case SystemZ::CEXTR: |
| 5444 | case SystemZ::CGFR: |
| 5445 | case SystemZ::CGR: |
| 5446 | case SystemZ::CGRTAsmE: |
| 5447 | case SystemZ::CGRTAsmH: |
| 5448 | case SystemZ::CGRTAsmHE: |
| 5449 | case SystemZ::CGRTAsmL: |
| 5450 | case SystemZ::CGRTAsmLE: |
| 5451 | case SystemZ::CGRTAsmLH: |
| 5452 | case SystemZ::CGRTAsmNE: |
| 5453 | case SystemZ::CGRTAsmNH: |
| 5454 | case SystemZ::CGRTAsmNHE: |
| 5455 | case SystemZ::CGRTAsmNL: |
| 5456 | case SystemZ::CGRTAsmNLE: |
| 5457 | case SystemZ::CGRTAsmNLH: |
| 5458 | case SystemZ::CHHR: |
| 5459 | case SystemZ::CHLR: |
| 5460 | case SystemZ::CKSM: |
| 5461 | case SystemZ::CLCL: |
| 5462 | case SystemZ::CLGFR: |
| 5463 | case SystemZ::CLGR: |
| 5464 | case SystemZ::CLGRTAsmE: |
| 5465 | case SystemZ::CLGRTAsmH: |
| 5466 | case SystemZ::CLGRTAsmHE: |
| 5467 | case SystemZ::CLGRTAsmL: |
| 5468 | case SystemZ::CLGRTAsmLE: |
| 5469 | case SystemZ::CLGRTAsmLH: |
| 5470 | case SystemZ::CLGRTAsmNE: |
| 5471 | case SystemZ::CLGRTAsmNH: |
| 5472 | case SystemZ::CLGRTAsmNHE: |
| 5473 | case SystemZ::CLGRTAsmNL: |
| 5474 | case SystemZ::CLGRTAsmNLE: |
| 5475 | case SystemZ::CLGRTAsmNLH: |
| 5476 | case SystemZ::CLHHR: |
| 5477 | case SystemZ::CLHLR: |
| 5478 | case SystemZ::CLR: |
| 5479 | case SystemZ::CLRTAsmE: |
| 5480 | case SystemZ::CLRTAsmH: |
| 5481 | case SystemZ::CLRTAsmHE: |
| 5482 | case SystemZ::CLRTAsmL: |
| 5483 | case SystemZ::CLRTAsmLE: |
| 5484 | case SystemZ::CLRTAsmLH: |
| 5485 | case SystemZ::CLRTAsmNE: |
| 5486 | case SystemZ::CLRTAsmNH: |
| 5487 | case SystemZ::CLRTAsmNHE: |
| 5488 | case SystemZ::CLRTAsmNL: |
| 5489 | case SystemZ::CLRTAsmNLE: |
| 5490 | case SystemZ::CLRTAsmNLH: |
| 5491 | case SystemZ::CLST: |
| 5492 | case SystemZ::CLZG: |
| 5493 | case SystemZ::CMPSC: |
| 5494 | case SystemZ::CPYA: |
| 5495 | case SystemZ::CR: |
| 5496 | case SystemZ::CRTAsmE: |
| 5497 | case SystemZ::CRTAsmH: |
| 5498 | case SystemZ::CRTAsmHE: |
| 5499 | case SystemZ::CRTAsmL: |
| 5500 | case SystemZ::CRTAsmLE: |
| 5501 | case SystemZ::CRTAsmLH: |
| 5502 | case SystemZ::CRTAsmNE: |
| 5503 | case SystemZ::CRTAsmNH: |
| 5504 | case SystemZ::CRTAsmNHE: |
| 5505 | case SystemZ::CRTAsmNL: |
| 5506 | case SystemZ::CRTAsmNLE: |
| 5507 | case SystemZ::CRTAsmNLH: |
| 5508 | case SystemZ::CTZG: |
| 5509 | case SystemZ::CU12Opt: |
| 5510 | case SystemZ::CU14Opt: |
| 5511 | case SystemZ::CU21Opt: |
| 5512 | case SystemZ::CU24Opt: |
| 5513 | case SystemZ::CU41: |
| 5514 | case SystemZ::CU42: |
| 5515 | case SystemZ::CUDTR: |
| 5516 | case SystemZ::CUSE: |
| 5517 | case SystemZ::CUTFUOpt: |
| 5518 | case SystemZ::CUUTFOpt: |
| 5519 | case SystemZ::CUXTR: |
| 5520 | case SystemZ::CXBR: |
| 5521 | case SystemZ::CXFBR: |
| 5522 | case SystemZ::CXFR: |
| 5523 | case SystemZ::CXGBR: |
| 5524 | case SystemZ::CXGR: |
| 5525 | case SystemZ::CXGTR: |
| 5526 | case SystemZ::CXR: |
| 5527 | case SystemZ::CXSTR: |
| 5528 | case SystemZ::CXTR: |
| 5529 | case SystemZ::CXUTR: |
| 5530 | case SystemZ::EAR: |
| 5531 | case SystemZ::ECCTR: |
| 5532 | case SystemZ::ECPGA: |
| 5533 | case SystemZ::EEDTR: |
| 5534 | case SystemZ::EEXTR: |
| 5535 | case SystemZ::EPCTR: |
| 5536 | case SystemZ::EPSW: |
| 5537 | case SystemZ::EREG: |
| 5538 | case SystemZ::EREGG: |
| 5539 | case SystemZ::ESDTR: |
| 5540 | case SystemZ::ESTA: |
| 5541 | case SystemZ::ESXTR: |
| 5542 | case SystemZ::FIDR: |
| 5543 | case SystemZ::FIER: |
| 5544 | case SystemZ::FIXR: |
| 5545 | case SystemZ::FLOGR: |
| 5546 | case SystemZ::HDR: |
| 5547 | case SystemZ::HER: |
| 5548 | case SystemZ::IPTEOptOpt: |
| 5549 | case SystemZ::IRBM: |
| 5550 | case SystemZ::KDBR: |
| 5551 | case SystemZ::KDTR: |
| 5552 | case SystemZ::KEBR: |
| 5553 | case SystemZ::KM: |
| 5554 | case SystemZ::KMC: |
| 5555 | case SystemZ::KMF: |
| 5556 | case SystemZ::KMO: |
| 5557 | case SystemZ::KXBR: |
| 5558 | case SystemZ::KXTR: |
| 5559 | case SystemZ::LBR: |
| 5560 | case SystemZ::LCDBR: |
| 5561 | case SystemZ::LCDFR: |
| 5562 | case SystemZ::LCDFR_16: |
| 5563 | case SystemZ::LCDFR_32: |
| 5564 | case SystemZ::LCDR: |
| 5565 | case SystemZ::LCEBR: |
| 5566 | case SystemZ::LCER: |
| 5567 | case SystemZ::LCGFR: |
| 5568 | case SystemZ::LCGR: |
| 5569 | case SystemZ::LCR: |
| 5570 | case SystemZ::LCXBR: |
| 5571 | case SystemZ::LCXR: |
| 5572 | case SystemZ::LDEBR: |
| 5573 | case SystemZ::LDER: |
| 5574 | case SystemZ::LDGR: |
| 5575 | case SystemZ::LDR: |
| 5576 | case SystemZ::LDR16: |
| 5577 | case SystemZ::LDR32: |
| 5578 | case SystemZ::LDXBR: |
| 5579 | case SystemZ::LDXR: |
| 5580 | case SystemZ::LEDBR: |
| 5581 | case SystemZ::LEDR: |
| 5582 | case SystemZ::LER: |
| 5583 | case SystemZ::LER16: |
| 5584 | case SystemZ::LEXBR: |
| 5585 | case SystemZ::LEXR: |
| 5586 | case SystemZ::LGBR: |
| 5587 | case SystemZ::LGDR: |
| 5588 | case SystemZ::LGFR: |
| 5589 | case SystemZ::LGHR: |
| 5590 | case SystemZ::LGR: |
| 5591 | case SystemZ::LHR: |
| 5592 | case SystemZ::LLCR: |
| 5593 | case SystemZ::LLGCR: |
| 5594 | case SystemZ::LLGFR: |
| 5595 | case SystemZ::LLGHR: |
| 5596 | case SystemZ::LLGTR: |
| 5597 | case SystemZ::LLHR: |
| 5598 | case SystemZ::LNDBR: |
| 5599 | case SystemZ::LNDFR: |
| 5600 | case SystemZ::LNDFR_16: |
| 5601 | case SystemZ::LNDFR_32: |
| 5602 | case SystemZ::LNDR: |
| 5603 | case SystemZ::LNEBR: |
| 5604 | case SystemZ::LNER: |
| 5605 | case SystemZ::LNGFR: |
| 5606 | case SystemZ::LNGR: |
| 5607 | case SystemZ::LNR: |
| 5608 | case SystemZ::LNXBR: |
| 5609 | case SystemZ::LNXR: |
| 5610 | case SystemZ::LPDBR: |
| 5611 | case SystemZ::LPDFR: |
| 5612 | case SystemZ::LPDFR_16: |
| 5613 | case SystemZ::LPDFR_32: |
| 5614 | case SystemZ::LPDR: |
| 5615 | case SystemZ::LPEBR: |
| 5616 | case SystemZ::LPER: |
| 5617 | case SystemZ::LPGFR: |
| 5618 | case SystemZ::LPGR: |
| 5619 | case SystemZ::LPR: |
| 5620 | case SystemZ::LPXBR: |
| 5621 | case SystemZ::LPXR: |
| 5622 | case SystemZ::LR: |
| 5623 | case SystemZ::LRDR: |
| 5624 | case SystemZ::LRER: |
| 5625 | case SystemZ::LRVGR: |
| 5626 | case SystemZ::LRVR: |
| 5627 | case SystemZ::LTDBR: |
| 5628 | case SystemZ::LTDR: |
| 5629 | case SystemZ::LTDTR: |
| 5630 | case SystemZ::LTEBR: |
| 5631 | case SystemZ::LTER: |
| 5632 | case SystemZ::LTGFR: |
| 5633 | case SystemZ::LTGR: |
| 5634 | case SystemZ::LTR: |
| 5635 | case SystemZ::LTXBR: |
| 5636 | case SystemZ::LTXR: |
| 5637 | case SystemZ::LTXTR: |
| 5638 | case SystemZ::LURA: |
| 5639 | case SystemZ::LURAG: |
| 5640 | case SystemZ::LXDBR: |
| 5641 | case SystemZ::LXDR: |
| 5642 | case SystemZ::LXEBR: |
| 5643 | case SystemZ::LXER: |
| 5644 | case SystemZ::LXR: |
| 5645 | case SystemZ::MVCL: |
| 5646 | case SystemZ::MVPG: |
| 5647 | case SystemZ::MVST: |
| 5648 | case SystemZ::PGIN: |
| 5649 | case SystemZ::PGOUT: |
| 5650 | case SystemZ::POPCNT: |
| 5651 | case SystemZ::PPNO: |
| 5652 | case SystemZ::PRNO: |
| 5653 | case SystemZ::PT: |
| 5654 | case SystemZ::PTI: |
| 5655 | case SystemZ::RRBE: |
| 5656 | case SystemZ::RRBM: |
| 5657 | case SystemZ::SAR: |
| 5658 | case SystemZ::SCCTR: |
| 5659 | case SystemZ::SORTL: |
| 5660 | case SystemZ::SPCTR: |
| 5661 | case SystemZ::SQDBR: |
| 5662 | case SystemZ::SQDR: |
| 5663 | case SystemZ::SQEBR: |
| 5664 | case SystemZ::SQER: |
| 5665 | case SystemZ::SQXBR: |
| 5666 | case SystemZ::SQXR: |
| 5667 | case SystemZ::SRST: |
| 5668 | case SystemZ::SRSTU: |
| 5669 | case SystemZ::SSKEOpt: |
| 5670 | case SystemZ::STURA: |
| 5671 | case SystemZ::STURG: |
| 5672 | case SystemZ::TAR: |
| 5673 | case SystemZ::TB: |
| 5674 | case SystemZ::THDER: |
| 5675 | case SystemZ::THDR: |
| 5676 | case SystemZ::TPEI: |
| 5677 | case SystemZ::TRE: |
| 5678 | case SystemZ::TROOOpt: |
| 5679 | case SystemZ::TROTOpt: |
| 5680 | case SystemZ::TRTOOpt: |
| 5681 | case SystemZ::TRTTOpt: { |
| 5682 | // op: R1 |
| 5683 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5684 | Value |= (op & 0xf) << 4; |
| 5685 | // op: R2 |
| 5686 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5687 | Value |= (op & 0xf); |
| 5688 | break; |
| 5689 | } |
| 5690 | case SystemZ::CGRTAsm: |
| 5691 | case SystemZ::CLGRTAsm: |
| 5692 | case SystemZ::CLRTAsm: |
| 5693 | case SystemZ::CRTAsm: |
| 5694 | case SystemZ::POPCNTOpt: |
| 5695 | case SystemZ::PPA: |
| 5696 | case SystemZ::SSKE: { |
| 5697 | // op: R1 |
| 5698 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5699 | Value |= (op & 0xf) << 4; |
| 5700 | // op: R2 |
| 5701 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5702 | Value |= (op & 0xf); |
| 5703 | // op: M3 |
| 5704 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 5705 | Value |= (op & 0xf) << 12; |
| 5706 | break; |
| 5707 | } |
| 5708 | case SystemZ::CU12: |
| 5709 | case SystemZ::CU14: |
| 5710 | case SystemZ::CU21: |
| 5711 | case SystemZ::CU24: |
| 5712 | case SystemZ::CUTFU: |
| 5713 | case SystemZ::CUUTF: |
| 5714 | case SystemZ::KIMDOpt: |
| 5715 | case SystemZ::KLMDOpt: |
| 5716 | case SystemZ::TROO: |
| 5717 | case SystemZ::TROT: |
| 5718 | case SystemZ::TRTO: |
| 5719 | case SystemZ::TRTT: { |
| 5720 | // op: R1 |
| 5721 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5722 | Value |= (op & 0xf) << 4; |
| 5723 | // op: R2 |
| 5724 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5725 | Value |= (op & 0xf); |
| 5726 | // op: M3 |
| 5727 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 5728 | Value |= (op & 0xf) << 12; |
| 5729 | break; |
| 5730 | } |
| 5731 | case SystemZ::CGRT: |
| 5732 | case SystemZ::CLGRT: |
| 5733 | case SystemZ::CLRT: |
| 5734 | case SystemZ::CRT: { |
| 5735 | // op: R1 |
| 5736 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5737 | Value |= (op & 0xf) << 4; |
| 5738 | // op: R2 |
| 5739 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5740 | Value |= (op & 0xf); |
| 5741 | // op: M3 |
| 5742 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5743 | Value |= (op & 0xf) << 12; |
| 5744 | break; |
| 5745 | } |
| 5746 | case SystemZ::CSDTR: |
| 5747 | case SystemZ::CSXTR: |
| 5748 | case SystemZ::LDETR: |
| 5749 | case SystemZ::LXDTR: { |
| 5750 | // op: R1 |
| 5751 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5752 | Value |= (op & 0xf) << 4; |
| 5753 | // op: R2 |
| 5754 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5755 | Value |= (op & 0xf); |
| 5756 | // op: M4 |
| 5757 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 5758 | Value |= (op & 0xf) << 8; |
| 5759 | break; |
| 5760 | } |
| 5761 | case SystemZ::ADTR: |
| 5762 | case SystemZ::AGRK: |
| 5763 | case SystemZ::AHHHR: |
| 5764 | case SystemZ::AHHLR: |
| 5765 | case SystemZ::ALGRK: |
| 5766 | case SystemZ::ALHHHR: |
| 5767 | case SystemZ::ALHHLR: |
| 5768 | case SystemZ::ALRK: |
| 5769 | case SystemZ::ARK: |
| 5770 | case SystemZ::AXTR: |
| 5771 | case SystemZ::BDEPG: |
| 5772 | case SystemZ::BEXTG: |
| 5773 | case SystemZ::CPSDRdd: |
| 5774 | case SystemZ::CPSDRdh: |
| 5775 | case SystemZ::CPSDRds: |
| 5776 | case SystemZ::CPSDRhd: |
| 5777 | case SystemZ::CPSDRhh: |
| 5778 | case SystemZ::CPSDRhs: |
| 5779 | case SystemZ::CPSDRsd: |
| 5780 | case SystemZ::CPSDRsh: |
| 5781 | case SystemZ::CPSDRss: |
| 5782 | case SystemZ::CRDTEOpt: |
| 5783 | case SystemZ::DDTR: |
| 5784 | case SystemZ::DXTR: |
| 5785 | case SystemZ::IDTEOpt: |
| 5786 | case SystemZ::IEDTR: |
| 5787 | case SystemZ::IEXTR: |
| 5788 | case SystemZ::IPTEOpt: |
| 5789 | case SystemZ::KMA: |
| 5790 | case SystemZ::KMCTR: |
| 5791 | case SystemZ::MDTR: |
| 5792 | case SystemZ::MGRK: |
| 5793 | case SystemZ::MSGRKC: |
| 5794 | case SystemZ::MSRKC: |
| 5795 | case SystemZ::MXTR: |
| 5796 | case SystemZ::NCGRK: |
| 5797 | case SystemZ::NCRK: |
| 5798 | case SystemZ::NGRK: |
| 5799 | case SystemZ::NNGRK: |
| 5800 | case SystemZ::NNRK: |
| 5801 | case SystemZ::NOGRK: |
| 5802 | case SystemZ::NORK: |
| 5803 | case SystemZ::NRK: |
| 5804 | case SystemZ::NXGRK: |
| 5805 | case SystemZ::NXRK: |
| 5806 | case SystemZ::OCGRK: |
| 5807 | case SystemZ::OCRK: |
| 5808 | case SystemZ::OGRK: |
| 5809 | case SystemZ::ORK: |
| 5810 | case SystemZ::RDPOpt: |
| 5811 | case SystemZ::SDTR: |
| 5812 | case SystemZ::SGRK: |
| 5813 | case SystemZ::SHHHR: |
| 5814 | case SystemZ::SHHLR: |
| 5815 | case SystemZ::SLGRK: |
| 5816 | case SystemZ::SLHHHR: |
| 5817 | case SystemZ::SLHHLR: |
| 5818 | case SystemZ::SLRK: |
| 5819 | case SystemZ::SRK: |
| 5820 | case SystemZ::SXTR: |
| 5821 | case SystemZ::XGRK: |
| 5822 | case SystemZ::XRK: { |
| 5823 | // op: R1 |
| 5824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5825 | Value |= (op & 0xf) << 4; |
| 5826 | // op: R2 |
| 5827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5828 | Value |= (op & 0xf); |
| 5829 | // op: R3 |
| 5830 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5831 | Value |= (op & 0xf) << 12; |
| 5832 | break; |
| 5833 | } |
| 5834 | case SystemZ::ADTRA: |
| 5835 | case SystemZ::AXTRA: |
| 5836 | case SystemZ::CRDTE: |
| 5837 | case SystemZ::DDTRA: |
| 5838 | case SystemZ::DXTRA: |
| 5839 | case SystemZ::IDTE: |
| 5840 | case SystemZ::IPTE: |
| 5841 | case SystemZ::MDTRA: |
| 5842 | case SystemZ::MXTRA: |
| 5843 | case SystemZ::RDP: |
| 5844 | case SystemZ::SDTRA: |
| 5845 | case SystemZ::SXTRA: { |
| 5846 | // op: R1 |
| 5847 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5848 | Value |= (op & 0xf) << 4; |
| 5849 | // op: R2 |
| 5850 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5851 | Value |= (op & 0xf); |
| 5852 | // op: R3 |
| 5853 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5854 | Value |= (op & 0xf) << 12; |
| 5855 | // op: M4 |
| 5856 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 5857 | Value |= (op & 0xf) << 8; |
| 5858 | break; |
| 5859 | } |
| 5860 | case SystemZ::DFLTCC: { |
| 5861 | // op: R1 |
| 5862 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5863 | Value |= (op & 0xf) << 4; |
| 5864 | // op: R2 |
| 5865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5866 | Value |= (op & 0xf); |
| 5867 | // op: R3 |
| 5868 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5869 | Value |= (op & 0xf) << 12; |
| 5870 | break; |
| 5871 | } |
| 5872 | case SystemZ::ADBR: |
| 5873 | case SystemZ::ADR: |
| 5874 | case SystemZ::AEBR: |
| 5875 | case SystemZ::AER: |
| 5876 | case SystemZ::AGFR: |
| 5877 | case SystemZ::AGR: |
| 5878 | case SystemZ::ALCGR: |
| 5879 | case SystemZ::ALCR: |
| 5880 | case SystemZ::ALGFR: |
| 5881 | case SystemZ::ALGR: |
| 5882 | case SystemZ::ALR: |
| 5883 | case SystemZ::AR: |
| 5884 | case SystemZ::AUR: |
| 5885 | case SystemZ::AWR: |
| 5886 | case SystemZ::AXBR: |
| 5887 | case SystemZ::AXR: |
| 5888 | case SystemZ::BCTGR: |
| 5889 | case SystemZ::BCTR: |
| 5890 | case SystemZ::CSP: |
| 5891 | case SystemZ::CSPG: |
| 5892 | case SystemZ::DDBR: |
| 5893 | case SystemZ::DDR: |
| 5894 | case SystemZ::DEBR: |
| 5895 | case SystemZ::DER: |
| 5896 | case SystemZ::DLGR: |
| 5897 | case SystemZ::DLR: |
| 5898 | case SystemZ::DR: |
| 5899 | case SystemZ::DSGFR: |
| 5900 | case SystemZ::DSGR: |
| 5901 | case SystemZ::DXBR: |
| 5902 | case SystemZ::DXR: |
| 5903 | case SystemZ::ISKE: |
| 5904 | case SystemZ::IVSK: |
| 5905 | case SystemZ::LOCFHRAsmE: |
| 5906 | case SystemZ::LOCFHRAsmH: |
| 5907 | case SystemZ::LOCFHRAsmHE: |
| 5908 | case SystemZ::LOCFHRAsmL: |
| 5909 | case SystemZ::LOCFHRAsmLE: |
| 5910 | case SystemZ::LOCFHRAsmLH: |
| 5911 | case SystemZ::LOCFHRAsmM: |
| 5912 | case SystemZ::LOCFHRAsmNE: |
| 5913 | case SystemZ::LOCFHRAsmNH: |
| 5914 | case SystemZ::LOCFHRAsmNHE: |
| 5915 | case SystemZ::LOCFHRAsmNL: |
| 5916 | case SystemZ::LOCFHRAsmNLE: |
| 5917 | case SystemZ::LOCFHRAsmNLH: |
| 5918 | case SystemZ::LOCFHRAsmNM: |
| 5919 | case SystemZ::LOCFHRAsmNO: |
| 5920 | case SystemZ::LOCFHRAsmNP: |
| 5921 | case SystemZ::LOCFHRAsmNZ: |
| 5922 | case SystemZ::LOCFHRAsmO: |
| 5923 | case SystemZ::LOCFHRAsmP: |
| 5924 | case SystemZ::LOCFHRAsmZ: |
| 5925 | case SystemZ::LOCGRAsmE: |
| 5926 | case SystemZ::LOCGRAsmH: |
| 5927 | case SystemZ::LOCGRAsmHE: |
| 5928 | case SystemZ::LOCGRAsmL: |
| 5929 | case SystemZ::LOCGRAsmLE: |
| 5930 | case SystemZ::LOCGRAsmLH: |
| 5931 | case SystemZ::LOCGRAsmM: |
| 5932 | case SystemZ::LOCGRAsmNE: |
| 5933 | case SystemZ::LOCGRAsmNH: |
| 5934 | case SystemZ::LOCGRAsmNHE: |
| 5935 | case SystemZ::LOCGRAsmNL: |
| 5936 | case SystemZ::LOCGRAsmNLE: |
| 5937 | case SystemZ::LOCGRAsmNLH: |
| 5938 | case SystemZ::LOCGRAsmNM: |
| 5939 | case SystemZ::LOCGRAsmNO: |
| 5940 | case SystemZ::LOCGRAsmNP: |
| 5941 | case SystemZ::LOCGRAsmNZ: |
| 5942 | case SystemZ::LOCGRAsmO: |
| 5943 | case SystemZ::LOCGRAsmP: |
| 5944 | case SystemZ::LOCGRAsmZ: |
| 5945 | case SystemZ::LOCRAsmE: |
| 5946 | case SystemZ::LOCRAsmH: |
| 5947 | case SystemZ::LOCRAsmHE: |
| 5948 | case SystemZ::LOCRAsmL: |
| 5949 | case SystemZ::LOCRAsmLE: |
| 5950 | case SystemZ::LOCRAsmLH: |
| 5951 | case SystemZ::LOCRAsmM: |
| 5952 | case SystemZ::LOCRAsmNE: |
| 5953 | case SystemZ::LOCRAsmNH: |
| 5954 | case SystemZ::LOCRAsmNHE: |
| 5955 | case SystemZ::LOCRAsmNL: |
| 5956 | case SystemZ::LOCRAsmNLE: |
| 5957 | case SystemZ::LOCRAsmNLH: |
| 5958 | case SystemZ::LOCRAsmNM: |
| 5959 | case SystemZ::LOCRAsmNO: |
| 5960 | case SystemZ::LOCRAsmNP: |
| 5961 | case SystemZ::LOCRAsmNZ: |
| 5962 | case SystemZ::LOCRAsmO: |
| 5963 | case SystemZ::LOCRAsmP: |
| 5964 | case SystemZ::LOCRAsmZ: |
| 5965 | case SystemZ::MDBR: |
| 5966 | case SystemZ::MDEBR: |
| 5967 | case SystemZ::MDER: |
| 5968 | case SystemZ::MDR: |
| 5969 | case SystemZ::MEEBR: |
| 5970 | case SystemZ::MEER: |
| 5971 | case SystemZ::MER: |
| 5972 | case SystemZ::MLGR: |
| 5973 | case SystemZ::MLR: |
| 5974 | case SystemZ::MR: |
| 5975 | case SystemZ::MSGFR: |
| 5976 | case SystemZ::MSGR: |
| 5977 | case SystemZ::MSR: |
| 5978 | case SystemZ::MXBR: |
| 5979 | case SystemZ::MXDBR: |
| 5980 | case SystemZ::MXDR: |
| 5981 | case SystemZ::MXR: |
| 5982 | case SystemZ::NGR: |
| 5983 | case SystemZ::NR: |
| 5984 | case SystemZ::OGR: |
| 5985 | case SystemZ::OR: |
| 5986 | case SystemZ::SDBR: |
| 5987 | case SystemZ::SDR: |
| 5988 | case SystemZ::SEBR: |
| 5989 | case SystemZ::SER: |
| 5990 | case SystemZ::SGFR: |
| 5991 | case SystemZ::SGR: |
| 5992 | case SystemZ::SLBGR: |
| 5993 | case SystemZ::SLBR: |
| 5994 | case SystemZ::SLGFR: |
| 5995 | case SystemZ::SLGR: |
| 5996 | case SystemZ::SLR: |
| 5997 | case SystemZ::SR: |
| 5998 | case SystemZ::SUR: |
| 5999 | case SystemZ::SWR: |
| 6000 | case SystemZ::SXBR: |
| 6001 | case SystemZ::SXR: |
| 6002 | case SystemZ::XGR: |
| 6003 | case SystemZ::XR: { |
| 6004 | // op: R1 |
| 6005 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6006 | Value |= (op & 0xf) << 4; |
| 6007 | // op: R2 |
| 6008 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6009 | Value |= (op & 0xf); |
| 6010 | break; |
| 6011 | } |
| 6012 | case SystemZ::CFDBR: |
| 6013 | case SystemZ::CFDR: |
| 6014 | case SystemZ::CFEBR: |
| 6015 | case SystemZ::CFER: |
| 6016 | case SystemZ::CFXBR: |
| 6017 | case SystemZ::CFXR: |
| 6018 | case SystemZ::CGDBR: |
| 6019 | case SystemZ::CGDR: |
| 6020 | case SystemZ::CGDTR: |
| 6021 | case SystemZ::CGEBR: |
| 6022 | case SystemZ::CGER: |
| 6023 | case SystemZ::CGXBR: |
| 6024 | case SystemZ::CGXR: |
| 6025 | case SystemZ::CGXTR: |
| 6026 | case SystemZ::FIDBR: |
| 6027 | case SystemZ::FIEBR: |
| 6028 | case SystemZ::FIXBR: |
| 6029 | case SystemZ::TBDR: |
| 6030 | case SystemZ::TBEDR: { |
| 6031 | // op: R1 |
| 6032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6033 | Value |= (op & 0xf) << 4; |
| 6034 | // op: R2 |
| 6035 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6036 | Value |= (op & 0xf); |
| 6037 | // op: M3 |
| 6038 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 6039 | Value |= (op & 0xf) << 12; |
| 6040 | break; |
| 6041 | } |
| 6042 | case SystemZ::CDFBRA: |
| 6043 | case SystemZ::CDFTR: |
| 6044 | case SystemZ::CDGBRA: |
| 6045 | case SystemZ::CDGTRA: |
| 6046 | case SystemZ::CDLFBR: |
| 6047 | case SystemZ::CDLFTR: |
| 6048 | case SystemZ::CDLGBR: |
| 6049 | case SystemZ::CDLGTR: |
| 6050 | case SystemZ::CEFBRA: |
| 6051 | case SystemZ::CEGBRA: |
| 6052 | case SystemZ::CELFBR: |
| 6053 | case SystemZ::CELGBR: |
| 6054 | case SystemZ::CFDBRA: |
| 6055 | case SystemZ::CFDTR: |
| 6056 | case SystemZ::CFEBRA: |
| 6057 | case SystemZ::CFXBRA: |
| 6058 | case SystemZ::CFXTR: |
| 6059 | case SystemZ::CGDBRA: |
| 6060 | case SystemZ::CGDTRA: |
| 6061 | case SystemZ::CGEBRA: |
| 6062 | case SystemZ::CGXBRA: |
| 6063 | case SystemZ::CGXTRA: |
| 6064 | case SystemZ::CLFDBR: |
| 6065 | case SystemZ::CLFDTR: |
| 6066 | case SystemZ::CLFEBR: |
| 6067 | case SystemZ::CLFXBR: |
| 6068 | case SystemZ::CLFXTR: |
| 6069 | case SystemZ::CLGDBR: |
| 6070 | case SystemZ::CLGDTR: |
| 6071 | case SystemZ::CLGEBR: |
| 6072 | case SystemZ::CLGXBR: |
| 6073 | case SystemZ::CLGXTR: |
| 6074 | case SystemZ::CXFBRA: |
| 6075 | case SystemZ::CXFTR: |
| 6076 | case SystemZ::CXGBRA: |
| 6077 | case SystemZ::CXGTRA: |
| 6078 | case SystemZ::CXLFBR: |
| 6079 | case SystemZ::CXLFTR: |
| 6080 | case SystemZ::CXLGBR: |
| 6081 | case SystemZ::CXLGTR: |
| 6082 | case SystemZ::FIDBRA: |
| 6083 | case SystemZ::FIDTR: |
| 6084 | case SystemZ::FIEBRA: |
| 6085 | case SystemZ::FIXBRA: |
| 6086 | case SystemZ::FIXTR: |
| 6087 | case SystemZ::LDXBRA: |
| 6088 | case SystemZ::LDXTR: |
| 6089 | case SystemZ::LEDBRA: |
| 6090 | case SystemZ::LEDTR: |
| 6091 | case SystemZ::LEXBRA: { |
| 6092 | // op: R1 |
| 6093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6094 | Value |= (op & 0xf) << 4; |
| 6095 | // op: R2 |
| 6096 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6097 | Value |= (op & 0xf); |
| 6098 | // op: M3 |
| 6099 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 6100 | Value |= (op & 0xf) << 12; |
| 6101 | // op: M4 |
| 6102 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6103 | Value |= (op & 0xf) << 8; |
| 6104 | break; |
| 6105 | } |
| 6106 | case SystemZ::LOCFHRAsm: |
| 6107 | case SystemZ::LOCGRAsm: |
| 6108 | case SystemZ::LOCRAsm: { |
| 6109 | // op: R1 |
| 6110 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6111 | Value |= (op & 0xf) << 4; |
| 6112 | // op: R2 |
| 6113 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6114 | Value |= (op & 0xf); |
| 6115 | // op: M3 |
| 6116 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6117 | Value |= (op & 0xf) << 12; |
| 6118 | break; |
| 6119 | } |
| 6120 | case SystemZ::LOCFHR: |
| 6121 | case SystemZ::LOCGR: |
| 6122 | case SystemZ::LOCR: { |
| 6123 | // op: R1 |
| 6124 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6125 | Value |= (op & 0xf) << 4; |
| 6126 | // op: R2 |
| 6127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6128 | Value |= (op & 0xf); |
| 6129 | // op: M3 |
| 6130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6131 | Value |= (op & 0xf) << 12; |
| 6132 | break; |
| 6133 | } |
| 6134 | case SystemZ::SELFHRAsmE: |
| 6135 | case SystemZ::SELFHRAsmH: |
| 6136 | case SystemZ::SELFHRAsmHE: |
| 6137 | case SystemZ::SELFHRAsmL: |
| 6138 | case SystemZ::SELFHRAsmLE: |
| 6139 | case SystemZ::SELFHRAsmLH: |
| 6140 | case SystemZ::SELFHRAsmM: |
| 6141 | case SystemZ::SELFHRAsmNE: |
| 6142 | case SystemZ::SELFHRAsmNH: |
| 6143 | case SystemZ::SELFHRAsmNHE: |
| 6144 | case SystemZ::SELFHRAsmNL: |
| 6145 | case SystemZ::SELFHRAsmNLE: |
| 6146 | case SystemZ::SELFHRAsmNLH: |
| 6147 | case SystemZ::SELFHRAsmNM: |
| 6148 | case SystemZ::SELFHRAsmNO: |
| 6149 | case SystemZ::SELFHRAsmNP: |
| 6150 | case SystemZ::SELFHRAsmNZ: |
| 6151 | case SystemZ::SELFHRAsmO: |
| 6152 | case SystemZ::SELFHRAsmP: |
| 6153 | case SystemZ::SELFHRAsmZ: |
| 6154 | case SystemZ::SELGRAsmE: |
| 6155 | case SystemZ::SELGRAsmH: |
| 6156 | case SystemZ::SELGRAsmHE: |
| 6157 | case SystemZ::SELGRAsmL: |
| 6158 | case SystemZ::SELGRAsmLE: |
| 6159 | case SystemZ::SELGRAsmLH: |
| 6160 | case SystemZ::SELGRAsmM: |
| 6161 | case SystemZ::SELGRAsmNE: |
| 6162 | case SystemZ::SELGRAsmNH: |
| 6163 | case SystemZ::SELGRAsmNHE: |
| 6164 | case SystemZ::SELGRAsmNL: |
| 6165 | case SystemZ::SELGRAsmNLE: |
| 6166 | case SystemZ::SELGRAsmNLH: |
| 6167 | case SystemZ::SELGRAsmNM: |
| 6168 | case SystemZ::SELGRAsmNO: |
| 6169 | case SystemZ::SELGRAsmNP: |
| 6170 | case SystemZ::SELGRAsmNZ: |
| 6171 | case SystemZ::SELGRAsmO: |
| 6172 | case SystemZ::SELGRAsmP: |
| 6173 | case SystemZ::SELGRAsmZ: |
| 6174 | case SystemZ::SELRAsmE: |
| 6175 | case SystemZ::SELRAsmH: |
| 6176 | case SystemZ::SELRAsmHE: |
| 6177 | case SystemZ::SELRAsmL: |
| 6178 | case SystemZ::SELRAsmLE: |
| 6179 | case SystemZ::SELRAsmLH: |
| 6180 | case SystemZ::SELRAsmM: |
| 6181 | case SystemZ::SELRAsmNE: |
| 6182 | case SystemZ::SELRAsmNH: |
| 6183 | case SystemZ::SELRAsmNHE: |
| 6184 | case SystemZ::SELRAsmNL: |
| 6185 | case SystemZ::SELRAsmNLE: |
| 6186 | case SystemZ::SELRAsmNLH: |
| 6187 | case SystemZ::SELRAsmNM: |
| 6188 | case SystemZ::SELRAsmNO: |
| 6189 | case SystemZ::SELRAsmNP: |
| 6190 | case SystemZ::SELRAsmNZ: |
| 6191 | case SystemZ::SELRAsmO: |
| 6192 | case SystemZ::SELRAsmP: |
| 6193 | case SystemZ::SELRAsmZ: { |
| 6194 | // op: R1 |
| 6195 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6196 | Value |= (op & 0xf) << 4; |
| 6197 | // op: R2 |
| 6198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6199 | Value |= (op & 0xf); |
| 6200 | // op: R3 |
| 6201 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6202 | Value |= (op & 0xf) << 12; |
| 6203 | break; |
| 6204 | } |
| 6205 | case SystemZ::SELFHRAsm: |
| 6206 | case SystemZ::SELGRAsm: |
| 6207 | case SystemZ::SELRAsm: { |
| 6208 | // op: R1 |
| 6209 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6210 | Value |= (op & 0xf) << 4; |
| 6211 | // op: R2 |
| 6212 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6213 | Value |= (op & 0xf); |
| 6214 | // op: R3 |
| 6215 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6216 | Value |= (op & 0xf) << 12; |
| 6217 | // op: M4 |
| 6218 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6219 | Value |= (op & 0xf) << 8; |
| 6220 | break; |
| 6221 | } |
| 6222 | case SystemZ::SELFHR: |
| 6223 | case SystemZ::SELGR: |
| 6224 | case SystemZ::SELR: { |
| 6225 | // op: R1 |
| 6226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6227 | Value |= (op & 0xf) << 4; |
| 6228 | // op: R2 |
| 6229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6230 | Value |= (op & 0xf); |
| 6231 | // op: R3 |
| 6232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6233 | Value |= (op & 0xf) << 12; |
| 6234 | // op: M4 |
| 6235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6236 | Value |= (op & 0xf) << 8; |
| 6237 | break; |
| 6238 | } |
| 6239 | case SystemZ::DIDBR: |
| 6240 | case SystemZ::DIEBR: |
| 6241 | case SystemZ::LPTEA: |
| 6242 | case SystemZ::QADTR: |
| 6243 | case SystemZ::QAXTR: |
| 6244 | case SystemZ::RRDTR: |
| 6245 | case SystemZ::RRXTR: { |
| 6246 | // op: R1 |
| 6247 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6248 | Value |= (op & 0xf) << 4; |
| 6249 | // op: R2 |
| 6250 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6251 | Value |= (op & 0xf); |
| 6252 | // op: R3 |
| 6253 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6254 | Value |= (op & 0xf) << 12; |
| 6255 | // op: M4 |
| 6256 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 6257 | Value |= (op & 0xf) << 8; |
| 6258 | break; |
| 6259 | } |
| 6260 | case SystemZ::KDSA: |
| 6261 | case SystemZ::KIMD: |
| 6262 | case SystemZ::KLMD: |
| 6263 | case SystemZ::KMAC: |
| 6264 | case SystemZ::PFMF: |
| 6265 | case SystemZ::TRTEOpt: |
| 6266 | case SystemZ::TRTREOpt: { |
| 6267 | // op: R1 |
| 6268 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6269 | Value |= (op & 0xf) << 4; |
| 6270 | // op: R2 |
| 6271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6272 | Value |= (op & 0xf); |
| 6273 | break; |
| 6274 | } |
| 6275 | case SystemZ::TRTE: |
| 6276 | case SystemZ::TRTRE: { |
| 6277 | // op: R1 |
| 6278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6279 | Value |= (op & 0xf) << 4; |
| 6280 | // op: R2 |
| 6281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6282 | Value |= (op & 0xf); |
| 6283 | // op: M3 |
| 6284 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6285 | Value |= (op & 0xf) << 12; |
| 6286 | break; |
| 6287 | } |
| 6288 | case SystemZ::BCR: { |
| 6289 | // op: R1 |
| 6290 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6291 | Value |= (op & 0xf) << 4; |
| 6292 | // op: R2 |
| 6293 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6294 | Value |= (op & 0xf); |
| 6295 | break; |
| 6296 | } |
| 6297 | case SystemZ::MVCK: |
| 6298 | case SystemZ::MVCP: |
| 6299 | case SystemZ::MVCS: { |
| 6300 | // op: R1 |
| 6301 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6302 | Value |= (op & 0xf) << 36; |
| 6303 | // op: B1 |
| 6304 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6305 | Value |= (op & 0xf) << 28; |
| 6306 | // op: D1 |
| 6307 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 6308 | Value |= (op & 0xfff) << 16; |
| 6309 | // op: B2 |
| 6310 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6311 | Value |= (op & 0xf) << 12; |
| 6312 | // op: D2 |
| 6313 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 6314 | Value |= (op & 0xfff); |
| 6315 | // op: R3 |
| 6316 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 6317 | Value |= (op & 0xf) << 32; |
| 6318 | break; |
| 6319 | } |
| 6320 | case SystemZ::BR: |
| 6321 | case SystemZ::BRAsmE: |
| 6322 | case SystemZ::BRAsmH: |
| 6323 | case SystemZ::BRAsmHE: |
| 6324 | case SystemZ::BRAsmL: |
| 6325 | case SystemZ::BRAsmLE: |
| 6326 | case SystemZ::BRAsmLH: |
| 6327 | case SystemZ::BRAsmM: |
| 6328 | case SystemZ::BRAsmNE: |
| 6329 | case SystemZ::BRAsmNH: |
| 6330 | case SystemZ::BRAsmNHE: |
| 6331 | case SystemZ::BRAsmNL: |
| 6332 | case SystemZ::BRAsmNLE: |
| 6333 | case SystemZ::BRAsmNLH: |
| 6334 | case SystemZ::BRAsmNM: |
| 6335 | case SystemZ::BRAsmNO: |
| 6336 | case SystemZ::BRAsmNP: |
| 6337 | case SystemZ::BRAsmNZ: |
| 6338 | case SystemZ::BRAsmO: |
| 6339 | case SystemZ::BRAsmP: |
| 6340 | case SystemZ::BRAsmZ: |
| 6341 | case SystemZ::NOPR: { |
| 6342 | // op: R2 |
| 6343 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6344 | Value |= (op & 0xf); |
| 6345 | break; |
| 6346 | } |
| 6347 | case SystemZ::J: |
| 6348 | case SystemZ::JAsmE: |
| 6349 | case SystemZ::JAsmH: |
| 6350 | case SystemZ::JAsmHE: |
| 6351 | case SystemZ::JAsmL: |
| 6352 | case SystemZ::JAsmLE: |
| 6353 | case SystemZ::JAsmLH: |
| 6354 | case SystemZ::JAsmM: |
| 6355 | case SystemZ::JAsmNE: |
| 6356 | case SystemZ::JAsmNH: |
| 6357 | case SystemZ::JAsmNHE: |
| 6358 | case SystemZ::JAsmNL: |
| 6359 | case SystemZ::JAsmNLE: |
| 6360 | case SystemZ::JAsmNLH: |
| 6361 | case SystemZ::JAsmNM: |
| 6362 | case SystemZ::JAsmNO: |
| 6363 | case SystemZ::JAsmNP: |
| 6364 | case SystemZ::JAsmNZ: |
| 6365 | case SystemZ::JAsmO: |
| 6366 | case SystemZ::JAsmP: |
| 6367 | case SystemZ::JAsmZ: |
| 6368 | case SystemZ::JNOP: { |
| 6369 | // op: RI2 |
| 6370 | op = getPC16DBLEncoding(MI, OpNum: 0, Fixups, STI); |
| 6371 | Value |= (op & 0xffff); |
| 6372 | break; |
| 6373 | } |
| 6374 | case SystemZ::JG: |
| 6375 | case SystemZ::JGAsmE: |
| 6376 | case SystemZ::JGAsmH: |
| 6377 | case SystemZ::JGAsmHE: |
| 6378 | case SystemZ::JGAsmL: |
| 6379 | case SystemZ::JGAsmLE: |
| 6380 | case SystemZ::JGAsmLH: |
| 6381 | case SystemZ::JGAsmM: |
| 6382 | case SystemZ::JGAsmNE: |
| 6383 | case SystemZ::JGAsmNH: |
| 6384 | case SystemZ::JGAsmNHE: |
| 6385 | case SystemZ::JGAsmNL: |
| 6386 | case SystemZ::JGAsmNLE: |
| 6387 | case SystemZ::JGAsmNLH: |
| 6388 | case SystemZ::JGAsmNM: |
| 6389 | case SystemZ::JGAsmNO: |
| 6390 | case SystemZ::JGAsmNP: |
| 6391 | case SystemZ::JGAsmNZ: |
| 6392 | case SystemZ::JGAsmO: |
| 6393 | case SystemZ::JGAsmP: |
| 6394 | case SystemZ::JGAsmZ: |
| 6395 | case SystemZ::JGNOP: { |
| 6396 | // op: RI2 |
| 6397 | op = getPC32DBLEncoding(MI, OpNum: 0, Fixups, STI); |
| 6398 | Value |= (op & 0xffffffff); |
| 6399 | break; |
| 6400 | } |
| 6401 | case SystemZ::VLRL: |
| 6402 | case SystemZ::VPKZ: |
| 6403 | case SystemZ::VSTRL: |
| 6404 | case SystemZ::VUPKZ: { |
| 6405 | // op: V1 |
| 6406 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6407 | Value |= (op & 0xf) << 12; |
| 6408 | Value |= (op & 0x10) << 4; |
| 6409 | // op: B2 |
| 6410 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6411 | Value |= (op & 0xf) << 28; |
| 6412 | // op: D2 |
| 6413 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 6414 | Value |= (op & 0xfff) << 16; |
| 6415 | // op: I3 |
| 6416 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 6417 | Value |= (op & 0xff) << 32; |
| 6418 | break; |
| 6419 | } |
| 6420 | case SystemZ::VLRLR: |
| 6421 | case SystemZ::VSTRLR: { |
| 6422 | // op: V1 |
| 6423 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6424 | Value |= (op & 0xf) << 12; |
| 6425 | Value |= (op & 0x10) << 4; |
| 6426 | // op: B2 |
| 6427 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6428 | Value |= (op & 0xf) << 28; |
| 6429 | // op: D2 |
| 6430 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 6431 | Value |= (op & 0xfff) << 16; |
| 6432 | // op: R3 |
| 6433 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6434 | Value |= (op & 0xf) << 32; |
| 6435 | break; |
| 6436 | } |
| 6437 | case SystemZ::VTP: { |
| 6438 | // op: V1 |
| 6439 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6440 | Value |= (op & 0xf) << 32; |
| 6441 | Value |= (op & 0x10) << 6; |
| 6442 | break; |
| 6443 | } |
| 6444 | case SystemZ::VTPOpt: { |
| 6445 | // op: V1 |
| 6446 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6447 | Value |= (op & 0xf) << 32; |
| 6448 | Value |= (op & 0x10) << 6; |
| 6449 | // op: I2 |
| 6450 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 1, Fixups, STI); |
| 6451 | Value |= (op & 0xffff) << 12; |
| 6452 | break; |
| 6453 | } |
| 6454 | case SystemZ::VTZ: { |
| 6455 | // op: V1 |
| 6456 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6457 | Value |= (op & 0xf) << 32; |
| 6458 | Value |= (op & 0x10) << 6; |
| 6459 | // op: V2 |
| 6460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6461 | Value |= (op & 0xf) << 28; |
| 6462 | Value |= (op & 0x10) << 5; |
| 6463 | // op: I3 |
| 6464 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 2, Fixups, STI); |
| 6465 | Value |= (op & 0xffff) << 12; |
| 6466 | break; |
| 6467 | } |
| 6468 | case SystemZ::VCP: { |
| 6469 | // op: V1 |
| 6470 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6471 | Value |= (op & 0xf) << 32; |
| 6472 | Value |= (op & 0x10) << 6; |
| 6473 | // op: V2 |
| 6474 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6475 | Value |= (op & 0xf) << 28; |
| 6476 | Value |= (op & 0x10) << 5; |
| 6477 | // op: M3 |
| 6478 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 6479 | Value |= (op & 0xf) << 20; |
| 6480 | break; |
| 6481 | } |
| 6482 | case SystemZ::VONE: |
| 6483 | case SystemZ::VZERO: { |
| 6484 | // op: V1 |
| 6485 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6486 | Value |= (op & 0xf) << 36; |
| 6487 | Value |= (op & 0x10) << 7; |
| 6488 | break; |
| 6489 | } |
| 6490 | case SystemZ::VLL: |
| 6491 | case SystemZ::VSTL: { |
| 6492 | // op: V1 |
| 6493 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6494 | Value |= (op & 0xf) << 36; |
| 6495 | Value |= (op & 0x10) << 7; |
| 6496 | // op: B2 |
| 6497 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6498 | Value |= (op & 0xf) << 28; |
| 6499 | // op: D2 |
| 6500 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 6501 | Value |= (op & 0xfff) << 16; |
| 6502 | // op: R3 |
| 6503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6504 | Value |= (op & 0xf) << 32; |
| 6505 | break; |
| 6506 | } |
| 6507 | case SystemZ::VERLLB: |
| 6508 | case SystemZ::VERLLF: |
| 6509 | case SystemZ::VERLLG: |
| 6510 | case SystemZ::VERLLH: |
| 6511 | case SystemZ::VESLB: |
| 6512 | case SystemZ::VESLF: |
| 6513 | case SystemZ::VESLG: |
| 6514 | case SystemZ::VESLH: |
| 6515 | case SystemZ::VESRAB: |
| 6516 | case SystemZ::VESRAF: |
| 6517 | case SystemZ::VESRAG: |
| 6518 | case SystemZ::VESRAH: |
| 6519 | case SystemZ::VESRLB: |
| 6520 | case SystemZ::VESRLF: |
| 6521 | case SystemZ::VESRLG: |
| 6522 | case SystemZ::VESRLH: |
| 6523 | case SystemZ::VLM: |
| 6524 | case SystemZ::VSTM: { |
| 6525 | // op: V1 |
| 6526 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6527 | Value |= (op & 0xf) << 36; |
| 6528 | Value |= (op & 0x10) << 7; |
| 6529 | // op: B2 |
| 6530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6531 | Value |= (op & 0xf) << 28; |
| 6532 | // op: D2 |
| 6533 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 6534 | Value |= (op & 0xfff) << 16; |
| 6535 | // op: V3 |
| 6536 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6537 | Value |= (op & 0xf) << 32; |
| 6538 | Value |= (op & 0x10) << 6; |
| 6539 | break; |
| 6540 | } |
| 6541 | case SystemZ::VERLL: |
| 6542 | case SystemZ::VESL: |
| 6543 | case SystemZ::VESRA: |
| 6544 | case SystemZ::VESRL: |
| 6545 | case SystemZ::VLMAlign: |
| 6546 | case SystemZ::VSTMAlign: { |
| 6547 | // op: V1 |
| 6548 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6549 | Value |= (op & 0xf) << 36; |
| 6550 | Value |= (op & 0x10) << 7; |
| 6551 | // op: B2 |
| 6552 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6553 | Value |= (op & 0xf) << 28; |
| 6554 | // op: D2 |
| 6555 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 6556 | Value |= (op & 0xfff) << 16; |
| 6557 | // op: V3 |
| 6558 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6559 | Value |= (op & 0xf) << 32; |
| 6560 | Value |= (op & 0x10) << 6; |
| 6561 | // op: M4 |
| 6562 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 6563 | Value |= (op & 0xf) << 12; |
| 6564 | break; |
| 6565 | } |
| 6566 | case SystemZ::VLVGB: |
| 6567 | case SystemZ::VLVGF: |
| 6568 | case SystemZ::VLVGG: |
| 6569 | case SystemZ::VLVGH: { |
| 6570 | // op: V1 |
| 6571 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6572 | Value |= (op & 0xf) << 36; |
| 6573 | Value |= (op & 0x10) << 7; |
| 6574 | // op: B2 |
| 6575 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6576 | Value |= (op & 0xf) << 28; |
| 6577 | // op: D2 |
| 6578 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 6579 | Value |= (op & 0xfff) << 16; |
| 6580 | // op: R3 |
| 6581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6582 | Value |= (op & 0xf) << 32; |
| 6583 | break; |
| 6584 | } |
| 6585 | case SystemZ::VLVG: { |
| 6586 | // op: V1 |
| 6587 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6588 | Value |= (op & 0xf) << 36; |
| 6589 | Value |= (op & 0x10) << 7; |
| 6590 | // op: B2 |
| 6591 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6592 | Value |= (op & 0xf) << 28; |
| 6593 | // op: D2 |
| 6594 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 6595 | Value |= (op & 0xfff) << 16; |
| 6596 | // op: R3 |
| 6597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6598 | Value |= (op & 0xf) << 32; |
| 6599 | // op: M4 |
| 6600 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 6601 | Value |= (op & 0xf) << 12; |
| 6602 | break; |
| 6603 | } |
| 6604 | case SystemZ::VREPIB: |
| 6605 | case SystemZ::VREPIF: |
| 6606 | case SystemZ::VREPIG: |
| 6607 | case SystemZ::VREPIH: { |
| 6608 | // op: V1 |
| 6609 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6610 | Value |= (op & 0xf) << 36; |
| 6611 | Value |= (op & 0x10) << 7; |
| 6612 | // op: I2 |
| 6613 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 1, Fixups, STI); |
| 6614 | Value |= (op & 0xffff) << 16; |
| 6615 | break; |
| 6616 | } |
| 6617 | case SystemZ::VREPI: { |
| 6618 | // op: V1 |
| 6619 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6620 | Value |= (op & 0xf) << 36; |
| 6621 | Value |= (op & 0x10) << 7; |
| 6622 | // op: I2 |
| 6623 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 1, Fixups, STI); |
| 6624 | Value |= (op & 0xffff) << 16; |
| 6625 | // op: M3 |
| 6626 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 6627 | Value |= (op & 0xf) << 12; |
| 6628 | break; |
| 6629 | } |
| 6630 | case SystemZ::VLEIG: { |
| 6631 | // op: V1 |
| 6632 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6633 | Value |= (op & 0xf) << 36; |
| 6634 | Value |= (op & 0x10) << 7; |
| 6635 | // op: I2 |
| 6636 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 6637 | Value |= (op & 0xffff) << 16; |
| 6638 | // op: M3 |
| 6639 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, OpNum: 3, Fixups, STI); |
| 6640 | Value |= (op & 0xf) << 12; |
| 6641 | break; |
| 6642 | } |
| 6643 | case SystemZ::VLEIF: { |
| 6644 | // op: V1 |
| 6645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6646 | Value |= (op & 0xf) << 36; |
| 6647 | Value |= (op & 0x10) << 7; |
| 6648 | // op: I2 |
| 6649 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 6650 | Value |= (op & 0xffff) << 16; |
| 6651 | // op: M3 |
| 6652 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, OpNum: 3, Fixups, STI); |
| 6653 | Value |= (op & 0xf) << 12; |
| 6654 | break; |
| 6655 | } |
| 6656 | case SystemZ::VLEIH: { |
| 6657 | // op: V1 |
| 6658 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6659 | Value |= (op & 0xf) << 36; |
| 6660 | Value |= (op & 0x10) << 7; |
| 6661 | // op: I2 |
| 6662 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 6663 | Value |= (op & 0xffff) << 16; |
| 6664 | // op: M3 |
| 6665 | op = getImmOpValue<SystemZ::FK_390_U3Imm>(MI, OpNum: 3, Fixups, STI); |
| 6666 | Value |= (op & 0xf) << 12; |
| 6667 | break; |
| 6668 | } |
| 6669 | case SystemZ::VLEIB: { |
| 6670 | // op: V1 |
| 6671 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6672 | Value |= (op & 0xf) << 36; |
| 6673 | Value |= (op & 0x10) << 7; |
| 6674 | // op: I2 |
| 6675 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 6676 | Value |= (op & 0xffff) << 16; |
| 6677 | // op: M3 |
| 6678 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6679 | Value |= (op & 0xf) << 12; |
| 6680 | break; |
| 6681 | } |
| 6682 | case SystemZ::VGBM: { |
| 6683 | // op: V1 |
| 6684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6685 | Value |= (op & 0xf) << 36; |
| 6686 | Value |= (op & 0x10) << 7; |
| 6687 | // op: I2 |
| 6688 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 1, Fixups, STI); |
| 6689 | Value |= (op & 0xffff) << 16; |
| 6690 | break; |
| 6691 | } |
| 6692 | case SystemZ::VLIP: { |
| 6693 | // op: V1 |
| 6694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6695 | Value |= (op & 0xf) << 36; |
| 6696 | Value |= (op & 0x10) << 7; |
| 6697 | // op: I2 |
| 6698 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 1, Fixups, STI); |
| 6699 | Value |= (op & 0xffff) << 16; |
| 6700 | // op: I3 |
| 6701 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 6702 | Value |= (op & 0xf) << 12; |
| 6703 | break; |
| 6704 | } |
| 6705 | case SystemZ::VGMB: |
| 6706 | case SystemZ::VGMF: |
| 6707 | case SystemZ::VGMG: |
| 6708 | case SystemZ::VGMH: { |
| 6709 | // op: V1 |
| 6710 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6711 | Value |= (op & 0xf) << 36; |
| 6712 | Value |= (op & 0x10) << 7; |
| 6713 | // op: I2 |
| 6714 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 1, Fixups, STI); |
| 6715 | Value |= (op & 0xff) << 24; |
| 6716 | // op: I3 |
| 6717 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 2, Fixups, STI); |
| 6718 | Value |= (op & 0xff) << 16; |
| 6719 | break; |
| 6720 | } |
| 6721 | case SystemZ::VGM: { |
| 6722 | // op: V1 |
| 6723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6724 | Value |= (op & 0xf) << 36; |
| 6725 | Value |= (op & 0x10) << 7; |
| 6726 | // op: I2 |
| 6727 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 1, Fixups, STI); |
| 6728 | Value |= (op & 0xff) << 24; |
| 6729 | // op: I3 |
| 6730 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 2, Fixups, STI); |
| 6731 | Value |= (op & 0xff) << 16; |
| 6732 | // op: M4 |
| 6733 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6734 | Value |= (op & 0xf) << 12; |
| 6735 | break; |
| 6736 | } |
| 6737 | case SystemZ::VCVD: |
| 6738 | case SystemZ::VCVDG: { |
| 6739 | // op: V1 |
| 6740 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6741 | Value |= (op & 0xf) << 36; |
| 6742 | Value |= (op & 0x10) << 7; |
| 6743 | // op: R2 |
| 6744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6745 | Value |= (op & 0xf) << 32; |
| 6746 | // op: I3 |
| 6747 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 2, Fixups, STI); |
| 6748 | Value |= (op & 0xff) << 12; |
| 6749 | // op: M4 |
| 6750 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6751 | Value |= (op & 0xf) << 20; |
| 6752 | break; |
| 6753 | } |
| 6754 | case SystemZ::VLVGP: { |
| 6755 | // op: V1 |
| 6756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6757 | Value |= (op & 0xf) << 36; |
| 6758 | Value |= (op & 0x10) << 7; |
| 6759 | // op: R2 |
| 6760 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6761 | Value |= (op & 0xf) << 32; |
| 6762 | // op: R3 |
| 6763 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6764 | Value |= (op & 0xf) << 28; |
| 6765 | break; |
| 6766 | } |
| 6767 | case SystemZ::VCLZB: |
| 6768 | case SystemZ::VCLZF: |
| 6769 | case SystemZ::VCLZG: |
| 6770 | case SystemZ::VCLZH: |
| 6771 | case SystemZ::VCLZQ: |
| 6772 | case SystemZ::VCTZB: |
| 6773 | case SystemZ::VCTZF: |
| 6774 | case SystemZ::VCTZG: |
| 6775 | case SystemZ::VCTZH: |
| 6776 | case SystemZ::VCTZQ: |
| 6777 | case SystemZ::VECB: |
| 6778 | case SystemZ::VECF: |
| 6779 | case SystemZ::VECG: |
| 6780 | case SystemZ::VECH: |
| 6781 | case SystemZ::VECLB: |
| 6782 | case SystemZ::VECLF: |
| 6783 | case SystemZ::VECLG: |
| 6784 | case SystemZ::VECLH: |
| 6785 | case SystemZ::VECLQ: |
| 6786 | case SystemZ::VECQ: |
| 6787 | case SystemZ::VFLCDB: |
| 6788 | case SystemZ::VFLCSB: |
| 6789 | case SystemZ::VFLLS: |
| 6790 | case SystemZ::VFLNDB: |
| 6791 | case SystemZ::VFLNSB: |
| 6792 | case SystemZ::VFLPDB: |
| 6793 | case SystemZ::VFLPSB: |
| 6794 | case SystemZ::VFSQDB: |
| 6795 | case SystemZ::VFSQSB: |
| 6796 | case SystemZ::VGEMB: |
| 6797 | case SystemZ::VGEMF: |
| 6798 | case SystemZ::VGEMG: |
| 6799 | case SystemZ::VGEMH: |
| 6800 | case SystemZ::VGEMQ: |
| 6801 | case SystemZ::VISTRBS: |
| 6802 | case SystemZ::VISTRFS: |
| 6803 | case SystemZ::VISTRHS: |
| 6804 | case SystemZ::VLCB: |
| 6805 | case SystemZ::VLCF: |
| 6806 | case SystemZ::VLCG: |
| 6807 | case SystemZ::VLCH: |
| 6808 | case SystemZ::VLCQ: |
| 6809 | case SystemZ::VLDEB: |
| 6810 | case SystemZ::VLPB: |
| 6811 | case SystemZ::VLPF: |
| 6812 | case SystemZ::VLPG: |
| 6813 | case SystemZ::VLPH: |
| 6814 | case SystemZ::VLPQ: |
| 6815 | case SystemZ::VLR: |
| 6816 | case SystemZ::VPOPCTB: |
| 6817 | case SystemZ::VPOPCTF: |
| 6818 | case SystemZ::VPOPCTG: |
| 6819 | case SystemZ::VPOPCTH: |
| 6820 | case SystemZ::VSEGB: |
| 6821 | case SystemZ::VSEGF: |
| 6822 | case SystemZ::VSEGH: |
| 6823 | case SystemZ::VTM: |
| 6824 | case SystemZ::VUPHB: |
| 6825 | case SystemZ::VUPHF: |
| 6826 | case SystemZ::VUPHG: |
| 6827 | case SystemZ::VUPHH: |
| 6828 | case SystemZ::VUPLB: |
| 6829 | case SystemZ::VUPLF: |
| 6830 | case SystemZ::VUPLG: |
| 6831 | case SystemZ::VUPLHB: |
| 6832 | case SystemZ::VUPLHF: |
| 6833 | case SystemZ::VUPLHG: |
| 6834 | case SystemZ::VUPLHH: |
| 6835 | case SystemZ::VUPLHW: |
| 6836 | case SystemZ::VUPLLB: |
| 6837 | case SystemZ::VUPLLF: |
| 6838 | case SystemZ::VUPLLG: |
| 6839 | case SystemZ::VUPLLH: |
| 6840 | case SystemZ::WFCDB: |
| 6841 | case SystemZ::WFCSB: |
| 6842 | case SystemZ::WFCXB: |
| 6843 | case SystemZ::WFKDB: |
| 6844 | case SystemZ::WFKSB: |
| 6845 | case SystemZ::WFKXB: |
| 6846 | case SystemZ::WFLCDB: |
| 6847 | case SystemZ::WFLCSB: |
| 6848 | case SystemZ::WFLCXB: |
| 6849 | case SystemZ::WFLLD: |
| 6850 | case SystemZ::WFLLS: |
| 6851 | case SystemZ::WFLNDB: |
| 6852 | case SystemZ::WFLNSB: |
| 6853 | case SystemZ::WFLNXB: |
| 6854 | case SystemZ::WFLPDB: |
| 6855 | case SystemZ::WFLPSB: |
| 6856 | case SystemZ::WFLPXB: |
| 6857 | case SystemZ::WFSQDB: |
| 6858 | case SystemZ::WFSQSB: |
| 6859 | case SystemZ::WFSQXB: |
| 6860 | case SystemZ::WLDEB: { |
| 6861 | // op: V1 |
| 6862 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6863 | Value |= (op & 0xf) << 36; |
| 6864 | Value |= (op & 0x10) << 7; |
| 6865 | // op: V2 |
| 6866 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6867 | Value |= (op & 0xf) << 32; |
| 6868 | Value |= (op & 0x10) << 6; |
| 6869 | break; |
| 6870 | } |
| 6871 | case SystemZ::VFTCIDB: |
| 6872 | case SystemZ::VFTCISB: |
| 6873 | case SystemZ::WFTCIDB: |
| 6874 | case SystemZ::WFTCISB: |
| 6875 | case SystemZ::WFTCIXB: { |
| 6876 | // op: V1 |
| 6877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6878 | Value |= (op & 0xf) << 36; |
| 6879 | Value |= (op & 0x10) << 7; |
| 6880 | // op: V2 |
| 6881 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6882 | Value |= (op & 0xf) << 32; |
| 6883 | Value |= (op & 0x10) << 6; |
| 6884 | // op: I3 |
| 6885 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 6886 | Value |= (op & 0xfff) << 20; |
| 6887 | break; |
| 6888 | } |
| 6889 | case SystemZ::VFTCI: { |
| 6890 | // op: V1 |
| 6891 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6892 | Value |= (op & 0xf) << 36; |
| 6893 | Value |= (op & 0x10) << 7; |
| 6894 | // op: V2 |
| 6895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6896 | Value |= (op & 0xf) << 32; |
| 6897 | Value |= (op & 0x10) << 6; |
| 6898 | // op: I3 |
| 6899 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 6900 | Value |= (op & 0xfff) << 20; |
| 6901 | // op: M4 |
| 6902 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6903 | Value |= (op & 0xf) << 12; |
| 6904 | // op: M5 |
| 6905 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 6906 | Value |= (op & 0xf) << 16; |
| 6907 | break; |
| 6908 | } |
| 6909 | case SystemZ::VPSOP: |
| 6910 | case SystemZ::VSRP: { |
| 6911 | // op: V1 |
| 6912 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6913 | Value |= (op & 0xf) << 36; |
| 6914 | Value |= (op & 0x10) << 7; |
| 6915 | // op: V2 |
| 6916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6917 | Value |= (op & 0xf) << 32; |
| 6918 | Value |= (op & 0x10) << 6; |
| 6919 | // op: I3 |
| 6920 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 2, Fixups, STI); |
| 6921 | Value |= (op & 0xff) << 12; |
| 6922 | // op: I4 |
| 6923 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 6924 | Value |= (op & 0xff) << 24; |
| 6925 | // op: M5 |
| 6926 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 6927 | Value |= (op & 0xf) << 20; |
| 6928 | break; |
| 6929 | } |
| 6930 | case SystemZ::VCVDQ: { |
| 6931 | // op: V1 |
| 6932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6933 | Value |= (op & 0xf) << 36; |
| 6934 | Value |= (op & 0x10) << 7; |
| 6935 | // op: V2 |
| 6936 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6937 | Value |= (op & 0xf) << 32; |
| 6938 | Value |= (op & 0x10) << 6; |
| 6939 | // op: I3 |
| 6940 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 2, Fixups, STI); |
| 6941 | Value |= (op & 0xff) << 12; |
| 6942 | // op: M4 |
| 6943 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6944 | Value |= (op & 0xf) << 20; |
| 6945 | break; |
| 6946 | } |
| 6947 | case SystemZ::VCLZ: |
| 6948 | case SystemZ::VCTZ: |
| 6949 | case SystemZ::VEC: |
| 6950 | case SystemZ::VECL: |
| 6951 | case SystemZ::VGEM: |
| 6952 | case SystemZ::VLC: |
| 6953 | case SystemZ::VLP: |
| 6954 | case SystemZ::VPOPCT: |
| 6955 | case SystemZ::VSEG: |
| 6956 | case SystemZ::VUPH: |
| 6957 | case SystemZ::VUPL: |
| 6958 | case SystemZ::VUPLH: |
| 6959 | case SystemZ::VUPLL: { |
| 6960 | // op: V1 |
| 6961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6962 | Value |= (op & 0xf) << 36; |
| 6963 | Value |= (op & 0x10) << 7; |
| 6964 | // op: V2 |
| 6965 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6966 | Value |= (op & 0xf) << 32; |
| 6967 | Value |= (op & 0x10) << 6; |
| 6968 | // op: M3 |
| 6969 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 6970 | Value |= (op & 0xf) << 12; |
| 6971 | break; |
| 6972 | } |
| 6973 | case SystemZ::VCFN: |
| 6974 | case SystemZ::VCLFNH: |
| 6975 | case SystemZ::VCLFNL: |
| 6976 | case SystemZ::VCNF: |
| 6977 | case SystemZ::VFLL: |
| 6978 | case SystemZ::VFSQ: |
| 6979 | case SystemZ::VLDE: |
| 6980 | case SystemZ::WFC: |
| 6981 | case SystemZ::WFK: { |
| 6982 | // op: V1 |
| 6983 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6984 | Value |= (op & 0xf) << 36; |
| 6985 | Value |= (op & 0x10) << 7; |
| 6986 | // op: V2 |
| 6987 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6988 | Value |= (op & 0xf) << 32; |
| 6989 | Value |= (op & 0x10) << 6; |
| 6990 | // op: M3 |
| 6991 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 6992 | Value |= (op & 0xf) << 12; |
| 6993 | // op: M4 |
| 6994 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 6995 | Value |= (op & 0xf) << 16; |
| 6996 | break; |
| 6997 | } |
| 6998 | case SystemZ::VCDG: |
| 6999 | case SystemZ::VCDLG: |
| 7000 | case SystemZ::VCFPL: |
| 7001 | case SystemZ::VCFPS: |
| 7002 | case SystemZ::VCGD: |
| 7003 | case SystemZ::VCLFP: |
| 7004 | case SystemZ::VCLGD: |
| 7005 | case SystemZ::VCSFP: |
| 7006 | case SystemZ::VFI: |
| 7007 | case SystemZ::VFLR: |
| 7008 | case SystemZ::VFPSO: |
| 7009 | case SystemZ::VLED: { |
| 7010 | // op: V1 |
| 7011 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7012 | Value |= (op & 0xf) << 36; |
| 7013 | Value |= (op & 0x10) << 7; |
| 7014 | // op: V2 |
| 7015 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7016 | Value |= (op & 0xf) << 32; |
| 7017 | Value |= (op & 0x10) << 6; |
| 7018 | // op: M3 |
| 7019 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 7020 | Value |= (op & 0xf) << 12; |
| 7021 | // op: M4 |
| 7022 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7023 | Value |= (op & 0xf) << 16; |
| 7024 | // op: M5 |
| 7025 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 7026 | Value |= (op & 0xf) << 20; |
| 7027 | break; |
| 7028 | } |
| 7029 | case SystemZ::VISTR: { |
| 7030 | // op: V1 |
| 7031 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7032 | Value |= (op & 0xf) << 36; |
| 7033 | Value |= (op & 0x10) << 7; |
| 7034 | // op: V2 |
| 7035 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7036 | Value |= (op & 0xf) << 32; |
| 7037 | Value |= (op & 0x10) << 6; |
| 7038 | // op: M3 |
| 7039 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 7040 | Value |= (op & 0xf) << 12; |
| 7041 | // op: M5 |
| 7042 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7043 | Value |= (op & 0xf) << 20; |
| 7044 | break; |
| 7045 | } |
| 7046 | case SystemZ::VCLZDP: |
| 7047 | case SystemZ::VCVBQ: |
| 7048 | case SystemZ::VUPKZH: |
| 7049 | case SystemZ::VUPKZL: { |
| 7050 | // op: V1 |
| 7051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7052 | Value |= (op & 0xf) << 36; |
| 7053 | Value |= (op & 0x10) << 7; |
| 7054 | // op: V2 |
| 7055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7056 | Value |= (op & 0xf) << 32; |
| 7057 | Value |= (op & 0x10) << 6; |
| 7058 | // op: M3 |
| 7059 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 7060 | Value |= (op & 0xf) << 20; |
| 7061 | break; |
| 7062 | } |
| 7063 | case SystemZ::WCDGB: |
| 7064 | case SystemZ::WCDLGB: |
| 7065 | case SystemZ::WCEFB: |
| 7066 | case SystemZ::WCELFB: |
| 7067 | case SystemZ::WCFEB: |
| 7068 | case SystemZ::WCGDB: |
| 7069 | case SystemZ::WCLFEB: |
| 7070 | case SystemZ::WCLGDB: |
| 7071 | case SystemZ::WFIDB: |
| 7072 | case SystemZ::WFISB: |
| 7073 | case SystemZ::WFIXB: |
| 7074 | case SystemZ::WFLRD: |
| 7075 | case SystemZ::WFLRX: |
| 7076 | case SystemZ::WLEDB: { |
| 7077 | // op: V1 |
| 7078 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7079 | Value |= (op & 0xf) << 36; |
| 7080 | Value |= (op & 0x10) << 7; |
| 7081 | // op: V2 |
| 7082 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7083 | Value |= (op & 0xf) << 32; |
| 7084 | Value |= (op & 0x10) << 6; |
| 7085 | // op: M4 |
| 7086 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 7087 | Value |= (op & 0x7) << 16; |
| 7088 | // op: M5 |
| 7089 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7090 | Value |= (op & 0xf) << 20; |
| 7091 | break; |
| 7092 | } |
| 7093 | case SystemZ::VCDGB: |
| 7094 | case SystemZ::VCDLGB: |
| 7095 | case SystemZ::VCEFB: |
| 7096 | case SystemZ::VCELFB: |
| 7097 | case SystemZ::VCFEB: |
| 7098 | case SystemZ::VCGDB: |
| 7099 | case SystemZ::VCLFEB: |
| 7100 | case SystemZ::VCLGDB: |
| 7101 | case SystemZ::VFIDB: |
| 7102 | case SystemZ::VFISB: |
| 7103 | case SystemZ::VFLRD: |
| 7104 | case SystemZ::VLEDB: { |
| 7105 | // op: V1 |
| 7106 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7107 | Value |= (op & 0xf) << 36; |
| 7108 | Value |= (op & 0x10) << 7; |
| 7109 | // op: V2 |
| 7110 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7111 | Value |= (op & 0xf) << 32; |
| 7112 | Value |= (op & 0x10) << 6; |
| 7113 | // op: M4 |
| 7114 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 7115 | Value |= (op & 0xf) << 16; |
| 7116 | // op: M5 |
| 7117 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7118 | Value |= (op & 0xf) << 20; |
| 7119 | break; |
| 7120 | } |
| 7121 | case SystemZ::VFPSODB: |
| 7122 | case SystemZ::VFPSOSB: |
| 7123 | case SystemZ::VISTRB: |
| 7124 | case SystemZ::VISTRF: |
| 7125 | case SystemZ::VISTRH: |
| 7126 | case SystemZ::WFPSODB: |
| 7127 | case SystemZ::WFPSOSB: |
| 7128 | case SystemZ::WFPSOXB: { |
| 7129 | // op: V1 |
| 7130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7131 | Value |= (op & 0xf) << 36; |
| 7132 | Value |= (op & 0x10) << 7; |
| 7133 | // op: V2 |
| 7134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7135 | Value |= (op & 0xf) << 32; |
| 7136 | Value |= (op & 0x10) << 6; |
| 7137 | // op: M5 |
| 7138 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 7139 | Value |= (op & 0xf) << 20; |
| 7140 | break; |
| 7141 | } |
| 7142 | case SystemZ::VAB: |
| 7143 | case SystemZ::VACCB: |
| 7144 | case SystemZ::VACCF: |
| 7145 | case SystemZ::VACCG: |
| 7146 | case SystemZ::VACCH: |
| 7147 | case SystemZ::VACCQ: |
| 7148 | case SystemZ::VAF: |
| 7149 | case SystemZ::VAG: |
| 7150 | case SystemZ::VAH: |
| 7151 | case SystemZ::VAQ: |
| 7152 | case SystemZ::VAVGB: |
| 7153 | case SystemZ::VAVGF: |
| 7154 | case SystemZ::VAVGG: |
| 7155 | case SystemZ::VAVGH: |
| 7156 | case SystemZ::VAVGLB: |
| 7157 | case SystemZ::VAVGLF: |
| 7158 | case SystemZ::VAVGLG: |
| 7159 | case SystemZ::VAVGLH: |
| 7160 | case SystemZ::VAVGLQ: |
| 7161 | case SystemZ::VAVGQ: |
| 7162 | case SystemZ::VBPERM: |
| 7163 | case SystemZ::VCEQB: |
| 7164 | case SystemZ::VCEQBS: |
| 7165 | case SystemZ::VCEQF: |
| 7166 | case SystemZ::VCEQFS: |
| 7167 | case SystemZ::VCEQG: |
| 7168 | case SystemZ::VCEQGS: |
| 7169 | case SystemZ::VCEQH: |
| 7170 | case SystemZ::VCEQHS: |
| 7171 | case SystemZ::VCEQQ: |
| 7172 | case SystemZ::VCEQQS: |
| 7173 | case SystemZ::VCHB: |
| 7174 | case SystemZ::VCHBS: |
| 7175 | case SystemZ::VCHF: |
| 7176 | case SystemZ::VCHFS: |
| 7177 | case SystemZ::VCHG: |
| 7178 | case SystemZ::VCHGS: |
| 7179 | case SystemZ::VCHH: |
| 7180 | case SystemZ::VCHHS: |
| 7181 | case SystemZ::VCHLB: |
| 7182 | case SystemZ::VCHLBS: |
| 7183 | case SystemZ::VCHLF: |
| 7184 | case SystemZ::VCHLFS: |
| 7185 | case SystemZ::VCHLG: |
| 7186 | case SystemZ::VCHLGS: |
| 7187 | case SystemZ::VCHLH: |
| 7188 | case SystemZ::VCHLHS: |
| 7189 | case SystemZ::VCHLQ: |
| 7190 | case SystemZ::VCHLQS: |
| 7191 | case SystemZ::VCHQ: |
| 7192 | case SystemZ::VCHQS: |
| 7193 | case SystemZ::VCKSM: |
| 7194 | case SystemZ::VERLLVB: |
| 7195 | case SystemZ::VERLLVF: |
| 7196 | case SystemZ::VERLLVG: |
| 7197 | case SystemZ::VERLLVH: |
| 7198 | case SystemZ::VESLVB: |
| 7199 | case SystemZ::VESLVF: |
| 7200 | case SystemZ::VESLVG: |
| 7201 | case SystemZ::VESLVH: |
| 7202 | case SystemZ::VESRAVB: |
| 7203 | case SystemZ::VESRAVF: |
| 7204 | case SystemZ::VESRAVG: |
| 7205 | case SystemZ::VESRAVH: |
| 7206 | case SystemZ::VESRLVB: |
| 7207 | case SystemZ::VESRLVF: |
| 7208 | case SystemZ::VESRLVG: |
| 7209 | case SystemZ::VESRLVH: |
| 7210 | case SystemZ::VFADB: |
| 7211 | case SystemZ::VFASB: |
| 7212 | case SystemZ::VFCEDB: |
| 7213 | case SystemZ::VFCEDBS: |
| 7214 | case SystemZ::VFCESB: |
| 7215 | case SystemZ::VFCESBS: |
| 7216 | case SystemZ::VFCHDB: |
| 7217 | case SystemZ::VFCHDBS: |
| 7218 | case SystemZ::VFCHEDB: |
| 7219 | case SystemZ::VFCHEDBS: |
| 7220 | case SystemZ::VFCHESB: |
| 7221 | case SystemZ::VFCHESBS: |
| 7222 | case SystemZ::VFCHSB: |
| 7223 | case SystemZ::VFCHSBS: |
| 7224 | case SystemZ::VFDDB: |
| 7225 | case SystemZ::VFDSB: |
| 7226 | case SystemZ::VFEEBS: |
| 7227 | case SystemZ::VFEEFS: |
| 7228 | case SystemZ::VFEEHS: |
| 7229 | case SystemZ::VFEEZB: |
| 7230 | case SystemZ::VFEEZBS: |
| 7231 | case SystemZ::VFEEZF: |
| 7232 | case SystemZ::VFEEZFS: |
| 7233 | case SystemZ::VFEEZH: |
| 7234 | case SystemZ::VFEEZHS: |
| 7235 | case SystemZ::VFENEBS: |
| 7236 | case SystemZ::VFENEFS: |
| 7237 | case SystemZ::VFENEHS: |
| 7238 | case SystemZ::VFENEZB: |
| 7239 | case SystemZ::VFENEZBS: |
| 7240 | case SystemZ::VFENEZF: |
| 7241 | case SystemZ::VFENEZFS: |
| 7242 | case SystemZ::VFENEZH: |
| 7243 | case SystemZ::VFENEZHS: |
| 7244 | case SystemZ::VFKEDB: |
| 7245 | case SystemZ::VFKEDBS: |
| 7246 | case SystemZ::VFKESB: |
| 7247 | case SystemZ::VFKESBS: |
| 7248 | case SystemZ::VFKHDB: |
| 7249 | case SystemZ::VFKHDBS: |
| 7250 | case SystemZ::VFKHEDB: |
| 7251 | case SystemZ::VFKHEDBS: |
| 7252 | case SystemZ::VFKHESB: |
| 7253 | case SystemZ::VFKHESBS: |
| 7254 | case SystemZ::VFKHSB: |
| 7255 | case SystemZ::VFKHSBS: |
| 7256 | case SystemZ::VFMDB: |
| 7257 | case SystemZ::VFMSB: |
| 7258 | case SystemZ::VFSDB: |
| 7259 | case SystemZ::VFSSB: |
| 7260 | case SystemZ::VGFMB: |
| 7261 | case SystemZ::VGFMF: |
| 7262 | case SystemZ::VGFMG: |
| 7263 | case SystemZ::VGFMH: |
| 7264 | case SystemZ::VMEB: |
| 7265 | case SystemZ::VMEF: |
| 7266 | case SystemZ::VMEG: |
| 7267 | case SystemZ::VMEH: |
| 7268 | case SystemZ::VMHB: |
| 7269 | case SystemZ::VMHF: |
| 7270 | case SystemZ::VMHG: |
| 7271 | case SystemZ::VMHH: |
| 7272 | case SystemZ::VMHQ: |
| 7273 | case SystemZ::VMLB: |
| 7274 | case SystemZ::VMLEB: |
| 7275 | case SystemZ::VMLEF: |
| 7276 | case SystemZ::VMLEG: |
| 7277 | case SystemZ::VMLEH: |
| 7278 | case SystemZ::VMLF: |
| 7279 | case SystemZ::VMLG: |
| 7280 | case SystemZ::VMLHB: |
| 7281 | case SystemZ::VMLHF: |
| 7282 | case SystemZ::VMLHG: |
| 7283 | case SystemZ::VMLHH: |
| 7284 | case SystemZ::VMLHQ: |
| 7285 | case SystemZ::VMLHW: |
| 7286 | case SystemZ::VMLOB: |
| 7287 | case SystemZ::VMLOF: |
| 7288 | case SystemZ::VMLOG: |
| 7289 | case SystemZ::VMLOH: |
| 7290 | case SystemZ::VMLQ: |
| 7291 | case SystemZ::VMNB: |
| 7292 | case SystemZ::VMNF: |
| 7293 | case SystemZ::VMNG: |
| 7294 | case SystemZ::VMNH: |
| 7295 | case SystemZ::VMNLB: |
| 7296 | case SystemZ::VMNLF: |
| 7297 | case SystemZ::VMNLG: |
| 7298 | case SystemZ::VMNLH: |
| 7299 | case SystemZ::VMNLQ: |
| 7300 | case SystemZ::VMNQ: |
| 7301 | case SystemZ::VMOB: |
| 7302 | case SystemZ::VMOF: |
| 7303 | case SystemZ::VMOG: |
| 7304 | case SystemZ::VMOH: |
| 7305 | case SystemZ::VMRHB: |
| 7306 | case SystemZ::VMRHF: |
| 7307 | case SystemZ::VMRHG: |
| 7308 | case SystemZ::VMRHH: |
| 7309 | case SystemZ::VMRLB: |
| 7310 | case SystemZ::VMRLF: |
| 7311 | case SystemZ::VMRLG: |
| 7312 | case SystemZ::VMRLH: |
| 7313 | case SystemZ::VMXB: |
| 7314 | case SystemZ::VMXF: |
| 7315 | case SystemZ::VMXG: |
| 7316 | case SystemZ::VMXH: |
| 7317 | case SystemZ::VMXLB: |
| 7318 | case SystemZ::VMXLF: |
| 7319 | case SystemZ::VMXLG: |
| 7320 | case SystemZ::VMXLH: |
| 7321 | case SystemZ::VMXLQ: |
| 7322 | case SystemZ::VMXQ: |
| 7323 | case SystemZ::VN: |
| 7324 | case SystemZ::VNC: |
| 7325 | case SystemZ::VNN: |
| 7326 | case SystemZ::VNO: |
| 7327 | case SystemZ::VNX: |
| 7328 | case SystemZ::VO: |
| 7329 | case SystemZ::VOC: |
| 7330 | case SystemZ::VPKF: |
| 7331 | case SystemZ::VPKG: |
| 7332 | case SystemZ::VPKH: |
| 7333 | case SystemZ::VPKLSF: |
| 7334 | case SystemZ::VPKLSFS: |
| 7335 | case SystemZ::VPKLSG: |
| 7336 | case SystemZ::VPKLSGS: |
| 7337 | case SystemZ::VPKLSH: |
| 7338 | case SystemZ::VPKLSHS: |
| 7339 | case SystemZ::VPKSF: |
| 7340 | case SystemZ::VPKSFS: |
| 7341 | case SystemZ::VPKSG: |
| 7342 | case SystemZ::VPKSGS: |
| 7343 | case SystemZ::VPKSH: |
| 7344 | case SystemZ::VPKSHS: |
| 7345 | case SystemZ::VSB: |
| 7346 | case SystemZ::VSCBIB: |
| 7347 | case SystemZ::VSCBIF: |
| 7348 | case SystemZ::VSCBIG: |
| 7349 | case SystemZ::VSCBIH: |
| 7350 | case SystemZ::VSCBIQ: |
| 7351 | case SystemZ::VSCSHP: |
| 7352 | case SystemZ::VSF: |
| 7353 | case SystemZ::VSG: |
| 7354 | case SystemZ::VSH: |
| 7355 | case SystemZ::VSL: |
| 7356 | case SystemZ::VSLB: |
| 7357 | case SystemZ::VSQ: |
| 7358 | case SystemZ::VSRA: |
| 7359 | case SystemZ::VSRAB: |
| 7360 | case SystemZ::VSRL: |
| 7361 | case SystemZ::VSRLB: |
| 7362 | case SystemZ::VSUMB: |
| 7363 | case SystemZ::VSUMGF: |
| 7364 | case SystemZ::VSUMGH: |
| 7365 | case SystemZ::VSUMH: |
| 7366 | case SystemZ::VSUMQF: |
| 7367 | case SystemZ::VSUMQG: |
| 7368 | case SystemZ::VX: |
| 7369 | case SystemZ::WFADB: |
| 7370 | case SystemZ::WFASB: |
| 7371 | case SystemZ::WFAXB: |
| 7372 | case SystemZ::WFCEDB: |
| 7373 | case SystemZ::WFCEDBS: |
| 7374 | case SystemZ::WFCESB: |
| 7375 | case SystemZ::WFCESBS: |
| 7376 | case SystemZ::WFCEXB: |
| 7377 | case SystemZ::WFCEXBS: |
| 7378 | case SystemZ::WFCHDB: |
| 7379 | case SystemZ::WFCHDBS: |
| 7380 | case SystemZ::WFCHEDB: |
| 7381 | case SystemZ::WFCHEDBS: |
| 7382 | case SystemZ::WFCHESB: |
| 7383 | case SystemZ::WFCHESBS: |
| 7384 | case SystemZ::WFCHEXB: |
| 7385 | case SystemZ::WFCHEXBS: |
| 7386 | case SystemZ::WFCHSB: |
| 7387 | case SystemZ::WFCHSBS: |
| 7388 | case SystemZ::WFCHXB: |
| 7389 | case SystemZ::WFCHXBS: |
| 7390 | case SystemZ::WFDDB: |
| 7391 | case SystemZ::WFDSB: |
| 7392 | case SystemZ::WFDXB: |
| 7393 | case SystemZ::WFKEDB: |
| 7394 | case SystemZ::WFKEDBS: |
| 7395 | case SystemZ::WFKESB: |
| 7396 | case SystemZ::WFKESBS: |
| 7397 | case SystemZ::WFKEXB: |
| 7398 | case SystemZ::WFKEXBS: |
| 7399 | case SystemZ::WFKHDB: |
| 7400 | case SystemZ::WFKHDBS: |
| 7401 | case SystemZ::WFKHEDB: |
| 7402 | case SystemZ::WFKHEDBS: |
| 7403 | case SystemZ::WFKHESB: |
| 7404 | case SystemZ::WFKHESBS: |
| 7405 | case SystemZ::WFKHEXB: |
| 7406 | case SystemZ::WFKHEXBS: |
| 7407 | case SystemZ::WFKHSB: |
| 7408 | case SystemZ::WFKHSBS: |
| 7409 | case SystemZ::WFKHXB: |
| 7410 | case SystemZ::WFKHXBS: |
| 7411 | case SystemZ::WFMDB: |
| 7412 | case SystemZ::WFMSB: |
| 7413 | case SystemZ::WFMXB: |
| 7414 | case SystemZ::WFSDB: |
| 7415 | case SystemZ::WFSSB: |
| 7416 | case SystemZ::WFSXB: { |
| 7417 | // op: V1 |
| 7418 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7419 | Value |= (op & 0xf) << 36; |
| 7420 | Value |= (op & 0x10) << 7; |
| 7421 | // op: V2 |
| 7422 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7423 | Value |= (op & 0xf) << 32; |
| 7424 | Value |= (op & 0x10) << 6; |
| 7425 | // op: V3 |
| 7426 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7427 | Value |= (op & 0xf) << 28; |
| 7428 | Value |= (op & 0x10) << 5; |
| 7429 | break; |
| 7430 | } |
| 7431 | case SystemZ::VAP: |
| 7432 | case SystemZ::VDP: |
| 7433 | case SystemZ::VMP: |
| 7434 | case SystemZ::VMSP: |
| 7435 | case SystemZ::VPKZR: |
| 7436 | case SystemZ::VRP: |
| 7437 | case SystemZ::VSDP: |
| 7438 | case SystemZ::VSP: |
| 7439 | case SystemZ::VSRPR: { |
| 7440 | // op: V1 |
| 7441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7442 | Value |= (op & 0xf) << 36; |
| 7443 | Value |= (op & 0x10) << 7; |
| 7444 | // op: V2 |
| 7445 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7446 | Value |= (op & 0xf) << 32; |
| 7447 | Value |= (op & 0x10) << 6; |
| 7448 | // op: V3 |
| 7449 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7450 | Value |= (op & 0xf) << 28; |
| 7451 | Value |= (op & 0x10) << 5; |
| 7452 | // op: I4 |
| 7453 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 7454 | Value |= (op & 0xff) << 12; |
| 7455 | // op: M5 |
| 7456 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 7457 | Value |= (op & 0xf) << 20; |
| 7458 | break; |
| 7459 | } |
| 7460 | case SystemZ::VSLD: |
| 7461 | case SystemZ::VSLDB: |
| 7462 | case SystemZ::VSRD: { |
| 7463 | // op: V1 |
| 7464 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7465 | Value |= (op & 0xf) << 36; |
| 7466 | Value |= (op & 0x10) << 7; |
| 7467 | // op: V2 |
| 7468 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7469 | Value |= (op & 0xf) << 32; |
| 7470 | Value |= (op & 0x10) << 6; |
| 7471 | // op: V3 |
| 7472 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7473 | Value |= (op & 0xf) << 28; |
| 7474 | Value |= (op & 0x10) << 5; |
| 7475 | // op: I4 |
| 7476 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 7477 | Value |= (op & 0xff) << 16; |
| 7478 | break; |
| 7479 | } |
| 7480 | case SystemZ::VA: |
| 7481 | case SystemZ::VACC: |
| 7482 | case SystemZ::VAVG: |
| 7483 | case SystemZ::VAVGL: |
| 7484 | case SystemZ::VERLLV: |
| 7485 | case SystemZ::VESLV: |
| 7486 | case SystemZ::VESRAV: |
| 7487 | case SystemZ::VESRLV: |
| 7488 | case SystemZ::VGFM: |
| 7489 | case SystemZ::VME: |
| 7490 | case SystemZ::VMH: |
| 7491 | case SystemZ::VML: |
| 7492 | case SystemZ::VMLE: |
| 7493 | case SystemZ::VMLH: |
| 7494 | case SystemZ::VMLO: |
| 7495 | case SystemZ::VMN: |
| 7496 | case SystemZ::VMNL: |
| 7497 | case SystemZ::VMO: |
| 7498 | case SystemZ::VMRH: |
| 7499 | case SystemZ::VMRL: |
| 7500 | case SystemZ::VMX: |
| 7501 | case SystemZ::VMXL: |
| 7502 | case SystemZ::VPDI: |
| 7503 | case SystemZ::VPK: |
| 7504 | case SystemZ::VS: |
| 7505 | case SystemZ::VSCBI: |
| 7506 | case SystemZ::VSUM: |
| 7507 | case SystemZ::VSUMG: |
| 7508 | case SystemZ::VSUMQ: { |
| 7509 | // op: V1 |
| 7510 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7511 | Value |= (op & 0xf) << 36; |
| 7512 | Value |= (op & 0x10) << 7; |
| 7513 | // op: V2 |
| 7514 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7515 | Value |= (op & 0xf) << 32; |
| 7516 | Value |= (op & 0x10) << 6; |
| 7517 | // op: V3 |
| 7518 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7519 | Value |= (op & 0xf) << 28; |
| 7520 | Value |= (op & 0x10) << 5; |
| 7521 | // op: M4 |
| 7522 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7523 | Value |= (op & 0xf) << 12; |
| 7524 | break; |
| 7525 | } |
| 7526 | case SystemZ::VCRNF: |
| 7527 | case SystemZ::VD: |
| 7528 | case SystemZ::VDL: |
| 7529 | case SystemZ::VFA: |
| 7530 | case SystemZ::VFD: |
| 7531 | case SystemZ::VFM: |
| 7532 | case SystemZ::VFS: |
| 7533 | case SystemZ::VR: |
| 7534 | case SystemZ::VRL: { |
| 7535 | // op: V1 |
| 7536 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7537 | Value |= (op & 0xf) << 36; |
| 7538 | Value |= (op & 0x10) << 7; |
| 7539 | // op: V2 |
| 7540 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7541 | Value |= (op & 0xf) << 32; |
| 7542 | Value |= (op & 0x10) << 6; |
| 7543 | // op: V3 |
| 7544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7545 | Value |= (op & 0xf) << 28; |
| 7546 | Value |= (op & 0x10) << 5; |
| 7547 | // op: M4 |
| 7548 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7549 | Value |= (op & 0xf) << 12; |
| 7550 | // op: M5 |
| 7551 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 7552 | Value |= (op & 0xf) << 16; |
| 7553 | break; |
| 7554 | } |
| 7555 | case SystemZ::VFCE: |
| 7556 | case SystemZ::VFCH: |
| 7557 | case SystemZ::VFCHE: |
| 7558 | case SystemZ::VFMAX: |
| 7559 | case SystemZ::VFMIN: { |
| 7560 | // op: V1 |
| 7561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7562 | Value |= (op & 0xf) << 36; |
| 7563 | Value |= (op & 0x10) << 7; |
| 7564 | // op: V2 |
| 7565 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7566 | Value |= (op & 0xf) << 32; |
| 7567 | Value |= (op & 0x10) << 6; |
| 7568 | // op: V3 |
| 7569 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7570 | Value |= (op & 0xf) << 28; |
| 7571 | Value |= (op & 0x10) << 5; |
| 7572 | // op: M4 |
| 7573 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7574 | Value |= (op & 0xf) << 12; |
| 7575 | // op: M5 |
| 7576 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 7577 | Value |= (op & 0xf) << 16; |
| 7578 | // op: M6 |
| 7579 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 7580 | Value |= (op & 0xf) << 20; |
| 7581 | break; |
| 7582 | } |
| 7583 | case SystemZ::VCEQ: |
| 7584 | case SystemZ::VCH: |
| 7585 | case SystemZ::VCHL: |
| 7586 | case SystemZ::VFAE: |
| 7587 | case SystemZ::VFEE: |
| 7588 | case SystemZ::VFENE: |
| 7589 | case SystemZ::VPKLS: |
| 7590 | case SystemZ::VPKS: |
| 7591 | case SystemZ::VSCHP: { |
| 7592 | // op: V1 |
| 7593 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7594 | Value |= (op & 0xf) << 36; |
| 7595 | Value |= (op & 0x10) << 7; |
| 7596 | // op: V2 |
| 7597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7598 | Value |= (op & 0xf) << 32; |
| 7599 | Value |= (op & 0x10) << 6; |
| 7600 | // op: V3 |
| 7601 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7602 | Value |= (op & 0xf) << 28; |
| 7603 | Value |= (op & 0x10) << 5; |
| 7604 | // op: M4 |
| 7605 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7606 | Value |= (op & 0xf) << 12; |
| 7607 | // op: M5 |
| 7608 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 7609 | Value |= (op & 0xf) << 20; |
| 7610 | break; |
| 7611 | } |
| 7612 | case SystemZ::VCSPH: { |
| 7613 | // op: V1 |
| 7614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7615 | Value |= (op & 0xf) << 36; |
| 7616 | Value |= (op & 0x10) << 7; |
| 7617 | // op: V2 |
| 7618 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7619 | Value |= (op & 0xf) << 32; |
| 7620 | Value |= (op & 0x10) << 6; |
| 7621 | // op: V3 |
| 7622 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7623 | Value |= (op & 0xf) << 28; |
| 7624 | Value |= (op & 0x10) << 5; |
| 7625 | // op: M4 |
| 7626 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7627 | Value |= (op & 0xf) << 20; |
| 7628 | break; |
| 7629 | } |
| 7630 | case SystemZ::VFAEZBS: |
| 7631 | case SystemZ::VFAEZFS: |
| 7632 | case SystemZ::VFAEZHS: { |
| 7633 | // op: V1 |
| 7634 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7635 | Value |= (op & 0xf) << 36; |
| 7636 | Value |= (op & 0x10) << 7; |
| 7637 | // op: V2 |
| 7638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7639 | Value |= (op & 0xf) << 32; |
| 7640 | Value |= (op & 0x10) << 6; |
| 7641 | // op: V3 |
| 7642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7643 | Value |= (op & 0xf) << 28; |
| 7644 | Value |= (op & 0x10) << 5; |
| 7645 | // op: M5 |
| 7646 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7647 | Value |= (op & 0xc) << 20; |
| 7648 | break; |
| 7649 | } |
| 7650 | case SystemZ::VFAEZB: |
| 7651 | case SystemZ::VFAEZF: |
| 7652 | case SystemZ::VFAEZH: { |
| 7653 | // op: V1 |
| 7654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7655 | Value |= (op & 0xf) << 36; |
| 7656 | Value |= (op & 0x10) << 7; |
| 7657 | // op: V2 |
| 7658 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7659 | Value |= (op & 0xf) << 32; |
| 7660 | Value |= (op & 0x10) << 6; |
| 7661 | // op: V3 |
| 7662 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7663 | Value |= (op & 0xf) << 28; |
| 7664 | Value |= (op & 0x10) << 5; |
| 7665 | // op: M5 |
| 7666 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7667 | Value |= (op & 0xc) << 20; |
| 7668 | Value |= (op & 0x1) << 20; |
| 7669 | break; |
| 7670 | } |
| 7671 | case SystemZ::VFAEBS: |
| 7672 | case SystemZ::VFAEFS: |
| 7673 | case SystemZ::VFAEHS: { |
| 7674 | // op: V1 |
| 7675 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7676 | Value |= (op & 0xf) << 36; |
| 7677 | Value |= (op & 0x10) << 7; |
| 7678 | // op: V2 |
| 7679 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7680 | Value |= (op & 0xf) << 32; |
| 7681 | Value |= (op & 0x10) << 6; |
| 7682 | // op: V3 |
| 7683 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7684 | Value |= (op & 0xf) << 28; |
| 7685 | Value |= (op & 0x10) << 5; |
| 7686 | // op: M5 |
| 7687 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7688 | Value |= (op & 0xe) << 20; |
| 7689 | break; |
| 7690 | } |
| 7691 | case SystemZ::VDF: |
| 7692 | case SystemZ::VDG: |
| 7693 | case SystemZ::VDLF: |
| 7694 | case SystemZ::VDLG: |
| 7695 | case SystemZ::VDLQ: |
| 7696 | case SystemZ::VDQ: |
| 7697 | case SystemZ::VRF: |
| 7698 | case SystemZ::VRG: |
| 7699 | case SystemZ::VRLF: |
| 7700 | case SystemZ::VRLG: |
| 7701 | case SystemZ::VRLQ: |
| 7702 | case SystemZ::VRQ: { |
| 7703 | // op: V1 |
| 7704 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7705 | Value |= (op & 0xf) << 36; |
| 7706 | Value |= (op & 0x10) << 7; |
| 7707 | // op: V2 |
| 7708 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7709 | Value |= (op & 0xf) << 32; |
| 7710 | Value |= (op & 0x10) << 6; |
| 7711 | // op: V3 |
| 7712 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7713 | Value |= (op & 0xf) << 28; |
| 7714 | Value |= (op & 0x10) << 5; |
| 7715 | // op: M5 |
| 7716 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7717 | Value |= (op & 0xf) << 16; |
| 7718 | break; |
| 7719 | } |
| 7720 | case SystemZ::VFAEB: |
| 7721 | case SystemZ::VFAEF: |
| 7722 | case SystemZ::VFAEH: |
| 7723 | case SystemZ::VFEEB: |
| 7724 | case SystemZ::VFEEF: |
| 7725 | case SystemZ::VFEEH: |
| 7726 | case SystemZ::VFENEB: |
| 7727 | case SystemZ::VFENEF: |
| 7728 | case SystemZ::VFENEH: |
| 7729 | case SystemZ::VSCHDP: |
| 7730 | case SystemZ::VSCHSP: |
| 7731 | case SystemZ::VSCHXP: { |
| 7732 | // op: V1 |
| 7733 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7734 | Value |= (op & 0xf) << 36; |
| 7735 | Value |= (op & 0x10) << 7; |
| 7736 | // op: V2 |
| 7737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7738 | Value |= (op & 0xf) << 32; |
| 7739 | Value |= (op & 0x10) << 6; |
| 7740 | // op: V3 |
| 7741 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7742 | Value |= (op & 0xf) << 28; |
| 7743 | Value |= (op & 0x10) << 5; |
| 7744 | // op: M5 |
| 7745 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7746 | Value |= (op & 0xf) << 20; |
| 7747 | break; |
| 7748 | } |
| 7749 | case SystemZ::VFMAXDB: |
| 7750 | case SystemZ::VFMAXSB: |
| 7751 | case SystemZ::VFMINDB: |
| 7752 | case SystemZ::VFMINSB: |
| 7753 | case SystemZ::WFMAXDB: |
| 7754 | case SystemZ::WFMAXSB: |
| 7755 | case SystemZ::WFMAXXB: |
| 7756 | case SystemZ::WFMINDB: |
| 7757 | case SystemZ::WFMINSB: |
| 7758 | case SystemZ::WFMINXB: { |
| 7759 | // op: V1 |
| 7760 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7761 | Value |= (op & 0xf) << 36; |
| 7762 | Value |= (op & 0x10) << 7; |
| 7763 | // op: V2 |
| 7764 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7765 | Value |= (op & 0xf) << 32; |
| 7766 | Value |= (op & 0x10) << 6; |
| 7767 | // op: V3 |
| 7768 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7769 | Value |= (op & 0xf) << 28; |
| 7770 | Value |= (op & 0x10) << 5; |
| 7771 | // op: M6 |
| 7772 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 7773 | Value |= (op & 0xf) << 20; |
| 7774 | break; |
| 7775 | } |
| 7776 | case SystemZ::VACCCQ: |
| 7777 | case SystemZ::VACQ: |
| 7778 | case SystemZ::VBLENDB: |
| 7779 | case SystemZ::VBLENDF: |
| 7780 | case SystemZ::VBLENDG: |
| 7781 | case SystemZ::VBLENDH: |
| 7782 | case SystemZ::VBLENDQ: |
| 7783 | case SystemZ::VFMADB: |
| 7784 | case SystemZ::VFMASB: |
| 7785 | case SystemZ::VFMSDB: |
| 7786 | case SystemZ::VFMSSB: |
| 7787 | case SystemZ::VFNMADB: |
| 7788 | case SystemZ::VFNMASB: |
| 7789 | case SystemZ::VFNMSDB: |
| 7790 | case SystemZ::VFNMSSB: |
| 7791 | case SystemZ::VGFMAB: |
| 7792 | case SystemZ::VGFMAF: |
| 7793 | case SystemZ::VGFMAG: |
| 7794 | case SystemZ::VGFMAH: |
| 7795 | case SystemZ::VMAEB: |
| 7796 | case SystemZ::VMAEF: |
| 7797 | case SystemZ::VMAEG: |
| 7798 | case SystemZ::VMAEH: |
| 7799 | case SystemZ::VMAHB: |
| 7800 | case SystemZ::VMAHF: |
| 7801 | case SystemZ::VMAHG: |
| 7802 | case SystemZ::VMAHH: |
| 7803 | case SystemZ::VMAHQ: |
| 7804 | case SystemZ::VMALB: |
| 7805 | case SystemZ::VMALEB: |
| 7806 | case SystemZ::VMALEF: |
| 7807 | case SystemZ::VMALEG: |
| 7808 | case SystemZ::VMALEH: |
| 7809 | case SystemZ::VMALF: |
| 7810 | case SystemZ::VMALG: |
| 7811 | case SystemZ::VMALHB: |
| 7812 | case SystemZ::VMALHF: |
| 7813 | case SystemZ::VMALHG: |
| 7814 | case SystemZ::VMALHH: |
| 7815 | case SystemZ::VMALHQ: |
| 7816 | case SystemZ::VMALHW: |
| 7817 | case SystemZ::VMALOB: |
| 7818 | case SystemZ::VMALOF: |
| 7819 | case SystemZ::VMALOG: |
| 7820 | case SystemZ::VMALOH: |
| 7821 | case SystemZ::VMALQ: |
| 7822 | case SystemZ::VMAOB: |
| 7823 | case SystemZ::VMAOF: |
| 7824 | case SystemZ::VMAOG: |
| 7825 | case SystemZ::VMAOH: |
| 7826 | case SystemZ::VPERM: |
| 7827 | case SystemZ::VSBCBIQ: |
| 7828 | case SystemZ::VSBIQ: |
| 7829 | case SystemZ::VSEL: |
| 7830 | case SystemZ::VSTRSZB: |
| 7831 | case SystemZ::VSTRSZF: |
| 7832 | case SystemZ::VSTRSZH: |
| 7833 | case SystemZ::WFMADB: |
| 7834 | case SystemZ::WFMASB: |
| 7835 | case SystemZ::WFMAXB: |
| 7836 | case SystemZ::WFMSDB: |
| 7837 | case SystemZ::WFMSSB: |
| 7838 | case SystemZ::WFMSXB: |
| 7839 | case SystemZ::WFNMADB: |
| 7840 | case SystemZ::WFNMASB: |
| 7841 | case SystemZ::WFNMAXB: |
| 7842 | case SystemZ::WFNMSDB: |
| 7843 | case SystemZ::WFNMSSB: |
| 7844 | case SystemZ::WFNMSXB: { |
| 7845 | // op: V1 |
| 7846 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7847 | Value |= (op & 0xf) << 36; |
| 7848 | Value |= (op & 0x10) << 7; |
| 7849 | // op: V2 |
| 7850 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7851 | Value |= (op & 0xf) << 32; |
| 7852 | Value |= (op & 0x10) << 6; |
| 7853 | // op: V3 |
| 7854 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7855 | Value |= (op & 0xf) << 28; |
| 7856 | Value |= (op & 0x10) << 5; |
| 7857 | // op: V4 |
| 7858 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7859 | Value |= (op & 0xf) << 12; |
| 7860 | Value |= (op & 0x10) << 4; |
| 7861 | break; |
| 7862 | } |
| 7863 | case SystemZ::VEVAL: { |
| 7864 | // op: V1 |
| 7865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7866 | Value |= (op & 0xf) << 36; |
| 7867 | Value |= (op & 0x10) << 7; |
| 7868 | // op: V2 |
| 7869 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7870 | Value |= (op & 0xf) << 32; |
| 7871 | Value |= (op & 0x10) << 6; |
| 7872 | // op: V3 |
| 7873 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7874 | Value |= (op & 0xf) << 28; |
| 7875 | Value |= (op & 0x10) << 5; |
| 7876 | // op: V4 |
| 7877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7878 | Value |= (op & 0xf) << 12; |
| 7879 | Value |= (op & 0x10) << 4; |
| 7880 | // op: I5 |
| 7881 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 7882 | Value |= (op & 0xff) << 16; |
| 7883 | break; |
| 7884 | } |
| 7885 | case SystemZ::VFMA: |
| 7886 | case SystemZ::VFMS: |
| 7887 | case SystemZ::VFNMA: |
| 7888 | case SystemZ::VFNMS: { |
| 7889 | // op: V1 |
| 7890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7891 | Value |= (op & 0xf) << 36; |
| 7892 | Value |= (op & 0x10) << 7; |
| 7893 | // op: V2 |
| 7894 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7895 | Value |= (op & 0xf) << 32; |
| 7896 | Value |= (op & 0x10) << 6; |
| 7897 | // op: V3 |
| 7898 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7899 | Value |= (op & 0xf) << 28; |
| 7900 | Value |= (op & 0x10) << 5; |
| 7901 | // op: V4 |
| 7902 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7903 | Value |= (op & 0xf) << 12; |
| 7904 | Value |= (op & 0x10) << 4; |
| 7905 | // op: M5 |
| 7906 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 7907 | Value |= (op & 0xf) << 16; |
| 7908 | // op: M6 |
| 7909 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 7910 | Value |= (op & 0xf) << 24; |
| 7911 | break; |
| 7912 | } |
| 7913 | case SystemZ::VAC: |
| 7914 | case SystemZ::VACCC: |
| 7915 | case SystemZ::VBLEND: |
| 7916 | case SystemZ::VGFMA: |
| 7917 | case SystemZ::VMAE: |
| 7918 | case SystemZ::VMAH: |
| 7919 | case SystemZ::VMAL: |
| 7920 | case SystemZ::VMALE: |
| 7921 | case SystemZ::VMALH: |
| 7922 | case SystemZ::VMALO: |
| 7923 | case SystemZ::VMAO: |
| 7924 | case SystemZ::VSBCBI: |
| 7925 | case SystemZ::VSBI: { |
| 7926 | // op: V1 |
| 7927 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7928 | Value |= (op & 0xf) << 36; |
| 7929 | Value |= (op & 0x10) << 7; |
| 7930 | // op: V2 |
| 7931 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7932 | Value |= (op & 0xf) << 32; |
| 7933 | Value |= (op & 0x10) << 6; |
| 7934 | // op: V3 |
| 7935 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7936 | Value |= (op & 0xf) << 28; |
| 7937 | Value |= (op & 0x10) << 5; |
| 7938 | // op: V4 |
| 7939 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7940 | Value |= (op & 0xf) << 12; |
| 7941 | Value |= (op & 0x10) << 4; |
| 7942 | // op: M5 |
| 7943 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 7944 | Value |= (op & 0xf) << 24; |
| 7945 | break; |
| 7946 | } |
| 7947 | case SystemZ::VMSL: |
| 7948 | case SystemZ::VSTRC: |
| 7949 | case SystemZ::VSTRS: { |
| 7950 | // op: V1 |
| 7951 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7952 | Value |= (op & 0xf) << 36; |
| 7953 | Value |= (op & 0x10) << 7; |
| 7954 | // op: V2 |
| 7955 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7956 | Value |= (op & 0xf) << 32; |
| 7957 | Value |= (op & 0x10) << 6; |
| 7958 | // op: V3 |
| 7959 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7960 | Value |= (op & 0xf) << 28; |
| 7961 | Value |= (op & 0x10) << 5; |
| 7962 | // op: V4 |
| 7963 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7964 | Value |= (op & 0xf) << 12; |
| 7965 | Value |= (op & 0x10) << 4; |
| 7966 | // op: M5 |
| 7967 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 7968 | Value |= (op & 0xf) << 24; |
| 7969 | // op: M6 |
| 7970 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 7971 | Value |= (op & 0xf) << 20; |
| 7972 | break; |
| 7973 | } |
| 7974 | case SystemZ::VSTRCZBS: |
| 7975 | case SystemZ::VSTRCZFS: |
| 7976 | case SystemZ::VSTRCZHS: { |
| 7977 | // op: V1 |
| 7978 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7979 | Value |= (op & 0xf) << 36; |
| 7980 | Value |= (op & 0x10) << 7; |
| 7981 | // op: V2 |
| 7982 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7983 | Value |= (op & 0xf) << 32; |
| 7984 | Value |= (op & 0x10) << 6; |
| 7985 | // op: V3 |
| 7986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7987 | Value |= (op & 0xf) << 28; |
| 7988 | Value |= (op & 0x10) << 5; |
| 7989 | // op: V4 |
| 7990 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7991 | Value |= (op & 0xf) << 12; |
| 7992 | Value |= (op & 0x10) << 4; |
| 7993 | // op: M6 |
| 7994 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 7995 | Value |= (op & 0xc) << 20; |
| 7996 | break; |
| 7997 | } |
| 7998 | case SystemZ::VSTRCZB: |
| 7999 | case SystemZ::VSTRCZF: |
| 8000 | case SystemZ::VSTRCZH: { |
| 8001 | // op: V1 |
| 8002 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8003 | Value |= (op & 0xf) << 36; |
| 8004 | Value |= (op & 0x10) << 7; |
| 8005 | // op: V2 |
| 8006 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8007 | Value |= (op & 0xf) << 32; |
| 8008 | Value |= (op & 0x10) << 6; |
| 8009 | // op: V3 |
| 8010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8011 | Value |= (op & 0xf) << 28; |
| 8012 | Value |= (op & 0x10) << 5; |
| 8013 | // op: V4 |
| 8014 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8015 | Value |= (op & 0xf) << 12; |
| 8016 | Value |= (op & 0x10) << 4; |
| 8017 | // op: M6 |
| 8018 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 8019 | Value |= (op & 0xc) << 20; |
| 8020 | Value |= (op & 0x1) << 20; |
| 8021 | break; |
| 8022 | } |
| 8023 | case SystemZ::VSTRCBS: |
| 8024 | case SystemZ::VSTRCFS: |
| 8025 | case SystemZ::VSTRCHS: { |
| 8026 | // op: V1 |
| 8027 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8028 | Value |= (op & 0xf) << 36; |
| 8029 | Value |= (op & 0x10) << 7; |
| 8030 | // op: V2 |
| 8031 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8032 | Value |= (op & 0xf) << 32; |
| 8033 | Value |= (op & 0x10) << 6; |
| 8034 | // op: V3 |
| 8035 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8036 | Value |= (op & 0xf) << 28; |
| 8037 | Value |= (op & 0x10) << 5; |
| 8038 | // op: V4 |
| 8039 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8040 | Value |= (op & 0xf) << 12; |
| 8041 | Value |= (op & 0x10) << 4; |
| 8042 | // op: M6 |
| 8043 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 8044 | Value |= (op & 0xe) << 20; |
| 8045 | break; |
| 8046 | } |
| 8047 | case SystemZ::VMSLG: |
| 8048 | case SystemZ::VSTRCB: |
| 8049 | case SystemZ::VSTRCF: |
| 8050 | case SystemZ::VSTRCH: |
| 8051 | case SystemZ::VSTRSB: |
| 8052 | case SystemZ::VSTRSF: |
| 8053 | case SystemZ::VSTRSH: { |
| 8054 | // op: V1 |
| 8055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8056 | Value |= (op & 0xf) << 36; |
| 8057 | Value |= (op & 0x10) << 7; |
| 8058 | // op: V2 |
| 8059 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8060 | Value |= (op & 0xf) << 32; |
| 8061 | Value |= (op & 0x10) << 6; |
| 8062 | // op: V3 |
| 8063 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8064 | Value |= (op & 0xf) << 28; |
| 8065 | Value |= (op & 0x10) << 5; |
| 8066 | // op: V4 |
| 8067 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8068 | Value |= (op & 0xf) << 12; |
| 8069 | Value |= (op & 0x10) << 4; |
| 8070 | // op: M6 |
| 8071 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 8072 | Value |= (op & 0xf) << 20; |
| 8073 | break; |
| 8074 | } |
| 8075 | case SystemZ::VERIMB: |
| 8076 | case SystemZ::VERIMF: |
| 8077 | case SystemZ::VERIMG: |
| 8078 | case SystemZ::VERIMH: { |
| 8079 | // op: V1 |
| 8080 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8081 | Value |= (op & 0xf) << 36; |
| 8082 | Value |= (op & 0x10) << 7; |
| 8083 | // op: V2 |
| 8084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8085 | Value |= (op & 0xf) << 32; |
| 8086 | Value |= (op & 0x10) << 6; |
| 8087 | // op: V3 |
| 8088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8089 | Value |= (op & 0xf) << 28; |
| 8090 | Value |= (op & 0x10) << 5; |
| 8091 | // op: I4 |
| 8092 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 8093 | Value |= (op & 0xff) << 16; |
| 8094 | break; |
| 8095 | } |
| 8096 | case SystemZ::VERIM: { |
| 8097 | // op: V1 |
| 8098 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8099 | Value |= (op & 0xf) << 36; |
| 8100 | Value |= (op & 0x10) << 7; |
| 8101 | // op: V2 |
| 8102 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8103 | Value |= (op & 0xf) << 32; |
| 8104 | Value |= (op & 0x10) << 6; |
| 8105 | // op: V3 |
| 8106 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8107 | Value |= (op & 0xf) << 28; |
| 8108 | Value |= (op & 0x10) << 5; |
| 8109 | // op: I4 |
| 8110 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 8111 | Value |= (op & 0xff) << 16; |
| 8112 | // op: M5 |
| 8113 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 8114 | Value |= (op & 0xf) << 12; |
| 8115 | break; |
| 8116 | } |
| 8117 | case SystemZ::VSCEG: { |
| 8118 | // op: V1 |
| 8119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8120 | Value |= (op & 0xf) << 36; |
| 8121 | Value |= (op & 0x10) << 7; |
| 8122 | // op: V2 |
| 8123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8124 | Value |= (op & 0xf) << 32; |
| 8125 | Value |= (op & 0x10) << 6; |
| 8126 | // op: B2 |
| 8127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8128 | Value |= (op & 0xf) << 28; |
| 8129 | // op: D2 |
| 8130 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8131 | Value |= (op & 0xfff) << 16; |
| 8132 | // op: M3 |
| 8133 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, OpNum: 4, Fixups, STI); |
| 8134 | Value |= (op & 0xf) << 12; |
| 8135 | break; |
| 8136 | } |
| 8137 | case SystemZ::VSCEF: { |
| 8138 | // op: V1 |
| 8139 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8140 | Value |= (op & 0xf) << 36; |
| 8141 | Value |= (op & 0x10) << 7; |
| 8142 | // op: V2 |
| 8143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8144 | Value |= (op & 0xf) << 32; |
| 8145 | Value |= (op & 0x10) << 6; |
| 8146 | // op: B2 |
| 8147 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8148 | Value |= (op & 0xf) << 28; |
| 8149 | // op: D2 |
| 8150 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8151 | Value |= (op & 0xfff) << 16; |
| 8152 | // op: M3 |
| 8153 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, OpNum: 4, Fixups, STI); |
| 8154 | Value |= (op & 0xf) << 12; |
| 8155 | break; |
| 8156 | } |
| 8157 | case SystemZ::VGEG: { |
| 8158 | // op: V1 |
| 8159 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8160 | Value |= (op & 0xf) << 36; |
| 8161 | Value |= (op & 0x10) << 7; |
| 8162 | // op: V2 |
| 8163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8164 | Value |= (op & 0xf) << 32; |
| 8165 | Value |= (op & 0x10) << 6; |
| 8166 | // op: B2 |
| 8167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8168 | Value |= (op & 0xf) << 28; |
| 8169 | // op: D2 |
| 8170 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8171 | Value |= (op & 0xfff) << 16; |
| 8172 | // op: M3 |
| 8173 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, OpNum: 5, Fixups, STI); |
| 8174 | Value |= (op & 0xf) << 12; |
| 8175 | break; |
| 8176 | } |
| 8177 | case SystemZ::VGEF: { |
| 8178 | // op: V1 |
| 8179 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8180 | Value |= (op & 0xf) << 36; |
| 8181 | Value |= (op & 0x10) << 7; |
| 8182 | // op: V2 |
| 8183 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8184 | Value |= (op & 0xf) << 32; |
| 8185 | Value |= (op & 0x10) << 6; |
| 8186 | // op: B2 |
| 8187 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8188 | Value |= (op & 0xf) << 28; |
| 8189 | // op: D2 |
| 8190 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8191 | Value |= (op & 0xfff) << 16; |
| 8192 | // op: M3 |
| 8193 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, OpNum: 5, Fixups, STI); |
| 8194 | Value |= (op & 0xf) << 12; |
| 8195 | break; |
| 8196 | } |
| 8197 | case SystemZ::VREPB: |
| 8198 | case SystemZ::VREPF: |
| 8199 | case SystemZ::VREPG: |
| 8200 | case SystemZ::VREPH: { |
| 8201 | // op: V1 |
| 8202 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8203 | Value |= (op & 0xf) << 36; |
| 8204 | Value |= (op & 0x10) << 7; |
| 8205 | // op: V3 |
| 8206 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8207 | Value |= (op & 0xf) << 32; |
| 8208 | Value |= (op & 0x10) << 6; |
| 8209 | // op: I2 |
| 8210 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 2, Fixups, STI); |
| 8211 | Value |= (op & 0xffff) << 16; |
| 8212 | break; |
| 8213 | } |
| 8214 | case SystemZ::VREP: { |
| 8215 | // op: V1 |
| 8216 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8217 | Value |= (op & 0xf) << 36; |
| 8218 | Value |= (op & 0x10) << 7; |
| 8219 | // op: V3 |
| 8220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8221 | Value |= (op & 0xf) << 32; |
| 8222 | Value |= (op & 0x10) << 6; |
| 8223 | // op: I2 |
| 8224 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 2, Fixups, STI); |
| 8225 | Value |= (op & 0xffff) << 16; |
| 8226 | // op: M4 |
| 8227 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 8228 | Value |= (op & 0xf) << 12; |
| 8229 | break; |
| 8230 | } |
| 8231 | case SystemZ::VL: |
| 8232 | case SystemZ::VLBRF: |
| 8233 | case SystemZ::VLBRG: |
| 8234 | case SystemZ::VLBRH: |
| 8235 | case SystemZ::VLBRQ: |
| 8236 | case SystemZ::VLBRREPF: |
| 8237 | case SystemZ::VLBRREPG: |
| 8238 | case SystemZ::VLBRREPH: |
| 8239 | case SystemZ::VLERF: |
| 8240 | case SystemZ::VLERG: |
| 8241 | case SystemZ::VLERH: |
| 8242 | case SystemZ::VLLEBRZE: |
| 8243 | case SystemZ::VLLEBRZF: |
| 8244 | case SystemZ::VLLEBRZG: |
| 8245 | case SystemZ::VLLEBRZH: |
| 8246 | case SystemZ::VLLEZB: |
| 8247 | case SystemZ::VLLEZF: |
| 8248 | case SystemZ::VLLEZG: |
| 8249 | case SystemZ::VLLEZH: |
| 8250 | case SystemZ::VLLEZLF: |
| 8251 | case SystemZ::VLREPB: |
| 8252 | case SystemZ::VLREPF: |
| 8253 | case SystemZ::VLREPG: |
| 8254 | case SystemZ::VLREPH: |
| 8255 | case SystemZ::VST: |
| 8256 | case SystemZ::VSTBRF: |
| 8257 | case SystemZ::VSTBRG: |
| 8258 | case SystemZ::VSTBRH: |
| 8259 | case SystemZ::VSTBRQ: |
| 8260 | case SystemZ::VSTERF: |
| 8261 | case SystemZ::VSTERG: |
| 8262 | case SystemZ::VSTERH: { |
| 8263 | // op: V1 |
| 8264 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8265 | Value |= (op & 0xf) << 36; |
| 8266 | Value |= (op & 0x10) << 7; |
| 8267 | // op: X2 |
| 8268 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8269 | Value |= (op & 0xf) << 32; |
| 8270 | // op: B2 |
| 8271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8272 | Value |= (op & 0xf) << 28; |
| 8273 | // op: D2 |
| 8274 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8275 | Value |= (op & 0xfff) << 16; |
| 8276 | break; |
| 8277 | } |
| 8278 | case SystemZ::VSTEBRG: |
| 8279 | case SystemZ::VSTEG: { |
| 8280 | // op: V1 |
| 8281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8282 | Value |= (op & 0xf) << 36; |
| 8283 | Value |= (op & 0x10) << 7; |
| 8284 | // op: X2 |
| 8285 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8286 | Value |= (op & 0xf) << 32; |
| 8287 | // op: B2 |
| 8288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8289 | Value |= (op & 0xf) << 28; |
| 8290 | // op: D2 |
| 8291 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8292 | Value |= (op & 0xfff) << 16; |
| 8293 | // op: M3 |
| 8294 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, OpNum: 4, Fixups, STI); |
| 8295 | Value |= (op & 0xf) << 12; |
| 8296 | break; |
| 8297 | } |
| 8298 | case SystemZ::VSTEBRF: |
| 8299 | case SystemZ::VSTEF: { |
| 8300 | // op: V1 |
| 8301 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8302 | Value |= (op & 0xf) << 36; |
| 8303 | Value |= (op & 0x10) << 7; |
| 8304 | // op: X2 |
| 8305 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8306 | Value |= (op & 0xf) << 32; |
| 8307 | // op: B2 |
| 8308 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8309 | Value |= (op & 0xf) << 28; |
| 8310 | // op: D2 |
| 8311 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8312 | Value |= (op & 0xfff) << 16; |
| 8313 | // op: M3 |
| 8314 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, OpNum: 4, Fixups, STI); |
| 8315 | Value |= (op & 0xf) << 12; |
| 8316 | break; |
| 8317 | } |
| 8318 | case SystemZ::VSTEBRH: |
| 8319 | case SystemZ::VSTEH: { |
| 8320 | // op: V1 |
| 8321 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8322 | Value |= (op & 0xf) << 36; |
| 8323 | Value |= (op & 0x10) << 7; |
| 8324 | // op: X2 |
| 8325 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8326 | Value |= (op & 0xf) << 32; |
| 8327 | // op: B2 |
| 8328 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8329 | Value |= (op & 0xf) << 28; |
| 8330 | // op: D2 |
| 8331 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8332 | Value |= (op & 0xfff) << 16; |
| 8333 | // op: M3 |
| 8334 | op = getImmOpValue<SystemZ::FK_390_U3Imm>(MI, OpNum: 4, Fixups, STI); |
| 8335 | Value |= (op & 0xf) << 12; |
| 8336 | break; |
| 8337 | } |
| 8338 | case SystemZ::VLAlign: |
| 8339 | case SystemZ::VLBB: |
| 8340 | case SystemZ::VLBR: |
| 8341 | case SystemZ::VLBRREP: |
| 8342 | case SystemZ::VLER: |
| 8343 | case SystemZ::VLLEBRZ: |
| 8344 | case SystemZ::VLLEZ: |
| 8345 | case SystemZ::VLREP: |
| 8346 | case SystemZ::VSTAlign: |
| 8347 | case SystemZ::VSTBR: |
| 8348 | case SystemZ::VSTEB: |
| 8349 | case SystemZ::VSTER: { |
| 8350 | // op: V1 |
| 8351 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8352 | Value |= (op & 0xf) << 36; |
| 8353 | Value |= (op & 0x10) << 7; |
| 8354 | // op: X2 |
| 8355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8356 | Value |= (op & 0xf) << 32; |
| 8357 | // op: B2 |
| 8358 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8359 | Value |= (op & 0xf) << 28; |
| 8360 | // op: D2 |
| 8361 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8362 | Value |= (op & 0xfff) << 16; |
| 8363 | // op: M3 |
| 8364 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 8365 | Value |= (op & 0xf) << 12; |
| 8366 | break; |
| 8367 | } |
| 8368 | case SystemZ::VLEBRG: |
| 8369 | case SystemZ::VLEG: { |
| 8370 | // op: V1 |
| 8371 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8372 | Value |= (op & 0xf) << 36; |
| 8373 | Value |= (op & 0x10) << 7; |
| 8374 | // op: X2 |
| 8375 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8376 | Value |= (op & 0xf) << 32; |
| 8377 | // op: B2 |
| 8378 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8379 | Value |= (op & 0xf) << 28; |
| 8380 | // op: D2 |
| 8381 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8382 | Value |= (op & 0xfff) << 16; |
| 8383 | // op: M3 |
| 8384 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, OpNum: 5, Fixups, STI); |
| 8385 | Value |= (op & 0xf) << 12; |
| 8386 | break; |
| 8387 | } |
| 8388 | case SystemZ::VLEBRF: |
| 8389 | case SystemZ::VLEF: { |
| 8390 | // op: V1 |
| 8391 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8392 | Value |= (op & 0xf) << 36; |
| 8393 | Value |= (op & 0x10) << 7; |
| 8394 | // op: X2 |
| 8395 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8396 | Value |= (op & 0xf) << 32; |
| 8397 | // op: B2 |
| 8398 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8399 | Value |= (op & 0xf) << 28; |
| 8400 | // op: D2 |
| 8401 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8402 | Value |= (op & 0xfff) << 16; |
| 8403 | // op: M3 |
| 8404 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, OpNum: 5, Fixups, STI); |
| 8405 | Value |= (op & 0xf) << 12; |
| 8406 | break; |
| 8407 | } |
| 8408 | case SystemZ::VLEBRH: |
| 8409 | case SystemZ::VLEH: { |
| 8410 | // op: V1 |
| 8411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8412 | Value |= (op & 0xf) << 36; |
| 8413 | Value |= (op & 0x10) << 7; |
| 8414 | // op: X2 |
| 8415 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8416 | Value |= (op & 0xf) << 32; |
| 8417 | // op: B2 |
| 8418 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8419 | Value |= (op & 0xf) << 28; |
| 8420 | // op: D2 |
| 8421 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8422 | Value |= (op & 0xfff) << 16; |
| 8423 | // op: M3 |
| 8424 | op = getImmOpValue<SystemZ::FK_390_U3Imm>(MI, OpNum: 5, Fixups, STI); |
| 8425 | Value |= (op & 0xf) << 12; |
| 8426 | break; |
| 8427 | } |
| 8428 | case SystemZ::VLEB: { |
| 8429 | // op: V1 |
| 8430 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8431 | Value |= (op & 0xf) << 36; |
| 8432 | Value |= (op & 0x10) << 7; |
| 8433 | // op: X2 |
| 8434 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8435 | Value |= (op & 0xf) << 32; |
| 8436 | // op: B2 |
| 8437 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8438 | Value |= (op & 0xf) << 28; |
| 8439 | // op: D2 |
| 8440 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8441 | Value |= (op & 0xfff) << 16; |
| 8442 | // op: M3 |
| 8443 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 8444 | Value |= (op & 0xf) << 12; |
| 8445 | break; |
| 8446 | } |
| 8447 | case SystemZ::B: |
| 8448 | case SystemZ::BAsmE: |
| 8449 | case SystemZ::BAsmH: |
| 8450 | case SystemZ::BAsmHE: |
| 8451 | case SystemZ::BAsmL: |
| 8452 | case SystemZ::BAsmLE: |
| 8453 | case SystemZ::BAsmLH: |
| 8454 | case SystemZ::BAsmM: |
| 8455 | case SystemZ::BAsmNE: |
| 8456 | case SystemZ::BAsmNH: |
| 8457 | case SystemZ::BAsmNHE: |
| 8458 | case SystemZ::BAsmNL: |
| 8459 | case SystemZ::BAsmNLE: |
| 8460 | case SystemZ::BAsmNLH: |
| 8461 | case SystemZ::BAsmNM: |
| 8462 | case SystemZ::BAsmNO: |
| 8463 | case SystemZ::BAsmNP: |
| 8464 | case SystemZ::BAsmNZ: |
| 8465 | case SystemZ::BAsmO: |
| 8466 | case SystemZ::BAsmP: |
| 8467 | case SystemZ::BAsmZ: |
| 8468 | case SystemZ::NOP: { |
| 8469 | // op: X2 |
| 8470 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8471 | Value |= (op & 0xf) << 16; |
| 8472 | // op: B2 |
| 8473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8474 | Value |= (op & 0xf) << 12; |
| 8475 | // op: D2 |
| 8476 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 1, Fixups, STI); |
| 8477 | Value |= (op & 0xfff); |
| 8478 | break; |
| 8479 | } |
| 8480 | case SystemZ::BI: |
| 8481 | case SystemZ::BIAsmE: |
| 8482 | case SystemZ::BIAsmH: |
| 8483 | case SystemZ::BIAsmHE: |
| 8484 | case SystemZ::BIAsmL: |
| 8485 | case SystemZ::BIAsmLE: |
| 8486 | case SystemZ::BIAsmLH: |
| 8487 | case SystemZ::BIAsmM: |
| 8488 | case SystemZ::BIAsmNE: |
| 8489 | case SystemZ::BIAsmNH: |
| 8490 | case SystemZ::BIAsmNHE: |
| 8491 | case SystemZ::BIAsmNL: |
| 8492 | case SystemZ::BIAsmNLE: |
| 8493 | case SystemZ::BIAsmNLH: |
| 8494 | case SystemZ::BIAsmNM: |
| 8495 | case SystemZ::BIAsmNO: |
| 8496 | case SystemZ::BIAsmNP: |
| 8497 | case SystemZ::BIAsmNZ: |
| 8498 | case SystemZ::BIAsmO: |
| 8499 | case SystemZ::BIAsmP: |
| 8500 | case SystemZ::BIAsmZ: { |
| 8501 | // op: X2 |
| 8502 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8503 | Value |= (op & 0xf) << 32; |
| 8504 | // op: B2 |
| 8505 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8506 | Value |= (op & 0xf) << 28; |
| 8507 | // op: D2 |
| 8508 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 1, Fixups, STI); |
| 8509 | Value |= (op & 0xfff) << 16; |
| 8510 | Value |= (op & 0xff000) >> 4; |
| 8511 | break; |
| 8512 | } |
| 8513 | case SystemZ::InsnI: { |
| 8514 | // op: enc |
| 8515 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 0, Fixups, STI); |
| 8516 | Value |= (op & 0xff00); |
| 8517 | // op: I1 |
| 8518 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 1, Fixups, STI); |
| 8519 | Value |= (op & 0xff); |
| 8520 | break; |
| 8521 | } |
| 8522 | case SystemZ::InsnRR: { |
| 8523 | // op: enc |
| 8524 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 0, Fixups, STI); |
| 8525 | Value |= (op & 0xff00); |
| 8526 | // op: R1 |
| 8527 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8528 | Value |= (op & 0xf) << 4; |
| 8529 | // op: R2 |
| 8530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8531 | Value |= (op & 0xf); |
| 8532 | break; |
| 8533 | } |
| 8534 | case SystemZ::InsnE: { |
| 8535 | // op: enc |
| 8536 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 0, Fixups, STI); |
| 8537 | Value |= (op & 0xffff); |
| 8538 | break; |
| 8539 | } |
| 8540 | case SystemZ::InsnSI: { |
| 8541 | // op: enc |
| 8542 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8543 | Value |= (op & 0xff000000); |
| 8544 | // op: B1 |
| 8545 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8546 | Value |= (op & 0xf) << 12; |
| 8547 | // op: D1 |
| 8548 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8549 | Value |= (op & 0xfff); |
| 8550 | // op: I2 |
| 8551 | op = getImmOpValue<SystemZ::FK_390_X8Imm>(MI, OpNum: 3, Fixups, STI); |
| 8552 | Value |= (op & 0xff) << 16; |
| 8553 | break; |
| 8554 | } |
| 8555 | case SystemZ::InsnRXb: { |
| 8556 | // op: enc |
| 8557 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8558 | Value |= (op & 0xff000000); |
| 8559 | // op: M1 |
| 8560 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 8561 | Value |= (op & 0xf) << 20; |
| 8562 | // op: X2 |
| 8563 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8564 | Value |= (op & 0xf) << 16; |
| 8565 | // op: B2 |
| 8566 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8567 | Value |= (op & 0xf) << 12; |
| 8568 | // op: D2 |
| 8569 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8570 | Value |= (op & 0xfff); |
| 8571 | break; |
| 8572 | } |
| 8573 | case SystemZ::InsnRSb: { |
| 8574 | // op: enc |
| 8575 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8576 | Value |= (op & 0xff000000); |
| 8577 | // op: R1 |
| 8578 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8579 | Value |= (op & 0xf) << 20; |
| 8580 | // op: M3 |
| 8581 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 8582 | Value |= (op & 0xf) << 16; |
| 8583 | // op: B2 |
| 8584 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8585 | Value |= (op & 0xf) << 12; |
| 8586 | // op: D2 |
| 8587 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8588 | Value |= (op & 0xfff); |
| 8589 | break; |
| 8590 | } |
| 8591 | case SystemZ::InsnRS: { |
| 8592 | // op: enc |
| 8593 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8594 | Value |= (op & 0xff000000); |
| 8595 | // op: R1 |
| 8596 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8597 | Value |= (op & 0xf) << 20; |
| 8598 | // op: R3 |
| 8599 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8600 | Value |= (op & 0xf) << 16; |
| 8601 | // op: B2 |
| 8602 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8603 | Value |= (op & 0xf) << 12; |
| 8604 | // op: D2 |
| 8605 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 8606 | Value |= (op & 0xfff); |
| 8607 | break; |
| 8608 | } |
| 8609 | case SystemZ::InsnRSI: { |
| 8610 | // op: enc |
| 8611 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8612 | Value |= (op & 0xff000000); |
| 8613 | // op: R1 |
| 8614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8615 | Value |= (op & 0xf) << 20; |
| 8616 | // op: R3 |
| 8617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8618 | Value |= (op & 0xf) << 16; |
| 8619 | // op: RI2 |
| 8620 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 8621 | Value |= (op & 0xffff); |
| 8622 | break; |
| 8623 | } |
| 8624 | case SystemZ::InsnRSa: { |
| 8625 | // op: enc |
| 8626 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8627 | Value |= (op & 0xff000000); |
| 8628 | // op: R1 |
| 8629 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8630 | Value |= (op & 0xf) << 20; |
| 8631 | // op: R3 |
| 8632 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8633 | Value |= (op & 0xf) << 16; |
| 8634 | // op: B2 |
| 8635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8636 | Value |= (op & 0xf) << 12; |
| 8637 | // op: D2 |
| 8638 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8639 | Value |= (op & 0xfff); |
| 8640 | break; |
| 8641 | } |
| 8642 | case SystemZ::InsnRX: |
| 8643 | case SystemZ::InsnRXa: { |
| 8644 | // op: enc |
| 8645 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8646 | Value |= (op & 0xff000000); |
| 8647 | // op: R1 |
| 8648 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8649 | Value |= (op & 0xf) << 20; |
| 8650 | // op: X2 |
| 8651 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8652 | Value |= (op & 0xf) << 16; |
| 8653 | // op: B2 |
| 8654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8655 | Value |= (op & 0xf) << 12; |
| 8656 | // op: D2 |
| 8657 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8658 | Value |= (op & 0xfff); |
| 8659 | break; |
| 8660 | } |
| 8661 | case SystemZ::InsnRIc: { |
| 8662 | // op: enc |
| 8663 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8664 | Value |= (op & 0xff000000); |
| 8665 | Value |= (op & 0xf0000); |
| 8666 | // op: M1 |
| 8667 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 8668 | Value |= (op & 0xf) << 20; |
| 8669 | // op: RI2 |
| 8670 | op = getPC16DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 8671 | Value |= (op & 0xffff); |
| 8672 | break; |
| 8673 | } |
| 8674 | case SystemZ::InsnRI: { |
| 8675 | // op: enc |
| 8676 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8677 | Value |= (op & 0xff000000); |
| 8678 | Value |= (op & 0xf0000); |
| 8679 | // op: R1 |
| 8680 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8681 | Value |= (op & 0xf) << 20; |
| 8682 | // op: I2 |
| 8683 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 8684 | Value |= (op & 0xffff); |
| 8685 | break; |
| 8686 | } |
| 8687 | case SystemZ::InsnRIa: { |
| 8688 | // op: enc |
| 8689 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8690 | Value |= (op & 0xff000000); |
| 8691 | Value |= (op & 0xf0000); |
| 8692 | // op: R1 |
| 8693 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8694 | Value |= (op & 0xf) << 20; |
| 8695 | // op: I2 |
| 8696 | op = getImmOpValue<SystemZ::FK_390_X16Imm>(MI, OpNum: 2, Fixups, STI); |
| 8697 | Value |= (op & 0xffff); |
| 8698 | break; |
| 8699 | } |
| 8700 | case SystemZ::InsnRIb: { |
| 8701 | // op: enc |
| 8702 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8703 | Value |= (op & 0xff000000); |
| 8704 | Value |= (op & 0xf0000); |
| 8705 | // op: R1 |
| 8706 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8707 | Value |= (op & 0xf) << 20; |
| 8708 | // op: RI2 |
| 8709 | op = getPC16DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 8710 | Value |= (op & 0xffff); |
| 8711 | break; |
| 8712 | } |
| 8713 | case SystemZ::InsnS: { |
| 8714 | // op: enc |
| 8715 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8716 | Value |= (op & 0xffff0000); |
| 8717 | // op: B2 |
| 8718 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8719 | Value |= (op & 0xf) << 12; |
| 8720 | // op: D2 |
| 8721 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8722 | Value |= (op & 0xfff); |
| 8723 | break; |
| 8724 | } |
| 8725 | case SystemZ::InsnIE: { |
| 8726 | // op: enc |
| 8727 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8728 | Value |= (op & 0xffff0000); |
| 8729 | // op: I1 |
| 8730 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 8731 | Value |= (op & 0xf) << 4; |
| 8732 | // op: I2 |
| 8733 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 8734 | Value |= (op & 0xf); |
| 8735 | break; |
| 8736 | } |
| 8737 | case SystemZ::InsnRRD: { |
| 8738 | // op: enc |
| 8739 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8740 | Value |= (op & 0xffff0000); |
| 8741 | // op: R1 |
| 8742 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8743 | Value |= (op & 0xf) << 12; |
| 8744 | // op: R3 |
| 8745 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8746 | Value |= (op & 0xf) << 4; |
| 8747 | // op: R2 |
| 8748 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8749 | Value |= (op & 0xf); |
| 8750 | break; |
| 8751 | } |
| 8752 | case SystemZ::InsnRRE: { |
| 8753 | // op: enc |
| 8754 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8755 | Value |= (op & 0xffff0000); |
| 8756 | // op: R1 |
| 8757 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8758 | Value |= (op & 0xf) << 4; |
| 8759 | // op: R2 |
| 8760 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8761 | Value |= (op & 0xf); |
| 8762 | break; |
| 8763 | } |
| 8764 | case SystemZ::InsnRRFc: { |
| 8765 | // op: enc |
| 8766 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8767 | Value |= (op & 0xffff0000); |
| 8768 | // op: R1 |
| 8769 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8770 | Value |= (op & 0xf) << 4; |
| 8771 | // op: R2 |
| 8772 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8773 | Value |= (op & 0xf); |
| 8774 | // op: M3 |
| 8775 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 8776 | Value |= (op & 0xf) << 12; |
| 8777 | break; |
| 8778 | } |
| 8779 | case SystemZ::InsnRRFd: { |
| 8780 | // op: enc |
| 8781 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8782 | Value |= (op & 0xffff0000); |
| 8783 | // op: R1 |
| 8784 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8785 | Value |= (op & 0xf) << 4; |
| 8786 | // op: R2 |
| 8787 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8788 | Value |= (op & 0xf); |
| 8789 | // op: M4 |
| 8790 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 8791 | Value |= (op & 0xf) << 8; |
| 8792 | break; |
| 8793 | } |
| 8794 | case SystemZ::InsnRRF: |
| 8795 | case SystemZ::InsnRRFa: { |
| 8796 | // op: enc |
| 8797 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8798 | Value |= (op & 0xffff0000); |
| 8799 | // op: R1 |
| 8800 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8801 | Value |= (op & 0xf) << 4; |
| 8802 | // op: R2 |
| 8803 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8804 | Value |= (op & 0xf); |
| 8805 | // op: R3 |
| 8806 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8807 | Value |= (op & 0xf) << 12; |
| 8808 | // op: M4 |
| 8809 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 8810 | Value |= (op & 0xf) << 8; |
| 8811 | break; |
| 8812 | } |
| 8813 | case SystemZ::InsnRRFe: { |
| 8814 | // op: enc |
| 8815 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8816 | Value |= (op & 0xffff0000); |
| 8817 | // op: R1 |
| 8818 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8819 | Value |= (op & 0xf) << 4; |
| 8820 | // op: R2 |
| 8821 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8822 | Value |= (op & 0xf); |
| 8823 | // op: M3 |
| 8824 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 2, Fixups, STI); |
| 8825 | Value |= (op & 0xf) << 12; |
| 8826 | // op: M4 |
| 8827 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 8828 | Value |= (op & 0xf) << 8; |
| 8829 | break; |
| 8830 | } |
| 8831 | case SystemZ::InsnRRFb: { |
| 8832 | // op: enc |
| 8833 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 0, Fixups, STI); |
| 8834 | Value |= (op & 0xffff0000); |
| 8835 | // op: R1 |
| 8836 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8837 | Value |= (op & 0xf) << 4; |
| 8838 | // op: R2 |
| 8839 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8840 | Value |= (op & 0xf); |
| 8841 | // op: R3 |
| 8842 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8843 | Value |= (op & 0xf) << 12; |
| 8844 | // op: M4 |
| 8845 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 8846 | Value |= (op & 0xf) << 8; |
| 8847 | break; |
| 8848 | } |
| 8849 | case SystemZ::InsnSSf: { |
| 8850 | // op: enc |
| 8851 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 8852 | Value |= (op & 0xff0000000000); |
| 8853 | // op: B1 |
| 8854 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8855 | Value |= (op & 0xf) << 28; |
| 8856 | // op: D1 |
| 8857 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8858 | Value |= (op & 0xfff) << 16; |
| 8859 | // op: B2 |
| 8860 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8861 | Value |= (op & 0xf) << 12; |
| 8862 | // op: D2 |
| 8863 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 8864 | Value |= (op & 0xfff); |
| 8865 | // op: L2 |
| 8866 | op = getLenEncoding<SystemZ::FK_390_U8Imm>(MI, OpNum: 5, Fixups, STI); |
| 8867 | Value |= (op & 0xff) << 32; |
| 8868 | break; |
| 8869 | } |
| 8870 | case SystemZ::InsnSSc: { |
| 8871 | // op: enc |
| 8872 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 8873 | Value |= (op & 0xff0000000000); |
| 8874 | // op: B1 |
| 8875 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8876 | Value |= (op & 0xf) << 28; |
| 8877 | // op: D1 |
| 8878 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8879 | Value |= (op & 0xfff) << 16; |
| 8880 | // op: L1 |
| 8881 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 8882 | Value |= (op & 0xf) << 36; |
| 8883 | // op: B2 |
| 8884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8885 | Value |= (op & 0xf) << 12; |
| 8886 | // op: D2 |
| 8887 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 5, Fixups, STI); |
| 8888 | Value |= (op & 0xfff); |
| 8889 | // op: I3 |
| 8890 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 6, Fixups, STI); |
| 8891 | Value |= (op & 0xf) << 32; |
| 8892 | break; |
| 8893 | } |
| 8894 | case SystemZ::InsnSSb: { |
| 8895 | // op: enc |
| 8896 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 8897 | Value |= (op & 0xff0000000000); |
| 8898 | // op: B1 |
| 8899 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8900 | Value |= (op & 0xf) << 28; |
| 8901 | // op: D1 |
| 8902 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8903 | Value |= (op & 0xfff) << 16; |
| 8904 | // op: L1 |
| 8905 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 8906 | Value |= (op & 0xf) << 36; |
| 8907 | // op: B2 |
| 8908 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8909 | Value |= (op & 0xf) << 12; |
| 8910 | // op: D2 |
| 8911 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 5, Fixups, STI); |
| 8912 | Value |= (op & 0xfff); |
| 8913 | // op: L2 |
| 8914 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, OpNum: 6, Fixups, STI); |
| 8915 | Value |= (op & 0xf) << 32; |
| 8916 | break; |
| 8917 | } |
| 8918 | case SystemZ::InsnSSa: { |
| 8919 | // op: enc |
| 8920 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 8921 | Value |= (op & 0xff0000000000); |
| 8922 | // op: B1 |
| 8923 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8924 | Value |= (op & 0xf) << 28; |
| 8925 | // op: D1 |
| 8926 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 8927 | Value |= (op & 0xfff) << 16; |
| 8928 | // op: L1 |
| 8929 | op = getLenEncoding<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 8930 | Value |= (op & 0xff) << 32; |
| 8931 | // op: B2 |
| 8932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8933 | Value |= (op & 0xf) << 12; |
| 8934 | // op: D2 |
| 8935 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 5, Fixups, STI); |
| 8936 | Value |= (op & 0xfff); |
| 8937 | break; |
| 8938 | } |
| 8939 | case SystemZ::InsnMII: { |
| 8940 | // op: enc |
| 8941 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 8942 | Value |= (op & 0xff0000000000); |
| 8943 | // op: M1 |
| 8944 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 8945 | Value |= (op & 0xf) << 36; |
| 8946 | // op: RI2 |
| 8947 | op = getPC12DBLBPPEncoding(MI, OpNum: 2, Fixups, STI); |
| 8948 | Value |= (op & 0xfff) << 24; |
| 8949 | // op: RI3 |
| 8950 | op = getPC24DBLBPPEncoding(MI, OpNum: 3, Fixups, STI); |
| 8951 | Value |= (op & 0xffffff); |
| 8952 | break; |
| 8953 | } |
| 8954 | case SystemZ::InsnSMI: { |
| 8955 | // op: enc |
| 8956 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 8957 | Value |= (op & 0xff0000000000); |
| 8958 | // op: M1 |
| 8959 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 8960 | Value |= (op & 0xf) << 36; |
| 8961 | // op: RI2 |
| 8962 | op = getPC16DBLBPPEncoding(MI, OpNum: 2, Fixups, STI); |
| 8963 | Value |= (op & 0xffff); |
| 8964 | // op: B3 |
| 8965 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8966 | Value |= (op & 0xf) << 28; |
| 8967 | // op: D3 |
| 8968 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 8969 | Value |= (op & 0xfff) << 16; |
| 8970 | break; |
| 8971 | } |
| 8972 | case SystemZ::InsnSSe: { |
| 8973 | // op: enc |
| 8974 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 8975 | Value |= (op & 0xff0000000000); |
| 8976 | // op: R1 |
| 8977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8978 | Value |= (op & 0xf) << 36; |
| 8979 | // op: B2 |
| 8980 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8981 | Value |= (op & 0xf) << 28; |
| 8982 | // op: D2 |
| 8983 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 8984 | Value |= (op & 0xfff) << 16; |
| 8985 | // op: R3 |
| 8986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8987 | Value |= (op & 0xf) << 32; |
| 8988 | // op: B4 |
| 8989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 8990 | Value |= (op & 0xf) << 12; |
| 8991 | // op: D4 |
| 8992 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 6, Fixups, STI); |
| 8993 | Value |= (op & 0xfff); |
| 8994 | break; |
| 8995 | } |
| 8996 | case SystemZ::InsnSS: |
| 8997 | case SystemZ::InsnSSd: { |
| 8998 | // op: enc |
| 8999 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9000 | Value |= (op & 0xff0000000000); |
| 9001 | // op: R1 |
| 9002 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9003 | Value |= (op & 0xf) << 36; |
| 9004 | // op: B1 |
| 9005 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9006 | Value |= (op & 0xf) << 28; |
| 9007 | // op: D1 |
| 9008 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 9009 | Value |= (op & 0xfff) << 16; |
| 9010 | // op: B2 |
| 9011 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9012 | Value |= (op & 0xf) << 12; |
| 9013 | // op: D2 |
| 9014 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 5, Fixups, STI); |
| 9015 | Value |= (op & 0xfff); |
| 9016 | // op: R3 |
| 9017 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 9018 | Value |= (op & 0xf) << 32; |
| 9019 | break; |
| 9020 | } |
| 9021 | case SystemZ::InsnSSF: { |
| 9022 | // op: enc |
| 9023 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9024 | Value |= (op & 0xff0000000000); |
| 9025 | Value |= (op & 0xf00000000); |
| 9026 | // op: B1 |
| 9027 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9028 | Value |= (op & 0xf) << 28; |
| 9029 | // op: D1 |
| 9030 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 9031 | Value |= (op & 0xfff) << 16; |
| 9032 | // op: B2 |
| 9033 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9034 | Value |= (op & 0xf) << 12; |
| 9035 | // op: D2 |
| 9036 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 9037 | Value |= (op & 0xfff); |
| 9038 | // op: R3 |
| 9039 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 9040 | Value |= (op & 0xf) << 36; |
| 9041 | break; |
| 9042 | } |
| 9043 | case SystemZ::InsnRILc: { |
| 9044 | // op: enc |
| 9045 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9046 | Value |= (op & 0xff0000000000); |
| 9047 | Value |= (op & 0xf00000000); |
| 9048 | // op: M1 |
| 9049 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 9050 | Value |= (op & 0xf) << 36; |
| 9051 | // op: RI2 |
| 9052 | op = getPC32DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 9053 | Value |= (op & 0xffffffff); |
| 9054 | break; |
| 9055 | } |
| 9056 | case SystemZ::InsnRILU: { |
| 9057 | // op: enc |
| 9058 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9059 | Value |= (op & 0xff0000000000); |
| 9060 | Value |= (op & 0xf00000000); |
| 9061 | // op: R1 |
| 9062 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9063 | Value |= (op & 0xf) << 36; |
| 9064 | // op: I2 |
| 9065 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, OpNum: 2, Fixups, STI); |
| 9066 | Value |= (op & 0xffffffff); |
| 9067 | break; |
| 9068 | } |
| 9069 | case SystemZ::InsnRILa: { |
| 9070 | // op: enc |
| 9071 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9072 | Value |= (op & 0xff0000000000); |
| 9073 | Value |= (op & 0xf00000000); |
| 9074 | // op: R1 |
| 9075 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9076 | Value |= (op & 0xf) << 36; |
| 9077 | // op: I2 |
| 9078 | op = getImmOpValue<SystemZ::FK_390_X32Imm>(MI, OpNum: 2, Fixups, STI); |
| 9079 | Value |= (op & 0xffffffff); |
| 9080 | break; |
| 9081 | } |
| 9082 | case SystemZ::InsnRIL: { |
| 9083 | // op: enc |
| 9084 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9085 | Value |= (op & 0xff0000000000); |
| 9086 | Value |= (op & 0xf00000000); |
| 9087 | // op: R1 |
| 9088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9089 | Value |= (op & 0xf) << 36; |
| 9090 | // op: I2 |
| 9091 | op = getPC32DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 9092 | Value |= (op & 0xffffffff); |
| 9093 | break; |
| 9094 | } |
| 9095 | case SystemZ::InsnRILb: { |
| 9096 | // op: enc |
| 9097 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9098 | Value |= (op & 0xff0000000000); |
| 9099 | Value |= (op & 0xf00000000); |
| 9100 | // op: R1 |
| 9101 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9102 | Value |= (op & 0xf) << 36; |
| 9103 | // op: RI2 |
| 9104 | op = getPC32DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 9105 | Value |= (op & 0xffffffff); |
| 9106 | break; |
| 9107 | } |
| 9108 | case SystemZ::InsnSIY: { |
| 9109 | // op: enc |
| 9110 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9111 | Value |= (op & 0xff0000000000); |
| 9112 | Value |= (op & 0xff); |
| 9113 | // op: B1 |
| 9114 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9115 | Value |= (op & 0xf) << 28; |
| 9116 | // op: D1 |
| 9117 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 2, Fixups, STI); |
| 9118 | Value |= (op & 0xfff) << 16; |
| 9119 | Value |= (op & 0xff000) >> 4; |
| 9120 | // op: I2 |
| 9121 | op = getImmOpValue<SystemZ::FK_390_X8Imm>(MI, OpNum: 3, Fixups, STI); |
| 9122 | Value |= (op & 0xff) << 32; |
| 9123 | break; |
| 9124 | } |
| 9125 | case SystemZ::InsnRSLa: { |
| 9126 | // op: enc |
| 9127 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9128 | Value |= (op & 0xff0000000000); |
| 9129 | Value |= (op & 0xff); |
| 9130 | // op: B1 |
| 9131 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9132 | Value |= (op & 0xf) << 28; |
| 9133 | // op: D1 |
| 9134 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 9135 | Value |= (op & 0xfff) << 16; |
| 9136 | // op: L1 |
| 9137 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9138 | Value |= (op & 0xf) << 36; |
| 9139 | break; |
| 9140 | } |
| 9141 | case SystemZ::InsnRXYb: { |
| 9142 | // op: enc |
| 9143 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9144 | Value |= (op & 0xff0000000000); |
| 9145 | Value |= (op & 0xff); |
| 9146 | // op: M1 |
| 9147 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 1, Fixups, STI); |
| 9148 | Value |= (op & 0xf) << 36; |
| 9149 | // op: X2 |
| 9150 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9151 | Value |= (op & 0xf) << 32; |
| 9152 | // op: B2 |
| 9153 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9154 | Value |= (op & 0xf) << 28; |
| 9155 | // op: D2 |
| 9156 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 9157 | Value |= (op & 0xfff) << 16; |
| 9158 | Value |= (op & 0xff000) >> 4; |
| 9159 | break; |
| 9160 | } |
| 9161 | case SystemZ::InsnRSLb: { |
| 9162 | // op: enc |
| 9163 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9164 | Value |= (op & 0xff0000000000); |
| 9165 | Value |= (op & 0xff); |
| 9166 | // op: R1 |
| 9167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9168 | Value |= (op & 0xf) << 12; |
| 9169 | // op: B2 |
| 9170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9171 | Value |= (op & 0xf) << 28; |
| 9172 | // op: D2 |
| 9173 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 9174 | Value |= (op & 0xfff) << 16; |
| 9175 | // op: L2 |
| 9176 | op = getLenEncoding<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 9177 | Value |= (op & 0xff) << 32; |
| 9178 | // op: M3 |
| 9179 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9180 | Value |= (op & 0xf) << 8; |
| 9181 | break; |
| 9182 | } |
| 9183 | case SystemZ::InsnRXF: { |
| 9184 | // op: enc |
| 9185 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9186 | Value |= (op & 0xff0000000000); |
| 9187 | Value |= (op & 0xff); |
| 9188 | // op: R1 |
| 9189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9190 | Value |= (op & 0xf) << 12; |
| 9191 | // op: R3 |
| 9192 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9193 | Value |= (op & 0xf) << 36; |
| 9194 | // op: X2 |
| 9195 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 9196 | Value |= (op & 0xf) << 32; |
| 9197 | // op: B2 |
| 9198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9199 | Value |= (op & 0xf) << 28; |
| 9200 | // op: D2 |
| 9201 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 9202 | Value |= (op & 0xfff) << 16; |
| 9203 | break; |
| 9204 | } |
| 9205 | case SystemZ::InsnVRSc: { |
| 9206 | // op: enc |
| 9207 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9208 | Value |= (op & 0xff0000000000); |
| 9209 | Value |= (op & 0xff); |
| 9210 | // op: R1 |
| 9211 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9212 | Value |= (op & 0xf) << 36; |
| 9213 | // op: B2 |
| 9214 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9215 | Value |= (op & 0xf) << 28; |
| 9216 | // op: D2 |
| 9217 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 9218 | Value |= (op & 0xfff) << 16; |
| 9219 | // op: V3 |
| 9220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9221 | Value |= (op & 0xf) << 32; |
| 9222 | Value |= (op & 0x10) << 6; |
| 9223 | // op: M4 |
| 9224 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9225 | Value |= (op & 0xf) << 12; |
| 9226 | break; |
| 9227 | } |
| 9228 | case SystemZ::InsnVRS: { |
| 9229 | // op: enc |
| 9230 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9231 | Value |= (op & 0xff0000000000); |
| 9232 | Value |= (op & 0xff); |
| 9233 | // op: R1 |
| 9234 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9235 | Value |= (op & 0xf) << 36; |
| 9236 | // op: B2 |
| 9237 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9238 | Value |= (op & 0xf) << 28; |
| 9239 | // op: D2 |
| 9240 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 9241 | Value |= (op & 0xfff) << 16; |
| 9242 | // op: V3 |
| 9243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9244 | Value |= (op & 0xf) << 32; |
| 9245 | Value |= (op & 0x10) << 6; |
| 9246 | // op: M4 |
| 9247 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9248 | Value |= (op & 0xf) << 12; |
| 9249 | break; |
| 9250 | } |
| 9251 | case SystemZ::InsnRIEa: { |
| 9252 | // op: enc |
| 9253 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9254 | Value |= (op & 0xff0000000000); |
| 9255 | Value |= (op & 0xff); |
| 9256 | // op: R1 |
| 9257 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9258 | Value |= (op & 0xf) << 36; |
| 9259 | // op: I2 |
| 9260 | op = getImmOpValue<SystemZ::FK_390_X16Imm>(MI, OpNum: 2, Fixups, STI); |
| 9261 | Value |= (op & 0xffff) << 16; |
| 9262 | // op: M3 |
| 9263 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9264 | Value |= (op & 0xf) << 12; |
| 9265 | break; |
| 9266 | } |
| 9267 | case SystemZ::InsnRIS: { |
| 9268 | // op: enc |
| 9269 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9270 | Value |= (op & 0xff0000000000); |
| 9271 | Value |= (op & 0xff); |
| 9272 | // op: R1 |
| 9273 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9274 | Value |= (op & 0xf) << 36; |
| 9275 | // op: I2 |
| 9276 | op = getImmOpValue<SystemZ::FK_390_X8Imm>(MI, OpNum: 2, Fixups, STI); |
| 9277 | Value |= (op & 0xff) << 8; |
| 9278 | // op: M3 |
| 9279 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9280 | Value |= (op & 0xf) << 32; |
| 9281 | // op: B4 |
| 9282 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9283 | Value |= (op & 0xf) << 28; |
| 9284 | // op: D4 |
| 9285 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 5, Fixups, STI); |
| 9286 | Value |= (op & 0xfff) << 16; |
| 9287 | break; |
| 9288 | } |
| 9289 | case SystemZ::InsnRIEc: { |
| 9290 | // op: enc |
| 9291 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9292 | Value |= (op & 0xff0000000000); |
| 9293 | Value |= (op & 0xff); |
| 9294 | // op: R1 |
| 9295 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9296 | Value |= (op & 0xf) << 36; |
| 9297 | // op: I2 |
| 9298 | op = getImmOpValue<SystemZ::FK_390_X8Imm>(MI, OpNum: 2, Fixups, STI); |
| 9299 | Value |= (op & 0xff) << 8; |
| 9300 | // op: M3 |
| 9301 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9302 | Value |= (op & 0xf) << 32; |
| 9303 | // op: RI4 |
| 9304 | op = getPC16DBLEncoding(MI, OpNum: 4, Fixups, STI); |
| 9305 | Value |= (op & 0xffff) << 16; |
| 9306 | break; |
| 9307 | } |
| 9308 | case SystemZ::InsnRIEg: { |
| 9309 | // op: enc |
| 9310 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9311 | Value |= (op & 0xff0000000000); |
| 9312 | Value |= (op & 0xff); |
| 9313 | // op: R1 |
| 9314 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9315 | Value |= (op & 0xf) << 36; |
| 9316 | // op: M3 |
| 9317 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9318 | Value |= (op & 0xf) << 32; |
| 9319 | // op: I2 |
| 9320 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 9321 | Value |= (op & 0xffff) << 16; |
| 9322 | break; |
| 9323 | } |
| 9324 | case SystemZ::InsnRSYb: { |
| 9325 | // op: enc |
| 9326 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9327 | Value |= (op & 0xff0000000000); |
| 9328 | Value |= (op & 0xff); |
| 9329 | // op: R1 |
| 9330 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9331 | Value |= (op & 0xf) << 36; |
| 9332 | // op: M3 |
| 9333 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 9334 | Value |= (op & 0xf) << 32; |
| 9335 | // op: B2 |
| 9336 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9337 | Value |= (op & 0xf) << 28; |
| 9338 | // op: D2 |
| 9339 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 9340 | Value |= (op & 0xfff) << 16; |
| 9341 | Value |= (op & 0xff000) >> 4; |
| 9342 | break; |
| 9343 | } |
| 9344 | case SystemZ::InsnRIEf: { |
| 9345 | // op: enc |
| 9346 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9347 | Value |= (op & 0xff0000000000); |
| 9348 | Value |= (op & 0xff); |
| 9349 | // op: R1 |
| 9350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9351 | Value |= (op & 0xf) << 36; |
| 9352 | // op: R2 |
| 9353 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9354 | Value |= (op & 0xf) << 32; |
| 9355 | // op: I3 |
| 9356 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 9357 | Value |= (op & 0xff) << 24; |
| 9358 | // op: I4 |
| 9359 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 9360 | Value |= (op & 0xff) << 16; |
| 9361 | // op: I5 |
| 9362 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 5, Fixups, STI); |
| 9363 | Value |= (op & 0xff) << 8; |
| 9364 | break; |
| 9365 | } |
| 9366 | case SystemZ::InsnRRS: { |
| 9367 | // op: enc |
| 9368 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9369 | Value |= (op & 0xff0000000000); |
| 9370 | Value |= (op & 0xff); |
| 9371 | // op: R1 |
| 9372 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9373 | Value |= (op & 0xf) << 36; |
| 9374 | // op: R2 |
| 9375 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9376 | Value |= (op & 0xf) << 32; |
| 9377 | // op: M3 |
| 9378 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9379 | Value |= (op & 0xf) << 12; |
| 9380 | // op: B4 |
| 9381 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9382 | Value |= (op & 0xf) << 28; |
| 9383 | // op: D4 |
| 9384 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 5, Fixups, STI); |
| 9385 | Value |= (op & 0xfff) << 16; |
| 9386 | break; |
| 9387 | } |
| 9388 | case SystemZ::InsnRIEb: { |
| 9389 | // op: enc |
| 9390 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9391 | Value |= (op & 0xff0000000000); |
| 9392 | Value |= (op & 0xff); |
| 9393 | // op: R1 |
| 9394 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9395 | Value |= (op & 0xf) << 36; |
| 9396 | // op: R2 |
| 9397 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9398 | Value |= (op & 0xf) << 32; |
| 9399 | // op: M3 |
| 9400 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9401 | Value |= (op & 0xf) << 12; |
| 9402 | // op: RI4 |
| 9403 | op = getPC16DBLEncoding(MI, OpNum: 4, Fixups, STI); |
| 9404 | Value |= (op & 0xffff) << 16; |
| 9405 | break; |
| 9406 | } |
| 9407 | case SystemZ::InsnRSY: { |
| 9408 | // op: enc |
| 9409 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9410 | Value |= (op & 0xff0000000000); |
| 9411 | Value |= (op & 0xff); |
| 9412 | // op: R1 |
| 9413 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9414 | Value |= (op & 0xf) << 36; |
| 9415 | // op: R3 |
| 9416 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9417 | Value |= (op & 0xf) << 32; |
| 9418 | // op: B2 |
| 9419 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9420 | Value |= (op & 0xf) << 28; |
| 9421 | // op: D2 |
| 9422 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 4, Fixups, STI); |
| 9423 | Value |= (op & 0xfff) << 16; |
| 9424 | Value |= (op & 0xff000) >> 4; |
| 9425 | break; |
| 9426 | } |
| 9427 | case SystemZ::InsnRSE: { |
| 9428 | // op: enc |
| 9429 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9430 | Value |= (op & 0xff0000000000); |
| 9431 | Value |= (op & 0xff); |
| 9432 | // op: R1 |
| 9433 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9434 | Value |= (op & 0xf) << 36; |
| 9435 | // op: R3 |
| 9436 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9437 | Value |= (op & 0xf) << 32; |
| 9438 | // op: B2 |
| 9439 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9440 | Value |= (op & 0xf) << 28; |
| 9441 | // op: D2 |
| 9442 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 9443 | Value |= (op & 0xfff) << 16; |
| 9444 | break; |
| 9445 | } |
| 9446 | case SystemZ::InsnRIE: { |
| 9447 | // op: enc |
| 9448 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9449 | Value |= (op & 0xff0000000000); |
| 9450 | Value |= (op & 0xff); |
| 9451 | // op: R1 |
| 9452 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9453 | Value |= (op & 0xf) << 36; |
| 9454 | // op: R3 |
| 9455 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9456 | Value |= (op & 0xf) << 32; |
| 9457 | // op: I2 |
| 9458 | op = getPC16DBLEncoding(MI, OpNum: 3, Fixups, STI); |
| 9459 | Value |= (op & 0xffff) << 16; |
| 9460 | break; |
| 9461 | } |
| 9462 | case SystemZ::InsnRIEd: { |
| 9463 | // op: enc |
| 9464 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9465 | Value |= (op & 0xff0000000000); |
| 9466 | Value |= (op & 0xff); |
| 9467 | // op: R1 |
| 9468 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9469 | Value |= (op & 0xf) << 36; |
| 9470 | // op: R3 |
| 9471 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9472 | Value |= (op & 0xf) << 32; |
| 9473 | // op: I2 |
| 9474 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, OpNum: 2, Fixups, STI); |
| 9475 | Value |= (op & 0xffff) << 16; |
| 9476 | break; |
| 9477 | } |
| 9478 | case SystemZ::InsnRIEe: { |
| 9479 | // op: enc |
| 9480 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9481 | Value |= (op & 0xff0000000000); |
| 9482 | Value |= (op & 0xff); |
| 9483 | // op: R1 |
| 9484 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9485 | Value |= (op & 0xf) << 36; |
| 9486 | // op: R3 |
| 9487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9488 | Value |= (op & 0xf) << 32; |
| 9489 | // op: RI2 |
| 9490 | op = getPC16DBLEncoding(MI, OpNum: 2, Fixups, STI); |
| 9491 | Value |= (op & 0xffff) << 16; |
| 9492 | break; |
| 9493 | } |
| 9494 | case SystemZ::InsnRSYa: { |
| 9495 | // op: enc |
| 9496 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9497 | Value |= (op & 0xff0000000000); |
| 9498 | Value |= (op & 0xff); |
| 9499 | // op: R1 |
| 9500 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9501 | Value |= (op & 0xf) << 36; |
| 9502 | // op: R3 |
| 9503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9504 | Value |= (op & 0xf) << 32; |
| 9505 | // op: B2 |
| 9506 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9507 | Value |= (op & 0xf) << 28; |
| 9508 | // op: D2 |
| 9509 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 9510 | Value |= (op & 0xfff) << 16; |
| 9511 | Value |= (op & 0xff000) >> 4; |
| 9512 | break; |
| 9513 | } |
| 9514 | case SystemZ::InsnVRRi: { |
| 9515 | // op: enc |
| 9516 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9517 | Value |= (op & 0xff0000000000); |
| 9518 | Value |= (op & 0xff); |
| 9519 | // op: R1 |
| 9520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9521 | Value |= (op & 0xf) << 36; |
| 9522 | // op: V2 |
| 9523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9524 | Value |= (op & 0xf) << 32; |
| 9525 | Value |= (op & 0x10) << 6; |
| 9526 | // op: M3 |
| 9527 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9528 | Value |= (op & 0xf) << 20; |
| 9529 | // op: M4 |
| 9530 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 9531 | Value |= (op & 0xf) << 16; |
| 9532 | break; |
| 9533 | } |
| 9534 | case SystemZ::InsnRXY: |
| 9535 | case SystemZ::InsnRXYa: |
| 9536 | case SystemZ::InsnRXYc: { |
| 9537 | // op: enc |
| 9538 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9539 | Value |= (op & 0xff0000000000); |
| 9540 | Value |= (op & 0xff); |
| 9541 | // op: R1 |
| 9542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9543 | Value |= (op & 0xf) << 36; |
| 9544 | // op: X2 |
| 9545 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9546 | Value |= (op & 0xf) << 32; |
| 9547 | // op: B2 |
| 9548 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9549 | Value |= (op & 0xf) << 28; |
| 9550 | // op: D2 |
| 9551 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, OpNum: 3, Fixups, STI); |
| 9552 | Value |= (op & 0xfff) << 16; |
| 9553 | Value |= (op & 0xff000) >> 4; |
| 9554 | break; |
| 9555 | } |
| 9556 | case SystemZ::InsnRXE: { |
| 9557 | // op: enc |
| 9558 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9559 | Value |= (op & 0xff0000000000); |
| 9560 | Value |= (op & 0xff); |
| 9561 | // op: R1 |
| 9562 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9563 | Value |= (op & 0xf) << 36; |
| 9564 | // op: X2 |
| 9565 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9566 | Value |= (op & 0xf) << 32; |
| 9567 | // op: B2 |
| 9568 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9569 | Value |= (op & 0xf) << 28; |
| 9570 | // op: D2 |
| 9571 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 9572 | Value |= (op & 0xfff) << 16; |
| 9573 | // op: M3 |
| 9574 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9575 | Value |= (op & 0xf) << 12; |
| 9576 | break; |
| 9577 | } |
| 9578 | case SystemZ::InsnVSI: { |
| 9579 | // op: enc |
| 9580 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9581 | Value |= (op & 0xff0000000000); |
| 9582 | Value |= (op & 0xff); |
| 9583 | // op: V1 |
| 9584 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9585 | Value |= (op & 0xf) << 12; |
| 9586 | Value |= (op & 0x10) << 4; |
| 9587 | // op: B2 |
| 9588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9589 | Value |= (op & 0xf) << 28; |
| 9590 | // op: D2 |
| 9591 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 9592 | Value |= (op & 0xfff) << 16; |
| 9593 | // op: I3 |
| 9594 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 9595 | Value |= (op & 0xff) << 32; |
| 9596 | break; |
| 9597 | } |
| 9598 | case SystemZ::InsnVRSd: { |
| 9599 | // op: enc |
| 9600 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9601 | Value |= (op & 0xff0000000000); |
| 9602 | Value |= (op & 0xff); |
| 9603 | // op: V1 |
| 9604 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9605 | Value |= (op & 0xf) << 12; |
| 9606 | Value |= (op & 0x10) << 4; |
| 9607 | // op: B2 |
| 9608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9609 | Value |= (op & 0xf) << 28; |
| 9610 | // op: D2 |
| 9611 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 9612 | Value |= (op & 0xfff) << 16; |
| 9613 | // op: R3 |
| 9614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9615 | Value |= (op & 0xf) << 32; |
| 9616 | break; |
| 9617 | } |
| 9618 | case SystemZ::InsnVRRg: { |
| 9619 | // op: enc |
| 9620 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9621 | Value |= (op & 0xff0000000000); |
| 9622 | Value |= (op & 0xff); |
| 9623 | // op: V1 |
| 9624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9625 | Value |= (op & 0xf) << 32; |
| 9626 | Value |= (op & 0x10) << 6; |
| 9627 | // op: I2 |
| 9628 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 2, Fixups, STI); |
| 9629 | Value |= (op & 0xffff) << 12; |
| 9630 | break; |
| 9631 | } |
| 9632 | case SystemZ::InsnVRIl: { |
| 9633 | // op: enc |
| 9634 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9635 | Value |= (op & 0xff0000000000); |
| 9636 | Value |= (op & 0xff); |
| 9637 | // op: V1 |
| 9638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9639 | Value |= (op & 0xf) << 32; |
| 9640 | Value |= (op & 0x10) << 6; |
| 9641 | // op: V2 |
| 9642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9643 | Value |= (op & 0xf) << 28; |
| 9644 | Value |= (op & 0x10) << 5; |
| 9645 | // op: I3 |
| 9646 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 3, Fixups, STI); |
| 9647 | Value |= (op & 0xffff) << 12; |
| 9648 | break; |
| 9649 | } |
| 9650 | case SystemZ::InsnVRRh: { |
| 9651 | // op: enc |
| 9652 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9653 | Value |= (op & 0xff0000000000); |
| 9654 | Value |= (op & 0xff); |
| 9655 | // op: V1 |
| 9656 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9657 | Value |= (op & 0xf) << 32; |
| 9658 | Value |= (op & 0x10) << 6; |
| 9659 | // op: V2 |
| 9660 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9661 | Value |= (op & 0xf) << 28; |
| 9662 | Value |= (op & 0x10) << 5; |
| 9663 | // op: M3 |
| 9664 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9665 | Value |= (op & 0xf) << 20; |
| 9666 | break; |
| 9667 | } |
| 9668 | case SystemZ::InsnVRSb: { |
| 9669 | // op: enc |
| 9670 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9671 | Value |= (op & 0xff0000000000); |
| 9672 | Value |= (op & 0xff); |
| 9673 | // op: V1 |
| 9674 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9675 | Value |= (op & 0xf) << 36; |
| 9676 | Value |= (op & 0x10) << 7; |
| 9677 | // op: B2 |
| 9678 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9679 | Value |= (op & 0xf) << 28; |
| 9680 | // op: D2 |
| 9681 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 9682 | Value |= (op & 0xfff) << 16; |
| 9683 | // op: R3 |
| 9684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9685 | Value |= (op & 0xf) << 32; |
| 9686 | // op: M4 |
| 9687 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9688 | Value |= (op & 0xf) << 12; |
| 9689 | break; |
| 9690 | } |
| 9691 | case SystemZ::InsnVRSa: { |
| 9692 | // op: enc |
| 9693 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9694 | Value |= (op & 0xff0000000000); |
| 9695 | Value |= (op & 0xff); |
| 9696 | // op: V1 |
| 9697 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9698 | Value |= (op & 0xf) << 36; |
| 9699 | Value |= (op & 0x10) << 7; |
| 9700 | // op: B2 |
| 9701 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9702 | Value |= (op & 0xf) << 28; |
| 9703 | // op: D2 |
| 9704 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 9705 | Value |= (op & 0xfff) << 16; |
| 9706 | // op: V3 |
| 9707 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9708 | Value |= (op & 0xf) << 32; |
| 9709 | Value |= (op & 0x10) << 6; |
| 9710 | // op: M4 |
| 9711 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9712 | Value |= (op & 0xf) << 12; |
| 9713 | break; |
| 9714 | } |
| 9715 | case SystemZ::InsnVRIh: { |
| 9716 | // op: enc |
| 9717 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9718 | Value |= (op & 0xff0000000000); |
| 9719 | Value |= (op & 0xff); |
| 9720 | // op: V1 |
| 9721 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9722 | Value |= (op & 0xf) << 36; |
| 9723 | Value |= (op & 0x10) << 7; |
| 9724 | // op: I2 |
| 9725 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 2, Fixups, STI); |
| 9726 | Value |= (op & 0xffff) << 16; |
| 9727 | // op: I3 |
| 9728 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9729 | Value |= (op & 0xf) << 12; |
| 9730 | break; |
| 9731 | } |
| 9732 | case SystemZ::InsnVRIb: { |
| 9733 | // op: enc |
| 9734 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9735 | Value |= (op & 0xff0000000000); |
| 9736 | Value |= (op & 0xff); |
| 9737 | // op: V1 |
| 9738 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9739 | Value |= (op & 0xf) << 36; |
| 9740 | Value |= (op & 0x10) << 7; |
| 9741 | // op: I2 |
| 9742 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 2, Fixups, STI); |
| 9743 | Value |= (op & 0xff) << 24; |
| 9744 | // op: I3 |
| 9745 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 9746 | Value |= (op & 0xff) << 16; |
| 9747 | // op: M4 |
| 9748 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 9749 | Value |= (op & 0xf) << 12; |
| 9750 | break; |
| 9751 | } |
| 9752 | case SystemZ::InsnVRIa: { |
| 9753 | // op: enc |
| 9754 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9755 | Value |= (op & 0xff0000000000); |
| 9756 | Value |= (op & 0xff); |
| 9757 | // op: V1 |
| 9758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9759 | Value |= (op & 0xf) << 36; |
| 9760 | Value |= (op & 0x10) << 7; |
| 9761 | // op: I2 |
| 9762 | op = getImmOpValue<SystemZ::FK_390_X16Imm>(MI, OpNum: 2, Fixups, STI); |
| 9763 | Value |= (op & 0xffff) << 16; |
| 9764 | // op: M3 |
| 9765 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9766 | Value |= (op & 0xf) << 12; |
| 9767 | break; |
| 9768 | } |
| 9769 | case SystemZ::InsnVRIi: { |
| 9770 | // op: enc |
| 9771 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9772 | Value |= (op & 0xff0000000000); |
| 9773 | Value |= (op & 0xff); |
| 9774 | // op: V1 |
| 9775 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9776 | Value |= (op & 0xf) << 36; |
| 9777 | Value |= (op & 0x10) << 7; |
| 9778 | // op: R2 |
| 9779 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9780 | Value |= (op & 0xf) << 32; |
| 9781 | // op: I3 |
| 9782 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 9783 | Value |= (op & 0xff) << 12; |
| 9784 | // op: M4 |
| 9785 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 9786 | Value |= (op & 0xf) << 20; |
| 9787 | break; |
| 9788 | } |
| 9789 | case SystemZ::InsnVRRf: { |
| 9790 | // op: enc |
| 9791 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9792 | Value |= (op & 0xff0000000000); |
| 9793 | Value |= (op & 0xff); |
| 9794 | // op: V1 |
| 9795 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9796 | Value |= (op & 0xf) << 36; |
| 9797 | Value |= (op & 0x10) << 7; |
| 9798 | // op: R2 |
| 9799 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9800 | Value |= (op & 0xf) << 32; |
| 9801 | // op: R3 |
| 9802 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9803 | Value |= (op & 0xf) << 28; |
| 9804 | break; |
| 9805 | } |
| 9806 | case SystemZ::InsnVRI: |
| 9807 | case SystemZ::InsnVRIe: { |
| 9808 | // op: enc |
| 9809 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9810 | Value |= (op & 0xff0000000000); |
| 9811 | Value |= (op & 0xff); |
| 9812 | // op: V1 |
| 9813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9814 | Value |= (op & 0xf) << 36; |
| 9815 | Value |= (op & 0x10) << 7; |
| 9816 | // op: V2 |
| 9817 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9818 | Value |= (op & 0xf) << 32; |
| 9819 | Value |= (op & 0x10) << 6; |
| 9820 | // op: I3 |
| 9821 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 9822 | Value |= (op & 0xfff) << 20; |
| 9823 | // op: M4 |
| 9824 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 9825 | Value |= (op & 0xf) << 12; |
| 9826 | // op: M5 |
| 9827 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9828 | Value |= (op & 0xf) << 16; |
| 9829 | break; |
| 9830 | } |
| 9831 | case SystemZ::InsnVRIg: { |
| 9832 | // op: enc |
| 9833 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9834 | Value |= (op & 0xff0000000000); |
| 9835 | Value |= (op & 0xff); |
| 9836 | // op: V1 |
| 9837 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9838 | Value |= (op & 0xf) << 36; |
| 9839 | Value |= (op & 0x10) << 7; |
| 9840 | // op: V2 |
| 9841 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9842 | Value |= (op & 0xf) << 32; |
| 9843 | Value |= (op & 0x10) << 6; |
| 9844 | // op: I3 |
| 9845 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 9846 | Value |= (op & 0xff) << 12; |
| 9847 | // op: I4 |
| 9848 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 9849 | Value |= (op & 0xff) << 24; |
| 9850 | // op: M5 |
| 9851 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9852 | Value |= (op & 0xf) << 20; |
| 9853 | break; |
| 9854 | } |
| 9855 | case SystemZ::InsnVRIj: { |
| 9856 | // op: enc |
| 9857 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9858 | Value |= (op & 0xff0000000000); |
| 9859 | Value |= (op & 0xff); |
| 9860 | // op: V1 |
| 9861 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9862 | Value |= (op & 0xf) << 36; |
| 9863 | Value |= (op & 0x10) << 7; |
| 9864 | // op: V2 |
| 9865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9866 | Value |= (op & 0xf) << 32; |
| 9867 | Value |= (op & 0x10) << 6; |
| 9868 | // op: I3 |
| 9869 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 3, Fixups, STI); |
| 9870 | Value |= (op & 0xff) << 12; |
| 9871 | // op: M4 |
| 9872 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 9873 | Value |= (op & 0xf) << 20; |
| 9874 | break; |
| 9875 | } |
| 9876 | case SystemZ::InsnVRRa: { |
| 9877 | // op: enc |
| 9878 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9879 | Value |= (op & 0xff0000000000); |
| 9880 | Value |= (op & 0xff); |
| 9881 | // op: V1 |
| 9882 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9883 | Value |= (op & 0xf) << 36; |
| 9884 | Value |= (op & 0x10) << 7; |
| 9885 | // op: V2 |
| 9886 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9887 | Value |= (op & 0xf) << 32; |
| 9888 | Value |= (op & 0x10) << 6; |
| 9889 | // op: M3 |
| 9890 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9891 | Value |= (op & 0xf) << 12; |
| 9892 | // op: M4 |
| 9893 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 9894 | Value |= (op & 0xf) << 16; |
| 9895 | // op: M5 |
| 9896 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9897 | Value |= (op & 0xf) << 20; |
| 9898 | break; |
| 9899 | } |
| 9900 | case SystemZ::InsnVRRk: { |
| 9901 | // op: enc |
| 9902 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9903 | Value |= (op & 0xff0000000000); |
| 9904 | Value |= (op & 0xff); |
| 9905 | // op: V1 |
| 9906 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9907 | Value |= (op & 0xf) << 36; |
| 9908 | Value |= (op & 0x10) << 7; |
| 9909 | // op: V2 |
| 9910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9911 | Value |= (op & 0xf) << 32; |
| 9912 | Value |= (op & 0x10) << 6; |
| 9913 | // op: M3 |
| 9914 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 3, Fixups, STI); |
| 9915 | Value |= (op & 0xf) << 20; |
| 9916 | break; |
| 9917 | } |
| 9918 | case SystemZ::InsnVRIf: { |
| 9919 | // op: enc |
| 9920 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9921 | Value |= (op & 0xff0000000000); |
| 9922 | Value |= (op & 0xff); |
| 9923 | // op: V1 |
| 9924 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9925 | Value |= (op & 0xf) << 36; |
| 9926 | Value |= (op & 0x10) << 7; |
| 9927 | // op: V2 |
| 9928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9929 | Value |= (op & 0xf) << 32; |
| 9930 | Value |= (op & 0x10) << 6; |
| 9931 | // op: V3 |
| 9932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9933 | Value |= (op & 0xf) << 28; |
| 9934 | Value |= (op & 0x10) << 5; |
| 9935 | // op: I4 |
| 9936 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 9937 | Value |= (op & 0xff) << 12; |
| 9938 | // op: M5 |
| 9939 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9940 | Value |= (op & 0xf) << 20; |
| 9941 | break; |
| 9942 | } |
| 9943 | case SystemZ::InsnVRId: { |
| 9944 | // op: enc |
| 9945 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9946 | Value |= (op & 0xff0000000000); |
| 9947 | Value |= (op & 0xff); |
| 9948 | // op: V1 |
| 9949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9950 | Value |= (op & 0xf) << 36; |
| 9951 | Value |= (op & 0x10) << 7; |
| 9952 | // op: V2 |
| 9953 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9954 | Value |= (op & 0xf) << 32; |
| 9955 | Value |= (op & 0x10) << 6; |
| 9956 | // op: V3 |
| 9957 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9958 | Value |= (op & 0xf) << 28; |
| 9959 | Value |= (op & 0x10) << 5; |
| 9960 | // op: I4 |
| 9961 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 4, Fixups, STI); |
| 9962 | Value |= (op & 0xff) << 16; |
| 9963 | // op: M5 |
| 9964 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9965 | Value |= (op & 0xf) << 12; |
| 9966 | break; |
| 9967 | } |
| 9968 | case SystemZ::InsnVRR: |
| 9969 | case SystemZ::InsnVRRc: { |
| 9970 | // op: enc |
| 9971 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 9972 | Value |= (op & 0xff0000000000); |
| 9973 | Value |= (op & 0xff); |
| 9974 | // op: V1 |
| 9975 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9976 | Value |= (op & 0xf) << 36; |
| 9977 | Value |= (op & 0x10) << 7; |
| 9978 | // op: V2 |
| 9979 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9980 | Value |= (op & 0xf) << 32; |
| 9981 | Value |= (op & 0x10) << 6; |
| 9982 | // op: V3 |
| 9983 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9984 | Value |= (op & 0xf) << 28; |
| 9985 | Value |= (op & 0x10) << 5; |
| 9986 | // op: M4 |
| 9987 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 9988 | Value |= (op & 0xf) << 12; |
| 9989 | // op: M5 |
| 9990 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 9991 | Value |= (op & 0xf) << 16; |
| 9992 | // op: M6 |
| 9993 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 6, Fixups, STI); |
| 9994 | Value |= (op & 0xf) << 20; |
| 9995 | break; |
| 9996 | } |
| 9997 | case SystemZ::InsnVRRb: { |
| 9998 | // op: enc |
| 9999 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10000 | Value |= (op & 0xff0000000000); |
| 10001 | Value |= (op & 0xff); |
| 10002 | // op: V1 |
| 10003 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10004 | Value |= (op & 0xf) << 36; |
| 10005 | Value |= (op & 0x10) << 7; |
| 10006 | // op: V2 |
| 10007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10008 | Value |= (op & 0xf) << 32; |
| 10009 | Value |= (op & 0x10) << 6; |
| 10010 | // op: V3 |
| 10011 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10012 | Value |= (op & 0xf) << 28; |
| 10013 | Value |= (op & 0x10) << 5; |
| 10014 | // op: M4 |
| 10015 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 10016 | Value |= (op & 0xf) << 12; |
| 10017 | // op: M5 |
| 10018 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 10019 | Value |= (op & 0xf) << 20; |
| 10020 | break; |
| 10021 | } |
| 10022 | case SystemZ::InsnVRRj: { |
| 10023 | // op: enc |
| 10024 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10025 | Value |= (op & 0xff0000000000); |
| 10026 | Value |= (op & 0xff); |
| 10027 | // op: V1 |
| 10028 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10029 | Value |= (op & 0xf) << 36; |
| 10030 | Value |= (op & 0x10) << 7; |
| 10031 | // op: V2 |
| 10032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10033 | Value |= (op & 0xf) << 32; |
| 10034 | Value |= (op & 0x10) << 6; |
| 10035 | // op: V3 |
| 10036 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10037 | Value |= (op & 0xf) << 28; |
| 10038 | Value |= (op & 0x10) << 5; |
| 10039 | // op: M4 |
| 10040 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 10041 | Value |= (op & 0xf) << 20; |
| 10042 | break; |
| 10043 | } |
| 10044 | case SystemZ::InsnVRIk: { |
| 10045 | // op: enc |
| 10046 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10047 | Value |= (op & 0xff0000000000); |
| 10048 | Value |= (op & 0xff); |
| 10049 | // op: V1 |
| 10050 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10051 | Value |= (op & 0xf) << 36; |
| 10052 | Value |= (op & 0x10) << 7; |
| 10053 | // op: V2 |
| 10054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10055 | Value |= (op & 0xf) << 32; |
| 10056 | Value |= (op & 0x10) << 6; |
| 10057 | // op: V3 |
| 10058 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10059 | Value |= (op & 0xf) << 28; |
| 10060 | Value |= (op & 0x10) << 5; |
| 10061 | // op: V4 |
| 10062 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10063 | Value |= (op & 0xf) << 12; |
| 10064 | Value |= (op & 0x10) << 4; |
| 10065 | // op: I5 |
| 10066 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, OpNum: 5, Fixups, STI); |
| 10067 | Value |= (op & 0xff) << 16; |
| 10068 | break; |
| 10069 | } |
| 10070 | case SystemZ::InsnVRRe: { |
| 10071 | // op: enc |
| 10072 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10073 | Value |= (op & 0xff0000000000); |
| 10074 | Value |= (op & 0xff); |
| 10075 | // op: V1 |
| 10076 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10077 | Value |= (op & 0xf) << 36; |
| 10078 | Value |= (op & 0x10) << 7; |
| 10079 | // op: V2 |
| 10080 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10081 | Value |= (op & 0xf) << 32; |
| 10082 | Value |= (op & 0x10) << 6; |
| 10083 | // op: V3 |
| 10084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10085 | Value |= (op & 0xf) << 28; |
| 10086 | Value |= (op & 0x10) << 5; |
| 10087 | // op: V4 |
| 10088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10089 | Value |= (op & 0xf) << 12; |
| 10090 | Value |= (op & 0x10) << 4; |
| 10091 | // op: M5 |
| 10092 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 10093 | Value |= (op & 0xf) << 16; |
| 10094 | // op: M6 |
| 10095 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 6, Fixups, STI); |
| 10096 | Value |= (op & 0xf) << 24; |
| 10097 | break; |
| 10098 | } |
| 10099 | case SystemZ::InsnVRRd: { |
| 10100 | // op: enc |
| 10101 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10102 | Value |= (op & 0xff0000000000); |
| 10103 | Value |= (op & 0xff); |
| 10104 | // op: V1 |
| 10105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10106 | Value |= (op & 0xf) << 36; |
| 10107 | Value |= (op & 0x10) << 7; |
| 10108 | // op: V2 |
| 10109 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10110 | Value |= (op & 0xf) << 32; |
| 10111 | Value |= (op & 0x10) << 6; |
| 10112 | // op: V3 |
| 10113 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10114 | Value |= (op & 0xf) << 28; |
| 10115 | Value |= (op & 0x10) << 5; |
| 10116 | // op: V4 |
| 10117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10118 | Value |= (op & 0xf) << 12; |
| 10119 | Value |= (op & 0x10) << 4; |
| 10120 | // op: M5 |
| 10121 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 10122 | Value |= (op & 0xf) << 24; |
| 10123 | // op: M6 |
| 10124 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 6, Fixups, STI); |
| 10125 | Value |= (op & 0xf) << 20; |
| 10126 | break; |
| 10127 | } |
| 10128 | case SystemZ::InsnVRV: { |
| 10129 | // op: enc |
| 10130 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10131 | Value |= (op & 0xff0000000000); |
| 10132 | Value |= (op & 0xff); |
| 10133 | // op: V1 |
| 10134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10135 | Value |= (op & 0xf) << 36; |
| 10136 | Value |= (op & 0x10) << 7; |
| 10137 | // op: V2 |
| 10138 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10139 | Value |= (op & 0xf) << 32; |
| 10140 | Value |= (op & 0x10) << 6; |
| 10141 | // op: B2 |
| 10142 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10143 | Value |= (op & 0xf) << 28; |
| 10144 | // op: D2 |
| 10145 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 10146 | Value |= (op & 0xfff) << 16; |
| 10147 | // op: M3 |
| 10148 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 10149 | Value |= (op & 0xf) << 12; |
| 10150 | break; |
| 10151 | } |
| 10152 | case SystemZ::InsnVRIc: { |
| 10153 | // op: enc |
| 10154 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10155 | Value |= (op & 0xff0000000000); |
| 10156 | Value |= (op & 0xff); |
| 10157 | // op: V1 |
| 10158 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10159 | Value |= (op & 0xf) << 36; |
| 10160 | Value |= (op & 0x10) << 7; |
| 10161 | // op: V3 |
| 10162 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10163 | Value |= (op & 0xf) << 32; |
| 10164 | Value |= (op & 0x10) << 6; |
| 10165 | // op: I2 |
| 10166 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, OpNum: 2, Fixups, STI); |
| 10167 | Value |= (op & 0xffff) << 16; |
| 10168 | // op: M4 |
| 10169 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 4, Fixups, STI); |
| 10170 | Value |= (op & 0xf) << 12; |
| 10171 | break; |
| 10172 | } |
| 10173 | case SystemZ::InsnVRX: { |
| 10174 | // op: enc |
| 10175 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10176 | Value |= (op & 0xff0000000000); |
| 10177 | Value |= (op & 0xff); |
| 10178 | // op: V1 |
| 10179 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10180 | Value |= (op & 0xf) << 36; |
| 10181 | Value |= (op & 0x10) << 7; |
| 10182 | // op: X2 |
| 10183 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 10184 | Value |= (op & 0xf) << 32; |
| 10185 | // op: B2 |
| 10186 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 10187 | Value |= (op & 0xf) << 28; |
| 10188 | // op: D2 |
| 10189 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 3, Fixups, STI); |
| 10190 | Value |= (op & 0xfff) << 16; |
| 10191 | // op: M3 |
| 10192 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, OpNum: 5, Fixups, STI); |
| 10193 | Value |= (op & 0xf) << 12; |
| 10194 | break; |
| 10195 | } |
| 10196 | case SystemZ::InsnSSE: { |
| 10197 | // op: enc |
| 10198 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10199 | Value |= (op & 0xffff00000000); |
| 10200 | // op: B1 |
| 10201 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10202 | Value |= (op & 0xf) << 28; |
| 10203 | // op: D1 |
| 10204 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 10205 | Value |= (op & 0xfff) << 16; |
| 10206 | // op: B2 |
| 10207 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 10208 | Value |= (op & 0xf) << 12; |
| 10209 | // op: D2 |
| 10210 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 4, Fixups, STI); |
| 10211 | Value |= (op & 0xfff); |
| 10212 | break; |
| 10213 | } |
| 10214 | case SystemZ::InsnSIL: { |
| 10215 | // op: enc |
| 10216 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, OpNum: 0, Fixups, STI); |
| 10217 | Value |= (op & 0xffff00000000); |
| 10218 | // op: B1 |
| 10219 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10220 | Value |= (op & 0xf) << 28; |
| 10221 | // op: D1 |
| 10222 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, OpNum: 2, Fixups, STI); |
| 10223 | Value |= (op & 0xfff) << 16; |
| 10224 | // op: I2 |
| 10225 | op = getImmOpValue<SystemZ::FK_390_X16Imm>(MI, OpNum: 3, Fixups, STI); |
| 10226 | Value |= (op & 0xffff); |
| 10227 | break; |
| 10228 | } |
| 10229 | default: |
| 10230 | reportUnsupportedInst(Inst: MI); |
| 10231 | } |
| 10232 | return Value; |
| 10233 | } |
| 10234 | |
| 10235 | #ifdef GET_OPERAND_BIT_OFFSET |
| 10236 | #undef GET_OPERAND_BIT_OFFSET |
| 10237 | |
| 10238 | uint32_t SystemZMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
| 10239 | unsigned OpNum, |
| 10240 | const MCSubtargetInfo &STI) const { |
| 10241 | switch (MI.getOpcode()) { |
| 10242 | case SystemZ::CSCH: |
| 10243 | case SystemZ::HSCH: |
| 10244 | case SystemZ::IPK: |
| 10245 | case SystemZ::NNPA: |
| 10246 | case SystemZ::NOPOpt: |
| 10247 | case SystemZ::NOPROpt: |
| 10248 | case SystemZ::PALB: |
| 10249 | case SystemZ::PCC: |
| 10250 | case SystemZ::PCKMO: |
| 10251 | case SystemZ::PFPO: |
| 10252 | case SystemZ::PR: |
| 10253 | case SystemZ::PTFF: |
| 10254 | case SystemZ::PTLB: |
| 10255 | case SystemZ::RCHP: |
| 10256 | case SystemZ::RSCH: |
| 10257 | case SystemZ::SAL: |
| 10258 | case SystemZ::SAM24: |
| 10259 | case SystemZ::SAM31: |
| 10260 | case SystemZ::SAM64: |
| 10261 | case SystemZ::SCHM: |
| 10262 | case SystemZ::SCKPF: |
| 10263 | case SystemZ::TAM: |
| 10264 | case SystemZ::TEND: |
| 10265 | case SystemZ::TRAP2: |
| 10266 | case SystemZ::UPT: |
| 10267 | case SystemZ::XSCH: { |
| 10268 | break; |
| 10269 | } |
| 10270 | case SystemZ::CLI: |
| 10271 | case SystemZ::MC: |
| 10272 | case SystemZ::MVI: |
| 10273 | case SystemZ::NI: |
| 10274 | case SystemZ::OI: |
| 10275 | case SystemZ::STNSM: |
| 10276 | case SystemZ::STOSM: |
| 10277 | case SystemZ::TM: |
| 10278 | case SystemZ::XI: { |
| 10279 | switch (OpNum) { |
| 10280 | case 0: |
| 10281 | // op: B1 |
| 10282 | return 12; |
| 10283 | case 1: |
| 10284 | // op: D1 |
| 10285 | return 0; |
| 10286 | case 2: |
| 10287 | // op: I2 |
| 10288 | return 16; |
| 10289 | } |
| 10290 | break; |
| 10291 | } |
| 10292 | case SystemZ::PKA: |
| 10293 | case SystemZ::PKU: { |
| 10294 | switch (OpNum) { |
| 10295 | case 0: |
| 10296 | // op: B1 |
| 10297 | return 28; |
| 10298 | case 1: |
| 10299 | // op: D1 |
| 10300 | return 16; |
| 10301 | case 2: |
| 10302 | // op: B2 |
| 10303 | return 12; |
| 10304 | case 3: |
| 10305 | // op: D2 |
| 10306 | return 0; |
| 10307 | case 4: |
| 10308 | // op: L2 |
| 10309 | return 32; |
| 10310 | } |
| 10311 | break; |
| 10312 | } |
| 10313 | case SystemZ::CSST: |
| 10314 | case SystemZ::ECTG: |
| 10315 | case SystemZ::MVCOS: { |
| 10316 | switch (OpNum) { |
| 10317 | case 0: |
| 10318 | // op: B1 |
| 10319 | return 28; |
| 10320 | case 1: |
| 10321 | // op: D1 |
| 10322 | return 16; |
| 10323 | case 2: |
| 10324 | // op: B2 |
| 10325 | return 12; |
| 10326 | case 3: |
| 10327 | // op: D2 |
| 10328 | return 0; |
| 10329 | case 4: |
| 10330 | // op: R3 |
| 10331 | return 36; |
| 10332 | } |
| 10333 | break; |
| 10334 | } |
| 10335 | case SystemZ::LASP: |
| 10336 | case SystemZ::MVCDK: |
| 10337 | case SystemZ::MVCRL: |
| 10338 | case SystemZ::MVCSK: |
| 10339 | case SystemZ::STRAG: |
| 10340 | case SystemZ::TPROT: { |
| 10341 | switch (OpNum) { |
| 10342 | case 0: |
| 10343 | // op: B1 |
| 10344 | return 28; |
| 10345 | case 1: |
| 10346 | // op: D1 |
| 10347 | return 16; |
| 10348 | case 2: |
| 10349 | // op: B2 |
| 10350 | return 12; |
| 10351 | case 3: |
| 10352 | // op: D2 |
| 10353 | return 0; |
| 10354 | } |
| 10355 | break; |
| 10356 | } |
| 10357 | case SystemZ::CGHSI: |
| 10358 | case SystemZ::CHHSI: |
| 10359 | case SystemZ::CHSI: |
| 10360 | case SystemZ::CLFHSI: |
| 10361 | case SystemZ::CLGHSI: |
| 10362 | case SystemZ::CLHHSI: |
| 10363 | case SystemZ::MVGHI: |
| 10364 | case SystemZ::MVHHI: |
| 10365 | case SystemZ::MVHI: |
| 10366 | case SystemZ::TBEGIN: |
| 10367 | case SystemZ::TBEGINC: { |
| 10368 | switch (OpNum) { |
| 10369 | case 0: |
| 10370 | // op: B1 |
| 10371 | return 28; |
| 10372 | case 1: |
| 10373 | // op: D1 |
| 10374 | return 16; |
| 10375 | case 2: |
| 10376 | // op: I2 |
| 10377 | return 0; |
| 10378 | } |
| 10379 | break; |
| 10380 | } |
| 10381 | case SystemZ::CLC: |
| 10382 | case SystemZ::ED: |
| 10383 | case SystemZ::EDMK: |
| 10384 | case SystemZ::MVC: |
| 10385 | case SystemZ::MVCIN: |
| 10386 | case SystemZ::MVN: |
| 10387 | case SystemZ::MVZ: |
| 10388 | case SystemZ::NC: |
| 10389 | case SystemZ::OC: |
| 10390 | case SystemZ::TR: |
| 10391 | case SystemZ::TRT: |
| 10392 | case SystemZ::TRTR: |
| 10393 | case SystemZ::UNPKA: |
| 10394 | case SystemZ::UNPKU: |
| 10395 | case SystemZ::XC: { |
| 10396 | switch (OpNum) { |
| 10397 | case 0: |
| 10398 | // op: B1 |
| 10399 | return 28; |
| 10400 | case 1: |
| 10401 | // op: D1 |
| 10402 | return 16; |
| 10403 | case 2: |
| 10404 | // op: L1 |
| 10405 | return 32; |
| 10406 | case 3: |
| 10407 | // op: B2 |
| 10408 | return 12; |
| 10409 | case 4: |
| 10410 | // op: D2 |
| 10411 | return 0; |
| 10412 | } |
| 10413 | break; |
| 10414 | } |
| 10415 | case SystemZ::SRP: { |
| 10416 | switch (OpNum) { |
| 10417 | case 0: |
| 10418 | // op: B1 |
| 10419 | return 28; |
| 10420 | case 1: |
| 10421 | // op: D1 |
| 10422 | return 16; |
| 10423 | case 2: |
| 10424 | // op: L1 |
| 10425 | return 36; |
| 10426 | case 3: |
| 10427 | // op: B2 |
| 10428 | return 12; |
| 10429 | case 4: |
| 10430 | // op: D2 |
| 10431 | return 0; |
| 10432 | case 5: |
| 10433 | // op: I3 |
| 10434 | return 32; |
| 10435 | } |
| 10436 | break; |
| 10437 | } |
| 10438 | case SystemZ::AP: |
| 10439 | case SystemZ::CP: |
| 10440 | case SystemZ::DP: |
| 10441 | case SystemZ::MP: |
| 10442 | case SystemZ::MVO: |
| 10443 | case SystemZ::PACK: |
| 10444 | case SystemZ::SP: |
| 10445 | case SystemZ::UNPK: |
| 10446 | case SystemZ::ZAP: { |
| 10447 | switch (OpNum) { |
| 10448 | case 0: |
| 10449 | // op: B1 |
| 10450 | return 28; |
| 10451 | case 1: |
| 10452 | // op: D1 |
| 10453 | return 16; |
| 10454 | case 2: |
| 10455 | // op: L1 |
| 10456 | return 36; |
| 10457 | case 3: |
| 10458 | // op: B2 |
| 10459 | return 12; |
| 10460 | case 4: |
| 10461 | // op: D2 |
| 10462 | return 0; |
| 10463 | case 5: |
| 10464 | // op: L2 |
| 10465 | return 32; |
| 10466 | } |
| 10467 | break; |
| 10468 | } |
| 10469 | case SystemZ::TP: { |
| 10470 | switch (OpNum) { |
| 10471 | case 0: |
| 10472 | // op: B1 |
| 10473 | return 28; |
| 10474 | case 1: |
| 10475 | // op: D1 |
| 10476 | return 16; |
| 10477 | case 2: |
| 10478 | // op: L1 |
| 10479 | return 36; |
| 10480 | } |
| 10481 | break; |
| 10482 | } |
| 10483 | case SystemZ::AGSI: |
| 10484 | case SystemZ::ALGSI: |
| 10485 | case SystemZ::ALSI: |
| 10486 | case SystemZ::ASI: |
| 10487 | case SystemZ::CLIY: |
| 10488 | case SystemZ::MVIY: |
| 10489 | case SystemZ::NIY: |
| 10490 | case SystemZ::OIY: |
| 10491 | case SystemZ::TMY: |
| 10492 | case SystemZ::XIY: { |
| 10493 | switch (OpNum) { |
| 10494 | case 0: |
| 10495 | // op: B1 |
| 10496 | return 28; |
| 10497 | case 1: |
| 10498 | // op: D1 |
| 10499 | return 8; |
| 10500 | case 2: |
| 10501 | // op: I2 |
| 10502 | return 32; |
| 10503 | } |
| 10504 | break; |
| 10505 | } |
| 10506 | case SystemZ::LPSWEY: { |
| 10507 | switch (OpNum) { |
| 10508 | case 0: |
| 10509 | // op: B1 |
| 10510 | return 28; |
| 10511 | case 1: |
| 10512 | // op: D1 |
| 10513 | return 8; |
| 10514 | } |
| 10515 | break; |
| 10516 | } |
| 10517 | case SystemZ::CFC: |
| 10518 | case SystemZ::LBEAR: |
| 10519 | case SystemZ::LCCTL: |
| 10520 | case SystemZ::LFAS: |
| 10521 | case SystemZ::LFPC: |
| 10522 | case SystemZ::LPCTL: |
| 10523 | case SystemZ::LPP: |
| 10524 | case SystemZ::LPSW: |
| 10525 | case SystemZ::LPSWE: |
| 10526 | case SystemZ::LSCTL: |
| 10527 | case SystemZ::MSCH: |
| 10528 | case SystemZ::PC: |
| 10529 | case SystemZ::QCTRI: |
| 10530 | case SystemZ::QPACI: |
| 10531 | case SystemZ::QSI: |
| 10532 | case SystemZ::RP: |
| 10533 | case SystemZ::SAC: |
| 10534 | case SystemZ::SACF: |
| 10535 | case SystemZ::SCK: |
| 10536 | case SystemZ::SCKC: |
| 10537 | case SystemZ::SIE: |
| 10538 | case SystemZ::SIGA: |
| 10539 | case SystemZ::SPKA: |
| 10540 | case SystemZ::SPT: |
| 10541 | case SystemZ::SPX: |
| 10542 | case SystemZ::SRNM: |
| 10543 | case SystemZ::SRNMB: |
| 10544 | case SystemZ::SRNMT: |
| 10545 | case SystemZ::SSCH: |
| 10546 | case SystemZ::SSM: |
| 10547 | case SystemZ::STAP: |
| 10548 | case SystemZ::STBEAR: |
| 10549 | case SystemZ::STCK: |
| 10550 | case SystemZ::STCKC: |
| 10551 | case SystemZ::STCKE: |
| 10552 | case SystemZ::STCKF: |
| 10553 | case SystemZ::STCPS: |
| 10554 | case SystemZ::STCRW: |
| 10555 | case SystemZ::STFL: |
| 10556 | case SystemZ::STFLE: |
| 10557 | case SystemZ::STFPC: |
| 10558 | case SystemZ::STIDP: |
| 10559 | case SystemZ::STPT: |
| 10560 | case SystemZ::STPX: |
| 10561 | case SystemZ::STSCH: |
| 10562 | case SystemZ::STSI: |
| 10563 | case SystemZ::TABORT: |
| 10564 | case SystemZ::TPI: |
| 10565 | case SystemZ::TRAP4: |
| 10566 | case SystemZ::TS: |
| 10567 | case SystemZ::TSCH: { |
| 10568 | switch (OpNum) { |
| 10569 | case 0: |
| 10570 | // op: B2 |
| 10571 | return 12; |
| 10572 | case 1: |
| 10573 | // op: D2 |
| 10574 | return 0; |
| 10575 | } |
| 10576 | break; |
| 10577 | } |
| 10578 | case SystemZ::SVC: { |
| 10579 | switch (OpNum) { |
| 10580 | case 0: |
| 10581 | // op: I1 |
| 10582 | return 0; |
| 10583 | } |
| 10584 | break; |
| 10585 | } |
| 10586 | case SystemZ::NIAI: { |
| 10587 | switch (OpNum) { |
| 10588 | case 0: |
| 10589 | // op: I1 |
| 10590 | return 4; |
| 10591 | case 1: |
| 10592 | // op: I2 |
| 10593 | return 0; |
| 10594 | } |
| 10595 | break; |
| 10596 | } |
| 10597 | case SystemZ::BRCAsm: { |
| 10598 | switch (OpNum) { |
| 10599 | case 0: |
| 10600 | // op: M1 |
| 10601 | return 20; |
| 10602 | case 1: |
| 10603 | // op: RI2 |
| 10604 | return 0; |
| 10605 | } |
| 10606 | break; |
| 10607 | } |
| 10608 | case SystemZ::BCAsm: { |
| 10609 | switch (OpNum) { |
| 10610 | case 0: |
| 10611 | // op: M1 |
| 10612 | return 20; |
| 10613 | case 3: |
| 10614 | // op: X2 |
| 10615 | return 16; |
| 10616 | case 1: |
| 10617 | // op: B2 |
| 10618 | return 12; |
| 10619 | case 2: |
| 10620 | // op: D2 |
| 10621 | return 0; |
| 10622 | } |
| 10623 | break; |
| 10624 | } |
| 10625 | case SystemZ::BPP: { |
| 10626 | switch (OpNum) { |
| 10627 | case 0: |
| 10628 | // op: M1 |
| 10629 | return 36; |
| 10630 | case 1: |
| 10631 | // op: RI2 |
| 10632 | return 0; |
| 10633 | case 2: |
| 10634 | // op: B3 |
| 10635 | return 28; |
| 10636 | case 3: |
| 10637 | // op: D3 |
| 10638 | return 16; |
| 10639 | } |
| 10640 | break; |
| 10641 | } |
| 10642 | case SystemZ::BRCLAsm: |
| 10643 | case SystemZ::PFDRL: { |
| 10644 | switch (OpNum) { |
| 10645 | case 0: |
| 10646 | // op: M1 |
| 10647 | return 36; |
| 10648 | case 1: |
| 10649 | // op: RI2 |
| 10650 | return 0; |
| 10651 | } |
| 10652 | break; |
| 10653 | } |
| 10654 | case SystemZ::BPRP: { |
| 10655 | switch (OpNum) { |
| 10656 | case 0: |
| 10657 | // op: M1 |
| 10658 | return 36; |
| 10659 | case 1: |
| 10660 | // op: RI2 |
| 10661 | return 24; |
| 10662 | case 2: |
| 10663 | // op: RI3 |
| 10664 | return 0; |
| 10665 | } |
| 10666 | break; |
| 10667 | } |
| 10668 | case SystemZ::BICAsm: |
| 10669 | case SystemZ::PFD: { |
| 10670 | switch (OpNum) { |
| 10671 | case 0: |
| 10672 | // op: M1 |
| 10673 | return 36; |
| 10674 | case 3: |
| 10675 | // op: X2 |
| 10676 | return 32; |
| 10677 | case 1: |
| 10678 | // op: B2 |
| 10679 | return 28; |
| 10680 | case 2: |
| 10681 | // op: D2 |
| 10682 | return 8; |
| 10683 | } |
| 10684 | break; |
| 10685 | } |
| 10686 | case SystemZ::CDPT: |
| 10687 | case SystemZ::CDZT: |
| 10688 | case SystemZ::CPDT: |
| 10689 | case SystemZ::CPXT: |
| 10690 | case SystemZ::CXPT: |
| 10691 | case SystemZ::CXZT: |
| 10692 | case SystemZ::CZDT: |
| 10693 | case SystemZ::CZXT: { |
| 10694 | switch (OpNum) { |
| 10695 | case 0: |
| 10696 | // op: R1 |
| 10697 | return 12; |
| 10698 | case 1: |
| 10699 | // op: B2 |
| 10700 | return 28; |
| 10701 | case 2: |
| 10702 | // op: D2 |
| 10703 | return 16; |
| 10704 | case 3: |
| 10705 | // op: L2 |
| 10706 | return 32; |
| 10707 | case 4: |
| 10708 | // op: M3 |
| 10709 | return 8; |
| 10710 | } |
| 10711 | break; |
| 10712 | } |
| 10713 | case SystemZ::MY: |
| 10714 | case SystemZ::MYH: |
| 10715 | case SystemZ::MYL: |
| 10716 | case SystemZ::SLDT: |
| 10717 | case SystemZ::SLXT: |
| 10718 | case SystemZ::SRDT: |
| 10719 | case SystemZ::SRXT: { |
| 10720 | switch (OpNum) { |
| 10721 | case 0: |
| 10722 | // op: R1 |
| 10723 | return 12; |
| 10724 | case 1: |
| 10725 | // op: R3 |
| 10726 | return 36; |
| 10727 | case 4: |
| 10728 | // op: X2 |
| 10729 | return 32; |
| 10730 | case 2: |
| 10731 | // op: B2 |
| 10732 | return 28; |
| 10733 | case 3: |
| 10734 | // op: D2 |
| 10735 | return 16; |
| 10736 | } |
| 10737 | break; |
| 10738 | } |
| 10739 | case SystemZ::MYHR: |
| 10740 | case SystemZ::MYLR: |
| 10741 | case SystemZ::MYR: { |
| 10742 | switch (OpNum) { |
| 10743 | case 0: |
| 10744 | // op: R1 |
| 10745 | return 12; |
| 10746 | case 1: |
| 10747 | // op: R3 |
| 10748 | return 4; |
| 10749 | case 2: |
| 10750 | // op: R2 |
| 10751 | return 0; |
| 10752 | } |
| 10753 | break; |
| 10754 | } |
| 10755 | case SystemZ::MAD: |
| 10756 | case SystemZ::MADB: |
| 10757 | case SystemZ::MAE: |
| 10758 | case SystemZ::MAEB: |
| 10759 | case SystemZ::MAY: |
| 10760 | case SystemZ::MAYH: |
| 10761 | case SystemZ::MAYL: |
| 10762 | case SystemZ::MSD: |
| 10763 | case SystemZ::MSDB: |
| 10764 | case SystemZ::MSE: |
| 10765 | case SystemZ::MSEB: { |
| 10766 | switch (OpNum) { |
| 10767 | case 0: |
| 10768 | // op: R1 |
| 10769 | return 12; |
| 10770 | case 2: |
| 10771 | // op: R3 |
| 10772 | return 36; |
| 10773 | case 5: |
| 10774 | // op: X2 |
| 10775 | return 32; |
| 10776 | case 3: |
| 10777 | // op: B2 |
| 10778 | return 28; |
| 10779 | case 4: |
| 10780 | // op: D2 |
| 10781 | return 16; |
| 10782 | } |
| 10783 | break; |
| 10784 | } |
| 10785 | case SystemZ::MADBR: |
| 10786 | case SystemZ::MADR: |
| 10787 | case SystemZ::MAEBR: |
| 10788 | case SystemZ::MAER: |
| 10789 | case SystemZ::MAYHR: |
| 10790 | case SystemZ::MAYLR: |
| 10791 | case SystemZ::MAYR: |
| 10792 | case SystemZ::MSDBR: |
| 10793 | case SystemZ::MSDR: |
| 10794 | case SystemZ::MSEBR: |
| 10795 | case SystemZ::MSER: { |
| 10796 | switch (OpNum) { |
| 10797 | case 0: |
| 10798 | // op: R1 |
| 10799 | return 12; |
| 10800 | case 2: |
| 10801 | // op: R3 |
| 10802 | return 4; |
| 10803 | case 3: |
| 10804 | // op: R2 |
| 10805 | return 0; |
| 10806 | } |
| 10807 | break; |
| 10808 | } |
| 10809 | case SystemZ::CGHI: |
| 10810 | case SystemZ::CHI: |
| 10811 | case SystemZ::LGHI: |
| 10812 | case SystemZ::LHI: |
| 10813 | case SystemZ::LLIHH: |
| 10814 | case SystemZ::LLIHL: |
| 10815 | case SystemZ::LLILH: |
| 10816 | case SystemZ::LLILL: |
| 10817 | case SystemZ::TMHH: |
| 10818 | case SystemZ::TMHL: |
| 10819 | case SystemZ::TMLH: |
| 10820 | case SystemZ::TMLL: { |
| 10821 | switch (OpNum) { |
| 10822 | case 0: |
| 10823 | // op: R1 |
| 10824 | return 20; |
| 10825 | case 1: |
| 10826 | // op: I2 |
| 10827 | return 0; |
| 10828 | } |
| 10829 | break; |
| 10830 | } |
| 10831 | case SystemZ::CLM: |
| 10832 | case SystemZ::STCM: { |
| 10833 | switch (OpNum) { |
| 10834 | case 0: |
| 10835 | // op: R1 |
| 10836 | return 20; |
| 10837 | case 1: |
| 10838 | // op: M3 |
| 10839 | return 16; |
| 10840 | case 2: |
| 10841 | // op: B2 |
| 10842 | return 12; |
| 10843 | case 3: |
| 10844 | // op: D2 |
| 10845 | return 0; |
| 10846 | } |
| 10847 | break; |
| 10848 | } |
| 10849 | case SystemZ::DIAG: |
| 10850 | case SystemZ::LAM: |
| 10851 | case SystemZ::LCTL: |
| 10852 | case SystemZ::LM: |
| 10853 | case SystemZ::SIGP: |
| 10854 | case SystemZ::STAM: |
| 10855 | case SystemZ::STCTL: |
| 10856 | case SystemZ::STM: |
| 10857 | case SystemZ::TRACE: { |
| 10858 | switch (OpNum) { |
| 10859 | case 0: |
| 10860 | // op: R1 |
| 10861 | return 20; |
| 10862 | case 1: |
| 10863 | // op: R3 |
| 10864 | return 16; |
| 10865 | case 2: |
| 10866 | // op: B2 |
| 10867 | return 12; |
| 10868 | case 3: |
| 10869 | // op: D2 |
| 10870 | return 0; |
| 10871 | } |
| 10872 | break; |
| 10873 | } |
| 10874 | case SystemZ::CLCLE: |
| 10875 | case SystemZ::MVCLE: { |
| 10876 | switch (OpNum) { |
| 10877 | case 0: |
| 10878 | // op: R1 |
| 10879 | return 20; |
| 10880 | case 1: |
| 10881 | // op: R3 |
| 10882 | return 16; |
| 10883 | case 4: |
| 10884 | // op: B2 |
| 10885 | return 12; |
| 10886 | case 5: |
| 10887 | // op: D2 |
| 10888 | return 0; |
| 10889 | } |
| 10890 | break; |
| 10891 | } |
| 10892 | case SystemZ::BRAS: { |
| 10893 | switch (OpNum) { |
| 10894 | case 0: |
| 10895 | // op: R1 |
| 10896 | return 20; |
| 10897 | case 1: |
| 10898 | // op: RI2 |
| 10899 | return 0; |
| 10900 | } |
| 10901 | break; |
| 10902 | } |
| 10903 | case SystemZ::SLA: |
| 10904 | case SystemZ::SLDA: |
| 10905 | case SystemZ::SLDL: |
| 10906 | case SystemZ::SLL: |
| 10907 | case SystemZ::SRA: |
| 10908 | case SystemZ::SRDA: |
| 10909 | case SystemZ::SRDL: |
| 10910 | case SystemZ::SRL: { |
| 10911 | switch (OpNum) { |
| 10912 | case 0: |
| 10913 | // op: R1 |
| 10914 | return 20; |
| 10915 | case 2: |
| 10916 | // op: B2 |
| 10917 | return 12; |
| 10918 | case 3: |
| 10919 | // op: D2 |
| 10920 | return 0; |
| 10921 | } |
| 10922 | break; |
| 10923 | } |
| 10924 | case SystemZ::AGHI: |
| 10925 | case SystemZ::AHI: |
| 10926 | case SystemZ::IIHH: |
| 10927 | case SystemZ::IIHL: |
| 10928 | case SystemZ::IILH: |
| 10929 | case SystemZ::IILL: |
| 10930 | case SystemZ::MGHI: |
| 10931 | case SystemZ::MHI: |
| 10932 | case SystemZ::NIHH: |
| 10933 | case SystemZ::NIHL: |
| 10934 | case SystemZ::NILH: |
| 10935 | case SystemZ::NILL: |
| 10936 | case SystemZ::OIHH: |
| 10937 | case SystemZ::OIHL: |
| 10938 | case SystemZ::OILH: |
| 10939 | case SystemZ::OILL: { |
| 10940 | switch (OpNum) { |
| 10941 | case 0: |
| 10942 | // op: R1 |
| 10943 | return 20; |
| 10944 | case 2: |
| 10945 | // op: I2 |
| 10946 | return 0; |
| 10947 | } |
| 10948 | break; |
| 10949 | } |
| 10950 | case SystemZ::ICM: { |
| 10951 | switch (OpNum) { |
| 10952 | case 0: |
| 10953 | // op: R1 |
| 10954 | return 20; |
| 10955 | case 2: |
| 10956 | // op: M3 |
| 10957 | return 16; |
| 10958 | case 3: |
| 10959 | // op: B2 |
| 10960 | return 12; |
| 10961 | case 4: |
| 10962 | // op: D2 |
| 10963 | return 0; |
| 10964 | } |
| 10965 | break; |
| 10966 | } |
| 10967 | case SystemZ::BXH: |
| 10968 | case SystemZ::BXLE: |
| 10969 | case SystemZ::CDS: |
| 10970 | case SystemZ::CS: { |
| 10971 | switch (OpNum) { |
| 10972 | case 0: |
| 10973 | // op: R1 |
| 10974 | return 20; |
| 10975 | case 2: |
| 10976 | // op: R3 |
| 10977 | return 16; |
| 10978 | case 3: |
| 10979 | // op: B2 |
| 10980 | return 12; |
| 10981 | case 4: |
| 10982 | // op: D2 |
| 10983 | return 0; |
| 10984 | } |
| 10985 | break; |
| 10986 | } |
| 10987 | case SystemZ::BRXH: |
| 10988 | case SystemZ::BRXLE: { |
| 10989 | switch (OpNum) { |
| 10990 | case 0: |
| 10991 | // op: R1 |
| 10992 | return 20; |
| 10993 | case 2: |
| 10994 | // op: R3 |
| 10995 | return 16; |
| 10996 | case 3: |
| 10997 | // op: RI2 |
| 10998 | return 0; |
| 10999 | } |
| 11000 | break; |
| 11001 | } |
| 11002 | case SystemZ::BRCT: |
| 11003 | case SystemZ::BRCTG: { |
| 11004 | switch (OpNum) { |
| 11005 | case 0: |
| 11006 | // op: R1 |
| 11007 | return 20; |
| 11008 | case 2: |
| 11009 | // op: RI2 |
| 11010 | return 0; |
| 11011 | } |
| 11012 | break; |
| 11013 | } |
| 11014 | case SystemZ::BAL: |
| 11015 | case SystemZ::BAS: |
| 11016 | case SystemZ::C: |
| 11017 | case SystemZ::CD: |
| 11018 | case SystemZ::CE: |
| 11019 | case SystemZ::CH: |
| 11020 | case SystemZ::CL: |
| 11021 | case SystemZ::CVD: |
| 11022 | case SystemZ::EX: |
| 11023 | case SystemZ::L: |
| 11024 | case SystemZ::LA: |
| 11025 | case SystemZ::LAE: |
| 11026 | case SystemZ::LD: |
| 11027 | case SystemZ::LE: |
| 11028 | case SystemZ::LE16: |
| 11029 | case SystemZ::LH: |
| 11030 | case SystemZ::LRA: |
| 11031 | case SystemZ::ST: |
| 11032 | case SystemZ::STC: |
| 11033 | case SystemZ::STD: |
| 11034 | case SystemZ::STE: |
| 11035 | case SystemZ::STE16: |
| 11036 | case SystemZ::STH: { |
| 11037 | switch (OpNum) { |
| 11038 | case 0: |
| 11039 | // op: R1 |
| 11040 | return 20; |
| 11041 | case 3: |
| 11042 | // op: X2 |
| 11043 | return 16; |
| 11044 | case 1: |
| 11045 | // op: B2 |
| 11046 | return 12; |
| 11047 | case 2: |
| 11048 | // op: D2 |
| 11049 | return 0; |
| 11050 | } |
| 11051 | break; |
| 11052 | } |
| 11053 | case SystemZ::A: |
| 11054 | case SystemZ::AD: |
| 11055 | case SystemZ::AE: |
| 11056 | case SystemZ::AH: |
| 11057 | case SystemZ::AL: |
| 11058 | case SystemZ::AU: |
| 11059 | case SystemZ::AW: |
| 11060 | case SystemZ::BCT: |
| 11061 | case SystemZ::CVB: |
| 11062 | case SystemZ::D: |
| 11063 | case SystemZ::DD: |
| 11064 | case SystemZ::DE: |
| 11065 | case SystemZ::IC: |
| 11066 | case SystemZ::IC32: |
| 11067 | case SystemZ::M: |
| 11068 | case SystemZ::MD: |
| 11069 | case SystemZ::MDE: |
| 11070 | case SystemZ::ME: |
| 11071 | case SystemZ::MH: |
| 11072 | case SystemZ::MS: |
| 11073 | case SystemZ::MXD: |
| 11074 | case SystemZ::N: |
| 11075 | case SystemZ::O: |
| 11076 | case SystemZ::S: |
| 11077 | case SystemZ::SD: |
| 11078 | case SystemZ::SE: |
| 11079 | case SystemZ::SH: |
| 11080 | case SystemZ::SL: |
| 11081 | case SystemZ::SU: |
| 11082 | case SystemZ::SW: |
| 11083 | case SystemZ::X: { |
| 11084 | switch (OpNum) { |
| 11085 | case 0: |
| 11086 | // op: R1 |
| 11087 | return 20; |
| 11088 | case 4: |
| 11089 | // op: X2 |
| 11090 | return 16; |
| 11091 | case 2: |
| 11092 | // op: B2 |
| 11093 | return 12; |
| 11094 | case 3: |
| 11095 | // op: D2 |
| 11096 | return 0; |
| 11097 | } |
| 11098 | break; |
| 11099 | } |
| 11100 | case SystemZ::PLO: { |
| 11101 | switch (OpNum) { |
| 11102 | case 0: |
| 11103 | // op: R1 |
| 11104 | return 36; |
| 11105 | case 1: |
| 11106 | // op: B2 |
| 11107 | return 28; |
| 11108 | case 2: |
| 11109 | // op: D2 |
| 11110 | return 16; |
| 11111 | case 3: |
| 11112 | // op: R3 |
| 11113 | return 32; |
| 11114 | case 4: |
| 11115 | // op: B4 |
| 11116 | return 12; |
| 11117 | case 5: |
| 11118 | // op: D4 |
| 11119 | return 0; |
| 11120 | } |
| 11121 | break; |
| 11122 | } |
| 11123 | case SystemZ::CLGTAsmE: |
| 11124 | case SystemZ::CLGTAsmH: |
| 11125 | case SystemZ::CLGTAsmHE: |
| 11126 | case SystemZ::CLGTAsmL: |
| 11127 | case SystemZ::CLGTAsmLE: |
| 11128 | case SystemZ::CLGTAsmLH: |
| 11129 | case SystemZ::CLGTAsmNE: |
| 11130 | case SystemZ::CLGTAsmNH: |
| 11131 | case SystemZ::CLGTAsmNHE: |
| 11132 | case SystemZ::CLGTAsmNL: |
| 11133 | case SystemZ::CLGTAsmNLE: |
| 11134 | case SystemZ::CLGTAsmNLH: |
| 11135 | case SystemZ::CLTAsmE: |
| 11136 | case SystemZ::CLTAsmH: |
| 11137 | case SystemZ::CLTAsmHE: |
| 11138 | case SystemZ::CLTAsmL: |
| 11139 | case SystemZ::CLTAsmLE: |
| 11140 | case SystemZ::CLTAsmLH: |
| 11141 | case SystemZ::CLTAsmNE: |
| 11142 | case SystemZ::CLTAsmNH: |
| 11143 | case SystemZ::CLTAsmNHE: |
| 11144 | case SystemZ::CLTAsmNL: |
| 11145 | case SystemZ::CLTAsmNLE: |
| 11146 | case SystemZ::CLTAsmNLH: |
| 11147 | case SystemZ::STOCAsmE: |
| 11148 | case SystemZ::STOCAsmH: |
| 11149 | case SystemZ::STOCAsmHE: |
| 11150 | case SystemZ::STOCAsmL: |
| 11151 | case SystemZ::STOCAsmLE: |
| 11152 | case SystemZ::STOCAsmLH: |
| 11153 | case SystemZ::STOCAsmM: |
| 11154 | case SystemZ::STOCAsmNE: |
| 11155 | case SystemZ::STOCAsmNH: |
| 11156 | case SystemZ::STOCAsmNHE: |
| 11157 | case SystemZ::STOCAsmNL: |
| 11158 | case SystemZ::STOCAsmNLE: |
| 11159 | case SystemZ::STOCAsmNLH: |
| 11160 | case SystemZ::STOCAsmNM: |
| 11161 | case SystemZ::STOCAsmNO: |
| 11162 | case SystemZ::STOCAsmNP: |
| 11163 | case SystemZ::STOCAsmNZ: |
| 11164 | case SystemZ::STOCAsmO: |
| 11165 | case SystemZ::STOCAsmP: |
| 11166 | case SystemZ::STOCAsmZ: |
| 11167 | case SystemZ::STOCFHAsmE: |
| 11168 | case SystemZ::STOCFHAsmH: |
| 11169 | case SystemZ::STOCFHAsmHE: |
| 11170 | case SystemZ::STOCFHAsmL: |
| 11171 | case SystemZ::STOCFHAsmLE: |
| 11172 | case SystemZ::STOCFHAsmLH: |
| 11173 | case SystemZ::STOCFHAsmM: |
| 11174 | case SystemZ::STOCFHAsmNE: |
| 11175 | case SystemZ::STOCFHAsmNH: |
| 11176 | case SystemZ::STOCFHAsmNHE: |
| 11177 | case SystemZ::STOCFHAsmNL: |
| 11178 | case SystemZ::STOCFHAsmNLE: |
| 11179 | case SystemZ::STOCFHAsmNLH: |
| 11180 | case SystemZ::STOCFHAsmNM: |
| 11181 | case SystemZ::STOCFHAsmNO: |
| 11182 | case SystemZ::STOCFHAsmNP: |
| 11183 | case SystemZ::STOCFHAsmNZ: |
| 11184 | case SystemZ::STOCFHAsmO: |
| 11185 | case SystemZ::STOCFHAsmP: |
| 11186 | case SystemZ::STOCFHAsmZ: |
| 11187 | case SystemZ::STOCGAsmE: |
| 11188 | case SystemZ::STOCGAsmH: |
| 11189 | case SystemZ::STOCGAsmHE: |
| 11190 | case SystemZ::STOCGAsmL: |
| 11191 | case SystemZ::STOCGAsmLE: |
| 11192 | case SystemZ::STOCGAsmLH: |
| 11193 | case SystemZ::STOCGAsmM: |
| 11194 | case SystemZ::STOCGAsmNE: |
| 11195 | case SystemZ::STOCGAsmNH: |
| 11196 | case SystemZ::STOCGAsmNHE: |
| 11197 | case SystemZ::STOCGAsmNL: |
| 11198 | case SystemZ::STOCGAsmNLE: |
| 11199 | case SystemZ::STOCGAsmNLH: |
| 11200 | case SystemZ::STOCGAsmNM: |
| 11201 | case SystemZ::STOCGAsmNO: |
| 11202 | case SystemZ::STOCGAsmNP: |
| 11203 | case SystemZ::STOCGAsmNZ: |
| 11204 | case SystemZ::STOCGAsmO: |
| 11205 | case SystemZ::STOCGAsmP: |
| 11206 | case SystemZ::STOCGAsmZ: { |
| 11207 | switch (OpNum) { |
| 11208 | case 0: |
| 11209 | // op: R1 |
| 11210 | return 36; |
| 11211 | case 1: |
| 11212 | // op: B2 |
| 11213 | return 28; |
| 11214 | case 2: |
| 11215 | // op: D2 |
| 11216 | return 8; |
| 11217 | } |
| 11218 | break; |
| 11219 | } |
| 11220 | case SystemZ::CFI: |
| 11221 | case SystemZ::CGFI: |
| 11222 | case SystemZ::CIH: |
| 11223 | case SystemZ::CLFI: |
| 11224 | case SystemZ::CLGFI: |
| 11225 | case SystemZ::CLIH: |
| 11226 | case SystemZ::IIHF: |
| 11227 | case SystemZ::IILF: |
| 11228 | case SystemZ::LGFI: |
| 11229 | case SystemZ::LLIHF: |
| 11230 | case SystemZ::LLILF: { |
| 11231 | switch (OpNum) { |
| 11232 | case 0: |
| 11233 | // op: R1 |
| 11234 | return 36; |
| 11235 | case 1: |
| 11236 | // op: I2 |
| 11237 | return 0; |
| 11238 | } |
| 11239 | break; |
| 11240 | } |
| 11241 | case SystemZ::CGIT: |
| 11242 | case SystemZ::CGITAsm: |
| 11243 | case SystemZ::CIT: |
| 11244 | case SystemZ::CITAsm: |
| 11245 | case SystemZ::CLFIT: |
| 11246 | case SystemZ::CLFITAsm: |
| 11247 | case SystemZ::CLGIT: |
| 11248 | case SystemZ::CLGITAsm: { |
| 11249 | switch (OpNum) { |
| 11250 | case 0: |
| 11251 | // op: R1 |
| 11252 | return 36; |
| 11253 | case 1: |
| 11254 | // op: I2 |
| 11255 | return 16; |
| 11256 | case 2: |
| 11257 | // op: M3 |
| 11258 | return 12; |
| 11259 | } |
| 11260 | break; |
| 11261 | } |
| 11262 | case SystemZ::CGITAsmE: |
| 11263 | case SystemZ::CGITAsmH: |
| 11264 | case SystemZ::CGITAsmHE: |
| 11265 | case SystemZ::CGITAsmL: |
| 11266 | case SystemZ::CGITAsmLE: |
| 11267 | case SystemZ::CGITAsmLH: |
| 11268 | case SystemZ::CGITAsmNE: |
| 11269 | case SystemZ::CGITAsmNH: |
| 11270 | case SystemZ::CGITAsmNHE: |
| 11271 | case SystemZ::CGITAsmNL: |
| 11272 | case SystemZ::CGITAsmNLE: |
| 11273 | case SystemZ::CGITAsmNLH: |
| 11274 | case SystemZ::CITAsmE: |
| 11275 | case SystemZ::CITAsmH: |
| 11276 | case SystemZ::CITAsmHE: |
| 11277 | case SystemZ::CITAsmL: |
| 11278 | case SystemZ::CITAsmLE: |
| 11279 | case SystemZ::CITAsmLH: |
| 11280 | case SystemZ::CITAsmNE: |
| 11281 | case SystemZ::CITAsmNH: |
| 11282 | case SystemZ::CITAsmNHE: |
| 11283 | case SystemZ::CITAsmNL: |
| 11284 | case SystemZ::CITAsmNLE: |
| 11285 | case SystemZ::CITAsmNLH: |
| 11286 | case SystemZ::CLFITAsmE: |
| 11287 | case SystemZ::CLFITAsmH: |
| 11288 | case SystemZ::CLFITAsmHE: |
| 11289 | case SystemZ::CLFITAsmL: |
| 11290 | case SystemZ::CLFITAsmLE: |
| 11291 | case SystemZ::CLFITAsmLH: |
| 11292 | case SystemZ::CLFITAsmNE: |
| 11293 | case SystemZ::CLFITAsmNH: |
| 11294 | case SystemZ::CLFITAsmNHE: |
| 11295 | case SystemZ::CLFITAsmNL: |
| 11296 | case SystemZ::CLFITAsmNLE: |
| 11297 | case SystemZ::CLFITAsmNLH: |
| 11298 | case SystemZ::CLGITAsmE: |
| 11299 | case SystemZ::CLGITAsmH: |
| 11300 | case SystemZ::CLGITAsmHE: |
| 11301 | case SystemZ::CLGITAsmL: |
| 11302 | case SystemZ::CLGITAsmLE: |
| 11303 | case SystemZ::CLGITAsmLH: |
| 11304 | case SystemZ::CLGITAsmNE: |
| 11305 | case SystemZ::CLGITAsmNH: |
| 11306 | case SystemZ::CLGITAsmNHE: |
| 11307 | case SystemZ::CLGITAsmNL: |
| 11308 | case SystemZ::CLGITAsmNLE: |
| 11309 | case SystemZ::CLGITAsmNLH: { |
| 11310 | switch (OpNum) { |
| 11311 | case 0: |
| 11312 | // op: R1 |
| 11313 | return 36; |
| 11314 | case 1: |
| 11315 | // op: I2 |
| 11316 | return 16; |
| 11317 | } |
| 11318 | break; |
| 11319 | } |
| 11320 | case SystemZ::CGIBAsmE: |
| 11321 | case SystemZ::CGIBAsmH: |
| 11322 | case SystemZ::CGIBAsmHE: |
| 11323 | case SystemZ::CGIBAsmL: |
| 11324 | case SystemZ::CGIBAsmLE: |
| 11325 | case SystemZ::CGIBAsmLH: |
| 11326 | case SystemZ::CGIBAsmNE: |
| 11327 | case SystemZ::CGIBAsmNH: |
| 11328 | case SystemZ::CGIBAsmNHE: |
| 11329 | case SystemZ::CGIBAsmNL: |
| 11330 | case SystemZ::CGIBAsmNLE: |
| 11331 | case SystemZ::CGIBAsmNLH: |
| 11332 | case SystemZ::CIBAsmE: |
| 11333 | case SystemZ::CIBAsmH: |
| 11334 | case SystemZ::CIBAsmHE: |
| 11335 | case SystemZ::CIBAsmL: |
| 11336 | case SystemZ::CIBAsmLE: |
| 11337 | case SystemZ::CIBAsmLH: |
| 11338 | case SystemZ::CIBAsmNE: |
| 11339 | case SystemZ::CIBAsmNH: |
| 11340 | case SystemZ::CIBAsmNHE: |
| 11341 | case SystemZ::CIBAsmNL: |
| 11342 | case SystemZ::CIBAsmNLE: |
| 11343 | case SystemZ::CIBAsmNLH: |
| 11344 | case SystemZ::CLGIBAsmE: |
| 11345 | case SystemZ::CLGIBAsmH: |
| 11346 | case SystemZ::CLGIBAsmHE: |
| 11347 | case SystemZ::CLGIBAsmL: |
| 11348 | case SystemZ::CLGIBAsmLE: |
| 11349 | case SystemZ::CLGIBAsmLH: |
| 11350 | case SystemZ::CLGIBAsmNE: |
| 11351 | case SystemZ::CLGIBAsmNH: |
| 11352 | case SystemZ::CLGIBAsmNHE: |
| 11353 | case SystemZ::CLGIBAsmNL: |
| 11354 | case SystemZ::CLGIBAsmNLE: |
| 11355 | case SystemZ::CLGIBAsmNLH: |
| 11356 | case SystemZ::CLIBAsmE: |
| 11357 | case SystemZ::CLIBAsmH: |
| 11358 | case SystemZ::CLIBAsmHE: |
| 11359 | case SystemZ::CLIBAsmL: |
| 11360 | case SystemZ::CLIBAsmLE: |
| 11361 | case SystemZ::CLIBAsmLH: |
| 11362 | case SystemZ::CLIBAsmNE: |
| 11363 | case SystemZ::CLIBAsmNH: |
| 11364 | case SystemZ::CLIBAsmNHE: |
| 11365 | case SystemZ::CLIBAsmNL: |
| 11366 | case SystemZ::CLIBAsmNLE: |
| 11367 | case SystemZ::CLIBAsmNLH: { |
| 11368 | switch (OpNum) { |
| 11369 | case 0: |
| 11370 | // op: R1 |
| 11371 | return 36; |
| 11372 | case 1: |
| 11373 | // op: I2 |
| 11374 | return 8; |
| 11375 | case 2: |
| 11376 | // op: B4 |
| 11377 | return 28; |
| 11378 | case 3: |
| 11379 | // op: D4 |
| 11380 | return 16; |
| 11381 | } |
| 11382 | break; |
| 11383 | } |
| 11384 | case SystemZ::CGIB: |
| 11385 | case SystemZ::CGIBAsm: |
| 11386 | case SystemZ::CIB: |
| 11387 | case SystemZ::CIBAsm: |
| 11388 | case SystemZ::CLGIB: |
| 11389 | case SystemZ::CLGIBAsm: |
| 11390 | case SystemZ::CLIB: |
| 11391 | case SystemZ::CLIBAsm: { |
| 11392 | switch (OpNum) { |
| 11393 | case 0: |
| 11394 | // op: R1 |
| 11395 | return 36; |
| 11396 | case 1: |
| 11397 | // op: I2 |
| 11398 | return 8; |
| 11399 | case 2: |
| 11400 | // op: M3 |
| 11401 | return 32; |
| 11402 | case 3: |
| 11403 | // op: B4 |
| 11404 | return 28; |
| 11405 | case 4: |
| 11406 | // op: D4 |
| 11407 | return 16; |
| 11408 | } |
| 11409 | break; |
| 11410 | } |
| 11411 | case SystemZ::CGIJ: |
| 11412 | case SystemZ::CGIJAsm: |
| 11413 | case SystemZ::CIJ: |
| 11414 | case SystemZ::CIJAsm: |
| 11415 | case SystemZ::CLGIJ: |
| 11416 | case SystemZ::CLGIJAsm: |
| 11417 | case SystemZ::CLIJ: |
| 11418 | case SystemZ::CLIJAsm: { |
| 11419 | switch (OpNum) { |
| 11420 | case 0: |
| 11421 | // op: R1 |
| 11422 | return 36; |
| 11423 | case 1: |
| 11424 | // op: I2 |
| 11425 | return 8; |
| 11426 | case 2: |
| 11427 | // op: M3 |
| 11428 | return 32; |
| 11429 | case 3: |
| 11430 | // op: RI4 |
| 11431 | return 16; |
| 11432 | } |
| 11433 | break; |
| 11434 | } |
| 11435 | case SystemZ::CGIJAsmE: |
| 11436 | case SystemZ::CGIJAsmH: |
| 11437 | case SystemZ::CGIJAsmHE: |
| 11438 | case SystemZ::CGIJAsmL: |
| 11439 | case SystemZ::CGIJAsmLE: |
| 11440 | case SystemZ::CGIJAsmLH: |
| 11441 | case SystemZ::CGIJAsmNE: |
| 11442 | case SystemZ::CGIJAsmNH: |
| 11443 | case SystemZ::CGIJAsmNHE: |
| 11444 | case SystemZ::CGIJAsmNL: |
| 11445 | case SystemZ::CGIJAsmNLE: |
| 11446 | case SystemZ::CGIJAsmNLH: |
| 11447 | case SystemZ::CIJAsmE: |
| 11448 | case SystemZ::CIJAsmH: |
| 11449 | case SystemZ::CIJAsmHE: |
| 11450 | case SystemZ::CIJAsmL: |
| 11451 | case SystemZ::CIJAsmLE: |
| 11452 | case SystemZ::CIJAsmLH: |
| 11453 | case SystemZ::CIJAsmNE: |
| 11454 | case SystemZ::CIJAsmNH: |
| 11455 | case SystemZ::CIJAsmNHE: |
| 11456 | case SystemZ::CIJAsmNL: |
| 11457 | case SystemZ::CIJAsmNLE: |
| 11458 | case SystemZ::CIJAsmNLH: |
| 11459 | case SystemZ::CLGIJAsmE: |
| 11460 | case SystemZ::CLGIJAsmH: |
| 11461 | case SystemZ::CLGIJAsmHE: |
| 11462 | case SystemZ::CLGIJAsmL: |
| 11463 | case SystemZ::CLGIJAsmLE: |
| 11464 | case SystemZ::CLGIJAsmLH: |
| 11465 | case SystemZ::CLGIJAsmNE: |
| 11466 | case SystemZ::CLGIJAsmNH: |
| 11467 | case SystemZ::CLGIJAsmNHE: |
| 11468 | case SystemZ::CLGIJAsmNL: |
| 11469 | case SystemZ::CLGIJAsmNLE: |
| 11470 | case SystemZ::CLGIJAsmNLH: |
| 11471 | case SystemZ::CLIJAsmE: |
| 11472 | case SystemZ::CLIJAsmH: |
| 11473 | case SystemZ::CLIJAsmHE: |
| 11474 | case SystemZ::CLIJAsmL: |
| 11475 | case SystemZ::CLIJAsmLE: |
| 11476 | case SystemZ::CLIJAsmLH: |
| 11477 | case SystemZ::CLIJAsmNE: |
| 11478 | case SystemZ::CLIJAsmNH: |
| 11479 | case SystemZ::CLIJAsmNHE: |
| 11480 | case SystemZ::CLIJAsmNL: |
| 11481 | case SystemZ::CLIJAsmNLE: |
| 11482 | case SystemZ::CLIJAsmNLH: { |
| 11483 | switch (OpNum) { |
| 11484 | case 0: |
| 11485 | // op: R1 |
| 11486 | return 36; |
| 11487 | case 1: |
| 11488 | // op: I2 |
| 11489 | return 8; |
| 11490 | case 2: |
| 11491 | // op: RI4 |
| 11492 | return 16; |
| 11493 | } |
| 11494 | break; |
| 11495 | } |
| 11496 | case SystemZ::CLMH: |
| 11497 | case SystemZ::CLMY: |
| 11498 | case SystemZ::STCMH: |
| 11499 | case SystemZ::STCMY: { |
| 11500 | switch (OpNum) { |
| 11501 | case 0: |
| 11502 | // op: R1 |
| 11503 | return 36; |
| 11504 | case 1: |
| 11505 | // op: M3 |
| 11506 | return 32; |
| 11507 | case 2: |
| 11508 | // op: B2 |
| 11509 | return 28; |
| 11510 | case 3: |
| 11511 | // op: D2 |
| 11512 | return 8; |
| 11513 | } |
| 11514 | break; |
| 11515 | } |
| 11516 | case SystemZ::CGRBAsmE: |
| 11517 | case SystemZ::CGRBAsmH: |
| 11518 | case SystemZ::CGRBAsmHE: |
| 11519 | case SystemZ::CGRBAsmL: |
| 11520 | case SystemZ::CGRBAsmLE: |
| 11521 | case SystemZ::CGRBAsmLH: |
| 11522 | case SystemZ::CGRBAsmNE: |
| 11523 | case SystemZ::CGRBAsmNH: |
| 11524 | case SystemZ::CGRBAsmNHE: |
| 11525 | case SystemZ::CGRBAsmNL: |
| 11526 | case SystemZ::CGRBAsmNLE: |
| 11527 | case SystemZ::CGRBAsmNLH: |
| 11528 | case SystemZ::CLGRBAsmE: |
| 11529 | case SystemZ::CLGRBAsmH: |
| 11530 | case SystemZ::CLGRBAsmHE: |
| 11531 | case SystemZ::CLGRBAsmL: |
| 11532 | case SystemZ::CLGRBAsmLE: |
| 11533 | case SystemZ::CLGRBAsmLH: |
| 11534 | case SystemZ::CLGRBAsmNE: |
| 11535 | case SystemZ::CLGRBAsmNH: |
| 11536 | case SystemZ::CLGRBAsmNHE: |
| 11537 | case SystemZ::CLGRBAsmNL: |
| 11538 | case SystemZ::CLGRBAsmNLE: |
| 11539 | case SystemZ::CLGRBAsmNLH: |
| 11540 | case SystemZ::CLRBAsmE: |
| 11541 | case SystemZ::CLRBAsmH: |
| 11542 | case SystemZ::CLRBAsmHE: |
| 11543 | case SystemZ::CLRBAsmL: |
| 11544 | case SystemZ::CLRBAsmLE: |
| 11545 | case SystemZ::CLRBAsmLH: |
| 11546 | case SystemZ::CLRBAsmNE: |
| 11547 | case SystemZ::CLRBAsmNH: |
| 11548 | case SystemZ::CLRBAsmNHE: |
| 11549 | case SystemZ::CLRBAsmNL: |
| 11550 | case SystemZ::CLRBAsmNLE: |
| 11551 | case SystemZ::CLRBAsmNLH: |
| 11552 | case SystemZ::CRBAsmE: |
| 11553 | case SystemZ::CRBAsmH: |
| 11554 | case SystemZ::CRBAsmHE: |
| 11555 | case SystemZ::CRBAsmL: |
| 11556 | case SystemZ::CRBAsmLE: |
| 11557 | case SystemZ::CRBAsmLH: |
| 11558 | case SystemZ::CRBAsmNE: |
| 11559 | case SystemZ::CRBAsmNH: |
| 11560 | case SystemZ::CRBAsmNHE: |
| 11561 | case SystemZ::CRBAsmNL: |
| 11562 | case SystemZ::CRBAsmNLE: |
| 11563 | case SystemZ::CRBAsmNLH: { |
| 11564 | switch (OpNum) { |
| 11565 | case 0: |
| 11566 | // op: R1 |
| 11567 | return 36; |
| 11568 | case 1: |
| 11569 | // op: R2 |
| 11570 | return 32; |
| 11571 | case 2: |
| 11572 | // op: B4 |
| 11573 | return 28; |
| 11574 | case 3: |
| 11575 | // op: D4 |
| 11576 | return 16; |
| 11577 | } |
| 11578 | break; |
| 11579 | } |
| 11580 | case SystemZ::CGRB: |
| 11581 | case SystemZ::CGRBAsm: |
| 11582 | case SystemZ::CLGRB: |
| 11583 | case SystemZ::CLGRBAsm: |
| 11584 | case SystemZ::CLRB: |
| 11585 | case SystemZ::CLRBAsm: |
| 11586 | case SystemZ::CRB: |
| 11587 | case SystemZ::CRBAsm: { |
| 11588 | switch (OpNum) { |
| 11589 | case 0: |
| 11590 | // op: R1 |
| 11591 | return 36; |
| 11592 | case 1: |
| 11593 | // op: R2 |
| 11594 | return 32; |
| 11595 | case 2: |
| 11596 | // op: M3 |
| 11597 | return 12; |
| 11598 | case 3: |
| 11599 | // op: B4 |
| 11600 | return 28; |
| 11601 | case 4: |
| 11602 | // op: D4 |
| 11603 | return 16; |
| 11604 | } |
| 11605 | break; |
| 11606 | } |
| 11607 | case SystemZ::CGRJ: |
| 11608 | case SystemZ::CGRJAsm: |
| 11609 | case SystemZ::CLGRJ: |
| 11610 | case SystemZ::CLGRJAsm: |
| 11611 | case SystemZ::CLRJ: |
| 11612 | case SystemZ::CLRJAsm: |
| 11613 | case SystemZ::CRJ: |
| 11614 | case SystemZ::CRJAsm: { |
| 11615 | switch (OpNum) { |
| 11616 | case 0: |
| 11617 | // op: R1 |
| 11618 | return 36; |
| 11619 | case 1: |
| 11620 | // op: R2 |
| 11621 | return 32; |
| 11622 | case 2: |
| 11623 | // op: M3 |
| 11624 | return 12; |
| 11625 | case 3: |
| 11626 | // op: RI4 |
| 11627 | return 16; |
| 11628 | } |
| 11629 | break; |
| 11630 | } |
| 11631 | case SystemZ::CGRJAsmE: |
| 11632 | case SystemZ::CGRJAsmH: |
| 11633 | case SystemZ::CGRJAsmHE: |
| 11634 | case SystemZ::CGRJAsmL: |
| 11635 | case SystemZ::CGRJAsmLE: |
| 11636 | case SystemZ::CGRJAsmLH: |
| 11637 | case SystemZ::CGRJAsmNE: |
| 11638 | case SystemZ::CGRJAsmNH: |
| 11639 | case SystemZ::CGRJAsmNHE: |
| 11640 | case SystemZ::CGRJAsmNL: |
| 11641 | case SystemZ::CGRJAsmNLE: |
| 11642 | case SystemZ::CGRJAsmNLH: |
| 11643 | case SystemZ::CLGRJAsmE: |
| 11644 | case SystemZ::CLGRJAsmH: |
| 11645 | case SystemZ::CLGRJAsmHE: |
| 11646 | case SystemZ::CLGRJAsmL: |
| 11647 | case SystemZ::CLGRJAsmLE: |
| 11648 | case SystemZ::CLGRJAsmLH: |
| 11649 | case SystemZ::CLGRJAsmNE: |
| 11650 | case SystemZ::CLGRJAsmNH: |
| 11651 | case SystemZ::CLGRJAsmNHE: |
| 11652 | case SystemZ::CLGRJAsmNL: |
| 11653 | case SystemZ::CLGRJAsmNLE: |
| 11654 | case SystemZ::CLGRJAsmNLH: |
| 11655 | case SystemZ::CLRJAsmE: |
| 11656 | case SystemZ::CLRJAsmH: |
| 11657 | case SystemZ::CLRJAsmHE: |
| 11658 | case SystemZ::CLRJAsmL: |
| 11659 | case SystemZ::CLRJAsmLE: |
| 11660 | case SystemZ::CLRJAsmLH: |
| 11661 | case SystemZ::CLRJAsmNE: |
| 11662 | case SystemZ::CLRJAsmNH: |
| 11663 | case SystemZ::CLRJAsmNHE: |
| 11664 | case SystemZ::CLRJAsmNL: |
| 11665 | case SystemZ::CLRJAsmNLE: |
| 11666 | case SystemZ::CLRJAsmNLH: |
| 11667 | case SystemZ::CRJAsmE: |
| 11668 | case SystemZ::CRJAsmH: |
| 11669 | case SystemZ::CRJAsmHE: |
| 11670 | case SystemZ::CRJAsmL: |
| 11671 | case SystemZ::CRJAsmLE: |
| 11672 | case SystemZ::CRJAsmLH: |
| 11673 | case SystemZ::CRJAsmNE: |
| 11674 | case SystemZ::CRJAsmNH: |
| 11675 | case SystemZ::CRJAsmNHE: |
| 11676 | case SystemZ::CRJAsmNL: |
| 11677 | case SystemZ::CRJAsmNLE: |
| 11678 | case SystemZ::CRJAsmNLH: { |
| 11679 | switch (OpNum) { |
| 11680 | case 0: |
| 11681 | // op: R1 |
| 11682 | return 36; |
| 11683 | case 1: |
| 11684 | // op: R2 |
| 11685 | return 32; |
| 11686 | case 2: |
| 11687 | // op: RI4 |
| 11688 | return 16; |
| 11689 | } |
| 11690 | break; |
| 11691 | } |
| 11692 | case SystemZ::ECAG: |
| 11693 | case SystemZ::LAA: |
| 11694 | case SystemZ::LAAG: |
| 11695 | case SystemZ::LAAL: |
| 11696 | case SystemZ::LAALG: |
| 11697 | case SystemZ::LAMY: |
| 11698 | case SystemZ::LAN: |
| 11699 | case SystemZ::LANG: |
| 11700 | case SystemZ::LAO: |
| 11701 | case SystemZ::LAOG: |
| 11702 | case SystemZ::LAX: |
| 11703 | case SystemZ::LAXG: |
| 11704 | case SystemZ::LCTLG: |
| 11705 | case SystemZ::LMG: |
| 11706 | case SystemZ::LMH: |
| 11707 | case SystemZ::LMY: |
| 11708 | case SystemZ::PFCR: |
| 11709 | case SystemZ::RLL: |
| 11710 | case SystemZ::RLLG: |
| 11711 | case SystemZ::SLAG: |
| 11712 | case SystemZ::SLAK: |
| 11713 | case SystemZ::SLLG: |
| 11714 | case SystemZ::SLLK: |
| 11715 | case SystemZ::SRAG: |
| 11716 | case SystemZ::SRAK: |
| 11717 | case SystemZ::SRLG: |
| 11718 | case SystemZ::SRLK: |
| 11719 | case SystemZ::STAMY: |
| 11720 | case SystemZ::STCTG: |
| 11721 | case SystemZ::STMG: |
| 11722 | case SystemZ::STMH: |
| 11723 | case SystemZ::STMY: |
| 11724 | case SystemZ::TRACG: { |
| 11725 | switch (OpNum) { |
| 11726 | case 0: |
| 11727 | // op: R1 |
| 11728 | return 36; |
| 11729 | case 1: |
| 11730 | // op: R3 |
| 11731 | return 32; |
| 11732 | case 2: |
| 11733 | // op: B2 |
| 11734 | return 28; |
| 11735 | case 3: |
| 11736 | // op: D2 |
| 11737 | return 8; |
| 11738 | } |
| 11739 | break; |
| 11740 | } |
| 11741 | case SystemZ::AGHIK: |
| 11742 | case SystemZ::AHIK: |
| 11743 | case SystemZ::ALGHSIK: |
| 11744 | case SystemZ::ALHSIK: { |
| 11745 | switch (OpNum) { |
| 11746 | case 0: |
| 11747 | // op: R1 |
| 11748 | return 36; |
| 11749 | case 1: |
| 11750 | // op: R3 |
| 11751 | return 32; |
| 11752 | case 2: |
| 11753 | // op: I2 |
| 11754 | return 16; |
| 11755 | } |
| 11756 | break; |
| 11757 | } |
| 11758 | case SystemZ::CLCLU: |
| 11759 | case SystemZ::MVCLU: { |
| 11760 | switch (OpNum) { |
| 11761 | case 0: |
| 11762 | // op: R1 |
| 11763 | return 36; |
| 11764 | case 1: |
| 11765 | // op: R3 |
| 11766 | return 32; |
| 11767 | case 4: |
| 11768 | // op: B2 |
| 11769 | return 28; |
| 11770 | case 5: |
| 11771 | // op: D2 |
| 11772 | return 8; |
| 11773 | } |
| 11774 | break; |
| 11775 | } |
| 11776 | case SystemZ::BRASL: |
| 11777 | case SystemZ::CGFRL: |
| 11778 | case SystemZ::CGHRL: |
| 11779 | case SystemZ::CGRL: |
| 11780 | case SystemZ::CHRL: |
| 11781 | case SystemZ::CLGFRL: |
| 11782 | case SystemZ::CLGHRL: |
| 11783 | case SystemZ::CLGRL: |
| 11784 | case SystemZ::CLHRL: |
| 11785 | case SystemZ::CLRL: |
| 11786 | case SystemZ::CRL: |
| 11787 | case SystemZ::EXRL: |
| 11788 | case SystemZ::LARL: |
| 11789 | case SystemZ::LGFRL: |
| 11790 | case SystemZ::LGHRL: |
| 11791 | case SystemZ::LGRL: |
| 11792 | case SystemZ::LHRL: |
| 11793 | case SystemZ::LLGFRL: |
| 11794 | case SystemZ::LLGHRL: |
| 11795 | case SystemZ::LLHRL: |
| 11796 | case SystemZ::LRL: |
| 11797 | case SystemZ::STGRL: |
| 11798 | case SystemZ::STHRL: |
| 11799 | case SystemZ::STRL: { |
| 11800 | switch (OpNum) { |
| 11801 | case 0: |
| 11802 | // op: R1 |
| 11803 | return 36; |
| 11804 | case 1: |
| 11805 | // op: RI2 |
| 11806 | return 0; |
| 11807 | } |
| 11808 | break; |
| 11809 | } |
| 11810 | case SystemZ::VCVBGOpt: |
| 11811 | case SystemZ::VCVBOpt: { |
| 11812 | switch (OpNum) { |
| 11813 | case 0: |
| 11814 | // op: R1 |
| 11815 | return 36; |
| 11816 | case 1: |
| 11817 | // op: V2 |
| 11818 | return 10; |
| 11819 | case 2: |
| 11820 | // op: M3 |
| 11821 | return 20; |
| 11822 | case 3: |
| 11823 | // op: M4 |
| 11824 | return 16; |
| 11825 | } |
| 11826 | break; |
| 11827 | } |
| 11828 | case SystemZ::VCVB: |
| 11829 | case SystemZ::VCVBG: { |
| 11830 | switch (OpNum) { |
| 11831 | case 0: |
| 11832 | // op: R1 |
| 11833 | return 36; |
| 11834 | case 1: |
| 11835 | // op: V2 |
| 11836 | return 10; |
| 11837 | case 2: |
| 11838 | // op: M3 |
| 11839 | return 20; |
| 11840 | } |
| 11841 | break; |
| 11842 | } |
| 11843 | case SystemZ::LMD: { |
| 11844 | switch (OpNum) { |
| 11845 | case 0: |
| 11846 | // op: R1 |
| 11847 | return 36; |
| 11848 | case 2: |
| 11849 | // op: B2 |
| 11850 | return 28; |
| 11851 | case 3: |
| 11852 | // op: D2 |
| 11853 | return 16; |
| 11854 | case 1: |
| 11855 | // op: R3 |
| 11856 | return 32; |
| 11857 | case 4: |
| 11858 | // op: B4 |
| 11859 | return 12; |
| 11860 | case 5: |
| 11861 | // op: D4 |
| 11862 | return 0; |
| 11863 | } |
| 11864 | break; |
| 11865 | } |
| 11866 | case SystemZ::VLGV: { |
| 11867 | switch (OpNum) { |
| 11868 | case 0: |
| 11869 | // op: R1 |
| 11870 | return 36; |
| 11871 | case 2: |
| 11872 | // op: B2 |
| 11873 | return 28; |
| 11874 | case 3: |
| 11875 | // op: D2 |
| 11876 | return 16; |
| 11877 | case 1: |
| 11878 | // op: V3 |
| 11879 | return 10; |
| 11880 | case 4: |
| 11881 | // op: M4 |
| 11882 | return 12; |
| 11883 | } |
| 11884 | break; |
| 11885 | } |
| 11886 | case SystemZ::VLGVB: |
| 11887 | case SystemZ::VLGVF: |
| 11888 | case SystemZ::VLGVG: |
| 11889 | case SystemZ::VLGVH: { |
| 11890 | switch (OpNum) { |
| 11891 | case 0: |
| 11892 | // op: R1 |
| 11893 | return 36; |
| 11894 | case 2: |
| 11895 | // op: B2 |
| 11896 | return 28; |
| 11897 | case 3: |
| 11898 | // op: D2 |
| 11899 | return 16; |
| 11900 | case 1: |
| 11901 | // op: V3 |
| 11902 | return 10; |
| 11903 | } |
| 11904 | break; |
| 11905 | } |
| 11906 | case SystemZ::LOCAsmE: |
| 11907 | case SystemZ::LOCAsmH: |
| 11908 | case SystemZ::LOCAsmHE: |
| 11909 | case SystemZ::LOCAsmL: |
| 11910 | case SystemZ::LOCAsmLE: |
| 11911 | case SystemZ::LOCAsmLH: |
| 11912 | case SystemZ::LOCAsmM: |
| 11913 | case SystemZ::LOCAsmNE: |
| 11914 | case SystemZ::LOCAsmNH: |
| 11915 | case SystemZ::LOCAsmNHE: |
| 11916 | case SystemZ::LOCAsmNL: |
| 11917 | case SystemZ::LOCAsmNLE: |
| 11918 | case SystemZ::LOCAsmNLH: |
| 11919 | case SystemZ::LOCAsmNM: |
| 11920 | case SystemZ::LOCAsmNO: |
| 11921 | case SystemZ::LOCAsmNP: |
| 11922 | case SystemZ::LOCAsmNZ: |
| 11923 | case SystemZ::LOCAsmO: |
| 11924 | case SystemZ::LOCAsmP: |
| 11925 | case SystemZ::LOCAsmZ: |
| 11926 | case SystemZ::LOCFHAsmE: |
| 11927 | case SystemZ::LOCFHAsmH: |
| 11928 | case SystemZ::LOCFHAsmHE: |
| 11929 | case SystemZ::LOCFHAsmL: |
| 11930 | case SystemZ::LOCFHAsmLE: |
| 11931 | case SystemZ::LOCFHAsmLH: |
| 11932 | case SystemZ::LOCFHAsmM: |
| 11933 | case SystemZ::LOCFHAsmNE: |
| 11934 | case SystemZ::LOCFHAsmNH: |
| 11935 | case SystemZ::LOCFHAsmNHE: |
| 11936 | case SystemZ::LOCFHAsmNL: |
| 11937 | case SystemZ::LOCFHAsmNLE: |
| 11938 | case SystemZ::LOCFHAsmNLH: |
| 11939 | case SystemZ::LOCFHAsmNM: |
| 11940 | case SystemZ::LOCFHAsmNO: |
| 11941 | case SystemZ::LOCFHAsmNP: |
| 11942 | case SystemZ::LOCFHAsmNZ: |
| 11943 | case SystemZ::LOCFHAsmO: |
| 11944 | case SystemZ::LOCFHAsmP: |
| 11945 | case SystemZ::LOCFHAsmZ: |
| 11946 | case SystemZ::LOCGAsmE: |
| 11947 | case SystemZ::LOCGAsmH: |
| 11948 | case SystemZ::LOCGAsmHE: |
| 11949 | case SystemZ::LOCGAsmL: |
| 11950 | case SystemZ::LOCGAsmLE: |
| 11951 | case SystemZ::LOCGAsmLH: |
| 11952 | case SystemZ::LOCGAsmM: |
| 11953 | case SystemZ::LOCGAsmNE: |
| 11954 | case SystemZ::LOCGAsmNH: |
| 11955 | case SystemZ::LOCGAsmNHE: |
| 11956 | case SystemZ::LOCGAsmNL: |
| 11957 | case SystemZ::LOCGAsmNLE: |
| 11958 | case SystemZ::LOCGAsmNLH: |
| 11959 | case SystemZ::LOCGAsmNM: |
| 11960 | case SystemZ::LOCGAsmNO: |
| 11961 | case SystemZ::LOCGAsmNP: |
| 11962 | case SystemZ::LOCGAsmNZ: |
| 11963 | case SystemZ::LOCGAsmO: |
| 11964 | case SystemZ::LOCGAsmP: |
| 11965 | case SystemZ::LOCGAsmZ: { |
| 11966 | switch (OpNum) { |
| 11967 | case 0: |
| 11968 | // op: R1 |
| 11969 | return 36; |
| 11970 | case 2: |
| 11971 | // op: B2 |
| 11972 | return 28; |
| 11973 | case 3: |
| 11974 | // op: D2 |
| 11975 | return 8; |
| 11976 | } |
| 11977 | break; |
| 11978 | } |
| 11979 | case SystemZ::AFI: |
| 11980 | case SystemZ::AGFI: |
| 11981 | case SystemZ::AIH: |
| 11982 | case SystemZ::ALFI: |
| 11983 | case SystemZ::ALGFI: |
| 11984 | case SystemZ::ALSIH: |
| 11985 | case SystemZ::ALSIHN: |
| 11986 | case SystemZ::MSFI: |
| 11987 | case SystemZ::MSGFI: |
| 11988 | case SystemZ::NIHF: |
| 11989 | case SystemZ::NILF: |
| 11990 | case SystemZ::OIHF: |
| 11991 | case SystemZ::OILF: |
| 11992 | case SystemZ::SLFI: |
| 11993 | case SystemZ::SLGFI: |
| 11994 | case SystemZ::XIHF: |
| 11995 | case SystemZ::XILF: { |
| 11996 | switch (OpNum) { |
| 11997 | case 0: |
| 11998 | // op: R1 |
| 11999 | return 36; |
| 12000 | case 2: |
| 12001 | // op: I2 |
| 12002 | return 0; |
| 12003 | } |
| 12004 | break; |
| 12005 | } |
| 12006 | case SystemZ::LOCGHIAsmE: |
| 12007 | case SystemZ::LOCGHIAsmH: |
| 12008 | case SystemZ::LOCGHIAsmHE: |
| 12009 | case SystemZ::LOCGHIAsmL: |
| 12010 | case SystemZ::LOCGHIAsmLE: |
| 12011 | case SystemZ::LOCGHIAsmLH: |
| 12012 | case SystemZ::LOCGHIAsmM: |
| 12013 | case SystemZ::LOCGHIAsmNE: |
| 12014 | case SystemZ::LOCGHIAsmNH: |
| 12015 | case SystemZ::LOCGHIAsmNHE: |
| 12016 | case SystemZ::LOCGHIAsmNL: |
| 12017 | case SystemZ::LOCGHIAsmNLE: |
| 12018 | case SystemZ::LOCGHIAsmNLH: |
| 12019 | case SystemZ::LOCGHIAsmNM: |
| 12020 | case SystemZ::LOCGHIAsmNO: |
| 12021 | case SystemZ::LOCGHIAsmNP: |
| 12022 | case SystemZ::LOCGHIAsmNZ: |
| 12023 | case SystemZ::LOCGHIAsmO: |
| 12024 | case SystemZ::LOCGHIAsmP: |
| 12025 | case SystemZ::LOCGHIAsmZ: |
| 12026 | case SystemZ::LOCHHIAsmE: |
| 12027 | case SystemZ::LOCHHIAsmH: |
| 12028 | case SystemZ::LOCHHIAsmHE: |
| 12029 | case SystemZ::LOCHHIAsmL: |
| 12030 | case SystemZ::LOCHHIAsmLE: |
| 12031 | case SystemZ::LOCHHIAsmLH: |
| 12032 | case SystemZ::LOCHHIAsmM: |
| 12033 | case SystemZ::LOCHHIAsmNE: |
| 12034 | case SystemZ::LOCHHIAsmNH: |
| 12035 | case SystemZ::LOCHHIAsmNHE: |
| 12036 | case SystemZ::LOCHHIAsmNL: |
| 12037 | case SystemZ::LOCHHIAsmNLE: |
| 12038 | case SystemZ::LOCHHIAsmNLH: |
| 12039 | case SystemZ::LOCHHIAsmNM: |
| 12040 | case SystemZ::LOCHHIAsmNO: |
| 12041 | case SystemZ::LOCHHIAsmNP: |
| 12042 | case SystemZ::LOCHHIAsmNZ: |
| 12043 | case SystemZ::LOCHHIAsmO: |
| 12044 | case SystemZ::LOCHHIAsmP: |
| 12045 | case SystemZ::LOCHHIAsmZ: |
| 12046 | case SystemZ::LOCHIAsmE: |
| 12047 | case SystemZ::LOCHIAsmH: |
| 12048 | case SystemZ::LOCHIAsmHE: |
| 12049 | case SystemZ::LOCHIAsmL: |
| 12050 | case SystemZ::LOCHIAsmLE: |
| 12051 | case SystemZ::LOCHIAsmLH: |
| 12052 | case SystemZ::LOCHIAsmM: |
| 12053 | case SystemZ::LOCHIAsmNE: |
| 12054 | case SystemZ::LOCHIAsmNH: |
| 12055 | case SystemZ::LOCHIAsmNHE: |
| 12056 | case SystemZ::LOCHIAsmNL: |
| 12057 | case SystemZ::LOCHIAsmNLE: |
| 12058 | case SystemZ::LOCHIAsmNLH: |
| 12059 | case SystemZ::LOCHIAsmNM: |
| 12060 | case SystemZ::LOCHIAsmNO: |
| 12061 | case SystemZ::LOCHIAsmNP: |
| 12062 | case SystemZ::LOCHIAsmNZ: |
| 12063 | case SystemZ::LOCHIAsmO: |
| 12064 | case SystemZ::LOCHIAsmP: |
| 12065 | case SystemZ::LOCHIAsmZ: { |
| 12066 | switch (OpNum) { |
| 12067 | case 0: |
| 12068 | // op: R1 |
| 12069 | return 36; |
| 12070 | case 2: |
| 12071 | // op: I2 |
| 12072 | return 16; |
| 12073 | } |
| 12074 | break; |
| 12075 | } |
| 12076 | case SystemZ::ICMH: |
| 12077 | case SystemZ::ICMY: { |
| 12078 | switch (OpNum) { |
| 12079 | case 0: |
| 12080 | // op: R1 |
| 12081 | return 36; |
| 12082 | case 2: |
| 12083 | // op: M3 |
| 12084 | return 32; |
| 12085 | case 3: |
| 12086 | // op: B2 |
| 12087 | return 28; |
| 12088 | case 4: |
| 12089 | // op: D2 |
| 12090 | return 8; |
| 12091 | } |
| 12092 | break; |
| 12093 | } |
| 12094 | case SystemZ::RISBG: |
| 12095 | case SystemZ::RISBG32: |
| 12096 | case SystemZ::RISBGN: |
| 12097 | case SystemZ::RISBGNZ: |
| 12098 | case SystemZ::RISBGZ: |
| 12099 | case SystemZ::RISBHG: |
| 12100 | case SystemZ::RISBLG: |
| 12101 | case SystemZ::RNSBG: |
| 12102 | case SystemZ::ROSBG: |
| 12103 | case SystemZ::RXSBG: { |
| 12104 | switch (OpNum) { |
| 12105 | case 0: |
| 12106 | // op: R1 |
| 12107 | return 36; |
| 12108 | case 2: |
| 12109 | // op: R2 |
| 12110 | return 32; |
| 12111 | case 3: |
| 12112 | // op: I3 |
| 12113 | return 24; |
| 12114 | case 4: |
| 12115 | // op: I4 |
| 12116 | return 16; |
| 12117 | case 5: |
| 12118 | // op: I5 |
| 12119 | return 8; |
| 12120 | } |
| 12121 | break; |
| 12122 | } |
| 12123 | case SystemZ::RISBG32Opt: |
| 12124 | case SystemZ::RISBGNOpt: |
| 12125 | case SystemZ::RISBGNZOpt: |
| 12126 | case SystemZ::RISBGOpt: |
| 12127 | case SystemZ::RISBGZOpt: |
| 12128 | case SystemZ::RISBHGOpt: |
| 12129 | case SystemZ::RISBLGOpt: |
| 12130 | case SystemZ::RNSBGOpt: |
| 12131 | case SystemZ::ROSBGOpt: |
| 12132 | case SystemZ::RXSBGOpt: { |
| 12133 | switch (OpNum) { |
| 12134 | case 0: |
| 12135 | // op: R1 |
| 12136 | return 36; |
| 12137 | case 2: |
| 12138 | // op: R2 |
| 12139 | return 32; |
| 12140 | case 3: |
| 12141 | // op: I3 |
| 12142 | return 24; |
| 12143 | case 4: |
| 12144 | // op: I4 |
| 12145 | return 16; |
| 12146 | } |
| 12147 | break; |
| 12148 | } |
| 12149 | case SystemZ::BXHG: |
| 12150 | case SystemZ::BXLEG: |
| 12151 | case SystemZ::CDSG: |
| 12152 | case SystemZ::CDSY: |
| 12153 | case SystemZ::CSG: |
| 12154 | case SystemZ::CSY: { |
| 12155 | switch (OpNum) { |
| 12156 | case 0: |
| 12157 | // op: R1 |
| 12158 | return 36; |
| 12159 | case 2: |
| 12160 | // op: R3 |
| 12161 | return 32; |
| 12162 | case 3: |
| 12163 | // op: B2 |
| 12164 | return 28; |
| 12165 | case 4: |
| 12166 | // op: D2 |
| 12167 | return 8; |
| 12168 | } |
| 12169 | break; |
| 12170 | } |
| 12171 | case SystemZ::BRXHG: |
| 12172 | case SystemZ::BRXLG: { |
| 12173 | switch (OpNum) { |
| 12174 | case 0: |
| 12175 | // op: R1 |
| 12176 | return 36; |
| 12177 | case 2: |
| 12178 | // op: R3 |
| 12179 | return 32; |
| 12180 | case 3: |
| 12181 | // op: RI2 |
| 12182 | return 16; |
| 12183 | } |
| 12184 | break; |
| 12185 | } |
| 12186 | case SystemZ::BRCTH: { |
| 12187 | switch (OpNum) { |
| 12188 | case 0: |
| 12189 | // op: R1 |
| 12190 | return 36; |
| 12191 | case 2: |
| 12192 | // op: RI2 |
| 12193 | return 0; |
| 12194 | } |
| 12195 | break; |
| 12196 | } |
| 12197 | case SystemZ::CLGT: |
| 12198 | case SystemZ::CLGTAsm: |
| 12199 | case SystemZ::CLT: |
| 12200 | case SystemZ::CLTAsm: |
| 12201 | case SystemZ::STOCAsm: |
| 12202 | case SystemZ::STOCFHAsm: |
| 12203 | case SystemZ::STOCGAsm: { |
| 12204 | switch (OpNum) { |
| 12205 | case 0: |
| 12206 | // op: R1 |
| 12207 | return 36; |
| 12208 | case 3: |
| 12209 | // op: M3 |
| 12210 | return 32; |
| 12211 | case 1: |
| 12212 | // op: B2 |
| 12213 | return 28; |
| 12214 | case 2: |
| 12215 | // op: D2 |
| 12216 | return 8; |
| 12217 | } |
| 12218 | break; |
| 12219 | } |
| 12220 | case SystemZ::LOCGHIAsm: |
| 12221 | case SystemZ::LOCHHIAsm: |
| 12222 | case SystemZ::LOCHIAsm: { |
| 12223 | switch (OpNum) { |
| 12224 | case 0: |
| 12225 | // op: R1 |
| 12226 | return 36; |
| 12227 | case 3: |
| 12228 | // op: M3 |
| 12229 | return 32; |
| 12230 | case 2: |
| 12231 | // op: I2 |
| 12232 | return 16; |
| 12233 | } |
| 12234 | break; |
| 12235 | } |
| 12236 | case SystemZ::LCBB: { |
| 12237 | switch (OpNum) { |
| 12238 | case 0: |
| 12239 | // op: R1 |
| 12240 | return 36; |
| 12241 | case 3: |
| 12242 | // op: X2 |
| 12243 | return 32; |
| 12244 | case 1: |
| 12245 | // op: B2 |
| 12246 | return 28; |
| 12247 | case 2: |
| 12248 | // op: D2 |
| 12249 | return 16; |
| 12250 | case 4: |
| 12251 | // op: M3 |
| 12252 | return 12; |
| 12253 | } |
| 12254 | break; |
| 12255 | } |
| 12256 | case SystemZ::CDB: |
| 12257 | case SystemZ::CEB: |
| 12258 | case SystemZ::KDB: |
| 12259 | case SystemZ::KEB: |
| 12260 | case SystemZ::LDE: |
| 12261 | case SystemZ::LDE32: |
| 12262 | case SystemZ::LDEB: |
| 12263 | case SystemZ::LXD: |
| 12264 | case SystemZ::LXDB: |
| 12265 | case SystemZ::LXE: |
| 12266 | case SystemZ::LXEB: |
| 12267 | case SystemZ::SQD: |
| 12268 | case SystemZ::SQDB: |
| 12269 | case SystemZ::SQE: |
| 12270 | case SystemZ::SQEB: |
| 12271 | case SystemZ::TCDB: |
| 12272 | case SystemZ::TCEB: |
| 12273 | case SystemZ::TCXB: |
| 12274 | case SystemZ::TDCDT: |
| 12275 | case SystemZ::TDCET: |
| 12276 | case SystemZ::TDCXT: |
| 12277 | case SystemZ::TDGDT: |
| 12278 | case SystemZ::TDGET: |
| 12279 | case SystemZ::TDGXT: { |
| 12280 | switch (OpNum) { |
| 12281 | case 0: |
| 12282 | // op: R1 |
| 12283 | return 36; |
| 12284 | case 3: |
| 12285 | // op: X2 |
| 12286 | return 32; |
| 12287 | case 1: |
| 12288 | // op: B2 |
| 12289 | return 28; |
| 12290 | case 2: |
| 12291 | // op: D2 |
| 12292 | return 16; |
| 12293 | } |
| 12294 | break; |
| 12295 | } |
| 12296 | case SystemZ::CG: |
| 12297 | case SystemZ::CGF: |
| 12298 | case SystemZ::CGH: |
| 12299 | case SystemZ::CHF: |
| 12300 | case SystemZ::CHY: |
| 12301 | case SystemZ::CLG: |
| 12302 | case SystemZ::CLGF: |
| 12303 | case SystemZ::CLHF: |
| 12304 | case SystemZ::CLY: |
| 12305 | case SystemZ::CVDG: |
| 12306 | case SystemZ::CVDY: |
| 12307 | case SystemZ::CY: |
| 12308 | case SystemZ::LAEY: |
| 12309 | case SystemZ::LAT: |
| 12310 | case SystemZ::LAY: |
| 12311 | case SystemZ::LB: |
| 12312 | case SystemZ::LBH: |
| 12313 | case SystemZ::LDY: |
| 12314 | case SystemZ::LE16Y: |
| 12315 | case SystemZ::LEY: |
| 12316 | case SystemZ::LFH: |
| 12317 | case SystemZ::LFHAT: |
| 12318 | case SystemZ::LG: |
| 12319 | case SystemZ::LGAT: |
| 12320 | case SystemZ::LGB: |
| 12321 | case SystemZ::LGF: |
| 12322 | case SystemZ::LGG: |
| 12323 | case SystemZ::LGH: |
| 12324 | case SystemZ::LGSC: |
| 12325 | case SystemZ::LHH: |
| 12326 | case SystemZ::LHY: |
| 12327 | case SystemZ::LLC: |
| 12328 | case SystemZ::LLCH: |
| 12329 | case SystemZ::LLGC: |
| 12330 | case SystemZ::LLGF: |
| 12331 | case SystemZ::LLGFAT: |
| 12332 | case SystemZ::LLGFSG: |
| 12333 | case SystemZ::LLGH: |
| 12334 | case SystemZ::LLGT: |
| 12335 | case SystemZ::LLGTAT: |
| 12336 | case SystemZ::LLH: |
| 12337 | case SystemZ::LLHH: |
| 12338 | case SystemZ::LLXAB: |
| 12339 | case SystemZ::LLXAF: |
| 12340 | case SystemZ::LLXAG: |
| 12341 | case SystemZ::LLXAH: |
| 12342 | case SystemZ::LLXAQ: |
| 12343 | case SystemZ::LLZRGF: |
| 12344 | case SystemZ::LPQ: |
| 12345 | case SystemZ::LRAG: |
| 12346 | case SystemZ::LRAY: |
| 12347 | case SystemZ::LRV: |
| 12348 | case SystemZ::LRVG: |
| 12349 | case SystemZ::LRVH: |
| 12350 | case SystemZ::LT: |
| 12351 | case SystemZ::LTG: |
| 12352 | case SystemZ::LTGF: |
| 12353 | case SystemZ::LXAB: |
| 12354 | case SystemZ::LXAF: |
| 12355 | case SystemZ::LXAG: |
| 12356 | case SystemZ::LXAH: |
| 12357 | case SystemZ::LXAQ: |
| 12358 | case SystemZ::LY: |
| 12359 | case SystemZ::LZRF: |
| 12360 | case SystemZ::LZRG: |
| 12361 | case SystemZ::NTSTG: |
| 12362 | case SystemZ::STCH: |
| 12363 | case SystemZ::STCY: |
| 12364 | case SystemZ::STDY: |
| 12365 | case SystemZ::STE16Y: |
| 12366 | case SystemZ::STEY: |
| 12367 | case SystemZ::STFH: |
| 12368 | case SystemZ::STG: |
| 12369 | case SystemZ::STGSC: |
| 12370 | case SystemZ::STHH: |
| 12371 | case SystemZ::STHY: |
| 12372 | case SystemZ::STPQ: |
| 12373 | case SystemZ::STRV: |
| 12374 | case SystemZ::STRVG: |
| 12375 | case SystemZ::STRVH: |
| 12376 | case SystemZ::STY: { |
| 12377 | switch (OpNum) { |
| 12378 | case 0: |
| 12379 | // op: R1 |
| 12380 | return 36; |
| 12381 | case 3: |
| 12382 | // op: X2 |
| 12383 | return 32; |
| 12384 | case 1: |
| 12385 | // op: B2 |
| 12386 | return 28; |
| 12387 | case 2: |
| 12388 | // op: D2 |
| 12389 | return 8; |
| 12390 | } |
| 12391 | break; |
| 12392 | } |
| 12393 | case SystemZ::STOC: |
| 12394 | case SystemZ::STOCFH: |
| 12395 | case SystemZ::STOCG: { |
| 12396 | switch (OpNum) { |
| 12397 | case 0: |
| 12398 | // op: R1 |
| 12399 | return 36; |
| 12400 | case 4: |
| 12401 | // op: M3 |
| 12402 | return 32; |
| 12403 | case 1: |
| 12404 | // op: B2 |
| 12405 | return 28; |
| 12406 | case 2: |
| 12407 | // op: D2 |
| 12408 | return 8; |
| 12409 | } |
| 12410 | break; |
| 12411 | } |
| 12412 | case SystemZ::LOCAsm: |
| 12413 | case SystemZ::LOCFHAsm: |
| 12414 | case SystemZ::LOCGAsm: { |
| 12415 | switch (OpNum) { |
| 12416 | case 0: |
| 12417 | // op: R1 |
| 12418 | return 36; |
| 12419 | case 4: |
| 12420 | // op: M3 |
| 12421 | return 32; |
| 12422 | case 2: |
| 12423 | // op: B2 |
| 12424 | return 28; |
| 12425 | case 3: |
| 12426 | // op: D2 |
| 12427 | return 8; |
| 12428 | } |
| 12429 | break; |
| 12430 | } |
| 12431 | case SystemZ::LOCGHI: |
| 12432 | case SystemZ::LOCHHI: |
| 12433 | case SystemZ::LOCHI: { |
| 12434 | switch (OpNum) { |
| 12435 | case 0: |
| 12436 | // op: R1 |
| 12437 | return 36; |
| 12438 | case 4: |
| 12439 | // op: M3 |
| 12440 | return 32; |
| 12441 | case 2: |
| 12442 | // op: I2 |
| 12443 | return 16; |
| 12444 | } |
| 12445 | break; |
| 12446 | } |
| 12447 | case SystemZ::ADB: |
| 12448 | case SystemZ::AEB: |
| 12449 | case SystemZ::DDB: |
| 12450 | case SystemZ::DEB: |
| 12451 | case SystemZ::MDB: |
| 12452 | case SystemZ::MDEB: |
| 12453 | case SystemZ::MEE: |
| 12454 | case SystemZ::MEEB: |
| 12455 | case SystemZ::MXDB: |
| 12456 | case SystemZ::SDB: |
| 12457 | case SystemZ::SEB: { |
| 12458 | switch (OpNum) { |
| 12459 | case 0: |
| 12460 | // op: R1 |
| 12461 | return 36; |
| 12462 | case 4: |
| 12463 | // op: X2 |
| 12464 | return 32; |
| 12465 | case 2: |
| 12466 | // op: B2 |
| 12467 | return 28; |
| 12468 | case 3: |
| 12469 | // op: D2 |
| 12470 | return 16; |
| 12471 | } |
| 12472 | break; |
| 12473 | } |
| 12474 | case SystemZ::AG: |
| 12475 | case SystemZ::AGF: |
| 12476 | case SystemZ::AGH: |
| 12477 | case SystemZ::AHY: |
| 12478 | case SystemZ::ALC: |
| 12479 | case SystemZ::ALCG: |
| 12480 | case SystemZ::ALG: |
| 12481 | case SystemZ::ALGF: |
| 12482 | case SystemZ::ALY: |
| 12483 | case SystemZ::AY: |
| 12484 | case SystemZ::BCTG: |
| 12485 | case SystemZ::CVBG: |
| 12486 | case SystemZ::CVBY: |
| 12487 | case SystemZ::DL: |
| 12488 | case SystemZ::DLG: |
| 12489 | case SystemZ::DSG: |
| 12490 | case SystemZ::DSGF: |
| 12491 | case SystemZ::IC32Y: |
| 12492 | case SystemZ::ICY: |
| 12493 | case SystemZ::MFY: |
| 12494 | case SystemZ::MG: |
| 12495 | case SystemZ::MGH: |
| 12496 | case SystemZ::MHY: |
| 12497 | case SystemZ::ML: |
| 12498 | case SystemZ::MLG: |
| 12499 | case SystemZ::MSC: |
| 12500 | case SystemZ::MSG: |
| 12501 | case SystemZ::MSGC: |
| 12502 | case SystemZ::MSGF: |
| 12503 | case SystemZ::MSY: |
| 12504 | case SystemZ::NG: |
| 12505 | case SystemZ::NY: |
| 12506 | case SystemZ::OG: |
| 12507 | case SystemZ::OY: |
| 12508 | case SystemZ::SG: |
| 12509 | case SystemZ::SGF: |
| 12510 | case SystemZ::SGH: |
| 12511 | case SystemZ::SHY: |
| 12512 | case SystemZ::SLB: |
| 12513 | case SystemZ::SLBG: |
| 12514 | case SystemZ::SLG: |
| 12515 | case SystemZ::SLGF: |
| 12516 | case SystemZ::SLY: |
| 12517 | case SystemZ::SY: |
| 12518 | case SystemZ::XG: |
| 12519 | case SystemZ::XY: { |
| 12520 | switch (OpNum) { |
| 12521 | case 0: |
| 12522 | // op: R1 |
| 12523 | return 36; |
| 12524 | case 4: |
| 12525 | // op: X2 |
| 12526 | return 32; |
| 12527 | case 2: |
| 12528 | // op: B2 |
| 12529 | return 28; |
| 12530 | case 3: |
| 12531 | // op: D2 |
| 12532 | return 8; |
| 12533 | } |
| 12534 | break; |
| 12535 | } |
| 12536 | case SystemZ::LOC: |
| 12537 | case SystemZ::LOCFH: |
| 12538 | case SystemZ::LOCG: { |
| 12539 | switch (OpNum) { |
| 12540 | case 0: |
| 12541 | // op: R1 |
| 12542 | return 36; |
| 12543 | case 5: |
| 12544 | // op: M3 |
| 12545 | return 32; |
| 12546 | case 2: |
| 12547 | // op: B2 |
| 12548 | return 28; |
| 12549 | case 3: |
| 12550 | // op: D2 |
| 12551 | return 8; |
| 12552 | } |
| 12553 | break; |
| 12554 | } |
| 12555 | case SystemZ::CGRT: |
| 12556 | case SystemZ::CGRTAsm: |
| 12557 | case SystemZ::CLGRT: |
| 12558 | case SystemZ::CLGRTAsm: |
| 12559 | case SystemZ::CLRT: |
| 12560 | case SystemZ::CLRTAsm: |
| 12561 | case SystemZ::CRT: |
| 12562 | case SystemZ::CRTAsm: |
| 12563 | case SystemZ::POPCNTOpt: |
| 12564 | case SystemZ::PPA: |
| 12565 | case SystemZ::SSKE: { |
| 12566 | switch (OpNum) { |
| 12567 | case 0: |
| 12568 | // op: R1 |
| 12569 | return 4; |
| 12570 | case 1: |
| 12571 | // op: R2 |
| 12572 | return 0; |
| 12573 | case 2: |
| 12574 | // op: M3 |
| 12575 | return 12; |
| 12576 | } |
| 12577 | break; |
| 12578 | } |
| 12579 | case SystemZ::CSDTR: |
| 12580 | case SystemZ::CSXTR: |
| 12581 | case SystemZ::LDETR: |
| 12582 | case SystemZ::LXDTR: { |
| 12583 | switch (OpNum) { |
| 12584 | case 0: |
| 12585 | // op: R1 |
| 12586 | return 4; |
| 12587 | case 1: |
| 12588 | // op: R2 |
| 12589 | return 0; |
| 12590 | case 2: |
| 12591 | // op: M4 |
| 12592 | return 8; |
| 12593 | } |
| 12594 | break; |
| 12595 | } |
| 12596 | case SystemZ::ADTRA: |
| 12597 | case SystemZ::AXTRA: |
| 12598 | case SystemZ::CRDTE: |
| 12599 | case SystemZ::DDTRA: |
| 12600 | case SystemZ::DXTRA: |
| 12601 | case SystemZ::IDTE: |
| 12602 | case SystemZ::IPTE: |
| 12603 | case SystemZ::MDTRA: |
| 12604 | case SystemZ::MXTRA: |
| 12605 | case SystemZ::RDP: |
| 12606 | case SystemZ::SDTRA: |
| 12607 | case SystemZ::SXTRA: { |
| 12608 | switch (OpNum) { |
| 12609 | case 0: |
| 12610 | // op: R1 |
| 12611 | return 4; |
| 12612 | case 1: |
| 12613 | // op: R2 |
| 12614 | return 0; |
| 12615 | case 2: |
| 12616 | // op: R3 |
| 12617 | return 12; |
| 12618 | case 3: |
| 12619 | // op: M4 |
| 12620 | return 8; |
| 12621 | } |
| 12622 | break; |
| 12623 | } |
| 12624 | case SystemZ::ADTR: |
| 12625 | case SystemZ::AGRK: |
| 12626 | case SystemZ::AHHHR: |
| 12627 | case SystemZ::AHHLR: |
| 12628 | case SystemZ::ALGRK: |
| 12629 | case SystemZ::ALHHHR: |
| 12630 | case SystemZ::ALHHLR: |
| 12631 | case SystemZ::ALRK: |
| 12632 | case SystemZ::ARK: |
| 12633 | case SystemZ::AXTR: |
| 12634 | case SystemZ::BDEPG: |
| 12635 | case SystemZ::BEXTG: |
| 12636 | case SystemZ::CPSDRdd: |
| 12637 | case SystemZ::CPSDRdh: |
| 12638 | case SystemZ::CPSDRds: |
| 12639 | case SystemZ::CPSDRhd: |
| 12640 | case SystemZ::CPSDRhh: |
| 12641 | case SystemZ::CPSDRhs: |
| 12642 | case SystemZ::CPSDRsd: |
| 12643 | case SystemZ::CPSDRsh: |
| 12644 | case SystemZ::CPSDRss: |
| 12645 | case SystemZ::CRDTEOpt: |
| 12646 | case SystemZ::DDTR: |
| 12647 | case SystemZ::DXTR: |
| 12648 | case SystemZ::IDTEOpt: |
| 12649 | case SystemZ::IEDTR: |
| 12650 | case SystemZ::IEXTR: |
| 12651 | case SystemZ::IPTEOpt: |
| 12652 | case SystemZ::KMA: |
| 12653 | case SystemZ::KMCTR: |
| 12654 | case SystemZ::MDTR: |
| 12655 | case SystemZ::MGRK: |
| 12656 | case SystemZ::MSGRKC: |
| 12657 | case SystemZ::MSRKC: |
| 12658 | case SystemZ::MXTR: |
| 12659 | case SystemZ::NCGRK: |
| 12660 | case SystemZ::NCRK: |
| 12661 | case SystemZ::NGRK: |
| 12662 | case SystemZ::NNGRK: |
| 12663 | case SystemZ::NNRK: |
| 12664 | case SystemZ::NOGRK: |
| 12665 | case SystemZ::NORK: |
| 12666 | case SystemZ::NRK: |
| 12667 | case SystemZ::NXGRK: |
| 12668 | case SystemZ::NXRK: |
| 12669 | case SystemZ::OCGRK: |
| 12670 | case SystemZ::OCRK: |
| 12671 | case SystemZ::OGRK: |
| 12672 | case SystemZ::ORK: |
| 12673 | case SystemZ::RDPOpt: |
| 12674 | case SystemZ::SDTR: |
| 12675 | case SystemZ::SGRK: |
| 12676 | case SystemZ::SHHHR: |
| 12677 | case SystemZ::SHHLR: |
| 12678 | case SystemZ::SLGRK: |
| 12679 | case SystemZ::SLHHHR: |
| 12680 | case SystemZ::SLHHLR: |
| 12681 | case SystemZ::SLRK: |
| 12682 | case SystemZ::SRK: |
| 12683 | case SystemZ::SXTR: |
| 12684 | case SystemZ::XGRK: |
| 12685 | case SystemZ::XRK: { |
| 12686 | switch (OpNum) { |
| 12687 | case 0: |
| 12688 | // op: R1 |
| 12689 | return 4; |
| 12690 | case 1: |
| 12691 | // op: R2 |
| 12692 | return 0; |
| 12693 | case 2: |
| 12694 | // op: R3 |
| 12695 | return 12; |
| 12696 | } |
| 12697 | break; |
| 12698 | } |
| 12699 | case SystemZ::CU12: |
| 12700 | case SystemZ::CU14: |
| 12701 | case SystemZ::CU21: |
| 12702 | case SystemZ::CU24: |
| 12703 | case SystemZ::CUTFU: |
| 12704 | case SystemZ::CUUTF: |
| 12705 | case SystemZ::KIMDOpt: |
| 12706 | case SystemZ::KLMDOpt: |
| 12707 | case SystemZ::TROO: |
| 12708 | case SystemZ::TROT: |
| 12709 | case SystemZ::TRTO: |
| 12710 | case SystemZ::TRTT: { |
| 12711 | switch (OpNum) { |
| 12712 | case 0: |
| 12713 | // op: R1 |
| 12714 | return 4; |
| 12715 | case 1: |
| 12716 | // op: R2 |
| 12717 | return 0; |
| 12718 | case 4: |
| 12719 | // op: M3 |
| 12720 | return 12; |
| 12721 | } |
| 12722 | break; |
| 12723 | } |
| 12724 | case SystemZ::DFLTCC: { |
| 12725 | switch (OpNum) { |
| 12726 | case 0: |
| 12727 | // op: R1 |
| 12728 | return 4; |
| 12729 | case 1: |
| 12730 | // op: R2 |
| 12731 | return 0; |
| 12732 | case 4: |
| 12733 | // op: R3 |
| 12734 | return 12; |
| 12735 | } |
| 12736 | break; |
| 12737 | } |
| 12738 | case SystemZ::BAKR: |
| 12739 | case SystemZ::BALR: |
| 12740 | case SystemZ::BASR: |
| 12741 | case SystemZ::BASSM: |
| 12742 | case SystemZ::BCRAsm: |
| 12743 | case SystemZ::BSA: |
| 12744 | case SystemZ::BSG: |
| 12745 | case SystemZ::BSM: |
| 12746 | case SystemZ::CDBR: |
| 12747 | case SystemZ::CDFBR: |
| 12748 | case SystemZ::CDFR: |
| 12749 | case SystemZ::CDGBR: |
| 12750 | case SystemZ::CDGR: |
| 12751 | case SystemZ::CDGTR: |
| 12752 | case SystemZ::CDR: |
| 12753 | case SystemZ::CDSTR: |
| 12754 | case SystemZ::CDTR: |
| 12755 | case SystemZ::CDUTR: |
| 12756 | case SystemZ::CEBR: |
| 12757 | case SystemZ::CEDTR: |
| 12758 | case SystemZ::CEFBR: |
| 12759 | case SystemZ::CEFR: |
| 12760 | case SystemZ::CEGBR: |
| 12761 | case SystemZ::CEGR: |
| 12762 | case SystemZ::CER: |
| 12763 | case SystemZ::CEXTR: |
| 12764 | case SystemZ::CGFR: |
| 12765 | case SystemZ::CGR: |
| 12766 | case SystemZ::CGRTAsmE: |
| 12767 | case SystemZ::CGRTAsmH: |
| 12768 | case SystemZ::CGRTAsmHE: |
| 12769 | case SystemZ::CGRTAsmL: |
| 12770 | case SystemZ::CGRTAsmLE: |
| 12771 | case SystemZ::CGRTAsmLH: |
| 12772 | case SystemZ::CGRTAsmNE: |
| 12773 | case SystemZ::CGRTAsmNH: |
| 12774 | case SystemZ::CGRTAsmNHE: |
| 12775 | case SystemZ::CGRTAsmNL: |
| 12776 | case SystemZ::CGRTAsmNLE: |
| 12777 | case SystemZ::CGRTAsmNLH: |
| 12778 | case SystemZ::CHHR: |
| 12779 | case SystemZ::CHLR: |
| 12780 | case SystemZ::CKSM: |
| 12781 | case SystemZ::CLCL: |
| 12782 | case SystemZ::CLGFR: |
| 12783 | case SystemZ::CLGR: |
| 12784 | case SystemZ::CLGRTAsmE: |
| 12785 | case SystemZ::CLGRTAsmH: |
| 12786 | case SystemZ::CLGRTAsmHE: |
| 12787 | case SystemZ::CLGRTAsmL: |
| 12788 | case SystemZ::CLGRTAsmLE: |
| 12789 | case SystemZ::CLGRTAsmLH: |
| 12790 | case SystemZ::CLGRTAsmNE: |
| 12791 | case SystemZ::CLGRTAsmNH: |
| 12792 | case SystemZ::CLGRTAsmNHE: |
| 12793 | case SystemZ::CLGRTAsmNL: |
| 12794 | case SystemZ::CLGRTAsmNLE: |
| 12795 | case SystemZ::CLGRTAsmNLH: |
| 12796 | case SystemZ::CLHHR: |
| 12797 | case SystemZ::CLHLR: |
| 12798 | case SystemZ::CLR: |
| 12799 | case SystemZ::CLRTAsmE: |
| 12800 | case SystemZ::CLRTAsmH: |
| 12801 | case SystemZ::CLRTAsmHE: |
| 12802 | case SystemZ::CLRTAsmL: |
| 12803 | case SystemZ::CLRTAsmLE: |
| 12804 | case SystemZ::CLRTAsmLH: |
| 12805 | case SystemZ::CLRTAsmNE: |
| 12806 | case SystemZ::CLRTAsmNH: |
| 12807 | case SystemZ::CLRTAsmNHE: |
| 12808 | case SystemZ::CLRTAsmNL: |
| 12809 | case SystemZ::CLRTAsmNLE: |
| 12810 | case SystemZ::CLRTAsmNLH: |
| 12811 | case SystemZ::CLST: |
| 12812 | case SystemZ::CLZG: |
| 12813 | case SystemZ::CMPSC: |
| 12814 | case SystemZ::CPYA: |
| 12815 | case SystemZ::CR: |
| 12816 | case SystemZ::CRTAsmE: |
| 12817 | case SystemZ::CRTAsmH: |
| 12818 | case SystemZ::CRTAsmHE: |
| 12819 | case SystemZ::CRTAsmL: |
| 12820 | case SystemZ::CRTAsmLE: |
| 12821 | case SystemZ::CRTAsmLH: |
| 12822 | case SystemZ::CRTAsmNE: |
| 12823 | case SystemZ::CRTAsmNH: |
| 12824 | case SystemZ::CRTAsmNHE: |
| 12825 | case SystemZ::CRTAsmNL: |
| 12826 | case SystemZ::CRTAsmNLE: |
| 12827 | case SystemZ::CRTAsmNLH: |
| 12828 | case SystemZ::CTZG: |
| 12829 | case SystemZ::CU12Opt: |
| 12830 | case SystemZ::CU14Opt: |
| 12831 | case SystemZ::CU21Opt: |
| 12832 | case SystemZ::CU24Opt: |
| 12833 | case SystemZ::CU41: |
| 12834 | case SystemZ::CU42: |
| 12835 | case SystemZ::CUDTR: |
| 12836 | case SystemZ::CUSE: |
| 12837 | case SystemZ::CUTFUOpt: |
| 12838 | case SystemZ::CUUTFOpt: |
| 12839 | case SystemZ::CUXTR: |
| 12840 | case SystemZ::CXBR: |
| 12841 | case SystemZ::CXFBR: |
| 12842 | case SystemZ::CXFR: |
| 12843 | case SystemZ::CXGBR: |
| 12844 | case SystemZ::CXGR: |
| 12845 | case SystemZ::CXGTR: |
| 12846 | case SystemZ::CXR: |
| 12847 | case SystemZ::CXSTR: |
| 12848 | case SystemZ::CXTR: |
| 12849 | case SystemZ::CXUTR: |
| 12850 | case SystemZ::EAR: |
| 12851 | case SystemZ::ECCTR: |
| 12852 | case SystemZ::ECPGA: |
| 12853 | case SystemZ::EEDTR: |
| 12854 | case SystemZ::EEXTR: |
| 12855 | case SystemZ::EPCTR: |
| 12856 | case SystemZ::EPSW: |
| 12857 | case SystemZ::EREG: |
| 12858 | case SystemZ::EREGG: |
| 12859 | case SystemZ::ESDTR: |
| 12860 | case SystemZ::ESTA: |
| 12861 | case SystemZ::ESXTR: |
| 12862 | case SystemZ::FIDR: |
| 12863 | case SystemZ::FIER: |
| 12864 | case SystemZ::FIXR: |
| 12865 | case SystemZ::FLOGR: |
| 12866 | case SystemZ::HDR: |
| 12867 | case SystemZ::HER: |
| 12868 | case SystemZ::IPTEOptOpt: |
| 12869 | case SystemZ::IRBM: |
| 12870 | case SystemZ::KDBR: |
| 12871 | case SystemZ::KDTR: |
| 12872 | case SystemZ::KEBR: |
| 12873 | case SystemZ::KM: |
| 12874 | case SystemZ::KMC: |
| 12875 | case SystemZ::KMF: |
| 12876 | case SystemZ::KMO: |
| 12877 | case SystemZ::KXBR: |
| 12878 | case SystemZ::KXTR: |
| 12879 | case SystemZ::LBR: |
| 12880 | case SystemZ::LCDBR: |
| 12881 | case SystemZ::LCDFR: |
| 12882 | case SystemZ::LCDFR_16: |
| 12883 | case SystemZ::LCDFR_32: |
| 12884 | case SystemZ::LCDR: |
| 12885 | case SystemZ::LCEBR: |
| 12886 | case SystemZ::LCER: |
| 12887 | case SystemZ::LCGFR: |
| 12888 | case SystemZ::LCGR: |
| 12889 | case SystemZ::LCR: |
| 12890 | case SystemZ::LCXBR: |
| 12891 | case SystemZ::LCXR: |
| 12892 | case SystemZ::LDEBR: |
| 12893 | case SystemZ::LDER: |
| 12894 | case SystemZ::LDGR: |
| 12895 | case SystemZ::LDR: |
| 12896 | case SystemZ::LDR16: |
| 12897 | case SystemZ::LDR32: |
| 12898 | case SystemZ::LDXBR: |
| 12899 | case SystemZ::LDXR: |
| 12900 | case SystemZ::LEDBR: |
| 12901 | case SystemZ::LEDR: |
| 12902 | case SystemZ::LER: |
| 12903 | case SystemZ::LER16: |
| 12904 | case SystemZ::LEXBR: |
| 12905 | case SystemZ::LEXR: |
| 12906 | case SystemZ::LGBR: |
| 12907 | case SystemZ::LGDR: |
| 12908 | case SystemZ::LGFR: |
| 12909 | case SystemZ::LGHR: |
| 12910 | case SystemZ::LGR: |
| 12911 | case SystemZ::LHR: |
| 12912 | case SystemZ::LLCR: |
| 12913 | case SystemZ::LLGCR: |
| 12914 | case SystemZ::LLGFR: |
| 12915 | case SystemZ::LLGHR: |
| 12916 | case SystemZ::LLGTR: |
| 12917 | case SystemZ::LLHR: |
| 12918 | case SystemZ::LNDBR: |
| 12919 | case SystemZ::LNDFR: |
| 12920 | case SystemZ::LNDFR_16: |
| 12921 | case SystemZ::LNDFR_32: |
| 12922 | case SystemZ::LNDR: |
| 12923 | case SystemZ::LNEBR: |
| 12924 | case SystemZ::LNER: |
| 12925 | case SystemZ::LNGFR: |
| 12926 | case SystemZ::LNGR: |
| 12927 | case SystemZ::LNR: |
| 12928 | case SystemZ::LNXBR: |
| 12929 | case SystemZ::LNXR: |
| 12930 | case SystemZ::LPDBR: |
| 12931 | case SystemZ::LPDFR: |
| 12932 | case SystemZ::LPDFR_16: |
| 12933 | case SystemZ::LPDFR_32: |
| 12934 | case SystemZ::LPDR: |
| 12935 | case SystemZ::LPEBR: |
| 12936 | case SystemZ::LPER: |
| 12937 | case SystemZ::LPGFR: |
| 12938 | case SystemZ::LPGR: |
| 12939 | case SystemZ::LPR: |
| 12940 | case SystemZ::LPXBR: |
| 12941 | case SystemZ::LPXR: |
| 12942 | case SystemZ::LR: |
| 12943 | case SystemZ::LRDR: |
| 12944 | case SystemZ::LRER: |
| 12945 | case SystemZ::LRVGR: |
| 12946 | case SystemZ::LRVR: |
| 12947 | case SystemZ::LTDBR: |
| 12948 | case SystemZ::LTDR: |
| 12949 | case SystemZ::LTDTR: |
| 12950 | case SystemZ::LTEBR: |
| 12951 | case SystemZ::LTER: |
| 12952 | case SystemZ::LTGFR: |
| 12953 | case SystemZ::LTGR: |
| 12954 | case SystemZ::LTR: |
| 12955 | case SystemZ::LTXBR: |
| 12956 | case SystemZ::LTXR: |
| 12957 | case SystemZ::LTXTR: |
| 12958 | case SystemZ::LURA: |
| 12959 | case SystemZ::LURAG: |
| 12960 | case SystemZ::LXDBR: |
| 12961 | case SystemZ::LXDR: |
| 12962 | case SystemZ::LXEBR: |
| 12963 | case SystemZ::LXER: |
| 12964 | case SystemZ::LXR: |
| 12965 | case SystemZ::MVCL: |
| 12966 | case SystemZ::MVPG: |
| 12967 | case SystemZ::MVST: |
| 12968 | case SystemZ::NOTGR: |
| 12969 | case SystemZ::NOTR: |
| 12970 | case SystemZ::PGIN: |
| 12971 | case SystemZ::PGOUT: |
| 12972 | case SystemZ::POPCNT: |
| 12973 | case SystemZ::PPNO: |
| 12974 | case SystemZ::PRNO: |
| 12975 | case SystemZ::PT: |
| 12976 | case SystemZ::PTI: |
| 12977 | case SystemZ::RRBE: |
| 12978 | case SystemZ::RRBM: |
| 12979 | case SystemZ::SAR: |
| 12980 | case SystemZ::SCCTR: |
| 12981 | case SystemZ::SORTL: |
| 12982 | case SystemZ::SPCTR: |
| 12983 | case SystemZ::SQDBR: |
| 12984 | case SystemZ::SQDR: |
| 12985 | case SystemZ::SQEBR: |
| 12986 | case SystemZ::SQER: |
| 12987 | case SystemZ::SQXBR: |
| 12988 | case SystemZ::SQXR: |
| 12989 | case SystemZ::SRST: |
| 12990 | case SystemZ::SRSTU: |
| 12991 | case SystemZ::SSKEOpt: |
| 12992 | case SystemZ::STURA: |
| 12993 | case SystemZ::STURG: |
| 12994 | case SystemZ::TAR: |
| 12995 | case SystemZ::TB: |
| 12996 | case SystemZ::THDER: |
| 12997 | case SystemZ::THDR: |
| 12998 | case SystemZ::TPEI: |
| 12999 | case SystemZ::TRE: |
| 13000 | case SystemZ::TROOOpt: |
| 13001 | case SystemZ::TROTOpt: |
| 13002 | case SystemZ::TRTOOpt: |
| 13003 | case SystemZ::TRTTOpt: { |
| 13004 | switch (OpNum) { |
| 13005 | case 0: |
| 13006 | // op: R1 |
| 13007 | return 4; |
| 13008 | case 1: |
| 13009 | // op: R2 |
| 13010 | return 0; |
| 13011 | } |
| 13012 | break; |
| 13013 | } |
| 13014 | case SystemZ::CDFBRA: |
| 13015 | case SystemZ::CDFTR: |
| 13016 | case SystemZ::CDGBRA: |
| 13017 | case SystemZ::CDGTRA: |
| 13018 | case SystemZ::CDLFBR: |
| 13019 | case SystemZ::CDLFTR: |
| 13020 | case SystemZ::CDLGBR: |
| 13021 | case SystemZ::CDLGTR: |
| 13022 | case SystemZ::CEFBRA: |
| 13023 | case SystemZ::CEGBRA: |
| 13024 | case SystemZ::CELFBR: |
| 13025 | case SystemZ::CELGBR: |
| 13026 | case SystemZ::CFDBRA: |
| 13027 | case SystemZ::CFDTR: |
| 13028 | case SystemZ::CFEBRA: |
| 13029 | case SystemZ::CFXBRA: |
| 13030 | case SystemZ::CFXTR: |
| 13031 | case SystemZ::CGDBRA: |
| 13032 | case SystemZ::CGDTRA: |
| 13033 | case SystemZ::CGEBRA: |
| 13034 | case SystemZ::CGXBRA: |
| 13035 | case SystemZ::CGXTRA: |
| 13036 | case SystemZ::CLFDBR: |
| 13037 | case SystemZ::CLFDTR: |
| 13038 | case SystemZ::CLFEBR: |
| 13039 | case SystemZ::CLFXBR: |
| 13040 | case SystemZ::CLFXTR: |
| 13041 | case SystemZ::CLGDBR: |
| 13042 | case SystemZ::CLGDTR: |
| 13043 | case SystemZ::CLGEBR: |
| 13044 | case SystemZ::CLGXBR: |
| 13045 | case SystemZ::CLGXTR: |
| 13046 | case SystemZ::CXFBRA: |
| 13047 | case SystemZ::CXFTR: |
| 13048 | case SystemZ::CXGBRA: |
| 13049 | case SystemZ::CXGTRA: |
| 13050 | case SystemZ::CXLFBR: |
| 13051 | case SystemZ::CXLFTR: |
| 13052 | case SystemZ::CXLGBR: |
| 13053 | case SystemZ::CXLGTR: |
| 13054 | case SystemZ::FIDBRA: |
| 13055 | case SystemZ::FIDTR: |
| 13056 | case SystemZ::FIEBRA: |
| 13057 | case SystemZ::FIXBRA: |
| 13058 | case SystemZ::FIXTR: |
| 13059 | case SystemZ::LDXBRA: |
| 13060 | case SystemZ::LDXTR: |
| 13061 | case SystemZ::LEDBRA: |
| 13062 | case SystemZ::LEDTR: |
| 13063 | case SystemZ::LEXBRA: { |
| 13064 | switch (OpNum) { |
| 13065 | case 0: |
| 13066 | // op: R1 |
| 13067 | return 4; |
| 13068 | case 2: |
| 13069 | // op: R2 |
| 13070 | return 0; |
| 13071 | case 1: |
| 13072 | // op: M3 |
| 13073 | return 12; |
| 13074 | case 3: |
| 13075 | // op: M4 |
| 13076 | return 8; |
| 13077 | } |
| 13078 | break; |
| 13079 | } |
| 13080 | case SystemZ::CFDBR: |
| 13081 | case SystemZ::CFDR: |
| 13082 | case SystemZ::CFEBR: |
| 13083 | case SystemZ::CFER: |
| 13084 | case SystemZ::CFXBR: |
| 13085 | case SystemZ::CFXR: |
| 13086 | case SystemZ::CGDBR: |
| 13087 | case SystemZ::CGDR: |
| 13088 | case SystemZ::CGDTR: |
| 13089 | case SystemZ::CGEBR: |
| 13090 | case SystemZ::CGER: |
| 13091 | case SystemZ::CGXBR: |
| 13092 | case SystemZ::CGXR: |
| 13093 | case SystemZ::CGXTR: |
| 13094 | case SystemZ::FIDBR: |
| 13095 | case SystemZ::FIEBR: |
| 13096 | case SystemZ::FIXBR: |
| 13097 | case SystemZ::TBDR: |
| 13098 | case SystemZ::TBEDR: { |
| 13099 | switch (OpNum) { |
| 13100 | case 0: |
| 13101 | // op: R1 |
| 13102 | return 4; |
| 13103 | case 2: |
| 13104 | // op: R2 |
| 13105 | return 0; |
| 13106 | case 1: |
| 13107 | // op: M3 |
| 13108 | return 12; |
| 13109 | } |
| 13110 | break; |
| 13111 | } |
| 13112 | case SystemZ::SELFHRAsm: |
| 13113 | case SystemZ::SELGRAsm: |
| 13114 | case SystemZ::SELRAsm: { |
| 13115 | switch (OpNum) { |
| 13116 | case 0: |
| 13117 | // op: R1 |
| 13118 | return 4; |
| 13119 | case 2: |
| 13120 | // op: R2 |
| 13121 | return 0; |
| 13122 | case 1: |
| 13123 | // op: R3 |
| 13124 | return 12; |
| 13125 | case 3: |
| 13126 | // op: M4 |
| 13127 | return 8; |
| 13128 | } |
| 13129 | break; |
| 13130 | } |
| 13131 | case SystemZ::SELFHR: |
| 13132 | case SystemZ::SELGR: |
| 13133 | case SystemZ::SELR: { |
| 13134 | switch (OpNum) { |
| 13135 | case 0: |
| 13136 | // op: R1 |
| 13137 | return 4; |
| 13138 | case 2: |
| 13139 | // op: R2 |
| 13140 | return 0; |
| 13141 | case 1: |
| 13142 | // op: R3 |
| 13143 | return 12; |
| 13144 | case 4: |
| 13145 | // op: M4 |
| 13146 | return 8; |
| 13147 | } |
| 13148 | break; |
| 13149 | } |
| 13150 | case SystemZ::SELFHRAsmE: |
| 13151 | case SystemZ::SELFHRAsmH: |
| 13152 | case SystemZ::SELFHRAsmHE: |
| 13153 | case SystemZ::SELFHRAsmL: |
| 13154 | case SystemZ::SELFHRAsmLE: |
| 13155 | case SystemZ::SELFHRAsmLH: |
| 13156 | case SystemZ::SELFHRAsmM: |
| 13157 | case SystemZ::SELFHRAsmNE: |
| 13158 | case SystemZ::SELFHRAsmNH: |
| 13159 | case SystemZ::SELFHRAsmNHE: |
| 13160 | case SystemZ::SELFHRAsmNL: |
| 13161 | case SystemZ::SELFHRAsmNLE: |
| 13162 | case SystemZ::SELFHRAsmNLH: |
| 13163 | case SystemZ::SELFHRAsmNM: |
| 13164 | case SystemZ::SELFHRAsmNO: |
| 13165 | case SystemZ::SELFHRAsmNP: |
| 13166 | case SystemZ::SELFHRAsmNZ: |
| 13167 | case SystemZ::SELFHRAsmO: |
| 13168 | case SystemZ::SELFHRAsmP: |
| 13169 | case SystemZ::SELFHRAsmZ: |
| 13170 | case SystemZ::SELGRAsmE: |
| 13171 | case SystemZ::SELGRAsmH: |
| 13172 | case SystemZ::SELGRAsmHE: |
| 13173 | case SystemZ::SELGRAsmL: |
| 13174 | case SystemZ::SELGRAsmLE: |
| 13175 | case SystemZ::SELGRAsmLH: |
| 13176 | case SystemZ::SELGRAsmM: |
| 13177 | case SystemZ::SELGRAsmNE: |
| 13178 | case SystemZ::SELGRAsmNH: |
| 13179 | case SystemZ::SELGRAsmNHE: |
| 13180 | case SystemZ::SELGRAsmNL: |
| 13181 | case SystemZ::SELGRAsmNLE: |
| 13182 | case SystemZ::SELGRAsmNLH: |
| 13183 | case SystemZ::SELGRAsmNM: |
| 13184 | case SystemZ::SELGRAsmNO: |
| 13185 | case SystemZ::SELGRAsmNP: |
| 13186 | case SystemZ::SELGRAsmNZ: |
| 13187 | case SystemZ::SELGRAsmO: |
| 13188 | case SystemZ::SELGRAsmP: |
| 13189 | case SystemZ::SELGRAsmZ: |
| 13190 | case SystemZ::SELRAsmE: |
| 13191 | case SystemZ::SELRAsmH: |
| 13192 | case SystemZ::SELRAsmHE: |
| 13193 | case SystemZ::SELRAsmL: |
| 13194 | case SystemZ::SELRAsmLE: |
| 13195 | case SystemZ::SELRAsmLH: |
| 13196 | case SystemZ::SELRAsmM: |
| 13197 | case SystemZ::SELRAsmNE: |
| 13198 | case SystemZ::SELRAsmNH: |
| 13199 | case SystemZ::SELRAsmNHE: |
| 13200 | case SystemZ::SELRAsmNL: |
| 13201 | case SystemZ::SELRAsmNLE: |
| 13202 | case SystemZ::SELRAsmNLH: |
| 13203 | case SystemZ::SELRAsmNM: |
| 13204 | case SystemZ::SELRAsmNO: |
| 13205 | case SystemZ::SELRAsmNP: |
| 13206 | case SystemZ::SELRAsmNZ: |
| 13207 | case SystemZ::SELRAsmO: |
| 13208 | case SystemZ::SELRAsmP: |
| 13209 | case SystemZ::SELRAsmZ: { |
| 13210 | switch (OpNum) { |
| 13211 | case 0: |
| 13212 | // op: R1 |
| 13213 | return 4; |
| 13214 | case 2: |
| 13215 | // op: R2 |
| 13216 | return 0; |
| 13217 | case 1: |
| 13218 | // op: R3 |
| 13219 | return 12; |
| 13220 | } |
| 13221 | break; |
| 13222 | } |
| 13223 | case SystemZ::LOCFHRAsm: |
| 13224 | case SystemZ::LOCGRAsm: |
| 13225 | case SystemZ::LOCRAsm: { |
| 13226 | switch (OpNum) { |
| 13227 | case 0: |
| 13228 | // op: R1 |
| 13229 | return 4; |
| 13230 | case 2: |
| 13231 | // op: R2 |
| 13232 | return 0; |
| 13233 | case 3: |
| 13234 | // op: M3 |
| 13235 | return 12; |
| 13236 | } |
| 13237 | break; |
| 13238 | } |
| 13239 | case SystemZ::LOCFHR: |
| 13240 | case SystemZ::LOCGR: |
| 13241 | case SystemZ::LOCR: { |
| 13242 | switch (OpNum) { |
| 13243 | case 0: |
| 13244 | // op: R1 |
| 13245 | return 4; |
| 13246 | case 2: |
| 13247 | // op: R2 |
| 13248 | return 0; |
| 13249 | case 4: |
| 13250 | // op: M3 |
| 13251 | return 12; |
| 13252 | } |
| 13253 | break; |
| 13254 | } |
| 13255 | case SystemZ::ADBR: |
| 13256 | case SystemZ::ADR: |
| 13257 | case SystemZ::AEBR: |
| 13258 | case SystemZ::AER: |
| 13259 | case SystemZ::AGFR: |
| 13260 | case SystemZ::AGR: |
| 13261 | case SystemZ::ALCGR: |
| 13262 | case SystemZ::ALCR: |
| 13263 | case SystemZ::ALGFR: |
| 13264 | case SystemZ::ALGR: |
| 13265 | case SystemZ::ALR: |
| 13266 | case SystemZ::AR: |
| 13267 | case SystemZ::AUR: |
| 13268 | case SystemZ::AWR: |
| 13269 | case SystemZ::AXBR: |
| 13270 | case SystemZ::AXR: |
| 13271 | case SystemZ::BCTGR: |
| 13272 | case SystemZ::BCTR: |
| 13273 | case SystemZ::CSP: |
| 13274 | case SystemZ::CSPG: |
| 13275 | case SystemZ::DDBR: |
| 13276 | case SystemZ::DDR: |
| 13277 | case SystemZ::DEBR: |
| 13278 | case SystemZ::DER: |
| 13279 | case SystemZ::DLGR: |
| 13280 | case SystemZ::DLR: |
| 13281 | case SystemZ::DR: |
| 13282 | case SystemZ::DSGFR: |
| 13283 | case SystemZ::DSGR: |
| 13284 | case SystemZ::DXBR: |
| 13285 | case SystemZ::DXR: |
| 13286 | case SystemZ::ISKE: |
| 13287 | case SystemZ::IVSK: |
| 13288 | case SystemZ::LOCFHRAsmE: |
| 13289 | case SystemZ::LOCFHRAsmH: |
| 13290 | case SystemZ::LOCFHRAsmHE: |
| 13291 | case SystemZ::LOCFHRAsmL: |
| 13292 | case SystemZ::LOCFHRAsmLE: |
| 13293 | case SystemZ::LOCFHRAsmLH: |
| 13294 | case SystemZ::LOCFHRAsmM: |
| 13295 | case SystemZ::LOCFHRAsmNE: |
| 13296 | case SystemZ::LOCFHRAsmNH: |
| 13297 | case SystemZ::LOCFHRAsmNHE: |
| 13298 | case SystemZ::LOCFHRAsmNL: |
| 13299 | case SystemZ::LOCFHRAsmNLE: |
| 13300 | case SystemZ::LOCFHRAsmNLH: |
| 13301 | case SystemZ::LOCFHRAsmNM: |
| 13302 | case SystemZ::LOCFHRAsmNO: |
| 13303 | case SystemZ::LOCFHRAsmNP: |
| 13304 | case SystemZ::LOCFHRAsmNZ: |
| 13305 | case SystemZ::LOCFHRAsmO: |
| 13306 | case SystemZ::LOCFHRAsmP: |
| 13307 | case SystemZ::LOCFHRAsmZ: |
| 13308 | case SystemZ::LOCGRAsmE: |
| 13309 | case SystemZ::LOCGRAsmH: |
| 13310 | case SystemZ::LOCGRAsmHE: |
| 13311 | case SystemZ::LOCGRAsmL: |
| 13312 | case SystemZ::LOCGRAsmLE: |
| 13313 | case SystemZ::LOCGRAsmLH: |
| 13314 | case SystemZ::LOCGRAsmM: |
| 13315 | case SystemZ::LOCGRAsmNE: |
| 13316 | case SystemZ::LOCGRAsmNH: |
| 13317 | case SystemZ::LOCGRAsmNHE: |
| 13318 | case SystemZ::LOCGRAsmNL: |
| 13319 | case SystemZ::LOCGRAsmNLE: |
| 13320 | case SystemZ::LOCGRAsmNLH: |
| 13321 | case SystemZ::LOCGRAsmNM: |
| 13322 | case SystemZ::LOCGRAsmNO: |
| 13323 | case SystemZ::LOCGRAsmNP: |
| 13324 | case SystemZ::LOCGRAsmNZ: |
| 13325 | case SystemZ::LOCGRAsmO: |
| 13326 | case SystemZ::LOCGRAsmP: |
| 13327 | case SystemZ::LOCGRAsmZ: |
| 13328 | case SystemZ::LOCRAsmE: |
| 13329 | case SystemZ::LOCRAsmH: |
| 13330 | case SystemZ::LOCRAsmHE: |
| 13331 | case SystemZ::LOCRAsmL: |
| 13332 | case SystemZ::LOCRAsmLE: |
| 13333 | case SystemZ::LOCRAsmLH: |
| 13334 | case SystemZ::LOCRAsmM: |
| 13335 | case SystemZ::LOCRAsmNE: |
| 13336 | case SystemZ::LOCRAsmNH: |
| 13337 | case SystemZ::LOCRAsmNHE: |
| 13338 | case SystemZ::LOCRAsmNL: |
| 13339 | case SystemZ::LOCRAsmNLE: |
| 13340 | case SystemZ::LOCRAsmNLH: |
| 13341 | case SystemZ::LOCRAsmNM: |
| 13342 | case SystemZ::LOCRAsmNO: |
| 13343 | case SystemZ::LOCRAsmNP: |
| 13344 | case SystemZ::LOCRAsmNZ: |
| 13345 | case SystemZ::LOCRAsmO: |
| 13346 | case SystemZ::LOCRAsmP: |
| 13347 | case SystemZ::LOCRAsmZ: |
| 13348 | case SystemZ::MDBR: |
| 13349 | case SystemZ::MDEBR: |
| 13350 | case SystemZ::MDER: |
| 13351 | case SystemZ::MDR: |
| 13352 | case SystemZ::MEEBR: |
| 13353 | case SystemZ::MEER: |
| 13354 | case SystemZ::MER: |
| 13355 | case SystemZ::MLGR: |
| 13356 | case SystemZ::MLR: |
| 13357 | case SystemZ::MR: |
| 13358 | case SystemZ::MSGFR: |
| 13359 | case SystemZ::MSGR: |
| 13360 | case SystemZ::MSR: |
| 13361 | case SystemZ::MXBR: |
| 13362 | case SystemZ::MXDBR: |
| 13363 | case SystemZ::MXDR: |
| 13364 | case SystemZ::MXR: |
| 13365 | case SystemZ::NGR: |
| 13366 | case SystemZ::NR: |
| 13367 | case SystemZ::OGR: |
| 13368 | case SystemZ::OR: |
| 13369 | case SystemZ::SDBR: |
| 13370 | case SystemZ::SDR: |
| 13371 | case SystemZ::SEBR: |
| 13372 | case SystemZ::SER: |
| 13373 | case SystemZ::SGFR: |
| 13374 | case SystemZ::SGR: |
| 13375 | case SystemZ::SLBGR: |
| 13376 | case SystemZ::SLBR: |
| 13377 | case SystemZ::SLGFR: |
| 13378 | case SystemZ::SLGR: |
| 13379 | case SystemZ::SLR: |
| 13380 | case SystemZ::SR: |
| 13381 | case SystemZ::SUR: |
| 13382 | case SystemZ::SWR: |
| 13383 | case SystemZ::SXBR: |
| 13384 | case SystemZ::SXR: |
| 13385 | case SystemZ::XGR: |
| 13386 | case SystemZ::XR: { |
| 13387 | switch (OpNum) { |
| 13388 | case 0: |
| 13389 | // op: R1 |
| 13390 | return 4; |
| 13391 | case 2: |
| 13392 | // op: R2 |
| 13393 | return 0; |
| 13394 | } |
| 13395 | break; |
| 13396 | } |
| 13397 | case SystemZ::DIDBR: |
| 13398 | case SystemZ::DIEBR: |
| 13399 | case SystemZ::LPTEA: |
| 13400 | case SystemZ::QADTR: |
| 13401 | case SystemZ::QAXTR: |
| 13402 | case SystemZ::RRDTR: |
| 13403 | case SystemZ::RRXTR: { |
| 13404 | switch (OpNum) { |
| 13405 | case 0: |
| 13406 | // op: R1 |
| 13407 | return 4; |
| 13408 | case 3: |
| 13409 | // op: R2 |
| 13410 | return 0; |
| 13411 | case 1: |
| 13412 | // op: R3 |
| 13413 | return 12; |
| 13414 | case 4: |
| 13415 | // op: M4 |
| 13416 | return 8; |
| 13417 | } |
| 13418 | break; |
| 13419 | } |
| 13420 | case SystemZ::EFPC: |
| 13421 | case SystemZ::EPAIR: |
| 13422 | case SystemZ::EPAR: |
| 13423 | case SystemZ::ESAIR: |
| 13424 | case SystemZ::ESAR: |
| 13425 | case SystemZ::ESEA: |
| 13426 | case SystemZ::ETND: |
| 13427 | case SystemZ::IAC: |
| 13428 | case SystemZ::IPM: |
| 13429 | case SystemZ::LZDR: |
| 13430 | case SystemZ::LZER: |
| 13431 | case SystemZ::LZER_16: |
| 13432 | case SystemZ::LZXR: |
| 13433 | case SystemZ::MSTA: |
| 13434 | case SystemZ::PTF: |
| 13435 | case SystemZ::SFASR: |
| 13436 | case SystemZ::SFPC: |
| 13437 | case SystemZ::SPM: |
| 13438 | case SystemZ::SSAIR: |
| 13439 | case SystemZ::SSAR: { |
| 13440 | switch (OpNum) { |
| 13441 | case 0: |
| 13442 | // op: R1 |
| 13443 | return 4; |
| 13444 | } |
| 13445 | break; |
| 13446 | } |
| 13447 | case SystemZ::BR: |
| 13448 | case SystemZ::BRAsmE: |
| 13449 | case SystemZ::BRAsmH: |
| 13450 | case SystemZ::BRAsmHE: |
| 13451 | case SystemZ::BRAsmL: |
| 13452 | case SystemZ::BRAsmLE: |
| 13453 | case SystemZ::BRAsmLH: |
| 13454 | case SystemZ::BRAsmM: |
| 13455 | case SystemZ::BRAsmNE: |
| 13456 | case SystemZ::BRAsmNH: |
| 13457 | case SystemZ::BRAsmNHE: |
| 13458 | case SystemZ::BRAsmNL: |
| 13459 | case SystemZ::BRAsmNLE: |
| 13460 | case SystemZ::BRAsmNLH: |
| 13461 | case SystemZ::BRAsmNM: |
| 13462 | case SystemZ::BRAsmNO: |
| 13463 | case SystemZ::BRAsmNP: |
| 13464 | case SystemZ::BRAsmNZ: |
| 13465 | case SystemZ::BRAsmO: |
| 13466 | case SystemZ::BRAsmP: |
| 13467 | case SystemZ::BRAsmZ: |
| 13468 | case SystemZ::NOPR: { |
| 13469 | switch (OpNum) { |
| 13470 | case 0: |
| 13471 | // op: R2 |
| 13472 | return 0; |
| 13473 | } |
| 13474 | break; |
| 13475 | } |
| 13476 | case SystemZ::J: |
| 13477 | case SystemZ::JAsmE: |
| 13478 | case SystemZ::JAsmH: |
| 13479 | case SystemZ::JAsmHE: |
| 13480 | case SystemZ::JAsmL: |
| 13481 | case SystemZ::JAsmLE: |
| 13482 | case SystemZ::JAsmLH: |
| 13483 | case SystemZ::JAsmM: |
| 13484 | case SystemZ::JAsmNE: |
| 13485 | case SystemZ::JAsmNH: |
| 13486 | case SystemZ::JAsmNHE: |
| 13487 | case SystemZ::JAsmNL: |
| 13488 | case SystemZ::JAsmNLE: |
| 13489 | case SystemZ::JAsmNLH: |
| 13490 | case SystemZ::JAsmNM: |
| 13491 | case SystemZ::JAsmNO: |
| 13492 | case SystemZ::JAsmNP: |
| 13493 | case SystemZ::JAsmNZ: |
| 13494 | case SystemZ::JAsmO: |
| 13495 | case SystemZ::JAsmP: |
| 13496 | case SystemZ::JAsmZ: |
| 13497 | case SystemZ::JG: |
| 13498 | case SystemZ::JGAsmE: |
| 13499 | case SystemZ::JGAsmH: |
| 13500 | case SystemZ::JGAsmHE: |
| 13501 | case SystemZ::JGAsmL: |
| 13502 | case SystemZ::JGAsmLE: |
| 13503 | case SystemZ::JGAsmLH: |
| 13504 | case SystemZ::JGAsmM: |
| 13505 | case SystemZ::JGAsmNE: |
| 13506 | case SystemZ::JGAsmNH: |
| 13507 | case SystemZ::JGAsmNHE: |
| 13508 | case SystemZ::JGAsmNL: |
| 13509 | case SystemZ::JGAsmNLE: |
| 13510 | case SystemZ::JGAsmNLH: |
| 13511 | case SystemZ::JGAsmNM: |
| 13512 | case SystemZ::JGAsmNO: |
| 13513 | case SystemZ::JGAsmNP: |
| 13514 | case SystemZ::JGAsmNZ: |
| 13515 | case SystemZ::JGAsmO: |
| 13516 | case SystemZ::JGAsmP: |
| 13517 | case SystemZ::JGAsmZ: |
| 13518 | case SystemZ::JGNOP: |
| 13519 | case SystemZ::JNOP: { |
| 13520 | switch (OpNum) { |
| 13521 | case 0: |
| 13522 | // op: RI2 |
| 13523 | return 0; |
| 13524 | } |
| 13525 | break; |
| 13526 | } |
| 13527 | case SystemZ::VTPOpt: { |
| 13528 | switch (OpNum) { |
| 13529 | case 0: |
| 13530 | // op: V1 |
| 13531 | return 10; |
| 13532 | case 1: |
| 13533 | // op: I2 |
| 13534 | return 12; |
| 13535 | } |
| 13536 | break; |
| 13537 | } |
| 13538 | case SystemZ::VTZ: { |
| 13539 | switch (OpNum) { |
| 13540 | case 0: |
| 13541 | // op: V1 |
| 13542 | return 10; |
| 13543 | case 1: |
| 13544 | // op: V2 |
| 13545 | return 9; |
| 13546 | case 2: |
| 13547 | // op: I3 |
| 13548 | return 12; |
| 13549 | } |
| 13550 | break; |
| 13551 | } |
| 13552 | case SystemZ::VCP: { |
| 13553 | switch (OpNum) { |
| 13554 | case 0: |
| 13555 | // op: V1 |
| 13556 | return 10; |
| 13557 | case 1: |
| 13558 | // op: V2 |
| 13559 | return 9; |
| 13560 | case 2: |
| 13561 | // op: M3 |
| 13562 | return 20; |
| 13563 | } |
| 13564 | break; |
| 13565 | } |
| 13566 | case SystemZ::VTP: { |
| 13567 | switch (OpNum) { |
| 13568 | case 0: |
| 13569 | // op: V1 |
| 13570 | return 10; |
| 13571 | } |
| 13572 | break; |
| 13573 | } |
| 13574 | case SystemZ::VLIP: { |
| 13575 | switch (OpNum) { |
| 13576 | case 0: |
| 13577 | // op: V1 |
| 13578 | return 11; |
| 13579 | case 1: |
| 13580 | // op: I2 |
| 13581 | return 16; |
| 13582 | case 2: |
| 13583 | // op: I3 |
| 13584 | return 12; |
| 13585 | } |
| 13586 | break; |
| 13587 | } |
| 13588 | case SystemZ::VREPI: { |
| 13589 | switch (OpNum) { |
| 13590 | case 0: |
| 13591 | // op: V1 |
| 13592 | return 11; |
| 13593 | case 1: |
| 13594 | // op: I2 |
| 13595 | return 16; |
| 13596 | case 2: |
| 13597 | // op: M3 |
| 13598 | return 12; |
| 13599 | } |
| 13600 | break; |
| 13601 | } |
| 13602 | case SystemZ::VGBM: |
| 13603 | case SystemZ::VREPIB: |
| 13604 | case SystemZ::VREPIF: |
| 13605 | case SystemZ::VREPIG: |
| 13606 | case SystemZ::VREPIH: { |
| 13607 | switch (OpNum) { |
| 13608 | case 0: |
| 13609 | // op: V1 |
| 13610 | return 11; |
| 13611 | case 1: |
| 13612 | // op: I2 |
| 13613 | return 16; |
| 13614 | } |
| 13615 | break; |
| 13616 | } |
| 13617 | case SystemZ::VGM: { |
| 13618 | switch (OpNum) { |
| 13619 | case 0: |
| 13620 | // op: V1 |
| 13621 | return 11; |
| 13622 | case 1: |
| 13623 | // op: I2 |
| 13624 | return 24; |
| 13625 | case 2: |
| 13626 | // op: I3 |
| 13627 | return 16; |
| 13628 | case 3: |
| 13629 | // op: M4 |
| 13630 | return 12; |
| 13631 | } |
| 13632 | break; |
| 13633 | } |
| 13634 | case SystemZ::VGMB: |
| 13635 | case SystemZ::VGMF: |
| 13636 | case SystemZ::VGMG: |
| 13637 | case SystemZ::VGMH: { |
| 13638 | switch (OpNum) { |
| 13639 | case 0: |
| 13640 | // op: V1 |
| 13641 | return 11; |
| 13642 | case 1: |
| 13643 | // op: I2 |
| 13644 | return 24; |
| 13645 | case 2: |
| 13646 | // op: I3 |
| 13647 | return 16; |
| 13648 | } |
| 13649 | break; |
| 13650 | } |
| 13651 | case SystemZ::VCVD: |
| 13652 | case SystemZ::VCVDG: { |
| 13653 | switch (OpNum) { |
| 13654 | case 0: |
| 13655 | // op: V1 |
| 13656 | return 11; |
| 13657 | case 1: |
| 13658 | // op: R2 |
| 13659 | return 32; |
| 13660 | case 2: |
| 13661 | // op: I3 |
| 13662 | return 12; |
| 13663 | case 3: |
| 13664 | // op: M4 |
| 13665 | return 20; |
| 13666 | } |
| 13667 | break; |
| 13668 | } |
| 13669 | case SystemZ::VLVGP: { |
| 13670 | switch (OpNum) { |
| 13671 | case 0: |
| 13672 | // op: V1 |
| 13673 | return 11; |
| 13674 | case 1: |
| 13675 | // op: R2 |
| 13676 | return 32; |
| 13677 | case 2: |
| 13678 | // op: R3 |
| 13679 | return 28; |
| 13680 | } |
| 13681 | break; |
| 13682 | } |
| 13683 | case SystemZ::VPSOP: |
| 13684 | case SystemZ::VSRP: { |
| 13685 | switch (OpNum) { |
| 13686 | case 0: |
| 13687 | // op: V1 |
| 13688 | return 11; |
| 13689 | case 1: |
| 13690 | // op: V2 |
| 13691 | return 10; |
| 13692 | case 2: |
| 13693 | // op: I3 |
| 13694 | return 12; |
| 13695 | case 3: |
| 13696 | // op: I4 |
| 13697 | return 24; |
| 13698 | case 4: |
| 13699 | // op: M5 |
| 13700 | return 20; |
| 13701 | } |
| 13702 | break; |
| 13703 | } |
| 13704 | case SystemZ::VCVDQ: { |
| 13705 | switch (OpNum) { |
| 13706 | case 0: |
| 13707 | // op: V1 |
| 13708 | return 11; |
| 13709 | case 1: |
| 13710 | // op: V2 |
| 13711 | return 10; |
| 13712 | case 2: |
| 13713 | // op: I3 |
| 13714 | return 12; |
| 13715 | case 3: |
| 13716 | // op: M4 |
| 13717 | return 20; |
| 13718 | } |
| 13719 | break; |
| 13720 | } |
| 13721 | case SystemZ::VFTCI: { |
| 13722 | switch (OpNum) { |
| 13723 | case 0: |
| 13724 | // op: V1 |
| 13725 | return 11; |
| 13726 | case 1: |
| 13727 | // op: V2 |
| 13728 | return 10; |
| 13729 | case 2: |
| 13730 | // op: I3 |
| 13731 | return 20; |
| 13732 | case 3: |
| 13733 | // op: M4 |
| 13734 | return 12; |
| 13735 | case 4: |
| 13736 | // op: M5 |
| 13737 | return 16; |
| 13738 | } |
| 13739 | break; |
| 13740 | } |
| 13741 | case SystemZ::VFTCIDB: |
| 13742 | case SystemZ::VFTCISB: |
| 13743 | case SystemZ::WFTCIDB: |
| 13744 | case SystemZ::WFTCISB: |
| 13745 | case SystemZ::WFTCIXB: { |
| 13746 | switch (OpNum) { |
| 13747 | case 0: |
| 13748 | // op: V1 |
| 13749 | return 11; |
| 13750 | case 1: |
| 13751 | // op: V2 |
| 13752 | return 10; |
| 13753 | case 2: |
| 13754 | // op: I3 |
| 13755 | return 20; |
| 13756 | } |
| 13757 | break; |
| 13758 | } |
| 13759 | case SystemZ::VCDG: |
| 13760 | case SystemZ::VCDLG: |
| 13761 | case SystemZ::VCFPL: |
| 13762 | case SystemZ::VCFPS: |
| 13763 | case SystemZ::VCGD: |
| 13764 | case SystemZ::VCLFP: |
| 13765 | case SystemZ::VCLGD: |
| 13766 | case SystemZ::VCSFP: |
| 13767 | case SystemZ::VFI: |
| 13768 | case SystemZ::VFLR: |
| 13769 | case SystemZ::VFPSO: |
| 13770 | case SystemZ::VLED: { |
| 13771 | switch (OpNum) { |
| 13772 | case 0: |
| 13773 | // op: V1 |
| 13774 | return 11; |
| 13775 | case 1: |
| 13776 | // op: V2 |
| 13777 | return 10; |
| 13778 | case 2: |
| 13779 | // op: M3 |
| 13780 | return 12; |
| 13781 | case 3: |
| 13782 | // op: M4 |
| 13783 | return 16; |
| 13784 | case 4: |
| 13785 | // op: M5 |
| 13786 | return 20; |
| 13787 | } |
| 13788 | break; |
| 13789 | } |
| 13790 | case SystemZ::VCFN: |
| 13791 | case SystemZ::VCLFNH: |
| 13792 | case SystemZ::VCLFNL: |
| 13793 | case SystemZ::VCNF: |
| 13794 | case SystemZ::VFLL: |
| 13795 | case SystemZ::VFSQ: |
| 13796 | case SystemZ::VLDE: |
| 13797 | case SystemZ::WFC: |
| 13798 | case SystemZ::WFK: { |
| 13799 | switch (OpNum) { |
| 13800 | case 0: |
| 13801 | // op: V1 |
| 13802 | return 11; |
| 13803 | case 1: |
| 13804 | // op: V2 |
| 13805 | return 10; |
| 13806 | case 2: |
| 13807 | // op: M3 |
| 13808 | return 12; |
| 13809 | case 3: |
| 13810 | // op: M4 |
| 13811 | return 16; |
| 13812 | } |
| 13813 | break; |
| 13814 | } |
| 13815 | case SystemZ::VISTR: { |
| 13816 | switch (OpNum) { |
| 13817 | case 0: |
| 13818 | // op: V1 |
| 13819 | return 11; |
| 13820 | case 1: |
| 13821 | // op: V2 |
| 13822 | return 10; |
| 13823 | case 2: |
| 13824 | // op: M3 |
| 13825 | return 12; |
| 13826 | case 3: |
| 13827 | // op: M5 |
| 13828 | return 20; |
| 13829 | } |
| 13830 | break; |
| 13831 | } |
| 13832 | case SystemZ::VCLZ: |
| 13833 | case SystemZ::VCTZ: |
| 13834 | case SystemZ::VEC: |
| 13835 | case SystemZ::VECL: |
| 13836 | case SystemZ::VGEM: |
| 13837 | case SystemZ::VLC: |
| 13838 | case SystemZ::VLP: |
| 13839 | case SystemZ::VPOPCT: |
| 13840 | case SystemZ::VSEG: |
| 13841 | case SystemZ::VUPH: |
| 13842 | case SystemZ::VUPL: |
| 13843 | case SystemZ::VUPLH: |
| 13844 | case SystemZ::VUPLL: { |
| 13845 | switch (OpNum) { |
| 13846 | case 0: |
| 13847 | // op: V1 |
| 13848 | return 11; |
| 13849 | case 1: |
| 13850 | // op: V2 |
| 13851 | return 10; |
| 13852 | case 2: |
| 13853 | // op: M3 |
| 13854 | return 12; |
| 13855 | } |
| 13856 | break; |
| 13857 | } |
| 13858 | case SystemZ::VCLZDP: |
| 13859 | case SystemZ::VCVBQ: |
| 13860 | case SystemZ::VUPKZH: |
| 13861 | case SystemZ::VUPKZL: { |
| 13862 | switch (OpNum) { |
| 13863 | case 0: |
| 13864 | // op: V1 |
| 13865 | return 11; |
| 13866 | case 1: |
| 13867 | // op: V2 |
| 13868 | return 10; |
| 13869 | case 2: |
| 13870 | // op: M3 |
| 13871 | return 20; |
| 13872 | } |
| 13873 | break; |
| 13874 | } |
| 13875 | case SystemZ::VCDGB: |
| 13876 | case SystemZ::VCDLGB: |
| 13877 | case SystemZ::VCEFB: |
| 13878 | case SystemZ::VCELFB: |
| 13879 | case SystemZ::VCFEB: |
| 13880 | case SystemZ::VCGDB: |
| 13881 | case SystemZ::VCLFEB: |
| 13882 | case SystemZ::VCLGDB: |
| 13883 | case SystemZ::VFIDB: |
| 13884 | case SystemZ::VFISB: |
| 13885 | case SystemZ::VFLRD: |
| 13886 | case SystemZ::VLEDB: |
| 13887 | case SystemZ::WCDGB: |
| 13888 | case SystemZ::WCDLGB: |
| 13889 | case SystemZ::WCEFB: |
| 13890 | case SystemZ::WCELFB: |
| 13891 | case SystemZ::WCFEB: |
| 13892 | case SystemZ::WCGDB: |
| 13893 | case SystemZ::WCLFEB: |
| 13894 | case SystemZ::WCLGDB: |
| 13895 | case SystemZ::WFIDB: |
| 13896 | case SystemZ::WFISB: |
| 13897 | case SystemZ::WFIXB: |
| 13898 | case SystemZ::WFLRD: |
| 13899 | case SystemZ::WFLRX: |
| 13900 | case SystemZ::WLEDB: { |
| 13901 | switch (OpNum) { |
| 13902 | case 0: |
| 13903 | // op: V1 |
| 13904 | return 11; |
| 13905 | case 1: |
| 13906 | // op: V2 |
| 13907 | return 10; |
| 13908 | case 2: |
| 13909 | // op: M4 |
| 13910 | return 16; |
| 13911 | case 3: |
| 13912 | // op: M5 |
| 13913 | return 20; |
| 13914 | } |
| 13915 | break; |
| 13916 | } |
| 13917 | case SystemZ::VFPSODB: |
| 13918 | case SystemZ::VFPSOSB: |
| 13919 | case SystemZ::VISTRB: |
| 13920 | case SystemZ::VISTRF: |
| 13921 | case SystemZ::VISTRH: |
| 13922 | case SystemZ::WFPSODB: |
| 13923 | case SystemZ::WFPSOSB: |
| 13924 | case SystemZ::WFPSOXB: { |
| 13925 | switch (OpNum) { |
| 13926 | case 0: |
| 13927 | // op: V1 |
| 13928 | return 11; |
| 13929 | case 1: |
| 13930 | // op: V2 |
| 13931 | return 10; |
| 13932 | case 2: |
| 13933 | // op: M5 |
| 13934 | return 20; |
| 13935 | } |
| 13936 | break; |
| 13937 | } |
| 13938 | case SystemZ::VAP: |
| 13939 | case SystemZ::VDP: |
| 13940 | case SystemZ::VMP: |
| 13941 | case SystemZ::VMSP: |
| 13942 | case SystemZ::VPKZR: |
| 13943 | case SystemZ::VRP: |
| 13944 | case SystemZ::VSDP: |
| 13945 | case SystemZ::VSP: |
| 13946 | case SystemZ::VSRPR: { |
| 13947 | switch (OpNum) { |
| 13948 | case 0: |
| 13949 | // op: V1 |
| 13950 | return 11; |
| 13951 | case 1: |
| 13952 | // op: V2 |
| 13953 | return 10; |
| 13954 | case 2: |
| 13955 | // op: V3 |
| 13956 | return 9; |
| 13957 | case 3: |
| 13958 | // op: I4 |
| 13959 | return 12; |
| 13960 | case 4: |
| 13961 | // op: M5 |
| 13962 | return 20; |
| 13963 | } |
| 13964 | break; |
| 13965 | } |
| 13966 | case SystemZ::VSLD: |
| 13967 | case SystemZ::VSLDB: |
| 13968 | case SystemZ::VSRD: { |
| 13969 | switch (OpNum) { |
| 13970 | case 0: |
| 13971 | // op: V1 |
| 13972 | return 11; |
| 13973 | case 1: |
| 13974 | // op: V2 |
| 13975 | return 10; |
| 13976 | case 2: |
| 13977 | // op: V3 |
| 13978 | return 9; |
| 13979 | case 3: |
| 13980 | // op: I4 |
| 13981 | return 16; |
| 13982 | } |
| 13983 | break; |
| 13984 | } |
| 13985 | case SystemZ::VFCE: |
| 13986 | case SystemZ::VFCH: |
| 13987 | case SystemZ::VFCHE: |
| 13988 | case SystemZ::VFMAX: |
| 13989 | case SystemZ::VFMIN: { |
| 13990 | switch (OpNum) { |
| 13991 | case 0: |
| 13992 | // op: V1 |
| 13993 | return 11; |
| 13994 | case 1: |
| 13995 | // op: V2 |
| 13996 | return 10; |
| 13997 | case 2: |
| 13998 | // op: V3 |
| 13999 | return 9; |
| 14000 | case 3: |
| 14001 | // op: M4 |
| 14002 | return 12; |
| 14003 | case 4: |
| 14004 | // op: M5 |
| 14005 | return 16; |
| 14006 | case 5: |
| 14007 | // op: M6 |
| 14008 | return 20; |
| 14009 | } |
| 14010 | break; |
| 14011 | } |
| 14012 | case SystemZ::VCRNF: |
| 14013 | case SystemZ::VD: |
| 14014 | case SystemZ::VDL: |
| 14015 | case SystemZ::VFA: |
| 14016 | case SystemZ::VFD: |
| 14017 | case SystemZ::VFM: |
| 14018 | case SystemZ::VFS: |
| 14019 | case SystemZ::VR: |
| 14020 | case SystemZ::VRL: { |
| 14021 | switch (OpNum) { |
| 14022 | case 0: |
| 14023 | // op: V1 |
| 14024 | return 11; |
| 14025 | case 1: |
| 14026 | // op: V2 |
| 14027 | return 10; |
| 14028 | case 2: |
| 14029 | // op: V3 |
| 14030 | return 9; |
| 14031 | case 3: |
| 14032 | // op: M4 |
| 14033 | return 12; |
| 14034 | case 4: |
| 14035 | // op: M5 |
| 14036 | return 16; |
| 14037 | } |
| 14038 | break; |
| 14039 | } |
| 14040 | case SystemZ::VCEQ: |
| 14041 | case SystemZ::VCH: |
| 14042 | case SystemZ::VCHL: |
| 14043 | case SystemZ::VFAE: |
| 14044 | case SystemZ::VFEE: |
| 14045 | case SystemZ::VFENE: |
| 14046 | case SystemZ::VPKLS: |
| 14047 | case SystemZ::VPKS: |
| 14048 | case SystemZ::VSCHP: { |
| 14049 | switch (OpNum) { |
| 14050 | case 0: |
| 14051 | // op: V1 |
| 14052 | return 11; |
| 14053 | case 1: |
| 14054 | // op: V2 |
| 14055 | return 10; |
| 14056 | case 2: |
| 14057 | // op: V3 |
| 14058 | return 9; |
| 14059 | case 3: |
| 14060 | // op: M4 |
| 14061 | return 12; |
| 14062 | case 4: |
| 14063 | // op: M5 |
| 14064 | return 20; |
| 14065 | } |
| 14066 | break; |
| 14067 | } |
| 14068 | case SystemZ::VA: |
| 14069 | case SystemZ::VACC: |
| 14070 | case SystemZ::VAVG: |
| 14071 | case SystemZ::VAVGL: |
| 14072 | case SystemZ::VERLLV: |
| 14073 | case SystemZ::VESLV: |
| 14074 | case SystemZ::VESRAV: |
| 14075 | case SystemZ::VESRLV: |
| 14076 | case SystemZ::VGFM: |
| 14077 | case SystemZ::VME: |
| 14078 | case SystemZ::VMH: |
| 14079 | case SystemZ::VML: |
| 14080 | case SystemZ::VMLE: |
| 14081 | case SystemZ::VMLH: |
| 14082 | case SystemZ::VMLO: |
| 14083 | case SystemZ::VMN: |
| 14084 | case SystemZ::VMNL: |
| 14085 | case SystemZ::VMO: |
| 14086 | case SystemZ::VMRH: |
| 14087 | case SystemZ::VMRL: |
| 14088 | case SystemZ::VMX: |
| 14089 | case SystemZ::VMXL: |
| 14090 | case SystemZ::VPDI: |
| 14091 | case SystemZ::VPK: |
| 14092 | case SystemZ::VS: |
| 14093 | case SystemZ::VSCBI: |
| 14094 | case SystemZ::VSUM: |
| 14095 | case SystemZ::VSUMG: |
| 14096 | case SystemZ::VSUMQ: { |
| 14097 | switch (OpNum) { |
| 14098 | case 0: |
| 14099 | // op: V1 |
| 14100 | return 11; |
| 14101 | case 1: |
| 14102 | // op: V2 |
| 14103 | return 10; |
| 14104 | case 2: |
| 14105 | // op: V3 |
| 14106 | return 9; |
| 14107 | case 3: |
| 14108 | // op: M4 |
| 14109 | return 12; |
| 14110 | } |
| 14111 | break; |
| 14112 | } |
| 14113 | case SystemZ::VCSPH: { |
| 14114 | switch (OpNum) { |
| 14115 | case 0: |
| 14116 | // op: V1 |
| 14117 | return 11; |
| 14118 | case 1: |
| 14119 | // op: V2 |
| 14120 | return 10; |
| 14121 | case 2: |
| 14122 | // op: V3 |
| 14123 | return 9; |
| 14124 | case 3: |
| 14125 | // op: M4 |
| 14126 | return 20; |
| 14127 | } |
| 14128 | break; |
| 14129 | } |
| 14130 | case SystemZ::VDF: |
| 14131 | case SystemZ::VDG: |
| 14132 | case SystemZ::VDLF: |
| 14133 | case SystemZ::VDLG: |
| 14134 | case SystemZ::VDLQ: |
| 14135 | case SystemZ::VDQ: |
| 14136 | case SystemZ::VRF: |
| 14137 | case SystemZ::VRG: |
| 14138 | case SystemZ::VRLF: |
| 14139 | case SystemZ::VRLG: |
| 14140 | case SystemZ::VRLQ: |
| 14141 | case SystemZ::VRQ: { |
| 14142 | switch (OpNum) { |
| 14143 | case 0: |
| 14144 | // op: V1 |
| 14145 | return 11; |
| 14146 | case 1: |
| 14147 | // op: V2 |
| 14148 | return 10; |
| 14149 | case 2: |
| 14150 | // op: V3 |
| 14151 | return 9; |
| 14152 | case 3: |
| 14153 | // op: M5 |
| 14154 | return 16; |
| 14155 | } |
| 14156 | break; |
| 14157 | } |
| 14158 | case SystemZ::VFAEB: |
| 14159 | case SystemZ::VFAEF: |
| 14160 | case SystemZ::VFAEH: |
| 14161 | case SystemZ::VFAEZB: |
| 14162 | case SystemZ::VFAEZF: |
| 14163 | case SystemZ::VFAEZH: |
| 14164 | case SystemZ::VFEEB: |
| 14165 | case SystemZ::VFEEF: |
| 14166 | case SystemZ::VFEEH: |
| 14167 | case SystemZ::VFENEB: |
| 14168 | case SystemZ::VFENEF: |
| 14169 | case SystemZ::VFENEH: |
| 14170 | case SystemZ::VSCHDP: |
| 14171 | case SystemZ::VSCHSP: |
| 14172 | case SystemZ::VSCHXP: { |
| 14173 | switch (OpNum) { |
| 14174 | case 0: |
| 14175 | // op: V1 |
| 14176 | return 11; |
| 14177 | case 1: |
| 14178 | // op: V2 |
| 14179 | return 10; |
| 14180 | case 2: |
| 14181 | // op: V3 |
| 14182 | return 9; |
| 14183 | case 3: |
| 14184 | // op: M5 |
| 14185 | return 20; |
| 14186 | } |
| 14187 | break; |
| 14188 | } |
| 14189 | case SystemZ::VFAEBS: |
| 14190 | case SystemZ::VFAEFS: |
| 14191 | case SystemZ::VFAEHS: { |
| 14192 | switch (OpNum) { |
| 14193 | case 0: |
| 14194 | // op: V1 |
| 14195 | return 11; |
| 14196 | case 1: |
| 14197 | // op: V2 |
| 14198 | return 10; |
| 14199 | case 2: |
| 14200 | // op: V3 |
| 14201 | return 9; |
| 14202 | case 3: |
| 14203 | // op: M5 |
| 14204 | return 21; |
| 14205 | } |
| 14206 | break; |
| 14207 | } |
| 14208 | case SystemZ::VFAEZBS: |
| 14209 | case SystemZ::VFAEZFS: |
| 14210 | case SystemZ::VFAEZHS: { |
| 14211 | switch (OpNum) { |
| 14212 | case 0: |
| 14213 | // op: V1 |
| 14214 | return 11; |
| 14215 | case 1: |
| 14216 | // op: V2 |
| 14217 | return 10; |
| 14218 | case 2: |
| 14219 | // op: V3 |
| 14220 | return 9; |
| 14221 | case 3: |
| 14222 | // op: M5 |
| 14223 | return 22; |
| 14224 | } |
| 14225 | break; |
| 14226 | } |
| 14227 | case SystemZ::VFMAXDB: |
| 14228 | case SystemZ::VFMAXSB: |
| 14229 | case SystemZ::VFMINDB: |
| 14230 | case SystemZ::VFMINSB: |
| 14231 | case SystemZ::WFMAXDB: |
| 14232 | case SystemZ::WFMAXSB: |
| 14233 | case SystemZ::WFMAXXB: |
| 14234 | case SystemZ::WFMINDB: |
| 14235 | case SystemZ::WFMINSB: |
| 14236 | case SystemZ::WFMINXB: { |
| 14237 | switch (OpNum) { |
| 14238 | case 0: |
| 14239 | // op: V1 |
| 14240 | return 11; |
| 14241 | case 1: |
| 14242 | // op: V2 |
| 14243 | return 10; |
| 14244 | case 2: |
| 14245 | // op: V3 |
| 14246 | return 9; |
| 14247 | case 3: |
| 14248 | // op: M6 |
| 14249 | return 20; |
| 14250 | } |
| 14251 | break; |
| 14252 | } |
| 14253 | case SystemZ::VEVAL: { |
| 14254 | switch (OpNum) { |
| 14255 | case 0: |
| 14256 | // op: V1 |
| 14257 | return 11; |
| 14258 | case 1: |
| 14259 | // op: V2 |
| 14260 | return 10; |
| 14261 | case 2: |
| 14262 | // op: V3 |
| 14263 | return 9; |
| 14264 | case 3: |
| 14265 | // op: V4 |
| 14266 | return 8; |
| 14267 | case 4: |
| 14268 | // op: I5 |
| 14269 | return 16; |
| 14270 | } |
| 14271 | break; |
| 14272 | } |
| 14273 | case SystemZ::VFMA: |
| 14274 | case SystemZ::VFMS: |
| 14275 | case SystemZ::VFNMA: |
| 14276 | case SystemZ::VFNMS: { |
| 14277 | switch (OpNum) { |
| 14278 | case 0: |
| 14279 | // op: V1 |
| 14280 | return 11; |
| 14281 | case 1: |
| 14282 | // op: V2 |
| 14283 | return 10; |
| 14284 | case 2: |
| 14285 | // op: V3 |
| 14286 | return 9; |
| 14287 | case 3: |
| 14288 | // op: V4 |
| 14289 | return 8; |
| 14290 | case 4: |
| 14291 | // op: M5 |
| 14292 | return 16; |
| 14293 | case 5: |
| 14294 | // op: M6 |
| 14295 | return 24; |
| 14296 | } |
| 14297 | break; |
| 14298 | } |
| 14299 | case SystemZ::VMSL: |
| 14300 | case SystemZ::VSTRC: |
| 14301 | case SystemZ::VSTRS: { |
| 14302 | switch (OpNum) { |
| 14303 | case 0: |
| 14304 | // op: V1 |
| 14305 | return 11; |
| 14306 | case 1: |
| 14307 | // op: V2 |
| 14308 | return 10; |
| 14309 | case 2: |
| 14310 | // op: V3 |
| 14311 | return 9; |
| 14312 | case 3: |
| 14313 | // op: V4 |
| 14314 | return 8; |
| 14315 | case 4: |
| 14316 | // op: M5 |
| 14317 | return 24; |
| 14318 | case 5: |
| 14319 | // op: M6 |
| 14320 | return 20; |
| 14321 | } |
| 14322 | break; |
| 14323 | } |
| 14324 | case SystemZ::VAC: |
| 14325 | case SystemZ::VACCC: |
| 14326 | case SystemZ::VBLEND: |
| 14327 | case SystemZ::VGFMA: |
| 14328 | case SystemZ::VMAE: |
| 14329 | case SystemZ::VMAH: |
| 14330 | case SystemZ::VMAL: |
| 14331 | case SystemZ::VMALE: |
| 14332 | case SystemZ::VMALH: |
| 14333 | case SystemZ::VMALO: |
| 14334 | case SystemZ::VMAO: |
| 14335 | case SystemZ::VSBCBI: |
| 14336 | case SystemZ::VSBI: { |
| 14337 | switch (OpNum) { |
| 14338 | case 0: |
| 14339 | // op: V1 |
| 14340 | return 11; |
| 14341 | case 1: |
| 14342 | // op: V2 |
| 14343 | return 10; |
| 14344 | case 2: |
| 14345 | // op: V3 |
| 14346 | return 9; |
| 14347 | case 3: |
| 14348 | // op: V4 |
| 14349 | return 8; |
| 14350 | case 4: |
| 14351 | // op: M5 |
| 14352 | return 24; |
| 14353 | } |
| 14354 | break; |
| 14355 | } |
| 14356 | case SystemZ::VMSLG: |
| 14357 | case SystemZ::VSTRCB: |
| 14358 | case SystemZ::VSTRCF: |
| 14359 | case SystemZ::VSTRCH: |
| 14360 | case SystemZ::VSTRCZB: |
| 14361 | case SystemZ::VSTRCZF: |
| 14362 | case SystemZ::VSTRCZH: |
| 14363 | case SystemZ::VSTRSB: |
| 14364 | case SystemZ::VSTRSF: |
| 14365 | case SystemZ::VSTRSH: { |
| 14366 | switch (OpNum) { |
| 14367 | case 0: |
| 14368 | // op: V1 |
| 14369 | return 11; |
| 14370 | case 1: |
| 14371 | // op: V2 |
| 14372 | return 10; |
| 14373 | case 2: |
| 14374 | // op: V3 |
| 14375 | return 9; |
| 14376 | case 3: |
| 14377 | // op: V4 |
| 14378 | return 8; |
| 14379 | case 4: |
| 14380 | // op: M6 |
| 14381 | return 20; |
| 14382 | } |
| 14383 | break; |
| 14384 | } |
| 14385 | case SystemZ::VSTRCBS: |
| 14386 | case SystemZ::VSTRCFS: |
| 14387 | case SystemZ::VSTRCHS: { |
| 14388 | switch (OpNum) { |
| 14389 | case 0: |
| 14390 | // op: V1 |
| 14391 | return 11; |
| 14392 | case 1: |
| 14393 | // op: V2 |
| 14394 | return 10; |
| 14395 | case 2: |
| 14396 | // op: V3 |
| 14397 | return 9; |
| 14398 | case 3: |
| 14399 | // op: V4 |
| 14400 | return 8; |
| 14401 | case 4: |
| 14402 | // op: M6 |
| 14403 | return 21; |
| 14404 | } |
| 14405 | break; |
| 14406 | } |
| 14407 | case SystemZ::VSTRCZBS: |
| 14408 | case SystemZ::VSTRCZFS: |
| 14409 | case SystemZ::VSTRCZHS: { |
| 14410 | switch (OpNum) { |
| 14411 | case 0: |
| 14412 | // op: V1 |
| 14413 | return 11; |
| 14414 | case 1: |
| 14415 | // op: V2 |
| 14416 | return 10; |
| 14417 | case 2: |
| 14418 | // op: V3 |
| 14419 | return 9; |
| 14420 | case 3: |
| 14421 | // op: V4 |
| 14422 | return 8; |
| 14423 | case 4: |
| 14424 | // op: M6 |
| 14425 | return 22; |
| 14426 | } |
| 14427 | break; |
| 14428 | } |
| 14429 | case SystemZ::VACCCQ: |
| 14430 | case SystemZ::VACQ: |
| 14431 | case SystemZ::VBLENDB: |
| 14432 | case SystemZ::VBLENDF: |
| 14433 | case SystemZ::VBLENDG: |
| 14434 | case SystemZ::VBLENDH: |
| 14435 | case SystemZ::VBLENDQ: |
| 14436 | case SystemZ::VFMADB: |
| 14437 | case SystemZ::VFMASB: |
| 14438 | case SystemZ::VFMSDB: |
| 14439 | case SystemZ::VFMSSB: |
| 14440 | case SystemZ::VFNMADB: |
| 14441 | case SystemZ::VFNMASB: |
| 14442 | case SystemZ::VFNMSDB: |
| 14443 | case SystemZ::VFNMSSB: |
| 14444 | case SystemZ::VGFMAB: |
| 14445 | case SystemZ::VGFMAF: |
| 14446 | case SystemZ::VGFMAG: |
| 14447 | case SystemZ::VGFMAH: |
| 14448 | case SystemZ::VMAEB: |
| 14449 | case SystemZ::VMAEF: |
| 14450 | case SystemZ::VMAEG: |
| 14451 | case SystemZ::VMAEH: |
| 14452 | case SystemZ::VMAHB: |
| 14453 | case SystemZ::VMAHF: |
| 14454 | case SystemZ::VMAHG: |
| 14455 | case SystemZ::VMAHH: |
| 14456 | case SystemZ::VMAHQ: |
| 14457 | case SystemZ::VMALB: |
| 14458 | case SystemZ::VMALEB: |
| 14459 | case SystemZ::VMALEF: |
| 14460 | case SystemZ::VMALEG: |
| 14461 | case SystemZ::VMALEH: |
| 14462 | case SystemZ::VMALF: |
| 14463 | case SystemZ::VMALG: |
| 14464 | case SystemZ::VMALHB: |
| 14465 | case SystemZ::VMALHF: |
| 14466 | case SystemZ::VMALHG: |
| 14467 | case SystemZ::VMALHH: |
| 14468 | case SystemZ::VMALHQ: |
| 14469 | case SystemZ::VMALHW: |
| 14470 | case SystemZ::VMALOB: |
| 14471 | case SystemZ::VMALOF: |
| 14472 | case SystemZ::VMALOG: |
| 14473 | case SystemZ::VMALOH: |
| 14474 | case SystemZ::VMALQ: |
| 14475 | case SystemZ::VMAOB: |
| 14476 | case SystemZ::VMAOF: |
| 14477 | case SystemZ::VMAOG: |
| 14478 | case SystemZ::VMAOH: |
| 14479 | case SystemZ::VPERM: |
| 14480 | case SystemZ::VSBCBIQ: |
| 14481 | case SystemZ::VSBIQ: |
| 14482 | case SystemZ::VSEL: |
| 14483 | case SystemZ::VSTRSZB: |
| 14484 | case SystemZ::VSTRSZF: |
| 14485 | case SystemZ::VSTRSZH: |
| 14486 | case SystemZ::WFMADB: |
| 14487 | case SystemZ::WFMASB: |
| 14488 | case SystemZ::WFMAXB: |
| 14489 | case SystemZ::WFMSDB: |
| 14490 | case SystemZ::WFMSSB: |
| 14491 | case SystemZ::WFMSXB: |
| 14492 | case SystemZ::WFNMADB: |
| 14493 | case SystemZ::WFNMASB: |
| 14494 | case SystemZ::WFNMAXB: |
| 14495 | case SystemZ::WFNMSDB: |
| 14496 | case SystemZ::WFNMSSB: |
| 14497 | case SystemZ::WFNMSXB: { |
| 14498 | switch (OpNum) { |
| 14499 | case 0: |
| 14500 | // op: V1 |
| 14501 | return 11; |
| 14502 | case 1: |
| 14503 | // op: V2 |
| 14504 | return 10; |
| 14505 | case 2: |
| 14506 | // op: V3 |
| 14507 | return 9; |
| 14508 | case 3: |
| 14509 | // op: V4 |
| 14510 | return 8; |
| 14511 | } |
| 14512 | break; |
| 14513 | } |
| 14514 | case SystemZ::VAB: |
| 14515 | case SystemZ::VACCB: |
| 14516 | case SystemZ::VACCF: |
| 14517 | case SystemZ::VACCG: |
| 14518 | case SystemZ::VACCH: |
| 14519 | case SystemZ::VACCQ: |
| 14520 | case SystemZ::VAF: |
| 14521 | case SystemZ::VAG: |
| 14522 | case SystemZ::VAH: |
| 14523 | case SystemZ::VAQ: |
| 14524 | case SystemZ::VAVGB: |
| 14525 | case SystemZ::VAVGF: |
| 14526 | case SystemZ::VAVGG: |
| 14527 | case SystemZ::VAVGH: |
| 14528 | case SystemZ::VAVGLB: |
| 14529 | case SystemZ::VAVGLF: |
| 14530 | case SystemZ::VAVGLG: |
| 14531 | case SystemZ::VAVGLH: |
| 14532 | case SystemZ::VAVGLQ: |
| 14533 | case SystemZ::VAVGQ: |
| 14534 | case SystemZ::VBPERM: |
| 14535 | case SystemZ::VCEQB: |
| 14536 | case SystemZ::VCEQBS: |
| 14537 | case SystemZ::VCEQF: |
| 14538 | case SystemZ::VCEQFS: |
| 14539 | case SystemZ::VCEQG: |
| 14540 | case SystemZ::VCEQGS: |
| 14541 | case SystemZ::VCEQH: |
| 14542 | case SystemZ::VCEQHS: |
| 14543 | case SystemZ::VCEQQ: |
| 14544 | case SystemZ::VCEQQS: |
| 14545 | case SystemZ::VCHB: |
| 14546 | case SystemZ::VCHBS: |
| 14547 | case SystemZ::VCHF: |
| 14548 | case SystemZ::VCHFS: |
| 14549 | case SystemZ::VCHG: |
| 14550 | case SystemZ::VCHGS: |
| 14551 | case SystemZ::VCHH: |
| 14552 | case SystemZ::VCHHS: |
| 14553 | case SystemZ::VCHLB: |
| 14554 | case SystemZ::VCHLBS: |
| 14555 | case SystemZ::VCHLF: |
| 14556 | case SystemZ::VCHLFS: |
| 14557 | case SystemZ::VCHLG: |
| 14558 | case SystemZ::VCHLGS: |
| 14559 | case SystemZ::VCHLH: |
| 14560 | case SystemZ::VCHLHS: |
| 14561 | case SystemZ::VCHLQ: |
| 14562 | case SystemZ::VCHLQS: |
| 14563 | case SystemZ::VCHQ: |
| 14564 | case SystemZ::VCHQS: |
| 14565 | case SystemZ::VCKSM: |
| 14566 | case SystemZ::VERLLVB: |
| 14567 | case SystemZ::VERLLVF: |
| 14568 | case SystemZ::VERLLVG: |
| 14569 | case SystemZ::VERLLVH: |
| 14570 | case SystemZ::VESLVB: |
| 14571 | case SystemZ::VESLVF: |
| 14572 | case SystemZ::VESLVG: |
| 14573 | case SystemZ::VESLVH: |
| 14574 | case SystemZ::VESRAVB: |
| 14575 | case SystemZ::VESRAVF: |
| 14576 | case SystemZ::VESRAVG: |
| 14577 | case SystemZ::VESRAVH: |
| 14578 | case SystemZ::VESRLVB: |
| 14579 | case SystemZ::VESRLVF: |
| 14580 | case SystemZ::VESRLVG: |
| 14581 | case SystemZ::VESRLVH: |
| 14582 | case SystemZ::VFADB: |
| 14583 | case SystemZ::VFASB: |
| 14584 | case SystemZ::VFCEDB: |
| 14585 | case SystemZ::VFCEDBS: |
| 14586 | case SystemZ::VFCESB: |
| 14587 | case SystemZ::VFCESBS: |
| 14588 | case SystemZ::VFCHDB: |
| 14589 | case SystemZ::VFCHDBS: |
| 14590 | case SystemZ::VFCHEDB: |
| 14591 | case SystemZ::VFCHEDBS: |
| 14592 | case SystemZ::VFCHESB: |
| 14593 | case SystemZ::VFCHESBS: |
| 14594 | case SystemZ::VFCHSB: |
| 14595 | case SystemZ::VFCHSBS: |
| 14596 | case SystemZ::VFDDB: |
| 14597 | case SystemZ::VFDSB: |
| 14598 | case SystemZ::VFEEBS: |
| 14599 | case SystemZ::VFEEFS: |
| 14600 | case SystemZ::VFEEHS: |
| 14601 | case SystemZ::VFEEZB: |
| 14602 | case SystemZ::VFEEZBS: |
| 14603 | case SystemZ::VFEEZF: |
| 14604 | case SystemZ::VFEEZFS: |
| 14605 | case SystemZ::VFEEZH: |
| 14606 | case SystemZ::VFEEZHS: |
| 14607 | case SystemZ::VFENEBS: |
| 14608 | case SystemZ::VFENEFS: |
| 14609 | case SystemZ::VFENEHS: |
| 14610 | case SystemZ::VFENEZB: |
| 14611 | case SystemZ::VFENEZBS: |
| 14612 | case SystemZ::VFENEZF: |
| 14613 | case SystemZ::VFENEZFS: |
| 14614 | case SystemZ::VFENEZH: |
| 14615 | case SystemZ::VFENEZHS: |
| 14616 | case SystemZ::VFKEDB: |
| 14617 | case SystemZ::VFKEDBS: |
| 14618 | case SystemZ::VFKESB: |
| 14619 | case SystemZ::VFKESBS: |
| 14620 | case SystemZ::VFKHDB: |
| 14621 | case SystemZ::VFKHDBS: |
| 14622 | case SystemZ::VFKHEDB: |
| 14623 | case SystemZ::VFKHEDBS: |
| 14624 | case SystemZ::VFKHESB: |
| 14625 | case SystemZ::VFKHESBS: |
| 14626 | case SystemZ::VFKHSB: |
| 14627 | case SystemZ::VFKHSBS: |
| 14628 | case SystemZ::VFMDB: |
| 14629 | case SystemZ::VFMSB: |
| 14630 | case SystemZ::VFSDB: |
| 14631 | case SystemZ::VFSSB: |
| 14632 | case SystemZ::VGFMB: |
| 14633 | case SystemZ::VGFMF: |
| 14634 | case SystemZ::VGFMG: |
| 14635 | case SystemZ::VGFMH: |
| 14636 | case SystemZ::VMEB: |
| 14637 | case SystemZ::VMEF: |
| 14638 | case SystemZ::VMEG: |
| 14639 | case SystemZ::VMEH: |
| 14640 | case SystemZ::VMHB: |
| 14641 | case SystemZ::VMHF: |
| 14642 | case SystemZ::VMHG: |
| 14643 | case SystemZ::VMHH: |
| 14644 | case SystemZ::VMHQ: |
| 14645 | case SystemZ::VMLB: |
| 14646 | case SystemZ::VMLEB: |
| 14647 | case SystemZ::VMLEF: |
| 14648 | case SystemZ::VMLEG: |
| 14649 | case SystemZ::VMLEH: |
| 14650 | case SystemZ::VMLF: |
| 14651 | case SystemZ::VMLG: |
| 14652 | case SystemZ::VMLHB: |
| 14653 | case SystemZ::VMLHF: |
| 14654 | case SystemZ::VMLHG: |
| 14655 | case SystemZ::VMLHH: |
| 14656 | case SystemZ::VMLHQ: |
| 14657 | case SystemZ::VMLHW: |
| 14658 | case SystemZ::VMLOB: |
| 14659 | case SystemZ::VMLOF: |
| 14660 | case SystemZ::VMLOG: |
| 14661 | case SystemZ::VMLOH: |
| 14662 | case SystemZ::VMLQ: |
| 14663 | case SystemZ::VMNB: |
| 14664 | case SystemZ::VMNF: |
| 14665 | case SystemZ::VMNG: |
| 14666 | case SystemZ::VMNH: |
| 14667 | case SystemZ::VMNLB: |
| 14668 | case SystemZ::VMNLF: |
| 14669 | case SystemZ::VMNLG: |
| 14670 | case SystemZ::VMNLH: |
| 14671 | case SystemZ::VMNLQ: |
| 14672 | case SystemZ::VMNQ: |
| 14673 | case SystemZ::VMOB: |
| 14674 | case SystemZ::VMOF: |
| 14675 | case SystemZ::VMOG: |
| 14676 | case SystemZ::VMOH: |
| 14677 | case SystemZ::VMRHB: |
| 14678 | case SystemZ::VMRHF: |
| 14679 | case SystemZ::VMRHG: |
| 14680 | case SystemZ::VMRHH: |
| 14681 | case SystemZ::VMRLB: |
| 14682 | case SystemZ::VMRLF: |
| 14683 | case SystemZ::VMRLG: |
| 14684 | case SystemZ::VMRLH: |
| 14685 | case SystemZ::VMXB: |
| 14686 | case SystemZ::VMXF: |
| 14687 | case SystemZ::VMXG: |
| 14688 | case SystemZ::VMXH: |
| 14689 | case SystemZ::VMXLB: |
| 14690 | case SystemZ::VMXLF: |
| 14691 | case SystemZ::VMXLG: |
| 14692 | case SystemZ::VMXLH: |
| 14693 | case SystemZ::VMXLQ: |
| 14694 | case SystemZ::VMXQ: |
| 14695 | case SystemZ::VN: |
| 14696 | case SystemZ::VNC: |
| 14697 | case SystemZ::VNN: |
| 14698 | case SystemZ::VNO: |
| 14699 | case SystemZ::VNX: |
| 14700 | case SystemZ::VO: |
| 14701 | case SystemZ::VOC: |
| 14702 | case SystemZ::VPKF: |
| 14703 | case SystemZ::VPKG: |
| 14704 | case SystemZ::VPKH: |
| 14705 | case SystemZ::VPKLSF: |
| 14706 | case SystemZ::VPKLSFS: |
| 14707 | case SystemZ::VPKLSG: |
| 14708 | case SystemZ::VPKLSGS: |
| 14709 | case SystemZ::VPKLSH: |
| 14710 | case SystemZ::VPKLSHS: |
| 14711 | case SystemZ::VPKSF: |
| 14712 | case SystemZ::VPKSFS: |
| 14713 | case SystemZ::VPKSG: |
| 14714 | case SystemZ::VPKSGS: |
| 14715 | case SystemZ::VPKSH: |
| 14716 | case SystemZ::VPKSHS: |
| 14717 | case SystemZ::VSB: |
| 14718 | case SystemZ::VSCBIB: |
| 14719 | case SystemZ::VSCBIF: |
| 14720 | case SystemZ::VSCBIG: |
| 14721 | case SystemZ::VSCBIH: |
| 14722 | case SystemZ::VSCBIQ: |
| 14723 | case SystemZ::VSCSHP: |
| 14724 | case SystemZ::VSF: |
| 14725 | case SystemZ::VSG: |
| 14726 | case SystemZ::VSH: |
| 14727 | case SystemZ::VSL: |
| 14728 | case SystemZ::VSLB: |
| 14729 | case SystemZ::VSQ: |
| 14730 | case SystemZ::VSRA: |
| 14731 | case SystemZ::VSRAB: |
| 14732 | case SystemZ::VSRL: |
| 14733 | case SystemZ::VSRLB: |
| 14734 | case SystemZ::VSUMB: |
| 14735 | case SystemZ::VSUMGF: |
| 14736 | case SystemZ::VSUMGH: |
| 14737 | case SystemZ::VSUMH: |
| 14738 | case SystemZ::VSUMQF: |
| 14739 | case SystemZ::VSUMQG: |
| 14740 | case SystemZ::VX: |
| 14741 | case SystemZ::WFADB: |
| 14742 | case SystemZ::WFASB: |
| 14743 | case SystemZ::WFAXB: |
| 14744 | case SystemZ::WFCEDB: |
| 14745 | case SystemZ::WFCEDBS: |
| 14746 | case SystemZ::WFCESB: |
| 14747 | case SystemZ::WFCESBS: |
| 14748 | case SystemZ::WFCEXB: |
| 14749 | case SystemZ::WFCEXBS: |
| 14750 | case SystemZ::WFCHDB: |
| 14751 | case SystemZ::WFCHDBS: |
| 14752 | case SystemZ::WFCHEDB: |
| 14753 | case SystemZ::WFCHEDBS: |
| 14754 | case SystemZ::WFCHESB: |
| 14755 | case SystemZ::WFCHESBS: |
| 14756 | case SystemZ::WFCHEXB: |
| 14757 | case SystemZ::WFCHEXBS: |
| 14758 | case SystemZ::WFCHSB: |
| 14759 | case SystemZ::WFCHSBS: |
| 14760 | case SystemZ::WFCHXB: |
| 14761 | case SystemZ::WFCHXBS: |
| 14762 | case SystemZ::WFDDB: |
| 14763 | case SystemZ::WFDSB: |
| 14764 | case SystemZ::WFDXB: |
| 14765 | case SystemZ::WFKEDB: |
| 14766 | case SystemZ::WFKEDBS: |
| 14767 | case SystemZ::WFKESB: |
| 14768 | case SystemZ::WFKESBS: |
| 14769 | case SystemZ::WFKEXB: |
| 14770 | case SystemZ::WFKEXBS: |
| 14771 | case SystemZ::WFKHDB: |
| 14772 | case SystemZ::WFKHDBS: |
| 14773 | case SystemZ::WFKHEDB: |
| 14774 | case SystemZ::WFKHEDBS: |
| 14775 | case SystemZ::WFKHESB: |
| 14776 | case SystemZ::WFKHESBS: |
| 14777 | case SystemZ::WFKHEXB: |
| 14778 | case SystemZ::WFKHEXBS: |
| 14779 | case SystemZ::WFKHSB: |
| 14780 | case SystemZ::WFKHSBS: |
| 14781 | case SystemZ::WFKHXB: |
| 14782 | case SystemZ::WFKHXBS: |
| 14783 | case SystemZ::WFMDB: |
| 14784 | case SystemZ::WFMSB: |
| 14785 | case SystemZ::WFMXB: |
| 14786 | case SystemZ::WFSDB: |
| 14787 | case SystemZ::WFSSB: |
| 14788 | case SystemZ::WFSXB: { |
| 14789 | switch (OpNum) { |
| 14790 | case 0: |
| 14791 | // op: V1 |
| 14792 | return 11; |
| 14793 | case 1: |
| 14794 | // op: V2 |
| 14795 | return 10; |
| 14796 | case 2: |
| 14797 | // op: V3 |
| 14798 | return 9; |
| 14799 | } |
| 14800 | break; |
| 14801 | } |
| 14802 | case SystemZ::VCLZB: |
| 14803 | case SystemZ::VCLZF: |
| 14804 | case SystemZ::VCLZG: |
| 14805 | case SystemZ::VCLZH: |
| 14806 | case SystemZ::VCLZQ: |
| 14807 | case SystemZ::VCTZB: |
| 14808 | case SystemZ::VCTZF: |
| 14809 | case SystemZ::VCTZG: |
| 14810 | case SystemZ::VCTZH: |
| 14811 | case SystemZ::VCTZQ: |
| 14812 | case SystemZ::VECB: |
| 14813 | case SystemZ::VECF: |
| 14814 | case SystemZ::VECG: |
| 14815 | case SystemZ::VECH: |
| 14816 | case SystemZ::VECLB: |
| 14817 | case SystemZ::VECLF: |
| 14818 | case SystemZ::VECLG: |
| 14819 | case SystemZ::VECLH: |
| 14820 | case SystemZ::VECLQ: |
| 14821 | case SystemZ::VECQ: |
| 14822 | case SystemZ::VFLCDB: |
| 14823 | case SystemZ::VFLCSB: |
| 14824 | case SystemZ::VFLLS: |
| 14825 | case SystemZ::VFLNDB: |
| 14826 | case SystemZ::VFLNSB: |
| 14827 | case SystemZ::VFLPDB: |
| 14828 | case SystemZ::VFLPSB: |
| 14829 | case SystemZ::VFSQDB: |
| 14830 | case SystemZ::VFSQSB: |
| 14831 | case SystemZ::VGEMB: |
| 14832 | case SystemZ::VGEMF: |
| 14833 | case SystemZ::VGEMG: |
| 14834 | case SystemZ::VGEMH: |
| 14835 | case SystemZ::VGEMQ: |
| 14836 | case SystemZ::VISTRBS: |
| 14837 | case SystemZ::VISTRFS: |
| 14838 | case SystemZ::VISTRHS: |
| 14839 | case SystemZ::VLCB: |
| 14840 | case SystemZ::VLCF: |
| 14841 | case SystemZ::VLCG: |
| 14842 | case SystemZ::VLCH: |
| 14843 | case SystemZ::VLCQ: |
| 14844 | case SystemZ::VLDEB: |
| 14845 | case SystemZ::VLPB: |
| 14846 | case SystemZ::VLPF: |
| 14847 | case SystemZ::VLPG: |
| 14848 | case SystemZ::VLPH: |
| 14849 | case SystemZ::VLPQ: |
| 14850 | case SystemZ::VLR: |
| 14851 | case SystemZ::VPOPCTB: |
| 14852 | case SystemZ::VPOPCTF: |
| 14853 | case SystemZ::VPOPCTG: |
| 14854 | case SystemZ::VPOPCTH: |
| 14855 | case SystemZ::VSEGB: |
| 14856 | case SystemZ::VSEGF: |
| 14857 | case SystemZ::VSEGH: |
| 14858 | case SystemZ::VTM: |
| 14859 | case SystemZ::VUPHB: |
| 14860 | case SystemZ::VUPHF: |
| 14861 | case SystemZ::VUPHG: |
| 14862 | case SystemZ::VUPHH: |
| 14863 | case SystemZ::VUPLB: |
| 14864 | case SystemZ::VUPLF: |
| 14865 | case SystemZ::VUPLG: |
| 14866 | case SystemZ::VUPLHB: |
| 14867 | case SystemZ::VUPLHF: |
| 14868 | case SystemZ::VUPLHG: |
| 14869 | case SystemZ::VUPLHH: |
| 14870 | case SystemZ::VUPLHW: |
| 14871 | case SystemZ::VUPLLB: |
| 14872 | case SystemZ::VUPLLF: |
| 14873 | case SystemZ::VUPLLG: |
| 14874 | case SystemZ::VUPLLH: |
| 14875 | case SystemZ::WFCDB: |
| 14876 | case SystemZ::WFCSB: |
| 14877 | case SystemZ::WFCXB: |
| 14878 | case SystemZ::WFKDB: |
| 14879 | case SystemZ::WFKSB: |
| 14880 | case SystemZ::WFKXB: |
| 14881 | case SystemZ::WFLCDB: |
| 14882 | case SystemZ::WFLCSB: |
| 14883 | case SystemZ::WFLCXB: |
| 14884 | case SystemZ::WFLLD: |
| 14885 | case SystemZ::WFLLS: |
| 14886 | case SystemZ::WFLNDB: |
| 14887 | case SystemZ::WFLNSB: |
| 14888 | case SystemZ::WFLNXB: |
| 14889 | case SystemZ::WFLPDB: |
| 14890 | case SystemZ::WFLPSB: |
| 14891 | case SystemZ::WFLPXB: |
| 14892 | case SystemZ::WFSQDB: |
| 14893 | case SystemZ::WFSQSB: |
| 14894 | case SystemZ::WFSQXB: |
| 14895 | case SystemZ::WLDEB: { |
| 14896 | switch (OpNum) { |
| 14897 | case 0: |
| 14898 | // op: V1 |
| 14899 | return 11; |
| 14900 | case 1: |
| 14901 | // op: V2 |
| 14902 | return 10; |
| 14903 | } |
| 14904 | break; |
| 14905 | } |
| 14906 | case SystemZ::VREP: { |
| 14907 | switch (OpNum) { |
| 14908 | case 0: |
| 14909 | // op: V1 |
| 14910 | return 11; |
| 14911 | case 1: |
| 14912 | // op: V3 |
| 14913 | return 10; |
| 14914 | case 2: |
| 14915 | // op: I2 |
| 14916 | return 16; |
| 14917 | case 3: |
| 14918 | // op: M4 |
| 14919 | return 12; |
| 14920 | } |
| 14921 | break; |
| 14922 | } |
| 14923 | case SystemZ::VREPB: |
| 14924 | case SystemZ::VREPF: |
| 14925 | case SystemZ::VREPG: |
| 14926 | case SystemZ::VREPH: { |
| 14927 | switch (OpNum) { |
| 14928 | case 0: |
| 14929 | // op: V1 |
| 14930 | return 11; |
| 14931 | case 1: |
| 14932 | // op: V3 |
| 14933 | return 10; |
| 14934 | case 2: |
| 14935 | // op: I2 |
| 14936 | return 16; |
| 14937 | } |
| 14938 | break; |
| 14939 | } |
| 14940 | case SystemZ::VLL: |
| 14941 | case SystemZ::VSTL: { |
| 14942 | switch (OpNum) { |
| 14943 | case 0: |
| 14944 | // op: V1 |
| 14945 | return 11; |
| 14946 | case 2: |
| 14947 | // op: B2 |
| 14948 | return 28; |
| 14949 | case 3: |
| 14950 | // op: D2 |
| 14951 | return 16; |
| 14952 | case 1: |
| 14953 | // op: R3 |
| 14954 | return 32; |
| 14955 | } |
| 14956 | break; |
| 14957 | } |
| 14958 | case SystemZ::VERLL: |
| 14959 | case SystemZ::VESL: |
| 14960 | case SystemZ::VESRA: |
| 14961 | case SystemZ::VESRL: |
| 14962 | case SystemZ::VLMAlign: |
| 14963 | case SystemZ::VSTMAlign: { |
| 14964 | switch (OpNum) { |
| 14965 | case 0: |
| 14966 | // op: V1 |
| 14967 | return 11; |
| 14968 | case 2: |
| 14969 | // op: B2 |
| 14970 | return 28; |
| 14971 | case 3: |
| 14972 | // op: D2 |
| 14973 | return 16; |
| 14974 | case 1: |
| 14975 | // op: V3 |
| 14976 | return 10; |
| 14977 | case 4: |
| 14978 | // op: M4 |
| 14979 | return 12; |
| 14980 | } |
| 14981 | break; |
| 14982 | } |
| 14983 | case SystemZ::VERLLB: |
| 14984 | case SystemZ::VERLLF: |
| 14985 | case SystemZ::VERLLG: |
| 14986 | case SystemZ::VERLLH: |
| 14987 | case SystemZ::VESLB: |
| 14988 | case SystemZ::VESLF: |
| 14989 | case SystemZ::VESLG: |
| 14990 | case SystemZ::VESLH: |
| 14991 | case SystemZ::VESRAB: |
| 14992 | case SystemZ::VESRAF: |
| 14993 | case SystemZ::VESRAG: |
| 14994 | case SystemZ::VESRAH: |
| 14995 | case SystemZ::VESRLB: |
| 14996 | case SystemZ::VESRLF: |
| 14997 | case SystemZ::VESRLG: |
| 14998 | case SystemZ::VESRLH: |
| 14999 | case SystemZ::VLM: |
| 15000 | case SystemZ::VSTM: { |
| 15001 | switch (OpNum) { |
| 15002 | case 0: |
| 15003 | // op: V1 |
| 15004 | return 11; |
| 15005 | case 2: |
| 15006 | // op: B2 |
| 15007 | return 28; |
| 15008 | case 3: |
| 15009 | // op: D2 |
| 15010 | return 16; |
| 15011 | case 1: |
| 15012 | // op: V3 |
| 15013 | return 10; |
| 15014 | } |
| 15015 | break; |
| 15016 | } |
| 15017 | case SystemZ::VLEIB: |
| 15018 | case SystemZ::VLEIF: |
| 15019 | case SystemZ::VLEIG: |
| 15020 | case SystemZ::VLEIH: { |
| 15021 | switch (OpNum) { |
| 15022 | case 0: |
| 15023 | // op: V1 |
| 15024 | return 11; |
| 15025 | case 2: |
| 15026 | // op: I2 |
| 15027 | return 16; |
| 15028 | case 3: |
| 15029 | // op: M3 |
| 15030 | return 12; |
| 15031 | } |
| 15032 | break; |
| 15033 | } |
| 15034 | case SystemZ::VERIM: { |
| 15035 | switch (OpNum) { |
| 15036 | case 0: |
| 15037 | // op: V1 |
| 15038 | return 11; |
| 15039 | case 2: |
| 15040 | // op: V2 |
| 15041 | return 10; |
| 15042 | case 3: |
| 15043 | // op: V3 |
| 15044 | return 9; |
| 15045 | case 4: |
| 15046 | // op: I4 |
| 15047 | return 16; |
| 15048 | case 5: |
| 15049 | // op: M5 |
| 15050 | return 12; |
| 15051 | } |
| 15052 | break; |
| 15053 | } |
| 15054 | case SystemZ::VERIMB: |
| 15055 | case SystemZ::VERIMF: |
| 15056 | case SystemZ::VERIMG: |
| 15057 | case SystemZ::VERIMH: { |
| 15058 | switch (OpNum) { |
| 15059 | case 0: |
| 15060 | // op: V1 |
| 15061 | return 11; |
| 15062 | case 2: |
| 15063 | // op: V2 |
| 15064 | return 10; |
| 15065 | case 3: |
| 15066 | // op: V3 |
| 15067 | return 9; |
| 15068 | case 4: |
| 15069 | // op: I4 |
| 15070 | return 16; |
| 15071 | } |
| 15072 | break; |
| 15073 | } |
| 15074 | case SystemZ::VLVG: { |
| 15075 | switch (OpNum) { |
| 15076 | case 0: |
| 15077 | // op: V1 |
| 15078 | return 11; |
| 15079 | case 3: |
| 15080 | // op: B2 |
| 15081 | return 28; |
| 15082 | case 4: |
| 15083 | // op: D2 |
| 15084 | return 16; |
| 15085 | case 2: |
| 15086 | // op: R3 |
| 15087 | return 32; |
| 15088 | case 5: |
| 15089 | // op: M4 |
| 15090 | return 12; |
| 15091 | } |
| 15092 | break; |
| 15093 | } |
| 15094 | case SystemZ::VLVGB: |
| 15095 | case SystemZ::VLVGF: |
| 15096 | case SystemZ::VLVGG: |
| 15097 | case SystemZ::VLVGH: { |
| 15098 | switch (OpNum) { |
| 15099 | case 0: |
| 15100 | // op: V1 |
| 15101 | return 11; |
| 15102 | case 3: |
| 15103 | // op: B2 |
| 15104 | return 28; |
| 15105 | case 4: |
| 15106 | // op: D2 |
| 15107 | return 16; |
| 15108 | case 2: |
| 15109 | // op: R3 |
| 15110 | return 32; |
| 15111 | } |
| 15112 | break; |
| 15113 | } |
| 15114 | case SystemZ::VSCEF: |
| 15115 | case SystemZ::VSCEG: { |
| 15116 | switch (OpNum) { |
| 15117 | case 0: |
| 15118 | // op: V1 |
| 15119 | return 11; |
| 15120 | case 3: |
| 15121 | // op: V2 |
| 15122 | return 10; |
| 15123 | case 1: |
| 15124 | // op: B2 |
| 15125 | return 28; |
| 15126 | case 2: |
| 15127 | // op: D2 |
| 15128 | return 16; |
| 15129 | case 4: |
| 15130 | // op: M3 |
| 15131 | return 12; |
| 15132 | } |
| 15133 | break; |
| 15134 | } |
| 15135 | case SystemZ::VLAlign: |
| 15136 | case SystemZ::VLBB: |
| 15137 | case SystemZ::VLBR: |
| 15138 | case SystemZ::VLBRREP: |
| 15139 | case SystemZ::VLER: |
| 15140 | case SystemZ::VLLEBRZ: |
| 15141 | case SystemZ::VLLEZ: |
| 15142 | case SystemZ::VLREP: |
| 15143 | case SystemZ::VSTAlign: |
| 15144 | case SystemZ::VSTBR: |
| 15145 | case SystemZ::VSTEB: |
| 15146 | case SystemZ::VSTEBRF: |
| 15147 | case SystemZ::VSTEBRG: |
| 15148 | case SystemZ::VSTEBRH: |
| 15149 | case SystemZ::VSTEF: |
| 15150 | case SystemZ::VSTEG: |
| 15151 | case SystemZ::VSTEH: |
| 15152 | case SystemZ::VSTER: { |
| 15153 | switch (OpNum) { |
| 15154 | case 0: |
| 15155 | // op: V1 |
| 15156 | return 11; |
| 15157 | case 3: |
| 15158 | // op: X2 |
| 15159 | return 32; |
| 15160 | case 1: |
| 15161 | // op: B2 |
| 15162 | return 28; |
| 15163 | case 2: |
| 15164 | // op: D2 |
| 15165 | return 16; |
| 15166 | case 4: |
| 15167 | // op: M3 |
| 15168 | return 12; |
| 15169 | } |
| 15170 | break; |
| 15171 | } |
| 15172 | case SystemZ::VL: |
| 15173 | case SystemZ::VLBRF: |
| 15174 | case SystemZ::VLBRG: |
| 15175 | case SystemZ::VLBRH: |
| 15176 | case SystemZ::VLBRQ: |
| 15177 | case SystemZ::VLBRREPF: |
| 15178 | case SystemZ::VLBRREPG: |
| 15179 | case SystemZ::VLBRREPH: |
| 15180 | case SystemZ::VLERF: |
| 15181 | case SystemZ::VLERG: |
| 15182 | case SystemZ::VLERH: |
| 15183 | case SystemZ::VLLEBRZE: |
| 15184 | case SystemZ::VLLEBRZF: |
| 15185 | case SystemZ::VLLEBRZG: |
| 15186 | case SystemZ::VLLEBRZH: |
| 15187 | case SystemZ::VLLEZB: |
| 15188 | case SystemZ::VLLEZF: |
| 15189 | case SystemZ::VLLEZG: |
| 15190 | case SystemZ::VLLEZH: |
| 15191 | case SystemZ::VLLEZLF: |
| 15192 | case SystemZ::VLREPB: |
| 15193 | case SystemZ::VLREPF: |
| 15194 | case SystemZ::VLREPG: |
| 15195 | case SystemZ::VLREPH: |
| 15196 | case SystemZ::VST: |
| 15197 | case SystemZ::VSTBRF: |
| 15198 | case SystemZ::VSTBRG: |
| 15199 | case SystemZ::VSTBRH: |
| 15200 | case SystemZ::VSTBRQ: |
| 15201 | case SystemZ::VSTERF: |
| 15202 | case SystemZ::VSTERG: |
| 15203 | case SystemZ::VSTERH: { |
| 15204 | switch (OpNum) { |
| 15205 | case 0: |
| 15206 | // op: V1 |
| 15207 | return 11; |
| 15208 | case 3: |
| 15209 | // op: X2 |
| 15210 | return 32; |
| 15211 | case 1: |
| 15212 | // op: B2 |
| 15213 | return 28; |
| 15214 | case 2: |
| 15215 | // op: D2 |
| 15216 | return 16; |
| 15217 | } |
| 15218 | break; |
| 15219 | } |
| 15220 | case SystemZ::VGEF: |
| 15221 | case SystemZ::VGEG: { |
| 15222 | switch (OpNum) { |
| 15223 | case 0: |
| 15224 | // op: V1 |
| 15225 | return 11; |
| 15226 | case 4: |
| 15227 | // op: V2 |
| 15228 | return 10; |
| 15229 | case 2: |
| 15230 | // op: B2 |
| 15231 | return 28; |
| 15232 | case 3: |
| 15233 | // op: D2 |
| 15234 | return 16; |
| 15235 | case 5: |
| 15236 | // op: M3 |
| 15237 | return 12; |
| 15238 | } |
| 15239 | break; |
| 15240 | } |
| 15241 | case SystemZ::VLEB: |
| 15242 | case SystemZ::VLEBRF: |
| 15243 | case SystemZ::VLEBRG: |
| 15244 | case SystemZ::VLEBRH: |
| 15245 | case SystemZ::VLEF: |
| 15246 | case SystemZ::VLEG: |
| 15247 | case SystemZ::VLEH: { |
| 15248 | switch (OpNum) { |
| 15249 | case 0: |
| 15250 | // op: V1 |
| 15251 | return 11; |
| 15252 | case 4: |
| 15253 | // op: X2 |
| 15254 | return 32; |
| 15255 | case 2: |
| 15256 | // op: B2 |
| 15257 | return 28; |
| 15258 | case 3: |
| 15259 | // op: D2 |
| 15260 | return 16; |
| 15261 | case 5: |
| 15262 | // op: M3 |
| 15263 | return 12; |
| 15264 | } |
| 15265 | break; |
| 15266 | } |
| 15267 | case SystemZ::VONE: |
| 15268 | case SystemZ::VZERO: { |
| 15269 | switch (OpNum) { |
| 15270 | case 0: |
| 15271 | // op: V1 |
| 15272 | return 11; |
| 15273 | } |
| 15274 | break; |
| 15275 | } |
| 15276 | case SystemZ::VLRL: |
| 15277 | case SystemZ::VPKZ: |
| 15278 | case SystemZ::VSTRL: |
| 15279 | case SystemZ::VUPKZ: { |
| 15280 | switch (OpNum) { |
| 15281 | case 0: |
| 15282 | // op: V1 |
| 15283 | return 8; |
| 15284 | case 1: |
| 15285 | // op: B2 |
| 15286 | return 28; |
| 15287 | case 2: |
| 15288 | // op: D2 |
| 15289 | return 16; |
| 15290 | case 3: |
| 15291 | // op: I3 |
| 15292 | return 32; |
| 15293 | } |
| 15294 | break; |
| 15295 | } |
| 15296 | case SystemZ::VLRLR: |
| 15297 | case SystemZ::VSTRLR: { |
| 15298 | switch (OpNum) { |
| 15299 | case 0: |
| 15300 | // op: V1 |
| 15301 | return 8; |
| 15302 | case 2: |
| 15303 | // op: B2 |
| 15304 | return 28; |
| 15305 | case 3: |
| 15306 | // op: D2 |
| 15307 | return 16; |
| 15308 | case 1: |
| 15309 | // op: R3 |
| 15310 | return 32; |
| 15311 | } |
| 15312 | break; |
| 15313 | } |
| 15314 | case SystemZ::InsnRSLa: { |
| 15315 | switch (OpNum) { |
| 15316 | case 0: |
| 15317 | // op: enc |
| 15318 | return 0; |
| 15319 | case 1: |
| 15320 | // op: B1 |
| 15321 | return 28; |
| 15322 | case 2: |
| 15323 | // op: D1 |
| 15324 | return 16; |
| 15325 | case 3: |
| 15326 | // op: L1 |
| 15327 | return 36; |
| 15328 | } |
| 15329 | break; |
| 15330 | } |
| 15331 | case SystemZ::InsnSIY: { |
| 15332 | switch (OpNum) { |
| 15333 | case 0: |
| 15334 | // op: enc |
| 15335 | return 0; |
| 15336 | case 1: |
| 15337 | // op: B1 |
| 15338 | return 28; |
| 15339 | case 2: |
| 15340 | // op: D1 |
| 15341 | return 8; |
| 15342 | case 3: |
| 15343 | // op: I2 |
| 15344 | return 32; |
| 15345 | } |
| 15346 | break; |
| 15347 | } |
| 15348 | case SystemZ::InsnRXYb: { |
| 15349 | switch (OpNum) { |
| 15350 | case 0: |
| 15351 | // op: enc |
| 15352 | return 0; |
| 15353 | case 1: |
| 15354 | // op: M1 |
| 15355 | return 36; |
| 15356 | case 4: |
| 15357 | // op: X2 |
| 15358 | return 32; |
| 15359 | case 2: |
| 15360 | // op: B2 |
| 15361 | return 28; |
| 15362 | case 3: |
| 15363 | // op: D2 |
| 15364 | return 8; |
| 15365 | } |
| 15366 | break; |
| 15367 | } |
| 15368 | case SystemZ::InsnRSLb: { |
| 15369 | switch (OpNum) { |
| 15370 | case 0: |
| 15371 | // op: enc |
| 15372 | return 0; |
| 15373 | case 1: |
| 15374 | // op: R1 |
| 15375 | return 12; |
| 15376 | case 2: |
| 15377 | // op: B2 |
| 15378 | return 28; |
| 15379 | case 3: |
| 15380 | // op: D2 |
| 15381 | return 16; |
| 15382 | case 4: |
| 15383 | // op: L2 |
| 15384 | return 32; |
| 15385 | case 5: |
| 15386 | // op: M3 |
| 15387 | return 8; |
| 15388 | } |
| 15389 | break; |
| 15390 | } |
| 15391 | case SystemZ::InsnRXF: { |
| 15392 | switch (OpNum) { |
| 15393 | case 0: |
| 15394 | // op: enc |
| 15395 | return 0; |
| 15396 | case 1: |
| 15397 | // op: R1 |
| 15398 | return 12; |
| 15399 | case 2: |
| 15400 | // op: R3 |
| 15401 | return 36; |
| 15402 | case 5: |
| 15403 | // op: X2 |
| 15404 | return 32; |
| 15405 | case 3: |
| 15406 | // op: B2 |
| 15407 | return 28; |
| 15408 | case 4: |
| 15409 | // op: D2 |
| 15410 | return 16; |
| 15411 | } |
| 15412 | break; |
| 15413 | } |
| 15414 | case SystemZ::InsnVRSc: { |
| 15415 | switch (OpNum) { |
| 15416 | case 0: |
| 15417 | // op: enc |
| 15418 | return 0; |
| 15419 | case 1: |
| 15420 | // op: R1 |
| 15421 | return 36; |
| 15422 | case 2: |
| 15423 | // op: B2 |
| 15424 | return 28; |
| 15425 | case 3: |
| 15426 | // op: D2 |
| 15427 | return 16; |
| 15428 | case 4: |
| 15429 | // op: V3 |
| 15430 | return 10; |
| 15431 | case 5: |
| 15432 | // op: M4 |
| 15433 | return 12; |
| 15434 | } |
| 15435 | break; |
| 15436 | } |
| 15437 | case SystemZ::InsnRIEa: { |
| 15438 | switch (OpNum) { |
| 15439 | case 0: |
| 15440 | // op: enc |
| 15441 | return 0; |
| 15442 | case 1: |
| 15443 | // op: R1 |
| 15444 | return 36; |
| 15445 | case 2: |
| 15446 | // op: I2 |
| 15447 | return 16; |
| 15448 | case 3: |
| 15449 | // op: M3 |
| 15450 | return 12; |
| 15451 | } |
| 15452 | break; |
| 15453 | } |
| 15454 | case SystemZ::InsnRIS: { |
| 15455 | switch (OpNum) { |
| 15456 | case 0: |
| 15457 | // op: enc |
| 15458 | return 0; |
| 15459 | case 1: |
| 15460 | // op: R1 |
| 15461 | return 36; |
| 15462 | case 2: |
| 15463 | // op: I2 |
| 15464 | return 8; |
| 15465 | case 3: |
| 15466 | // op: M3 |
| 15467 | return 32; |
| 15468 | case 4: |
| 15469 | // op: B4 |
| 15470 | return 28; |
| 15471 | case 5: |
| 15472 | // op: D4 |
| 15473 | return 16; |
| 15474 | } |
| 15475 | break; |
| 15476 | } |
| 15477 | case SystemZ::InsnRIEc: { |
| 15478 | switch (OpNum) { |
| 15479 | case 0: |
| 15480 | // op: enc |
| 15481 | return 0; |
| 15482 | case 1: |
| 15483 | // op: R1 |
| 15484 | return 36; |
| 15485 | case 2: |
| 15486 | // op: I2 |
| 15487 | return 8; |
| 15488 | case 3: |
| 15489 | // op: M3 |
| 15490 | return 32; |
| 15491 | case 4: |
| 15492 | // op: RI4 |
| 15493 | return 16; |
| 15494 | } |
| 15495 | break; |
| 15496 | } |
| 15497 | case SystemZ::InsnRIEf: { |
| 15498 | switch (OpNum) { |
| 15499 | case 0: |
| 15500 | // op: enc |
| 15501 | return 0; |
| 15502 | case 1: |
| 15503 | // op: R1 |
| 15504 | return 36; |
| 15505 | case 2: |
| 15506 | // op: R2 |
| 15507 | return 32; |
| 15508 | case 3: |
| 15509 | // op: I3 |
| 15510 | return 24; |
| 15511 | case 4: |
| 15512 | // op: I4 |
| 15513 | return 16; |
| 15514 | case 5: |
| 15515 | // op: I5 |
| 15516 | return 8; |
| 15517 | } |
| 15518 | break; |
| 15519 | } |
| 15520 | case SystemZ::InsnRRS: { |
| 15521 | switch (OpNum) { |
| 15522 | case 0: |
| 15523 | // op: enc |
| 15524 | return 0; |
| 15525 | case 1: |
| 15526 | // op: R1 |
| 15527 | return 36; |
| 15528 | case 2: |
| 15529 | // op: R2 |
| 15530 | return 32; |
| 15531 | case 3: |
| 15532 | // op: M3 |
| 15533 | return 12; |
| 15534 | case 4: |
| 15535 | // op: B4 |
| 15536 | return 28; |
| 15537 | case 5: |
| 15538 | // op: D4 |
| 15539 | return 16; |
| 15540 | } |
| 15541 | break; |
| 15542 | } |
| 15543 | case SystemZ::InsnRIEb: { |
| 15544 | switch (OpNum) { |
| 15545 | case 0: |
| 15546 | // op: enc |
| 15547 | return 0; |
| 15548 | case 1: |
| 15549 | // op: R1 |
| 15550 | return 36; |
| 15551 | case 2: |
| 15552 | // op: R2 |
| 15553 | return 32; |
| 15554 | case 3: |
| 15555 | // op: M3 |
| 15556 | return 12; |
| 15557 | case 4: |
| 15558 | // op: RI4 |
| 15559 | return 16; |
| 15560 | } |
| 15561 | break; |
| 15562 | } |
| 15563 | case SystemZ::InsnRSE: { |
| 15564 | switch (OpNum) { |
| 15565 | case 0: |
| 15566 | // op: enc |
| 15567 | return 0; |
| 15568 | case 1: |
| 15569 | // op: R1 |
| 15570 | return 36; |
| 15571 | case 2: |
| 15572 | // op: R3 |
| 15573 | return 32; |
| 15574 | case 3: |
| 15575 | // op: B2 |
| 15576 | return 28; |
| 15577 | case 4: |
| 15578 | // op: D2 |
| 15579 | return 16; |
| 15580 | } |
| 15581 | break; |
| 15582 | } |
| 15583 | case SystemZ::InsnRSY: { |
| 15584 | switch (OpNum) { |
| 15585 | case 0: |
| 15586 | // op: enc |
| 15587 | return 0; |
| 15588 | case 1: |
| 15589 | // op: R1 |
| 15590 | return 36; |
| 15591 | case 2: |
| 15592 | // op: R3 |
| 15593 | return 32; |
| 15594 | case 3: |
| 15595 | // op: B2 |
| 15596 | return 28; |
| 15597 | case 4: |
| 15598 | // op: D2 |
| 15599 | return 8; |
| 15600 | } |
| 15601 | break; |
| 15602 | } |
| 15603 | case SystemZ::InsnRIE: { |
| 15604 | switch (OpNum) { |
| 15605 | case 0: |
| 15606 | // op: enc |
| 15607 | return 0; |
| 15608 | case 1: |
| 15609 | // op: R1 |
| 15610 | return 36; |
| 15611 | case 2: |
| 15612 | // op: R3 |
| 15613 | return 32; |
| 15614 | case 3: |
| 15615 | // op: I2 |
| 15616 | return 16; |
| 15617 | } |
| 15618 | break; |
| 15619 | } |
| 15620 | case SystemZ::InsnVRRi: { |
| 15621 | switch (OpNum) { |
| 15622 | case 0: |
| 15623 | // op: enc |
| 15624 | return 0; |
| 15625 | case 1: |
| 15626 | // op: R1 |
| 15627 | return 36; |
| 15628 | case 2: |
| 15629 | // op: V2 |
| 15630 | return 10; |
| 15631 | case 3: |
| 15632 | // op: M3 |
| 15633 | return 20; |
| 15634 | case 4: |
| 15635 | // op: M4 |
| 15636 | return 16; |
| 15637 | } |
| 15638 | break; |
| 15639 | } |
| 15640 | case SystemZ::InsnVRS: { |
| 15641 | switch (OpNum) { |
| 15642 | case 0: |
| 15643 | // op: enc |
| 15644 | return 0; |
| 15645 | case 1: |
| 15646 | // op: R1 |
| 15647 | return 36; |
| 15648 | case 3: |
| 15649 | // op: B2 |
| 15650 | return 28; |
| 15651 | case 4: |
| 15652 | // op: D2 |
| 15653 | return 16; |
| 15654 | case 2: |
| 15655 | // op: V3 |
| 15656 | return 10; |
| 15657 | case 5: |
| 15658 | // op: M4 |
| 15659 | return 12; |
| 15660 | } |
| 15661 | break; |
| 15662 | } |
| 15663 | case SystemZ::InsnRIEg: { |
| 15664 | switch (OpNum) { |
| 15665 | case 0: |
| 15666 | // op: enc |
| 15667 | return 0; |
| 15668 | case 1: |
| 15669 | // op: R1 |
| 15670 | return 36; |
| 15671 | case 3: |
| 15672 | // op: M3 |
| 15673 | return 32; |
| 15674 | case 2: |
| 15675 | // op: I2 |
| 15676 | return 16; |
| 15677 | } |
| 15678 | break; |
| 15679 | } |
| 15680 | case SystemZ::InsnRIEd: { |
| 15681 | switch (OpNum) { |
| 15682 | case 0: |
| 15683 | // op: enc |
| 15684 | return 0; |
| 15685 | case 1: |
| 15686 | // op: R1 |
| 15687 | return 36; |
| 15688 | case 3: |
| 15689 | // op: R3 |
| 15690 | return 32; |
| 15691 | case 2: |
| 15692 | // op: I2 |
| 15693 | return 16; |
| 15694 | } |
| 15695 | break; |
| 15696 | } |
| 15697 | case SystemZ::InsnRIEe: { |
| 15698 | switch (OpNum) { |
| 15699 | case 0: |
| 15700 | // op: enc |
| 15701 | return 0; |
| 15702 | case 1: |
| 15703 | // op: R1 |
| 15704 | return 36; |
| 15705 | case 3: |
| 15706 | // op: R3 |
| 15707 | return 32; |
| 15708 | case 2: |
| 15709 | // op: RI2 |
| 15710 | return 16; |
| 15711 | } |
| 15712 | break; |
| 15713 | } |
| 15714 | case SystemZ::InsnRSYb: { |
| 15715 | switch (OpNum) { |
| 15716 | case 0: |
| 15717 | // op: enc |
| 15718 | return 0; |
| 15719 | case 1: |
| 15720 | // op: R1 |
| 15721 | return 36; |
| 15722 | case 4: |
| 15723 | // op: M3 |
| 15724 | return 32; |
| 15725 | case 2: |
| 15726 | // op: B2 |
| 15727 | return 28; |
| 15728 | case 3: |
| 15729 | // op: D2 |
| 15730 | return 8; |
| 15731 | } |
| 15732 | break; |
| 15733 | } |
| 15734 | case SystemZ::InsnRSYa: { |
| 15735 | switch (OpNum) { |
| 15736 | case 0: |
| 15737 | // op: enc |
| 15738 | return 0; |
| 15739 | case 1: |
| 15740 | // op: R1 |
| 15741 | return 36; |
| 15742 | case 4: |
| 15743 | // op: R3 |
| 15744 | return 32; |
| 15745 | case 2: |
| 15746 | // op: B2 |
| 15747 | return 28; |
| 15748 | case 3: |
| 15749 | // op: D2 |
| 15750 | return 8; |
| 15751 | } |
| 15752 | break; |
| 15753 | } |
| 15754 | case SystemZ::InsnRXE: { |
| 15755 | switch (OpNum) { |
| 15756 | case 0: |
| 15757 | // op: enc |
| 15758 | return 0; |
| 15759 | case 1: |
| 15760 | // op: R1 |
| 15761 | return 36; |
| 15762 | case 4: |
| 15763 | // op: X2 |
| 15764 | return 32; |
| 15765 | case 2: |
| 15766 | // op: B2 |
| 15767 | return 28; |
| 15768 | case 3: |
| 15769 | // op: D2 |
| 15770 | return 16; |
| 15771 | case 5: |
| 15772 | // op: M3 |
| 15773 | return 12; |
| 15774 | } |
| 15775 | break; |
| 15776 | } |
| 15777 | case SystemZ::InsnRXY: |
| 15778 | case SystemZ::InsnRXYa: |
| 15779 | case SystemZ::InsnRXYc: { |
| 15780 | switch (OpNum) { |
| 15781 | case 0: |
| 15782 | // op: enc |
| 15783 | return 0; |
| 15784 | case 1: |
| 15785 | // op: R1 |
| 15786 | return 36; |
| 15787 | case 4: |
| 15788 | // op: X2 |
| 15789 | return 32; |
| 15790 | case 2: |
| 15791 | // op: B2 |
| 15792 | return 28; |
| 15793 | case 3: |
| 15794 | // op: D2 |
| 15795 | return 8; |
| 15796 | } |
| 15797 | break; |
| 15798 | } |
| 15799 | case SystemZ::InsnVRRg: { |
| 15800 | switch (OpNum) { |
| 15801 | case 0: |
| 15802 | // op: enc |
| 15803 | return 0; |
| 15804 | case 1: |
| 15805 | // op: V1 |
| 15806 | return 10; |
| 15807 | case 2: |
| 15808 | // op: I2 |
| 15809 | return 12; |
| 15810 | } |
| 15811 | break; |
| 15812 | } |
| 15813 | case SystemZ::InsnVRIl: { |
| 15814 | switch (OpNum) { |
| 15815 | case 0: |
| 15816 | // op: enc |
| 15817 | return 0; |
| 15818 | case 1: |
| 15819 | // op: V1 |
| 15820 | return 10; |
| 15821 | case 2: |
| 15822 | // op: V2 |
| 15823 | return 9; |
| 15824 | case 3: |
| 15825 | // op: I3 |
| 15826 | return 12; |
| 15827 | } |
| 15828 | break; |
| 15829 | } |
| 15830 | case SystemZ::InsnVRRh: { |
| 15831 | switch (OpNum) { |
| 15832 | case 0: |
| 15833 | // op: enc |
| 15834 | return 0; |
| 15835 | case 1: |
| 15836 | // op: V1 |
| 15837 | return 10; |
| 15838 | case 2: |
| 15839 | // op: V2 |
| 15840 | return 9; |
| 15841 | case 3: |
| 15842 | // op: M3 |
| 15843 | return 20; |
| 15844 | } |
| 15845 | break; |
| 15846 | } |
| 15847 | case SystemZ::InsnVRSb: { |
| 15848 | switch (OpNum) { |
| 15849 | case 0: |
| 15850 | // op: enc |
| 15851 | return 0; |
| 15852 | case 1: |
| 15853 | // op: V1 |
| 15854 | return 11; |
| 15855 | case 2: |
| 15856 | // op: B2 |
| 15857 | return 28; |
| 15858 | case 3: |
| 15859 | // op: D2 |
| 15860 | return 16; |
| 15861 | case 4: |
| 15862 | // op: R3 |
| 15863 | return 32; |
| 15864 | case 5: |
| 15865 | // op: M4 |
| 15866 | return 12; |
| 15867 | } |
| 15868 | break; |
| 15869 | } |
| 15870 | case SystemZ::InsnVRSa: { |
| 15871 | switch (OpNum) { |
| 15872 | case 0: |
| 15873 | // op: enc |
| 15874 | return 0; |
| 15875 | case 1: |
| 15876 | // op: V1 |
| 15877 | return 11; |
| 15878 | case 2: |
| 15879 | // op: B2 |
| 15880 | return 28; |
| 15881 | case 3: |
| 15882 | // op: D2 |
| 15883 | return 16; |
| 15884 | case 4: |
| 15885 | // op: V3 |
| 15886 | return 10; |
| 15887 | case 5: |
| 15888 | // op: M4 |
| 15889 | return 12; |
| 15890 | } |
| 15891 | break; |
| 15892 | } |
| 15893 | case SystemZ::InsnVRIh: { |
| 15894 | switch (OpNum) { |
| 15895 | case 0: |
| 15896 | // op: enc |
| 15897 | return 0; |
| 15898 | case 1: |
| 15899 | // op: V1 |
| 15900 | return 11; |
| 15901 | case 2: |
| 15902 | // op: I2 |
| 15903 | return 16; |
| 15904 | case 3: |
| 15905 | // op: I3 |
| 15906 | return 12; |
| 15907 | } |
| 15908 | break; |
| 15909 | } |
| 15910 | case SystemZ::InsnVRIa: { |
| 15911 | switch (OpNum) { |
| 15912 | case 0: |
| 15913 | // op: enc |
| 15914 | return 0; |
| 15915 | case 1: |
| 15916 | // op: V1 |
| 15917 | return 11; |
| 15918 | case 2: |
| 15919 | // op: I2 |
| 15920 | return 16; |
| 15921 | case 3: |
| 15922 | // op: M3 |
| 15923 | return 12; |
| 15924 | } |
| 15925 | break; |
| 15926 | } |
| 15927 | case SystemZ::InsnVRIb: { |
| 15928 | switch (OpNum) { |
| 15929 | case 0: |
| 15930 | // op: enc |
| 15931 | return 0; |
| 15932 | case 1: |
| 15933 | // op: V1 |
| 15934 | return 11; |
| 15935 | case 2: |
| 15936 | // op: I2 |
| 15937 | return 24; |
| 15938 | case 3: |
| 15939 | // op: I3 |
| 15940 | return 16; |
| 15941 | case 4: |
| 15942 | // op: M4 |
| 15943 | return 12; |
| 15944 | } |
| 15945 | break; |
| 15946 | } |
| 15947 | case SystemZ::InsnVRIi: { |
| 15948 | switch (OpNum) { |
| 15949 | case 0: |
| 15950 | // op: enc |
| 15951 | return 0; |
| 15952 | case 1: |
| 15953 | // op: V1 |
| 15954 | return 11; |
| 15955 | case 2: |
| 15956 | // op: R2 |
| 15957 | return 32; |
| 15958 | case 3: |
| 15959 | // op: I3 |
| 15960 | return 12; |
| 15961 | case 4: |
| 15962 | // op: M4 |
| 15963 | return 20; |
| 15964 | } |
| 15965 | break; |
| 15966 | } |
| 15967 | case SystemZ::InsnVRRf: { |
| 15968 | switch (OpNum) { |
| 15969 | case 0: |
| 15970 | // op: enc |
| 15971 | return 0; |
| 15972 | case 1: |
| 15973 | // op: V1 |
| 15974 | return 11; |
| 15975 | case 2: |
| 15976 | // op: R2 |
| 15977 | return 32; |
| 15978 | case 3: |
| 15979 | // op: R3 |
| 15980 | return 28; |
| 15981 | } |
| 15982 | break; |
| 15983 | } |
| 15984 | case SystemZ::InsnVRIg: { |
| 15985 | switch (OpNum) { |
| 15986 | case 0: |
| 15987 | // op: enc |
| 15988 | return 0; |
| 15989 | case 1: |
| 15990 | // op: V1 |
| 15991 | return 11; |
| 15992 | case 2: |
| 15993 | // op: V2 |
| 15994 | return 10; |
| 15995 | case 3: |
| 15996 | // op: I3 |
| 15997 | return 12; |
| 15998 | case 4: |
| 15999 | // op: I4 |
| 16000 | return 24; |
| 16001 | case 5: |
| 16002 | // op: M5 |
| 16003 | return 20; |
| 16004 | } |
| 16005 | break; |
| 16006 | } |
| 16007 | case SystemZ::InsnVRIj: { |
| 16008 | switch (OpNum) { |
| 16009 | case 0: |
| 16010 | // op: enc |
| 16011 | return 0; |
| 16012 | case 1: |
| 16013 | // op: V1 |
| 16014 | return 11; |
| 16015 | case 2: |
| 16016 | // op: V2 |
| 16017 | return 10; |
| 16018 | case 3: |
| 16019 | // op: I3 |
| 16020 | return 12; |
| 16021 | case 4: |
| 16022 | // op: M4 |
| 16023 | return 20; |
| 16024 | } |
| 16025 | break; |
| 16026 | } |
| 16027 | case SystemZ::InsnVRI: |
| 16028 | case SystemZ::InsnVRIe: { |
| 16029 | switch (OpNum) { |
| 16030 | case 0: |
| 16031 | // op: enc |
| 16032 | return 0; |
| 16033 | case 1: |
| 16034 | // op: V1 |
| 16035 | return 11; |
| 16036 | case 2: |
| 16037 | // op: V2 |
| 16038 | return 10; |
| 16039 | case 3: |
| 16040 | // op: I3 |
| 16041 | return 20; |
| 16042 | case 4: |
| 16043 | // op: M4 |
| 16044 | return 12; |
| 16045 | case 5: |
| 16046 | // op: M5 |
| 16047 | return 16; |
| 16048 | } |
| 16049 | break; |
| 16050 | } |
| 16051 | case SystemZ::InsnVRRa: { |
| 16052 | switch (OpNum) { |
| 16053 | case 0: |
| 16054 | // op: enc |
| 16055 | return 0; |
| 16056 | case 1: |
| 16057 | // op: V1 |
| 16058 | return 11; |
| 16059 | case 2: |
| 16060 | // op: V2 |
| 16061 | return 10; |
| 16062 | case 3: |
| 16063 | // op: M3 |
| 16064 | return 12; |
| 16065 | case 4: |
| 16066 | // op: M4 |
| 16067 | return 16; |
| 16068 | case 5: |
| 16069 | // op: M5 |
| 16070 | return 20; |
| 16071 | } |
| 16072 | break; |
| 16073 | } |
| 16074 | case SystemZ::InsnVRRk: { |
| 16075 | switch (OpNum) { |
| 16076 | case 0: |
| 16077 | // op: enc |
| 16078 | return 0; |
| 16079 | case 1: |
| 16080 | // op: V1 |
| 16081 | return 11; |
| 16082 | case 2: |
| 16083 | // op: V2 |
| 16084 | return 10; |
| 16085 | case 3: |
| 16086 | // op: M3 |
| 16087 | return 20; |
| 16088 | } |
| 16089 | break; |
| 16090 | } |
| 16091 | case SystemZ::InsnVRIf: { |
| 16092 | switch (OpNum) { |
| 16093 | case 0: |
| 16094 | // op: enc |
| 16095 | return 0; |
| 16096 | case 1: |
| 16097 | // op: V1 |
| 16098 | return 11; |
| 16099 | case 2: |
| 16100 | // op: V2 |
| 16101 | return 10; |
| 16102 | case 3: |
| 16103 | // op: V3 |
| 16104 | return 9; |
| 16105 | case 4: |
| 16106 | // op: I4 |
| 16107 | return 12; |
| 16108 | case 5: |
| 16109 | // op: M5 |
| 16110 | return 20; |
| 16111 | } |
| 16112 | break; |
| 16113 | } |
| 16114 | case SystemZ::InsnVRId: { |
| 16115 | switch (OpNum) { |
| 16116 | case 0: |
| 16117 | // op: enc |
| 16118 | return 0; |
| 16119 | case 1: |
| 16120 | // op: V1 |
| 16121 | return 11; |
| 16122 | case 2: |
| 16123 | // op: V2 |
| 16124 | return 10; |
| 16125 | case 3: |
| 16126 | // op: V3 |
| 16127 | return 9; |
| 16128 | case 4: |
| 16129 | // op: I4 |
| 16130 | return 16; |
| 16131 | case 5: |
| 16132 | // op: M5 |
| 16133 | return 12; |
| 16134 | } |
| 16135 | break; |
| 16136 | } |
| 16137 | case SystemZ::InsnVRR: |
| 16138 | case SystemZ::InsnVRRc: { |
| 16139 | switch (OpNum) { |
| 16140 | case 0: |
| 16141 | // op: enc |
| 16142 | return 0; |
| 16143 | case 1: |
| 16144 | // op: V1 |
| 16145 | return 11; |
| 16146 | case 2: |
| 16147 | // op: V2 |
| 16148 | return 10; |
| 16149 | case 3: |
| 16150 | // op: V3 |
| 16151 | return 9; |
| 16152 | case 4: |
| 16153 | // op: M4 |
| 16154 | return 12; |
| 16155 | case 5: |
| 16156 | // op: M5 |
| 16157 | return 16; |
| 16158 | case 6: |
| 16159 | // op: M6 |
| 16160 | return 20; |
| 16161 | } |
| 16162 | break; |
| 16163 | } |
| 16164 | case SystemZ::InsnVRRb: { |
| 16165 | switch (OpNum) { |
| 16166 | case 0: |
| 16167 | // op: enc |
| 16168 | return 0; |
| 16169 | case 1: |
| 16170 | // op: V1 |
| 16171 | return 11; |
| 16172 | case 2: |
| 16173 | // op: V2 |
| 16174 | return 10; |
| 16175 | case 3: |
| 16176 | // op: V3 |
| 16177 | return 9; |
| 16178 | case 4: |
| 16179 | // op: M4 |
| 16180 | return 12; |
| 16181 | case 5: |
| 16182 | // op: M5 |
| 16183 | return 20; |
| 16184 | } |
| 16185 | break; |
| 16186 | } |
| 16187 | case SystemZ::InsnVRRj: { |
| 16188 | switch (OpNum) { |
| 16189 | case 0: |
| 16190 | // op: enc |
| 16191 | return 0; |
| 16192 | case 1: |
| 16193 | // op: V1 |
| 16194 | return 11; |
| 16195 | case 2: |
| 16196 | // op: V2 |
| 16197 | return 10; |
| 16198 | case 3: |
| 16199 | // op: V3 |
| 16200 | return 9; |
| 16201 | case 4: |
| 16202 | // op: M4 |
| 16203 | return 20; |
| 16204 | } |
| 16205 | break; |
| 16206 | } |
| 16207 | case SystemZ::InsnVRIk: { |
| 16208 | switch (OpNum) { |
| 16209 | case 0: |
| 16210 | // op: enc |
| 16211 | return 0; |
| 16212 | case 1: |
| 16213 | // op: V1 |
| 16214 | return 11; |
| 16215 | case 2: |
| 16216 | // op: V2 |
| 16217 | return 10; |
| 16218 | case 3: |
| 16219 | // op: V3 |
| 16220 | return 9; |
| 16221 | case 4: |
| 16222 | // op: V4 |
| 16223 | return 8; |
| 16224 | case 5: |
| 16225 | // op: I5 |
| 16226 | return 16; |
| 16227 | } |
| 16228 | break; |
| 16229 | } |
| 16230 | case SystemZ::InsnVRRe: { |
| 16231 | switch (OpNum) { |
| 16232 | case 0: |
| 16233 | // op: enc |
| 16234 | return 0; |
| 16235 | case 1: |
| 16236 | // op: V1 |
| 16237 | return 11; |
| 16238 | case 2: |
| 16239 | // op: V2 |
| 16240 | return 10; |
| 16241 | case 3: |
| 16242 | // op: V3 |
| 16243 | return 9; |
| 16244 | case 4: |
| 16245 | // op: V4 |
| 16246 | return 8; |
| 16247 | case 5: |
| 16248 | // op: M5 |
| 16249 | return 16; |
| 16250 | case 6: |
| 16251 | // op: M6 |
| 16252 | return 24; |
| 16253 | } |
| 16254 | break; |
| 16255 | } |
| 16256 | case SystemZ::InsnVRRd: { |
| 16257 | switch (OpNum) { |
| 16258 | case 0: |
| 16259 | // op: enc |
| 16260 | return 0; |
| 16261 | case 1: |
| 16262 | // op: V1 |
| 16263 | return 11; |
| 16264 | case 2: |
| 16265 | // op: V2 |
| 16266 | return 10; |
| 16267 | case 3: |
| 16268 | // op: V3 |
| 16269 | return 9; |
| 16270 | case 4: |
| 16271 | // op: V4 |
| 16272 | return 8; |
| 16273 | case 5: |
| 16274 | // op: M5 |
| 16275 | return 24; |
| 16276 | case 6: |
| 16277 | // op: M6 |
| 16278 | return 20; |
| 16279 | } |
| 16280 | break; |
| 16281 | } |
| 16282 | case SystemZ::InsnVRIc: { |
| 16283 | switch (OpNum) { |
| 16284 | case 0: |
| 16285 | // op: enc |
| 16286 | return 0; |
| 16287 | case 1: |
| 16288 | // op: V1 |
| 16289 | return 11; |
| 16290 | case 3: |
| 16291 | // op: V3 |
| 16292 | return 10; |
| 16293 | case 2: |
| 16294 | // op: I2 |
| 16295 | return 16; |
| 16296 | case 4: |
| 16297 | // op: M4 |
| 16298 | return 12; |
| 16299 | } |
| 16300 | break; |
| 16301 | } |
| 16302 | case SystemZ::InsnVRV: { |
| 16303 | switch (OpNum) { |
| 16304 | case 0: |
| 16305 | // op: enc |
| 16306 | return 0; |
| 16307 | case 1: |
| 16308 | // op: V1 |
| 16309 | return 11; |
| 16310 | case 4: |
| 16311 | // op: V2 |
| 16312 | return 10; |
| 16313 | case 2: |
| 16314 | // op: B2 |
| 16315 | return 28; |
| 16316 | case 3: |
| 16317 | // op: D2 |
| 16318 | return 16; |
| 16319 | case 5: |
| 16320 | // op: M3 |
| 16321 | return 12; |
| 16322 | } |
| 16323 | break; |
| 16324 | } |
| 16325 | case SystemZ::InsnVRX: { |
| 16326 | switch (OpNum) { |
| 16327 | case 0: |
| 16328 | // op: enc |
| 16329 | return 0; |
| 16330 | case 1: |
| 16331 | // op: V1 |
| 16332 | return 11; |
| 16333 | case 4: |
| 16334 | // op: X2 |
| 16335 | return 32; |
| 16336 | case 2: |
| 16337 | // op: B2 |
| 16338 | return 28; |
| 16339 | case 3: |
| 16340 | // op: D2 |
| 16341 | return 16; |
| 16342 | case 5: |
| 16343 | // op: M3 |
| 16344 | return 12; |
| 16345 | } |
| 16346 | break; |
| 16347 | } |
| 16348 | case SystemZ::InsnVSI: { |
| 16349 | switch (OpNum) { |
| 16350 | case 0: |
| 16351 | // op: enc |
| 16352 | return 0; |
| 16353 | case 1: |
| 16354 | // op: V1 |
| 16355 | return 8; |
| 16356 | case 2: |
| 16357 | // op: B2 |
| 16358 | return 28; |
| 16359 | case 3: |
| 16360 | // op: D2 |
| 16361 | return 16; |
| 16362 | case 4: |
| 16363 | // op: I3 |
| 16364 | return 32; |
| 16365 | } |
| 16366 | break; |
| 16367 | } |
| 16368 | case SystemZ::InsnVRSd: { |
| 16369 | switch (OpNum) { |
| 16370 | case 0: |
| 16371 | // op: enc |
| 16372 | return 0; |
| 16373 | case 1: |
| 16374 | // op: V1 |
| 16375 | return 8; |
| 16376 | case 2: |
| 16377 | // op: B2 |
| 16378 | return 28; |
| 16379 | case 3: |
| 16380 | // op: D2 |
| 16381 | return 16; |
| 16382 | case 4: |
| 16383 | // op: R3 |
| 16384 | return 32; |
| 16385 | } |
| 16386 | break; |
| 16387 | } |
| 16388 | case SystemZ::InsnE: { |
| 16389 | switch (OpNum) { |
| 16390 | case 0: |
| 16391 | // op: enc |
| 16392 | return 0; |
| 16393 | } |
| 16394 | break; |
| 16395 | } |
| 16396 | case SystemZ::InsnS: { |
| 16397 | switch (OpNum) { |
| 16398 | case 0: |
| 16399 | // op: enc |
| 16400 | return 16; |
| 16401 | case 1: |
| 16402 | // op: B2 |
| 16403 | return 12; |
| 16404 | case 2: |
| 16405 | // op: D2 |
| 16406 | return 0; |
| 16407 | } |
| 16408 | break; |
| 16409 | } |
| 16410 | case SystemZ::InsnIE: { |
| 16411 | switch (OpNum) { |
| 16412 | case 0: |
| 16413 | // op: enc |
| 16414 | return 16; |
| 16415 | case 1: |
| 16416 | // op: I1 |
| 16417 | return 4; |
| 16418 | case 2: |
| 16419 | // op: I2 |
| 16420 | return 0; |
| 16421 | } |
| 16422 | break; |
| 16423 | } |
| 16424 | case SystemZ::InsnRIc: { |
| 16425 | switch (OpNum) { |
| 16426 | case 0: |
| 16427 | // op: enc |
| 16428 | return 16; |
| 16429 | case 1: |
| 16430 | // op: M1 |
| 16431 | return 20; |
| 16432 | case 2: |
| 16433 | // op: RI2 |
| 16434 | return 0; |
| 16435 | } |
| 16436 | break; |
| 16437 | } |
| 16438 | case SystemZ::InsnRRD: { |
| 16439 | switch (OpNum) { |
| 16440 | case 0: |
| 16441 | // op: enc |
| 16442 | return 16; |
| 16443 | case 1: |
| 16444 | // op: R1 |
| 16445 | return 12; |
| 16446 | case 3: |
| 16447 | // op: R3 |
| 16448 | return 4; |
| 16449 | case 2: |
| 16450 | // op: R2 |
| 16451 | return 0; |
| 16452 | } |
| 16453 | break; |
| 16454 | } |
| 16455 | case SystemZ::InsnRI: |
| 16456 | case SystemZ::InsnRIa: { |
| 16457 | switch (OpNum) { |
| 16458 | case 0: |
| 16459 | // op: enc |
| 16460 | return 16; |
| 16461 | case 1: |
| 16462 | // op: R1 |
| 16463 | return 20; |
| 16464 | case 2: |
| 16465 | // op: I2 |
| 16466 | return 0; |
| 16467 | } |
| 16468 | break; |
| 16469 | } |
| 16470 | case SystemZ::InsnRIb: { |
| 16471 | switch (OpNum) { |
| 16472 | case 0: |
| 16473 | // op: enc |
| 16474 | return 16; |
| 16475 | case 1: |
| 16476 | // op: R1 |
| 16477 | return 20; |
| 16478 | case 2: |
| 16479 | // op: RI2 |
| 16480 | return 0; |
| 16481 | } |
| 16482 | break; |
| 16483 | } |
| 16484 | case SystemZ::InsnRRFc: { |
| 16485 | switch (OpNum) { |
| 16486 | case 0: |
| 16487 | // op: enc |
| 16488 | return 16; |
| 16489 | case 1: |
| 16490 | // op: R1 |
| 16491 | return 4; |
| 16492 | case 2: |
| 16493 | // op: R2 |
| 16494 | return 0; |
| 16495 | case 3: |
| 16496 | // op: M3 |
| 16497 | return 12; |
| 16498 | } |
| 16499 | break; |
| 16500 | } |
| 16501 | case SystemZ::InsnRRFd: { |
| 16502 | switch (OpNum) { |
| 16503 | case 0: |
| 16504 | // op: enc |
| 16505 | return 16; |
| 16506 | case 1: |
| 16507 | // op: R1 |
| 16508 | return 4; |
| 16509 | case 2: |
| 16510 | // op: R2 |
| 16511 | return 0; |
| 16512 | case 3: |
| 16513 | // op: M4 |
| 16514 | return 8; |
| 16515 | } |
| 16516 | break; |
| 16517 | } |
| 16518 | case SystemZ::InsnRRF: |
| 16519 | case SystemZ::InsnRRFa: { |
| 16520 | switch (OpNum) { |
| 16521 | case 0: |
| 16522 | // op: enc |
| 16523 | return 16; |
| 16524 | case 1: |
| 16525 | // op: R1 |
| 16526 | return 4; |
| 16527 | case 2: |
| 16528 | // op: R2 |
| 16529 | return 0; |
| 16530 | case 3: |
| 16531 | // op: R3 |
| 16532 | return 12; |
| 16533 | case 4: |
| 16534 | // op: M4 |
| 16535 | return 8; |
| 16536 | } |
| 16537 | break; |
| 16538 | } |
| 16539 | case SystemZ::InsnRRE: { |
| 16540 | switch (OpNum) { |
| 16541 | case 0: |
| 16542 | // op: enc |
| 16543 | return 16; |
| 16544 | case 1: |
| 16545 | // op: R1 |
| 16546 | return 4; |
| 16547 | case 2: |
| 16548 | // op: R2 |
| 16549 | return 0; |
| 16550 | } |
| 16551 | break; |
| 16552 | } |
| 16553 | case SystemZ::InsnRRFe: { |
| 16554 | switch (OpNum) { |
| 16555 | case 0: |
| 16556 | // op: enc |
| 16557 | return 16; |
| 16558 | case 1: |
| 16559 | // op: R1 |
| 16560 | return 4; |
| 16561 | case 3: |
| 16562 | // op: R2 |
| 16563 | return 0; |
| 16564 | case 2: |
| 16565 | // op: M3 |
| 16566 | return 12; |
| 16567 | case 4: |
| 16568 | // op: M4 |
| 16569 | return 8; |
| 16570 | } |
| 16571 | break; |
| 16572 | } |
| 16573 | case SystemZ::InsnRRFb: { |
| 16574 | switch (OpNum) { |
| 16575 | case 0: |
| 16576 | // op: enc |
| 16577 | return 16; |
| 16578 | case 1: |
| 16579 | // op: R1 |
| 16580 | return 4; |
| 16581 | case 3: |
| 16582 | // op: R2 |
| 16583 | return 0; |
| 16584 | case 2: |
| 16585 | // op: R3 |
| 16586 | return 12; |
| 16587 | case 4: |
| 16588 | // op: M4 |
| 16589 | return 8; |
| 16590 | } |
| 16591 | break; |
| 16592 | } |
| 16593 | case SystemZ::InsnSI: { |
| 16594 | switch (OpNum) { |
| 16595 | case 0: |
| 16596 | // op: enc |
| 16597 | return 24; |
| 16598 | case 1: |
| 16599 | // op: B1 |
| 16600 | return 12; |
| 16601 | case 2: |
| 16602 | // op: D1 |
| 16603 | return 0; |
| 16604 | case 3: |
| 16605 | // op: I2 |
| 16606 | return 16; |
| 16607 | } |
| 16608 | break; |
| 16609 | } |
| 16610 | case SystemZ::InsnRXb: { |
| 16611 | switch (OpNum) { |
| 16612 | case 0: |
| 16613 | // op: enc |
| 16614 | return 24; |
| 16615 | case 1: |
| 16616 | // op: M1 |
| 16617 | return 20; |
| 16618 | case 4: |
| 16619 | // op: X2 |
| 16620 | return 16; |
| 16621 | case 2: |
| 16622 | // op: B2 |
| 16623 | return 12; |
| 16624 | case 3: |
| 16625 | // op: D2 |
| 16626 | return 0; |
| 16627 | } |
| 16628 | break; |
| 16629 | } |
| 16630 | case SystemZ::InsnRS: { |
| 16631 | switch (OpNum) { |
| 16632 | case 0: |
| 16633 | // op: enc |
| 16634 | return 24; |
| 16635 | case 1: |
| 16636 | // op: R1 |
| 16637 | return 20; |
| 16638 | case 2: |
| 16639 | // op: R3 |
| 16640 | return 16; |
| 16641 | case 3: |
| 16642 | // op: B2 |
| 16643 | return 12; |
| 16644 | case 4: |
| 16645 | // op: D2 |
| 16646 | return 0; |
| 16647 | } |
| 16648 | break; |
| 16649 | } |
| 16650 | case SystemZ::InsnRSI: { |
| 16651 | switch (OpNum) { |
| 16652 | case 0: |
| 16653 | // op: enc |
| 16654 | return 24; |
| 16655 | case 1: |
| 16656 | // op: R1 |
| 16657 | return 20; |
| 16658 | case 2: |
| 16659 | // op: R3 |
| 16660 | return 16; |
| 16661 | case 3: |
| 16662 | // op: RI2 |
| 16663 | return 0; |
| 16664 | } |
| 16665 | break; |
| 16666 | } |
| 16667 | case SystemZ::InsnRSb: { |
| 16668 | switch (OpNum) { |
| 16669 | case 0: |
| 16670 | // op: enc |
| 16671 | return 24; |
| 16672 | case 1: |
| 16673 | // op: R1 |
| 16674 | return 20; |
| 16675 | case 4: |
| 16676 | // op: M3 |
| 16677 | return 16; |
| 16678 | case 2: |
| 16679 | // op: B2 |
| 16680 | return 12; |
| 16681 | case 3: |
| 16682 | // op: D2 |
| 16683 | return 0; |
| 16684 | } |
| 16685 | break; |
| 16686 | } |
| 16687 | case SystemZ::InsnRSa: { |
| 16688 | switch (OpNum) { |
| 16689 | case 0: |
| 16690 | // op: enc |
| 16691 | return 24; |
| 16692 | case 1: |
| 16693 | // op: R1 |
| 16694 | return 20; |
| 16695 | case 4: |
| 16696 | // op: R3 |
| 16697 | return 16; |
| 16698 | case 2: |
| 16699 | // op: B2 |
| 16700 | return 12; |
| 16701 | case 3: |
| 16702 | // op: D2 |
| 16703 | return 0; |
| 16704 | } |
| 16705 | break; |
| 16706 | } |
| 16707 | case SystemZ::InsnRX: |
| 16708 | case SystemZ::InsnRXa: { |
| 16709 | switch (OpNum) { |
| 16710 | case 0: |
| 16711 | // op: enc |
| 16712 | return 24; |
| 16713 | case 1: |
| 16714 | // op: R1 |
| 16715 | return 20; |
| 16716 | case 4: |
| 16717 | // op: X2 |
| 16718 | return 16; |
| 16719 | case 2: |
| 16720 | // op: B2 |
| 16721 | return 12; |
| 16722 | case 3: |
| 16723 | // op: D2 |
| 16724 | return 0; |
| 16725 | } |
| 16726 | break; |
| 16727 | } |
| 16728 | case SystemZ::InsnSSF: { |
| 16729 | switch (OpNum) { |
| 16730 | case 0: |
| 16731 | // op: enc |
| 16732 | return 32; |
| 16733 | case 1: |
| 16734 | // op: B1 |
| 16735 | return 28; |
| 16736 | case 2: |
| 16737 | // op: D1 |
| 16738 | return 16; |
| 16739 | case 3: |
| 16740 | // op: B2 |
| 16741 | return 12; |
| 16742 | case 4: |
| 16743 | // op: D2 |
| 16744 | return 0; |
| 16745 | case 5: |
| 16746 | // op: R3 |
| 16747 | return 36; |
| 16748 | } |
| 16749 | break; |
| 16750 | } |
| 16751 | case SystemZ::InsnSSE: { |
| 16752 | switch (OpNum) { |
| 16753 | case 0: |
| 16754 | // op: enc |
| 16755 | return 32; |
| 16756 | case 1: |
| 16757 | // op: B1 |
| 16758 | return 28; |
| 16759 | case 2: |
| 16760 | // op: D1 |
| 16761 | return 16; |
| 16762 | case 3: |
| 16763 | // op: B2 |
| 16764 | return 12; |
| 16765 | case 4: |
| 16766 | // op: D2 |
| 16767 | return 0; |
| 16768 | } |
| 16769 | break; |
| 16770 | } |
| 16771 | case SystemZ::InsnSIL: { |
| 16772 | switch (OpNum) { |
| 16773 | case 0: |
| 16774 | // op: enc |
| 16775 | return 32; |
| 16776 | case 1: |
| 16777 | // op: B1 |
| 16778 | return 28; |
| 16779 | case 2: |
| 16780 | // op: D1 |
| 16781 | return 16; |
| 16782 | case 3: |
| 16783 | // op: I2 |
| 16784 | return 0; |
| 16785 | } |
| 16786 | break; |
| 16787 | } |
| 16788 | case SystemZ::InsnRILc: { |
| 16789 | switch (OpNum) { |
| 16790 | case 0: |
| 16791 | // op: enc |
| 16792 | return 32; |
| 16793 | case 1: |
| 16794 | // op: M1 |
| 16795 | return 36; |
| 16796 | case 2: |
| 16797 | // op: RI2 |
| 16798 | return 0; |
| 16799 | } |
| 16800 | break; |
| 16801 | } |
| 16802 | case SystemZ::InsnRIL: |
| 16803 | case SystemZ::InsnRILU: |
| 16804 | case SystemZ::InsnRILa: { |
| 16805 | switch (OpNum) { |
| 16806 | case 0: |
| 16807 | // op: enc |
| 16808 | return 32; |
| 16809 | case 1: |
| 16810 | // op: R1 |
| 16811 | return 36; |
| 16812 | case 2: |
| 16813 | // op: I2 |
| 16814 | return 0; |
| 16815 | } |
| 16816 | break; |
| 16817 | } |
| 16818 | case SystemZ::InsnRILb: { |
| 16819 | switch (OpNum) { |
| 16820 | case 0: |
| 16821 | // op: enc |
| 16822 | return 32; |
| 16823 | case 1: |
| 16824 | // op: R1 |
| 16825 | return 36; |
| 16826 | case 2: |
| 16827 | // op: RI2 |
| 16828 | return 0; |
| 16829 | } |
| 16830 | break; |
| 16831 | } |
| 16832 | case SystemZ::InsnSSf: { |
| 16833 | switch (OpNum) { |
| 16834 | case 0: |
| 16835 | // op: enc |
| 16836 | return 40; |
| 16837 | case 1: |
| 16838 | // op: B1 |
| 16839 | return 28; |
| 16840 | case 2: |
| 16841 | // op: D1 |
| 16842 | return 16; |
| 16843 | case 3: |
| 16844 | // op: B2 |
| 16845 | return 12; |
| 16846 | case 4: |
| 16847 | // op: D2 |
| 16848 | return 0; |
| 16849 | case 5: |
| 16850 | // op: L2 |
| 16851 | return 32; |
| 16852 | } |
| 16853 | break; |
| 16854 | } |
| 16855 | case SystemZ::InsnSSa: { |
| 16856 | switch (OpNum) { |
| 16857 | case 0: |
| 16858 | // op: enc |
| 16859 | return 40; |
| 16860 | case 1: |
| 16861 | // op: B1 |
| 16862 | return 28; |
| 16863 | case 2: |
| 16864 | // op: D1 |
| 16865 | return 16; |
| 16866 | case 3: |
| 16867 | // op: L1 |
| 16868 | return 32; |
| 16869 | case 4: |
| 16870 | // op: B2 |
| 16871 | return 12; |
| 16872 | case 5: |
| 16873 | // op: D2 |
| 16874 | return 0; |
| 16875 | } |
| 16876 | break; |
| 16877 | } |
| 16878 | case SystemZ::InsnSSc: { |
| 16879 | switch (OpNum) { |
| 16880 | case 0: |
| 16881 | // op: enc |
| 16882 | return 40; |
| 16883 | case 1: |
| 16884 | // op: B1 |
| 16885 | return 28; |
| 16886 | case 2: |
| 16887 | // op: D1 |
| 16888 | return 16; |
| 16889 | case 3: |
| 16890 | // op: L1 |
| 16891 | return 36; |
| 16892 | case 4: |
| 16893 | // op: B2 |
| 16894 | return 12; |
| 16895 | case 5: |
| 16896 | // op: D2 |
| 16897 | return 0; |
| 16898 | case 6: |
| 16899 | // op: I3 |
| 16900 | return 32; |
| 16901 | } |
| 16902 | break; |
| 16903 | } |
| 16904 | case SystemZ::InsnSSb: { |
| 16905 | switch (OpNum) { |
| 16906 | case 0: |
| 16907 | // op: enc |
| 16908 | return 40; |
| 16909 | case 1: |
| 16910 | // op: B1 |
| 16911 | return 28; |
| 16912 | case 2: |
| 16913 | // op: D1 |
| 16914 | return 16; |
| 16915 | case 3: |
| 16916 | // op: L1 |
| 16917 | return 36; |
| 16918 | case 4: |
| 16919 | // op: B2 |
| 16920 | return 12; |
| 16921 | case 5: |
| 16922 | // op: D2 |
| 16923 | return 0; |
| 16924 | case 6: |
| 16925 | // op: L2 |
| 16926 | return 32; |
| 16927 | } |
| 16928 | break; |
| 16929 | } |
| 16930 | case SystemZ::InsnSMI: { |
| 16931 | switch (OpNum) { |
| 16932 | case 0: |
| 16933 | // op: enc |
| 16934 | return 40; |
| 16935 | case 1: |
| 16936 | // op: M1 |
| 16937 | return 36; |
| 16938 | case 2: |
| 16939 | // op: RI2 |
| 16940 | return 0; |
| 16941 | case 3: |
| 16942 | // op: B3 |
| 16943 | return 28; |
| 16944 | case 4: |
| 16945 | // op: D3 |
| 16946 | return 16; |
| 16947 | } |
| 16948 | break; |
| 16949 | } |
| 16950 | case SystemZ::InsnMII: { |
| 16951 | switch (OpNum) { |
| 16952 | case 0: |
| 16953 | // op: enc |
| 16954 | return 40; |
| 16955 | case 1: |
| 16956 | // op: M1 |
| 16957 | return 36; |
| 16958 | case 2: |
| 16959 | // op: RI2 |
| 16960 | return 24; |
| 16961 | case 3: |
| 16962 | // op: RI3 |
| 16963 | return 0; |
| 16964 | } |
| 16965 | break; |
| 16966 | } |
| 16967 | case SystemZ::InsnSSe: { |
| 16968 | switch (OpNum) { |
| 16969 | case 0: |
| 16970 | // op: enc |
| 16971 | return 40; |
| 16972 | case 1: |
| 16973 | // op: R1 |
| 16974 | return 36; |
| 16975 | case 2: |
| 16976 | // op: B2 |
| 16977 | return 28; |
| 16978 | case 3: |
| 16979 | // op: D2 |
| 16980 | return 16; |
| 16981 | case 4: |
| 16982 | // op: R3 |
| 16983 | return 32; |
| 16984 | case 5: |
| 16985 | // op: B4 |
| 16986 | return 12; |
| 16987 | case 6: |
| 16988 | // op: D4 |
| 16989 | return 0; |
| 16990 | } |
| 16991 | break; |
| 16992 | } |
| 16993 | case SystemZ::InsnSS: |
| 16994 | case SystemZ::InsnSSd: { |
| 16995 | switch (OpNum) { |
| 16996 | case 0: |
| 16997 | // op: enc |
| 16998 | return 40; |
| 16999 | case 3: |
| 17000 | // op: R1 |
| 17001 | return 36; |
| 17002 | case 1: |
| 17003 | // op: B1 |
| 17004 | return 28; |
| 17005 | case 2: |
| 17006 | // op: D1 |
| 17007 | return 16; |
| 17008 | case 4: |
| 17009 | // op: B2 |
| 17010 | return 12; |
| 17011 | case 5: |
| 17012 | // op: D2 |
| 17013 | return 0; |
| 17014 | case 6: |
| 17015 | // op: R3 |
| 17016 | return 32; |
| 17017 | } |
| 17018 | break; |
| 17019 | } |
| 17020 | case SystemZ::InsnI: { |
| 17021 | switch (OpNum) { |
| 17022 | case 0: |
| 17023 | // op: enc |
| 17024 | return 8; |
| 17025 | case 1: |
| 17026 | // op: I1 |
| 17027 | return 0; |
| 17028 | } |
| 17029 | break; |
| 17030 | } |
| 17031 | case SystemZ::InsnRR: { |
| 17032 | switch (OpNum) { |
| 17033 | case 0: |
| 17034 | // op: enc |
| 17035 | return 8; |
| 17036 | case 1: |
| 17037 | // op: R1 |
| 17038 | return 4; |
| 17039 | case 2: |
| 17040 | // op: R2 |
| 17041 | return 0; |
| 17042 | } |
| 17043 | break; |
| 17044 | } |
| 17045 | case SystemZ::CAL: |
| 17046 | case SystemZ::CALG: |
| 17047 | case SystemZ::CALGF: |
| 17048 | case SystemZ::LPD: |
| 17049 | case SystemZ::LPDG: { |
| 17050 | switch (OpNum) { |
| 17051 | case 1: |
| 17052 | // op: B1 |
| 17053 | return 28; |
| 17054 | case 2: |
| 17055 | // op: D1 |
| 17056 | return 16; |
| 17057 | case 3: |
| 17058 | // op: B2 |
| 17059 | return 12; |
| 17060 | case 4: |
| 17061 | // op: D2 |
| 17062 | return 0; |
| 17063 | case 0: |
| 17064 | // op: R3 |
| 17065 | return 36; |
| 17066 | } |
| 17067 | break; |
| 17068 | } |
| 17069 | case SystemZ::BRC: { |
| 17070 | switch (OpNum) { |
| 17071 | case 1: |
| 17072 | // op: M1 |
| 17073 | return 20; |
| 17074 | case 2: |
| 17075 | // op: RI2 |
| 17076 | return 0; |
| 17077 | } |
| 17078 | break; |
| 17079 | } |
| 17080 | case SystemZ::BC: { |
| 17081 | switch (OpNum) { |
| 17082 | case 1: |
| 17083 | // op: M1 |
| 17084 | return 20; |
| 17085 | case 4: |
| 17086 | // op: X2 |
| 17087 | return 16; |
| 17088 | case 2: |
| 17089 | // op: B2 |
| 17090 | return 12; |
| 17091 | case 3: |
| 17092 | // op: D2 |
| 17093 | return 0; |
| 17094 | } |
| 17095 | break; |
| 17096 | } |
| 17097 | case SystemZ::BRCL: { |
| 17098 | switch (OpNum) { |
| 17099 | case 1: |
| 17100 | // op: M1 |
| 17101 | return 36; |
| 17102 | case 2: |
| 17103 | // op: RI2 |
| 17104 | return 0; |
| 17105 | } |
| 17106 | break; |
| 17107 | } |
| 17108 | case SystemZ::BIC: { |
| 17109 | switch (OpNum) { |
| 17110 | case 1: |
| 17111 | // op: M1 |
| 17112 | return 36; |
| 17113 | case 4: |
| 17114 | // op: X2 |
| 17115 | return 32; |
| 17116 | case 2: |
| 17117 | // op: B2 |
| 17118 | return 28; |
| 17119 | case 3: |
| 17120 | // op: D2 |
| 17121 | return 8; |
| 17122 | } |
| 17123 | break; |
| 17124 | } |
| 17125 | case SystemZ::TRTE: |
| 17126 | case SystemZ::TRTRE: { |
| 17127 | switch (OpNum) { |
| 17128 | case 1: |
| 17129 | // op: R1 |
| 17130 | return 4; |
| 17131 | case 0: |
| 17132 | // op: R2 |
| 17133 | return 0; |
| 17134 | case 3: |
| 17135 | // op: M3 |
| 17136 | return 12; |
| 17137 | } |
| 17138 | break; |
| 17139 | } |
| 17140 | case SystemZ::KDSA: |
| 17141 | case SystemZ::KIMD: |
| 17142 | case SystemZ::KLMD: |
| 17143 | case SystemZ::KMAC: |
| 17144 | case SystemZ::PFMF: |
| 17145 | case SystemZ::TRTEOpt: |
| 17146 | case SystemZ::TRTREOpt: { |
| 17147 | switch (OpNum) { |
| 17148 | case 1: |
| 17149 | // op: R1 |
| 17150 | return 4; |
| 17151 | case 0: |
| 17152 | // op: R2 |
| 17153 | return 0; |
| 17154 | } |
| 17155 | break; |
| 17156 | } |
| 17157 | case SystemZ::BCR: { |
| 17158 | switch (OpNum) { |
| 17159 | case 1: |
| 17160 | // op: R1 |
| 17161 | return 4; |
| 17162 | case 2: |
| 17163 | // op: R2 |
| 17164 | return 0; |
| 17165 | } |
| 17166 | break; |
| 17167 | } |
| 17168 | case SystemZ::MVCK: |
| 17169 | case SystemZ::MVCP: |
| 17170 | case SystemZ::MVCS: { |
| 17171 | switch (OpNum) { |
| 17172 | case 2: |
| 17173 | // op: R1 |
| 17174 | return 36; |
| 17175 | case 0: |
| 17176 | // op: B1 |
| 17177 | return 28; |
| 17178 | case 1: |
| 17179 | // op: D1 |
| 17180 | return 16; |
| 17181 | case 3: |
| 17182 | // op: B2 |
| 17183 | return 12; |
| 17184 | case 4: |
| 17185 | // op: D2 |
| 17186 | return 0; |
| 17187 | case 5: |
| 17188 | // op: R3 |
| 17189 | return 32; |
| 17190 | } |
| 17191 | break; |
| 17192 | } |
| 17193 | case SystemZ::B: |
| 17194 | case SystemZ::BAsmE: |
| 17195 | case SystemZ::BAsmH: |
| 17196 | case SystemZ::BAsmHE: |
| 17197 | case SystemZ::BAsmL: |
| 17198 | case SystemZ::BAsmLE: |
| 17199 | case SystemZ::BAsmLH: |
| 17200 | case SystemZ::BAsmM: |
| 17201 | case SystemZ::BAsmNE: |
| 17202 | case SystemZ::BAsmNH: |
| 17203 | case SystemZ::BAsmNHE: |
| 17204 | case SystemZ::BAsmNL: |
| 17205 | case SystemZ::BAsmNLE: |
| 17206 | case SystemZ::BAsmNLH: |
| 17207 | case SystemZ::BAsmNM: |
| 17208 | case SystemZ::BAsmNO: |
| 17209 | case SystemZ::BAsmNP: |
| 17210 | case SystemZ::BAsmNZ: |
| 17211 | case SystemZ::BAsmO: |
| 17212 | case SystemZ::BAsmP: |
| 17213 | case SystemZ::BAsmZ: |
| 17214 | case SystemZ::NOP: { |
| 17215 | switch (OpNum) { |
| 17216 | case 2: |
| 17217 | // op: X2 |
| 17218 | return 16; |
| 17219 | case 0: |
| 17220 | // op: B2 |
| 17221 | return 12; |
| 17222 | case 1: |
| 17223 | // op: D2 |
| 17224 | return 0; |
| 17225 | } |
| 17226 | break; |
| 17227 | } |
| 17228 | case SystemZ::BI: |
| 17229 | case SystemZ::BIAsmE: |
| 17230 | case SystemZ::BIAsmH: |
| 17231 | case SystemZ::BIAsmHE: |
| 17232 | case SystemZ::BIAsmL: |
| 17233 | case SystemZ::BIAsmLE: |
| 17234 | case SystemZ::BIAsmLH: |
| 17235 | case SystemZ::BIAsmM: |
| 17236 | case SystemZ::BIAsmNE: |
| 17237 | case SystemZ::BIAsmNH: |
| 17238 | case SystemZ::BIAsmNHE: |
| 17239 | case SystemZ::BIAsmNL: |
| 17240 | case SystemZ::BIAsmNLE: |
| 17241 | case SystemZ::BIAsmNLH: |
| 17242 | case SystemZ::BIAsmNM: |
| 17243 | case SystemZ::BIAsmNO: |
| 17244 | case SystemZ::BIAsmNP: |
| 17245 | case SystemZ::BIAsmNZ: |
| 17246 | case SystemZ::BIAsmO: |
| 17247 | case SystemZ::BIAsmP: |
| 17248 | case SystemZ::BIAsmZ: { |
| 17249 | switch (OpNum) { |
| 17250 | case 2: |
| 17251 | // op: X2 |
| 17252 | return 32; |
| 17253 | case 0: |
| 17254 | // op: B2 |
| 17255 | return 28; |
| 17256 | case 1: |
| 17257 | // op: D2 |
| 17258 | return 8; |
| 17259 | } |
| 17260 | break; |
| 17261 | } |
| 17262 | default: |
| 17263 | reportUnsupportedInst(Inst: MI); |
| 17264 | } |
| 17265 | reportUnsupportedOperand(Inst: MI, OpNum); |
| 17266 | } |
| 17267 | |
| 17268 | #endif // GET_OPERAND_BIT_OFFSET |
| 17269 | |
| 17270 |
Generated while processing llvm_projects/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
Generated on 2026-Oct-10 from project llvm_projects revision b1dd93c6a
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