1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass SystemZMCRegisterClasses[];
13
14namespace SystemZ {
15
16enum : unsigned {
17 NoRegister,
18 CC = 1,
19 FPC = 2,
20 A0 = 3,
21 A1 = 4,
22 A2 = 5,
23 A3 = 6,
24 A4 = 7,
25 A5 = 8,
26 A6 = 9,
27 A7 = 10,
28 A8 = 11,
29 A9 = 12,
30 A10 = 13,
31 A11 = 14,
32 A12 = 15,
33 A13 = 16,
34 A14 = 17,
35 A15 = 18,
36 C0 = 19,
37 C1 = 20,
38 C2 = 21,
39 C3 = 22,
40 C4 = 23,
41 C5 = 24,
42 C6 = 25,
43 C7 = 26,
44 C8 = 27,
45 C9 = 28,
46 C10 = 29,
47 C11 = 30,
48 C12 = 31,
49 C13 = 32,
50 C14 = 33,
51 C15 = 34,
52 V0 = 35,
53 V1 = 36,
54 V2 = 37,
55 V3 = 38,
56 V4 = 39,
57 V5 = 40,
58 V6 = 41,
59 V7 = 42,
60 V8 = 43,
61 V9 = 44,
62 V10 = 45,
63 V11 = 46,
64 V12 = 47,
65 V13 = 48,
66 V14 = 49,
67 V15 = 50,
68 V16 = 51,
69 V17 = 52,
70 V18 = 53,
71 V19 = 54,
72 V20 = 55,
73 V21 = 56,
74 V22 = 57,
75 V23 = 58,
76 V24 = 59,
77 V25 = 60,
78 V26 = 61,
79 V27 = 62,
80 V28 = 63,
81 V29 = 64,
82 V30 = 65,
83 V31 = 66,
84 F0D = 67,
85 F1D = 68,
86 F2D = 69,
87 F3D = 70,
88 F4D = 71,
89 F5D = 72,
90 F6D = 73,
91 F7D = 74,
92 F8D = 75,
93 F9D = 76,
94 F10D = 77,
95 F11D = 78,
96 F12D = 79,
97 F13D = 80,
98 F14D = 81,
99 F15D = 82,
100 F16D = 83,
101 F17D = 84,
102 F18D = 85,
103 F19D = 86,
104 F20D = 87,
105 F21D = 88,
106 F22D = 89,
107 F23D = 90,
108 F24D = 91,
109 F25D = 92,
110 F26D = 93,
111 F27D = 94,
112 F28D = 95,
113 F29D = 96,
114 F30D = 97,
115 F31D = 98,
116 F0H = 99,
117 F1H = 100,
118 F2H = 101,
119 F3H = 102,
120 F4H = 103,
121 F5H = 104,
122 F6H = 105,
123 F7H = 106,
124 F8H = 107,
125 F9H = 108,
126 F10H = 109,
127 F11H = 110,
128 F12H = 111,
129 F13H = 112,
130 F14H = 113,
131 F15H = 114,
132 F16H = 115,
133 F17H = 116,
134 F18H = 117,
135 F19H = 118,
136 F20H = 119,
137 F21H = 120,
138 F22H = 121,
139 F23H = 122,
140 F24H = 123,
141 F25H = 124,
142 F26H = 125,
143 F27H = 126,
144 F28H = 127,
145 F29H = 128,
146 F30H = 129,
147 F31H = 130,
148 F0Q = 131,
149 F1Q = 132,
150 F4Q = 133,
151 F5Q = 134,
152 F8Q = 135,
153 F9Q = 136,
154 F12Q = 137,
155 F13Q = 138,
156 F0S = 139,
157 F1S = 140,
158 F2S = 141,
159 F3S = 142,
160 F4S = 143,
161 F5S = 144,
162 F6S = 145,
163 F7S = 146,
164 F8S = 147,
165 F9S = 148,
166 F10S = 149,
167 F11S = 150,
168 F12S = 151,
169 F13S = 152,
170 F14S = 153,
171 F15S = 154,
172 F16S = 155,
173 F17S = 156,
174 F18S = 157,
175 F19S = 158,
176 F20S = 159,
177 F21S = 160,
178 F22S = 161,
179 F23S = 162,
180 F24S = 163,
181 F25S = 164,
182 F26S = 165,
183 F27S = 166,
184 F28S = 167,
185 F29S = 168,
186 F30S = 169,
187 F31S = 170,
188 R0D = 171,
189 R1D = 172,
190 R2D = 173,
191 R3D = 174,
192 R4D = 175,
193 R5D = 176,
194 R6D = 177,
195 R7D = 178,
196 R8D = 179,
197 R9D = 180,
198 R10D = 181,
199 R11D = 182,
200 R12D = 183,
201 R13D = 184,
202 R14D = 185,
203 R15D = 186,
204 R0H = 187,
205 R1H = 188,
206 R2H = 189,
207 R3H = 190,
208 R4H = 191,
209 R5H = 192,
210 R6H = 193,
211 R7H = 194,
212 R8H = 195,
213 R9H = 196,
214 R10H = 197,
215 R11H = 198,
216 R12H = 199,
217 R13H = 200,
218 R14H = 201,
219 R15H = 202,
220 R0L = 203,
221 R1L = 204,
222 R2L = 205,
223 R3L = 206,
224 R4L = 207,
225 R5L = 208,
226 R6L = 209,
227 R7L = 210,
228 R8L = 211,
229 R9L = 212,
230 R10L = 213,
231 R11L = 214,
232 R12L = 215,
233 R13L = 216,
234 R14L = 217,
235 R15L = 218,
236 R0Q = 219,
237 R2Q = 220,
238 R4Q = 221,
239 R6Q = 222,
240 R8Q = 223,
241 R10Q = 224,
242 R12Q = 225,
243 R14Q = 226,
244 NUM_TARGET_REGS // 227
245};
246
247} // namespace SystemZ
248
249// Register classes
250
251namespace SystemZ {
252
253enum {
254 VR16BitRegClassID = 0,
255 FP16BitRegClassID = 1,
256 GRX32BitRegClassID = 2,
257 VR32BitRegClassID = 3,
258 AR32BitRegClassID = 4,
259 FP32BitRegClassID = 5,
260 GR32BitRegClassID = 6,
261 GRH32BitRegClassID = 7,
262 ADDR32BitRegClassID = 8,
263 CCRRegClassID = 9,
264 FPCRegsRegClassID = 10,
265 AnyRegBitRegClassID = 11,
266 AnyRegBit_with_subreg_h16RegClassID = 12,
267 VR64BitRegClassID = 13,
268 AnyRegBit_with_subreg_h64RegClassID = 14,
269 CR64BitRegClassID = 15,
270 FP64BitRegClassID = 16,
271 GR64BitRegClassID = 17,
272 ADDR64BitRegClassID = 18,
273 VR128BitRegClassID = 19,
274 VF128BitRegClassID = 20,
275 FP128BitRegClassID = 21,
276 GR128BitRegClassID = 22,
277 ADDR128BitRegClassID = 23,
278
279};
280
281} // namespace SystemZ
282
283// Subregister indices
284
285namespace SystemZ {
286
287enum : uint16_t {
288 NoSubRegister,
289 subreg_h16, // 1
290 subreg_h32, // 2
291 subreg_h64, // 3
292 subreg_l32, // 4
293 subreg_l64, // 5
294 subreg_lh32, // 6
295 subreg_ll32, // 7
296 subreg_lh32_then_subreg_h16, // 8
297 NUM_TARGET_SUBREGS
298};
299
300} // namespace SystemZ
301// Register pressure sets enum.
302namespace SystemZ {
303
304enum RegisterPressureSets {
305 FP16Bit = 0,
306 GR32Bit = 1,
307 GRH32Bit = 2,
308 VR16Bit = 3,
309 GRX32Bit = 4,
310};
311
312} // namespace SystemZ
313
314} // namespace llvm
315