1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass SystemZMCRegisterClasses[];
13
14namespace SystemZ {
15enum : unsigned {
16 NoRegister,
17 CC = 1,
18 FPC = 2,
19 A0 = 3,
20 A1 = 4,
21 A2 = 5,
22 A3 = 6,
23 A4 = 7,
24 A5 = 8,
25 A6 = 9,
26 A7 = 10,
27 A8 = 11,
28 A9 = 12,
29 A10 = 13,
30 A11 = 14,
31 A12 = 15,
32 A13 = 16,
33 A14 = 17,
34 A15 = 18,
35 C0 = 19,
36 C1 = 20,
37 C2 = 21,
38 C3 = 22,
39 C4 = 23,
40 C5 = 24,
41 C6 = 25,
42 C7 = 26,
43 C8 = 27,
44 C9 = 28,
45 C10 = 29,
46 C11 = 30,
47 C12 = 31,
48 C13 = 32,
49 C14 = 33,
50 C15 = 34,
51 V0 = 35,
52 V1 = 36,
53 V2 = 37,
54 V3 = 38,
55 V4 = 39,
56 V5 = 40,
57 V6 = 41,
58 V7 = 42,
59 V8 = 43,
60 V9 = 44,
61 V10 = 45,
62 V11 = 46,
63 V12 = 47,
64 V13 = 48,
65 V14 = 49,
66 V15 = 50,
67 V16 = 51,
68 V17 = 52,
69 V18 = 53,
70 V19 = 54,
71 V20 = 55,
72 V21 = 56,
73 V22 = 57,
74 V23 = 58,
75 V24 = 59,
76 V25 = 60,
77 V26 = 61,
78 V27 = 62,
79 V28 = 63,
80 V29 = 64,
81 V30 = 65,
82 V31 = 66,
83 F0D = 67,
84 F1D = 68,
85 F2D = 69,
86 F3D = 70,
87 F4D = 71,
88 F5D = 72,
89 F6D = 73,
90 F7D = 74,
91 F8D = 75,
92 F9D = 76,
93 F10D = 77,
94 F11D = 78,
95 F12D = 79,
96 F13D = 80,
97 F14D = 81,
98 F15D = 82,
99 F16D = 83,
100 F17D = 84,
101 F18D = 85,
102 F19D = 86,
103 F20D = 87,
104 F21D = 88,
105 F22D = 89,
106 F23D = 90,
107 F24D = 91,
108 F25D = 92,
109 F26D = 93,
110 F27D = 94,
111 F28D = 95,
112 F29D = 96,
113 F30D = 97,
114 F31D = 98,
115 F0H = 99,
116 F1H = 100,
117 F2H = 101,
118 F3H = 102,
119 F4H = 103,
120 F5H = 104,
121 F6H = 105,
122 F7H = 106,
123 F8H = 107,
124 F9H = 108,
125 F10H = 109,
126 F11H = 110,
127 F12H = 111,
128 F13H = 112,
129 F14H = 113,
130 F15H = 114,
131 F16H = 115,
132 F17H = 116,
133 F18H = 117,
134 F19H = 118,
135 F20H = 119,
136 F21H = 120,
137 F22H = 121,
138 F23H = 122,
139 F24H = 123,
140 F25H = 124,
141 F26H = 125,
142 F27H = 126,
143 F28H = 127,
144 F29H = 128,
145 F30H = 129,
146 F31H = 130,
147 F0Q = 131,
148 F1Q = 132,
149 F4Q = 133,
150 F5Q = 134,
151 F8Q = 135,
152 F9Q = 136,
153 F12Q = 137,
154 F13Q = 138,
155 F0S = 139,
156 F1S = 140,
157 F2S = 141,
158 F3S = 142,
159 F4S = 143,
160 F5S = 144,
161 F6S = 145,
162 F7S = 146,
163 F8S = 147,
164 F9S = 148,
165 F10S = 149,
166 F11S = 150,
167 F12S = 151,
168 F13S = 152,
169 F14S = 153,
170 F15S = 154,
171 F16S = 155,
172 F17S = 156,
173 F18S = 157,
174 F19S = 158,
175 F20S = 159,
176 F21S = 160,
177 F22S = 161,
178 F23S = 162,
179 F24S = 163,
180 F25S = 164,
181 F26S = 165,
182 F27S = 166,
183 F28S = 167,
184 F29S = 168,
185 F30S = 169,
186 F31S = 170,
187 R0D = 171,
188 R1D = 172,
189 R2D = 173,
190 R3D = 174,
191 R4D = 175,
192 R5D = 176,
193 R6D = 177,
194 R7D = 178,
195 R8D = 179,
196 R9D = 180,
197 R10D = 181,
198 R11D = 182,
199 R12D = 183,
200 R13D = 184,
201 R14D = 185,
202 R15D = 186,
203 R0H = 187,
204 R1H = 188,
205 R2H = 189,
206 R3H = 190,
207 R4H = 191,
208 R5H = 192,
209 R6H = 193,
210 R7H = 194,
211 R8H = 195,
212 R9H = 196,
213 R10H = 197,
214 R11H = 198,
215 R12H = 199,
216 R13H = 200,
217 R14H = 201,
218 R15H = 202,
219 R0L = 203,
220 R1L = 204,
221 R2L = 205,
222 R3L = 206,
223 R4L = 207,
224 R5L = 208,
225 R6L = 209,
226 R7L = 210,
227 R8L = 211,
228 R9L = 212,
229 R10L = 213,
230 R11L = 214,
231 R12L = 215,
232 R13L = 216,
233 R14L = 217,
234 R15L = 218,
235 R0Q = 219,
236 R2Q = 220,
237 R4Q = 221,
238 R6Q = 222,
239 R8Q = 223,
240 R10Q = 224,
241 R12Q = 225,
242 R14Q = 226,
243 NUM_TARGET_REGS // 227
244};
245} // end namespace SystemZ
246
247// Register classes
248
249namespace SystemZ {
250enum {
251 VR16BitRegClassID = 0,
252 FP16BitRegClassID = 1,
253 GRX32BitRegClassID = 2,
254 VR32BitRegClassID = 3,
255 AR32BitRegClassID = 4,
256 FP32BitRegClassID = 5,
257 GR32BitRegClassID = 6,
258 GRH32BitRegClassID = 7,
259 ADDR32BitRegClassID = 8,
260 CCRRegClassID = 9,
261 FPCRegsRegClassID = 10,
262 AnyRegBitRegClassID = 11,
263 AnyRegBit_with_subreg_h16RegClassID = 12,
264 VR64BitRegClassID = 13,
265 AnyRegBit_with_subreg_h64RegClassID = 14,
266 CR64BitRegClassID = 15,
267 FP64BitRegClassID = 16,
268 GR64BitRegClassID = 17,
269 ADDR64BitRegClassID = 18,
270 VR128BitRegClassID = 19,
271 VF128BitRegClassID = 20,
272 FP128BitRegClassID = 21,
273 GR128BitRegClassID = 22,
274 ADDR128BitRegClassID = 23,
275
276};
277} // end namespace SystemZ
278
279
280// Subregister indices
281
282namespace SystemZ {
283enum : uint16_t {
284 NoSubRegister,
285 subreg_h16, // 1
286 subreg_h32, // 2
287 subreg_h64, // 3
288 subreg_l32, // 4
289 subreg_l64, // 5
290 subreg_lh32, // 6
291 subreg_ll32, // 7
292 subreg_lh32_then_subreg_h16, // 8
293 NUM_TARGET_SUBREGS
294};
295} // end namespace SystemZ
296
297// Register pressure sets enum.
298namespace SystemZ {
299enum RegisterPressureSets {
300 FP16Bit = 0,
301 GR32Bit = 1,
302 GRH32Bit = 2,
303 VR16Bit = 3,
304 GRX32Bit = 4,
305};
306} // end namespace SystemZ
307
308} // end namespace llvm
309
310