| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* * VE Disassembler *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | |
| 10 | #include "llvm/MC/MCInst.h" |
| 11 | #include "llvm/MC/MCSubtargetInfo.h" |
| 12 | #include "llvm/Support/DataTypes.h" |
| 13 | #include "llvm/Support/Debug.h" |
| 14 | #include "llvm/Support/LEB128.h" |
| 15 | #include "llvm/Support/raw_ostream.h" |
| 16 | #include "llvm/TargetParser/SubtargetFeature.h" |
| 17 | #include <assert.h> |
| 18 | |
| 19 | namespace { |
| 20 | |
| 21 | // InsnBitWidth is essentially a type trait used by the decoder emitter to query |
| 22 | // the supported bitwidth for a given type. But default, the value is 0, making |
| 23 | // it an invalid type for use as `InsnType` when instantiating the decoder. |
| 24 | // Individual targets are expected to provide specializations for these based |
| 25 | // on their usage. |
| 26 | template <typename T> constexpr uint32_t InsnBitWidth = 0; |
| 27 | |
| 28 | static const uint8_t DecoderTableVE64[32221] = { |
| 29 | OPC_SwitchField, 55, 9, // 0: switch Inst[63:55] { |
| 30 | 2, 37, // 3: case 0x2: { |
| 31 | OPC_SwitchField, 39, 1, // 5: switch Inst[39] { |
| 32 | 0, 15, // 8: case 0x0: { |
| 33 | OPC_SwitchField, 47, 1, // 10: switch Inst[47] { |
| 34 | 0, 4, // 13: case 0x0: { |
| 35 | OPC_Decode, 150, 6, 0, // 15: decode to LDzii using decoder 0 |
| 36 | // 15: } |
| 37 | 1, 0, // 19: case 0x1: { |
| 38 | OPC_Decode, 151, 6, 0, // 21: decode to LDzri using decoder 0 |
| 39 | // 21: } |
| 40 | // 21: } // switch Inst[47] |
| 41 | // 21: } |
| 42 | 1, 0, // 25: case 0x1: { |
| 43 | OPC_SwitchField, 47, 1, // 27: switch Inst[47] { |
| 44 | 0, 4, // 30: case 0x0: { |
| 45 | OPC_Decode, 148, 6, 0, // 32: decode to LDrii using decoder 0 |
| 46 | // 32: } |
| 47 | 1, 0, // 36: case 0x1: { |
| 48 | OPC_Decode, 149, 6, 0, // 38: decode to LDrri using decoder 0 |
| 49 | // 38: } |
| 50 | // 38: } // switch Inst[47] |
| 51 | // 38: } |
| 52 | // 38: } // switch Inst[39] |
| 53 | // 38: } |
| 54 | 4, 37, // 42: case 0x4: { |
| 55 | OPC_SwitchField, 39, 1, // 44: switch Inst[39] { |
| 56 | 0, 15, // 47: case 0x0: { |
| 57 | OPC_SwitchField, 47, 1, // 49: switch Inst[47] { |
| 58 | 0, 4, // 52: case 0x0: { |
| 59 | OPC_Decode, 144, 6, 1, // 54: decode to LDUzii using decoder 1 |
| 60 | // 54: } |
| 61 | 1, 0, // 58: case 0x1: { |
| 62 | OPC_Decode, 145, 6, 1, // 60: decode to LDUzri using decoder 1 |
| 63 | // 60: } |
| 64 | // 60: } // switch Inst[47] |
| 65 | // 60: } |
| 66 | 1, 0, // 64: case 0x1: { |
| 67 | OPC_SwitchField, 47, 1, // 66: switch Inst[47] { |
| 68 | 0, 4, // 69: case 0x0: { |
| 69 | OPC_Decode, 142, 6, 1, // 71: decode to LDUrii using decoder 1 |
| 70 | // 71: } |
| 71 | 1, 0, // 75: case 0x1: { |
| 72 | OPC_Decode, 143, 6, 1, // 77: decode to LDUrri using decoder 1 |
| 73 | // 77: } |
| 74 | // 77: } // switch Inst[47] |
| 75 | // 77: } |
| 76 | // 77: } // switch Inst[39] |
| 77 | // 77: } |
| 78 | 6, 37, // 81: case 0x6: { |
| 79 | OPC_SwitchField, 39, 1, // 83: switch Inst[39] { |
| 80 | 0, 15, // 86: case 0x0: { |
| 81 | OPC_SwitchField, 47, 1, // 88: switch Inst[47] { |
| 82 | 0, 4, // 91: case 0x0: { |
| 83 | OPC_Decode, 136, 6, 2, // 93: decode to LDLSXzii using decoder 2 |
| 84 | // 93: } |
| 85 | 1, 0, // 97: case 0x1: { |
| 86 | OPC_Decode, 137, 6, 2, // 99: decode to LDLSXzri using decoder 2 |
| 87 | // 99: } |
| 88 | // 99: } // switch Inst[47] |
| 89 | // 99: } |
| 90 | 1, 0, // 103: case 0x1: { |
| 91 | OPC_SwitchField, 47, 1, // 105: switch Inst[47] { |
| 92 | 0, 4, // 108: case 0x0: { |
| 93 | OPC_Decode, 134, 6, 2, // 110: decode to LDLSXrii using decoder 2 |
| 94 | // 110: } |
| 95 | 1, 0, // 114: case 0x1: { |
| 96 | OPC_Decode, 135, 6, 2, // 116: decode to LDLSXrri using decoder 2 |
| 97 | // 116: } |
| 98 | // 116: } // switch Inst[47] |
| 99 | // 116: } |
| 100 | // 116: } // switch Inst[39] |
| 101 | // 116: } |
| 102 | 7, 37, // 120: case 0x7: { |
| 103 | OPC_SwitchField, 39, 1, // 122: switch Inst[39] { |
| 104 | 0, 15, // 125: case 0x0: { |
| 105 | OPC_SwitchField, 47, 1, // 127: switch Inst[47] { |
| 106 | 0, 4, // 130: case 0x0: { |
| 107 | OPC_Decode, 140, 6, 2, // 132: decode to LDLZXzii using decoder 2 |
| 108 | // 132: } |
| 109 | 1, 0, // 136: case 0x1: { |
| 110 | OPC_Decode, 141, 6, 2, // 138: decode to LDLZXzri using decoder 2 |
| 111 | // 138: } |
| 112 | // 138: } // switch Inst[47] |
| 113 | // 138: } |
| 114 | 1, 0, // 142: case 0x1: { |
| 115 | OPC_SwitchField, 47, 1, // 144: switch Inst[47] { |
| 116 | 0, 4, // 147: case 0x0: { |
| 117 | OPC_Decode, 138, 6, 2, // 149: decode to LDLZXrii using decoder 2 |
| 118 | // 149: } |
| 119 | 1, 0, // 153: case 0x1: { |
| 120 | OPC_Decode, 139, 6, 2, // 155: decode to LDLZXrri using decoder 2 |
| 121 | // 155: } |
| 122 | // 155: } // switch Inst[47] |
| 123 | // 155: } |
| 124 | // 155: } // switch Inst[39] |
| 125 | // 155: } |
| 126 | 8, 37, // 159: case 0x8: { |
| 127 | OPC_SwitchField, 39, 1, // 161: switch Inst[39] { |
| 128 | 0, 15, // 164: case 0x0: { |
| 129 | OPC_SwitchField, 47, 1, // 166: switch Inst[47] { |
| 130 | 0, 4, // 169: case 0x0: { |
| 131 | OPC_Decode, 128, 6, 2, // 171: decode to LD2BSXzii using decoder 2 |
| 132 | // 171: } |
| 133 | 1, 0, // 175: case 0x1: { |
| 134 | OPC_Decode, 129, 6, 2, // 177: decode to LD2BSXzri using decoder 2 |
| 135 | // 177: } |
| 136 | // 177: } // switch Inst[47] |
| 137 | // 177: } |
| 138 | 1, 0, // 181: case 0x1: { |
| 139 | OPC_SwitchField, 47, 1, // 183: switch Inst[47] { |
| 140 | 0, 4, // 186: case 0x0: { |
| 141 | OPC_Decode, 254, 5, 2, // 188: decode to LD2BSXrii using decoder 2 |
| 142 | // 188: } |
| 143 | 1, 0, // 192: case 0x1: { |
| 144 | OPC_Decode, 255, 5, 2, // 194: decode to LD2BSXrri using decoder 2 |
| 145 | // 194: } |
| 146 | // 194: } // switch Inst[47] |
| 147 | // 194: } |
| 148 | // 194: } // switch Inst[39] |
| 149 | // 194: } |
| 150 | 9, 37, // 198: case 0x9: { |
| 151 | OPC_SwitchField, 39, 1, // 200: switch Inst[39] { |
| 152 | 0, 15, // 203: case 0x0: { |
| 153 | OPC_SwitchField, 47, 1, // 205: switch Inst[47] { |
| 154 | 0, 4, // 208: case 0x0: { |
| 155 | OPC_Decode, 132, 6, 2, // 210: decode to LD2BZXzii using decoder 2 |
| 156 | // 210: } |
| 157 | 1, 0, // 214: case 0x1: { |
| 158 | OPC_Decode, 133, 6, 2, // 216: decode to LD2BZXzri using decoder 2 |
| 159 | // 216: } |
| 160 | // 216: } // switch Inst[47] |
| 161 | // 216: } |
| 162 | 1, 0, // 220: case 0x1: { |
| 163 | OPC_SwitchField, 47, 1, // 222: switch Inst[47] { |
| 164 | 0, 4, // 225: case 0x0: { |
| 165 | OPC_Decode, 130, 6, 2, // 227: decode to LD2BZXrii using decoder 2 |
| 166 | // 227: } |
| 167 | 1, 0, // 231: case 0x1: { |
| 168 | OPC_Decode, 131, 6, 2, // 233: decode to LD2BZXrri using decoder 2 |
| 169 | // 233: } |
| 170 | // 233: } // switch Inst[47] |
| 171 | // 233: } |
| 172 | // 233: } // switch Inst[39] |
| 173 | // 233: } |
| 174 | 10, 37, // 237: case 0xa: { |
| 175 | OPC_SwitchField, 39, 1, // 239: switch Inst[39] { |
| 176 | 0, 15, // 242: case 0x0: { |
| 177 | OPC_SwitchField, 47, 1, // 244: switch Inst[47] { |
| 178 | 0, 4, // 247: case 0x0: { |
| 179 | OPC_Decode, 248, 5, 2, // 249: decode to LD1BSXzii using decoder 2 |
| 180 | // 249: } |
| 181 | 1, 0, // 253: case 0x1: { |
| 182 | OPC_Decode, 249, 5, 2, // 255: decode to LD1BSXzri using decoder 2 |
| 183 | // 255: } |
| 184 | // 255: } // switch Inst[47] |
| 185 | // 255: } |
| 186 | 1, 0, // 259: case 0x1: { |
| 187 | OPC_SwitchField, 47, 1, // 261: switch Inst[47] { |
| 188 | 0, 4, // 264: case 0x0: { |
| 189 | OPC_Decode, 246, 5, 2, // 266: decode to LD1BSXrii using decoder 2 |
| 190 | // 266: } |
| 191 | 1, 0, // 270: case 0x1: { |
| 192 | OPC_Decode, 247, 5, 2, // 272: decode to LD1BSXrri using decoder 2 |
| 193 | // 272: } |
| 194 | // 272: } // switch Inst[47] |
| 195 | // 272: } |
| 196 | // 272: } // switch Inst[39] |
| 197 | // 272: } |
| 198 | 11, 37, // 276: case 0xb: { |
| 199 | OPC_SwitchField, 39, 1, // 278: switch Inst[39] { |
| 200 | 0, 15, // 281: case 0x0: { |
| 201 | OPC_SwitchField, 47, 1, // 283: switch Inst[47] { |
| 202 | 0, 4, // 286: case 0x0: { |
| 203 | OPC_Decode, 252, 5, 2, // 288: decode to LD1BZXzii using decoder 2 |
| 204 | // 288: } |
| 205 | 1, 0, // 292: case 0x1: { |
| 206 | OPC_Decode, 253, 5, 2, // 294: decode to LD1BZXzri using decoder 2 |
| 207 | // 294: } |
| 208 | // 294: } // switch Inst[47] |
| 209 | // 294: } |
| 210 | 1, 0, // 298: case 0x1: { |
| 211 | OPC_SwitchField, 47, 1, // 300: switch Inst[47] { |
| 212 | 0, 4, // 303: case 0x0: { |
| 213 | OPC_Decode, 250, 5, 2, // 305: decode to LD1BZXrii using decoder 2 |
| 214 | // 305: } |
| 215 | 1, 0, // 309: case 0x1: { |
| 216 | OPC_Decode, 251, 5, 2, // 311: decode to LD1BZXrri using decoder 2 |
| 217 | // 311: } |
| 218 | // 311: } // switch Inst[47] |
| 219 | // 311: } |
| 220 | // 311: } // switch Inst[39] |
| 221 | // 311: } |
| 222 | 12, 37, // 315: case 0xc: { |
| 223 | OPC_SwitchField, 39, 1, // 317: switch Inst[39] { |
| 224 | 0, 15, // 320: case 0x0: { |
| 225 | OPC_SwitchField, 47, 1, // 322: switch Inst[47] { |
| 226 | 0, 4, // 325: case 0x0: { |
| 227 | OPC_Decode, 158, 6, 0, // 327: decode to LEAzii using decoder 0 |
| 228 | // 327: } |
| 229 | 1, 0, // 331: case 0x1: { |
| 230 | OPC_Decode, 159, 6, 0, // 333: decode to LEAzri using decoder 0 |
| 231 | // 333: } |
| 232 | // 333: } // switch Inst[47] |
| 233 | // 333: } |
| 234 | 1, 0, // 337: case 0x1: { |
| 235 | OPC_SwitchField, 47, 1, // 339: switch Inst[47] { |
| 236 | 0, 4, // 342: case 0x0: { |
| 237 | OPC_Decode, 156, 6, 0, // 344: decode to LEArii using decoder 0 |
| 238 | // 344: } |
| 239 | 1, 0, // 348: case 0x1: { |
| 240 | OPC_Decode, 157, 6, 0, // 350: decode to LEArri using decoder 0 |
| 241 | // 350: } |
| 242 | // 350: } // switch Inst[47] |
| 243 | // 350: } |
| 244 | // 350: } // switch Inst[39] |
| 245 | // 350: } |
| 246 | 13, 37, // 354: case 0xd: { |
| 247 | OPC_SwitchField, 39, 1, // 356: switch Inst[39] { |
| 248 | 0, 15, // 359: case 0x0: { |
| 249 | OPC_SwitchField, 47, 1, // 361: switch Inst[47] { |
| 250 | 0, 4, // 364: case 0x0: { |
| 251 | OPC_Decode, 154, 6, 0, // 366: decode to LEASLzii using decoder 0 |
| 252 | // 366: } |
| 253 | 1, 0, // 370: case 0x1: { |
| 254 | OPC_Decode, 155, 6, 0, // 372: decode to LEASLzri using decoder 0 |
| 255 | // 372: } |
| 256 | // 372: } // switch Inst[47] |
| 257 | // 372: } |
| 258 | 1, 0, // 376: case 0x1: { |
| 259 | OPC_SwitchField, 47, 1, // 378: switch Inst[47] { |
| 260 | 0, 4, // 381: case 0x0: { |
| 261 | OPC_Decode, 152, 6, 0, // 383: decode to LEASLrii using decoder 0 |
| 262 | // 383: } |
| 263 | 1, 0, // 387: case 0x1: { |
| 264 | OPC_Decode, 153, 6, 0, // 389: decode to LEASLrri using decoder 0 |
| 265 | // 389: } |
| 266 | // 389: } // switch Inst[47] |
| 267 | // 389: } |
| 268 | // 389: } // switch Inst[39] |
| 269 | // 389: } |
| 270 | 16, 37, // 393: case 0x10: { |
| 271 | OPC_SwitchField, 39, 1, // 395: switch Inst[39] { |
| 272 | 0, 15, // 398: case 0x0: { |
| 273 | OPC_SwitchField, 47, 1, // 400: switch Inst[47] { |
| 274 | 0, 4, // 403: case 0x0: { |
| 275 | OPC_Decode, 175, 4, 3, // 405: decode to BSICzii using decoder 3 |
| 276 | // 405: } |
| 277 | 1, 0, // 409: case 0x1: { |
| 278 | OPC_Decode, 176, 4, 3, // 411: decode to BSICzri using decoder 3 |
| 279 | // 411: } |
| 280 | // 411: } // switch Inst[47] |
| 281 | // 411: } |
| 282 | 1, 0, // 415: case 0x1: { |
| 283 | OPC_SwitchField, 47, 1, // 417: switch Inst[47] { |
| 284 | 0, 4, // 420: case 0x0: { |
| 285 | OPC_Decode, 173, 4, 3, // 422: decode to BSICrii using decoder 3 |
| 286 | // 422: } |
| 287 | 1, 0, // 426: case 0x1: { |
| 288 | OPC_Decode, 174, 4, 3, // 428: decode to BSICrri using decoder 3 |
| 289 | // 428: } |
| 290 | // 428: } // switch Inst[47] |
| 291 | // 428: } |
| 292 | // 428: } // switch Inst[39] |
| 293 | // 428: } |
| 294 | 18, 37, // 432: case 0x12: { |
| 295 | OPC_SwitchField, 39, 1, // 434: switch Inst[39] { |
| 296 | 0, 15, // 437: case 0x0: { |
| 297 | OPC_SwitchField, 47, 1, // 439: switch Inst[47] { |
| 298 | 0, 4, // 442: case 0x0: { |
| 299 | OPC_Decode, 158, 5, 0, // 444: decode to DLDzii using decoder 0 |
| 300 | // 444: } |
| 301 | 1, 0, // 448: case 0x1: { |
| 302 | OPC_Decode, 159, 5, 0, // 450: decode to DLDzri using decoder 0 |
| 303 | // 450: } |
| 304 | // 450: } // switch Inst[47] |
| 305 | // 450: } |
| 306 | 1, 0, // 454: case 0x1: { |
| 307 | OPC_SwitchField, 47, 1, // 456: switch Inst[47] { |
| 308 | 0, 4, // 459: case 0x0: { |
| 309 | OPC_Decode, 156, 5, 0, // 461: decode to DLDrii using decoder 0 |
| 310 | // 461: } |
| 311 | 1, 0, // 465: case 0x1: { |
| 312 | OPC_Decode, 157, 5, 0, // 467: decode to DLDrri using decoder 0 |
| 313 | // 467: } |
| 314 | // 467: } // switch Inst[47] |
| 315 | // 467: } |
| 316 | // 467: } // switch Inst[39] |
| 317 | // 467: } |
| 318 | 20, 37, // 471: case 0x14: { |
| 319 | OPC_SwitchField, 39, 1, // 473: switch Inst[39] { |
| 320 | 0, 15, // 476: case 0x0: { |
| 321 | OPC_SwitchField, 47, 1, // 478: switch Inst[47] { |
| 322 | 0, 4, // 481: case 0x0: { |
| 323 | OPC_Decode, 154, 5, 1, // 483: decode to DLDUzii using decoder 1 |
| 324 | // 483: } |
| 325 | 1, 0, // 487: case 0x1: { |
| 326 | OPC_Decode, 155, 5, 1, // 489: decode to DLDUzri using decoder 1 |
| 327 | // 489: } |
| 328 | // 489: } // switch Inst[47] |
| 329 | // 489: } |
| 330 | 1, 0, // 493: case 0x1: { |
| 331 | OPC_SwitchField, 47, 1, // 495: switch Inst[47] { |
| 332 | 0, 4, // 498: case 0x0: { |
| 333 | OPC_Decode, 152, 5, 1, // 500: decode to DLDUrii using decoder 1 |
| 334 | // 500: } |
| 335 | 1, 0, // 504: case 0x1: { |
| 336 | OPC_Decode, 153, 5, 1, // 506: decode to DLDUrri using decoder 1 |
| 337 | // 506: } |
| 338 | // 506: } // switch Inst[47] |
| 339 | // 506: } |
| 340 | // 506: } // switch Inst[39] |
| 341 | // 506: } |
| 342 | 22, 37, // 510: case 0x16: { |
| 343 | OPC_SwitchField, 39, 1, // 512: switch Inst[39] { |
| 344 | 0, 15, // 515: case 0x0: { |
| 345 | OPC_SwitchField, 47, 1, // 517: switch Inst[47] { |
| 346 | 0, 4, // 520: case 0x0: { |
| 347 | OPC_Decode, 146, 5, 2, // 522: decode to DLDLSXzii using decoder 2 |
| 348 | // 522: } |
| 349 | 1, 0, // 526: case 0x1: { |
| 350 | OPC_Decode, 147, 5, 2, // 528: decode to DLDLSXzri using decoder 2 |
| 351 | // 528: } |
| 352 | // 528: } // switch Inst[47] |
| 353 | // 528: } |
| 354 | 1, 0, // 532: case 0x1: { |
| 355 | OPC_SwitchField, 47, 1, // 534: switch Inst[47] { |
| 356 | 0, 4, // 537: case 0x0: { |
| 357 | OPC_Decode, 144, 5, 2, // 539: decode to DLDLSXrii using decoder 2 |
| 358 | // 539: } |
| 359 | 1, 0, // 543: case 0x1: { |
| 360 | OPC_Decode, 145, 5, 2, // 545: decode to DLDLSXrri using decoder 2 |
| 361 | // 545: } |
| 362 | // 545: } // switch Inst[47] |
| 363 | // 545: } |
| 364 | // 545: } // switch Inst[39] |
| 365 | // 545: } |
| 366 | 23, 37, // 549: case 0x17: { |
| 367 | OPC_SwitchField, 39, 1, // 551: switch Inst[39] { |
| 368 | 0, 15, // 554: case 0x0: { |
| 369 | OPC_SwitchField, 47, 1, // 556: switch Inst[47] { |
| 370 | 0, 4, // 559: case 0x0: { |
| 371 | OPC_Decode, 150, 5, 2, // 561: decode to DLDLZXzii using decoder 2 |
| 372 | // 561: } |
| 373 | 1, 0, // 565: case 0x1: { |
| 374 | OPC_Decode, 151, 5, 2, // 567: decode to DLDLZXzri using decoder 2 |
| 375 | // 567: } |
| 376 | // 567: } // switch Inst[47] |
| 377 | // 567: } |
| 378 | 1, 0, // 571: case 0x1: { |
| 379 | OPC_SwitchField, 47, 1, // 573: switch Inst[47] { |
| 380 | 0, 4, // 576: case 0x0: { |
| 381 | OPC_Decode, 148, 5, 2, // 578: decode to DLDLZXrii using decoder 2 |
| 382 | // 578: } |
| 383 | 1, 0, // 582: case 0x1: { |
| 384 | OPC_Decode, 149, 5, 2, // 584: decode to DLDLZXrri using decoder 2 |
| 385 | // 584: } |
| 386 | // 584: } // switch Inst[47] |
| 387 | // 584: } |
| 388 | // 584: } // switch Inst[39] |
| 389 | // 584: } |
| 390 | 24, 37, // 588: case 0x18: { |
| 391 | OPC_SwitchField, 39, 1, // 590: switch Inst[39] { |
| 392 | 0, 15, // 593: case 0x0: { |
| 393 | OPC_SwitchField, 47, 8, // 595: switch Inst[54:47] { |
| 394 | 0, 4, // 598: case 0x0: { |
| 395 | OPC_Decode, 165, 7, 4, // 600: decode to PFCHzii using decoder 4 |
| 396 | // 600: } |
| 397 | 1, 0, // 604: case 0x1: { |
| 398 | OPC_Decode, 166, 7, 4, // 606: decode to PFCHzri using decoder 4 |
| 399 | // 606: } |
| 400 | // 606: } // switch Inst[54:47] |
| 401 | // 606: } |
| 402 | 1, 0, // 610: case 0x1: { |
| 403 | OPC_SwitchField, 47, 8, // 612: switch Inst[54:47] { |
| 404 | 0, 4, // 615: case 0x0: { |
| 405 | OPC_Decode, 163, 7, 4, // 617: decode to PFCHrii using decoder 4 |
| 406 | // 617: } |
| 407 | 1, 0, // 621: case 0x1: { |
| 408 | OPC_Decode, 164, 7, 4, // 623: decode to PFCHrri using decoder 4 |
| 409 | // 623: } |
| 410 | // 623: } // switch Inst[54:47] |
| 411 | // 623: } |
| 412 | // 623: } // switch Inst[39] |
| 413 | // 623: } |
| 414 | 30, 23, // 627: case 0x1e: { |
| 415 | OPC_SwitchField, 47, 1, // 629: switch Inst[47] { |
| 416 | 0, 8, // 632: case 0x0: { |
| 417 | OPC_CheckField, 0, 40, 0, // 634: check Inst[39:0] == 0x0 |
| 418 | OPC_Decode, 228, 4, 5, // 638: decode to CVTDSi using decoder 5 |
| 419 | // 638: } |
| 420 | 1, 0, // 642: case 0x1: { |
| 421 | OPC_CheckField, 0, 40, 0, // 644: check Inst[39:0] == 0x0 |
| 422 | OPC_Decode, 229, 4, 6, // 648: decode to CVTDSr using decoder 6 |
| 423 | // 648: } |
| 424 | // 648: } // switch Inst[47] |
| 425 | // 648: } |
| 426 | 31, 23, // 652: case 0x1f: { |
| 427 | OPC_SwitchField, 47, 1, // 654: switch Inst[47] { |
| 428 | 0, 8, // 657: case 0x0: { |
| 429 | OPC_CheckField, 0, 40, 0, // 659: check Inst[39:0] == 0x0 |
| 430 | OPC_Decode, 226, 4, 5, // 663: decode to CVTDQi using decoder 5 |
| 431 | // 663: } |
| 432 | 1, 0, // 667: case 0x1: { |
| 433 | OPC_CheckField, 0, 40, 0, // 669: check Inst[39:0] == 0x0 |
| 434 | OPC_Decode, 227, 4, 7, // 673: decode to CVTDQr using decoder 7 |
| 435 | // 673: } |
| 436 | // 673: } // switch Inst[47] |
| 437 | // 673: } |
| 438 | 34, 37, // 677: case 0x22: { |
| 439 | OPC_SwitchField, 39, 1, // 679: switch Inst[39] { |
| 440 | 0, 15, // 682: case 0x0: { |
| 441 | OPC_SwitchField, 47, 1, // 684: switch Inst[47] { |
| 442 | 0, 4, // 687: case 0x0: { |
| 443 | OPC_Decode, 175, 35, 8, // 689: decode to STzii using decoder 8 |
| 444 | // 689: } |
| 445 | 1, 0, // 693: case 0x1: { |
| 446 | OPC_Decode, 176, 35, 8, // 695: decode to STzri using decoder 8 |
| 447 | // 695: } |
| 448 | // 695: } // switch Inst[47] |
| 449 | // 695: } |
| 450 | 1, 0, // 699: case 0x1: { |
| 451 | OPC_SwitchField, 47, 1, // 701: switch Inst[47] { |
| 452 | 0, 4, // 704: case 0x0: { |
| 453 | OPC_Decode, 173, 35, 8, // 706: decode to STrii using decoder 8 |
| 454 | // 706: } |
| 455 | 1, 0, // 710: case 0x1: { |
| 456 | OPC_Decode, 174, 35, 8, // 712: decode to STrri using decoder 8 |
| 457 | // 712: } |
| 458 | // 712: } // switch Inst[47] |
| 459 | // 712: } |
| 460 | // 712: } // switch Inst[39] |
| 461 | // 712: } |
| 462 | 36, 37, // 716: case 0x24: { |
| 463 | OPC_SwitchField, 39, 1, // 718: switch Inst[39] { |
| 464 | 0, 15, // 721: case 0x0: { |
| 465 | OPC_SwitchField, 47, 1, // 723: switch Inst[47] { |
| 466 | 0, 4, // 726: case 0x0: { |
| 467 | OPC_Decode, 171, 35, 9, // 728: decode to STUzii using decoder 9 |
| 468 | // 728: } |
| 469 | 1, 0, // 732: case 0x1: { |
| 470 | OPC_Decode, 172, 35, 9, // 734: decode to STUzri using decoder 9 |
| 471 | // 734: } |
| 472 | // 734: } // switch Inst[47] |
| 473 | // 734: } |
| 474 | 1, 0, // 738: case 0x1: { |
| 475 | OPC_SwitchField, 47, 1, // 740: switch Inst[47] { |
| 476 | 0, 4, // 743: case 0x0: { |
| 477 | OPC_Decode, 169, 35, 9, // 745: decode to STUrii using decoder 9 |
| 478 | // 745: } |
| 479 | 1, 0, // 749: case 0x1: { |
| 480 | OPC_Decode, 170, 35, 9, // 751: decode to STUrri using decoder 9 |
| 481 | // 751: } |
| 482 | // 751: } // switch Inst[47] |
| 483 | // 751: } |
| 484 | // 751: } // switch Inst[39] |
| 485 | // 751: } |
| 486 | 38, 37, // 755: case 0x26: { |
| 487 | OPC_SwitchField, 39, 1, // 757: switch Inst[39] { |
| 488 | 0, 15, // 760: case 0x0: { |
| 489 | OPC_SwitchField, 47, 1, // 762: switch Inst[47] { |
| 490 | 0, 4, // 765: case 0x0: { |
| 491 | OPC_Decode, 167, 35, 10, // 767: decode to STLzii using decoder 10 |
| 492 | // 767: } |
| 493 | 1, 0, // 771: case 0x1: { |
| 494 | OPC_Decode, 168, 35, 10, // 773: decode to STLzri using decoder 10 |
| 495 | // 773: } |
| 496 | // 773: } // switch Inst[47] |
| 497 | // 773: } |
| 498 | 1, 0, // 777: case 0x1: { |
| 499 | OPC_SwitchField, 47, 1, // 779: switch Inst[47] { |
| 500 | 0, 4, // 782: case 0x0: { |
| 501 | OPC_Decode, 165, 35, 10, // 784: decode to STLrii using decoder 10 |
| 502 | // 784: } |
| 503 | 1, 0, // 788: case 0x1: { |
| 504 | OPC_Decode, 166, 35, 10, // 790: decode to STLrri using decoder 10 |
| 505 | // 790: } |
| 506 | // 790: } // switch Inst[47] |
| 507 | // 790: } |
| 508 | // 790: } // switch Inst[39] |
| 509 | // 790: } |
| 510 | 40, 37, // 794: case 0x28: { |
| 511 | OPC_SwitchField, 39, 1, // 796: switch Inst[39] { |
| 512 | 0, 15, // 799: case 0x0: { |
| 513 | OPC_SwitchField, 47, 1, // 801: switch Inst[47] { |
| 514 | 0, 4, // 804: case 0x0: { |
| 515 | OPC_Decode, 163, 35, 10, // 806: decode to ST2Bzii using decoder 10 |
| 516 | // 806: } |
| 517 | 1, 0, // 810: case 0x1: { |
| 518 | OPC_Decode, 164, 35, 10, // 812: decode to ST2Bzri using decoder 10 |
| 519 | // 812: } |
| 520 | // 812: } // switch Inst[47] |
| 521 | // 812: } |
| 522 | 1, 0, // 816: case 0x1: { |
| 523 | OPC_SwitchField, 47, 1, // 818: switch Inst[47] { |
| 524 | 0, 4, // 821: case 0x0: { |
| 525 | OPC_Decode, 161, 35, 10, // 823: decode to ST2Brii using decoder 10 |
| 526 | // 823: } |
| 527 | 1, 0, // 827: case 0x1: { |
| 528 | OPC_Decode, 162, 35, 10, // 829: decode to ST2Brri using decoder 10 |
| 529 | // 829: } |
| 530 | // 829: } // switch Inst[47] |
| 531 | // 829: } |
| 532 | // 829: } // switch Inst[39] |
| 533 | // 829: } |
| 534 | 42, 37, // 833: case 0x2a: { |
| 535 | OPC_SwitchField, 39, 1, // 835: switch Inst[39] { |
| 536 | 0, 15, // 838: case 0x0: { |
| 537 | OPC_SwitchField, 47, 1, // 840: switch Inst[47] { |
| 538 | 0, 4, // 843: case 0x0: { |
| 539 | OPC_Decode, 159, 35, 10, // 845: decode to ST1Bzii using decoder 10 |
| 540 | // 845: } |
| 541 | 1, 0, // 849: case 0x1: { |
| 542 | OPC_Decode, 160, 35, 10, // 851: decode to ST1Bzri using decoder 10 |
| 543 | // 851: } |
| 544 | // 851: } // switch Inst[47] |
| 545 | // 851: } |
| 546 | 1, 0, // 855: case 0x1: { |
| 547 | OPC_SwitchField, 47, 1, // 857: switch Inst[47] { |
| 548 | 0, 4, // 860: case 0x0: { |
| 549 | OPC_Decode, 157, 35, 10, // 862: decode to ST1Brii using decoder 10 |
| 550 | // 862: } |
| 551 | 1, 0, // 866: case 0x1: { |
| 552 | OPC_Decode, 158, 35, 10, // 868: decode to ST1Brri using decoder 10 |
| 553 | // 868: } |
| 554 | // 868: } // switch Inst[47] |
| 555 | // 868: } |
| 556 | // 868: } // switch Inst[39] |
| 557 | // 868: } |
| 558 | 48, 179, 3, // 872: case 0x30: { |
| 559 | OPC_SwitchField, 52, 3, // 875: switch Inst[54:52] { |
| 560 | 0, 70, // 878: case 0x0: { |
| 561 | OPC_SwitchField, 39, 1, // 880: switch Inst[39] { |
| 562 | 0, 48, // 883: case 0x0: { |
| 563 | OPC_SwitchField, 47, 1, // 885: switch Inst[47] { |
| 564 | 0, 37, // 888: case 0x0: { |
| 565 | OPC_Scope, 31, // 890: try { |
| 566 | OPC_SwitchField, 48, 4, // 892: switch Inst[51:48] { |
| 567 | 0, 12, // 895: case 0x0: { |
| 568 | OPC_CheckField, 40, 7, 0, // 897: check Inst[46:40] == 0x0 |
| 569 | OPC_CheckField, 32, 7, 0, // 901: check Inst[38:32] == 0x0 |
| 570 | OPC_Decode, 254, 3, 11, // 905: decode to BRCFLna using decoder 11 |
| 571 | // 905: } |
| 572 | 15, 0, // 909: case 0xf: { |
| 573 | OPC_CheckField, 40, 7, 0, // 911: check Inst[46:40] == 0x0 |
| 574 | OPC_CheckField, 32, 7, 0, // 915: check Inst[38:32] == 0x0 |
| 575 | OPC_Decode, 245, 3, 11, // 919: decode to BRCFLa using decoder 11 |
| 576 | // 919: } |
| 577 | // 919: } // switch Inst[51:48] |
| 578 | // 919: } else try { |
| 579 | OPC_Decode, 251, 3, 12, // 923: decode to BRCFLiz using decoder 12 |
| 580 | // 923: } |
| 581 | // 923: } |
| 582 | 1, 0, // 927: case 0x1: { |
| 583 | OPC_Decode, 132, 4, 13, // 929: decode to BRCFLrz using decoder 13 |
| 584 | // 929: } |
| 585 | // 929: } // switch Inst[47] |
| 586 | // 929: } |
| 587 | 1, 0, // 933: case 0x1: { |
| 588 | OPC_SwitchField, 47, 1, // 935: switch Inst[47] { |
| 589 | 0, 4, // 938: case 0x0: { |
| 590 | OPC_Decode, 248, 3, 14, // 940: decode to BRCFLir using decoder 14 |
| 591 | // 940: } |
| 592 | 1, 0, // 944: case 0x1: { |
| 593 | OPC_Decode, 129, 4, 15, // 946: decode to BRCFLrr using decoder 15 |
| 594 | // 946: } |
| 595 | // 946: } // switch Inst[47] |
| 596 | // 946: } |
| 597 | // 946: } // switch Inst[39] |
| 598 | // 946: } |
| 599 | 2, 70, // 950: case 0x2: { |
| 600 | OPC_SwitchField, 39, 1, // 952: switch Inst[39] { |
| 601 | 0, 48, // 955: case 0x0: { |
| 602 | OPC_SwitchField, 47, 1, // 957: switch Inst[47] { |
| 603 | 0, 37, // 960: case 0x0: { |
| 604 | OPC_Scope, 31, // 962: try { |
| 605 | OPC_SwitchField, 48, 4, // 964: switch Inst[51:48] { |
| 606 | 0, 12, // 967: case 0x0: { |
| 607 | OPC_CheckField, 40, 7, 0, // 969: check Inst[46:40] == 0x0 |
| 608 | OPC_CheckField, 32, 7, 0, // 973: check Inst[38:32] == 0x0 |
| 609 | OPC_Decode, 255, 3, 11, // 977: decode to BRCFLna_nt using decoder 11 |
| 610 | // 977: } |
| 611 | 15, 0, // 981: case 0xf: { |
| 612 | OPC_CheckField, 40, 7, 0, // 983: check Inst[46:40] == 0x0 |
| 613 | OPC_CheckField, 32, 7, 0, // 987: check Inst[38:32] == 0x0 |
| 614 | OPC_Decode, 246, 3, 11, // 991: decode to BRCFLa_nt using decoder 11 |
| 615 | // 991: } |
| 616 | // 991: } // switch Inst[51:48] |
| 617 | // 991: } else try { |
| 618 | OPC_Decode, 252, 3, 12, // 995: decode to BRCFLiz_nt using decoder 12 |
| 619 | // 995: } |
| 620 | // 995: } |
| 621 | 1, 0, // 999: case 0x1: { |
| 622 | OPC_Decode, 133, 4, 13, // 1001: decode to BRCFLrz_nt using decoder 13 |
| 623 | // 1001: } |
| 624 | // 1001: } // switch Inst[47] |
| 625 | // 1001: } |
| 626 | 1, 0, // 1005: case 0x1: { |
| 627 | OPC_SwitchField, 47, 1, // 1007: switch Inst[47] { |
| 628 | 0, 4, // 1010: case 0x0: { |
| 629 | OPC_Decode, 249, 3, 14, // 1012: decode to BRCFLir_nt using decoder 14 |
| 630 | // 1012: } |
| 631 | 1, 0, // 1016: case 0x1: { |
| 632 | OPC_Decode, 130, 4, 15, // 1018: decode to BRCFLrr_nt using decoder 15 |
| 633 | // 1018: } |
| 634 | // 1018: } // switch Inst[47] |
| 635 | // 1018: } |
| 636 | // 1018: } // switch Inst[39] |
| 637 | // 1018: } |
| 638 | 3, 70, // 1022: case 0x3: { |
| 639 | OPC_SwitchField, 39, 1, // 1024: switch Inst[39] { |
| 640 | 0, 48, // 1027: case 0x0: { |
| 641 | OPC_SwitchField, 47, 1, // 1029: switch Inst[47] { |
| 642 | 0, 37, // 1032: case 0x0: { |
| 643 | OPC_Scope, 31, // 1034: try { |
| 644 | OPC_SwitchField, 48, 4, // 1036: switch Inst[51:48] { |
| 645 | 0, 12, // 1039: case 0x0: { |
| 646 | OPC_CheckField, 40, 7, 0, // 1041: check Inst[46:40] == 0x0 |
| 647 | OPC_CheckField, 32, 7, 0, // 1045: check Inst[38:32] == 0x0 |
| 648 | OPC_Decode, 128, 4, 11, // 1049: decode to BRCFLna_t using decoder 11 |
| 649 | // 1049: } |
| 650 | 15, 0, // 1053: case 0xf: { |
| 651 | OPC_CheckField, 40, 7, 0, // 1055: check Inst[46:40] == 0x0 |
| 652 | OPC_CheckField, 32, 7, 0, // 1059: check Inst[38:32] == 0x0 |
| 653 | OPC_Decode, 247, 3, 11, // 1063: decode to BRCFLa_t using decoder 11 |
| 654 | // 1063: } |
| 655 | // 1063: } // switch Inst[51:48] |
| 656 | // 1063: } else try { |
| 657 | OPC_Decode, 253, 3, 12, // 1067: decode to BRCFLiz_t using decoder 12 |
| 658 | // 1067: } |
| 659 | // 1067: } |
| 660 | 1, 0, // 1071: case 0x1: { |
| 661 | OPC_Decode, 134, 4, 13, // 1073: decode to BRCFLrz_t using decoder 13 |
| 662 | // 1073: } |
| 663 | // 1073: } // switch Inst[47] |
| 664 | // 1073: } |
| 665 | 1, 0, // 1077: case 0x1: { |
| 666 | OPC_SwitchField, 47, 1, // 1079: switch Inst[47] { |
| 667 | 0, 4, // 1082: case 0x0: { |
| 668 | OPC_Decode, 250, 3, 14, // 1084: decode to BRCFLir_t using decoder 14 |
| 669 | // 1084: } |
| 670 | 1, 0, // 1088: case 0x1: { |
| 671 | OPC_Decode, 131, 4, 15, // 1090: decode to BRCFLrr_t using decoder 15 |
| 672 | // 1090: } |
| 673 | // 1090: } // switch Inst[47] |
| 674 | // 1090: } |
| 675 | // 1090: } // switch Inst[39] |
| 676 | // 1090: } |
| 677 | 4, 70, // 1094: case 0x4: { |
| 678 | OPC_SwitchField, 39, 1, // 1096: switch Inst[39] { |
| 679 | 0, 48, // 1099: case 0x0: { |
| 680 | OPC_SwitchField, 47, 1, // 1101: switch Inst[47] { |
| 681 | 0, 37, // 1104: case 0x0: { |
| 682 | OPC_Scope, 31, // 1106: try { |
| 683 | OPC_SwitchField, 48, 4, // 1108: switch Inst[51:48] { |
| 684 | 0, 12, // 1111: case 0x0: { |
| 685 | OPC_CheckField, 40, 7, 0, // 1113: check Inst[46:40] == 0x0 |
| 686 | OPC_CheckField, 32, 7, 0, // 1117: check Inst[38:32] == 0x0 |
| 687 | OPC_Decode, 236, 3, 11, // 1121: decode to BRCFDna using decoder 11 |
| 688 | // 1121: } |
| 689 | 15, 0, // 1125: case 0xf: { |
| 690 | OPC_CheckField, 40, 7, 0, // 1127: check Inst[46:40] == 0x0 |
| 691 | OPC_CheckField, 32, 7, 0, // 1131: check Inst[38:32] == 0x0 |
| 692 | OPC_Decode, 227, 3, 11, // 1135: decode to BRCFDa using decoder 11 |
| 693 | // 1135: } |
| 694 | // 1135: } // switch Inst[51:48] |
| 695 | // 1135: } else try { |
| 696 | OPC_Decode, 233, 3, 12, // 1139: decode to BRCFDiz using decoder 12 |
| 697 | // 1139: } |
| 698 | // 1139: } |
| 699 | 1, 0, // 1143: case 0x1: { |
| 700 | OPC_Decode, 242, 3, 13, // 1145: decode to BRCFDrz using decoder 13 |
| 701 | // 1145: } |
| 702 | // 1145: } // switch Inst[47] |
| 703 | // 1145: } |
| 704 | 1, 0, // 1149: case 0x1: { |
| 705 | OPC_SwitchField, 47, 1, // 1151: switch Inst[47] { |
| 706 | 0, 4, // 1154: case 0x0: { |
| 707 | OPC_Decode, 230, 3, 14, // 1156: decode to BRCFDir using decoder 14 |
| 708 | // 1156: } |
| 709 | 1, 0, // 1160: case 0x1: { |
| 710 | OPC_Decode, 239, 3, 15, // 1162: decode to BRCFDrr using decoder 15 |
| 711 | // 1162: } |
| 712 | // 1162: } // switch Inst[47] |
| 713 | // 1162: } |
| 714 | // 1162: } // switch Inst[39] |
| 715 | // 1162: } |
| 716 | 6, 70, // 1166: case 0x6: { |
| 717 | OPC_SwitchField, 39, 1, // 1168: switch Inst[39] { |
| 718 | 0, 48, // 1171: case 0x0: { |
| 719 | OPC_SwitchField, 47, 1, // 1173: switch Inst[47] { |
| 720 | 0, 37, // 1176: case 0x0: { |
| 721 | OPC_Scope, 31, // 1178: try { |
| 722 | OPC_SwitchField, 48, 4, // 1180: switch Inst[51:48] { |
| 723 | 0, 12, // 1183: case 0x0: { |
| 724 | OPC_CheckField, 40, 7, 0, // 1185: check Inst[46:40] == 0x0 |
| 725 | OPC_CheckField, 32, 7, 0, // 1189: check Inst[38:32] == 0x0 |
| 726 | OPC_Decode, 237, 3, 11, // 1193: decode to BRCFDna_nt using decoder 11 |
| 727 | // 1193: } |
| 728 | 15, 0, // 1197: case 0xf: { |
| 729 | OPC_CheckField, 40, 7, 0, // 1199: check Inst[46:40] == 0x0 |
| 730 | OPC_CheckField, 32, 7, 0, // 1203: check Inst[38:32] == 0x0 |
| 731 | OPC_Decode, 228, 3, 11, // 1207: decode to BRCFDa_nt using decoder 11 |
| 732 | // 1207: } |
| 733 | // 1207: } // switch Inst[51:48] |
| 734 | // 1207: } else try { |
| 735 | OPC_Decode, 234, 3, 12, // 1211: decode to BRCFDiz_nt using decoder 12 |
| 736 | // 1211: } |
| 737 | // 1211: } |
| 738 | 1, 0, // 1215: case 0x1: { |
| 739 | OPC_Decode, 243, 3, 13, // 1217: decode to BRCFDrz_nt using decoder 13 |
| 740 | // 1217: } |
| 741 | // 1217: } // switch Inst[47] |
| 742 | // 1217: } |
| 743 | 1, 0, // 1221: case 0x1: { |
| 744 | OPC_SwitchField, 47, 1, // 1223: switch Inst[47] { |
| 745 | 0, 4, // 1226: case 0x0: { |
| 746 | OPC_Decode, 231, 3, 14, // 1228: decode to BRCFDir_nt using decoder 14 |
| 747 | // 1228: } |
| 748 | 1, 0, // 1232: case 0x1: { |
| 749 | OPC_Decode, 240, 3, 15, // 1234: decode to BRCFDrr_nt using decoder 15 |
| 750 | // 1234: } |
| 751 | // 1234: } // switch Inst[47] |
| 752 | // 1234: } |
| 753 | // 1234: } // switch Inst[39] |
| 754 | // 1234: } |
| 755 | 7, 0, // 1238: case 0x7: { |
| 756 | OPC_SwitchField, 39, 1, // 1240: switch Inst[39] { |
| 757 | 0, 48, // 1243: case 0x0: { |
| 758 | OPC_SwitchField, 47, 1, // 1245: switch Inst[47] { |
| 759 | 0, 37, // 1248: case 0x0: { |
| 760 | OPC_Scope, 31, // 1250: try { |
| 761 | OPC_SwitchField, 48, 4, // 1252: switch Inst[51:48] { |
| 762 | 0, 12, // 1255: case 0x0: { |
| 763 | OPC_CheckField, 40, 7, 0, // 1257: check Inst[46:40] == 0x0 |
| 764 | OPC_CheckField, 32, 7, 0, // 1261: check Inst[38:32] == 0x0 |
| 765 | OPC_Decode, 238, 3, 11, // 1265: decode to BRCFDna_t using decoder 11 |
| 766 | // 1265: } |
| 767 | 15, 0, // 1269: case 0xf: { |
| 768 | OPC_CheckField, 40, 7, 0, // 1271: check Inst[46:40] == 0x0 |
| 769 | OPC_CheckField, 32, 7, 0, // 1275: check Inst[38:32] == 0x0 |
| 770 | OPC_Decode, 229, 3, 11, // 1279: decode to BRCFDa_t using decoder 11 |
| 771 | // 1279: } |
| 772 | // 1279: } // switch Inst[51:48] |
| 773 | // 1279: } else try { |
| 774 | OPC_Decode, 235, 3, 12, // 1283: decode to BRCFDiz_t using decoder 12 |
| 775 | // 1283: } |
| 776 | // 1283: } |
| 777 | 1, 0, // 1287: case 0x1: { |
| 778 | OPC_Decode, 244, 3, 13, // 1289: decode to BRCFDrz_t using decoder 13 |
| 779 | // 1289: } |
| 780 | // 1289: } // switch Inst[47] |
| 781 | // 1289: } |
| 782 | 1, 0, // 1293: case 0x1: { |
| 783 | OPC_SwitchField, 47, 1, // 1295: switch Inst[47] { |
| 784 | 0, 4, // 1298: case 0x0: { |
| 785 | OPC_Decode, 232, 3, 14, // 1300: decode to BRCFDir_t using decoder 14 |
| 786 | // 1300: } |
| 787 | 1, 0, // 1304: case 0x1: { |
| 788 | OPC_Decode, 241, 3, 15, // 1306: decode to BRCFDrr_t using decoder 15 |
| 789 | // 1306: } |
| 790 | // 1306: } // switch Inst[47] |
| 791 | // 1306: } |
| 792 | // 1306: } // switch Inst[39] |
| 793 | // 1306: } |
| 794 | // 1306: } // switch Inst[54:52] |
| 795 | // 1306: } |
| 796 | 49, 179, 3, // 1310: case 0x31: { |
| 797 | OPC_SwitchField, 52, 3, // 1313: switch Inst[54:52] { |
| 798 | 0, 70, // 1316: case 0x0: { |
| 799 | OPC_SwitchField, 39, 1, // 1318: switch Inst[39] { |
| 800 | 0, 48, // 1321: case 0x0: { |
| 801 | OPC_SwitchField, 47, 1, // 1323: switch Inst[47] { |
| 802 | 0, 37, // 1326: case 0x0: { |
| 803 | OPC_Scope, 31, // 1328: try { |
| 804 | OPC_SwitchField, 48, 4, // 1330: switch Inst[51:48] { |
| 805 | 0, 12, // 1333: case 0x0: { |
| 806 | OPC_CheckField, 40, 7, 0, // 1335: check Inst[46:40] == 0x0 |
| 807 | OPC_CheckField, 32, 7, 0, // 1339: check Inst[38:32] == 0x0 |
| 808 | OPC_Decode, 162, 4, 11, // 1343: decode to BRCFWna using decoder 11 |
| 809 | // 1343: } |
| 810 | 15, 0, // 1347: case 0xf: { |
| 811 | OPC_CheckField, 40, 7, 0, // 1349: check Inst[46:40] == 0x0 |
| 812 | OPC_CheckField, 32, 7, 0, // 1353: check Inst[38:32] == 0x0 |
| 813 | OPC_Decode, 153, 4, 11, // 1357: decode to BRCFWa using decoder 11 |
| 814 | // 1357: } |
| 815 | // 1357: } // switch Inst[51:48] |
| 816 | // 1357: } else try { |
| 817 | OPC_Decode, 159, 4, 12, // 1361: decode to BRCFWiz using decoder 12 |
| 818 | // 1361: } |
| 819 | // 1361: } |
| 820 | 1, 0, // 1365: case 0x1: { |
| 821 | OPC_Decode, 168, 4, 16, // 1367: decode to BRCFWrz using decoder 16 |
| 822 | // 1367: } |
| 823 | // 1367: } // switch Inst[47] |
| 824 | // 1367: } |
| 825 | 1, 0, // 1371: case 0x1: { |
| 826 | OPC_SwitchField, 47, 1, // 1373: switch Inst[47] { |
| 827 | 0, 4, // 1376: case 0x0: { |
| 828 | OPC_Decode, 156, 4, 17, // 1378: decode to BRCFWir using decoder 17 |
| 829 | // 1378: } |
| 830 | 1, 0, // 1382: case 0x1: { |
| 831 | OPC_Decode, 165, 4, 18, // 1384: decode to BRCFWrr using decoder 18 |
| 832 | // 1384: } |
| 833 | // 1384: } // switch Inst[47] |
| 834 | // 1384: } |
| 835 | // 1384: } // switch Inst[39] |
| 836 | // 1384: } |
| 837 | 2, 70, // 1388: case 0x2: { |
| 838 | OPC_SwitchField, 39, 1, // 1390: switch Inst[39] { |
| 839 | 0, 48, // 1393: case 0x0: { |
| 840 | OPC_SwitchField, 47, 1, // 1395: switch Inst[47] { |
| 841 | 0, 37, // 1398: case 0x0: { |
| 842 | OPC_Scope, 31, // 1400: try { |
| 843 | OPC_SwitchField, 48, 4, // 1402: switch Inst[51:48] { |
| 844 | 0, 12, // 1405: case 0x0: { |
| 845 | OPC_CheckField, 40, 7, 0, // 1407: check Inst[46:40] == 0x0 |
| 846 | OPC_CheckField, 32, 7, 0, // 1411: check Inst[38:32] == 0x0 |
| 847 | OPC_Decode, 163, 4, 11, // 1415: decode to BRCFWna_nt using decoder 11 |
| 848 | // 1415: } |
| 849 | 15, 0, // 1419: case 0xf: { |
| 850 | OPC_CheckField, 40, 7, 0, // 1421: check Inst[46:40] == 0x0 |
| 851 | OPC_CheckField, 32, 7, 0, // 1425: check Inst[38:32] == 0x0 |
| 852 | OPC_Decode, 154, 4, 11, // 1429: decode to BRCFWa_nt using decoder 11 |
| 853 | // 1429: } |
| 854 | // 1429: } // switch Inst[51:48] |
| 855 | // 1429: } else try { |
| 856 | OPC_Decode, 160, 4, 12, // 1433: decode to BRCFWiz_nt using decoder 12 |
| 857 | // 1433: } |
| 858 | // 1433: } |
| 859 | 1, 0, // 1437: case 0x1: { |
| 860 | OPC_Decode, 169, 4, 16, // 1439: decode to BRCFWrz_nt using decoder 16 |
| 861 | // 1439: } |
| 862 | // 1439: } // switch Inst[47] |
| 863 | // 1439: } |
| 864 | 1, 0, // 1443: case 0x1: { |
| 865 | OPC_SwitchField, 47, 1, // 1445: switch Inst[47] { |
| 866 | 0, 4, // 1448: case 0x0: { |
| 867 | OPC_Decode, 157, 4, 17, // 1450: decode to BRCFWir_nt using decoder 17 |
| 868 | // 1450: } |
| 869 | 1, 0, // 1454: case 0x1: { |
| 870 | OPC_Decode, 166, 4, 18, // 1456: decode to BRCFWrr_nt using decoder 18 |
| 871 | // 1456: } |
| 872 | // 1456: } // switch Inst[47] |
| 873 | // 1456: } |
| 874 | // 1456: } // switch Inst[39] |
| 875 | // 1456: } |
| 876 | 3, 70, // 1460: case 0x3: { |
| 877 | OPC_SwitchField, 39, 1, // 1462: switch Inst[39] { |
| 878 | 0, 48, // 1465: case 0x0: { |
| 879 | OPC_SwitchField, 47, 1, // 1467: switch Inst[47] { |
| 880 | 0, 37, // 1470: case 0x0: { |
| 881 | OPC_Scope, 31, // 1472: try { |
| 882 | OPC_SwitchField, 48, 4, // 1474: switch Inst[51:48] { |
| 883 | 0, 12, // 1477: case 0x0: { |
| 884 | OPC_CheckField, 40, 7, 0, // 1479: check Inst[46:40] == 0x0 |
| 885 | OPC_CheckField, 32, 7, 0, // 1483: check Inst[38:32] == 0x0 |
| 886 | OPC_Decode, 164, 4, 11, // 1487: decode to BRCFWna_t using decoder 11 |
| 887 | // 1487: } |
| 888 | 15, 0, // 1491: case 0xf: { |
| 889 | OPC_CheckField, 40, 7, 0, // 1493: check Inst[46:40] == 0x0 |
| 890 | OPC_CheckField, 32, 7, 0, // 1497: check Inst[38:32] == 0x0 |
| 891 | OPC_Decode, 155, 4, 11, // 1501: decode to BRCFWa_t using decoder 11 |
| 892 | // 1501: } |
| 893 | // 1501: } // switch Inst[51:48] |
| 894 | // 1501: } else try { |
| 895 | OPC_Decode, 161, 4, 12, // 1505: decode to BRCFWiz_t using decoder 12 |
| 896 | // 1505: } |
| 897 | // 1505: } |
| 898 | 1, 0, // 1509: case 0x1: { |
| 899 | OPC_Decode, 170, 4, 16, // 1511: decode to BRCFWrz_t using decoder 16 |
| 900 | // 1511: } |
| 901 | // 1511: } // switch Inst[47] |
| 902 | // 1511: } |
| 903 | 1, 0, // 1515: case 0x1: { |
| 904 | OPC_SwitchField, 47, 1, // 1517: switch Inst[47] { |
| 905 | 0, 4, // 1520: case 0x0: { |
| 906 | OPC_Decode, 158, 4, 17, // 1522: decode to BRCFWir_t using decoder 17 |
| 907 | // 1522: } |
| 908 | 1, 0, // 1526: case 0x1: { |
| 909 | OPC_Decode, 167, 4, 18, // 1528: decode to BRCFWrr_t using decoder 18 |
| 910 | // 1528: } |
| 911 | // 1528: } // switch Inst[47] |
| 912 | // 1528: } |
| 913 | // 1528: } // switch Inst[39] |
| 914 | // 1528: } |
| 915 | 4, 70, // 1532: case 0x4: { |
| 916 | OPC_SwitchField, 39, 1, // 1534: switch Inst[39] { |
| 917 | 0, 48, // 1537: case 0x0: { |
| 918 | OPC_SwitchField, 47, 1, // 1539: switch Inst[47] { |
| 919 | 0, 37, // 1542: case 0x0: { |
| 920 | OPC_Scope, 31, // 1544: try { |
| 921 | OPC_SwitchField, 48, 4, // 1546: switch Inst[51:48] { |
| 922 | 0, 12, // 1549: case 0x0: { |
| 923 | OPC_CheckField, 40, 7, 0, // 1551: check Inst[46:40] == 0x0 |
| 924 | OPC_CheckField, 32, 7, 0, // 1555: check Inst[38:32] == 0x0 |
| 925 | OPC_Decode, 144, 4, 11, // 1559: decode to BRCFSna using decoder 11 |
| 926 | // 1559: } |
| 927 | 15, 0, // 1563: case 0xf: { |
| 928 | OPC_CheckField, 40, 7, 0, // 1565: check Inst[46:40] == 0x0 |
| 929 | OPC_CheckField, 32, 7, 0, // 1569: check Inst[38:32] == 0x0 |
| 930 | OPC_Decode, 135, 4, 11, // 1573: decode to BRCFSa using decoder 11 |
| 931 | // 1573: } |
| 932 | // 1573: } // switch Inst[51:48] |
| 933 | // 1573: } else try { |
| 934 | OPC_Decode, 141, 4, 12, // 1577: decode to BRCFSiz using decoder 12 |
| 935 | // 1577: } |
| 936 | // 1577: } |
| 937 | 1, 0, // 1581: case 0x1: { |
| 938 | OPC_Decode, 150, 4, 19, // 1583: decode to BRCFSrz using decoder 19 |
| 939 | // 1583: } |
| 940 | // 1583: } // switch Inst[47] |
| 941 | // 1583: } |
| 942 | 1, 0, // 1587: case 0x1: { |
| 943 | OPC_SwitchField, 47, 1, // 1589: switch Inst[47] { |
| 944 | 0, 4, // 1592: case 0x0: { |
| 945 | OPC_Decode, 138, 4, 20, // 1594: decode to BRCFSir using decoder 20 |
| 946 | // 1594: } |
| 947 | 1, 0, // 1598: case 0x1: { |
| 948 | OPC_Decode, 147, 4, 21, // 1600: decode to BRCFSrr using decoder 21 |
| 949 | // 1600: } |
| 950 | // 1600: } // switch Inst[47] |
| 951 | // 1600: } |
| 952 | // 1600: } // switch Inst[39] |
| 953 | // 1600: } |
| 954 | 6, 70, // 1604: case 0x6: { |
| 955 | OPC_SwitchField, 39, 1, // 1606: switch Inst[39] { |
| 956 | 0, 48, // 1609: case 0x0: { |
| 957 | OPC_SwitchField, 47, 1, // 1611: switch Inst[47] { |
| 958 | 0, 37, // 1614: case 0x0: { |
| 959 | OPC_Scope, 31, // 1616: try { |
| 960 | OPC_SwitchField, 48, 4, // 1618: switch Inst[51:48] { |
| 961 | 0, 12, // 1621: case 0x0: { |
| 962 | OPC_CheckField, 40, 7, 0, // 1623: check Inst[46:40] == 0x0 |
| 963 | OPC_CheckField, 32, 7, 0, // 1627: check Inst[38:32] == 0x0 |
| 964 | OPC_Decode, 145, 4, 11, // 1631: decode to BRCFSna_nt using decoder 11 |
| 965 | // 1631: } |
| 966 | 15, 0, // 1635: case 0xf: { |
| 967 | OPC_CheckField, 40, 7, 0, // 1637: check Inst[46:40] == 0x0 |
| 968 | OPC_CheckField, 32, 7, 0, // 1641: check Inst[38:32] == 0x0 |
| 969 | OPC_Decode, 136, 4, 11, // 1645: decode to BRCFSa_nt using decoder 11 |
| 970 | // 1645: } |
| 971 | // 1645: } // switch Inst[51:48] |
| 972 | // 1645: } else try { |
| 973 | OPC_Decode, 142, 4, 12, // 1649: decode to BRCFSiz_nt using decoder 12 |
| 974 | // 1649: } |
| 975 | // 1649: } |
| 976 | 1, 0, // 1653: case 0x1: { |
| 977 | OPC_Decode, 151, 4, 19, // 1655: decode to BRCFSrz_nt using decoder 19 |
| 978 | // 1655: } |
| 979 | // 1655: } // switch Inst[47] |
| 980 | // 1655: } |
| 981 | 1, 0, // 1659: case 0x1: { |
| 982 | OPC_SwitchField, 47, 1, // 1661: switch Inst[47] { |
| 983 | 0, 4, // 1664: case 0x0: { |
| 984 | OPC_Decode, 139, 4, 20, // 1666: decode to BRCFSir_nt using decoder 20 |
| 985 | // 1666: } |
| 986 | 1, 0, // 1670: case 0x1: { |
| 987 | OPC_Decode, 148, 4, 21, // 1672: decode to BRCFSrr_nt using decoder 21 |
| 988 | // 1672: } |
| 989 | // 1672: } // switch Inst[47] |
| 990 | // 1672: } |
| 991 | // 1672: } // switch Inst[39] |
| 992 | // 1672: } |
| 993 | 7, 0, // 1676: case 0x7: { |
| 994 | OPC_SwitchField, 39, 1, // 1678: switch Inst[39] { |
| 995 | 0, 48, // 1681: case 0x0: { |
| 996 | OPC_SwitchField, 47, 1, // 1683: switch Inst[47] { |
| 997 | 0, 37, // 1686: case 0x0: { |
| 998 | OPC_Scope, 31, // 1688: try { |
| 999 | OPC_SwitchField, 48, 4, // 1690: switch Inst[51:48] { |
| 1000 | 0, 12, // 1693: case 0x0: { |
| 1001 | OPC_CheckField, 40, 7, 0, // 1695: check Inst[46:40] == 0x0 |
| 1002 | OPC_CheckField, 32, 7, 0, // 1699: check Inst[38:32] == 0x0 |
| 1003 | OPC_Decode, 146, 4, 11, // 1703: decode to BRCFSna_t using decoder 11 |
| 1004 | // 1703: } |
| 1005 | 15, 0, // 1707: case 0xf: { |
| 1006 | OPC_CheckField, 40, 7, 0, // 1709: check Inst[46:40] == 0x0 |
| 1007 | OPC_CheckField, 32, 7, 0, // 1713: check Inst[38:32] == 0x0 |
| 1008 | OPC_Decode, 137, 4, 11, // 1717: decode to BRCFSa_t using decoder 11 |
| 1009 | // 1717: } |
| 1010 | // 1717: } // switch Inst[51:48] |
| 1011 | // 1717: } else try { |
| 1012 | OPC_Decode, 143, 4, 12, // 1721: decode to BRCFSiz_t using decoder 12 |
| 1013 | // 1721: } |
| 1014 | // 1721: } |
| 1015 | 1, 0, // 1725: case 0x1: { |
| 1016 | OPC_Decode, 152, 4, 19, // 1727: decode to BRCFSrz_t using decoder 19 |
| 1017 | // 1727: } |
| 1018 | // 1727: } // switch Inst[47] |
| 1019 | // 1727: } |
| 1020 | 1, 0, // 1731: case 0x1: { |
| 1021 | OPC_SwitchField, 47, 1, // 1733: switch Inst[47] { |
| 1022 | 0, 4, // 1736: case 0x0: { |
| 1023 | OPC_Decode, 140, 4, 20, // 1738: decode to BRCFSir_t using decoder 20 |
| 1024 | // 1738: } |
| 1025 | 1, 0, // 1742: case 0x1: { |
| 1026 | OPC_Decode, 149, 4, 21, // 1744: decode to BRCFSrr_t using decoder 21 |
| 1027 | // 1744: } |
| 1028 | // 1744: } // switch Inst[47] |
| 1029 | // 1744: } |
| 1030 | // 1744: } // switch Inst[39] |
| 1031 | // 1744: } |
| 1032 | // 1744: } // switch Inst[54:52] |
| 1033 | // 1744: } |
| 1034 | 50, 142, 2, // 1748: case 0x32: { |
| 1035 | OPC_SwitchField, 52, 3, // 1751: switch Inst[54:52] { |
| 1036 | 0, 87, // 1754: case 0x0: { |
| 1037 | OPC_SwitchField, 39, 1, // 1756: switch Inst[39] { |
| 1038 | 0, 40, // 1759: case 0x0: { |
| 1039 | OPC_SwitchField, 47, 1, // 1761: switch Inst[47] { |
| 1040 | 0, 29, // 1764: case 0x0: { |
| 1041 | OPC_Scope, 23, // 1766: try { |
| 1042 | OPC_SwitchField, 48, 4, // 1768: switch Inst[51:48] { |
| 1043 | 0, 8, // 1771: case 0x0: { |
| 1044 | OPC_CheckField, 40, 7, 0, // 1773: check Inst[46:40] == 0x0 |
| 1045 | OPC_Decode, 170, 3, 22, // 1777: decode to BCFLnazi using decoder 22 |
| 1046 | // 1777: } |
| 1047 | 15, 0, // 1781: case 0xf: { |
| 1048 | OPC_CheckField, 40, 7, 0, // 1783: check Inst[46:40] == 0x0 |
| 1049 | OPC_Decode, 158, 3, 22, // 1787: decode to BCFLazi using decoder 22 |
| 1050 | // 1787: } |
| 1051 | // 1787: } // switch Inst[51:48] |
| 1052 | // 1787: } else try { |
| 1053 | OPC_Decode, 164, 3, 23, // 1791: decode to BCFLizi using decoder 23 |
| 1054 | // 1791: } |
| 1055 | // 1791: } |
| 1056 | 1, 0, // 1795: case 0x1: { |
| 1057 | OPC_Decode, 176, 3, 23, // 1797: decode to BCFLrzi using decoder 23 |
| 1058 | // 1797: } |
| 1059 | // 1797: } // switch Inst[47] |
| 1060 | // 1797: } |
| 1061 | 1, 0, // 1801: case 0x1: { |
| 1062 | OPC_SwitchField, 47, 1, // 1803: switch Inst[47] { |
| 1063 | 0, 29, // 1806: case 0x0: { |
| 1064 | OPC_Scope, 23, // 1808: try { |
| 1065 | OPC_SwitchField, 48, 4, // 1810: switch Inst[51:48] { |
| 1066 | 0, 8, // 1813: case 0x0: { |
| 1067 | OPC_CheckField, 40, 7, 0, // 1815: check Inst[46:40] == 0x0 |
| 1068 | OPC_Decode, 167, 3, 22, // 1819: decode to BCFLnari using decoder 22 |
| 1069 | // 1819: } |
| 1070 | 15, 0, // 1823: case 0xf: { |
| 1071 | OPC_CheckField, 40, 7, 0, // 1825: check Inst[46:40] == 0x0 |
| 1072 | OPC_Decode, 155, 3, 22, // 1829: decode to BCFLari using decoder 22 |
| 1073 | // 1829: } |
| 1074 | // 1829: } // switch Inst[51:48] |
| 1075 | // 1829: } else try { |
| 1076 | OPC_Decode, 161, 3, 23, // 1833: decode to BCFLiri using decoder 23 |
| 1077 | // 1833: } |
| 1078 | // 1833: } |
| 1079 | 1, 0, // 1837: case 0x1: { |
| 1080 | OPC_Decode, 173, 3, 23, // 1839: decode to BCFLrri using decoder 23 |
| 1081 | // 1839: } |
| 1082 | // 1839: } // switch Inst[47] |
| 1083 | // 1839: } |
| 1084 | // 1839: } // switch Inst[39] |
| 1085 | // 1839: } |
| 1086 | 2, 87, // 1843: case 0x2: { |
| 1087 | OPC_SwitchField, 39, 1, // 1845: switch Inst[39] { |
| 1088 | 0, 40, // 1848: case 0x0: { |
| 1089 | OPC_SwitchField, 47, 1, // 1850: switch Inst[47] { |
| 1090 | 0, 29, // 1853: case 0x0: { |
| 1091 | OPC_Scope, 23, // 1855: try { |
| 1092 | OPC_SwitchField, 48, 4, // 1857: switch Inst[51:48] { |
| 1093 | 0, 8, // 1860: case 0x0: { |
| 1094 | OPC_CheckField, 40, 7, 0, // 1862: check Inst[46:40] == 0x0 |
| 1095 | OPC_Decode, 171, 3, 22, // 1866: decode to BCFLnazi_nt using decoder 22 |
| 1096 | // 1866: } |
| 1097 | 15, 0, // 1870: case 0xf: { |
| 1098 | OPC_CheckField, 40, 7, 0, // 1872: check Inst[46:40] == 0x0 |
| 1099 | OPC_Decode, 159, 3, 22, // 1876: decode to BCFLazi_nt using decoder 22 |
| 1100 | // 1876: } |
| 1101 | // 1876: } // switch Inst[51:48] |
| 1102 | // 1876: } else try { |
| 1103 | OPC_Decode, 165, 3, 23, // 1880: decode to BCFLizi_nt using decoder 23 |
| 1104 | // 1880: } |
| 1105 | // 1880: } |
| 1106 | 1, 0, // 1884: case 0x1: { |
| 1107 | OPC_Decode, 177, 3, 23, // 1886: decode to BCFLrzi_nt using decoder 23 |
| 1108 | // 1886: } |
| 1109 | // 1886: } // switch Inst[47] |
| 1110 | // 1886: } |
| 1111 | 1, 0, // 1890: case 0x1: { |
| 1112 | OPC_SwitchField, 47, 1, // 1892: switch Inst[47] { |
| 1113 | 0, 29, // 1895: case 0x0: { |
| 1114 | OPC_Scope, 23, // 1897: try { |
| 1115 | OPC_SwitchField, 48, 4, // 1899: switch Inst[51:48] { |
| 1116 | 0, 8, // 1902: case 0x0: { |
| 1117 | OPC_CheckField, 40, 7, 0, // 1904: check Inst[46:40] == 0x0 |
| 1118 | OPC_Decode, 168, 3, 22, // 1908: decode to BCFLnari_nt using decoder 22 |
| 1119 | // 1908: } |
| 1120 | 15, 0, // 1912: case 0xf: { |
| 1121 | OPC_CheckField, 40, 7, 0, // 1914: check Inst[46:40] == 0x0 |
| 1122 | OPC_Decode, 156, 3, 22, // 1918: decode to BCFLari_nt using decoder 22 |
| 1123 | // 1918: } |
| 1124 | // 1918: } // switch Inst[51:48] |
| 1125 | // 1918: } else try { |
| 1126 | OPC_Decode, 162, 3, 23, // 1922: decode to BCFLiri_nt using decoder 23 |
| 1127 | // 1922: } |
| 1128 | // 1922: } |
| 1129 | 1, 0, // 1926: case 0x1: { |
| 1130 | OPC_Decode, 174, 3, 23, // 1928: decode to BCFLrri_nt using decoder 23 |
| 1131 | // 1928: } |
| 1132 | // 1928: } // switch Inst[47] |
| 1133 | // 1928: } |
| 1134 | // 1928: } // switch Inst[39] |
| 1135 | // 1928: } |
| 1136 | 3, 0, // 1932: case 0x3: { |
| 1137 | OPC_SwitchField, 39, 1, // 1934: switch Inst[39] { |
| 1138 | 0, 40, // 1937: case 0x0: { |
| 1139 | OPC_SwitchField, 47, 1, // 1939: switch Inst[47] { |
| 1140 | 0, 29, // 1942: case 0x0: { |
| 1141 | OPC_Scope, 23, // 1944: try { |
| 1142 | OPC_SwitchField, 48, 4, // 1946: switch Inst[51:48] { |
| 1143 | 0, 8, // 1949: case 0x0: { |
| 1144 | OPC_CheckField, 40, 7, 0, // 1951: check Inst[46:40] == 0x0 |
| 1145 | OPC_Decode, 172, 3, 22, // 1955: decode to BCFLnazi_t using decoder 22 |
| 1146 | // 1955: } |
| 1147 | 15, 0, // 1959: case 0xf: { |
| 1148 | OPC_CheckField, 40, 7, 0, // 1961: check Inst[46:40] == 0x0 |
| 1149 | OPC_Decode, 160, 3, 22, // 1965: decode to BCFLazi_t using decoder 22 |
| 1150 | // 1965: } |
| 1151 | // 1965: } // switch Inst[51:48] |
| 1152 | // 1965: } else try { |
| 1153 | OPC_Decode, 166, 3, 23, // 1969: decode to BCFLizi_t using decoder 23 |
| 1154 | // 1969: } |
| 1155 | // 1969: } |
| 1156 | 1, 0, // 1973: case 0x1: { |
| 1157 | OPC_Decode, 178, 3, 23, // 1975: decode to BCFLrzi_t using decoder 23 |
| 1158 | // 1975: } |
| 1159 | // 1975: } // switch Inst[47] |
| 1160 | // 1975: } |
| 1161 | 1, 0, // 1979: case 0x1: { |
| 1162 | OPC_SwitchField, 47, 1, // 1981: switch Inst[47] { |
| 1163 | 0, 29, // 1984: case 0x0: { |
| 1164 | OPC_Scope, 23, // 1986: try { |
| 1165 | OPC_SwitchField, 48, 4, // 1988: switch Inst[51:48] { |
| 1166 | 0, 8, // 1991: case 0x0: { |
| 1167 | OPC_CheckField, 40, 7, 0, // 1993: check Inst[46:40] == 0x0 |
| 1168 | OPC_Decode, 169, 3, 22, // 1997: decode to BCFLnari_t using decoder 22 |
| 1169 | // 1997: } |
| 1170 | 15, 0, // 2001: case 0xf: { |
| 1171 | OPC_CheckField, 40, 7, 0, // 2003: check Inst[46:40] == 0x0 |
| 1172 | OPC_Decode, 157, 3, 22, // 2007: decode to BCFLari_t using decoder 22 |
| 1173 | // 2007: } |
| 1174 | // 2007: } // switch Inst[51:48] |
| 1175 | // 2007: } else try { |
| 1176 | OPC_Decode, 163, 3, 23, // 2011: decode to BCFLiri_t using decoder 23 |
| 1177 | // 2011: } |
| 1178 | // 2011: } |
| 1179 | 1, 0, // 2015: case 0x1: { |
| 1180 | OPC_Decode, 175, 3, 23, // 2017: decode to BCFLrri_t using decoder 23 |
| 1181 | // 2017: } |
| 1182 | // 2017: } // switch Inst[47] |
| 1183 | // 2017: } |
| 1184 | // 2017: } // switch Inst[39] |
| 1185 | // 2017: } |
| 1186 | // 2017: } // switch Inst[54:52] |
| 1187 | // 2017: } |
| 1188 | 54, 142, 2, // 2021: case 0x36: { |
| 1189 | OPC_SwitchField, 52, 3, // 2024: switch Inst[54:52] { |
| 1190 | 0, 87, // 2027: case 0x0: { |
| 1191 | OPC_SwitchField, 39, 1, // 2029: switch Inst[39] { |
| 1192 | 0, 40, // 2032: case 0x0: { |
| 1193 | OPC_SwitchField, 47, 1, // 2034: switch Inst[47] { |
| 1194 | 0, 29, // 2037: case 0x0: { |
| 1195 | OPC_Scope, 23, // 2039: try { |
| 1196 | OPC_SwitchField, 48, 4, // 2041: switch Inst[51:48] { |
| 1197 | 0, 8, // 2044: case 0x0: { |
| 1198 | OPC_CheckField, 40, 7, 0, // 2046: check Inst[46:40] == 0x0 |
| 1199 | OPC_Decode, 218, 3, 22, // 2050: decode to BCFWnazi using decoder 22 |
| 1200 | // 2050: } |
| 1201 | 15, 0, // 2054: case 0xf: { |
| 1202 | OPC_CheckField, 40, 7, 0, // 2056: check Inst[46:40] == 0x0 |
| 1203 | OPC_Decode, 206, 3, 22, // 2060: decode to BCFWazi using decoder 22 |
| 1204 | // 2060: } |
| 1205 | // 2060: } // switch Inst[51:48] |
| 1206 | // 2060: } else try { |
| 1207 | OPC_Decode, 212, 3, 23, // 2064: decode to BCFWizi using decoder 23 |
| 1208 | // 2064: } |
| 1209 | // 2064: } |
| 1210 | 1, 0, // 2068: case 0x1: { |
| 1211 | OPC_Decode, 224, 3, 23, // 2070: decode to BCFWrzi using decoder 23 |
| 1212 | // 2070: } |
| 1213 | // 2070: } // switch Inst[47] |
| 1214 | // 2070: } |
| 1215 | 1, 0, // 2074: case 0x1: { |
| 1216 | OPC_SwitchField, 47, 1, // 2076: switch Inst[47] { |
| 1217 | 0, 29, // 2079: case 0x0: { |
| 1218 | OPC_Scope, 23, // 2081: try { |
| 1219 | OPC_SwitchField, 48, 4, // 2083: switch Inst[51:48] { |
| 1220 | 0, 8, // 2086: case 0x0: { |
| 1221 | OPC_CheckField, 40, 7, 0, // 2088: check Inst[46:40] == 0x0 |
| 1222 | OPC_Decode, 215, 3, 22, // 2092: decode to BCFWnari using decoder 22 |
| 1223 | // 2092: } |
| 1224 | 15, 0, // 2096: case 0xf: { |
| 1225 | OPC_CheckField, 40, 7, 0, // 2098: check Inst[46:40] == 0x0 |
| 1226 | OPC_Decode, 203, 3, 22, // 2102: decode to BCFWari using decoder 22 |
| 1227 | // 2102: } |
| 1228 | // 2102: } // switch Inst[51:48] |
| 1229 | // 2102: } else try { |
| 1230 | OPC_Decode, 209, 3, 23, // 2106: decode to BCFWiri using decoder 23 |
| 1231 | // 2106: } |
| 1232 | // 2106: } |
| 1233 | 1, 0, // 2110: case 0x1: { |
| 1234 | OPC_Decode, 221, 3, 23, // 2112: decode to BCFWrri using decoder 23 |
| 1235 | // 2112: } |
| 1236 | // 2112: } // switch Inst[47] |
| 1237 | // 2112: } |
| 1238 | // 2112: } // switch Inst[39] |
| 1239 | // 2112: } |
| 1240 | 2, 87, // 2116: case 0x2: { |
| 1241 | OPC_SwitchField, 39, 1, // 2118: switch Inst[39] { |
| 1242 | 0, 40, // 2121: case 0x0: { |
| 1243 | OPC_SwitchField, 47, 1, // 2123: switch Inst[47] { |
| 1244 | 0, 29, // 2126: case 0x0: { |
| 1245 | OPC_Scope, 23, // 2128: try { |
| 1246 | OPC_SwitchField, 48, 4, // 2130: switch Inst[51:48] { |
| 1247 | 0, 8, // 2133: case 0x0: { |
| 1248 | OPC_CheckField, 40, 7, 0, // 2135: check Inst[46:40] == 0x0 |
| 1249 | OPC_Decode, 219, 3, 22, // 2139: decode to BCFWnazi_nt using decoder 22 |
| 1250 | // 2139: } |
| 1251 | 15, 0, // 2143: case 0xf: { |
| 1252 | OPC_CheckField, 40, 7, 0, // 2145: check Inst[46:40] == 0x0 |
| 1253 | OPC_Decode, 207, 3, 22, // 2149: decode to BCFWazi_nt using decoder 22 |
| 1254 | // 2149: } |
| 1255 | // 2149: } // switch Inst[51:48] |
| 1256 | // 2149: } else try { |
| 1257 | OPC_Decode, 213, 3, 23, // 2153: decode to BCFWizi_nt using decoder 23 |
| 1258 | // 2153: } |
| 1259 | // 2153: } |
| 1260 | 1, 0, // 2157: case 0x1: { |
| 1261 | OPC_Decode, 225, 3, 23, // 2159: decode to BCFWrzi_nt using decoder 23 |
| 1262 | // 2159: } |
| 1263 | // 2159: } // switch Inst[47] |
| 1264 | // 2159: } |
| 1265 | 1, 0, // 2163: case 0x1: { |
| 1266 | OPC_SwitchField, 47, 1, // 2165: switch Inst[47] { |
| 1267 | 0, 29, // 2168: case 0x0: { |
| 1268 | OPC_Scope, 23, // 2170: try { |
| 1269 | OPC_SwitchField, 48, 4, // 2172: switch Inst[51:48] { |
| 1270 | 0, 8, // 2175: case 0x0: { |
| 1271 | OPC_CheckField, 40, 7, 0, // 2177: check Inst[46:40] == 0x0 |
| 1272 | OPC_Decode, 216, 3, 22, // 2181: decode to BCFWnari_nt using decoder 22 |
| 1273 | // 2181: } |
| 1274 | 15, 0, // 2185: case 0xf: { |
| 1275 | OPC_CheckField, 40, 7, 0, // 2187: check Inst[46:40] == 0x0 |
| 1276 | OPC_Decode, 204, 3, 22, // 2191: decode to BCFWari_nt using decoder 22 |
| 1277 | // 2191: } |
| 1278 | // 2191: } // switch Inst[51:48] |
| 1279 | // 2191: } else try { |
| 1280 | OPC_Decode, 210, 3, 23, // 2195: decode to BCFWiri_nt using decoder 23 |
| 1281 | // 2195: } |
| 1282 | // 2195: } |
| 1283 | 1, 0, // 2199: case 0x1: { |
| 1284 | OPC_Decode, 222, 3, 23, // 2201: decode to BCFWrri_nt using decoder 23 |
| 1285 | // 2201: } |
| 1286 | // 2201: } // switch Inst[47] |
| 1287 | // 2201: } |
| 1288 | // 2201: } // switch Inst[39] |
| 1289 | // 2201: } |
| 1290 | 3, 0, // 2205: case 0x3: { |
| 1291 | OPC_SwitchField, 39, 1, // 2207: switch Inst[39] { |
| 1292 | 0, 40, // 2210: case 0x0: { |
| 1293 | OPC_SwitchField, 47, 1, // 2212: switch Inst[47] { |
| 1294 | 0, 29, // 2215: case 0x0: { |
| 1295 | OPC_Scope, 23, // 2217: try { |
| 1296 | OPC_SwitchField, 48, 4, // 2219: switch Inst[51:48] { |
| 1297 | 0, 8, // 2222: case 0x0: { |
| 1298 | OPC_CheckField, 40, 7, 0, // 2224: check Inst[46:40] == 0x0 |
| 1299 | OPC_Decode, 220, 3, 22, // 2228: decode to BCFWnazi_t using decoder 22 |
| 1300 | // 2228: } |
| 1301 | 15, 0, // 2232: case 0xf: { |
| 1302 | OPC_CheckField, 40, 7, 0, // 2234: check Inst[46:40] == 0x0 |
| 1303 | OPC_Decode, 208, 3, 22, // 2238: decode to BCFWazi_t using decoder 22 |
| 1304 | // 2238: } |
| 1305 | // 2238: } // switch Inst[51:48] |
| 1306 | // 2238: } else try { |
| 1307 | OPC_Decode, 214, 3, 23, // 2242: decode to BCFWizi_t using decoder 23 |
| 1308 | // 2242: } |
| 1309 | // 2242: } |
| 1310 | 1, 0, // 2246: case 0x1: { |
| 1311 | OPC_Decode, 226, 3, 23, // 2248: decode to BCFWrzi_t using decoder 23 |
| 1312 | // 2248: } |
| 1313 | // 2248: } // switch Inst[47] |
| 1314 | // 2248: } |
| 1315 | 1, 0, // 2252: case 0x1: { |
| 1316 | OPC_SwitchField, 47, 1, // 2254: switch Inst[47] { |
| 1317 | 0, 29, // 2257: case 0x0: { |
| 1318 | OPC_Scope, 23, // 2259: try { |
| 1319 | OPC_SwitchField, 48, 4, // 2261: switch Inst[51:48] { |
| 1320 | 0, 8, // 2264: case 0x0: { |
| 1321 | OPC_CheckField, 40, 7, 0, // 2266: check Inst[46:40] == 0x0 |
| 1322 | OPC_Decode, 217, 3, 22, // 2270: decode to BCFWnari_t using decoder 22 |
| 1323 | // 2270: } |
| 1324 | 15, 0, // 2274: case 0xf: { |
| 1325 | OPC_CheckField, 40, 7, 0, // 2276: check Inst[46:40] == 0x0 |
| 1326 | OPC_Decode, 205, 3, 22, // 2280: decode to BCFWari_t using decoder 22 |
| 1327 | // 2280: } |
| 1328 | // 2280: } // switch Inst[51:48] |
| 1329 | // 2280: } else try { |
| 1330 | OPC_Decode, 211, 3, 23, // 2284: decode to BCFWiri_t using decoder 23 |
| 1331 | // 2284: } |
| 1332 | // 2284: } |
| 1333 | 1, 0, // 2288: case 0x1: { |
| 1334 | OPC_Decode, 223, 3, 23, // 2290: decode to BCFWrri_t using decoder 23 |
| 1335 | // 2290: } |
| 1336 | // 2290: } // switch Inst[47] |
| 1337 | // 2290: } |
| 1338 | // 2290: } // switch Inst[39] |
| 1339 | // 2290: } |
| 1340 | // 2290: } // switch Inst[54:52] |
| 1341 | // 2290: } |
| 1342 | 56, 142, 2, // 2294: case 0x38: { |
| 1343 | OPC_SwitchField, 52, 3, // 2297: switch Inst[54:52] { |
| 1344 | 0, 87, // 2300: case 0x0: { |
| 1345 | OPC_SwitchField, 39, 1, // 2302: switch Inst[39] { |
| 1346 | 0, 40, // 2305: case 0x0: { |
| 1347 | OPC_SwitchField, 47, 1, // 2307: switch Inst[47] { |
| 1348 | 0, 29, // 2310: case 0x0: { |
| 1349 | OPC_Scope, 23, // 2312: try { |
| 1350 | OPC_SwitchField, 48, 4, // 2314: switch Inst[51:48] { |
| 1351 | 0, 8, // 2317: case 0x0: { |
| 1352 | OPC_CheckField, 40, 7, 0, // 2319: check Inst[46:40] == 0x0 |
| 1353 | OPC_Decode, 146, 3, 22, // 2323: decode to BCFDnazi using decoder 22 |
| 1354 | // 2323: } |
| 1355 | 15, 0, // 2327: case 0xf: { |
| 1356 | OPC_CheckField, 40, 7, 0, // 2329: check Inst[46:40] == 0x0 |
| 1357 | OPC_Decode, 134, 3, 22, // 2333: decode to BCFDazi using decoder 22 |
| 1358 | // 2333: } |
| 1359 | // 2333: } // switch Inst[51:48] |
| 1360 | // 2333: } else try { |
| 1361 | OPC_Decode, 140, 3, 23, // 2337: decode to BCFDizi using decoder 23 |
| 1362 | // 2337: } |
| 1363 | // 2337: } |
| 1364 | 1, 0, // 2341: case 0x1: { |
| 1365 | OPC_Decode, 152, 3, 23, // 2343: decode to BCFDrzi using decoder 23 |
| 1366 | // 2343: } |
| 1367 | // 2343: } // switch Inst[47] |
| 1368 | // 2343: } |
| 1369 | 1, 0, // 2347: case 0x1: { |
| 1370 | OPC_SwitchField, 47, 1, // 2349: switch Inst[47] { |
| 1371 | 0, 29, // 2352: case 0x0: { |
| 1372 | OPC_Scope, 23, // 2354: try { |
| 1373 | OPC_SwitchField, 48, 4, // 2356: switch Inst[51:48] { |
| 1374 | 0, 8, // 2359: case 0x0: { |
| 1375 | OPC_CheckField, 40, 7, 0, // 2361: check Inst[46:40] == 0x0 |
| 1376 | OPC_Decode, 143, 3, 22, // 2365: decode to BCFDnari using decoder 22 |
| 1377 | // 2365: } |
| 1378 | 15, 0, // 2369: case 0xf: { |
| 1379 | OPC_CheckField, 40, 7, 0, // 2371: check Inst[46:40] == 0x0 |
| 1380 | OPC_Decode, 131, 3, 22, // 2375: decode to BCFDari using decoder 22 |
| 1381 | // 2375: } |
| 1382 | // 2375: } // switch Inst[51:48] |
| 1383 | // 2375: } else try { |
| 1384 | OPC_Decode, 137, 3, 23, // 2379: decode to BCFDiri using decoder 23 |
| 1385 | // 2379: } |
| 1386 | // 2379: } |
| 1387 | 1, 0, // 2383: case 0x1: { |
| 1388 | OPC_Decode, 149, 3, 23, // 2385: decode to BCFDrri using decoder 23 |
| 1389 | // 2385: } |
| 1390 | // 2385: } // switch Inst[47] |
| 1391 | // 2385: } |
| 1392 | // 2385: } // switch Inst[39] |
| 1393 | // 2385: } |
| 1394 | 2, 87, // 2389: case 0x2: { |
| 1395 | OPC_SwitchField, 39, 1, // 2391: switch Inst[39] { |
| 1396 | 0, 40, // 2394: case 0x0: { |
| 1397 | OPC_SwitchField, 47, 1, // 2396: switch Inst[47] { |
| 1398 | 0, 29, // 2399: case 0x0: { |
| 1399 | OPC_Scope, 23, // 2401: try { |
| 1400 | OPC_SwitchField, 48, 4, // 2403: switch Inst[51:48] { |
| 1401 | 0, 8, // 2406: case 0x0: { |
| 1402 | OPC_CheckField, 40, 7, 0, // 2408: check Inst[46:40] == 0x0 |
| 1403 | OPC_Decode, 147, 3, 22, // 2412: decode to BCFDnazi_nt using decoder 22 |
| 1404 | // 2412: } |
| 1405 | 15, 0, // 2416: case 0xf: { |
| 1406 | OPC_CheckField, 40, 7, 0, // 2418: check Inst[46:40] == 0x0 |
| 1407 | OPC_Decode, 135, 3, 22, // 2422: decode to BCFDazi_nt using decoder 22 |
| 1408 | // 2422: } |
| 1409 | // 2422: } // switch Inst[51:48] |
| 1410 | // 2422: } else try { |
| 1411 | OPC_Decode, 141, 3, 23, // 2426: decode to BCFDizi_nt using decoder 23 |
| 1412 | // 2426: } |
| 1413 | // 2426: } |
| 1414 | 1, 0, // 2430: case 0x1: { |
| 1415 | OPC_Decode, 153, 3, 23, // 2432: decode to BCFDrzi_nt using decoder 23 |
| 1416 | // 2432: } |
| 1417 | // 2432: } // switch Inst[47] |
| 1418 | // 2432: } |
| 1419 | 1, 0, // 2436: case 0x1: { |
| 1420 | OPC_SwitchField, 47, 1, // 2438: switch Inst[47] { |
| 1421 | 0, 29, // 2441: case 0x0: { |
| 1422 | OPC_Scope, 23, // 2443: try { |
| 1423 | OPC_SwitchField, 48, 4, // 2445: switch Inst[51:48] { |
| 1424 | 0, 8, // 2448: case 0x0: { |
| 1425 | OPC_CheckField, 40, 7, 0, // 2450: check Inst[46:40] == 0x0 |
| 1426 | OPC_Decode, 144, 3, 22, // 2454: decode to BCFDnari_nt using decoder 22 |
| 1427 | // 2454: } |
| 1428 | 15, 0, // 2458: case 0xf: { |
| 1429 | OPC_CheckField, 40, 7, 0, // 2460: check Inst[46:40] == 0x0 |
| 1430 | OPC_Decode, 132, 3, 22, // 2464: decode to BCFDari_nt using decoder 22 |
| 1431 | // 2464: } |
| 1432 | // 2464: } // switch Inst[51:48] |
| 1433 | // 2464: } else try { |
| 1434 | OPC_Decode, 138, 3, 23, // 2468: decode to BCFDiri_nt using decoder 23 |
| 1435 | // 2468: } |
| 1436 | // 2468: } |
| 1437 | 1, 0, // 2472: case 0x1: { |
| 1438 | OPC_Decode, 150, 3, 23, // 2474: decode to BCFDrri_nt using decoder 23 |
| 1439 | // 2474: } |
| 1440 | // 2474: } // switch Inst[47] |
| 1441 | // 2474: } |
| 1442 | // 2474: } // switch Inst[39] |
| 1443 | // 2474: } |
| 1444 | 3, 0, // 2478: case 0x3: { |
| 1445 | OPC_SwitchField, 39, 1, // 2480: switch Inst[39] { |
| 1446 | 0, 40, // 2483: case 0x0: { |
| 1447 | OPC_SwitchField, 47, 1, // 2485: switch Inst[47] { |
| 1448 | 0, 29, // 2488: case 0x0: { |
| 1449 | OPC_Scope, 23, // 2490: try { |
| 1450 | OPC_SwitchField, 48, 4, // 2492: switch Inst[51:48] { |
| 1451 | 0, 8, // 2495: case 0x0: { |
| 1452 | OPC_CheckField, 40, 7, 0, // 2497: check Inst[46:40] == 0x0 |
| 1453 | OPC_Decode, 148, 3, 22, // 2501: decode to BCFDnazi_t using decoder 22 |
| 1454 | // 2501: } |
| 1455 | 15, 0, // 2505: case 0xf: { |
| 1456 | OPC_CheckField, 40, 7, 0, // 2507: check Inst[46:40] == 0x0 |
| 1457 | OPC_Decode, 136, 3, 22, // 2511: decode to BCFDazi_t using decoder 22 |
| 1458 | // 2511: } |
| 1459 | // 2511: } // switch Inst[51:48] |
| 1460 | // 2511: } else try { |
| 1461 | OPC_Decode, 142, 3, 23, // 2515: decode to BCFDizi_t using decoder 23 |
| 1462 | // 2515: } |
| 1463 | // 2515: } |
| 1464 | 1, 0, // 2519: case 0x1: { |
| 1465 | OPC_Decode, 154, 3, 23, // 2521: decode to BCFDrzi_t using decoder 23 |
| 1466 | // 2521: } |
| 1467 | // 2521: } // switch Inst[47] |
| 1468 | // 2521: } |
| 1469 | 1, 0, // 2525: case 0x1: { |
| 1470 | OPC_SwitchField, 47, 1, // 2527: switch Inst[47] { |
| 1471 | 0, 29, // 2530: case 0x0: { |
| 1472 | OPC_Scope, 23, // 2532: try { |
| 1473 | OPC_SwitchField, 48, 4, // 2534: switch Inst[51:48] { |
| 1474 | 0, 8, // 2537: case 0x0: { |
| 1475 | OPC_CheckField, 40, 7, 0, // 2539: check Inst[46:40] == 0x0 |
| 1476 | OPC_Decode, 145, 3, 22, // 2543: decode to BCFDnari_t using decoder 22 |
| 1477 | // 2543: } |
| 1478 | 15, 0, // 2547: case 0xf: { |
| 1479 | OPC_CheckField, 40, 7, 0, // 2549: check Inst[46:40] == 0x0 |
| 1480 | OPC_Decode, 133, 3, 22, // 2553: decode to BCFDari_t using decoder 22 |
| 1481 | // 2553: } |
| 1482 | // 2553: } // switch Inst[51:48] |
| 1483 | // 2553: } else try { |
| 1484 | OPC_Decode, 139, 3, 23, // 2557: decode to BCFDiri_t using decoder 23 |
| 1485 | // 2557: } |
| 1486 | // 2557: } |
| 1487 | 1, 0, // 2561: case 0x1: { |
| 1488 | OPC_Decode, 151, 3, 23, // 2563: decode to BCFDrri_t using decoder 23 |
| 1489 | // 2563: } |
| 1490 | // 2563: } // switch Inst[47] |
| 1491 | // 2563: } |
| 1492 | // 2563: } // switch Inst[39] |
| 1493 | // 2563: } |
| 1494 | // 2563: } // switch Inst[54:52] |
| 1495 | // 2563: } |
| 1496 | 57, 142, 2, // 2567: case 0x39: { |
| 1497 | OPC_SwitchField, 52, 3, // 2570: switch Inst[54:52] { |
| 1498 | 0, 87, // 2573: case 0x0: { |
| 1499 | OPC_SwitchField, 39, 1, // 2575: switch Inst[39] { |
| 1500 | 0, 40, // 2578: case 0x0: { |
| 1501 | OPC_SwitchField, 47, 1, // 2580: switch Inst[47] { |
| 1502 | 0, 29, // 2583: case 0x0: { |
| 1503 | OPC_Scope, 23, // 2585: try { |
| 1504 | OPC_SwitchField, 48, 4, // 2587: switch Inst[51:48] { |
| 1505 | 0, 8, // 2590: case 0x0: { |
| 1506 | OPC_CheckField, 40, 7, 0, // 2592: check Inst[46:40] == 0x0 |
| 1507 | OPC_Decode, 194, 3, 22, // 2596: decode to BCFSnazi using decoder 22 |
| 1508 | // 2596: } |
| 1509 | 15, 0, // 2600: case 0xf: { |
| 1510 | OPC_CheckField, 40, 7, 0, // 2602: check Inst[46:40] == 0x0 |
| 1511 | OPC_Decode, 182, 3, 22, // 2606: decode to BCFSazi using decoder 22 |
| 1512 | // 2606: } |
| 1513 | // 2606: } // switch Inst[51:48] |
| 1514 | // 2606: } else try { |
| 1515 | OPC_Decode, 188, 3, 23, // 2610: decode to BCFSizi using decoder 23 |
| 1516 | // 2610: } |
| 1517 | // 2610: } |
| 1518 | 1, 0, // 2614: case 0x1: { |
| 1519 | OPC_Decode, 200, 3, 23, // 2616: decode to BCFSrzi using decoder 23 |
| 1520 | // 2616: } |
| 1521 | // 2616: } // switch Inst[47] |
| 1522 | // 2616: } |
| 1523 | 1, 0, // 2620: case 0x1: { |
| 1524 | OPC_SwitchField, 47, 1, // 2622: switch Inst[47] { |
| 1525 | 0, 29, // 2625: case 0x0: { |
| 1526 | OPC_Scope, 23, // 2627: try { |
| 1527 | OPC_SwitchField, 48, 4, // 2629: switch Inst[51:48] { |
| 1528 | 0, 8, // 2632: case 0x0: { |
| 1529 | OPC_CheckField, 40, 7, 0, // 2634: check Inst[46:40] == 0x0 |
| 1530 | OPC_Decode, 191, 3, 22, // 2638: decode to BCFSnari using decoder 22 |
| 1531 | // 2638: } |
| 1532 | 15, 0, // 2642: case 0xf: { |
| 1533 | OPC_CheckField, 40, 7, 0, // 2644: check Inst[46:40] == 0x0 |
| 1534 | OPC_Decode, 179, 3, 22, // 2648: decode to BCFSari using decoder 22 |
| 1535 | // 2648: } |
| 1536 | // 2648: } // switch Inst[51:48] |
| 1537 | // 2648: } else try { |
| 1538 | OPC_Decode, 185, 3, 23, // 2652: decode to BCFSiri using decoder 23 |
| 1539 | // 2652: } |
| 1540 | // 2652: } |
| 1541 | 1, 0, // 2656: case 0x1: { |
| 1542 | OPC_Decode, 197, 3, 23, // 2658: decode to BCFSrri using decoder 23 |
| 1543 | // 2658: } |
| 1544 | // 2658: } // switch Inst[47] |
| 1545 | // 2658: } |
| 1546 | // 2658: } // switch Inst[39] |
| 1547 | // 2658: } |
| 1548 | 2, 87, // 2662: case 0x2: { |
| 1549 | OPC_SwitchField, 39, 1, // 2664: switch Inst[39] { |
| 1550 | 0, 40, // 2667: case 0x0: { |
| 1551 | OPC_SwitchField, 47, 1, // 2669: switch Inst[47] { |
| 1552 | 0, 29, // 2672: case 0x0: { |
| 1553 | OPC_Scope, 23, // 2674: try { |
| 1554 | OPC_SwitchField, 48, 4, // 2676: switch Inst[51:48] { |
| 1555 | 0, 8, // 2679: case 0x0: { |
| 1556 | OPC_CheckField, 40, 7, 0, // 2681: check Inst[46:40] == 0x0 |
| 1557 | OPC_Decode, 195, 3, 22, // 2685: decode to BCFSnazi_nt using decoder 22 |
| 1558 | // 2685: } |
| 1559 | 15, 0, // 2689: case 0xf: { |
| 1560 | OPC_CheckField, 40, 7, 0, // 2691: check Inst[46:40] == 0x0 |
| 1561 | OPC_Decode, 183, 3, 22, // 2695: decode to BCFSazi_nt using decoder 22 |
| 1562 | // 2695: } |
| 1563 | // 2695: } // switch Inst[51:48] |
| 1564 | // 2695: } else try { |
| 1565 | OPC_Decode, 189, 3, 23, // 2699: decode to BCFSizi_nt using decoder 23 |
| 1566 | // 2699: } |
| 1567 | // 2699: } |
| 1568 | 1, 0, // 2703: case 0x1: { |
| 1569 | OPC_Decode, 201, 3, 23, // 2705: decode to BCFSrzi_nt using decoder 23 |
| 1570 | // 2705: } |
| 1571 | // 2705: } // switch Inst[47] |
| 1572 | // 2705: } |
| 1573 | 1, 0, // 2709: case 0x1: { |
| 1574 | OPC_SwitchField, 47, 1, // 2711: switch Inst[47] { |
| 1575 | 0, 29, // 2714: case 0x0: { |
| 1576 | OPC_Scope, 23, // 2716: try { |
| 1577 | OPC_SwitchField, 48, 4, // 2718: switch Inst[51:48] { |
| 1578 | 0, 8, // 2721: case 0x0: { |
| 1579 | OPC_CheckField, 40, 7, 0, // 2723: check Inst[46:40] == 0x0 |
| 1580 | OPC_Decode, 192, 3, 22, // 2727: decode to BCFSnari_nt using decoder 22 |
| 1581 | // 2727: } |
| 1582 | 15, 0, // 2731: case 0xf: { |
| 1583 | OPC_CheckField, 40, 7, 0, // 2733: check Inst[46:40] == 0x0 |
| 1584 | OPC_Decode, 180, 3, 22, // 2737: decode to BCFSari_nt using decoder 22 |
| 1585 | // 2737: } |
| 1586 | // 2737: } // switch Inst[51:48] |
| 1587 | // 2737: } else try { |
| 1588 | OPC_Decode, 186, 3, 23, // 2741: decode to BCFSiri_nt using decoder 23 |
| 1589 | // 2741: } |
| 1590 | // 2741: } |
| 1591 | 1, 0, // 2745: case 0x1: { |
| 1592 | OPC_Decode, 198, 3, 23, // 2747: decode to BCFSrri_nt using decoder 23 |
| 1593 | // 2747: } |
| 1594 | // 2747: } // switch Inst[47] |
| 1595 | // 2747: } |
| 1596 | // 2747: } // switch Inst[39] |
| 1597 | // 2747: } |
| 1598 | 3, 0, // 2751: case 0x3: { |
| 1599 | OPC_SwitchField, 39, 1, // 2753: switch Inst[39] { |
| 1600 | 0, 40, // 2756: case 0x0: { |
| 1601 | OPC_SwitchField, 47, 1, // 2758: switch Inst[47] { |
| 1602 | 0, 29, // 2761: case 0x0: { |
| 1603 | OPC_Scope, 23, // 2763: try { |
| 1604 | OPC_SwitchField, 48, 4, // 2765: switch Inst[51:48] { |
| 1605 | 0, 8, // 2768: case 0x0: { |
| 1606 | OPC_CheckField, 40, 7, 0, // 2770: check Inst[46:40] == 0x0 |
| 1607 | OPC_Decode, 196, 3, 22, // 2774: decode to BCFSnazi_t using decoder 22 |
| 1608 | // 2774: } |
| 1609 | 15, 0, // 2778: case 0xf: { |
| 1610 | OPC_CheckField, 40, 7, 0, // 2780: check Inst[46:40] == 0x0 |
| 1611 | OPC_Decode, 184, 3, 22, // 2784: decode to BCFSazi_t using decoder 22 |
| 1612 | // 2784: } |
| 1613 | // 2784: } // switch Inst[51:48] |
| 1614 | // 2784: } else try { |
| 1615 | OPC_Decode, 190, 3, 23, // 2788: decode to BCFSizi_t using decoder 23 |
| 1616 | // 2788: } |
| 1617 | // 2788: } |
| 1618 | 1, 0, // 2792: case 0x1: { |
| 1619 | OPC_Decode, 202, 3, 23, // 2794: decode to BCFSrzi_t using decoder 23 |
| 1620 | // 2794: } |
| 1621 | // 2794: } // switch Inst[47] |
| 1622 | // 2794: } |
| 1623 | 1, 0, // 2798: case 0x1: { |
| 1624 | OPC_SwitchField, 47, 1, // 2800: switch Inst[47] { |
| 1625 | 0, 29, // 2803: case 0x0: { |
| 1626 | OPC_Scope, 23, // 2805: try { |
| 1627 | OPC_SwitchField, 48, 4, // 2807: switch Inst[51:48] { |
| 1628 | 0, 8, // 2810: case 0x0: { |
| 1629 | OPC_CheckField, 40, 7, 0, // 2812: check Inst[46:40] == 0x0 |
| 1630 | OPC_Decode, 193, 3, 22, // 2816: decode to BCFSnari_t using decoder 22 |
| 1631 | // 2816: } |
| 1632 | 15, 0, // 2820: case 0xf: { |
| 1633 | OPC_CheckField, 40, 7, 0, // 2822: check Inst[46:40] == 0x0 |
| 1634 | OPC_Decode, 181, 3, 22, // 2826: decode to BCFSari_t using decoder 22 |
| 1635 | // 2826: } |
| 1636 | // 2826: } // switch Inst[51:48] |
| 1637 | // 2826: } else try { |
| 1638 | OPC_Decode, 187, 3, 23, // 2830: decode to BCFSiri_t using decoder 23 |
| 1639 | // 2830: } |
| 1640 | // 2830: } |
| 1641 | 1, 0, // 2834: case 0x1: { |
| 1642 | OPC_Decode, 199, 3, 23, // 2836: decode to BCFSrri_t using decoder 23 |
| 1643 | // 2836: } |
| 1644 | // 2836: } // switch Inst[47] |
| 1645 | // 2836: } |
| 1646 | // 2836: } // switch Inst[39] |
| 1647 | // 2836: } |
| 1648 | // 2836: } // switch Inst[54:52] |
| 1649 | // 2836: } |
| 1650 | 62, 23, // 2840: case 0x3e: { |
| 1651 | OPC_SwitchField, 47, 1, // 2842: switch Inst[47] { |
| 1652 | 0, 8, // 2845: case 0x0: { |
| 1653 | OPC_CheckField, 0, 40, 0, // 2847: check Inst[39:0] == 0x0 |
| 1654 | OPC_Decode, 238, 4, 24, // 2851: decode to CVTSDi using decoder 24 |
| 1655 | // 2851: } |
| 1656 | 1, 0, // 2855: case 0x1: { |
| 1657 | OPC_CheckField, 0, 40, 0, // 2857: check Inst[39:0] == 0x0 |
| 1658 | OPC_Decode, 239, 4, 25, // 2861: decode to CVTSDr using decoder 25 |
| 1659 | // 2861: } |
| 1660 | // 2861: } // switch Inst[47] |
| 1661 | // 2861: } |
| 1662 | 63, 23, // 2865: case 0x3f: { |
| 1663 | OPC_SwitchField, 47, 1, // 2867: switch Inst[47] { |
| 1664 | 0, 8, // 2870: case 0x0: { |
| 1665 | OPC_CheckField, 0, 40, 0, // 2872: check Inst[39:0] == 0x0 |
| 1666 | OPC_Decode, 240, 4, 24, // 2876: decode to CVTSQi using decoder 24 |
| 1667 | // 2876: } |
| 1668 | 1, 0, // 2880: case 0x1: { |
| 1669 | OPC_CheckField, 0, 40, 0, // 2882: check Inst[39:0] == 0x0 |
| 1670 | OPC_Decode, 241, 4, 26, // 2886: decode to CVTSQr using decoder 26 |
| 1671 | // 2886: } |
| 1672 | // 2886: } // switch Inst[47] |
| 1673 | // 2886: } |
| 1674 | 64, 30, // 2890: case 0x40: { |
| 1675 | OPC_CheckField, 0, 40, 0, // 2892: check Inst[39:0] == 0x0 |
| 1676 | OPC_CheckField, 43, 5, 0, // 2896: check Inst[47:43] == 0x0 |
| 1677 | OPC_CheckField, 50, 5, 0, // 2900: check Inst[54:50] == 0x0 |
| 1678 | OPC_Scope, 8, // 2904: try { |
| 1679 | OPC_CheckField, 40, 3, 0, // 2906: check Inst[42:40] == 0x0 |
| 1680 | OPC_Decode, 199, 5, 27, // 2910: decode to FENCEM using decoder 27 |
| 1681 | // 2910: } else try { |
| 1682 | OPC_CheckField, 48, 2, 0, // 2914: check Inst[49:48] == 0x0 |
| 1683 | OPC_Decode, 197, 5, 28, // 2918: decode to FENCEC using decoder 28 |
| 1684 | // 2918: } |
| 1685 | // 2918: } |
| 1686 | 65, 8, // 2922: case 0x41: { |
| 1687 | OPC_CheckField, 0, 55, 0, // 2924: check Inst[54:0] == 0x0 |
| 1688 | OPC_Decode, 198, 5, 29, // 2928: decode to FENCEI using decoder 29 |
| 1689 | // 2928: } |
| 1690 | 66, 51, // 2932: case 0x42: { |
| 1691 | OPC_SwitchField, 39, 9, // 2934: switch Inst[47:39] { |
| 1692 | 0, 4, // 2937: case 0x0: { |
| 1693 | OPC_Decode, 163, 6, 30, // 2939: decode to LHMBzi using decoder 30 |
| 1694 | // 2939: } |
| 1695 | 1, 4, // 2943: case 0x1: { |
| 1696 | OPC_Decode, 162, 6, 30, // 2945: decode to LHMBri using decoder 30 |
| 1697 | // 2945: } |
| 1698 | 2, 4, // 2949: case 0x2: { |
| 1699 | OPC_Decode, 165, 6, 30, // 2951: decode to LHMHzi using decoder 30 |
| 1700 | // 2951: } |
| 1701 | 3, 4, // 2955: case 0x3: { |
| 1702 | OPC_Decode, 164, 6, 30, // 2957: decode to LHMHri using decoder 30 |
| 1703 | // 2957: } |
| 1704 | 4, 4, // 2961: case 0x4: { |
| 1705 | OPC_Decode, 169, 6, 30, // 2963: decode to LHMWzi using decoder 30 |
| 1706 | // 2963: } |
| 1707 | 5, 4, // 2967: case 0x5: { |
| 1708 | OPC_Decode, 168, 6, 30, // 2969: decode to LHMWri using decoder 30 |
| 1709 | // 2969: } |
| 1710 | 6, 4, // 2973: case 0x6: { |
| 1711 | OPC_Decode, 167, 6, 30, // 2975: decode to LHMLzi using decoder 30 |
| 1712 | // 2975: } |
| 1713 | 7, 0, // 2979: case 0x7: { |
| 1714 | OPC_Decode, 166, 6, 30, // 2981: decode to LHMLri using decoder 30 |
| 1715 | // 2981: } |
| 1716 | // 2981: } // switch Inst[47:39] |
| 1717 | // 2981: } |
| 1718 | 68, 12, // 2985: case 0x44: { |
| 1719 | OPC_CheckField, 47, 1, 0, // 2987: check Inst[47] == 0x0 |
| 1720 | OPC_CheckField, 0, 40, 0, // 2991: check Inst[39:0] == 0x0 |
| 1721 | OPC_Decode, 134, 35, 31, // 2995: decode to SMIR using decoder 31 |
| 1722 | // 2995: } |
| 1723 | 80, 8, // 2999: case 0x50: { |
| 1724 | OPC_CheckField, 0, 48, 0, // 3001: check Inst[47:0] == 0x0 |
| 1725 | OPC_Decode, 241, 34, 32, // 3005: decode to SIC using decoder 32 |
| 1726 | // 3005: } |
| 1727 | 82, 8, // 3009: case 0x52: { |
| 1728 | OPC_CheckField, 0, 48, 0, // 3011: check Inst[47:0] == 0x0 |
| 1729 | OPC_Decode, 232, 34, 33, // 3015: decode to SFR using decoder 33 |
| 1730 | // 3015: } |
| 1731 | 84, 8, // 3019: case 0x54: { |
| 1732 | OPC_CheckField, 0, 48, 0, // 3021: check Inst[47:0] == 0x0 |
| 1733 | OPC_Decode, 136, 35, 33, // 3025: decode to SPM using decoder 33 |
| 1734 | // 3025: } |
| 1735 | 86, 31, // 3029: case 0x56: { |
| 1736 | OPC_SwitchField, 39, 1, // 3031: switch Inst[39] { |
| 1737 | 0, 12, // 3034: case 0x0: { |
| 1738 | OPC_CheckField, 47, 1, 0, // 3036: check Inst[47] == 0x0 |
| 1739 | OPC_CheckField, 0, 32, 0, // 3040: check Inst[31:0] == 0x0 |
| 1740 | OPC_Decode, 177, 4, 34, // 3044: decode to BSWPmi using decoder 34 |
| 1741 | // 3044: } |
| 1742 | 1, 0, // 3048: case 0x1: { |
| 1743 | OPC_CheckField, 47, 1, 0, // 3050: check Inst[47] == 0x0 |
| 1744 | OPC_CheckField, 0, 32, 0, // 3054: check Inst[31:0] == 0x0 |
| 1745 | OPC_Decode, 178, 4, 35, // 3058: decode to BSWPri using decoder 35 |
| 1746 | // 3058: } |
| 1747 | // 3058: } // switch Inst[39] |
| 1748 | // 3058: } |
| 1749 | 90, 23, // 3062: case 0x5a: { |
| 1750 | OPC_SwitchField, 47, 1, // 3064: switch Inst[47] { |
| 1751 | 0, 8, // 3067: case 0x0: { |
| 1752 | OPC_CheckField, 0, 40, 0, // 3069: check Inst[39:0] == 0x0 |
| 1753 | OPC_Decode, 234, 4, 36, // 3073: decode to CVTQDi using decoder 36 |
| 1754 | // 3073: } |
| 1755 | 1, 0, // 3077: case 0x1: { |
| 1756 | OPC_CheckField, 0, 40, 0, // 3079: check Inst[39:0] == 0x0 |
| 1757 | OPC_Decode, 235, 4, 37, // 3083: decode to CVTQDr using decoder 37 |
| 1758 | // 3083: } |
| 1759 | // 3083: } // switch Inst[47] |
| 1760 | // 3083: } |
| 1761 | 91, 23, // 3087: case 0x5b: { |
| 1762 | OPC_SwitchField, 47, 1, // 3089: switch Inst[47] { |
| 1763 | 0, 8, // 3092: case 0x0: { |
| 1764 | OPC_CheckField, 0, 40, 0, // 3094: check Inst[39:0] == 0x0 |
| 1765 | OPC_Decode, 236, 4, 36, // 3098: decode to CVTQSi using decoder 36 |
| 1766 | // 3098: } |
| 1767 | 1, 0, // 3102: case 0x1: { |
| 1768 | OPC_CheckField, 0, 40, 0, // 3104: check Inst[39:0] == 0x0 |
| 1769 | OPC_Decode, 237, 4, 38, // 3108: decode to CVTQSr using decoder 38 |
| 1770 | // 3108: } |
| 1771 | // 3108: } // switch Inst[47] |
| 1772 | // 3108: } |
| 1773 | 92, 8, // 3112: case 0x5c: { |
| 1774 | OPC_CheckField, 0, 48, 0, // 3114: check Inst[47:0] == 0x0 |
| 1775 | OPC_Decode, 135, 35, 33, // 3118: decode to SMVL using decoder 33 |
| 1776 | // 3118: } |
| 1777 | 94, 8, // 3122: case 0x5e: { |
| 1778 | OPC_CheckField, 0, 48, 0, // 3124: check Inst[47:0] == 0x0 |
| 1779 | OPC_Decode, 197, 35, 33, // 3128: decode to SVL using decoder 33 |
| 1780 | // 3128: } |
| 1781 | 96, 8, // 3132: case 0x60: { |
| 1782 | OPC_CheckField, 0, 55, 0, // 3134: check Inst[54:0] == 0x0 |
| 1783 | OPC_Decode, 200, 35, 29, // 3138: decode to SVOB using decoder 29 |
| 1784 | // 3138: } |
| 1785 | 98, 51, // 3142: case 0x62: { |
| 1786 | OPC_SwitchField, 39, 9, // 3144: switch Inst[47:39] { |
| 1787 | 0, 4, // 3147: case 0x0: { |
| 1788 | OPC_Decode, 234, 34, 39, // 3149: decode to SHMBzi using decoder 39 |
| 1789 | // 3149: } |
| 1790 | 1, 4, // 3153: case 0x1: { |
| 1791 | OPC_Decode, 233, 34, 39, // 3155: decode to SHMBri using decoder 39 |
| 1792 | // 3155: } |
| 1793 | 2, 4, // 3159: case 0x2: { |
| 1794 | OPC_Decode, 236, 34, 39, // 3161: decode to SHMHzi using decoder 39 |
| 1795 | // 3161: } |
| 1796 | 3, 4, // 3165: case 0x3: { |
| 1797 | OPC_Decode, 235, 34, 39, // 3167: decode to SHMHri using decoder 39 |
| 1798 | // 3167: } |
| 1799 | 4, 4, // 3171: case 0x4: { |
| 1800 | OPC_Decode, 240, 34, 39, // 3173: decode to SHMWzi using decoder 39 |
| 1801 | // 3173: } |
| 1802 | 5, 4, // 3177: case 0x5: { |
| 1803 | OPC_Decode, 239, 34, 39, // 3179: decode to SHMWri using decoder 39 |
| 1804 | // 3179: } |
| 1805 | 6, 4, // 3183: case 0x6: { |
| 1806 | OPC_Decode, 238, 34, 39, // 3185: decode to SHMLzi using decoder 39 |
| 1807 | // 3185: } |
| 1808 | 7, 0, // 3189: case 0x7: { |
| 1809 | OPC_Decode, 237, 34, 39, // 3191: decode to SHMLri using decoder 39 |
| 1810 | // 3191: } |
| 1811 | // 3191: } // switch Inst[47:39] |
| 1812 | // 3191: } |
| 1813 | 112, 23, // 3195: case 0x70: { |
| 1814 | OPC_SwitchField, 39, 9, // 3197: switch Inst[47:39] { |
| 1815 | 0, 8, // 3200: case 0x0: { |
| 1816 | OPC_CheckField, 0, 32, 0, // 3202: check Inst[31:0] == 0x0 |
| 1817 | OPC_Decode, 134, 7, 40, // 3206: decode to PCNTm using decoder 40 |
| 1818 | // 3206: } |
| 1819 | 1, 0, // 3210: case 0x1: { |
| 1820 | OPC_CheckField, 0, 32, 0, // 3212: check Inst[31:0] == 0x0 |
| 1821 | OPC_Decode, 135, 7, 41, // 3216: decode to PCNTr using decoder 41 |
| 1822 | // 3216: } |
| 1823 | // 3216: } // switch Inst[47:39] |
| 1824 | // 3216: } |
| 1825 | 114, 23, // 3220: case 0x72: { |
| 1826 | OPC_SwitchField, 39, 9, // 3222: switch Inst[47:39] { |
| 1827 | 0, 8, // 3225: case 0x0: { |
| 1828 | OPC_CheckField, 0, 32, 0, // 3227: check Inst[31:0] == 0x0 |
| 1829 | OPC_Decode, 171, 4, 40, // 3231: decode to BRVm using decoder 40 |
| 1830 | // 3231: } |
| 1831 | 1, 0, // 3235: case 0x1: { |
| 1832 | OPC_CheckField, 0, 32, 0, // 3237: check Inst[31:0] == 0x0 |
| 1833 | OPC_Decode, 172, 4, 41, // 3241: decode to BRVr using decoder 41 |
| 1834 | // 3241: } |
| 1835 | // 3241: } // switch Inst[47:39] |
| 1836 | // 3241: } |
| 1837 | 116, 12, // 3245: case 0x74: { |
| 1838 | OPC_CheckField, 47, 8, 1, // 3247: check Inst[54:47] == 0x1 |
| 1839 | OPC_CheckField, 0, 40, 0, // 3251: check Inst[39:0] == 0x0 |
| 1840 | OPC_Decode, 170, 6, 42, // 3255: decode to LPM using decoder 42 |
| 1841 | // 3255: } |
| 1842 | 118, 159, 1, // 3259: case 0x76: { |
| 1843 | OPC_SwitchField, 4, 28, // 3262: switch Inst[31:4] { |
| 1844 | 0, 37, // 3265: case 0x0: { |
| 1845 | OPC_SwitchField, 39, 1, // 3267: switch Inst[39] { |
| 1846 | 0, 15, // 3270: case 0x0: { |
| 1847 | OPC_SwitchField, 47, 1, // 3272: switch Inst[47] { |
| 1848 | 0, 4, // 3275: case 0x0: { |
| 1849 | OPC_Decode, 192, 4, 43, // 3277: decode to CMOVLim using decoder 43 |
| 1850 | // 3277: } |
| 1851 | 1, 0, // 3281: case 0x1: { |
| 1852 | OPC_Decode, 194, 4, 44, // 3283: decode to CMOVLrm using decoder 44 |
| 1853 | // 3283: } |
| 1854 | // 3283: } // switch Inst[47] |
| 1855 | // 3283: } |
| 1856 | 1, 0, // 3287: case 0x1: { |
| 1857 | OPC_SwitchField, 47, 1, // 3289: switch Inst[47] { |
| 1858 | 0, 4, // 3292: case 0x0: { |
| 1859 | OPC_Decode, 193, 4, 45, // 3294: decode to CMOVLir using decoder 45 |
| 1860 | // 3294: } |
| 1861 | 1, 0, // 3298: case 0x1: { |
| 1862 | OPC_Decode, 195, 4, 46, // 3300: decode to CMOVLrr using decoder 46 |
| 1863 | // 3300: } |
| 1864 | // 3300: } // switch Inst[47] |
| 1865 | // 3300: } |
| 1866 | // 3300: } // switch Inst[39] |
| 1867 | // 3300: } |
| 1868 | 4, 37, // 3304: case 0x4: { |
| 1869 | OPC_SwitchField, 39, 1, // 3306: switch Inst[39] { |
| 1870 | 0, 15, // 3309: case 0x0: { |
| 1871 | OPC_SwitchField, 47, 1, // 3311: switch Inst[47] { |
| 1872 | 0, 4, // 3314: case 0x0: { |
| 1873 | OPC_Decode, 188, 4, 43, // 3316: decode to CMOVDim using decoder 43 |
| 1874 | // 3316: } |
| 1875 | 1, 0, // 3320: case 0x1: { |
| 1876 | OPC_Decode, 190, 4, 44, // 3322: decode to CMOVDrm using decoder 44 |
| 1877 | // 3322: } |
| 1878 | // 3322: } // switch Inst[47] |
| 1879 | // 3322: } |
| 1880 | 1, 0, // 3326: case 0x1: { |
| 1881 | OPC_SwitchField, 47, 1, // 3328: switch Inst[47] { |
| 1882 | 0, 4, // 3331: case 0x0: { |
| 1883 | OPC_Decode, 189, 4, 45, // 3333: decode to CMOVDir using decoder 45 |
| 1884 | // 3333: } |
| 1885 | 1, 0, // 3337: case 0x1: { |
| 1886 | OPC_Decode, 191, 4, 46, // 3339: decode to CMOVDrr using decoder 46 |
| 1887 | // 3339: } |
| 1888 | // 3339: } // switch Inst[47] |
| 1889 | // 3339: } |
| 1890 | // 3339: } // switch Inst[39] |
| 1891 | // 3339: } |
| 1892 | 8, 37, // 3343: case 0x8: { |
| 1893 | OPC_SwitchField, 39, 1, // 3345: switch Inst[39] { |
| 1894 | 0, 15, // 3348: case 0x0: { |
| 1895 | OPC_SwitchField, 47, 1, // 3350: switch Inst[47] { |
| 1896 | 0, 4, // 3353: case 0x0: { |
| 1897 | OPC_Decode, 200, 4, 43, // 3355: decode to CMOVWim using decoder 43 |
| 1898 | // 3355: } |
| 1899 | 1, 0, // 3359: case 0x1: { |
| 1900 | OPC_Decode, 202, 4, 47, // 3361: decode to CMOVWrm using decoder 47 |
| 1901 | // 3361: } |
| 1902 | // 3361: } // switch Inst[47] |
| 1903 | // 3361: } |
| 1904 | 1, 0, // 3365: case 0x1: { |
| 1905 | OPC_SwitchField, 47, 1, // 3367: switch Inst[47] { |
| 1906 | 0, 4, // 3370: case 0x0: { |
| 1907 | OPC_Decode, 201, 4, 45, // 3372: decode to CMOVWir using decoder 45 |
| 1908 | // 3372: } |
| 1909 | 1, 0, // 3376: case 0x1: { |
| 1910 | OPC_Decode, 203, 4, 48, // 3378: decode to CMOVWrr using decoder 48 |
| 1911 | // 3378: } |
| 1912 | // 3378: } // switch Inst[47] |
| 1913 | // 3378: } |
| 1914 | // 3378: } // switch Inst[39] |
| 1915 | // 3378: } |
| 1916 | 12, 0, // 3382: case 0xc: { |
| 1917 | OPC_SwitchField, 39, 1, // 3384: switch Inst[39] { |
| 1918 | 0, 15, // 3387: case 0x0: { |
| 1919 | OPC_SwitchField, 47, 1, // 3389: switch Inst[47] { |
| 1920 | 0, 4, // 3392: case 0x0: { |
| 1921 | OPC_Decode, 196, 4, 43, // 3394: decode to CMOVSim using decoder 43 |
| 1922 | // 3394: } |
| 1923 | 1, 0, // 3398: case 0x1: { |
| 1924 | OPC_Decode, 198, 4, 49, // 3400: decode to CMOVSrm using decoder 49 |
| 1925 | // 3400: } |
| 1926 | // 3400: } // switch Inst[47] |
| 1927 | // 3400: } |
| 1928 | 1, 0, // 3404: case 0x1: { |
| 1929 | OPC_SwitchField, 47, 1, // 3406: switch Inst[47] { |
| 1930 | 0, 4, // 3409: case 0x0: { |
| 1931 | OPC_Decode, 197, 4, 45, // 3411: decode to CMOVSir using decoder 45 |
| 1932 | // 3411: } |
| 1933 | 1, 0, // 3415: case 0x1: { |
| 1934 | OPC_Decode, 199, 4, 50, // 3417: decode to CMOVSrr using decoder 50 |
| 1935 | // 3417: } |
| 1936 | // 3417: } // switch Inst[47] |
| 1937 | // 3417: } |
| 1938 | // 3417: } // switch Inst[39] |
| 1939 | // 3417: } |
| 1940 | // 3417: } // switch Inst[31:4] |
| 1941 | // 3417: } |
| 1942 | 124, 82, // 3421: case 0x7c: { |
| 1943 | OPC_SwitchField, 0, 32, // 3423: switch Inst[31:0] { |
| 1944 | 0, 37, // 3426: case 0x0: { |
| 1945 | OPC_SwitchField, 39, 1, // 3428: switch Inst[39] { |
| 1946 | 0, 15, // 3431: case 0x0: { |
| 1947 | OPC_SwitchField, 47, 1, // 3433: switch Inst[47] { |
| 1948 | 0, 4, // 3436: case 0x0: { |
| 1949 | OPC_Decode, 202, 5, 51, // 3438: decode to FMAXDim using decoder 51 |
| 1950 | // 3438: } |
| 1951 | 1, 0, // 3442: case 0x1: { |
| 1952 | OPC_Decode, 204, 5, 52, // 3444: decode to FMAXDrm using decoder 52 |
| 1953 | // 3444: } |
| 1954 | // 3444: } // switch Inst[47] |
| 1955 | // 3444: } |
| 1956 | 1, 0, // 3448: case 0x1: { |
| 1957 | OPC_SwitchField, 47, 1, // 3450: switch Inst[47] { |
| 1958 | 0, 4, // 3453: case 0x0: { |
| 1959 | OPC_Decode, 203, 5, 53, // 3455: decode to FMAXDir using decoder 53 |
| 1960 | // 3455: } |
| 1961 | 1, 0, // 3459: case 0x1: { |
| 1962 | OPC_Decode, 205, 5, 54, // 3461: decode to FMAXDrr using decoder 54 |
| 1963 | // 3461: } |
| 1964 | // 3461: } // switch Inst[47] |
| 1965 | // 3461: } |
| 1966 | // 3461: } // switch Inst[39] |
| 1967 | // 3461: } |
| 1968 | 128, 1, 0, // 3465: case 0x80: { |
| 1969 | OPC_SwitchField, 39, 1, // 3468: switch Inst[39] { |
| 1970 | 0, 15, // 3471: case 0x0: { |
| 1971 | OPC_SwitchField, 47, 1, // 3473: switch Inst[47] { |
| 1972 | 0, 4, // 3476: case 0x0: { |
| 1973 | OPC_Decode, 210, 5, 51, // 3478: decode to FMINDim using decoder 51 |
| 1974 | // 3478: } |
| 1975 | 1, 0, // 3482: case 0x1: { |
| 1976 | OPC_Decode, 212, 5, 52, // 3484: decode to FMINDrm using decoder 52 |
| 1977 | // 3484: } |
| 1978 | // 3484: } // switch Inst[47] |
| 1979 | // 3484: } |
| 1980 | 1, 0, // 3488: case 0x1: { |
| 1981 | OPC_SwitchField, 47, 1, // 3490: switch Inst[47] { |
| 1982 | 0, 4, // 3493: case 0x0: { |
| 1983 | OPC_Decode, 211, 5, 53, // 3495: decode to FMINDir using decoder 53 |
| 1984 | // 3495: } |
| 1985 | 1, 0, // 3499: case 0x1: { |
| 1986 | OPC_Decode, 213, 5, 54, // 3501: decode to FMINDrr using decoder 54 |
| 1987 | // 3501: } |
| 1988 | // 3501: } // switch Inst[47] |
| 1989 | // 3501: } |
| 1990 | // 3501: } // switch Inst[39] |
| 1991 | // 3501: } |
| 1992 | // 3501: } // switch Inst[31:0] |
| 1993 | // 3501: } |
| 1994 | 125, 82, // 3505: case 0x7d: { |
| 1995 | OPC_SwitchField, 0, 32, // 3507: switch Inst[31:0] { |
| 1996 | 0, 37, // 3510: case 0x0: { |
| 1997 | OPC_SwitchField, 39, 1, // 3512: switch Inst[39] { |
| 1998 | 0, 15, // 3515: case 0x0: { |
| 1999 | OPC_SwitchField, 47, 1, // 3517: switch Inst[47] { |
| 2000 | 0, 4, // 3520: case 0x0: { |
| 2001 | OPC_Decode, 206, 5, 55, // 3522: decode to FMAXSim using decoder 55 |
| 2002 | // 3522: } |
| 2003 | 1, 0, // 3526: case 0x1: { |
| 2004 | OPC_Decode, 208, 5, 56, // 3528: decode to FMAXSrm using decoder 56 |
| 2005 | // 3528: } |
| 2006 | // 3528: } // switch Inst[47] |
| 2007 | // 3528: } |
| 2008 | 1, 0, // 3532: case 0x1: { |
| 2009 | OPC_SwitchField, 47, 1, // 3534: switch Inst[47] { |
| 2010 | 0, 4, // 3537: case 0x0: { |
| 2011 | OPC_Decode, 207, 5, 57, // 3539: decode to FMAXSir using decoder 57 |
| 2012 | // 3539: } |
| 2013 | 1, 0, // 3543: case 0x1: { |
| 2014 | OPC_Decode, 209, 5, 58, // 3545: decode to FMAXSrr using decoder 58 |
| 2015 | // 3545: } |
| 2016 | // 3545: } // switch Inst[47] |
| 2017 | // 3545: } |
| 2018 | // 3545: } // switch Inst[39] |
| 2019 | // 3545: } |
| 2020 | 128, 1, 0, // 3549: case 0x80: { |
| 2021 | OPC_SwitchField, 39, 1, // 3552: switch Inst[39] { |
| 2022 | 0, 15, // 3555: case 0x0: { |
| 2023 | OPC_SwitchField, 47, 1, // 3557: switch Inst[47] { |
| 2024 | 0, 4, // 3560: case 0x0: { |
| 2025 | OPC_Decode, 214, 5, 55, // 3562: decode to FMINSim using decoder 55 |
| 2026 | // 3562: } |
| 2027 | 1, 0, // 3566: case 0x1: { |
| 2028 | OPC_Decode, 216, 5, 56, // 3568: decode to FMINSrm using decoder 56 |
| 2029 | // 3568: } |
| 2030 | // 3568: } // switch Inst[47] |
| 2031 | // 3568: } |
| 2032 | 1, 0, // 3572: case 0x1: { |
| 2033 | OPC_SwitchField, 47, 1, // 3574: switch Inst[47] { |
| 2034 | 0, 4, // 3577: case 0x0: { |
| 2035 | OPC_Decode, 215, 5, 57, // 3579: decode to FMINSir using decoder 57 |
| 2036 | // 3579: } |
| 2037 | 1, 0, // 3583: case 0x1: { |
| 2038 | OPC_Decode, 217, 5, 58, // 3585: decode to FMINSrr using decoder 58 |
| 2039 | // 3585: } |
| 2040 | // 3585: } // switch Inst[47] |
| 2041 | // 3585: } |
| 2042 | // 3585: } // switch Inst[39] |
| 2043 | // 3585: } |
| 2044 | // 3585: } // switch Inst[31:0] |
| 2045 | // 3585: } |
| 2046 | 126, 8, // 3589: case 0x7e: { |
| 2047 | OPC_CheckField, 0, 55, 0, // 3591: check Inst[54:0] == 0x0 |
| 2048 | OPC_Decode, 220, 6, 29, // 3595: decode to MONC using decoder 29 |
| 2049 | // 3595: } |
| 2050 | 127, 8, // 3599: case 0x7f: { |
| 2051 | OPC_CheckField, 0, 55, 0, // 3601: check Inst[54:0] == 0x0 |
| 2052 | OPC_Decode, 221, 6, 29, // 3605: decode to MONCHDB using decoder 29 |
| 2053 | // 3605: } |
| 2054 | 128, 1, 53, // 3609: case 0x80: { |
| 2055 | OPC_SwitchField, 39, 1, // 3612: switch Inst[39] { |
| 2056 | 0, 23, // 3615: case 0x0: { |
| 2057 | OPC_SwitchField, 47, 1, // 3617: switch Inst[47] { |
| 2058 | 0, 8, // 3620: case 0x0: { |
| 2059 | OPC_CheckField, 0, 32, 0, // 3622: check Inst[31:0] == 0x0 |
| 2060 | OPC_Decode, 243, 5, 51, // 3626: decode to LCRiz using decoder 51 |
| 2061 | // 3626: } |
| 2062 | 1, 0, // 3630: case 0x1: { |
| 2063 | OPC_CheckField, 0, 32, 0, // 3632: check Inst[31:0] == 0x0 |
| 2064 | OPC_Decode, 245, 5, 52, // 3636: decode to LCRrz using decoder 52 |
| 2065 | // 3636: } |
| 2066 | // 3636: } // switch Inst[47] |
| 2067 | // 3636: } |
| 2068 | 1, 0, // 3640: case 0x1: { |
| 2069 | OPC_SwitchField, 47, 1, // 3642: switch Inst[47] { |
| 2070 | 0, 8, // 3645: case 0x0: { |
| 2071 | OPC_CheckField, 0, 32, 0, // 3647: check Inst[31:0] == 0x0 |
| 2072 | OPC_Decode, 242, 5, 53, // 3651: decode to LCRir using decoder 53 |
| 2073 | // 3651: } |
| 2074 | 1, 0, // 3655: case 0x1: { |
| 2075 | OPC_CheckField, 0, 32, 0, // 3657: check Inst[31:0] == 0x0 |
| 2076 | OPC_Decode, 244, 5, 54, // 3661: decode to LCRrr using decoder 54 |
| 2077 | // 3661: } |
| 2078 | // 3661: } // switch Inst[47] |
| 2079 | // 3661: } |
| 2080 | // 3661: } // switch Inst[39] |
| 2081 | // 3661: } |
| 2082 | 130, 1, 53, // 3665: case 0x82: { |
| 2083 | OPC_SwitchField, 39, 1, // 3668: switch Inst[39] { |
| 2084 | 0, 23, // 3671: case 0x0: { |
| 2085 | OPC_SwitchField, 47, 1, // 3673: switch Inst[47] { |
| 2086 | 0, 8, // 3676: case 0x0: { |
| 2087 | OPC_CheckField, 0, 32, 0, // 3678: check Inst[31:0] == 0x0 |
| 2088 | OPC_Decode, 221, 35, 59, // 3682: decode to TSCRizr using decoder 59 |
| 2089 | // 3682: } |
| 2090 | 1, 0, // 3686: case 0x1: { |
| 2091 | OPC_CheckField, 0, 32, 0, // 3688: check Inst[31:0] == 0x0 |
| 2092 | OPC_Decode, 223, 35, 60, // 3692: decode to TSCRrzr using decoder 60 |
| 2093 | // 3692: } |
| 2094 | // 3692: } // switch Inst[47] |
| 2095 | // 3692: } |
| 2096 | 1, 0, // 3696: case 0x1: { |
| 2097 | OPC_SwitchField, 47, 1, // 3698: switch Inst[47] { |
| 2098 | 0, 8, // 3701: case 0x0: { |
| 2099 | OPC_CheckField, 0, 32, 0, // 3703: check Inst[31:0] == 0x0 |
| 2100 | OPC_Decode, 220, 35, 61, // 3707: decode to TSCRirr using decoder 61 |
| 2101 | // 3707: } |
| 2102 | 1, 0, // 3711: case 0x1: { |
| 2103 | OPC_CheckField, 0, 32, 0, // 3713: check Inst[31:0] == 0x0 |
| 2104 | OPC_Decode, 222, 35, 62, // 3717: decode to TSCRrrr using decoder 62 |
| 2105 | // 3717: } |
| 2106 | // 3717: } // switch Inst[47] |
| 2107 | // 3717: } |
| 2108 | // 3717: } // switch Inst[39] |
| 2109 | // 3717: } |
| 2110 | 132, 1, 37, // 3721: case 0x84: { |
| 2111 | OPC_SwitchField, 39, 1, // 3724: switch Inst[39] { |
| 2112 | 0, 15, // 3727: case 0x0: { |
| 2113 | OPC_SwitchField, 47, 1, // 3729: switch Inst[47] { |
| 2114 | 0, 4, // 3732: case 0x0: { |
| 2115 | OPC_Decode, 206, 35, 63, // 3734: decode to TS1AMLzii using decoder 63 |
| 2116 | // 3734: } |
| 2117 | 1, 0, // 3738: case 0x1: { |
| 2118 | OPC_Decode, 207, 35, 63, // 3740: decode to TS1AMLzir using decoder 63 |
| 2119 | // 3740: } |
| 2120 | // 3740: } // switch Inst[47] |
| 2121 | // 3740: } |
| 2122 | 1, 0, // 3744: case 0x1: { |
| 2123 | OPC_SwitchField, 47, 1, // 3746: switch Inst[47] { |
| 2124 | 0, 4, // 3749: case 0x0: { |
| 2125 | OPC_Decode, 204, 35, 63, // 3751: decode to TS1AMLrii using decoder 63 |
| 2126 | // 3751: } |
| 2127 | 1, 0, // 3755: case 0x1: { |
| 2128 | OPC_Decode, 205, 35, 63, // 3757: decode to TS1AMLrir using decoder 63 |
| 2129 | // 3757: } |
| 2130 | // 3757: } // switch Inst[47] |
| 2131 | // 3757: } |
| 2132 | // 3757: } // switch Inst[39] |
| 2133 | // 3757: } |
| 2134 | 133, 1, 37, // 3761: case 0x85: { |
| 2135 | OPC_SwitchField, 39, 1, // 3764: switch Inst[39] { |
| 2136 | 0, 15, // 3767: case 0x0: { |
| 2137 | OPC_SwitchField, 47, 1, // 3769: switch Inst[47] { |
| 2138 | 0, 4, // 3772: case 0x0: { |
| 2139 | OPC_Decode, 210, 35, 64, // 3774: decode to TS1AMWzii using decoder 64 |
| 2140 | // 3774: } |
| 2141 | 1, 0, // 3778: case 0x1: { |
| 2142 | OPC_Decode, 211, 35, 64, // 3780: decode to TS1AMWzir using decoder 64 |
| 2143 | // 3780: } |
| 2144 | // 3780: } // switch Inst[47] |
| 2145 | // 3780: } |
| 2146 | 1, 0, // 3784: case 0x1: { |
| 2147 | OPC_SwitchField, 47, 1, // 3786: switch Inst[47] { |
| 2148 | 0, 4, // 3789: case 0x0: { |
| 2149 | OPC_Decode, 208, 35, 64, // 3791: decode to TS1AMWrii using decoder 64 |
| 2150 | // 3791: } |
| 2151 | 1, 0, // 3795: case 0x1: { |
| 2152 | OPC_Decode, 209, 35, 64, // 3797: decode to TS1AMWrir using decoder 64 |
| 2153 | // 3797: } |
| 2154 | // 3797: } // switch Inst[47] |
| 2155 | // 3797: } |
| 2156 | // 3797: } // switch Inst[39] |
| 2157 | // 3797: } |
| 2158 | 134, 1, 37, // 3801: case 0x86: { |
| 2159 | OPC_SwitchField, 39, 1, // 3804: switch Inst[39] { |
| 2160 | 0, 15, // 3807: case 0x0: { |
| 2161 | OPC_SwitchField, 47, 1, // 3809: switch Inst[47] { |
| 2162 | 0, 4, // 3812: case 0x0: { |
| 2163 | OPC_Decode, 214, 35, 63, // 3814: decode to TS2AMzii using decoder 63 |
| 2164 | // 3814: } |
| 2165 | 1, 0, // 3818: case 0x1: { |
| 2166 | OPC_Decode, 215, 35, 63, // 3820: decode to TS2AMzir using decoder 63 |
| 2167 | // 3820: } |
| 2168 | // 3820: } // switch Inst[47] |
| 2169 | // 3820: } |
| 2170 | 1, 0, // 3824: case 0x1: { |
| 2171 | OPC_SwitchField, 47, 1, // 3826: switch Inst[47] { |
| 2172 | 0, 4, // 3829: case 0x0: { |
| 2173 | OPC_Decode, 212, 35, 63, // 3831: decode to TS2AMrii using decoder 63 |
| 2174 | // 3831: } |
| 2175 | 1, 0, // 3835: case 0x1: { |
| 2176 | OPC_Decode, 213, 35, 63, // 3837: decode to TS2AMrir using decoder 63 |
| 2177 | // 3837: } |
| 2178 | // 3837: } // switch Inst[47] |
| 2179 | // 3837: } |
| 2180 | // 3837: } // switch Inst[39] |
| 2181 | // 3837: } |
| 2182 | 136, 1, 53, // 3841: case 0x88: { |
| 2183 | OPC_SwitchField, 39, 1, // 3844: switch Inst[39] { |
| 2184 | 0, 23, // 3847: case 0x0: { |
| 2185 | OPC_SwitchField, 47, 1, // 3849: switch Inst[47] { |
| 2186 | 0, 8, // 3852: case 0x0: { |
| 2187 | OPC_CheckField, 0, 32, 0, // 3854: check Inst[31:0] == 0x0 |
| 2188 | OPC_Decode, 251, 2, 51, // 3858: decode to ANDim using decoder 51 |
| 2189 | // 3858: } |
| 2190 | 1, 0, // 3862: case 0x1: { |
| 2191 | OPC_CheckField, 0, 32, 0, // 3864: check Inst[31:0] == 0x0 |
| 2192 | OPC_Decode, 253, 2, 52, // 3868: decode to ANDrm using decoder 52 |
| 2193 | // 3868: } |
| 2194 | // 3868: } // switch Inst[47] |
| 2195 | // 3868: } |
| 2196 | 1, 0, // 3872: case 0x1: { |
| 2197 | OPC_SwitchField, 47, 1, // 3874: switch Inst[47] { |
| 2198 | 0, 8, // 3877: case 0x0: { |
| 2199 | OPC_CheckField, 0, 32, 0, // 3879: check Inst[31:0] == 0x0 |
| 2200 | OPC_Decode, 252, 2, 65, // 3883: decode to ANDri using decoder 65 |
| 2201 | // 3883: } |
| 2202 | 1, 0, // 3887: case 0x1: { |
| 2203 | OPC_CheckField, 0, 32, 0, // 3889: check Inst[31:0] == 0x0 |
| 2204 | OPC_Decode, 254, 2, 54, // 3893: decode to ANDrr using decoder 54 |
| 2205 | // 3893: } |
| 2206 | // 3893: } // switch Inst[47] |
| 2207 | // 3893: } |
| 2208 | // 3893: } // switch Inst[39] |
| 2209 | // 3893: } |
| 2210 | 138, 1, 53, // 3897: case 0x8a: { |
| 2211 | OPC_SwitchField, 39, 1, // 3900: switch Inst[39] { |
| 2212 | 0, 23, // 3903: case 0x0: { |
| 2213 | OPC_SwitchField, 47, 1, // 3905: switch Inst[47] { |
| 2214 | 0, 8, // 3908: case 0x0: { |
| 2215 | OPC_CheckField, 0, 32, 0, // 3910: check Inst[31:0] == 0x0 |
| 2216 | OPC_Decode, 130, 7, 51, // 3914: decode to ORim using decoder 51 |
| 2217 | // 3914: } |
| 2218 | 1, 0, // 3918: case 0x1: { |
| 2219 | OPC_CheckField, 0, 32, 0, // 3920: check Inst[31:0] == 0x0 |
| 2220 | OPC_Decode, 132, 7, 52, // 3924: decode to ORrm using decoder 52 |
| 2221 | // 3924: } |
| 2222 | // 3924: } // switch Inst[47] |
| 2223 | // 3924: } |
| 2224 | 1, 0, // 3928: case 0x1: { |
| 2225 | OPC_SwitchField, 47, 1, // 3930: switch Inst[47] { |
| 2226 | 0, 8, // 3933: case 0x0: { |
| 2227 | OPC_CheckField, 0, 32, 0, // 3935: check Inst[31:0] == 0x0 |
| 2228 | OPC_Decode, 131, 7, 65, // 3939: decode to ORri using decoder 65 |
| 2229 | // 3939: } |
| 2230 | 1, 0, // 3943: case 0x1: { |
| 2231 | OPC_CheckField, 0, 32, 0, // 3945: check Inst[31:0] == 0x0 |
| 2232 | OPC_Decode, 133, 7, 54, // 3949: decode to ORrr using decoder 54 |
| 2233 | // 3949: } |
| 2234 | // 3949: } // switch Inst[47] |
| 2235 | // 3949: } |
| 2236 | // 3949: } // switch Inst[39] |
| 2237 | // 3949: } |
| 2238 | 140, 1, 53, // 3953: case 0x8c: { |
| 2239 | OPC_SwitchField, 39, 1, // 3956: switch Inst[39] { |
| 2240 | 0, 23, // 3959: case 0x0: { |
| 2241 | OPC_SwitchField, 47, 1, // 3961: switch Inst[47] { |
| 2242 | 0, 8, // 3964: case 0x0: { |
| 2243 | OPC_CheckField, 0, 32, 0, // 3966: check Inst[31:0] == 0x0 |
| 2244 | OPC_Decode, 133, 84, 51, // 3970: decode to XORim using decoder 51 |
| 2245 | // 3970: } |
| 2246 | 1, 0, // 3974: case 0x1: { |
| 2247 | OPC_CheckField, 0, 32, 0, // 3976: check Inst[31:0] == 0x0 |
| 2248 | OPC_Decode, 135, 84, 52, // 3980: decode to XORrm using decoder 52 |
| 2249 | // 3980: } |
| 2250 | // 3980: } // switch Inst[47] |
| 2251 | // 3980: } |
| 2252 | 1, 0, // 3984: case 0x1: { |
| 2253 | OPC_SwitchField, 47, 1, // 3986: switch Inst[47] { |
| 2254 | 0, 8, // 3989: case 0x0: { |
| 2255 | OPC_CheckField, 0, 32, 0, // 3991: check Inst[31:0] == 0x0 |
| 2256 | OPC_Decode, 134, 84, 65, // 3995: decode to XORri using decoder 65 |
| 2257 | // 3995: } |
| 2258 | 1, 0, // 3999: case 0x1: { |
| 2259 | OPC_CheckField, 0, 32, 0, // 4001: check Inst[31:0] == 0x0 |
| 2260 | OPC_Decode, 136, 84, 54, // 4005: decode to XORrr using decoder 54 |
| 2261 | // 4005: } |
| 2262 | // 4005: } // switch Inst[47] |
| 2263 | // 4005: } |
| 2264 | // 4005: } // switch Inst[39] |
| 2265 | // 4005: } |
| 2266 | 142, 1, 53, // 4009: case 0x8e: { |
| 2267 | OPC_SwitchField, 39, 1, // 4012: switch Inst[39] { |
| 2268 | 0, 23, // 4015: case 0x0: { |
| 2269 | OPC_SwitchField, 47, 1, // 4017: switch Inst[47] { |
| 2270 | 0, 8, // 4020: case 0x0: { |
| 2271 | OPC_CheckField, 0, 32, 0, // 4022: check Inst[31:0] == 0x0 |
| 2272 | OPC_Decode, 161, 5, 51, // 4026: decode to EQVim using decoder 51 |
| 2273 | // 4026: } |
| 2274 | 1, 0, // 4030: case 0x1: { |
| 2275 | OPC_CheckField, 0, 32, 0, // 4032: check Inst[31:0] == 0x0 |
| 2276 | OPC_Decode, 163, 5, 52, // 4036: decode to EQVrm using decoder 52 |
| 2277 | // 4036: } |
| 2278 | // 4036: } // switch Inst[47] |
| 2279 | // 4036: } |
| 2280 | 1, 0, // 4040: case 0x1: { |
| 2281 | OPC_SwitchField, 47, 1, // 4042: switch Inst[47] { |
| 2282 | 0, 8, // 4045: case 0x0: { |
| 2283 | OPC_CheckField, 0, 32, 0, // 4047: check Inst[31:0] == 0x0 |
| 2284 | OPC_Decode, 162, 5, 65, // 4051: decode to EQVri using decoder 65 |
| 2285 | // 4051: } |
| 2286 | 1, 0, // 4055: case 0x1: { |
| 2287 | OPC_CheckField, 0, 32, 0, // 4057: check Inst[31:0] == 0x0 |
| 2288 | OPC_Decode, 164, 5, 54, // 4061: decode to EQVrr using decoder 54 |
| 2289 | // 4061: } |
| 2290 | // 4061: } // switch Inst[47] |
| 2291 | // 4061: } |
| 2292 | // 4061: } // switch Inst[39] |
| 2293 | // 4061: } |
| 2294 | 144, 1, 53, // 4065: case 0x90: { |
| 2295 | OPC_SwitchField, 39, 1, // 4068: switch Inst[39] { |
| 2296 | 0, 23, // 4071: case 0x0: { |
| 2297 | OPC_SwitchField, 47, 1, // 4073: switch Inst[47] { |
| 2298 | 0, 8, // 4076: case 0x0: { |
| 2299 | OPC_CheckField, 0, 32, 0, // 4078: check Inst[31:0] == 0x0 |
| 2300 | OPC_Decode, 242, 2, 51, // 4082: decode to ADDULim using decoder 51 |
| 2301 | // 4082: } |
| 2302 | 1, 0, // 4086: case 0x1: { |
| 2303 | OPC_CheckField, 0, 32, 0, // 4088: check Inst[31:0] == 0x0 |
| 2304 | OPC_Decode, 244, 2, 52, // 4092: decode to ADDULrm using decoder 52 |
| 2305 | // 4092: } |
| 2306 | // 4092: } // switch Inst[47] |
| 2307 | // 4092: } |
| 2308 | 1, 0, // 4096: case 0x1: { |
| 2309 | OPC_SwitchField, 47, 1, // 4098: switch Inst[47] { |
| 2310 | 0, 8, // 4101: case 0x0: { |
| 2311 | OPC_CheckField, 0, 32, 0, // 4103: check Inst[31:0] == 0x0 |
| 2312 | OPC_Decode, 243, 2, 65, // 4107: decode to ADDULri using decoder 65 |
| 2313 | // 4107: } |
| 2314 | 1, 0, // 4111: case 0x1: { |
| 2315 | OPC_CheckField, 0, 32, 0, // 4113: check Inst[31:0] == 0x0 |
| 2316 | OPC_Decode, 245, 2, 54, // 4117: decode to ADDULrr using decoder 54 |
| 2317 | // 4117: } |
| 2318 | // 4117: } // switch Inst[47] |
| 2319 | // 4117: } |
| 2320 | // 4117: } // switch Inst[39] |
| 2321 | // 4117: } |
| 2322 | 145, 1, 53, // 4121: case 0x91: { |
| 2323 | OPC_SwitchField, 39, 1, // 4124: switch Inst[39] { |
| 2324 | 0, 23, // 4127: case 0x0: { |
| 2325 | OPC_SwitchField, 47, 1, // 4129: switch Inst[47] { |
| 2326 | 0, 8, // 4132: case 0x0: { |
| 2327 | OPC_CheckField, 0, 32, 0, // 4134: check Inst[31:0] == 0x0 |
| 2328 | OPC_Decode, 246, 2, 66, // 4138: decode to ADDUWim using decoder 66 |
| 2329 | // 4138: } |
| 2330 | 1, 0, // 4142: case 0x1: { |
| 2331 | OPC_CheckField, 0, 32, 0, // 4144: check Inst[31:0] == 0x0 |
| 2332 | OPC_Decode, 248, 2, 67, // 4148: decode to ADDUWrm using decoder 67 |
| 2333 | // 4148: } |
| 2334 | // 4148: } // switch Inst[47] |
| 2335 | // 4148: } |
| 2336 | 1, 0, // 4152: case 0x1: { |
| 2337 | OPC_SwitchField, 47, 1, // 4154: switch Inst[47] { |
| 2338 | 0, 8, // 4157: case 0x0: { |
| 2339 | OPC_CheckField, 0, 32, 0, // 4159: check Inst[31:0] == 0x0 |
| 2340 | OPC_Decode, 247, 2, 68, // 4163: decode to ADDUWri using decoder 68 |
| 2341 | // 4163: } |
| 2342 | 1, 0, // 4167: case 0x1: { |
| 2343 | OPC_CheckField, 0, 32, 0, // 4169: check Inst[31:0] == 0x0 |
| 2344 | OPC_Decode, 249, 2, 69, // 4173: decode to ADDUWrr using decoder 69 |
| 2345 | // 4173: } |
| 2346 | // 4173: } // switch Inst[47] |
| 2347 | // 4173: } |
| 2348 | // 4173: } // switch Inst[39] |
| 2349 | // 4173: } |
| 2350 | 146, 1, 53, // 4177: case 0x92: { |
| 2351 | OPC_SwitchField, 39, 1, // 4180: switch Inst[39] { |
| 2352 | 0, 23, // 4183: case 0x0: { |
| 2353 | OPC_SwitchField, 47, 1, // 4185: switch Inst[47] { |
| 2354 | 0, 8, // 4188: case 0x0: { |
| 2355 | OPC_CheckField, 0, 32, 0, // 4190: check Inst[31:0] == 0x0 |
| 2356 | OPC_Decode, 242, 6, 51, // 4194: decode to MULULim using decoder 51 |
| 2357 | // 4194: } |
| 2358 | 1, 0, // 4198: case 0x1: { |
| 2359 | OPC_CheckField, 0, 32, 0, // 4200: check Inst[31:0] == 0x0 |
| 2360 | OPC_Decode, 244, 6, 52, // 4204: decode to MULULrm using decoder 52 |
| 2361 | // 4204: } |
| 2362 | // 4204: } // switch Inst[47] |
| 2363 | // 4204: } |
| 2364 | 1, 0, // 4208: case 0x1: { |
| 2365 | OPC_SwitchField, 47, 1, // 4210: switch Inst[47] { |
| 2366 | 0, 8, // 4213: case 0x0: { |
| 2367 | OPC_CheckField, 0, 32, 0, // 4215: check Inst[31:0] == 0x0 |
| 2368 | OPC_Decode, 243, 6, 65, // 4219: decode to MULULri using decoder 65 |
| 2369 | // 4219: } |
| 2370 | 1, 0, // 4223: case 0x1: { |
| 2371 | OPC_CheckField, 0, 32, 0, // 4225: check Inst[31:0] == 0x0 |
| 2372 | OPC_Decode, 245, 6, 54, // 4229: decode to MULULrr using decoder 54 |
| 2373 | // 4229: } |
| 2374 | // 4229: } // switch Inst[47] |
| 2375 | // 4229: } |
| 2376 | // 4229: } // switch Inst[39] |
| 2377 | // 4229: } |
| 2378 | 147, 1, 53, // 4233: case 0x93: { |
| 2379 | OPC_SwitchField, 39, 1, // 4236: switch Inst[39] { |
| 2380 | 0, 23, // 4239: case 0x0: { |
| 2381 | OPC_SwitchField, 47, 1, // 4241: switch Inst[47] { |
| 2382 | 0, 8, // 4244: case 0x0: { |
| 2383 | OPC_CheckField, 0, 32, 0, // 4246: check Inst[31:0] == 0x0 |
| 2384 | OPC_Decode, 246, 6, 66, // 4250: decode to MULUWim using decoder 66 |
| 2385 | // 4250: } |
| 2386 | 1, 0, // 4254: case 0x1: { |
| 2387 | OPC_CheckField, 0, 32, 0, // 4256: check Inst[31:0] == 0x0 |
| 2388 | OPC_Decode, 248, 6, 67, // 4260: decode to MULUWrm using decoder 67 |
| 2389 | // 4260: } |
| 2390 | // 4260: } // switch Inst[47] |
| 2391 | // 4260: } |
| 2392 | 1, 0, // 4264: case 0x1: { |
| 2393 | OPC_SwitchField, 47, 1, // 4266: switch Inst[47] { |
| 2394 | 0, 8, // 4269: case 0x0: { |
| 2395 | OPC_CheckField, 0, 32, 0, // 4271: check Inst[31:0] == 0x0 |
| 2396 | OPC_Decode, 247, 6, 68, // 4275: decode to MULUWri using decoder 68 |
| 2397 | // 4275: } |
| 2398 | 1, 0, // 4279: case 0x1: { |
| 2399 | OPC_CheckField, 0, 32, 0, // 4281: check Inst[31:0] == 0x0 |
| 2400 | OPC_Decode, 249, 6, 69, // 4285: decode to MULUWrr using decoder 69 |
| 2401 | // 4285: } |
| 2402 | // 4285: } // switch Inst[47] |
| 2403 | // 4285: } |
| 2404 | // 4285: } // switch Inst[39] |
| 2405 | // 4285: } |
| 2406 | 148, 1, 53, // 4289: case 0x94: { |
| 2407 | OPC_SwitchField, 39, 1, // 4292: switch Inst[39] { |
| 2408 | 0, 23, // 4295: case 0x0: { |
| 2409 | OPC_SwitchField, 47, 1, // 4297: switch Inst[47] { |
| 2410 | 0, 8, // 4300: case 0x0: { |
| 2411 | OPC_CheckField, 0, 32, 0, // 4302: check Inst[31:0] == 0x0 |
| 2412 | OPC_Decode, 234, 2, 66, // 4306: decode to ADDSWSXim using decoder 66 |
| 2413 | // 4306: } |
| 2414 | 1, 0, // 4310: case 0x1: { |
| 2415 | OPC_CheckField, 0, 32, 0, // 4312: check Inst[31:0] == 0x0 |
| 2416 | OPC_Decode, 236, 2, 67, // 4316: decode to ADDSWSXrm using decoder 67 |
| 2417 | // 4316: } |
| 2418 | // 4316: } // switch Inst[47] |
| 2419 | // 4316: } |
| 2420 | 1, 0, // 4320: case 0x1: { |
| 2421 | OPC_SwitchField, 47, 1, // 4322: switch Inst[47] { |
| 2422 | 0, 8, // 4325: case 0x0: { |
| 2423 | OPC_CheckField, 0, 32, 0, // 4327: check Inst[31:0] == 0x0 |
| 2424 | OPC_Decode, 235, 2, 68, // 4331: decode to ADDSWSXri using decoder 68 |
| 2425 | // 4331: } |
| 2426 | 1, 0, // 4335: case 0x1: { |
| 2427 | OPC_CheckField, 0, 32, 0, // 4337: check Inst[31:0] == 0x0 |
| 2428 | OPC_Decode, 237, 2, 69, // 4341: decode to ADDSWSXrr using decoder 69 |
| 2429 | // 4341: } |
| 2430 | // 4341: } // switch Inst[47] |
| 2431 | // 4341: } |
| 2432 | // 4341: } // switch Inst[39] |
| 2433 | // 4341: } |
| 2434 | 149, 1, 53, // 4345: case 0x95: { |
| 2435 | OPC_SwitchField, 39, 1, // 4348: switch Inst[39] { |
| 2436 | 0, 23, // 4351: case 0x0: { |
| 2437 | OPC_SwitchField, 47, 1, // 4353: switch Inst[47] { |
| 2438 | 0, 8, // 4356: case 0x0: { |
| 2439 | OPC_CheckField, 0, 32, 0, // 4358: check Inst[31:0] == 0x0 |
| 2440 | OPC_Decode, 238, 2, 66, // 4362: decode to ADDSWZXim using decoder 66 |
| 2441 | // 4362: } |
| 2442 | 1, 0, // 4366: case 0x1: { |
| 2443 | OPC_CheckField, 0, 32, 0, // 4368: check Inst[31:0] == 0x0 |
| 2444 | OPC_Decode, 240, 2, 67, // 4372: decode to ADDSWZXrm using decoder 67 |
| 2445 | // 4372: } |
| 2446 | // 4372: } // switch Inst[47] |
| 2447 | // 4372: } |
| 2448 | 1, 0, // 4376: case 0x1: { |
| 2449 | OPC_SwitchField, 47, 1, // 4378: switch Inst[47] { |
| 2450 | 0, 8, // 4381: case 0x0: { |
| 2451 | OPC_CheckField, 0, 32, 0, // 4383: check Inst[31:0] == 0x0 |
| 2452 | OPC_Decode, 239, 2, 68, // 4387: decode to ADDSWZXri using decoder 68 |
| 2453 | // 4387: } |
| 2454 | 1, 0, // 4391: case 0x1: { |
| 2455 | OPC_CheckField, 0, 32, 0, // 4393: check Inst[31:0] == 0x0 |
| 2456 | OPC_Decode, 241, 2, 69, // 4397: decode to ADDSWZXrr using decoder 69 |
| 2457 | // 4397: } |
| 2458 | // 4397: } // switch Inst[47] |
| 2459 | // 4397: } |
| 2460 | // 4397: } // switch Inst[39] |
| 2461 | // 4397: } |
| 2462 | 150, 1, 53, // 4401: case 0x96: { |
| 2463 | OPC_SwitchField, 39, 1, // 4404: switch Inst[39] { |
| 2464 | 0, 23, // 4407: case 0x0: { |
| 2465 | OPC_SwitchField, 47, 1, // 4409: switch Inst[47] { |
| 2466 | 0, 8, // 4412: case 0x0: { |
| 2467 | OPC_CheckField, 0, 32, 0, // 4414: check Inst[31:0] == 0x0 |
| 2468 | OPC_Decode, 234, 6, 66, // 4418: decode to MULSWSXim using decoder 66 |
| 2469 | // 4418: } |
| 2470 | 1, 0, // 4422: case 0x1: { |
| 2471 | OPC_CheckField, 0, 32, 0, // 4424: check Inst[31:0] == 0x0 |
| 2472 | OPC_Decode, 236, 6, 67, // 4428: decode to MULSWSXrm using decoder 67 |
| 2473 | // 4428: } |
| 2474 | // 4428: } // switch Inst[47] |
| 2475 | // 4428: } |
| 2476 | 1, 0, // 4432: case 0x1: { |
| 2477 | OPC_SwitchField, 47, 1, // 4434: switch Inst[47] { |
| 2478 | 0, 8, // 4437: case 0x0: { |
| 2479 | OPC_CheckField, 0, 32, 0, // 4439: check Inst[31:0] == 0x0 |
| 2480 | OPC_Decode, 235, 6, 68, // 4443: decode to MULSWSXri using decoder 68 |
| 2481 | // 4443: } |
| 2482 | 1, 0, // 4447: case 0x1: { |
| 2483 | OPC_CheckField, 0, 32, 0, // 4449: check Inst[31:0] == 0x0 |
| 2484 | OPC_Decode, 237, 6, 69, // 4453: decode to MULSWSXrr using decoder 69 |
| 2485 | // 4453: } |
| 2486 | // 4453: } // switch Inst[47] |
| 2487 | // 4453: } |
| 2488 | // 4453: } // switch Inst[39] |
| 2489 | // 4453: } |
| 2490 | 151, 1, 53, // 4457: case 0x97: { |
| 2491 | OPC_SwitchField, 39, 1, // 4460: switch Inst[39] { |
| 2492 | 0, 23, // 4463: case 0x0: { |
| 2493 | OPC_SwitchField, 47, 1, // 4465: switch Inst[47] { |
| 2494 | 0, 8, // 4468: case 0x0: { |
| 2495 | OPC_CheckField, 0, 32, 0, // 4470: check Inst[31:0] == 0x0 |
| 2496 | OPC_Decode, 238, 6, 66, // 4474: decode to MULSWZXim using decoder 66 |
| 2497 | // 4474: } |
| 2498 | 1, 0, // 4478: case 0x1: { |
| 2499 | OPC_CheckField, 0, 32, 0, // 4480: check Inst[31:0] == 0x0 |
| 2500 | OPC_Decode, 240, 6, 67, // 4484: decode to MULSWZXrm using decoder 67 |
| 2501 | // 4484: } |
| 2502 | // 4484: } // switch Inst[47] |
| 2503 | // 4484: } |
| 2504 | 1, 0, // 4488: case 0x1: { |
| 2505 | OPC_SwitchField, 47, 1, // 4490: switch Inst[47] { |
| 2506 | 0, 8, // 4493: case 0x0: { |
| 2507 | OPC_CheckField, 0, 32, 0, // 4495: check Inst[31:0] == 0x0 |
| 2508 | OPC_Decode, 239, 6, 68, // 4499: decode to MULSWZXri using decoder 68 |
| 2509 | // 4499: } |
| 2510 | 1, 0, // 4503: case 0x1: { |
| 2511 | OPC_CheckField, 0, 32, 0, // 4505: check Inst[31:0] == 0x0 |
| 2512 | OPC_Decode, 241, 6, 69, // 4509: decode to MULSWZXrr using decoder 69 |
| 2513 | // 4509: } |
| 2514 | // 4509: } // switch Inst[47] |
| 2515 | // 4509: } |
| 2516 | // 4509: } // switch Inst[39] |
| 2517 | // 4509: } |
| 2518 | 152, 1, 53, // 4513: case 0x98: { |
| 2519 | OPC_SwitchField, 39, 1, // 4516: switch Inst[39] { |
| 2520 | 0, 23, // 4519: case 0x0: { |
| 2521 | OPC_SwitchField, 47, 1, // 4521: switch Inst[47] { |
| 2522 | 0, 8, // 4524: case 0x0: { |
| 2523 | OPC_CheckField, 0, 32, 0, // 4526: check Inst[31:0] == 0x0 |
| 2524 | OPC_Decode, 165, 5, 51, // 4530: decode to FADDDim using decoder 51 |
| 2525 | // 4530: } |
| 2526 | 1, 0, // 4534: case 0x1: { |
| 2527 | OPC_CheckField, 0, 32, 0, // 4536: check Inst[31:0] == 0x0 |
| 2528 | OPC_Decode, 167, 5, 52, // 4540: decode to FADDDrm using decoder 52 |
| 2529 | // 4540: } |
| 2530 | // 4540: } // switch Inst[47] |
| 2531 | // 4540: } |
| 2532 | 1, 0, // 4544: case 0x1: { |
| 2533 | OPC_SwitchField, 47, 1, // 4546: switch Inst[47] { |
| 2534 | 0, 8, // 4549: case 0x0: { |
| 2535 | OPC_CheckField, 0, 32, 0, // 4551: check Inst[31:0] == 0x0 |
| 2536 | OPC_Decode, 166, 5, 53, // 4555: decode to FADDDir using decoder 53 |
| 2537 | // 4555: } |
| 2538 | 1, 0, // 4559: case 0x1: { |
| 2539 | OPC_CheckField, 0, 32, 0, // 4561: check Inst[31:0] == 0x0 |
| 2540 | OPC_Decode, 168, 5, 54, // 4565: decode to FADDDrr using decoder 54 |
| 2541 | // 4565: } |
| 2542 | // 4565: } // switch Inst[47] |
| 2543 | // 4565: } |
| 2544 | // 4565: } // switch Inst[39] |
| 2545 | // 4565: } |
| 2546 | 153, 1, 53, // 4569: case 0x99: { |
| 2547 | OPC_SwitchField, 39, 1, // 4572: switch Inst[39] { |
| 2548 | 0, 23, // 4575: case 0x0: { |
| 2549 | OPC_SwitchField, 47, 1, // 4577: switch Inst[47] { |
| 2550 | 0, 8, // 4580: case 0x0: { |
| 2551 | OPC_CheckField, 0, 32, 0, // 4582: check Inst[31:0] == 0x0 |
| 2552 | OPC_Decode, 173, 5, 55, // 4586: decode to FADDSim using decoder 55 |
| 2553 | // 4586: } |
| 2554 | 1, 0, // 4590: case 0x1: { |
| 2555 | OPC_CheckField, 0, 32, 0, // 4592: check Inst[31:0] == 0x0 |
| 2556 | OPC_Decode, 175, 5, 56, // 4596: decode to FADDSrm using decoder 56 |
| 2557 | // 4596: } |
| 2558 | // 4596: } // switch Inst[47] |
| 2559 | // 4596: } |
| 2560 | 1, 0, // 4600: case 0x1: { |
| 2561 | OPC_SwitchField, 47, 1, // 4602: switch Inst[47] { |
| 2562 | 0, 8, // 4605: case 0x0: { |
| 2563 | OPC_CheckField, 0, 32, 0, // 4607: check Inst[31:0] == 0x0 |
| 2564 | OPC_Decode, 174, 5, 57, // 4611: decode to FADDSir using decoder 57 |
| 2565 | // 4611: } |
| 2566 | 1, 0, // 4615: case 0x1: { |
| 2567 | OPC_CheckField, 0, 32, 0, // 4617: check Inst[31:0] == 0x0 |
| 2568 | OPC_Decode, 176, 5, 58, // 4621: decode to FADDSrr using decoder 58 |
| 2569 | // 4621: } |
| 2570 | // 4621: } // switch Inst[47] |
| 2571 | // 4621: } |
| 2572 | // 4621: } // switch Inst[39] |
| 2573 | // 4621: } |
| 2574 | 154, 1, 53, // 4625: case 0x9a: { |
| 2575 | OPC_SwitchField, 39, 1, // 4628: switch Inst[39] { |
| 2576 | 0, 23, // 4631: case 0x0: { |
| 2577 | OPC_SwitchField, 47, 1, // 4633: switch Inst[47] { |
| 2578 | 0, 8, // 4636: case 0x0: { |
| 2579 | OPC_CheckField, 0, 32, 0, // 4638: check Inst[31:0] == 0x0 |
| 2580 | OPC_Decode, 218, 5, 51, // 4642: decode to FMULDim using decoder 51 |
| 2581 | // 4642: } |
| 2582 | 1, 0, // 4646: case 0x1: { |
| 2583 | OPC_CheckField, 0, 32, 0, // 4648: check Inst[31:0] == 0x0 |
| 2584 | OPC_Decode, 220, 5, 52, // 4652: decode to FMULDrm using decoder 52 |
| 2585 | // 4652: } |
| 2586 | // 4652: } // switch Inst[47] |
| 2587 | // 4652: } |
| 2588 | 1, 0, // 4656: case 0x1: { |
| 2589 | OPC_SwitchField, 47, 1, // 4658: switch Inst[47] { |
| 2590 | 0, 8, // 4661: case 0x0: { |
| 2591 | OPC_CheckField, 0, 32, 0, // 4663: check Inst[31:0] == 0x0 |
| 2592 | OPC_Decode, 219, 5, 53, // 4667: decode to FMULDir using decoder 53 |
| 2593 | // 4667: } |
| 2594 | 1, 0, // 4671: case 0x1: { |
| 2595 | OPC_CheckField, 0, 32, 0, // 4673: check Inst[31:0] == 0x0 |
| 2596 | OPC_Decode, 221, 5, 54, // 4677: decode to FMULDrr using decoder 54 |
| 2597 | // 4677: } |
| 2598 | // 4677: } // switch Inst[47] |
| 2599 | // 4677: } |
| 2600 | // 4677: } // switch Inst[39] |
| 2601 | // 4677: } |
| 2602 | 155, 1, 53, // 4681: case 0x9b: { |
| 2603 | OPC_SwitchField, 39, 1, // 4684: switch Inst[39] { |
| 2604 | 0, 23, // 4687: case 0x0: { |
| 2605 | OPC_SwitchField, 47, 1, // 4689: switch Inst[47] { |
| 2606 | 0, 8, // 4692: case 0x0: { |
| 2607 | OPC_CheckField, 0, 32, 0, // 4694: check Inst[31:0] == 0x0 |
| 2608 | OPC_Decode, 226, 5, 55, // 4698: decode to FMULSim using decoder 55 |
| 2609 | // 4698: } |
| 2610 | 1, 0, // 4702: case 0x1: { |
| 2611 | OPC_CheckField, 0, 32, 0, // 4704: check Inst[31:0] == 0x0 |
| 2612 | OPC_Decode, 228, 5, 56, // 4708: decode to FMULSrm using decoder 56 |
| 2613 | // 4708: } |
| 2614 | // 4708: } // switch Inst[47] |
| 2615 | // 4708: } |
| 2616 | 1, 0, // 4712: case 0x1: { |
| 2617 | OPC_SwitchField, 47, 1, // 4714: switch Inst[47] { |
| 2618 | 0, 8, // 4717: case 0x0: { |
| 2619 | OPC_CheckField, 0, 32, 0, // 4719: check Inst[31:0] == 0x0 |
| 2620 | OPC_Decode, 227, 5, 57, // 4723: decode to FMULSir using decoder 57 |
| 2621 | // 4723: } |
| 2622 | 1, 0, // 4727: case 0x1: { |
| 2623 | OPC_CheckField, 0, 32, 0, // 4729: check Inst[31:0] == 0x0 |
| 2624 | OPC_Decode, 229, 5, 58, // 4733: decode to FMULSrr using decoder 58 |
| 2625 | // 4733: } |
| 2626 | // 4733: } // switch Inst[47] |
| 2627 | // 4733: } |
| 2628 | // 4733: } // switch Inst[39] |
| 2629 | // 4733: } |
| 2630 | 156, 1, 54, // 4737: case 0x9c: { |
| 2631 | OPC_SwitchField, 0, 32, // 4740: switch Inst[31:0] { |
| 2632 | 0, 23, // 4743: case 0x0: { |
| 2633 | OPC_SwitchField, 47, 1, // 4745: switch Inst[47] { |
| 2634 | 0, 8, // 4748: case 0x0: { |
| 2635 | OPC_CheckField, 36, 4, 0, // 4750: check Inst[39:36] == 0x0 |
| 2636 | OPC_Decode, 244, 4, 70, // 4754: decode to CVTWDSXi using decoder 70 |
| 2637 | // 4754: } |
| 2638 | 1, 0, // 4758: case 0x1: { |
| 2639 | OPC_CheckField, 36, 4, 0, // 4760: check Inst[39:36] == 0x0 |
| 2640 | OPC_Decode, 245, 4, 71, // 4764: decode to CVTWDSXr using decoder 71 |
| 2641 | // 4764: } |
| 2642 | // 4764: } // switch Inst[47] |
| 2643 | // 4764: } |
| 2644 | 128, 1, 0, // 4768: case 0x80: { |
| 2645 | OPC_SwitchField, 47, 1, // 4771: switch Inst[47] { |
| 2646 | 0, 8, // 4774: case 0x0: { |
| 2647 | OPC_CheckField, 36, 4, 0, // 4776: check Inst[39:36] == 0x0 |
| 2648 | OPC_Decode, 246, 4, 70, // 4780: decode to CVTWDZXi using decoder 70 |
| 2649 | // 4780: } |
| 2650 | 1, 0, // 4784: case 0x1: { |
| 2651 | OPC_CheckField, 36, 4, 0, // 4786: check Inst[39:36] == 0x0 |
| 2652 | OPC_Decode, 247, 4, 71, // 4790: decode to CVTWDZXr using decoder 71 |
| 2653 | // 4790: } |
| 2654 | // 4790: } // switch Inst[47] |
| 2655 | // 4790: } |
| 2656 | // 4790: } // switch Inst[31:0] |
| 2657 | // 4790: } |
| 2658 | 157, 1, 54, // 4794: case 0x9d: { |
| 2659 | OPC_SwitchField, 0, 32, // 4797: switch Inst[31:0] { |
| 2660 | 0, 23, // 4800: case 0x0: { |
| 2661 | OPC_SwitchField, 47, 1, // 4802: switch Inst[47] { |
| 2662 | 0, 8, // 4805: case 0x0: { |
| 2663 | OPC_CheckField, 36, 4, 0, // 4807: check Inst[39:36] == 0x0 |
| 2664 | OPC_Decode, 248, 4, 70, // 4811: decode to CVTWSSXi using decoder 70 |
| 2665 | // 4811: } |
| 2666 | 1, 0, // 4815: case 0x1: { |
| 2667 | OPC_CheckField, 36, 4, 0, // 4817: check Inst[39:36] == 0x0 |
| 2668 | OPC_Decode, 249, 4, 72, // 4821: decode to CVTWSSXr using decoder 72 |
| 2669 | // 4821: } |
| 2670 | // 4821: } // switch Inst[47] |
| 2671 | // 4821: } |
| 2672 | 128, 1, 0, // 4825: case 0x80: { |
| 2673 | OPC_SwitchField, 47, 1, // 4828: switch Inst[47] { |
| 2674 | 0, 8, // 4831: case 0x0: { |
| 2675 | OPC_CheckField, 36, 4, 0, // 4833: check Inst[39:36] == 0x0 |
| 2676 | OPC_Decode, 250, 4, 70, // 4837: decode to CVTWSZXi using decoder 70 |
| 2677 | // 4837: } |
| 2678 | 1, 0, // 4841: case 0x1: { |
| 2679 | OPC_CheckField, 36, 4, 0, // 4843: check Inst[39:36] == 0x0 |
| 2680 | OPC_Decode, 251, 4, 72, // 4847: decode to CVTWSZXr using decoder 72 |
| 2681 | // 4847: } |
| 2682 | // 4847: } // switch Inst[47] |
| 2683 | // 4847: } |
| 2684 | // 4847: } // switch Inst[31:0] |
| 2685 | // 4847: } |
| 2686 | 158, 1, 31, // 4851: case 0x9e: { |
| 2687 | OPC_SwitchField, 47, 1, // 4854: switch Inst[47] { |
| 2688 | 0, 12, // 4857: case 0x0: { |
| 2689 | OPC_CheckField, 36, 4, 0, // 4859: check Inst[39:36] == 0x0 |
| 2690 | OPC_CheckField, 0, 32, 0, // 4863: check Inst[31:0] == 0x0 |
| 2691 | OPC_Decode, 232, 4, 73, // 4867: decode to CVTLDi using decoder 73 |
| 2692 | // 4867: } |
| 2693 | 1, 0, // 4871: case 0x1: { |
| 2694 | OPC_CheckField, 36, 4, 0, // 4873: check Inst[39:36] == 0x0 |
| 2695 | OPC_CheckField, 0, 32, 0, // 4877: check Inst[31:0] == 0x0 |
| 2696 | OPC_Decode, 233, 4, 74, // 4881: decode to CVTLDr using decoder 74 |
| 2697 | // 4881: } |
| 2698 | // 4881: } // switch Inst[47] |
| 2699 | // 4881: } |
| 2700 | 160, 1, 53, // 4885: case 0xa0: { |
| 2701 | OPC_SwitchField, 39, 1, // 4888: switch Inst[39] { |
| 2702 | 0, 23, // 4891: case 0x0: { |
| 2703 | OPC_SwitchField, 47, 1, // 4893: switch Inst[47] { |
| 2704 | 0, 8, // 4896: case 0x0: { |
| 2705 | OPC_CheckField, 0, 32, 0, // 4898: check Inst[31:0] == 0x0 |
| 2706 | OPC_Decode, 229, 34, 75, // 4902: decode to SCRizr using decoder 75 |
| 2707 | // 4902: } |
| 2708 | 1, 0, // 4906: case 0x1: { |
| 2709 | OPC_CheckField, 0, 32, 0, // 4908: check Inst[31:0] == 0x0 |
| 2710 | OPC_Decode, 231, 34, 76, // 4912: decode to SCRrzr using decoder 76 |
| 2711 | // 4912: } |
| 2712 | // 4912: } // switch Inst[47] |
| 2713 | // 4912: } |
| 2714 | 1, 0, // 4916: case 0x1: { |
| 2715 | OPC_SwitchField, 47, 1, // 4918: switch Inst[47] { |
| 2716 | 0, 8, // 4921: case 0x0: { |
| 2717 | OPC_CheckField, 0, 32, 0, // 4923: check Inst[31:0] == 0x0 |
| 2718 | OPC_Decode, 228, 34, 77, // 4927: decode to SCRirr using decoder 77 |
| 2719 | // 4927: } |
| 2720 | 1, 0, // 4931: case 0x1: { |
| 2721 | OPC_CheckField, 0, 32, 0, // 4933: check Inst[31:0] == 0x0 |
| 2722 | OPC_Decode, 230, 34, 78, // 4937: decode to SCRrrr using decoder 78 |
| 2723 | // 4937: } |
| 2724 | // 4937: } // switch Inst[47] |
| 2725 | // 4937: } |
| 2726 | // 4937: } // switch Inst[39] |
| 2727 | // 4937: } |
| 2728 | 162, 1, 31, // 4941: case 0xa2: { |
| 2729 | OPC_SwitchField, 47, 1, // 4944: switch Inst[47] { |
| 2730 | 0, 12, // 4947: case 0x0: { |
| 2731 | OPC_CheckField, 39, 1, 0, // 4949: check Inst[39] == 0x0 |
| 2732 | OPC_CheckField, 0, 32, 0, // 4953: check Inst[31:0] == 0x0 |
| 2733 | OPC_Decode, 200, 5, 51, // 4957: decode to FIDCRii using decoder 51 |
| 2734 | // 4957: } |
| 2735 | 1, 0, // 4961: case 0x1: { |
| 2736 | OPC_CheckField, 39, 1, 0, // 4963: check Inst[39] == 0x0 |
| 2737 | OPC_CheckField, 0, 32, 0, // 4967: check Inst[31:0] == 0x0 |
| 2738 | OPC_Decode, 201, 5, 52, // 4971: decode to FIDCRri using decoder 52 |
| 2739 | // 4971: } |
| 2740 | // 4971: } // switch Inst[47] |
| 2741 | // 4971: } |
| 2742 | 164, 1, 37, // 4975: case 0xa4: { |
| 2743 | OPC_SwitchField, 39, 1, // 4978: switch Inst[39] { |
| 2744 | 0, 15, // 4981: case 0x0: { |
| 2745 | OPC_SwitchField, 47, 1, // 4983: switch Inst[47] { |
| 2746 | 0, 4, // 4986: case 0x0: { |
| 2747 | OPC_Decode, 218, 35, 63, // 4988: decode to TS3AMzii using decoder 63 |
| 2748 | // 4988: } |
| 2749 | 1, 0, // 4992: case 0x1: { |
| 2750 | OPC_Decode, 219, 35, 63, // 4994: decode to TS3AMzir using decoder 63 |
| 2751 | // 4994: } |
| 2752 | // 4994: } // switch Inst[47] |
| 2753 | // 4994: } |
| 2754 | 1, 0, // 4998: case 0x1: { |
| 2755 | OPC_SwitchField, 47, 1, // 5000: switch Inst[47] { |
| 2756 | 0, 4, // 5003: case 0x0: { |
| 2757 | OPC_Decode, 216, 35, 63, // 5005: decode to TS3AMrii using decoder 63 |
| 2758 | // 5005: } |
| 2759 | 1, 0, // 5009: case 0x1: { |
| 2760 | OPC_Decode, 217, 35, 63, // 5011: decode to TS3AMrir using decoder 63 |
| 2761 | // 5011: } |
| 2762 | // 5011: } // switch Inst[47] |
| 2763 | // 5011: } |
| 2764 | // 5011: } // switch Inst[39] |
| 2765 | // 5011: } |
| 2766 | 166, 1, 37, // 5015: case 0xa6: { |
| 2767 | OPC_SwitchField, 39, 1, // 5018: switch Inst[39] { |
| 2768 | 0, 15, // 5021: case 0x0: { |
| 2769 | OPC_SwitchField, 47, 1, // 5023: switch Inst[47] { |
| 2770 | 0, 4, // 5026: case 0x0: { |
| 2771 | OPC_Decode, 129, 3, 63, // 5028: decode to ATMAMzii using decoder 63 |
| 2772 | // 5028: } |
| 2773 | 1, 0, // 5032: case 0x1: { |
| 2774 | OPC_Decode, 130, 3, 63, // 5034: decode to ATMAMzir using decoder 63 |
| 2775 | // 5034: } |
| 2776 | // 5034: } // switch Inst[47] |
| 2777 | // 5034: } |
| 2778 | 1, 0, // 5038: case 0x1: { |
| 2779 | OPC_SwitchField, 47, 1, // 5040: switch Inst[47] { |
| 2780 | 0, 4, // 5043: case 0x0: { |
| 2781 | OPC_Decode, 255, 2, 63, // 5045: decode to ATMAMrii using decoder 63 |
| 2782 | // 5045: } |
| 2783 | 1, 0, // 5049: case 0x1: { |
| 2784 | OPC_Decode, 128, 3, 63, // 5051: decode to ATMAMrir using decoder 63 |
| 2785 | // 5051: } |
| 2786 | // 5051: } // switch Inst[47] |
| 2787 | // 5051: } |
| 2788 | // 5051: } // switch Inst[39] |
| 2789 | // 5051: } |
| 2790 | 168, 1, 53, // 5055: case 0xa8: { |
| 2791 | OPC_SwitchField, 39, 1, // 5058: switch Inst[39] { |
| 2792 | 0, 23, // 5061: case 0x0: { |
| 2793 | OPC_SwitchField, 47, 1, // 5063: switch Inst[47] { |
| 2794 | 0, 8, // 5066: case 0x0: { |
| 2795 | OPC_CheckField, 0, 32, 0, // 5068: check Inst[31:0] == 0x0 |
| 2796 | OPC_Decode, 252, 6, 51, // 5072: decode to NNDim using decoder 51 |
| 2797 | // 5072: } |
| 2798 | 1, 0, // 5076: case 0x1: { |
| 2799 | OPC_CheckField, 0, 32, 0, // 5078: check Inst[31:0] == 0x0 |
| 2800 | OPC_Decode, 254, 6, 52, // 5082: decode to NNDrm using decoder 52 |
| 2801 | // 5082: } |
| 2802 | // 5082: } // switch Inst[47] |
| 2803 | // 5082: } |
| 2804 | 1, 0, // 5086: case 0x1: { |
| 2805 | OPC_SwitchField, 47, 1, // 5088: switch Inst[47] { |
| 2806 | 0, 8, // 5091: case 0x0: { |
| 2807 | OPC_CheckField, 0, 32, 0, // 5093: check Inst[31:0] == 0x0 |
| 2808 | OPC_Decode, 253, 6, 53, // 5097: decode to NNDir using decoder 53 |
| 2809 | // 5097: } |
| 2810 | 1, 0, // 5101: case 0x1: { |
| 2811 | OPC_CheckField, 0, 32, 0, // 5103: check Inst[31:0] == 0x0 |
| 2812 | OPC_Decode, 255, 6, 54, // 5107: decode to NNDrr using decoder 54 |
| 2813 | // 5107: } |
| 2814 | // 5107: } // switch Inst[47] |
| 2815 | // 5107: } |
| 2816 | // 5107: } // switch Inst[39] |
| 2817 | // 5107: } |
| 2818 | 170, 1, 53, // 5111: case 0xaa: { |
| 2819 | OPC_SwitchField, 39, 1, // 5114: switch Inst[39] { |
| 2820 | 0, 23, // 5117: case 0x0: { |
| 2821 | OPC_SwitchField, 47, 1, // 5119: switch Inst[47] { |
| 2822 | 0, 8, // 5122: case 0x0: { |
| 2823 | OPC_CheckField, 0, 32, 0, // 5124: check Inst[31:0] == 0x0 |
| 2824 | OPC_Decode, 216, 4, 51, // 5128: decode to CMPULim using decoder 51 |
| 2825 | // 5128: } |
| 2826 | 1, 0, // 5132: case 0x1: { |
| 2827 | OPC_CheckField, 0, 32, 0, // 5134: check Inst[31:0] == 0x0 |
| 2828 | OPC_Decode, 218, 4, 52, // 5138: decode to CMPULrm using decoder 52 |
| 2829 | // 5138: } |
| 2830 | // 5138: } // switch Inst[47] |
| 2831 | // 5138: } |
| 2832 | 1, 0, // 5142: case 0x1: { |
| 2833 | OPC_SwitchField, 47, 1, // 5144: switch Inst[47] { |
| 2834 | 0, 8, // 5147: case 0x0: { |
| 2835 | OPC_CheckField, 0, 32, 0, // 5149: check Inst[31:0] == 0x0 |
| 2836 | OPC_Decode, 217, 4, 53, // 5153: decode to CMPULir using decoder 53 |
| 2837 | // 5153: } |
| 2838 | 1, 0, // 5157: case 0x1: { |
| 2839 | OPC_CheckField, 0, 32, 0, // 5159: check Inst[31:0] == 0x0 |
| 2840 | OPC_Decode, 219, 4, 54, // 5163: decode to CMPULrr using decoder 54 |
| 2841 | // 5163: } |
| 2842 | // 5163: } // switch Inst[47] |
| 2843 | // 5163: } |
| 2844 | // 5163: } // switch Inst[39] |
| 2845 | // 5163: } |
| 2846 | 171, 1, 53, // 5167: case 0xab: { |
| 2847 | OPC_SwitchField, 39, 1, // 5170: switch Inst[39] { |
| 2848 | 0, 23, // 5173: case 0x0: { |
| 2849 | OPC_SwitchField, 47, 1, // 5175: switch Inst[47] { |
| 2850 | 0, 8, // 5178: case 0x0: { |
| 2851 | OPC_CheckField, 0, 32, 0, // 5180: check Inst[31:0] == 0x0 |
| 2852 | OPC_Decode, 220, 4, 66, // 5184: decode to CMPUWim using decoder 66 |
| 2853 | // 5184: } |
| 2854 | 1, 0, // 5188: case 0x1: { |
| 2855 | OPC_CheckField, 0, 32, 0, // 5190: check Inst[31:0] == 0x0 |
| 2856 | OPC_Decode, 222, 4, 67, // 5194: decode to CMPUWrm using decoder 67 |
| 2857 | // 5194: } |
| 2858 | // 5194: } // switch Inst[47] |
| 2859 | // 5194: } |
| 2860 | 1, 0, // 5198: case 0x1: { |
| 2861 | OPC_SwitchField, 47, 1, // 5200: switch Inst[47] { |
| 2862 | 0, 8, // 5203: case 0x0: { |
| 2863 | OPC_CheckField, 0, 32, 0, // 5205: check Inst[31:0] == 0x0 |
| 2864 | OPC_Decode, 221, 4, 79, // 5209: decode to CMPUWir using decoder 79 |
| 2865 | // 5209: } |
| 2866 | 1, 0, // 5213: case 0x1: { |
| 2867 | OPC_CheckField, 0, 32, 0, // 5215: check Inst[31:0] == 0x0 |
| 2868 | OPC_Decode, 223, 4, 69, // 5219: decode to CMPUWrr using decoder 69 |
| 2869 | // 5219: } |
| 2870 | // 5219: } // switch Inst[47] |
| 2871 | // 5219: } |
| 2872 | // 5219: } // switch Inst[39] |
| 2873 | // 5219: } |
| 2874 | 172, 1, 53, // 5223: case 0xac: { |
| 2875 | OPC_SwitchField, 39, 1, // 5226: switch Inst[39] { |
| 2876 | 0, 23, // 5229: case 0x0: { |
| 2877 | OPC_SwitchField, 47, 1, // 5231: switch Inst[47] { |
| 2878 | 0, 8, // 5234: case 0x0: { |
| 2879 | OPC_CheckField, 0, 32, 0, // 5236: check Inst[31:0] == 0x0 |
| 2880 | OPC_Decode, 222, 6, 59, // 5240: decode to MRGim using decoder 59 |
| 2881 | // 5240: } |
| 2882 | 1, 0, // 5244: case 0x1: { |
| 2883 | OPC_CheckField, 0, 32, 0, // 5246: check Inst[31:0] == 0x0 |
| 2884 | OPC_Decode, 224, 6, 60, // 5250: decode to MRGrm using decoder 60 |
| 2885 | // 5250: } |
| 2886 | // 5250: } // switch Inst[47] |
| 2887 | // 5250: } |
| 2888 | 1, 0, // 5254: case 0x1: { |
| 2889 | OPC_SwitchField, 47, 1, // 5256: switch Inst[47] { |
| 2890 | 0, 8, // 5259: case 0x0: { |
| 2891 | OPC_CheckField, 0, 32, 0, // 5261: check Inst[31:0] == 0x0 |
| 2892 | OPC_Decode, 223, 6, 61, // 5265: decode to MRGir using decoder 61 |
| 2893 | // 5265: } |
| 2894 | 1, 0, // 5269: case 0x1: { |
| 2895 | OPC_CheckField, 0, 32, 0, // 5271: check Inst[31:0] == 0x0 |
| 2896 | OPC_Decode, 225, 6, 62, // 5275: decode to MRGrr using decoder 62 |
| 2897 | // 5275: } |
| 2898 | // 5275: } // switch Inst[47] |
| 2899 | // 5275: } |
| 2900 | // 5275: } // switch Inst[39] |
| 2901 | // 5275: } |
| 2902 | 174, 1, 53, // 5279: case 0xae: { |
| 2903 | OPC_SwitchField, 39, 1, // 5282: switch Inst[39] { |
| 2904 | 0, 23, // 5285: case 0x0: { |
| 2905 | OPC_SwitchField, 47, 1, // 5287: switch Inst[47] { |
| 2906 | 0, 8, // 5290: case 0x0: { |
| 2907 | OPC_CheckField, 0, 32, 0, // 5292: check Inst[31:0] == 0x0 |
| 2908 | OPC_Decode, 242, 34, 34, // 5296: decode to SLALmi using decoder 34 |
| 2909 | // 5296: } |
| 2910 | 1, 0, // 5300: case 0x1: { |
| 2911 | OPC_CheckField, 0, 32, 0, // 5302: check Inst[31:0] == 0x0 |
| 2912 | OPC_Decode, 243, 34, 80, // 5306: decode to SLALmr using decoder 80 |
| 2913 | // 5306: } |
| 2914 | // 5306: } // switch Inst[47] |
| 2915 | // 5306: } |
| 2916 | 1, 0, // 5310: case 0x1: { |
| 2917 | OPC_SwitchField, 47, 1, // 5312: switch Inst[47] { |
| 2918 | 0, 8, // 5315: case 0x0: { |
| 2919 | OPC_CheckField, 0, 32, 0, // 5317: check Inst[31:0] == 0x0 |
| 2920 | OPC_Decode, 244, 34, 35, // 5321: decode to SLALri using decoder 35 |
| 2921 | // 5321: } |
| 2922 | 1, 0, // 5325: case 0x1: { |
| 2923 | OPC_CheckField, 0, 32, 0, // 5327: check Inst[31:0] == 0x0 |
| 2924 | OPC_Decode, 245, 34, 81, // 5331: decode to SLALrr using decoder 81 |
| 2925 | // 5331: } |
| 2926 | // 5331: } // switch Inst[47] |
| 2927 | // 5331: } |
| 2928 | // 5331: } // switch Inst[39] |
| 2929 | // 5331: } |
| 2930 | 176, 1, 53, // 5335: case 0xb0: { |
| 2931 | OPC_SwitchField, 39, 1, // 5338: switch Inst[39] { |
| 2932 | 0, 23, // 5341: case 0x0: { |
| 2933 | OPC_SwitchField, 47, 1, // 5343: switch Inst[47] { |
| 2934 | 0, 8, // 5346: case 0x0: { |
| 2935 | OPC_CheckField, 0, 32, 0, // 5348: check Inst[31:0] == 0x0 |
| 2936 | OPC_Decode, 189, 35, 51, // 5352: decode to SUBULim using decoder 51 |
| 2937 | // 5352: } |
| 2938 | 1, 0, // 5356: case 0x1: { |
| 2939 | OPC_CheckField, 0, 32, 0, // 5358: check Inst[31:0] == 0x0 |
| 2940 | OPC_Decode, 191, 35, 52, // 5362: decode to SUBULrm using decoder 52 |
| 2941 | // 5362: } |
| 2942 | // 5362: } // switch Inst[47] |
| 2943 | // 5362: } |
| 2944 | 1, 0, // 5366: case 0x1: { |
| 2945 | OPC_SwitchField, 47, 1, // 5368: switch Inst[47] { |
| 2946 | 0, 8, // 5371: case 0x0: { |
| 2947 | OPC_CheckField, 0, 32, 0, // 5373: check Inst[31:0] == 0x0 |
| 2948 | OPC_Decode, 190, 35, 53, // 5377: decode to SUBULir using decoder 53 |
| 2949 | // 5377: } |
| 2950 | 1, 0, // 5381: case 0x1: { |
| 2951 | OPC_CheckField, 0, 32, 0, // 5383: check Inst[31:0] == 0x0 |
| 2952 | OPC_Decode, 192, 35, 54, // 5387: decode to SUBULrr using decoder 54 |
| 2953 | // 5387: } |
| 2954 | // 5387: } // switch Inst[47] |
| 2955 | // 5387: } |
| 2956 | // 5387: } // switch Inst[39] |
| 2957 | // 5387: } |
| 2958 | 177, 1, 53, // 5391: case 0xb1: { |
| 2959 | OPC_SwitchField, 39, 1, // 5394: switch Inst[39] { |
| 2960 | 0, 23, // 5397: case 0x0: { |
| 2961 | OPC_SwitchField, 47, 1, // 5399: switch Inst[47] { |
| 2962 | 0, 8, // 5402: case 0x0: { |
| 2963 | OPC_CheckField, 0, 32, 0, // 5404: check Inst[31:0] == 0x0 |
| 2964 | OPC_Decode, 193, 35, 66, // 5408: decode to SUBUWim using decoder 66 |
| 2965 | // 5408: } |
| 2966 | 1, 0, // 5412: case 0x1: { |
| 2967 | OPC_CheckField, 0, 32, 0, // 5414: check Inst[31:0] == 0x0 |
| 2968 | OPC_Decode, 195, 35, 67, // 5418: decode to SUBUWrm using decoder 67 |
| 2969 | // 5418: } |
| 2970 | // 5418: } // switch Inst[47] |
| 2971 | // 5418: } |
| 2972 | 1, 0, // 5422: case 0x1: { |
| 2973 | OPC_SwitchField, 47, 1, // 5424: switch Inst[47] { |
| 2974 | 0, 8, // 5427: case 0x0: { |
| 2975 | OPC_CheckField, 0, 32, 0, // 5429: check Inst[31:0] == 0x0 |
| 2976 | OPC_Decode, 194, 35, 79, // 5433: decode to SUBUWir using decoder 79 |
| 2977 | // 5433: } |
| 2978 | 1, 0, // 5437: case 0x1: { |
| 2979 | OPC_CheckField, 0, 32, 0, // 5439: check Inst[31:0] == 0x0 |
| 2980 | OPC_Decode, 196, 35, 69, // 5443: decode to SUBUWrr using decoder 69 |
| 2981 | // 5443: } |
| 2982 | // 5443: } // switch Inst[47] |
| 2983 | // 5443: } |
| 2984 | // 5443: } // switch Inst[39] |
| 2985 | // 5443: } |
| 2986 | 178, 1, 53, // 5447: case 0xb2: { |
| 2987 | OPC_SwitchField, 39, 1, // 5450: switch Inst[39] { |
| 2988 | 0, 23, // 5453: case 0x0: { |
| 2989 | OPC_SwitchField, 47, 1, // 5455: switch Inst[47] { |
| 2990 | 0, 8, // 5458: case 0x0: { |
| 2991 | OPC_CheckField, 0, 32, 0, // 5460: check Inst[31:0] == 0x0 |
| 2992 | OPC_Decode, 230, 2, 51, // 5464: decode to ADDSLim using decoder 51 |
| 2993 | // 5464: } |
| 2994 | 1, 0, // 5468: case 0x1: { |
| 2995 | OPC_CheckField, 0, 32, 0, // 5470: check Inst[31:0] == 0x0 |
| 2996 | OPC_Decode, 232, 2, 52, // 5474: decode to ADDSLrm using decoder 52 |
| 2997 | // 5474: } |
| 2998 | // 5474: } // switch Inst[47] |
| 2999 | // 5474: } |
| 3000 | 1, 0, // 5478: case 0x1: { |
| 3001 | OPC_SwitchField, 47, 1, // 5480: switch Inst[47] { |
| 3002 | 0, 8, // 5483: case 0x0: { |
| 3003 | OPC_CheckField, 0, 32, 0, // 5485: check Inst[31:0] == 0x0 |
| 3004 | OPC_Decode, 231, 2, 65, // 5489: decode to ADDSLri using decoder 65 |
| 3005 | // 5489: } |
| 3006 | 1, 0, // 5493: case 0x1: { |
| 3007 | OPC_CheckField, 0, 32, 0, // 5495: check Inst[31:0] == 0x0 |
| 3008 | OPC_Decode, 233, 2, 54, // 5499: decode to ADDSLrr using decoder 54 |
| 3009 | // 5499: } |
| 3010 | // 5499: } // switch Inst[47] |
| 3011 | // 5499: } |
| 3012 | // 5499: } // switch Inst[39] |
| 3013 | // 5499: } |
| 3014 | 180, 1, 53, // 5503: case 0xb4: { |
| 3015 | OPC_SwitchField, 39, 1, // 5506: switch Inst[39] { |
| 3016 | 0, 23, // 5509: case 0x0: { |
| 3017 | OPC_SwitchField, 47, 1, // 5511: switch Inst[47] { |
| 3018 | 0, 8, // 5514: case 0x0: { |
| 3019 | OPC_CheckField, 0, 32, 0, // 5516: check Inst[31:0] == 0x0 |
| 3020 | OPC_Decode, 181, 35, 66, // 5520: decode to SUBSWSXim using decoder 66 |
| 3021 | // 5520: } |
| 3022 | 1, 0, // 5524: case 0x1: { |
| 3023 | OPC_CheckField, 0, 32, 0, // 5526: check Inst[31:0] == 0x0 |
| 3024 | OPC_Decode, 183, 35, 67, // 5530: decode to SUBSWSXrm using decoder 67 |
| 3025 | // 5530: } |
| 3026 | // 5530: } // switch Inst[47] |
| 3027 | // 5530: } |
| 3028 | 1, 0, // 5534: case 0x1: { |
| 3029 | OPC_SwitchField, 47, 1, // 5536: switch Inst[47] { |
| 3030 | 0, 8, // 5539: case 0x0: { |
| 3031 | OPC_CheckField, 0, 32, 0, // 5541: check Inst[31:0] == 0x0 |
| 3032 | OPC_Decode, 182, 35, 79, // 5545: decode to SUBSWSXir using decoder 79 |
| 3033 | // 5545: } |
| 3034 | 1, 0, // 5549: case 0x1: { |
| 3035 | OPC_CheckField, 0, 32, 0, // 5551: check Inst[31:0] == 0x0 |
| 3036 | OPC_Decode, 184, 35, 69, // 5555: decode to SUBSWSXrr using decoder 69 |
| 3037 | // 5555: } |
| 3038 | // 5555: } // switch Inst[47] |
| 3039 | // 5555: } |
| 3040 | // 5555: } // switch Inst[39] |
| 3041 | // 5555: } |
| 3042 | 181, 1, 53, // 5559: case 0xb5: { |
| 3043 | OPC_SwitchField, 39, 1, // 5562: switch Inst[39] { |
| 3044 | 0, 23, // 5565: case 0x0: { |
| 3045 | OPC_SwitchField, 47, 1, // 5567: switch Inst[47] { |
| 3046 | 0, 8, // 5570: case 0x0: { |
| 3047 | OPC_CheckField, 0, 32, 0, // 5572: check Inst[31:0] == 0x0 |
| 3048 | OPC_Decode, 185, 35, 66, // 5576: decode to SUBSWZXim using decoder 66 |
| 3049 | // 5576: } |
| 3050 | 1, 0, // 5580: case 0x1: { |
| 3051 | OPC_CheckField, 0, 32, 0, // 5582: check Inst[31:0] == 0x0 |
| 3052 | OPC_Decode, 187, 35, 67, // 5586: decode to SUBSWZXrm using decoder 67 |
| 3053 | // 5586: } |
| 3054 | // 5586: } // switch Inst[47] |
| 3055 | // 5586: } |
| 3056 | 1, 0, // 5590: case 0x1: { |
| 3057 | OPC_SwitchField, 47, 1, // 5592: switch Inst[47] { |
| 3058 | 0, 8, // 5595: case 0x0: { |
| 3059 | OPC_CheckField, 0, 32, 0, // 5597: check Inst[31:0] == 0x0 |
| 3060 | OPC_Decode, 186, 35, 79, // 5601: decode to SUBSWZXir using decoder 79 |
| 3061 | // 5601: } |
| 3062 | 1, 0, // 5605: case 0x1: { |
| 3063 | OPC_CheckField, 0, 32, 0, // 5607: check Inst[31:0] == 0x0 |
| 3064 | OPC_Decode, 188, 35, 69, // 5611: decode to SUBSWZXrr using decoder 69 |
| 3065 | // 5611: } |
| 3066 | // 5611: } // switch Inst[47] |
| 3067 | // 5611: } |
| 3068 | // 5611: } // switch Inst[39] |
| 3069 | // 5611: } |
| 3070 | 182, 1, 53, // 5615: case 0xb6: { |
| 3071 | OPC_SwitchField, 39, 1, // 5618: switch Inst[39] { |
| 3072 | 0, 23, // 5621: case 0x0: { |
| 3073 | OPC_SwitchField, 47, 1, // 5623: switch Inst[47] { |
| 3074 | 0, 8, // 5626: case 0x0: { |
| 3075 | OPC_CheckField, 0, 32, 0, // 5628: check Inst[31:0] == 0x0 |
| 3076 | OPC_Decode, 177, 35, 51, // 5632: decode to SUBSLim using decoder 51 |
| 3077 | // 5632: } |
| 3078 | 1, 0, // 5636: case 0x1: { |
| 3079 | OPC_CheckField, 0, 32, 0, // 5638: check Inst[31:0] == 0x0 |
| 3080 | OPC_Decode, 179, 35, 52, // 5642: decode to SUBSLrm using decoder 52 |
| 3081 | // 5642: } |
| 3082 | // 5642: } // switch Inst[47] |
| 3083 | // 5642: } |
| 3084 | 1, 0, // 5646: case 0x1: { |
| 3085 | OPC_SwitchField, 47, 1, // 5648: switch Inst[47] { |
| 3086 | 0, 8, // 5651: case 0x0: { |
| 3087 | OPC_CheckField, 0, 32, 0, // 5653: check Inst[31:0] == 0x0 |
| 3088 | OPC_Decode, 178, 35, 53, // 5657: decode to SUBSLir using decoder 53 |
| 3089 | // 5657: } |
| 3090 | 1, 0, // 5661: case 0x1: { |
| 3091 | OPC_CheckField, 0, 32, 0, // 5663: check Inst[31:0] == 0x0 |
| 3092 | OPC_Decode, 180, 35, 54, // 5667: decode to SUBSLrr using decoder 54 |
| 3093 | // 5667: } |
| 3094 | // 5667: } // switch Inst[47] |
| 3095 | // 5667: } |
| 3096 | // 5667: } // switch Inst[39] |
| 3097 | // 5667: } |
| 3098 | 184, 1, 53, // 5671: case 0xb8: { |
| 3099 | OPC_SwitchField, 39, 1, // 5674: switch Inst[39] { |
| 3100 | 0, 23, // 5677: case 0x0: { |
| 3101 | OPC_SwitchField, 47, 1, // 5679: switch Inst[47] { |
| 3102 | 0, 8, // 5682: case 0x0: { |
| 3103 | OPC_CheckField, 0, 32, 0, // 5684: check Inst[31:0] == 0x0 |
| 3104 | OPC_Decode, 230, 5, 51, // 5688: decode to FSUBDim using decoder 51 |
| 3105 | // 5688: } |
| 3106 | 1, 0, // 5692: case 0x1: { |
| 3107 | OPC_CheckField, 0, 32, 0, // 5694: check Inst[31:0] == 0x0 |
| 3108 | OPC_Decode, 232, 5, 52, // 5698: decode to FSUBDrm using decoder 52 |
| 3109 | // 5698: } |
| 3110 | // 5698: } // switch Inst[47] |
| 3111 | // 5698: } |
| 3112 | 1, 0, // 5702: case 0x1: { |
| 3113 | OPC_SwitchField, 47, 1, // 5704: switch Inst[47] { |
| 3114 | 0, 8, // 5707: case 0x0: { |
| 3115 | OPC_CheckField, 0, 32, 0, // 5709: check Inst[31:0] == 0x0 |
| 3116 | OPC_Decode, 231, 5, 53, // 5713: decode to FSUBDir using decoder 53 |
| 3117 | // 5713: } |
| 3118 | 1, 0, // 5717: case 0x1: { |
| 3119 | OPC_CheckField, 0, 32, 0, // 5719: check Inst[31:0] == 0x0 |
| 3120 | OPC_Decode, 233, 5, 54, // 5723: decode to FSUBDrr using decoder 54 |
| 3121 | // 5723: } |
| 3122 | // 5723: } // switch Inst[47] |
| 3123 | // 5723: } |
| 3124 | // 5723: } // switch Inst[39] |
| 3125 | // 5723: } |
| 3126 | 185, 1, 53, // 5727: case 0xb9: { |
| 3127 | OPC_SwitchField, 39, 1, // 5730: switch Inst[39] { |
| 3128 | 0, 23, // 5733: case 0x0: { |
| 3129 | OPC_SwitchField, 47, 1, // 5735: switch Inst[47] { |
| 3130 | 0, 8, // 5738: case 0x0: { |
| 3131 | OPC_CheckField, 0, 32, 0, // 5740: check Inst[31:0] == 0x0 |
| 3132 | OPC_Decode, 238, 5, 55, // 5744: decode to FSUBSim using decoder 55 |
| 3133 | // 5744: } |
| 3134 | 1, 0, // 5748: case 0x1: { |
| 3135 | OPC_CheckField, 0, 32, 0, // 5750: check Inst[31:0] == 0x0 |
| 3136 | OPC_Decode, 240, 5, 56, // 5754: decode to FSUBSrm using decoder 56 |
| 3137 | // 5754: } |
| 3138 | // 5754: } // switch Inst[47] |
| 3139 | // 5754: } |
| 3140 | 1, 0, // 5758: case 0x1: { |
| 3141 | OPC_SwitchField, 47, 1, // 5760: switch Inst[47] { |
| 3142 | 0, 8, // 5763: case 0x0: { |
| 3143 | OPC_CheckField, 0, 32, 0, // 5765: check Inst[31:0] == 0x0 |
| 3144 | OPC_Decode, 239, 5, 57, // 5769: decode to FSUBSir using decoder 57 |
| 3145 | // 5769: } |
| 3146 | 1, 0, // 5773: case 0x1: { |
| 3147 | OPC_CheckField, 0, 32, 0, // 5775: check Inst[31:0] == 0x0 |
| 3148 | OPC_Decode, 241, 5, 58, // 5779: decode to FSUBSrr using decoder 58 |
| 3149 | // 5779: } |
| 3150 | // 5779: } // switch Inst[47] |
| 3151 | // 5779: } |
| 3152 | // 5779: } // switch Inst[39] |
| 3153 | // 5779: } |
| 3154 | 186, 1, 53, // 5783: case 0xba: { |
| 3155 | OPC_SwitchField, 39, 1, // 5786: switch Inst[39] { |
| 3156 | 0, 23, // 5789: case 0x0: { |
| 3157 | OPC_SwitchField, 47, 1, // 5791: switch Inst[47] { |
| 3158 | 0, 8, // 5794: case 0x0: { |
| 3159 | OPC_CheckField, 0, 32, 0, // 5796: check Inst[31:0] == 0x0 |
| 3160 | OPC_Decode, 189, 5, 51, // 5800: decode to FDIVDim using decoder 51 |
| 3161 | // 5800: } |
| 3162 | 1, 0, // 5804: case 0x1: { |
| 3163 | OPC_CheckField, 0, 32, 0, // 5806: check Inst[31:0] == 0x0 |
| 3164 | OPC_Decode, 191, 5, 52, // 5810: decode to FDIVDrm using decoder 52 |
| 3165 | // 5810: } |
| 3166 | // 5810: } // switch Inst[47] |
| 3167 | // 5810: } |
| 3168 | 1, 0, // 5814: case 0x1: { |
| 3169 | OPC_SwitchField, 47, 1, // 5816: switch Inst[47] { |
| 3170 | 0, 8, // 5819: case 0x0: { |
| 3171 | OPC_CheckField, 0, 32, 0, // 5821: check Inst[31:0] == 0x0 |
| 3172 | OPC_Decode, 190, 5, 53, // 5825: decode to FDIVDir using decoder 53 |
| 3173 | // 5825: } |
| 3174 | 1, 0, // 5829: case 0x1: { |
| 3175 | OPC_CheckField, 0, 32, 0, // 5831: check Inst[31:0] == 0x0 |
| 3176 | OPC_Decode, 192, 5, 54, // 5835: decode to FDIVDrr using decoder 54 |
| 3177 | // 5835: } |
| 3178 | // 5835: } // switch Inst[47] |
| 3179 | // 5835: } |
| 3180 | // 5835: } // switch Inst[39] |
| 3181 | // 5835: } |
| 3182 | 187, 1, 53, // 5839: case 0xbb: { |
| 3183 | OPC_SwitchField, 39, 1, // 5842: switch Inst[39] { |
| 3184 | 0, 23, // 5845: case 0x0: { |
| 3185 | OPC_SwitchField, 47, 1, // 5847: switch Inst[47] { |
| 3186 | 0, 8, // 5850: case 0x0: { |
| 3187 | OPC_CheckField, 0, 32, 0, // 5852: check Inst[31:0] == 0x0 |
| 3188 | OPC_Decode, 193, 5, 55, // 5856: decode to FDIVSim using decoder 55 |
| 3189 | // 5856: } |
| 3190 | 1, 0, // 5860: case 0x1: { |
| 3191 | OPC_CheckField, 0, 32, 0, // 5862: check Inst[31:0] == 0x0 |
| 3192 | OPC_Decode, 195, 5, 56, // 5866: decode to FDIVSrm using decoder 56 |
| 3193 | // 5866: } |
| 3194 | // 5866: } // switch Inst[47] |
| 3195 | // 5866: } |
| 3196 | 1, 0, // 5870: case 0x1: { |
| 3197 | OPC_SwitchField, 47, 1, // 5872: switch Inst[47] { |
| 3198 | 0, 8, // 5875: case 0x0: { |
| 3199 | OPC_CheckField, 0, 32, 0, // 5877: check Inst[31:0] == 0x0 |
| 3200 | OPC_Decode, 194, 5, 57, // 5881: decode to FDIVSir using decoder 57 |
| 3201 | // 5881: } |
| 3202 | 1, 0, // 5885: case 0x1: { |
| 3203 | OPC_CheckField, 0, 32, 0, // 5887: check Inst[31:0] == 0x0 |
| 3204 | OPC_Decode, 196, 5, 58, // 5891: decode to FDIVSrr using decoder 58 |
| 3205 | // 5891: } |
| 3206 | // 5891: } // switch Inst[47] |
| 3207 | // 5891: } |
| 3208 | // 5891: } // switch Inst[39] |
| 3209 | // 5891: } |
| 3210 | 188, 1, 23, // 5895: case 0xbc: { |
| 3211 | OPC_SwitchField, 47, 1, // 5898: switch Inst[47] { |
| 3212 | 0, 8, // 5901: case 0x0: { |
| 3213 | OPC_CheckField, 0, 40, 0, // 5903: check Inst[39:0] == 0x0 |
| 3214 | OPC_Decode, 230, 4, 5, // 5907: decode to CVTDWi using decoder 5 |
| 3215 | // 5907: } |
| 3216 | 1, 0, // 5911: case 0x1: { |
| 3217 | OPC_CheckField, 0, 40, 0, // 5913: check Inst[39:0] == 0x0 |
| 3218 | OPC_Decode, 231, 4, 82, // 5917: decode to CVTDWr using decoder 82 |
| 3219 | // 5917: } |
| 3220 | // 5917: } // switch Inst[47] |
| 3221 | // 5917: } |
| 3222 | 189, 1, 23, // 5921: case 0xbd: { |
| 3223 | OPC_SwitchField, 47, 1, // 5924: switch Inst[47] { |
| 3224 | 0, 8, // 5927: case 0x0: { |
| 3225 | OPC_CheckField, 0, 40, 0, // 5929: check Inst[39:0] == 0x0 |
| 3226 | OPC_Decode, 242, 4, 24, // 5933: decode to CVTSWi using decoder 24 |
| 3227 | // 5933: } |
| 3228 | 1, 0, // 5937: case 0x1: { |
| 3229 | OPC_CheckField, 0, 40, 0, // 5939: check Inst[39:0] == 0x0 |
| 3230 | OPC_Decode, 243, 4, 83, // 5943: decode to CVTSWr using decoder 83 |
| 3231 | // 5943: } |
| 3232 | // 5943: } // switch Inst[47] |
| 3233 | // 5943: } |
| 3234 | 190, 1, 23, // 5947: case 0xbe: { |
| 3235 | OPC_SwitchField, 47, 1, // 5950: switch Inst[47] { |
| 3236 | 0, 8, // 5953: case 0x0: { |
| 3237 | OPC_CheckField, 0, 40, 0, // 5955: check Inst[39:0] == 0x0 |
| 3238 | OPC_Decode, 224, 4, 5, // 5959: decode to CVTDLi using decoder 5 |
| 3239 | // 5959: } |
| 3240 | 1, 0, // 5963: case 0x1: { |
| 3241 | OPC_CheckField, 0, 40, 0, // 5965: check Inst[39:0] == 0x0 |
| 3242 | OPC_Decode, 225, 4, 84, // 5969: decode to CVTDLr using decoder 84 |
| 3243 | // 5969: } |
| 3244 | // 5969: } // switch Inst[47] |
| 3245 | // 5969: } |
| 3246 | 196, 1, 37, // 5973: case 0xc4: { |
| 3247 | OPC_SwitchField, 39, 1, // 5976: switch Inst[39] { |
| 3248 | 0, 15, // 5979: case 0x0: { |
| 3249 | OPC_SwitchField, 47, 1, // 5981: switch Inst[47] { |
| 3250 | 0, 4, // 5984: case 0x0: { |
| 3251 | OPC_Decode, 182, 4, 85, // 5986: decode to CASLzii using decoder 85 |
| 3252 | // 5986: } |
| 3253 | 1, 0, // 5990: case 0x1: { |
| 3254 | OPC_Decode, 183, 4, 85, // 5992: decode to CASLzir using decoder 85 |
| 3255 | // 5992: } |
| 3256 | // 5992: } // switch Inst[47] |
| 3257 | // 5992: } |
| 3258 | 1, 0, // 5996: case 0x1: { |
| 3259 | OPC_SwitchField, 47, 1, // 5998: switch Inst[47] { |
| 3260 | 0, 4, // 6001: case 0x0: { |
| 3261 | OPC_Decode, 180, 4, 85, // 6003: decode to CASLrii using decoder 85 |
| 3262 | // 6003: } |
| 3263 | 1, 0, // 6007: case 0x1: { |
| 3264 | OPC_Decode, 181, 4, 85, // 6009: decode to CASLrir using decoder 85 |
| 3265 | // 6009: } |
| 3266 | // 6009: } // switch Inst[47] |
| 3267 | // 6009: } |
| 3268 | // 6009: } // switch Inst[39] |
| 3269 | // 6009: } |
| 3270 | 197, 1, 37, // 6013: case 0xc5: { |
| 3271 | OPC_SwitchField, 39, 1, // 6016: switch Inst[39] { |
| 3272 | 0, 15, // 6019: case 0x0: { |
| 3273 | OPC_SwitchField, 47, 1, // 6021: switch Inst[47] { |
| 3274 | 0, 4, // 6024: case 0x0: { |
| 3275 | OPC_Decode, 186, 4, 86, // 6026: decode to CASWzii using decoder 86 |
| 3276 | // 6026: } |
| 3277 | 1, 0, // 6030: case 0x1: { |
| 3278 | OPC_Decode, 187, 4, 86, // 6032: decode to CASWzir using decoder 86 |
| 3279 | // 6032: } |
| 3280 | // 6032: } // switch Inst[47] |
| 3281 | // 6032: } |
| 3282 | 1, 0, // 6036: case 0x1: { |
| 3283 | OPC_SwitchField, 47, 1, // 6038: switch Inst[47] { |
| 3284 | 0, 4, // 6041: case 0x0: { |
| 3285 | OPC_Decode, 184, 4, 86, // 6043: decode to CASWrii using decoder 86 |
| 3286 | // 6043: } |
| 3287 | 1, 0, // 6047: case 0x1: { |
| 3288 | OPC_Decode, 185, 4, 86, // 6049: decode to CASWrir using decoder 86 |
| 3289 | // 6049: } |
| 3290 | // 6049: } // switch Inst[47] |
| 3291 | // 6049: } |
| 3292 | // 6049: } // switch Inst[39] |
| 3293 | // 6049: } |
| 3294 | 200, 1, 53, // 6053: case 0xc8: { |
| 3295 | OPC_SwitchField, 39, 1, // 6056: switch Inst[39] { |
| 3296 | 0, 23, // 6059: case 0x0: { |
| 3297 | OPC_SwitchField, 47, 1, // 6061: switch Inst[47] { |
| 3298 | 0, 8, // 6064: case 0x0: { |
| 3299 | OPC_CheckField, 0, 32, 0, // 6066: check Inst[31:0] == 0x0 |
| 3300 | OPC_Decode, 254, 34, 87, // 6070: decode to SLDrmi using decoder 87 |
| 3301 | // 6070: } |
| 3302 | 1, 0, // 6074: case 0x1: { |
| 3303 | OPC_CheckField, 0, 32, 0, // 6076: check Inst[31:0] == 0x0 |
| 3304 | OPC_Decode, 255, 34, 88, // 6080: decode to SLDrmr using decoder 88 |
| 3305 | // 6080: } |
| 3306 | // 6080: } // switch Inst[47] |
| 3307 | // 6080: } |
| 3308 | 1, 0, // 6084: case 0x1: { |
| 3309 | OPC_SwitchField, 47, 1, // 6086: switch Inst[47] { |
| 3310 | 0, 8, // 6089: case 0x0: { |
| 3311 | OPC_CheckField, 0, 32, 0, // 6091: check Inst[31:0] == 0x0 |
| 3312 | OPC_Decode, 128, 35, 89, // 6095: decode to SLDrri using decoder 89 |
| 3313 | // 6095: } |
| 3314 | 1, 0, // 6099: case 0x1: { |
| 3315 | OPC_CheckField, 0, 32, 0, // 6101: check Inst[31:0] == 0x0 |
| 3316 | OPC_Decode, 129, 35, 90, // 6105: decode to SLDrrr using decoder 90 |
| 3317 | // 6105: } |
| 3318 | // 6105: } // switch Inst[47] |
| 3319 | // 6105: } |
| 3320 | // 6105: } // switch Inst[39] |
| 3321 | // 6105: } |
| 3322 | 202, 1, 53, // 6109: case 0xca: { |
| 3323 | OPC_SwitchField, 39, 1, // 6112: switch Inst[39] { |
| 3324 | 0, 23, // 6115: case 0x0: { |
| 3325 | OPC_SwitchField, 47, 1, // 6117: switch Inst[47] { |
| 3326 | 0, 8, // 6120: case 0x0: { |
| 3327 | OPC_CheckField, 0, 32, 0, // 6122: check Inst[31:0] == 0x0 |
| 3328 | OPC_Decode, 130, 35, 34, // 6126: decode to SLLmi using decoder 34 |
| 3329 | // 6126: } |
| 3330 | 1, 0, // 6130: case 0x1: { |
| 3331 | OPC_CheckField, 0, 32, 0, // 6132: check Inst[31:0] == 0x0 |
| 3332 | OPC_Decode, 131, 35, 80, // 6136: decode to SLLmr using decoder 80 |
| 3333 | // 6136: } |
| 3334 | // 6136: } // switch Inst[47] |
| 3335 | // 6136: } |
| 3336 | 1, 0, // 6140: case 0x1: { |
| 3337 | OPC_SwitchField, 47, 1, // 6142: switch Inst[47] { |
| 3338 | 0, 8, // 6145: case 0x0: { |
| 3339 | OPC_CheckField, 0, 32, 0, // 6147: check Inst[31:0] == 0x0 |
| 3340 | OPC_Decode, 132, 35, 35, // 6151: decode to SLLri using decoder 35 |
| 3341 | // 6151: } |
| 3342 | 1, 0, // 6155: case 0x1: { |
| 3343 | OPC_CheckField, 0, 32, 0, // 6157: check Inst[31:0] == 0x0 |
| 3344 | OPC_Decode, 133, 35, 81, // 6161: decode to SLLrr using decoder 81 |
| 3345 | // 6161: } |
| 3346 | // 6161: } // switch Inst[47] |
| 3347 | // 6161: } |
| 3348 | // 6161: } // switch Inst[39] |
| 3349 | // 6161: } |
| 3350 | 204, 1, 53, // 6165: case 0xcc: { |
| 3351 | OPC_SwitchField, 39, 1, // 6168: switch Inst[39] { |
| 3352 | 0, 23, // 6171: case 0x0: { |
| 3353 | OPC_SwitchField, 47, 1, // 6173: switch Inst[47] { |
| 3354 | 0, 8, // 6176: case 0x0: { |
| 3355 | OPC_CheckField, 0, 32, 0, // 6178: check Inst[31:0] == 0x0 |
| 3356 | OPC_Decode, 246, 34, 91, // 6182: decode to SLAWSXmi using decoder 91 |
| 3357 | // 6182: } |
| 3358 | 1, 0, // 6186: case 0x1: { |
| 3359 | OPC_CheckField, 0, 32, 0, // 6188: check Inst[31:0] == 0x0 |
| 3360 | OPC_Decode, 247, 34, 92, // 6192: decode to SLAWSXmr using decoder 92 |
| 3361 | // 6192: } |
| 3362 | // 6192: } // switch Inst[47] |
| 3363 | // 6192: } |
| 3364 | 1, 0, // 6196: case 0x1: { |
| 3365 | OPC_SwitchField, 47, 1, // 6198: switch Inst[47] { |
| 3366 | 0, 8, // 6201: case 0x0: { |
| 3367 | OPC_CheckField, 0, 32, 0, // 6203: check Inst[31:0] == 0x0 |
| 3368 | OPC_Decode, 248, 34, 93, // 6207: decode to SLAWSXri using decoder 93 |
| 3369 | // 6207: } |
| 3370 | 1, 0, // 6211: case 0x1: { |
| 3371 | OPC_CheckField, 0, 32, 0, // 6213: check Inst[31:0] == 0x0 |
| 3372 | OPC_Decode, 249, 34, 94, // 6217: decode to SLAWSXrr using decoder 94 |
| 3373 | // 6217: } |
| 3374 | // 6217: } // switch Inst[47] |
| 3375 | // 6217: } |
| 3376 | // 6217: } // switch Inst[39] |
| 3377 | // 6217: } |
| 3378 | 205, 1, 53, // 6221: case 0xcd: { |
| 3379 | OPC_SwitchField, 39, 1, // 6224: switch Inst[39] { |
| 3380 | 0, 23, // 6227: case 0x0: { |
| 3381 | OPC_SwitchField, 47, 1, // 6229: switch Inst[47] { |
| 3382 | 0, 8, // 6232: case 0x0: { |
| 3383 | OPC_CheckField, 0, 32, 0, // 6234: check Inst[31:0] == 0x0 |
| 3384 | OPC_Decode, 250, 34, 91, // 6238: decode to SLAWZXmi using decoder 91 |
| 3385 | // 6238: } |
| 3386 | 1, 0, // 6242: case 0x1: { |
| 3387 | OPC_CheckField, 0, 32, 0, // 6244: check Inst[31:0] == 0x0 |
| 3388 | OPC_Decode, 251, 34, 92, // 6248: decode to SLAWZXmr using decoder 92 |
| 3389 | // 6248: } |
| 3390 | // 6248: } // switch Inst[47] |
| 3391 | // 6248: } |
| 3392 | 1, 0, // 6252: case 0x1: { |
| 3393 | OPC_SwitchField, 47, 1, // 6254: switch Inst[47] { |
| 3394 | 0, 8, // 6257: case 0x0: { |
| 3395 | OPC_CheckField, 0, 32, 0, // 6259: check Inst[31:0] == 0x0 |
| 3396 | OPC_Decode, 252, 34, 93, // 6263: decode to SLAWZXri using decoder 93 |
| 3397 | // 6263: } |
| 3398 | 1, 0, // 6267: case 0x1: { |
| 3399 | OPC_CheckField, 0, 32, 0, // 6269: check Inst[31:0] == 0x0 |
| 3400 | OPC_Decode, 253, 34, 94, // 6273: decode to SLAWZXrr using decoder 94 |
| 3401 | // 6273: } |
| 3402 | // 6273: } // switch Inst[47] |
| 3403 | // 6273: } |
| 3404 | // 6273: } // switch Inst[39] |
| 3405 | // 6273: } |
| 3406 | 206, 1, 23, // 6277: case 0xce: { |
| 3407 | OPC_SwitchField, 39, 9, // 6280: switch Inst[47:39] { |
| 3408 | 0, 8, // 6283: case 0x0: { |
| 3409 | OPC_CheckField, 0, 32, 0, // 6285: check Inst[31:0] == 0x0 |
| 3410 | OPC_Decode, 146, 6, 40, // 6289: decode to LDZm using decoder 40 |
| 3411 | // 6289: } |
| 3412 | 1, 0, // 6293: case 0x1: { |
| 3413 | OPC_CheckField, 0, 32, 0, // 6295: check Inst[31:0] == 0x0 |
| 3414 | OPC_Decode, 147, 6, 41, // 6299: decode to LDZr using decoder 41 |
| 3415 | // 6299: } |
| 3416 | // 6299: } // switch Inst[47:39] |
| 3417 | // 6299: } |
| 3418 | 208, 1, 82, // 6303: case 0xd0: { |
| 3419 | OPC_SwitchField, 0, 32, // 6306: switch Inst[31:0] { |
| 3420 | 0, 37, // 6309: case 0x0: { |
| 3421 | OPC_SwitchField, 39, 1, // 6311: switch Inst[39] { |
| 3422 | 0, 15, // 6314: case 0x0: { |
| 3423 | OPC_SwitchField, 47, 1, // 6316: switch Inst[47] { |
| 3424 | 0, 4, // 6319: case 0x0: { |
| 3425 | OPC_Decode, 196, 6, 51, // 6321: decode to MAXSLim using decoder 51 |
| 3426 | // 6321: } |
| 3427 | 1, 0, // 6325: case 0x1: { |
| 3428 | OPC_Decode, 198, 6, 52, // 6327: decode to MAXSLrm using decoder 52 |
| 3429 | // 6327: } |
| 3430 | // 6327: } // switch Inst[47] |
| 3431 | // 6327: } |
| 3432 | 1, 0, // 6331: case 0x1: { |
| 3433 | OPC_SwitchField, 47, 1, // 6333: switch Inst[47] { |
| 3434 | 0, 4, // 6336: case 0x0: { |
| 3435 | OPC_Decode, 197, 6, 65, // 6338: decode to MAXSLri using decoder 65 |
| 3436 | // 6338: } |
| 3437 | 1, 0, // 6342: case 0x1: { |
| 3438 | OPC_Decode, 199, 6, 54, // 6344: decode to MAXSLrr using decoder 54 |
| 3439 | // 6344: } |
| 3440 | // 6344: } // switch Inst[47] |
| 3441 | // 6344: } |
| 3442 | // 6344: } // switch Inst[39] |
| 3443 | // 6344: } |
| 3444 | 128, 1, 0, // 6348: case 0x80: { |
| 3445 | OPC_SwitchField, 39, 1, // 6351: switch Inst[39] { |
| 3446 | 0, 15, // 6354: case 0x0: { |
| 3447 | OPC_SwitchField, 47, 1, // 6356: switch Inst[47] { |
| 3448 | 0, 4, // 6359: case 0x0: { |
| 3449 | OPC_Decode, 208, 6, 51, // 6361: decode to MINSLim using decoder 51 |
| 3450 | // 6361: } |
| 3451 | 1, 0, // 6365: case 0x1: { |
| 3452 | OPC_Decode, 210, 6, 52, // 6367: decode to MINSLrm using decoder 52 |
| 3453 | // 6367: } |
| 3454 | // 6367: } // switch Inst[47] |
| 3455 | // 6367: } |
| 3456 | 1, 0, // 6371: case 0x1: { |
| 3457 | OPC_SwitchField, 47, 1, // 6373: switch Inst[47] { |
| 3458 | 0, 4, // 6376: case 0x0: { |
| 3459 | OPC_Decode, 209, 6, 65, // 6378: decode to MINSLri using decoder 65 |
| 3460 | // 6378: } |
| 3461 | 1, 0, // 6382: case 0x1: { |
| 3462 | OPC_Decode, 211, 6, 54, // 6384: decode to MINSLrr using decoder 54 |
| 3463 | // 6384: } |
| 3464 | // 6384: } // switch Inst[47] |
| 3465 | // 6384: } |
| 3466 | // 6384: } // switch Inst[39] |
| 3467 | // 6384: } |
| 3468 | // 6384: } // switch Inst[31:0] |
| 3469 | // 6384: } |
| 3470 | 210, 1, 23, // 6388: case 0xd2: { |
| 3471 | OPC_SwitchField, 47, 8, // 6391: switch Inst[54:47] { |
| 3472 | 0, 8, // 6394: case 0x0: { |
| 3473 | OPC_CheckField, 0, 40, 0, // 6396: check Inst[39:0] == 0x0 |
| 3474 | OPC_Decode, 160, 6, 95, // 6400: decode to LFRi using decoder 95 |
| 3475 | // 6400: } |
| 3476 | 1, 0, // 6404: case 0x1: { |
| 3477 | OPC_CheckField, 0, 40, 0, // 6406: check Inst[39:0] == 0x0 |
| 3478 | OPC_Decode, 161, 6, 42, // 6410: decode to LFRr using decoder 42 |
| 3479 | // 6410: } |
| 3480 | // 6410: } // switch Inst[54:47] |
| 3481 | // 6410: } |
| 3482 | 212, 1, 53, // 6414: case 0xd4: { |
| 3483 | OPC_SwitchField, 39, 1, // 6417: switch Inst[39] { |
| 3484 | 0, 23, // 6420: case 0x0: { |
| 3485 | OPC_SwitchField, 47, 1, // 6422: switch Inst[47] { |
| 3486 | 0, 8, // 6425: case 0x0: { |
| 3487 | OPC_CheckField, 0, 32, 0, // 6427: check Inst[31:0] == 0x0 |
| 3488 | OPC_Decode, 204, 4, 51, // 6431: decode to CMPSLim using decoder 51 |
| 3489 | // 6431: } |
| 3490 | 1, 0, // 6435: case 0x1: { |
| 3491 | OPC_CheckField, 0, 32, 0, // 6437: check Inst[31:0] == 0x0 |
| 3492 | OPC_Decode, 206, 4, 52, // 6441: decode to CMPSLrm using decoder 52 |
| 3493 | // 6441: } |
| 3494 | // 6441: } // switch Inst[47] |
| 3495 | // 6441: } |
| 3496 | 1, 0, // 6445: case 0x1: { |
| 3497 | OPC_SwitchField, 47, 1, // 6447: switch Inst[47] { |
| 3498 | 0, 8, // 6450: case 0x0: { |
| 3499 | OPC_CheckField, 0, 32, 0, // 6452: check Inst[31:0] == 0x0 |
| 3500 | OPC_Decode, 205, 4, 53, // 6456: decode to CMPSLir using decoder 53 |
| 3501 | // 6456: } |
| 3502 | 1, 0, // 6460: case 0x1: { |
| 3503 | OPC_CheckField, 0, 32, 0, // 6462: check Inst[31:0] == 0x0 |
| 3504 | OPC_Decode, 207, 4, 54, // 6466: decode to CMPSLrr using decoder 54 |
| 3505 | // 6466: } |
| 3506 | // 6466: } // switch Inst[47] |
| 3507 | // 6466: } |
| 3508 | // 6466: } // switch Inst[39] |
| 3509 | // 6466: } |
| 3510 | 214, 1, 53, // 6470: case 0xd6: { |
| 3511 | OPC_SwitchField, 39, 1, // 6473: switch Inst[39] { |
| 3512 | 0, 23, // 6476: case 0x0: { |
| 3513 | OPC_SwitchField, 47, 1, // 6478: switch Inst[47] { |
| 3514 | 0, 8, // 6481: case 0x0: { |
| 3515 | OPC_CheckField, 0, 32, 0, // 6483: check Inst[31:0] == 0x0 |
| 3516 | OPC_Decode, 226, 6, 51, // 6487: decode to MULSLWim using decoder 51 |
| 3517 | // 6487: } |
| 3518 | 1, 0, // 6491: case 0x1: { |
| 3519 | OPC_CheckField, 0, 32, 0, // 6493: check Inst[31:0] == 0x0 |
| 3520 | OPC_Decode, 228, 6, 96, // 6497: decode to MULSLWrm using decoder 96 |
| 3521 | // 6497: } |
| 3522 | // 6497: } // switch Inst[47] |
| 3523 | // 6497: } |
| 3524 | 1, 0, // 6501: case 0x1: { |
| 3525 | OPC_SwitchField, 47, 1, // 6503: switch Inst[47] { |
| 3526 | 0, 8, // 6506: case 0x0: { |
| 3527 | OPC_CheckField, 0, 32, 0, // 6508: check Inst[31:0] == 0x0 |
| 3528 | OPC_Decode, 227, 6, 97, // 6512: decode to MULSLWri using decoder 97 |
| 3529 | // 6512: } |
| 3530 | 1, 0, // 6516: case 0x1: { |
| 3531 | OPC_CheckField, 0, 32, 0, // 6518: check Inst[31:0] == 0x0 |
| 3532 | OPC_Decode, 229, 6, 98, // 6522: decode to MULSLWrr using decoder 98 |
| 3533 | // 6522: } |
| 3534 | // 6522: } // switch Inst[47] |
| 3535 | // 6522: } |
| 3536 | // 6522: } // switch Inst[39] |
| 3537 | // 6522: } |
| 3538 | 216, 1, 53, // 6526: case 0xd8: { |
| 3539 | OPC_SwitchField, 39, 1, // 6529: switch Inst[39] { |
| 3540 | 0, 23, // 6532: case 0x0: { |
| 3541 | OPC_SwitchField, 47, 1, // 6534: switch Inst[47] { |
| 3542 | 0, 8, // 6537: case 0x0: { |
| 3543 | OPC_CheckField, 0, 32, 0, // 6539: check Inst[31:0] == 0x0 |
| 3544 | OPC_Decode, 169, 5, 99, // 6543: decode to FADDQim using decoder 99 |
| 3545 | // 6543: } |
| 3546 | 1, 0, // 6547: case 0x1: { |
| 3547 | OPC_CheckField, 0, 32, 0, // 6549: check Inst[31:0] == 0x0 |
| 3548 | OPC_Decode, 171, 5, 100, // 6553: decode to FADDQrm using decoder 100 |
| 3549 | // 6553: } |
| 3550 | // 6553: } // switch Inst[47] |
| 3551 | // 6553: } |
| 3552 | 1, 0, // 6557: case 0x1: { |
| 3553 | OPC_SwitchField, 47, 1, // 6559: switch Inst[47] { |
| 3554 | 0, 8, // 6562: case 0x0: { |
| 3555 | OPC_CheckField, 0, 32, 0, // 6564: check Inst[31:0] == 0x0 |
| 3556 | OPC_Decode, 170, 5, 101, // 6568: decode to FADDQir using decoder 101 |
| 3557 | // 6568: } |
| 3558 | 1, 0, // 6572: case 0x1: { |
| 3559 | OPC_CheckField, 0, 32, 0, // 6574: check Inst[31:0] == 0x0 |
| 3560 | OPC_Decode, 172, 5, 102, // 6578: decode to FADDQrr using decoder 102 |
| 3561 | // 6578: } |
| 3562 | // 6578: } // switch Inst[47] |
| 3563 | // 6578: } |
| 3564 | // 6578: } // switch Inst[39] |
| 3565 | // 6578: } |
| 3566 | 218, 1, 53, // 6582: case 0xda: { |
| 3567 | OPC_SwitchField, 39, 1, // 6585: switch Inst[39] { |
| 3568 | 0, 23, // 6588: case 0x0: { |
| 3569 | OPC_SwitchField, 47, 1, // 6590: switch Inst[47] { |
| 3570 | 0, 8, // 6593: case 0x0: { |
| 3571 | OPC_CheckField, 0, 32, 0, // 6595: check Inst[31:0] == 0x0 |
| 3572 | OPC_Decode, 222, 5, 99, // 6599: decode to FMULQim using decoder 99 |
| 3573 | // 6599: } |
| 3574 | 1, 0, // 6603: case 0x1: { |
| 3575 | OPC_CheckField, 0, 32, 0, // 6605: check Inst[31:0] == 0x0 |
| 3576 | OPC_Decode, 224, 5, 100, // 6609: decode to FMULQrm using decoder 100 |
| 3577 | // 6609: } |
| 3578 | // 6609: } // switch Inst[47] |
| 3579 | // 6609: } |
| 3580 | 1, 0, // 6613: case 0x1: { |
| 3581 | OPC_SwitchField, 47, 1, // 6615: switch Inst[47] { |
| 3582 | 0, 8, // 6618: case 0x0: { |
| 3583 | OPC_CheckField, 0, 32, 0, // 6620: check Inst[31:0] == 0x0 |
| 3584 | OPC_Decode, 223, 5, 101, // 6624: decode to FMULQir using decoder 101 |
| 3585 | // 6624: } |
| 3586 | 1, 0, // 6628: case 0x1: { |
| 3587 | OPC_CheckField, 0, 32, 0, // 6630: check Inst[31:0] == 0x0 |
| 3588 | OPC_Decode, 225, 5, 102, // 6634: decode to FMULQrr using decoder 102 |
| 3589 | // 6634: } |
| 3590 | // 6634: } // switch Inst[47] |
| 3591 | // 6634: } |
| 3592 | // 6634: } // switch Inst[39] |
| 3593 | // 6634: } |
| 3594 | 220, 1, 53, // 6638: case 0xdc: { |
| 3595 | OPC_SwitchField, 39, 1, // 6641: switch Inst[39] { |
| 3596 | 0, 23, // 6644: case 0x0: { |
| 3597 | OPC_SwitchField, 47, 1, // 6646: switch Inst[47] { |
| 3598 | 0, 8, // 6649: case 0x0: { |
| 3599 | OPC_CheckField, 0, 32, 0, // 6651: check Inst[31:0] == 0x0 |
| 3600 | OPC_Decode, 230, 6, 51, // 6655: decode to MULSLim using decoder 51 |
| 3601 | // 6655: } |
| 3602 | 1, 0, // 6659: case 0x1: { |
| 3603 | OPC_CheckField, 0, 32, 0, // 6661: check Inst[31:0] == 0x0 |
| 3604 | OPC_Decode, 232, 6, 52, // 6665: decode to MULSLrm using decoder 52 |
| 3605 | // 6665: } |
| 3606 | // 6665: } // switch Inst[47] |
| 3607 | // 6665: } |
| 3608 | 1, 0, // 6669: case 0x1: { |
| 3609 | OPC_SwitchField, 47, 1, // 6671: switch Inst[47] { |
| 3610 | 0, 8, // 6674: case 0x0: { |
| 3611 | OPC_CheckField, 0, 32, 0, // 6676: check Inst[31:0] == 0x0 |
| 3612 | OPC_Decode, 231, 6, 65, // 6680: decode to MULSLri using decoder 65 |
| 3613 | // 6680: } |
| 3614 | 1, 0, // 6684: case 0x1: { |
| 3615 | OPC_CheckField, 0, 32, 0, // 6686: check Inst[31:0] == 0x0 |
| 3616 | OPC_Decode, 233, 6, 54, // 6690: decode to MULSLrr using decoder 54 |
| 3617 | // 6690: } |
| 3618 | // 6690: } // switch Inst[47] |
| 3619 | // 6690: } |
| 3620 | // 6690: } // switch Inst[39] |
| 3621 | // 6690: } |
| 3622 | 222, 1, 53, // 6694: case 0xde: { |
| 3623 | OPC_SwitchField, 39, 1, // 6697: switch Inst[39] { |
| 3624 | 0, 23, // 6700: case 0x0: { |
| 3625 | OPC_SwitchField, 47, 1, // 6702: switch Inst[47] { |
| 3626 | 0, 8, // 6705: case 0x0: { |
| 3627 | OPC_CheckField, 0, 32, 0, // 6707: check Inst[31:0] == 0x0 |
| 3628 | OPC_Decode, 136, 5, 51, // 6711: decode to DIVULim using decoder 51 |
| 3629 | // 6711: } |
| 3630 | 1, 0, // 6715: case 0x1: { |
| 3631 | OPC_CheckField, 0, 32, 0, // 6717: check Inst[31:0] == 0x0 |
| 3632 | OPC_Decode, 138, 5, 52, // 6721: decode to DIVULrm using decoder 52 |
| 3633 | // 6721: } |
| 3634 | // 6721: } // switch Inst[47] |
| 3635 | // 6721: } |
| 3636 | 1, 0, // 6725: case 0x1: { |
| 3637 | OPC_SwitchField, 47, 1, // 6727: switch Inst[47] { |
| 3638 | 0, 8, // 6730: case 0x0: { |
| 3639 | OPC_CheckField, 0, 32, 0, // 6732: check Inst[31:0] == 0x0 |
| 3640 | OPC_Decode, 137, 5, 53, // 6736: decode to DIVULir using decoder 53 |
| 3641 | // 6736: } |
| 3642 | 1, 0, // 6740: case 0x1: { |
| 3643 | OPC_CheckField, 0, 32, 0, // 6742: check Inst[31:0] == 0x0 |
| 3644 | OPC_Decode, 139, 5, 54, // 6746: decode to DIVULrr using decoder 54 |
| 3645 | // 6746: } |
| 3646 | // 6746: } // switch Inst[47] |
| 3647 | // 6746: } |
| 3648 | // 6746: } // switch Inst[39] |
| 3649 | // 6746: } |
| 3650 | 223, 1, 53, // 6750: case 0xdf: { |
| 3651 | OPC_SwitchField, 39, 1, // 6753: switch Inst[39] { |
| 3652 | 0, 23, // 6756: case 0x0: { |
| 3653 | OPC_SwitchField, 47, 1, // 6758: switch Inst[47] { |
| 3654 | 0, 8, // 6761: case 0x0: { |
| 3655 | OPC_CheckField, 0, 32, 0, // 6763: check Inst[31:0] == 0x0 |
| 3656 | OPC_Decode, 140, 5, 66, // 6767: decode to DIVUWim using decoder 66 |
| 3657 | // 6767: } |
| 3658 | 1, 0, // 6771: case 0x1: { |
| 3659 | OPC_CheckField, 0, 32, 0, // 6773: check Inst[31:0] == 0x0 |
| 3660 | OPC_Decode, 142, 5, 67, // 6777: decode to DIVUWrm using decoder 67 |
| 3661 | // 6777: } |
| 3662 | // 6777: } // switch Inst[47] |
| 3663 | // 6777: } |
| 3664 | 1, 0, // 6781: case 0x1: { |
| 3665 | OPC_SwitchField, 47, 1, // 6783: switch Inst[47] { |
| 3666 | 0, 8, // 6786: case 0x0: { |
| 3667 | OPC_CheckField, 0, 32, 0, // 6788: check Inst[31:0] == 0x0 |
| 3668 | OPC_Decode, 141, 5, 79, // 6792: decode to DIVUWir using decoder 79 |
| 3669 | // 6792: } |
| 3670 | 1, 0, // 6796: case 0x1: { |
| 3671 | OPC_CheckField, 0, 32, 0, // 6798: check Inst[31:0] == 0x0 |
| 3672 | OPC_Decode, 143, 5, 69, // 6802: decode to DIVUWrr using decoder 69 |
| 3673 | // 6802: } |
| 3674 | // 6802: } // switch Inst[47] |
| 3675 | // 6802: } |
| 3676 | // 6802: } // switch Inst[39] |
| 3677 | // 6802: } |
| 3678 | 232, 1, 53, // 6806: case 0xe8: { |
| 3679 | OPC_SwitchField, 39, 1, // 6809: switch Inst[39] { |
| 3680 | 0, 23, // 6812: case 0x0: { |
| 3681 | OPC_SwitchField, 47, 1, // 6814: switch Inst[47] { |
| 3682 | 0, 8, // 6817: case 0x0: { |
| 3683 | OPC_CheckField, 0, 32, 0, // 6819: check Inst[31:0] == 0x0 |
| 3684 | OPC_Decode, 149, 35, 103, // 6823: decode to SRDmri using decoder 103 |
| 3685 | // 6823: } |
| 3686 | 1, 0, // 6827: case 0x1: { |
| 3687 | OPC_CheckField, 0, 32, 0, // 6829: check Inst[31:0] == 0x0 |
| 3688 | OPC_Decode, 150, 35, 104, // 6833: decode to SRDmrr using decoder 104 |
| 3689 | // 6833: } |
| 3690 | // 6833: } // switch Inst[47] |
| 3691 | // 6833: } |
| 3692 | 1, 0, // 6837: case 0x1: { |
| 3693 | OPC_SwitchField, 47, 1, // 6839: switch Inst[47] { |
| 3694 | 0, 8, // 6842: case 0x0: { |
| 3695 | OPC_CheckField, 0, 32, 0, // 6844: check Inst[31:0] == 0x0 |
| 3696 | OPC_Decode, 151, 35, 105, // 6848: decode to SRDrri using decoder 105 |
| 3697 | // 6848: } |
| 3698 | 1, 0, // 6852: case 0x1: { |
| 3699 | OPC_CheckField, 0, 32, 0, // 6854: check Inst[31:0] == 0x0 |
| 3700 | OPC_Decode, 152, 35, 106, // 6858: decode to SRDrrr using decoder 106 |
| 3701 | // 6858: } |
| 3702 | // 6858: } // switch Inst[47] |
| 3703 | // 6858: } |
| 3704 | // 6858: } // switch Inst[39] |
| 3705 | // 6858: } |
| 3706 | 234, 1, 53, // 6862: case 0xea: { |
| 3707 | OPC_SwitchField, 39, 1, // 6865: switch Inst[39] { |
| 3708 | 0, 23, // 6868: case 0x0: { |
| 3709 | OPC_SwitchField, 47, 1, // 6870: switch Inst[47] { |
| 3710 | 0, 8, // 6873: case 0x0: { |
| 3711 | OPC_CheckField, 0, 32, 0, // 6875: check Inst[31:0] == 0x0 |
| 3712 | OPC_Decode, 153, 35, 34, // 6879: decode to SRLmi using decoder 34 |
| 3713 | // 6879: } |
| 3714 | 1, 0, // 6883: case 0x1: { |
| 3715 | OPC_CheckField, 0, 32, 0, // 6885: check Inst[31:0] == 0x0 |
| 3716 | OPC_Decode, 154, 35, 80, // 6889: decode to SRLmr using decoder 80 |
| 3717 | // 6889: } |
| 3718 | // 6889: } // switch Inst[47] |
| 3719 | // 6889: } |
| 3720 | 1, 0, // 6893: case 0x1: { |
| 3721 | OPC_SwitchField, 47, 1, // 6895: switch Inst[47] { |
| 3722 | 0, 8, // 6898: case 0x0: { |
| 3723 | OPC_CheckField, 0, 32, 0, // 6900: check Inst[31:0] == 0x0 |
| 3724 | OPC_Decode, 155, 35, 35, // 6904: decode to SRLri using decoder 35 |
| 3725 | // 6904: } |
| 3726 | 1, 0, // 6908: case 0x1: { |
| 3727 | OPC_CheckField, 0, 32, 0, // 6910: check Inst[31:0] == 0x0 |
| 3728 | OPC_Decode, 156, 35, 81, // 6914: decode to SRLrr using decoder 81 |
| 3729 | // 6914: } |
| 3730 | // 6914: } // switch Inst[47] |
| 3731 | // 6914: } |
| 3732 | // 6914: } // switch Inst[39] |
| 3733 | // 6914: } |
| 3734 | 236, 1, 53, // 6918: case 0xec: { |
| 3735 | OPC_SwitchField, 39, 1, // 6921: switch Inst[39] { |
| 3736 | 0, 23, // 6924: case 0x0: { |
| 3737 | OPC_SwitchField, 47, 1, // 6926: switch Inst[47] { |
| 3738 | 0, 8, // 6929: case 0x0: { |
| 3739 | OPC_CheckField, 0, 32, 0, // 6931: check Inst[31:0] == 0x0 |
| 3740 | OPC_Decode, 141, 35, 91, // 6935: decode to SRAWSXmi using decoder 91 |
| 3741 | // 6935: } |
| 3742 | 1, 0, // 6939: case 0x1: { |
| 3743 | OPC_CheckField, 0, 32, 0, // 6941: check Inst[31:0] == 0x0 |
| 3744 | OPC_Decode, 142, 35, 92, // 6945: decode to SRAWSXmr using decoder 92 |
| 3745 | // 6945: } |
| 3746 | // 6945: } // switch Inst[47] |
| 3747 | // 6945: } |
| 3748 | 1, 0, // 6949: case 0x1: { |
| 3749 | OPC_SwitchField, 47, 1, // 6951: switch Inst[47] { |
| 3750 | 0, 8, // 6954: case 0x0: { |
| 3751 | OPC_CheckField, 0, 32, 0, // 6956: check Inst[31:0] == 0x0 |
| 3752 | OPC_Decode, 143, 35, 93, // 6960: decode to SRAWSXri using decoder 93 |
| 3753 | // 6960: } |
| 3754 | 1, 0, // 6964: case 0x1: { |
| 3755 | OPC_CheckField, 0, 32, 0, // 6966: check Inst[31:0] == 0x0 |
| 3756 | OPC_Decode, 144, 35, 94, // 6970: decode to SRAWSXrr using decoder 94 |
| 3757 | // 6970: } |
| 3758 | // 6970: } // switch Inst[47] |
| 3759 | // 6970: } |
| 3760 | // 6970: } // switch Inst[39] |
| 3761 | // 6970: } |
| 3762 | 237, 1, 53, // 6974: case 0xed: { |
| 3763 | OPC_SwitchField, 39, 1, // 6977: switch Inst[39] { |
| 3764 | 0, 23, // 6980: case 0x0: { |
| 3765 | OPC_SwitchField, 47, 1, // 6982: switch Inst[47] { |
| 3766 | 0, 8, // 6985: case 0x0: { |
| 3767 | OPC_CheckField, 0, 32, 0, // 6987: check Inst[31:0] == 0x0 |
| 3768 | OPC_Decode, 145, 35, 91, // 6991: decode to SRAWZXmi using decoder 91 |
| 3769 | // 6991: } |
| 3770 | 1, 0, // 6995: case 0x1: { |
| 3771 | OPC_CheckField, 0, 32, 0, // 6997: check Inst[31:0] == 0x0 |
| 3772 | OPC_Decode, 146, 35, 92, // 7001: decode to SRAWZXmr using decoder 92 |
| 3773 | // 7001: } |
| 3774 | // 7001: } // switch Inst[47] |
| 3775 | // 7001: } |
| 3776 | 1, 0, // 7005: case 0x1: { |
| 3777 | OPC_SwitchField, 47, 1, // 7007: switch Inst[47] { |
| 3778 | 0, 8, // 7010: case 0x0: { |
| 3779 | OPC_CheckField, 0, 32, 0, // 7012: check Inst[31:0] == 0x0 |
| 3780 | OPC_Decode, 147, 35, 93, // 7016: decode to SRAWZXri using decoder 93 |
| 3781 | // 7016: } |
| 3782 | 1, 0, // 7020: case 0x1: { |
| 3783 | OPC_CheckField, 0, 32, 0, // 7022: check Inst[31:0] == 0x0 |
| 3784 | OPC_Decode, 148, 35, 94, // 7026: decode to SRAWZXrr using decoder 94 |
| 3785 | // 7026: } |
| 3786 | // 7026: } // switch Inst[47] |
| 3787 | // 7026: } |
| 3788 | // 7026: } // switch Inst[39] |
| 3789 | // 7026: } |
| 3790 | 238, 1, 53, // 7030: case 0xee: { |
| 3791 | OPC_SwitchField, 39, 1, // 7033: switch Inst[39] { |
| 3792 | 0, 23, // 7036: case 0x0: { |
| 3793 | OPC_SwitchField, 47, 1, // 7038: switch Inst[47] { |
| 3794 | 0, 8, // 7041: case 0x0: { |
| 3795 | OPC_CheckField, 0, 32, 0, // 7043: check Inst[31:0] == 0x0 |
| 3796 | OPC_Decode, 137, 35, 34, // 7047: decode to SRALmi using decoder 34 |
| 3797 | // 7047: } |
| 3798 | 1, 0, // 7051: case 0x1: { |
| 3799 | OPC_CheckField, 0, 32, 0, // 7053: check Inst[31:0] == 0x0 |
| 3800 | OPC_Decode, 138, 35, 80, // 7057: decode to SRALmr using decoder 80 |
| 3801 | // 7057: } |
| 3802 | // 7057: } // switch Inst[47] |
| 3803 | // 7057: } |
| 3804 | 1, 0, // 7061: case 0x1: { |
| 3805 | OPC_SwitchField, 47, 1, // 7063: switch Inst[47] { |
| 3806 | 0, 8, // 7066: case 0x0: { |
| 3807 | OPC_CheckField, 0, 32, 0, // 7068: check Inst[31:0] == 0x0 |
| 3808 | OPC_Decode, 139, 35, 35, // 7072: decode to SRALri using decoder 35 |
| 3809 | // 7072: } |
| 3810 | 1, 0, // 7076: case 0x1: { |
| 3811 | OPC_CheckField, 0, 32, 0, // 7078: check Inst[31:0] == 0x0 |
| 3812 | OPC_Decode, 140, 35, 81, // 7082: decode to SRALrr using decoder 81 |
| 3813 | // 7082: } |
| 3814 | // 7082: } // switch Inst[47] |
| 3815 | // 7082: } |
| 3816 | // 7082: } // switch Inst[39] |
| 3817 | // 7082: } |
| 3818 | 240, 1, 82, // 7086: case 0xf0: { |
| 3819 | OPC_SwitchField, 0, 32, // 7089: switch Inst[31:0] { |
| 3820 | 0, 37, // 7092: case 0x0: { |
| 3821 | OPC_SwitchField, 39, 1, // 7094: switch Inst[39] { |
| 3822 | 0, 15, // 7097: case 0x0: { |
| 3823 | OPC_SwitchField, 47, 1, // 7099: switch Inst[47] { |
| 3824 | 0, 4, // 7102: case 0x0: { |
| 3825 | OPC_Decode, 200, 6, 66, // 7104: decode to MAXSWSXim using decoder 66 |
| 3826 | // 7104: } |
| 3827 | 1, 0, // 7108: case 0x1: { |
| 3828 | OPC_Decode, 202, 6, 67, // 7110: decode to MAXSWSXrm using decoder 67 |
| 3829 | // 7110: } |
| 3830 | // 7110: } // switch Inst[47] |
| 3831 | // 7110: } |
| 3832 | 1, 0, // 7114: case 0x1: { |
| 3833 | OPC_SwitchField, 47, 1, // 7116: switch Inst[47] { |
| 3834 | 0, 4, // 7119: case 0x0: { |
| 3835 | OPC_Decode, 201, 6, 68, // 7121: decode to MAXSWSXri using decoder 68 |
| 3836 | // 7121: } |
| 3837 | 1, 0, // 7125: case 0x1: { |
| 3838 | OPC_Decode, 203, 6, 69, // 7127: decode to MAXSWSXrr using decoder 69 |
| 3839 | // 7127: } |
| 3840 | // 7127: } // switch Inst[47] |
| 3841 | // 7127: } |
| 3842 | // 7127: } // switch Inst[39] |
| 3843 | // 7127: } |
| 3844 | 128, 1, 0, // 7131: case 0x80: { |
| 3845 | OPC_SwitchField, 39, 1, // 7134: switch Inst[39] { |
| 3846 | 0, 15, // 7137: case 0x0: { |
| 3847 | OPC_SwitchField, 47, 1, // 7139: switch Inst[47] { |
| 3848 | 0, 4, // 7142: case 0x0: { |
| 3849 | OPC_Decode, 212, 6, 66, // 7144: decode to MINSWSXim using decoder 66 |
| 3850 | // 7144: } |
| 3851 | 1, 0, // 7148: case 0x1: { |
| 3852 | OPC_Decode, 214, 6, 67, // 7150: decode to MINSWSXrm using decoder 67 |
| 3853 | // 7150: } |
| 3854 | // 7150: } // switch Inst[47] |
| 3855 | // 7150: } |
| 3856 | 1, 0, // 7154: case 0x1: { |
| 3857 | OPC_SwitchField, 47, 1, // 7156: switch Inst[47] { |
| 3858 | 0, 4, // 7159: case 0x0: { |
| 3859 | OPC_Decode, 213, 6, 68, // 7161: decode to MINSWSXri using decoder 68 |
| 3860 | // 7161: } |
| 3861 | 1, 0, // 7165: case 0x1: { |
| 3862 | OPC_Decode, 215, 6, 69, // 7167: decode to MINSWSXrr using decoder 69 |
| 3863 | // 7167: } |
| 3864 | // 7167: } // switch Inst[47] |
| 3865 | // 7167: } |
| 3866 | // 7167: } // switch Inst[39] |
| 3867 | // 7167: } |
| 3868 | // 7167: } // switch Inst[31:0] |
| 3869 | // 7167: } |
| 3870 | 241, 1, 82, // 7171: case 0xf1: { |
| 3871 | OPC_SwitchField, 0, 32, // 7174: switch Inst[31:0] { |
| 3872 | 0, 37, // 7177: case 0x0: { |
| 3873 | OPC_SwitchField, 39, 1, // 7179: switch Inst[39] { |
| 3874 | 0, 15, // 7182: case 0x0: { |
| 3875 | OPC_SwitchField, 47, 1, // 7184: switch Inst[47] { |
| 3876 | 0, 4, // 7187: case 0x0: { |
| 3877 | OPC_Decode, 204, 6, 66, // 7189: decode to MAXSWZXim using decoder 66 |
| 3878 | // 7189: } |
| 3879 | 1, 0, // 7193: case 0x1: { |
| 3880 | OPC_Decode, 206, 6, 67, // 7195: decode to MAXSWZXrm using decoder 67 |
| 3881 | // 7195: } |
| 3882 | // 7195: } // switch Inst[47] |
| 3883 | // 7195: } |
| 3884 | 1, 0, // 7199: case 0x1: { |
| 3885 | OPC_SwitchField, 47, 1, // 7201: switch Inst[47] { |
| 3886 | 0, 4, // 7204: case 0x0: { |
| 3887 | OPC_Decode, 205, 6, 68, // 7206: decode to MAXSWZXri using decoder 68 |
| 3888 | // 7206: } |
| 3889 | 1, 0, // 7210: case 0x1: { |
| 3890 | OPC_Decode, 207, 6, 69, // 7212: decode to MAXSWZXrr using decoder 69 |
| 3891 | // 7212: } |
| 3892 | // 7212: } // switch Inst[47] |
| 3893 | // 7212: } |
| 3894 | // 7212: } // switch Inst[39] |
| 3895 | // 7212: } |
| 3896 | 128, 1, 0, // 7216: case 0x80: { |
| 3897 | OPC_SwitchField, 39, 1, // 7219: switch Inst[39] { |
| 3898 | 0, 15, // 7222: case 0x0: { |
| 3899 | OPC_SwitchField, 47, 1, // 7224: switch Inst[47] { |
| 3900 | 0, 4, // 7227: case 0x0: { |
| 3901 | OPC_Decode, 216, 6, 66, // 7229: decode to MINSWZXim using decoder 66 |
| 3902 | // 7229: } |
| 3903 | 1, 0, // 7233: case 0x1: { |
| 3904 | OPC_Decode, 218, 6, 67, // 7235: decode to MINSWZXrm using decoder 67 |
| 3905 | // 7235: } |
| 3906 | // 7235: } // switch Inst[47] |
| 3907 | // 7235: } |
| 3908 | 1, 0, // 7239: case 0x1: { |
| 3909 | OPC_SwitchField, 47, 1, // 7241: switch Inst[47] { |
| 3910 | 0, 4, // 7244: case 0x0: { |
| 3911 | OPC_Decode, 217, 6, 68, // 7246: decode to MINSWZXri using decoder 68 |
| 3912 | // 7246: } |
| 3913 | 1, 0, // 7250: case 0x1: { |
| 3914 | OPC_Decode, 219, 6, 69, // 7252: decode to MINSWZXrr using decoder 69 |
| 3915 | // 7252: } |
| 3916 | // 7252: } // switch Inst[47] |
| 3917 | // 7252: } |
| 3918 | // 7252: } // switch Inst[39] |
| 3919 | // 7252: } |
| 3920 | // 7252: } // switch Inst[31:0] |
| 3921 | // 7252: } |
| 3922 | 242, 1, 8, // 7256: case 0xf2: { |
| 3923 | OPC_CheckField, 0, 55, 0, // 7259: check Inst[54:0] == 0x0 |
| 3924 | OPC_Decode, 128, 7, 29, // 7263: decode to NOP using decoder 29 |
| 3925 | // 7263: } |
| 3926 | 244, 1, 53, // 7267: case 0xf4: { |
| 3927 | OPC_SwitchField, 39, 1, // 7270: switch Inst[39] { |
| 3928 | 0, 23, // 7273: case 0x0: { |
| 3929 | OPC_SwitchField, 47, 1, // 7275: switch Inst[47] { |
| 3930 | 0, 8, // 7278: case 0x0: { |
| 3931 | OPC_CheckField, 0, 32, 0, // 7280: check Inst[31:0] == 0x0 |
| 3932 | OPC_Decode, 208, 4, 66, // 7284: decode to CMPSWSXim using decoder 66 |
| 3933 | // 7284: } |
| 3934 | 1, 0, // 7288: case 0x1: { |
| 3935 | OPC_CheckField, 0, 32, 0, // 7290: check Inst[31:0] == 0x0 |
| 3936 | OPC_Decode, 210, 4, 67, // 7294: decode to CMPSWSXrm using decoder 67 |
| 3937 | // 7294: } |
| 3938 | // 7294: } // switch Inst[47] |
| 3939 | // 7294: } |
| 3940 | 1, 0, // 7298: case 0x1: { |
| 3941 | OPC_SwitchField, 47, 1, // 7300: switch Inst[47] { |
| 3942 | 0, 8, // 7303: case 0x0: { |
| 3943 | OPC_CheckField, 0, 32, 0, // 7305: check Inst[31:0] == 0x0 |
| 3944 | OPC_Decode, 209, 4, 79, // 7309: decode to CMPSWSXir using decoder 79 |
| 3945 | // 7309: } |
| 3946 | 1, 0, // 7313: case 0x1: { |
| 3947 | OPC_CheckField, 0, 32, 0, // 7315: check Inst[31:0] == 0x0 |
| 3948 | OPC_Decode, 211, 4, 69, // 7319: decode to CMPSWSXrr using decoder 69 |
| 3949 | // 7319: } |
| 3950 | // 7319: } // switch Inst[47] |
| 3951 | // 7319: } |
| 3952 | // 7319: } // switch Inst[39] |
| 3953 | // 7319: } |
| 3954 | 245, 1, 53, // 7323: case 0xf5: { |
| 3955 | OPC_SwitchField, 39, 1, // 7326: switch Inst[39] { |
| 3956 | 0, 23, // 7329: case 0x0: { |
| 3957 | OPC_SwitchField, 47, 1, // 7331: switch Inst[47] { |
| 3958 | 0, 8, // 7334: case 0x0: { |
| 3959 | OPC_CheckField, 0, 32, 0, // 7336: check Inst[31:0] == 0x0 |
| 3960 | OPC_Decode, 212, 4, 66, // 7340: decode to CMPSWZXim using decoder 66 |
| 3961 | // 7340: } |
| 3962 | 1, 0, // 7344: case 0x1: { |
| 3963 | OPC_CheckField, 0, 32, 0, // 7346: check Inst[31:0] == 0x0 |
| 3964 | OPC_Decode, 214, 4, 67, // 7350: decode to CMPSWZXrm using decoder 67 |
| 3965 | // 7350: } |
| 3966 | // 7350: } // switch Inst[47] |
| 3967 | // 7350: } |
| 3968 | 1, 0, // 7354: case 0x1: { |
| 3969 | OPC_SwitchField, 47, 1, // 7356: switch Inst[47] { |
| 3970 | 0, 8, // 7359: case 0x0: { |
| 3971 | OPC_CheckField, 0, 32, 0, // 7361: check Inst[31:0] == 0x0 |
| 3972 | OPC_Decode, 213, 4, 79, // 7365: decode to CMPSWZXir using decoder 79 |
| 3973 | // 7365: } |
| 3974 | 1, 0, // 7369: case 0x1: { |
| 3975 | OPC_CheckField, 0, 32, 0, // 7371: check Inst[31:0] == 0x0 |
| 3976 | OPC_Decode, 215, 4, 69, // 7375: decode to CMPSWZXrr using decoder 69 |
| 3977 | // 7375: } |
| 3978 | // 7375: } // switch Inst[47] |
| 3979 | // 7375: } |
| 3980 | // 7375: } // switch Inst[39] |
| 3981 | // 7375: } |
| 3982 | 246, 1, 53, // 7379: case 0xf6: { |
| 3983 | OPC_SwitchField, 39, 1, // 7382: switch Inst[39] { |
| 3984 | 0, 23, // 7385: case 0x0: { |
| 3985 | OPC_SwitchField, 47, 1, // 7387: switch Inst[47] { |
| 3986 | 0, 8, // 7390: case 0x0: { |
| 3987 | OPC_CheckField, 0, 32, 0, // 7392: check Inst[31:0] == 0x0 |
| 3988 | OPC_Decode, 128, 5, 66, // 7396: decode to DIVSWSXim using decoder 66 |
| 3989 | // 7396: } |
| 3990 | 1, 0, // 7400: case 0x1: { |
| 3991 | OPC_CheckField, 0, 32, 0, // 7402: check Inst[31:0] == 0x0 |
| 3992 | OPC_Decode, 130, 5, 67, // 7406: decode to DIVSWSXrm using decoder 67 |
| 3993 | // 7406: } |
| 3994 | // 7406: } // switch Inst[47] |
| 3995 | // 7406: } |
| 3996 | 1, 0, // 7410: case 0x1: { |
| 3997 | OPC_SwitchField, 47, 1, // 7412: switch Inst[47] { |
| 3998 | 0, 8, // 7415: case 0x0: { |
| 3999 | OPC_CheckField, 0, 32, 0, // 7417: check Inst[31:0] == 0x0 |
| 4000 | OPC_Decode, 129, 5, 79, // 7421: decode to DIVSWSXir using decoder 79 |
| 4001 | // 7421: } |
| 4002 | 1, 0, // 7425: case 0x1: { |
| 4003 | OPC_CheckField, 0, 32, 0, // 7427: check Inst[31:0] == 0x0 |
| 4004 | OPC_Decode, 131, 5, 69, // 7431: decode to DIVSWSXrr using decoder 69 |
| 4005 | // 7431: } |
| 4006 | // 7431: } // switch Inst[47] |
| 4007 | // 7431: } |
| 4008 | // 7431: } // switch Inst[39] |
| 4009 | // 7431: } |
| 4010 | 247, 1, 53, // 7435: case 0xf7: { |
| 4011 | OPC_SwitchField, 39, 1, // 7438: switch Inst[39] { |
| 4012 | 0, 23, // 7441: case 0x0: { |
| 4013 | OPC_SwitchField, 47, 1, // 7443: switch Inst[47] { |
| 4014 | 0, 8, // 7446: case 0x0: { |
| 4015 | OPC_CheckField, 0, 32, 0, // 7448: check Inst[31:0] == 0x0 |
| 4016 | OPC_Decode, 132, 5, 66, // 7452: decode to DIVSWZXim using decoder 66 |
| 4017 | // 7452: } |
| 4018 | 1, 0, // 7456: case 0x1: { |
| 4019 | OPC_CheckField, 0, 32, 0, // 7458: check Inst[31:0] == 0x0 |
| 4020 | OPC_Decode, 134, 5, 67, // 7462: decode to DIVSWZXrm using decoder 67 |
| 4021 | // 7462: } |
| 4022 | // 7462: } // switch Inst[47] |
| 4023 | // 7462: } |
| 4024 | 1, 0, // 7466: case 0x1: { |
| 4025 | OPC_SwitchField, 47, 1, // 7468: switch Inst[47] { |
| 4026 | 0, 8, // 7471: case 0x0: { |
| 4027 | OPC_CheckField, 0, 32, 0, // 7473: check Inst[31:0] == 0x0 |
| 4028 | OPC_Decode, 133, 5, 79, // 7477: decode to DIVSWZXir using decoder 79 |
| 4029 | // 7477: } |
| 4030 | 1, 0, // 7481: case 0x1: { |
| 4031 | OPC_CheckField, 0, 32, 0, // 7483: check Inst[31:0] == 0x0 |
| 4032 | OPC_Decode, 135, 5, 69, // 7487: decode to DIVSWZXrr using decoder 69 |
| 4033 | // 7487: } |
| 4034 | // 7487: } // switch Inst[47] |
| 4035 | // 7487: } |
| 4036 | // 7487: } // switch Inst[39] |
| 4037 | // 7487: } |
| 4038 | 248, 1, 53, // 7491: case 0xf8: { |
| 4039 | OPC_SwitchField, 39, 1, // 7494: switch Inst[39] { |
| 4040 | 0, 23, // 7497: case 0x0: { |
| 4041 | OPC_SwitchField, 47, 1, // 7499: switch Inst[47] { |
| 4042 | 0, 8, // 7502: case 0x0: { |
| 4043 | OPC_CheckField, 0, 32, 0, // 7504: check Inst[31:0] == 0x0 |
| 4044 | OPC_Decode, 234, 5, 99, // 7508: decode to FSUBQim using decoder 99 |
| 4045 | // 7508: } |
| 4046 | 1, 0, // 7512: case 0x1: { |
| 4047 | OPC_CheckField, 0, 32, 0, // 7514: check Inst[31:0] == 0x0 |
| 4048 | OPC_Decode, 236, 5, 100, // 7518: decode to FSUBQrm using decoder 100 |
| 4049 | // 7518: } |
| 4050 | // 7518: } // switch Inst[47] |
| 4051 | // 7518: } |
| 4052 | 1, 0, // 7522: case 0x1: { |
| 4053 | OPC_SwitchField, 47, 1, // 7524: switch Inst[47] { |
| 4054 | 0, 8, // 7527: case 0x0: { |
| 4055 | OPC_CheckField, 0, 32, 0, // 7529: check Inst[31:0] == 0x0 |
| 4056 | OPC_Decode, 235, 5, 101, // 7533: decode to FSUBQir using decoder 101 |
| 4057 | // 7533: } |
| 4058 | 1, 0, // 7537: case 0x1: { |
| 4059 | OPC_CheckField, 0, 32, 0, // 7539: check Inst[31:0] == 0x0 |
| 4060 | OPC_Decode, 237, 5, 102, // 7543: decode to FSUBQrr using decoder 102 |
| 4061 | // 7543: } |
| 4062 | // 7543: } // switch Inst[47] |
| 4063 | // 7543: } |
| 4064 | // 7543: } // switch Inst[39] |
| 4065 | // 7543: } |
| 4066 | 250, 1, 53, // 7547: case 0xfa: { |
| 4067 | OPC_SwitchField, 39, 1, // 7550: switch Inst[39] { |
| 4068 | 0, 23, // 7553: case 0x0: { |
| 4069 | OPC_SwitchField, 47, 1, // 7555: switch Inst[47] { |
| 4070 | 0, 8, // 7558: case 0x0: { |
| 4071 | OPC_CheckField, 0, 32, 0, // 7560: check Inst[31:0] == 0x0 |
| 4072 | OPC_Decode, 181, 5, 51, // 7564: decode to FCMPQim using decoder 51 |
| 4073 | // 7564: } |
| 4074 | 1, 0, // 7568: case 0x1: { |
| 4075 | OPC_CheckField, 0, 32, 0, // 7570: check Inst[31:0] == 0x0 |
| 4076 | OPC_Decode, 183, 5, 107, // 7574: decode to FCMPQrm using decoder 107 |
| 4077 | // 7574: } |
| 4078 | // 7574: } // switch Inst[47] |
| 4079 | // 7574: } |
| 4080 | 1, 0, // 7578: case 0x1: { |
| 4081 | OPC_SwitchField, 47, 1, // 7580: switch Inst[47] { |
| 4082 | 0, 8, // 7583: case 0x0: { |
| 4083 | OPC_CheckField, 0, 32, 0, // 7585: check Inst[31:0] == 0x0 |
| 4084 | OPC_Decode, 182, 5, 108, // 7589: decode to FCMPQir using decoder 108 |
| 4085 | // 7589: } |
| 4086 | 1, 0, // 7593: case 0x1: { |
| 4087 | OPC_CheckField, 0, 32, 0, // 7595: check Inst[31:0] == 0x0 |
| 4088 | OPC_Decode, 184, 5, 109, // 7599: decode to FCMPQrr using decoder 109 |
| 4089 | // 7599: } |
| 4090 | // 7599: } // switch Inst[47] |
| 4091 | // 7599: } |
| 4092 | // 7599: } // switch Inst[39] |
| 4093 | // 7599: } |
| 4094 | 252, 1, 53, // 7603: case 0xfc: { |
| 4095 | OPC_SwitchField, 39, 1, // 7606: switch Inst[39] { |
| 4096 | 0, 23, // 7609: case 0x0: { |
| 4097 | OPC_SwitchField, 47, 1, // 7611: switch Inst[47] { |
| 4098 | 0, 8, // 7614: case 0x0: { |
| 4099 | OPC_CheckField, 0, 32, 0, // 7616: check Inst[31:0] == 0x0 |
| 4100 | OPC_Decode, 177, 5, 51, // 7620: decode to FCMPDim using decoder 51 |
| 4101 | // 7620: } |
| 4102 | 1, 0, // 7624: case 0x1: { |
| 4103 | OPC_CheckField, 0, 32, 0, // 7626: check Inst[31:0] == 0x0 |
| 4104 | OPC_Decode, 179, 5, 52, // 7630: decode to FCMPDrm using decoder 52 |
| 4105 | // 7630: } |
| 4106 | // 7630: } // switch Inst[47] |
| 4107 | // 7630: } |
| 4108 | 1, 0, // 7634: case 0x1: { |
| 4109 | OPC_SwitchField, 47, 1, // 7636: switch Inst[47] { |
| 4110 | 0, 8, // 7639: case 0x0: { |
| 4111 | OPC_CheckField, 0, 32, 0, // 7641: check Inst[31:0] == 0x0 |
| 4112 | OPC_Decode, 178, 5, 53, // 7645: decode to FCMPDir using decoder 53 |
| 4113 | // 7645: } |
| 4114 | 1, 0, // 7649: case 0x1: { |
| 4115 | OPC_CheckField, 0, 32, 0, // 7651: check Inst[31:0] == 0x0 |
| 4116 | OPC_Decode, 180, 5, 54, // 7655: decode to FCMPDrr using decoder 54 |
| 4117 | // 7655: } |
| 4118 | // 7655: } // switch Inst[47] |
| 4119 | // 7655: } |
| 4120 | // 7655: } // switch Inst[39] |
| 4121 | // 7655: } |
| 4122 | 253, 1, 53, // 7659: case 0xfd: { |
| 4123 | OPC_SwitchField, 39, 1, // 7662: switch Inst[39] { |
| 4124 | 0, 23, // 7665: case 0x0: { |
| 4125 | OPC_SwitchField, 47, 1, // 7667: switch Inst[47] { |
| 4126 | 0, 8, // 7670: case 0x0: { |
| 4127 | OPC_CheckField, 0, 32, 0, // 7672: check Inst[31:0] == 0x0 |
| 4128 | OPC_Decode, 185, 5, 55, // 7676: decode to FCMPSim using decoder 55 |
| 4129 | // 7676: } |
| 4130 | 1, 0, // 7680: case 0x1: { |
| 4131 | OPC_CheckField, 0, 32, 0, // 7682: check Inst[31:0] == 0x0 |
| 4132 | OPC_Decode, 187, 5, 56, // 7686: decode to FCMPSrm using decoder 56 |
| 4133 | // 7686: } |
| 4134 | // 7686: } // switch Inst[47] |
| 4135 | // 7686: } |
| 4136 | 1, 0, // 7690: case 0x1: { |
| 4137 | OPC_SwitchField, 47, 1, // 7692: switch Inst[47] { |
| 4138 | 0, 8, // 7695: case 0x0: { |
| 4139 | OPC_CheckField, 0, 32, 0, // 7697: check Inst[31:0] == 0x0 |
| 4140 | OPC_Decode, 186, 5, 57, // 7701: decode to FCMPSir using decoder 57 |
| 4141 | // 7701: } |
| 4142 | 1, 0, // 7705: case 0x1: { |
| 4143 | OPC_CheckField, 0, 32, 0, // 7707: check Inst[31:0] == 0x0 |
| 4144 | OPC_Decode, 188, 5, 58, // 7711: decode to FCMPSrr using decoder 58 |
| 4145 | // 7711: } |
| 4146 | // 7711: } // switch Inst[47] |
| 4147 | // 7711: } |
| 4148 | // 7711: } // switch Inst[39] |
| 4149 | // 7711: } |
| 4150 | 254, 1, 53, // 7715: case 0xfe: { |
| 4151 | OPC_SwitchField, 39, 1, // 7718: switch Inst[39] { |
| 4152 | 0, 23, // 7721: case 0x0: { |
| 4153 | OPC_SwitchField, 47, 1, // 7723: switch Inst[47] { |
| 4154 | 0, 8, // 7726: case 0x0: { |
| 4155 | OPC_CheckField, 0, 32, 0, // 7728: check Inst[31:0] == 0x0 |
| 4156 | OPC_Decode, 252, 4, 51, // 7732: decode to DIVSLim using decoder 51 |
| 4157 | // 7732: } |
| 4158 | 1, 0, // 7736: case 0x1: { |
| 4159 | OPC_CheckField, 0, 32, 0, // 7738: check Inst[31:0] == 0x0 |
| 4160 | OPC_Decode, 254, 4, 52, // 7742: decode to DIVSLrm using decoder 52 |
| 4161 | // 7742: } |
| 4162 | // 7742: } // switch Inst[47] |
| 4163 | // 7742: } |
| 4164 | 1, 0, // 7746: case 0x1: { |
| 4165 | OPC_SwitchField, 47, 1, // 7748: switch Inst[47] { |
| 4166 | 0, 8, // 7751: case 0x0: { |
| 4167 | OPC_CheckField, 0, 32, 0, // 7753: check Inst[31:0] == 0x0 |
| 4168 | OPC_Decode, 253, 4, 53, // 7757: decode to DIVSLir using decoder 53 |
| 4169 | // 7757: } |
| 4170 | 1, 0, // 7761: case 0x1: { |
| 4171 | OPC_CheckField, 0, 32, 0, // 7763: check Inst[31:0] == 0x0 |
| 4172 | OPC_Decode, 255, 4, 54, // 7767: decode to DIVSLrr using decoder 54 |
| 4173 | // 7767: } |
| 4174 | // 7767: } // switch Inst[47] |
| 4175 | // 7767: } |
| 4176 | // 7767: } // switch Inst[39] |
| 4177 | // 7767: } |
| 4178 | 128, 2, 105, // 7771: case 0x100: { |
| 4179 | OPC_SwitchField, 47, 8, // 7774: switch Inst[54:47] { |
| 4180 | 0, 23, // 7777: case 0x0: { |
| 4181 | OPC_SwitchField, 39, 1, // 7779: switch Inst[39] { |
| 4182 | 0, 8, // 7782: case 0x0: { |
| 4183 | OPC_CheckField, 0, 32, 0, // 7784: check Inst[31:0] == 0x0 |
| 4184 | OPC_Decode, 142, 7, 110, // 7788: decode to PFCHVNCiz using decoder 110 |
| 4185 | // 7788: } |
| 4186 | 1, 0, // 7792: case 0x1: { |
| 4187 | OPC_CheckField, 0, 32, 0, // 7794: check Inst[31:0] == 0x0 |
| 4188 | OPC_Decode, 139, 7, 111, // 7798: decode to PFCHVNCir using decoder 111 |
| 4189 | // 7798: } |
| 4190 | // 7798: } // switch Inst[39] |
| 4191 | // 7798: } |
| 4192 | 1, 23, // 7802: case 0x1: { |
| 4193 | OPC_SwitchField, 39, 1, // 7804: switch Inst[39] { |
| 4194 | 0, 8, // 7807: case 0x0: { |
| 4195 | OPC_CheckField, 0, 32, 0, // 7809: check Inst[31:0] == 0x0 |
| 4196 | OPC_Decode, 148, 7, 112, // 7813: decode to PFCHVNCrz using decoder 112 |
| 4197 | // 7813: } |
| 4198 | 1, 0, // 7817: case 0x1: { |
| 4199 | OPC_CheckField, 0, 32, 0, // 7819: check Inst[31:0] == 0x0 |
| 4200 | OPC_Decode, 145, 7, 113, // 7823: decode to PFCHVNCrr using decoder 113 |
| 4201 | // 7823: } |
| 4202 | // 7823: } // switch Inst[39] |
| 4203 | // 7823: } |
| 4204 | 128, 1, 23, // 7827: case 0x80: { |
| 4205 | OPC_SwitchField, 39, 1, // 7830: switch Inst[39] { |
| 4206 | 0, 8, // 7833: case 0x0: { |
| 4207 | OPC_CheckField, 0, 32, 0, // 7835: check Inst[31:0] == 0x0 |
| 4208 | OPC_Decode, 154, 7, 110, // 7839: decode to PFCHViz using decoder 110 |
| 4209 | // 7839: } |
| 4210 | 1, 0, // 7843: case 0x1: { |
| 4211 | OPC_CheckField, 0, 32, 0, // 7845: check Inst[31:0] == 0x0 |
| 4212 | OPC_Decode, 151, 7, 111, // 7849: decode to PFCHVir using decoder 111 |
| 4213 | // 7849: } |
| 4214 | // 7849: } // switch Inst[39] |
| 4215 | // 7849: } |
| 4216 | 129, 1, 0, // 7853: case 0x81: { |
| 4217 | OPC_SwitchField, 39, 1, // 7856: switch Inst[39] { |
| 4218 | 0, 8, // 7859: case 0x0: { |
| 4219 | OPC_CheckField, 0, 32, 0, // 7861: check Inst[31:0] == 0x0 |
| 4220 | OPC_Decode, 160, 7, 112, // 7865: decode to PFCHVrz using decoder 112 |
| 4221 | // 7865: } |
| 4222 | 1, 0, // 7869: case 0x1: { |
| 4223 | OPC_CheckField, 0, 32, 0, // 7871: check Inst[31:0] == 0x0 |
| 4224 | OPC_Decode, 157, 7, 113, // 7875: decode to PFCHVrr using decoder 113 |
| 4225 | // 7875: } |
| 4226 | // 7875: } // switch Inst[39] |
| 4227 | // 7875: } |
| 4228 | // 7875: } // switch Inst[54:47] |
| 4229 | // 7875: } |
| 4230 | 130, 2, 105, // 7879: case 0x102: { |
| 4231 | OPC_SwitchField, 47, 8, // 7882: switch Inst[54:47] { |
| 4232 | 0, 23, // 7885: case 0x0: { |
| 4233 | OPC_SwitchField, 39, 1, // 7887: switch Inst[39] { |
| 4234 | 0, 8, // 7890: case 0x0: { |
| 4235 | OPC_CheckField, 0, 24, 0, // 7892: check Inst[23:0] == 0x0 |
| 4236 | OPC_Decode, 158, 62, 114, // 7896: decode to VLDNCiz using decoder 114 |
| 4237 | // 7896: } |
| 4238 | 1, 0, // 7900: case 0x1: { |
| 4239 | OPC_CheckField, 0, 24, 0, // 7902: check Inst[23:0] == 0x0 |
| 4240 | OPC_Decode, 152, 62, 115, // 7906: decode to VLDNCir using decoder 115 |
| 4241 | // 7906: } |
| 4242 | // 7906: } // switch Inst[39] |
| 4243 | // 7906: } |
| 4244 | 1, 23, // 7910: case 0x1: { |
| 4245 | OPC_SwitchField, 39, 1, // 7912: switch Inst[39] { |
| 4246 | 0, 8, // 7915: case 0x0: { |
| 4247 | OPC_CheckField, 0, 24, 0, // 7917: check Inst[23:0] == 0x0 |
| 4248 | OPC_Decode, 170, 62, 116, // 7921: decode to VLDNCrz using decoder 116 |
| 4249 | // 7921: } |
| 4250 | 1, 0, // 7925: case 0x1: { |
| 4251 | OPC_CheckField, 0, 24, 0, // 7927: check Inst[23:0] == 0x0 |
| 4252 | OPC_Decode, 164, 62, 117, // 7931: decode to VLDNCrr using decoder 117 |
| 4253 | // 7931: } |
| 4254 | // 7931: } // switch Inst[39] |
| 4255 | // 7931: } |
| 4256 | 128, 1, 23, // 7935: case 0x80: { |
| 4257 | OPC_SwitchField, 39, 1, // 7938: switch Inst[39] { |
| 4258 | 0, 8, // 7941: case 0x0: { |
| 4259 | OPC_CheckField, 0, 24, 0, // 7943: check Inst[23:0] == 0x0 |
| 4260 | OPC_Decode, 162, 63, 114, // 7947: decode to VLDiz using decoder 114 |
| 4261 | // 7947: } |
| 4262 | 1, 0, // 7951: case 0x1: { |
| 4263 | OPC_CheckField, 0, 24, 0, // 7953: check Inst[23:0] == 0x0 |
| 4264 | OPC_Decode, 156, 63, 115, // 7957: decode to VLDir using decoder 115 |
| 4265 | // 7957: } |
| 4266 | // 7957: } // switch Inst[39] |
| 4267 | // 7957: } |
| 4268 | 129, 1, 0, // 7961: case 0x81: { |
| 4269 | OPC_SwitchField, 39, 1, // 7964: switch Inst[39] { |
| 4270 | 0, 8, // 7967: case 0x0: { |
| 4271 | OPC_CheckField, 0, 24, 0, // 7969: check Inst[23:0] == 0x0 |
| 4272 | OPC_Decode, 174, 63, 116, // 7973: decode to VLDrz using decoder 116 |
| 4273 | // 7973: } |
| 4274 | 1, 0, // 7977: case 0x1: { |
| 4275 | OPC_CheckField, 0, 24, 0, // 7979: check Inst[23:0] == 0x0 |
| 4276 | OPC_Decode, 168, 63, 117, // 7983: decode to VLDrr using decoder 117 |
| 4277 | // 7983: } |
| 4278 | // 7983: } // switch Inst[39] |
| 4279 | // 7983: } |
| 4280 | // 7983: } // switch Inst[54:47] |
| 4281 | // 7983: } |
| 4282 | 132, 2, 105, // 7987: case 0x104: { |
| 4283 | OPC_SwitchField, 47, 8, // 7990: switch Inst[54:47] { |
| 4284 | 0, 23, // 7993: case 0x0: { |
| 4285 | OPC_SwitchField, 39, 1, // 7995: switch Inst[39] { |
| 4286 | 0, 8, // 7998: case 0x0: { |
| 4287 | OPC_CheckField, 0, 24, 0, // 8000: check Inst[23:0] == 0x0 |
| 4288 | OPC_Decode, 230, 62, 114, // 8004: decode to VLDUNCiz using decoder 114 |
| 4289 | // 8004: } |
| 4290 | 1, 0, // 8008: case 0x1: { |
| 4291 | OPC_CheckField, 0, 24, 0, // 8010: check Inst[23:0] == 0x0 |
| 4292 | OPC_Decode, 224, 62, 115, // 8014: decode to VLDUNCir using decoder 115 |
| 4293 | // 8014: } |
| 4294 | // 8014: } // switch Inst[39] |
| 4295 | // 8014: } |
| 4296 | 1, 23, // 8018: case 0x1: { |
| 4297 | OPC_SwitchField, 39, 1, // 8020: switch Inst[39] { |
| 4298 | 0, 8, // 8023: case 0x0: { |
| 4299 | OPC_CheckField, 0, 24, 0, // 8025: check Inst[23:0] == 0x0 |
| 4300 | OPC_Decode, 242, 62, 116, // 8029: decode to VLDUNCrz using decoder 116 |
| 4301 | // 8029: } |
| 4302 | 1, 0, // 8033: case 0x1: { |
| 4303 | OPC_CheckField, 0, 24, 0, // 8035: check Inst[23:0] == 0x0 |
| 4304 | OPC_Decode, 236, 62, 117, // 8039: decode to VLDUNCrr using decoder 117 |
| 4305 | // 8039: } |
| 4306 | // 8039: } // switch Inst[39] |
| 4307 | // 8039: } |
| 4308 | 128, 1, 23, // 8043: case 0x80: { |
| 4309 | OPC_SwitchField, 39, 1, // 8046: switch Inst[39] { |
| 4310 | 0, 8, // 8049: case 0x0: { |
| 4311 | OPC_CheckField, 0, 24, 0, // 8051: check Inst[23:0] == 0x0 |
| 4312 | OPC_Decode, 254, 62, 114, // 8055: decode to VLDUiz using decoder 114 |
| 4313 | // 8055: } |
| 4314 | 1, 0, // 8059: case 0x1: { |
| 4315 | OPC_CheckField, 0, 24, 0, // 8061: check Inst[23:0] == 0x0 |
| 4316 | OPC_Decode, 248, 62, 115, // 8065: decode to VLDUir using decoder 115 |
| 4317 | // 8065: } |
| 4318 | // 8065: } // switch Inst[39] |
| 4319 | // 8065: } |
| 4320 | 129, 1, 0, // 8069: case 0x81: { |
| 4321 | OPC_SwitchField, 39, 1, // 8072: switch Inst[39] { |
| 4322 | 0, 8, // 8075: case 0x0: { |
| 4323 | OPC_CheckField, 0, 24, 0, // 8077: check Inst[23:0] == 0x0 |
| 4324 | OPC_Decode, 138, 63, 116, // 8081: decode to VLDUrz using decoder 116 |
| 4325 | // 8081: } |
| 4326 | 1, 0, // 8085: case 0x1: { |
| 4327 | OPC_CheckField, 0, 24, 0, // 8087: check Inst[23:0] == 0x0 |
| 4328 | OPC_Decode, 132, 63, 117, // 8091: decode to VLDUrr using decoder 117 |
| 4329 | // 8091: } |
| 4330 | // 8091: } // switch Inst[39] |
| 4331 | // 8091: } |
| 4332 | // 8091: } // switch Inst[54:47] |
| 4333 | // 8091: } |
| 4334 | 134, 2, 105, // 8095: case 0x106: { |
| 4335 | OPC_SwitchField, 47, 8, // 8098: switch Inst[54:47] { |
| 4336 | 0, 23, // 8101: case 0x0: { |
| 4337 | OPC_SwitchField, 39, 1, // 8103: switch Inst[39] { |
| 4338 | 0, 8, // 8106: case 0x0: { |
| 4339 | OPC_CheckField, 0, 24, 0, // 8108: check Inst[23:0] == 0x0 |
| 4340 | OPC_Decode, 190, 61, 114, // 8112: decode to VLDLSXNCiz using decoder 114 |
| 4341 | // 8112: } |
| 4342 | 1, 0, // 8116: case 0x1: { |
| 4343 | OPC_CheckField, 0, 24, 0, // 8118: check Inst[23:0] == 0x0 |
| 4344 | OPC_Decode, 184, 61, 115, // 8122: decode to VLDLSXNCir using decoder 115 |
| 4345 | // 8122: } |
| 4346 | // 8122: } // switch Inst[39] |
| 4347 | // 8122: } |
| 4348 | 1, 23, // 8126: case 0x1: { |
| 4349 | OPC_SwitchField, 39, 1, // 8128: switch Inst[39] { |
| 4350 | 0, 8, // 8131: case 0x0: { |
| 4351 | OPC_CheckField, 0, 24, 0, // 8133: check Inst[23:0] == 0x0 |
| 4352 | OPC_Decode, 202, 61, 116, // 8137: decode to VLDLSXNCrz using decoder 116 |
| 4353 | // 8137: } |
| 4354 | 1, 0, // 8141: case 0x1: { |
| 4355 | OPC_CheckField, 0, 24, 0, // 8143: check Inst[23:0] == 0x0 |
| 4356 | OPC_Decode, 196, 61, 117, // 8147: decode to VLDLSXNCrr using decoder 117 |
| 4357 | // 8147: } |
| 4358 | // 8147: } // switch Inst[39] |
| 4359 | // 8147: } |
| 4360 | 128, 1, 23, // 8151: case 0x80: { |
| 4361 | OPC_SwitchField, 39, 1, // 8154: switch Inst[39] { |
| 4362 | 0, 8, // 8157: case 0x0: { |
| 4363 | OPC_CheckField, 0, 24, 0, // 8159: check Inst[23:0] == 0x0 |
| 4364 | OPC_Decode, 214, 61, 114, // 8163: decode to VLDLSXiz using decoder 114 |
| 4365 | // 8163: } |
| 4366 | 1, 0, // 8167: case 0x1: { |
| 4367 | OPC_CheckField, 0, 24, 0, // 8169: check Inst[23:0] == 0x0 |
| 4368 | OPC_Decode, 208, 61, 115, // 8173: decode to VLDLSXir using decoder 115 |
| 4369 | // 8173: } |
| 4370 | // 8173: } // switch Inst[39] |
| 4371 | // 8173: } |
| 4372 | 129, 1, 0, // 8177: case 0x81: { |
| 4373 | OPC_SwitchField, 39, 1, // 8180: switch Inst[39] { |
| 4374 | 0, 8, // 8183: case 0x0: { |
| 4375 | OPC_CheckField, 0, 24, 0, // 8185: check Inst[23:0] == 0x0 |
| 4376 | OPC_Decode, 226, 61, 116, // 8189: decode to VLDLSXrz using decoder 116 |
| 4377 | // 8189: } |
| 4378 | 1, 0, // 8193: case 0x1: { |
| 4379 | OPC_CheckField, 0, 24, 0, // 8195: check Inst[23:0] == 0x0 |
| 4380 | OPC_Decode, 220, 61, 117, // 8199: decode to VLDLSXrr using decoder 117 |
| 4381 | // 8199: } |
| 4382 | // 8199: } // switch Inst[39] |
| 4383 | // 8199: } |
| 4384 | // 8199: } // switch Inst[54:47] |
| 4385 | // 8199: } |
| 4386 | 135, 2, 105, // 8203: case 0x107: { |
| 4387 | OPC_SwitchField, 47, 8, // 8206: switch Inst[54:47] { |
| 4388 | 0, 23, // 8209: case 0x0: { |
| 4389 | OPC_SwitchField, 39, 1, // 8211: switch Inst[39] { |
| 4390 | 0, 8, // 8214: case 0x0: { |
| 4391 | OPC_CheckField, 0, 24, 0, // 8216: check Inst[23:0] == 0x0 |
| 4392 | OPC_Decode, 238, 61, 114, // 8220: decode to VLDLZXNCiz using decoder 114 |
| 4393 | // 8220: } |
| 4394 | 1, 0, // 8224: case 0x1: { |
| 4395 | OPC_CheckField, 0, 24, 0, // 8226: check Inst[23:0] == 0x0 |
| 4396 | OPC_Decode, 232, 61, 115, // 8230: decode to VLDLZXNCir using decoder 115 |
| 4397 | // 8230: } |
| 4398 | // 8230: } // switch Inst[39] |
| 4399 | // 8230: } |
| 4400 | 1, 23, // 8234: case 0x1: { |
| 4401 | OPC_SwitchField, 39, 1, // 8236: switch Inst[39] { |
| 4402 | 0, 8, // 8239: case 0x0: { |
| 4403 | OPC_CheckField, 0, 24, 0, // 8241: check Inst[23:0] == 0x0 |
| 4404 | OPC_Decode, 250, 61, 116, // 8245: decode to VLDLZXNCrz using decoder 116 |
| 4405 | // 8245: } |
| 4406 | 1, 0, // 8249: case 0x1: { |
| 4407 | OPC_CheckField, 0, 24, 0, // 8251: check Inst[23:0] == 0x0 |
| 4408 | OPC_Decode, 244, 61, 117, // 8255: decode to VLDLZXNCrr using decoder 117 |
| 4409 | // 8255: } |
| 4410 | // 8255: } // switch Inst[39] |
| 4411 | // 8255: } |
| 4412 | 128, 1, 23, // 8259: case 0x80: { |
| 4413 | OPC_SwitchField, 39, 1, // 8262: switch Inst[39] { |
| 4414 | 0, 8, // 8265: case 0x0: { |
| 4415 | OPC_CheckField, 0, 24, 0, // 8267: check Inst[23:0] == 0x0 |
| 4416 | OPC_Decode, 134, 62, 114, // 8271: decode to VLDLZXiz using decoder 114 |
| 4417 | // 8271: } |
| 4418 | 1, 0, // 8275: case 0x1: { |
| 4419 | OPC_CheckField, 0, 24, 0, // 8277: check Inst[23:0] == 0x0 |
| 4420 | OPC_Decode, 128, 62, 115, // 8281: decode to VLDLZXir using decoder 115 |
| 4421 | // 8281: } |
| 4422 | // 8281: } // switch Inst[39] |
| 4423 | // 8281: } |
| 4424 | 129, 1, 0, // 8285: case 0x81: { |
| 4425 | OPC_SwitchField, 39, 1, // 8288: switch Inst[39] { |
| 4426 | 0, 8, // 8291: case 0x0: { |
| 4427 | OPC_CheckField, 0, 24, 0, // 8293: check Inst[23:0] == 0x0 |
| 4428 | OPC_Decode, 146, 62, 116, // 8297: decode to VLDLZXrz using decoder 116 |
| 4429 | // 8297: } |
| 4430 | 1, 0, // 8301: case 0x1: { |
| 4431 | OPC_CheckField, 0, 24, 0, // 8303: check Inst[23:0] == 0x0 |
| 4432 | OPC_Decode, 140, 62, 117, // 8307: decode to VLDLZXrr using decoder 117 |
| 4433 | // 8307: } |
| 4434 | // 8307: } // switch Inst[39] |
| 4435 | // 8307: } |
| 4436 | // 8307: } // switch Inst[54:47] |
| 4437 | // 8307: } |
| 4438 | 136, 2, 12, // 8311: case 0x108: { |
| 4439 | OPC_CheckField, 32, 23, 0, // 8314: check Inst[54:32] == 0x0 |
| 4440 | OPC_CheckField, 0, 8, 0, // 8318: check Inst[7:0] == 0x0 |
| 4441 | OPC_Decode, 250, 2, 118, // 8322: decode to ANDMmm using decoder 118 |
| 4442 | // 8322: } |
| 4443 | 138, 2, 12, // 8326: case 0x10a: { |
| 4444 | OPC_CheckField, 32, 23, 0, // 8329: check Inst[54:32] == 0x0 |
| 4445 | OPC_CheckField, 0, 8, 0, // 8333: check Inst[7:0] == 0x0 |
| 4446 | OPC_Decode, 129, 7, 118, // 8337: decode to ORMmm using decoder 118 |
| 4447 | // 8337: } |
| 4448 | 140, 2, 12, // 8341: case 0x10c: { |
| 4449 | OPC_CheckField, 32, 23, 0, // 8344: check Inst[54:32] == 0x0 |
| 4450 | OPC_CheckField, 0, 8, 0, // 8348: check Inst[7:0] == 0x0 |
| 4451 | OPC_Decode, 132, 84, 118, // 8352: decode to XORMmm using decoder 118 |
| 4452 | // 8352: } |
| 4453 | 142, 2, 12, // 8356: case 0x10e: { |
| 4454 | OPC_CheckField, 32, 23, 0, // 8359: check Inst[54:32] == 0x0 |
| 4455 | OPC_CheckField, 0, 8, 0, // 8363: check Inst[7:0] == 0x0 |
| 4456 | OPC_Decode, 160, 5, 118, // 8367: decode to EQVMmm using decoder 118 |
| 4457 | // 8367: } |
| 4458 | 144, 2, 26, // 8371: case 0x110: { |
| 4459 | OPC_CheckField, 0, 16, 0, // 8374: check Inst[15:0] == 0x0 |
| 4460 | OPC_CheckField, 32, 16, 0, // 8378: check Inst[47:32] == 0x0 |
| 4461 | OPC_CheckField, 52, 3, 0, // 8382: check Inst[54:52] == 0x0 |
| 4462 | OPC_Scope, 8, // 8386: try { |
| 4463 | OPC_CheckField, 48, 4, 0, // 8388: check Inst[51:48] == 0x0 |
| 4464 | OPC_Decode, 244, 67, 119, // 8392: decode to VRANDv using decoder 119 |
| 4465 | // 8392: } else try { |
| 4466 | OPC_Decode, 250, 67, 120, // 8396: decode to VRANDvm using decoder 120 |
| 4467 | // 8396: } |
| 4468 | // 8396: } |
| 4469 | 146, 2, 26, // 8400: case 0x112: { |
| 4470 | OPC_CheckField, 0, 16, 0, // 8403: check Inst[15:0] == 0x0 |
| 4471 | OPC_CheckField, 32, 16, 0, // 8407: check Inst[47:32] == 0x0 |
| 4472 | OPC_CheckField, 52, 3, 0, // 8411: check Inst[54:52] == 0x0 |
| 4473 | OPC_Scope, 8, // 8415: try { |
| 4474 | OPC_CheckField, 48, 4, 0, // 8417: check Inst[51:48] == 0x0 |
| 4475 | OPC_Decode, 228, 69, 119, // 8421: decode to VRXORv using decoder 119 |
| 4476 | // 8421: } else try { |
| 4477 | OPC_Decode, 234, 69, 120, // 8425: decode to VRXORvm using decoder 120 |
| 4478 | // 8425: } |
| 4479 | // 8425: } |
| 4480 | 148, 2, 215, 2, // 8429: case 0x114: { |
| 4481 | OPC_SwitchField, 52, 3, // 8433: switch Inst[54:52] { |
| 4482 | 0, 22, // 8436: case 0x0: { |
| 4483 | OPC_CheckField, 0, 8, 0, // 8438: check Inst[7:0] == 0x0 |
| 4484 | OPC_CheckField, 32, 16, 0, // 8442: check Inst[47:32] == 0x0 |
| 4485 | OPC_Scope, 8, // 8446: try { |
| 4486 | OPC_CheckField, 48, 4, 0, // 8448: check Inst[51:48] == 0x0 |
| 4487 | OPC_Decode, 240, 63, 121, // 8452: decode to VMAXSWSXvv using decoder 121 |
| 4488 | // 8452: } else try { |
| 4489 | OPC_Decode, 246, 63, 122, // 8456: decode to VMAXSWSXvvm using decoder 122 |
| 4490 | // 8456: } |
| 4491 | // 8456: } |
| 4492 | 1, 22, // 8460: case 0x1: { |
| 4493 | OPC_CheckField, 0, 8, 0, // 8462: check Inst[7:0] == 0x0 |
| 4494 | OPC_CheckField, 32, 16, 0, // 8466: check Inst[47:32] == 0x0 |
| 4495 | OPC_Scope, 8, // 8470: try { |
| 4496 | OPC_CheckField, 48, 4, 0, // 8472: check Inst[51:48] == 0x0 |
| 4497 | OPC_Decode, 220, 64, 121, // 8476: decode to VMINSWSXvv using decoder 121 |
| 4498 | // 8476: } else try { |
| 4499 | OPC_Decode, 226, 64, 122, // 8480: decode to VMINSWSXvvm using decoder 122 |
| 4500 | // 8480: } |
| 4501 | // 8480: } |
| 4502 | 2, 59, // 8484: case 0x2: { |
| 4503 | OPC_SwitchField, 47, 1, // 8486: switch Inst[47] { |
| 4504 | 0, 26, // 8489: case 0x0: { |
| 4505 | OPC_CheckField, 0, 8, 0, // 8491: check Inst[7:0] == 0x0 |
| 4506 | OPC_CheckField, 16, 8, 0, // 8495: check Inst[23:16] == 0x0 |
| 4507 | OPC_CheckField, 32, 8, 0, // 8499: check Inst[39:32] == 0x0 |
| 4508 | OPC_Scope, 8, // 8503: try { |
| 4509 | OPC_CheckField, 48, 4, 0, // 8505: check Inst[51:48] == 0x0 |
| 4510 | OPC_Decode, 216, 63, 123, // 8509: decode to VMAXSWSXiv using decoder 123 |
| 4511 | // 8509: } else try { |
| 4512 | OPC_Decode, 222, 63, 124, // 8513: decode to VMAXSWSXivm using decoder 124 |
| 4513 | // 8513: } |
| 4514 | // 8513: } |
| 4515 | 1, 0, // 8517: case 0x1: { |
| 4516 | OPC_CheckField, 0, 8, 0, // 8519: check Inst[7:0] == 0x0 |
| 4517 | OPC_CheckField, 16, 8, 0, // 8523: check Inst[23:16] == 0x0 |
| 4518 | OPC_CheckField, 32, 8, 0, // 8527: check Inst[39:32] == 0x0 |
| 4519 | OPC_Scope, 8, // 8531: try { |
| 4520 | OPC_CheckField, 48, 4, 0, // 8533: check Inst[51:48] == 0x0 |
| 4521 | OPC_Decode, 228, 63, 125, // 8537: decode to VMAXSWSXrv using decoder 125 |
| 4522 | // 8537: } else try { |
| 4523 | OPC_Decode, 234, 63, 126, // 8541: decode to VMAXSWSXrvm using decoder 126 |
| 4524 | // 8541: } |
| 4525 | // 8541: } |
| 4526 | // 8541: } // switch Inst[47] |
| 4527 | // 8541: } |
| 4528 | 3, 59, // 8545: case 0x3: { |
| 4529 | OPC_SwitchField, 47, 1, // 8547: switch Inst[47] { |
| 4530 | 0, 26, // 8550: case 0x0: { |
| 4531 | OPC_CheckField, 0, 8, 0, // 8552: check Inst[7:0] == 0x0 |
| 4532 | OPC_CheckField, 16, 8, 0, // 8556: check Inst[23:16] == 0x0 |
| 4533 | OPC_CheckField, 32, 8, 0, // 8560: check Inst[39:32] == 0x0 |
| 4534 | OPC_Scope, 8, // 8564: try { |
| 4535 | OPC_CheckField, 48, 4, 0, // 8566: check Inst[51:48] == 0x0 |
| 4536 | OPC_Decode, 196, 64, 123, // 8570: decode to VMINSWSXiv using decoder 123 |
| 4537 | // 8570: } else try { |
| 4538 | OPC_Decode, 202, 64, 124, // 8574: decode to VMINSWSXivm using decoder 124 |
| 4539 | // 8574: } |
| 4540 | // 8574: } |
| 4541 | 1, 0, // 8578: case 0x1: { |
| 4542 | OPC_CheckField, 0, 8, 0, // 8580: check Inst[7:0] == 0x0 |
| 4543 | OPC_CheckField, 16, 8, 0, // 8584: check Inst[23:16] == 0x0 |
| 4544 | OPC_CheckField, 32, 8, 0, // 8588: check Inst[39:32] == 0x0 |
| 4545 | OPC_Scope, 8, // 8592: try { |
| 4546 | OPC_CheckField, 48, 4, 0, // 8594: check Inst[51:48] == 0x0 |
| 4547 | OPC_Decode, 208, 64, 125, // 8598: decode to VMINSWSXrv using decoder 125 |
| 4548 | // 8598: } else try { |
| 4549 | OPC_Decode, 214, 64, 126, // 8602: decode to VMINSWSXrvm using decoder 126 |
| 4550 | // 8602: } |
| 4551 | // 8602: } |
| 4552 | // 8602: } // switch Inst[47] |
| 4553 | // 8602: } |
| 4554 | 4, 22, // 8606: case 0x4: { |
| 4555 | OPC_CheckField, 0, 8, 0, // 8608: check Inst[7:0] == 0x0 |
| 4556 | OPC_CheckField, 32, 16, 0, // 8612: check Inst[47:32] == 0x0 |
| 4557 | OPC_Scope, 8, // 8616: try { |
| 4558 | OPC_CheckField, 48, 4, 0, // 8618: check Inst[51:48] == 0x0 |
| 4559 | OPC_Decode, 143, 25, 121, // 8622: decode to PVMAXSLOvv using decoder 121 |
| 4560 | // 8622: } else try { |
| 4561 | OPC_Decode, 149, 25, 122, // 8626: decode to PVMAXSLOvvm using decoder 122 |
| 4562 | // 8626: } |
| 4563 | // 8626: } |
| 4564 | 5, 22, // 8630: case 0x5: { |
| 4565 | OPC_CheckField, 0, 8, 0, // 8632: check Inst[7:0] == 0x0 |
| 4566 | OPC_CheckField, 32, 16, 0, // 8636: check Inst[47:32] == 0x0 |
| 4567 | OPC_Scope, 8, // 8640: try { |
| 4568 | OPC_CheckField, 48, 4, 0, // 8642: check Inst[51:48] == 0x0 |
| 4569 | OPC_Decode, 251, 25, 121, // 8646: decode to PVMINSLOvv using decoder 121 |
| 4570 | // 8646: } else try { |
| 4571 | OPC_Decode, 129, 26, 122, // 8650: decode to PVMINSLOvvm using decoder 122 |
| 4572 | // 8650: } |
| 4573 | // 8650: } |
| 4574 | 6, 59, // 8654: case 0x6: { |
| 4575 | OPC_SwitchField, 47, 1, // 8656: switch Inst[47] { |
| 4576 | 0, 26, // 8659: case 0x0: { |
| 4577 | OPC_CheckField, 0, 8, 0, // 8661: check Inst[7:0] == 0x0 |
| 4578 | OPC_CheckField, 16, 8, 0, // 8665: check Inst[23:16] == 0x0 |
| 4579 | OPC_CheckField, 32, 8, 0, // 8669: check Inst[39:32] == 0x0 |
| 4580 | OPC_Scope, 8, // 8673: try { |
| 4581 | OPC_CheckField, 48, 4, 0, // 8675: check Inst[51:48] == 0x0 |
| 4582 | OPC_Decode, 247, 24, 123, // 8679: decode to PVMAXSLOiv using decoder 123 |
| 4583 | // 8679: } else try { |
| 4584 | OPC_Decode, 253, 24, 124, // 8683: decode to PVMAXSLOivm using decoder 124 |
| 4585 | // 8683: } |
| 4586 | // 8683: } |
| 4587 | 1, 0, // 8687: case 0x1: { |
| 4588 | OPC_CheckField, 0, 8, 0, // 8689: check Inst[7:0] == 0x0 |
| 4589 | OPC_CheckField, 16, 8, 0, // 8693: check Inst[23:16] == 0x0 |
| 4590 | OPC_CheckField, 32, 8, 0, // 8697: check Inst[39:32] == 0x0 |
| 4591 | OPC_Scope, 8, // 8701: try { |
| 4592 | OPC_CheckField, 48, 4, 0, // 8703: check Inst[51:48] == 0x0 |
| 4593 | OPC_Decode, 131, 25, 125, // 8707: decode to PVMAXSLOrv using decoder 125 |
| 4594 | // 8707: } else try { |
| 4595 | OPC_Decode, 137, 25, 126, // 8711: decode to PVMAXSLOrvm using decoder 126 |
| 4596 | // 8711: } |
| 4597 | // 8711: } |
| 4598 | // 8711: } // switch Inst[47] |
| 4599 | // 8711: } |
| 4600 | 7, 0, // 8715: case 0x7: { |
| 4601 | OPC_SwitchField, 47, 1, // 8717: switch Inst[47] { |
| 4602 | 0, 26, // 8720: case 0x0: { |
| 4603 | OPC_CheckField, 0, 8, 0, // 8722: check Inst[7:0] == 0x0 |
| 4604 | OPC_CheckField, 16, 8, 0, // 8726: check Inst[23:16] == 0x0 |
| 4605 | OPC_CheckField, 32, 8, 0, // 8730: check Inst[39:32] == 0x0 |
| 4606 | OPC_Scope, 8, // 8734: try { |
| 4607 | OPC_CheckField, 48, 4, 0, // 8736: check Inst[51:48] == 0x0 |
| 4608 | OPC_Decode, 227, 25, 123, // 8740: decode to PVMINSLOiv using decoder 123 |
| 4609 | // 8740: } else try { |
| 4610 | OPC_Decode, 233, 25, 124, // 8744: decode to PVMINSLOivm using decoder 124 |
| 4611 | // 8744: } |
| 4612 | // 8744: } |
| 4613 | 1, 0, // 8748: case 0x1: { |
| 4614 | OPC_CheckField, 0, 8, 0, // 8750: check Inst[7:0] == 0x0 |
| 4615 | OPC_CheckField, 16, 8, 0, // 8754: check Inst[23:16] == 0x0 |
| 4616 | OPC_CheckField, 32, 8, 0, // 8758: check Inst[39:32] == 0x0 |
| 4617 | OPC_Scope, 8, // 8762: try { |
| 4618 | OPC_CheckField, 48, 4, 0, // 8764: check Inst[51:48] == 0x0 |
| 4619 | OPC_Decode, 239, 25, 125, // 8768: decode to PVMINSLOrv using decoder 125 |
| 4620 | // 8768: } else try { |
| 4621 | OPC_Decode, 245, 25, 126, // 8772: decode to PVMINSLOrvm using decoder 126 |
| 4622 | // 8772: } |
| 4623 | // 8772: } |
| 4624 | // 8772: } // switch Inst[47] |
| 4625 | // 8772: } |
| 4626 | // 8772: } // switch Inst[54:52] |
| 4627 | // 8772: } |
| 4628 | 149, 2, 223, 2, // 8776: case 0x115: { |
| 4629 | OPC_SwitchField, 52, 3, // 8780: switch Inst[54:52] { |
| 4630 | 0, 22, // 8783: case 0x0: { |
| 4631 | OPC_CheckField, 0, 8, 0, // 8785: check Inst[7:0] == 0x0 |
| 4632 | OPC_CheckField, 32, 16, 0, // 8789: check Inst[47:32] == 0x0 |
| 4633 | OPC_Scope, 8, // 8793: try { |
| 4634 | OPC_CheckField, 48, 4, 0, // 8795: check Inst[51:48] == 0x0 |
| 4635 | OPC_Decode, 179, 25, 121, // 8799: decode to PVMAXSUPvv using decoder 121 |
| 4636 | // 8799: } else try { |
| 4637 | OPC_Decode, 185, 25, 122, // 8803: decode to PVMAXSUPvvm using decoder 122 |
| 4638 | // 8803: } |
| 4639 | // 8803: } |
| 4640 | 1, 22, // 8807: case 0x1: { |
| 4641 | OPC_CheckField, 0, 8, 0, // 8809: check Inst[7:0] == 0x0 |
| 4642 | OPC_CheckField, 32, 16, 0, // 8813: check Inst[47:32] == 0x0 |
| 4643 | OPC_Scope, 8, // 8817: try { |
| 4644 | OPC_CheckField, 48, 4, 0, // 8819: check Inst[51:48] == 0x0 |
| 4645 | OPC_Decode, 159, 26, 121, // 8823: decode to PVMINSUPvv using decoder 121 |
| 4646 | // 8823: } else try { |
| 4647 | OPC_Decode, 165, 26, 122, // 8827: decode to PVMINSUPvvm using decoder 122 |
| 4648 | // 8827: } |
| 4649 | // 8827: } |
| 4650 | 2, 60, // 8831: case 0x2: { |
| 4651 | OPC_SwitchField, 47, 1, // 8833: switch Inst[47] { |
| 4652 | 0, 26, // 8836: case 0x0: { |
| 4653 | OPC_CheckField, 0, 8, 0, // 8838: check Inst[7:0] == 0x0 |
| 4654 | OPC_CheckField, 16, 8, 0, // 8842: check Inst[23:16] == 0x0 |
| 4655 | OPC_CheckField, 32, 8, 0, // 8846: check Inst[39:32] == 0x0 |
| 4656 | OPC_Scope, 8, // 8850: try { |
| 4657 | OPC_CheckField, 48, 4, 0, // 8852: check Inst[51:48] == 0x0 |
| 4658 | OPC_Decode, 155, 25, 123, // 8856: decode to PVMAXSUPiv using decoder 123 |
| 4659 | // 8856: } else try { |
| 4660 | OPC_Decode, 161, 25, 124, // 8860: decode to PVMAXSUPivm using decoder 124 |
| 4661 | // 8860: } |
| 4662 | // 8860: } |
| 4663 | 1, 0, // 8864: case 0x1: { |
| 4664 | OPC_CheckField, 0, 8, 0, // 8866: check Inst[7:0] == 0x0 |
| 4665 | OPC_CheckField, 16, 8, 0, // 8870: check Inst[23:16] == 0x0 |
| 4666 | OPC_CheckField, 32, 8, 0, // 8874: check Inst[39:32] == 0x0 |
| 4667 | OPC_Scope, 8, // 8878: try { |
| 4668 | OPC_CheckField, 48, 4, 0, // 8880: check Inst[51:48] == 0x0 |
| 4669 | OPC_Decode, 167, 25, 127, // 8884: decode to PVMAXSUPrv using decoder 127 |
| 4670 | // 8884: } else try { |
| 4671 | OPC_Decode, 173, 25, 128, 1, // 8888: decode to PVMAXSUPrvm using decoder 128 |
| 4672 | // 8888: } |
| 4673 | // 8888: } |
| 4674 | // 8888: } // switch Inst[47] |
| 4675 | // 8888: } |
| 4676 | 3, 60, // 8893: case 0x3: { |
| 4677 | OPC_SwitchField, 47, 1, // 8895: switch Inst[47] { |
| 4678 | 0, 26, // 8898: case 0x0: { |
| 4679 | OPC_CheckField, 0, 8, 0, // 8900: check Inst[7:0] == 0x0 |
| 4680 | OPC_CheckField, 16, 8, 0, // 8904: check Inst[23:16] == 0x0 |
| 4681 | OPC_CheckField, 32, 8, 0, // 8908: check Inst[39:32] == 0x0 |
| 4682 | OPC_Scope, 8, // 8912: try { |
| 4683 | OPC_CheckField, 48, 4, 0, // 8914: check Inst[51:48] == 0x0 |
| 4684 | OPC_Decode, 135, 26, 123, // 8918: decode to PVMINSUPiv using decoder 123 |
| 4685 | // 8918: } else try { |
| 4686 | OPC_Decode, 141, 26, 124, // 8922: decode to PVMINSUPivm using decoder 124 |
| 4687 | // 8922: } |
| 4688 | // 8922: } |
| 4689 | 1, 0, // 8926: case 0x1: { |
| 4690 | OPC_CheckField, 0, 8, 0, // 8928: check Inst[7:0] == 0x0 |
| 4691 | OPC_CheckField, 16, 8, 0, // 8932: check Inst[23:16] == 0x0 |
| 4692 | OPC_CheckField, 32, 8, 0, // 8936: check Inst[39:32] == 0x0 |
| 4693 | OPC_Scope, 8, // 8940: try { |
| 4694 | OPC_CheckField, 48, 4, 0, // 8942: check Inst[51:48] == 0x0 |
| 4695 | OPC_Decode, 147, 26, 127, // 8946: decode to PVMINSUPrv using decoder 127 |
| 4696 | // 8946: } else try { |
| 4697 | OPC_Decode, 153, 26, 128, 1, // 8950: decode to PVMINSUPrvm using decoder 128 |
| 4698 | // 8950: } |
| 4699 | // 8950: } |
| 4700 | // 8950: } // switch Inst[47] |
| 4701 | // 8950: } |
| 4702 | 4, 23, // 8955: case 0x4: { |
| 4703 | OPC_CheckField, 0, 8, 0, // 8957: check Inst[7:0] == 0x0 |
| 4704 | OPC_CheckField, 32, 16, 0, // 8961: check Inst[47:32] == 0x0 |
| 4705 | OPC_Scope, 8, // 8965: try { |
| 4706 | OPC_CheckField, 48, 4, 0, // 8967: check Inst[51:48] == 0x0 |
| 4707 | OPC_Decode, 215, 25, 121, // 8971: decode to PVMAXSvv using decoder 121 |
| 4708 | // 8971: } else try { |
| 4709 | OPC_Decode, 221, 25, 129, 1, // 8975: decode to PVMAXSvvm using decoder 129 |
| 4710 | // 8975: } |
| 4711 | // 8975: } |
| 4712 | 5, 23, // 8980: case 0x5: { |
| 4713 | OPC_CheckField, 0, 8, 0, // 8982: check Inst[7:0] == 0x0 |
| 4714 | OPC_CheckField, 32, 16, 0, // 8986: check Inst[47:32] == 0x0 |
| 4715 | OPC_Scope, 8, // 8990: try { |
| 4716 | OPC_CheckField, 48, 4, 0, // 8992: check Inst[51:48] == 0x0 |
| 4717 | OPC_Decode, 195, 26, 121, // 8996: decode to PVMINSvv using decoder 121 |
| 4718 | // 8996: } else try { |
| 4719 | OPC_Decode, 201, 26, 129, 1, // 9000: decode to PVMINSvvm using decoder 129 |
| 4720 | // 9000: } |
| 4721 | // 9000: } |
| 4722 | 6, 61, // 9005: case 0x6: { |
| 4723 | OPC_SwitchField, 47, 1, // 9007: switch Inst[47] { |
| 4724 | 0, 27, // 9010: case 0x0: { |
| 4725 | OPC_CheckField, 0, 8, 0, // 9012: check Inst[7:0] == 0x0 |
| 4726 | OPC_CheckField, 16, 8, 0, // 9016: check Inst[23:16] == 0x0 |
| 4727 | OPC_CheckField, 32, 8, 0, // 9020: check Inst[39:32] == 0x0 |
| 4728 | OPC_Scope, 8, // 9024: try { |
| 4729 | OPC_CheckField, 48, 4, 0, // 9026: check Inst[51:48] == 0x0 |
| 4730 | OPC_Decode, 191, 25, 123, // 9030: decode to PVMAXSiv using decoder 123 |
| 4731 | // 9030: } else try { |
| 4732 | OPC_Decode, 197, 25, 130, 1, // 9034: decode to PVMAXSivm using decoder 130 |
| 4733 | // 9034: } |
| 4734 | // 9034: } |
| 4735 | 1, 0, // 9039: case 0x1: { |
| 4736 | OPC_CheckField, 0, 8, 0, // 9041: check Inst[7:0] == 0x0 |
| 4737 | OPC_CheckField, 16, 8, 0, // 9045: check Inst[23:16] == 0x0 |
| 4738 | OPC_CheckField, 32, 8, 0, // 9049: check Inst[39:32] == 0x0 |
| 4739 | OPC_Scope, 8, // 9053: try { |
| 4740 | OPC_CheckField, 48, 4, 0, // 9055: check Inst[51:48] == 0x0 |
| 4741 | OPC_Decode, 203, 25, 127, // 9059: decode to PVMAXSrv using decoder 127 |
| 4742 | // 9059: } else try { |
| 4743 | OPC_Decode, 209, 25, 131, 1, // 9063: decode to PVMAXSrvm using decoder 131 |
| 4744 | // 9063: } |
| 4745 | // 9063: } |
| 4746 | // 9063: } // switch Inst[47] |
| 4747 | // 9063: } |
| 4748 | 7, 0, // 9068: case 0x7: { |
| 4749 | OPC_SwitchField, 47, 1, // 9070: switch Inst[47] { |
| 4750 | 0, 27, // 9073: case 0x0: { |
| 4751 | OPC_CheckField, 0, 8, 0, // 9075: check Inst[7:0] == 0x0 |
| 4752 | OPC_CheckField, 16, 8, 0, // 9079: check Inst[23:16] == 0x0 |
| 4753 | OPC_CheckField, 32, 8, 0, // 9083: check Inst[39:32] == 0x0 |
| 4754 | OPC_Scope, 8, // 9087: try { |
| 4755 | OPC_CheckField, 48, 4, 0, // 9089: check Inst[51:48] == 0x0 |
| 4756 | OPC_Decode, 171, 26, 123, // 9093: decode to PVMINSiv using decoder 123 |
| 4757 | // 9093: } else try { |
| 4758 | OPC_Decode, 177, 26, 130, 1, // 9097: decode to PVMINSivm using decoder 130 |
| 4759 | // 9097: } |
| 4760 | // 9097: } |
| 4761 | 1, 0, // 9102: case 0x1: { |
| 4762 | OPC_CheckField, 0, 8, 0, // 9104: check Inst[7:0] == 0x0 |
| 4763 | OPC_CheckField, 16, 8, 0, // 9108: check Inst[23:16] == 0x0 |
| 4764 | OPC_CheckField, 32, 8, 0, // 9112: check Inst[39:32] == 0x0 |
| 4765 | OPC_Scope, 8, // 9116: try { |
| 4766 | OPC_CheckField, 48, 4, 0, // 9118: check Inst[51:48] == 0x0 |
| 4767 | OPC_Decode, 183, 26, 127, // 9122: decode to PVMINSrv using decoder 127 |
| 4768 | // 9122: } else try { |
| 4769 | OPC_Decode, 189, 26, 131, 1, // 9126: decode to PVMINSrvm using decoder 131 |
| 4770 | // 9126: } |
| 4771 | // 9126: } |
| 4772 | // 9126: } // switch Inst[47] |
| 4773 | // 9126: } |
| 4774 | // 9126: } // switch Inst[54:52] |
| 4775 | // 9126: } |
| 4776 | 150, 2, 93, // 9131: case 0x116: { |
| 4777 | OPC_SwitchField, 47, 1, // 9134: switch Inst[47] { |
| 4778 | 0, 55, // 9137: case 0x0: { |
| 4779 | OPC_SwitchField, 52, 3, // 9139: switch Inst[54:52] { |
| 4780 | 0, 22, // 9142: case 0x0: { |
| 4781 | OPC_CheckField, 0, 8, 0, // 9144: check Inst[7:0] == 0x0 |
| 4782 | OPC_CheckField, 32, 15, 0, // 9148: check Inst[46:32] == 0x0 |
| 4783 | OPC_Scope, 8, // 9152: try { |
| 4784 | OPC_CheckField, 48, 4, 0, // 9154: check Inst[51:48] == 0x0 |
| 4785 | OPC_Decode, 248, 35, 121, // 9158: decode to VADDSLvv using decoder 121 |
| 4786 | // 9158: } else try { |
| 4787 | OPC_Decode, 254, 35, 122, // 9162: decode to VADDSLvvm using decoder 122 |
| 4788 | // 9162: } |
| 4789 | // 9162: } |
| 4790 | 2, 0, // 9166: case 0x2: { |
| 4791 | OPC_CheckField, 0, 8, 0, // 9168: check Inst[7:0] == 0x0 |
| 4792 | OPC_CheckField, 16, 8, 0, // 9172: check Inst[23:16] == 0x0 |
| 4793 | OPC_CheckField, 32, 8, 0, // 9176: check Inst[39:32] == 0x0 |
| 4794 | OPC_Scope, 8, // 9180: try { |
| 4795 | OPC_CheckField, 48, 4, 0, // 9182: check Inst[51:48] == 0x0 |
| 4796 | OPC_Decode, 224, 35, 123, // 9186: decode to VADDSLiv using decoder 123 |
| 4797 | // 9186: } else try { |
| 4798 | OPC_Decode, 230, 35, 124, // 9190: decode to VADDSLivm using decoder 124 |
| 4799 | // 9190: } |
| 4800 | // 9190: } |
| 4801 | // 9190: } // switch Inst[54:52] |
| 4802 | // 9190: } |
| 4803 | 1, 0, // 9194: case 0x1: { |
| 4804 | OPC_CheckField, 0, 8, 0, // 9196: check Inst[7:0] == 0x0 |
| 4805 | OPC_CheckField, 16, 8, 0, // 9200: check Inst[23:16] == 0x0 |
| 4806 | OPC_CheckField, 32, 8, 0, // 9204: check Inst[39:32] == 0x0 |
| 4807 | OPC_CheckField, 52, 3, 2, // 9208: check Inst[54:52] == 0x2 |
| 4808 | OPC_Scope, 8, // 9212: try { |
| 4809 | OPC_CheckField, 48, 4, 0, // 9214: check Inst[51:48] == 0x0 |
| 4810 | OPC_Decode, 236, 35, 127, // 9218: decode to VADDSLrv using decoder 127 |
| 4811 | // 9218: } else try { |
| 4812 | OPC_Decode, 242, 35, 128, 1, // 9222: decode to VADDSLrvm using decoder 128 |
| 4813 | // 9222: } |
| 4814 | // 9222: } |
| 4815 | // 9222: } // switch Inst[47] |
| 4816 | // 9222: } |
| 4817 | 152, 2, 117, // 9227: case 0x118: { |
| 4818 | OPC_SwitchField, 47, 1, // 9230: switch Inst[47] { |
| 4819 | 0, 55, // 9233: case 0x0: { |
| 4820 | OPC_SwitchField, 52, 3, // 9235: switch Inst[54:52] { |
| 4821 | 0, 24, // 9238: case 0x0: { |
| 4822 | OPC_CheckField, 0, 24, 0, // 9240: check Inst[23:0] == 0x0 |
| 4823 | OPC_CheckField, 32, 8, 0, // 9244: check Inst[39:32] == 0x0 |
| 4824 | OPC_Scope, 9, // 9248: try { |
| 4825 | OPC_CheckField, 48, 4, 0, // 9250: check Inst[51:48] == 0x0 |
| 4826 | OPC_Decode, 232, 37, 132, 1, // 9254: decode to VBRDi using decoder 132 |
| 4827 | // 9254: } else try { |
| 4828 | OPC_Decode, 238, 37, 133, 1, // 9259: decode to VBRDim using decoder 133 |
| 4829 | // 9259: } |
| 4830 | // 9259: } |
| 4831 | 4, 0, // 9264: case 0x4: { |
| 4832 | OPC_CheckField, 0, 24, 0, // 9266: check Inst[23:0] == 0x0 |
| 4833 | OPC_CheckField, 32, 8, 0, // 9270: check Inst[39:32] == 0x0 |
| 4834 | OPC_Scope, 9, // 9274: try { |
| 4835 | OPC_CheckField, 48, 4, 0, // 9276: check Inst[51:48] == 0x0 |
| 4836 | OPC_Decode, 184, 37, 132, 1, // 9280: decode to VBRDLi using decoder 132 |
| 4837 | // 9280: } else try { |
| 4838 | OPC_Decode, 190, 37, 133, 1, // 9285: decode to VBRDLim using decoder 133 |
| 4839 | // 9285: } |
| 4840 | // 9285: } |
| 4841 | // 9285: } // switch Inst[54:52] |
| 4842 | // 9285: } |
| 4843 | 1, 0, // 9290: case 0x1: { |
| 4844 | OPC_SwitchField, 52, 3, // 9292: switch Inst[54:52] { |
| 4845 | 0, 24, // 9295: case 0x0: { |
| 4846 | OPC_CheckField, 0, 24, 0, // 9297: check Inst[23:0] == 0x0 |
| 4847 | OPC_CheckField, 32, 8, 0, // 9301: check Inst[39:32] == 0x0 |
| 4848 | OPC_Scope, 9, // 9305: try { |
| 4849 | OPC_CheckField, 48, 4, 0, // 9307: check Inst[51:48] == 0x0 |
| 4850 | OPC_Decode, 244, 37, 134, 1, // 9311: decode to VBRDr using decoder 134 |
| 4851 | // 9311: } else try { |
| 4852 | OPC_Decode, 250, 37, 135, 1, // 9316: decode to VBRDrm using decoder 135 |
| 4853 | // 9316: } |
| 4854 | // 9316: } |
| 4855 | 4, 0, // 9321: case 0x4: { |
| 4856 | OPC_CheckField, 0, 24, 0, // 9323: check Inst[23:0] == 0x0 |
| 4857 | OPC_CheckField, 32, 8, 0, // 9327: check Inst[39:32] == 0x0 |
| 4858 | OPC_Scope, 9, // 9331: try { |
| 4859 | OPC_CheckField, 48, 4, 0, // 9333: check Inst[51:48] == 0x0 |
| 4860 | OPC_Decode, 196, 37, 136, 1, // 9337: decode to VBRDLr using decoder 136 |
| 4861 | // 9337: } else try { |
| 4862 | OPC_Decode, 202, 37, 137, 1, // 9342: decode to VBRDLrm using decoder 137 |
| 4863 | // 9342: } |
| 4864 | // 9342: } |
| 4865 | // 9342: } // switch Inst[54:52] |
| 4866 | // 9342: } |
| 4867 | // 9342: } // switch Inst[47] |
| 4868 | // 9342: } |
| 4869 | 153, 2, 117, // 9347: case 0x119: { |
| 4870 | OPC_SwitchField, 47, 1, // 9350: switch Inst[47] { |
| 4871 | 0, 55, // 9353: case 0x0: { |
| 4872 | OPC_SwitchField, 52, 3, // 9355: switch Inst[54:52] { |
| 4873 | 0, 24, // 9358: case 0x0: { |
| 4874 | OPC_CheckField, 0, 24, 0, // 9360: check Inst[23:0] == 0x0 |
| 4875 | OPC_CheckField, 32, 8, 0, // 9364: check Inst[39:32] == 0x0 |
| 4876 | OPC_Scope, 9, // 9368: try { |
| 4877 | OPC_CheckField, 48, 4, 0, // 9370: check Inst[51:48] == 0x0 |
| 4878 | OPC_Decode, 208, 37, 132, 1, // 9374: decode to VBRDUi using decoder 132 |
| 4879 | // 9374: } else try { |
| 4880 | OPC_Decode, 214, 37, 133, 1, // 9379: decode to VBRDUim using decoder 133 |
| 4881 | // 9379: } |
| 4882 | // 9379: } |
| 4883 | 4, 0, // 9384: case 0x4: { |
| 4884 | OPC_CheckField, 0, 24, 0, // 9386: check Inst[23:0] == 0x0 |
| 4885 | OPC_CheckField, 32, 8, 0, // 9390: check Inst[39:32] == 0x0 |
| 4886 | OPC_Scope, 9, // 9394: try { |
| 4887 | OPC_CheckField, 48, 4, 0, // 9396: check Inst[51:48] == 0x0 |
| 4888 | OPC_Decode, 235, 9, 132, 1, // 9400: decode to PVBRDi using decoder 132 |
| 4889 | // 9400: } else try { |
| 4890 | OPC_Decode, 241, 9, 138, 1, // 9405: decode to PVBRDim using decoder 138 |
| 4891 | // 9405: } |
| 4892 | // 9405: } |
| 4893 | // 9405: } // switch Inst[54:52] |
| 4894 | // 9405: } |
| 4895 | 1, 0, // 9410: case 0x1: { |
| 4896 | OPC_SwitchField, 52, 3, // 9412: switch Inst[54:52] { |
| 4897 | 0, 24, // 9415: case 0x0: { |
| 4898 | OPC_CheckField, 0, 24, 0, // 9417: check Inst[23:0] == 0x0 |
| 4899 | OPC_CheckField, 32, 8, 0, // 9421: check Inst[39:32] == 0x0 |
| 4900 | OPC_Scope, 9, // 9425: try { |
| 4901 | OPC_CheckField, 48, 4, 0, // 9427: check Inst[51:48] == 0x0 |
| 4902 | OPC_Decode, 220, 37, 139, 1, // 9431: decode to VBRDUr using decoder 139 |
| 4903 | // 9431: } else try { |
| 4904 | OPC_Decode, 226, 37, 140, 1, // 9436: decode to VBRDUrm using decoder 140 |
| 4905 | // 9436: } |
| 4906 | // 9436: } |
| 4907 | 4, 0, // 9441: case 0x4: { |
| 4908 | OPC_CheckField, 0, 24, 0, // 9443: check Inst[23:0] == 0x0 |
| 4909 | OPC_CheckField, 32, 8, 0, // 9447: check Inst[39:32] == 0x0 |
| 4910 | OPC_Scope, 9, // 9451: try { |
| 4911 | OPC_CheckField, 48, 4, 0, // 9453: check Inst[51:48] == 0x0 |
| 4912 | OPC_Decode, 247, 9, 134, 1, // 9457: decode to PVBRDr using decoder 134 |
| 4913 | // 9457: } else try { |
| 4914 | OPC_Decode, 253, 9, 141, 1, // 9462: decode to PVBRDrm using decoder 141 |
| 4915 | // 9462: } |
| 4916 | // 9462: } |
| 4917 | // 9462: } // switch Inst[54:52] |
| 4918 | // 9462: } |
| 4919 | // 9462: } // switch Inst[47] |
| 4920 | // 9462: } |
| 4921 | 154, 2, 32, // 9467: case 0x11a: { |
| 4922 | OPC_CheckField, 0, 8, 0, // 9470: check Inst[7:0] == 0x0 |
| 4923 | OPC_CheckField, 16, 8, 0, // 9474: check Inst[23:16] == 0x0 |
| 4924 | OPC_CheckField, 32, 16, 0, // 9478: check Inst[47:32] == 0x0 |
| 4925 | OPC_CheckField, 52, 3, 0, // 9482: check Inst[54:52] == 0x0 |
| 4926 | OPC_Scope, 9, // 9486: try { |
| 4927 | OPC_CheckField, 48, 4, 0, // 9488: check Inst[51:48] == 0x0 |
| 4928 | OPC_Decode, 192, 39, 142, 1, // 9492: decode to VCPv using decoder 142 |
| 4929 | // 9492: } else try { |
| 4930 | OPC_Decode, 198, 39, 143, 1, // 9497: decode to VCPvm using decoder 143 |
| 4931 | // 9497: } |
| 4932 | // 9497: } |
| 4933 | 156, 2, 55, // 9502: case 0x11c: { |
| 4934 | OPC_SwitchField, 39, 1, // 9505: switch Inst[39] { |
| 4935 | 0, 24, // 9508: case 0x0: { |
| 4936 | OPC_SwitchField, 47, 8, // 9510: switch Inst[54:47] { |
| 4937 | 0, 9, // 9513: case 0x0: { |
| 4938 | OPC_CheckField, 0, 24, 0, // 9515: check Inst[23:0] == 0x0 |
| 4939 | OPC_Decode, 171, 6, 144, 1, // 9519: decode to LSVim using decoder 144 |
| 4940 | // 9519: } |
| 4941 | 1, 0, // 9524: case 0x1: { |
| 4942 | OPC_CheckField, 0, 24, 0, // 9526: check Inst[23:0] == 0x0 |
| 4943 | OPC_Decode, 175, 6, 116, // 9530: decode to LSVrm using decoder 116 |
| 4944 | // 9530: } |
| 4945 | // 9530: } // switch Inst[54:47] |
| 4946 | // 9530: } |
| 4947 | 1, 0, // 9534: case 0x1: { |
| 4948 | OPC_SwitchField, 47, 8, // 9536: switch Inst[54:47] { |
| 4949 | 0, 9, // 9539: case 0x0: { |
| 4950 | OPC_CheckField, 0, 24, 0, // 9541: check Inst[23:0] == 0x0 |
| 4951 | OPC_Decode, 173, 6, 145, 1, // 9545: decode to LSVir using decoder 145 |
| 4952 | // 9545: } |
| 4953 | 1, 0, // 9550: case 0x1: { |
| 4954 | OPC_CheckField, 0, 24, 0, // 9552: check Inst[23:0] == 0x0 |
| 4955 | OPC_Decode, 177, 6, 117, // 9556: decode to LSVrr using decoder 117 |
| 4956 | // 9556: } |
| 4957 | // 9556: } // switch Inst[54:47] |
| 4958 | // 9556: } |
| 4959 | // 9556: } // switch Inst[39] |
| 4960 | // 9556: } |
| 4961 | 158, 2, 26, // 9560: case 0x11e: { |
| 4962 | OPC_CheckField, 0, 16, 0, // 9563: check Inst[15:0] == 0x0 |
| 4963 | OPC_CheckField, 32, 16, 0, // 9567: check Inst[47:32] == 0x0 |
| 4964 | OPC_CheckField, 52, 3, 0, // 9571: check Inst[54:52] == 0x0 |
| 4965 | OPC_Scope, 8, // 9575: try { |
| 4966 | OPC_CheckField, 48, 4, 0, // 9577: check Inst[51:48] == 0x0 |
| 4967 | OPC_Decode, 216, 39, 119, // 9581: decode to VCVTDSv using decoder 119 |
| 4968 | // 9581: } else try { |
| 4969 | OPC_Decode, 222, 39, 120, // 9585: decode to VCVTDSvm using decoder 120 |
| 4970 | // 9585: } |
| 4971 | // 9585: } |
| 4972 | 162, 2, 209, 1, // 9589: case 0x122: { |
| 4973 | OPC_SwitchField, 39, 1, // 9593: switch Inst[39] { |
| 4974 | 0, 101, // 9596: case 0x0: { |
| 4975 | OPC_SwitchField, 47, 1, // 9598: switch Inst[47] { |
| 4976 | 0, 47, // 9601: case 0x0: { |
| 4977 | OPC_SwitchField, 52, 3, // 9603: switch Inst[54:52] { |
| 4978 | 0, 20, // 9606: case 0x0: { |
| 4979 | OPC_CheckField, 0, 24, 0, // 9608: check Inst[23:0] == 0x0 |
| 4980 | OPC_Scope, 9, // 9612: try { |
| 4981 | OPC_CheckField, 48, 4, 0, // 9614: check Inst[51:48] == 0x0 |
| 4982 | OPC_Decode, 134, 80, 146, 1, // 9618: decode to VSTNCizv using decoder 146 |
| 4983 | // 9618: } else try { |
| 4984 | OPC_Decode, 137, 80, 147, 1, // 9623: decode to VSTNCizvm using decoder 147 |
| 4985 | // 9623: } |
| 4986 | // 9623: } |
| 4987 | 4, 0, // 9628: case 0x4: { |
| 4988 | OPC_CheckField, 0, 24, 0, // 9630: check Inst[23:0] == 0x0 |
| 4989 | OPC_Scope, 9, // 9634: try { |
| 4990 | OPC_CheckField, 48, 4, 0, // 9636: check Inst[51:48] == 0x0 |
| 4991 | OPC_Decode, 246, 81, 146, 1, // 9640: decode to VSTizv using decoder 146 |
| 4992 | // 9640: } else try { |
| 4993 | OPC_Decode, 249, 81, 147, 1, // 9645: decode to VSTizvm using decoder 147 |
| 4994 | // 9645: } |
| 4995 | // 9645: } |
| 4996 | // 9645: } // switch Inst[54:52] |
| 4997 | // 9645: } |
| 4998 | 1, 0, // 9650: case 0x1: { |
| 4999 | OPC_SwitchField, 52, 3, // 9652: switch Inst[54:52] { |
| 5000 | 0, 20, // 9655: case 0x0: { |
| 5001 | OPC_CheckField, 0, 24, 0, // 9657: check Inst[23:0] == 0x0 |
| 5002 | OPC_Scope, 9, // 9661: try { |
| 5003 | OPC_CheckField, 48, 4, 0, // 9663: check Inst[51:48] == 0x0 |
| 5004 | OPC_Decode, 146, 80, 148, 1, // 9667: decode to VSTNCrzv using decoder 148 |
| 5005 | // 9667: } else try { |
| 5006 | OPC_Decode, 149, 80, 149, 1, // 9672: decode to VSTNCrzvm using decoder 149 |
| 5007 | // 9672: } |
| 5008 | // 9672: } |
| 5009 | 4, 0, // 9677: case 0x4: { |
| 5010 | OPC_CheckField, 0, 24, 0, // 9679: check Inst[23:0] == 0x0 |
| 5011 | OPC_Scope, 9, // 9683: try { |
| 5012 | OPC_CheckField, 48, 4, 0, // 9685: check Inst[51:48] == 0x0 |
| 5013 | OPC_Decode, 130, 82, 148, 1, // 9689: decode to VSTrzv using decoder 148 |
| 5014 | // 9689: } else try { |
| 5015 | OPC_Decode, 133, 82, 149, 1, // 9694: decode to VSTrzvm using decoder 149 |
| 5016 | // 9694: } |
| 5017 | // 9694: } |
| 5018 | // 9694: } // switch Inst[54:52] |
| 5019 | // 9694: } |
| 5020 | // 9694: } // switch Inst[47] |
| 5021 | // 9694: } |
| 5022 | 1, 0, // 9699: case 0x1: { |
| 5023 | OPC_SwitchField, 47, 1, // 9701: switch Inst[47] { |
| 5024 | 0, 47, // 9704: case 0x0: { |
| 5025 | OPC_SwitchField, 52, 3, // 9706: switch Inst[54:52] { |
| 5026 | 0, 20, // 9709: case 0x0: { |
| 5027 | OPC_CheckField, 0, 24, 0, // 9711: check Inst[23:0] == 0x0 |
| 5028 | OPC_Scope, 9, // 9715: try { |
| 5029 | OPC_CheckField, 48, 4, 0, // 9717: check Inst[51:48] == 0x0 |
| 5030 | OPC_Decode, 128, 80, 150, 1, // 9721: decode to VSTNCirv using decoder 150 |
| 5031 | // 9721: } else try { |
| 5032 | OPC_Decode, 131, 80, 151, 1, // 9726: decode to VSTNCirvm using decoder 151 |
| 5033 | // 9726: } |
| 5034 | // 9726: } |
| 5035 | 4, 0, // 9731: case 0x4: { |
| 5036 | OPC_CheckField, 0, 24, 0, // 9733: check Inst[23:0] == 0x0 |
| 5037 | OPC_Scope, 9, // 9737: try { |
| 5038 | OPC_CheckField, 48, 4, 0, // 9739: check Inst[51:48] == 0x0 |
| 5039 | OPC_Decode, 240, 81, 150, 1, // 9743: decode to VSTirv using decoder 150 |
| 5040 | // 9743: } else try { |
| 5041 | OPC_Decode, 243, 81, 151, 1, // 9748: decode to VSTirvm using decoder 151 |
| 5042 | // 9748: } |
| 5043 | // 9748: } |
| 5044 | // 9748: } // switch Inst[54:52] |
| 5045 | // 9748: } |
| 5046 | 1, 0, // 9753: case 0x1: { |
| 5047 | OPC_SwitchField, 52, 3, // 9755: switch Inst[54:52] { |
| 5048 | 0, 20, // 9758: case 0x0: { |
| 5049 | OPC_CheckField, 0, 24, 0, // 9760: check Inst[23:0] == 0x0 |
| 5050 | OPC_Scope, 9, // 9764: try { |
| 5051 | OPC_CheckField, 48, 4, 0, // 9766: check Inst[51:48] == 0x0 |
| 5052 | OPC_Decode, 140, 80, 152, 1, // 9770: decode to VSTNCrrv using decoder 152 |
| 5053 | // 9770: } else try { |
| 5054 | OPC_Decode, 143, 80, 153, 1, // 9775: decode to VSTNCrrvm using decoder 153 |
| 5055 | // 9775: } |
| 5056 | // 9775: } |
| 5057 | 4, 0, // 9780: case 0x4: { |
| 5058 | OPC_CheckField, 0, 24, 0, // 9782: check Inst[23:0] == 0x0 |
| 5059 | OPC_Scope, 9, // 9786: try { |
| 5060 | OPC_CheckField, 48, 4, 0, // 9788: check Inst[51:48] == 0x0 |
| 5061 | OPC_Decode, 252, 81, 152, 1, // 9792: decode to VSTrrv using decoder 152 |
| 5062 | // 9792: } else try { |
| 5063 | OPC_Decode, 255, 81, 153, 1, // 9797: decode to VSTrrvm using decoder 153 |
| 5064 | // 9797: } |
| 5065 | // 9797: } |
| 5066 | // 9797: } // switch Inst[54:52] |
| 5067 | // 9797: } |
| 5068 | // 9797: } // switch Inst[47] |
| 5069 | // 9797: } |
| 5070 | // 9797: } // switch Inst[39] |
| 5071 | // 9797: } |
| 5072 | 163, 2, 209, 1, // 9802: case 0x123: { |
| 5073 | OPC_SwitchField, 39, 1, // 9806: switch Inst[39] { |
| 5074 | 0, 101, // 9809: case 0x0: { |
| 5075 | OPC_SwitchField, 47, 1, // 9811: switch Inst[47] { |
| 5076 | 0, 47, // 9814: case 0x0: { |
| 5077 | OPC_SwitchField, 52, 3, // 9816: switch Inst[54:52] { |
| 5078 | 0, 20, // 9819: case 0x0: { |
| 5079 | OPC_CheckField, 0, 24, 0, // 9821: check Inst[23:0] == 0x0 |
| 5080 | OPC_Scope, 9, // 9825: try { |
| 5081 | OPC_CheckField, 48, 4, 0, // 9827: check Inst[51:48] == 0x0 |
| 5082 | OPC_Decode, 238, 79, 146, 1, // 9831: decode to VSTNCOTizv using decoder 146 |
| 5083 | // 9831: } else try { |
| 5084 | OPC_Decode, 241, 79, 147, 1, // 9836: decode to VSTNCOTizvm using decoder 147 |
| 5085 | // 9836: } |
| 5086 | // 9836: } |
| 5087 | 4, 0, // 9841: case 0x4: { |
| 5088 | OPC_CheckField, 0, 24, 0, // 9843: check Inst[23:0] == 0x0 |
| 5089 | OPC_Scope, 9, // 9847: try { |
| 5090 | OPC_CheckField, 48, 4, 0, // 9849: check Inst[51:48] == 0x0 |
| 5091 | OPC_Decode, 158, 80, 146, 1, // 9853: decode to VSTOTizv using decoder 146 |
| 5092 | // 9853: } else try { |
| 5093 | OPC_Decode, 161, 80, 147, 1, // 9858: decode to VSTOTizvm using decoder 147 |
| 5094 | // 9858: } |
| 5095 | // 9858: } |
| 5096 | // 9858: } // switch Inst[54:52] |
| 5097 | // 9858: } |
| 5098 | 1, 0, // 9863: case 0x1: { |
| 5099 | OPC_SwitchField, 52, 3, // 9865: switch Inst[54:52] { |
| 5100 | 0, 20, // 9868: case 0x0: { |
| 5101 | OPC_CheckField, 0, 24, 0, // 9870: check Inst[23:0] == 0x0 |
| 5102 | OPC_Scope, 9, // 9874: try { |
| 5103 | OPC_CheckField, 48, 4, 0, // 9876: check Inst[51:48] == 0x0 |
| 5104 | OPC_Decode, 250, 79, 148, 1, // 9880: decode to VSTNCOTrzv using decoder 148 |
| 5105 | // 9880: } else try { |
| 5106 | OPC_Decode, 253, 79, 149, 1, // 9885: decode to VSTNCOTrzvm using decoder 149 |
| 5107 | // 9885: } |
| 5108 | // 9885: } |
| 5109 | 4, 0, // 9890: case 0x4: { |
| 5110 | OPC_CheckField, 0, 24, 0, // 9892: check Inst[23:0] == 0x0 |
| 5111 | OPC_Scope, 9, // 9896: try { |
| 5112 | OPC_CheckField, 48, 4, 0, // 9898: check Inst[51:48] == 0x0 |
| 5113 | OPC_Decode, 170, 80, 148, 1, // 9902: decode to VSTOTrzv using decoder 148 |
| 5114 | // 9902: } else try { |
| 5115 | OPC_Decode, 173, 80, 149, 1, // 9907: decode to VSTOTrzvm using decoder 149 |
| 5116 | // 9907: } |
| 5117 | // 9907: } |
| 5118 | // 9907: } // switch Inst[54:52] |
| 5119 | // 9907: } |
| 5120 | // 9907: } // switch Inst[47] |
| 5121 | // 9907: } |
| 5122 | 1, 0, // 9912: case 0x1: { |
| 5123 | OPC_SwitchField, 47, 1, // 9914: switch Inst[47] { |
| 5124 | 0, 47, // 9917: case 0x0: { |
| 5125 | OPC_SwitchField, 52, 3, // 9919: switch Inst[54:52] { |
| 5126 | 0, 20, // 9922: case 0x0: { |
| 5127 | OPC_CheckField, 0, 24, 0, // 9924: check Inst[23:0] == 0x0 |
| 5128 | OPC_Scope, 9, // 9928: try { |
| 5129 | OPC_CheckField, 48, 4, 0, // 9930: check Inst[51:48] == 0x0 |
| 5130 | OPC_Decode, 232, 79, 150, 1, // 9934: decode to VSTNCOTirv using decoder 150 |
| 5131 | // 9934: } else try { |
| 5132 | OPC_Decode, 235, 79, 151, 1, // 9939: decode to VSTNCOTirvm using decoder 151 |
| 5133 | // 9939: } |
| 5134 | // 9939: } |
| 5135 | 4, 0, // 9944: case 0x4: { |
| 5136 | OPC_CheckField, 0, 24, 0, // 9946: check Inst[23:0] == 0x0 |
| 5137 | OPC_Scope, 9, // 9950: try { |
| 5138 | OPC_CheckField, 48, 4, 0, // 9952: check Inst[51:48] == 0x0 |
| 5139 | OPC_Decode, 152, 80, 150, 1, // 9956: decode to VSTOTirv using decoder 150 |
| 5140 | // 9956: } else try { |
| 5141 | OPC_Decode, 155, 80, 151, 1, // 9961: decode to VSTOTirvm using decoder 151 |
| 5142 | // 9961: } |
| 5143 | // 9961: } |
| 5144 | // 9961: } // switch Inst[54:52] |
| 5145 | // 9961: } |
| 5146 | 1, 0, // 9966: case 0x1: { |
| 5147 | OPC_SwitchField, 52, 3, // 9968: switch Inst[54:52] { |
| 5148 | 0, 20, // 9971: case 0x0: { |
| 5149 | OPC_CheckField, 0, 24, 0, // 9973: check Inst[23:0] == 0x0 |
| 5150 | OPC_Scope, 9, // 9977: try { |
| 5151 | OPC_CheckField, 48, 4, 0, // 9979: check Inst[51:48] == 0x0 |
| 5152 | OPC_Decode, 244, 79, 152, 1, // 9983: decode to VSTNCOTrrv using decoder 152 |
| 5153 | // 9983: } else try { |
| 5154 | OPC_Decode, 247, 79, 153, 1, // 9988: decode to VSTNCOTrrvm using decoder 153 |
| 5155 | // 9988: } |
| 5156 | // 9988: } |
| 5157 | 4, 0, // 9993: case 0x4: { |
| 5158 | OPC_CheckField, 0, 24, 0, // 9995: check Inst[23:0] == 0x0 |
| 5159 | OPC_Scope, 9, // 9999: try { |
| 5160 | OPC_CheckField, 48, 4, 0, // 10001: check Inst[51:48] == 0x0 |
| 5161 | OPC_Decode, 164, 80, 152, 1, // 10005: decode to VSTOTrrv using decoder 152 |
| 5162 | // 10005: } else try { |
| 5163 | OPC_Decode, 167, 80, 153, 1, // 10010: decode to VSTOTrrvm using decoder 153 |
| 5164 | // 10010: } |
| 5165 | // 10010: } |
| 5166 | // 10010: } // switch Inst[54:52] |
| 5167 | // 10010: } |
| 5168 | // 10010: } // switch Inst[47] |
| 5169 | // 10010: } |
| 5170 | // 10010: } // switch Inst[39] |
| 5171 | // 10010: } |
| 5172 | 164, 2, 209, 1, // 10015: case 0x124: { |
| 5173 | OPC_SwitchField, 39, 1, // 10019: switch Inst[39] { |
| 5174 | 0, 101, // 10022: case 0x0: { |
| 5175 | OPC_SwitchField, 47, 1, // 10024: switch Inst[47] { |
| 5176 | 0, 47, // 10027: case 0x0: { |
| 5177 | OPC_SwitchField, 52, 3, // 10029: switch Inst[54:52] { |
| 5178 | 0, 20, // 10032: case 0x0: { |
| 5179 | OPC_CheckField, 0, 24, 0, // 10034: check Inst[23:0] == 0x0 |
| 5180 | OPC_Scope, 9, // 10038: try { |
| 5181 | OPC_CheckField, 48, 4, 0, // 10040: check Inst[51:48] == 0x0 |
| 5182 | OPC_Decode, 174, 81, 146, 1, // 10044: decode to VSTUNCizv using decoder 146 |
| 5183 | // 10044: } else try { |
| 5184 | OPC_Decode, 177, 81, 147, 1, // 10049: decode to VSTUNCizvm using decoder 147 |
| 5185 | // 10049: } |
| 5186 | // 10049: } |
| 5187 | 4, 0, // 10054: case 0x4: { |
| 5188 | OPC_CheckField, 0, 24, 0, // 10056: check Inst[23:0] == 0x0 |
| 5189 | OPC_Scope, 9, // 10060: try { |
| 5190 | OPC_CheckField, 48, 4, 0, // 10062: check Inst[51:48] == 0x0 |
| 5191 | OPC_Decode, 222, 81, 146, 1, // 10066: decode to VSTUizv using decoder 146 |
| 5192 | // 10066: } else try { |
| 5193 | OPC_Decode, 225, 81, 147, 1, // 10071: decode to VSTUizvm using decoder 147 |
| 5194 | // 10071: } |
| 5195 | // 10071: } |
| 5196 | // 10071: } // switch Inst[54:52] |
| 5197 | // 10071: } |
| 5198 | 1, 0, // 10076: case 0x1: { |
| 5199 | OPC_SwitchField, 52, 3, // 10078: switch Inst[54:52] { |
| 5200 | 0, 20, // 10081: case 0x0: { |
| 5201 | OPC_CheckField, 0, 24, 0, // 10083: check Inst[23:0] == 0x0 |
| 5202 | OPC_Scope, 9, // 10087: try { |
| 5203 | OPC_CheckField, 48, 4, 0, // 10089: check Inst[51:48] == 0x0 |
| 5204 | OPC_Decode, 186, 81, 148, 1, // 10093: decode to VSTUNCrzv using decoder 148 |
| 5205 | // 10093: } else try { |
| 5206 | OPC_Decode, 189, 81, 149, 1, // 10098: decode to VSTUNCrzvm using decoder 149 |
| 5207 | // 10098: } |
| 5208 | // 10098: } |
| 5209 | 4, 0, // 10103: case 0x4: { |
| 5210 | OPC_CheckField, 0, 24, 0, // 10105: check Inst[23:0] == 0x0 |
| 5211 | OPC_Scope, 9, // 10109: try { |
| 5212 | OPC_CheckField, 48, 4, 0, // 10111: check Inst[51:48] == 0x0 |
| 5213 | OPC_Decode, 234, 81, 148, 1, // 10115: decode to VSTUrzv using decoder 148 |
| 5214 | // 10115: } else try { |
| 5215 | OPC_Decode, 237, 81, 149, 1, // 10120: decode to VSTUrzvm using decoder 149 |
| 5216 | // 10120: } |
| 5217 | // 10120: } |
| 5218 | // 10120: } // switch Inst[54:52] |
| 5219 | // 10120: } |
| 5220 | // 10120: } // switch Inst[47] |
| 5221 | // 10120: } |
| 5222 | 1, 0, // 10125: case 0x1: { |
| 5223 | OPC_SwitchField, 47, 1, // 10127: switch Inst[47] { |
| 5224 | 0, 47, // 10130: case 0x0: { |
| 5225 | OPC_SwitchField, 52, 3, // 10132: switch Inst[54:52] { |
| 5226 | 0, 20, // 10135: case 0x0: { |
| 5227 | OPC_CheckField, 0, 24, 0, // 10137: check Inst[23:0] == 0x0 |
| 5228 | OPC_Scope, 9, // 10141: try { |
| 5229 | OPC_CheckField, 48, 4, 0, // 10143: check Inst[51:48] == 0x0 |
| 5230 | OPC_Decode, 168, 81, 150, 1, // 10147: decode to VSTUNCirv using decoder 150 |
| 5231 | // 10147: } else try { |
| 5232 | OPC_Decode, 171, 81, 151, 1, // 10152: decode to VSTUNCirvm using decoder 151 |
| 5233 | // 10152: } |
| 5234 | // 10152: } |
| 5235 | 4, 0, // 10157: case 0x4: { |
| 5236 | OPC_CheckField, 0, 24, 0, // 10159: check Inst[23:0] == 0x0 |
| 5237 | OPC_Scope, 9, // 10163: try { |
| 5238 | OPC_CheckField, 48, 4, 0, // 10165: check Inst[51:48] == 0x0 |
| 5239 | OPC_Decode, 216, 81, 150, 1, // 10169: decode to VSTUirv using decoder 150 |
| 5240 | // 10169: } else try { |
| 5241 | OPC_Decode, 219, 81, 151, 1, // 10174: decode to VSTUirvm using decoder 151 |
| 5242 | // 10174: } |
| 5243 | // 10174: } |
| 5244 | // 10174: } // switch Inst[54:52] |
| 5245 | // 10174: } |
| 5246 | 1, 0, // 10179: case 0x1: { |
| 5247 | OPC_SwitchField, 52, 3, // 10181: switch Inst[54:52] { |
| 5248 | 0, 20, // 10184: case 0x0: { |
| 5249 | OPC_CheckField, 0, 24, 0, // 10186: check Inst[23:0] == 0x0 |
| 5250 | OPC_Scope, 9, // 10190: try { |
| 5251 | OPC_CheckField, 48, 4, 0, // 10192: check Inst[51:48] == 0x0 |
| 5252 | OPC_Decode, 180, 81, 152, 1, // 10196: decode to VSTUNCrrv using decoder 152 |
| 5253 | // 10196: } else try { |
| 5254 | OPC_Decode, 183, 81, 153, 1, // 10201: decode to VSTUNCrrvm using decoder 153 |
| 5255 | // 10201: } |
| 5256 | // 10201: } |
| 5257 | 4, 0, // 10206: case 0x4: { |
| 5258 | OPC_CheckField, 0, 24, 0, // 10208: check Inst[23:0] == 0x0 |
| 5259 | OPC_Scope, 9, // 10212: try { |
| 5260 | OPC_CheckField, 48, 4, 0, // 10214: check Inst[51:48] == 0x0 |
| 5261 | OPC_Decode, 228, 81, 152, 1, // 10218: decode to VSTUrrv using decoder 152 |
| 5262 | // 10218: } else try { |
| 5263 | OPC_Decode, 231, 81, 153, 1, // 10223: decode to VSTUrrvm using decoder 153 |
| 5264 | // 10223: } |
| 5265 | // 10223: } |
| 5266 | // 10223: } // switch Inst[54:52] |
| 5267 | // 10223: } |
| 5268 | // 10223: } // switch Inst[47] |
| 5269 | // 10223: } |
| 5270 | // 10223: } // switch Inst[39] |
| 5271 | // 10223: } |
| 5272 | 165, 2, 209, 1, // 10228: case 0x125: { |
| 5273 | OPC_SwitchField, 39, 1, // 10232: switch Inst[39] { |
| 5274 | 0, 101, // 10235: case 0x0: { |
| 5275 | OPC_SwitchField, 47, 1, // 10237: switch Inst[47] { |
| 5276 | 0, 47, // 10240: case 0x0: { |
| 5277 | OPC_SwitchField, 52, 3, // 10242: switch Inst[54:52] { |
| 5278 | 0, 20, // 10245: case 0x0: { |
| 5279 | OPC_CheckField, 0, 24, 0, // 10247: check Inst[23:0] == 0x0 |
| 5280 | OPC_Scope, 9, // 10251: try { |
| 5281 | OPC_CheckField, 48, 4, 0, // 10253: check Inst[51:48] == 0x0 |
| 5282 | OPC_Decode, 150, 81, 146, 1, // 10257: decode to VSTUNCOTizv using decoder 146 |
| 5283 | // 10257: } else try { |
| 5284 | OPC_Decode, 153, 81, 147, 1, // 10262: decode to VSTUNCOTizvm using decoder 147 |
| 5285 | // 10262: } |
| 5286 | // 10262: } |
| 5287 | 4, 0, // 10267: case 0x4: { |
| 5288 | OPC_CheckField, 0, 24, 0, // 10269: check Inst[23:0] == 0x0 |
| 5289 | OPC_Scope, 9, // 10273: try { |
| 5290 | OPC_CheckField, 48, 4, 0, // 10275: check Inst[51:48] == 0x0 |
| 5291 | OPC_Decode, 198, 81, 146, 1, // 10279: decode to VSTUOTizv using decoder 146 |
| 5292 | // 10279: } else try { |
| 5293 | OPC_Decode, 201, 81, 147, 1, // 10284: decode to VSTUOTizvm using decoder 147 |
| 5294 | // 10284: } |
| 5295 | // 10284: } |
| 5296 | // 10284: } // switch Inst[54:52] |
| 5297 | // 10284: } |
| 5298 | 1, 0, // 10289: case 0x1: { |
| 5299 | OPC_SwitchField, 52, 3, // 10291: switch Inst[54:52] { |
| 5300 | 0, 20, // 10294: case 0x0: { |
| 5301 | OPC_CheckField, 0, 24, 0, // 10296: check Inst[23:0] == 0x0 |
| 5302 | OPC_Scope, 9, // 10300: try { |
| 5303 | OPC_CheckField, 48, 4, 0, // 10302: check Inst[51:48] == 0x0 |
| 5304 | OPC_Decode, 162, 81, 148, 1, // 10306: decode to VSTUNCOTrzv using decoder 148 |
| 5305 | // 10306: } else try { |
| 5306 | OPC_Decode, 165, 81, 149, 1, // 10311: decode to VSTUNCOTrzvm using decoder 149 |
| 5307 | // 10311: } |
| 5308 | // 10311: } |
| 5309 | 4, 0, // 10316: case 0x4: { |
| 5310 | OPC_CheckField, 0, 24, 0, // 10318: check Inst[23:0] == 0x0 |
| 5311 | OPC_Scope, 9, // 10322: try { |
| 5312 | OPC_CheckField, 48, 4, 0, // 10324: check Inst[51:48] == 0x0 |
| 5313 | OPC_Decode, 210, 81, 148, 1, // 10328: decode to VSTUOTrzv using decoder 148 |
| 5314 | // 10328: } else try { |
| 5315 | OPC_Decode, 213, 81, 149, 1, // 10333: decode to VSTUOTrzvm using decoder 149 |
| 5316 | // 10333: } |
| 5317 | // 10333: } |
| 5318 | // 10333: } // switch Inst[54:52] |
| 5319 | // 10333: } |
| 5320 | // 10333: } // switch Inst[47] |
| 5321 | // 10333: } |
| 5322 | 1, 0, // 10338: case 0x1: { |
| 5323 | OPC_SwitchField, 47, 1, // 10340: switch Inst[47] { |
| 5324 | 0, 47, // 10343: case 0x0: { |
| 5325 | OPC_SwitchField, 52, 3, // 10345: switch Inst[54:52] { |
| 5326 | 0, 20, // 10348: case 0x0: { |
| 5327 | OPC_CheckField, 0, 24, 0, // 10350: check Inst[23:0] == 0x0 |
| 5328 | OPC_Scope, 9, // 10354: try { |
| 5329 | OPC_CheckField, 48, 4, 0, // 10356: check Inst[51:48] == 0x0 |
| 5330 | OPC_Decode, 144, 81, 150, 1, // 10360: decode to VSTUNCOTirv using decoder 150 |
| 5331 | // 10360: } else try { |
| 5332 | OPC_Decode, 147, 81, 151, 1, // 10365: decode to VSTUNCOTirvm using decoder 151 |
| 5333 | // 10365: } |
| 5334 | // 10365: } |
| 5335 | 4, 0, // 10370: case 0x4: { |
| 5336 | OPC_CheckField, 0, 24, 0, // 10372: check Inst[23:0] == 0x0 |
| 5337 | OPC_Scope, 9, // 10376: try { |
| 5338 | OPC_CheckField, 48, 4, 0, // 10378: check Inst[51:48] == 0x0 |
| 5339 | OPC_Decode, 192, 81, 150, 1, // 10382: decode to VSTUOTirv using decoder 150 |
| 5340 | // 10382: } else try { |
| 5341 | OPC_Decode, 195, 81, 151, 1, // 10387: decode to VSTUOTirvm using decoder 151 |
| 5342 | // 10387: } |
| 5343 | // 10387: } |
| 5344 | // 10387: } // switch Inst[54:52] |
| 5345 | // 10387: } |
| 5346 | 1, 0, // 10392: case 0x1: { |
| 5347 | OPC_SwitchField, 52, 3, // 10394: switch Inst[54:52] { |
| 5348 | 0, 20, // 10397: case 0x0: { |
| 5349 | OPC_CheckField, 0, 24, 0, // 10399: check Inst[23:0] == 0x0 |
| 5350 | OPC_Scope, 9, // 10403: try { |
| 5351 | OPC_CheckField, 48, 4, 0, // 10405: check Inst[51:48] == 0x0 |
| 5352 | OPC_Decode, 156, 81, 152, 1, // 10409: decode to VSTUNCOTrrv using decoder 152 |
| 5353 | // 10409: } else try { |
| 5354 | OPC_Decode, 159, 81, 153, 1, // 10414: decode to VSTUNCOTrrvm using decoder 153 |
| 5355 | // 10414: } |
| 5356 | // 10414: } |
| 5357 | 4, 0, // 10419: case 0x4: { |
| 5358 | OPC_CheckField, 0, 24, 0, // 10421: check Inst[23:0] == 0x0 |
| 5359 | OPC_Scope, 9, // 10425: try { |
| 5360 | OPC_CheckField, 48, 4, 0, // 10427: check Inst[51:48] == 0x0 |
| 5361 | OPC_Decode, 204, 81, 152, 1, // 10431: decode to VSTUOTrrv using decoder 152 |
| 5362 | // 10431: } else try { |
| 5363 | OPC_Decode, 207, 81, 153, 1, // 10436: decode to VSTUOTrrvm using decoder 153 |
| 5364 | // 10436: } |
| 5365 | // 10436: } |
| 5366 | // 10436: } // switch Inst[54:52] |
| 5367 | // 10436: } |
| 5368 | // 10436: } // switch Inst[47] |
| 5369 | // 10436: } |
| 5370 | // 10436: } // switch Inst[39] |
| 5371 | // 10436: } |
| 5372 | 166, 2, 209, 1, // 10441: case 0x126: { |
| 5373 | OPC_SwitchField, 39, 1, // 10445: switch Inst[39] { |
| 5374 | 0, 101, // 10448: case 0x0: { |
| 5375 | OPC_SwitchField, 47, 1, // 10450: switch Inst[47] { |
| 5376 | 0, 47, // 10453: case 0x0: { |
| 5377 | OPC_SwitchField, 52, 3, // 10455: switch Inst[54:52] { |
| 5378 | 0, 20, // 10458: case 0x0: { |
| 5379 | OPC_CheckField, 0, 24, 0, // 10460: check Inst[23:0] == 0x0 |
| 5380 | OPC_Scope, 9, // 10464: try { |
| 5381 | OPC_CheckField, 48, 4, 0, // 10466: check Inst[51:48] == 0x0 |
| 5382 | OPC_Decode, 166, 79, 146, 1, // 10470: decode to VSTLNCizv using decoder 146 |
| 5383 | // 10470: } else try { |
| 5384 | OPC_Decode, 169, 79, 147, 1, // 10475: decode to VSTLNCizvm using decoder 147 |
| 5385 | // 10475: } |
| 5386 | // 10475: } |
| 5387 | 4, 0, // 10480: case 0x4: { |
| 5388 | OPC_CheckField, 0, 24, 0, // 10482: check Inst[23:0] == 0x0 |
| 5389 | OPC_Scope, 9, // 10486: try { |
| 5390 | OPC_CheckField, 48, 4, 0, // 10488: check Inst[51:48] == 0x0 |
| 5391 | OPC_Decode, 214, 79, 146, 1, // 10492: decode to VSTLizv using decoder 146 |
| 5392 | // 10492: } else try { |
| 5393 | OPC_Decode, 217, 79, 147, 1, // 10497: decode to VSTLizvm using decoder 147 |
| 5394 | // 10497: } |
| 5395 | // 10497: } |
| 5396 | // 10497: } // switch Inst[54:52] |
| 5397 | // 10497: } |
| 5398 | 1, 0, // 10502: case 0x1: { |
| 5399 | OPC_SwitchField, 52, 3, // 10504: switch Inst[54:52] { |
| 5400 | 0, 20, // 10507: case 0x0: { |
| 5401 | OPC_CheckField, 0, 24, 0, // 10509: check Inst[23:0] == 0x0 |
| 5402 | OPC_Scope, 9, // 10513: try { |
| 5403 | OPC_CheckField, 48, 4, 0, // 10515: check Inst[51:48] == 0x0 |
| 5404 | OPC_Decode, 178, 79, 148, 1, // 10519: decode to VSTLNCrzv using decoder 148 |
| 5405 | // 10519: } else try { |
| 5406 | OPC_Decode, 181, 79, 149, 1, // 10524: decode to VSTLNCrzvm using decoder 149 |
| 5407 | // 10524: } |
| 5408 | // 10524: } |
| 5409 | 4, 0, // 10529: case 0x4: { |
| 5410 | OPC_CheckField, 0, 24, 0, // 10531: check Inst[23:0] == 0x0 |
| 5411 | OPC_Scope, 9, // 10535: try { |
| 5412 | OPC_CheckField, 48, 4, 0, // 10537: check Inst[51:48] == 0x0 |
| 5413 | OPC_Decode, 226, 79, 148, 1, // 10541: decode to VSTLrzv using decoder 148 |
| 5414 | // 10541: } else try { |
| 5415 | OPC_Decode, 229, 79, 149, 1, // 10546: decode to VSTLrzvm using decoder 149 |
| 5416 | // 10546: } |
| 5417 | // 10546: } |
| 5418 | // 10546: } // switch Inst[54:52] |
| 5419 | // 10546: } |
| 5420 | // 10546: } // switch Inst[47] |
| 5421 | // 10546: } |
| 5422 | 1, 0, // 10551: case 0x1: { |
| 5423 | OPC_SwitchField, 47, 1, // 10553: switch Inst[47] { |
| 5424 | 0, 47, // 10556: case 0x0: { |
| 5425 | OPC_SwitchField, 52, 3, // 10558: switch Inst[54:52] { |
| 5426 | 0, 20, // 10561: case 0x0: { |
| 5427 | OPC_CheckField, 0, 24, 0, // 10563: check Inst[23:0] == 0x0 |
| 5428 | OPC_Scope, 9, // 10567: try { |
| 5429 | OPC_CheckField, 48, 4, 0, // 10569: check Inst[51:48] == 0x0 |
| 5430 | OPC_Decode, 160, 79, 150, 1, // 10573: decode to VSTLNCirv using decoder 150 |
| 5431 | // 10573: } else try { |
| 5432 | OPC_Decode, 163, 79, 151, 1, // 10578: decode to VSTLNCirvm using decoder 151 |
| 5433 | // 10578: } |
| 5434 | // 10578: } |
| 5435 | 4, 0, // 10583: case 0x4: { |
| 5436 | OPC_CheckField, 0, 24, 0, // 10585: check Inst[23:0] == 0x0 |
| 5437 | OPC_Scope, 9, // 10589: try { |
| 5438 | OPC_CheckField, 48, 4, 0, // 10591: check Inst[51:48] == 0x0 |
| 5439 | OPC_Decode, 208, 79, 150, 1, // 10595: decode to VSTLirv using decoder 150 |
| 5440 | // 10595: } else try { |
| 5441 | OPC_Decode, 211, 79, 151, 1, // 10600: decode to VSTLirvm using decoder 151 |
| 5442 | // 10600: } |
| 5443 | // 10600: } |
| 5444 | // 10600: } // switch Inst[54:52] |
| 5445 | // 10600: } |
| 5446 | 1, 0, // 10605: case 0x1: { |
| 5447 | OPC_SwitchField, 52, 3, // 10607: switch Inst[54:52] { |
| 5448 | 0, 20, // 10610: case 0x0: { |
| 5449 | OPC_CheckField, 0, 24, 0, // 10612: check Inst[23:0] == 0x0 |
| 5450 | OPC_Scope, 9, // 10616: try { |
| 5451 | OPC_CheckField, 48, 4, 0, // 10618: check Inst[51:48] == 0x0 |
| 5452 | OPC_Decode, 172, 79, 152, 1, // 10622: decode to VSTLNCrrv using decoder 152 |
| 5453 | // 10622: } else try { |
| 5454 | OPC_Decode, 175, 79, 153, 1, // 10627: decode to VSTLNCrrvm using decoder 153 |
| 5455 | // 10627: } |
| 5456 | // 10627: } |
| 5457 | 4, 0, // 10632: case 0x4: { |
| 5458 | OPC_CheckField, 0, 24, 0, // 10634: check Inst[23:0] == 0x0 |
| 5459 | OPC_Scope, 9, // 10638: try { |
| 5460 | OPC_CheckField, 48, 4, 0, // 10640: check Inst[51:48] == 0x0 |
| 5461 | OPC_Decode, 220, 79, 152, 1, // 10644: decode to VSTLrrv using decoder 152 |
| 5462 | // 10644: } else try { |
| 5463 | OPC_Decode, 223, 79, 153, 1, // 10649: decode to VSTLrrvm using decoder 153 |
| 5464 | // 10649: } |
| 5465 | // 10649: } |
| 5466 | // 10649: } // switch Inst[54:52] |
| 5467 | // 10649: } |
| 5468 | // 10649: } // switch Inst[47] |
| 5469 | // 10649: } |
| 5470 | // 10649: } // switch Inst[39] |
| 5471 | // 10649: } |
| 5472 | 167, 2, 209, 1, // 10654: case 0x127: { |
| 5473 | OPC_SwitchField, 39, 1, // 10658: switch Inst[39] { |
| 5474 | 0, 101, // 10661: case 0x0: { |
| 5475 | OPC_SwitchField, 47, 1, // 10663: switch Inst[47] { |
| 5476 | 0, 47, // 10666: case 0x0: { |
| 5477 | OPC_SwitchField, 52, 3, // 10668: switch Inst[54:52] { |
| 5478 | 0, 20, // 10671: case 0x0: { |
| 5479 | OPC_CheckField, 0, 24, 0, // 10673: check Inst[23:0] == 0x0 |
| 5480 | OPC_Scope, 9, // 10677: try { |
| 5481 | OPC_CheckField, 48, 4, 0, // 10679: check Inst[51:48] == 0x0 |
| 5482 | OPC_Decode, 142, 79, 146, 1, // 10683: decode to VSTLNCOTizv using decoder 146 |
| 5483 | // 10683: } else try { |
| 5484 | OPC_Decode, 145, 79, 147, 1, // 10688: decode to VSTLNCOTizvm using decoder 147 |
| 5485 | // 10688: } |
| 5486 | // 10688: } |
| 5487 | 4, 0, // 10693: case 0x4: { |
| 5488 | OPC_CheckField, 0, 24, 0, // 10695: check Inst[23:0] == 0x0 |
| 5489 | OPC_Scope, 9, // 10699: try { |
| 5490 | OPC_CheckField, 48, 4, 0, // 10701: check Inst[51:48] == 0x0 |
| 5491 | OPC_Decode, 190, 79, 146, 1, // 10705: decode to VSTLOTizv using decoder 146 |
| 5492 | // 10705: } else try { |
| 5493 | OPC_Decode, 193, 79, 147, 1, // 10710: decode to VSTLOTizvm using decoder 147 |
| 5494 | // 10710: } |
| 5495 | // 10710: } |
| 5496 | // 10710: } // switch Inst[54:52] |
| 5497 | // 10710: } |
| 5498 | 1, 0, // 10715: case 0x1: { |
| 5499 | OPC_SwitchField, 52, 3, // 10717: switch Inst[54:52] { |
| 5500 | 0, 20, // 10720: case 0x0: { |
| 5501 | OPC_CheckField, 0, 24, 0, // 10722: check Inst[23:0] == 0x0 |
| 5502 | OPC_Scope, 9, // 10726: try { |
| 5503 | OPC_CheckField, 48, 4, 0, // 10728: check Inst[51:48] == 0x0 |
| 5504 | OPC_Decode, 154, 79, 148, 1, // 10732: decode to VSTLNCOTrzv using decoder 148 |
| 5505 | // 10732: } else try { |
| 5506 | OPC_Decode, 157, 79, 149, 1, // 10737: decode to VSTLNCOTrzvm using decoder 149 |
| 5507 | // 10737: } |
| 5508 | // 10737: } |
| 5509 | 4, 0, // 10742: case 0x4: { |
| 5510 | OPC_CheckField, 0, 24, 0, // 10744: check Inst[23:0] == 0x0 |
| 5511 | OPC_Scope, 9, // 10748: try { |
| 5512 | OPC_CheckField, 48, 4, 0, // 10750: check Inst[51:48] == 0x0 |
| 5513 | OPC_Decode, 202, 79, 148, 1, // 10754: decode to VSTLOTrzv using decoder 148 |
| 5514 | // 10754: } else try { |
| 5515 | OPC_Decode, 205, 79, 149, 1, // 10759: decode to VSTLOTrzvm using decoder 149 |
| 5516 | // 10759: } |
| 5517 | // 10759: } |
| 5518 | // 10759: } // switch Inst[54:52] |
| 5519 | // 10759: } |
| 5520 | // 10759: } // switch Inst[47] |
| 5521 | // 10759: } |
| 5522 | 1, 0, // 10764: case 0x1: { |
| 5523 | OPC_SwitchField, 47, 1, // 10766: switch Inst[47] { |
| 5524 | 0, 47, // 10769: case 0x0: { |
| 5525 | OPC_SwitchField, 52, 3, // 10771: switch Inst[54:52] { |
| 5526 | 0, 20, // 10774: case 0x0: { |
| 5527 | OPC_CheckField, 0, 24, 0, // 10776: check Inst[23:0] == 0x0 |
| 5528 | OPC_Scope, 9, // 10780: try { |
| 5529 | OPC_CheckField, 48, 4, 0, // 10782: check Inst[51:48] == 0x0 |
| 5530 | OPC_Decode, 136, 79, 150, 1, // 10786: decode to VSTLNCOTirv using decoder 150 |
| 5531 | // 10786: } else try { |
| 5532 | OPC_Decode, 139, 79, 151, 1, // 10791: decode to VSTLNCOTirvm using decoder 151 |
| 5533 | // 10791: } |
| 5534 | // 10791: } |
| 5535 | 4, 0, // 10796: case 0x4: { |
| 5536 | OPC_CheckField, 0, 24, 0, // 10798: check Inst[23:0] == 0x0 |
| 5537 | OPC_Scope, 9, // 10802: try { |
| 5538 | OPC_CheckField, 48, 4, 0, // 10804: check Inst[51:48] == 0x0 |
| 5539 | OPC_Decode, 184, 79, 150, 1, // 10808: decode to VSTLOTirv using decoder 150 |
| 5540 | // 10808: } else try { |
| 5541 | OPC_Decode, 187, 79, 151, 1, // 10813: decode to VSTLOTirvm using decoder 151 |
| 5542 | // 10813: } |
| 5543 | // 10813: } |
| 5544 | // 10813: } // switch Inst[54:52] |
| 5545 | // 10813: } |
| 5546 | 1, 0, // 10818: case 0x1: { |
| 5547 | OPC_SwitchField, 52, 3, // 10820: switch Inst[54:52] { |
| 5548 | 0, 20, // 10823: case 0x0: { |
| 5549 | OPC_CheckField, 0, 24, 0, // 10825: check Inst[23:0] == 0x0 |
| 5550 | OPC_Scope, 9, // 10829: try { |
| 5551 | OPC_CheckField, 48, 4, 0, // 10831: check Inst[51:48] == 0x0 |
| 5552 | OPC_Decode, 148, 79, 152, 1, // 10835: decode to VSTLNCOTrrv using decoder 152 |
| 5553 | // 10835: } else try { |
| 5554 | OPC_Decode, 151, 79, 153, 1, // 10840: decode to VSTLNCOTrrvm using decoder 153 |
| 5555 | // 10840: } |
| 5556 | // 10840: } |
| 5557 | 4, 0, // 10845: case 0x4: { |
| 5558 | OPC_CheckField, 0, 24, 0, // 10847: check Inst[23:0] == 0x0 |
| 5559 | OPC_Scope, 9, // 10851: try { |
| 5560 | OPC_CheckField, 48, 4, 0, // 10853: check Inst[51:48] == 0x0 |
| 5561 | OPC_Decode, 196, 79, 152, 1, // 10857: decode to VSTLOTrrv using decoder 152 |
| 5562 | // 10857: } else try { |
| 5563 | OPC_Decode, 199, 79, 153, 1, // 10862: decode to VSTLOTrrvm using decoder 153 |
| 5564 | // 10862: } |
| 5565 | // 10862: } |
| 5566 | // 10862: } // switch Inst[54:52] |
| 5567 | // 10862: } |
| 5568 | // 10862: } // switch Inst[47] |
| 5569 | // 10862: } |
| 5570 | // 10862: } // switch Inst[39] |
| 5571 | // 10862: } |
| 5572 | 168, 2, 12, // 10867: case 0x128: { |
| 5573 | OPC_CheckField, 32, 23, 0, // 10870: check Inst[54:32] == 0x0 |
| 5574 | OPC_CheckField, 0, 8, 0, // 10874: check Inst[7:0] == 0x0 |
| 5575 | OPC_Decode, 251, 6, 118, // 10878: decode to NNDMmm using decoder 118 |
| 5576 | // 10878: } |
| 5577 | 170, 2, 13, // 10882: case 0x12a: { |
| 5578 | OPC_CheckField, 32, 23, 0, // 10885: check Inst[54:32] == 0x0 |
| 5579 | OPC_CheckField, 0, 16, 0, // 10889: check Inst[15:0] == 0x0 |
| 5580 | OPC_Decode, 250, 6, 154, 1, // 10893: decode to NEGMm using decoder 154 |
| 5581 | // 10893: } |
| 5582 | 176, 2, 26, // 10898: case 0x130: { |
| 5583 | OPC_CheckField, 0, 16, 0, // 10901: check Inst[15:0] == 0x0 |
| 5584 | OPC_CheckField, 32, 16, 0, // 10905: check Inst[47:32] == 0x0 |
| 5585 | OPC_CheckField, 52, 3, 0, // 10909: check Inst[54:52] == 0x0 |
| 5586 | OPC_Scope, 8, // 10913: try { |
| 5587 | OPC_CheckField, 48, 4, 0, // 10915: check Inst[51:48] == 0x0 |
| 5588 | OPC_Decode, 168, 69, 119, // 10919: decode to VRORv using decoder 119 |
| 5589 | // 10919: } else try { |
| 5590 | OPC_Decode, 174, 69, 120, // 10923: decode to VRORvm using decoder 120 |
| 5591 | // 10923: } |
| 5592 | // 10923: } |
| 5593 | 178, 2, 55, // 10927: case 0x132: { |
| 5594 | OPC_SwitchField, 52, 3, // 10930: switch Inst[54:52] { |
| 5595 | 0, 24, // 10933: case 0x0: { |
| 5596 | OPC_CheckField, 0, 24, 0, // 10935: check Inst[23:0] == 0x0 |
| 5597 | OPC_CheckField, 32, 16, 0, // 10939: check Inst[47:32] == 0x0 |
| 5598 | OPC_Scope, 9, // 10943: try { |
| 5599 | OPC_CheckField, 48, 4, 0, // 10945: check Inst[51:48] == 0x0 |
| 5600 | OPC_Decode, 176, 74, 155, 1, // 10949: decode to VSEQ using decoder 155 |
| 5601 | // 10949: } else try { |
| 5602 | OPC_Decode, 182, 74, 156, 1, // 10954: decode to VSEQm using decoder 156 |
| 5603 | // 10954: } |
| 5604 | // 10954: } |
| 5605 | 4, 0, // 10959: case 0x4: { |
| 5606 | OPC_CheckField, 0, 24, 0, // 10961: check Inst[23:0] == 0x0 |
| 5607 | OPC_CheckField, 32, 16, 0, // 10965: check Inst[47:32] == 0x0 |
| 5608 | OPC_Scope, 9, // 10969: try { |
| 5609 | OPC_CheckField, 48, 4, 0, // 10971: check Inst[51:48] == 0x0 |
| 5610 | OPC_Decode, 205, 28, 155, 1, // 10975: decode to PVSEQLO using decoder 155 |
| 5611 | // 10975: } else try { |
| 5612 | OPC_Decode, 211, 28, 156, 1, // 10980: decode to PVSEQLOm using decoder 156 |
| 5613 | // 10980: } |
| 5614 | // 10980: } |
| 5615 | // 10980: } // switch Inst[54:52] |
| 5616 | // 10980: } |
| 5617 | 179, 2, 55, // 10985: case 0x133: { |
| 5618 | OPC_SwitchField, 52, 3, // 10988: switch Inst[54:52] { |
| 5619 | 0, 24, // 10991: case 0x0: { |
| 5620 | OPC_CheckField, 0, 24, 0, // 10993: check Inst[23:0] == 0x0 |
| 5621 | OPC_CheckField, 32, 16, 0, // 10997: check Inst[47:32] == 0x0 |
| 5622 | OPC_Scope, 9, // 11001: try { |
| 5623 | OPC_CheckField, 48, 4, 0, // 11003: check Inst[51:48] == 0x0 |
| 5624 | OPC_Decode, 218, 28, 155, 1, // 11007: decode to PVSEQUP using decoder 155 |
| 5625 | // 11007: } else try { |
| 5626 | OPC_Decode, 224, 28, 156, 1, // 11012: decode to PVSEQUPm using decoder 156 |
| 5627 | // 11012: } |
| 5628 | // 11012: } |
| 5629 | 4, 0, // 11017: case 0x4: { |
| 5630 | OPC_CheckField, 0, 24, 0, // 11019: check Inst[23:0] == 0x0 |
| 5631 | OPC_CheckField, 32, 16, 0, // 11023: check Inst[47:32] == 0x0 |
| 5632 | OPC_Scope, 9, // 11027: try { |
| 5633 | OPC_CheckField, 48, 4, 0, // 11029: check Inst[51:48] == 0x0 |
| 5634 | OPC_Decode, 203, 28, 155, 1, // 11033: decode to PVSEQ using decoder 155 |
| 5635 | // 11033: } else try { |
| 5636 | OPC_Decode, 233, 28, 157, 1, // 11038: decode to PVSEQm using decoder 157 |
| 5637 | // 11038: } |
| 5638 | // 11038: } |
| 5639 | // 11038: } // switch Inst[54:52] |
| 5640 | // 11038: } |
| 5641 | 180, 2, 175, 1, // 11043: case 0x134: { |
| 5642 | OPC_SwitchField, 52, 3, // 11047: switch Inst[54:52] { |
| 5643 | 0, 22, // 11050: case 0x0: { |
| 5644 | OPC_CheckField, 0, 8, 0, // 11052: check Inst[7:0] == 0x0 |
| 5645 | OPC_CheckField, 32, 16, 0, // 11056: check Inst[47:32] == 0x0 |
| 5646 | OPC_Scope, 8, // 11060: try { |
| 5647 | OPC_CheckField, 48, 4, 0, // 11062: check Inst[51:48] == 0x0 |
| 5648 | OPC_Decode, 204, 63, 121, // 11066: decode to VMAXSLvv using decoder 121 |
| 5649 | // 11066: } else try { |
| 5650 | OPC_Decode, 210, 63, 122, // 11070: decode to VMAXSLvvm using decoder 122 |
| 5651 | // 11070: } |
| 5652 | // 11070: } |
| 5653 | 1, 22, // 11074: case 0x1: { |
| 5654 | OPC_CheckField, 0, 8, 0, // 11076: check Inst[7:0] == 0x0 |
| 5655 | OPC_CheckField, 32, 16, 0, // 11080: check Inst[47:32] == 0x0 |
| 5656 | OPC_Scope, 8, // 11084: try { |
| 5657 | OPC_CheckField, 48, 4, 0, // 11086: check Inst[51:48] == 0x0 |
| 5658 | OPC_Decode, 184, 64, 121, // 11090: decode to VMINSLvv using decoder 121 |
| 5659 | // 11090: } else try { |
| 5660 | OPC_Decode, 190, 64, 122, // 11094: decode to VMINSLvvm using decoder 122 |
| 5661 | // 11094: } |
| 5662 | // 11094: } |
| 5663 | 2, 60, // 11098: case 0x2: { |
| 5664 | OPC_SwitchField, 47, 1, // 11100: switch Inst[47] { |
| 5665 | 0, 26, // 11103: case 0x0: { |
| 5666 | OPC_CheckField, 0, 8, 0, // 11105: check Inst[7:0] == 0x0 |
| 5667 | OPC_CheckField, 16, 8, 0, // 11109: check Inst[23:16] == 0x0 |
| 5668 | OPC_CheckField, 32, 8, 0, // 11113: check Inst[39:32] == 0x0 |
| 5669 | OPC_Scope, 8, // 11117: try { |
| 5670 | OPC_CheckField, 48, 4, 0, // 11119: check Inst[51:48] == 0x0 |
| 5671 | OPC_Decode, 180, 63, 123, // 11123: decode to VMAXSLiv using decoder 123 |
| 5672 | // 11123: } else try { |
| 5673 | OPC_Decode, 186, 63, 124, // 11127: decode to VMAXSLivm using decoder 124 |
| 5674 | // 11127: } |
| 5675 | // 11127: } |
| 5676 | 1, 0, // 11131: case 0x1: { |
| 5677 | OPC_CheckField, 0, 8, 0, // 11133: check Inst[7:0] == 0x0 |
| 5678 | OPC_CheckField, 16, 8, 0, // 11137: check Inst[23:16] == 0x0 |
| 5679 | OPC_CheckField, 32, 8, 0, // 11141: check Inst[39:32] == 0x0 |
| 5680 | OPC_Scope, 8, // 11145: try { |
| 5681 | OPC_CheckField, 48, 4, 0, // 11147: check Inst[51:48] == 0x0 |
| 5682 | OPC_Decode, 192, 63, 127, // 11151: decode to VMAXSLrv using decoder 127 |
| 5683 | // 11151: } else try { |
| 5684 | OPC_Decode, 198, 63, 128, 1, // 11155: decode to VMAXSLrvm using decoder 128 |
| 5685 | // 11155: } |
| 5686 | // 11155: } |
| 5687 | // 11155: } // switch Inst[47] |
| 5688 | // 11155: } |
| 5689 | 3, 0, // 11160: case 0x3: { |
| 5690 | OPC_SwitchField, 47, 1, // 11162: switch Inst[47] { |
| 5691 | 0, 26, // 11165: case 0x0: { |
| 5692 | OPC_CheckField, 0, 8, 0, // 11167: check Inst[7:0] == 0x0 |
| 5693 | OPC_CheckField, 16, 8, 0, // 11171: check Inst[23:16] == 0x0 |
| 5694 | OPC_CheckField, 32, 8, 0, // 11175: check Inst[39:32] == 0x0 |
| 5695 | OPC_Scope, 8, // 11179: try { |
| 5696 | OPC_CheckField, 48, 4, 0, // 11181: check Inst[51:48] == 0x0 |
| 5697 | OPC_Decode, 160, 64, 123, // 11185: decode to VMINSLiv using decoder 123 |
| 5698 | // 11185: } else try { |
| 5699 | OPC_Decode, 166, 64, 124, // 11189: decode to VMINSLivm using decoder 124 |
| 5700 | // 11189: } |
| 5701 | // 11189: } |
| 5702 | 1, 0, // 11193: case 0x1: { |
| 5703 | OPC_CheckField, 0, 8, 0, // 11195: check Inst[7:0] == 0x0 |
| 5704 | OPC_CheckField, 16, 8, 0, // 11199: check Inst[23:16] == 0x0 |
| 5705 | OPC_CheckField, 32, 8, 0, // 11203: check Inst[39:32] == 0x0 |
| 5706 | OPC_Scope, 8, // 11207: try { |
| 5707 | OPC_CheckField, 48, 4, 0, // 11209: check Inst[51:48] == 0x0 |
| 5708 | OPC_Decode, 172, 64, 127, // 11213: decode to VMINSLrv using decoder 127 |
| 5709 | // 11213: } else try { |
| 5710 | OPC_Decode, 178, 64, 128, 1, // 11217: decode to VMINSLrvm using decoder 128 |
| 5711 | // 11217: } |
| 5712 | // 11217: } |
| 5713 | // 11217: } // switch Inst[47] |
| 5714 | // 11217: } |
| 5715 | // 11217: } // switch Inst[54:52] |
| 5716 | // 11217: } |
| 5717 | 182, 2, 93, // 11222: case 0x136: { |
| 5718 | OPC_SwitchField, 47, 1, // 11225: switch Inst[47] { |
| 5719 | 0, 55, // 11228: case 0x0: { |
| 5720 | OPC_SwitchField, 52, 3, // 11230: switch Inst[54:52] { |
| 5721 | 0, 22, // 11233: case 0x0: { |
| 5722 | OPC_CheckField, 0, 8, 0, // 11235: check Inst[7:0] == 0x0 |
| 5723 | OPC_CheckField, 32, 15, 0, // 11239: check Inst[46:32] == 0x0 |
| 5724 | OPC_Scope, 8, // 11243: try { |
| 5725 | OPC_CheckField, 48, 4, 0, // 11245: check Inst[51:48] == 0x0 |
| 5726 | OPC_Decode, 160, 82, 121, // 11249: decode to VSUBSLvv using decoder 121 |
| 5727 | // 11249: } else try { |
| 5728 | OPC_Decode, 166, 82, 122, // 11253: decode to VSUBSLvvm using decoder 122 |
| 5729 | // 11253: } |
| 5730 | // 11253: } |
| 5731 | 2, 0, // 11257: case 0x2: { |
| 5732 | OPC_CheckField, 0, 8, 0, // 11259: check Inst[7:0] == 0x0 |
| 5733 | OPC_CheckField, 16, 8, 0, // 11263: check Inst[23:16] == 0x0 |
| 5734 | OPC_CheckField, 32, 8, 0, // 11267: check Inst[39:32] == 0x0 |
| 5735 | OPC_Scope, 8, // 11271: try { |
| 5736 | OPC_CheckField, 48, 4, 0, // 11273: check Inst[51:48] == 0x0 |
| 5737 | OPC_Decode, 136, 82, 123, // 11277: decode to VSUBSLiv using decoder 123 |
| 5738 | // 11277: } else try { |
| 5739 | OPC_Decode, 142, 82, 124, // 11281: decode to VSUBSLivm using decoder 124 |
| 5740 | // 11281: } |
| 5741 | // 11281: } |
| 5742 | // 11281: } // switch Inst[54:52] |
| 5743 | // 11281: } |
| 5744 | 1, 0, // 11285: case 0x1: { |
| 5745 | OPC_CheckField, 0, 8, 0, // 11287: check Inst[7:0] == 0x0 |
| 5746 | OPC_CheckField, 16, 8, 0, // 11291: check Inst[23:16] == 0x0 |
| 5747 | OPC_CheckField, 32, 8, 0, // 11295: check Inst[39:32] == 0x0 |
| 5748 | OPC_CheckField, 52, 3, 2, // 11299: check Inst[54:52] == 0x2 |
| 5749 | OPC_Scope, 8, // 11303: try { |
| 5750 | OPC_CheckField, 48, 4, 0, // 11305: check Inst[51:48] == 0x0 |
| 5751 | OPC_Decode, 148, 82, 127, // 11309: decode to VSUBSLrv using decoder 127 |
| 5752 | // 11309: } else try { |
| 5753 | OPC_Decode, 154, 82, 128, 1, // 11313: decode to VSUBSLrvm using decoder 128 |
| 5754 | // 11313: } |
| 5755 | // 11313: } |
| 5756 | // 11313: } // switch Inst[47] |
| 5757 | // 11313: } |
| 5758 | 184, 2, 70, // 11318: case 0x138: { |
| 5759 | OPC_SwitchField, 47, 1, // 11321: switch Inst[47] { |
| 5760 | 0, 32, // 11324: case 0x0: { |
| 5761 | OPC_CheckField, 0, 8, 0, // 11326: check Inst[7:0] == 0x0 |
| 5762 | OPC_CheckField, 16, 8, 0, // 11330: check Inst[23:16] == 0x0 |
| 5763 | OPC_CheckField, 32, 8, 0, // 11334: check Inst[39:32] == 0x0 |
| 5764 | OPC_CheckField, 52, 3, 0, // 11338: check Inst[54:52] == 0x0 |
| 5765 | OPC_Scope, 9, // 11342: try { |
| 5766 | OPC_CheckField, 48, 4, 0, // 11344: check Inst[51:48] == 0x0 |
| 5767 | OPC_Decode, 172, 67, 158, 1, // 11348: decode to VMViv using decoder 158 |
| 5768 | // 11348: } else try { |
| 5769 | OPC_Decode, 178, 67, 159, 1, // 11353: decode to VMVivm using decoder 159 |
| 5770 | // 11353: } |
| 5771 | // 11353: } |
| 5772 | 1, 0, // 11358: case 0x1: { |
| 5773 | OPC_CheckField, 0, 8, 0, // 11360: check Inst[7:0] == 0x0 |
| 5774 | OPC_CheckField, 16, 8, 0, // 11364: check Inst[23:16] == 0x0 |
| 5775 | OPC_CheckField, 32, 8, 0, // 11368: check Inst[39:32] == 0x0 |
| 5776 | OPC_CheckField, 52, 3, 0, // 11372: check Inst[54:52] == 0x0 |
| 5777 | OPC_Scope, 8, // 11376: try { |
| 5778 | OPC_CheckField, 48, 4, 0, // 11378: check Inst[51:48] == 0x0 |
| 5779 | OPC_Decode, 184, 67, 127, // 11382: decode to VMVrv using decoder 127 |
| 5780 | // 11382: } else try { |
| 5781 | OPC_Decode, 190, 67, 128, 1, // 11386: decode to VMVrvm using decoder 128 |
| 5782 | // 11386: } |
| 5783 | // 11386: } |
| 5784 | // 11386: } // switch Inst[47] |
| 5785 | // 11386: } |
| 5786 | 186, 2, 32, // 11391: case 0x13a: { |
| 5787 | OPC_CheckField, 0, 8, 0, // 11394: check Inst[7:0] == 0x0 |
| 5788 | OPC_CheckField, 16, 8, 0, // 11398: check Inst[23:16] == 0x0 |
| 5789 | OPC_CheckField, 32, 16, 0, // 11402: check Inst[47:32] == 0x0 |
| 5790 | OPC_CheckField, 52, 3, 0, // 11406: check Inst[54:52] == 0x0 |
| 5791 | OPC_Scope, 9, // 11410: try { |
| 5792 | OPC_CheckField, 48, 4, 0, // 11412: check Inst[51:48] == 0x0 |
| 5793 | OPC_Decode, 148, 43, 142, 1, // 11416: decode to VEXv using decoder 142 |
| 5794 | // 11416: } else try { |
| 5795 | OPC_Decode, 154, 43, 143, 1, // 11421: decode to VEXvm using decoder 143 |
| 5796 | // 11421: } |
| 5797 | // 11421: } |
| 5798 | 188, 2, 33, // 11426: case 0x13c: { |
| 5799 | OPC_SwitchField, 47, 1, // 11429: switch Inst[47] { |
| 5800 | 0, 13, // 11432: case 0x0: { |
| 5801 | OPC_CheckField, 32, 8, 0, // 11434: check Inst[39:32] == 0x0 |
| 5802 | OPC_CheckField, 0, 24, 0, // 11438: check Inst[23:0] == 0x0 |
| 5803 | OPC_Decode, 191, 6, 160, 1, // 11442: decode to LVSvi using decoder 160 |
| 5804 | // 11442: } |
| 5805 | 1, 0, // 11447: case 0x1: { |
| 5806 | OPC_CheckField, 32, 8, 0, // 11449: check Inst[39:32] == 0x0 |
| 5807 | OPC_CheckField, 0, 24, 0, // 11453: check Inst[23:0] == 0x0 |
| 5808 | OPC_Decode, 192, 6, 161, 1, // 11457: decode to LVSvr using decoder 161 |
| 5809 | // 11457: } |
| 5810 | // 11457: } // switch Inst[47] |
| 5811 | // 11457: } |
| 5812 | 190, 2, 26, // 11462: case 0x13e: { |
| 5813 | OPC_CheckField, 0, 16, 0, // 11465: check Inst[15:0] == 0x0 |
| 5814 | OPC_CheckField, 32, 16, 0, // 11469: check Inst[47:32] == 0x0 |
| 5815 | OPC_CheckField, 52, 3, 0, // 11473: check Inst[54:52] == 0x0 |
| 5816 | OPC_Scope, 8, // 11477: try { |
| 5817 | OPC_CheckField, 48, 4, 0, // 11479: check Inst[51:48] == 0x0 |
| 5818 | OPC_Decode, 252, 39, 119, // 11483: decode to VCVTSDv using decoder 119 |
| 5819 | // 11483: } else try { |
| 5820 | OPC_Decode, 130, 40, 120, // 11487: decode to VCVTSDvm using decoder 120 |
| 5821 | // 11487: } |
| 5822 | // 11487: } |
| 5823 | 194, 2, 159, 3, // 11491: case 0x142: { |
| 5824 | OPC_SwitchField, 52, 3, // 11495: switch Inst[54:52] { |
| 5825 | 0, 101, // 11498: case 0x0: { |
| 5826 | OPC_SwitchField, 39, 1, // 11500: switch Inst[39] { |
| 5827 | 0, 47, // 11503: case 0x0: { |
| 5828 | OPC_SwitchField, 47, 1, // 11505: switch Inst[47] { |
| 5829 | 0, 20, // 11508: case 0x0: { |
| 5830 | OPC_CheckField, 0, 16, 0, // 11510: check Inst[15:0] == 0x0 |
| 5831 | OPC_Scope, 9, // 11514: try { |
| 5832 | OPC_CheckField, 48, 4, 0, // 11516: check Inst[51:48] == 0x0 |
| 5833 | OPC_Decode, 228, 57, 162, 1, // 11520: decode to VGTNCviz using decoder 162 |
| 5834 | // 11520: } else try { |
| 5835 | OPC_Decode, 234, 57, 163, 1, // 11525: decode to VGTNCvizm using decoder 163 |
| 5836 | // 11525: } |
| 5837 | // 11525: } |
| 5838 | 1, 0, // 11530: case 0x1: { |
| 5839 | OPC_CheckField, 0, 16, 0, // 11532: check Inst[15:0] == 0x0 |
| 5840 | OPC_Scope, 9, // 11536: try { |
| 5841 | OPC_CheckField, 48, 4, 0, // 11538: check Inst[51:48] == 0x0 |
| 5842 | OPC_Decode, 252, 57, 164, 1, // 11542: decode to VGTNCvrz using decoder 164 |
| 5843 | // 11542: } else try { |
| 5844 | OPC_Decode, 130, 58, 165, 1, // 11547: decode to VGTNCvrzm using decoder 165 |
| 5845 | // 11547: } |
| 5846 | // 11547: } |
| 5847 | // 11547: } // switch Inst[47] |
| 5848 | // 11547: } |
| 5849 | 1, 0, // 11552: case 0x1: { |
| 5850 | OPC_SwitchField, 47, 1, // 11554: switch Inst[47] { |
| 5851 | 0, 20, // 11557: case 0x0: { |
| 5852 | OPC_CheckField, 0, 16, 0, // 11559: check Inst[15:0] == 0x0 |
| 5853 | OPC_Scope, 9, // 11563: try { |
| 5854 | OPC_CheckField, 48, 4, 0, // 11565: check Inst[51:48] == 0x0 |
| 5855 | OPC_Decode, 216, 57, 166, 1, // 11569: decode to VGTNCvir using decoder 166 |
| 5856 | // 11569: } else try { |
| 5857 | OPC_Decode, 222, 57, 167, 1, // 11574: decode to VGTNCvirm using decoder 167 |
| 5858 | // 11574: } |
| 5859 | // 11574: } |
| 5860 | 1, 0, // 11579: case 0x1: { |
| 5861 | OPC_CheckField, 0, 16, 0, // 11581: check Inst[15:0] == 0x0 |
| 5862 | OPC_Scope, 9, // 11585: try { |
| 5863 | OPC_CheckField, 48, 4, 0, // 11587: check Inst[51:48] == 0x0 |
| 5864 | OPC_Decode, 240, 57, 168, 1, // 11591: decode to VGTNCvrr using decoder 168 |
| 5865 | // 11591: } else try { |
| 5866 | OPC_Decode, 246, 57, 169, 1, // 11596: decode to VGTNCvrrm using decoder 169 |
| 5867 | // 11596: } |
| 5868 | // 11596: } |
| 5869 | // 11596: } // switch Inst[47] |
| 5870 | // 11596: } |
| 5871 | // 11596: } // switch Inst[39] |
| 5872 | // 11596: } |
| 5873 | 2, 101, // 11601: case 0x2: { |
| 5874 | OPC_SwitchField, 39, 1, // 11603: switch Inst[39] { |
| 5875 | 0, 47, // 11606: case 0x0: { |
| 5876 | OPC_SwitchField, 47, 1, // 11608: switch Inst[47] { |
| 5877 | 0, 20, // 11611: case 0x0: { |
| 5878 | OPC_CheckField, 7, 17, 0, // 11613: check Inst[23:7] == 0x0 |
| 5879 | OPC_Scope, 9, // 11617: try { |
| 5880 | OPC_CheckField, 48, 4, 0, // 11619: check Inst[51:48] == 0x0 |
| 5881 | OPC_Decode, 180, 57, 170, 1, // 11623: decode to VGTNCsiz using decoder 170 |
| 5882 | // 11623: } else try { |
| 5883 | OPC_Decode, 186, 57, 171, 1, // 11628: decode to VGTNCsizm using decoder 171 |
| 5884 | // 11628: } |
| 5885 | // 11628: } |
| 5886 | 1, 0, // 11633: case 0x1: { |
| 5887 | OPC_CheckField, 7, 17, 0, // 11635: check Inst[23:7] == 0x0 |
| 5888 | OPC_Scope, 9, // 11639: try { |
| 5889 | OPC_CheckField, 48, 4, 0, // 11641: check Inst[51:48] == 0x0 |
| 5890 | OPC_Decode, 204, 57, 172, 1, // 11645: decode to VGTNCsrz using decoder 172 |
| 5891 | // 11645: } else try { |
| 5892 | OPC_Decode, 210, 57, 173, 1, // 11650: decode to VGTNCsrzm using decoder 173 |
| 5893 | // 11650: } |
| 5894 | // 11650: } |
| 5895 | // 11650: } // switch Inst[47] |
| 5896 | // 11650: } |
| 5897 | 1, 0, // 11655: case 0x1: { |
| 5898 | OPC_SwitchField, 47, 1, // 11657: switch Inst[47] { |
| 5899 | 0, 20, // 11660: case 0x0: { |
| 5900 | OPC_CheckField, 7, 17, 0, // 11662: check Inst[23:7] == 0x0 |
| 5901 | OPC_Scope, 9, // 11666: try { |
| 5902 | OPC_CheckField, 48, 4, 0, // 11668: check Inst[51:48] == 0x0 |
| 5903 | OPC_Decode, 168, 57, 174, 1, // 11672: decode to VGTNCsir using decoder 174 |
| 5904 | // 11672: } else try { |
| 5905 | OPC_Decode, 174, 57, 175, 1, // 11677: decode to VGTNCsirm using decoder 175 |
| 5906 | // 11677: } |
| 5907 | // 11677: } |
| 5908 | 1, 0, // 11682: case 0x1: { |
| 5909 | OPC_CheckField, 7, 17, 0, // 11684: check Inst[23:7] == 0x0 |
| 5910 | OPC_Scope, 9, // 11688: try { |
| 5911 | OPC_CheckField, 48, 4, 0, // 11690: check Inst[51:48] == 0x0 |
| 5912 | OPC_Decode, 192, 57, 176, 1, // 11694: decode to VGTNCsrr using decoder 176 |
| 5913 | // 11694: } else try { |
| 5914 | OPC_Decode, 198, 57, 177, 1, // 11699: decode to VGTNCsrrm using decoder 177 |
| 5915 | // 11699: } |
| 5916 | // 11699: } |
| 5917 | // 11699: } // switch Inst[47] |
| 5918 | // 11699: } |
| 5919 | // 11699: } // switch Inst[39] |
| 5920 | // 11699: } |
| 5921 | 4, 101, // 11704: case 0x4: { |
| 5922 | OPC_SwitchField, 39, 1, // 11706: switch Inst[39] { |
| 5923 | 0, 47, // 11709: case 0x0: { |
| 5924 | OPC_SwitchField, 47, 1, // 11711: switch Inst[47] { |
| 5925 | 0, 20, // 11714: case 0x0: { |
| 5926 | OPC_CheckField, 0, 16, 0, // 11716: check Inst[15:0] == 0x0 |
| 5927 | OPC_Scope, 9, // 11720: try { |
| 5928 | OPC_CheckField, 48, 4, 0, // 11722: check Inst[51:48] == 0x0 |
| 5929 | OPC_Decode, 132, 60, 162, 1, // 11726: decode to VGTviz using decoder 162 |
| 5930 | // 11726: } else try { |
| 5931 | OPC_Decode, 138, 60, 163, 1, // 11731: decode to VGTvizm using decoder 163 |
| 5932 | // 11731: } |
| 5933 | // 11731: } |
| 5934 | 1, 0, // 11736: case 0x1: { |
| 5935 | OPC_CheckField, 0, 16, 0, // 11738: check Inst[15:0] == 0x0 |
| 5936 | OPC_Scope, 9, // 11742: try { |
| 5937 | OPC_CheckField, 48, 4, 0, // 11744: check Inst[51:48] == 0x0 |
| 5938 | OPC_Decode, 156, 60, 164, 1, // 11748: decode to VGTvrz using decoder 164 |
| 5939 | // 11748: } else try { |
| 5940 | OPC_Decode, 162, 60, 165, 1, // 11753: decode to VGTvrzm using decoder 165 |
| 5941 | // 11753: } |
| 5942 | // 11753: } |
| 5943 | // 11753: } // switch Inst[47] |
| 5944 | // 11753: } |
| 5945 | 1, 0, // 11758: case 0x1: { |
| 5946 | OPC_SwitchField, 47, 1, // 11760: switch Inst[47] { |
| 5947 | 0, 20, // 11763: case 0x0: { |
| 5948 | OPC_CheckField, 0, 16, 0, // 11765: check Inst[15:0] == 0x0 |
| 5949 | OPC_Scope, 9, // 11769: try { |
| 5950 | OPC_CheckField, 48, 4, 0, // 11771: check Inst[51:48] == 0x0 |
| 5951 | OPC_Decode, 248, 59, 166, 1, // 11775: decode to VGTvir using decoder 166 |
| 5952 | // 11775: } else try { |
| 5953 | OPC_Decode, 254, 59, 167, 1, // 11780: decode to VGTvirm using decoder 167 |
| 5954 | // 11780: } |
| 5955 | // 11780: } |
| 5956 | 1, 0, // 11785: case 0x1: { |
| 5957 | OPC_CheckField, 0, 16, 0, // 11787: check Inst[15:0] == 0x0 |
| 5958 | OPC_Scope, 9, // 11791: try { |
| 5959 | OPC_CheckField, 48, 4, 0, // 11793: check Inst[51:48] == 0x0 |
| 5960 | OPC_Decode, 144, 60, 168, 1, // 11797: decode to VGTvrr using decoder 168 |
| 5961 | // 11797: } else try { |
| 5962 | OPC_Decode, 150, 60, 169, 1, // 11802: decode to VGTvrrm using decoder 169 |
| 5963 | // 11802: } |
| 5964 | // 11802: } |
| 5965 | // 11802: } // switch Inst[47] |
| 5966 | // 11802: } |
| 5967 | // 11802: } // switch Inst[39] |
| 5968 | // 11802: } |
| 5969 | 6, 0, // 11807: case 0x6: { |
| 5970 | OPC_SwitchField, 39, 1, // 11809: switch Inst[39] { |
| 5971 | 0, 47, // 11812: case 0x0: { |
| 5972 | OPC_SwitchField, 47, 1, // 11814: switch Inst[47] { |
| 5973 | 0, 20, // 11817: case 0x0: { |
| 5974 | OPC_CheckField, 7, 17, 0, // 11819: check Inst[23:7] == 0x0 |
| 5975 | OPC_Scope, 9, // 11823: try { |
| 5976 | OPC_CheckField, 48, 4, 0, // 11825: check Inst[51:48] == 0x0 |
| 5977 | OPC_Decode, 212, 59, 170, 1, // 11829: decode to VGTsiz using decoder 170 |
| 5978 | // 11829: } else try { |
| 5979 | OPC_Decode, 218, 59, 171, 1, // 11834: decode to VGTsizm using decoder 171 |
| 5980 | // 11834: } |
| 5981 | // 11834: } |
| 5982 | 1, 0, // 11839: case 0x1: { |
| 5983 | OPC_CheckField, 7, 17, 0, // 11841: check Inst[23:7] == 0x0 |
| 5984 | OPC_Scope, 9, // 11845: try { |
| 5985 | OPC_CheckField, 48, 4, 0, // 11847: check Inst[51:48] == 0x0 |
| 5986 | OPC_Decode, 236, 59, 172, 1, // 11851: decode to VGTsrz using decoder 172 |
| 5987 | // 11851: } else try { |
| 5988 | OPC_Decode, 242, 59, 173, 1, // 11856: decode to VGTsrzm using decoder 173 |
| 5989 | // 11856: } |
| 5990 | // 11856: } |
| 5991 | // 11856: } // switch Inst[47] |
| 5992 | // 11856: } |
| 5993 | 1, 0, // 11861: case 0x1: { |
| 5994 | OPC_SwitchField, 47, 1, // 11863: switch Inst[47] { |
| 5995 | 0, 20, // 11866: case 0x0: { |
| 5996 | OPC_CheckField, 7, 17, 0, // 11868: check Inst[23:7] == 0x0 |
| 5997 | OPC_Scope, 9, // 11872: try { |
| 5998 | OPC_CheckField, 48, 4, 0, // 11874: check Inst[51:48] == 0x0 |
| 5999 | OPC_Decode, 200, 59, 174, 1, // 11878: decode to VGTsir using decoder 174 |
| 6000 | // 11878: } else try { |
| 6001 | OPC_Decode, 206, 59, 175, 1, // 11883: decode to VGTsirm using decoder 175 |
| 6002 | // 11883: } |
| 6003 | // 11883: } |
| 6004 | 1, 0, // 11888: case 0x1: { |
| 6005 | OPC_CheckField, 7, 17, 0, // 11890: check Inst[23:7] == 0x0 |
| 6006 | OPC_Scope, 9, // 11894: try { |
| 6007 | OPC_CheckField, 48, 4, 0, // 11896: check Inst[51:48] == 0x0 |
| 6008 | OPC_Decode, 224, 59, 176, 1, // 11900: decode to VGTsrr using decoder 176 |
| 6009 | // 11900: } else try { |
| 6010 | OPC_Decode, 230, 59, 177, 1, // 11905: decode to VGTsrrm using decoder 177 |
| 6011 | // 11905: } |
| 6012 | // 11905: } |
| 6013 | // 11905: } // switch Inst[47] |
| 6014 | // 11905: } |
| 6015 | // 11905: } // switch Inst[39] |
| 6016 | // 11905: } |
| 6017 | // 11905: } // switch Inst[54:52] |
| 6018 | // 11905: } |
| 6019 | 196, 2, 159, 3, // 11910: case 0x144: { |
| 6020 | OPC_SwitchField, 52, 3, // 11914: switch Inst[54:52] { |
| 6021 | 0, 101, // 11917: case 0x0: { |
| 6022 | OPC_SwitchField, 39, 1, // 11919: switch Inst[39] { |
| 6023 | 0, 47, // 11922: case 0x0: { |
| 6024 | OPC_SwitchField, 47, 1, // 11924: switch Inst[47] { |
| 6025 | 0, 20, // 11927: case 0x0: { |
| 6026 | OPC_CheckField, 0, 16, 0, // 11929: check Inst[15:0] == 0x0 |
| 6027 | OPC_Scope, 9, // 11933: try { |
| 6028 | OPC_CheckField, 48, 4, 0, // 11935: check Inst[51:48] == 0x0 |
| 6029 | OPC_Decode, 196, 58, 162, 1, // 11939: decode to VGTUNCviz using decoder 162 |
| 6030 | // 11939: } else try { |
| 6031 | OPC_Decode, 202, 58, 163, 1, // 11944: decode to VGTUNCvizm using decoder 163 |
| 6032 | // 11944: } |
| 6033 | // 11944: } |
| 6034 | 1, 0, // 11949: case 0x1: { |
| 6035 | OPC_CheckField, 0, 16, 0, // 11951: check Inst[15:0] == 0x0 |
| 6036 | OPC_Scope, 9, // 11955: try { |
| 6037 | OPC_CheckField, 48, 4, 0, // 11957: check Inst[51:48] == 0x0 |
| 6038 | OPC_Decode, 220, 58, 164, 1, // 11961: decode to VGTUNCvrz using decoder 164 |
| 6039 | // 11961: } else try { |
| 6040 | OPC_Decode, 226, 58, 165, 1, // 11966: decode to VGTUNCvrzm using decoder 165 |
| 6041 | // 11966: } |
| 6042 | // 11966: } |
| 6043 | // 11966: } // switch Inst[47] |
| 6044 | // 11966: } |
| 6045 | 1, 0, // 11971: case 0x1: { |
| 6046 | OPC_SwitchField, 47, 1, // 11973: switch Inst[47] { |
| 6047 | 0, 20, // 11976: case 0x0: { |
| 6048 | OPC_CheckField, 0, 16, 0, // 11978: check Inst[15:0] == 0x0 |
| 6049 | OPC_Scope, 9, // 11982: try { |
| 6050 | OPC_CheckField, 48, 4, 0, // 11984: check Inst[51:48] == 0x0 |
| 6051 | OPC_Decode, 184, 58, 166, 1, // 11988: decode to VGTUNCvir using decoder 166 |
| 6052 | // 11988: } else try { |
| 6053 | OPC_Decode, 190, 58, 167, 1, // 11993: decode to VGTUNCvirm using decoder 167 |
| 6054 | // 11993: } |
| 6055 | // 11993: } |
| 6056 | 1, 0, // 11998: case 0x1: { |
| 6057 | OPC_CheckField, 0, 16, 0, // 12000: check Inst[15:0] == 0x0 |
| 6058 | OPC_Scope, 9, // 12004: try { |
| 6059 | OPC_CheckField, 48, 4, 0, // 12006: check Inst[51:48] == 0x0 |
| 6060 | OPC_Decode, 208, 58, 168, 1, // 12010: decode to VGTUNCvrr using decoder 168 |
| 6061 | // 12010: } else try { |
| 6062 | OPC_Decode, 214, 58, 169, 1, // 12015: decode to VGTUNCvrrm using decoder 169 |
| 6063 | // 12015: } |
| 6064 | // 12015: } |
| 6065 | // 12015: } // switch Inst[47] |
| 6066 | // 12015: } |
| 6067 | // 12015: } // switch Inst[39] |
| 6068 | // 12015: } |
| 6069 | 2, 101, // 12020: case 0x2: { |
| 6070 | OPC_SwitchField, 39, 1, // 12022: switch Inst[39] { |
| 6071 | 0, 47, // 12025: case 0x0: { |
| 6072 | OPC_SwitchField, 47, 1, // 12027: switch Inst[47] { |
| 6073 | 0, 20, // 12030: case 0x0: { |
| 6074 | OPC_CheckField, 7, 17, 0, // 12032: check Inst[23:7] == 0x0 |
| 6075 | OPC_Scope, 9, // 12036: try { |
| 6076 | OPC_CheckField, 48, 4, 0, // 12038: check Inst[51:48] == 0x0 |
| 6077 | OPC_Decode, 148, 58, 170, 1, // 12042: decode to VGTUNCsiz using decoder 170 |
| 6078 | // 12042: } else try { |
| 6079 | OPC_Decode, 154, 58, 171, 1, // 12047: decode to VGTUNCsizm using decoder 171 |
| 6080 | // 12047: } |
| 6081 | // 12047: } |
| 6082 | 1, 0, // 12052: case 0x1: { |
| 6083 | OPC_CheckField, 7, 17, 0, // 12054: check Inst[23:7] == 0x0 |
| 6084 | OPC_Scope, 9, // 12058: try { |
| 6085 | OPC_CheckField, 48, 4, 0, // 12060: check Inst[51:48] == 0x0 |
| 6086 | OPC_Decode, 172, 58, 172, 1, // 12064: decode to VGTUNCsrz using decoder 172 |
| 6087 | // 12064: } else try { |
| 6088 | OPC_Decode, 178, 58, 173, 1, // 12069: decode to VGTUNCsrzm using decoder 173 |
| 6089 | // 12069: } |
| 6090 | // 12069: } |
| 6091 | // 12069: } // switch Inst[47] |
| 6092 | // 12069: } |
| 6093 | 1, 0, // 12074: case 0x1: { |
| 6094 | OPC_SwitchField, 47, 1, // 12076: switch Inst[47] { |
| 6095 | 0, 20, // 12079: case 0x0: { |
| 6096 | OPC_CheckField, 7, 17, 0, // 12081: check Inst[23:7] == 0x0 |
| 6097 | OPC_Scope, 9, // 12085: try { |
| 6098 | OPC_CheckField, 48, 4, 0, // 12087: check Inst[51:48] == 0x0 |
| 6099 | OPC_Decode, 136, 58, 174, 1, // 12091: decode to VGTUNCsir using decoder 174 |
| 6100 | // 12091: } else try { |
| 6101 | OPC_Decode, 142, 58, 175, 1, // 12096: decode to VGTUNCsirm using decoder 175 |
| 6102 | // 12096: } |
| 6103 | // 12096: } |
| 6104 | 1, 0, // 12101: case 0x1: { |
| 6105 | OPC_CheckField, 7, 17, 0, // 12103: check Inst[23:7] == 0x0 |
| 6106 | OPC_Scope, 9, // 12107: try { |
| 6107 | OPC_CheckField, 48, 4, 0, // 12109: check Inst[51:48] == 0x0 |
| 6108 | OPC_Decode, 160, 58, 176, 1, // 12113: decode to VGTUNCsrr using decoder 176 |
| 6109 | // 12113: } else try { |
| 6110 | OPC_Decode, 166, 58, 177, 1, // 12118: decode to VGTUNCsrrm using decoder 177 |
| 6111 | // 12118: } |
| 6112 | // 12118: } |
| 6113 | // 12118: } // switch Inst[47] |
| 6114 | // 12118: } |
| 6115 | // 12118: } // switch Inst[39] |
| 6116 | // 12118: } |
| 6117 | 4, 101, // 12123: case 0x4: { |
| 6118 | OPC_SwitchField, 39, 1, // 12125: switch Inst[39] { |
| 6119 | 0, 47, // 12128: case 0x0: { |
| 6120 | OPC_SwitchField, 47, 1, // 12130: switch Inst[47] { |
| 6121 | 0, 20, // 12133: case 0x0: { |
| 6122 | OPC_CheckField, 0, 16, 0, // 12135: check Inst[15:0] == 0x0 |
| 6123 | OPC_Scope, 9, // 12139: try { |
| 6124 | OPC_CheckField, 48, 4, 0, // 12141: check Inst[51:48] == 0x0 |
| 6125 | OPC_Decode, 164, 59, 162, 1, // 12145: decode to VGTUviz using decoder 162 |
| 6126 | // 12145: } else try { |
| 6127 | OPC_Decode, 170, 59, 163, 1, // 12150: decode to VGTUvizm using decoder 163 |
| 6128 | // 12150: } |
| 6129 | // 12150: } |
| 6130 | 1, 0, // 12155: case 0x1: { |
| 6131 | OPC_CheckField, 0, 16, 0, // 12157: check Inst[15:0] == 0x0 |
| 6132 | OPC_Scope, 9, // 12161: try { |
| 6133 | OPC_CheckField, 48, 4, 0, // 12163: check Inst[51:48] == 0x0 |
| 6134 | OPC_Decode, 188, 59, 164, 1, // 12167: decode to VGTUvrz using decoder 164 |
| 6135 | // 12167: } else try { |
| 6136 | OPC_Decode, 194, 59, 165, 1, // 12172: decode to VGTUvrzm using decoder 165 |
| 6137 | // 12172: } |
| 6138 | // 12172: } |
| 6139 | // 12172: } // switch Inst[47] |
| 6140 | // 12172: } |
| 6141 | 1, 0, // 12177: case 0x1: { |
| 6142 | OPC_SwitchField, 47, 1, // 12179: switch Inst[47] { |
| 6143 | 0, 20, // 12182: case 0x0: { |
| 6144 | OPC_CheckField, 0, 16, 0, // 12184: check Inst[15:0] == 0x0 |
| 6145 | OPC_Scope, 9, // 12188: try { |
| 6146 | OPC_CheckField, 48, 4, 0, // 12190: check Inst[51:48] == 0x0 |
| 6147 | OPC_Decode, 152, 59, 166, 1, // 12194: decode to VGTUvir using decoder 166 |
| 6148 | // 12194: } else try { |
| 6149 | OPC_Decode, 158, 59, 167, 1, // 12199: decode to VGTUvirm using decoder 167 |
| 6150 | // 12199: } |
| 6151 | // 12199: } |
| 6152 | 1, 0, // 12204: case 0x1: { |
| 6153 | OPC_CheckField, 0, 16, 0, // 12206: check Inst[15:0] == 0x0 |
| 6154 | OPC_Scope, 9, // 12210: try { |
| 6155 | OPC_CheckField, 48, 4, 0, // 12212: check Inst[51:48] == 0x0 |
| 6156 | OPC_Decode, 176, 59, 168, 1, // 12216: decode to VGTUvrr using decoder 168 |
| 6157 | // 12216: } else try { |
| 6158 | OPC_Decode, 182, 59, 169, 1, // 12221: decode to VGTUvrrm using decoder 169 |
| 6159 | // 12221: } |
| 6160 | // 12221: } |
| 6161 | // 12221: } // switch Inst[47] |
| 6162 | // 12221: } |
| 6163 | // 12221: } // switch Inst[39] |
| 6164 | // 12221: } |
| 6165 | 6, 0, // 12226: case 0x6: { |
| 6166 | OPC_SwitchField, 39, 1, // 12228: switch Inst[39] { |
| 6167 | 0, 47, // 12231: case 0x0: { |
| 6168 | OPC_SwitchField, 47, 1, // 12233: switch Inst[47] { |
| 6169 | 0, 20, // 12236: case 0x0: { |
| 6170 | OPC_CheckField, 7, 17, 0, // 12238: check Inst[23:7] == 0x0 |
| 6171 | OPC_Scope, 9, // 12242: try { |
| 6172 | OPC_CheckField, 48, 4, 0, // 12244: check Inst[51:48] == 0x0 |
| 6173 | OPC_Decode, 244, 58, 170, 1, // 12248: decode to VGTUsiz using decoder 170 |
| 6174 | // 12248: } else try { |
| 6175 | OPC_Decode, 250, 58, 171, 1, // 12253: decode to VGTUsizm using decoder 171 |
| 6176 | // 12253: } |
| 6177 | // 12253: } |
| 6178 | 1, 0, // 12258: case 0x1: { |
| 6179 | OPC_CheckField, 7, 17, 0, // 12260: check Inst[23:7] == 0x0 |
| 6180 | OPC_Scope, 9, // 12264: try { |
| 6181 | OPC_CheckField, 48, 4, 0, // 12266: check Inst[51:48] == 0x0 |
| 6182 | OPC_Decode, 140, 59, 172, 1, // 12270: decode to VGTUsrz using decoder 172 |
| 6183 | // 12270: } else try { |
| 6184 | OPC_Decode, 146, 59, 173, 1, // 12275: decode to VGTUsrzm using decoder 173 |
| 6185 | // 12275: } |
| 6186 | // 12275: } |
| 6187 | // 12275: } // switch Inst[47] |
| 6188 | // 12275: } |
| 6189 | 1, 0, // 12280: case 0x1: { |
| 6190 | OPC_SwitchField, 47, 1, // 12282: switch Inst[47] { |
| 6191 | 0, 20, // 12285: case 0x0: { |
| 6192 | OPC_CheckField, 7, 17, 0, // 12287: check Inst[23:7] == 0x0 |
| 6193 | OPC_Scope, 9, // 12291: try { |
| 6194 | OPC_CheckField, 48, 4, 0, // 12293: check Inst[51:48] == 0x0 |
| 6195 | OPC_Decode, 232, 58, 174, 1, // 12297: decode to VGTUsir using decoder 174 |
| 6196 | // 12297: } else try { |
| 6197 | OPC_Decode, 238, 58, 175, 1, // 12302: decode to VGTUsirm using decoder 175 |
| 6198 | // 12302: } |
| 6199 | // 12302: } |
| 6200 | 1, 0, // 12307: case 0x1: { |
| 6201 | OPC_CheckField, 7, 17, 0, // 12309: check Inst[23:7] == 0x0 |
| 6202 | OPC_Scope, 9, // 12313: try { |
| 6203 | OPC_CheckField, 48, 4, 0, // 12315: check Inst[51:48] == 0x0 |
| 6204 | OPC_Decode, 128, 59, 176, 1, // 12319: decode to VGTUsrr using decoder 176 |
| 6205 | // 12319: } else try { |
| 6206 | OPC_Decode, 134, 59, 177, 1, // 12324: decode to VGTUsrrm using decoder 177 |
| 6207 | // 12324: } |
| 6208 | // 12324: } |
| 6209 | // 12324: } // switch Inst[47] |
| 6210 | // 12324: } |
| 6211 | // 12324: } // switch Inst[39] |
| 6212 | // 12324: } |
| 6213 | // 12324: } // switch Inst[54:52] |
| 6214 | // 12324: } |
| 6215 | 198, 2, 159, 3, // 12329: case 0x146: { |
| 6216 | OPC_SwitchField, 52, 3, // 12333: switch Inst[54:52] { |
| 6217 | 0, 101, // 12336: case 0x0: { |
| 6218 | OPC_SwitchField, 39, 1, // 12338: switch Inst[39] { |
| 6219 | 0, 47, // 12341: case 0x0: { |
| 6220 | OPC_SwitchField, 47, 1, // 12343: switch Inst[47] { |
| 6221 | 0, 20, // 12346: case 0x0: { |
| 6222 | OPC_CheckField, 0, 16, 0, // 12348: check Inst[15:0] == 0x0 |
| 6223 | OPC_Scope, 9, // 12352: try { |
| 6224 | OPC_CheckField, 48, 4, 0, // 12354: check Inst[51:48] == 0x0 |
| 6225 | OPC_Decode, 228, 54, 162, 1, // 12358: decode to VGTLSXNCviz using decoder 162 |
| 6226 | // 12358: } else try { |
| 6227 | OPC_Decode, 234, 54, 163, 1, // 12363: decode to VGTLSXNCvizm using decoder 163 |
| 6228 | // 12363: } |
| 6229 | // 12363: } |
| 6230 | 1, 0, // 12368: case 0x1: { |
| 6231 | OPC_CheckField, 0, 16, 0, // 12370: check Inst[15:0] == 0x0 |
| 6232 | OPC_Scope, 9, // 12374: try { |
| 6233 | OPC_CheckField, 48, 4, 0, // 12376: check Inst[51:48] == 0x0 |
| 6234 | OPC_Decode, 252, 54, 164, 1, // 12380: decode to VGTLSXNCvrz using decoder 164 |
| 6235 | // 12380: } else try { |
| 6236 | OPC_Decode, 130, 55, 165, 1, // 12385: decode to VGTLSXNCvrzm using decoder 165 |
| 6237 | // 12385: } |
| 6238 | // 12385: } |
| 6239 | // 12385: } // switch Inst[47] |
| 6240 | // 12385: } |
| 6241 | 1, 0, // 12390: case 0x1: { |
| 6242 | OPC_SwitchField, 47, 1, // 12392: switch Inst[47] { |
| 6243 | 0, 20, // 12395: case 0x0: { |
| 6244 | OPC_CheckField, 0, 16, 0, // 12397: check Inst[15:0] == 0x0 |
| 6245 | OPC_Scope, 9, // 12401: try { |
| 6246 | OPC_CheckField, 48, 4, 0, // 12403: check Inst[51:48] == 0x0 |
| 6247 | OPC_Decode, 216, 54, 166, 1, // 12407: decode to VGTLSXNCvir using decoder 166 |
| 6248 | // 12407: } else try { |
| 6249 | OPC_Decode, 222, 54, 167, 1, // 12412: decode to VGTLSXNCvirm using decoder 167 |
| 6250 | // 12412: } |
| 6251 | // 12412: } |
| 6252 | 1, 0, // 12417: case 0x1: { |
| 6253 | OPC_CheckField, 0, 16, 0, // 12419: check Inst[15:0] == 0x0 |
| 6254 | OPC_Scope, 9, // 12423: try { |
| 6255 | OPC_CheckField, 48, 4, 0, // 12425: check Inst[51:48] == 0x0 |
| 6256 | OPC_Decode, 240, 54, 168, 1, // 12429: decode to VGTLSXNCvrr using decoder 168 |
| 6257 | // 12429: } else try { |
| 6258 | OPC_Decode, 246, 54, 169, 1, // 12434: decode to VGTLSXNCvrrm using decoder 169 |
| 6259 | // 12434: } |
| 6260 | // 12434: } |
| 6261 | // 12434: } // switch Inst[47] |
| 6262 | // 12434: } |
| 6263 | // 12434: } // switch Inst[39] |
| 6264 | // 12434: } |
| 6265 | 2, 101, // 12439: case 0x2: { |
| 6266 | OPC_SwitchField, 39, 1, // 12441: switch Inst[39] { |
| 6267 | 0, 47, // 12444: case 0x0: { |
| 6268 | OPC_SwitchField, 47, 1, // 12446: switch Inst[47] { |
| 6269 | 0, 20, // 12449: case 0x0: { |
| 6270 | OPC_CheckField, 7, 17, 0, // 12451: check Inst[23:7] == 0x0 |
| 6271 | OPC_Scope, 9, // 12455: try { |
| 6272 | OPC_CheckField, 48, 4, 0, // 12457: check Inst[51:48] == 0x0 |
| 6273 | OPC_Decode, 180, 54, 170, 1, // 12461: decode to VGTLSXNCsiz using decoder 170 |
| 6274 | // 12461: } else try { |
| 6275 | OPC_Decode, 186, 54, 171, 1, // 12466: decode to VGTLSXNCsizm using decoder 171 |
| 6276 | // 12466: } |
| 6277 | // 12466: } |
| 6278 | 1, 0, // 12471: case 0x1: { |
| 6279 | OPC_CheckField, 7, 17, 0, // 12473: check Inst[23:7] == 0x0 |
| 6280 | OPC_Scope, 9, // 12477: try { |
| 6281 | OPC_CheckField, 48, 4, 0, // 12479: check Inst[51:48] == 0x0 |
| 6282 | OPC_Decode, 204, 54, 172, 1, // 12483: decode to VGTLSXNCsrz using decoder 172 |
| 6283 | // 12483: } else try { |
| 6284 | OPC_Decode, 210, 54, 173, 1, // 12488: decode to VGTLSXNCsrzm using decoder 173 |
| 6285 | // 12488: } |
| 6286 | // 12488: } |
| 6287 | // 12488: } // switch Inst[47] |
| 6288 | // 12488: } |
| 6289 | 1, 0, // 12493: case 0x1: { |
| 6290 | OPC_SwitchField, 47, 1, // 12495: switch Inst[47] { |
| 6291 | 0, 20, // 12498: case 0x0: { |
| 6292 | OPC_CheckField, 7, 17, 0, // 12500: check Inst[23:7] == 0x0 |
| 6293 | OPC_Scope, 9, // 12504: try { |
| 6294 | OPC_CheckField, 48, 4, 0, // 12506: check Inst[51:48] == 0x0 |
| 6295 | OPC_Decode, 168, 54, 174, 1, // 12510: decode to VGTLSXNCsir using decoder 174 |
| 6296 | // 12510: } else try { |
| 6297 | OPC_Decode, 174, 54, 175, 1, // 12515: decode to VGTLSXNCsirm using decoder 175 |
| 6298 | // 12515: } |
| 6299 | // 12515: } |
| 6300 | 1, 0, // 12520: case 0x1: { |
| 6301 | OPC_CheckField, 7, 17, 0, // 12522: check Inst[23:7] == 0x0 |
| 6302 | OPC_Scope, 9, // 12526: try { |
| 6303 | OPC_CheckField, 48, 4, 0, // 12528: check Inst[51:48] == 0x0 |
| 6304 | OPC_Decode, 192, 54, 176, 1, // 12532: decode to VGTLSXNCsrr using decoder 176 |
| 6305 | // 12532: } else try { |
| 6306 | OPC_Decode, 198, 54, 177, 1, // 12537: decode to VGTLSXNCsrrm using decoder 177 |
| 6307 | // 12537: } |
| 6308 | // 12537: } |
| 6309 | // 12537: } // switch Inst[47] |
| 6310 | // 12537: } |
| 6311 | // 12537: } // switch Inst[39] |
| 6312 | // 12537: } |
| 6313 | 4, 101, // 12542: case 0x4: { |
| 6314 | OPC_SwitchField, 39, 1, // 12544: switch Inst[39] { |
| 6315 | 0, 47, // 12547: case 0x0: { |
| 6316 | OPC_SwitchField, 47, 1, // 12549: switch Inst[47] { |
| 6317 | 0, 20, // 12552: case 0x0: { |
| 6318 | OPC_CheckField, 0, 16, 0, // 12554: check Inst[15:0] == 0x0 |
| 6319 | OPC_Scope, 9, // 12558: try { |
| 6320 | OPC_CheckField, 48, 4, 0, // 12560: check Inst[51:48] == 0x0 |
| 6321 | OPC_Decode, 196, 55, 162, 1, // 12564: decode to VGTLSXviz using decoder 162 |
| 6322 | // 12564: } else try { |
| 6323 | OPC_Decode, 202, 55, 163, 1, // 12569: decode to VGTLSXvizm using decoder 163 |
| 6324 | // 12569: } |
| 6325 | // 12569: } |
| 6326 | 1, 0, // 12574: case 0x1: { |
| 6327 | OPC_CheckField, 0, 16, 0, // 12576: check Inst[15:0] == 0x0 |
| 6328 | OPC_Scope, 9, // 12580: try { |
| 6329 | OPC_CheckField, 48, 4, 0, // 12582: check Inst[51:48] == 0x0 |
| 6330 | OPC_Decode, 220, 55, 164, 1, // 12586: decode to VGTLSXvrz using decoder 164 |
| 6331 | // 12586: } else try { |
| 6332 | OPC_Decode, 226, 55, 165, 1, // 12591: decode to VGTLSXvrzm using decoder 165 |
| 6333 | // 12591: } |
| 6334 | // 12591: } |
| 6335 | // 12591: } // switch Inst[47] |
| 6336 | // 12591: } |
| 6337 | 1, 0, // 12596: case 0x1: { |
| 6338 | OPC_SwitchField, 47, 1, // 12598: switch Inst[47] { |
| 6339 | 0, 20, // 12601: case 0x0: { |
| 6340 | OPC_CheckField, 0, 16, 0, // 12603: check Inst[15:0] == 0x0 |
| 6341 | OPC_Scope, 9, // 12607: try { |
| 6342 | OPC_CheckField, 48, 4, 0, // 12609: check Inst[51:48] == 0x0 |
| 6343 | OPC_Decode, 184, 55, 166, 1, // 12613: decode to VGTLSXvir using decoder 166 |
| 6344 | // 12613: } else try { |
| 6345 | OPC_Decode, 190, 55, 167, 1, // 12618: decode to VGTLSXvirm using decoder 167 |
| 6346 | // 12618: } |
| 6347 | // 12618: } |
| 6348 | 1, 0, // 12623: case 0x1: { |
| 6349 | OPC_CheckField, 0, 16, 0, // 12625: check Inst[15:0] == 0x0 |
| 6350 | OPC_Scope, 9, // 12629: try { |
| 6351 | OPC_CheckField, 48, 4, 0, // 12631: check Inst[51:48] == 0x0 |
| 6352 | OPC_Decode, 208, 55, 168, 1, // 12635: decode to VGTLSXvrr using decoder 168 |
| 6353 | // 12635: } else try { |
| 6354 | OPC_Decode, 214, 55, 169, 1, // 12640: decode to VGTLSXvrrm using decoder 169 |
| 6355 | // 12640: } |
| 6356 | // 12640: } |
| 6357 | // 12640: } // switch Inst[47] |
| 6358 | // 12640: } |
| 6359 | // 12640: } // switch Inst[39] |
| 6360 | // 12640: } |
| 6361 | 6, 0, // 12645: case 0x6: { |
| 6362 | OPC_SwitchField, 39, 1, // 12647: switch Inst[39] { |
| 6363 | 0, 47, // 12650: case 0x0: { |
| 6364 | OPC_SwitchField, 47, 1, // 12652: switch Inst[47] { |
| 6365 | 0, 20, // 12655: case 0x0: { |
| 6366 | OPC_CheckField, 7, 17, 0, // 12657: check Inst[23:7] == 0x0 |
| 6367 | OPC_Scope, 9, // 12661: try { |
| 6368 | OPC_CheckField, 48, 4, 0, // 12663: check Inst[51:48] == 0x0 |
| 6369 | OPC_Decode, 148, 55, 170, 1, // 12667: decode to VGTLSXsiz using decoder 170 |
| 6370 | // 12667: } else try { |
| 6371 | OPC_Decode, 154, 55, 171, 1, // 12672: decode to VGTLSXsizm using decoder 171 |
| 6372 | // 12672: } |
| 6373 | // 12672: } |
| 6374 | 1, 0, // 12677: case 0x1: { |
| 6375 | OPC_CheckField, 7, 17, 0, // 12679: check Inst[23:7] == 0x0 |
| 6376 | OPC_Scope, 9, // 12683: try { |
| 6377 | OPC_CheckField, 48, 4, 0, // 12685: check Inst[51:48] == 0x0 |
| 6378 | OPC_Decode, 172, 55, 172, 1, // 12689: decode to VGTLSXsrz using decoder 172 |
| 6379 | // 12689: } else try { |
| 6380 | OPC_Decode, 178, 55, 173, 1, // 12694: decode to VGTLSXsrzm using decoder 173 |
| 6381 | // 12694: } |
| 6382 | // 12694: } |
| 6383 | // 12694: } // switch Inst[47] |
| 6384 | // 12694: } |
| 6385 | 1, 0, // 12699: case 0x1: { |
| 6386 | OPC_SwitchField, 47, 1, // 12701: switch Inst[47] { |
| 6387 | 0, 20, // 12704: case 0x0: { |
| 6388 | OPC_CheckField, 7, 17, 0, // 12706: check Inst[23:7] == 0x0 |
| 6389 | OPC_Scope, 9, // 12710: try { |
| 6390 | OPC_CheckField, 48, 4, 0, // 12712: check Inst[51:48] == 0x0 |
| 6391 | OPC_Decode, 136, 55, 174, 1, // 12716: decode to VGTLSXsir using decoder 174 |
| 6392 | // 12716: } else try { |
| 6393 | OPC_Decode, 142, 55, 175, 1, // 12721: decode to VGTLSXsirm using decoder 175 |
| 6394 | // 12721: } |
| 6395 | // 12721: } |
| 6396 | 1, 0, // 12726: case 0x1: { |
| 6397 | OPC_CheckField, 7, 17, 0, // 12728: check Inst[23:7] == 0x0 |
| 6398 | OPC_Scope, 9, // 12732: try { |
| 6399 | OPC_CheckField, 48, 4, 0, // 12734: check Inst[51:48] == 0x0 |
| 6400 | OPC_Decode, 160, 55, 176, 1, // 12738: decode to VGTLSXsrr using decoder 176 |
| 6401 | // 12738: } else try { |
| 6402 | OPC_Decode, 166, 55, 177, 1, // 12743: decode to VGTLSXsrrm using decoder 177 |
| 6403 | // 12743: } |
| 6404 | // 12743: } |
| 6405 | // 12743: } // switch Inst[47] |
| 6406 | // 12743: } |
| 6407 | // 12743: } // switch Inst[39] |
| 6408 | // 12743: } |
| 6409 | // 12743: } // switch Inst[54:52] |
| 6410 | // 12743: } |
| 6411 | 199, 2, 159, 3, // 12748: case 0x147: { |
| 6412 | OPC_SwitchField, 52, 3, // 12752: switch Inst[54:52] { |
| 6413 | 0, 101, // 12755: case 0x0: { |
| 6414 | OPC_SwitchField, 39, 1, // 12757: switch Inst[39] { |
| 6415 | 0, 47, // 12760: case 0x0: { |
| 6416 | OPC_SwitchField, 47, 1, // 12762: switch Inst[47] { |
| 6417 | 0, 20, // 12765: case 0x0: { |
| 6418 | OPC_CheckField, 0, 16, 0, // 12767: check Inst[15:0] == 0x0 |
| 6419 | OPC_Scope, 9, // 12771: try { |
| 6420 | OPC_CheckField, 48, 4, 0, // 12773: check Inst[51:48] == 0x0 |
| 6421 | OPC_Decode, 164, 56, 162, 1, // 12777: decode to VGTLZXNCviz using decoder 162 |
| 6422 | // 12777: } else try { |
| 6423 | OPC_Decode, 170, 56, 163, 1, // 12782: decode to VGTLZXNCvizm using decoder 163 |
| 6424 | // 12782: } |
| 6425 | // 12782: } |
| 6426 | 1, 0, // 12787: case 0x1: { |
| 6427 | OPC_CheckField, 0, 16, 0, // 12789: check Inst[15:0] == 0x0 |
| 6428 | OPC_Scope, 9, // 12793: try { |
| 6429 | OPC_CheckField, 48, 4, 0, // 12795: check Inst[51:48] == 0x0 |
| 6430 | OPC_Decode, 188, 56, 164, 1, // 12799: decode to VGTLZXNCvrz using decoder 164 |
| 6431 | // 12799: } else try { |
| 6432 | OPC_Decode, 194, 56, 165, 1, // 12804: decode to VGTLZXNCvrzm using decoder 165 |
| 6433 | // 12804: } |
| 6434 | // 12804: } |
| 6435 | // 12804: } // switch Inst[47] |
| 6436 | // 12804: } |
| 6437 | 1, 0, // 12809: case 0x1: { |
| 6438 | OPC_SwitchField, 47, 1, // 12811: switch Inst[47] { |
| 6439 | 0, 20, // 12814: case 0x0: { |
| 6440 | OPC_CheckField, 0, 16, 0, // 12816: check Inst[15:0] == 0x0 |
| 6441 | OPC_Scope, 9, // 12820: try { |
| 6442 | OPC_CheckField, 48, 4, 0, // 12822: check Inst[51:48] == 0x0 |
| 6443 | OPC_Decode, 152, 56, 166, 1, // 12826: decode to VGTLZXNCvir using decoder 166 |
| 6444 | // 12826: } else try { |
| 6445 | OPC_Decode, 158, 56, 167, 1, // 12831: decode to VGTLZXNCvirm using decoder 167 |
| 6446 | // 12831: } |
| 6447 | // 12831: } |
| 6448 | 1, 0, // 12836: case 0x1: { |
| 6449 | OPC_CheckField, 0, 16, 0, // 12838: check Inst[15:0] == 0x0 |
| 6450 | OPC_Scope, 9, // 12842: try { |
| 6451 | OPC_CheckField, 48, 4, 0, // 12844: check Inst[51:48] == 0x0 |
| 6452 | OPC_Decode, 176, 56, 168, 1, // 12848: decode to VGTLZXNCvrr using decoder 168 |
| 6453 | // 12848: } else try { |
| 6454 | OPC_Decode, 182, 56, 169, 1, // 12853: decode to VGTLZXNCvrrm using decoder 169 |
| 6455 | // 12853: } |
| 6456 | // 12853: } |
| 6457 | // 12853: } // switch Inst[47] |
| 6458 | // 12853: } |
| 6459 | // 12853: } // switch Inst[39] |
| 6460 | // 12853: } |
| 6461 | 2, 101, // 12858: case 0x2: { |
| 6462 | OPC_SwitchField, 39, 1, // 12860: switch Inst[39] { |
| 6463 | 0, 47, // 12863: case 0x0: { |
| 6464 | OPC_SwitchField, 47, 1, // 12865: switch Inst[47] { |
| 6465 | 0, 20, // 12868: case 0x0: { |
| 6466 | OPC_CheckField, 7, 17, 0, // 12870: check Inst[23:7] == 0x0 |
| 6467 | OPC_Scope, 9, // 12874: try { |
| 6468 | OPC_CheckField, 48, 4, 0, // 12876: check Inst[51:48] == 0x0 |
| 6469 | OPC_Decode, 244, 55, 170, 1, // 12880: decode to VGTLZXNCsiz using decoder 170 |
| 6470 | // 12880: } else try { |
| 6471 | OPC_Decode, 250, 55, 171, 1, // 12885: decode to VGTLZXNCsizm using decoder 171 |
| 6472 | // 12885: } |
| 6473 | // 12885: } |
| 6474 | 1, 0, // 12890: case 0x1: { |
| 6475 | OPC_CheckField, 7, 17, 0, // 12892: check Inst[23:7] == 0x0 |
| 6476 | OPC_Scope, 9, // 12896: try { |
| 6477 | OPC_CheckField, 48, 4, 0, // 12898: check Inst[51:48] == 0x0 |
| 6478 | OPC_Decode, 140, 56, 172, 1, // 12902: decode to VGTLZXNCsrz using decoder 172 |
| 6479 | // 12902: } else try { |
| 6480 | OPC_Decode, 146, 56, 173, 1, // 12907: decode to VGTLZXNCsrzm using decoder 173 |
| 6481 | // 12907: } |
| 6482 | // 12907: } |
| 6483 | // 12907: } // switch Inst[47] |
| 6484 | // 12907: } |
| 6485 | 1, 0, // 12912: case 0x1: { |
| 6486 | OPC_SwitchField, 47, 1, // 12914: switch Inst[47] { |
| 6487 | 0, 20, // 12917: case 0x0: { |
| 6488 | OPC_CheckField, 7, 17, 0, // 12919: check Inst[23:7] == 0x0 |
| 6489 | OPC_Scope, 9, // 12923: try { |
| 6490 | OPC_CheckField, 48, 4, 0, // 12925: check Inst[51:48] == 0x0 |
| 6491 | OPC_Decode, 232, 55, 174, 1, // 12929: decode to VGTLZXNCsir using decoder 174 |
| 6492 | // 12929: } else try { |
| 6493 | OPC_Decode, 238, 55, 175, 1, // 12934: decode to VGTLZXNCsirm using decoder 175 |
| 6494 | // 12934: } |
| 6495 | // 12934: } |
| 6496 | 1, 0, // 12939: case 0x1: { |
| 6497 | OPC_CheckField, 7, 17, 0, // 12941: check Inst[23:7] == 0x0 |
| 6498 | OPC_Scope, 9, // 12945: try { |
| 6499 | OPC_CheckField, 48, 4, 0, // 12947: check Inst[51:48] == 0x0 |
| 6500 | OPC_Decode, 128, 56, 176, 1, // 12951: decode to VGTLZXNCsrr using decoder 176 |
| 6501 | // 12951: } else try { |
| 6502 | OPC_Decode, 134, 56, 177, 1, // 12956: decode to VGTLZXNCsrrm using decoder 177 |
| 6503 | // 12956: } |
| 6504 | // 12956: } |
| 6505 | // 12956: } // switch Inst[47] |
| 6506 | // 12956: } |
| 6507 | // 12956: } // switch Inst[39] |
| 6508 | // 12956: } |
| 6509 | 4, 101, // 12961: case 0x4: { |
| 6510 | OPC_SwitchField, 39, 1, // 12963: switch Inst[39] { |
| 6511 | 0, 47, // 12966: case 0x0: { |
| 6512 | OPC_SwitchField, 47, 1, // 12968: switch Inst[47] { |
| 6513 | 0, 20, // 12971: case 0x0: { |
| 6514 | OPC_CheckField, 0, 16, 0, // 12973: check Inst[15:0] == 0x0 |
| 6515 | OPC_Scope, 9, // 12977: try { |
| 6516 | OPC_CheckField, 48, 4, 0, // 12979: check Inst[51:48] == 0x0 |
| 6517 | OPC_Decode, 132, 57, 162, 1, // 12983: decode to VGTLZXviz using decoder 162 |
| 6518 | // 12983: } else try { |
| 6519 | OPC_Decode, 138, 57, 163, 1, // 12988: decode to VGTLZXvizm using decoder 163 |
| 6520 | // 12988: } |
| 6521 | // 12988: } |
| 6522 | 1, 0, // 12993: case 0x1: { |
| 6523 | OPC_CheckField, 0, 16, 0, // 12995: check Inst[15:0] == 0x0 |
| 6524 | OPC_Scope, 9, // 12999: try { |
| 6525 | OPC_CheckField, 48, 4, 0, // 13001: check Inst[51:48] == 0x0 |
| 6526 | OPC_Decode, 156, 57, 164, 1, // 13005: decode to VGTLZXvrz using decoder 164 |
| 6527 | // 13005: } else try { |
| 6528 | OPC_Decode, 162, 57, 165, 1, // 13010: decode to VGTLZXvrzm using decoder 165 |
| 6529 | // 13010: } |
| 6530 | // 13010: } |
| 6531 | // 13010: } // switch Inst[47] |
| 6532 | // 13010: } |
| 6533 | 1, 0, // 13015: case 0x1: { |
| 6534 | OPC_SwitchField, 47, 1, // 13017: switch Inst[47] { |
| 6535 | 0, 20, // 13020: case 0x0: { |
| 6536 | OPC_CheckField, 0, 16, 0, // 13022: check Inst[15:0] == 0x0 |
| 6537 | OPC_Scope, 9, // 13026: try { |
| 6538 | OPC_CheckField, 48, 4, 0, // 13028: check Inst[51:48] == 0x0 |
| 6539 | OPC_Decode, 248, 56, 166, 1, // 13032: decode to VGTLZXvir using decoder 166 |
| 6540 | // 13032: } else try { |
| 6541 | OPC_Decode, 254, 56, 167, 1, // 13037: decode to VGTLZXvirm using decoder 167 |
| 6542 | // 13037: } |
| 6543 | // 13037: } |
| 6544 | 1, 0, // 13042: case 0x1: { |
| 6545 | OPC_CheckField, 0, 16, 0, // 13044: check Inst[15:0] == 0x0 |
| 6546 | OPC_Scope, 9, // 13048: try { |
| 6547 | OPC_CheckField, 48, 4, 0, // 13050: check Inst[51:48] == 0x0 |
| 6548 | OPC_Decode, 144, 57, 168, 1, // 13054: decode to VGTLZXvrr using decoder 168 |
| 6549 | // 13054: } else try { |
| 6550 | OPC_Decode, 150, 57, 169, 1, // 13059: decode to VGTLZXvrrm using decoder 169 |
| 6551 | // 13059: } |
| 6552 | // 13059: } |
| 6553 | // 13059: } // switch Inst[47] |
| 6554 | // 13059: } |
| 6555 | // 13059: } // switch Inst[39] |
| 6556 | // 13059: } |
| 6557 | 6, 0, // 13064: case 0x6: { |
| 6558 | OPC_SwitchField, 39, 1, // 13066: switch Inst[39] { |
| 6559 | 0, 47, // 13069: case 0x0: { |
| 6560 | OPC_SwitchField, 47, 1, // 13071: switch Inst[47] { |
| 6561 | 0, 20, // 13074: case 0x0: { |
| 6562 | OPC_CheckField, 7, 17, 0, // 13076: check Inst[23:7] == 0x0 |
| 6563 | OPC_Scope, 9, // 13080: try { |
| 6564 | OPC_CheckField, 48, 4, 0, // 13082: check Inst[51:48] == 0x0 |
| 6565 | OPC_Decode, 212, 56, 170, 1, // 13086: decode to VGTLZXsiz using decoder 170 |
| 6566 | // 13086: } else try { |
| 6567 | OPC_Decode, 218, 56, 171, 1, // 13091: decode to VGTLZXsizm using decoder 171 |
| 6568 | // 13091: } |
| 6569 | // 13091: } |
| 6570 | 1, 0, // 13096: case 0x1: { |
| 6571 | OPC_CheckField, 7, 17, 0, // 13098: check Inst[23:7] == 0x0 |
| 6572 | OPC_Scope, 9, // 13102: try { |
| 6573 | OPC_CheckField, 48, 4, 0, // 13104: check Inst[51:48] == 0x0 |
| 6574 | OPC_Decode, 236, 56, 172, 1, // 13108: decode to VGTLZXsrz using decoder 172 |
| 6575 | // 13108: } else try { |
| 6576 | OPC_Decode, 242, 56, 173, 1, // 13113: decode to VGTLZXsrzm using decoder 173 |
| 6577 | // 13113: } |
| 6578 | // 13113: } |
| 6579 | // 13113: } // switch Inst[47] |
| 6580 | // 13113: } |
| 6581 | 1, 0, // 13118: case 0x1: { |
| 6582 | OPC_SwitchField, 47, 1, // 13120: switch Inst[47] { |
| 6583 | 0, 20, // 13123: case 0x0: { |
| 6584 | OPC_CheckField, 7, 17, 0, // 13125: check Inst[23:7] == 0x0 |
| 6585 | OPC_Scope, 9, // 13129: try { |
| 6586 | OPC_CheckField, 48, 4, 0, // 13131: check Inst[51:48] == 0x0 |
| 6587 | OPC_Decode, 200, 56, 174, 1, // 13135: decode to VGTLZXsir using decoder 174 |
| 6588 | // 13135: } else try { |
| 6589 | OPC_Decode, 206, 56, 175, 1, // 13140: decode to VGTLZXsirm using decoder 175 |
| 6590 | // 13140: } |
| 6591 | // 13140: } |
| 6592 | 1, 0, // 13145: case 0x1: { |
| 6593 | OPC_CheckField, 7, 17, 0, // 13147: check Inst[23:7] == 0x0 |
| 6594 | OPC_Scope, 9, // 13151: try { |
| 6595 | OPC_CheckField, 48, 4, 0, // 13153: check Inst[51:48] == 0x0 |
| 6596 | OPC_Decode, 224, 56, 176, 1, // 13157: decode to VGTLZXsrr using decoder 176 |
| 6597 | // 13157: } else try { |
| 6598 | OPC_Decode, 230, 56, 177, 1, // 13162: decode to VGTLZXsrrm using decoder 177 |
| 6599 | // 13162: } |
| 6600 | // 13162: } |
| 6601 | // 13162: } // switch Inst[47] |
| 6602 | // 13162: } |
| 6603 | // 13162: } // switch Inst[39] |
| 6604 | // 13162: } |
| 6605 | // 13162: } // switch Inst[54:52] |
| 6606 | // 13162: } |
| 6607 | 200, 2, 13, // 13167: case 0x148: { |
| 6608 | OPC_CheckField, 24, 24, 0, // 13170: check Inst[47:24] == 0x0 |
| 6609 | OPC_CheckField, 0, 16, 0, // 13174: check Inst[15:0] == 0x0 |
| 6610 | OPC_Decode, 136, 7, 178, 1, // 13178: decode to PCVMm using decoder 178 |
| 6611 | // 13178: } |
| 6612 | 202, 2, 13, // 13183: case 0x14a: { |
| 6613 | OPC_CheckField, 24, 24, 0, // 13186: check Inst[47:24] == 0x0 |
| 6614 | OPC_CheckField, 0, 16, 0, // 13190: check Inst[15:0] == 0x0 |
| 6615 | OPC_Decode, 193, 6, 178, 1, // 13194: decode to LZVMm using decoder 178 |
| 6616 | // 13194: } |
| 6617 | 204, 2, 13, // 13199: case 0x14c: { |
| 6618 | OPC_CheckField, 24, 24, 0, // 13202: check Inst[47:24] == 0x0 |
| 6619 | OPC_CheckField, 0, 16, 0, // 13206: check Inst[15:0] == 0x0 |
| 6620 | OPC_Decode, 201, 35, 178, 1, // 13210: decode to TOVMm using decoder 178 |
| 6621 | // 13210: } |
| 6622 | 206, 2, 33, // 13215: case 0x14e: { |
| 6623 | OPC_SwitchField, 47, 1, // 13218: switch Inst[47] { |
| 6624 | 0, 13, // 13221: case 0x0: { |
| 6625 | OPC_CheckField, 16, 24, 0, // 13223: check Inst[39:16] == 0x0 |
| 6626 | OPC_CheckField, 0, 8, 0, // 13227: check Inst[7:0] == 0x0 |
| 6627 | OPC_Decode, 198, 35, 179, 1, // 13231: decode to SVMmi using decoder 179 |
| 6628 | // 13231: } |
| 6629 | 1, 0, // 13236: case 0x1: { |
| 6630 | OPC_CheckField, 16, 24, 0, // 13238: check Inst[39:16] == 0x0 |
| 6631 | OPC_CheckField, 0, 8, 0, // 13242: check Inst[7:0] == 0x0 |
| 6632 | OPC_Decode, 199, 35, 180, 1, // 13246: decode to SVMmr using decoder 180 |
| 6633 | // 13246: } |
| 6634 | // 13246: } // switch Inst[47] |
| 6635 | // 13246: } |
| 6636 | 208, 2, 28, // 13251: case 0x150: { |
| 6637 | OPC_CheckField, 0, 8, 0, // 13254: check Inst[7:0] == 0x0 |
| 6638 | OPC_CheckField, 32, 16, 0, // 13258: check Inst[47:32] == 0x0 |
| 6639 | OPC_CheckField, 52, 3, 0, // 13262: check Inst[54:52] == 0x0 |
| 6640 | OPC_Scope, 9, // 13266: try { |
| 6641 | OPC_CheckField, 48, 4, 0, // 13268: check Inst[51:48] == 0x0 |
| 6642 | OPC_Decode, 240, 39, 181, 1, // 13272: decode to VCVTLDv using decoder 181 |
| 6643 | // 13272: } else try { |
| 6644 | OPC_Decode, 246, 39, 182, 1, // 13277: decode to VCVTLDvm using decoder 182 |
| 6645 | // 13277: } |
| 6646 | // 13277: } |
| 6647 | 212, 2, 26, // 13282: case 0x154: { |
| 6648 | OPC_CheckField, 0, 16, 0, // 13285: check Inst[15:0] == 0x0 |
| 6649 | OPC_CheckField, 32, 16, 0, // 13289: check Inst[47:32] == 0x0 |
| 6650 | OPC_CheckField, 52, 3, 0, // 13293: check Inst[54:52] == 0x0 |
| 6651 | OPC_Scope, 8, // 13297: try { |
| 6652 | OPC_CheckField, 48, 4, 0, // 13299: check Inst[51:48] == 0x0 |
| 6653 | OPC_Decode, 188, 83, 119, // 13303: decode to VSUMLv using decoder 119 |
| 6654 | // 13303: } else try { |
| 6655 | OPC_Decode, 194, 83, 120, // 13307: decode to VSUMLvm using decoder 120 |
| 6656 | // 13307: } |
| 6657 | // 13307: } |
| 6658 | 214, 2, 99, // 13311: case 0x156: { |
| 6659 | OPC_SwitchField, 52, 3, // 13314: switch Inst[54:52] { |
| 6660 | 0, 22, // 13317: case 0x0: { |
| 6661 | OPC_CheckField, 0, 16, 0, // 13319: check Inst[15:0] == 0x0 |
| 6662 | OPC_CheckField, 32, 16, 0, // 13323: check Inst[47:32] == 0x0 |
| 6663 | OPC_Scope, 8, // 13327: try { |
| 6664 | OPC_CheckField, 48, 4, 0, // 13329: check Inst[51:48] == 0x0 |
| 6665 | OPC_Decode, 152, 68, 119, // 13333: decode to VRMAXSLFSTv using decoder 119 |
| 6666 | // 13333: } else try { |
| 6667 | OPC_Decode, 158, 68, 120, // 13337: decode to VRMAXSLFSTvm using decoder 120 |
| 6668 | // 13337: } |
| 6669 | // 13337: } |
| 6670 | 1, 22, // 13341: case 0x1: { |
| 6671 | OPC_CheckField, 0, 16, 0, // 13343: check Inst[15:0] == 0x0 |
| 6672 | OPC_CheckField, 32, 16, 0, // 13347: check Inst[47:32] == 0x0 |
| 6673 | OPC_Scope, 8, // 13351: try { |
| 6674 | OPC_CheckField, 48, 4, 0, // 13353: check Inst[51:48] == 0x0 |
| 6675 | OPC_Decode, 224, 68, 119, // 13357: decode to VRMINSLFSTv using decoder 119 |
| 6676 | // 13357: } else try { |
| 6677 | OPC_Decode, 230, 68, 120, // 13361: decode to VRMINSLFSTvm using decoder 120 |
| 6678 | // 13361: } |
| 6679 | // 13361: } |
| 6680 | 2, 22, // 13365: case 0x2: { |
| 6681 | OPC_CheckField, 0, 16, 0, // 13367: check Inst[15:0] == 0x0 |
| 6682 | OPC_CheckField, 32, 16, 0, // 13371: check Inst[47:32] == 0x0 |
| 6683 | OPC_Scope, 8, // 13375: try { |
| 6684 | OPC_CheckField, 48, 4, 0, // 13377: check Inst[51:48] == 0x0 |
| 6685 | OPC_Decode, 164, 68, 119, // 13381: decode to VRMAXSLLSTv using decoder 119 |
| 6686 | // 13381: } else try { |
| 6687 | OPC_Decode, 170, 68, 120, // 13385: decode to VRMAXSLLSTvm using decoder 120 |
| 6688 | // 13385: } |
| 6689 | // 13385: } |
| 6690 | 3, 0, // 13389: case 0x3: { |
| 6691 | OPC_CheckField, 0, 16, 0, // 13391: check Inst[15:0] == 0x0 |
| 6692 | OPC_CheckField, 32, 16, 0, // 13395: check Inst[47:32] == 0x0 |
| 6693 | OPC_Scope, 8, // 13399: try { |
| 6694 | OPC_CheckField, 48, 4, 0, // 13401: check Inst[51:48] == 0x0 |
| 6695 | OPC_Decode, 236, 68, 119, // 13405: decode to VRMINSLLSTv using decoder 119 |
| 6696 | // 13405: } else try { |
| 6697 | OPC_Decode, 242, 68, 120, // 13409: decode to VRMINSLLSTvm using decoder 120 |
| 6698 | // 13409: } |
| 6699 | // 13409: } |
| 6700 | // 13409: } // switch Inst[54:52] |
| 6701 | // 13409: } |
| 6702 | 216, 2, 63, // 13413: case 0x158: { |
| 6703 | OPC_SwitchField, 52, 3, // 13416: switch Inst[54:52] { |
| 6704 | 0, 28, // 13419: case 0x0: { |
| 6705 | OPC_CheckField, 0, 8, 0, // 13421: check Inst[7:0] == 0x0 |
| 6706 | OPC_CheckField, 16, 8, 0, // 13425: check Inst[23:16] == 0x0 |
| 6707 | OPC_CheckField, 32, 16, 0, // 13429: check Inst[47:32] == 0x0 |
| 6708 | OPC_Scope, 9, // 13433: try { |
| 6709 | OPC_CheckField, 48, 4, 0, // 13435: check Inst[51:48] == 0x0 |
| 6710 | OPC_Decode, 232, 67, 142, 1, // 13439: decode to VPCNTv using decoder 142 |
| 6711 | // 13439: } else try { |
| 6712 | OPC_Decode, 238, 67, 143, 1, // 13444: decode to VPCNTvm using decoder 143 |
| 6713 | // 13444: } |
| 6714 | // 13444: } |
| 6715 | 4, 0, // 13449: case 0x4: { |
| 6716 | OPC_CheckField, 0, 8, 0, // 13451: check Inst[7:0] == 0x0 |
| 6717 | OPC_CheckField, 16, 8, 0, // 13455: check Inst[23:16] == 0x0 |
| 6718 | OPC_CheckField, 32, 16, 0, // 13459: check Inst[47:32] == 0x0 |
| 6719 | OPC_Scope, 9, // 13463: try { |
| 6720 | OPC_CheckField, 48, 4, 0, // 13465: check Inst[51:48] == 0x0 |
| 6721 | OPC_Decode, 187, 27, 142, 1, // 13469: decode to PVPCNTLOv using decoder 142 |
| 6722 | // 13469: } else try { |
| 6723 | OPC_Decode, 193, 27, 143, 1, // 13474: decode to PVPCNTLOvm using decoder 143 |
| 6724 | // 13474: } |
| 6725 | // 13474: } |
| 6726 | // 13474: } // switch Inst[54:52] |
| 6727 | // 13474: } |
| 6728 | 217, 2, 63, // 13479: case 0x159: { |
| 6729 | OPC_SwitchField, 52, 3, // 13482: switch Inst[54:52] { |
| 6730 | 0, 28, // 13485: case 0x0: { |
| 6731 | OPC_CheckField, 0, 8, 0, // 13487: check Inst[7:0] == 0x0 |
| 6732 | OPC_CheckField, 16, 8, 0, // 13491: check Inst[23:16] == 0x0 |
| 6733 | OPC_CheckField, 32, 16, 0, // 13495: check Inst[47:32] == 0x0 |
| 6734 | OPC_Scope, 9, // 13499: try { |
| 6735 | OPC_CheckField, 48, 4, 0, // 13501: check Inst[51:48] == 0x0 |
| 6736 | OPC_Decode, 199, 27, 142, 1, // 13505: decode to PVPCNTUPv using decoder 142 |
| 6737 | // 13505: } else try { |
| 6738 | OPC_Decode, 205, 27, 143, 1, // 13510: decode to PVPCNTUPvm using decoder 143 |
| 6739 | // 13510: } |
| 6740 | // 13510: } |
| 6741 | 4, 0, // 13515: case 0x4: { |
| 6742 | OPC_CheckField, 0, 8, 0, // 13517: check Inst[7:0] == 0x0 |
| 6743 | OPC_CheckField, 16, 8, 0, // 13521: check Inst[23:16] == 0x0 |
| 6744 | OPC_CheckField, 32, 16, 0, // 13525: check Inst[47:32] == 0x0 |
| 6745 | OPC_Scope, 9, // 13529: try { |
| 6746 | OPC_CheckField, 48, 4, 0, // 13531: check Inst[51:48] == 0x0 |
| 6747 | OPC_Decode, 211, 27, 142, 1, // 13535: decode to PVPCNTv using decoder 142 |
| 6748 | // 13535: } else try { |
| 6749 | OPC_Decode, 217, 27, 183, 1, // 13540: decode to PVPCNTvm using decoder 183 |
| 6750 | // 13540: } |
| 6751 | // 13540: } |
| 6752 | // 13540: } // switch Inst[54:52] |
| 6753 | // 13540: } |
| 6754 | 218, 2, 99, // 13545: case 0x15a: { |
| 6755 | OPC_SwitchField, 52, 3, // 13548: switch Inst[54:52] { |
| 6756 | 0, 22, // 13551: case 0x0: { |
| 6757 | OPC_CheckField, 0, 16, 0, // 13553: check Inst[15:0] == 0x0 |
| 6758 | OPC_CheckField, 32, 16, 0, // 13557: check Inst[47:32] == 0x0 |
| 6759 | OPC_Scope, 8, // 13561: try { |
| 6760 | OPC_CheckField, 48, 4, 0, // 13563: check Inst[51:48] == 0x0 |
| 6761 | OPC_Decode, 208, 52, 119, // 13567: decode to VFRMAXDFSTv using decoder 119 |
| 6762 | // 13567: } else try { |
| 6763 | OPC_Decode, 214, 52, 120, // 13571: decode to VFRMAXDFSTvm using decoder 120 |
| 6764 | // 13571: } |
| 6765 | // 13571: } |
| 6766 | 1, 22, // 13575: case 0x1: { |
| 6767 | OPC_CheckField, 0, 16, 0, // 13577: check Inst[15:0] == 0x0 |
| 6768 | OPC_CheckField, 32, 16, 0, // 13581: check Inst[47:32] == 0x0 |
| 6769 | OPC_Scope, 8, // 13585: try { |
| 6770 | OPC_CheckField, 48, 4, 0, // 13587: check Inst[51:48] == 0x0 |
| 6771 | OPC_Decode, 128, 53, 119, // 13591: decode to VFRMINDFSTv using decoder 119 |
| 6772 | // 13591: } else try { |
| 6773 | OPC_Decode, 134, 53, 120, // 13595: decode to VFRMINDFSTvm using decoder 120 |
| 6774 | // 13595: } |
| 6775 | // 13595: } |
| 6776 | 2, 22, // 13599: case 0x2: { |
| 6777 | OPC_CheckField, 0, 16, 0, // 13601: check Inst[15:0] == 0x0 |
| 6778 | OPC_CheckField, 32, 16, 0, // 13605: check Inst[47:32] == 0x0 |
| 6779 | OPC_Scope, 8, // 13609: try { |
| 6780 | OPC_CheckField, 48, 4, 0, // 13611: check Inst[51:48] == 0x0 |
| 6781 | OPC_Decode, 220, 52, 119, // 13615: decode to VFRMAXDLSTv using decoder 119 |
| 6782 | // 13615: } else try { |
| 6783 | OPC_Decode, 226, 52, 120, // 13619: decode to VFRMAXDLSTvm using decoder 120 |
| 6784 | // 13619: } |
| 6785 | // 13619: } |
| 6786 | 3, 0, // 13623: case 0x3: { |
| 6787 | OPC_CheckField, 0, 16, 0, // 13625: check Inst[15:0] == 0x0 |
| 6788 | OPC_CheckField, 32, 16, 0, // 13629: check Inst[47:32] == 0x0 |
| 6789 | OPC_Scope, 8, // 13633: try { |
| 6790 | OPC_CheckField, 48, 4, 0, // 13635: check Inst[51:48] == 0x0 |
| 6791 | OPC_Decode, 140, 53, 119, // 13639: decode to VFRMINDLSTv using decoder 119 |
| 6792 | // 13639: } else try { |
| 6793 | OPC_Decode, 146, 53, 120, // 13643: decode to VFRMINDLSTvm using decoder 120 |
| 6794 | // 13643: } |
| 6795 | // 13643: } |
| 6796 | // 13643: } // switch Inst[54:52] |
| 6797 | // 13643: } |
| 6798 | 219, 2, 99, // 13647: case 0x15b: { |
| 6799 | OPC_SwitchField, 52, 3, // 13650: switch Inst[54:52] { |
| 6800 | 0, 22, // 13653: case 0x0: { |
| 6801 | OPC_CheckField, 0, 16, 0, // 13655: check Inst[15:0] == 0x0 |
| 6802 | OPC_CheckField, 32, 16, 0, // 13659: check Inst[47:32] == 0x0 |
| 6803 | OPC_Scope, 8, // 13663: try { |
| 6804 | OPC_CheckField, 48, 4, 0, // 13665: check Inst[51:48] == 0x0 |
| 6805 | OPC_Decode, 232, 52, 119, // 13669: decode to VFRMAXSFSTv using decoder 119 |
| 6806 | // 13669: } else try { |
| 6807 | OPC_Decode, 238, 52, 120, // 13673: decode to VFRMAXSFSTvm using decoder 120 |
| 6808 | // 13673: } |
| 6809 | // 13673: } |
| 6810 | 1, 22, // 13677: case 0x1: { |
| 6811 | OPC_CheckField, 0, 16, 0, // 13679: check Inst[15:0] == 0x0 |
| 6812 | OPC_CheckField, 32, 16, 0, // 13683: check Inst[47:32] == 0x0 |
| 6813 | OPC_Scope, 8, // 13687: try { |
| 6814 | OPC_CheckField, 48, 4, 0, // 13689: check Inst[51:48] == 0x0 |
| 6815 | OPC_Decode, 152, 53, 119, // 13693: decode to VFRMINSFSTv using decoder 119 |
| 6816 | // 13693: } else try { |
| 6817 | OPC_Decode, 158, 53, 120, // 13697: decode to VFRMINSFSTvm using decoder 120 |
| 6818 | // 13697: } |
| 6819 | // 13697: } |
| 6820 | 2, 22, // 13701: case 0x2: { |
| 6821 | OPC_CheckField, 0, 16, 0, // 13703: check Inst[15:0] == 0x0 |
| 6822 | OPC_CheckField, 32, 16, 0, // 13707: check Inst[47:32] == 0x0 |
| 6823 | OPC_Scope, 8, // 13711: try { |
| 6824 | OPC_CheckField, 48, 4, 0, // 13713: check Inst[51:48] == 0x0 |
| 6825 | OPC_Decode, 244, 52, 119, // 13717: decode to VFRMAXSLSTv using decoder 119 |
| 6826 | // 13717: } else try { |
| 6827 | OPC_Decode, 250, 52, 120, // 13721: decode to VFRMAXSLSTvm using decoder 120 |
| 6828 | // 13721: } |
| 6829 | // 13721: } |
| 6830 | 3, 0, // 13725: case 0x3: { |
| 6831 | OPC_CheckField, 0, 16, 0, // 13727: check Inst[15:0] == 0x0 |
| 6832 | OPC_CheckField, 32, 16, 0, // 13731: check Inst[47:32] == 0x0 |
| 6833 | OPC_Scope, 8, // 13735: try { |
| 6834 | OPC_CheckField, 48, 4, 0, // 13737: check Inst[51:48] == 0x0 |
| 6835 | OPC_Decode, 164, 53, 119, // 13741: decode to VFRMINSLSTv using decoder 119 |
| 6836 | // 13741: } else try { |
| 6837 | OPC_Decode, 170, 53, 120, // 13745: decode to VFRMINSLSTvm using decoder 120 |
| 6838 | // 13745: } |
| 6839 | // 13745: } |
| 6840 | // 13745: } // switch Inst[54:52] |
| 6841 | // 13745: } |
| 6842 | 222, 2, 23, // 13749: case 0x15e: { |
| 6843 | OPC_SwitchField, 47, 8, // 13752: switch Inst[54:47] { |
| 6844 | 0, 8, // 13755: case 0x0: { |
| 6845 | OPC_CheckField, 0, 40, 0, // 13757: check Inst[39:0] == 0x0 |
| 6846 | OPC_Decode, 179, 6, 95, // 13761: decode to LVIXi using decoder 95 |
| 6847 | // 13761: } |
| 6848 | 1, 0, // 13765: case 0x1: { |
| 6849 | OPC_CheckField, 0, 40, 0, // 13767: check Inst[39:0] == 0x0 |
| 6850 | OPC_Decode, 180, 6, 42, // 13771: decode to LVIXr using decoder 42 |
| 6851 | // 13771: } |
| 6852 | // 13771: } // switch Inst[54:47] |
| 6853 | // 13771: } |
| 6854 | 226, 2, 159, 3, // 13775: case 0x162: { |
| 6855 | OPC_SwitchField, 52, 3, // 13779: switch Inst[54:52] { |
| 6856 | 0, 101, // 13782: case 0x0: { |
| 6857 | OPC_SwitchField, 39, 1, // 13784: switch Inst[39] { |
| 6858 | 0, 47, // 13787: case 0x0: { |
| 6859 | OPC_SwitchField, 47, 1, // 13789: switch Inst[47] { |
| 6860 | 0, 20, // 13792: case 0x0: { |
| 6861 | OPC_CheckField, 0, 16, 0, // 13794: check Inst[15:0] == 0x0 |
| 6862 | OPC_Scope, 9, // 13798: try { |
| 6863 | OPC_CheckField, 48, 4, 0, // 13800: check Inst[51:48] == 0x0 |
| 6864 | OPC_Decode, 254, 71, 184, 1, // 13804: decode to VSCNCvizv using decoder 184 |
| 6865 | // 13804: } else try { |
| 6866 | OPC_Decode, 129, 72, 185, 1, // 13809: decode to VSCNCvizvm using decoder 185 |
| 6867 | // 13809: } |
| 6868 | // 13809: } |
| 6869 | 1, 0, // 13814: case 0x1: { |
| 6870 | OPC_CheckField, 0, 16, 0, // 13816: check Inst[15:0] == 0x0 |
| 6871 | OPC_Scope, 9, // 13820: try { |
| 6872 | OPC_CheckField, 48, 4, 0, // 13822: check Inst[51:48] == 0x0 |
| 6873 | OPC_Decode, 138, 72, 186, 1, // 13826: decode to VSCNCvrzv using decoder 186 |
| 6874 | // 13826: } else try { |
| 6875 | OPC_Decode, 141, 72, 187, 1, // 13831: decode to VSCNCvrzvm using decoder 187 |
| 6876 | // 13831: } |
| 6877 | // 13831: } |
| 6878 | // 13831: } // switch Inst[47] |
| 6879 | // 13831: } |
| 6880 | 1, 0, // 13836: case 0x1: { |
| 6881 | OPC_SwitchField, 47, 1, // 13838: switch Inst[47] { |
| 6882 | 0, 20, // 13841: case 0x0: { |
| 6883 | OPC_CheckField, 0, 16, 0, // 13843: check Inst[15:0] == 0x0 |
| 6884 | OPC_Scope, 9, // 13847: try { |
| 6885 | OPC_CheckField, 48, 4, 0, // 13849: check Inst[51:48] == 0x0 |
| 6886 | OPC_Decode, 248, 71, 188, 1, // 13853: decode to VSCNCvirv using decoder 188 |
| 6887 | // 13853: } else try { |
| 6888 | OPC_Decode, 251, 71, 189, 1, // 13858: decode to VSCNCvirvm using decoder 189 |
| 6889 | // 13858: } |
| 6890 | // 13858: } |
| 6891 | 1, 0, // 13863: case 0x1: { |
| 6892 | OPC_CheckField, 0, 16, 0, // 13865: check Inst[15:0] == 0x0 |
| 6893 | OPC_Scope, 9, // 13869: try { |
| 6894 | OPC_CheckField, 48, 4, 0, // 13871: check Inst[51:48] == 0x0 |
| 6895 | OPC_Decode, 132, 72, 190, 1, // 13875: decode to VSCNCvrrv using decoder 190 |
| 6896 | // 13875: } else try { |
| 6897 | OPC_Decode, 135, 72, 191, 1, // 13880: decode to VSCNCvrrvm using decoder 191 |
| 6898 | // 13880: } |
| 6899 | // 13880: } |
| 6900 | // 13880: } // switch Inst[47] |
| 6901 | // 13880: } |
| 6902 | // 13880: } // switch Inst[39] |
| 6903 | // 13880: } |
| 6904 | 2, 101, // 13885: case 0x2: { |
| 6905 | OPC_SwitchField, 39, 1, // 13887: switch Inst[39] { |
| 6906 | 0, 47, // 13890: case 0x0: { |
| 6907 | OPC_SwitchField, 47, 1, // 13892: switch Inst[47] { |
| 6908 | 0, 20, // 13895: case 0x0: { |
| 6909 | OPC_CheckField, 7, 17, 0, // 13897: check Inst[23:7] == 0x0 |
| 6910 | OPC_Scope, 9, // 13901: try { |
| 6911 | OPC_CheckField, 48, 4, 0, // 13903: check Inst[51:48] == 0x0 |
| 6912 | OPC_Decode, 230, 71, 192, 1, // 13907: decode to VSCNCsizv using decoder 192 |
| 6913 | // 13907: } else try { |
| 6914 | OPC_Decode, 233, 71, 193, 1, // 13912: decode to VSCNCsizvm using decoder 193 |
| 6915 | // 13912: } |
| 6916 | // 13912: } |
| 6917 | 1, 0, // 13917: case 0x1: { |
| 6918 | OPC_CheckField, 7, 17, 0, // 13919: check Inst[23:7] == 0x0 |
| 6919 | OPC_Scope, 9, // 13923: try { |
| 6920 | OPC_CheckField, 48, 4, 0, // 13925: check Inst[51:48] == 0x0 |
| 6921 | OPC_Decode, 242, 71, 194, 1, // 13929: decode to VSCNCsrzv using decoder 194 |
| 6922 | // 13929: } else try { |
| 6923 | OPC_Decode, 245, 71, 195, 1, // 13934: decode to VSCNCsrzvm using decoder 195 |
| 6924 | // 13934: } |
| 6925 | // 13934: } |
| 6926 | // 13934: } // switch Inst[47] |
| 6927 | // 13934: } |
| 6928 | 1, 0, // 13939: case 0x1: { |
| 6929 | OPC_SwitchField, 47, 1, // 13941: switch Inst[47] { |
| 6930 | 0, 20, // 13944: case 0x0: { |
| 6931 | OPC_CheckField, 7, 17, 0, // 13946: check Inst[23:7] == 0x0 |
| 6932 | OPC_Scope, 9, // 13950: try { |
| 6933 | OPC_CheckField, 48, 4, 0, // 13952: check Inst[51:48] == 0x0 |
| 6934 | OPC_Decode, 224, 71, 196, 1, // 13956: decode to VSCNCsirv using decoder 196 |
| 6935 | // 13956: } else try { |
| 6936 | OPC_Decode, 227, 71, 197, 1, // 13961: decode to VSCNCsirvm using decoder 197 |
| 6937 | // 13961: } |
| 6938 | // 13961: } |
| 6939 | 1, 0, // 13966: case 0x1: { |
| 6940 | OPC_CheckField, 7, 17, 0, // 13968: check Inst[23:7] == 0x0 |
| 6941 | OPC_Scope, 9, // 13972: try { |
| 6942 | OPC_CheckField, 48, 4, 0, // 13974: check Inst[51:48] == 0x0 |
| 6943 | OPC_Decode, 236, 71, 198, 1, // 13978: decode to VSCNCsrrv using decoder 198 |
| 6944 | // 13978: } else try { |
| 6945 | OPC_Decode, 239, 71, 199, 1, // 13983: decode to VSCNCsrrvm using decoder 199 |
| 6946 | // 13983: } |
| 6947 | // 13983: } |
| 6948 | // 13983: } // switch Inst[47] |
| 6949 | // 13983: } |
| 6950 | // 13983: } // switch Inst[39] |
| 6951 | // 13983: } |
| 6952 | 4, 101, // 13988: case 0x4: { |
| 6953 | OPC_SwitchField, 39, 1, // 13990: switch Inst[39] { |
| 6954 | 0, 47, // 13993: case 0x0: { |
| 6955 | OPC_SwitchField, 47, 1, // 13995: switch Inst[47] { |
| 6956 | 0, 20, // 13998: case 0x0: { |
| 6957 | OPC_CheckField, 0, 16, 0, // 14000: check Inst[15:0] == 0x0 |
| 6958 | OPC_Scope, 9, // 14004: try { |
| 6959 | OPC_CheckField, 48, 4, 0, // 14006: check Inst[51:48] == 0x0 |
| 6960 | OPC_Decode, 158, 74, 184, 1, // 14010: decode to VSCvizv using decoder 184 |
| 6961 | // 14010: } else try { |
| 6962 | OPC_Decode, 161, 74, 185, 1, // 14015: decode to VSCvizvm using decoder 185 |
| 6963 | // 14015: } |
| 6964 | // 14015: } |
| 6965 | 1, 0, // 14020: case 0x1: { |
| 6966 | OPC_CheckField, 0, 16, 0, // 14022: check Inst[15:0] == 0x0 |
| 6967 | OPC_Scope, 9, // 14026: try { |
| 6968 | OPC_CheckField, 48, 4, 0, // 14028: check Inst[51:48] == 0x0 |
| 6969 | OPC_Decode, 170, 74, 186, 1, // 14032: decode to VSCvrzv using decoder 186 |
| 6970 | // 14032: } else try { |
| 6971 | OPC_Decode, 173, 74, 187, 1, // 14037: decode to VSCvrzvm using decoder 187 |
| 6972 | // 14037: } |
| 6973 | // 14037: } |
| 6974 | // 14037: } // switch Inst[47] |
| 6975 | // 14037: } |
| 6976 | 1, 0, // 14042: case 0x1: { |
| 6977 | OPC_SwitchField, 47, 1, // 14044: switch Inst[47] { |
| 6978 | 0, 20, // 14047: case 0x0: { |
| 6979 | OPC_CheckField, 0, 16, 0, // 14049: check Inst[15:0] == 0x0 |
| 6980 | OPC_Scope, 9, // 14053: try { |
| 6981 | OPC_CheckField, 48, 4, 0, // 14055: check Inst[51:48] == 0x0 |
| 6982 | OPC_Decode, 152, 74, 188, 1, // 14059: decode to VSCvirv using decoder 188 |
| 6983 | // 14059: } else try { |
| 6984 | OPC_Decode, 155, 74, 189, 1, // 14064: decode to VSCvirvm using decoder 189 |
| 6985 | // 14064: } |
| 6986 | // 14064: } |
| 6987 | 1, 0, // 14069: case 0x1: { |
| 6988 | OPC_CheckField, 0, 16, 0, // 14071: check Inst[15:0] == 0x0 |
| 6989 | OPC_Scope, 9, // 14075: try { |
| 6990 | OPC_CheckField, 48, 4, 0, // 14077: check Inst[51:48] == 0x0 |
| 6991 | OPC_Decode, 164, 74, 190, 1, // 14081: decode to VSCvrrv using decoder 190 |
| 6992 | // 14081: } else try { |
| 6993 | OPC_Decode, 167, 74, 191, 1, // 14086: decode to VSCvrrvm using decoder 191 |
| 6994 | // 14086: } |
| 6995 | // 14086: } |
| 6996 | // 14086: } // switch Inst[47] |
| 6997 | // 14086: } |
| 6998 | // 14086: } // switch Inst[39] |
| 6999 | // 14086: } |
| 7000 | 6, 0, // 14091: case 0x6: { |
| 7001 | OPC_SwitchField, 39, 1, // 14093: switch Inst[39] { |
| 7002 | 0, 47, // 14096: case 0x0: { |
| 7003 | OPC_SwitchField, 47, 1, // 14098: switch Inst[47] { |
| 7004 | 0, 20, // 14101: case 0x0: { |
| 7005 | OPC_CheckField, 7, 17, 0, // 14103: check Inst[23:7] == 0x0 |
| 7006 | OPC_Scope, 9, // 14107: try { |
| 7007 | OPC_CheckField, 48, 4, 0, // 14109: check Inst[51:48] == 0x0 |
| 7008 | OPC_Decode, 134, 74, 192, 1, // 14113: decode to VSCsizv using decoder 192 |
| 7009 | // 14113: } else try { |
| 7010 | OPC_Decode, 137, 74, 193, 1, // 14118: decode to VSCsizvm using decoder 193 |
| 7011 | // 14118: } |
| 7012 | // 14118: } |
| 7013 | 1, 0, // 14123: case 0x1: { |
| 7014 | OPC_CheckField, 7, 17, 0, // 14125: check Inst[23:7] == 0x0 |
| 7015 | OPC_Scope, 9, // 14129: try { |
| 7016 | OPC_CheckField, 48, 4, 0, // 14131: check Inst[51:48] == 0x0 |
| 7017 | OPC_Decode, 146, 74, 194, 1, // 14135: decode to VSCsrzv using decoder 194 |
| 7018 | // 14135: } else try { |
| 7019 | OPC_Decode, 149, 74, 195, 1, // 14140: decode to VSCsrzvm using decoder 195 |
| 7020 | // 14140: } |
| 7021 | // 14140: } |
| 7022 | // 14140: } // switch Inst[47] |
| 7023 | // 14140: } |
| 7024 | 1, 0, // 14145: case 0x1: { |
| 7025 | OPC_SwitchField, 47, 1, // 14147: switch Inst[47] { |
| 7026 | 0, 20, // 14150: case 0x0: { |
| 7027 | OPC_CheckField, 7, 17, 0, // 14152: check Inst[23:7] == 0x0 |
| 7028 | OPC_Scope, 9, // 14156: try { |
| 7029 | OPC_CheckField, 48, 4, 0, // 14158: check Inst[51:48] == 0x0 |
| 7030 | OPC_Decode, 128, 74, 196, 1, // 14162: decode to VSCsirv using decoder 196 |
| 7031 | // 14162: } else try { |
| 7032 | OPC_Decode, 131, 74, 197, 1, // 14167: decode to VSCsirvm using decoder 197 |
| 7033 | // 14167: } |
| 7034 | // 14167: } |
| 7035 | 1, 0, // 14172: case 0x1: { |
| 7036 | OPC_CheckField, 7, 17, 0, // 14174: check Inst[23:7] == 0x0 |
| 7037 | OPC_Scope, 9, // 14178: try { |
| 7038 | OPC_CheckField, 48, 4, 0, // 14180: check Inst[51:48] == 0x0 |
| 7039 | OPC_Decode, 140, 74, 198, 1, // 14184: decode to VSCsrrv using decoder 198 |
| 7040 | // 14184: } else try { |
| 7041 | OPC_Decode, 143, 74, 199, 1, // 14189: decode to VSCsrrvm using decoder 199 |
| 7042 | // 14189: } |
| 7043 | // 14189: } |
| 7044 | // 14189: } // switch Inst[47] |
| 7045 | // 14189: } |
| 7046 | // 14189: } // switch Inst[39] |
| 7047 | // 14189: } |
| 7048 | // 14189: } // switch Inst[54:52] |
| 7049 | // 14189: } |
| 7050 | 227, 2, 159, 3, // 14194: case 0x163: { |
| 7051 | OPC_SwitchField, 52, 3, // 14198: switch Inst[54:52] { |
| 7052 | 0, 101, // 14201: case 0x0: { |
| 7053 | OPC_SwitchField, 39, 1, // 14203: switch Inst[39] { |
| 7054 | 0, 47, // 14206: case 0x0: { |
| 7055 | OPC_SwitchField, 47, 1, // 14208: switch Inst[47] { |
| 7056 | 0, 20, // 14211: case 0x0: { |
| 7057 | OPC_CheckField, 0, 16, 0, // 14213: check Inst[15:0] == 0x0 |
| 7058 | OPC_Scope, 9, // 14217: try { |
| 7059 | OPC_CheckField, 48, 4, 0, // 14219: check Inst[51:48] == 0x0 |
| 7060 | OPC_Decode, 206, 71, 184, 1, // 14223: decode to VSCNCOTvizv using decoder 184 |
| 7061 | // 14223: } else try { |
| 7062 | OPC_Decode, 209, 71, 185, 1, // 14228: decode to VSCNCOTvizvm using decoder 185 |
| 7063 | // 14228: } |
| 7064 | // 14228: } |
| 7065 | 1, 0, // 14233: case 0x1: { |
| 7066 | OPC_CheckField, 0, 16, 0, // 14235: check Inst[15:0] == 0x0 |
| 7067 | OPC_Scope, 9, // 14239: try { |
| 7068 | OPC_CheckField, 48, 4, 0, // 14241: check Inst[51:48] == 0x0 |
| 7069 | OPC_Decode, 218, 71, 186, 1, // 14245: decode to VSCNCOTvrzv using decoder 186 |
| 7070 | // 14245: } else try { |
| 7071 | OPC_Decode, 221, 71, 187, 1, // 14250: decode to VSCNCOTvrzvm using decoder 187 |
| 7072 | // 14250: } |
| 7073 | // 14250: } |
| 7074 | // 14250: } // switch Inst[47] |
| 7075 | // 14250: } |
| 7076 | 1, 0, // 14255: case 0x1: { |
| 7077 | OPC_SwitchField, 47, 1, // 14257: switch Inst[47] { |
| 7078 | 0, 20, // 14260: case 0x0: { |
| 7079 | OPC_CheckField, 0, 16, 0, // 14262: check Inst[15:0] == 0x0 |
| 7080 | OPC_Scope, 9, // 14266: try { |
| 7081 | OPC_CheckField, 48, 4, 0, // 14268: check Inst[51:48] == 0x0 |
| 7082 | OPC_Decode, 200, 71, 188, 1, // 14272: decode to VSCNCOTvirv using decoder 188 |
| 7083 | // 14272: } else try { |
| 7084 | OPC_Decode, 203, 71, 189, 1, // 14277: decode to VSCNCOTvirvm using decoder 189 |
| 7085 | // 14277: } |
| 7086 | // 14277: } |
| 7087 | 1, 0, // 14282: case 0x1: { |
| 7088 | OPC_CheckField, 0, 16, 0, // 14284: check Inst[15:0] == 0x0 |
| 7089 | OPC_Scope, 9, // 14288: try { |
| 7090 | OPC_CheckField, 48, 4, 0, // 14290: check Inst[51:48] == 0x0 |
| 7091 | OPC_Decode, 212, 71, 190, 1, // 14294: decode to VSCNCOTvrrv using decoder 190 |
| 7092 | // 14294: } else try { |
| 7093 | OPC_Decode, 215, 71, 191, 1, // 14299: decode to VSCNCOTvrrvm using decoder 191 |
| 7094 | // 14299: } |
| 7095 | // 14299: } |
| 7096 | // 14299: } // switch Inst[47] |
| 7097 | // 14299: } |
| 7098 | // 14299: } // switch Inst[39] |
| 7099 | // 14299: } |
| 7100 | 2, 101, // 14304: case 0x2: { |
| 7101 | OPC_SwitchField, 39, 1, // 14306: switch Inst[39] { |
| 7102 | 0, 47, // 14309: case 0x0: { |
| 7103 | OPC_SwitchField, 47, 1, // 14311: switch Inst[47] { |
| 7104 | 0, 20, // 14314: case 0x0: { |
| 7105 | OPC_CheckField, 7, 17, 0, // 14316: check Inst[23:7] == 0x0 |
| 7106 | OPC_Scope, 9, // 14320: try { |
| 7107 | OPC_CheckField, 48, 4, 0, // 14322: check Inst[51:48] == 0x0 |
| 7108 | OPC_Decode, 182, 71, 192, 1, // 14326: decode to VSCNCOTsizv using decoder 192 |
| 7109 | // 14326: } else try { |
| 7110 | OPC_Decode, 185, 71, 193, 1, // 14331: decode to VSCNCOTsizvm using decoder 193 |
| 7111 | // 14331: } |
| 7112 | // 14331: } |
| 7113 | 1, 0, // 14336: case 0x1: { |
| 7114 | OPC_CheckField, 7, 17, 0, // 14338: check Inst[23:7] == 0x0 |
| 7115 | OPC_Scope, 9, // 14342: try { |
| 7116 | OPC_CheckField, 48, 4, 0, // 14344: check Inst[51:48] == 0x0 |
| 7117 | OPC_Decode, 194, 71, 194, 1, // 14348: decode to VSCNCOTsrzv using decoder 194 |
| 7118 | // 14348: } else try { |
| 7119 | OPC_Decode, 197, 71, 195, 1, // 14353: decode to VSCNCOTsrzvm using decoder 195 |
| 7120 | // 14353: } |
| 7121 | // 14353: } |
| 7122 | // 14353: } // switch Inst[47] |
| 7123 | // 14353: } |
| 7124 | 1, 0, // 14358: case 0x1: { |
| 7125 | OPC_SwitchField, 47, 1, // 14360: switch Inst[47] { |
| 7126 | 0, 20, // 14363: case 0x0: { |
| 7127 | OPC_CheckField, 7, 17, 0, // 14365: check Inst[23:7] == 0x0 |
| 7128 | OPC_Scope, 9, // 14369: try { |
| 7129 | OPC_CheckField, 48, 4, 0, // 14371: check Inst[51:48] == 0x0 |
| 7130 | OPC_Decode, 176, 71, 196, 1, // 14375: decode to VSCNCOTsirv using decoder 196 |
| 7131 | // 14375: } else try { |
| 7132 | OPC_Decode, 179, 71, 197, 1, // 14380: decode to VSCNCOTsirvm using decoder 197 |
| 7133 | // 14380: } |
| 7134 | // 14380: } |
| 7135 | 1, 0, // 14385: case 0x1: { |
| 7136 | OPC_CheckField, 7, 17, 0, // 14387: check Inst[23:7] == 0x0 |
| 7137 | OPC_Scope, 9, // 14391: try { |
| 7138 | OPC_CheckField, 48, 4, 0, // 14393: check Inst[51:48] == 0x0 |
| 7139 | OPC_Decode, 188, 71, 198, 1, // 14397: decode to VSCNCOTsrrv using decoder 198 |
| 7140 | // 14397: } else try { |
| 7141 | OPC_Decode, 191, 71, 199, 1, // 14402: decode to VSCNCOTsrrvm using decoder 199 |
| 7142 | // 14402: } |
| 7143 | // 14402: } |
| 7144 | // 14402: } // switch Inst[47] |
| 7145 | // 14402: } |
| 7146 | // 14402: } // switch Inst[39] |
| 7147 | // 14402: } |
| 7148 | 4, 101, // 14407: case 0x4: { |
| 7149 | OPC_SwitchField, 39, 1, // 14409: switch Inst[39] { |
| 7150 | 0, 47, // 14412: case 0x0: { |
| 7151 | OPC_SwitchField, 47, 1, // 14414: switch Inst[47] { |
| 7152 | 0, 20, // 14417: case 0x0: { |
| 7153 | OPC_CheckField, 0, 16, 0, // 14419: check Inst[15:0] == 0x0 |
| 7154 | OPC_Scope, 9, // 14423: try { |
| 7155 | OPC_CheckField, 48, 4, 0, // 14425: check Inst[51:48] == 0x0 |
| 7156 | OPC_Decode, 174, 72, 184, 1, // 14429: decode to VSCOTvizv using decoder 184 |
| 7157 | // 14429: } else try { |
| 7158 | OPC_Decode, 177, 72, 185, 1, // 14434: decode to VSCOTvizvm using decoder 185 |
| 7159 | // 14434: } |
| 7160 | // 14434: } |
| 7161 | 1, 0, // 14439: case 0x1: { |
| 7162 | OPC_CheckField, 0, 16, 0, // 14441: check Inst[15:0] == 0x0 |
| 7163 | OPC_Scope, 9, // 14445: try { |
| 7164 | OPC_CheckField, 48, 4, 0, // 14447: check Inst[51:48] == 0x0 |
| 7165 | OPC_Decode, 186, 72, 186, 1, // 14451: decode to VSCOTvrzv using decoder 186 |
| 7166 | // 14451: } else try { |
| 7167 | OPC_Decode, 189, 72, 187, 1, // 14456: decode to VSCOTvrzvm using decoder 187 |
| 7168 | // 14456: } |
| 7169 | // 14456: } |
| 7170 | // 14456: } // switch Inst[47] |
| 7171 | // 14456: } |
| 7172 | 1, 0, // 14461: case 0x1: { |
| 7173 | OPC_SwitchField, 47, 1, // 14463: switch Inst[47] { |
| 7174 | 0, 20, // 14466: case 0x0: { |
| 7175 | OPC_CheckField, 0, 16, 0, // 14468: check Inst[15:0] == 0x0 |
| 7176 | OPC_Scope, 9, // 14472: try { |
| 7177 | OPC_CheckField, 48, 4, 0, // 14474: check Inst[51:48] == 0x0 |
| 7178 | OPC_Decode, 168, 72, 188, 1, // 14478: decode to VSCOTvirv using decoder 188 |
| 7179 | // 14478: } else try { |
| 7180 | OPC_Decode, 171, 72, 189, 1, // 14483: decode to VSCOTvirvm using decoder 189 |
| 7181 | // 14483: } |
| 7182 | // 14483: } |
| 7183 | 1, 0, // 14488: case 0x1: { |
| 7184 | OPC_CheckField, 0, 16, 0, // 14490: check Inst[15:0] == 0x0 |
| 7185 | OPC_Scope, 9, // 14494: try { |
| 7186 | OPC_CheckField, 48, 4, 0, // 14496: check Inst[51:48] == 0x0 |
| 7187 | OPC_Decode, 180, 72, 190, 1, // 14500: decode to VSCOTvrrv using decoder 190 |
| 7188 | // 14500: } else try { |
| 7189 | OPC_Decode, 183, 72, 191, 1, // 14505: decode to VSCOTvrrvm using decoder 191 |
| 7190 | // 14505: } |
| 7191 | // 14505: } |
| 7192 | // 14505: } // switch Inst[47] |
| 7193 | // 14505: } |
| 7194 | // 14505: } // switch Inst[39] |
| 7195 | // 14505: } |
| 7196 | 6, 0, // 14510: case 0x6: { |
| 7197 | OPC_SwitchField, 39, 1, // 14512: switch Inst[39] { |
| 7198 | 0, 47, // 14515: case 0x0: { |
| 7199 | OPC_SwitchField, 47, 1, // 14517: switch Inst[47] { |
| 7200 | 0, 20, // 14520: case 0x0: { |
| 7201 | OPC_CheckField, 7, 17, 0, // 14522: check Inst[23:7] == 0x0 |
| 7202 | OPC_Scope, 9, // 14526: try { |
| 7203 | OPC_CheckField, 48, 4, 0, // 14528: check Inst[51:48] == 0x0 |
| 7204 | OPC_Decode, 150, 72, 192, 1, // 14532: decode to VSCOTsizv using decoder 192 |
| 7205 | // 14532: } else try { |
| 7206 | OPC_Decode, 153, 72, 193, 1, // 14537: decode to VSCOTsizvm using decoder 193 |
| 7207 | // 14537: } |
| 7208 | // 14537: } |
| 7209 | 1, 0, // 14542: case 0x1: { |
| 7210 | OPC_CheckField, 7, 17, 0, // 14544: check Inst[23:7] == 0x0 |
| 7211 | OPC_Scope, 9, // 14548: try { |
| 7212 | OPC_CheckField, 48, 4, 0, // 14550: check Inst[51:48] == 0x0 |
| 7213 | OPC_Decode, 162, 72, 194, 1, // 14554: decode to VSCOTsrzv using decoder 194 |
| 7214 | // 14554: } else try { |
| 7215 | OPC_Decode, 165, 72, 195, 1, // 14559: decode to VSCOTsrzvm using decoder 195 |
| 7216 | // 14559: } |
| 7217 | // 14559: } |
| 7218 | // 14559: } // switch Inst[47] |
| 7219 | // 14559: } |
| 7220 | 1, 0, // 14564: case 0x1: { |
| 7221 | OPC_SwitchField, 47, 1, // 14566: switch Inst[47] { |
| 7222 | 0, 20, // 14569: case 0x0: { |
| 7223 | OPC_CheckField, 7, 17, 0, // 14571: check Inst[23:7] == 0x0 |
| 7224 | OPC_Scope, 9, // 14575: try { |
| 7225 | OPC_CheckField, 48, 4, 0, // 14577: check Inst[51:48] == 0x0 |
| 7226 | OPC_Decode, 144, 72, 196, 1, // 14581: decode to VSCOTsirv using decoder 196 |
| 7227 | // 14581: } else try { |
| 7228 | OPC_Decode, 147, 72, 197, 1, // 14586: decode to VSCOTsirvm using decoder 197 |
| 7229 | // 14586: } |
| 7230 | // 14586: } |
| 7231 | 1, 0, // 14591: case 0x1: { |
| 7232 | OPC_CheckField, 7, 17, 0, // 14593: check Inst[23:7] == 0x0 |
| 7233 | OPC_Scope, 9, // 14597: try { |
| 7234 | OPC_CheckField, 48, 4, 0, // 14599: check Inst[51:48] == 0x0 |
| 7235 | OPC_Decode, 156, 72, 198, 1, // 14603: decode to VSCOTsrrv using decoder 198 |
| 7236 | // 14603: } else try { |
| 7237 | OPC_Decode, 159, 72, 199, 1, // 14608: decode to VSCOTsrrvm using decoder 199 |
| 7238 | // 14608: } |
| 7239 | // 14608: } |
| 7240 | // 14608: } // switch Inst[47] |
| 7241 | // 14608: } |
| 7242 | // 14608: } // switch Inst[39] |
| 7243 | // 14608: } |
| 7244 | // 14608: } // switch Inst[54:52] |
| 7245 | // 14608: } |
| 7246 | 228, 2, 159, 3, // 14613: case 0x164: { |
| 7247 | OPC_SwitchField, 52, 3, // 14617: switch Inst[54:52] { |
| 7248 | 0, 101, // 14620: case 0x0: { |
| 7249 | OPC_SwitchField, 39, 1, // 14622: switch Inst[39] { |
| 7250 | 0, 47, // 14625: case 0x0: { |
| 7251 | OPC_SwitchField, 47, 1, // 14627: switch Inst[47] { |
| 7252 | 0, 20, // 14630: case 0x0: { |
| 7253 | OPC_CheckField, 0, 16, 0, // 14632: check Inst[15:0] == 0x0 |
| 7254 | OPC_Scope, 9, // 14636: try { |
| 7255 | OPC_CheckField, 48, 4, 0, // 14638: check Inst[51:48] == 0x0 |
| 7256 | OPC_Decode, 142, 73, 184, 1, // 14642: decode to VSCUNCvizv using decoder 184 |
| 7257 | // 14642: } else try { |
| 7258 | OPC_Decode, 145, 73, 185, 1, // 14647: decode to VSCUNCvizvm using decoder 185 |
| 7259 | // 14647: } |
| 7260 | // 14647: } |
| 7261 | 1, 0, // 14652: case 0x1: { |
| 7262 | OPC_CheckField, 0, 16, 0, // 14654: check Inst[15:0] == 0x0 |
| 7263 | OPC_Scope, 9, // 14658: try { |
| 7264 | OPC_CheckField, 48, 4, 0, // 14660: check Inst[51:48] == 0x0 |
| 7265 | OPC_Decode, 154, 73, 186, 1, // 14664: decode to VSCUNCvrzv using decoder 186 |
| 7266 | // 14664: } else try { |
| 7267 | OPC_Decode, 157, 73, 187, 1, // 14669: decode to VSCUNCvrzvm using decoder 187 |
| 7268 | // 14669: } |
| 7269 | // 14669: } |
| 7270 | // 14669: } // switch Inst[47] |
| 7271 | // 14669: } |
| 7272 | 1, 0, // 14674: case 0x1: { |
| 7273 | OPC_SwitchField, 47, 1, // 14676: switch Inst[47] { |
| 7274 | 0, 20, // 14679: case 0x0: { |
| 7275 | OPC_CheckField, 0, 16, 0, // 14681: check Inst[15:0] == 0x0 |
| 7276 | OPC_Scope, 9, // 14685: try { |
| 7277 | OPC_CheckField, 48, 4, 0, // 14687: check Inst[51:48] == 0x0 |
| 7278 | OPC_Decode, 136, 73, 188, 1, // 14691: decode to VSCUNCvirv using decoder 188 |
| 7279 | // 14691: } else try { |
| 7280 | OPC_Decode, 139, 73, 189, 1, // 14696: decode to VSCUNCvirvm using decoder 189 |
| 7281 | // 14696: } |
| 7282 | // 14696: } |
| 7283 | 1, 0, // 14701: case 0x1: { |
| 7284 | OPC_CheckField, 0, 16, 0, // 14703: check Inst[15:0] == 0x0 |
| 7285 | OPC_Scope, 9, // 14707: try { |
| 7286 | OPC_CheckField, 48, 4, 0, // 14709: check Inst[51:48] == 0x0 |
| 7287 | OPC_Decode, 148, 73, 190, 1, // 14713: decode to VSCUNCvrrv using decoder 190 |
| 7288 | // 14713: } else try { |
| 7289 | OPC_Decode, 151, 73, 191, 1, // 14718: decode to VSCUNCvrrvm using decoder 191 |
| 7290 | // 14718: } |
| 7291 | // 14718: } |
| 7292 | // 14718: } // switch Inst[47] |
| 7293 | // 14718: } |
| 7294 | // 14718: } // switch Inst[39] |
| 7295 | // 14718: } |
| 7296 | 2, 101, // 14723: case 0x2: { |
| 7297 | OPC_SwitchField, 39, 1, // 14725: switch Inst[39] { |
| 7298 | 0, 47, // 14728: case 0x0: { |
| 7299 | OPC_SwitchField, 47, 1, // 14730: switch Inst[47] { |
| 7300 | 0, 20, // 14733: case 0x0: { |
| 7301 | OPC_CheckField, 7, 17, 0, // 14735: check Inst[23:7] == 0x0 |
| 7302 | OPC_Scope, 9, // 14739: try { |
| 7303 | OPC_CheckField, 48, 4, 0, // 14741: check Inst[51:48] == 0x0 |
| 7304 | OPC_Decode, 246, 72, 192, 1, // 14745: decode to VSCUNCsizv using decoder 192 |
| 7305 | // 14745: } else try { |
| 7306 | OPC_Decode, 249, 72, 193, 1, // 14750: decode to VSCUNCsizvm using decoder 193 |
| 7307 | // 14750: } |
| 7308 | // 14750: } |
| 7309 | 1, 0, // 14755: case 0x1: { |
| 7310 | OPC_CheckField, 7, 17, 0, // 14757: check Inst[23:7] == 0x0 |
| 7311 | OPC_Scope, 9, // 14761: try { |
| 7312 | OPC_CheckField, 48, 4, 0, // 14763: check Inst[51:48] == 0x0 |
| 7313 | OPC_Decode, 130, 73, 194, 1, // 14767: decode to VSCUNCsrzv using decoder 194 |
| 7314 | // 14767: } else try { |
| 7315 | OPC_Decode, 133, 73, 195, 1, // 14772: decode to VSCUNCsrzvm using decoder 195 |
| 7316 | // 14772: } |
| 7317 | // 14772: } |
| 7318 | // 14772: } // switch Inst[47] |
| 7319 | // 14772: } |
| 7320 | 1, 0, // 14777: case 0x1: { |
| 7321 | OPC_SwitchField, 47, 1, // 14779: switch Inst[47] { |
| 7322 | 0, 20, // 14782: case 0x0: { |
| 7323 | OPC_CheckField, 7, 17, 0, // 14784: check Inst[23:7] == 0x0 |
| 7324 | OPC_Scope, 9, // 14788: try { |
| 7325 | OPC_CheckField, 48, 4, 0, // 14790: check Inst[51:48] == 0x0 |
| 7326 | OPC_Decode, 240, 72, 196, 1, // 14794: decode to VSCUNCsirv using decoder 196 |
| 7327 | // 14794: } else try { |
| 7328 | OPC_Decode, 243, 72, 197, 1, // 14799: decode to VSCUNCsirvm using decoder 197 |
| 7329 | // 14799: } |
| 7330 | // 14799: } |
| 7331 | 1, 0, // 14804: case 0x1: { |
| 7332 | OPC_CheckField, 7, 17, 0, // 14806: check Inst[23:7] == 0x0 |
| 7333 | OPC_Scope, 9, // 14810: try { |
| 7334 | OPC_CheckField, 48, 4, 0, // 14812: check Inst[51:48] == 0x0 |
| 7335 | OPC_Decode, 252, 72, 198, 1, // 14816: decode to VSCUNCsrrv using decoder 198 |
| 7336 | // 14816: } else try { |
| 7337 | OPC_Decode, 255, 72, 199, 1, // 14821: decode to VSCUNCsrrvm using decoder 199 |
| 7338 | // 14821: } |
| 7339 | // 14821: } |
| 7340 | // 14821: } // switch Inst[47] |
| 7341 | // 14821: } |
| 7342 | // 14821: } // switch Inst[39] |
| 7343 | // 14821: } |
| 7344 | 4, 101, // 14826: case 0x4: { |
| 7345 | OPC_SwitchField, 39, 1, // 14828: switch Inst[39] { |
| 7346 | 0, 47, // 14831: case 0x0: { |
| 7347 | OPC_SwitchField, 47, 1, // 14833: switch Inst[47] { |
| 7348 | 0, 20, // 14836: case 0x0: { |
| 7349 | OPC_CheckField, 0, 16, 0, // 14838: check Inst[15:0] == 0x0 |
| 7350 | OPC_Scope, 9, // 14842: try { |
| 7351 | OPC_CheckField, 48, 4, 0, // 14844: check Inst[51:48] == 0x0 |
| 7352 | OPC_Decode, 238, 73, 184, 1, // 14848: decode to VSCUvizv using decoder 184 |
| 7353 | // 14848: } else try { |
| 7354 | OPC_Decode, 241, 73, 185, 1, // 14853: decode to VSCUvizvm using decoder 185 |
| 7355 | // 14853: } |
| 7356 | // 14853: } |
| 7357 | 1, 0, // 14858: case 0x1: { |
| 7358 | OPC_CheckField, 0, 16, 0, // 14860: check Inst[15:0] == 0x0 |
| 7359 | OPC_Scope, 9, // 14864: try { |
| 7360 | OPC_CheckField, 48, 4, 0, // 14866: check Inst[51:48] == 0x0 |
| 7361 | OPC_Decode, 250, 73, 186, 1, // 14870: decode to VSCUvrzv using decoder 186 |
| 7362 | // 14870: } else try { |
| 7363 | OPC_Decode, 253, 73, 187, 1, // 14875: decode to VSCUvrzvm using decoder 187 |
| 7364 | // 14875: } |
| 7365 | // 14875: } |
| 7366 | // 14875: } // switch Inst[47] |
| 7367 | // 14875: } |
| 7368 | 1, 0, // 14880: case 0x1: { |
| 7369 | OPC_SwitchField, 47, 1, // 14882: switch Inst[47] { |
| 7370 | 0, 20, // 14885: case 0x0: { |
| 7371 | OPC_CheckField, 0, 16, 0, // 14887: check Inst[15:0] == 0x0 |
| 7372 | OPC_Scope, 9, // 14891: try { |
| 7373 | OPC_CheckField, 48, 4, 0, // 14893: check Inst[51:48] == 0x0 |
| 7374 | OPC_Decode, 232, 73, 188, 1, // 14897: decode to VSCUvirv using decoder 188 |
| 7375 | // 14897: } else try { |
| 7376 | OPC_Decode, 235, 73, 189, 1, // 14902: decode to VSCUvirvm using decoder 189 |
| 7377 | // 14902: } |
| 7378 | // 14902: } |
| 7379 | 1, 0, // 14907: case 0x1: { |
| 7380 | OPC_CheckField, 0, 16, 0, // 14909: check Inst[15:0] == 0x0 |
| 7381 | OPC_Scope, 9, // 14913: try { |
| 7382 | OPC_CheckField, 48, 4, 0, // 14915: check Inst[51:48] == 0x0 |
| 7383 | OPC_Decode, 244, 73, 190, 1, // 14919: decode to VSCUvrrv using decoder 190 |
| 7384 | // 14919: } else try { |
| 7385 | OPC_Decode, 247, 73, 191, 1, // 14924: decode to VSCUvrrvm using decoder 191 |
| 7386 | // 14924: } |
| 7387 | // 14924: } |
| 7388 | // 14924: } // switch Inst[47] |
| 7389 | // 14924: } |
| 7390 | // 14924: } // switch Inst[39] |
| 7391 | // 14924: } |
| 7392 | 6, 0, // 14929: case 0x6: { |
| 7393 | OPC_SwitchField, 39, 1, // 14931: switch Inst[39] { |
| 7394 | 0, 47, // 14934: case 0x0: { |
| 7395 | OPC_SwitchField, 47, 1, // 14936: switch Inst[47] { |
| 7396 | 0, 20, // 14939: case 0x0: { |
| 7397 | OPC_CheckField, 7, 17, 0, // 14941: check Inst[23:7] == 0x0 |
| 7398 | OPC_Scope, 9, // 14945: try { |
| 7399 | OPC_CheckField, 48, 4, 0, // 14947: check Inst[51:48] == 0x0 |
| 7400 | OPC_Decode, 214, 73, 192, 1, // 14951: decode to VSCUsizv using decoder 192 |
| 7401 | // 14951: } else try { |
| 7402 | OPC_Decode, 217, 73, 193, 1, // 14956: decode to VSCUsizvm using decoder 193 |
| 7403 | // 14956: } |
| 7404 | // 14956: } |
| 7405 | 1, 0, // 14961: case 0x1: { |
| 7406 | OPC_CheckField, 7, 17, 0, // 14963: check Inst[23:7] == 0x0 |
| 7407 | OPC_Scope, 9, // 14967: try { |
| 7408 | OPC_CheckField, 48, 4, 0, // 14969: check Inst[51:48] == 0x0 |
| 7409 | OPC_Decode, 226, 73, 194, 1, // 14973: decode to VSCUsrzv using decoder 194 |
| 7410 | // 14973: } else try { |
| 7411 | OPC_Decode, 229, 73, 195, 1, // 14978: decode to VSCUsrzvm using decoder 195 |
| 7412 | // 14978: } |
| 7413 | // 14978: } |
| 7414 | // 14978: } // switch Inst[47] |
| 7415 | // 14978: } |
| 7416 | 1, 0, // 14983: case 0x1: { |
| 7417 | OPC_SwitchField, 47, 1, // 14985: switch Inst[47] { |
| 7418 | 0, 20, // 14988: case 0x0: { |
| 7419 | OPC_CheckField, 7, 17, 0, // 14990: check Inst[23:7] == 0x0 |
| 7420 | OPC_Scope, 9, // 14994: try { |
| 7421 | OPC_CheckField, 48, 4, 0, // 14996: check Inst[51:48] == 0x0 |
| 7422 | OPC_Decode, 208, 73, 196, 1, // 15000: decode to VSCUsirv using decoder 196 |
| 7423 | // 15000: } else try { |
| 7424 | OPC_Decode, 211, 73, 197, 1, // 15005: decode to VSCUsirvm using decoder 197 |
| 7425 | // 15005: } |
| 7426 | // 15005: } |
| 7427 | 1, 0, // 15010: case 0x1: { |
| 7428 | OPC_CheckField, 7, 17, 0, // 15012: check Inst[23:7] == 0x0 |
| 7429 | OPC_Scope, 9, // 15016: try { |
| 7430 | OPC_CheckField, 48, 4, 0, // 15018: check Inst[51:48] == 0x0 |
| 7431 | OPC_Decode, 220, 73, 198, 1, // 15022: decode to VSCUsrrv using decoder 198 |
| 7432 | // 15022: } else try { |
| 7433 | OPC_Decode, 223, 73, 199, 1, // 15027: decode to VSCUsrrvm using decoder 199 |
| 7434 | // 15027: } |
| 7435 | // 15027: } |
| 7436 | // 15027: } // switch Inst[47] |
| 7437 | // 15027: } |
| 7438 | // 15027: } // switch Inst[39] |
| 7439 | // 15027: } |
| 7440 | // 15027: } // switch Inst[54:52] |
| 7441 | // 15027: } |
| 7442 | 229, 2, 159, 3, // 15032: case 0x165: { |
| 7443 | OPC_SwitchField, 52, 3, // 15036: switch Inst[54:52] { |
| 7444 | 0, 101, // 15039: case 0x0: { |
| 7445 | OPC_SwitchField, 39, 1, // 15041: switch Inst[39] { |
| 7446 | 0, 47, // 15044: case 0x0: { |
| 7447 | OPC_SwitchField, 47, 1, // 15046: switch Inst[47] { |
| 7448 | 0, 20, // 15049: case 0x0: { |
| 7449 | OPC_CheckField, 0, 16, 0, // 15051: check Inst[15:0] == 0x0 |
| 7450 | OPC_Scope, 9, // 15055: try { |
| 7451 | OPC_CheckField, 48, 4, 0, // 15057: check Inst[51:48] == 0x0 |
| 7452 | OPC_Decode, 222, 72, 184, 1, // 15061: decode to VSCUNCOTvizv using decoder 184 |
| 7453 | // 15061: } else try { |
| 7454 | OPC_Decode, 225, 72, 185, 1, // 15066: decode to VSCUNCOTvizvm using decoder 185 |
| 7455 | // 15066: } |
| 7456 | // 15066: } |
| 7457 | 1, 0, // 15071: case 0x1: { |
| 7458 | OPC_CheckField, 0, 16, 0, // 15073: check Inst[15:0] == 0x0 |
| 7459 | OPC_Scope, 9, // 15077: try { |
| 7460 | OPC_CheckField, 48, 4, 0, // 15079: check Inst[51:48] == 0x0 |
| 7461 | OPC_Decode, 234, 72, 186, 1, // 15083: decode to VSCUNCOTvrzv using decoder 186 |
| 7462 | // 15083: } else try { |
| 7463 | OPC_Decode, 237, 72, 187, 1, // 15088: decode to VSCUNCOTvrzvm using decoder 187 |
| 7464 | // 15088: } |
| 7465 | // 15088: } |
| 7466 | // 15088: } // switch Inst[47] |
| 7467 | // 15088: } |
| 7468 | 1, 0, // 15093: case 0x1: { |
| 7469 | OPC_SwitchField, 47, 1, // 15095: switch Inst[47] { |
| 7470 | 0, 20, // 15098: case 0x0: { |
| 7471 | OPC_CheckField, 0, 16, 0, // 15100: check Inst[15:0] == 0x0 |
| 7472 | OPC_Scope, 9, // 15104: try { |
| 7473 | OPC_CheckField, 48, 4, 0, // 15106: check Inst[51:48] == 0x0 |
| 7474 | OPC_Decode, 216, 72, 188, 1, // 15110: decode to VSCUNCOTvirv using decoder 188 |
| 7475 | // 15110: } else try { |
| 7476 | OPC_Decode, 219, 72, 189, 1, // 15115: decode to VSCUNCOTvirvm using decoder 189 |
| 7477 | // 15115: } |
| 7478 | // 15115: } |
| 7479 | 1, 0, // 15120: case 0x1: { |
| 7480 | OPC_CheckField, 0, 16, 0, // 15122: check Inst[15:0] == 0x0 |
| 7481 | OPC_Scope, 9, // 15126: try { |
| 7482 | OPC_CheckField, 48, 4, 0, // 15128: check Inst[51:48] == 0x0 |
| 7483 | OPC_Decode, 228, 72, 190, 1, // 15132: decode to VSCUNCOTvrrv using decoder 190 |
| 7484 | // 15132: } else try { |
| 7485 | OPC_Decode, 231, 72, 191, 1, // 15137: decode to VSCUNCOTvrrvm using decoder 191 |
| 7486 | // 15137: } |
| 7487 | // 15137: } |
| 7488 | // 15137: } // switch Inst[47] |
| 7489 | // 15137: } |
| 7490 | // 15137: } // switch Inst[39] |
| 7491 | // 15137: } |
| 7492 | 2, 101, // 15142: case 0x2: { |
| 7493 | OPC_SwitchField, 39, 1, // 15144: switch Inst[39] { |
| 7494 | 0, 47, // 15147: case 0x0: { |
| 7495 | OPC_SwitchField, 47, 1, // 15149: switch Inst[47] { |
| 7496 | 0, 20, // 15152: case 0x0: { |
| 7497 | OPC_CheckField, 7, 17, 0, // 15154: check Inst[23:7] == 0x0 |
| 7498 | OPC_Scope, 9, // 15158: try { |
| 7499 | OPC_CheckField, 48, 4, 0, // 15160: check Inst[51:48] == 0x0 |
| 7500 | OPC_Decode, 198, 72, 192, 1, // 15164: decode to VSCUNCOTsizv using decoder 192 |
| 7501 | // 15164: } else try { |
| 7502 | OPC_Decode, 201, 72, 193, 1, // 15169: decode to VSCUNCOTsizvm using decoder 193 |
| 7503 | // 15169: } |
| 7504 | // 15169: } |
| 7505 | 1, 0, // 15174: case 0x1: { |
| 7506 | OPC_CheckField, 7, 17, 0, // 15176: check Inst[23:7] == 0x0 |
| 7507 | OPC_Scope, 9, // 15180: try { |
| 7508 | OPC_CheckField, 48, 4, 0, // 15182: check Inst[51:48] == 0x0 |
| 7509 | OPC_Decode, 210, 72, 194, 1, // 15186: decode to VSCUNCOTsrzv using decoder 194 |
| 7510 | // 15186: } else try { |
| 7511 | OPC_Decode, 213, 72, 195, 1, // 15191: decode to VSCUNCOTsrzvm using decoder 195 |
| 7512 | // 15191: } |
| 7513 | // 15191: } |
| 7514 | // 15191: } // switch Inst[47] |
| 7515 | // 15191: } |
| 7516 | 1, 0, // 15196: case 0x1: { |
| 7517 | OPC_SwitchField, 47, 1, // 15198: switch Inst[47] { |
| 7518 | 0, 20, // 15201: case 0x0: { |
| 7519 | OPC_CheckField, 7, 17, 0, // 15203: check Inst[23:7] == 0x0 |
| 7520 | OPC_Scope, 9, // 15207: try { |
| 7521 | OPC_CheckField, 48, 4, 0, // 15209: check Inst[51:48] == 0x0 |
| 7522 | OPC_Decode, 192, 72, 196, 1, // 15213: decode to VSCUNCOTsirv using decoder 196 |
| 7523 | // 15213: } else try { |
| 7524 | OPC_Decode, 195, 72, 197, 1, // 15218: decode to VSCUNCOTsirvm using decoder 197 |
| 7525 | // 15218: } |
| 7526 | // 15218: } |
| 7527 | 1, 0, // 15223: case 0x1: { |
| 7528 | OPC_CheckField, 7, 17, 0, // 15225: check Inst[23:7] == 0x0 |
| 7529 | OPC_Scope, 9, // 15229: try { |
| 7530 | OPC_CheckField, 48, 4, 0, // 15231: check Inst[51:48] == 0x0 |
| 7531 | OPC_Decode, 204, 72, 198, 1, // 15235: decode to VSCUNCOTsrrv using decoder 198 |
| 7532 | // 15235: } else try { |
| 7533 | OPC_Decode, 207, 72, 199, 1, // 15240: decode to VSCUNCOTsrrvm using decoder 199 |
| 7534 | // 15240: } |
| 7535 | // 15240: } |
| 7536 | // 15240: } // switch Inst[47] |
| 7537 | // 15240: } |
| 7538 | // 15240: } // switch Inst[39] |
| 7539 | // 15240: } |
| 7540 | 4, 101, // 15245: case 0x4: { |
| 7541 | OPC_SwitchField, 39, 1, // 15247: switch Inst[39] { |
| 7542 | 0, 47, // 15250: case 0x0: { |
| 7543 | OPC_SwitchField, 47, 1, // 15252: switch Inst[47] { |
| 7544 | 0, 20, // 15255: case 0x0: { |
| 7545 | OPC_CheckField, 0, 16, 0, // 15257: check Inst[15:0] == 0x0 |
| 7546 | OPC_Scope, 9, // 15261: try { |
| 7547 | OPC_CheckField, 48, 4, 0, // 15263: check Inst[51:48] == 0x0 |
| 7548 | OPC_Decode, 190, 73, 184, 1, // 15267: decode to VSCUOTvizv using decoder 184 |
| 7549 | // 15267: } else try { |
| 7550 | OPC_Decode, 193, 73, 185, 1, // 15272: decode to VSCUOTvizvm using decoder 185 |
| 7551 | // 15272: } |
| 7552 | // 15272: } |
| 7553 | 1, 0, // 15277: case 0x1: { |
| 7554 | OPC_CheckField, 0, 16, 0, // 15279: check Inst[15:0] == 0x0 |
| 7555 | OPC_Scope, 9, // 15283: try { |
| 7556 | OPC_CheckField, 48, 4, 0, // 15285: check Inst[51:48] == 0x0 |
| 7557 | OPC_Decode, 202, 73, 186, 1, // 15289: decode to VSCUOTvrzv using decoder 186 |
| 7558 | // 15289: } else try { |
| 7559 | OPC_Decode, 205, 73, 187, 1, // 15294: decode to VSCUOTvrzvm using decoder 187 |
| 7560 | // 15294: } |
| 7561 | // 15294: } |
| 7562 | // 15294: } // switch Inst[47] |
| 7563 | // 15294: } |
| 7564 | 1, 0, // 15299: case 0x1: { |
| 7565 | OPC_SwitchField, 47, 1, // 15301: switch Inst[47] { |
| 7566 | 0, 20, // 15304: case 0x0: { |
| 7567 | OPC_CheckField, 0, 16, 0, // 15306: check Inst[15:0] == 0x0 |
| 7568 | OPC_Scope, 9, // 15310: try { |
| 7569 | OPC_CheckField, 48, 4, 0, // 15312: check Inst[51:48] == 0x0 |
| 7570 | OPC_Decode, 184, 73, 188, 1, // 15316: decode to VSCUOTvirv using decoder 188 |
| 7571 | // 15316: } else try { |
| 7572 | OPC_Decode, 187, 73, 189, 1, // 15321: decode to VSCUOTvirvm using decoder 189 |
| 7573 | // 15321: } |
| 7574 | // 15321: } |
| 7575 | 1, 0, // 15326: case 0x1: { |
| 7576 | OPC_CheckField, 0, 16, 0, // 15328: check Inst[15:0] == 0x0 |
| 7577 | OPC_Scope, 9, // 15332: try { |
| 7578 | OPC_CheckField, 48, 4, 0, // 15334: check Inst[51:48] == 0x0 |
| 7579 | OPC_Decode, 196, 73, 190, 1, // 15338: decode to VSCUOTvrrv using decoder 190 |
| 7580 | // 15338: } else try { |
| 7581 | OPC_Decode, 199, 73, 191, 1, // 15343: decode to VSCUOTvrrvm using decoder 191 |
| 7582 | // 15343: } |
| 7583 | // 15343: } |
| 7584 | // 15343: } // switch Inst[47] |
| 7585 | // 15343: } |
| 7586 | // 15343: } // switch Inst[39] |
| 7587 | // 15343: } |
| 7588 | 6, 0, // 15348: case 0x6: { |
| 7589 | OPC_SwitchField, 39, 1, // 15350: switch Inst[39] { |
| 7590 | 0, 47, // 15353: case 0x0: { |
| 7591 | OPC_SwitchField, 47, 1, // 15355: switch Inst[47] { |
| 7592 | 0, 20, // 15358: case 0x0: { |
| 7593 | OPC_CheckField, 7, 17, 0, // 15360: check Inst[23:7] == 0x0 |
| 7594 | OPC_Scope, 9, // 15364: try { |
| 7595 | OPC_CheckField, 48, 4, 0, // 15366: check Inst[51:48] == 0x0 |
| 7596 | OPC_Decode, 166, 73, 192, 1, // 15370: decode to VSCUOTsizv using decoder 192 |
| 7597 | // 15370: } else try { |
| 7598 | OPC_Decode, 169, 73, 193, 1, // 15375: decode to VSCUOTsizvm using decoder 193 |
| 7599 | // 15375: } |
| 7600 | // 15375: } |
| 7601 | 1, 0, // 15380: case 0x1: { |
| 7602 | OPC_CheckField, 7, 17, 0, // 15382: check Inst[23:7] == 0x0 |
| 7603 | OPC_Scope, 9, // 15386: try { |
| 7604 | OPC_CheckField, 48, 4, 0, // 15388: check Inst[51:48] == 0x0 |
| 7605 | OPC_Decode, 178, 73, 194, 1, // 15392: decode to VSCUOTsrzv using decoder 194 |
| 7606 | // 15392: } else try { |
| 7607 | OPC_Decode, 181, 73, 195, 1, // 15397: decode to VSCUOTsrzvm using decoder 195 |
| 7608 | // 15397: } |
| 7609 | // 15397: } |
| 7610 | // 15397: } // switch Inst[47] |
| 7611 | // 15397: } |
| 7612 | 1, 0, // 15402: case 0x1: { |
| 7613 | OPC_SwitchField, 47, 1, // 15404: switch Inst[47] { |
| 7614 | 0, 20, // 15407: case 0x0: { |
| 7615 | OPC_CheckField, 7, 17, 0, // 15409: check Inst[23:7] == 0x0 |
| 7616 | OPC_Scope, 9, // 15413: try { |
| 7617 | OPC_CheckField, 48, 4, 0, // 15415: check Inst[51:48] == 0x0 |
| 7618 | OPC_Decode, 160, 73, 196, 1, // 15419: decode to VSCUOTsirv using decoder 196 |
| 7619 | // 15419: } else try { |
| 7620 | OPC_Decode, 163, 73, 197, 1, // 15424: decode to VSCUOTsirvm using decoder 197 |
| 7621 | // 15424: } |
| 7622 | // 15424: } |
| 7623 | 1, 0, // 15429: case 0x1: { |
| 7624 | OPC_CheckField, 7, 17, 0, // 15431: check Inst[23:7] == 0x0 |
| 7625 | OPC_Scope, 9, // 15435: try { |
| 7626 | OPC_CheckField, 48, 4, 0, // 15437: check Inst[51:48] == 0x0 |
| 7627 | OPC_Decode, 172, 73, 198, 1, // 15441: decode to VSCUOTsrrv using decoder 198 |
| 7628 | // 15441: } else try { |
| 7629 | OPC_Decode, 175, 73, 199, 1, // 15446: decode to VSCUOTsrrvm using decoder 199 |
| 7630 | // 15446: } |
| 7631 | // 15446: } |
| 7632 | // 15446: } // switch Inst[47] |
| 7633 | // 15446: } |
| 7634 | // 15446: } // switch Inst[39] |
| 7635 | // 15446: } |
| 7636 | // 15446: } // switch Inst[54:52] |
| 7637 | // 15446: } |
| 7638 | 230, 2, 159, 3, // 15451: case 0x166: { |
| 7639 | OPC_SwitchField, 52, 3, // 15455: switch Inst[54:52] { |
| 7640 | 0, 101, // 15458: case 0x0: { |
| 7641 | OPC_SwitchField, 39, 1, // 15460: switch Inst[39] { |
| 7642 | 0, 47, // 15463: case 0x0: { |
| 7643 | OPC_SwitchField, 47, 1, // 15465: switch Inst[47] { |
| 7644 | 0, 20, // 15468: case 0x0: { |
| 7645 | OPC_CheckField, 0, 16, 0, // 15470: check Inst[15:0] == 0x0 |
| 7646 | OPC_Scope, 9, // 15474: try { |
| 7647 | OPC_CheckField, 48, 4, 0, // 15476: check Inst[51:48] == 0x0 |
| 7648 | OPC_Decode, 190, 70, 184, 1, // 15480: decode to VSCLNCvizv using decoder 184 |
| 7649 | // 15480: } else try { |
| 7650 | OPC_Decode, 193, 70, 185, 1, // 15485: decode to VSCLNCvizvm using decoder 185 |
| 7651 | // 15485: } |
| 7652 | // 15485: } |
| 7653 | 1, 0, // 15490: case 0x1: { |
| 7654 | OPC_CheckField, 0, 16, 0, // 15492: check Inst[15:0] == 0x0 |
| 7655 | OPC_Scope, 9, // 15496: try { |
| 7656 | OPC_CheckField, 48, 4, 0, // 15498: check Inst[51:48] == 0x0 |
| 7657 | OPC_Decode, 202, 70, 186, 1, // 15502: decode to VSCLNCvrzv using decoder 186 |
| 7658 | // 15502: } else try { |
| 7659 | OPC_Decode, 205, 70, 187, 1, // 15507: decode to VSCLNCvrzvm using decoder 187 |
| 7660 | // 15507: } |
| 7661 | // 15507: } |
| 7662 | // 15507: } // switch Inst[47] |
| 7663 | // 15507: } |
| 7664 | 1, 0, // 15512: case 0x1: { |
| 7665 | OPC_SwitchField, 47, 1, // 15514: switch Inst[47] { |
| 7666 | 0, 20, // 15517: case 0x0: { |
| 7667 | OPC_CheckField, 0, 16, 0, // 15519: check Inst[15:0] == 0x0 |
| 7668 | OPC_Scope, 9, // 15523: try { |
| 7669 | OPC_CheckField, 48, 4, 0, // 15525: check Inst[51:48] == 0x0 |
| 7670 | OPC_Decode, 184, 70, 188, 1, // 15529: decode to VSCLNCvirv using decoder 188 |
| 7671 | // 15529: } else try { |
| 7672 | OPC_Decode, 187, 70, 189, 1, // 15534: decode to VSCLNCvirvm using decoder 189 |
| 7673 | // 15534: } |
| 7674 | // 15534: } |
| 7675 | 1, 0, // 15539: case 0x1: { |
| 7676 | OPC_CheckField, 0, 16, 0, // 15541: check Inst[15:0] == 0x0 |
| 7677 | OPC_Scope, 9, // 15545: try { |
| 7678 | OPC_CheckField, 48, 4, 0, // 15547: check Inst[51:48] == 0x0 |
| 7679 | OPC_Decode, 196, 70, 190, 1, // 15551: decode to VSCLNCvrrv using decoder 190 |
| 7680 | // 15551: } else try { |
| 7681 | OPC_Decode, 199, 70, 191, 1, // 15556: decode to VSCLNCvrrvm using decoder 191 |
| 7682 | // 15556: } |
| 7683 | // 15556: } |
| 7684 | // 15556: } // switch Inst[47] |
| 7685 | // 15556: } |
| 7686 | // 15556: } // switch Inst[39] |
| 7687 | // 15556: } |
| 7688 | 2, 101, // 15561: case 0x2: { |
| 7689 | OPC_SwitchField, 39, 1, // 15563: switch Inst[39] { |
| 7690 | 0, 47, // 15566: case 0x0: { |
| 7691 | OPC_SwitchField, 47, 1, // 15568: switch Inst[47] { |
| 7692 | 0, 20, // 15571: case 0x0: { |
| 7693 | OPC_CheckField, 7, 17, 0, // 15573: check Inst[23:7] == 0x0 |
| 7694 | OPC_Scope, 9, // 15577: try { |
| 7695 | OPC_CheckField, 48, 4, 0, // 15579: check Inst[51:48] == 0x0 |
| 7696 | OPC_Decode, 166, 70, 192, 1, // 15583: decode to VSCLNCsizv using decoder 192 |
| 7697 | // 15583: } else try { |
| 7698 | OPC_Decode, 169, 70, 193, 1, // 15588: decode to VSCLNCsizvm using decoder 193 |
| 7699 | // 15588: } |
| 7700 | // 15588: } |
| 7701 | 1, 0, // 15593: case 0x1: { |
| 7702 | OPC_CheckField, 7, 17, 0, // 15595: check Inst[23:7] == 0x0 |
| 7703 | OPC_Scope, 9, // 15599: try { |
| 7704 | OPC_CheckField, 48, 4, 0, // 15601: check Inst[51:48] == 0x0 |
| 7705 | OPC_Decode, 178, 70, 194, 1, // 15605: decode to VSCLNCsrzv using decoder 194 |
| 7706 | // 15605: } else try { |
| 7707 | OPC_Decode, 181, 70, 195, 1, // 15610: decode to VSCLNCsrzvm using decoder 195 |
| 7708 | // 15610: } |
| 7709 | // 15610: } |
| 7710 | // 15610: } // switch Inst[47] |
| 7711 | // 15610: } |
| 7712 | 1, 0, // 15615: case 0x1: { |
| 7713 | OPC_SwitchField, 47, 1, // 15617: switch Inst[47] { |
| 7714 | 0, 20, // 15620: case 0x0: { |
| 7715 | OPC_CheckField, 7, 17, 0, // 15622: check Inst[23:7] == 0x0 |
| 7716 | OPC_Scope, 9, // 15626: try { |
| 7717 | OPC_CheckField, 48, 4, 0, // 15628: check Inst[51:48] == 0x0 |
| 7718 | OPC_Decode, 160, 70, 196, 1, // 15632: decode to VSCLNCsirv using decoder 196 |
| 7719 | // 15632: } else try { |
| 7720 | OPC_Decode, 163, 70, 197, 1, // 15637: decode to VSCLNCsirvm using decoder 197 |
| 7721 | // 15637: } |
| 7722 | // 15637: } |
| 7723 | 1, 0, // 15642: case 0x1: { |
| 7724 | OPC_CheckField, 7, 17, 0, // 15644: check Inst[23:7] == 0x0 |
| 7725 | OPC_Scope, 9, // 15648: try { |
| 7726 | OPC_CheckField, 48, 4, 0, // 15650: check Inst[51:48] == 0x0 |
| 7727 | OPC_Decode, 172, 70, 198, 1, // 15654: decode to VSCLNCsrrv using decoder 198 |
| 7728 | // 15654: } else try { |
| 7729 | OPC_Decode, 175, 70, 199, 1, // 15659: decode to VSCLNCsrrvm using decoder 199 |
| 7730 | // 15659: } |
| 7731 | // 15659: } |
| 7732 | // 15659: } // switch Inst[47] |
| 7733 | // 15659: } |
| 7734 | // 15659: } // switch Inst[39] |
| 7735 | // 15659: } |
| 7736 | 4, 101, // 15664: case 0x4: { |
| 7737 | OPC_SwitchField, 39, 1, // 15666: switch Inst[39] { |
| 7738 | 0, 47, // 15669: case 0x0: { |
| 7739 | OPC_SwitchField, 47, 1, // 15671: switch Inst[47] { |
| 7740 | 0, 20, // 15674: case 0x0: { |
| 7741 | OPC_CheckField, 0, 16, 0, // 15676: check Inst[15:0] == 0x0 |
| 7742 | OPC_Scope, 9, // 15680: try { |
| 7743 | OPC_CheckField, 48, 4, 0, // 15682: check Inst[51:48] == 0x0 |
| 7744 | OPC_Decode, 158, 71, 184, 1, // 15686: decode to VSCLvizv using decoder 184 |
| 7745 | // 15686: } else try { |
| 7746 | OPC_Decode, 161, 71, 185, 1, // 15691: decode to VSCLvizvm using decoder 185 |
| 7747 | // 15691: } |
| 7748 | // 15691: } |
| 7749 | 1, 0, // 15696: case 0x1: { |
| 7750 | OPC_CheckField, 0, 16, 0, // 15698: check Inst[15:0] == 0x0 |
| 7751 | OPC_Scope, 9, // 15702: try { |
| 7752 | OPC_CheckField, 48, 4, 0, // 15704: check Inst[51:48] == 0x0 |
| 7753 | OPC_Decode, 170, 71, 186, 1, // 15708: decode to VSCLvrzv using decoder 186 |
| 7754 | // 15708: } else try { |
| 7755 | OPC_Decode, 173, 71, 187, 1, // 15713: decode to VSCLvrzvm using decoder 187 |
| 7756 | // 15713: } |
| 7757 | // 15713: } |
| 7758 | // 15713: } // switch Inst[47] |
| 7759 | // 15713: } |
| 7760 | 1, 0, // 15718: case 0x1: { |
| 7761 | OPC_SwitchField, 47, 1, // 15720: switch Inst[47] { |
| 7762 | 0, 20, // 15723: case 0x0: { |
| 7763 | OPC_CheckField, 0, 16, 0, // 15725: check Inst[15:0] == 0x0 |
| 7764 | OPC_Scope, 9, // 15729: try { |
| 7765 | OPC_CheckField, 48, 4, 0, // 15731: check Inst[51:48] == 0x0 |
| 7766 | OPC_Decode, 152, 71, 188, 1, // 15735: decode to VSCLvirv using decoder 188 |
| 7767 | // 15735: } else try { |
| 7768 | OPC_Decode, 155, 71, 189, 1, // 15740: decode to VSCLvirvm using decoder 189 |
| 7769 | // 15740: } |
| 7770 | // 15740: } |
| 7771 | 1, 0, // 15745: case 0x1: { |
| 7772 | OPC_CheckField, 0, 16, 0, // 15747: check Inst[15:0] == 0x0 |
| 7773 | OPC_Scope, 9, // 15751: try { |
| 7774 | OPC_CheckField, 48, 4, 0, // 15753: check Inst[51:48] == 0x0 |
| 7775 | OPC_Decode, 164, 71, 190, 1, // 15757: decode to VSCLvrrv using decoder 190 |
| 7776 | // 15757: } else try { |
| 7777 | OPC_Decode, 167, 71, 191, 1, // 15762: decode to VSCLvrrvm using decoder 191 |
| 7778 | // 15762: } |
| 7779 | // 15762: } |
| 7780 | // 15762: } // switch Inst[47] |
| 7781 | // 15762: } |
| 7782 | // 15762: } // switch Inst[39] |
| 7783 | // 15762: } |
| 7784 | 6, 0, // 15767: case 0x6: { |
| 7785 | OPC_SwitchField, 39, 1, // 15769: switch Inst[39] { |
| 7786 | 0, 47, // 15772: case 0x0: { |
| 7787 | OPC_SwitchField, 47, 1, // 15774: switch Inst[47] { |
| 7788 | 0, 20, // 15777: case 0x0: { |
| 7789 | OPC_CheckField, 7, 17, 0, // 15779: check Inst[23:7] == 0x0 |
| 7790 | OPC_Scope, 9, // 15783: try { |
| 7791 | OPC_CheckField, 48, 4, 0, // 15785: check Inst[51:48] == 0x0 |
| 7792 | OPC_Decode, 134, 71, 192, 1, // 15789: decode to VSCLsizv using decoder 192 |
| 7793 | // 15789: } else try { |
| 7794 | OPC_Decode, 137, 71, 193, 1, // 15794: decode to VSCLsizvm using decoder 193 |
| 7795 | // 15794: } |
| 7796 | // 15794: } |
| 7797 | 1, 0, // 15799: case 0x1: { |
| 7798 | OPC_CheckField, 7, 17, 0, // 15801: check Inst[23:7] == 0x0 |
| 7799 | OPC_Scope, 9, // 15805: try { |
| 7800 | OPC_CheckField, 48, 4, 0, // 15807: check Inst[51:48] == 0x0 |
| 7801 | OPC_Decode, 146, 71, 194, 1, // 15811: decode to VSCLsrzv using decoder 194 |
| 7802 | // 15811: } else try { |
| 7803 | OPC_Decode, 149, 71, 195, 1, // 15816: decode to VSCLsrzvm using decoder 195 |
| 7804 | // 15816: } |
| 7805 | // 15816: } |
| 7806 | // 15816: } // switch Inst[47] |
| 7807 | // 15816: } |
| 7808 | 1, 0, // 15821: case 0x1: { |
| 7809 | OPC_SwitchField, 47, 1, // 15823: switch Inst[47] { |
| 7810 | 0, 20, // 15826: case 0x0: { |
| 7811 | OPC_CheckField, 7, 17, 0, // 15828: check Inst[23:7] == 0x0 |
| 7812 | OPC_Scope, 9, // 15832: try { |
| 7813 | OPC_CheckField, 48, 4, 0, // 15834: check Inst[51:48] == 0x0 |
| 7814 | OPC_Decode, 128, 71, 196, 1, // 15838: decode to VSCLsirv using decoder 196 |
| 7815 | // 15838: } else try { |
| 7816 | OPC_Decode, 131, 71, 197, 1, // 15843: decode to VSCLsirvm using decoder 197 |
| 7817 | // 15843: } |
| 7818 | // 15843: } |
| 7819 | 1, 0, // 15848: case 0x1: { |
| 7820 | OPC_CheckField, 7, 17, 0, // 15850: check Inst[23:7] == 0x0 |
| 7821 | OPC_Scope, 9, // 15854: try { |
| 7822 | OPC_CheckField, 48, 4, 0, // 15856: check Inst[51:48] == 0x0 |
| 7823 | OPC_Decode, 140, 71, 198, 1, // 15860: decode to VSCLsrrv using decoder 198 |
| 7824 | // 15860: } else try { |
| 7825 | OPC_Decode, 143, 71, 199, 1, // 15865: decode to VSCLsrrvm using decoder 199 |
| 7826 | // 15865: } |
| 7827 | // 15865: } |
| 7828 | // 15865: } // switch Inst[47] |
| 7829 | // 15865: } |
| 7830 | // 15865: } // switch Inst[39] |
| 7831 | // 15865: } |
| 7832 | // 15865: } // switch Inst[54:52] |
| 7833 | // 15865: } |
| 7834 | 231, 2, 159, 3, // 15870: case 0x167: { |
| 7835 | OPC_SwitchField, 52, 3, // 15874: switch Inst[54:52] { |
| 7836 | 0, 101, // 15877: case 0x0: { |
| 7837 | OPC_SwitchField, 39, 1, // 15879: switch Inst[39] { |
| 7838 | 0, 47, // 15882: case 0x0: { |
| 7839 | OPC_SwitchField, 47, 1, // 15884: switch Inst[47] { |
| 7840 | 0, 20, // 15887: case 0x0: { |
| 7841 | OPC_CheckField, 0, 16, 0, // 15889: check Inst[15:0] == 0x0 |
| 7842 | OPC_Scope, 9, // 15893: try { |
| 7843 | OPC_CheckField, 48, 4, 0, // 15895: check Inst[51:48] == 0x0 |
| 7844 | OPC_Decode, 142, 70, 184, 1, // 15899: decode to VSCLNCOTvizv using decoder 184 |
| 7845 | // 15899: } else try { |
| 7846 | OPC_Decode, 145, 70, 185, 1, // 15904: decode to VSCLNCOTvizvm using decoder 185 |
| 7847 | // 15904: } |
| 7848 | // 15904: } |
| 7849 | 1, 0, // 15909: case 0x1: { |
| 7850 | OPC_CheckField, 0, 16, 0, // 15911: check Inst[15:0] == 0x0 |
| 7851 | OPC_Scope, 9, // 15915: try { |
| 7852 | OPC_CheckField, 48, 4, 0, // 15917: check Inst[51:48] == 0x0 |
| 7853 | OPC_Decode, 154, 70, 186, 1, // 15921: decode to VSCLNCOTvrzv using decoder 186 |
| 7854 | // 15921: } else try { |
| 7855 | OPC_Decode, 157, 70, 187, 1, // 15926: decode to VSCLNCOTvrzvm using decoder 187 |
| 7856 | // 15926: } |
| 7857 | // 15926: } |
| 7858 | // 15926: } // switch Inst[47] |
| 7859 | // 15926: } |
| 7860 | 1, 0, // 15931: case 0x1: { |
| 7861 | OPC_SwitchField, 47, 1, // 15933: switch Inst[47] { |
| 7862 | 0, 20, // 15936: case 0x0: { |
| 7863 | OPC_CheckField, 0, 16, 0, // 15938: check Inst[15:0] == 0x0 |
| 7864 | OPC_Scope, 9, // 15942: try { |
| 7865 | OPC_CheckField, 48, 4, 0, // 15944: check Inst[51:48] == 0x0 |
| 7866 | OPC_Decode, 136, 70, 188, 1, // 15948: decode to VSCLNCOTvirv using decoder 188 |
| 7867 | // 15948: } else try { |
| 7868 | OPC_Decode, 139, 70, 189, 1, // 15953: decode to VSCLNCOTvirvm using decoder 189 |
| 7869 | // 15953: } |
| 7870 | // 15953: } |
| 7871 | 1, 0, // 15958: case 0x1: { |
| 7872 | OPC_CheckField, 0, 16, 0, // 15960: check Inst[15:0] == 0x0 |
| 7873 | OPC_Scope, 9, // 15964: try { |
| 7874 | OPC_CheckField, 48, 4, 0, // 15966: check Inst[51:48] == 0x0 |
| 7875 | OPC_Decode, 148, 70, 190, 1, // 15970: decode to VSCLNCOTvrrv using decoder 190 |
| 7876 | // 15970: } else try { |
| 7877 | OPC_Decode, 151, 70, 191, 1, // 15975: decode to VSCLNCOTvrrvm using decoder 191 |
| 7878 | // 15975: } |
| 7879 | // 15975: } |
| 7880 | // 15975: } // switch Inst[47] |
| 7881 | // 15975: } |
| 7882 | // 15975: } // switch Inst[39] |
| 7883 | // 15975: } |
| 7884 | 2, 101, // 15980: case 0x2: { |
| 7885 | OPC_SwitchField, 39, 1, // 15982: switch Inst[39] { |
| 7886 | 0, 47, // 15985: case 0x0: { |
| 7887 | OPC_SwitchField, 47, 1, // 15987: switch Inst[47] { |
| 7888 | 0, 20, // 15990: case 0x0: { |
| 7889 | OPC_CheckField, 7, 17, 0, // 15992: check Inst[23:7] == 0x0 |
| 7890 | OPC_Scope, 9, // 15996: try { |
| 7891 | OPC_CheckField, 48, 4, 0, // 15998: check Inst[51:48] == 0x0 |
| 7892 | OPC_Decode, 246, 69, 192, 1, // 16002: decode to VSCLNCOTsizv using decoder 192 |
| 7893 | // 16002: } else try { |
| 7894 | OPC_Decode, 249, 69, 193, 1, // 16007: decode to VSCLNCOTsizvm using decoder 193 |
| 7895 | // 16007: } |
| 7896 | // 16007: } |
| 7897 | 1, 0, // 16012: case 0x1: { |
| 7898 | OPC_CheckField, 7, 17, 0, // 16014: check Inst[23:7] == 0x0 |
| 7899 | OPC_Scope, 9, // 16018: try { |
| 7900 | OPC_CheckField, 48, 4, 0, // 16020: check Inst[51:48] == 0x0 |
| 7901 | OPC_Decode, 130, 70, 194, 1, // 16024: decode to VSCLNCOTsrzv using decoder 194 |
| 7902 | // 16024: } else try { |
| 7903 | OPC_Decode, 133, 70, 195, 1, // 16029: decode to VSCLNCOTsrzvm using decoder 195 |
| 7904 | // 16029: } |
| 7905 | // 16029: } |
| 7906 | // 16029: } // switch Inst[47] |
| 7907 | // 16029: } |
| 7908 | 1, 0, // 16034: case 0x1: { |
| 7909 | OPC_SwitchField, 47, 1, // 16036: switch Inst[47] { |
| 7910 | 0, 20, // 16039: case 0x0: { |
| 7911 | OPC_CheckField, 7, 17, 0, // 16041: check Inst[23:7] == 0x0 |
| 7912 | OPC_Scope, 9, // 16045: try { |
| 7913 | OPC_CheckField, 48, 4, 0, // 16047: check Inst[51:48] == 0x0 |
| 7914 | OPC_Decode, 240, 69, 196, 1, // 16051: decode to VSCLNCOTsirv using decoder 196 |
| 7915 | // 16051: } else try { |
| 7916 | OPC_Decode, 243, 69, 197, 1, // 16056: decode to VSCLNCOTsirvm using decoder 197 |
| 7917 | // 16056: } |
| 7918 | // 16056: } |
| 7919 | 1, 0, // 16061: case 0x1: { |
| 7920 | OPC_CheckField, 7, 17, 0, // 16063: check Inst[23:7] == 0x0 |
| 7921 | OPC_Scope, 9, // 16067: try { |
| 7922 | OPC_CheckField, 48, 4, 0, // 16069: check Inst[51:48] == 0x0 |
| 7923 | OPC_Decode, 252, 69, 198, 1, // 16073: decode to VSCLNCOTsrrv using decoder 198 |
| 7924 | // 16073: } else try { |
| 7925 | OPC_Decode, 255, 69, 199, 1, // 16078: decode to VSCLNCOTsrrvm using decoder 199 |
| 7926 | // 16078: } |
| 7927 | // 16078: } |
| 7928 | // 16078: } // switch Inst[47] |
| 7929 | // 16078: } |
| 7930 | // 16078: } // switch Inst[39] |
| 7931 | // 16078: } |
| 7932 | 4, 101, // 16083: case 0x4: { |
| 7933 | OPC_SwitchField, 39, 1, // 16085: switch Inst[39] { |
| 7934 | 0, 47, // 16088: case 0x0: { |
| 7935 | OPC_SwitchField, 47, 1, // 16090: switch Inst[47] { |
| 7936 | 0, 20, // 16093: case 0x0: { |
| 7937 | OPC_CheckField, 0, 16, 0, // 16095: check Inst[15:0] == 0x0 |
| 7938 | OPC_Scope, 9, // 16099: try { |
| 7939 | OPC_CheckField, 48, 4, 0, // 16101: check Inst[51:48] == 0x0 |
| 7940 | OPC_Decode, 238, 70, 184, 1, // 16105: decode to VSCLOTvizv using decoder 184 |
| 7941 | // 16105: } else try { |
| 7942 | OPC_Decode, 241, 70, 185, 1, // 16110: decode to VSCLOTvizvm using decoder 185 |
| 7943 | // 16110: } |
| 7944 | // 16110: } |
| 7945 | 1, 0, // 16115: case 0x1: { |
| 7946 | OPC_CheckField, 0, 16, 0, // 16117: check Inst[15:0] == 0x0 |
| 7947 | OPC_Scope, 9, // 16121: try { |
| 7948 | OPC_CheckField, 48, 4, 0, // 16123: check Inst[51:48] == 0x0 |
| 7949 | OPC_Decode, 250, 70, 186, 1, // 16127: decode to VSCLOTvrzv using decoder 186 |
| 7950 | // 16127: } else try { |
| 7951 | OPC_Decode, 253, 70, 187, 1, // 16132: decode to VSCLOTvrzvm using decoder 187 |
| 7952 | // 16132: } |
| 7953 | // 16132: } |
| 7954 | // 16132: } // switch Inst[47] |
| 7955 | // 16132: } |
| 7956 | 1, 0, // 16137: case 0x1: { |
| 7957 | OPC_SwitchField, 47, 1, // 16139: switch Inst[47] { |
| 7958 | 0, 20, // 16142: case 0x0: { |
| 7959 | OPC_CheckField, 0, 16, 0, // 16144: check Inst[15:0] == 0x0 |
| 7960 | OPC_Scope, 9, // 16148: try { |
| 7961 | OPC_CheckField, 48, 4, 0, // 16150: check Inst[51:48] == 0x0 |
| 7962 | OPC_Decode, 232, 70, 188, 1, // 16154: decode to VSCLOTvirv using decoder 188 |
| 7963 | // 16154: } else try { |
| 7964 | OPC_Decode, 235, 70, 189, 1, // 16159: decode to VSCLOTvirvm using decoder 189 |
| 7965 | // 16159: } |
| 7966 | // 16159: } |
| 7967 | 1, 0, // 16164: case 0x1: { |
| 7968 | OPC_CheckField, 0, 16, 0, // 16166: check Inst[15:0] == 0x0 |
| 7969 | OPC_Scope, 9, // 16170: try { |
| 7970 | OPC_CheckField, 48, 4, 0, // 16172: check Inst[51:48] == 0x0 |
| 7971 | OPC_Decode, 244, 70, 190, 1, // 16176: decode to VSCLOTvrrv using decoder 190 |
| 7972 | // 16176: } else try { |
| 7973 | OPC_Decode, 247, 70, 191, 1, // 16181: decode to VSCLOTvrrvm using decoder 191 |
| 7974 | // 16181: } |
| 7975 | // 16181: } |
| 7976 | // 16181: } // switch Inst[47] |
| 7977 | // 16181: } |
| 7978 | // 16181: } // switch Inst[39] |
| 7979 | // 16181: } |
| 7980 | 6, 0, // 16186: case 0x6: { |
| 7981 | OPC_SwitchField, 39, 1, // 16188: switch Inst[39] { |
| 7982 | 0, 47, // 16191: case 0x0: { |
| 7983 | OPC_SwitchField, 47, 1, // 16193: switch Inst[47] { |
| 7984 | 0, 20, // 16196: case 0x0: { |
| 7985 | OPC_CheckField, 7, 17, 0, // 16198: check Inst[23:7] == 0x0 |
| 7986 | OPC_Scope, 9, // 16202: try { |
| 7987 | OPC_CheckField, 48, 4, 0, // 16204: check Inst[51:48] == 0x0 |
| 7988 | OPC_Decode, 214, 70, 192, 1, // 16208: decode to VSCLOTsizv using decoder 192 |
| 7989 | // 16208: } else try { |
| 7990 | OPC_Decode, 217, 70, 193, 1, // 16213: decode to VSCLOTsizvm using decoder 193 |
| 7991 | // 16213: } |
| 7992 | // 16213: } |
| 7993 | 1, 0, // 16218: case 0x1: { |
| 7994 | OPC_CheckField, 7, 17, 0, // 16220: check Inst[23:7] == 0x0 |
| 7995 | OPC_Scope, 9, // 16224: try { |
| 7996 | OPC_CheckField, 48, 4, 0, // 16226: check Inst[51:48] == 0x0 |
| 7997 | OPC_Decode, 226, 70, 194, 1, // 16230: decode to VSCLOTsrzv using decoder 194 |
| 7998 | // 16230: } else try { |
| 7999 | OPC_Decode, 229, 70, 195, 1, // 16235: decode to VSCLOTsrzvm using decoder 195 |
| 8000 | // 16235: } |
| 8001 | // 16235: } |
| 8002 | // 16235: } // switch Inst[47] |
| 8003 | // 16235: } |
| 8004 | 1, 0, // 16240: case 0x1: { |
| 8005 | OPC_SwitchField, 47, 1, // 16242: switch Inst[47] { |
| 8006 | 0, 20, // 16245: case 0x0: { |
| 8007 | OPC_CheckField, 7, 17, 0, // 16247: check Inst[23:7] == 0x0 |
| 8008 | OPC_Scope, 9, // 16251: try { |
| 8009 | OPC_CheckField, 48, 4, 0, // 16253: check Inst[51:48] == 0x0 |
| 8010 | OPC_Decode, 208, 70, 196, 1, // 16257: decode to VSCLOTsirv using decoder 196 |
| 8011 | // 16257: } else try { |
| 8012 | OPC_Decode, 211, 70, 197, 1, // 16262: decode to VSCLOTsirvm using decoder 197 |
| 8013 | // 16262: } |
| 8014 | // 16262: } |
| 8015 | 1, 0, // 16267: case 0x1: { |
| 8016 | OPC_CheckField, 7, 17, 0, // 16269: check Inst[23:7] == 0x0 |
| 8017 | OPC_Scope, 9, // 16273: try { |
| 8018 | OPC_CheckField, 48, 4, 0, // 16275: check Inst[51:48] == 0x0 |
| 8019 | OPC_Decode, 220, 70, 198, 1, // 16279: decode to VSCLOTsrrv using decoder 198 |
| 8020 | // 16279: } else try { |
| 8021 | OPC_Decode, 223, 70, 199, 1, // 16284: decode to VSCLOTsrrvm using decoder 199 |
| 8022 | // 16284: } |
| 8023 | // 16284: } |
| 8024 | // 16284: } // switch Inst[47] |
| 8025 | // 16284: } |
| 8026 | // 16284: } // switch Inst[39] |
| 8027 | // 16284: } |
| 8028 | // 16284: } // switch Inst[54:52] |
| 8029 | // 16284: } |
| 8030 | 232, 2, 70, // 16289: case 0x168: { |
| 8031 | OPC_CheckField, 0, 8, 0, // 16292: check Inst[7:0] == 0x0 |
| 8032 | OPC_CheckField, 32, 16, 0, // 16296: check Inst[47:32] == 0x0 |
| 8033 | OPC_CheckField, 52, 3, 0, // 16300: check Inst[54:52] == 0x0 |
| 8034 | OPC_Scope, 40, // 16304: try { |
| 8035 | OPC_SwitchField, 8, 16, // 16306: switch Inst[23:8] { |
| 8036 | 0, 16, // 16309: case 0x0: { |
| 8037 | OPC_Scope, 9, // 16311: try { |
| 8038 | OPC_CheckField, 48, 4, 0, // 16313: check Inst[51:48] == 0x0 |
| 8039 | OPC_Decode, 240, 48, 200, 1, // 16317: decode to VFMKLna using decoder 200 |
| 8040 | // 16317: } else try { |
| 8041 | OPC_Decode, 243, 48, 201, 1, // 16322: decode to VFMKLnam using decoder 201 |
| 8042 | // 16322: } |
| 8043 | // 16322: } |
| 8044 | 128, 30, 0, // 16327: case 0xf00: { |
| 8045 | OPC_Scope, 9, // 16330: try { |
| 8046 | OPC_CheckField, 48, 4, 0, // 16332: check Inst[51:48] == 0x0 |
| 8047 | OPC_Decode, 234, 48, 200, 1, // 16336: decode to VFMKLa using decoder 200 |
| 8048 | // 16336: } else try { |
| 8049 | OPC_Decode, 237, 48, 201, 1, // 16341: decode to VFMKLam using decoder 201 |
| 8050 | // 16341: } |
| 8051 | // 16341: } |
| 8052 | // 16341: } // switch Inst[23:8] |
| 8053 | OPC_Scope, 9, // 16346: } else try { |
| 8054 | OPC_CheckField, 48, 4, 0, // 16348: check Inst[51:48] == 0x0 |
| 8055 | OPC_Decode, 246, 48, 202, 1, // 16352: decode to VFMKLv using decoder 202 |
| 8056 | // 16352: } else try { |
| 8057 | OPC_Decode, 249, 48, 203, 1, // 16357: decode to VFMKLvm using decoder 203 |
| 8058 | // 16357: } |
| 8059 | // 16357: } |
| 8060 | 234, 2, 70, // 16362: case 0x16a: { |
| 8061 | OPC_CheckField, 0, 8, 0, // 16365: check Inst[7:0] == 0x0 |
| 8062 | OPC_CheckField, 32, 16, 0, // 16369: check Inst[47:32] == 0x0 |
| 8063 | OPC_CheckField, 52, 3, 0, // 16373: check Inst[54:52] == 0x0 |
| 8064 | OPC_Scope, 40, // 16377: try { |
| 8065 | OPC_SwitchField, 8, 16, // 16379: switch Inst[23:8] { |
| 8066 | 0, 16, // 16382: case 0x0: { |
| 8067 | OPC_Scope, 9, // 16384: try { |
| 8068 | OPC_CheckField, 48, 4, 0, // 16386: check Inst[51:48] == 0x0 |
| 8069 | OPC_Decode, 148, 49, 200, 1, // 16390: decode to VFMKWna using decoder 200 |
| 8070 | // 16390: } else try { |
| 8071 | OPC_Decode, 151, 49, 201, 1, // 16395: decode to VFMKWnam using decoder 201 |
| 8072 | // 16395: } |
| 8073 | // 16395: } |
| 8074 | 128, 30, 0, // 16400: case 0xf00: { |
| 8075 | OPC_Scope, 9, // 16403: try { |
| 8076 | OPC_CheckField, 48, 4, 0, // 16405: check Inst[51:48] == 0x0 |
| 8077 | OPC_Decode, 142, 49, 200, 1, // 16409: decode to VFMKWa using decoder 200 |
| 8078 | // 16409: } else try { |
| 8079 | OPC_Decode, 145, 49, 201, 1, // 16414: decode to VFMKWam using decoder 201 |
| 8080 | // 16414: } |
| 8081 | // 16414: } |
| 8082 | // 16414: } // switch Inst[23:8] |
| 8083 | OPC_Scope, 9, // 16419: } else try { |
| 8084 | OPC_CheckField, 48, 4, 0, // 16421: check Inst[51:48] == 0x0 |
| 8085 | OPC_Decode, 154, 49, 202, 1, // 16425: decode to VFMKWv using decoder 202 |
| 8086 | // 16425: } else try { |
| 8087 | OPC_Decode, 157, 49, 203, 1, // 16430: decode to VFMKWvm using decoder 203 |
| 8088 | // 16430: } |
| 8089 | // 16430: } |
| 8090 | 235, 2, 70, // 16435: case 0x16b: { |
| 8091 | OPC_CheckField, 0, 8, 0, // 16438: check Inst[7:0] == 0x0 |
| 8092 | OPC_CheckField, 32, 16, 0, // 16442: check Inst[47:32] == 0x0 |
| 8093 | OPC_CheckField, 52, 3, 0, // 16446: check Inst[54:52] == 0x0 |
| 8094 | OPC_Scope, 40, // 16450: try { |
| 8095 | OPC_SwitchField, 8, 16, // 16452: switch Inst[23:8] { |
| 8096 | 0, 16, // 16455: case 0x0: { |
| 8097 | OPC_Scope, 9, // 16457: try { |
| 8098 | OPC_CheckField, 48, 4, 0, // 16459: check Inst[51:48] == 0x0 |
| 8099 | OPC_Decode, 211, 18, 200, 1, // 16463: decode to PVFMKWUPna using decoder 200 |
| 8100 | // 16463: } else try { |
| 8101 | OPC_Decode, 214, 18, 201, 1, // 16468: decode to PVFMKWUPnam using decoder 201 |
| 8102 | // 16468: } |
| 8103 | // 16468: } |
| 8104 | 128, 30, 0, // 16473: case 0xf00: { |
| 8105 | OPC_Scope, 9, // 16476: try { |
| 8106 | OPC_CheckField, 48, 4, 0, // 16478: check Inst[51:48] == 0x0 |
| 8107 | OPC_Decode, 205, 18, 200, 1, // 16482: decode to PVFMKWUPa using decoder 200 |
| 8108 | // 16482: } else try { |
| 8109 | OPC_Decode, 208, 18, 201, 1, // 16487: decode to PVFMKWUPam using decoder 201 |
| 8110 | // 16487: } |
| 8111 | // 16487: } |
| 8112 | // 16487: } // switch Inst[23:8] |
| 8113 | OPC_Scope, 9, // 16492: } else try { |
| 8114 | OPC_CheckField, 48, 4, 0, // 16494: check Inst[51:48] == 0x0 |
| 8115 | OPC_Decode, 217, 18, 202, 1, // 16498: decode to PVFMKWUPv using decoder 202 |
| 8116 | // 16498: } else try { |
| 8117 | OPC_Decode, 220, 18, 203, 1, // 16503: decode to PVFMKWUPvm using decoder 203 |
| 8118 | // 16503: } |
| 8119 | // 16503: } |
| 8120 | 236, 2, 139, 1, // 16508: case 0x16c: { |
| 8121 | OPC_SwitchField, 52, 3, // 16512: switch Inst[54:52] { |
| 8122 | 0, 66, // 16515: case 0x0: { |
| 8123 | OPC_CheckField, 0, 8, 0, // 16517: check Inst[7:0] == 0x0 |
| 8124 | OPC_CheckField, 32, 16, 0, // 16521: check Inst[47:32] == 0x0 |
| 8125 | OPC_Scope, 40, // 16525: try { |
| 8126 | OPC_SwitchField, 8, 16, // 16527: switch Inst[23:8] { |
| 8127 | 0, 16, // 16530: case 0x0: { |
| 8128 | OPC_Scope, 9, // 16532: try { |
| 8129 | OPC_CheckField, 48, 4, 0, // 16534: check Inst[51:48] == 0x0 |
| 8130 | OPC_Decode, 222, 48, 200, 1, // 16538: decode to VFMKDna using decoder 200 |
| 8131 | // 16538: } else try { |
| 8132 | OPC_Decode, 225, 48, 201, 1, // 16543: decode to VFMKDnam using decoder 201 |
| 8133 | // 16543: } |
| 8134 | // 16543: } |
| 8135 | 128, 30, 0, // 16548: case 0xf00: { |
| 8136 | OPC_Scope, 9, // 16551: try { |
| 8137 | OPC_CheckField, 48, 4, 0, // 16553: check Inst[51:48] == 0x0 |
| 8138 | OPC_Decode, 216, 48, 200, 1, // 16557: decode to VFMKDa using decoder 200 |
| 8139 | // 16557: } else try { |
| 8140 | OPC_Decode, 219, 48, 201, 1, // 16562: decode to VFMKDam using decoder 201 |
| 8141 | // 16562: } |
| 8142 | // 16562: } |
| 8143 | // 16562: } // switch Inst[23:8] |
| 8144 | OPC_Scope, 9, // 16567: } else try { |
| 8145 | OPC_CheckField, 48, 4, 0, // 16569: check Inst[51:48] == 0x0 |
| 8146 | OPC_Decode, 228, 48, 202, 1, // 16573: decode to VFMKDv using decoder 202 |
| 8147 | // 16573: } else try { |
| 8148 | OPC_Decode, 231, 48, 203, 1, // 16578: decode to VFMKDvm using decoder 203 |
| 8149 | // 16578: } |
| 8150 | // 16578: } |
| 8151 | 4, 0, // 16583: case 0x4: { |
| 8152 | OPC_CheckField, 0, 8, 0, // 16585: check Inst[7:0] == 0x0 |
| 8153 | OPC_CheckField, 32, 16, 0, // 16589: check Inst[47:32] == 0x0 |
| 8154 | OPC_Scope, 40, // 16593: try { |
| 8155 | OPC_SwitchField, 8, 16, // 16595: switch Inst[23:8] { |
| 8156 | 0, 16, // 16598: case 0x0: { |
| 8157 | OPC_Scope, 9, // 16600: try { |
| 8158 | OPC_CheckField, 48, 4, 0, // 16602: check Inst[51:48] == 0x0 |
| 8159 | OPC_Decode, 157, 18, 200, 1, // 16606: decode to PVFMKSLOna using decoder 200 |
| 8160 | // 16606: } else try { |
| 8161 | OPC_Decode, 160, 18, 201, 1, // 16611: decode to PVFMKSLOnam using decoder 201 |
| 8162 | // 16611: } |
| 8163 | // 16611: } |
| 8164 | 128, 30, 0, // 16616: case 0xf00: { |
| 8165 | OPC_Scope, 9, // 16619: try { |
| 8166 | OPC_CheckField, 48, 4, 0, // 16621: check Inst[51:48] == 0x0 |
| 8167 | OPC_Decode, 151, 18, 200, 1, // 16625: decode to PVFMKSLOa using decoder 200 |
| 8168 | // 16625: } else try { |
| 8169 | OPC_Decode, 154, 18, 201, 1, // 16630: decode to PVFMKSLOam using decoder 201 |
| 8170 | // 16630: } |
| 8171 | // 16630: } |
| 8172 | // 16630: } // switch Inst[23:8] |
| 8173 | OPC_Scope, 9, // 16635: } else try { |
| 8174 | OPC_CheckField, 48, 4, 0, // 16637: check Inst[51:48] == 0x0 |
| 8175 | OPC_Decode, 163, 18, 202, 1, // 16641: decode to PVFMKSLOv using decoder 202 |
| 8176 | // 16641: } else try { |
| 8177 | OPC_Decode, 166, 18, 203, 1, // 16646: decode to PVFMKSLOvm using decoder 203 |
| 8178 | // 16646: } |
| 8179 | // 16646: } |
| 8180 | // 16646: } // switch Inst[54:52] |
| 8181 | // 16646: } |
| 8182 | 237, 2, 70, // 16651: case 0x16d: { |
| 8183 | OPC_CheckField, 0, 8, 0, // 16654: check Inst[7:0] == 0x0 |
| 8184 | OPC_CheckField, 32, 16, 0, // 16658: check Inst[47:32] == 0x0 |
| 8185 | OPC_CheckField, 52, 3, 0, // 16662: check Inst[54:52] == 0x0 |
| 8186 | OPC_Scope, 40, // 16666: try { |
| 8187 | OPC_SwitchField, 8, 16, // 16668: switch Inst[23:8] { |
| 8188 | 0, 16, // 16671: case 0x0: { |
| 8189 | OPC_Scope, 9, // 16673: try { |
| 8190 | OPC_CheckField, 48, 4, 0, // 16675: check Inst[51:48] == 0x0 |
| 8191 | OPC_Decode, 175, 18, 200, 1, // 16679: decode to PVFMKSUPna using decoder 200 |
| 8192 | // 16679: } else try { |
| 8193 | OPC_Decode, 178, 18, 201, 1, // 16684: decode to PVFMKSUPnam using decoder 201 |
| 8194 | // 16684: } |
| 8195 | // 16684: } |
| 8196 | 128, 30, 0, // 16689: case 0xf00: { |
| 8197 | OPC_Scope, 9, // 16692: try { |
| 8198 | OPC_CheckField, 48, 4, 0, // 16694: check Inst[51:48] == 0x0 |
| 8199 | OPC_Decode, 169, 18, 200, 1, // 16698: decode to PVFMKSUPa using decoder 200 |
| 8200 | // 16698: } else try { |
| 8201 | OPC_Decode, 172, 18, 201, 1, // 16703: decode to PVFMKSUPam using decoder 201 |
| 8202 | // 16703: } |
| 8203 | // 16703: } |
| 8204 | // 16703: } // switch Inst[23:8] |
| 8205 | OPC_Scope, 9, // 16708: } else try { |
| 8206 | OPC_CheckField, 48, 4, 0, // 16710: check Inst[51:48] == 0x0 |
| 8207 | OPC_Decode, 181, 18, 202, 1, // 16714: decode to PVFMKSUPv using decoder 202 |
| 8208 | // 16714: } else try { |
| 8209 | OPC_Decode, 184, 18, 203, 1, // 16719: decode to PVFMKSUPvm using decoder 203 |
| 8210 | // 16719: } |
| 8211 | // 16719: } |
| 8212 | 238, 2, 57, // 16724: case 0x16e: { |
| 8213 | OPC_SwitchField, 39, 1, // 16727: switch Inst[39] { |
| 8214 | 0, 25, // 16730: case 0x0: { |
| 8215 | OPC_SwitchField, 47, 8, // 16732: switch Inst[54:47] { |
| 8216 | 0, 9, // 16735: case 0x0: { |
| 8217 | OPC_CheckField, 0, 24, 0, // 16737: check Inst[23:0] == 0x0 |
| 8218 | OPC_Decode, 183, 6, 204, 1, // 16741: decode to LVMim using decoder 204 |
| 8219 | // 16741: } |
| 8220 | 1, 0, // 16746: case 0x1: { |
| 8221 | OPC_CheckField, 0, 24, 0, // 16748: check Inst[23:0] == 0x0 |
| 8222 | OPC_Decode, 187, 6, 205, 1, // 16752: decode to LVMrm using decoder 205 |
| 8223 | // 16752: } |
| 8224 | // 16752: } // switch Inst[54:47] |
| 8225 | // 16752: } |
| 8226 | 1, 0, // 16757: case 0x1: { |
| 8227 | OPC_SwitchField, 47, 8, // 16759: switch Inst[54:47] { |
| 8228 | 0, 9, // 16762: case 0x0: { |
| 8229 | OPC_CheckField, 0, 24, 0, // 16764: check Inst[23:0] == 0x0 |
| 8230 | OPC_Decode, 185, 6, 206, 1, // 16768: decode to LVMir using decoder 206 |
| 8231 | // 16768: } |
| 8232 | 1, 0, // 16773: case 0x1: { |
| 8233 | OPC_CheckField, 0, 24, 0, // 16775: check Inst[23:0] == 0x0 |
| 8234 | OPC_Decode, 189, 6, 207, 1, // 16779: decode to LVMrr using decoder 207 |
| 8235 | // 16779: } |
| 8236 | // 16779: } // switch Inst[54:47] |
| 8237 | // 16779: } |
| 8238 | // 16779: } // switch Inst[39] |
| 8239 | // 16779: } |
| 8240 | 240, 2, 26, // 16784: case 0x170: { |
| 8241 | OPC_CheckField, 0, 16, 0, // 16787: check Inst[15:0] == 0x0 |
| 8242 | OPC_CheckField, 32, 16, 0, // 16791: check Inst[47:32] == 0x0 |
| 8243 | OPC_CheckField, 52, 3, 0, // 16795: check Inst[54:52] == 0x0 |
| 8244 | OPC_Scope, 8, // 16799: try { |
| 8245 | OPC_CheckField, 48, 4, 0, // 16801: check Inst[51:48] == 0x0 |
| 8246 | OPC_Decode, 204, 39, 119, // 16805: decode to VCVTDLv using decoder 119 |
| 8247 | // 16805: } else try { |
| 8248 | OPC_Decode, 210, 39, 120, // 16809: decode to VCVTDLvm using decoder 120 |
| 8249 | // 16809: } |
| 8250 | // 16809: } |
| 8251 | 242, 2, 174, 1, // 16813: case 0x172: { |
| 8252 | OPC_SwitchField, 52, 3, // 16817: switch Inst[54:52] { |
| 8253 | 0, 22, // 16820: case 0x0: { |
| 8254 | OPC_CheckField, 0, 8, 0, // 16822: check Inst[7:0] == 0x0 |
| 8255 | OPC_CheckField, 32, 16, 0, // 16826: check Inst[47:32] == 0x0 |
| 8256 | OPC_Scope, 8, // 16830: try { |
| 8257 | OPC_CheckField, 48, 4, 0, // 16832: check Inst[51:48] == 0x0 |
| 8258 | OPC_Decode, 144, 39, 121, // 16836: decode to VCMPULvv using decoder 121 |
| 8259 | // 16836: } else try { |
| 8260 | OPC_Decode, 150, 39, 122, // 16840: decode to VCMPULvvm using decoder 122 |
| 8261 | // 16840: } |
| 8262 | // 16840: } |
| 8263 | 2, 60, // 16844: case 0x2: { |
| 8264 | OPC_SwitchField, 47, 1, // 16846: switch Inst[47] { |
| 8265 | 0, 26, // 16849: case 0x0: { |
| 8266 | OPC_CheckField, 0, 8, 0, // 16851: check Inst[7:0] == 0x0 |
| 8267 | OPC_CheckField, 16, 8, 0, // 16855: check Inst[23:16] == 0x0 |
| 8268 | OPC_CheckField, 32, 8, 0, // 16859: check Inst[39:32] == 0x0 |
| 8269 | OPC_Scope, 8, // 16863: try { |
| 8270 | OPC_CheckField, 48, 4, 0, // 16865: check Inst[51:48] == 0x0 |
| 8271 | OPC_Decode, 248, 38, 123, // 16869: decode to VCMPULiv using decoder 123 |
| 8272 | // 16869: } else try { |
| 8273 | OPC_Decode, 254, 38, 124, // 16873: decode to VCMPULivm using decoder 124 |
| 8274 | // 16873: } |
| 8275 | // 16873: } |
| 8276 | 1, 0, // 16877: case 0x1: { |
| 8277 | OPC_CheckField, 0, 8, 0, // 16879: check Inst[7:0] == 0x0 |
| 8278 | OPC_CheckField, 16, 8, 0, // 16883: check Inst[23:16] == 0x0 |
| 8279 | OPC_CheckField, 32, 8, 0, // 16887: check Inst[39:32] == 0x0 |
| 8280 | OPC_Scope, 8, // 16891: try { |
| 8281 | OPC_CheckField, 48, 4, 0, // 16893: check Inst[51:48] == 0x0 |
| 8282 | OPC_Decode, 132, 39, 127, // 16897: decode to VCMPULrv using decoder 127 |
| 8283 | // 16897: } else try { |
| 8284 | OPC_Decode, 138, 39, 128, 1, // 16901: decode to VCMPULrvm using decoder 128 |
| 8285 | // 16901: } |
| 8286 | // 16901: } |
| 8287 | // 16901: } // switch Inst[47] |
| 8288 | // 16901: } |
| 8289 | 4, 22, // 16906: case 0x4: { |
| 8290 | OPC_CheckField, 0, 8, 0, // 16908: check Inst[7:0] == 0x0 |
| 8291 | OPC_CheckField, 32, 16, 0, // 16912: check Inst[47:32] == 0x0 |
| 8292 | OPC_Scope, 8, // 16916: try { |
| 8293 | OPC_CheckField, 48, 4, 0, // 16918: check Inst[51:48] == 0x0 |
| 8294 | OPC_Decode, 171, 11, 121, // 16922: decode to PVCMPULOvv using decoder 121 |
| 8295 | // 16922: } else try { |
| 8296 | OPC_Decode, 177, 11, 122, // 16926: decode to PVCMPULOvvm using decoder 122 |
| 8297 | // 16926: } |
| 8298 | // 16926: } |
| 8299 | 6, 0, // 16930: case 0x6: { |
| 8300 | OPC_SwitchField, 47, 1, // 16932: switch Inst[47] { |
| 8301 | 0, 26, // 16935: case 0x0: { |
| 8302 | OPC_CheckField, 0, 8, 0, // 16937: check Inst[7:0] == 0x0 |
| 8303 | OPC_CheckField, 16, 8, 0, // 16941: check Inst[23:16] == 0x0 |
| 8304 | OPC_CheckField, 32, 8, 0, // 16945: check Inst[39:32] == 0x0 |
| 8305 | OPC_Scope, 8, // 16949: try { |
| 8306 | OPC_CheckField, 48, 4, 0, // 16951: check Inst[51:48] == 0x0 |
| 8307 | OPC_Decode, 147, 11, 123, // 16955: decode to PVCMPULOiv using decoder 123 |
| 8308 | // 16955: } else try { |
| 8309 | OPC_Decode, 153, 11, 124, // 16959: decode to PVCMPULOivm using decoder 124 |
| 8310 | // 16959: } |
| 8311 | // 16959: } |
| 8312 | 1, 0, // 16963: case 0x1: { |
| 8313 | OPC_CheckField, 0, 8, 0, // 16965: check Inst[7:0] == 0x0 |
| 8314 | OPC_CheckField, 16, 8, 0, // 16969: check Inst[23:16] == 0x0 |
| 8315 | OPC_CheckField, 32, 8, 0, // 16973: check Inst[39:32] == 0x0 |
| 8316 | OPC_Scope, 8, // 16977: try { |
| 8317 | OPC_CheckField, 48, 4, 0, // 16979: check Inst[51:48] == 0x0 |
| 8318 | OPC_Decode, 159, 11, 125, // 16983: decode to PVCMPULOrv using decoder 125 |
| 8319 | // 16983: } else try { |
| 8320 | OPC_Decode, 165, 11, 126, // 16987: decode to PVCMPULOrvm using decoder 126 |
| 8321 | // 16987: } |
| 8322 | // 16987: } |
| 8323 | // 16987: } // switch Inst[47] |
| 8324 | // 16987: } |
| 8325 | // 16987: } // switch Inst[54:52] |
| 8326 | // 16987: } |
| 8327 | 243, 2, 177, 1, // 16991: case 0x173: { |
| 8328 | OPC_SwitchField, 52, 3, // 16995: switch Inst[54:52] { |
| 8329 | 0, 22, // 16998: case 0x0: { |
| 8330 | OPC_CheckField, 0, 8, 0, // 17000: check Inst[7:0] == 0x0 |
| 8331 | OPC_CheckField, 32, 16, 0, // 17004: check Inst[47:32] == 0x0 |
| 8332 | OPC_Scope, 8, // 17008: try { |
| 8333 | OPC_CheckField, 48, 4, 0, // 17010: check Inst[51:48] == 0x0 |
| 8334 | OPC_Decode, 207, 11, 121, // 17014: decode to PVCMPUUPvv using decoder 121 |
| 8335 | // 17014: } else try { |
| 8336 | OPC_Decode, 213, 11, 122, // 17018: decode to PVCMPUUPvvm using decoder 122 |
| 8337 | // 17018: } |
| 8338 | // 17018: } |
| 8339 | 2, 60, // 17022: case 0x2: { |
| 8340 | OPC_SwitchField, 47, 1, // 17024: switch Inst[47] { |
| 8341 | 0, 26, // 17027: case 0x0: { |
| 8342 | OPC_CheckField, 0, 8, 0, // 17029: check Inst[7:0] == 0x0 |
| 8343 | OPC_CheckField, 16, 8, 0, // 17033: check Inst[23:16] == 0x0 |
| 8344 | OPC_CheckField, 32, 8, 0, // 17037: check Inst[39:32] == 0x0 |
| 8345 | OPC_Scope, 8, // 17041: try { |
| 8346 | OPC_CheckField, 48, 4, 0, // 17043: check Inst[51:48] == 0x0 |
| 8347 | OPC_Decode, 183, 11, 123, // 17047: decode to PVCMPUUPiv using decoder 123 |
| 8348 | // 17047: } else try { |
| 8349 | OPC_Decode, 189, 11, 124, // 17051: decode to PVCMPUUPivm using decoder 124 |
| 8350 | // 17051: } |
| 8351 | // 17051: } |
| 8352 | 1, 0, // 17055: case 0x1: { |
| 8353 | OPC_CheckField, 0, 8, 0, // 17057: check Inst[7:0] == 0x0 |
| 8354 | OPC_CheckField, 16, 8, 0, // 17061: check Inst[23:16] == 0x0 |
| 8355 | OPC_CheckField, 32, 8, 0, // 17065: check Inst[39:32] == 0x0 |
| 8356 | OPC_Scope, 8, // 17069: try { |
| 8357 | OPC_CheckField, 48, 4, 0, // 17071: check Inst[51:48] == 0x0 |
| 8358 | OPC_Decode, 195, 11, 127, // 17075: decode to PVCMPUUPrv using decoder 127 |
| 8359 | // 17075: } else try { |
| 8360 | OPC_Decode, 201, 11, 128, 1, // 17079: decode to PVCMPUUPrvm using decoder 128 |
| 8361 | // 17079: } |
| 8362 | // 17079: } |
| 8363 | // 17079: } // switch Inst[47] |
| 8364 | // 17079: } |
| 8365 | 4, 23, // 17084: case 0x4: { |
| 8366 | OPC_CheckField, 0, 8, 0, // 17086: check Inst[7:0] == 0x0 |
| 8367 | OPC_CheckField, 32, 16, 0, // 17090: check Inst[47:32] == 0x0 |
| 8368 | OPC_Scope, 8, // 17094: try { |
| 8369 | OPC_CheckField, 48, 4, 0, // 17096: check Inst[51:48] == 0x0 |
| 8370 | OPC_Decode, 243, 11, 121, // 17100: decode to PVCMPUvv using decoder 121 |
| 8371 | // 17100: } else try { |
| 8372 | OPC_Decode, 249, 11, 129, 1, // 17104: decode to PVCMPUvvm using decoder 129 |
| 8373 | // 17104: } |
| 8374 | // 17104: } |
| 8375 | 6, 0, // 17109: case 0x6: { |
| 8376 | OPC_SwitchField, 47, 1, // 17111: switch Inst[47] { |
| 8377 | 0, 27, // 17114: case 0x0: { |
| 8378 | OPC_CheckField, 0, 8, 0, // 17116: check Inst[7:0] == 0x0 |
| 8379 | OPC_CheckField, 16, 8, 0, // 17120: check Inst[23:16] == 0x0 |
| 8380 | OPC_CheckField, 32, 8, 0, // 17124: check Inst[39:32] == 0x0 |
| 8381 | OPC_Scope, 8, // 17128: try { |
| 8382 | OPC_CheckField, 48, 4, 0, // 17130: check Inst[51:48] == 0x0 |
| 8383 | OPC_Decode, 219, 11, 123, // 17134: decode to PVCMPUiv using decoder 123 |
| 8384 | // 17134: } else try { |
| 8385 | OPC_Decode, 225, 11, 130, 1, // 17138: decode to PVCMPUivm using decoder 130 |
| 8386 | // 17138: } |
| 8387 | // 17138: } |
| 8388 | 1, 0, // 17143: case 0x1: { |
| 8389 | OPC_CheckField, 0, 8, 0, // 17145: check Inst[7:0] == 0x0 |
| 8390 | OPC_CheckField, 16, 8, 0, // 17149: check Inst[23:16] == 0x0 |
| 8391 | OPC_CheckField, 32, 8, 0, // 17153: check Inst[39:32] == 0x0 |
| 8392 | OPC_Scope, 8, // 17157: try { |
| 8393 | OPC_CheckField, 48, 4, 0, // 17159: check Inst[51:48] == 0x0 |
| 8394 | OPC_Decode, 231, 11, 127, // 17163: decode to PVCMPUrv using decoder 127 |
| 8395 | // 17163: } else try { |
| 8396 | OPC_Decode, 237, 11, 131, 1, // 17167: decode to PVCMPUrvm using decoder 131 |
| 8397 | // 17167: } |
| 8398 | // 17167: } |
| 8399 | // 17167: } // switch Inst[47] |
| 8400 | // 17167: } |
| 8401 | // 17167: } // switch Inst[54:52] |
| 8402 | // 17167: } |
| 8403 | 244, 2, 93, // 17172: case 0x174: { |
| 8404 | OPC_SwitchField, 47, 1, // 17175: switch Inst[47] { |
| 8405 | 0, 55, // 17178: case 0x0: { |
| 8406 | OPC_SwitchField, 52, 3, // 17180: switch Inst[54:52] { |
| 8407 | 0, 22, // 17183: case 0x0: { |
| 8408 | OPC_CheckField, 0, 8, 0, // 17185: check Inst[7:0] == 0x0 |
| 8409 | OPC_CheckField, 32, 15, 0, // 17189: check Inst[46:32] == 0x0 |
| 8410 | OPC_Scope, 8, // 17193: try { |
| 8411 | OPC_CheckField, 48, 4, 0, // 17195: check Inst[51:48] == 0x0 |
| 8412 | OPC_Decode, 164, 38, 121, // 17199: decode to VCMPSLvv using decoder 121 |
| 8413 | // 17199: } else try { |
| 8414 | OPC_Decode, 170, 38, 122, // 17203: decode to VCMPSLvvm using decoder 122 |
| 8415 | // 17203: } |
| 8416 | // 17203: } |
| 8417 | 2, 0, // 17207: case 0x2: { |
| 8418 | OPC_CheckField, 0, 8, 0, // 17209: check Inst[7:0] == 0x0 |
| 8419 | OPC_CheckField, 16, 8, 0, // 17213: check Inst[23:16] == 0x0 |
| 8420 | OPC_CheckField, 32, 8, 0, // 17217: check Inst[39:32] == 0x0 |
| 8421 | OPC_Scope, 8, // 17221: try { |
| 8422 | OPC_CheckField, 48, 4, 0, // 17223: check Inst[51:48] == 0x0 |
| 8423 | OPC_Decode, 140, 38, 123, // 17227: decode to VCMPSLiv using decoder 123 |
| 8424 | // 17227: } else try { |
| 8425 | OPC_Decode, 146, 38, 124, // 17231: decode to VCMPSLivm using decoder 124 |
| 8426 | // 17231: } |
| 8427 | // 17231: } |
| 8428 | // 17231: } // switch Inst[54:52] |
| 8429 | // 17231: } |
| 8430 | 1, 0, // 17235: case 0x1: { |
| 8431 | OPC_CheckField, 0, 8, 0, // 17237: check Inst[7:0] == 0x0 |
| 8432 | OPC_CheckField, 16, 8, 0, // 17241: check Inst[23:16] == 0x0 |
| 8433 | OPC_CheckField, 32, 8, 0, // 17245: check Inst[39:32] == 0x0 |
| 8434 | OPC_CheckField, 52, 3, 2, // 17249: check Inst[54:52] == 0x2 |
| 8435 | OPC_Scope, 8, // 17253: try { |
| 8436 | OPC_CheckField, 48, 4, 0, // 17255: check Inst[51:48] == 0x0 |
| 8437 | OPC_Decode, 152, 38, 127, // 17259: decode to VCMPSLrv using decoder 127 |
| 8438 | // 17259: } else try { |
| 8439 | OPC_Decode, 158, 38, 128, 1, // 17263: decode to VCMPSLrvm using decoder 128 |
| 8440 | // 17263: } |
| 8441 | // 17263: } |
| 8442 | // 17263: } // switch Inst[47] |
| 8443 | // 17263: } |
| 8444 | 246, 2, 195, 1, // 17268: case 0x176: { |
| 8445 | OPC_SwitchField, 52, 3, // 17272: switch Inst[54:52] { |
| 8446 | 0, 22, // 17275: case 0x0: { |
| 8447 | OPC_CheckField, 0, 16, 0, // 17277: check Inst[15:0] == 0x0 |
| 8448 | OPC_CheckField, 32, 16, 0, // 17281: check Inst[47:32] == 0x0 |
| 8449 | OPC_Scope, 8, // 17285: try { |
| 8450 | OPC_CheckField, 48, 4, 0, // 17287: check Inst[51:48] == 0x0 |
| 8451 | OPC_Decode, 176, 68, 119, // 17291: decode to VRMAXSWFSTSXv using decoder 119 |
| 8452 | // 17291: } else try { |
| 8453 | OPC_Decode, 182, 68, 120, // 17295: decode to VRMAXSWFSTSXvm using decoder 120 |
| 8454 | // 17295: } |
| 8455 | // 17295: } |
| 8456 | 1, 22, // 17299: case 0x1: { |
| 8457 | OPC_CheckField, 0, 16, 0, // 17301: check Inst[15:0] == 0x0 |
| 8458 | OPC_CheckField, 32, 16, 0, // 17305: check Inst[47:32] == 0x0 |
| 8459 | OPC_Scope, 8, // 17309: try { |
| 8460 | OPC_CheckField, 48, 4, 0, // 17311: check Inst[51:48] == 0x0 |
| 8461 | OPC_Decode, 248, 68, 119, // 17315: decode to VRMINSWFSTSXv using decoder 119 |
| 8462 | // 17315: } else try { |
| 8463 | OPC_Decode, 254, 68, 120, // 17319: decode to VRMINSWFSTSXvm using decoder 120 |
| 8464 | // 17319: } |
| 8465 | // 17319: } |
| 8466 | 2, 22, // 17323: case 0x2: { |
| 8467 | OPC_CheckField, 0, 16, 0, // 17325: check Inst[15:0] == 0x0 |
| 8468 | OPC_CheckField, 32, 16, 0, // 17329: check Inst[47:32] == 0x0 |
| 8469 | OPC_Scope, 8, // 17333: try { |
| 8470 | OPC_CheckField, 48, 4, 0, // 17335: check Inst[51:48] == 0x0 |
| 8471 | OPC_Decode, 200, 68, 119, // 17339: decode to VRMAXSWLSTSXv using decoder 119 |
| 8472 | // 17339: } else try { |
| 8473 | OPC_Decode, 206, 68, 120, // 17343: decode to VRMAXSWLSTSXvm using decoder 120 |
| 8474 | // 17343: } |
| 8475 | // 17343: } |
| 8476 | 3, 22, // 17347: case 0x3: { |
| 8477 | OPC_CheckField, 0, 16, 0, // 17349: check Inst[15:0] == 0x0 |
| 8478 | OPC_CheckField, 32, 16, 0, // 17353: check Inst[47:32] == 0x0 |
| 8479 | OPC_Scope, 8, // 17357: try { |
| 8480 | OPC_CheckField, 48, 4, 0, // 17359: check Inst[51:48] == 0x0 |
| 8481 | OPC_Decode, 144, 69, 119, // 17363: decode to VRMINSWLSTSXv using decoder 119 |
| 8482 | // 17363: } else try { |
| 8483 | OPC_Decode, 150, 69, 120, // 17367: decode to VRMINSWLSTSXvm using decoder 120 |
| 8484 | // 17367: } |
| 8485 | // 17367: } |
| 8486 | 4, 22, // 17371: case 0x4: { |
| 8487 | OPC_CheckField, 0, 16, 0, // 17373: check Inst[15:0] == 0x0 |
| 8488 | OPC_CheckField, 32, 16, 0, // 17377: check Inst[47:32] == 0x0 |
| 8489 | OPC_Scope, 8, // 17381: try { |
| 8490 | OPC_CheckField, 48, 4, 0, // 17383: check Inst[51:48] == 0x0 |
| 8491 | OPC_Decode, 188, 68, 119, // 17387: decode to VRMAXSWFSTZXv using decoder 119 |
| 8492 | // 17387: } else try { |
| 8493 | OPC_Decode, 194, 68, 120, // 17391: decode to VRMAXSWFSTZXvm using decoder 120 |
| 8494 | // 17391: } |
| 8495 | // 17391: } |
| 8496 | 5, 22, // 17395: case 0x5: { |
| 8497 | OPC_CheckField, 0, 16, 0, // 17397: check Inst[15:0] == 0x0 |
| 8498 | OPC_CheckField, 32, 16, 0, // 17401: check Inst[47:32] == 0x0 |
| 8499 | OPC_Scope, 8, // 17405: try { |
| 8500 | OPC_CheckField, 48, 4, 0, // 17407: check Inst[51:48] == 0x0 |
| 8501 | OPC_Decode, 132, 69, 119, // 17411: decode to VRMINSWFSTZXv using decoder 119 |
| 8502 | // 17411: } else try { |
| 8503 | OPC_Decode, 138, 69, 120, // 17415: decode to VRMINSWFSTZXvm using decoder 120 |
| 8504 | // 17415: } |
| 8505 | // 17415: } |
| 8506 | 6, 22, // 17419: case 0x6: { |
| 8507 | OPC_CheckField, 0, 16, 0, // 17421: check Inst[15:0] == 0x0 |
| 8508 | OPC_CheckField, 32, 16, 0, // 17425: check Inst[47:32] == 0x0 |
| 8509 | OPC_Scope, 8, // 17429: try { |
| 8510 | OPC_CheckField, 48, 4, 0, // 17431: check Inst[51:48] == 0x0 |
| 8511 | OPC_Decode, 212, 68, 119, // 17435: decode to VRMAXSWLSTZXv using decoder 119 |
| 8512 | // 17435: } else try { |
| 8513 | OPC_Decode, 218, 68, 120, // 17439: decode to VRMAXSWLSTZXvm using decoder 120 |
| 8514 | // 17439: } |
| 8515 | // 17439: } |
| 8516 | 7, 0, // 17443: case 0x7: { |
| 8517 | OPC_CheckField, 0, 16, 0, // 17445: check Inst[15:0] == 0x0 |
| 8518 | OPC_CheckField, 32, 16, 0, // 17449: check Inst[47:32] == 0x0 |
| 8519 | OPC_Scope, 8, // 17453: try { |
| 8520 | OPC_CheckField, 48, 4, 0, // 17455: check Inst[51:48] == 0x0 |
| 8521 | OPC_Decode, 156, 69, 119, // 17459: decode to VRMINSWLSTZXv using decoder 119 |
| 8522 | // 17459: } else try { |
| 8523 | OPC_Decode, 162, 69, 120, // 17463: decode to VRMINSWLSTZXvm using decoder 120 |
| 8524 | // 17463: } |
| 8525 | // 17463: } |
| 8526 | // 17463: } // switch Inst[54:52] |
| 8527 | // 17463: } |
| 8528 | 248, 2, 33, // 17467: case 0x178: { |
| 8529 | OPC_SwitchField, 47, 8, // 17470: switch Inst[54:47] { |
| 8530 | 0, 13, // 17473: case 0x0: { |
| 8531 | OPC_CheckField, 32, 8, 0, // 17475: check Inst[39:32] == 0x0 |
| 8532 | OPC_CheckField, 0, 8, 0, // 17479: check Inst[7:0] == 0x0 |
| 8533 | OPC_Decode, 236, 74, 208, 1, // 17483: decode to VSHFvvi using decoder 208 |
| 8534 | // 17483: } |
| 8535 | 1, 0, // 17488: case 0x1: { |
| 8536 | OPC_CheckField, 32, 8, 0, // 17490: check Inst[39:32] == 0x0 |
| 8537 | OPC_CheckField, 0, 8, 0, // 17494: check Inst[7:0] == 0x0 |
| 8538 | OPC_Decode, 242, 74, 209, 1, // 17498: decode to VSHFvvr using decoder 209 |
| 8539 | // 17498: } |
| 8540 | // 17498: } // switch Inst[54:47] |
| 8541 | // 17498: } |
| 8542 | 250, 2, 219, 2, // 17503: case 0x17a: { |
| 8543 | OPC_SwitchField, 52, 3, // 17507: switch Inst[54:52] { |
| 8544 | 0, 22, // 17510: case 0x0: { |
| 8545 | OPC_CheckField, 0, 8, 0, // 17512: check Inst[7:0] == 0x0 |
| 8546 | OPC_CheckField, 32, 16, 0, // 17516: check Inst[47:32] == 0x0 |
| 8547 | OPC_Scope, 8, // 17520: try { |
| 8548 | OPC_CheckField, 48, 4, 0, // 17522: check Inst[51:48] == 0x0 |
| 8549 | OPC_Decode, 224, 47, 121, // 17526: decode to VFMAXDvv using decoder 121 |
| 8550 | // 17526: } else try { |
| 8551 | OPC_Decode, 230, 47, 122, // 17530: decode to VFMAXDvvm using decoder 122 |
| 8552 | // 17530: } |
| 8553 | // 17530: } |
| 8554 | 1, 22, // 17534: case 0x1: { |
| 8555 | OPC_CheckField, 0, 8, 0, // 17536: check Inst[7:0] == 0x0 |
| 8556 | OPC_CheckField, 32, 16, 0, // 17540: check Inst[47:32] == 0x0 |
| 8557 | OPC_Scope, 8, // 17544: try { |
| 8558 | OPC_CheckField, 48, 4, 0, // 17546: check Inst[51:48] == 0x0 |
| 8559 | OPC_Decode, 168, 48, 121, // 17550: decode to VFMINDvv using decoder 121 |
| 8560 | // 17550: } else try { |
| 8561 | OPC_Decode, 174, 48, 122, // 17554: decode to VFMINDvvm using decoder 122 |
| 8562 | // 17554: } |
| 8563 | // 17554: } |
| 8564 | 2, 60, // 17558: case 0x2: { |
| 8565 | OPC_SwitchField, 47, 1, // 17560: switch Inst[47] { |
| 8566 | 0, 26, // 17563: case 0x0: { |
| 8567 | OPC_CheckField, 0, 8, 0, // 17565: check Inst[7:0] == 0x0 |
| 8568 | OPC_CheckField, 16, 8, 0, // 17569: check Inst[23:16] == 0x0 |
| 8569 | OPC_CheckField, 32, 8, 0, // 17573: check Inst[39:32] == 0x0 |
| 8570 | OPC_Scope, 8, // 17577: try { |
| 8571 | OPC_CheckField, 48, 4, 0, // 17579: check Inst[51:48] == 0x0 |
| 8572 | OPC_Decode, 200, 47, 123, // 17583: decode to VFMAXDiv using decoder 123 |
| 8573 | // 17583: } else try { |
| 8574 | OPC_Decode, 206, 47, 124, // 17587: decode to VFMAXDivm using decoder 124 |
| 8575 | // 17587: } |
| 8576 | // 17587: } |
| 8577 | 1, 0, // 17591: case 0x1: { |
| 8578 | OPC_CheckField, 0, 8, 0, // 17593: check Inst[7:0] == 0x0 |
| 8579 | OPC_CheckField, 16, 8, 0, // 17597: check Inst[23:16] == 0x0 |
| 8580 | OPC_CheckField, 32, 8, 0, // 17601: check Inst[39:32] == 0x0 |
| 8581 | OPC_Scope, 8, // 17605: try { |
| 8582 | OPC_CheckField, 48, 4, 0, // 17607: check Inst[51:48] == 0x0 |
| 8583 | OPC_Decode, 212, 47, 127, // 17611: decode to VFMAXDrv using decoder 127 |
| 8584 | // 17611: } else try { |
| 8585 | OPC_Decode, 218, 47, 128, 1, // 17615: decode to VFMAXDrvm using decoder 128 |
| 8586 | // 17615: } |
| 8587 | // 17615: } |
| 8588 | // 17615: } // switch Inst[47] |
| 8589 | // 17615: } |
| 8590 | 3, 60, // 17620: case 0x3: { |
| 8591 | OPC_SwitchField, 47, 1, // 17622: switch Inst[47] { |
| 8592 | 0, 26, // 17625: case 0x0: { |
| 8593 | OPC_CheckField, 0, 8, 0, // 17627: check Inst[7:0] == 0x0 |
| 8594 | OPC_CheckField, 16, 8, 0, // 17631: check Inst[23:16] == 0x0 |
| 8595 | OPC_CheckField, 32, 8, 0, // 17635: check Inst[39:32] == 0x0 |
| 8596 | OPC_Scope, 8, // 17639: try { |
| 8597 | OPC_CheckField, 48, 4, 0, // 17641: check Inst[51:48] == 0x0 |
| 8598 | OPC_Decode, 144, 48, 123, // 17645: decode to VFMINDiv using decoder 123 |
| 8599 | // 17645: } else try { |
| 8600 | OPC_Decode, 150, 48, 124, // 17649: decode to VFMINDivm using decoder 124 |
| 8601 | // 17649: } |
| 8602 | // 17649: } |
| 8603 | 1, 0, // 17653: case 0x1: { |
| 8604 | OPC_CheckField, 0, 8, 0, // 17655: check Inst[7:0] == 0x0 |
| 8605 | OPC_CheckField, 16, 8, 0, // 17659: check Inst[23:16] == 0x0 |
| 8606 | OPC_CheckField, 32, 8, 0, // 17663: check Inst[39:32] == 0x0 |
| 8607 | OPC_Scope, 8, // 17667: try { |
| 8608 | OPC_CheckField, 48, 4, 0, // 17669: check Inst[51:48] == 0x0 |
| 8609 | OPC_Decode, 156, 48, 127, // 17673: decode to VFMINDrv using decoder 127 |
| 8610 | // 17673: } else try { |
| 8611 | OPC_Decode, 162, 48, 128, 1, // 17677: decode to VFMINDrvm using decoder 128 |
| 8612 | // 17677: } |
| 8613 | // 17677: } |
| 8614 | // 17677: } // switch Inst[47] |
| 8615 | // 17677: } |
| 8616 | 4, 22, // 17682: case 0x4: { |
| 8617 | OPC_CheckField, 0, 8, 0, // 17684: check Inst[7:0] == 0x0 |
| 8618 | OPC_CheckField, 32, 16, 0, // 17688: check Inst[47:32] == 0x0 |
| 8619 | OPC_Scope, 8, // 17692: try { |
| 8620 | OPC_CheckField, 48, 4, 0, // 17694: check Inst[51:48] == 0x0 |
| 8621 | OPC_Decode, 215, 16, 121, // 17698: decode to PVFMAXLOvv using decoder 121 |
| 8622 | // 17698: } else try { |
| 8623 | OPC_Decode, 221, 16, 122, // 17702: decode to PVFMAXLOvvm using decoder 122 |
| 8624 | // 17702: } |
| 8625 | // 17702: } |
| 8626 | 5, 22, // 17706: case 0x5: { |
| 8627 | OPC_CheckField, 0, 8, 0, // 17708: check Inst[7:0] == 0x0 |
| 8628 | OPC_CheckField, 32, 16, 0, // 17712: check Inst[47:32] == 0x0 |
| 8629 | OPC_Scope, 8, // 17716: try { |
| 8630 | OPC_CheckField, 48, 4, 0, // 17718: check Inst[51:48] == 0x0 |
| 8631 | OPC_Decode, 195, 17, 121, // 17722: decode to PVFMINLOvv using decoder 121 |
| 8632 | // 17722: } else try { |
| 8633 | OPC_Decode, 201, 17, 122, // 17726: decode to PVFMINLOvvm using decoder 122 |
| 8634 | // 17726: } |
| 8635 | // 17726: } |
| 8636 | 6, 60, // 17730: case 0x6: { |
| 8637 | OPC_SwitchField, 47, 1, // 17732: switch Inst[47] { |
| 8638 | 0, 26, // 17735: case 0x0: { |
| 8639 | OPC_CheckField, 0, 8, 0, // 17737: check Inst[7:0] == 0x0 |
| 8640 | OPC_CheckField, 16, 8, 0, // 17741: check Inst[23:16] == 0x0 |
| 8641 | OPC_CheckField, 32, 8, 0, // 17745: check Inst[39:32] == 0x0 |
| 8642 | OPC_Scope, 8, // 17749: try { |
| 8643 | OPC_CheckField, 48, 4, 0, // 17751: check Inst[51:48] == 0x0 |
| 8644 | OPC_Decode, 191, 16, 123, // 17755: decode to PVFMAXLOiv using decoder 123 |
| 8645 | // 17755: } else try { |
| 8646 | OPC_Decode, 197, 16, 124, // 17759: decode to PVFMAXLOivm using decoder 124 |
| 8647 | // 17759: } |
| 8648 | // 17759: } |
| 8649 | 1, 0, // 17763: case 0x1: { |
| 8650 | OPC_CheckField, 0, 8, 0, // 17765: check Inst[7:0] == 0x0 |
| 8651 | OPC_CheckField, 16, 8, 0, // 17769: check Inst[23:16] == 0x0 |
| 8652 | OPC_CheckField, 32, 8, 0, // 17773: check Inst[39:32] == 0x0 |
| 8653 | OPC_Scope, 8, // 17777: try { |
| 8654 | OPC_CheckField, 48, 4, 0, // 17779: check Inst[51:48] == 0x0 |
| 8655 | OPC_Decode, 203, 16, 127, // 17783: decode to PVFMAXLOrv using decoder 127 |
| 8656 | // 17783: } else try { |
| 8657 | OPC_Decode, 209, 16, 128, 1, // 17787: decode to PVFMAXLOrvm using decoder 128 |
| 8658 | // 17787: } |
| 8659 | // 17787: } |
| 8660 | // 17787: } // switch Inst[47] |
| 8661 | // 17787: } |
| 8662 | 7, 0, // 17792: case 0x7: { |
| 8663 | OPC_SwitchField, 47, 1, // 17794: switch Inst[47] { |
| 8664 | 0, 26, // 17797: case 0x0: { |
| 8665 | OPC_CheckField, 0, 8, 0, // 17799: check Inst[7:0] == 0x0 |
| 8666 | OPC_CheckField, 16, 8, 0, // 17803: check Inst[23:16] == 0x0 |
| 8667 | OPC_CheckField, 32, 8, 0, // 17807: check Inst[39:32] == 0x0 |
| 8668 | OPC_Scope, 8, // 17811: try { |
| 8669 | OPC_CheckField, 48, 4, 0, // 17813: check Inst[51:48] == 0x0 |
| 8670 | OPC_Decode, 171, 17, 123, // 17817: decode to PVFMINLOiv using decoder 123 |
| 8671 | // 17817: } else try { |
| 8672 | OPC_Decode, 177, 17, 124, // 17821: decode to PVFMINLOivm using decoder 124 |
| 8673 | // 17821: } |
| 8674 | // 17821: } |
| 8675 | 1, 0, // 17825: case 0x1: { |
| 8676 | OPC_CheckField, 0, 8, 0, // 17827: check Inst[7:0] == 0x0 |
| 8677 | OPC_CheckField, 16, 8, 0, // 17831: check Inst[23:16] == 0x0 |
| 8678 | OPC_CheckField, 32, 8, 0, // 17835: check Inst[39:32] == 0x0 |
| 8679 | OPC_Scope, 8, // 17839: try { |
| 8680 | OPC_CheckField, 48, 4, 0, // 17841: check Inst[51:48] == 0x0 |
| 8681 | OPC_Decode, 183, 17, 127, // 17845: decode to PVFMINLOrv using decoder 127 |
| 8682 | // 17845: } else try { |
| 8683 | OPC_Decode, 189, 17, 128, 1, // 17849: decode to PVFMINLOrvm using decoder 128 |
| 8684 | // 17849: } |
| 8685 | // 17849: } |
| 8686 | // 17849: } // switch Inst[47] |
| 8687 | // 17849: } |
| 8688 | // 17849: } // switch Inst[54:52] |
| 8689 | // 17849: } |
| 8690 | 251, 2, 225, 2, // 17854: case 0x17b: { |
| 8691 | OPC_SwitchField, 52, 3, // 17858: switch Inst[54:52] { |
| 8692 | 0, 22, // 17861: case 0x0: { |
| 8693 | OPC_CheckField, 0, 8, 0, // 17863: check Inst[7:0] == 0x0 |
| 8694 | OPC_CheckField, 32, 16, 0, // 17867: check Inst[47:32] == 0x0 |
| 8695 | OPC_Scope, 8, // 17871: try { |
| 8696 | OPC_CheckField, 48, 4, 0, // 17873: check Inst[51:48] == 0x0 |
| 8697 | OPC_Decode, 251, 16, 121, // 17877: decode to PVFMAXUPvv using decoder 121 |
| 8698 | // 17877: } else try { |
| 8699 | OPC_Decode, 129, 17, 122, // 17881: decode to PVFMAXUPvvm using decoder 122 |
| 8700 | // 17881: } |
| 8701 | // 17881: } |
| 8702 | 1, 22, // 17885: case 0x1: { |
| 8703 | OPC_CheckField, 0, 8, 0, // 17887: check Inst[7:0] == 0x0 |
| 8704 | OPC_CheckField, 32, 16, 0, // 17891: check Inst[47:32] == 0x0 |
| 8705 | OPC_Scope, 8, // 17895: try { |
| 8706 | OPC_CheckField, 48, 4, 0, // 17897: check Inst[51:48] == 0x0 |
| 8707 | OPC_Decode, 231, 17, 121, // 17901: decode to PVFMINUPvv using decoder 121 |
| 8708 | // 17901: } else try { |
| 8709 | OPC_Decode, 237, 17, 122, // 17905: decode to PVFMINUPvvm using decoder 122 |
| 8710 | // 17905: } |
| 8711 | // 17905: } |
| 8712 | 2, 61, // 17909: case 0x2: { |
| 8713 | OPC_SwitchField, 47, 1, // 17911: switch Inst[47] { |
| 8714 | 0, 26, // 17914: case 0x0: { |
| 8715 | OPC_CheckField, 0, 8, 0, // 17916: check Inst[7:0] == 0x0 |
| 8716 | OPC_CheckField, 16, 8, 0, // 17920: check Inst[23:16] == 0x0 |
| 8717 | OPC_CheckField, 32, 8, 0, // 17924: check Inst[39:32] == 0x0 |
| 8718 | OPC_Scope, 8, // 17928: try { |
| 8719 | OPC_CheckField, 48, 4, 0, // 17930: check Inst[51:48] == 0x0 |
| 8720 | OPC_Decode, 227, 16, 123, // 17934: decode to PVFMAXUPiv using decoder 123 |
| 8721 | // 17934: } else try { |
| 8722 | OPC_Decode, 233, 16, 124, // 17938: decode to PVFMAXUPivm using decoder 124 |
| 8723 | // 17938: } |
| 8724 | // 17938: } |
| 8725 | 1, 0, // 17942: case 0x1: { |
| 8726 | OPC_CheckField, 0, 8, 0, // 17944: check Inst[7:0] == 0x0 |
| 8727 | OPC_CheckField, 16, 8, 0, // 17948: check Inst[23:16] == 0x0 |
| 8728 | OPC_CheckField, 32, 8, 0, // 17952: check Inst[39:32] == 0x0 |
| 8729 | OPC_Scope, 9, // 17956: try { |
| 8730 | OPC_CheckField, 48, 4, 0, // 17958: check Inst[51:48] == 0x0 |
| 8731 | OPC_Decode, 239, 16, 210, 1, // 17962: decode to PVFMAXUPrv using decoder 210 |
| 8732 | // 17962: } else try { |
| 8733 | OPC_Decode, 245, 16, 211, 1, // 17967: decode to PVFMAXUPrvm using decoder 211 |
| 8734 | // 17967: } |
| 8735 | // 17967: } |
| 8736 | // 17967: } // switch Inst[47] |
| 8737 | // 17967: } |
| 8738 | 3, 61, // 17972: case 0x3: { |
| 8739 | OPC_SwitchField, 47, 1, // 17974: switch Inst[47] { |
| 8740 | 0, 26, // 17977: case 0x0: { |
| 8741 | OPC_CheckField, 0, 8, 0, // 17979: check Inst[7:0] == 0x0 |
| 8742 | OPC_CheckField, 16, 8, 0, // 17983: check Inst[23:16] == 0x0 |
| 8743 | OPC_CheckField, 32, 8, 0, // 17987: check Inst[39:32] == 0x0 |
| 8744 | OPC_Scope, 8, // 17991: try { |
| 8745 | OPC_CheckField, 48, 4, 0, // 17993: check Inst[51:48] == 0x0 |
| 8746 | OPC_Decode, 207, 17, 123, // 17997: decode to PVFMINUPiv using decoder 123 |
| 8747 | // 17997: } else try { |
| 8748 | OPC_Decode, 213, 17, 124, // 18001: decode to PVFMINUPivm using decoder 124 |
| 8749 | // 18001: } |
| 8750 | // 18001: } |
| 8751 | 1, 0, // 18005: case 0x1: { |
| 8752 | OPC_CheckField, 0, 8, 0, // 18007: check Inst[7:0] == 0x0 |
| 8753 | OPC_CheckField, 16, 8, 0, // 18011: check Inst[23:16] == 0x0 |
| 8754 | OPC_CheckField, 32, 8, 0, // 18015: check Inst[39:32] == 0x0 |
| 8755 | OPC_Scope, 9, // 18019: try { |
| 8756 | OPC_CheckField, 48, 4, 0, // 18021: check Inst[51:48] == 0x0 |
| 8757 | OPC_Decode, 219, 17, 210, 1, // 18025: decode to PVFMINUPrv using decoder 210 |
| 8758 | // 18025: } else try { |
| 8759 | OPC_Decode, 225, 17, 211, 1, // 18030: decode to PVFMINUPrvm using decoder 211 |
| 8760 | // 18030: } |
| 8761 | // 18030: } |
| 8762 | // 18030: } // switch Inst[47] |
| 8763 | // 18030: } |
| 8764 | 4, 23, // 18035: case 0x4: { |
| 8765 | OPC_CheckField, 0, 8, 0, // 18037: check Inst[7:0] == 0x0 |
| 8766 | OPC_CheckField, 32, 16, 0, // 18041: check Inst[47:32] == 0x0 |
| 8767 | OPC_Scope, 8, // 18045: try { |
| 8768 | OPC_CheckField, 48, 4, 0, // 18047: check Inst[51:48] == 0x0 |
| 8769 | OPC_Decode, 159, 17, 121, // 18051: decode to PVFMAXvv using decoder 121 |
| 8770 | // 18051: } else try { |
| 8771 | OPC_Decode, 165, 17, 129, 1, // 18055: decode to PVFMAXvvm using decoder 129 |
| 8772 | // 18055: } |
| 8773 | // 18055: } |
| 8774 | 5, 23, // 18060: case 0x5: { |
| 8775 | OPC_CheckField, 0, 8, 0, // 18062: check Inst[7:0] == 0x0 |
| 8776 | OPC_CheckField, 32, 16, 0, // 18066: check Inst[47:32] == 0x0 |
| 8777 | OPC_Scope, 8, // 18070: try { |
| 8778 | OPC_CheckField, 48, 4, 0, // 18072: check Inst[51:48] == 0x0 |
| 8779 | OPC_Decode, 139, 18, 121, // 18076: decode to PVFMINvv using decoder 121 |
| 8780 | // 18076: } else try { |
| 8781 | OPC_Decode, 145, 18, 129, 1, // 18080: decode to PVFMINvvm using decoder 129 |
| 8782 | // 18080: } |
| 8783 | // 18080: } |
| 8784 | 6, 61, // 18085: case 0x6: { |
| 8785 | OPC_SwitchField, 47, 1, // 18087: switch Inst[47] { |
| 8786 | 0, 27, // 18090: case 0x0: { |
| 8787 | OPC_CheckField, 0, 8, 0, // 18092: check Inst[7:0] == 0x0 |
| 8788 | OPC_CheckField, 16, 8, 0, // 18096: check Inst[23:16] == 0x0 |
| 8789 | OPC_CheckField, 32, 8, 0, // 18100: check Inst[39:32] == 0x0 |
| 8790 | OPC_Scope, 8, // 18104: try { |
| 8791 | OPC_CheckField, 48, 4, 0, // 18106: check Inst[51:48] == 0x0 |
| 8792 | OPC_Decode, 135, 17, 123, // 18110: decode to PVFMAXiv using decoder 123 |
| 8793 | // 18110: } else try { |
| 8794 | OPC_Decode, 141, 17, 130, 1, // 18114: decode to PVFMAXivm using decoder 130 |
| 8795 | // 18114: } |
| 8796 | // 18114: } |
| 8797 | 1, 0, // 18119: case 0x1: { |
| 8798 | OPC_CheckField, 0, 8, 0, // 18121: check Inst[7:0] == 0x0 |
| 8799 | OPC_CheckField, 16, 8, 0, // 18125: check Inst[23:16] == 0x0 |
| 8800 | OPC_CheckField, 32, 8, 0, // 18129: check Inst[39:32] == 0x0 |
| 8801 | OPC_Scope, 8, // 18133: try { |
| 8802 | OPC_CheckField, 48, 4, 0, // 18135: check Inst[51:48] == 0x0 |
| 8803 | OPC_Decode, 147, 17, 127, // 18139: decode to PVFMAXrv using decoder 127 |
| 8804 | // 18139: } else try { |
| 8805 | OPC_Decode, 153, 17, 131, 1, // 18143: decode to PVFMAXrvm using decoder 131 |
| 8806 | // 18143: } |
| 8807 | // 18143: } |
| 8808 | // 18143: } // switch Inst[47] |
| 8809 | // 18143: } |
| 8810 | 7, 0, // 18148: case 0x7: { |
| 8811 | OPC_SwitchField, 47, 1, // 18150: switch Inst[47] { |
| 8812 | 0, 27, // 18153: case 0x0: { |
| 8813 | OPC_CheckField, 0, 8, 0, // 18155: check Inst[7:0] == 0x0 |
| 8814 | OPC_CheckField, 16, 8, 0, // 18159: check Inst[23:16] == 0x0 |
| 8815 | OPC_CheckField, 32, 8, 0, // 18163: check Inst[39:32] == 0x0 |
| 8816 | OPC_Scope, 8, // 18167: try { |
| 8817 | OPC_CheckField, 48, 4, 0, // 18169: check Inst[51:48] == 0x0 |
| 8818 | OPC_Decode, 243, 17, 123, // 18173: decode to PVFMINiv using decoder 123 |
| 8819 | // 18173: } else try { |
| 8820 | OPC_Decode, 249, 17, 130, 1, // 18177: decode to PVFMINivm using decoder 130 |
| 8821 | // 18177: } |
| 8822 | // 18177: } |
| 8823 | 1, 0, // 18182: case 0x1: { |
| 8824 | OPC_CheckField, 0, 8, 0, // 18184: check Inst[7:0] == 0x0 |
| 8825 | OPC_CheckField, 16, 8, 0, // 18188: check Inst[23:16] == 0x0 |
| 8826 | OPC_CheckField, 32, 8, 0, // 18192: check Inst[39:32] == 0x0 |
| 8827 | OPC_Scope, 8, // 18196: try { |
| 8828 | OPC_CheckField, 48, 4, 0, // 18198: check Inst[51:48] == 0x0 |
| 8829 | OPC_Decode, 255, 17, 127, // 18202: decode to PVFMINrv using decoder 127 |
| 8830 | // 18202: } else try { |
| 8831 | OPC_Decode, 133, 18, 131, 1, // 18206: decode to PVFMINrvm using decoder 131 |
| 8832 | // 18206: } |
| 8833 | // 18206: } |
| 8834 | // 18206: } // switch Inst[47] |
| 8835 | // 18206: } |
| 8836 | // 18206: } // switch Inst[54:52] |
| 8837 | // 18206: } |
| 8838 | 254, 2, 24, // 18211: case 0x17e: { |
| 8839 | OPC_SwitchField, 47, 8, // 18214: switch Inst[54:47] { |
| 8840 | 0, 9, // 18217: case 0x0: { |
| 8841 | OPC_CheckField, 0, 40, 0, // 18219: check Inst[39:0] == 0x0 |
| 8842 | OPC_Decode, 181, 6, 212, 1, // 18223: decode to LVLi using decoder 212 |
| 8843 | // 18223: } |
| 8844 | 1, 0, // 18228: case 0x1: { |
| 8845 | OPC_CheckField, 0, 40, 0, // 18230: check Inst[39:0] == 0x0 |
| 8846 | OPC_Decode, 182, 6, 42, // 18234: decode to LVLr using decoder 42 |
| 8847 | // 18234: } |
| 8848 | // 18234: } // switch Inst[54:47] |
| 8849 | // 18234: } |
| 8850 | 130, 3, 105, // 18238: case 0x182: { |
| 8851 | OPC_SwitchField, 47, 8, // 18241: switch Inst[54:47] { |
| 8852 | 0, 23, // 18244: case 0x0: { |
| 8853 | OPC_SwitchField, 39, 1, // 18246: switch Inst[39] { |
| 8854 | 0, 8, // 18249: case 0x0: { |
| 8855 | OPC_CheckField, 0, 24, 0, // 18251: check Inst[23:0] == 0x0 |
| 8856 | OPC_Decode, 174, 60, 114, // 18255: decode to VLD2DNCiz using decoder 114 |
| 8857 | // 18255: } |
| 8858 | 1, 0, // 18259: case 0x1: { |
| 8859 | OPC_CheckField, 0, 24, 0, // 18261: check Inst[23:0] == 0x0 |
| 8860 | OPC_Decode, 168, 60, 115, // 18265: decode to VLD2DNCir using decoder 115 |
| 8861 | // 18265: } |
| 8862 | // 18265: } // switch Inst[39] |
| 8863 | // 18265: } |
| 8864 | 1, 23, // 18269: case 0x1: { |
| 8865 | OPC_SwitchField, 39, 1, // 18271: switch Inst[39] { |
| 8866 | 0, 8, // 18274: case 0x0: { |
| 8867 | OPC_CheckField, 0, 24, 0, // 18276: check Inst[23:0] == 0x0 |
| 8868 | OPC_Decode, 186, 60, 116, // 18280: decode to VLD2DNCrz using decoder 116 |
| 8869 | // 18280: } |
| 8870 | 1, 0, // 18284: case 0x1: { |
| 8871 | OPC_CheckField, 0, 24, 0, // 18286: check Inst[23:0] == 0x0 |
| 8872 | OPC_Decode, 180, 60, 117, // 18290: decode to VLD2DNCrr using decoder 117 |
| 8873 | // 18290: } |
| 8874 | // 18290: } // switch Inst[39] |
| 8875 | // 18290: } |
| 8876 | 128, 1, 23, // 18294: case 0x80: { |
| 8877 | OPC_SwitchField, 39, 1, // 18297: switch Inst[39] { |
| 8878 | 0, 8, // 18300: case 0x0: { |
| 8879 | OPC_CheckField, 0, 24, 0, // 18302: check Inst[23:0] == 0x0 |
| 8880 | OPC_Decode, 198, 60, 114, // 18306: decode to VLD2Diz using decoder 114 |
| 8881 | // 18306: } |
| 8882 | 1, 0, // 18310: case 0x1: { |
| 8883 | OPC_CheckField, 0, 24, 0, // 18312: check Inst[23:0] == 0x0 |
| 8884 | OPC_Decode, 192, 60, 115, // 18316: decode to VLD2Dir using decoder 115 |
| 8885 | // 18316: } |
| 8886 | // 18316: } // switch Inst[39] |
| 8887 | // 18316: } |
| 8888 | 129, 1, 0, // 18320: case 0x81: { |
| 8889 | OPC_SwitchField, 39, 1, // 18323: switch Inst[39] { |
| 8890 | 0, 8, // 18326: case 0x0: { |
| 8891 | OPC_CheckField, 0, 24, 0, // 18328: check Inst[23:0] == 0x0 |
| 8892 | OPC_Decode, 210, 60, 116, // 18332: decode to VLD2Drz using decoder 116 |
| 8893 | // 18332: } |
| 8894 | 1, 0, // 18336: case 0x1: { |
| 8895 | OPC_CheckField, 0, 24, 0, // 18338: check Inst[23:0] == 0x0 |
| 8896 | OPC_Decode, 204, 60, 117, // 18342: decode to VLD2Drr using decoder 117 |
| 8897 | // 18342: } |
| 8898 | // 18342: } // switch Inst[39] |
| 8899 | // 18342: } |
| 8900 | // 18342: } // switch Inst[54:47] |
| 8901 | // 18342: } |
| 8902 | 132, 3, 105, // 18346: case 0x184: { |
| 8903 | OPC_SwitchField, 47, 8, // 18349: switch Inst[54:47] { |
| 8904 | 0, 23, // 18352: case 0x0: { |
| 8905 | OPC_SwitchField, 39, 1, // 18354: switch Inst[39] { |
| 8906 | 0, 8, // 18357: case 0x0: { |
| 8907 | OPC_CheckField, 0, 24, 0, // 18359: check Inst[23:0] == 0x0 |
| 8908 | OPC_Decode, 182, 62, 114, // 18363: decode to VLDU2DNCiz using decoder 114 |
| 8909 | // 18363: } |
| 8910 | 1, 0, // 18367: case 0x1: { |
| 8911 | OPC_CheckField, 0, 24, 0, // 18369: check Inst[23:0] == 0x0 |
| 8912 | OPC_Decode, 176, 62, 115, // 18373: decode to VLDU2DNCir using decoder 115 |
| 8913 | // 18373: } |
| 8914 | // 18373: } // switch Inst[39] |
| 8915 | // 18373: } |
| 8916 | 1, 23, // 18377: case 0x1: { |
| 8917 | OPC_SwitchField, 39, 1, // 18379: switch Inst[39] { |
| 8918 | 0, 8, // 18382: case 0x0: { |
| 8919 | OPC_CheckField, 0, 24, 0, // 18384: check Inst[23:0] == 0x0 |
| 8920 | OPC_Decode, 194, 62, 116, // 18388: decode to VLDU2DNCrz using decoder 116 |
| 8921 | // 18388: } |
| 8922 | 1, 0, // 18392: case 0x1: { |
| 8923 | OPC_CheckField, 0, 24, 0, // 18394: check Inst[23:0] == 0x0 |
| 8924 | OPC_Decode, 188, 62, 117, // 18398: decode to VLDU2DNCrr using decoder 117 |
| 8925 | // 18398: } |
| 8926 | // 18398: } // switch Inst[39] |
| 8927 | // 18398: } |
| 8928 | 128, 1, 23, // 18402: case 0x80: { |
| 8929 | OPC_SwitchField, 39, 1, // 18405: switch Inst[39] { |
| 8930 | 0, 8, // 18408: case 0x0: { |
| 8931 | OPC_CheckField, 0, 24, 0, // 18410: check Inst[23:0] == 0x0 |
| 8932 | OPC_Decode, 206, 62, 114, // 18414: decode to VLDU2Diz using decoder 114 |
| 8933 | // 18414: } |
| 8934 | 1, 0, // 18418: case 0x1: { |
| 8935 | OPC_CheckField, 0, 24, 0, // 18420: check Inst[23:0] == 0x0 |
| 8936 | OPC_Decode, 200, 62, 115, // 18424: decode to VLDU2Dir using decoder 115 |
| 8937 | // 18424: } |
| 8938 | // 18424: } // switch Inst[39] |
| 8939 | // 18424: } |
| 8940 | 129, 1, 0, // 18428: case 0x81: { |
| 8941 | OPC_SwitchField, 39, 1, // 18431: switch Inst[39] { |
| 8942 | 0, 8, // 18434: case 0x0: { |
| 8943 | OPC_CheckField, 0, 24, 0, // 18436: check Inst[23:0] == 0x0 |
| 8944 | OPC_Decode, 218, 62, 116, // 18440: decode to VLDU2Drz using decoder 116 |
| 8945 | // 18440: } |
| 8946 | 1, 0, // 18444: case 0x1: { |
| 8947 | OPC_CheckField, 0, 24, 0, // 18446: check Inst[23:0] == 0x0 |
| 8948 | OPC_Decode, 212, 62, 117, // 18450: decode to VLDU2Drr using decoder 117 |
| 8949 | // 18450: } |
| 8950 | // 18450: } // switch Inst[39] |
| 8951 | // 18450: } |
| 8952 | // 18450: } // switch Inst[54:47] |
| 8953 | // 18450: } |
| 8954 | 134, 3, 105, // 18454: case 0x186: { |
| 8955 | OPC_SwitchField, 47, 8, // 18457: switch Inst[54:47] { |
| 8956 | 0, 23, // 18460: case 0x0: { |
| 8957 | OPC_SwitchField, 39, 1, // 18462: switch Inst[39] { |
| 8958 | 0, 8, // 18465: case 0x0: { |
| 8959 | OPC_CheckField, 0, 24, 0, // 18467: check Inst[23:0] == 0x0 |
| 8960 | OPC_Decode, 222, 60, 114, // 18471: decode to VLDL2DSXNCiz using decoder 114 |
| 8961 | // 18471: } |
| 8962 | 1, 0, // 18475: case 0x1: { |
| 8963 | OPC_CheckField, 0, 24, 0, // 18477: check Inst[23:0] == 0x0 |
| 8964 | OPC_Decode, 216, 60, 115, // 18481: decode to VLDL2DSXNCir using decoder 115 |
| 8965 | // 18481: } |
| 8966 | // 18481: } // switch Inst[39] |
| 8967 | // 18481: } |
| 8968 | 1, 23, // 18485: case 0x1: { |
| 8969 | OPC_SwitchField, 39, 1, // 18487: switch Inst[39] { |
| 8970 | 0, 8, // 18490: case 0x0: { |
| 8971 | OPC_CheckField, 0, 24, 0, // 18492: check Inst[23:0] == 0x0 |
| 8972 | OPC_Decode, 234, 60, 116, // 18496: decode to VLDL2DSXNCrz using decoder 116 |
| 8973 | // 18496: } |
| 8974 | 1, 0, // 18500: case 0x1: { |
| 8975 | OPC_CheckField, 0, 24, 0, // 18502: check Inst[23:0] == 0x0 |
| 8976 | OPC_Decode, 228, 60, 117, // 18506: decode to VLDL2DSXNCrr using decoder 117 |
| 8977 | // 18506: } |
| 8978 | // 18506: } // switch Inst[39] |
| 8979 | // 18506: } |
| 8980 | 128, 1, 23, // 18510: case 0x80: { |
| 8981 | OPC_SwitchField, 39, 1, // 18513: switch Inst[39] { |
| 8982 | 0, 8, // 18516: case 0x0: { |
| 8983 | OPC_CheckField, 0, 24, 0, // 18518: check Inst[23:0] == 0x0 |
| 8984 | OPC_Decode, 246, 60, 114, // 18522: decode to VLDL2DSXiz using decoder 114 |
| 8985 | // 18522: } |
| 8986 | 1, 0, // 18526: case 0x1: { |
| 8987 | OPC_CheckField, 0, 24, 0, // 18528: check Inst[23:0] == 0x0 |
| 8988 | OPC_Decode, 240, 60, 115, // 18532: decode to VLDL2DSXir using decoder 115 |
| 8989 | // 18532: } |
| 8990 | // 18532: } // switch Inst[39] |
| 8991 | // 18532: } |
| 8992 | 129, 1, 0, // 18536: case 0x81: { |
| 8993 | OPC_SwitchField, 39, 1, // 18539: switch Inst[39] { |
| 8994 | 0, 8, // 18542: case 0x0: { |
| 8995 | OPC_CheckField, 0, 24, 0, // 18544: check Inst[23:0] == 0x0 |
| 8996 | OPC_Decode, 130, 61, 116, // 18548: decode to VLDL2DSXrz using decoder 116 |
| 8997 | // 18548: } |
| 8998 | 1, 0, // 18552: case 0x1: { |
| 8999 | OPC_CheckField, 0, 24, 0, // 18554: check Inst[23:0] == 0x0 |
| 9000 | OPC_Decode, 252, 60, 117, // 18558: decode to VLDL2DSXrr using decoder 117 |
| 9001 | // 18558: } |
| 9002 | // 18558: } // switch Inst[39] |
| 9003 | // 18558: } |
| 9004 | // 18558: } // switch Inst[54:47] |
| 9005 | // 18558: } |
| 9006 | 135, 3, 105, // 18562: case 0x187: { |
| 9007 | OPC_SwitchField, 47, 8, // 18565: switch Inst[54:47] { |
| 9008 | 0, 23, // 18568: case 0x0: { |
| 9009 | OPC_SwitchField, 39, 1, // 18570: switch Inst[39] { |
| 9010 | 0, 8, // 18573: case 0x0: { |
| 9011 | OPC_CheckField, 0, 24, 0, // 18575: check Inst[23:0] == 0x0 |
| 9012 | OPC_Decode, 142, 61, 114, // 18579: decode to VLDL2DZXNCiz using decoder 114 |
| 9013 | // 18579: } |
| 9014 | 1, 0, // 18583: case 0x1: { |
| 9015 | OPC_CheckField, 0, 24, 0, // 18585: check Inst[23:0] == 0x0 |
| 9016 | OPC_Decode, 136, 61, 115, // 18589: decode to VLDL2DZXNCir using decoder 115 |
| 9017 | // 18589: } |
| 9018 | // 18589: } // switch Inst[39] |
| 9019 | // 18589: } |
| 9020 | 1, 23, // 18593: case 0x1: { |
| 9021 | OPC_SwitchField, 39, 1, // 18595: switch Inst[39] { |
| 9022 | 0, 8, // 18598: case 0x0: { |
| 9023 | OPC_CheckField, 0, 24, 0, // 18600: check Inst[23:0] == 0x0 |
| 9024 | OPC_Decode, 154, 61, 116, // 18604: decode to VLDL2DZXNCrz using decoder 116 |
| 9025 | // 18604: } |
| 9026 | 1, 0, // 18608: case 0x1: { |
| 9027 | OPC_CheckField, 0, 24, 0, // 18610: check Inst[23:0] == 0x0 |
| 9028 | OPC_Decode, 148, 61, 117, // 18614: decode to VLDL2DZXNCrr using decoder 117 |
| 9029 | // 18614: } |
| 9030 | // 18614: } // switch Inst[39] |
| 9031 | // 18614: } |
| 9032 | 128, 1, 23, // 18618: case 0x80: { |
| 9033 | OPC_SwitchField, 39, 1, // 18621: switch Inst[39] { |
| 9034 | 0, 8, // 18624: case 0x0: { |
| 9035 | OPC_CheckField, 0, 24, 0, // 18626: check Inst[23:0] == 0x0 |
| 9036 | OPC_Decode, 166, 61, 114, // 18630: decode to VLDL2DZXiz using decoder 114 |
| 9037 | // 18630: } |
| 9038 | 1, 0, // 18634: case 0x1: { |
| 9039 | OPC_CheckField, 0, 24, 0, // 18636: check Inst[23:0] == 0x0 |
| 9040 | OPC_Decode, 160, 61, 115, // 18640: decode to VLDL2DZXir using decoder 115 |
| 9041 | // 18640: } |
| 9042 | // 18640: } // switch Inst[39] |
| 9043 | // 18640: } |
| 9044 | 129, 1, 0, // 18644: case 0x81: { |
| 9045 | OPC_SwitchField, 39, 1, // 18647: switch Inst[39] { |
| 9046 | 0, 8, // 18650: case 0x0: { |
| 9047 | OPC_CheckField, 0, 24, 0, // 18652: check Inst[23:0] == 0x0 |
| 9048 | OPC_Decode, 178, 61, 116, // 18656: decode to VLDL2DZXrz using decoder 116 |
| 9049 | // 18656: } |
| 9050 | 1, 0, // 18660: case 0x1: { |
| 9051 | OPC_CheckField, 0, 24, 0, // 18662: check Inst[23:0] == 0x0 |
| 9052 | OPC_Decode, 172, 61, 117, // 18666: decode to VLDL2DZXrr using decoder 117 |
| 9053 | // 18666: } |
| 9054 | // 18666: } // switch Inst[39] |
| 9055 | // 18666: } |
| 9056 | // 18666: } // switch Inst[54:47] |
| 9057 | // 18666: } |
| 9058 | 136, 3, 178, 1, // 18670: case 0x188: { |
| 9059 | OPC_SwitchField, 52, 3, // 18674: switch Inst[54:52] { |
| 9060 | 0, 22, // 18677: case 0x0: { |
| 9061 | OPC_CheckField, 0, 8, 0, // 18679: check Inst[7:0] == 0x0 |
| 9062 | OPC_CheckField, 32, 16, 0, // 18683: check Inst[47:32] == 0x0 |
| 9063 | OPC_Scope, 8, // 18687: try { |
| 9064 | OPC_CheckField, 48, 4, 0, // 18689: check Inst[51:48] == 0x0 |
| 9065 | OPC_Decode, 172, 37, 121, // 18693: decode to VANDvv using decoder 121 |
| 9066 | // 18693: } else try { |
| 9067 | OPC_Decode, 178, 37, 122, // 18697: decode to VANDvvm using decoder 122 |
| 9068 | // 18697: } |
| 9069 | // 18697: } |
| 9070 | 2, 62, // 18701: case 0x2: { |
| 9071 | OPC_SwitchField, 47, 1, // 18703: switch Inst[47] { |
| 9072 | 0, 28, // 18706: case 0x0: { |
| 9073 | OPC_CheckField, 0, 8, 0, // 18708: check Inst[7:0] == 0x0 |
| 9074 | OPC_CheckField, 16, 8, 0, // 18712: check Inst[23:16] == 0x0 |
| 9075 | OPC_CheckField, 32, 8, 0, // 18716: check Inst[39:32] == 0x0 |
| 9076 | OPC_Scope, 9, // 18720: try { |
| 9077 | OPC_CheckField, 48, 4, 0, // 18722: check Inst[51:48] == 0x0 |
| 9078 | OPC_Decode, 148, 37, 158, 1, // 18726: decode to VANDmv using decoder 158 |
| 9079 | // 18726: } else try { |
| 9080 | OPC_Decode, 154, 37, 159, 1, // 18731: decode to VANDmvm using decoder 159 |
| 9081 | // 18731: } |
| 9082 | // 18731: } |
| 9083 | 1, 0, // 18736: case 0x1: { |
| 9084 | OPC_CheckField, 0, 8, 0, // 18738: check Inst[7:0] == 0x0 |
| 9085 | OPC_CheckField, 16, 8, 0, // 18742: check Inst[23:16] == 0x0 |
| 9086 | OPC_CheckField, 32, 8, 0, // 18746: check Inst[39:32] == 0x0 |
| 9087 | OPC_Scope, 8, // 18750: try { |
| 9088 | OPC_CheckField, 48, 4, 0, // 18752: check Inst[51:48] == 0x0 |
| 9089 | OPC_Decode, 160, 37, 127, // 18756: decode to VANDrv using decoder 127 |
| 9090 | // 18756: } else try { |
| 9091 | OPC_Decode, 166, 37, 128, 1, // 18760: decode to VANDrvm using decoder 128 |
| 9092 | // 18760: } |
| 9093 | // 18760: } |
| 9094 | // 18760: } // switch Inst[47] |
| 9095 | // 18760: } |
| 9096 | 4, 22, // 18765: case 0x4: { |
| 9097 | OPC_CheckField, 0, 8, 0, // 18767: check Inst[7:0] == 0x0 |
| 9098 | OPC_CheckField, 32, 16, 0, // 18771: check Inst[47:32] == 0x0 |
| 9099 | OPC_Scope, 8, // 18775: try { |
| 9100 | OPC_CheckField, 48, 4, 0, // 18777: check Inst[51:48] == 0x0 |
| 9101 | OPC_Decode, 151, 9, 121, // 18781: decode to PVANDLOvv using decoder 121 |
| 9102 | // 18781: } else try { |
| 9103 | OPC_Decode, 157, 9, 122, // 18785: decode to PVANDLOvvm using decoder 122 |
| 9104 | // 18785: } |
| 9105 | // 18785: } |
| 9106 | 6, 0, // 18789: case 0x6: { |
| 9107 | OPC_SwitchField, 47, 1, // 18791: switch Inst[47] { |
| 9108 | 0, 28, // 18794: case 0x0: { |
| 9109 | OPC_CheckField, 0, 8, 0, // 18796: check Inst[7:0] == 0x0 |
| 9110 | OPC_CheckField, 16, 8, 0, // 18800: check Inst[23:16] == 0x0 |
| 9111 | OPC_CheckField, 32, 8, 0, // 18804: check Inst[39:32] == 0x0 |
| 9112 | OPC_Scope, 9, // 18808: try { |
| 9113 | OPC_CheckField, 48, 4, 0, // 18810: check Inst[51:48] == 0x0 |
| 9114 | OPC_Decode, 255, 8, 158, 1, // 18814: decode to PVANDLOmv using decoder 158 |
| 9115 | // 18814: } else try { |
| 9116 | OPC_Decode, 133, 9, 159, 1, // 18819: decode to PVANDLOmvm using decoder 159 |
| 9117 | // 18819: } |
| 9118 | // 18819: } |
| 9119 | 1, 0, // 18824: case 0x1: { |
| 9120 | OPC_CheckField, 0, 8, 0, // 18826: check Inst[7:0] == 0x0 |
| 9121 | OPC_CheckField, 16, 8, 0, // 18830: check Inst[23:16] == 0x0 |
| 9122 | OPC_CheckField, 32, 8, 0, // 18834: check Inst[39:32] == 0x0 |
| 9123 | OPC_Scope, 8, // 18838: try { |
| 9124 | OPC_CheckField, 48, 4, 0, // 18840: check Inst[51:48] == 0x0 |
| 9125 | OPC_Decode, 139, 9, 125, // 18844: decode to PVANDLOrv using decoder 125 |
| 9126 | // 18844: } else try { |
| 9127 | OPC_Decode, 145, 9, 126, // 18848: decode to PVANDLOrvm using decoder 126 |
| 9128 | // 18848: } |
| 9129 | // 18848: } |
| 9130 | // 18848: } // switch Inst[47] |
| 9131 | // 18848: } |
| 9132 | // 18848: } // switch Inst[54:52] |
| 9133 | // 18848: } |
| 9134 | 137, 3, 181, 1, // 18852: case 0x189: { |
| 9135 | OPC_SwitchField, 52, 3, // 18856: switch Inst[54:52] { |
| 9136 | 0, 22, // 18859: case 0x0: { |
| 9137 | OPC_CheckField, 0, 8, 0, // 18861: check Inst[7:0] == 0x0 |
| 9138 | OPC_CheckField, 32, 16, 0, // 18865: check Inst[47:32] == 0x0 |
| 9139 | OPC_Scope, 8, // 18869: try { |
| 9140 | OPC_CheckField, 48, 4, 0, // 18871: check Inst[51:48] == 0x0 |
| 9141 | OPC_Decode, 187, 9, 121, // 18875: decode to PVANDUPvv using decoder 121 |
| 9142 | // 18875: } else try { |
| 9143 | OPC_Decode, 193, 9, 122, // 18879: decode to PVANDUPvvm using decoder 122 |
| 9144 | // 18879: } |
| 9145 | // 18879: } |
| 9146 | 2, 63, // 18883: case 0x2: { |
| 9147 | OPC_SwitchField, 47, 1, // 18885: switch Inst[47] { |
| 9148 | 0, 28, // 18888: case 0x0: { |
| 9149 | OPC_CheckField, 0, 8, 0, // 18890: check Inst[7:0] == 0x0 |
| 9150 | OPC_CheckField, 16, 8, 0, // 18894: check Inst[23:16] == 0x0 |
| 9151 | OPC_CheckField, 32, 8, 0, // 18898: check Inst[39:32] == 0x0 |
| 9152 | OPC_Scope, 9, // 18902: try { |
| 9153 | OPC_CheckField, 48, 4, 0, // 18904: check Inst[51:48] == 0x0 |
| 9154 | OPC_Decode, 163, 9, 158, 1, // 18908: decode to PVANDUPmv using decoder 158 |
| 9155 | // 18908: } else try { |
| 9156 | OPC_Decode, 169, 9, 159, 1, // 18913: decode to PVANDUPmvm using decoder 159 |
| 9157 | // 18913: } |
| 9158 | // 18913: } |
| 9159 | 1, 0, // 18918: case 0x1: { |
| 9160 | OPC_CheckField, 0, 8, 0, // 18920: check Inst[7:0] == 0x0 |
| 9161 | OPC_CheckField, 16, 8, 0, // 18924: check Inst[23:16] == 0x0 |
| 9162 | OPC_CheckField, 32, 8, 0, // 18928: check Inst[39:32] == 0x0 |
| 9163 | OPC_Scope, 9, // 18932: try { |
| 9164 | OPC_CheckField, 48, 4, 0, // 18934: check Inst[51:48] == 0x0 |
| 9165 | OPC_Decode, 175, 9, 210, 1, // 18938: decode to PVANDUPrv using decoder 210 |
| 9166 | // 18938: } else try { |
| 9167 | OPC_Decode, 181, 9, 211, 1, // 18943: decode to PVANDUPrvm using decoder 211 |
| 9168 | // 18943: } |
| 9169 | // 18943: } |
| 9170 | // 18943: } // switch Inst[47] |
| 9171 | // 18943: } |
| 9172 | 4, 23, // 18948: case 0x4: { |
| 9173 | OPC_CheckField, 0, 8, 0, // 18950: check Inst[7:0] == 0x0 |
| 9174 | OPC_CheckField, 32, 16, 0, // 18954: check Inst[47:32] == 0x0 |
| 9175 | OPC_Scope, 8, // 18958: try { |
| 9176 | OPC_CheckField, 48, 4, 0, // 18960: check Inst[51:48] == 0x0 |
| 9177 | OPC_Decode, 223, 9, 121, // 18964: decode to PVANDvv using decoder 121 |
| 9178 | // 18964: } else try { |
| 9179 | OPC_Decode, 229, 9, 129, 1, // 18968: decode to PVANDvvm using decoder 129 |
| 9180 | // 18968: } |
| 9181 | // 18968: } |
| 9182 | 6, 0, // 18973: case 0x6: { |
| 9183 | OPC_SwitchField, 47, 1, // 18975: switch Inst[47] { |
| 9184 | 0, 28, // 18978: case 0x0: { |
| 9185 | OPC_CheckField, 0, 8, 0, // 18980: check Inst[7:0] == 0x0 |
| 9186 | OPC_CheckField, 16, 8, 0, // 18984: check Inst[23:16] == 0x0 |
| 9187 | OPC_CheckField, 32, 8, 0, // 18988: check Inst[39:32] == 0x0 |
| 9188 | OPC_Scope, 9, // 18992: try { |
| 9189 | OPC_CheckField, 48, 4, 0, // 18994: check Inst[51:48] == 0x0 |
| 9190 | OPC_Decode, 199, 9, 158, 1, // 18998: decode to PVANDmv using decoder 158 |
| 9191 | // 18998: } else try { |
| 9192 | OPC_Decode, 205, 9, 213, 1, // 19003: decode to PVANDmvm using decoder 213 |
| 9193 | // 19003: } |
| 9194 | // 19003: } |
| 9195 | 1, 0, // 19008: case 0x1: { |
| 9196 | OPC_CheckField, 0, 8, 0, // 19010: check Inst[7:0] == 0x0 |
| 9197 | OPC_CheckField, 16, 8, 0, // 19014: check Inst[23:16] == 0x0 |
| 9198 | OPC_CheckField, 32, 8, 0, // 19018: check Inst[39:32] == 0x0 |
| 9199 | OPC_Scope, 8, // 19022: try { |
| 9200 | OPC_CheckField, 48, 4, 0, // 19024: check Inst[51:48] == 0x0 |
| 9201 | OPC_Decode, 211, 9, 127, // 19028: decode to PVANDrv using decoder 127 |
| 9202 | // 19028: } else try { |
| 9203 | OPC_Decode, 217, 9, 131, 1, // 19032: decode to PVANDrvm using decoder 131 |
| 9204 | // 19032: } |
| 9205 | // 19032: } |
| 9206 | // 19032: } // switch Inst[47] |
| 9207 | // 19032: } |
| 9208 | // 19032: } // switch Inst[54:52] |
| 9209 | // 19032: } |
| 9210 | 138, 3, 178, 1, // 19037: case 0x18a: { |
| 9211 | OPC_SwitchField, 52, 3, // 19041: switch Inst[54:52] { |
| 9212 | 0, 22, // 19044: case 0x0: { |
| 9213 | OPC_CheckField, 0, 8, 0, // 19046: check Inst[7:0] == 0x0 |
| 9214 | OPC_CheckField, 32, 16, 0, // 19050: check Inst[47:32] == 0x0 |
| 9215 | OPC_Scope, 8, // 19054: try { |
| 9216 | OPC_CheckField, 48, 4, 0, // 19056: check Inst[51:48] == 0x0 |
| 9217 | OPC_Decode, 220, 67, 121, // 19060: decode to VORvv using decoder 121 |
| 9218 | // 19060: } else try { |
| 9219 | OPC_Decode, 226, 67, 122, // 19064: decode to VORvvm using decoder 122 |
| 9220 | // 19064: } |
| 9221 | // 19064: } |
| 9222 | 2, 62, // 19068: case 0x2: { |
| 9223 | OPC_SwitchField, 47, 1, // 19070: switch Inst[47] { |
| 9224 | 0, 28, // 19073: case 0x0: { |
| 9225 | OPC_CheckField, 0, 8, 0, // 19075: check Inst[7:0] == 0x0 |
| 9226 | OPC_CheckField, 16, 8, 0, // 19079: check Inst[23:16] == 0x0 |
| 9227 | OPC_CheckField, 32, 8, 0, // 19083: check Inst[39:32] == 0x0 |
| 9228 | OPC_Scope, 9, // 19087: try { |
| 9229 | OPC_CheckField, 48, 4, 0, // 19089: check Inst[51:48] == 0x0 |
| 9230 | OPC_Decode, 196, 67, 158, 1, // 19093: decode to VORmv using decoder 158 |
| 9231 | // 19093: } else try { |
| 9232 | OPC_Decode, 202, 67, 159, 1, // 19098: decode to VORmvm using decoder 159 |
| 9233 | // 19098: } |
| 9234 | // 19098: } |
| 9235 | 1, 0, // 19103: case 0x1: { |
| 9236 | OPC_CheckField, 0, 8, 0, // 19105: check Inst[7:0] == 0x0 |
| 9237 | OPC_CheckField, 16, 8, 0, // 19109: check Inst[23:16] == 0x0 |
| 9238 | OPC_CheckField, 32, 8, 0, // 19113: check Inst[39:32] == 0x0 |
| 9239 | OPC_Scope, 8, // 19117: try { |
| 9240 | OPC_CheckField, 48, 4, 0, // 19119: check Inst[51:48] == 0x0 |
| 9241 | OPC_Decode, 208, 67, 127, // 19123: decode to VORrv using decoder 127 |
| 9242 | // 19123: } else try { |
| 9243 | OPC_Decode, 214, 67, 128, 1, // 19127: decode to VORrvm using decoder 128 |
| 9244 | // 19127: } |
| 9245 | // 19127: } |
| 9246 | // 19127: } // switch Inst[47] |
| 9247 | // 19127: } |
| 9248 | 4, 22, // 19132: case 0x4: { |
| 9249 | OPC_CheckField, 0, 8, 0, // 19134: check Inst[7:0] == 0x0 |
| 9250 | OPC_CheckField, 32, 16, 0, // 19138: check Inst[47:32] == 0x0 |
| 9251 | OPC_Scope, 8, // 19142: try { |
| 9252 | OPC_CheckField, 48, 4, 0, // 19144: check Inst[51:48] == 0x0 |
| 9253 | OPC_Decode, 231, 26, 121, // 19148: decode to PVORLOvv using decoder 121 |
| 9254 | // 19148: } else try { |
| 9255 | OPC_Decode, 237, 26, 122, // 19152: decode to PVORLOvvm using decoder 122 |
| 9256 | // 19152: } |
| 9257 | // 19152: } |
| 9258 | 6, 0, // 19156: case 0x6: { |
| 9259 | OPC_SwitchField, 47, 1, // 19158: switch Inst[47] { |
| 9260 | 0, 28, // 19161: case 0x0: { |
| 9261 | OPC_CheckField, 0, 8, 0, // 19163: check Inst[7:0] == 0x0 |
| 9262 | OPC_CheckField, 16, 8, 0, // 19167: check Inst[23:16] == 0x0 |
| 9263 | OPC_CheckField, 32, 8, 0, // 19171: check Inst[39:32] == 0x0 |
| 9264 | OPC_Scope, 9, // 19175: try { |
| 9265 | OPC_CheckField, 48, 4, 0, // 19177: check Inst[51:48] == 0x0 |
| 9266 | OPC_Decode, 207, 26, 158, 1, // 19181: decode to PVORLOmv using decoder 158 |
| 9267 | // 19181: } else try { |
| 9268 | OPC_Decode, 213, 26, 159, 1, // 19186: decode to PVORLOmvm using decoder 159 |
| 9269 | // 19186: } |
| 9270 | // 19186: } |
| 9271 | 1, 0, // 19191: case 0x1: { |
| 9272 | OPC_CheckField, 0, 8, 0, // 19193: check Inst[7:0] == 0x0 |
| 9273 | OPC_CheckField, 16, 8, 0, // 19197: check Inst[23:16] == 0x0 |
| 9274 | OPC_CheckField, 32, 8, 0, // 19201: check Inst[39:32] == 0x0 |
| 9275 | OPC_Scope, 8, // 19205: try { |
| 9276 | OPC_CheckField, 48, 4, 0, // 19207: check Inst[51:48] == 0x0 |
| 9277 | OPC_Decode, 219, 26, 125, // 19211: decode to PVORLOrv using decoder 125 |
| 9278 | // 19211: } else try { |
| 9279 | OPC_Decode, 225, 26, 126, // 19215: decode to PVORLOrvm using decoder 126 |
| 9280 | // 19215: } |
| 9281 | // 19215: } |
| 9282 | // 19215: } // switch Inst[47] |
| 9283 | // 19215: } |
| 9284 | // 19215: } // switch Inst[54:52] |
| 9285 | // 19215: } |
| 9286 | 139, 3, 181, 1, // 19219: case 0x18b: { |
| 9287 | OPC_SwitchField, 52, 3, // 19223: switch Inst[54:52] { |
| 9288 | 0, 22, // 19226: case 0x0: { |
| 9289 | OPC_CheckField, 0, 8, 0, // 19228: check Inst[7:0] == 0x0 |
| 9290 | OPC_CheckField, 32, 16, 0, // 19232: check Inst[47:32] == 0x0 |
| 9291 | OPC_Scope, 8, // 19236: try { |
| 9292 | OPC_CheckField, 48, 4, 0, // 19238: check Inst[51:48] == 0x0 |
| 9293 | OPC_Decode, 139, 27, 121, // 19242: decode to PVORUPvv using decoder 121 |
| 9294 | // 19242: } else try { |
| 9295 | OPC_Decode, 145, 27, 122, // 19246: decode to PVORUPvvm using decoder 122 |
| 9296 | // 19246: } |
| 9297 | // 19246: } |
| 9298 | 2, 63, // 19250: case 0x2: { |
| 9299 | OPC_SwitchField, 47, 1, // 19252: switch Inst[47] { |
| 9300 | 0, 28, // 19255: case 0x0: { |
| 9301 | OPC_CheckField, 0, 8, 0, // 19257: check Inst[7:0] == 0x0 |
| 9302 | OPC_CheckField, 16, 8, 0, // 19261: check Inst[23:16] == 0x0 |
| 9303 | OPC_CheckField, 32, 8, 0, // 19265: check Inst[39:32] == 0x0 |
| 9304 | OPC_Scope, 9, // 19269: try { |
| 9305 | OPC_CheckField, 48, 4, 0, // 19271: check Inst[51:48] == 0x0 |
| 9306 | OPC_Decode, 243, 26, 158, 1, // 19275: decode to PVORUPmv using decoder 158 |
| 9307 | // 19275: } else try { |
| 9308 | OPC_Decode, 249, 26, 159, 1, // 19280: decode to PVORUPmvm using decoder 159 |
| 9309 | // 19280: } |
| 9310 | // 19280: } |
| 9311 | 1, 0, // 19285: case 0x1: { |
| 9312 | OPC_CheckField, 0, 8, 0, // 19287: check Inst[7:0] == 0x0 |
| 9313 | OPC_CheckField, 16, 8, 0, // 19291: check Inst[23:16] == 0x0 |
| 9314 | OPC_CheckField, 32, 8, 0, // 19295: check Inst[39:32] == 0x0 |
| 9315 | OPC_Scope, 9, // 19299: try { |
| 9316 | OPC_CheckField, 48, 4, 0, // 19301: check Inst[51:48] == 0x0 |
| 9317 | OPC_Decode, 255, 26, 210, 1, // 19305: decode to PVORUPrv using decoder 210 |
| 9318 | // 19305: } else try { |
| 9319 | OPC_Decode, 133, 27, 211, 1, // 19310: decode to PVORUPrvm using decoder 211 |
| 9320 | // 19310: } |
| 9321 | // 19310: } |
| 9322 | // 19310: } // switch Inst[47] |
| 9323 | // 19310: } |
| 9324 | 4, 23, // 19315: case 0x4: { |
| 9325 | OPC_CheckField, 0, 8, 0, // 19317: check Inst[7:0] == 0x0 |
| 9326 | OPC_CheckField, 32, 16, 0, // 19321: check Inst[47:32] == 0x0 |
| 9327 | OPC_Scope, 8, // 19325: try { |
| 9328 | OPC_CheckField, 48, 4, 0, // 19327: check Inst[51:48] == 0x0 |
| 9329 | OPC_Decode, 175, 27, 121, // 19331: decode to PVORvv using decoder 121 |
| 9330 | // 19331: } else try { |
| 9331 | OPC_Decode, 181, 27, 129, 1, // 19335: decode to PVORvvm using decoder 129 |
| 9332 | // 19335: } |
| 9333 | // 19335: } |
| 9334 | 6, 0, // 19340: case 0x6: { |
| 9335 | OPC_SwitchField, 47, 1, // 19342: switch Inst[47] { |
| 9336 | 0, 28, // 19345: case 0x0: { |
| 9337 | OPC_CheckField, 0, 8, 0, // 19347: check Inst[7:0] == 0x0 |
| 9338 | OPC_CheckField, 16, 8, 0, // 19351: check Inst[23:16] == 0x0 |
| 9339 | OPC_CheckField, 32, 8, 0, // 19355: check Inst[39:32] == 0x0 |
| 9340 | OPC_Scope, 9, // 19359: try { |
| 9341 | OPC_CheckField, 48, 4, 0, // 19361: check Inst[51:48] == 0x0 |
| 9342 | OPC_Decode, 151, 27, 158, 1, // 19365: decode to PVORmv using decoder 158 |
| 9343 | // 19365: } else try { |
| 9344 | OPC_Decode, 157, 27, 213, 1, // 19370: decode to PVORmvm using decoder 213 |
| 9345 | // 19370: } |
| 9346 | // 19370: } |
| 9347 | 1, 0, // 19375: case 0x1: { |
| 9348 | OPC_CheckField, 0, 8, 0, // 19377: check Inst[7:0] == 0x0 |
| 9349 | OPC_CheckField, 16, 8, 0, // 19381: check Inst[23:16] == 0x0 |
| 9350 | OPC_CheckField, 32, 8, 0, // 19385: check Inst[39:32] == 0x0 |
| 9351 | OPC_Scope, 8, // 19389: try { |
| 9352 | OPC_CheckField, 48, 4, 0, // 19391: check Inst[51:48] == 0x0 |
| 9353 | OPC_Decode, 163, 27, 127, // 19395: decode to PVORrv using decoder 127 |
| 9354 | // 19395: } else try { |
| 9355 | OPC_Decode, 169, 27, 131, 1, // 19399: decode to PVORrvm using decoder 131 |
| 9356 | // 19399: } |
| 9357 | // 19399: } |
| 9358 | // 19399: } // switch Inst[47] |
| 9359 | // 19399: } |
| 9360 | // 19399: } // switch Inst[54:52] |
| 9361 | // 19399: } |
| 9362 | 140, 3, 178, 1, // 19404: case 0x18c: { |
| 9363 | OPC_SwitchField, 52, 3, // 19408: switch Inst[54:52] { |
| 9364 | 0, 22, // 19411: case 0x0: { |
| 9365 | OPC_CheckField, 0, 8, 0, // 19413: check Inst[7:0] == 0x0 |
| 9366 | OPC_CheckField, 32, 16, 0, // 19417: check Inst[47:32] == 0x0 |
| 9367 | OPC_Scope, 8, // 19421: try { |
| 9368 | OPC_CheckField, 48, 4, 0, // 19423: check Inst[51:48] == 0x0 |
| 9369 | OPC_Decode, 248, 83, 121, // 19427: decode to VXORvv using decoder 121 |
| 9370 | // 19427: } else try { |
| 9371 | OPC_Decode, 254, 83, 122, // 19431: decode to VXORvvm using decoder 122 |
| 9372 | // 19431: } |
| 9373 | // 19431: } |
| 9374 | 2, 62, // 19435: case 0x2: { |
| 9375 | OPC_SwitchField, 47, 1, // 19437: switch Inst[47] { |
| 9376 | 0, 28, // 19440: case 0x0: { |
| 9377 | OPC_CheckField, 0, 8, 0, // 19442: check Inst[7:0] == 0x0 |
| 9378 | OPC_CheckField, 16, 8, 0, // 19446: check Inst[23:16] == 0x0 |
| 9379 | OPC_CheckField, 32, 8, 0, // 19450: check Inst[39:32] == 0x0 |
| 9380 | OPC_Scope, 9, // 19454: try { |
| 9381 | OPC_CheckField, 48, 4, 0, // 19456: check Inst[51:48] == 0x0 |
| 9382 | OPC_Decode, 224, 83, 158, 1, // 19460: decode to VXORmv using decoder 158 |
| 9383 | // 19460: } else try { |
| 9384 | OPC_Decode, 230, 83, 159, 1, // 19465: decode to VXORmvm using decoder 159 |
| 9385 | // 19465: } |
| 9386 | // 19465: } |
| 9387 | 1, 0, // 19470: case 0x1: { |
| 9388 | OPC_CheckField, 0, 8, 0, // 19472: check Inst[7:0] == 0x0 |
| 9389 | OPC_CheckField, 16, 8, 0, // 19476: check Inst[23:16] == 0x0 |
| 9390 | OPC_CheckField, 32, 8, 0, // 19480: check Inst[39:32] == 0x0 |
| 9391 | OPC_Scope, 8, // 19484: try { |
| 9392 | OPC_CheckField, 48, 4, 0, // 19486: check Inst[51:48] == 0x0 |
| 9393 | OPC_Decode, 236, 83, 127, // 19490: decode to VXORrv using decoder 127 |
| 9394 | // 19490: } else try { |
| 9395 | OPC_Decode, 242, 83, 128, 1, // 19494: decode to VXORrvm using decoder 128 |
| 9396 | // 19494: } |
| 9397 | // 19494: } |
| 9398 | // 19494: } // switch Inst[47] |
| 9399 | // 19494: } |
| 9400 | 4, 22, // 19499: case 0x4: { |
| 9401 | OPC_CheckField, 0, 8, 0, // 19501: check Inst[7:0] == 0x0 |
| 9402 | OPC_CheckField, 32, 16, 0, // 19505: check Inst[47:32] == 0x0 |
| 9403 | OPC_Scope, 8, // 19509: try { |
| 9404 | OPC_CheckField, 48, 4, 0, // 19511: check Inst[51:48] == 0x0 |
| 9405 | OPC_Decode, 143, 34, 121, // 19515: decode to PVXORLOvv using decoder 121 |
| 9406 | // 19515: } else try { |
| 9407 | OPC_Decode, 149, 34, 122, // 19519: decode to PVXORLOvvm using decoder 122 |
| 9408 | // 19519: } |
| 9409 | // 19519: } |
| 9410 | 6, 0, // 19523: case 0x6: { |
| 9411 | OPC_SwitchField, 47, 1, // 19525: switch Inst[47] { |
| 9412 | 0, 28, // 19528: case 0x0: { |
| 9413 | OPC_CheckField, 0, 8, 0, // 19530: check Inst[7:0] == 0x0 |
| 9414 | OPC_CheckField, 16, 8, 0, // 19534: check Inst[23:16] == 0x0 |
| 9415 | OPC_CheckField, 32, 8, 0, // 19538: check Inst[39:32] == 0x0 |
| 9416 | OPC_Scope, 9, // 19542: try { |
| 9417 | OPC_CheckField, 48, 4, 0, // 19544: check Inst[51:48] == 0x0 |
| 9418 | OPC_Decode, 247, 33, 158, 1, // 19548: decode to PVXORLOmv using decoder 158 |
| 9419 | // 19548: } else try { |
| 9420 | OPC_Decode, 253, 33, 159, 1, // 19553: decode to PVXORLOmvm using decoder 159 |
| 9421 | // 19553: } |
| 9422 | // 19553: } |
| 9423 | 1, 0, // 19558: case 0x1: { |
| 9424 | OPC_CheckField, 0, 8, 0, // 19560: check Inst[7:0] == 0x0 |
| 9425 | OPC_CheckField, 16, 8, 0, // 19564: check Inst[23:16] == 0x0 |
| 9426 | OPC_CheckField, 32, 8, 0, // 19568: check Inst[39:32] == 0x0 |
| 9427 | OPC_Scope, 8, // 19572: try { |
| 9428 | OPC_CheckField, 48, 4, 0, // 19574: check Inst[51:48] == 0x0 |
| 9429 | OPC_Decode, 131, 34, 125, // 19578: decode to PVXORLOrv using decoder 125 |
| 9430 | // 19578: } else try { |
| 9431 | OPC_Decode, 137, 34, 126, // 19582: decode to PVXORLOrvm using decoder 126 |
| 9432 | // 19582: } |
| 9433 | // 19582: } |
| 9434 | // 19582: } // switch Inst[47] |
| 9435 | // 19582: } |
| 9436 | // 19582: } // switch Inst[54:52] |
| 9437 | // 19582: } |
| 9438 | 141, 3, 181, 1, // 19586: case 0x18d: { |
| 9439 | OPC_SwitchField, 52, 3, // 19590: switch Inst[54:52] { |
| 9440 | 0, 22, // 19593: case 0x0: { |
| 9441 | OPC_CheckField, 0, 8, 0, // 19595: check Inst[7:0] == 0x0 |
| 9442 | OPC_CheckField, 32, 16, 0, // 19599: check Inst[47:32] == 0x0 |
| 9443 | OPC_Scope, 8, // 19603: try { |
| 9444 | OPC_CheckField, 48, 4, 0, // 19605: check Inst[51:48] == 0x0 |
| 9445 | OPC_Decode, 179, 34, 121, // 19609: decode to PVXORUPvv using decoder 121 |
| 9446 | // 19609: } else try { |
| 9447 | OPC_Decode, 185, 34, 122, // 19613: decode to PVXORUPvvm using decoder 122 |
| 9448 | // 19613: } |
| 9449 | // 19613: } |
| 9450 | 2, 63, // 19617: case 0x2: { |
| 9451 | OPC_SwitchField, 47, 1, // 19619: switch Inst[47] { |
| 9452 | 0, 28, // 19622: case 0x0: { |
| 9453 | OPC_CheckField, 0, 8, 0, // 19624: check Inst[7:0] == 0x0 |
| 9454 | OPC_CheckField, 16, 8, 0, // 19628: check Inst[23:16] == 0x0 |
| 9455 | OPC_CheckField, 32, 8, 0, // 19632: check Inst[39:32] == 0x0 |
| 9456 | OPC_Scope, 9, // 19636: try { |
| 9457 | OPC_CheckField, 48, 4, 0, // 19638: check Inst[51:48] == 0x0 |
| 9458 | OPC_Decode, 155, 34, 158, 1, // 19642: decode to PVXORUPmv using decoder 158 |
| 9459 | // 19642: } else try { |
| 9460 | OPC_Decode, 161, 34, 159, 1, // 19647: decode to PVXORUPmvm using decoder 159 |
| 9461 | // 19647: } |
| 9462 | // 19647: } |
| 9463 | 1, 0, // 19652: case 0x1: { |
| 9464 | OPC_CheckField, 0, 8, 0, // 19654: check Inst[7:0] == 0x0 |
| 9465 | OPC_CheckField, 16, 8, 0, // 19658: check Inst[23:16] == 0x0 |
| 9466 | OPC_CheckField, 32, 8, 0, // 19662: check Inst[39:32] == 0x0 |
| 9467 | OPC_Scope, 9, // 19666: try { |
| 9468 | OPC_CheckField, 48, 4, 0, // 19668: check Inst[51:48] == 0x0 |
| 9469 | OPC_Decode, 167, 34, 210, 1, // 19672: decode to PVXORUPrv using decoder 210 |
| 9470 | // 19672: } else try { |
| 9471 | OPC_Decode, 173, 34, 211, 1, // 19677: decode to PVXORUPrvm using decoder 211 |
| 9472 | // 19677: } |
| 9473 | // 19677: } |
| 9474 | // 19677: } // switch Inst[47] |
| 9475 | // 19677: } |
| 9476 | 4, 23, // 19682: case 0x4: { |
| 9477 | OPC_CheckField, 0, 8, 0, // 19684: check Inst[7:0] == 0x0 |
| 9478 | OPC_CheckField, 32, 16, 0, // 19688: check Inst[47:32] == 0x0 |
| 9479 | OPC_Scope, 8, // 19692: try { |
| 9480 | OPC_CheckField, 48, 4, 0, // 19694: check Inst[51:48] == 0x0 |
| 9481 | OPC_Decode, 215, 34, 121, // 19698: decode to PVXORvv using decoder 121 |
| 9482 | // 19698: } else try { |
| 9483 | OPC_Decode, 221, 34, 129, 1, // 19702: decode to PVXORvvm using decoder 129 |
| 9484 | // 19702: } |
| 9485 | // 19702: } |
| 9486 | 6, 0, // 19707: case 0x6: { |
| 9487 | OPC_SwitchField, 47, 1, // 19709: switch Inst[47] { |
| 9488 | 0, 28, // 19712: case 0x0: { |
| 9489 | OPC_CheckField, 0, 8, 0, // 19714: check Inst[7:0] == 0x0 |
| 9490 | OPC_CheckField, 16, 8, 0, // 19718: check Inst[23:16] == 0x0 |
| 9491 | OPC_CheckField, 32, 8, 0, // 19722: check Inst[39:32] == 0x0 |
| 9492 | OPC_Scope, 9, // 19726: try { |
| 9493 | OPC_CheckField, 48, 4, 0, // 19728: check Inst[51:48] == 0x0 |
| 9494 | OPC_Decode, 191, 34, 158, 1, // 19732: decode to PVXORmv using decoder 158 |
| 9495 | // 19732: } else try { |
| 9496 | OPC_Decode, 197, 34, 213, 1, // 19737: decode to PVXORmvm using decoder 213 |
| 9497 | // 19737: } |
| 9498 | // 19737: } |
| 9499 | 1, 0, // 19742: case 0x1: { |
| 9500 | OPC_CheckField, 0, 8, 0, // 19744: check Inst[7:0] == 0x0 |
| 9501 | OPC_CheckField, 16, 8, 0, // 19748: check Inst[23:16] == 0x0 |
| 9502 | OPC_CheckField, 32, 8, 0, // 19752: check Inst[39:32] == 0x0 |
| 9503 | OPC_Scope, 8, // 19756: try { |
| 9504 | OPC_CheckField, 48, 4, 0, // 19758: check Inst[51:48] == 0x0 |
| 9505 | OPC_Decode, 203, 34, 127, // 19762: decode to PVXORrv using decoder 127 |
| 9506 | // 19762: } else try { |
| 9507 | OPC_Decode, 209, 34, 131, 1, // 19766: decode to PVXORrvm using decoder 131 |
| 9508 | // 19766: } |
| 9509 | // 19766: } |
| 9510 | // 19766: } // switch Inst[47] |
| 9511 | // 19766: } |
| 9512 | // 19766: } // switch Inst[54:52] |
| 9513 | // 19766: } |
| 9514 | 142, 3, 178, 1, // 19771: case 0x18e: { |
| 9515 | OPC_SwitchField, 52, 3, // 19775: switch Inst[54:52] { |
| 9516 | 0, 22, // 19778: case 0x0: { |
| 9517 | OPC_CheckField, 0, 8, 0, // 19780: check Inst[7:0] == 0x0 |
| 9518 | OPC_CheckField, 32, 16, 0, // 19784: check Inst[47:32] == 0x0 |
| 9519 | OPC_Scope, 8, // 19788: try { |
| 9520 | OPC_CheckField, 48, 4, 0, // 19790: check Inst[51:48] == 0x0 |
| 9521 | OPC_Decode, 136, 43, 121, // 19794: decode to VEQVvv using decoder 121 |
| 9522 | // 19794: } else try { |
| 9523 | OPC_Decode, 142, 43, 122, // 19798: decode to VEQVvvm using decoder 122 |
| 9524 | // 19798: } |
| 9525 | // 19798: } |
| 9526 | 2, 62, // 19802: case 0x2: { |
| 9527 | OPC_SwitchField, 47, 1, // 19804: switch Inst[47] { |
| 9528 | 0, 28, // 19807: case 0x0: { |
| 9529 | OPC_CheckField, 0, 8, 0, // 19809: check Inst[7:0] == 0x0 |
| 9530 | OPC_CheckField, 16, 8, 0, // 19813: check Inst[23:16] == 0x0 |
| 9531 | OPC_CheckField, 32, 8, 0, // 19817: check Inst[39:32] == 0x0 |
| 9532 | OPC_Scope, 9, // 19821: try { |
| 9533 | OPC_CheckField, 48, 4, 0, // 19823: check Inst[51:48] == 0x0 |
| 9534 | OPC_Decode, 240, 42, 158, 1, // 19827: decode to VEQVmv using decoder 158 |
| 9535 | // 19827: } else try { |
| 9536 | OPC_Decode, 246, 42, 159, 1, // 19832: decode to VEQVmvm using decoder 159 |
| 9537 | // 19832: } |
| 9538 | // 19832: } |
| 9539 | 1, 0, // 19837: case 0x1: { |
| 9540 | OPC_CheckField, 0, 8, 0, // 19839: check Inst[7:0] == 0x0 |
| 9541 | OPC_CheckField, 16, 8, 0, // 19843: check Inst[23:16] == 0x0 |
| 9542 | OPC_CheckField, 32, 8, 0, // 19847: check Inst[39:32] == 0x0 |
| 9543 | OPC_Scope, 8, // 19851: try { |
| 9544 | OPC_CheckField, 48, 4, 0, // 19853: check Inst[51:48] == 0x0 |
| 9545 | OPC_Decode, 252, 42, 127, // 19857: decode to VEQVrv using decoder 127 |
| 9546 | // 19857: } else try { |
| 9547 | OPC_Decode, 130, 43, 128, 1, // 19861: decode to VEQVrvm using decoder 128 |
| 9548 | // 19861: } |
| 9549 | // 19861: } |
| 9550 | // 19861: } // switch Inst[47] |
| 9551 | // 19861: } |
| 9552 | 4, 22, // 19866: case 0x4: { |
| 9553 | OPC_CheckField, 0, 8, 0, // 19868: check Inst[7:0] == 0x0 |
| 9554 | OPC_CheckField, 32, 16, 0, // 19872: check Inst[47:32] == 0x0 |
| 9555 | OPC_Scope, 8, // 19876: try { |
| 9556 | OPC_CheckField, 48, 4, 0, // 19878: check Inst[51:48] == 0x0 |
| 9557 | OPC_Decode, 223, 12, 121, // 19882: decode to PVEQVLOvv using decoder 121 |
| 9558 | // 19882: } else try { |
| 9559 | OPC_Decode, 229, 12, 122, // 19886: decode to PVEQVLOvvm using decoder 122 |
| 9560 | // 19886: } |
| 9561 | // 19886: } |
| 9562 | 6, 0, // 19890: case 0x6: { |
| 9563 | OPC_SwitchField, 47, 1, // 19892: switch Inst[47] { |
| 9564 | 0, 28, // 19895: case 0x0: { |
| 9565 | OPC_CheckField, 0, 8, 0, // 19897: check Inst[7:0] == 0x0 |
| 9566 | OPC_CheckField, 16, 8, 0, // 19901: check Inst[23:16] == 0x0 |
| 9567 | OPC_CheckField, 32, 8, 0, // 19905: check Inst[39:32] == 0x0 |
| 9568 | OPC_Scope, 9, // 19909: try { |
| 9569 | OPC_CheckField, 48, 4, 0, // 19911: check Inst[51:48] == 0x0 |
| 9570 | OPC_Decode, 199, 12, 158, 1, // 19915: decode to PVEQVLOmv using decoder 158 |
| 9571 | // 19915: } else try { |
| 9572 | OPC_Decode, 205, 12, 159, 1, // 19920: decode to PVEQVLOmvm using decoder 159 |
| 9573 | // 19920: } |
| 9574 | // 19920: } |
| 9575 | 1, 0, // 19925: case 0x1: { |
| 9576 | OPC_CheckField, 0, 8, 0, // 19927: check Inst[7:0] == 0x0 |
| 9577 | OPC_CheckField, 16, 8, 0, // 19931: check Inst[23:16] == 0x0 |
| 9578 | OPC_CheckField, 32, 8, 0, // 19935: check Inst[39:32] == 0x0 |
| 9579 | OPC_Scope, 8, // 19939: try { |
| 9580 | OPC_CheckField, 48, 4, 0, // 19941: check Inst[51:48] == 0x0 |
| 9581 | OPC_Decode, 211, 12, 125, // 19945: decode to PVEQVLOrv using decoder 125 |
| 9582 | // 19945: } else try { |
| 9583 | OPC_Decode, 217, 12, 126, // 19949: decode to PVEQVLOrvm using decoder 126 |
| 9584 | // 19949: } |
| 9585 | // 19949: } |
| 9586 | // 19949: } // switch Inst[47] |
| 9587 | // 19949: } |
| 9588 | // 19949: } // switch Inst[54:52] |
| 9589 | // 19949: } |
| 9590 | 143, 3, 181, 1, // 19953: case 0x18f: { |
| 9591 | OPC_SwitchField, 52, 3, // 19957: switch Inst[54:52] { |
| 9592 | 0, 22, // 19960: case 0x0: { |
| 9593 | OPC_CheckField, 0, 8, 0, // 19962: check Inst[7:0] == 0x0 |
| 9594 | OPC_CheckField, 32, 16, 0, // 19966: check Inst[47:32] == 0x0 |
| 9595 | OPC_Scope, 8, // 19970: try { |
| 9596 | OPC_CheckField, 48, 4, 0, // 19972: check Inst[51:48] == 0x0 |
| 9597 | OPC_Decode, 131, 13, 121, // 19976: decode to PVEQVUPvv using decoder 121 |
| 9598 | // 19976: } else try { |
| 9599 | OPC_Decode, 137, 13, 122, // 19980: decode to PVEQVUPvvm using decoder 122 |
| 9600 | // 19980: } |
| 9601 | // 19980: } |
| 9602 | 2, 63, // 19984: case 0x2: { |
| 9603 | OPC_SwitchField, 47, 1, // 19986: switch Inst[47] { |
| 9604 | 0, 28, // 19989: case 0x0: { |
| 9605 | OPC_CheckField, 0, 8, 0, // 19991: check Inst[7:0] == 0x0 |
| 9606 | OPC_CheckField, 16, 8, 0, // 19995: check Inst[23:16] == 0x0 |
| 9607 | OPC_CheckField, 32, 8, 0, // 19999: check Inst[39:32] == 0x0 |
| 9608 | OPC_Scope, 9, // 20003: try { |
| 9609 | OPC_CheckField, 48, 4, 0, // 20005: check Inst[51:48] == 0x0 |
| 9610 | OPC_Decode, 235, 12, 158, 1, // 20009: decode to PVEQVUPmv using decoder 158 |
| 9611 | // 20009: } else try { |
| 9612 | OPC_Decode, 241, 12, 159, 1, // 20014: decode to PVEQVUPmvm using decoder 159 |
| 9613 | // 20014: } |
| 9614 | // 20014: } |
| 9615 | 1, 0, // 20019: case 0x1: { |
| 9616 | OPC_CheckField, 0, 8, 0, // 20021: check Inst[7:0] == 0x0 |
| 9617 | OPC_CheckField, 16, 8, 0, // 20025: check Inst[23:16] == 0x0 |
| 9618 | OPC_CheckField, 32, 8, 0, // 20029: check Inst[39:32] == 0x0 |
| 9619 | OPC_Scope, 9, // 20033: try { |
| 9620 | OPC_CheckField, 48, 4, 0, // 20035: check Inst[51:48] == 0x0 |
| 9621 | OPC_Decode, 247, 12, 210, 1, // 20039: decode to PVEQVUPrv using decoder 210 |
| 9622 | // 20039: } else try { |
| 9623 | OPC_Decode, 253, 12, 211, 1, // 20044: decode to PVEQVUPrvm using decoder 211 |
| 9624 | // 20044: } |
| 9625 | // 20044: } |
| 9626 | // 20044: } // switch Inst[47] |
| 9627 | // 20044: } |
| 9628 | 4, 23, // 20049: case 0x4: { |
| 9629 | OPC_CheckField, 0, 8, 0, // 20051: check Inst[7:0] == 0x0 |
| 9630 | OPC_CheckField, 32, 16, 0, // 20055: check Inst[47:32] == 0x0 |
| 9631 | OPC_Scope, 8, // 20059: try { |
| 9632 | OPC_CheckField, 48, 4, 0, // 20061: check Inst[51:48] == 0x0 |
| 9633 | OPC_Decode, 167, 13, 121, // 20065: decode to PVEQVvv using decoder 121 |
| 9634 | // 20065: } else try { |
| 9635 | OPC_Decode, 173, 13, 129, 1, // 20069: decode to PVEQVvvm using decoder 129 |
| 9636 | // 20069: } |
| 9637 | // 20069: } |
| 9638 | 6, 0, // 20074: case 0x6: { |
| 9639 | OPC_SwitchField, 47, 1, // 20076: switch Inst[47] { |
| 9640 | 0, 28, // 20079: case 0x0: { |
| 9641 | OPC_CheckField, 0, 8, 0, // 20081: check Inst[7:0] == 0x0 |
| 9642 | OPC_CheckField, 16, 8, 0, // 20085: check Inst[23:16] == 0x0 |
| 9643 | OPC_CheckField, 32, 8, 0, // 20089: check Inst[39:32] == 0x0 |
| 9644 | OPC_Scope, 9, // 20093: try { |
| 9645 | OPC_CheckField, 48, 4, 0, // 20095: check Inst[51:48] == 0x0 |
| 9646 | OPC_Decode, 143, 13, 158, 1, // 20099: decode to PVEQVmv using decoder 158 |
| 9647 | // 20099: } else try { |
| 9648 | OPC_Decode, 149, 13, 213, 1, // 20104: decode to PVEQVmvm using decoder 213 |
| 9649 | // 20104: } |
| 9650 | // 20104: } |
| 9651 | 1, 0, // 20109: case 0x1: { |
| 9652 | OPC_CheckField, 0, 8, 0, // 20111: check Inst[7:0] == 0x0 |
| 9653 | OPC_CheckField, 16, 8, 0, // 20115: check Inst[23:16] == 0x0 |
| 9654 | OPC_CheckField, 32, 8, 0, // 20119: check Inst[39:32] == 0x0 |
| 9655 | OPC_Scope, 8, // 20123: try { |
| 9656 | OPC_CheckField, 48, 4, 0, // 20125: check Inst[51:48] == 0x0 |
| 9657 | OPC_Decode, 155, 13, 127, // 20129: decode to PVEQVrv using decoder 127 |
| 9658 | // 20129: } else try { |
| 9659 | OPC_Decode, 161, 13, 131, 1, // 20133: decode to PVEQVrvm using decoder 131 |
| 9660 | // 20133: } |
| 9661 | // 20133: } |
| 9662 | // 20133: } // switch Inst[47] |
| 9663 | // 20133: } |
| 9664 | // 20133: } // switch Inst[54:52] |
| 9665 | // 20133: } |
| 9666 | 144, 3, 174, 1, // 20138: case 0x190: { |
| 9667 | OPC_SwitchField, 52, 3, // 20142: switch Inst[54:52] { |
| 9668 | 0, 22, // 20145: case 0x0: { |
| 9669 | OPC_CheckField, 0, 8, 0, // 20147: check Inst[7:0] == 0x0 |
| 9670 | OPC_CheckField, 32, 16, 0, // 20151: check Inst[47:32] == 0x0 |
| 9671 | OPC_Scope, 8, // 20155: try { |
| 9672 | OPC_CheckField, 48, 4, 0, // 20157: check Inst[51:48] == 0x0 |
| 9673 | OPC_Decode, 228, 36, 121, // 20161: decode to VADDULvv using decoder 121 |
| 9674 | // 20161: } else try { |
| 9675 | OPC_Decode, 234, 36, 122, // 20165: decode to VADDULvvm using decoder 122 |
| 9676 | // 20165: } |
| 9677 | // 20165: } |
| 9678 | 2, 60, // 20169: case 0x2: { |
| 9679 | OPC_SwitchField, 47, 1, // 20171: switch Inst[47] { |
| 9680 | 0, 26, // 20174: case 0x0: { |
| 9681 | OPC_CheckField, 0, 8, 0, // 20176: check Inst[7:0] == 0x0 |
| 9682 | OPC_CheckField, 16, 8, 0, // 20180: check Inst[23:16] == 0x0 |
| 9683 | OPC_CheckField, 32, 8, 0, // 20184: check Inst[39:32] == 0x0 |
| 9684 | OPC_Scope, 8, // 20188: try { |
| 9685 | OPC_CheckField, 48, 4, 0, // 20190: check Inst[51:48] == 0x0 |
| 9686 | OPC_Decode, 204, 36, 123, // 20194: decode to VADDULiv using decoder 123 |
| 9687 | // 20194: } else try { |
| 9688 | OPC_Decode, 210, 36, 124, // 20198: decode to VADDULivm using decoder 124 |
| 9689 | // 20198: } |
| 9690 | // 20198: } |
| 9691 | 1, 0, // 20202: case 0x1: { |
| 9692 | OPC_CheckField, 0, 8, 0, // 20204: check Inst[7:0] == 0x0 |
| 9693 | OPC_CheckField, 16, 8, 0, // 20208: check Inst[23:16] == 0x0 |
| 9694 | OPC_CheckField, 32, 8, 0, // 20212: check Inst[39:32] == 0x0 |
| 9695 | OPC_Scope, 8, // 20216: try { |
| 9696 | OPC_CheckField, 48, 4, 0, // 20218: check Inst[51:48] == 0x0 |
| 9697 | OPC_Decode, 216, 36, 127, // 20222: decode to VADDULrv using decoder 127 |
| 9698 | // 20222: } else try { |
| 9699 | OPC_Decode, 222, 36, 128, 1, // 20226: decode to VADDULrvm using decoder 128 |
| 9700 | // 20226: } |
| 9701 | // 20226: } |
| 9702 | // 20226: } // switch Inst[47] |
| 9703 | // 20226: } |
| 9704 | 4, 22, // 20231: case 0x4: { |
| 9705 | OPC_CheckField, 0, 8, 0, // 20233: check Inst[7:0] == 0x0 |
| 9706 | OPC_CheckField, 32, 16, 0, // 20237: check Inst[47:32] == 0x0 |
| 9707 | OPC_Scope, 8, // 20241: try { |
| 9708 | OPC_CheckField, 48, 4, 0, // 20243: check Inst[51:48] == 0x0 |
| 9709 | OPC_Decode, 171, 8, 121, // 20247: decode to PVADDULOvv using decoder 121 |
| 9710 | // 20247: } else try { |
| 9711 | OPC_Decode, 177, 8, 122, // 20251: decode to PVADDULOvvm using decoder 122 |
| 9712 | // 20251: } |
| 9713 | // 20251: } |
| 9714 | 6, 0, // 20255: case 0x6: { |
| 9715 | OPC_SwitchField, 47, 1, // 20257: switch Inst[47] { |
| 9716 | 0, 26, // 20260: case 0x0: { |
| 9717 | OPC_CheckField, 0, 8, 0, // 20262: check Inst[7:0] == 0x0 |
| 9718 | OPC_CheckField, 16, 8, 0, // 20266: check Inst[23:16] == 0x0 |
| 9719 | OPC_CheckField, 32, 8, 0, // 20270: check Inst[39:32] == 0x0 |
| 9720 | OPC_Scope, 8, // 20274: try { |
| 9721 | OPC_CheckField, 48, 4, 0, // 20276: check Inst[51:48] == 0x0 |
| 9722 | OPC_Decode, 147, 8, 123, // 20280: decode to PVADDULOiv using decoder 123 |
| 9723 | // 20280: } else try { |
| 9724 | OPC_Decode, 153, 8, 124, // 20284: decode to PVADDULOivm using decoder 124 |
| 9725 | // 20284: } |
| 9726 | // 20284: } |
| 9727 | 1, 0, // 20288: case 0x1: { |
| 9728 | OPC_CheckField, 0, 8, 0, // 20290: check Inst[7:0] == 0x0 |
| 9729 | OPC_CheckField, 16, 8, 0, // 20294: check Inst[23:16] == 0x0 |
| 9730 | OPC_CheckField, 32, 8, 0, // 20298: check Inst[39:32] == 0x0 |
| 9731 | OPC_Scope, 8, // 20302: try { |
| 9732 | OPC_CheckField, 48, 4, 0, // 20304: check Inst[51:48] == 0x0 |
| 9733 | OPC_Decode, 159, 8, 125, // 20308: decode to PVADDULOrv using decoder 125 |
| 9734 | // 20308: } else try { |
| 9735 | OPC_Decode, 165, 8, 126, // 20312: decode to PVADDULOrvm using decoder 126 |
| 9736 | // 20312: } |
| 9737 | // 20312: } |
| 9738 | // 20312: } // switch Inst[47] |
| 9739 | // 20312: } |
| 9740 | // 20312: } // switch Inst[54:52] |
| 9741 | // 20312: } |
| 9742 | 145, 3, 177, 1, // 20316: case 0x191: { |
| 9743 | OPC_SwitchField, 52, 3, // 20320: switch Inst[54:52] { |
| 9744 | 0, 22, // 20323: case 0x0: { |
| 9745 | OPC_CheckField, 0, 8, 0, // 20325: check Inst[7:0] == 0x0 |
| 9746 | OPC_CheckField, 32, 16, 0, // 20329: check Inst[47:32] == 0x0 |
| 9747 | OPC_Scope, 8, // 20333: try { |
| 9748 | OPC_CheckField, 48, 4, 0, // 20335: check Inst[51:48] == 0x0 |
| 9749 | OPC_Decode, 207, 8, 121, // 20339: decode to PVADDUUPvv using decoder 121 |
| 9750 | // 20339: } else try { |
| 9751 | OPC_Decode, 213, 8, 122, // 20343: decode to PVADDUUPvvm using decoder 122 |
| 9752 | // 20343: } |
| 9753 | // 20343: } |
| 9754 | 2, 60, // 20347: case 0x2: { |
| 9755 | OPC_SwitchField, 47, 1, // 20349: switch Inst[47] { |
| 9756 | 0, 26, // 20352: case 0x0: { |
| 9757 | OPC_CheckField, 0, 8, 0, // 20354: check Inst[7:0] == 0x0 |
| 9758 | OPC_CheckField, 16, 8, 0, // 20358: check Inst[23:16] == 0x0 |
| 9759 | OPC_CheckField, 32, 8, 0, // 20362: check Inst[39:32] == 0x0 |
| 9760 | OPC_Scope, 8, // 20366: try { |
| 9761 | OPC_CheckField, 48, 4, 0, // 20368: check Inst[51:48] == 0x0 |
| 9762 | OPC_Decode, 183, 8, 123, // 20372: decode to PVADDUUPiv using decoder 123 |
| 9763 | // 20372: } else try { |
| 9764 | OPC_Decode, 189, 8, 124, // 20376: decode to PVADDUUPivm using decoder 124 |
| 9765 | // 20376: } |
| 9766 | // 20376: } |
| 9767 | 1, 0, // 20380: case 0x1: { |
| 9768 | OPC_CheckField, 0, 8, 0, // 20382: check Inst[7:0] == 0x0 |
| 9769 | OPC_CheckField, 16, 8, 0, // 20386: check Inst[23:16] == 0x0 |
| 9770 | OPC_CheckField, 32, 8, 0, // 20390: check Inst[39:32] == 0x0 |
| 9771 | OPC_Scope, 8, // 20394: try { |
| 9772 | OPC_CheckField, 48, 4, 0, // 20396: check Inst[51:48] == 0x0 |
| 9773 | OPC_Decode, 195, 8, 127, // 20400: decode to PVADDUUPrv using decoder 127 |
| 9774 | // 20400: } else try { |
| 9775 | OPC_Decode, 201, 8, 128, 1, // 20404: decode to PVADDUUPrvm using decoder 128 |
| 9776 | // 20404: } |
| 9777 | // 20404: } |
| 9778 | // 20404: } // switch Inst[47] |
| 9779 | // 20404: } |
| 9780 | 4, 23, // 20409: case 0x4: { |
| 9781 | OPC_CheckField, 0, 8, 0, // 20411: check Inst[7:0] == 0x0 |
| 9782 | OPC_CheckField, 32, 16, 0, // 20415: check Inst[47:32] == 0x0 |
| 9783 | OPC_Scope, 8, // 20419: try { |
| 9784 | OPC_CheckField, 48, 4, 0, // 20421: check Inst[51:48] == 0x0 |
| 9785 | OPC_Decode, 243, 8, 121, // 20425: decode to PVADDUvv using decoder 121 |
| 9786 | // 20425: } else try { |
| 9787 | OPC_Decode, 249, 8, 129, 1, // 20429: decode to PVADDUvvm using decoder 129 |
| 9788 | // 20429: } |
| 9789 | // 20429: } |
| 9790 | 6, 0, // 20434: case 0x6: { |
| 9791 | OPC_SwitchField, 47, 1, // 20436: switch Inst[47] { |
| 9792 | 0, 27, // 20439: case 0x0: { |
| 9793 | OPC_CheckField, 0, 8, 0, // 20441: check Inst[7:0] == 0x0 |
| 9794 | OPC_CheckField, 16, 8, 0, // 20445: check Inst[23:16] == 0x0 |
| 9795 | OPC_CheckField, 32, 8, 0, // 20449: check Inst[39:32] == 0x0 |
| 9796 | OPC_Scope, 8, // 20453: try { |
| 9797 | OPC_CheckField, 48, 4, 0, // 20455: check Inst[51:48] == 0x0 |
| 9798 | OPC_Decode, 219, 8, 123, // 20459: decode to PVADDUiv using decoder 123 |
| 9799 | // 20459: } else try { |
| 9800 | OPC_Decode, 225, 8, 130, 1, // 20463: decode to PVADDUivm using decoder 130 |
| 9801 | // 20463: } |
| 9802 | // 20463: } |
| 9803 | 1, 0, // 20468: case 0x1: { |
| 9804 | OPC_CheckField, 0, 8, 0, // 20470: check Inst[7:0] == 0x0 |
| 9805 | OPC_CheckField, 16, 8, 0, // 20474: check Inst[23:16] == 0x0 |
| 9806 | OPC_CheckField, 32, 8, 0, // 20478: check Inst[39:32] == 0x0 |
| 9807 | OPC_Scope, 8, // 20482: try { |
| 9808 | OPC_CheckField, 48, 4, 0, // 20484: check Inst[51:48] == 0x0 |
| 9809 | OPC_Decode, 231, 8, 127, // 20488: decode to PVADDUrv using decoder 127 |
| 9810 | // 20488: } else try { |
| 9811 | OPC_Decode, 237, 8, 131, 1, // 20492: decode to PVADDUrvm using decoder 131 |
| 9812 | // 20492: } |
| 9813 | // 20492: } |
| 9814 | // 20492: } // switch Inst[47] |
| 9815 | // 20492: } |
| 9816 | // 20492: } // switch Inst[54:52] |
| 9817 | // 20492: } |
| 9818 | 146, 3, 174, 1, // 20497: case 0x192: { |
| 9819 | OPC_SwitchField, 52, 3, // 20501: switch Inst[54:52] { |
| 9820 | 0, 22, // 20504: case 0x0: { |
| 9821 | OPC_CheckField, 0, 8, 0, // 20506: check Inst[7:0] == 0x0 |
| 9822 | OPC_CheckField, 32, 16, 0, // 20510: check Inst[47:32] == 0x0 |
| 9823 | OPC_Scope, 8, // 20514: try { |
| 9824 | OPC_CheckField, 48, 4, 0, // 20516: check Inst[51:48] == 0x0 |
| 9825 | OPC_Decode, 252, 66, 121, // 20520: decode to VMULULvv using decoder 121 |
| 9826 | // 20520: } else try { |
| 9827 | OPC_Decode, 130, 67, 122, // 20524: decode to VMULULvvm using decoder 122 |
| 9828 | // 20524: } |
| 9829 | // 20524: } |
| 9830 | 2, 60, // 20528: case 0x2: { |
| 9831 | OPC_SwitchField, 47, 1, // 20530: switch Inst[47] { |
| 9832 | 0, 26, // 20533: case 0x0: { |
| 9833 | OPC_CheckField, 0, 8, 0, // 20535: check Inst[7:0] == 0x0 |
| 9834 | OPC_CheckField, 16, 8, 0, // 20539: check Inst[23:16] == 0x0 |
| 9835 | OPC_CheckField, 32, 8, 0, // 20543: check Inst[39:32] == 0x0 |
| 9836 | OPC_Scope, 8, // 20547: try { |
| 9837 | OPC_CheckField, 48, 4, 0, // 20549: check Inst[51:48] == 0x0 |
| 9838 | OPC_Decode, 228, 66, 123, // 20553: decode to VMULULiv using decoder 123 |
| 9839 | // 20553: } else try { |
| 9840 | OPC_Decode, 234, 66, 124, // 20557: decode to VMULULivm using decoder 124 |
| 9841 | // 20557: } |
| 9842 | // 20557: } |
| 9843 | 1, 0, // 20561: case 0x1: { |
| 9844 | OPC_CheckField, 0, 8, 0, // 20563: check Inst[7:0] == 0x0 |
| 9845 | OPC_CheckField, 16, 8, 0, // 20567: check Inst[23:16] == 0x0 |
| 9846 | OPC_CheckField, 32, 8, 0, // 20571: check Inst[39:32] == 0x0 |
| 9847 | OPC_Scope, 8, // 20575: try { |
| 9848 | OPC_CheckField, 48, 4, 0, // 20577: check Inst[51:48] == 0x0 |
| 9849 | OPC_Decode, 240, 66, 127, // 20581: decode to VMULULrv using decoder 127 |
| 9850 | // 20581: } else try { |
| 9851 | OPC_Decode, 246, 66, 128, 1, // 20585: decode to VMULULrvm using decoder 128 |
| 9852 | // 20585: } |
| 9853 | // 20585: } |
| 9854 | // 20585: } // switch Inst[47] |
| 9855 | // 20585: } |
| 9856 | 4, 22, // 20590: case 0x4: { |
| 9857 | OPC_CheckField, 0, 8, 0, // 20592: check Inst[7:0] == 0x0 |
| 9858 | OPC_CheckField, 32, 16, 0, // 20596: check Inst[47:32] == 0x0 |
| 9859 | OPC_Scope, 8, // 20600: try { |
| 9860 | OPC_CheckField, 48, 4, 0, // 20602: check Inst[51:48] == 0x0 |
| 9861 | OPC_Decode, 160, 67, 121, // 20606: decode to VMULUWvv using decoder 121 |
| 9862 | // 20606: } else try { |
| 9863 | OPC_Decode, 166, 67, 122, // 20610: decode to VMULUWvvm using decoder 122 |
| 9864 | // 20610: } |
| 9865 | // 20610: } |
| 9866 | 6, 0, // 20614: case 0x6: { |
| 9867 | OPC_SwitchField, 47, 1, // 20616: switch Inst[47] { |
| 9868 | 0, 26, // 20619: case 0x0: { |
| 9869 | OPC_CheckField, 0, 8, 0, // 20621: check Inst[7:0] == 0x0 |
| 9870 | OPC_CheckField, 16, 8, 0, // 20625: check Inst[23:16] == 0x0 |
| 9871 | OPC_CheckField, 32, 8, 0, // 20629: check Inst[39:32] == 0x0 |
| 9872 | OPC_Scope, 8, // 20633: try { |
| 9873 | OPC_CheckField, 48, 4, 0, // 20635: check Inst[51:48] == 0x0 |
| 9874 | OPC_Decode, 136, 67, 123, // 20639: decode to VMULUWiv using decoder 123 |
| 9875 | // 20639: } else try { |
| 9876 | OPC_Decode, 142, 67, 124, // 20643: decode to VMULUWivm using decoder 124 |
| 9877 | // 20643: } |
| 9878 | // 20643: } |
| 9879 | 1, 0, // 20647: case 0x1: { |
| 9880 | OPC_CheckField, 0, 8, 0, // 20649: check Inst[7:0] == 0x0 |
| 9881 | OPC_CheckField, 16, 8, 0, // 20653: check Inst[23:16] == 0x0 |
| 9882 | OPC_CheckField, 32, 8, 0, // 20657: check Inst[39:32] == 0x0 |
| 9883 | OPC_Scope, 8, // 20661: try { |
| 9884 | OPC_CheckField, 48, 4, 0, // 20663: check Inst[51:48] == 0x0 |
| 9885 | OPC_Decode, 148, 67, 125, // 20667: decode to VMULUWrv using decoder 125 |
| 9886 | // 20667: } else try { |
| 9887 | OPC_Decode, 154, 67, 126, // 20671: decode to VMULUWrvm using decoder 126 |
| 9888 | // 20671: } |
| 9889 | // 20671: } |
| 9890 | // 20671: } // switch Inst[47] |
| 9891 | // 20671: } |
| 9892 | // 20671: } // switch Inst[54:52] |
| 9893 | // 20671: } |
| 9894 | 148, 3, 173, 1, // 20675: case 0x194: { |
| 9895 | OPC_SwitchField, 52, 3, // 20679: switch Inst[54:52] { |
| 9896 | 0, 22, // 20682: case 0x0: { |
| 9897 | OPC_CheckField, 0, 8, 0, // 20684: check Inst[7:0] == 0x0 |
| 9898 | OPC_CheckField, 32, 16, 0, // 20688: check Inst[47:32] == 0x0 |
| 9899 | OPC_Scope, 8, // 20692: try { |
| 9900 | OPC_CheckField, 48, 4, 0, // 20694: check Inst[51:48] == 0x0 |
| 9901 | OPC_Decode, 156, 36, 121, // 20698: decode to VADDSWSXvv using decoder 121 |
| 9902 | // 20698: } else try { |
| 9903 | OPC_Decode, 162, 36, 122, // 20702: decode to VADDSWSXvvm using decoder 122 |
| 9904 | // 20702: } |
| 9905 | // 20702: } |
| 9906 | 2, 59, // 20706: case 0x2: { |
| 9907 | OPC_SwitchField, 47, 1, // 20708: switch Inst[47] { |
| 9908 | 0, 26, // 20711: case 0x0: { |
| 9909 | OPC_CheckField, 0, 8, 0, // 20713: check Inst[7:0] == 0x0 |
| 9910 | OPC_CheckField, 16, 8, 0, // 20717: check Inst[23:16] == 0x0 |
| 9911 | OPC_CheckField, 32, 8, 0, // 20721: check Inst[39:32] == 0x0 |
| 9912 | OPC_Scope, 8, // 20725: try { |
| 9913 | OPC_CheckField, 48, 4, 0, // 20727: check Inst[51:48] == 0x0 |
| 9914 | OPC_Decode, 132, 36, 123, // 20731: decode to VADDSWSXiv using decoder 123 |
| 9915 | // 20731: } else try { |
| 9916 | OPC_Decode, 138, 36, 124, // 20735: decode to VADDSWSXivm using decoder 124 |
| 9917 | // 20735: } |
| 9918 | // 20735: } |
| 9919 | 1, 0, // 20739: case 0x1: { |
| 9920 | OPC_CheckField, 0, 8, 0, // 20741: check Inst[7:0] == 0x0 |
| 9921 | OPC_CheckField, 16, 8, 0, // 20745: check Inst[23:16] == 0x0 |
| 9922 | OPC_CheckField, 32, 8, 0, // 20749: check Inst[39:32] == 0x0 |
| 9923 | OPC_Scope, 8, // 20753: try { |
| 9924 | OPC_CheckField, 48, 4, 0, // 20755: check Inst[51:48] == 0x0 |
| 9925 | OPC_Decode, 144, 36, 125, // 20759: decode to VADDSWSXrv using decoder 125 |
| 9926 | // 20759: } else try { |
| 9927 | OPC_Decode, 150, 36, 126, // 20763: decode to VADDSWSXrvm using decoder 126 |
| 9928 | // 20763: } |
| 9929 | // 20763: } |
| 9930 | // 20763: } // switch Inst[47] |
| 9931 | // 20763: } |
| 9932 | 4, 22, // 20767: case 0x4: { |
| 9933 | OPC_CheckField, 0, 8, 0, // 20769: check Inst[7:0] == 0x0 |
| 9934 | OPC_CheckField, 32, 16, 0, // 20773: check Inst[47:32] == 0x0 |
| 9935 | OPC_Scope, 8, // 20777: try { |
| 9936 | OPC_CheckField, 48, 4, 0, // 20779: check Inst[51:48] == 0x0 |
| 9937 | OPC_Decode, 191, 7, 121, // 20783: decode to PVADDSLOvv using decoder 121 |
| 9938 | // 20783: } else try { |
| 9939 | OPC_Decode, 197, 7, 122, // 20787: decode to PVADDSLOvvm using decoder 122 |
| 9940 | // 20787: } |
| 9941 | // 20787: } |
| 9942 | 6, 0, // 20791: case 0x6: { |
| 9943 | OPC_SwitchField, 47, 1, // 20793: switch Inst[47] { |
| 9944 | 0, 26, // 20796: case 0x0: { |
| 9945 | OPC_CheckField, 0, 8, 0, // 20798: check Inst[7:0] == 0x0 |
| 9946 | OPC_CheckField, 16, 8, 0, // 20802: check Inst[23:16] == 0x0 |
| 9947 | OPC_CheckField, 32, 8, 0, // 20806: check Inst[39:32] == 0x0 |
| 9948 | OPC_Scope, 8, // 20810: try { |
| 9949 | OPC_CheckField, 48, 4, 0, // 20812: check Inst[51:48] == 0x0 |
| 9950 | OPC_Decode, 167, 7, 123, // 20816: decode to PVADDSLOiv using decoder 123 |
| 9951 | // 20816: } else try { |
| 9952 | OPC_Decode, 173, 7, 124, // 20820: decode to PVADDSLOivm using decoder 124 |
| 9953 | // 20820: } |
| 9954 | // 20820: } |
| 9955 | 1, 0, // 20824: case 0x1: { |
| 9956 | OPC_CheckField, 0, 8, 0, // 20826: check Inst[7:0] == 0x0 |
| 9957 | OPC_CheckField, 16, 8, 0, // 20830: check Inst[23:16] == 0x0 |
| 9958 | OPC_CheckField, 32, 8, 0, // 20834: check Inst[39:32] == 0x0 |
| 9959 | OPC_Scope, 8, // 20838: try { |
| 9960 | OPC_CheckField, 48, 4, 0, // 20840: check Inst[51:48] == 0x0 |
| 9961 | OPC_Decode, 179, 7, 125, // 20844: decode to PVADDSLOrv using decoder 125 |
| 9962 | // 20844: } else try { |
| 9963 | OPC_Decode, 185, 7, 126, // 20848: decode to PVADDSLOrvm using decoder 126 |
| 9964 | // 20848: } |
| 9965 | // 20848: } |
| 9966 | // 20848: } // switch Inst[47] |
| 9967 | // 20848: } |
| 9968 | // 20848: } // switch Inst[54:52] |
| 9969 | // 20848: } |
| 9970 | 149, 3, 177, 1, // 20852: case 0x195: { |
| 9971 | OPC_SwitchField, 52, 3, // 20856: switch Inst[54:52] { |
| 9972 | 0, 22, // 20859: case 0x0: { |
| 9973 | OPC_CheckField, 0, 8, 0, // 20861: check Inst[7:0] == 0x0 |
| 9974 | OPC_CheckField, 32, 16, 0, // 20865: check Inst[47:32] == 0x0 |
| 9975 | OPC_Scope, 8, // 20869: try { |
| 9976 | OPC_CheckField, 48, 4, 0, // 20871: check Inst[51:48] == 0x0 |
| 9977 | OPC_Decode, 227, 7, 121, // 20875: decode to PVADDSUPvv using decoder 121 |
| 9978 | // 20875: } else try { |
| 9979 | OPC_Decode, 233, 7, 122, // 20879: decode to PVADDSUPvvm using decoder 122 |
| 9980 | // 20879: } |
| 9981 | // 20879: } |
| 9982 | 2, 60, // 20883: case 0x2: { |
| 9983 | OPC_SwitchField, 47, 1, // 20885: switch Inst[47] { |
| 9984 | 0, 26, // 20888: case 0x0: { |
| 9985 | OPC_CheckField, 0, 8, 0, // 20890: check Inst[7:0] == 0x0 |
| 9986 | OPC_CheckField, 16, 8, 0, // 20894: check Inst[23:16] == 0x0 |
| 9987 | OPC_CheckField, 32, 8, 0, // 20898: check Inst[39:32] == 0x0 |
| 9988 | OPC_Scope, 8, // 20902: try { |
| 9989 | OPC_CheckField, 48, 4, 0, // 20904: check Inst[51:48] == 0x0 |
| 9990 | OPC_Decode, 203, 7, 123, // 20908: decode to PVADDSUPiv using decoder 123 |
| 9991 | // 20908: } else try { |
| 9992 | OPC_Decode, 209, 7, 124, // 20912: decode to PVADDSUPivm using decoder 124 |
| 9993 | // 20912: } |
| 9994 | // 20912: } |
| 9995 | 1, 0, // 20916: case 0x1: { |
| 9996 | OPC_CheckField, 0, 8, 0, // 20918: check Inst[7:0] == 0x0 |
| 9997 | OPC_CheckField, 16, 8, 0, // 20922: check Inst[23:16] == 0x0 |
| 9998 | OPC_CheckField, 32, 8, 0, // 20926: check Inst[39:32] == 0x0 |
| 9999 | OPC_Scope, 8, // 20930: try { |
| 10000 | OPC_CheckField, 48, 4, 0, // 20932: check Inst[51:48] == 0x0 |
| 10001 | OPC_Decode, 215, 7, 127, // 20936: decode to PVADDSUPrv using decoder 127 |
| 10002 | // 20936: } else try { |
| 10003 | OPC_Decode, 221, 7, 128, 1, // 20940: decode to PVADDSUPrvm using decoder 128 |
| 10004 | // 20940: } |
| 10005 | // 20940: } |
| 10006 | // 20940: } // switch Inst[47] |
| 10007 | // 20940: } |
| 10008 | 4, 23, // 20945: case 0x4: { |
| 10009 | OPC_CheckField, 0, 8, 0, // 20947: check Inst[7:0] == 0x0 |
| 10010 | OPC_CheckField, 32, 16, 0, // 20951: check Inst[47:32] == 0x0 |
| 10011 | OPC_Scope, 8, // 20955: try { |
| 10012 | OPC_CheckField, 48, 4, 0, // 20957: check Inst[51:48] == 0x0 |
| 10013 | OPC_Decode, 135, 8, 121, // 20961: decode to PVADDSvv using decoder 121 |
| 10014 | // 20961: } else try { |
| 10015 | OPC_Decode, 141, 8, 129, 1, // 20965: decode to PVADDSvvm using decoder 129 |
| 10016 | // 20965: } |
| 10017 | // 20965: } |
| 10018 | 6, 0, // 20970: case 0x6: { |
| 10019 | OPC_SwitchField, 47, 1, // 20972: switch Inst[47] { |
| 10020 | 0, 27, // 20975: case 0x0: { |
| 10021 | OPC_CheckField, 0, 8, 0, // 20977: check Inst[7:0] == 0x0 |
| 10022 | OPC_CheckField, 16, 8, 0, // 20981: check Inst[23:16] == 0x0 |
| 10023 | OPC_CheckField, 32, 8, 0, // 20985: check Inst[39:32] == 0x0 |
| 10024 | OPC_Scope, 8, // 20989: try { |
| 10025 | OPC_CheckField, 48, 4, 0, // 20991: check Inst[51:48] == 0x0 |
| 10026 | OPC_Decode, 239, 7, 123, // 20995: decode to PVADDSiv using decoder 123 |
| 10027 | // 20995: } else try { |
| 10028 | OPC_Decode, 245, 7, 130, 1, // 20999: decode to PVADDSivm using decoder 130 |
| 10029 | // 20999: } |
| 10030 | // 20999: } |
| 10031 | 1, 0, // 21004: case 0x1: { |
| 10032 | OPC_CheckField, 0, 8, 0, // 21006: check Inst[7:0] == 0x0 |
| 10033 | OPC_CheckField, 16, 8, 0, // 21010: check Inst[23:16] == 0x0 |
| 10034 | OPC_CheckField, 32, 8, 0, // 21014: check Inst[39:32] == 0x0 |
| 10035 | OPC_Scope, 8, // 21018: try { |
| 10036 | OPC_CheckField, 48, 4, 0, // 21020: check Inst[51:48] == 0x0 |
| 10037 | OPC_Decode, 251, 7, 127, // 21024: decode to PVADDSrv using decoder 127 |
| 10038 | // 21024: } else try { |
| 10039 | OPC_Decode, 129, 8, 131, 1, // 21028: decode to PVADDSrvm using decoder 131 |
| 10040 | // 21028: } |
| 10041 | // 21028: } |
| 10042 | // 21028: } // switch Inst[47] |
| 10043 | // 21028: } |
| 10044 | // 21028: } // switch Inst[54:52] |
| 10045 | // 21028: } |
| 10046 | 150, 3, 173, 1, // 21033: case 0x196: { |
| 10047 | OPC_SwitchField, 52, 3, // 21037: switch Inst[54:52] { |
| 10048 | 0, 22, // 21040: case 0x0: { |
| 10049 | OPC_CheckField, 0, 8, 0, // 21042: check Inst[7:0] == 0x0 |
| 10050 | OPC_CheckField, 32, 16, 0, // 21046: check Inst[47:32] == 0x0 |
| 10051 | OPC_Scope, 8, // 21050: try { |
| 10052 | OPC_CheckField, 48, 4, 0, // 21052: check Inst[51:48] == 0x0 |
| 10053 | OPC_Decode, 180, 66, 121, // 21056: decode to VMULSWSXvv using decoder 121 |
| 10054 | // 21056: } else try { |
| 10055 | OPC_Decode, 186, 66, 122, // 21060: decode to VMULSWSXvvm using decoder 122 |
| 10056 | // 21060: } |
| 10057 | // 21060: } |
| 10058 | 2, 59, // 21064: case 0x2: { |
| 10059 | OPC_SwitchField, 47, 1, // 21066: switch Inst[47] { |
| 10060 | 0, 26, // 21069: case 0x0: { |
| 10061 | OPC_CheckField, 0, 8, 0, // 21071: check Inst[7:0] == 0x0 |
| 10062 | OPC_CheckField, 16, 8, 0, // 21075: check Inst[23:16] == 0x0 |
| 10063 | OPC_CheckField, 32, 8, 0, // 21079: check Inst[39:32] == 0x0 |
| 10064 | OPC_Scope, 8, // 21083: try { |
| 10065 | OPC_CheckField, 48, 4, 0, // 21085: check Inst[51:48] == 0x0 |
| 10066 | OPC_Decode, 156, 66, 123, // 21089: decode to VMULSWSXiv using decoder 123 |
| 10067 | // 21089: } else try { |
| 10068 | OPC_Decode, 162, 66, 124, // 21093: decode to VMULSWSXivm using decoder 124 |
| 10069 | // 21093: } |
| 10070 | // 21093: } |
| 10071 | 1, 0, // 21097: case 0x1: { |
| 10072 | OPC_CheckField, 0, 8, 0, // 21099: check Inst[7:0] == 0x0 |
| 10073 | OPC_CheckField, 16, 8, 0, // 21103: check Inst[23:16] == 0x0 |
| 10074 | OPC_CheckField, 32, 8, 0, // 21107: check Inst[39:32] == 0x0 |
| 10075 | OPC_Scope, 8, // 21111: try { |
| 10076 | OPC_CheckField, 48, 4, 0, // 21113: check Inst[51:48] == 0x0 |
| 10077 | OPC_Decode, 168, 66, 125, // 21117: decode to VMULSWSXrv using decoder 125 |
| 10078 | // 21117: } else try { |
| 10079 | OPC_Decode, 174, 66, 126, // 21121: decode to VMULSWSXrvm using decoder 126 |
| 10080 | // 21121: } |
| 10081 | // 21121: } |
| 10082 | // 21121: } // switch Inst[47] |
| 10083 | // 21121: } |
| 10084 | 4, 22, // 21125: case 0x4: { |
| 10085 | OPC_CheckField, 0, 8, 0, // 21127: check Inst[7:0] == 0x0 |
| 10086 | OPC_CheckField, 32, 16, 0, // 21131: check Inst[47:32] == 0x0 |
| 10087 | OPC_Scope, 8, // 21135: try { |
| 10088 | OPC_CheckField, 48, 4, 0, // 21137: check Inst[51:48] == 0x0 |
| 10089 | OPC_Decode, 216, 66, 121, // 21141: decode to VMULSWZXvv using decoder 121 |
| 10090 | // 21141: } else try { |
| 10091 | OPC_Decode, 222, 66, 122, // 21145: decode to VMULSWZXvvm using decoder 122 |
| 10092 | // 21145: } |
| 10093 | // 21145: } |
| 10094 | 6, 0, // 21149: case 0x6: { |
| 10095 | OPC_SwitchField, 47, 1, // 21151: switch Inst[47] { |
| 10096 | 0, 26, // 21154: case 0x0: { |
| 10097 | OPC_CheckField, 0, 8, 0, // 21156: check Inst[7:0] == 0x0 |
| 10098 | OPC_CheckField, 16, 8, 0, // 21160: check Inst[23:16] == 0x0 |
| 10099 | OPC_CheckField, 32, 8, 0, // 21164: check Inst[39:32] == 0x0 |
| 10100 | OPC_Scope, 8, // 21168: try { |
| 10101 | OPC_CheckField, 48, 4, 0, // 21170: check Inst[51:48] == 0x0 |
| 10102 | OPC_Decode, 192, 66, 123, // 21174: decode to VMULSWZXiv using decoder 123 |
| 10103 | // 21174: } else try { |
| 10104 | OPC_Decode, 198, 66, 124, // 21178: decode to VMULSWZXivm using decoder 124 |
| 10105 | // 21178: } |
| 10106 | // 21178: } |
| 10107 | 1, 0, // 21182: case 0x1: { |
| 10108 | OPC_CheckField, 0, 8, 0, // 21184: check Inst[7:0] == 0x0 |
| 10109 | OPC_CheckField, 16, 8, 0, // 21188: check Inst[23:16] == 0x0 |
| 10110 | OPC_CheckField, 32, 8, 0, // 21192: check Inst[39:32] == 0x0 |
| 10111 | OPC_Scope, 8, // 21196: try { |
| 10112 | OPC_CheckField, 48, 4, 0, // 21198: check Inst[51:48] == 0x0 |
| 10113 | OPC_Decode, 204, 66, 125, // 21202: decode to VMULSWZXrv using decoder 125 |
| 10114 | // 21202: } else try { |
| 10115 | OPC_Decode, 210, 66, 126, // 21206: decode to VMULSWZXrvm using decoder 126 |
| 10116 | // 21206: } |
| 10117 | // 21206: } |
| 10118 | // 21206: } // switch Inst[47] |
| 10119 | // 21206: } |
| 10120 | // 21206: } // switch Inst[54:52] |
| 10121 | // 21206: } |
| 10122 | 152, 3, 175, 1, // 21210: case 0x198: { |
| 10123 | OPC_SwitchField, 52, 3, // 21214: switch Inst[54:52] { |
| 10124 | 0, 22, // 21217: case 0x0: { |
| 10125 | OPC_CheckField, 0, 8, 0, // 21219: check Inst[7:0] == 0x0 |
| 10126 | OPC_CheckField, 32, 16, 0, // 21223: check Inst[47:32] == 0x0 |
| 10127 | OPC_Scope, 8, // 21227: try { |
| 10128 | OPC_CheckField, 48, 4, 0, // 21229: check Inst[51:48] == 0x0 |
| 10129 | OPC_Decode, 184, 43, 121, // 21233: decode to VFADDDvv using decoder 121 |
| 10130 | // 21233: } else try { |
| 10131 | OPC_Decode, 190, 43, 122, // 21237: decode to VFADDDvvm using decoder 122 |
| 10132 | // 21237: } |
| 10133 | // 21237: } |
| 10134 | 2, 60, // 21241: case 0x2: { |
| 10135 | OPC_SwitchField, 47, 1, // 21243: switch Inst[47] { |
| 10136 | 0, 26, // 21246: case 0x0: { |
| 10137 | OPC_CheckField, 0, 8, 0, // 21248: check Inst[7:0] == 0x0 |
| 10138 | OPC_CheckField, 16, 8, 0, // 21252: check Inst[23:16] == 0x0 |
| 10139 | OPC_CheckField, 32, 8, 0, // 21256: check Inst[39:32] == 0x0 |
| 10140 | OPC_Scope, 8, // 21260: try { |
| 10141 | OPC_CheckField, 48, 4, 0, // 21262: check Inst[51:48] == 0x0 |
| 10142 | OPC_Decode, 160, 43, 123, // 21266: decode to VFADDDiv using decoder 123 |
| 10143 | // 21266: } else try { |
| 10144 | OPC_Decode, 166, 43, 124, // 21270: decode to VFADDDivm using decoder 124 |
| 10145 | // 21270: } |
| 10146 | // 21270: } |
| 10147 | 1, 0, // 21274: case 0x1: { |
| 10148 | OPC_CheckField, 0, 8, 0, // 21276: check Inst[7:0] == 0x0 |
| 10149 | OPC_CheckField, 16, 8, 0, // 21280: check Inst[23:16] == 0x0 |
| 10150 | OPC_CheckField, 32, 8, 0, // 21284: check Inst[39:32] == 0x0 |
| 10151 | OPC_Scope, 8, // 21288: try { |
| 10152 | OPC_CheckField, 48, 4, 0, // 21290: check Inst[51:48] == 0x0 |
| 10153 | OPC_Decode, 172, 43, 127, // 21294: decode to VFADDDrv using decoder 127 |
| 10154 | // 21294: } else try { |
| 10155 | OPC_Decode, 178, 43, 128, 1, // 21298: decode to VFADDDrvm using decoder 128 |
| 10156 | // 21298: } |
| 10157 | // 21298: } |
| 10158 | // 21298: } // switch Inst[47] |
| 10159 | // 21298: } |
| 10160 | 4, 22, // 21303: case 0x4: { |
| 10161 | OPC_CheckField, 0, 8, 0, // 21305: check Inst[7:0] == 0x0 |
| 10162 | OPC_CheckField, 32, 16, 0, // 21309: check Inst[47:32] == 0x0 |
| 10163 | OPC_Scope, 8, // 21313: try { |
| 10164 | OPC_CheckField, 48, 4, 0, // 21315: check Inst[51:48] == 0x0 |
| 10165 | OPC_Decode, 203, 13, 121, // 21319: decode to PVFADDLOvv using decoder 121 |
| 10166 | // 21319: } else try { |
| 10167 | OPC_Decode, 209, 13, 122, // 21323: decode to PVFADDLOvvm using decoder 122 |
| 10168 | // 21323: } |
| 10169 | // 21323: } |
| 10170 | 6, 0, // 21327: case 0x6: { |
| 10171 | OPC_SwitchField, 47, 1, // 21329: switch Inst[47] { |
| 10172 | 0, 26, // 21332: case 0x0: { |
| 10173 | OPC_CheckField, 0, 8, 0, // 21334: check Inst[7:0] == 0x0 |
| 10174 | OPC_CheckField, 16, 8, 0, // 21338: check Inst[23:16] == 0x0 |
| 10175 | OPC_CheckField, 32, 8, 0, // 21342: check Inst[39:32] == 0x0 |
| 10176 | OPC_Scope, 8, // 21346: try { |
| 10177 | OPC_CheckField, 48, 4, 0, // 21348: check Inst[51:48] == 0x0 |
| 10178 | OPC_Decode, 179, 13, 123, // 21352: decode to PVFADDLOiv using decoder 123 |
| 10179 | // 21352: } else try { |
| 10180 | OPC_Decode, 185, 13, 124, // 21356: decode to PVFADDLOivm using decoder 124 |
| 10181 | // 21356: } |
| 10182 | // 21356: } |
| 10183 | 1, 0, // 21360: case 0x1: { |
| 10184 | OPC_CheckField, 0, 8, 0, // 21362: check Inst[7:0] == 0x0 |
| 10185 | OPC_CheckField, 16, 8, 0, // 21366: check Inst[23:16] == 0x0 |
| 10186 | OPC_CheckField, 32, 8, 0, // 21370: check Inst[39:32] == 0x0 |
| 10187 | OPC_Scope, 8, // 21374: try { |
| 10188 | OPC_CheckField, 48, 4, 0, // 21376: check Inst[51:48] == 0x0 |
| 10189 | OPC_Decode, 191, 13, 127, // 21380: decode to PVFADDLOrv using decoder 127 |
| 10190 | // 21380: } else try { |
| 10191 | OPC_Decode, 197, 13, 128, 1, // 21384: decode to PVFADDLOrvm using decoder 128 |
| 10192 | // 21384: } |
| 10193 | // 21384: } |
| 10194 | // 21384: } // switch Inst[47] |
| 10195 | // 21384: } |
| 10196 | // 21384: } // switch Inst[54:52] |
| 10197 | // 21384: } |
| 10198 | 153, 3, 178, 1, // 21389: case 0x199: { |
| 10199 | OPC_SwitchField, 52, 3, // 21393: switch Inst[54:52] { |
| 10200 | 0, 22, // 21396: case 0x0: { |
| 10201 | OPC_CheckField, 0, 8, 0, // 21398: check Inst[7:0] == 0x0 |
| 10202 | OPC_CheckField, 32, 16, 0, // 21402: check Inst[47:32] == 0x0 |
| 10203 | OPC_Scope, 8, // 21406: try { |
| 10204 | OPC_CheckField, 48, 4, 0, // 21408: check Inst[51:48] == 0x0 |
| 10205 | OPC_Decode, 239, 13, 121, // 21412: decode to PVFADDUPvv using decoder 121 |
| 10206 | // 21412: } else try { |
| 10207 | OPC_Decode, 245, 13, 122, // 21416: decode to PVFADDUPvvm using decoder 122 |
| 10208 | // 21416: } |
| 10209 | // 21416: } |
| 10210 | 2, 61, // 21420: case 0x2: { |
| 10211 | OPC_SwitchField, 47, 1, // 21422: switch Inst[47] { |
| 10212 | 0, 26, // 21425: case 0x0: { |
| 10213 | OPC_CheckField, 0, 8, 0, // 21427: check Inst[7:0] == 0x0 |
| 10214 | OPC_CheckField, 16, 8, 0, // 21431: check Inst[23:16] == 0x0 |
| 10215 | OPC_CheckField, 32, 8, 0, // 21435: check Inst[39:32] == 0x0 |
| 10216 | OPC_Scope, 8, // 21439: try { |
| 10217 | OPC_CheckField, 48, 4, 0, // 21441: check Inst[51:48] == 0x0 |
| 10218 | OPC_Decode, 215, 13, 123, // 21445: decode to PVFADDUPiv using decoder 123 |
| 10219 | // 21445: } else try { |
| 10220 | OPC_Decode, 221, 13, 124, // 21449: decode to PVFADDUPivm using decoder 124 |
| 10221 | // 21449: } |
| 10222 | // 21449: } |
| 10223 | 1, 0, // 21453: case 0x1: { |
| 10224 | OPC_CheckField, 0, 8, 0, // 21455: check Inst[7:0] == 0x0 |
| 10225 | OPC_CheckField, 16, 8, 0, // 21459: check Inst[23:16] == 0x0 |
| 10226 | OPC_CheckField, 32, 8, 0, // 21463: check Inst[39:32] == 0x0 |
| 10227 | OPC_Scope, 9, // 21467: try { |
| 10228 | OPC_CheckField, 48, 4, 0, // 21469: check Inst[51:48] == 0x0 |
| 10229 | OPC_Decode, 227, 13, 210, 1, // 21473: decode to PVFADDUPrv using decoder 210 |
| 10230 | // 21473: } else try { |
| 10231 | OPC_Decode, 233, 13, 211, 1, // 21478: decode to PVFADDUPrvm using decoder 211 |
| 10232 | // 21478: } |
| 10233 | // 21478: } |
| 10234 | // 21478: } // switch Inst[47] |
| 10235 | // 21478: } |
| 10236 | 4, 23, // 21483: case 0x4: { |
| 10237 | OPC_CheckField, 0, 8, 0, // 21485: check Inst[7:0] == 0x0 |
| 10238 | OPC_CheckField, 32, 16, 0, // 21489: check Inst[47:32] == 0x0 |
| 10239 | OPC_Scope, 8, // 21493: try { |
| 10240 | OPC_CheckField, 48, 4, 0, // 21495: check Inst[51:48] == 0x0 |
| 10241 | OPC_Decode, 147, 14, 121, // 21499: decode to PVFADDvv using decoder 121 |
| 10242 | // 21499: } else try { |
| 10243 | OPC_Decode, 153, 14, 129, 1, // 21503: decode to PVFADDvvm using decoder 129 |
| 10244 | // 21503: } |
| 10245 | // 21503: } |
| 10246 | 6, 0, // 21508: case 0x6: { |
| 10247 | OPC_SwitchField, 47, 1, // 21510: switch Inst[47] { |
| 10248 | 0, 27, // 21513: case 0x0: { |
| 10249 | OPC_CheckField, 0, 8, 0, // 21515: check Inst[7:0] == 0x0 |
| 10250 | OPC_CheckField, 16, 8, 0, // 21519: check Inst[23:16] == 0x0 |
| 10251 | OPC_CheckField, 32, 8, 0, // 21523: check Inst[39:32] == 0x0 |
| 10252 | OPC_Scope, 8, // 21527: try { |
| 10253 | OPC_CheckField, 48, 4, 0, // 21529: check Inst[51:48] == 0x0 |
| 10254 | OPC_Decode, 251, 13, 123, // 21533: decode to PVFADDiv using decoder 123 |
| 10255 | // 21533: } else try { |
| 10256 | OPC_Decode, 129, 14, 130, 1, // 21537: decode to PVFADDivm using decoder 130 |
| 10257 | // 21537: } |
| 10258 | // 21537: } |
| 10259 | 1, 0, // 21542: case 0x1: { |
| 10260 | OPC_CheckField, 0, 8, 0, // 21544: check Inst[7:0] == 0x0 |
| 10261 | OPC_CheckField, 16, 8, 0, // 21548: check Inst[23:16] == 0x0 |
| 10262 | OPC_CheckField, 32, 8, 0, // 21552: check Inst[39:32] == 0x0 |
| 10263 | OPC_Scope, 8, // 21556: try { |
| 10264 | OPC_CheckField, 48, 4, 0, // 21558: check Inst[51:48] == 0x0 |
| 10265 | OPC_Decode, 135, 14, 127, // 21562: decode to PVFADDrv using decoder 127 |
| 10266 | // 21562: } else try { |
| 10267 | OPC_Decode, 141, 14, 131, 1, // 21566: decode to PVFADDrvm using decoder 131 |
| 10268 | // 21566: } |
| 10269 | // 21566: } |
| 10270 | // 21566: } // switch Inst[47] |
| 10271 | // 21566: } |
| 10272 | // 21566: } // switch Inst[54:52] |
| 10273 | // 21566: } |
| 10274 | 154, 3, 175, 1, // 21571: case 0x19a: { |
| 10275 | OPC_SwitchField, 52, 3, // 21575: switch Inst[54:52] { |
| 10276 | 0, 22, // 21578: case 0x0: { |
| 10277 | OPC_CheckField, 0, 8, 0, // 21580: check Inst[7:0] == 0x0 |
| 10278 | OPC_CheckField, 32, 16, 0, // 21584: check Inst[47:32] == 0x0 |
| 10279 | OPC_Scope, 8, // 21588: try { |
| 10280 | OPC_CheckField, 48, 4, 0, // 21590: check Inst[51:48] == 0x0 |
| 10281 | OPC_Decode, 176, 50, 121, // 21594: decode to VFMULDvv using decoder 121 |
| 10282 | // 21594: } else try { |
| 10283 | OPC_Decode, 182, 50, 122, // 21598: decode to VFMULDvvm using decoder 122 |
| 10284 | // 21598: } |
| 10285 | // 21598: } |
| 10286 | 2, 60, // 21602: case 0x2: { |
| 10287 | OPC_SwitchField, 47, 1, // 21604: switch Inst[47] { |
| 10288 | 0, 26, // 21607: case 0x0: { |
| 10289 | OPC_CheckField, 0, 8, 0, // 21609: check Inst[7:0] == 0x0 |
| 10290 | OPC_CheckField, 16, 8, 0, // 21613: check Inst[23:16] == 0x0 |
| 10291 | OPC_CheckField, 32, 8, 0, // 21617: check Inst[39:32] == 0x0 |
| 10292 | OPC_Scope, 8, // 21621: try { |
| 10293 | OPC_CheckField, 48, 4, 0, // 21623: check Inst[51:48] == 0x0 |
| 10294 | OPC_Decode, 152, 50, 123, // 21627: decode to VFMULDiv using decoder 123 |
| 10295 | // 21627: } else try { |
| 10296 | OPC_Decode, 158, 50, 124, // 21631: decode to VFMULDivm using decoder 124 |
| 10297 | // 21631: } |
| 10298 | // 21631: } |
| 10299 | 1, 0, // 21635: case 0x1: { |
| 10300 | OPC_CheckField, 0, 8, 0, // 21637: check Inst[7:0] == 0x0 |
| 10301 | OPC_CheckField, 16, 8, 0, // 21641: check Inst[23:16] == 0x0 |
| 10302 | OPC_CheckField, 32, 8, 0, // 21645: check Inst[39:32] == 0x0 |
| 10303 | OPC_Scope, 8, // 21649: try { |
| 10304 | OPC_CheckField, 48, 4, 0, // 21651: check Inst[51:48] == 0x0 |
| 10305 | OPC_Decode, 164, 50, 127, // 21655: decode to VFMULDrv using decoder 127 |
| 10306 | // 21655: } else try { |
| 10307 | OPC_Decode, 170, 50, 128, 1, // 21659: decode to VFMULDrvm using decoder 128 |
| 10308 | // 21659: } |
| 10309 | // 21659: } |
| 10310 | // 21659: } // switch Inst[47] |
| 10311 | // 21659: } |
| 10312 | 4, 22, // 21664: case 0x4: { |
| 10313 | OPC_CheckField, 0, 8, 0, // 21666: check Inst[7:0] == 0x0 |
| 10314 | OPC_CheckField, 32, 16, 0, // 21670: check Inst[47:32] == 0x0 |
| 10315 | OPC_Scope, 8, // 21674: try { |
| 10316 | OPC_CheckField, 48, 4, 0, // 21676: check Inst[51:48] == 0x0 |
| 10317 | OPC_Decode, 171, 20, 121, // 21680: decode to PVFMULLOvv using decoder 121 |
| 10318 | // 21680: } else try { |
| 10319 | OPC_Decode, 177, 20, 122, // 21684: decode to PVFMULLOvvm using decoder 122 |
| 10320 | // 21684: } |
| 10321 | // 21684: } |
| 10322 | 6, 0, // 21688: case 0x6: { |
| 10323 | OPC_SwitchField, 47, 1, // 21690: switch Inst[47] { |
| 10324 | 0, 26, // 21693: case 0x0: { |
| 10325 | OPC_CheckField, 0, 8, 0, // 21695: check Inst[7:0] == 0x0 |
| 10326 | OPC_CheckField, 16, 8, 0, // 21699: check Inst[23:16] == 0x0 |
| 10327 | OPC_CheckField, 32, 8, 0, // 21703: check Inst[39:32] == 0x0 |
| 10328 | OPC_Scope, 8, // 21707: try { |
| 10329 | OPC_CheckField, 48, 4, 0, // 21709: check Inst[51:48] == 0x0 |
| 10330 | OPC_Decode, 147, 20, 123, // 21713: decode to PVFMULLOiv using decoder 123 |
| 10331 | // 21713: } else try { |
| 10332 | OPC_Decode, 153, 20, 124, // 21717: decode to PVFMULLOivm using decoder 124 |
| 10333 | // 21717: } |
| 10334 | // 21717: } |
| 10335 | 1, 0, // 21721: case 0x1: { |
| 10336 | OPC_CheckField, 0, 8, 0, // 21723: check Inst[7:0] == 0x0 |
| 10337 | OPC_CheckField, 16, 8, 0, // 21727: check Inst[23:16] == 0x0 |
| 10338 | OPC_CheckField, 32, 8, 0, // 21731: check Inst[39:32] == 0x0 |
| 10339 | OPC_Scope, 8, // 21735: try { |
| 10340 | OPC_CheckField, 48, 4, 0, // 21737: check Inst[51:48] == 0x0 |
| 10341 | OPC_Decode, 159, 20, 127, // 21741: decode to PVFMULLOrv using decoder 127 |
| 10342 | // 21741: } else try { |
| 10343 | OPC_Decode, 165, 20, 128, 1, // 21745: decode to PVFMULLOrvm using decoder 128 |
| 10344 | // 21745: } |
| 10345 | // 21745: } |
| 10346 | // 21745: } // switch Inst[47] |
| 10347 | // 21745: } |
| 10348 | // 21745: } // switch Inst[54:52] |
| 10349 | // 21745: } |
| 10350 | 155, 3, 178, 1, // 21750: case 0x19b: { |
| 10351 | OPC_SwitchField, 52, 3, // 21754: switch Inst[54:52] { |
| 10352 | 0, 22, // 21757: case 0x0: { |
| 10353 | OPC_CheckField, 0, 8, 0, // 21759: check Inst[7:0] == 0x0 |
| 10354 | OPC_CheckField, 32, 16, 0, // 21763: check Inst[47:32] == 0x0 |
| 10355 | OPC_Scope, 8, // 21767: try { |
| 10356 | OPC_CheckField, 48, 4, 0, // 21769: check Inst[51:48] == 0x0 |
| 10357 | OPC_Decode, 207, 20, 121, // 21773: decode to PVFMULUPvv using decoder 121 |
| 10358 | // 21773: } else try { |
| 10359 | OPC_Decode, 213, 20, 122, // 21777: decode to PVFMULUPvvm using decoder 122 |
| 10360 | // 21777: } |
| 10361 | // 21777: } |
| 10362 | 2, 61, // 21781: case 0x2: { |
| 10363 | OPC_SwitchField, 47, 1, // 21783: switch Inst[47] { |
| 10364 | 0, 26, // 21786: case 0x0: { |
| 10365 | OPC_CheckField, 0, 8, 0, // 21788: check Inst[7:0] == 0x0 |
| 10366 | OPC_CheckField, 16, 8, 0, // 21792: check Inst[23:16] == 0x0 |
| 10367 | OPC_CheckField, 32, 8, 0, // 21796: check Inst[39:32] == 0x0 |
| 10368 | OPC_Scope, 8, // 21800: try { |
| 10369 | OPC_CheckField, 48, 4, 0, // 21802: check Inst[51:48] == 0x0 |
| 10370 | OPC_Decode, 183, 20, 123, // 21806: decode to PVFMULUPiv using decoder 123 |
| 10371 | // 21806: } else try { |
| 10372 | OPC_Decode, 189, 20, 124, // 21810: decode to PVFMULUPivm using decoder 124 |
| 10373 | // 21810: } |
| 10374 | // 21810: } |
| 10375 | 1, 0, // 21814: case 0x1: { |
| 10376 | OPC_CheckField, 0, 8, 0, // 21816: check Inst[7:0] == 0x0 |
| 10377 | OPC_CheckField, 16, 8, 0, // 21820: check Inst[23:16] == 0x0 |
| 10378 | OPC_CheckField, 32, 8, 0, // 21824: check Inst[39:32] == 0x0 |
| 10379 | OPC_Scope, 9, // 21828: try { |
| 10380 | OPC_CheckField, 48, 4, 0, // 21830: check Inst[51:48] == 0x0 |
| 10381 | OPC_Decode, 195, 20, 210, 1, // 21834: decode to PVFMULUPrv using decoder 210 |
| 10382 | // 21834: } else try { |
| 10383 | OPC_Decode, 201, 20, 211, 1, // 21839: decode to PVFMULUPrvm using decoder 211 |
| 10384 | // 21839: } |
| 10385 | // 21839: } |
| 10386 | // 21839: } // switch Inst[47] |
| 10387 | // 21839: } |
| 10388 | 4, 23, // 21844: case 0x4: { |
| 10389 | OPC_CheckField, 0, 8, 0, // 21846: check Inst[7:0] == 0x0 |
| 10390 | OPC_CheckField, 32, 16, 0, // 21850: check Inst[47:32] == 0x0 |
| 10391 | OPC_Scope, 8, // 21854: try { |
| 10392 | OPC_CheckField, 48, 4, 0, // 21856: check Inst[51:48] == 0x0 |
| 10393 | OPC_Decode, 243, 20, 121, // 21860: decode to PVFMULvv using decoder 121 |
| 10394 | // 21860: } else try { |
| 10395 | OPC_Decode, 249, 20, 129, 1, // 21864: decode to PVFMULvvm using decoder 129 |
| 10396 | // 21864: } |
| 10397 | // 21864: } |
| 10398 | 6, 0, // 21869: case 0x6: { |
| 10399 | OPC_SwitchField, 47, 1, // 21871: switch Inst[47] { |
| 10400 | 0, 27, // 21874: case 0x0: { |
| 10401 | OPC_CheckField, 0, 8, 0, // 21876: check Inst[7:0] == 0x0 |
| 10402 | OPC_CheckField, 16, 8, 0, // 21880: check Inst[23:16] == 0x0 |
| 10403 | OPC_CheckField, 32, 8, 0, // 21884: check Inst[39:32] == 0x0 |
| 10404 | OPC_Scope, 8, // 21888: try { |
| 10405 | OPC_CheckField, 48, 4, 0, // 21890: check Inst[51:48] == 0x0 |
| 10406 | OPC_Decode, 219, 20, 123, // 21894: decode to PVFMULiv using decoder 123 |
| 10407 | // 21894: } else try { |
| 10408 | OPC_Decode, 225, 20, 130, 1, // 21898: decode to PVFMULivm using decoder 130 |
| 10409 | // 21898: } |
| 10410 | // 21898: } |
| 10411 | 1, 0, // 21903: case 0x1: { |
| 10412 | OPC_CheckField, 0, 8, 0, // 21905: check Inst[7:0] == 0x0 |
| 10413 | OPC_CheckField, 16, 8, 0, // 21909: check Inst[23:16] == 0x0 |
| 10414 | OPC_CheckField, 32, 8, 0, // 21913: check Inst[39:32] == 0x0 |
| 10415 | OPC_Scope, 8, // 21917: try { |
| 10416 | OPC_CheckField, 48, 4, 0, // 21919: check Inst[51:48] == 0x0 |
| 10417 | OPC_Decode, 231, 20, 127, // 21923: decode to PVFMULrv using decoder 127 |
| 10418 | // 21923: } else try { |
| 10419 | OPC_Decode, 237, 20, 131, 1, // 21927: decode to PVFMULrvm using decoder 131 |
| 10420 | // 21927: } |
| 10421 | // 21927: } |
| 10422 | // 21927: } // switch Inst[47] |
| 10423 | // 21927: } |
| 10424 | // 21927: } // switch Inst[54:52] |
| 10425 | // 21927: } |
| 10426 | 156, 3, 33, // 21932: case 0x19c: { |
| 10427 | OPC_SwitchField, 47, 8, // 21935: switch Inst[54:47] { |
| 10428 | 0, 13, // 21938: case 0x0: { |
| 10429 | OPC_CheckField, 32, 8, 0, // 21940: check Inst[39:32] == 0x0 |
| 10430 | OPC_CheckField, 0, 16, 0, // 21944: check Inst[15:0] == 0x0 |
| 10431 | OPC_Decode, 168, 45, 214, 1, // 21948: decode to VFIADvi using decoder 214 |
| 10432 | // 21948: } |
| 10433 | 1, 0, // 21953: case 0x1: { |
| 10434 | OPC_CheckField, 32, 8, 0, // 21955: check Inst[39:32] == 0x0 |
| 10435 | OPC_CheckField, 0, 16, 0, // 21959: check Inst[15:0] == 0x0 |
| 10436 | OPC_Decode, 174, 45, 215, 1, // 21963: decode to VFIADvr using decoder 215 |
| 10437 | // 21963: } |
| 10438 | // 21963: } // switch Inst[54:47] |
| 10439 | // 21963: } |
| 10440 | 157, 3, 33, // 21968: case 0x19d: { |
| 10441 | OPC_SwitchField, 47, 8, // 21971: switch Inst[54:47] { |
| 10442 | 0, 13, // 21974: case 0x0: { |
| 10443 | OPC_CheckField, 32, 8, 0, // 21976: check Inst[39:32] == 0x0 |
| 10444 | OPC_CheckField, 0, 16, 0, // 21980: check Inst[15:0] == 0x0 |
| 10445 | OPC_Decode, 204, 45, 214, 1, // 21984: decode to VFIASvi using decoder 214 |
| 10446 | // 21984: } |
| 10447 | 1, 0, // 21989: case 0x1: { |
| 10448 | OPC_CheckField, 32, 8, 0, // 21991: check Inst[39:32] == 0x0 |
| 10449 | OPC_CheckField, 0, 16, 0, // 21995: check Inst[15:0] == 0x0 |
| 10450 | OPC_Decode, 210, 45, 216, 1, // 21999: decode to VFIASvr using decoder 216 |
| 10451 | // 21999: } |
| 10452 | // 21999: } // switch Inst[54:47] |
| 10453 | // 21999: } |
| 10454 | 158, 3, 33, // 22004: case 0x19e: { |
| 10455 | OPC_SwitchField, 47, 8, // 22007: switch Inst[54:47] { |
| 10456 | 0, 13, // 22010: case 0x0: { |
| 10457 | OPC_CheckField, 32, 8, 0, // 22012: check Inst[39:32] == 0x0 |
| 10458 | OPC_CheckField, 0, 16, 0, // 22016: check Inst[15:0] == 0x0 |
| 10459 | OPC_Decode, 240, 45, 214, 1, // 22020: decode to VFIMDvi using decoder 214 |
| 10460 | // 22020: } |
| 10461 | 1, 0, // 22025: case 0x1: { |
| 10462 | OPC_CheckField, 32, 8, 0, // 22027: check Inst[39:32] == 0x0 |
| 10463 | OPC_CheckField, 0, 16, 0, // 22031: check Inst[15:0] == 0x0 |
| 10464 | OPC_Decode, 246, 45, 215, 1, // 22035: decode to VFIMDvr using decoder 215 |
| 10465 | // 22035: } |
| 10466 | // 22035: } // switch Inst[54:47] |
| 10467 | // 22035: } |
| 10468 | 159, 3, 33, // 22040: case 0x19f: { |
| 10469 | OPC_SwitchField, 47, 8, // 22043: switch Inst[54:47] { |
| 10470 | 0, 13, // 22046: case 0x0: { |
| 10471 | OPC_CheckField, 32, 8, 0, // 22048: check Inst[39:32] == 0x0 |
| 10472 | OPC_CheckField, 0, 16, 0, // 22052: check Inst[15:0] == 0x0 |
| 10473 | OPC_Decode, 148, 46, 214, 1, // 22056: decode to VFIMSvi using decoder 214 |
| 10474 | // 22056: } |
| 10475 | 1, 0, // 22061: case 0x1: { |
| 10476 | OPC_CheckField, 32, 8, 0, // 22063: check Inst[39:32] == 0x0 |
| 10477 | OPC_CheckField, 0, 16, 0, // 22067: check Inst[15:0] == 0x0 |
| 10478 | OPC_Decode, 154, 46, 216, 1, // 22071: decode to VFIMSvr using decoder 216 |
| 10479 | // 22071: } |
| 10480 | // 22071: } // switch Inst[54:47] |
| 10481 | // 22071: } |
| 10482 | 162, 3, 209, 1, // 22076: case 0x1a2: { |
| 10483 | OPC_SwitchField, 39, 1, // 22080: switch Inst[39] { |
| 10484 | 0, 101, // 22083: case 0x0: { |
| 10485 | OPC_SwitchField, 47, 1, // 22085: switch Inst[47] { |
| 10486 | 0, 47, // 22088: case 0x0: { |
| 10487 | OPC_SwitchField, 52, 3, // 22090: switch Inst[54:52] { |
| 10488 | 0, 20, // 22093: case 0x0: { |
| 10489 | OPC_CheckField, 0, 24, 0, // 22095: check Inst[23:0] == 0x0 |
| 10490 | OPC_Scope, 9, // 22099: try { |
| 10491 | OPC_CheckField, 48, 4, 0, // 22101: check Inst[51:48] == 0x0 |
| 10492 | OPC_Decode, 230, 77, 146, 1, // 22105: decode to VST2DNCizv using decoder 146 |
| 10493 | // 22105: } else try { |
| 10494 | OPC_Decode, 233, 77, 147, 1, // 22110: decode to VST2DNCizvm using decoder 147 |
| 10495 | // 22110: } |
| 10496 | // 22110: } |
| 10497 | 4, 0, // 22115: case 0x4: { |
| 10498 | OPC_CheckField, 0, 24, 0, // 22117: check Inst[23:0] == 0x0 |
| 10499 | OPC_Scope, 9, // 22121: try { |
| 10500 | OPC_CheckField, 48, 4, 0, // 22123: check Inst[51:48] == 0x0 |
| 10501 | OPC_Decode, 150, 78, 146, 1, // 22127: decode to VST2Dizv using decoder 146 |
| 10502 | // 22127: } else try { |
| 10503 | OPC_Decode, 153, 78, 147, 1, // 22132: decode to VST2Dizvm using decoder 147 |
| 10504 | // 22132: } |
| 10505 | // 22132: } |
| 10506 | // 22132: } // switch Inst[54:52] |
| 10507 | // 22132: } |
| 10508 | 1, 0, // 22137: case 0x1: { |
| 10509 | OPC_SwitchField, 52, 3, // 22139: switch Inst[54:52] { |
| 10510 | 0, 20, // 22142: case 0x0: { |
| 10511 | OPC_CheckField, 0, 24, 0, // 22144: check Inst[23:0] == 0x0 |
| 10512 | OPC_Scope, 9, // 22148: try { |
| 10513 | OPC_CheckField, 48, 4, 0, // 22150: check Inst[51:48] == 0x0 |
| 10514 | OPC_Decode, 242, 77, 148, 1, // 22154: decode to VST2DNCrzv using decoder 148 |
| 10515 | // 22154: } else try { |
| 10516 | OPC_Decode, 245, 77, 149, 1, // 22159: decode to VST2DNCrzvm using decoder 149 |
| 10517 | // 22159: } |
| 10518 | // 22159: } |
| 10519 | 4, 0, // 22164: case 0x4: { |
| 10520 | OPC_CheckField, 0, 24, 0, // 22166: check Inst[23:0] == 0x0 |
| 10521 | OPC_Scope, 9, // 22170: try { |
| 10522 | OPC_CheckField, 48, 4, 0, // 22172: check Inst[51:48] == 0x0 |
| 10523 | OPC_Decode, 162, 78, 148, 1, // 22176: decode to VST2Drzv using decoder 148 |
| 10524 | // 22176: } else try { |
| 10525 | OPC_Decode, 165, 78, 149, 1, // 22181: decode to VST2Drzvm using decoder 149 |
| 10526 | // 22181: } |
| 10527 | // 22181: } |
| 10528 | // 22181: } // switch Inst[54:52] |
| 10529 | // 22181: } |
| 10530 | // 22181: } // switch Inst[47] |
| 10531 | // 22181: } |
| 10532 | 1, 0, // 22186: case 0x1: { |
| 10533 | OPC_SwitchField, 47, 1, // 22188: switch Inst[47] { |
| 10534 | 0, 47, // 22191: case 0x0: { |
| 10535 | OPC_SwitchField, 52, 3, // 22193: switch Inst[54:52] { |
| 10536 | 0, 20, // 22196: case 0x0: { |
| 10537 | OPC_CheckField, 0, 24, 0, // 22198: check Inst[23:0] == 0x0 |
| 10538 | OPC_Scope, 9, // 22202: try { |
| 10539 | OPC_CheckField, 48, 4, 0, // 22204: check Inst[51:48] == 0x0 |
| 10540 | OPC_Decode, 224, 77, 150, 1, // 22208: decode to VST2DNCirv using decoder 150 |
| 10541 | // 22208: } else try { |
| 10542 | OPC_Decode, 227, 77, 151, 1, // 22213: decode to VST2DNCirvm using decoder 151 |
| 10543 | // 22213: } |
| 10544 | // 22213: } |
| 10545 | 4, 0, // 22218: case 0x4: { |
| 10546 | OPC_CheckField, 0, 24, 0, // 22220: check Inst[23:0] == 0x0 |
| 10547 | OPC_Scope, 9, // 22224: try { |
| 10548 | OPC_CheckField, 48, 4, 0, // 22226: check Inst[51:48] == 0x0 |
| 10549 | OPC_Decode, 144, 78, 150, 1, // 22230: decode to VST2Dirv using decoder 150 |
| 10550 | // 22230: } else try { |
| 10551 | OPC_Decode, 147, 78, 151, 1, // 22235: decode to VST2Dirvm using decoder 151 |
| 10552 | // 22235: } |
| 10553 | // 22235: } |
| 10554 | // 22235: } // switch Inst[54:52] |
| 10555 | // 22235: } |
| 10556 | 1, 0, // 22240: case 0x1: { |
| 10557 | OPC_SwitchField, 52, 3, // 22242: switch Inst[54:52] { |
| 10558 | 0, 20, // 22245: case 0x0: { |
| 10559 | OPC_CheckField, 0, 24, 0, // 22247: check Inst[23:0] == 0x0 |
| 10560 | OPC_Scope, 9, // 22251: try { |
| 10561 | OPC_CheckField, 48, 4, 0, // 22253: check Inst[51:48] == 0x0 |
| 10562 | OPC_Decode, 236, 77, 152, 1, // 22257: decode to VST2DNCrrv using decoder 152 |
| 10563 | // 22257: } else try { |
| 10564 | OPC_Decode, 239, 77, 153, 1, // 22262: decode to VST2DNCrrvm using decoder 153 |
| 10565 | // 22262: } |
| 10566 | // 22262: } |
| 10567 | 4, 0, // 22267: case 0x4: { |
| 10568 | OPC_CheckField, 0, 24, 0, // 22269: check Inst[23:0] == 0x0 |
| 10569 | OPC_Scope, 9, // 22273: try { |
| 10570 | OPC_CheckField, 48, 4, 0, // 22275: check Inst[51:48] == 0x0 |
| 10571 | OPC_Decode, 156, 78, 152, 1, // 22279: decode to VST2Drrv using decoder 152 |
| 10572 | // 22279: } else try { |
| 10573 | OPC_Decode, 159, 78, 153, 1, // 22284: decode to VST2Drrvm using decoder 153 |
| 10574 | // 22284: } |
| 10575 | // 22284: } |
| 10576 | // 22284: } // switch Inst[54:52] |
| 10577 | // 22284: } |
| 10578 | // 22284: } // switch Inst[47] |
| 10579 | // 22284: } |
| 10580 | // 22284: } // switch Inst[39] |
| 10581 | // 22284: } |
| 10582 | 163, 3, 209, 1, // 22289: case 0x1a3: { |
| 10583 | OPC_SwitchField, 39, 1, // 22293: switch Inst[39] { |
| 10584 | 0, 101, // 22296: case 0x0: { |
| 10585 | OPC_SwitchField, 47, 1, // 22298: switch Inst[47] { |
| 10586 | 0, 47, // 22301: case 0x0: { |
| 10587 | OPC_SwitchField, 52, 3, // 22303: switch Inst[54:52] { |
| 10588 | 0, 20, // 22306: case 0x0: { |
| 10589 | OPC_CheckField, 0, 24, 0, // 22308: check Inst[23:0] == 0x0 |
| 10590 | OPC_Scope, 9, // 22312: try { |
| 10591 | OPC_CheckField, 48, 4, 0, // 22314: check Inst[51:48] == 0x0 |
| 10592 | OPC_Decode, 206, 77, 146, 1, // 22318: decode to VST2DNCOTizv using decoder 146 |
| 10593 | // 22318: } else try { |
| 10594 | OPC_Decode, 209, 77, 147, 1, // 22323: decode to VST2DNCOTizvm using decoder 147 |
| 10595 | // 22323: } |
| 10596 | // 22323: } |
| 10597 | 4, 0, // 22328: case 0x4: { |
| 10598 | OPC_CheckField, 0, 24, 0, // 22330: check Inst[23:0] == 0x0 |
| 10599 | OPC_Scope, 9, // 22334: try { |
| 10600 | OPC_CheckField, 48, 4, 0, // 22336: check Inst[51:48] == 0x0 |
| 10601 | OPC_Decode, 254, 77, 146, 1, // 22340: decode to VST2DOTizv using decoder 146 |
| 10602 | // 22340: } else try { |
| 10603 | OPC_Decode, 129, 78, 147, 1, // 22345: decode to VST2DOTizvm using decoder 147 |
| 10604 | // 22345: } |
| 10605 | // 22345: } |
| 10606 | // 22345: } // switch Inst[54:52] |
| 10607 | // 22345: } |
| 10608 | 1, 0, // 22350: case 0x1: { |
| 10609 | OPC_SwitchField, 52, 3, // 22352: switch Inst[54:52] { |
| 10610 | 0, 20, // 22355: case 0x0: { |
| 10611 | OPC_CheckField, 0, 24, 0, // 22357: check Inst[23:0] == 0x0 |
| 10612 | OPC_Scope, 9, // 22361: try { |
| 10613 | OPC_CheckField, 48, 4, 0, // 22363: check Inst[51:48] == 0x0 |
| 10614 | OPC_Decode, 218, 77, 148, 1, // 22367: decode to VST2DNCOTrzv using decoder 148 |
| 10615 | // 22367: } else try { |
| 10616 | OPC_Decode, 221, 77, 149, 1, // 22372: decode to VST2DNCOTrzvm using decoder 149 |
| 10617 | // 22372: } |
| 10618 | // 22372: } |
| 10619 | 4, 0, // 22377: case 0x4: { |
| 10620 | OPC_CheckField, 0, 24, 0, // 22379: check Inst[23:0] == 0x0 |
| 10621 | OPC_Scope, 9, // 22383: try { |
| 10622 | OPC_CheckField, 48, 4, 0, // 22385: check Inst[51:48] == 0x0 |
| 10623 | OPC_Decode, 138, 78, 148, 1, // 22389: decode to VST2DOTrzv using decoder 148 |
| 10624 | // 22389: } else try { |
| 10625 | OPC_Decode, 141, 78, 149, 1, // 22394: decode to VST2DOTrzvm using decoder 149 |
| 10626 | // 22394: } |
| 10627 | // 22394: } |
| 10628 | // 22394: } // switch Inst[54:52] |
| 10629 | // 22394: } |
| 10630 | // 22394: } // switch Inst[47] |
| 10631 | // 22394: } |
| 10632 | 1, 0, // 22399: case 0x1: { |
| 10633 | OPC_SwitchField, 47, 1, // 22401: switch Inst[47] { |
| 10634 | 0, 47, // 22404: case 0x0: { |
| 10635 | OPC_SwitchField, 52, 3, // 22406: switch Inst[54:52] { |
| 10636 | 0, 20, // 22409: case 0x0: { |
| 10637 | OPC_CheckField, 0, 24, 0, // 22411: check Inst[23:0] == 0x0 |
| 10638 | OPC_Scope, 9, // 22415: try { |
| 10639 | OPC_CheckField, 48, 4, 0, // 22417: check Inst[51:48] == 0x0 |
| 10640 | OPC_Decode, 200, 77, 150, 1, // 22421: decode to VST2DNCOTirv using decoder 150 |
| 10641 | // 22421: } else try { |
| 10642 | OPC_Decode, 203, 77, 151, 1, // 22426: decode to VST2DNCOTirvm using decoder 151 |
| 10643 | // 22426: } |
| 10644 | // 22426: } |
| 10645 | 4, 0, // 22431: case 0x4: { |
| 10646 | OPC_CheckField, 0, 24, 0, // 22433: check Inst[23:0] == 0x0 |
| 10647 | OPC_Scope, 9, // 22437: try { |
| 10648 | OPC_CheckField, 48, 4, 0, // 22439: check Inst[51:48] == 0x0 |
| 10649 | OPC_Decode, 248, 77, 150, 1, // 22443: decode to VST2DOTirv using decoder 150 |
| 10650 | // 22443: } else try { |
| 10651 | OPC_Decode, 251, 77, 151, 1, // 22448: decode to VST2DOTirvm using decoder 151 |
| 10652 | // 22448: } |
| 10653 | // 22448: } |
| 10654 | // 22448: } // switch Inst[54:52] |
| 10655 | // 22448: } |
| 10656 | 1, 0, // 22453: case 0x1: { |
| 10657 | OPC_SwitchField, 52, 3, // 22455: switch Inst[54:52] { |
| 10658 | 0, 20, // 22458: case 0x0: { |
| 10659 | OPC_CheckField, 0, 24, 0, // 22460: check Inst[23:0] == 0x0 |
| 10660 | OPC_Scope, 9, // 22464: try { |
| 10661 | OPC_CheckField, 48, 4, 0, // 22466: check Inst[51:48] == 0x0 |
| 10662 | OPC_Decode, 212, 77, 152, 1, // 22470: decode to VST2DNCOTrrv using decoder 152 |
| 10663 | // 22470: } else try { |
| 10664 | OPC_Decode, 215, 77, 153, 1, // 22475: decode to VST2DNCOTrrvm using decoder 153 |
| 10665 | // 22475: } |
| 10666 | // 22475: } |
| 10667 | 4, 0, // 22480: case 0x4: { |
| 10668 | OPC_CheckField, 0, 24, 0, // 22482: check Inst[23:0] == 0x0 |
| 10669 | OPC_Scope, 9, // 22486: try { |
| 10670 | OPC_CheckField, 48, 4, 0, // 22488: check Inst[51:48] == 0x0 |
| 10671 | OPC_Decode, 132, 78, 152, 1, // 22492: decode to VST2DOTrrv using decoder 152 |
| 10672 | // 22492: } else try { |
| 10673 | OPC_Decode, 135, 78, 153, 1, // 22497: decode to VST2DOTrrvm using decoder 153 |
| 10674 | // 22497: } |
| 10675 | // 22497: } |
| 10676 | // 22497: } // switch Inst[54:52] |
| 10677 | // 22497: } |
| 10678 | // 22497: } // switch Inst[47] |
| 10679 | // 22497: } |
| 10680 | // 22497: } // switch Inst[39] |
| 10681 | // 22497: } |
| 10682 | 164, 3, 209, 1, // 22502: case 0x1a4: { |
| 10683 | OPC_SwitchField, 39, 1, // 22506: switch Inst[39] { |
| 10684 | 0, 101, // 22509: case 0x0: { |
| 10685 | OPC_SwitchField, 47, 1, // 22511: switch Inst[47] { |
| 10686 | 0, 47, // 22514: case 0x0: { |
| 10687 | OPC_SwitchField, 52, 3, // 22516: switch Inst[54:52] { |
| 10688 | 0, 20, // 22519: case 0x0: { |
| 10689 | OPC_CheckField, 0, 24, 0, // 22521: check Inst[23:0] == 0x0 |
| 10690 | OPC_Scope, 9, // 22525: try { |
| 10691 | OPC_CheckField, 48, 4, 0, // 22527: check Inst[51:48] == 0x0 |
| 10692 | OPC_Decode, 206, 80, 146, 1, // 22531: decode to VSTU2DNCizv using decoder 146 |
| 10693 | // 22531: } else try { |
| 10694 | OPC_Decode, 209, 80, 147, 1, // 22536: decode to VSTU2DNCizvm using decoder 147 |
| 10695 | // 22536: } |
| 10696 | // 22536: } |
| 10697 | 4, 0, // 22541: case 0x4: { |
| 10698 | OPC_CheckField, 0, 24, 0, // 22543: check Inst[23:0] == 0x0 |
| 10699 | OPC_Scope, 9, // 22547: try { |
| 10700 | OPC_CheckField, 48, 4, 0, // 22549: check Inst[51:48] == 0x0 |
| 10701 | OPC_Decode, 254, 80, 146, 1, // 22553: decode to VSTU2Dizv using decoder 146 |
| 10702 | // 22553: } else try { |
| 10703 | OPC_Decode, 129, 81, 147, 1, // 22558: decode to VSTU2Dizvm using decoder 147 |
| 10704 | // 22558: } |
| 10705 | // 22558: } |
| 10706 | // 22558: } // switch Inst[54:52] |
| 10707 | // 22558: } |
| 10708 | 1, 0, // 22563: case 0x1: { |
| 10709 | OPC_SwitchField, 52, 3, // 22565: switch Inst[54:52] { |
| 10710 | 0, 20, // 22568: case 0x0: { |
| 10711 | OPC_CheckField, 0, 24, 0, // 22570: check Inst[23:0] == 0x0 |
| 10712 | OPC_Scope, 9, // 22574: try { |
| 10713 | OPC_CheckField, 48, 4, 0, // 22576: check Inst[51:48] == 0x0 |
| 10714 | OPC_Decode, 218, 80, 148, 1, // 22580: decode to VSTU2DNCrzv using decoder 148 |
| 10715 | // 22580: } else try { |
| 10716 | OPC_Decode, 221, 80, 149, 1, // 22585: decode to VSTU2DNCrzvm using decoder 149 |
| 10717 | // 22585: } |
| 10718 | // 22585: } |
| 10719 | 4, 0, // 22590: case 0x4: { |
| 10720 | OPC_CheckField, 0, 24, 0, // 22592: check Inst[23:0] == 0x0 |
| 10721 | OPC_Scope, 9, // 22596: try { |
| 10722 | OPC_CheckField, 48, 4, 0, // 22598: check Inst[51:48] == 0x0 |
| 10723 | OPC_Decode, 138, 81, 148, 1, // 22602: decode to VSTU2Drzv using decoder 148 |
| 10724 | // 22602: } else try { |
| 10725 | OPC_Decode, 141, 81, 149, 1, // 22607: decode to VSTU2Drzvm using decoder 149 |
| 10726 | // 22607: } |
| 10727 | // 22607: } |
| 10728 | // 22607: } // switch Inst[54:52] |
| 10729 | // 22607: } |
| 10730 | // 22607: } // switch Inst[47] |
| 10731 | // 22607: } |
| 10732 | 1, 0, // 22612: case 0x1: { |
| 10733 | OPC_SwitchField, 47, 1, // 22614: switch Inst[47] { |
| 10734 | 0, 47, // 22617: case 0x0: { |
| 10735 | OPC_SwitchField, 52, 3, // 22619: switch Inst[54:52] { |
| 10736 | 0, 20, // 22622: case 0x0: { |
| 10737 | OPC_CheckField, 0, 24, 0, // 22624: check Inst[23:0] == 0x0 |
| 10738 | OPC_Scope, 9, // 22628: try { |
| 10739 | OPC_CheckField, 48, 4, 0, // 22630: check Inst[51:48] == 0x0 |
| 10740 | OPC_Decode, 200, 80, 150, 1, // 22634: decode to VSTU2DNCirv using decoder 150 |
| 10741 | // 22634: } else try { |
| 10742 | OPC_Decode, 203, 80, 151, 1, // 22639: decode to VSTU2DNCirvm using decoder 151 |
| 10743 | // 22639: } |
| 10744 | // 22639: } |
| 10745 | 4, 0, // 22644: case 0x4: { |
| 10746 | OPC_CheckField, 0, 24, 0, // 22646: check Inst[23:0] == 0x0 |
| 10747 | OPC_Scope, 9, // 22650: try { |
| 10748 | OPC_CheckField, 48, 4, 0, // 22652: check Inst[51:48] == 0x0 |
| 10749 | OPC_Decode, 248, 80, 150, 1, // 22656: decode to VSTU2Dirv using decoder 150 |
| 10750 | // 22656: } else try { |
| 10751 | OPC_Decode, 251, 80, 151, 1, // 22661: decode to VSTU2Dirvm using decoder 151 |
| 10752 | // 22661: } |
| 10753 | // 22661: } |
| 10754 | // 22661: } // switch Inst[54:52] |
| 10755 | // 22661: } |
| 10756 | 1, 0, // 22666: case 0x1: { |
| 10757 | OPC_SwitchField, 52, 3, // 22668: switch Inst[54:52] { |
| 10758 | 0, 20, // 22671: case 0x0: { |
| 10759 | OPC_CheckField, 0, 24, 0, // 22673: check Inst[23:0] == 0x0 |
| 10760 | OPC_Scope, 9, // 22677: try { |
| 10761 | OPC_CheckField, 48, 4, 0, // 22679: check Inst[51:48] == 0x0 |
| 10762 | OPC_Decode, 212, 80, 152, 1, // 22683: decode to VSTU2DNCrrv using decoder 152 |
| 10763 | // 22683: } else try { |
| 10764 | OPC_Decode, 215, 80, 153, 1, // 22688: decode to VSTU2DNCrrvm using decoder 153 |
| 10765 | // 22688: } |
| 10766 | // 22688: } |
| 10767 | 4, 0, // 22693: case 0x4: { |
| 10768 | OPC_CheckField, 0, 24, 0, // 22695: check Inst[23:0] == 0x0 |
| 10769 | OPC_Scope, 9, // 22699: try { |
| 10770 | OPC_CheckField, 48, 4, 0, // 22701: check Inst[51:48] == 0x0 |
| 10771 | OPC_Decode, 132, 81, 152, 1, // 22705: decode to VSTU2Drrv using decoder 152 |
| 10772 | // 22705: } else try { |
| 10773 | OPC_Decode, 135, 81, 153, 1, // 22710: decode to VSTU2Drrvm using decoder 153 |
| 10774 | // 22710: } |
| 10775 | // 22710: } |
| 10776 | // 22710: } // switch Inst[54:52] |
| 10777 | // 22710: } |
| 10778 | // 22710: } // switch Inst[47] |
| 10779 | // 22710: } |
| 10780 | // 22710: } // switch Inst[39] |
| 10781 | // 22710: } |
| 10782 | 165, 3, 209, 1, // 22715: case 0x1a5: { |
| 10783 | OPC_SwitchField, 39, 1, // 22719: switch Inst[39] { |
| 10784 | 0, 101, // 22722: case 0x0: { |
| 10785 | OPC_SwitchField, 47, 1, // 22724: switch Inst[47] { |
| 10786 | 0, 47, // 22727: case 0x0: { |
| 10787 | OPC_SwitchField, 52, 3, // 22729: switch Inst[54:52] { |
| 10788 | 0, 20, // 22732: case 0x0: { |
| 10789 | OPC_CheckField, 0, 24, 0, // 22734: check Inst[23:0] == 0x0 |
| 10790 | OPC_Scope, 9, // 22738: try { |
| 10791 | OPC_CheckField, 48, 4, 0, // 22740: check Inst[51:48] == 0x0 |
| 10792 | OPC_Decode, 182, 80, 146, 1, // 22744: decode to VSTU2DNCOTizv using decoder 146 |
| 10793 | // 22744: } else try { |
| 10794 | OPC_Decode, 185, 80, 147, 1, // 22749: decode to VSTU2DNCOTizvm using decoder 147 |
| 10795 | // 22749: } |
| 10796 | // 22749: } |
| 10797 | 4, 0, // 22754: case 0x4: { |
| 10798 | OPC_CheckField, 0, 24, 0, // 22756: check Inst[23:0] == 0x0 |
| 10799 | OPC_Scope, 9, // 22760: try { |
| 10800 | OPC_CheckField, 48, 4, 0, // 22762: check Inst[51:48] == 0x0 |
| 10801 | OPC_Decode, 230, 80, 146, 1, // 22766: decode to VSTU2DOTizv using decoder 146 |
| 10802 | // 22766: } else try { |
| 10803 | OPC_Decode, 233, 80, 147, 1, // 22771: decode to VSTU2DOTizvm using decoder 147 |
| 10804 | // 22771: } |
| 10805 | // 22771: } |
| 10806 | // 22771: } // switch Inst[54:52] |
| 10807 | // 22771: } |
| 10808 | 1, 0, // 22776: case 0x1: { |
| 10809 | OPC_SwitchField, 52, 3, // 22778: switch Inst[54:52] { |
| 10810 | 0, 20, // 22781: case 0x0: { |
| 10811 | OPC_CheckField, 0, 24, 0, // 22783: check Inst[23:0] == 0x0 |
| 10812 | OPC_Scope, 9, // 22787: try { |
| 10813 | OPC_CheckField, 48, 4, 0, // 22789: check Inst[51:48] == 0x0 |
| 10814 | OPC_Decode, 194, 80, 148, 1, // 22793: decode to VSTU2DNCOTrzv using decoder 148 |
| 10815 | // 22793: } else try { |
| 10816 | OPC_Decode, 197, 80, 149, 1, // 22798: decode to VSTU2DNCOTrzvm using decoder 149 |
| 10817 | // 22798: } |
| 10818 | // 22798: } |
| 10819 | 4, 0, // 22803: case 0x4: { |
| 10820 | OPC_CheckField, 0, 24, 0, // 22805: check Inst[23:0] == 0x0 |
| 10821 | OPC_Scope, 9, // 22809: try { |
| 10822 | OPC_CheckField, 48, 4, 0, // 22811: check Inst[51:48] == 0x0 |
| 10823 | OPC_Decode, 242, 80, 148, 1, // 22815: decode to VSTU2DOTrzv using decoder 148 |
| 10824 | // 22815: } else try { |
| 10825 | OPC_Decode, 245, 80, 149, 1, // 22820: decode to VSTU2DOTrzvm using decoder 149 |
| 10826 | // 22820: } |
| 10827 | // 22820: } |
| 10828 | // 22820: } // switch Inst[54:52] |
| 10829 | // 22820: } |
| 10830 | // 22820: } // switch Inst[47] |
| 10831 | // 22820: } |
| 10832 | 1, 0, // 22825: case 0x1: { |
| 10833 | OPC_SwitchField, 47, 1, // 22827: switch Inst[47] { |
| 10834 | 0, 47, // 22830: case 0x0: { |
| 10835 | OPC_SwitchField, 52, 3, // 22832: switch Inst[54:52] { |
| 10836 | 0, 20, // 22835: case 0x0: { |
| 10837 | OPC_CheckField, 0, 24, 0, // 22837: check Inst[23:0] == 0x0 |
| 10838 | OPC_Scope, 9, // 22841: try { |
| 10839 | OPC_CheckField, 48, 4, 0, // 22843: check Inst[51:48] == 0x0 |
| 10840 | OPC_Decode, 176, 80, 150, 1, // 22847: decode to VSTU2DNCOTirv using decoder 150 |
| 10841 | // 22847: } else try { |
| 10842 | OPC_Decode, 179, 80, 151, 1, // 22852: decode to VSTU2DNCOTirvm using decoder 151 |
| 10843 | // 22852: } |
| 10844 | // 22852: } |
| 10845 | 4, 0, // 22857: case 0x4: { |
| 10846 | OPC_CheckField, 0, 24, 0, // 22859: check Inst[23:0] == 0x0 |
| 10847 | OPC_Scope, 9, // 22863: try { |
| 10848 | OPC_CheckField, 48, 4, 0, // 22865: check Inst[51:48] == 0x0 |
| 10849 | OPC_Decode, 224, 80, 150, 1, // 22869: decode to VSTU2DOTirv using decoder 150 |
| 10850 | // 22869: } else try { |
| 10851 | OPC_Decode, 227, 80, 151, 1, // 22874: decode to VSTU2DOTirvm using decoder 151 |
| 10852 | // 22874: } |
| 10853 | // 22874: } |
| 10854 | // 22874: } // switch Inst[54:52] |
| 10855 | // 22874: } |
| 10856 | 1, 0, // 22879: case 0x1: { |
| 10857 | OPC_SwitchField, 52, 3, // 22881: switch Inst[54:52] { |
| 10858 | 0, 20, // 22884: case 0x0: { |
| 10859 | OPC_CheckField, 0, 24, 0, // 22886: check Inst[23:0] == 0x0 |
| 10860 | OPC_Scope, 9, // 22890: try { |
| 10861 | OPC_CheckField, 48, 4, 0, // 22892: check Inst[51:48] == 0x0 |
| 10862 | OPC_Decode, 188, 80, 152, 1, // 22896: decode to VSTU2DNCOTrrv using decoder 152 |
| 10863 | // 22896: } else try { |
| 10864 | OPC_Decode, 191, 80, 153, 1, // 22901: decode to VSTU2DNCOTrrvm using decoder 153 |
| 10865 | // 22901: } |
| 10866 | // 22901: } |
| 10867 | 4, 0, // 22906: case 0x4: { |
| 10868 | OPC_CheckField, 0, 24, 0, // 22908: check Inst[23:0] == 0x0 |
| 10869 | OPC_Scope, 9, // 22912: try { |
| 10870 | OPC_CheckField, 48, 4, 0, // 22914: check Inst[51:48] == 0x0 |
| 10871 | OPC_Decode, 236, 80, 152, 1, // 22918: decode to VSTU2DOTrrv using decoder 152 |
| 10872 | // 22918: } else try { |
| 10873 | OPC_Decode, 239, 80, 153, 1, // 22923: decode to VSTU2DOTrrvm using decoder 153 |
| 10874 | // 22923: } |
| 10875 | // 22923: } |
| 10876 | // 22923: } // switch Inst[54:52] |
| 10877 | // 22923: } |
| 10878 | // 22923: } // switch Inst[47] |
| 10879 | // 22923: } |
| 10880 | // 22923: } // switch Inst[39] |
| 10881 | // 22923: } |
| 10882 | 166, 3, 209, 1, // 22928: case 0x1a6: { |
| 10883 | OPC_SwitchField, 39, 1, // 22932: switch Inst[39] { |
| 10884 | 0, 101, // 22935: case 0x0: { |
| 10885 | OPC_SwitchField, 47, 1, // 22937: switch Inst[47] { |
| 10886 | 0, 47, // 22940: case 0x0: { |
| 10887 | OPC_SwitchField, 52, 3, // 22942: switch Inst[54:52] { |
| 10888 | 0, 20, // 22945: case 0x0: { |
| 10889 | OPC_CheckField, 0, 24, 0, // 22947: check Inst[23:0] == 0x0 |
| 10890 | OPC_Scope, 9, // 22951: try { |
| 10891 | OPC_CheckField, 48, 4, 0, // 22953: check Inst[51:48] == 0x0 |
| 10892 | OPC_Decode, 198, 78, 146, 1, // 22957: decode to VSTL2DNCizv using decoder 146 |
| 10893 | // 22957: } else try { |
| 10894 | OPC_Decode, 201, 78, 147, 1, // 22962: decode to VSTL2DNCizvm using decoder 147 |
| 10895 | // 22962: } |
| 10896 | // 22962: } |
| 10897 | 4, 0, // 22967: case 0x4: { |
| 10898 | OPC_CheckField, 0, 24, 0, // 22969: check Inst[23:0] == 0x0 |
| 10899 | OPC_Scope, 9, // 22973: try { |
| 10900 | OPC_CheckField, 48, 4, 0, // 22975: check Inst[51:48] == 0x0 |
| 10901 | OPC_Decode, 246, 78, 146, 1, // 22979: decode to VSTL2Dizv using decoder 146 |
| 10902 | // 22979: } else try { |
| 10903 | OPC_Decode, 249, 78, 147, 1, // 22984: decode to VSTL2Dizvm using decoder 147 |
| 10904 | // 22984: } |
| 10905 | // 22984: } |
| 10906 | // 22984: } // switch Inst[54:52] |
| 10907 | // 22984: } |
| 10908 | 1, 0, // 22989: case 0x1: { |
| 10909 | OPC_SwitchField, 52, 3, // 22991: switch Inst[54:52] { |
| 10910 | 0, 20, // 22994: case 0x0: { |
| 10911 | OPC_CheckField, 0, 24, 0, // 22996: check Inst[23:0] == 0x0 |
| 10912 | OPC_Scope, 9, // 23000: try { |
| 10913 | OPC_CheckField, 48, 4, 0, // 23002: check Inst[51:48] == 0x0 |
| 10914 | OPC_Decode, 210, 78, 148, 1, // 23006: decode to VSTL2DNCrzv using decoder 148 |
| 10915 | // 23006: } else try { |
| 10916 | OPC_Decode, 213, 78, 149, 1, // 23011: decode to VSTL2DNCrzvm using decoder 149 |
| 10917 | // 23011: } |
| 10918 | // 23011: } |
| 10919 | 4, 0, // 23016: case 0x4: { |
| 10920 | OPC_CheckField, 0, 24, 0, // 23018: check Inst[23:0] == 0x0 |
| 10921 | OPC_Scope, 9, // 23022: try { |
| 10922 | OPC_CheckField, 48, 4, 0, // 23024: check Inst[51:48] == 0x0 |
| 10923 | OPC_Decode, 130, 79, 148, 1, // 23028: decode to VSTL2Drzv using decoder 148 |
| 10924 | // 23028: } else try { |
| 10925 | OPC_Decode, 133, 79, 149, 1, // 23033: decode to VSTL2Drzvm using decoder 149 |
| 10926 | // 23033: } |
| 10927 | // 23033: } |
| 10928 | // 23033: } // switch Inst[54:52] |
| 10929 | // 23033: } |
| 10930 | // 23033: } // switch Inst[47] |
| 10931 | // 23033: } |
| 10932 | 1, 0, // 23038: case 0x1: { |
| 10933 | OPC_SwitchField, 47, 1, // 23040: switch Inst[47] { |
| 10934 | 0, 47, // 23043: case 0x0: { |
| 10935 | OPC_SwitchField, 52, 3, // 23045: switch Inst[54:52] { |
| 10936 | 0, 20, // 23048: case 0x0: { |
| 10937 | OPC_CheckField, 0, 24, 0, // 23050: check Inst[23:0] == 0x0 |
| 10938 | OPC_Scope, 9, // 23054: try { |
| 10939 | OPC_CheckField, 48, 4, 0, // 23056: check Inst[51:48] == 0x0 |
| 10940 | OPC_Decode, 192, 78, 150, 1, // 23060: decode to VSTL2DNCirv using decoder 150 |
| 10941 | // 23060: } else try { |
| 10942 | OPC_Decode, 195, 78, 151, 1, // 23065: decode to VSTL2DNCirvm using decoder 151 |
| 10943 | // 23065: } |
| 10944 | // 23065: } |
| 10945 | 4, 0, // 23070: case 0x4: { |
| 10946 | OPC_CheckField, 0, 24, 0, // 23072: check Inst[23:0] == 0x0 |
| 10947 | OPC_Scope, 9, // 23076: try { |
| 10948 | OPC_CheckField, 48, 4, 0, // 23078: check Inst[51:48] == 0x0 |
| 10949 | OPC_Decode, 240, 78, 150, 1, // 23082: decode to VSTL2Dirv using decoder 150 |
| 10950 | // 23082: } else try { |
| 10951 | OPC_Decode, 243, 78, 151, 1, // 23087: decode to VSTL2Dirvm using decoder 151 |
| 10952 | // 23087: } |
| 10953 | // 23087: } |
| 10954 | // 23087: } // switch Inst[54:52] |
| 10955 | // 23087: } |
| 10956 | 1, 0, // 23092: case 0x1: { |
| 10957 | OPC_SwitchField, 52, 3, // 23094: switch Inst[54:52] { |
| 10958 | 0, 20, // 23097: case 0x0: { |
| 10959 | OPC_CheckField, 0, 24, 0, // 23099: check Inst[23:0] == 0x0 |
| 10960 | OPC_Scope, 9, // 23103: try { |
| 10961 | OPC_CheckField, 48, 4, 0, // 23105: check Inst[51:48] == 0x0 |
| 10962 | OPC_Decode, 204, 78, 152, 1, // 23109: decode to VSTL2DNCrrv using decoder 152 |
| 10963 | // 23109: } else try { |
| 10964 | OPC_Decode, 207, 78, 153, 1, // 23114: decode to VSTL2DNCrrvm using decoder 153 |
| 10965 | // 23114: } |
| 10966 | // 23114: } |
| 10967 | 4, 0, // 23119: case 0x4: { |
| 10968 | OPC_CheckField, 0, 24, 0, // 23121: check Inst[23:0] == 0x0 |
| 10969 | OPC_Scope, 9, // 23125: try { |
| 10970 | OPC_CheckField, 48, 4, 0, // 23127: check Inst[51:48] == 0x0 |
| 10971 | OPC_Decode, 252, 78, 152, 1, // 23131: decode to VSTL2Drrv using decoder 152 |
| 10972 | // 23131: } else try { |
| 10973 | OPC_Decode, 255, 78, 153, 1, // 23136: decode to VSTL2Drrvm using decoder 153 |
| 10974 | // 23136: } |
| 10975 | // 23136: } |
| 10976 | // 23136: } // switch Inst[54:52] |
| 10977 | // 23136: } |
| 10978 | // 23136: } // switch Inst[47] |
| 10979 | // 23136: } |
| 10980 | // 23136: } // switch Inst[39] |
| 10981 | // 23136: } |
| 10982 | 167, 3, 209, 1, // 23141: case 0x1a7: { |
| 10983 | OPC_SwitchField, 39, 1, // 23145: switch Inst[39] { |
| 10984 | 0, 101, // 23148: case 0x0: { |
| 10985 | OPC_SwitchField, 47, 1, // 23150: switch Inst[47] { |
| 10986 | 0, 47, // 23153: case 0x0: { |
| 10987 | OPC_SwitchField, 52, 3, // 23155: switch Inst[54:52] { |
| 10988 | 0, 20, // 23158: case 0x0: { |
| 10989 | OPC_CheckField, 0, 24, 0, // 23160: check Inst[23:0] == 0x0 |
| 10990 | OPC_Scope, 9, // 23164: try { |
| 10991 | OPC_CheckField, 48, 4, 0, // 23166: check Inst[51:48] == 0x0 |
| 10992 | OPC_Decode, 174, 78, 146, 1, // 23170: decode to VSTL2DNCOTizv using decoder 146 |
| 10993 | // 23170: } else try { |
| 10994 | OPC_Decode, 177, 78, 147, 1, // 23175: decode to VSTL2DNCOTizvm using decoder 147 |
| 10995 | // 23175: } |
| 10996 | // 23175: } |
| 10997 | 4, 0, // 23180: case 0x4: { |
| 10998 | OPC_CheckField, 0, 24, 0, // 23182: check Inst[23:0] == 0x0 |
| 10999 | OPC_Scope, 9, // 23186: try { |
| 11000 | OPC_CheckField, 48, 4, 0, // 23188: check Inst[51:48] == 0x0 |
| 11001 | OPC_Decode, 222, 78, 146, 1, // 23192: decode to VSTL2DOTizv using decoder 146 |
| 11002 | // 23192: } else try { |
| 11003 | OPC_Decode, 225, 78, 147, 1, // 23197: decode to VSTL2DOTizvm using decoder 147 |
| 11004 | // 23197: } |
| 11005 | // 23197: } |
| 11006 | // 23197: } // switch Inst[54:52] |
| 11007 | // 23197: } |
| 11008 | 1, 0, // 23202: case 0x1: { |
| 11009 | OPC_SwitchField, 52, 3, // 23204: switch Inst[54:52] { |
| 11010 | 0, 20, // 23207: case 0x0: { |
| 11011 | OPC_CheckField, 0, 24, 0, // 23209: check Inst[23:0] == 0x0 |
| 11012 | OPC_Scope, 9, // 23213: try { |
| 11013 | OPC_CheckField, 48, 4, 0, // 23215: check Inst[51:48] == 0x0 |
| 11014 | OPC_Decode, 186, 78, 148, 1, // 23219: decode to VSTL2DNCOTrzv using decoder 148 |
| 11015 | // 23219: } else try { |
| 11016 | OPC_Decode, 189, 78, 149, 1, // 23224: decode to VSTL2DNCOTrzvm using decoder 149 |
| 11017 | // 23224: } |
| 11018 | // 23224: } |
| 11019 | 4, 0, // 23229: case 0x4: { |
| 11020 | OPC_CheckField, 0, 24, 0, // 23231: check Inst[23:0] == 0x0 |
| 11021 | OPC_Scope, 9, // 23235: try { |
| 11022 | OPC_CheckField, 48, 4, 0, // 23237: check Inst[51:48] == 0x0 |
| 11023 | OPC_Decode, 234, 78, 148, 1, // 23241: decode to VSTL2DOTrzv using decoder 148 |
| 11024 | // 23241: } else try { |
| 11025 | OPC_Decode, 237, 78, 149, 1, // 23246: decode to VSTL2DOTrzvm using decoder 149 |
| 11026 | // 23246: } |
| 11027 | // 23246: } |
| 11028 | // 23246: } // switch Inst[54:52] |
| 11029 | // 23246: } |
| 11030 | // 23246: } // switch Inst[47] |
| 11031 | // 23246: } |
| 11032 | 1, 0, // 23251: case 0x1: { |
| 11033 | OPC_SwitchField, 47, 1, // 23253: switch Inst[47] { |
| 11034 | 0, 47, // 23256: case 0x0: { |
| 11035 | OPC_SwitchField, 52, 3, // 23258: switch Inst[54:52] { |
| 11036 | 0, 20, // 23261: case 0x0: { |
| 11037 | OPC_CheckField, 0, 24, 0, // 23263: check Inst[23:0] == 0x0 |
| 11038 | OPC_Scope, 9, // 23267: try { |
| 11039 | OPC_CheckField, 48, 4, 0, // 23269: check Inst[51:48] == 0x0 |
| 11040 | OPC_Decode, 168, 78, 150, 1, // 23273: decode to VSTL2DNCOTirv using decoder 150 |
| 11041 | // 23273: } else try { |
| 11042 | OPC_Decode, 171, 78, 151, 1, // 23278: decode to VSTL2DNCOTirvm using decoder 151 |
| 11043 | // 23278: } |
| 11044 | // 23278: } |
| 11045 | 4, 0, // 23283: case 0x4: { |
| 11046 | OPC_CheckField, 0, 24, 0, // 23285: check Inst[23:0] == 0x0 |
| 11047 | OPC_Scope, 9, // 23289: try { |
| 11048 | OPC_CheckField, 48, 4, 0, // 23291: check Inst[51:48] == 0x0 |
| 11049 | OPC_Decode, 216, 78, 150, 1, // 23295: decode to VSTL2DOTirv using decoder 150 |
| 11050 | // 23295: } else try { |
| 11051 | OPC_Decode, 219, 78, 151, 1, // 23300: decode to VSTL2DOTirvm using decoder 151 |
| 11052 | // 23300: } |
| 11053 | // 23300: } |
| 11054 | // 23300: } // switch Inst[54:52] |
| 11055 | // 23300: } |
| 11056 | 1, 0, // 23305: case 0x1: { |
| 11057 | OPC_SwitchField, 52, 3, // 23307: switch Inst[54:52] { |
| 11058 | 0, 20, // 23310: case 0x0: { |
| 11059 | OPC_CheckField, 0, 24, 0, // 23312: check Inst[23:0] == 0x0 |
| 11060 | OPC_Scope, 9, // 23316: try { |
| 11061 | OPC_CheckField, 48, 4, 0, // 23318: check Inst[51:48] == 0x0 |
| 11062 | OPC_Decode, 180, 78, 152, 1, // 23322: decode to VSTL2DNCOTrrv using decoder 152 |
| 11063 | // 23322: } else try { |
| 11064 | OPC_Decode, 183, 78, 153, 1, // 23327: decode to VSTL2DNCOTrrvm using decoder 153 |
| 11065 | // 23327: } |
| 11066 | // 23327: } |
| 11067 | 4, 0, // 23332: case 0x4: { |
| 11068 | OPC_CheckField, 0, 24, 0, // 23334: check Inst[23:0] == 0x0 |
| 11069 | OPC_Scope, 9, // 23338: try { |
| 11070 | OPC_CheckField, 48, 4, 0, // 23340: check Inst[51:48] == 0x0 |
| 11071 | OPC_Decode, 228, 78, 152, 1, // 23344: decode to VSTL2DOTrrv using decoder 152 |
| 11072 | // 23344: } else try { |
| 11073 | OPC_Decode, 231, 78, 153, 1, // 23349: decode to VSTL2DOTrrvm using decoder 153 |
| 11074 | // 23349: } |
| 11075 | // 23349: } |
| 11076 | // 23349: } // switch Inst[54:52] |
| 11077 | // 23349: } |
| 11078 | // 23349: } // switch Inst[47] |
| 11079 | // 23349: } |
| 11080 | // 23349: } // switch Inst[39] |
| 11081 | // 23349: } |
| 11082 | 168, 3, 98, // 23354: case 0x1a8: { |
| 11083 | OPC_SwitchField, 47, 1, // 23357: switch Inst[47] { |
| 11084 | 0, 59, // 23360: case 0x0: { |
| 11085 | OPC_SwitchField, 52, 3, // 23362: switch Inst[54:52] { |
| 11086 | 0, 24, // 23365: case 0x0: { |
| 11087 | OPC_CheckField, 0, 8, 0, // 23367: check Inst[7:0] == 0x0 |
| 11088 | OPC_CheckField, 32, 15, 0, // 23371: check Inst[46:32] == 0x0 |
| 11089 | OPC_Scope, 9, // 23375: try { |
| 11090 | OPC_CheckField, 48, 4, 0, // 23377: check Inst[51:48] == 0x0 |
| 11091 | OPC_Decode, 144, 75, 217, 1, // 23381: decode to VSLALvv using decoder 217 |
| 11092 | // 23381: } else try { |
| 11093 | OPC_Decode, 150, 75, 218, 1, // 23386: decode to VSLALvvm using decoder 218 |
| 11094 | // 23386: } |
| 11095 | // 23386: } |
| 11096 | 2, 0, // 23391: case 0x2: { |
| 11097 | OPC_CheckField, 0, 8, 0, // 23393: check Inst[7:0] == 0x0 |
| 11098 | OPC_CheckField, 16, 8, 0, // 23397: check Inst[23:16] == 0x0 |
| 11099 | OPC_CheckField, 32, 8, 0, // 23401: check Inst[39:32] == 0x0 |
| 11100 | OPC_Scope, 9, // 23405: try { |
| 11101 | OPC_CheckField, 48, 4, 0, // 23407: check Inst[51:48] == 0x0 |
| 11102 | OPC_Decode, 248, 74, 219, 1, // 23411: decode to VSLALvi using decoder 219 |
| 11103 | // 23411: } else try { |
| 11104 | OPC_Decode, 254, 74, 220, 1, // 23416: decode to VSLALvim using decoder 220 |
| 11105 | // 23416: } |
| 11106 | // 23416: } |
| 11107 | // 23416: } // switch Inst[54:52] |
| 11108 | // 23416: } |
| 11109 | 1, 0, // 23421: case 0x1: { |
| 11110 | OPC_CheckField, 0, 8, 0, // 23423: check Inst[7:0] == 0x0 |
| 11111 | OPC_CheckField, 16, 8, 0, // 23427: check Inst[23:16] == 0x0 |
| 11112 | OPC_CheckField, 32, 8, 0, // 23431: check Inst[39:32] == 0x0 |
| 11113 | OPC_CheckField, 52, 3, 2, // 23435: check Inst[54:52] == 0x2 |
| 11114 | OPC_Scope, 9, // 23439: try { |
| 11115 | OPC_CheckField, 48, 4, 0, // 23441: check Inst[51:48] == 0x0 |
| 11116 | OPC_Decode, 132, 75, 221, 1, // 23445: decode to VSLALvr using decoder 221 |
| 11117 | // 23445: } else try { |
| 11118 | OPC_Decode, 138, 75, 222, 1, // 23450: decode to VSLALvrm using decoder 222 |
| 11119 | // 23450: } |
| 11120 | // 23450: } |
| 11121 | // 23450: } // switch Inst[47] |
| 11122 | // 23450: } |
| 11123 | 170, 3, 98, // 23455: case 0x1aa: { |
| 11124 | OPC_SwitchField, 47, 1, // 23458: switch Inst[47] { |
| 11125 | 0, 59, // 23461: case 0x0: { |
| 11126 | OPC_SwitchField, 52, 3, // 23463: switch Inst[54:52] { |
| 11127 | 0, 24, // 23466: case 0x0: { |
| 11128 | OPC_CheckField, 0, 8, 0, // 23468: check Inst[7:0] == 0x0 |
| 11129 | OPC_CheckField, 32, 15, 0, // 23472: check Inst[46:32] == 0x0 |
| 11130 | OPC_Scope, 9, // 23476: try { |
| 11131 | OPC_CheckField, 48, 4, 0, // 23478: check Inst[51:48] == 0x0 |
| 11132 | OPC_Decode, 184, 76, 217, 1, // 23482: decode to VSRALvv using decoder 217 |
| 11133 | // 23482: } else try { |
| 11134 | OPC_Decode, 190, 76, 218, 1, // 23487: decode to VSRALvvm using decoder 218 |
| 11135 | // 23487: } |
| 11136 | // 23487: } |
| 11137 | 2, 0, // 23492: case 0x2: { |
| 11138 | OPC_CheckField, 0, 8, 0, // 23494: check Inst[7:0] == 0x0 |
| 11139 | OPC_CheckField, 16, 8, 0, // 23498: check Inst[23:16] == 0x0 |
| 11140 | OPC_CheckField, 32, 8, 0, // 23502: check Inst[39:32] == 0x0 |
| 11141 | OPC_Scope, 9, // 23506: try { |
| 11142 | OPC_CheckField, 48, 4, 0, // 23508: check Inst[51:48] == 0x0 |
| 11143 | OPC_Decode, 160, 76, 219, 1, // 23512: decode to VSRALvi using decoder 219 |
| 11144 | // 23512: } else try { |
| 11145 | OPC_Decode, 166, 76, 220, 1, // 23517: decode to VSRALvim using decoder 220 |
| 11146 | // 23517: } |
| 11147 | // 23517: } |
| 11148 | // 23517: } // switch Inst[54:52] |
| 11149 | // 23517: } |
| 11150 | 1, 0, // 23522: case 0x1: { |
| 11151 | OPC_CheckField, 0, 8, 0, // 23524: check Inst[7:0] == 0x0 |
| 11152 | OPC_CheckField, 16, 8, 0, // 23528: check Inst[23:16] == 0x0 |
| 11153 | OPC_CheckField, 32, 8, 0, // 23532: check Inst[39:32] == 0x0 |
| 11154 | OPC_CheckField, 52, 3, 2, // 23536: check Inst[54:52] == 0x2 |
| 11155 | OPC_Scope, 9, // 23540: try { |
| 11156 | OPC_CheckField, 48, 4, 0, // 23542: check Inst[51:48] == 0x0 |
| 11157 | OPC_Decode, 172, 76, 221, 1, // 23546: decode to VSRALvr using decoder 221 |
| 11158 | // 23546: } else try { |
| 11159 | OPC_Decode, 178, 76, 222, 1, // 23551: decode to VSRALvrm using decoder 222 |
| 11160 | // 23551: } |
| 11161 | // 23551: } |
| 11162 | // 23551: } // switch Inst[47] |
| 11163 | // 23551: } |
| 11164 | 172, 3, 93, // 23556: case 0x1ac: { |
| 11165 | OPC_SwitchField, 47, 1, // 23559: switch Inst[47] { |
| 11166 | 0, 55, // 23562: case 0x0: { |
| 11167 | OPC_SwitchField, 52, 3, // 23564: switch Inst[54:52] { |
| 11168 | 0, 22, // 23567: case 0x0: { |
| 11169 | OPC_CheckField, 0, 8, 0, // 23569: check Inst[7:0] == 0x0 |
| 11170 | OPC_CheckField, 32, 15, 0, // 23573: check Inst[46:32] == 0x0 |
| 11171 | OPC_Scope, 8, // 23577: try { |
| 11172 | OPC_CheckField, 48, 4, 0, // 23579: check Inst[51:48] == 0x0 |
| 11173 | OPC_Decode, 200, 65, 121, // 23583: decode to VMRGvv using decoder 121 |
| 11174 | // 23583: } else try { |
| 11175 | OPC_Decode, 206, 65, 122, // 23587: decode to VMRGvvm using decoder 122 |
| 11176 | // 23587: } |
| 11177 | // 23587: } |
| 11178 | 2, 0, // 23591: case 0x2: { |
| 11179 | OPC_CheckField, 0, 8, 0, // 23593: check Inst[7:0] == 0x0 |
| 11180 | OPC_CheckField, 16, 8, 0, // 23597: check Inst[23:16] == 0x0 |
| 11181 | OPC_CheckField, 32, 8, 0, // 23601: check Inst[39:32] == 0x0 |
| 11182 | OPC_Scope, 8, // 23605: try { |
| 11183 | OPC_CheckField, 48, 4, 0, // 23607: check Inst[51:48] == 0x0 |
| 11184 | OPC_Decode, 176, 65, 123, // 23611: decode to VMRGiv using decoder 123 |
| 11185 | // 23611: } else try { |
| 11186 | OPC_Decode, 182, 65, 124, // 23615: decode to VMRGivm using decoder 124 |
| 11187 | // 23615: } |
| 11188 | // 23615: } |
| 11189 | // 23615: } // switch Inst[54:52] |
| 11190 | // 23615: } |
| 11191 | 1, 0, // 23619: case 0x1: { |
| 11192 | OPC_CheckField, 0, 8, 0, // 23621: check Inst[7:0] == 0x0 |
| 11193 | OPC_CheckField, 16, 8, 0, // 23625: check Inst[23:16] == 0x0 |
| 11194 | OPC_CheckField, 32, 8, 0, // 23629: check Inst[39:32] == 0x0 |
| 11195 | OPC_CheckField, 52, 3, 2, // 23633: check Inst[54:52] == 0x2 |
| 11196 | OPC_Scope, 8, // 23637: try { |
| 11197 | OPC_CheckField, 48, 4, 0, // 23639: check Inst[51:48] == 0x0 |
| 11198 | OPC_Decode, 188, 65, 127, // 23643: decode to VMRGrv using decoder 127 |
| 11199 | // 23643: } else try { |
| 11200 | OPC_Decode, 194, 65, 128, 1, // 23647: decode to VMRGrvm using decoder 128 |
| 11201 | // 23647: } |
| 11202 | // 23647: } |
| 11203 | // 23647: } // switch Inst[47] |
| 11204 | // 23647: } |
| 11205 | 173, 3, 95, // 23652: case 0x1ad: { |
| 11206 | OPC_SwitchField, 47, 1, // 23655: switch Inst[47] { |
| 11207 | 0, 57, // 23658: case 0x0: { |
| 11208 | OPC_SwitchField, 52, 3, // 23660: switch Inst[54:52] { |
| 11209 | 0, 23, // 23663: case 0x0: { |
| 11210 | OPC_CheckField, 0, 8, 0, // 23665: check Inst[7:0] == 0x0 |
| 11211 | OPC_CheckField, 32, 15, 0, // 23669: check Inst[46:32] == 0x0 |
| 11212 | OPC_Scope, 8, // 23673: try { |
| 11213 | OPC_CheckField, 48, 4, 0, // 23675: check Inst[51:48] == 0x0 |
| 11214 | OPC_Decode, 164, 65, 121, // 23679: decode to VMRGWvv using decoder 121 |
| 11215 | // 23679: } else try { |
| 11216 | OPC_Decode, 170, 65, 129, 1, // 23683: decode to VMRGWvvm using decoder 129 |
| 11217 | // 23683: } |
| 11218 | // 23683: } |
| 11219 | 2, 0, // 23688: case 0x2: { |
| 11220 | OPC_CheckField, 0, 8, 0, // 23690: check Inst[7:0] == 0x0 |
| 11221 | OPC_CheckField, 16, 8, 0, // 23694: check Inst[23:16] == 0x0 |
| 11222 | OPC_CheckField, 32, 8, 0, // 23698: check Inst[39:32] == 0x0 |
| 11223 | OPC_Scope, 8, // 23702: try { |
| 11224 | OPC_CheckField, 48, 4, 0, // 23704: check Inst[51:48] == 0x0 |
| 11225 | OPC_Decode, 140, 65, 123, // 23708: decode to VMRGWiv using decoder 123 |
| 11226 | // 23708: } else try { |
| 11227 | OPC_Decode, 146, 65, 130, 1, // 23712: decode to VMRGWivm using decoder 130 |
| 11228 | // 23712: } |
| 11229 | // 23712: } |
| 11230 | // 23712: } // switch Inst[54:52] |
| 11231 | // 23712: } |
| 11232 | 1, 0, // 23717: case 0x1: { |
| 11233 | OPC_CheckField, 0, 8, 0, // 23719: check Inst[7:0] == 0x0 |
| 11234 | OPC_CheckField, 16, 8, 0, // 23723: check Inst[23:16] == 0x0 |
| 11235 | OPC_CheckField, 32, 8, 0, // 23727: check Inst[39:32] == 0x0 |
| 11236 | OPC_CheckField, 52, 3, 2, // 23731: check Inst[54:52] == 0x2 |
| 11237 | OPC_Scope, 8, // 23735: try { |
| 11238 | OPC_CheckField, 48, 4, 0, // 23737: check Inst[51:48] == 0x0 |
| 11239 | OPC_Decode, 152, 65, 127, // 23741: decode to VMRGWrv using decoder 127 |
| 11240 | // 23741: } else try { |
| 11241 | OPC_Decode, 158, 65, 131, 1, // 23745: decode to VMRGWrvm using decoder 131 |
| 11242 | // 23745: } |
| 11243 | // 23745: } |
| 11244 | // 23745: } // switch Inst[47] |
| 11245 | // 23745: } |
| 11246 | 174, 3, 133, 1, // 23750: case 0x1ae: { |
| 11247 | OPC_SwitchField, 39, 1, // 23754: switch Inst[39] { |
| 11248 | 0, 63, // 23757: case 0x0: { |
| 11249 | OPC_SwitchField, 47, 1, // 23759: switch Inst[47] { |
| 11250 | 0, 28, // 23762: case 0x0: { |
| 11251 | OPC_CheckField, 0, 8, 0, // 23764: check Inst[7:0] == 0x0 |
| 11252 | OPC_CheckField, 16, 8, 0, // 23768: check Inst[23:16] == 0x0 |
| 11253 | OPC_CheckField, 52, 3, 0, // 23772: check Inst[54:52] == 0x0 |
| 11254 | OPC_Scope, 9, // 23776: try { |
| 11255 | OPC_CheckField, 48, 4, 0, // 23778: check Inst[51:48] == 0x0 |
| 11256 | OPC_Decode, 188, 74, 223, 1, // 23782: decode to VSFAvim using decoder 223 |
| 11257 | // 23782: } else try { |
| 11258 | OPC_Decode, 194, 74, 224, 1, // 23787: decode to VSFAvimm using decoder 224 |
| 11259 | // 23787: } |
| 11260 | // 23787: } |
| 11261 | 1, 0, // 23792: case 0x1: { |
| 11262 | OPC_CheckField, 0, 8, 0, // 23794: check Inst[7:0] == 0x0 |
| 11263 | OPC_CheckField, 16, 8, 0, // 23798: check Inst[23:16] == 0x0 |
| 11264 | OPC_CheckField, 52, 3, 0, // 23802: check Inst[54:52] == 0x0 |
| 11265 | OPC_Scope, 9, // 23806: try { |
| 11266 | OPC_CheckField, 48, 4, 0, // 23808: check Inst[51:48] == 0x0 |
| 11267 | OPC_Decode, 212, 74, 225, 1, // 23812: decode to VSFAvrm using decoder 225 |
| 11268 | // 23812: } else try { |
| 11269 | OPC_Decode, 218, 74, 226, 1, // 23817: decode to VSFAvrmm using decoder 226 |
| 11270 | // 23817: } |
| 11271 | // 23817: } |
| 11272 | // 23817: } // switch Inst[47] |
| 11273 | // 23817: } |
| 11274 | 1, 0, // 23822: case 0x1: { |
| 11275 | OPC_SwitchField, 47, 1, // 23824: switch Inst[47] { |
| 11276 | 0, 28, // 23827: case 0x0: { |
| 11277 | OPC_CheckField, 0, 8, 0, // 23829: check Inst[7:0] == 0x0 |
| 11278 | OPC_CheckField, 16, 8, 0, // 23833: check Inst[23:16] == 0x0 |
| 11279 | OPC_CheckField, 52, 3, 0, // 23837: check Inst[54:52] == 0x0 |
| 11280 | OPC_Scope, 9, // 23841: try { |
| 11281 | OPC_CheckField, 48, 4, 0, // 23843: check Inst[51:48] == 0x0 |
| 11282 | OPC_Decode, 200, 74, 227, 1, // 23847: decode to VSFAvir using decoder 227 |
| 11283 | // 23847: } else try { |
| 11284 | OPC_Decode, 206, 74, 228, 1, // 23852: decode to VSFAvirm using decoder 228 |
| 11285 | // 23852: } |
| 11286 | // 23852: } |
| 11287 | 1, 0, // 23857: case 0x1: { |
| 11288 | OPC_CheckField, 0, 8, 0, // 23859: check Inst[7:0] == 0x0 |
| 11289 | OPC_CheckField, 16, 8, 0, // 23863: check Inst[23:16] == 0x0 |
| 11290 | OPC_CheckField, 52, 3, 0, // 23867: check Inst[54:52] == 0x0 |
| 11291 | OPC_Scope, 9, // 23871: try { |
| 11292 | OPC_CheckField, 48, 4, 0, // 23873: check Inst[51:48] == 0x0 |
| 11293 | OPC_Decode, 224, 74, 229, 1, // 23877: decode to VSFAvrr using decoder 229 |
| 11294 | // 23877: } else try { |
| 11295 | OPC_Decode, 230, 74, 230, 1, // 23882: decode to VSFAvrrm using decoder 230 |
| 11296 | // 23882: } |
| 11297 | // 23882: } |
| 11298 | // 23882: } // switch Inst[47] |
| 11299 | // 23882: } |
| 11300 | // 23882: } // switch Inst[39] |
| 11301 | // 23882: } |
| 11302 | 176, 3, 174, 1, // 23887: case 0x1b0: { |
| 11303 | OPC_SwitchField, 52, 3, // 23891: switch Inst[54:52] { |
| 11304 | 0, 22, // 23894: case 0x0: { |
| 11305 | OPC_CheckField, 0, 8, 0, // 23896: check Inst[7:0] == 0x0 |
| 11306 | OPC_CheckField, 32, 16, 0, // 23900: check Inst[47:32] == 0x0 |
| 11307 | OPC_Scope, 8, // 23904: try { |
| 11308 | OPC_CheckField, 48, 4, 0, // 23906: check Inst[51:48] == 0x0 |
| 11309 | OPC_Decode, 140, 83, 121, // 23910: decode to VSUBULvv using decoder 121 |
| 11310 | // 23910: } else try { |
| 11311 | OPC_Decode, 146, 83, 122, // 23914: decode to VSUBULvvm using decoder 122 |
| 11312 | // 23914: } |
| 11313 | // 23914: } |
| 11314 | 2, 60, // 23918: case 0x2: { |
| 11315 | OPC_SwitchField, 47, 1, // 23920: switch Inst[47] { |
| 11316 | 0, 26, // 23923: case 0x0: { |
| 11317 | OPC_CheckField, 0, 8, 0, // 23925: check Inst[7:0] == 0x0 |
| 11318 | OPC_CheckField, 16, 8, 0, // 23929: check Inst[23:16] == 0x0 |
| 11319 | OPC_CheckField, 32, 8, 0, // 23933: check Inst[39:32] == 0x0 |
| 11320 | OPC_Scope, 8, // 23937: try { |
| 11321 | OPC_CheckField, 48, 4, 0, // 23939: check Inst[51:48] == 0x0 |
| 11322 | OPC_Decode, 244, 82, 123, // 23943: decode to VSUBULiv using decoder 123 |
| 11323 | // 23943: } else try { |
| 11324 | OPC_Decode, 250, 82, 124, // 23947: decode to VSUBULivm using decoder 124 |
| 11325 | // 23947: } |
| 11326 | // 23947: } |
| 11327 | 1, 0, // 23951: case 0x1: { |
| 11328 | OPC_CheckField, 0, 8, 0, // 23953: check Inst[7:0] == 0x0 |
| 11329 | OPC_CheckField, 16, 8, 0, // 23957: check Inst[23:16] == 0x0 |
| 11330 | OPC_CheckField, 32, 8, 0, // 23961: check Inst[39:32] == 0x0 |
| 11331 | OPC_Scope, 8, // 23965: try { |
| 11332 | OPC_CheckField, 48, 4, 0, // 23967: check Inst[51:48] == 0x0 |
| 11333 | OPC_Decode, 128, 83, 127, // 23971: decode to VSUBULrv using decoder 127 |
| 11334 | // 23971: } else try { |
| 11335 | OPC_Decode, 134, 83, 128, 1, // 23975: decode to VSUBULrvm using decoder 128 |
| 11336 | // 23975: } |
| 11337 | // 23975: } |
| 11338 | // 23975: } // switch Inst[47] |
| 11339 | // 23975: } |
| 11340 | 4, 22, // 23980: case 0x4: { |
| 11341 | OPC_CheckField, 0, 8, 0, // 23982: check Inst[7:0] == 0x0 |
| 11342 | OPC_CheckField, 32, 16, 0, // 23986: check Inst[47:32] == 0x0 |
| 11343 | OPC_Scope, 8, // 23990: try { |
| 11344 | OPC_CheckField, 48, 4, 0, // 23992: check Inst[51:48] == 0x0 |
| 11345 | OPC_Decode, 163, 33, 121, // 23996: decode to PVSUBULOvv using decoder 121 |
| 11346 | // 23996: } else try { |
| 11347 | OPC_Decode, 169, 33, 122, // 24000: decode to PVSUBULOvvm using decoder 122 |
| 11348 | // 24000: } |
| 11349 | // 24000: } |
| 11350 | 6, 0, // 24004: case 0x6: { |
| 11351 | OPC_SwitchField, 47, 1, // 24006: switch Inst[47] { |
| 11352 | 0, 26, // 24009: case 0x0: { |
| 11353 | OPC_CheckField, 0, 8, 0, // 24011: check Inst[7:0] == 0x0 |
| 11354 | OPC_CheckField, 16, 8, 0, // 24015: check Inst[23:16] == 0x0 |
| 11355 | OPC_CheckField, 32, 8, 0, // 24019: check Inst[39:32] == 0x0 |
| 11356 | OPC_Scope, 8, // 24023: try { |
| 11357 | OPC_CheckField, 48, 4, 0, // 24025: check Inst[51:48] == 0x0 |
| 11358 | OPC_Decode, 139, 33, 123, // 24029: decode to PVSUBULOiv using decoder 123 |
| 11359 | // 24029: } else try { |
| 11360 | OPC_Decode, 145, 33, 124, // 24033: decode to PVSUBULOivm using decoder 124 |
| 11361 | // 24033: } |
| 11362 | // 24033: } |
| 11363 | 1, 0, // 24037: case 0x1: { |
| 11364 | OPC_CheckField, 0, 8, 0, // 24039: check Inst[7:0] == 0x0 |
| 11365 | OPC_CheckField, 16, 8, 0, // 24043: check Inst[23:16] == 0x0 |
| 11366 | OPC_CheckField, 32, 8, 0, // 24047: check Inst[39:32] == 0x0 |
| 11367 | OPC_Scope, 8, // 24051: try { |
| 11368 | OPC_CheckField, 48, 4, 0, // 24053: check Inst[51:48] == 0x0 |
| 11369 | OPC_Decode, 151, 33, 125, // 24057: decode to PVSUBULOrv using decoder 125 |
| 11370 | // 24057: } else try { |
| 11371 | OPC_Decode, 157, 33, 126, // 24061: decode to PVSUBULOrvm using decoder 126 |
| 11372 | // 24061: } |
| 11373 | // 24061: } |
| 11374 | // 24061: } // switch Inst[47] |
| 11375 | // 24061: } |
| 11376 | // 24061: } // switch Inst[54:52] |
| 11377 | // 24061: } |
| 11378 | 177, 3, 177, 1, // 24065: case 0x1b1: { |
| 11379 | OPC_SwitchField, 52, 3, // 24069: switch Inst[54:52] { |
| 11380 | 0, 22, // 24072: case 0x0: { |
| 11381 | OPC_CheckField, 0, 8, 0, // 24074: check Inst[7:0] == 0x0 |
| 11382 | OPC_CheckField, 32, 16, 0, // 24078: check Inst[47:32] == 0x0 |
| 11383 | OPC_Scope, 8, // 24082: try { |
| 11384 | OPC_CheckField, 48, 4, 0, // 24084: check Inst[51:48] == 0x0 |
| 11385 | OPC_Decode, 199, 33, 121, // 24088: decode to PVSUBUUPvv using decoder 121 |
| 11386 | // 24088: } else try { |
| 11387 | OPC_Decode, 205, 33, 122, // 24092: decode to PVSUBUUPvvm using decoder 122 |
| 11388 | // 24092: } |
| 11389 | // 24092: } |
| 11390 | 2, 60, // 24096: case 0x2: { |
| 11391 | OPC_SwitchField, 47, 1, // 24098: switch Inst[47] { |
| 11392 | 0, 26, // 24101: case 0x0: { |
| 11393 | OPC_CheckField, 0, 8, 0, // 24103: check Inst[7:0] == 0x0 |
| 11394 | OPC_CheckField, 16, 8, 0, // 24107: check Inst[23:16] == 0x0 |
| 11395 | OPC_CheckField, 32, 8, 0, // 24111: check Inst[39:32] == 0x0 |
| 11396 | OPC_Scope, 8, // 24115: try { |
| 11397 | OPC_CheckField, 48, 4, 0, // 24117: check Inst[51:48] == 0x0 |
| 11398 | OPC_Decode, 175, 33, 123, // 24121: decode to PVSUBUUPiv using decoder 123 |
| 11399 | // 24121: } else try { |
| 11400 | OPC_Decode, 181, 33, 124, // 24125: decode to PVSUBUUPivm using decoder 124 |
| 11401 | // 24125: } |
| 11402 | // 24125: } |
| 11403 | 1, 0, // 24129: case 0x1: { |
| 11404 | OPC_CheckField, 0, 8, 0, // 24131: check Inst[7:0] == 0x0 |
| 11405 | OPC_CheckField, 16, 8, 0, // 24135: check Inst[23:16] == 0x0 |
| 11406 | OPC_CheckField, 32, 8, 0, // 24139: check Inst[39:32] == 0x0 |
| 11407 | OPC_Scope, 8, // 24143: try { |
| 11408 | OPC_CheckField, 48, 4, 0, // 24145: check Inst[51:48] == 0x0 |
| 11409 | OPC_Decode, 187, 33, 127, // 24149: decode to PVSUBUUPrv using decoder 127 |
| 11410 | // 24149: } else try { |
| 11411 | OPC_Decode, 193, 33, 128, 1, // 24153: decode to PVSUBUUPrvm using decoder 128 |
| 11412 | // 24153: } |
| 11413 | // 24153: } |
| 11414 | // 24153: } // switch Inst[47] |
| 11415 | // 24153: } |
| 11416 | 4, 23, // 24158: case 0x4: { |
| 11417 | OPC_CheckField, 0, 8, 0, // 24160: check Inst[7:0] == 0x0 |
| 11418 | OPC_CheckField, 32, 16, 0, // 24164: check Inst[47:32] == 0x0 |
| 11419 | OPC_Scope, 8, // 24168: try { |
| 11420 | OPC_CheckField, 48, 4, 0, // 24170: check Inst[51:48] == 0x0 |
| 11421 | OPC_Decode, 235, 33, 121, // 24174: decode to PVSUBUvv using decoder 121 |
| 11422 | // 24174: } else try { |
| 11423 | OPC_Decode, 241, 33, 129, 1, // 24178: decode to PVSUBUvvm using decoder 129 |
| 11424 | // 24178: } |
| 11425 | // 24178: } |
| 11426 | 6, 0, // 24183: case 0x6: { |
| 11427 | OPC_SwitchField, 47, 1, // 24185: switch Inst[47] { |
| 11428 | 0, 27, // 24188: case 0x0: { |
| 11429 | OPC_CheckField, 0, 8, 0, // 24190: check Inst[7:0] == 0x0 |
| 11430 | OPC_CheckField, 16, 8, 0, // 24194: check Inst[23:16] == 0x0 |
| 11431 | OPC_CheckField, 32, 8, 0, // 24198: check Inst[39:32] == 0x0 |
| 11432 | OPC_Scope, 8, // 24202: try { |
| 11433 | OPC_CheckField, 48, 4, 0, // 24204: check Inst[51:48] == 0x0 |
| 11434 | OPC_Decode, 211, 33, 123, // 24208: decode to PVSUBUiv using decoder 123 |
| 11435 | // 24208: } else try { |
| 11436 | OPC_Decode, 217, 33, 130, 1, // 24212: decode to PVSUBUivm using decoder 130 |
| 11437 | // 24212: } |
| 11438 | // 24212: } |
| 11439 | 1, 0, // 24217: case 0x1: { |
| 11440 | OPC_CheckField, 0, 8, 0, // 24219: check Inst[7:0] == 0x0 |
| 11441 | OPC_CheckField, 16, 8, 0, // 24223: check Inst[23:16] == 0x0 |
| 11442 | OPC_CheckField, 32, 8, 0, // 24227: check Inst[39:32] == 0x0 |
| 11443 | OPC_Scope, 8, // 24231: try { |
| 11444 | OPC_CheckField, 48, 4, 0, // 24233: check Inst[51:48] == 0x0 |
| 11445 | OPC_Decode, 223, 33, 127, // 24237: decode to PVSUBUrv using decoder 127 |
| 11446 | // 24237: } else try { |
| 11447 | OPC_Decode, 229, 33, 131, 1, // 24241: decode to PVSUBUrvm using decoder 131 |
| 11448 | // 24241: } |
| 11449 | // 24241: } |
| 11450 | // 24241: } // switch Inst[47] |
| 11451 | // 24241: } |
| 11452 | // 24241: } // switch Inst[54:52] |
| 11453 | // 24241: } |
| 11454 | 178, 3, 92, // 24246: case 0x1b2: { |
| 11455 | OPC_SwitchField, 47, 1, // 24249: switch Inst[47] { |
| 11456 | 0, 55, // 24252: case 0x0: { |
| 11457 | OPC_SwitchField, 52, 3, // 24254: switch Inst[54:52] { |
| 11458 | 0, 22, // 24257: case 0x0: { |
| 11459 | OPC_CheckField, 0, 8, 0, // 24259: check Inst[7:0] == 0x0 |
| 11460 | OPC_CheckField, 32, 15, 0, // 24263: check Inst[46:32] == 0x0 |
| 11461 | OPC_Scope, 8, // 24267: try { |
| 11462 | OPC_CheckField, 48, 4, 0, // 24269: check Inst[51:48] == 0x0 |
| 11463 | OPC_Decode, 236, 65, 121, // 24273: decode to VMULSLWvv using decoder 121 |
| 11464 | // 24273: } else try { |
| 11465 | OPC_Decode, 242, 65, 122, // 24277: decode to VMULSLWvvm using decoder 122 |
| 11466 | // 24277: } |
| 11467 | // 24277: } |
| 11468 | 2, 0, // 24281: case 0x2: { |
| 11469 | OPC_CheckField, 0, 8, 0, // 24283: check Inst[7:0] == 0x0 |
| 11470 | OPC_CheckField, 16, 8, 0, // 24287: check Inst[23:16] == 0x0 |
| 11471 | OPC_CheckField, 32, 8, 0, // 24291: check Inst[39:32] == 0x0 |
| 11472 | OPC_Scope, 8, // 24295: try { |
| 11473 | OPC_CheckField, 48, 4, 0, // 24297: check Inst[51:48] == 0x0 |
| 11474 | OPC_Decode, 212, 65, 123, // 24301: decode to VMULSLWiv using decoder 123 |
| 11475 | // 24301: } else try { |
| 11476 | OPC_Decode, 218, 65, 124, // 24305: decode to VMULSLWivm using decoder 124 |
| 11477 | // 24305: } |
| 11478 | // 24305: } |
| 11479 | // 24305: } // switch Inst[54:52] |
| 11480 | // 24305: } |
| 11481 | 1, 0, // 24309: case 0x1: { |
| 11482 | OPC_CheckField, 0, 8, 0, // 24311: check Inst[7:0] == 0x0 |
| 11483 | OPC_CheckField, 16, 8, 0, // 24315: check Inst[23:16] == 0x0 |
| 11484 | OPC_CheckField, 32, 8, 0, // 24319: check Inst[39:32] == 0x0 |
| 11485 | OPC_CheckField, 52, 3, 2, // 24323: check Inst[54:52] == 0x2 |
| 11486 | OPC_Scope, 8, // 24327: try { |
| 11487 | OPC_CheckField, 48, 4, 0, // 24329: check Inst[51:48] == 0x0 |
| 11488 | OPC_Decode, 224, 65, 125, // 24333: decode to VMULSLWrv using decoder 125 |
| 11489 | // 24333: } else try { |
| 11490 | OPC_Decode, 230, 65, 126, // 24337: decode to VMULSLWrvm using decoder 126 |
| 11491 | // 24337: } |
| 11492 | // 24337: } |
| 11493 | // 24337: } // switch Inst[47] |
| 11494 | // 24337: } |
| 11495 | 180, 3, 173, 1, // 24341: case 0x1b4: { |
| 11496 | OPC_SwitchField, 52, 3, // 24345: switch Inst[54:52] { |
| 11497 | 0, 22, // 24348: case 0x0: { |
| 11498 | OPC_CheckField, 0, 8, 0, // 24350: check Inst[7:0] == 0x0 |
| 11499 | OPC_CheckField, 32, 16, 0, // 24354: check Inst[47:32] == 0x0 |
| 11500 | OPC_Scope, 8, // 24358: try { |
| 11501 | OPC_CheckField, 48, 4, 0, // 24360: check Inst[51:48] == 0x0 |
| 11502 | OPC_Decode, 196, 82, 121, // 24364: decode to VSUBSWSXvv using decoder 121 |
| 11503 | // 24364: } else try { |
| 11504 | OPC_Decode, 202, 82, 122, // 24368: decode to VSUBSWSXvvm using decoder 122 |
| 11505 | // 24368: } |
| 11506 | // 24368: } |
| 11507 | 2, 59, // 24372: case 0x2: { |
| 11508 | OPC_SwitchField, 47, 1, // 24374: switch Inst[47] { |
| 11509 | 0, 26, // 24377: case 0x0: { |
| 11510 | OPC_CheckField, 0, 8, 0, // 24379: check Inst[7:0] == 0x0 |
| 11511 | OPC_CheckField, 16, 8, 0, // 24383: check Inst[23:16] == 0x0 |
| 11512 | OPC_CheckField, 32, 8, 0, // 24387: check Inst[39:32] == 0x0 |
| 11513 | OPC_Scope, 8, // 24391: try { |
| 11514 | OPC_CheckField, 48, 4, 0, // 24393: check Inst[51:48] == 0x0 |
| 11515 | OPC_Decode, 172, 82, 123, // 24397: decode to VSUBSWSXiv using decoder 123 |
| 11516 | // 24397: } else try { |
| 11517 | OPC_Decode, 178, 82, 124, // 24401: decode to VSUBSWSXivm using decoder 124 |
| 11518 | // 24401: } |
| 11519 | // 24401: } |
| 11520 | 1, 0, // 24405: case 0x1: { |
| 11521 | OPC_CheckField, 0, 8, 0, // 24407: check Inst[7:0] == 0x0 |
| 11522 | OPC_CheckField, 16, 8, 0, // 24411: check Inst[23:16] == 0x0 |
| 11523 | OPC_CheckField, 32, 8, 0, // 24415: check Inst[39:32] == 0x0 |
| 11524 | OPC_Scope, 8, // 24419: try { |
| 11525 | OPC_CheckField, 48, 4, 0, // 24421: check Inst[51:48] == 0x0 |
| 11526 | OPC_Decode, 184, 82, 125, // 24425: decode to VSUBSWSXrv using decoder 125 |
| 11527 | // 24425: } else try { |
| 11528 | OPC_Decode, 190, 82, 126, // 24429: decode to VSUBSWSXrvm using decoder 126 |
| 11529 | // 24429: } |
| 11530 | // 24429: } |
| 11531 | // 24429: } // switch Inst[47] |
| 11532 | // 24429: } |
| 11533 | 4, 22, // 24433: case 0x4: { |
| 11534 | OPC_CheckField, 0, 8, 0, // 24435: check Inst[7:0] == 0x0 |
| 11535 | OPC_CheckField, 32, 16, 0, // 24439: check Inst[47:32] == 0x0 |
| 11536 | OPC_Scope, 8, // 24443: try { |
| 11537 | OPC_CheckField, 48, 4, 0, // 24445: check Inst[51:48] == 0x0 |
| 11538 | OPC_Decode, 183, 32, 121, // 24449: decode to PVSUBSLOvv using decoder 121 |
| 11539 | // 24449: } else try { |
| 11540 | OPC_Decode, 189, 32, 122, // 24453: decode to PVSUBSLOvvm using decoder 122 |
| 11541 | // 24453: } |
| 11542 | // 24453: } |
| 11543 | 6, 0, // 24457: case 0x6: { |
| 11544 | OPC_SwitchField, 47, 1, // 24459: switch Inst[47] { |
| 11545 | 0, 26, // 24462: case 0x0: { |
| 11546 | OPC_CheckField, 0, 8, 0, // 24464: check Inst[7:0] == 0x0 |
| 11547 | OPC_CheckField, 16, 8, 0, // 24468: check Inst[23:16] == 0x0 |
| 11548 | OPC_CheckField, 32, 8, 0, // 24472: check Inst[39:32] == 0x0 |
| 11549 | OPC_Scope, 8, // 24476: try { |
| 11550 | OPC_CheckField, 48, 4, 0, // 24478: check Inst[51:48] == 0x0 |
| 11551 | OPC_Decode, 159, 32, 123, // 24482: decode to PVSUBSLOiv using decoder 123 |
| 11552 | // 24482: } else try { |
| 11553 | OPC_Decode, 165, 32, 124, // 24486: decode to PVSUBSLOivm using decoder 124 |
| 11554 | // 24486: } |
| 11555 | // 24486: } |
| 11556 | 1, 0, // 24490: case 0x1: { |
| 11557 | OPC_CheckField, 0, 8, 0, // 24492: check Inst[7:0] == 0x0 |
| 11558 | OPC_CheckField, 16, 8, 0, // 24496: check Inst[23:16] == 0x0 |
| 11559 | OPC_CheckField, 32, 8, 0, // 24500: check Inst[39:32] == 0x0 |
| 11560 | OPC_Scope, 8, // 24504: try { |
| 11561 | OPC_CheckField, 48, 4, 0, // 24506: check Inst[51:48] == 0x0 |
| 11562 | OPC_Decode, 171, 32, 125, // 24510: decode to PVSUBSLOrv using decoder 125 |
| 11563 | // 24510: } else try { |
| 11564 | OPC_Decode, 177, 32, 126, // 24514: decode to PVSUBSLOrvm using decoder 126 |
| 11565 | // 24514: } |
| 11566 | // 24514: } |
| 11567 | // 24514: } // switch Inst[47] |
| 11568 | // 24514: } |
| 11569 | // 24514: } // switch Inst[54:52] |
| 11570 | // 24514: } |
| 11571 | 181, 3, 177, 1, // 24518: case 0x1b5: { |
| 11572 | OPC_SwitchField, 52, 3, // 24522: switch Inst[54:52] { |
| 11573 | 0, 22, // 24525: case 0x0: { |
| 11574 | OPC_CheckField, 0, 8, 0, // 24527: check Inst[7:0] == 0x0 |
| 11575 | OPC_CheckField, 32, 16, 0, // 24531: check Inst[47:32] == 0x0 |
| 11576 | OPC_Scope, 8, // 24535: try { |
| 11577 | OPC_CheckField, 48, 4, 0, // 24537: check Inst[51:48] == 0x0 |
| 11578 | OPC_Decode, 219, 32, 121, // 24541: decode to PVSUBSUPvv using decoder 121 |
| 11579 | // 24541: } else try { |
| 11580 | OPC_Decode, 225, 32, 122, // 24545: decode to PVSUBSUPvvm using decoder 122 |
| 11581 | // 24545: } |
| 11582 | // 24545: } |
| 11583 | 2, 60, // 24549: case 0x2: { |
| 11584 | OPC_SwitchField, 47, 1, // 24551: switch Inst[47] { |
| 11585 | 0, 26, // 24554: case 0x0: { |
| 11586 | OPC_CheckField, 0, 8, 0, // 24556: check Inst[7:0] == 0x0 |
| 11587 | OPC_CheckField, 16, 8, 0, // 24560: check Inst[23:16] == 0x0 |
| 11588 | OPC_CheckField, 32, 8, 0, // 24564: check Inst[39:32] == 0x0 |
| 11589 | OPC_Scope, 8, // 24568: try { |
| 11590 | OPC_CheckField, 48, 4, 0, // 24570: check Inst[51:48] == 0x0 |
| 11591 | OPC_Decode, 195, 32, 123, // 24574: decode to PVSUBSUPiv using decoder 123 |
| 11592 | // 24574: } else try { |
| 11593 | OPC_Decode, 201, 32, 124, // 24578: decode to PVSUBSUPivm using decoder 124 |
| 11594 | // 24578: } |
| 11595 | // 24578: } |
| 11596 | 1, 0, // 24582: case 0x1: { |
| 11597 | OPC_CheckField, 0, 8, 0, // 24584: check Inst[7:0] == 0x0 |
| 11598 | OPC_CheckField, 16, 8, 0, // 24588: check Inst[23:16] == 0x0 |
| 11599 | OPC_CheckField, 32, 8, 0, // 24592: check Inst[39:32] == 0x0 |
| 11600 | OPC_Scope, 8, // 24596: try { |
| 11601 | OPC_CheckField, 48, 4, 0, // 24598: check Inst[51:48] == 0x0 |
| 11602 | OPC_Decode, 207, 32, 127, // 24602: decode to PVSUBSUPrv using decoder 127 |
| 11603 | // 24602: } else try { |
| 11604 | OPC_Decode, 213, 32, 128, 1, // 24606: decode to PVSUBSUPrvm using decoder 128 |
| 11605 | // 24606: } |
| 11606 | // 24606: } |
| 11607 | // 24606: } // switch Inst[47] |
| 11608 | // 24606: } |
| 11609 | 4, 23, // 24611: case 0x4: { |
| 11610 | OPC_CheckField, 0, 8, 0, // 24613: check Inst[7:0] == 0x0 |
| 11611 | OPC_CheckField, 32, 16, 0, // 24617: check Inst[47:32] == 0x0 |
| 11612 | OPC_Scope, 8, // 24621: try { |
| 11613 | OPC_CheckField, 48, 4, 0, // 24623: check Inst[51:48] == 0x0 |
| 11614 | OPC_Decode, 255, 32, 121, // 24627: decode to PVSUBSvv using decoder 121 |
| 11615 | // 24627: } else try { |
| 11616 | OPC_Decode, 133, 33, 129, 1, // 24631: decode to PVSUBSvvm using decoder 129 |
| 11617 | // 24631: } |
| 11618 | // 24631: } |
| 11619 | 6, 0, // 24636: case 0x6: { |
| 11620 | OPC_SwitchField, 47, 1, // 24638: switch Inst[47] { |
| 11621 | 0, 27, // 24641: case 0x0: { |
| 11622 | OPC_CheckField, 0, 8, 0, // 24643: check Inst[7:0] == 0x0 |
| 11623 | OPC_CheckField, 16, 8, 0, // 24647: check Inst[23:16] == 0x0 |
| 11624 | OPC_CheckField, 32, 8, 0, // 24651: check Inst[39:32] == 0x0 |
| 11625 | OPC_Scope, 8, // 24655: try { |
| 11626 | OPC_CheckField, 48, 4, 0, // 24657: check Inst[51:48] == 0x0 |
| 11627 | OPC_Decode, 231, 32, 123, // 24661: decode to PVSUBSiv using decoder 123 |
| 11628 | // 24661: } else try { |
| 11629 | OPC_Decode, 237, 32, 130, 1, // 24665: decode to PVSUBSivm using decoder 130 |
| 11630 | // 24665: } |
| 11631 | // 24665: } |
| 11632 | 1, 0, // 24670: case 0x1: { |
| 11633 | OPC_CheckField, 0, 8, 0, // 24672: check Inst[7:0] == 0x0 |
| 11634 | OPC_CheckField, 16, 8, 0, // 24676: check Inst[23:16] == 0x0 |
| 11635 | OPC_CheckField, 32, 8, 0, // 24680: check Inst[39:32] == 0x0 |
| 11636 | OPC_Scope, 8, // 24684: try { |
| 11637 | OPC_CheckField, 48, 4, 0, // 24686: check Inst[51:48] == 0x0 |
| 11638 | OPC_Decode, 243, 32, 127, // 24690: decode to PVSUBSrv using decoder 127 |
| 11639 | // 24690: } else try { |
| 11640 | OPC_Decode, 249, 32, 131, 1, // 24694: decode to PVSUBSrvm using decoder 131 |
| 11641 | // 24694: } |
| 11642 | // 24694: } |
| 11643 | // 24694: } // switch Inst[47] |
| 11644 | // 24694: } |
| 11645 | // 24694: } // switch Inst[54:52] |
| 11646 | // 24694: } |
| 11647 | 182, 3, 93, // 24699: case 0x1b6: { |
| 11648 | OPC_SwitchField, 47, 1, // 24702: switch Inst[47] { |
| 11649 | 0, 55, // 24705: case 0x0: { |
| 11650 | OPC_SwitchField, 52, 3, // 24707: switch Inst[54:52] { |
| 11651 | 0, 22, // 24710: case 0x0: { |
| 11652 | OPC_CheckField, 0, 8, 0, // 24712: check Inst[7:0] == 0x0 |
| 11653 | OPC_CheckField, 32, 15, 0, // 24716: check Inst[46:32] == 0x0 |
| 11654 | OPC_Scope, 8, // 24720: try { |
| 11655 | OPC_CheckField, 48, 4, 0, // 24722: check Inst[51:48] == 0x0 |
| 11656 | OPC_Decode, 144, 66, 121, // 24726: decode to VMULSLvv using decoder 121 |
| 11657 | // 24726: } else try { |
| 11658 | OPC_Decode, 150, 66, 122, // 24730: decode to VMULSLvvm using decoder 122 |
| 11659 | // 24730: } |
| 11660 | // 24730: } |
| 11661 | 2, 0, // 24734: case 0x2: { |
| 11662 | OPC_CheckField, 0, 8, 0, // 24736: check Inst[7:0] == 0x0 |
| 11663 | OPC_CheckField, 16, 8, 0, // 24740: check Inst[23:16] == 0x0 |
| 11664 | OPC_CheckField, 32, 8, 0, // 24744: check Inst[39:32] == 0x0 |
| 11665 | OPC_Scope, 8, // 24748: try { |
| 11666 | OPC_CheckField, 48, 4, 0, // 24750: check Inst[51:48] == 0x0 |
| 11667 | OPC_Decode, 248, 65, 123, // 24754: decode to VMULSLiv using decoder 123 |
| 11668 | // 24754: } else try { |
| 11669 | OPC_Decode, 254, 65, 124, // 24758: decode to VMULSLivm using decoder 124 |
| 11670 | // 24758: } |
| 11671 | // 24758: } |
| 11672 | // 24758: } // switch Inst[54:52] |
| 11673 | // 24758: } |
| 11674 | 1, 0, // 24762: case 0x1: { |
| 11675 | OPC_CheckField, 0, 8, 0, // 24764: check Inst[7:0] == 0x0 |
| 11676 | OPC_CheckField, 16, 8, 0, // 24768: check Inst[23:16] == 0x0 |
| 11677 | OPC_CheckField, 32, 8, 0, // 24772: check Inst[39:32] == 0x0 |
| 11678 | OPC_CheckField, 52, 3, 2, // 24776: check Inst[54:52] == 0x2 |
| 11679 | OPC_Scope, 8, // 24780: try { |
| 11680 | OPC_CheckField, 48, 4, 0, // 24782: check Inst[51:48] == 0x0 |
| 11681 | OPC_Decode, 132, 66, 127, // 24786: decode to VMULSLrv using decoder 127 |
| 11682 | // 24786: } else try { |
| 11683 | OPC_Decode, 138, 66, 128, 1, // 24790: decode to VMULSLrvm using decoder 128 |
| 11684 | // 24790: } |
| 11685 | // 24790: } |
| 11686 | // 24790: } // switch Inst[47] |
| 11687 | // 24790: } |
| 11688 | 184, 3, 175, 1, // 24795: case 0x1b8: { |
| 11689 | OPC_SwitchField, 52, 3, // 24799: switch Inst[54:52] { |
| 11690 | 0, 22, // 24802: case 0x0: { |
| 11691 | OPC_CheckField, 0, 8, 0, // 24804: check Inst[7:0] == 0x0 |
| 11692 | OPC_CheckField, 32, 16, 0, // 24808: check Inst[47:32] == 0x0 |
| 11693 | OPC_Scope, 8, // 24812: try { |
| 11694 | OPC_CheckField, 48, 4, 0, // 24814: check Inst[51:48] == 0x0 |
| 11695 | OPC_Decode, 224, 53, 121, // 24818: decode to VFSUBDvv using decoder 121 |
| 11696 | // 24818: } else try { |
| 11697 | OPC_Decode, 230, 53, 122, // 24822: decode to VFSUBDvvm using decoder 122 |
| 11698 | // 24822: } |
| 11699 | // 24822: } |
| 11700 | 2, 60, // 24826: case 0x2: { |
| 11701 | OPC_SwitchField, 47, 1, // 24828: switch Inst[47] { |
| 11702 | 0, 26, // 24831: case 0x0: { |
| 11703 | OPC_CheckField, 0, 8, 0, // 24833: check Inst[7:0] == 0x0 |
| 11704 | OPC_CheckField, 16, 8, 0, // 24837: check Inst[23:16] == 0x0 |
| 11705 | OPC_CheckField, 32, 8, 0, // 24841: check Inst[39:32] == 0x0 |
| 11706 | OPC_Scope, 8, // 24845: try { |
| 11707 | OPC_CheckField, 48, 4, 0, // 24847: check Inst[51:48] == 0x0 |
| 11708 | OPC_Decode, 200, 53, 123, // 24851: decode to VFSUBDiv using decoder 123 |
| 11709 | // 24851: } else try { |
| 11710 | OPC_Decode, 206, 53, 124, // 24855: decode to VFSUBDivm using decoder 124 |
| 11711 | // 24855: } |
| 11712 | // 24855: } |
| 11713 | 1, 0, // 24859: case 0x1: { |
| 11714 | OPC_CheckField, 0, 8, 0, // 24861: check Inst[7:0] == 0x0 |
| 11715 | OPC_CheckField, 16, 8, 0, // 24865: check Inst[23:16] == 0x0 |
| 11716 | OPC_CheckField, 32, 8, 0, // 24869: check Inst[39:32] == 0x0 |
| 11717 | OPC_Scope, 8, // 24873: try { |
| 11718 | OPC_CheckField, 48, 4, 0, // 24875: check Inst[51:48] == 0x0 |
| 11719 | OPC_Decode, 212, 53, 127, // 24879: decode to VFSUBDrv using decoder 127 |
| 11720 | // 24879: } else try { |
| 11721 | OPC_Decode, 218, 53, 128, 1, // 24883: decode to VFSUBDrvm using decoder 128 |
| 11722 | // 24883: } |
| 11723 | // 24883: } |
| 11724 | // 24883: } // switch Inst[47] |
| 11725 | // 24883: } |
| 11726 | 4, 22, // 24888: case 0x4: { |
| 11727 | OPC_CheckField, 0, 8, 0, // 24890: check Inst[7:0] == 0x0 |
| 11728 | OPC_CheckField, 32, 16, 0, // 24894: check Inst[47:32] == 0x0 |
| 11729 | OPC_Scope, 8, // 24898: try { |
| 11730 | OPC_CheckField, 48, 4, 0, // 24900: check Inst[51:48] == 0x0 |
| 11731 | OPC_Decode, 255, 23, 121, // 24904: decode to PVFSUBLOvv using decoder 121 |
| 11732 | // 24904: } else try { |
| 11733 | OPC_Decode, 133, 24, 122, // 24908: decode to PVFSUBLOvvm using decoder 122 |
| 11734 | // 24908: } |
| 11735 | // 24908: } |
| 11736 | 6, 0, // 24912: case 0x6: { |
| 11737 | OPC_SwitchField, 47, 1, // 24914: switch Inst[47] { |
| 11738 | 0, 26, // 24917: case 0x0: { |
| 11739 | OPC_CheckField, 0, 8, 0, // 24919: check Inst[7:0] == 0x0 |
| 11740 | OPC_CheckField, 16, 8, 0, // 24923: check Inst[23:16] == 0x0 |
| 11741 | OPC_CheckField, 32, 8, 0, // 24927: check Inst[39:32] == 0x0 |
| 11742 | OPC_Scope, 8, // 24931: try { |
| 11743 | OPC_CheckField, 48, 4, 0, // 24933: check Inst[51:48] == 0x0 |
| 11744 | OPC_Decode, 231, 23, 123, // 24937: decode to PVFSUBLOiv using decoder 123 |
| 11745 | // 24937: } else try { |
| 11746 | OPC_Decode, 237, 23, 124, // 24941: decode to PVFSUBLOivm using decoder 124 |
| 11747 | // 24941: } |
| 11748 | // 24941: } |
| 11749 | 1, 0, // 24945: case 0x1: { |
| 11750 | OPC_CheckField, 0, 8, 0, // 24947: check Inst[7:0] == 0x0 |
| 11751 | OPC_CheckField, 16, 8, 0, // 24951: check Inst[23:16] == 0x0 |
| 11752 | OPC_CheckField, 32, 8, 0, // 24955: check Inst[39:32] == 0x0 |
| 11753 | OPC_Scope, 8, // 24959: try { |
| 11754 | OPC_CheckField, 48, 4, 0, // 24961: check Inst[51:48] == 0x0 |
| 11755 | OPC_Decode, 243, 23, 127, // 24965: decode to PVFSUBLOrv using decoder 127 |
| 11756 | // 24965: } else try { |
| 11757 | OPC_Decode, 249, 23, 128, 1, // 24969: decode to PVFSUBLOrvm using decoder 128 |
| 11758 | // 24969: } |
| 11759 | // 24969: } |
| 11760 | // 24969: } // switch Inst[47] |
| 11761 | // 24969: } |
| 11762 | // 24969: } // switch Inst[54:52] |
| 11763 | // 24969: } |
| 11764 | 185, 3, 178, 1, // 24974: case 0x1b9: { |
| 11765 | OPC_SwitchField, 52, 3, // 24978: switch Inst[54:52] { |
| 11766 | 0, 22, // 24981: case 0x0: { |
| 11767 | OPC_CheckField, 0, 8, 0, // 24983: check Inst[7:0] == 0x0 |
| 11768 | OPC_CheckField, 32, 16, 0, // 24987: check Inst[47:32] == 0x0 |
| 11769 | OPC_Scope, 8, // 24991: try { |
| 11770 | OPC_CheckField, 48, 4, 0, // 24993: check Inst[51:48] == 0x0 |
| 11771 | OPC_Decode, 163, 24, 121, // 24997: decode to PVFSUBUPvv using decoder 121 |
| 11772 | // 24997: } else try { |
| 11773 | OPC_Decode, 169, 24, 122, // 25001: decode to PVFSUBUPvvm using decoder 122 |
| 11774 | // 25001: } |
| 11775 | // 25001: } |
| 11776 | 2, 61, // 25005: case 0x2: { |
| 11777 | OPC_SwitchField, 47, 1, // 25007: switch Inst[47] { |
| 11778 | 0, 26, // 25010: case 0x0: { |
| 11779 | OPC_CheckField, 0, 8, 0, // 25012: check Inst[7:0] == 0x0 |
| 11780 | OPC_CheckField, 16, 8, 0, // 25016: check Inst[23:16] == 0x0 |
| 11781 | OPC_CheckField, 32, 8, 0, // 25020: check Inst[39:32] == 0x0 |
| 11782 | OPC_Scope, 8, // 25024: try { |
| 11783 | OPC_CheckField, 48, 4, 0, // 25026: check Inst[51:48] == 0x0 |
| 11784 | OPC_Decode, 139, 24, 123, // 25030: decode to PVFSUBUPiv using decoder 123 |
| 11785 | // 25030: } else try { |
| 11786 | OPC_Decode, 145, 24, 124, // 25034: decode to PVFSUBUPivm using decoder 124 |
| 11787 | // 25034: } |
| 11788 | // 25034: } |
| 11789 | 1, 0, // 25038: case 0x1: { |
| 11790 | OPC_CheckField, 0, 8, 0, // 25040: check Inst[7:0] == 0x0 |
| 11791 | OPC_CheckField, 16, 8, 0, // 25044: check Inst[23:16] == 0x0 |
| 11792 | OPC_CheckField, 32, 8, 0, // 25048: check Inst[39:32] == 0x0 |
| 11793 | OPC_Scope, 9, // 25052: try { |
| 11794 | OPC_CheckField, 48, 4, 0, // 25054: check Inst[51:48] == 0x0 |
| 11795 | OPC_Decode, 151, 24, 210, 1, // 25058: decode to PVFSUBUPrv using decoder 210 |
| 11796 | // 25058: } else try { |
| 11797 | OPC_Decode, 157, 24, 211, 1, // 25063: decode to PVFSUBUPrvm using decoder 211 |
| 11798 | // 25063: } |
| 11799 | // 25063: } |
| 11800 | // 25063: } // switch Inst[47] |
| 11801 | // 25063: } |
| 11802 | 4, 23, // 25068: case 0x4: { |
| 11803 | OPC_CheckField, 0, 8, 0, // 25070: check Inst[7:0] == 0x0 |
| 11804 | OPC_CheckField, 32, 16, 0, // 25074: check Inst[47:32] == 0x0 |
| 11805 | OPC_Scope, 8, // 25078: try { |
| 11806 | OPC_CheckField, 48, 4, 0, // 25080: check Inst[51:48] == 0x0 |
| 11807 | OPC_Decode, 199, 24, 121, // 25084: decode to PVFSUBvv using decoder 121 |
| 11808 | // 25084: } else try { |
| 11809 | OPC_Decode, 205, 24, 129, 1, // 25088: decode to PVFSUBvvm using decoder 129 |
| 11810 | // 25088: } |
| 11811 | // 25088: } |
| 11812 | 6, 0, // 25093: case 0x6: { |
| 11813 | OPC_SwitchField, 47, 1, // 25095: switch Inst[47] { |
| 11814 | 0, 27, // 25098: case 0x0: { |
| 11815 | OPC_CheckField, 0, 8, 0, // 25100: check Inst[7:0] == 0x0 |
| 11816 | OPC_CheckField, 16, 8, 0, // 25104: check Inst[23:16] == 0x0 |
| 11817 | OPC_CheckField, 32, 8, 0, // 25108: check Inst[39:32] == 0x0 |
| 11818 | OPC_Scope, 8, // 25112: try { |
| 11819 | OPC_CheckField, 48, 4, 0, // 25114: check Inst[51:48] == 0x0 |
| 11820 | OPC_Decode, 175, 24, 123, // 25118: decode to PVFSUBiv using decoder 123 |
| 11821 | // 25118: } else try { |
| 11822 | OPC_Decode, 181, 24, 130, 1, // 25122: decode to PVFSUBivm using decoder 130 |
| 11823 | // 25122: } |
| 11824 | // 25122: } |
| 11825 | 1, 0, // 25127: case 0x1: { |
| 11826 | OPC_CheckField, 0, 8, 0, // 25129: check Inst[7:0] == 0x0 |
| 11827 | OPC_CheckField, 16, 8, 0, // 25133: check Inst[23:16] == 0x0 |
| 11828 | OPC_CheckField, 32, 8, 0, // 25137: check Inst[39:32] == 0x0 |
| 11829 | OPC_Scope, 8, // 25141: try { |
| 11830 | OPC_CheckField, 48, 4, 0, // 25143: check Inst[51:48] == 0x0 |
| 11831 | OPC_Decode, 187, 24, 127, // 25147: decode to PVFSUBrv using decoder 127 |
| 11832 | // 25147: } else try { |
| 11833 | OPC_Decode, 193, 24, 131, 1, // 25151: decode to PVFSUBrvm using decoder 131 |
| 11834 | // 25151: } |
| 11835 | // 25151: } |
| 11836 | // 25151: } // switch Inst[47] |
| 11837 | // 25151: } |
| 11838 | // 25151: } // switch Inst[54:52] |
| 11839 | // 25151: } |
| 11840 | 186, 3, 146, 1, // 25156: case 0x1ba: { |
| 11841 | OPC_SwitchField, 52, 3, // 25160: switch Inst[54:52] { |
| 11842 | 0, 22, // 25163: case 0x0: { |
| 11843 | OPC_CheckField, 0, 8, 0, // 25165: check Inst[7:0] == 0x0 |
| 11844 | OPC_CheckField, 32, 16, 0, // 25169: check Inst[47:32] == 0x0 |
| 11845 | OPC_Scope, 8, // 25173: try { |
| 11846 | OPC_CheckField, 48, 4, 0, // 25175: check Inst[51:48] == 0x0 |
| 11847 | OPC_Decode, 224, 44, 121, // 25179: decode to VFDIVDvv using decoder 121 |
| 11848 | // 25179: } else try { |
| 11849 | OPC_Decode, 230, 44, 122, // 25183: decode to VFDIVDvvm using decoder 122 |
| 11850 | // 25183: } |
| 11851 | // 25183: } |
| 11852 | 1, 55, // 25187: case 0x1: { |
| 11853 | OPC_SwitchField, 47, 1, // 25189: switch Inst[47] { |
| 11854 | 0, 24, // 25192: case 0x0: { |
| 11855 | OPC_CheckField, 0, 16, 0, // 25194: check Inst[15:0] == 0x0 |
| 11856 | OPC_CheckField, 32, 8, 0, // 25198: check Inst[39:32] == 0x0 |
| 11857 | OPC_Scope, 9, // 25202: try { |
| 11858 | OPC_CheckField, 48, 4, 0, // 25204: check Inst[51:48] == 0x0 |
| 11859 | OPC_Decode, 200, 44, 214, 1, // 25208: decode to VFDIVDvi using decoder 214 |
| 11860 | // 25208: } else try { |
| 11861 | OPC_Decode, 206, 44, 231, 1, // 25213: decode to VFDIVDvim using decoder 231 |
| 11862 | // 25213: } |
| 11863 | // 25213: } |
| 11864 | 1, 0, // 25218: case 0x1: { |
| 11865 | OPC_CheckField, 0, 16, 0, // 25220: check Inst[15:0] == 0x0 |
| 11866 | OPC_CheckField, 32, 8, 0, // 25224: check Inst[39:32] == 0x0 |
| 11867 | OPC_Scope, 9, // 25228: try { |
| 11868 | OPC_CheckField, 48, 4, 0, // 25230: check Inst[51:48] == 0x0 |
| 11869 | OPC_Decode, 212, 44, 215, 1, // 25234: decode to VFDIVDvr using decoder 215 |
| 11870 | // 25234: } else try { |
| 11871 | OPC_Decode, 218, 44, 232, 1, // 25239: decode to VFDIVDvrm using decoder 232 |
| 11872 | // 25239: } |
| 11873 | // 25239: } |
| 11874 | // 25239: } // switch Inst[47] |
| 11875 | // 25239: } |
| 11876 | 2, 0, // 25244: case 0x2: { |
| 11877 | OPC_SwitchField, 47, 1, // 25246: switch Inst[47] { |
| 11878 | 0, 26, // 25249: case 0x0: { |
| 11879 | OPC_CheckField, 0, 8, 0, // 25251: check Inst[7:0] == 0x0 |
| 11880 | OPC_CheckField, 16, 8, 0, // 25255: check Inst[23:16] == 0x0 |
| 11881 | OPC_CheckField, 32, 8, 0, // 25259: check Inst[39:32] == 0x0 |
| 11882 | OPC_Scope, 8, // 25263: try { |
| 11883 | OPC_CheckField, 48, 4, 0, // 25265: check Inst[51:48] == 0x0 |
| 11884 | OPC_Decode, 176, 44, 123, // 25269: decode to VFDIVDiv using decoder 123 |
| 11885 | // 25269: } else try { |
| 11886 | OPC_Decode, 182, 44, 124, // 25273: decode to VFDIVDivm using decoder 124 |
| 11887 | // 25273: } |
| 11888 | // 25273: } |
| 11889 | 1, 0, // 25277: case 0x1: { |
| 11890 | OPC_CheckField, 0, 8, 0, // 25279: check Inst[7:0] == 0x0 |
| 11891 | OPC_CheckField, 16, 8, 0, // 25283: check Inst[23:16] == 0x0 |
| 11892 | OPC_CheckField, 32, 8, 0, // 25287: check Inst[39:32] == 0x0 |
| 11893 | OPC_Scope, 8, // 25291: try { |
| 11894 | OPC_CheckField, 48, 4, 0, // 25293: check Inst[51:48] == 0x0 |
| 11895 | OPC_Decode, 188, 44, 127, // 25297: decode to VFDIVDrv using decoder 127 |
| 11896 | // 25297: } else try { |
| 11897 | OPC_Decode, 194, 44, 128, 1, // 25301: decode to VFDIVDrvm using decoder 128 |
| 11898 | // 25301: } |
| 11899 | // 25301: } |
| 11900 | // 25301: } // switch Inst[47] |
| 11901 | // 25301: } |
| 11902 | // 25301: } // switch Inst[54:52] |
| 11903 | // 25301: } |
| 11904 | 187, 3, 147, 1, // 25306: case 0x1bb: { |
| 11905 | OPC_SwitchField, 52, 3, // 25310: switch Inst[54:52] { |
| 11906 | 0, 22, // 25313: case 0x0: { |
| 11907 | OPC_CheckField, 0, 8, 0, // 25315: check Inst[7:0] == 0x0 |
| 11908 | OPC_CheckField, 32, 16, 0, // 25319: check Inst[47:32] == 0x0 |
| 11909 | OPC_Scope, 8, // 25323: try { |
| 11910 | OPC_CheckField, 48, 4, 0, // 25325: check Inst[51:48] == 0x0 |
| 11911 | OPC_Decode, 156, 45, 121, // 25329: decode to VFDIVSvv using decoder 121 |
| 11912 | // 25329: } else try { |
| 11913 | OPC_Decode, 162, 45, 122, // 25333: decode to VFDIVSvvm using decoder 122 |
| 11914 | // 25333: } |
| 11915 | // 25333: } |
| 11916 | 1, 55, // 25337: case 0x1: { |
| 11917 | OPC_SwitchField, 47, 1, // 25339: switch Inst[47] { |
| 11918 | 0, 24, // 25342: case 0x0: { |
| 11919 | OPC_CheckField, 0, 16, 0, // 25344: check Inst[15:0] == 0x0 |
| 11920 | OPC_CheckField, 32, 8, 0, // 25348: check Inst[39:32] == 0x0 |
| 11921 | OPC_Scope, 9, // 25352: try { |
| 11922 | OPC_CheckField, 48, 4, 0, // 25354: check Inst[51:48] == 0x0 |
| 11923 | OPC_Decode, 132, 45, 214, 1, // 25358: decode to VFDIVSvi using decoder 214 |
| 11924 | // 25358: } else try { |
| 11925 | OPC_Decode, 138, 45, 231, 1, // 25363: decode to VFDIVSvim using decoder 231 |
| 11926 | // 25363: } |
| 11927 | // 25363: } |
| 11928 | 1, 0, // 25368: case 0x1: { |
| 11929 | OPC_CheckField, 0, 16, 0, // 25370: check Inst[15:0] == 0x0 |
| 11930 | OPC_CheckField, 32, 8, 0, // 25374: check Inst[39:32] == 0x0 |
| 11931 | OPC_Scope, 9, // 25378: try { |
| 11932 | OPC_CheckField, 48, 4, 0, // 25380: check Inst[51:48] == 0x0 |
| 11933 | OPC_Decode, 144, 45, 216, 1, // 25384: decode to VFDIVSvr using decoder 216 |
| 11934 | // 25384: } else try { |
| 11935 | OPC_Decode, 150, 45, 233, 1, // 25389: decode to VFDIVSvrm using decoder 233 |
| 11936 | // 25389: } |
| 11937 | // 25389: } |
| 11938 | // 25389: } // switch Inst[47] |
| 11939 | // 25389: } |
| 11940 | 2, 0, // 25394: case 0x2: { |
| 11941 | OPC_SwitchField, 47, 1, // 25396: switch Inst[47] { |
| 11942 | 0, 26, // 25399: case 0x0: { |
| 11943 | OPC_CheckField, 0, 8, 0, // 25401: check Inst[7:0] == 0x0 |
| 11944 | OPC_CheckField, 16, 8, 0, // 25405: check Inst[23:16] == 0x0 |
| 11945 | OPC_CheckField, 32, 8, 0, // 25409: check Inst[39:32] == 0x0 |
| 11946 | OPC_Scope, 8, // 25413: try { |
| 11947 | OPC_CheckField, 48, 4, 0, // 25415: check Inst[51:48] == 0x0 |
| 11948 | OPC_Decode, 236, 44, 123, // 25419: decode to VFDIVSiv using decoder 123 |
| 11949 | // 25419: } else try { |
| 11950 | OPC_Decode, 242, 44, 124, // 25423: decode to VFDIVSivm using decoder 124 |
| 11951 | // 25423: } |
| 11952 | // 25423: } |
| 11953 | 1, 0, // 25427: case 0x1: { |
| 11954 | OPC_CheckField, 0, 8, 0, // 25429: check Inst[7:0] == 0x0 |
| 11955 | OPC_CheckField, 16, 8, 0, // 25433: check Inst[23:16] == 0x0 |
| 11956 | OPC_CheckField, 32, 8, 0, // 25437: check Inst[39:32] == 0x0 |
| 11957 | OPC_Scope, 9, // 25441: try { |
| 11958 | OPC_CheckField, 48, 4, 0, // 25443: check Inst[51:48] == 0x0 |
| 11959 | OPC_Decode, 248, 44, 210, 1, // 25447: decode to VFDIVSrv using decoder 210 |
| 11960 | // 25447: } else try { |
| 11961 | OPC_Decode, 254, 44, 211, 1, // 25452: decode to VFDIVSrvm using decoder 211 |
| 11962 | // 25452: } |
| 11963 | // 25452: } |
| 11964 | // 25452: } // switch Inst[47] |
| 11965 | // 25452: } |
| 11966 | // 25452: } // switch Inst[54:52] |
| 11967 | // 25452: } |
| 11968 | 188, 3, 33, // 25457: case 0x1bc: { |
| 11969 | OPC_SwitchField, 47, 8, // 25460: switch Inst[54:47] { |
| 11970 | 0, 13, // 25463: case 0x0: { |
| 11971 | OPC_CheckField, 32, 8, 0, // 25465: check Inst[39:32] == 0x0 |
| 11972 | OPC_CheckField, 0, 16, 0, // 25469: check Inst[15:0] == 0x0 |
| 11973 | OPC_Decode, 160, 46, 214, 1, // 25473: decode to VFISDvi using decoder 214 |
| 11974 | // 25473: } |
| 11975 | 1, 0, // 25478: case 0x1: { |
| 11976 | OPC_CheckField, 32, 8, 0, // 25480: check Inst[39:32] == 0x0 |
| 11977 | OPC_CheckField, 0, 16, 0, // 25484: check Inst[15:0] == 0x0 |
| 11978 | OPC_Decode, 166, 46, 215, 1, // 25488: decode to VFISDvr using decoder 215 |
| 11979 | // 25488: } |
| 11980 | // 25488: } // switch Inst[54:47] |
| 11981 | // 25488: } |
| 11982 | 189, 3, 33, // 25493: case 0x1bd: { |
| 11983 | OPC_SwitchField, 47, 8, // 25496: switch Inst[54:47] { |
| 11984 | 0, 13, // 25499: case 0x0: { |
| 11985 | OPC_CheckField, 32, 8, 0, // 25501: check Inst[39:32] == 0x0 |
| 11986 | OPC_CheckField, 0, 16, 0, // 25505: check Inst[15:0] == 0x0 |
| 11987 | OPC_Decode, 196, 46, 214, 1, // 25509: decode to VFISSvi using decoder 214 |
| 11988 | // 25509: } |
| 11989 | 1, 0, // 25514: case 0x1: { |
| 11990 | OPC_CheckField, 32, 8, 0, // 25516: check Inst[39:32] == 0x0 |
| 11991 | OPC_CheckField, 0, 16, 0, // 25520: check Inst[15:0] == 0x0 |
| 11992 | OPC_Decode, 202, 46, 216, 1, // 25524: decode to VFISSvr using decoder 216 |
| 11993 | // 25524: } |
| 11994 | // 25524: } // switch Inst[54:47] |
| 11995 | // 25524: } |
| 11996 | 194, 3, 51, // 25529: case 0x1c2: { |
| 11997 | OPC_SwitchField, 52, 3, // 25532: switch Inst[54:52] { |
| 11998 | 0, 22, // 25535: case 0x0: { |
| 11999 | OPC_CheckField, 0, 16, 0, // 25537: check Inst[15:0] == 0x0 |
| 12000 | OPC_CheckField, 32, 16, 0, // 25541: check Inst[47:32] == 0x0 |
| 12001 | OPC_Scope, 8, // 25545: try { |
| 12002 | OPC_CheckField, 48, 4, 0, // 25547: check Inst[51:48] == 0x0 |
| 12003 | OPC_Decode, 128, 68, 119, // 25551: decode to VRCPDv using decoder 119 |
| 12004 | // 25551: } else try { |
| 12005 | OPC_Decode, 134, 68, 120, // 25555: decode to VRCPDvm using decoder 120 |
| 12006 | // 25555: } |
| 12007 | // 25555: } |
| 12008 | 4, 0, // 25559: case 0x4: { |
| 12009 | OPC_CheckField, 0, 16, 0, // 25561: check Inst[15:0] == 0x0 |
| 12010 | OPC_CheckField, 32, 16, 0, // 25565: check Inst[47:32] == 0x0 |
| 12011 | OPC_Scope, 8, // 25569: try { |
| 12012 | OPC_CheckField, 48, 4, 0, // 25571: check Inst[51:48] == 0x0 |
| 12013 | OPC_Decode, 223, 27, 119, // 25575: decode to PVRCPLOv using decoder 119 |
| 12014 | // 25575: } else try { |
| 12015 | OPC_Decode, 229, 27, 120, // 25579: decode to PVRCPLOvm using decoder 120 |
| 12016 | // 25579: } |
| 12017 | // 25579: } |
| 12018 | // 25579: } // switch Inst[54:52] |
| 12019 | // 25579: } |
| 12020 | 195, 3, 52, // 25583: case 0x1c3: { |
| 12021 | OPC_SwitchField, 52, 3, // 25586: switch Inst[54:52] { |
| 12022 | 0, 22, // 25589: case 0x0: { |
| 12023 | OPC_CheckField, 0, 16, 0, // 25591: check Inst[15:0] == 0x0 |
| 12024 | OPC_CheckField, 32, 16, 0, // 25595: check Inst[47:32] == 0x0 |
| 12025 | OPC_Scope, 8, // 25599: try { |
| 12026 | OPC_CheckField, 48, 4, 0, // 25601: check Inst[51:48] == 0x0 |
| 12027 | OPC_Decode, 235, 27, 119, // 25605: decode to PVRCPUPv using decoder 119 |
| 12028 | // 25605: } else try { |
| 12029 | OPC_Decode, 241, 27, 120, // 25609: decode to PVRCPUPvm using decoder 120 |
| 12030 | // 25609: } |
| 12031 | // 25609: } |
| 12032 | 4, 0, // 25613: case 0x4: { |
| 12033 | OPC_CheckField, 0, 16, 0, // 25615: check Inst[15:0] == 0x0 |
| 12034 | OPC_CheckField, 32, 16, 0, // 25619: check Inst[47:32] == 0x0 |
| 12035 | OPC_Scope, 8, // 25623: try { |
| 12036 | OPC_CheckField, 48, 4, 0, // 25625: check Inst[51:48] == 0x0 |
| 12037 | OPC_Decode, 247, 27, 119, // 25629: decode to PVRCPv using decoder 119 |
| 12038 | // 25629: } else try { |
| 12039 | OPC_Decode, 253, 27, 234, 1, // 25633: decode to PVRCPvm using decoder 234 |
| 12040 | // 25633: } |
| 12041 | // 25633: } |
| 12042 | // 25633: } // switch Inst[54:52] |
| 12043 | // 25633: } |
| 12044 | 196, 3, 147, 2, // 25638: case 0x1c4: { |
| 12045 | OPC_SwitchField, 52, 3, // 25642: switch Inst[54:52] { |
| 12046 | 0, 20, // 25645: case 0x0: { |
| 12047 | OPC_CheckField, 32, 16, 0, // 25647: check Inst[47:32] == 0x0 |
| 12048 | OPC_Scope, 9, // 25651: try { |
| 12049 | OPC_CheckField, 48, 4, 0, // 25653: check Inst[51:48] == 0x0 |
| 12050 | OPC_Decode, 128, 47, 235, 1, // 25657: decode to VFMADDvvv using decoder 235 |
| 12051 | // 25657: } else try { |
| 12052 | OPC_Decode, 134, 47, 236, 1, // 25662: decode to VFMADDvvvm using decoder 236 |
| 12053 | // 25662: } |
| 12054 | // 25662: } |
| 12055 | 1, 55, // 25667: case 0x1: { |
| 12056 | OPC_SwitchField, 47, 1, // 25669: switch Inst[47] { |
| 12057 | 0, 24, // 25672: case 0x0: { |
| 12058 | OPC_CheckField, 8, 8, 0, // 25674: check Inst[15:8] == 0x0 |
| 12059 | OPC_CheckField, 32, 8, 0, // 25678: check Inst[39:32] == 0x0 |
| 12060 | OPC_Scope, 9, // 25682: try { |
| 12061 | OPC_CheckField, 48, 4, 0, // 25684: check Inst[51:48] == 0x0 |
| 12062 | OPC_Decode, 232, 46, 237, 1, // 25688: decode to VFMADDviv using decoder 237 |
| 12063 | // 25688: } else try { |
| 12064 | OPC_Decode, 238, 46, 238, 1, // 25693: decode to VFMADDvivm using decoder 238 |
| 12065 | // 25693: } |
| 12066 | // 25693: } |
| 12067 | 1, 0, // 25698: case 0x1: { |
| 12068 | OPC_CheckField, 8, 8, 0, // 25700: check Inst[15:8] == 0x0 |
| 12069 | OPC_CheckField, 32, 8, 0, // 25704: check Inst[39:32] == 0x0 |
| 12070 | OPC_Scope, 9, // 25708: try { |
| 12071 | OPC_CheckField, 48, 4, 0, // 25710: check Inst[51:48] == 0x0 |
| 12072 | OPC_Decode, 244, 46, 239, 1, // 25714: decode to VFMADDvrv using decoder 239 |
| 12073 | // 25714: } else try { |
| 12074 | OPC_Decode, 250, 46, 240, 1, // 25719: decode to VFMADDvrvm using decoder 240 |
| 12075 | // 25719: } |
| 12076 | // 25719: } |
| 12077 | // 25719: } // switch Inst[47] |
| 12078 | // 25719: } |
| 12079 | 2, 55, // 25724: case 0x2: { |
| 12080 | OPC_SwitchField, 47, 1, // 25726: switch Inst[47] { |
| 12081 | 0, 24, // 25729: case 0x0: { |
| 12082 | OPC_CheckField, 16, 8, 0, // 25731: check Inst[23:16] == 0x0 |
| 12083 | OPC_CheckField, 32, 8, 0, // 25735: check Inst[39:32] == 0x0 |
| 12084 | OPC_Scope, 9, // 25739: try { |
| 12085 | OPC_CheckField, 48, 4, 0, // 25741: check Inst[51:48] == 0x0 |
| 12086 | OPC_Decode, 208, 46, 241, 1, // 25745: decode to VFMADDivv using decoder 241 |
| 12087 | // 25745: } else try { |
| 12088 | OPC_Decode, 214, 46, 242, 1, // 25750: decode to VFMADDivvm using decoder 242 |
| 12089 | // 25750: } |
| 12090 | // 25750: } |
| 12091 | 1, 0, // 25755: case 0x1: { |
| 12092 | OPC_CheckField, 16, 8, 0, // 25757: check Inst[23:16] == 0x0 |
| 12093 | OPC_CheckField, 32, 8, 0, // 25761: check Inst[39:32] == 0x0 |
| 12094 | OPC_Scope, 9, // 25765: try { |
| 12095 | OPC_CheckField, 48, 4, 0, // 25767: check Inst[51:48] == 0x0 |
| 12096 | OPC_Decode, 220, 46, 243, 1, // 25771: decode to VFMADDrvv using decoder 243 |
| 12097 | // 25771: } else try { |
| 12098 | OPC_Decode, 226, 46, 244, 1, // 25776: decode to VFMADDrvvm using decoder 244 |
| 12099 | // 25776: } |
| 12100 | // 25776: } |
| 12101 | // 25776: } // switch Inst[47] |
| 12102 | // 25776: } |
| 12103 | 4, 20, // 25781: case 0x4: { |
| 12104 | OPC_CheckField, 32, 16, 0, // 25783: check Inst[47:32] == 0x0 |
| 12105 | OPC_Scope, 9, // 25787: try { |
| 12106 | OPC_CheckField, 48, 4, 0, // 25789: check Inst[51:48] == 0x0 |
| 12107 | OPC_Decode, 187, 15, 235, 1, // 25793: decode to PVFMADLOvvv using decoder 235 |
| 12108 | // 25793: } else try { |
| 12109 | OPC_Decode, 193, 15, 236, 1, // 25798: decode to PVFMADLOvvvm using decoder 236 |
| 12110 | // 25798: } |
| 12111 | // 25798: } |
| 12112 | 5, 55, // 25803: case 0x5: { |
| 12113 | OPC_SwitchField, 47, 1, // 25805: switch Inst[47] { |
| 12114 | 0, 24, // 25808: case 0x0: { |
| 12115 | OPC_CheckField, 8, 8, 0, // 25810: check Inst[15:8] == 0x0 |
| 12116 | OPC_CheckField, 32, 8, 0, // 25814: check Inst[39:32] == 0x0 |
| 12117 | OPC_Scope, 9, // 25818: try { |
| 12118 | OPC_CheckField, 48, 4, 0, // 25820: check Inst[51:48] == 0x0 |
| 12119 | OPC_Decode, 163, 15, 237, 1, // 25824: decode to PVFMADLOviv using decoder 237 |
| 12120 | // 25824: } else try { |
| 12121 | OPC_Decode, 169, 15, 238, 1, // 25829: decode to PVFMADLOvivm using decoder 238 |
| 12122 | // 25829: } |
| 12123 | // 25829: } |
| 12124 | 1, 0, // 25834: case 0x1: { |
| 12125 | OPC_CheckField, 8, 8, 0, // 25836: check Inst[15:8] == 0x0 |
| 12126 | OPC_CheckField, 32, 8, 0, // 25840: check Inst[39:32] == 0x0 |
| 12127 | OPC_Scope, 9, // 25844: try { |
| 12128 | OPC_CheckField, 48, 4, 0, // 25846: check Inst[51:48] == 0x0 |
| 12129 | OPC_Decode, 175, 15, 239, 1, // 25850: decode to PVFMADLOvrv using decoder 239 |
| 12130 | // 25850: } else try { |
| 12131 | OPC_Decode, 181, 15, 240, 1, // 25855: decode to PVFMADLOvrvm using decoder 240 |
| 12132 | // 25855: } |
| 12133 | // 25855: } |
| 12134 | // 25855: } // switch Inst[47] |
| 12135 | // 25855: } |
| 12136 | 6, 0, // 25860: case 0x6: { |
| 12137 | OPC_SwitchField, 47, 1, // 25862: switch Inst[47] { |
| 12138 | 0, 24, // 25865: case 0x0: { |
| 12139 | OPC_CheckField, 16, 8, 0, // 25867: check Inst[23:16] == 0x0 |
| 12140 | OPC_CheckField, 32, 8, 0, // 25871: check Inst[39:32] == 0x0 |
| 12141 | OPC_Scope, 9, // 25875: try { |
| 12142 | OPC_CheckField, 48, 4, 0, // 25877: check Inst[51:48] == 0x0 |
| 12143 | OPC_Decode, 139, 15, 241, 1, // 25881: decode to PVFMADLOivv using decoder 241 |
| 12144 | // 25881: } else try { |
| 12145 | OPC_Decode, 145, 15, 242, 1, // 25886: decode to PVFMADLOivvm using decoder 242 |
| 12146 | // 25886: } |
| 12147 | // 25886: } |
| 12148 | 1, 0, // 25891: case 0x1: { |
| 12149 | OPC_CheckField, 16, 8, 0, // 25893: check Inst[23:16] == 0x0 |
| 12150 | OPC_CheckField, 32, 8, 0, // 25897: check Inst[39:32] == 0x0 |
| 12151 | OPC_Scope, 9, // 25901: try { |
| 12152 | OPC_CheckField, 48, 4, 0, // 25903: check Inst[51:48] == 0x0 |
| 12153 | OPC_Decode, 151, 15, 243, 1, // 25907: decode to PVFMADLOrvv using decoder 243 |
| 12154 | // 25907: } else try { |
| 12155 | OPC_Decode, 157, 15, 244, 1, // 25912: decode to PVFMADLOrvvm using decoder 244 |
| 12156 | // 25912: } |
| 12157 | // 25912: } |
| 12158 | // 25912: } // switch Inst[47] |
| 12159 | // 25912: } |
| 12160 | // 25912: } // switch Inst[54:52] |
| 12161 | // 25912: } |
| 12162 | 197, 3, 147, 2, // 25917: case 0x1c5: { |
| 12163 | OPC_SwitchField, 52, 3, // 25921: switch Inst[54:52] { |
| 12164 | 0, 20, // 25924: case 0x0: { |
| 12165 | OPC_CheckField, 32, 16, 0, // 25926: check Inst[47:32] == 0x0 |
| 12166 | OPC_Scope, 9, // 25930: try { |
| 12167 | OPC_CheckField, 48, 4, 0, // 25932: check Inst[51:48] == 0x0 |
| 12168 | OPC_Decode, 247, 15, 235, 1, // 25936: decode to PVFMADUPvvv using decoder 235 |
| 12169 | // 25936: } else try { |
| 12170 | OPC_Decode, 253, 15, 236, 1, // 25941: decode to PVFMADUPvvvm using decoder 236 |
| 12171 | // 25941: } |
| 12172 | // 25941: } |
| 12173 | 1, 55, // 25946: case 0x1: { |
| 12174 | OPC_SwitchField, 47, 1, // 25948: switch Inst[47] { |
| 12175 | 0, 24, // 25951: case 0x0: { |
| 12176 | OPC_CheckField, 8, 8, 0, // 25953: check Inst[15:8] == 0x0 |
| 12177 | OPC_CheckField, 32, 8, 0, // 25957: check Inst[39:32] == 0x0 |
| 12178 | OPC_Scope, 9, // 25961: try { |
| 12179 | OPC_CheckField, 48, 4, 0, // 25963: check Inst[51:48] == 0x0 |
| 12180 | OPC_Decode, 223, 15, 237, 1, // 25967: decode to PVFMADUPviv using decoder 237 |
| 12181 | // 25967: } else try { |
| 12182 | OPC_Decode, 229, 15, 238, 1, // 25972: decode to PVFMADUPvivm using decoder 238 |
| 12183 | // 25972: } |
| 12184 | // 25972: } |
| 12185 | 1, 0, // 25977: case 0x1: { |
| 12186 | OPC_CheckField, 8, 8, 0, // 25979: check Inst[15:8] == 0x0 |
| 12187 | OPC_CheckField, 32, 8, 0, // 25983: check Inst[39:32] == 0x0 |
| 12188 | OPC_Scope, 9, // 25987: try { |
| 12189 | OPC_CheckField, 48, 4, 0, // 25989: check Inst[51:48] == 0x0 |
| 12190 | OPC_Decode, 235, 15, 245, 1, // 25993: decode to PVFMADUPvrv using decoder 245 |
| 12191 | // 25993: } else try { |
| 12192 | OPC_Decode, 241, 15, 246, 1, // 25998: decode to PVFMADUPvrvm using decoder 246 |
| 12193 | // 25998: } |
| 12194 | // 25998: } |
| 12195 | // 25998: } // switch Inst[47] |
| 12196 | // 25998: } |
| 12197 | 2, 55, // 26003: case 0x2: { |
| 12198 | OPC_SwitchField, 47, 1, // 26005: switch Inst[47] { |
| 12199 | 0, 24, // 26008: case 0x0: { |
| 12200 | OPC_CheckField, 16, 8, 0, // 26010: check Inst[23:16] == 0x0 |
| 12201 | OPC_CheckField, 32, 8, 0, // 26014: check Inst[39:32] == 0x0 |
| 12202 | OPC_Scope, 9, // 26018: try { |
| 12203 | OPC_CheckField, 48, 4, 0, // 26020: check Inst[51:48] == 0x0 |
| 12204 | OPC_Decode, 199, 15, 241, 1, // 26024: decode to PVFMADUPivv using decoder 241 |
| 12205 | // 26024: } else try { |
| 12206 | OPC_Decode, 205, 15, 242, 1, // 26029: decode to PVFMADUPivvm using decoder 242 |
| 12207 | // 26029: } |
| 12208 | // 26029: } |
| 12209 | 1, 0, // 26034: case 0x1: { |
| 12210 | OPC_CheckField, 16, 8, 0, // 26036: check Inst[23:16] == 0x0 |
| 12211 | OPC_CheckField, 32, 8, 0, // 26040: check Inst[39:32] == 0x0 |
| 12212 | OPC_Scope, 9, // 26044: try { |
| 12213 | OPC_CheckField, 48, 4, 0, // 26046: check Inst[51:48] == 0x0 |
| 12214 | OPC_Decode, 211, 15, 247, 1, // 26050: decode to PVFMADUPrvv using decoder 247 |
| 12215 | // 26050: } else try { |
| 12216 | OPC_Decode, 217, 15, 248, 1, // 26055: decode to PVFMADUPrvvm using decoder 248 |
| 12217 | // 26055: } |
| 12218 | // 26055: } |
| 12219 | // 26055: } // switch Inst[47] |
| 12220 | // 26055: } |
| 12221 | 4, 20, // 26060: case 0x4: { |
| 12222 | OPC_CheckField, 32, 16, 0, // 26062: check Inst[47:32] == 0x0 |
| 12223 | OPC_Scope, 9, // 26066: try { |
| 12224 | OPC_CheckField, 48, 4, 0, // 26068: check Inst[51:48] == 0x0 |
| 12225 | OPC_Decode, 179, 16, 235, 1, // 26072: decode to PVFMADvvv using decoder 235 |
| 12226 | // 26072: } else try { |
| 12227 | OPC_Decode, 185, 16, 249, 1, // 26077: decode to PVFMADvvvm using decoder 249 |
| 12228 | // 26077: } |
| 12229 | // 26077: } |
| 12230 | 5, 55, // 26082: case 0x5: { |
| 12231 | OPC_SwitchField, 47, 1, // 26084: switch Inst[47] { |
| 12232 | 0, 24, // 26087: case 0x0: { |
| 12233 | OPC_CheckField, 8, 8, 0, // 26089: check Inst[15:8] == 0x0 |
| 12234 | OPC_CheckField, 32, 8, 0, // 26093: check Inst[39:32] == 0x0 |
| 12235 | OPC_Scope, 9, // 26097: try { |
| 12236 | OPC_CheckField, 48, 4, 0, // 26099: check Inst[51:48] == 0x0 |
| 12237 | OPC_Decode, 155, 16, 237, 1, // 26103: decode to PVFMADviv using decoder 237 |
| 12238 | // 26103: } else try { |
| 12239 | OPC_Decode, 161, 16, 250, 1, // 26108: decode to PVFMADvivm using decoder 250 |
| 12240 | // 26108: } |
| 12241 | // 26108: } |
| 12242 | 1, 0, // 26113: case 0x1: { |
| 12243 | OPC_CheckField, 8, 8, 0, // 26115: check Inst[15:8] == 0x0 |
| 12244 | OPC_CheckField, 32, 8, 0, // 26119: check Inst[39:32] == 0x0 |
| 12245 | OPC_Scope, 9, // 26123: try { |
| 12246 | OPC_CheckField, 48, 4, 0, // 26125: check Inst[51:48] == 0x0 |
| 12247 | OPC_Decode, 167, 16, 239, 1, // 26129: decode to PVFMADvrv using decoder 239 |
| 12248 | // 26129: } else try { |
| 12249 | OPC_Decode, 173, 16, 251, 1, // 26134: decode to PVFMADvrvm using decoder 251 |
| 12250 | // 26134: } |
| 12251 | // 26134: } |
| 12252 | // 26134: } // switch Inst[47] |
| 12253 | // 26134: } |
| 12254 | 6, 0, // 26139: case 0x6: { |
| 12255 | OPC_SwitchField, 47, 1, // 26141: switch Inst[47] { |
| 12256 | 0, 24, // 26144: case 0x0: { |
| 12257 | OPC_CheckField, 16, 8, 0, // 26146: check Inst[23:16] == 0x0 |
| 12258 | OPC_CheckField, 32, 8, 0, // 26150: check Inst[39:32] == 0x0 |
| 12259 | OPC_Scope, 9, // 26154: try { |
| 12260 | OPC_CheckField, 48, 4, 0, // 26156: check Inst[51:48] == 0x0 |
| 12261 | OPC_Decode, 131, 16, 241, 1, // 26160: decode to PVFMADivv using decoder 241 |
| 12262 | // 26160: } else try { |
| 12263 | OPC_Decode, 137, 16, 252, 1, // 26165: decode to PVFMADivvm using decoder 252 |
| 12264 | // 26165: } |
| 12265 | // 26165: } |
| 12266 | 1, 0, // 26170: case 0x1: { |
| 12267 | OPC_CheckField, 16, 8, 0, // 26172: check Inst[23:16] == 0x0 |
| 12268 | OPC_CheckField, 32, 8, 0, // 26176: check Inst[39:32] == 0x0 |
| 12269 | OPC_Scope, 9, // 26180: try { |
| 12270 | OPC_CheckField, 48, 4, 0, // 26182: check Inst[51:48] == 0x0 |
| 12271 | OPC_Decode, 143, 16, 243, 1, // 26186: decode to PVFMADrvv using decoder 243 |
| 12272 | // 26186: } else try { |
| 12273 | OPC_Decode, 149, 16, 253, 1, // 26191: decode to PVFMADrvvm using decoder 253 |
| 12274 | // 26191: } |
| 12275 | // 26191: } |
| 12276 | // 26191: } // switch Inst[47] |
| 12277 | // 26191: } |
| 12278 | // 26191: } // switch Inst[54:52] |
| 12279 | // 26191: } |
| 12280 | 198, 3, 147, 2, // 26196: case 0x1c6: { |
| 12281 | OPC_SwitchField, 52, 3, // 26200: switch Inst[54:52] { |
| 12282 | 0, 20, // 26203: case 0x0: { |
| 12283 | OPC_CheckField, 32, 16, 0, // 26205: check Inst[47:32] == 0x0 |
| 12284 | OPC_Scope, 9, // 26209: try { |
| 12285 | OPC_CheckField, 48, 4, 0, // 26211: check Inst[51:48] == 0x0 |
| 12286 | OPC_Decode, 144, 51, 235, 1, // 26215: decode to VFNMADDvvv using decoder 235 |
| 12287 | // 26215: } else try { |
| 12288 | OPC_Decode, 150, 51, 236, 1, // 26220: decode to VFNMADDvvvm using decoder 236 |
| 12289 | // 26220: } |
| 12290 | // 26220: } |
| 12291 | 1, 55, // 26225: case 0x1: { |
| 12292 | OPC_SwitchField, 47, 1, // 26227: switch Inst[47] { |
| 12293 | 0, 24, // 26230: case 0x0: { |
| 12294 | OPC_CheckField, 8, 8, 0, // 26232: check Inst[15:8] == 0x0 |
| 12295 | OPC_CheckField, 32, 8, 0, // 26236: check Inst[39:32] == 0x0 |
| 12296 | OPC_Scope, 9, // 26240: try { |
| 12297 | OPC_CheckField, 48, 4, 0, // 26242: check Inst[51:48] == 0x0 |
| 12298 | OPC_Decode, 248, 50, 237, 1, // 26246: decode to VFNMADDviv using decoder 237 |
| 12299 | // 26246: } else try { |
| 12300 | OPC_Decode, 254, 50, 238, 1, // 26251: decode to VFNMADDvivm using decoder 238 |
| 12301 | // 26251: } |
| 12302 | // 26251: } |
| 12303 | 1, 0, // 26256: case 0x1: { |
| 12304 | OPC_CheckField, 8, 8, 0, // 26258: check Inst[15:8] == 0x0 |
| 12305 | OPC_CheckField, 32, 8, 0, // 26262: check Inst[39:32] == 0x0 |
| 12306 | OPC_Scope, 9, // 26266: try { |
| 12307 | OPC_CheckField, 48, 4, 0, // 26268: check Inst[51:48] == 0x0 |
| 12308 | OPC_Decode, 132, 51, 239, 1, // 26272: decode to VFNMADDvrv using decoder 239 |
| 12309 | // 26272: } else try { |
| 12310 | OPC_Decode, 138, 51, 240, 1, // 26277: decode to VFNMADDvrvm using decoder 240 |
| 12311 | // 26277: } |
| 12312 | // 26277: } |
| 12313 | // 26277: } // switch Inst[47] |
| 12314 | // 26277: } |
| 12315 | 2, 55, // 26282: case 0x2: { |
| 12316 | OPC_SwitchField, 47, 1, // 26284: switch Inst[47] { |
| 12317 | 0, 24, // 26287: case 0x0: { |
| 12318 | OPC_CheckField, 16, 8, 0, // 26289: check Inst[23:16] == 0x0 |
| 12319 | OPC_CheckField, 32, 8, 0, // 26293: check Inst[39:32] == 0x0 |
| 12320 | OPC_Scope, 9, // 26297: try { |
| 12321 | OPC_CheckField, 48, 4, 0, // 26299: check Inst[51:48] == 0x0 |
| 12322 | OPC_Decode, 224, 50, 241, 1, // 26303: decode to VFNMADDivv using decoder 241 |
| 12323 | // 26303: } else try { |
| 12324 | OPC_Decode, 230, 50, 242, 1, // 26308: decode to VFNMADDivvm using decoder 242 |
| 12325 | // 26308: } |
| 12326 | // 26308: } |
| 12327 | 1, 0, // 26313: case 0x1: { |
| 12328 | OPC_CheckField, 16, 8, 0, // 26315: check Inst[23:16] == 0x0 |
| 12329 | OPC_CheckField, 32, 8, 0, // 26319: check Inst[39:32] == 0x0 |
| 12330 | OPC_Scope, 9, // 26323: try { |
| 12331 | OPC_CheckField, 48, 4, 0, // 26325: check Inst[51:48] == 0x0 |
| 12332 | OPC_Decode, 236, 50, 243, 1, // 26329: decode to VFNMADDrvv using decoder 243 |
| 12333 | // 26329: } else try { |
| 12334 | OPC_Decode, 242, 50, 244, 1, // 26334: decode to VFNMADDrvvm using decoder 244 |
| 12335 | // 26334: } |
| 12336 | // 26334: } |
| 12337 | // 26334: } // switch Inst[47] |
| 12338 | // 26334: } |
| 12339 | 4, 20, // 26339: case 0x4: { |
| 12340 | OPC_CheckField, 32, 16, 0, // 26341: check Inst[47:32] == 0x0 |
| 12341 | OPC_Scope, 9, // 26345: try { |
| 12342 | OPC_CheckField, 48, 4, 0, // 26347: check Inst[51:48] == 0x0 |
| 12343 | OPC_Decode, 175, 21, 235, 1, // 26351: decode to PVFNMADLOvvv using decoder 235 |
| 12344 | // 26351: } else try { |
| 12345 | OPC_Decode, 181, 21, 236, 1, // 26356: decode to PVFNMADLOvvvm using decoder 236 |
| 12346 | // 26356: } |
| 12347 | // 26356: } |
| 12348 | 5, 55, // 26361: case 0x5: { |
| 12349 | OPC_SwitchField, 47, 1, // 26363: switch Inst[47] { |
| 12350 | 0, 24, // 26366: case 0x0: { |
| 12351 | OPC_CheckField, 8, 8, 0, // 26368: check Inst[15:8] == 0x0 |
| 12352 | OPC_CheckField, 32, 8, 0, // 26372: check Inst[39:32] == 0x0 |
| 12353 | OPC_Scope, 9, // 26376: try { |
| 12354 | OPC_CheckField, 48, 4, 0, // 26378: check Inst[51:48] == 0x0 |
| 12355 | OPC_Decode, 151, 21, 237, 1, // 26382: decode to PVFNMADLOviv using decoder 237 |
| 12356 | // 26382: } else try { |
| 12357 | OPC_Decode, 157, 21, 238, 1, // 26387: decode to PVFNMADLOvivm using decoder 238 |
| 12358 | // 26387: } |
| 12359 | // 26387: } |
| 12360 | 1, 0, // 26392: case 0x1: { |
| 12361 | OPC_CheckField, 8, 8, 0, // 26394: check Inst[15:8] == 0x0 |
| 12362 | OPC_CheckField, 32, 8, 0, // 26398: check Inst[39:32] == 0x0 |
| 12363 | OPC_Scope, 9, // 26402: try { |
| 12364 | OPC_CheckField, 48, 4, 0, // 26404: check Inst[51:48] == 0x0 |
| 12365 | OPC_Decode, 163, 21, 239, 1, // 26408: decode to PVFNMADLOvrv using decoder 239 |
| 12366 | // 26408: } else try { |
| 12367 | OPC_Decode, 169, 21, 240, 1, // 26413: decode to PVFNMADLOvrvm using decoder 240 |
| 12368 | // 26413: } |
| 12369 | // 26413: } |
| 12370 | // 26413: } // switch Inst[47] |
| 12371 | // 26413: } |
| 12372 | 6, 0, // 26418: case 0x6: { |
| 12373 | OPC_SwitchField, 47, 1, // 26420: switch Inst[47] { |
| 12374 | 0, 24, // 26423: case 0x0: { |
| 12375 | OPC_CheckField, 16, 8, 0, // 26425: check Inst[23:16] == 0x0 |
| 12376 | OPC_CheckField, 32, 8, 0, // 26429: check Inst[39:32] == 0x0 |
| 12377 | OPC_Scope, 9, // 26433: try { |
| 12378 | OPC_CheckField, 48, 4, 0, // 26435: check Inst[51:48] == 0x0 |
| 12379 | OPC_Decode, 255, 20, 241, 1, // 26439: decode to PVFNMADLOivv using decoder 241 |
| 12380 | // 26439: } else try { |
| 12381 | OPC_Decode, 133, 21, 242, 1, // 26444: decode to PVFNMADLOivvm using decoder 242 |
| 12382 | // 26444: } |
| 12383 | // 26444: } |
| 12384 | 1, 0, // 26449: case 0x1: { |
| 12385 | OPC_CheckField, 16, 8, 0, // 26451: check Inst[23:16] == 0x0 |
| 12386 | OPC_CheckField, 32, 8, 0, // 26455: check Inst[39:32] == 0x0 |
| 12387 | OPC_Scope, 9, // 26459: try { |
| 12388 | OPC_CheckField, 48, 4, 0, // 26461: check Inst[51:48] == 0x0 |
| 12389 | OPC_Decode, 139, 21, 243, 1, // 26465: decode to PVFNMADLOrvv using decoder 243 |
| 12390 | // 26465: } else try { |
| 12391 | OPC_Decode, 145, 21, 244, 1, // 26470: decode to PVFNMADLOrvvm using decoder 244 |
| 12392 | // 26470: } |
| 12393 | // 26470: } |
| 12394 | // 26470: } // switch Inst[47] |
| 12395 | // 26470: } |
| 12396 | // 26470: } // switch Inst[54:52] |
| 12397 | // 26470: } |
| 12398 | 199, 3, 147, 2, // 26475: case 0x1c7: { |
| 12399 | OPC_SwitchField, 52, 3, // 26479: switch Inst[54:52] { |
| 12400 | 0, 20, // 26482: case 0x0: { |
| 12401 | OPC_CheckField, 32, 16, 0, // 26484: check Inst[47:32] == 0x0 |
| 12402 | OPC_Scope, 9, // 26488: try { |
| 12403 | OPC_CheckField, 48, 4, 0, // 26490: check Inst[51:48] == 0x0 |
| 12404 | OPC_Decode, 235, 21, 235, 1, // 26494: decode to PVFNMADUPvvv using decoder 235 |
| 12405 | // 26494: } else try { |
| 12406 | OPC_Decode, 241, 21, 236, 1, // 26499: decode to PVFNMADUPvvvm using decoder 236 |
| 12407 | // 26499: } |
| 12408 | // 26499: } |
| 12409 | 1, 55, // 26504: case 0x1: { |
| 12410 | OPC_SwitchField, 47, 1, // 26506: switch Inst[47] { |
| 12411 | 0, 24, // 26509: case 0x0: { |
| 12412 | OPC_CheckField, 8, 8, 0, // 26511: check Inst[15:8] == 0x0 |
| 12413 | OPC_CheckField, 32, 8, 0, // 26515: check Inst[39:32] == 0x0 |
| 12414 | OPC_Scope, 9, // 26519: try { |
| 12415 | OPC_CheckField, 48, 4, 0, // 26521: check Inst[51:48] == 0x0 |
| 12416 | OPC_Decode, 211, 21, 237, 1, // 26525: decode to PVFNMADUPviv using decoder 237 |
| 12417 | // 26525: } else try { |
| 12418 | OPC_Decode, 217, 21, 238, 1, // 26530: decode to PVFNMADUPvivm using decoder 238 |
| 12419 | // 26530: } |
| 12420 | // 26530: } |
| 12421 | 1, 0, // 26535: case 0x1: { |
| 12422 | OPC_CheckField, 8, 8, 0, // 26537: check Inst[15:8] == 0x0 |
| 12423 | OPC_CheckField, 32, 8, 0, // 26541: check Inst[39:32] == 0x0 |
| 12424 | OPC_Scope, 9, // 26545: try { |
| 12425 | OPC_CheckField, 48, 4, 0, // 26547: check Inst[51:48] == 0x0 |
| 12426 | OPC_Decode, 223, 21, 245, 1, // 26551: decode to PVFNMADUPvrv using decoder 245 |
| 12427 | // 26551: } else try { |
| 12428 | OPC_Decode, 229, 21, 246, 1, // 26556: decode to PVFNMADUPvrvm using decoder 246 |
| 12429 | // 26556: } |
| 12430 | // 26556: } |
| 12431 | // 26556: } // switch Inst[47] |
| 12432 | // 26556: } |
| 12433 | 2, 55, // 26561: case 0x2: { |
| 12434 | OPC_SwitchField, 47, 1, // 26563: switch Inst[47] { |
| 12435 | 0, 24, // 26566: case 0x0: { |
| 12436 | OPC_CheckField, 16, 8, 0, // 26568: check Inst[23:16] == 0x0 |
| 12437 | OPC_CheckField, 32, 8, 0, // 26572: check Inst[39:32] == 0x0 |
| 12438 | OPC_Scope, 9, // 26576: try { |
| 12439 | OPC_CheckField, 48, 4, 0, // 26578: check Inst[51:48] == 0x0 |
| 12440 | OPC_Decode, 187, 21, 241, 1, // 26582: decode to PVFNMADUPivv using decoder 241 |
| 12441 | // 26582: } else try { |
| 12442 | OPC_Decode, 193, 21, 242, 1, // 26587: decode to PVFNMADUPivvm using decoder 242 |
| 12443 | // 26587: } |
| 12444 | // 26587: } |
| 12445 | 1, 0, // 26592: case 0x1: { |
| 12446 | OPC_CheckField, 16, 8, 0, // 26594: check Inst[23:16] == 0x0 |
| 12447 | OPC_CheckField, 32, 8, 0, // 26598: check Inst[39:32] == 0x0 |
| 12448 | OPC_Scope, 9, // 26602: try { |
| 12449 | OPC_CheckField, 48, 4, 0, // 26604: check Inst[51:48] == 0x0 |
| 12450 | OPC_Decode, 199, 21, 247, 1, // 26608: decode to PVFNMADUPrvv using decoder 247 |
| 12451 | // 26608: } else try { |
| 12452 | OPC_Decode, 205, 21, 248, 1, // 26613: decode to PVFNMADUPrvvm using decoder 248 |
| 12453 | // 26613: } |
| 12454 | // 26613: } |
| 12455 | // 26613: } // switch Inst[47] |
| 12456 | // 26613: } |
| 12457 | 4, 20, // 26618: case 0x4: { |
| 12458 | OPC_CheckField, 32, 16, 0, // 26620: check Inst[47:32] == 0x0 |
| 12459 | OPC_Scope, 9, // 26624: try { |
| 12460 | OPC_CheckField, 48, 4, 0, // 26626: check Inst[51:48] == 0x0 |
| 12461 | OPC_Decode, 167, 22, 235, 1, // 26630: decode to PVFNMADvvv using decoder 235 |
| 12462 | // 26630: } else try { |
| 12463 | OPC_Decode, 173, 22, 249, 1, // 26635: decode to PVFNMADvvvm using decoder 249 |
| 12464 | // 26635: } |
| 12465 | // 26635: } |
| 12466 | 5, 55, // 26640: case 0x5: { |
| 12467 | OPC_SwitchField, 47, 1, // 26642: switch Inst[47] { |
| 12468 | 0, 24, // 26645: case 0x0: { |
| 12469 | OPC_CheckField, 8, 8, 0, // 26647: check Inst[15:8] == 0x0 |
| 12470 | OPC_CheckField, 32, 8, 0, // 26651: check Inst[39:32] == 0x0 |
| 12471 | OPC_Scope, 9, // 26655: try { |
| 12472 | OPC_CheckField, 48, 4, 0, // 26657: check Inst[51:48] == 0x0 |
| 12473 | OPC_Decode, 143, 22, 237, 1, // 26661: decode to PVFNMADviv using decoder 237 |
| 12474 | // 26661: } else try { |
| 12475 | OPC_Decode, 149, 22, 250, 1, // 26666: decode to PVFNMADvivm using decoder 250 |
| 12476 | // 26666: } |
| 12477 | // 26666: } |
| 12478 | 1, 0, // 26671: case 0x1: { |
| 12479 | OPC_CheckField, 8, 8, 0, // 26673: check Inst[15:8] == 0x0 |
| 12480 | OPC_CheckField, 32, 8, 0, // 26677: check Inst[39:32] == 0x0 |
| 12481 | OPC_Scope, 9, // 26681: try { |
| 12482 | OPC_CheckField, 48, 4, 0, // 26683: check Inst[51:48] == 0x0 |
| 12483 | OPC_Decode, 155, 22, 239, 1, // 26687: decode to PVFNMADvrv using decoder 239 |
| 12484 | // 26687: } else try { |
| 12485 | OPC_Decode, 161, 22, 251, 1, // 26692: decode to PVFNMADvrvm using decoder 251 |
| 12486 | // 26692: } |
| 12487 | // 26692: } |
| 12488 | // 26692: } // switch Inst[47] |
| 12489 | // 26692: } |
| 12490 | 6, 0, // 26697: case 0x6: { |
| 12491 | OPC_SwitchField, 47, 1, // 26699: switch Inst[47] { |
| 12492 | 0, 24, // 26702: case 0x0: { |
| 12493 | OPC_CheckField, 16, 8, 0, // 26704: check Inst[23:16] == 0x0 |
| 12494 | OPC_CheckField, 32, 8, 0, // 26708: check Inst[39:32] == 0x0 |
| 12495 | OPC_Scope, 9, // 26712: try { |
| 12496 | OPC_CheckField, 48, 4, 0, // 26714: check Inst[51:48] == 0x0 |
| 12497 | OPC_Decode, 247, 21, 241, 1, // 26718: decode to PVFNMADivv using decoder 241 |
| 12498 | // 26718: } else try { |
| 12499 | OPC_Decode, 253, 21, 252, 1, // 26723: decode to PVFNMADivvm using decoder 252 |
| 12500 | // 26723: } |
| 12501 | // 26723: } |
| 12502 | 1, 0, // 26728: case 0x1: { |
| 12503 | OPC_CheckField, 16, 8, 0, // 26730: check Inst[23:16] == 0x0 |
| 12504 | OPC_CheckField, 32, 8, 0, // 26734: check Inst[39:32] == 0x0 |
| 12505 | OPC_Scope, 9, // 26738: try { |
| 12506 | OPC_CheckField, 48, 4, 0, // 26740: check Inst[51:48] == 0x0 |
| 12507 | OPC_Decode, 131, 22, 243, 1, // 26744: decode to PVFNMADrvv using decoder 243 |
| 12508 | // 26744: } else try { |
| 12509 | OPC_Decode, 137, 22, 253, 1, // 26749: decode to PVFNMADrvvm using decoder 253 |
| 12510 | // 26749: } |
| 12511 | // 26749: } |
| 12512 | // 26749: } // switch Inst[47] |
| 12513 | // 26749: } |
| 12514 | // 26749: } // switch Inst[54:52] |
| 12515 | // 26749: } |
| 12516 | 200, 3, 63, // 26754: case 0x1c8: { |
| 12517 | OPC_SwitchField, 47, 1, // 26757: switch Inst[47] { |
| 12518 | 0, 28, // 26760: case 0x0: { |
| 12519 | OPC_CheckField, 0, 8, 0, // 26762: check Inst[7:0] == 0x0 |
| 12520 | OPC_CheckField, 32, 8, 0, // 26766: check Inst[39:32] == 0x0 |
| 12521 | OPC_CheckField, 52, 3, 0, // 26770: check Inst[54:52] == 0x0 |
| 12522 | OPC_Scope, 9, // 26774: try { |
| 12523 | OPC_CheckField, 48, 4, 0, // 26776: check Inst[51:48] == 0x0 |
| 12524 | OPC_Decode, 228, 75, 208, 1, // 26780: decode to VSLDvvi using decoder 208 |
| 12525 | // 26780: } else try { |
| 12526 | OPC_Decode, 234, 75, 254, 1, // 26785: decode to VSLDvvim using decoder 254 |
| 12527 | // 26785: } |
| 12528 | // 26785: } |
| 12529 | 1, 0, // 26790: case 0x1: { |
| 12530 | OPC_CheckField, 0, 8, 0, // 26792: check Inst[7:0] == 0x0 |
| 12531 | OPC_CheckField, 32, 8, 0, // 26796: check Inst[39:32] == 0x0 |
| 12532 | OPC_CheckField, 52, 3, 0, // 26800: check Inst[54:52] == 0x0 |
| 12533 | OPC_Scope, 9, // 26804: try { |
| 12534 | OPC_CheckField, 48, 4, 0, // 26806: check Inst[51:48] == 0x0 |
| 12535 | OPC_Decode, 240, 75, 209, 1, // 26810: decode to VSLDvvr using decoder 209 |
| 12536 | // 26810: } else try { |
| 12537 | OPC_Decode, 246, 75, 255, 1, // 26815: decode to VSLDvvrm using decoder 255 |
| 12538 | // 26815: } |
| 12539 | // 26815: } |
| 12540 | // 26815: } // switch Inst[47] |
| 12541 | // 26815: } |
| 12542 | 202, 3, 185, 1, // 26820: case 0x1ca: { |
| 12543 | OPC_SwitchField, 52, 3, // 26824: switch Inst[54:52] { |
| 12544 | 0, 24, // 26827: case 0x0: { |
| 12545 | OPC_CheckField, 0, 8, 0, // 26829: check Inst[7:0] == 0x0 |
| 12546 | OPC_CheckField, 32, 16, 0, // 26833: check Inst[47:32] == 0x0 |
| 12547 | OPC_Scope, 9, // 26837: try { |
| 12548 | OPC_CheckField, 48, 4, 0, // 26839: check Inst[51:48] == 0x0 |
| 12549 | OPC_Decode, 148, 76, 217, 1, // 26843: decode to VSLLvv using decoder 217 |
| 12550 | // 26843: } else try { |
| 12551 | OPC_Decode, 154, 76, 218, 1, // 26848: decode to VSLLvvm using decoder 218 |
| 12552 | // 26848: } |
| 12553 | // 26848: } |
| 12554 | 2, 63, // 26853: case 0x2: { |
| 12555 | OPC_SwitchField, 47, 1, // 26855: switch Inst[47] { |
| 12556 | 0, 28, // 26858: case 0x0: { |
| 12557 | OPC_CheckField, 0, 8, 0, // 26860: check Inst[7:0] == 0x0 |
| 12558 | OPC_CheckField, 16, 8, 0, // 26864: check Inst[23:16] == 0x0 |
| 12559 | OPC_CheckField, 32, 8, 0, // 26868: check Inst[39:32] == 0x0 |
| 12560 | OPC_Scope, 9, // 26872: try { |
| 12561 | OPC_CheckField, 48, 4, 0, // 26874: check Inst[51:48] == 0x0 |
| 12562 | OPC_Decode, 252, 75, 219, 1, // 26878: decode to VSLLvi using decoder 219 |
| 12563 | // 26878: } else try { |
| 12564 | OPC_Decode, 130, 76, 220, 1, // 26883: decode to VSLLvim using decoder 220 |
| 12565 | // 26883: } |
| 12566 | // 26883: } |
| 12567 | 1, 0, // 26888: case 0x1: { |
| 12568 | OPC_CheckField, 0, 8, 0, // 26890: check Inst[7:0] == 0x0 |
| 12569 | OPC_CheckField, 16, 8, 0, // 26894: check Inst[23:16] == 0x0 |
| 12570 | OPC_CheckField, 32, 8, 0, // 26898: check Inst[39:32] == 0x0 |
| 12571 | OPC_Scope, 9, // 26902: try { |
| 12572 | OPC_CheckField, 48, 4, 0, // 26904: check Inst[51:48] == 0x0 |
| 12573 | OPC_Decode, 136, 76, 221, 1, // 26908: decode to VSLLvr using decoder 221 |
| 12574 | // 26908: } else try { |
| 12575 | OPC_Decode, 142, 76, 222, 1, // 26913: decode to VSLLvrm using decoder 222 |
| 12576 | // 26913: } |
| 12577 | // 26913: } |
| 12578 | // 26913: } // switch Inst[47] |
| 12579 | // 26913: } |
| 12580 | 4, 24, // 26918: case 0x4: { |
| 12581 | OPC_CheckField, 0, 8, 0, // 26920: check Inst[7:0] == 0x0 |
| 12582 | OPC_CheckField, 32, 16, 0, // 26924: check Inst[47:32] == 0x0 |
| 12583 | OPC_Scope, 9, // 26928: try { |
| 12584 | OPC_CheckField, 48, 4, 0, // 26930: check Inst[51:48] == 0x0 |
| 12585 | OPC_Decode, 243, 29, 217, 1, // 26934: decode to PVSLLLOvv using decoder 217 |
| 12586 | // 26934: } else try { |
| 12587 | OPC_Decode, 249, 29, 218, 1, // 26939: decode to PVSLLLOvvm using decoder 218 |
| 12588 | // 26939: } |
| 12589 | // 26939: } |
| 12590 | 6, 0, // 26944: case 0x6: { |
| 12591 | OPC_SwitchField, 47, 1, // 26946: switch Inst[47] { |
| 12592 | 0, 28, // 26949: case 0x0: { |
| 12593 | OPC_CheckField, 0, 8, 0, // 26951: check Inst[7:0] == 0x0 |
| 12594 | OPC_CheckField, 16, 8, 0, // 26955: check Inst[23:16] == 0x0 |
| 12595 | OPC_CheckField, 32, 8, 0, // 26959: check Inst[39:32] == 0x0 |
| 12596 | OPC_Scope, 9, // 26963: try { |
| 12597 | OPC_CheckField, 48, 4, 0, // 26965: check Inst[51:48] == 0x0 |
| 12598 | OPC_Decode, 219, 29, 219, 1, // 26969: decode to PVSLLLOvi using decoder 219 |
| 12599 | // 26969: } else try { |
| 12600 | OPC_Decode, 225, 29, 220, 1, // 26974: decode to PVSLLLOvim using decoder 220 |
| 12601 | // 26974: } |
| 12602 | // 26974: } |
| 12603 | 1, 0, // 26979: case 0x1: { |
| 12604 | OPC_CheckField, 0, 8, 0, // 26981: check Inst[7:0] == 0x0 |
| 12605 | OPC_CheckField, 16, 8, 0, // 26985: check Inst[23:16] == 0x0 |
| 12606 | OPC_CheckField, 32, 8, 0, // 26989: check Inst[39:32] == 0x0 |
| 12607 | OPC_Scope, 9, // 26993: try { |
| 12608 | OPC_CheckField, 48, 4, 0, // 26995: check Inst[51:48] == 0x0 |
| 12609 | OPC_Decode, 231, 29, 128, 2, // 26999: decode to PVSLLLOvr using decoder 256 |
| 12610 | // 26999: } else try { |
| 12611 | OPC_Decode, 237, 29, 129, 2, // 27004: decode to PVSLLLOvrm using decoder 257 |
| 12612 | // 27004: } |
| 12613 | // 27004: } |
| 12614 | // 27004: } // switch Inst[47] |
| 12615 | // 27004: } |
| 12616 | // 27004: } // switch Inst[54:52] |
| 12617 | // 27004: } |
| 12618 | 203, 3, 185, 1, // 27009: case 0x1cb: { |
| 12619 | OPC_SwitchField, 52, 3, // 27013: switch Inst[54:52] { |
| 12620 | 0, 24, // 27016: case 0x0: { |
| 12621 | OPC_CheckField, 0, 8, 0, // 27018: check Inst[7:0] == 0x0 |
| 12622 | OPC_CheckField, 32, 16, 0, // 27022: check Inst[47:32] == 0x0 |
| 12623 | OPC_Scope, 9, // 27026: try { |
| 12624 | OPC_CheckField, 48, 4, 0, // 27028: check Inst[51:48] == 0x0 |
| 12625 | OPC_Decode, 151, 30, 217, 1, // 27032: decode to PVSLLUPvv using decoder 217 |
| 12626 | // 27032: } else try { |
| 12627 | OPC_Decode, 157, 30, 218, 1, // 27037: decode to PVSLLUPvvm using decoder 218 |
| 12628 | // 27037: } |
| 12629 | // 27037: } |
| 12630 | 2, 63, // 27042: case 0x2: { |
| 12631 | OPC_SwitchField, 47, 1, // 27044: switch Inst[47] { |
| 12632 | 0, 28, // 27047: case 0x0: { |
| 12633 | OPC_CheckField, 0, 8, 0, // 27049: check Inst[7:0] == 0x0 |
| 12634 | OPC_CheckField, 16, 8, 0, // 27053: check Inst[23:16] == 0x0 |
| 12635 | OPC_CheckField, 32, 8, 0, // 27057: check Inst[39:32] == 0x0 |
| 12636 | OPC_Scope, 9, // 27061: try { |
| 12637 | OPC_CheckField, 48, 4, 0, // 27063: check Inst[51:48] == 0x0 |
| 12638 | OPC_Decode, 255, 29, 219, 1, // 27067: decode to PVSLLUPvi using decoder 219 |
| 12639 | // 27067: } else try { |
| 12640 | OPC_Decode, 133, 30, 220, 1, // 27072: decode to PVSLLUPvim using decoder 220 |
| 12641 | // 27072: } |
| 12642 | // 27072: } |
| 12643 | 1, 0, // 27077: case 0x1: { |
| 12644 | OPC_CheckField, 0, 8, 0, // 27079: check Inst[7:0] == 0x0 |
| 12645 | OPC_CheckField, 16, 8, 0, // 27083: check Inst[23:16] == 0x0 |
| 12646 | OPC_CheckField, 32, 8, 0, // 27087: check Inst[39:32] == 0x0 |
| 12647 | OPC_Scope, 9, // 27091: try { |
| 12648 | OPC_CheckField, 48, 4, 0, // 27093: check Inst[51:48] == 0x0 |
| 12649 | OPC_Decode, 139, 30, 130, 2, // 27097: decode to PVSLLUPvr using decoder 258 |
| 12650 | // 27097: } else try { |
| 12651 | OPC_Decode, 145, 30, 131, 2, // 27102: decode to PVSLLUPvrm using decoder 259 |
| 12652 | // 27102: } |
| 12653 | // 27102: } |
| 12654 | // 27102: } // switch Inst[47] |
| 12655 | // 27102: } |
| 12656 | 4, 24, // 27107: case 0x4: { |
| 12657 | OPC_CheckField, 0, 8, 0, // 27109: check Inst[7:0] == 0x0 |
| 12658 | OPC_CheckField, 32, 16, 0, // 27113: check Inst[47:32] == 0x0 |
| 12659 | OPC_Scope, 9, // 27117: try { |
| 12660 | OPC_CheckField, 48, 4, 0, // 27119: check Inst[51:48] == 0x0 |
| 12661 | OPC_Decode, 187, 30, 217, 1, // 27123: decode to PVSLLvv using decoder 217 |
| 12662 | // 27123: } else try { |
| 12663 | OPC_Decode, 193, 30, 132, 2, // 27128: decode to PVSLLvvm using decoder 260 |
| 12664 | // 27128: } |
| 12665 | // 27128: } |
| 12666 | 6, 0, // 27133: case 0x6: { |
| 12667 | OPC_SwitchField, 47, 1, // 27135: switch Inst[47] { |
| 12668 | 0, 28, // 27138: case 0x0: { |
| 12669 | OPC_CheckField, 0, 8, 0, // 27140: check Inst[7:0] == 0x0 |
| 12670 | OPC_CheckField, 16, 8, 0, // 27144: check Inst[23:16] == 0x0 |
| 12671 | OPC_CheckField, 32, 8, 0, // 27148: check Inst[39:32] == 0x0 |
| 12672 | OPC_Scope, 9, // 27152: try { |
| 12673 | OPC_CheckField, 48, 4, 0, // 27154: check Inst[51:48] == 0x0 |
| 12674 | OPC_Decode, 163, 30, 219, 1, // 27158: decode to PVSLLvi using decoder 219 |
| 12675 | // 27158: } else try { |
| 12676 | OPC_Decode, 169, 30, 133, 2, // 27163: decode to PVSLLvim using decoder 261 |
| 12677 | // 27163: } |
| 12678 | // 27163: } |
| 12679 | 1, 0, // 27168: case 0x1: { |
| 12680 | OPC_CheckField, 0, 8, 0, // 27170: check Inst[7:0] == 0x0 |
| 12681 | OPC_CheckField, 16, 8, 0, // 27174: check Inst[23:16] == 0x0 |
| 12682 | OPC_CheckField, 32, 8, 0, // 27178: check Inst[39:32] == 0x0 |
| 12683 | OPC_Scope, 9, // 27182: try { |
| 12684 | OPC_CheckField, 48, 4, 0, // 27184: check Inst[51:48] == 0x0 |
| 12685 | OPC_Decode, 175, 30, 221, 1, // 27188: decode to PVSLLvr using decoder 221 |
| 12686 | // 27188: } else try { |
| 12687 | OPC_Decode, 181, 30, 134, 2, // 27193: decode to PVSLLvrm using decoder 262 |
| 12688 | // 27193: } |
| 12689 | // 27193: } |
| 12690 | // 27193: } // switch Inst[47] |
| 12691 | // 27193: } |
| 12692 | // 27193: } // switch Inst[54:52] |
| 12693 | // 27193: } |
| 12694 | 204, 3, 185, 1, // 27198: case 0x1cc: { |
| 12695 | OPC_SwitchField, 52, 3, // 27202: switch Inst[54:52] { |
| 12696 | 0, 24, // 27205: case 0x0: { |
| 12697 | OPC_CheckField, 0, 8, 0, // 27207: check Inst[7:0] == 0x0 |
| 12698 | OPC_CheckField, 32, 16, 0, // 27211: check Inst[47:32] == 0x0 |
| 12699 | OPC_Scope, 9, // 27215: try { |
| 12700 | OPC_CheckField, 48, 4, 0, // 27217: check Inst[51:48] == 0x0 |
| 12701 | OPC_Decode, 180, 75, 217, 1, // 27221: decode to VSLAWSXvv using decoder 217 |
| 12702 | // 27221: } else try { |
| 12703 | OPC_Decode, 186, 75, 218, 1, // 27226: decode to VSLAWSXvvm using decoder 218 |
| 12704 | // 27226: } |
| 12705 | // 27226: } |
| 12706 | 2, 63, // 27231: case 0x2: { |
| 12707 | OPC_SwitchField, 47, 1, // 27233: switch Inst[47] { |
| 12708 | 0, 28, // 27236: case 0x0: { |
| 12709 | OPC_CheckField, 0, 8, 0, // 27238: check Inst[7:0] == 0x0 |
| 12710 | OPC_CheckField, 16, 8, 0, // 27242: check Inst[23:16] == 0x0 |
| 12711 | OPC_CheckField, 32, 8, 0, // 27246: check Inst[39:32] == 0x0 |
| 12712 | OPC_Scope, 9, // 27250: try { |
| 12713 | OPC_CheckField, 48, 4, 0, // 27252: check Inst[51:48] == 0x0 |
| 12714 | OPC_Decode, 156, 75, 219, 1, // 27256: decode to VSLAWSXvi using decoder 219 |
| 12715 | // 27256: } else try { |
| 12716 | OPC_Decode, 162, 75, 220, 1, // 27261: decode to VSLAWSXvim using decoder 220 |
| 12717 | // 27261: } |
| 12718 | // 27261: } |
| 12719 | 1, 0, // 27266: case 0x1: { |
| 12720 | OPC_CheckField, 0, 8, 0, // 27268: check Inst[7:0] == 0x0 |
| 12721 | OPC_CheckField, 16, 8, 0, // 27272: check Inst[23:16] == 0x0 |
| 12722 | OPC_CheckField, 32, 8, 0, // 27276: check Inst[39:32] == 0x0 |
| 12723 | OPC_Scope, 9, // 27280: try { |
| 12724 | OPC_CheckField, 48, 4, 0, // 27282: check Inst[51:48] == 0x0 |
| 12725 | OPC_Decode, 168, 75, 128, 2, // 27286: decode to VSLAWSXvr using decoder 256 |
| 12726 | // 27286: } else try { |
| 12727 | OPC_Decode, 174, 75, 129, 2, // 27291: decode to VSLAWSXvrm using decoder 257 |
| 12728 | // 27291: } |
| 12729 | // 27291: } |
| 12730 | // 27291: } // switch Inst[47] |
| 12731 | // 27291: } |
| 12732 | 4, 24, // 27296: case 0x4: { |
| 12733 | OPC_CheckField, 0, 8, 0, // 27298: check Inst[7:0] == 0x0 |
| 12734 | OPC_CheckField, 32, 16, 0, // 27302: check Inst[47:32] == 0x0 |
| 12735 | OPC_Scope, 9, // 27306: try { |
| 12736 | OPC_CheckField, 48, 4, 0, // 27308: check Inst[51:48] == 0x0 |
| 12737 | OPC_Decode, 135, 29, 217, 1, // 27312: decode to PVSLALOvv using decoder 217 |
| 12738 | // 27312: } else try { |
| 12739 | OPC_Decode, 141, 29, 218, 1, // 27317: decode to PVSLALOvvm using decoder 218 |
| 12740 | // 27317: } |
| 12741 | // 27317: } |
| 12742 | 6, 0, // 27322: case 0x6: { |
| 12743 | OPC_SwitchField, 47, 1, // 27324: switch Inst[47] { |
| 12744 | 0, 28, // 27327: case 0x0: { |
| 12745 | OPC_CheckField, 0, 8, 0, // 27329: check Inst[7:0] == 0x0 |
| 12746 | OPC_CheckField, 16, 8, 0, // 27333: check Inst[23:16] == 0x0 |
| 12747 | OPC_CheckField, 32, 8, 0, // 27337: check Inst[39:32] == 0x0 |
| 12748 | OPC_Scope, 9, // 27341: try { |
| 12749 | OPC_CheckField, 48, 4, 0, // 27343: check Inst[51:48] == 0x0 |
| 12750 | OPC_Decode, 239, 28, 219, 1, // 27347: decode to PVSLALOvi using decoder 219 |
| 12751 | // 27347: } else try { |
| 12752 | OPC_Decode, 245, 28, 220, 1, // 27352: decode to PVSLALOvim using decoder 220 |
| 12753 | // 27352: } |
| 12754 | // 27352: } |
| 12755 | 1, 0, // 27357: case 0x1: { |
| 12756 | OPC_CheckField, 0, 8, 0, // 27359: check Inst[7:0] == 0x0 |
| 12757 | OPC_CheckField, 16, 8, 0, // 27363: check Inst[23:16] == 0x0 |
| 12758 | OPC_CheckField, 32, 8, 0, // 27367: check Inst[39:32] == 0x0 |
| 12759 | OPC_Scope, 9, // 27371: try { |
| 12760 | OPC_CheckField, 48, 4, 0, // 27373: check Inst[51:48] == 0x0 |
| 12761 | OPC_Decode, 251, 28, 128, 2, // 27377: decode to PVSLALOvr using decoder 256 |
| 12762 | // 27377: } else try { |
| 12763 | OPC_Decode, 129, 29, 129, 2, // 27382: decode to PVSLALOvrm using decoder 257 |
| 12764 | // 27382: } |
| 12765 | // 27382: } |
| 12766 | // 27382: } // switch Inst[47] |
| 12767 | // 27382: } |
| 12768 | // 27382: } // switch Inst[54:52] |
| 12769 | // 27382: } |
| 12770 | 205, 3, 185, 1, // 27387: case 0x1cd: { |
| 12771 | OPC_SwitchField, 52, 3, // 27391: switch Inst[54:52] { |
| 12772 | 0, 24, // 27394: case 0x0: { |
| 12773 | OPC_CheckField, 0, 8, 0, // 27396: check Inst[7:0] == 0x0 |
| 12774 | OPC_CheckField, 32, 16, 0, // 27400: check Inst[47:32] == 0x0 |
| 12775 | OPC_Scope, 9, // 27404: try { |
| 12776 | OPC_CheckField, 48, 4, 0, // 27406: check Inst[51:48] == 0x0 |
| 12777 | OPC_Decode, 171, 29, 217, 1, // 27410: decode to PVSLAUPvv using decoder 217 |
| 12778 | // 27410: } else try { |
| 12779 | OPC_Decode, 177, 29, 218, 1, // 27415: decode to PVSLAUPvvm using decoder 218 |
| 12780 | // 27415: } |
| 12781 | // 27415: } |
| 12782 | 2, 63, // 27420: case 0x2: { |
| 12783 | OPC_SwitchField, 47, 1, // 27422: switch Inst[47] { |
| 12784 | 0, 28, // 27425: case 0x0: { |
| 12785 | OPC_CheckField, 0, 8, 0, // 27427: check Inst[7:0] == 0x0 |
| 12786 | OPC_CheckField, 16, 8, 0, // 27431: check Inst[23:16] == 0x0 |
| 12787 | OPC_CheckField, 32, 8, 0, // 27435: check Inst[39:32] == 0x0 |
| 12788 | OPC_Scope, 9, // 27439: try { |
| 12789 | OPC_CheckField, 48, 4, 0, // 27441: check Inst[51:48] == 0x0 |
| 12790 | OPC_Decode, 147, 29, 219, 1, // 27445: decode to PVSLAUPvi using decoder 219 |
| 12791 | // 27445: } else try { |
| 12792 | OPC_Decode, 153, 29, 220, 1, // 27450: decode to PVSLAUPvim using decoder 220 |
| 12793 | // 27450: } |
| 12794 | // 27450: } |
| 12795 | 1, 0, // 27455: case 0x1: { |
| 12796 | OPC_CheckField, 0, 8, 0, // 27457: check Inst[7:0] == 0x0 |
| 12797 | OPC_CheckField, 16, 8, 0, // 27461: check Inst[23:16] == 0x0 |
| 12798 | OPC_CheckField, 32, 8, 0, // 27465: check Inst[39:32] == 0x0 |
| 12799 | OPC_Scope, 9, // 27469: try { |
| 12800 | OPC_CheckField, 48, 4, 0, // 27471: check Inst[51:48] == 0x0 |
| 12801 | OPC_Decode, 159, 29, 130, 2, // 27475: decode to PVSLAUPvr using decoder 258 |
| 12802 | // 27475: } else try { |
| 12803 | OPC_Decode, 165, 29, 131, 2, // 27480: decode to PVSLAUPvrm using decoder 259 |
| 12804 | // 27480: } |
| 12805 | // 27480: } |
| 12806 | // 27480: } // switch Inst[47] |
| 12807 | // 27480: } |
| 12808 | 4, 24, // 27485: case 0x4: { |
| 12809 | OPC_CheckField, 0, 8, 0, // 27487: check Inst[7:0] == 0x0 |
| 12810 | OPC_CheckField, 32, 16, 0, // 27491: check Inst[47:32] == 0x0 |
| 12811 | OPC_Scope, 9, // 27495: try { |
| 12812 | OPC_CheckField, 48, 4, 0, // 27497: check Inst[51:48] == 0x0 |
| 12813 | OPC_Decode, 207, 29, 217, 1, // 27501: decode to PVSLAvv using decoder 217 |
| 12814 | // 27501: } else try { |
| 12815 | OPC_Decode, 213, 29, 132, 2, // 27506: decode to PVSLAvvm using decoder 260 |
| 12816 | // 27506: } |
| 12817 | // 27506: } |
| 12818 | 6, 0, // 27511: case 0x6: { |
| 12819 | OPC_SwitchField, 47, 1, // 27513: switch Inst[47] { |
| 12820 | 0, 28, // 27516: case 0x0: { |
| 12821 | OPC_CheckField, 0, 8, 0, // 27518: check Inst[7:0] == 0x0 |
| 12822 | OPC_CheckField, 16, 8, 0, // 27522: check Inst[23:16] == 0x0 |
| 12823 | OPC_CheckField, 32, 8, 0, // 27526: check Inst[39:32] == 0x0 |
| 12824 | OPC_Scope, 9, // 27530: try { |
| 12825 | OPC_CheckField, 48, 4, 0, // 27532: check Inst[51:48] == 0x0 |
| 12826 | OPC_Decode, 183, 29, 219, 1, // 27536: decode to PVSLAvi using decoder 219 |
| 12827 | // 27536: } else try { |
| 12828 | OPC_Decode, 189, 29, 133, 2, // 27541: decode to PVSLAvim using decoder 261 |
| 12829 | // 27541: } |
| 12830 | // 27541: } |
| 12831 | 1, 0, // 27546: case 0x1: { |
| 12832 | OPC_CheckField, 0, 8, 0, // 27548: check Inst[7:0] == 0x0 |
| 12833 | OPC_CheckField, 16, 8, 0, // 27552: check Inst[23:16] == 0x0 |
| 12834 | OPC_CheckField, 32, 8, 0, // 27556: check Inst[39:32] == 0x0 |
| 12835 | OPC_Scope, 9, // 27560: try { |
| 12836 | OPC_CheckField, 48, 4, 0, // 27562: check Inst[51:48] == 0x0 |
| 12837 | OPC_Decode, 195, 29, 221, 1, // 27566: decode to PVSLAvr using decoder 221 |
| 12838 | // 27566: } else try { |
| 12839 | OPC_Decode, 201, 29, 134, 2, // 27571: decode to PVSLAvrm using decoder 262 |
| 12840 | // 27571: } |
| 12841 | // 27571: } |
| 12842 | // 27571: } // switch Inst[47] |
| 12843 | // 27571: } |
| 12844 | // 27571: } // switch Inst[54:52] |
| 12845 | // 27571: } |
| 12846 | 206, 3, 63, // 27576: case 0x1ce: { |
| 12847 | OPC_SwitchField, 52, 3, // 27579: switch Inst[54:52] { |
| 12848 | 0, 28, // 27582: case 0x0: { |
| 12849 | OPC_CheckField, 0, 8, 0, // 27584: check Inst[7:0] == 0x0 |
| 12850 | OPC_CheckField, 16, 8, 0, // 27588: check Inst[23:16] == 0x0 |
| 12851 | OPC_CheckField, 32, 16, 0, // 27592: check Inst[47:32] == 0x0 |
| 12852 | OPC_Scope, 9, // 27596: try { |
| 12853 | OPC_CheckField, 48, 4, 0, // 27598: check Inst[51:48] == 0x0 |
| 12854 | OPC_Decode, 144, 63, 142, 1, // 27602: decode to VLDZv using decoder 142 |
| 12855 | // 27602: } else try { |
| 12856 | OPC_Decode, 150, 63, 143, 1, // 27607: decode to VLDZvm using decoder 143 |
| 12857 | // 27607: } |
| 12858 | // 27607: } |
| 12859 | 4, 0, // 27612: case 0x4: { |
| 12860 | OPC_CheckField, 0, 8, 0, // 27614: check Inst[7:0] == 0x0 |
| 12861 | OPC_CheckField, 16, 8, 0, // 27618: check Inst[23:16] == 0x0 |
| 12862 | OPC_CheckField, 32, 16, 0, // 27622: check Inst[47:32] == 0x0 |
| 12863 | OPC_Scope, 9, // 27626: try { |
| 12864 | OPC_CheckField, 48, 4, 0, // 27628: check Inst[51:48] == 0x0 |
| 12865 | OPC_Decode, 211, 24, 142, 1, // 27632: decode to PVLDZLOv using decoder 142 |
| 12866 | // 27632: } else try { |
| 12867 | OPC_Decode, 217, 24, 143, 1, // 27637: decode to PVLDZLOvm using decoder 143 |
| 12868 | // 27637: } |
| 12869 | // 27637: } |
| 12870 | // 27637: } // switch Inst[54:52] |
| 12871 | // 27637: } |
| 12872 | 207, 3, 63, // 27642: case 0x1cf: { |
| 12873 | OPC_SwitchField, 52, 3, // 27645: switch Inst[54:52] { |
| 12874 | 0, 28, // 27648: case 0x0: { |
| 12875 | OPC_CheckField, 0, 8, 0, // 27650: check Inst[7:0] == 0x0 |
| 12876 | OPC_CheckField, 16, 8, 0, // 27654: check Inst[23:16] == 0x0 |
| 12877 | OPC_CheckField, 32, 16, 0, // 27658: check Inst[47:32] == 0x0 |
| 12878 | OPC_Scope, 9, // 27662: try { |
| 12879 | OPC_CheckField, 48, 4, 0, // 27664: check Inst[51:48] == 0x0 |
| 12880 | OPC_Decode, 223, 24, 142, 1, // 27668: decode to PVLDZUPv using decoder 142 |
| 12881 | // 27668: } else try { |
| 12882 | OPC_Decode, 229, 24, 143, 1, // 27673: decode to PVLDZUPvm using decoder 143 |
| 12883 | // 27673: } |
| 12884 | // 27673: } |
| 12885 | 4, 0, // 27678: case 0x4: { |
| 12886 | OPC_CheckField, 0, 8, 0, // 27680: check Inst[7:0] == 0x0 |
| 12887 | OPC_CheckField, 16, 8, 0, // 27684: check Inst[23:16] == 0x0 |
| 12888 | OPC_CheckField, 32, 16, 0, // 27688: check Inst[47:32] == 0x0 |
| 12889 | OPC_Scope, 9, // 27692: try { |
| 12890 | OPC_CheckField, 48, 4, 0, // 27694: check Inst[51:48] == 0x0 |
| 12891 | OPC_Decode, 235, 24, 142, 1, // 27698: decode to PVLDZv using decoder 142 |
| 12892 | // 27698: } else try { |
| 12893 | OPC_Decode, 241, 24, 183, 1, // 27703: decode to PVLDZvm using decoder 183 |
| 12894 | // 27703: } |
| 12895 | // 27703: } |
| 12896 | // 27703: } // switch Inst[54:52] |
| 12897 | // 27703: } |
| 12898 | 208, 3, 81, // 27708: case 0x1d0: { |
| 12899 | OPC_SwitchField, 52, 3, // 27711: switch Inst[54:52] { |
| 12900 | 0, 24, // 27714: case 0x0: { |
| 12901 | OPC_CheckField, 0, 8, 0, // 27716: check Inst[7:0] == 0x0 |
| 12902 | OPC_CheckField, 32, 16, 0, // 27720: check Inst[47:32] == 0x0 |
| 12903 | OPC_Scope, 9, // 27724: try { |
| 12904 | OPC_CheckField, 48, 4, 0, // 27726: check Inst[51:48] == 0x0 |
| 12905 | OPC_Decode, 148, 40, 181, 1, // 27730: decode to VCVTWDSXv using decoder 181 |
| 12906 | // 27730: } else try { |
| 12907 | OPC_Decode, 154, 40, 182, 1, // 27735: decode to VCVTWDSXvm using decoder 182 |
| 12908 | // 27735: } |
| 12909 | // 27735: } |
| 12910 | 4, 24, // 27740: case 0x4: { |
| 12911 | OPC_CheckField, 0, 8, 0, // 27742: check Inst[7:0] == 0x0 |
| 12912 | OPC_CheckField, 32, 16, 0, // 27746: check Inst[47:32] == 0x0 |
| 12913 | OPC_Scope, 9, // 27750: try { |
| 12914 | OPC_CheckField, 48, 4, 0, // 27752: check Inst[51:48] == 0x0 |
| 12915 | OPC_Decode, 160, 40, 181, 1, // 27756: decode to VCVTWDZXv using decoder 181 |
| 12916 | // 27756: } else try { |
| 12917 | OPC_Decode, 166, 40, 182, 1, // 27761: decode to VCVTWDZXvm using decoder 182 |
| 12918 | // 27761: } |
| 12919 | // 27761: } |
| 12920 | 5, 0, // 27766: case 0x5: { |
| 12921 | OPC_CheckField, 0, 8, 0, // 27768: check Inst[7:0] == 0x0 |
| 12922 | OPC_CheckField, 32, 16, 0, // 27772: check Inst[47:32] == 0x0 |
| 12923 | OPC_Scope, 9, // 27776: try { |
| 12924 | OPC_CheckField, 48, 4, 0, // 27778: check Inst[51:48] == 0x0 |
| 12925 | OPC_Decode, 163, 12, 181, 1, // 27782: decode to PVCVTWSLOv using decoder 181 |
| 12926 | // 27782: } else try { |
| 12927 | OPC_Decode, 169, 12, 182, 1, // 27787: decode to PVCVTWSLOvm using decoder 182 |
| 12928 | // 27787: } |
| 12929 | // 27787: } |
| 12930 | // 27787: } // switch Inst[54:52] |
| 12931 | // 27787: } |
| 12932 | 209, 3, 107, // 27792: case 0x1d1: { |
| 12933 | OPC_SwitchField, 52, 3, // 27795: switch Inst[54:52] { |
| 12934 | 0, 24, // 27798: case 0x0: { |
| 12935 | OPC_CheckField, 0, 8, 0, // 27800: check Inst[7:0] == 0x0 |
| 12936 | OPC_CheckField, 32, 16, 0, // 27804: check Inst[47:32] == 0x0 |
| 12937 | OPC_Scope, 9, // 27808: try { |
| 12938 | OPC_CheckField, 48, 4, 0, // 27810: check Inst[51:48] == 0x0 |
| 12939 | OPC_Decode, 172, 40, 181, 1, // 27814: decode to VCVTWSSXv using decoder 181 |
| 12940 | // 27814: } else try { |
| 12941 | OPC_Decode, 178, 40, 182, 1, // 27819: decode to VCVTWSSXvm using decoder 182 |
| 12942 | // 27819: } |
| 12943 | // 27819: } |
| 12944 | 1, 24, // 27824: case 0x1: { |
| 12945 | OPC_CheckField, 0, 8, 0, // 27826: check Inst[7:0] == 0x0 |
| 12946 | OPC_CheckField, 32, 16, 0, // 27830: check Inst[47:32] == 0x0 |
| 12947 | OPC_Scope, 9, // 27834: try { |
| 12948 | OPC_CheckField, 48, 4, 0, // 27836: check Inst[51:48] == 0x0 |
| 12949 | OPC_Decode, 175, 12, 181, 1, // 27840: decode to PVCVTWSUPv using decoder 181 |
| 12950 | // 27840: } else try { |
| 12951 | OPC_Decode, 181, 12, 182, 1, // 27845: decode to PVCVTWSUPvm using decoder 182 |
| 12952 | // 27845: } |
| 12953 | // 27845: } |
| 12954 | 4, 24, // 27850: case 0x4: { |
| 12955 | OPC_CheckField, 0, 8, 0, // 27852: check Inst[7:0] == 0x0 |
| 12956 | OPC_CheckField, 32, 16, 0, // 27856: check Inst[47:32] == 0x0 |
| 12957 | OPC_Scope, 9, // 27860: try { |
| 12958 | OPC_CheckField, 48, 4, 0, // 27862: check Inst[51:48] == 0x0 |
| 12959 | OPC_Decode, 184, 40, 181, 1, // 27866: decode to VCVTWSZXv using decoder 181 |
| 12960 | // 27866: } else try { |
| 12961 | OPC_Decode, 190, 40, 182, 1, // 27871: decode to VCVTWSZXvm using decoder 182 |
| 12962 | // 27871: } |
| 12963 | // 27871: } |
| 12964 | 5, 0, // 27876: case 0x5: { |
| 12965 | OPC_CheckField, 0, 8, 0, // 27878: check Inst[7:0] == 0x0 |
| 12966 | OPC_CheckField, 32, 16, 0, // 27882: check Inst[47:32] == 0x0 |
| 12967 | OPC_Scope, 9, // 27886: try { |
| 12968 | OPC_CheckField, 48, 4, 0, // 27888: check Inst[51:48] == 0x0 |
| 12969 | OPC_Decode, 187, 12, 181, 1, // 27892: decode to PVCVTWSv using decoder 181 |
| 12970 | // 27892: } else try { |
| 12971 | OPC_Decode, 193, 12, 135, 2, // 27897: decode to PVCVTWSvm using decoder 263 |
| 12972 | // 27897: } |
| 12973 | // 27897: } |
| 12974 | // 27897: } // switch Inst[54:52] |
| 12975 | // 27897: } |
| 12976 | 210, 3, 160, 2, // 27902: case 0x1d2: { |
| 12977 | OPC_SwitchField, 52, 3, // 27906: switch Inst[54:52] { |
| 12978 | 0, 22, // 27909: case 0x0: { |
| 12979 | OPC_CheckField, 0, 8, 0, // 27911: check Inst[7:0] == 0x0 |
| 12980 | OPC_CheckField, 32, 16, 0, // 27915: check Inst[47:32] == 0x0 |
| 12981 | OPC_Scope, 8, // 27919: try { |
| 12982 | OPC_CheckField, 48, 4, 0, // 27921: check Inst[51:48] == 0x0 |
| 12983 | OPC_Decode, 168, 42, 121, // 27925: decode to VDIVULvv using decoder 121 |
| 12984 | // 27925: } else try { |
| 12985 | OPC_Decode, 174, 42, 122, // 27929: decode to VDIVULvvm using decoder 122 |
| 12986 | // 27929: } |
| 12987 | // 27929: } |
| 12988 | 1, 55, // 27933: case 0x1: { |
| 12989 | OPC_SwitchField, 47, 1, // 27935: switch Inst[47] { |
| 12990 | 0, 24, // 27938: case 0x0: { |
| 12991 | OPC_CheckField, 0, 16, 0, // 27940: check Inst[15:0] == 0x0 |
| 12992 | OPC_CheckField, 32, 8, 0, // 27944: check Inst[39:32] == 0x0 |
| 12993 | OPC_Scope, 9, // 27948: try { |
| 12994 | OPC_CheckField, 48, 4, 0, // 27950: check Inst[51:48] == 0x0 |
| 12995 | OPC_Decode, 144, 42, 214, 1, // 27954: decode to VDIVULvi using decoder 214 |
| 12996 | // 27954: } else try { |
| 12997 | OPC_Decode, 150, 42, 231, 1, // 27959: decode to VDIVULvim using decoder 231 |
| 12998 | // 27959: } |
| 12999 | // 27959: } |
| 13000 | 1, 0, // 27964: case 0x1: { |
| 13001 | OPC_CheckField, 0, 16, 0, // 27966: check Inst[15:0] == 0x0 |
| 13002 | OPC_CheckField, 32, 8, 0, // 27970: check Inst[39:32] == 0x0 |
| 13003 | OPC_Scope, 9, // 27974: try { |
| 13004 | OPC_CheckField, 48, 4, 0, // 27976: check Inst[51:48] == 0x0 |
| 13005 | OPC_Decode, 156, 42, 215, 1, // 27980: decode to VDIVULvr using decoder 215 |
| 13006 | // 27980: } else try { |
| 13007 | OPC_Decode, 162, 42, 232, 1, // 27985: decode to VDIVULvrm using decoder 232 |
| 13008 | // 27985: } |
| 13009 | // 27985: } |
| 13010 | // 27985: } // switch Inst[47] |
| 13011 | // 27985: } |
| 13012 | 2, 60, // 27990: case 0x2: { |
| 13013 | OPC_SwitchField, 47, 1, // 27992: switch Inst[47] { |
| 13014 | 0, 26, // 27995: case 0x0: { |
| 13015 | OPC_CheckField, 0, 8, 0, // 27997: check Inst[7:0] == 0x0 |
| 13016 | OPC_CheckField, 16, 8, 0, // 28001: check Inst[23:16] == 0x0 |
| 13017 | OPC_CheckField, 32, 8, 0, // 28005: check Inst[39:32] == 0x0 |
| 13018 | OPC_Scope, 8, // 28009: try { |
| 13019 | OPC_CheckField, 48, 4, 0, // 28011: check Inst[51:48] == 0x0 |
| 13020 | OPC_Decode, 248, 41, 123, // 28015: decode to VDIVULiv using decoder 123 |
| 13021 | // 28015: } else try { |
| 13022 | OPC_Decode, 254, 41, 124, // 28019: decode to VDIVULivm using decoder 124 |
| 13023 | // 28019: } |
| 13024 | // 28019: } |
| 13025 | 1, 0, // 28023: case 0x1: { |
| 13026 | OPC_CheckField, 0, 8, 0, // 28025: check Inst[7:0] == 0x0 |
| 13027 | OPC_CheckField, 16, 8, 0, // 28029: check Inst[23:16] == 0x0 |
| 13028 | OPC_CheckField, 32, 8, 0, // 28033: check Inst[39:32] == 0x0 |
| 13029 | OPC_Scope, 8, // 28037: try { |
| 13030 | OPC_CheckField, 48, 4, 0, // 28039: check Inst[51:48] == 0x0 |
| 13031 | OPC_Decode, 132, 42, 127, // 28043: decode to VDIVULrv using decoder 127 |
| 13032 | // 28043: } else try { |
| 13033 | OPC_Decode, 138, 42, 128, 1, // 28047: decode to VDIVULrvm using decoder 128 |
| 13034 | // 28047: } |
| 13035 | // 28047: } |
| 13036 | // 28047: } // switch Inst[47] |
| 13037 | // 28047: } |
| 13038 | 4, 22, // 28052: case 0x4: { |
| 13039 | OPC_CheckField, 0, 8, 0, // 28054: check Inst[7:0] == 0x0 |
| 13040 | OPC_CheckField, 32, 16, 0, // 28058: check Inst[47:32] == 0x0 |
| 13041 | OPC_Scope, 8, // 28062: try { |
| 13042 | OPC_CheckField, 48, 4, 0, // 28064: check Inst[51:48] == 0x0 |
| 13043 | OPC_Decode, 228, 42, 121, // 28068: decode to VDIVUWvv using decoder 121 |
| 13044 | // 28068: } else try { |
| 13045 | OPC_Decode, 234, 42, 122, // 28072: decode to VDIVUWvvm using decoder 122 |
| 13046 | // 28072: } |
| 13047 | // 28072: } |
| 13048 | 5, 55, // 28076: case 0x5: { |
| 13049 | OPC_SwitchField, 47, 1, // 28078: switch Inst[47] { |
| 13050 | 0, 24, // 28081: case 0x0: { |
| 13051 | OPC_CheckField, 0, 16, 0, // 28083: check Inst[15:0] == 0x0 |
| 13052 | OPC_CheckField, 32, 8, 0, // 28087: check Inst[39:32] == 0x0 |
| 13053 | OPC_Scope, 9, // 28091: try { |
| 13054 | OPC_CheckField, 48, 4, 0, // 28093: check Inst[51:48] == 0x0 |
| 13055 | OPC_Decode, 204, 42, 214, 1, // 28097: decode to VDIVUWvi using decoder 214 |
| 13056 | // 28097: } else try { |
| 13057 | OPC_Decode, 210, 42, 231, 1, // 28102: decode to VDIVUWvim using decoder 231 |
| 13058 | // 28102: } |
| 13059 | // 28102: } |
| 13060 | 1, 0, // 28107: case 0x1: { |
| 13061 | OPC_CheckField, 0, 16, 0, // 28109: check Inst[15:0] == 0x0 |
| 13062 | OPC_CheckField, 32, 8, 0, // 28113: check Inst[39:32] == 0x0 |
| 13063 | OPC_Scope, 9, // 28117: try { |
| 13064 | OPC_CheckField, 48, 4, 0, // 28119: check Inst[51:48] == 0x0 |
| 13065 | OPC_Decode, 216, 42, 136, 2, // 28123: decode to VDIVUWvr using decoder 264 |
| 13066 | // 28123: } else try { |
| 13067 | OPC_Decode, 222, 42, 137, 2, // 28128: decode to VDIVUWvrm using decoder 265 |
| 13068 | // 28128: } |
| 13069 | // 28128: } |
| 13070 | // 28128: } // switch Inst[47] |
| 13071 | // 28128: } |
| 13072 | 6, 0, // 28133: case 0x6: { |
| 13073 | OPC_SwitchField, 47, 1, // 28135: switch Inst[47] { |
| 13074 | 0, 26, // 28138: case 0x0: { |
| 13075 | OPC_CheckField, 0, 8, 0, // 28140: check Inst[7:0] == 0x0 |
| 13076 | OPC_CheckField, 16, 8, 0, // 28144: check Inst[23:16] == 0x0 |
| 13077 | OPC_CheckField, 32, 8, 0, // 28148: check Inst[39:32] == 0x0 |
| 13078 | OPC_Scope, 8, // 28152: try { |
| 13079 | OPC_CheckField, 48, 4, 0, // 28154: check Inst[51:48] == 0x0 |
| 13080 | OPC_Decode, 180, 42, 123, // 28158: decode to VDIVUWiv using decoder 123 |
| 13081 | // 28158: } else try { |
| 13082 | OPC_Decode, 186, 42, 124, // 28162: decode to VDIVUWivm using decoder 124 |
| 13083 | // 28162: } |
| 13084 | // 28162: } |
| 13085 | 1, 0, // 28166: case 0x1: { |
| 13086 | OPC_CheckField, 0, 8, 0, // 28168: check Inst[7:0] == 0x0 |
| 13087 | OPC_CheckField, 16, 8, 0, // 28172: check Inst[23:16] == 0x0 |
| 13088 | OPC_CheckField, 32, 8, 0, // 28176: check Inst[39:32] == 0x0 |
| 13089 | OPC_Scope, 8, // 28180: try { |
| 13090 | OPC_CheckField, 48, 4, 0, // 28182: check Inst[51:48] == 0x0 |
| 13091 | OPC_Decode, 192, 42, 125, // 28186: decode to VDIVUWrv using decoder 125 |
| 13092 | // 28186: } else try { |
| 13093 | OPC_Decode, 198, 42, 126, // 28190: decode to VDIVUWrvm using decoder 126 |
| 13094 | // 28190: } |
| 13095 | // 28190: } |
| 13096 | // 28190: } // switch Inst[47] |
| 13097 | // 28190: } |
| 13098 | // 28190: } // switch Inst[54:52] |
| 13099 | // 28190: } |
| 13100 | 212, 3, 51, // 28194: case 0x1d4: { |
| 13101 | OPC_SwitchField, 52, 3, // 28197: switch Inst[54:52] { |
| 13102 | 0, 22, // 28200: case 0x0: { |
| 13103 | OPC_CheckField, 0, 16, 0, // 28202: check Inst[15:0] == 0x0 |
| 13104 | OPC_CheckField, 32, 16, 0, // 28206: check Inst[47:32] == 0x0 |
| 13105 | OPC_Scope, 8, // 28210: try { |
| 13106 | OPC_CheckField, 48, 4, 0, // 28212: check Inst[51:48] == 0x0 |
| 13107 | OPC_Decode, 200, 83, 119, // 28216: decode to VSUMWSXv using decoder 119 |
| 13108 | // 28216: } else try { |
| 13109 | OPC_Decode, 206, 83, 120, // 28220: decode to VSUMWSXvm using decoder 120 |
| 13110 | // 28220: } |
| 13111 | // 28220: } |
| 13112 | 4, 0, // 28224: case 0x4: { |
| 13113 | OPC_CheckField, 0, 16, 0, // 28226: check Inst[15:0] == 0x0 |
| 13114 | OPC_CheckField, 32, 16, 0, // 28230: check Inst[47:32] == 0x0 |
| 13115 | OPC_Scope, 8, // 28234: try { |
| 13116 | OPC_CheckField, 48, 4, 0, // 28236: check Inst[51:48] == 0x0 |
| 13117 | OPC_Decode, 212, 83, 119, // 28240: decode to VSUMWZXv using decoder 119 |
| 13118 | // 28240: } else try { |
| 13119 | OPC_Decode, 218, 83, 120, // 28244: decode to VSUMWZXvm using decoder 120 |
| 13120 | // 28244: } |
| 13121 | // 28244: } |
| 13122 | // 28244: } // switch Inst[54:52] |
| 13123 | // 28244: } |
| 13124 | 214, 3, 159, 2, // 28248: case 0x1d6: { |
| 13125 | OPC_SwitchField, 52, 3, // 28252: switch Inst[54:52] { |
| 13126 | 0, 22, // 28255: case 0x0: { |
| 13127 | OPC_CheckField, 0, 8, 0, // 28257: check Inst[7:0] == 0x0 |
| 13128 | OPC_CheckField, 32, 16, 0, // 28261: check Inst[47:32] == 0x0 |
| 13129 | OPC_Scope, 8, // 28265: try { |
| 13130 | OPC_CheckField, 48, 4, 0, // 28267: check Inst[51:48] == 0x0 |
| 13131 | OPC_Decode, 176, 41, 121, // 28271: decode to VDIVSWSXvv using decoder 121 |
| 13132 | // 28271: } else try { |
| 13133 | OPC_Decode, 182, 41, 122, // 28275: decode to VDIVSWSXvvm using decoder 122 |
| 13134 | // 28275: } |
| 13135 | // 28275: } |
| 13136 | 1, 55, // 28279: case 0x1: { |
| 13137 | OPC_SwitchField, 47, 1, // 28281: switch Inst[47] { |
| 13138 | 0, 24, // 28284: case 0x0: { |
| 13139 | OPC_CheckField, 0, 16, 0, // 28286: check Inst[15:0] == 0x0 |
| 13140 | OPC_CheckField, 32, 8, 0, // 28290: check Inst[39:32] == 0x0 |
| 13141 | OPC_Scope, 9, // 28294: try { |
| 13142 | OPC_CheckField, 48, 4, 0, // 28296: check Inst[51:48] == 0x0 |
| 13143 | OPC_Decode, 152, 41, 214, 1, // 28300: decode to VDIVSWSXvi using decoder 214 |
| 13144 | // 28300: } else try { |
| 13145 | OPC_Decode, 158, 41, 231, 1, // 28305: decode to VDIVSWSXvim using decoder 231 |
| 13146 | // 28305: } |
| 13147 | // 28305: } |
| 13148 | 1, 0, // 28310: case 0x1: { |
| 13149 | OPC_CheckField, 0, 16, 0, // 28312: check Inst[15:0] == 0x0 |
| 13150 | OPC_CheckField, 32, 8, 0, // 28316: check Inst[39:32] == 0x0 |
| 13151 | OPC_Scope, 9, // 28320: try { |
| 13152 | OPC_CheckField, 48, 4, 0, // 28322: check Inst[51:48] == 0x0 |
| 13153 | OPC_Decode, 164, 41, 136, 2, // 28326: decode to VDIVSWSXvr using decoder 264 |
| 13154 | // 28326: } else try { |
| 13155 | OPC_Decode, 170, 41, 137, 2, // 28331: decode to VDIVSWSXvrm using decoder 265 |
| 13156 | // 28331: } |
| 13157 | // 28331: } |
| 13158 | // 28331: } // switch Inst[47] |
| 13159 | // 28331: } |
| 13160 | 2, 59, // 28336: case 0x2: { |
| 13161 | OPC_SwitchField, 47, 1, // 28338: switch Inst[47] { |
| 13162 | 0, 26, // 28341: case 0x0: { |
| 13163 | OPC_CheckField, 0, 8, 0, // 28343: check Inst[7:0] == 0x0 |
| 13164 | OPC_CheckField, 16, 8, 0, // 28347: check Inst[23:16] == 0x0 |
| 13165 | OPC_CheckField, 32, 8, 0, // 28351: check Inst[39:32] == 0x0 |
| 13166 | OPC_Scope, 8, // 28355: try { |
| 13167 | OPC_CheckField, 48, 4, 0, // 28357: check Inst[51:48] == 0x0 |
| 13168 | OPC_Decode, 128, 41, 123, // 28361: decode to VDIVSWSXiv using decoder 123 |
| 13169 | // 28361: } else try { |
| 13170 | OPC_Decode, 134, 41, 124, // 28365: decode to VDIVSWSXivm using decoder 124 |
| 13171 | // 28365: } |
| 13172 | // 28365: } |
| 13173 | 1, 0, // 28369: case 0x1: { |
| 13174 | OPC_CheckField, 0, 8, 0, // 28371: check Inst[7:0] == 0x0 |
| 13175 | OPC_CheckField, 16, 8, 0, // 28375: check Inst[23:16] == 0x0 |
| 13176 | OPC_CheckField, 32, 8, 0, // 28379: check Inst[39:32] == 0x0 |
| 13177 | OPC_Scope, 8, // 28383: try { |
| 13178 | OPC_CheckField, 48, 4, 0, // 28385: check Inst[51:48] == 0x0 |
| 13179 | OPC_Decode, 140, 41, 125, // 28389: decode to VDIVSWSXrv using decoder 125 |
| 13180 | // 28389: } else try { |
| 13181 | OPC_Decode, 146, 41, 126, // 28393: decode to VDIVSWSXrvm using decoder 126 |
| 13182 | // 28393: } |
| 13183 | // 28393: } |
| 13184 | // 28393: } // switch Inst[47] |
| 13185 | // 28393: } |
| 13186 | 4, 22, // 28397: case 0x4: { |
| 13187 | OPC_CheckField, 0, 8, 0, // 28399: check Inst[7:0] == 0x0 |
| 13188 | OPC_CheckField, 32, 16, 0, // 28403: check Inst[47:32] == 0x0 |
| 13189 | OPC_Scope, 8, // 28407: try { |
| 13190 | OPC_CheckField, 48, 4, 0, // 28409: check Inst[51:48] == 0x0 |
| 13191 | OPC_Decode, 236, 41, 121, // 28413: decode to VDIVSWZXvv using decoder 121 |
| 13192 | // 28413: } else try { |
| 13193 | OPC_Decode, 242, 41, 122, // 28417: decode to VDIVSWZXvvm using decoder 122 |
| 13194 | // 28417: } |
| 13195 | // 28417: } |
| 13196 | 5, 55, // 28421: case 0x5: { |
| 13197 | OPC_SwitchField, 47, 1, // 28423: switch Inst[47] { |
| 13198 | 0, 24, // 28426: case 0x0: { |
| 13199 | OPC_CheckField, 0, 16, 0, // 28428: check Inst[15:0] == 0x0 |
| 13200 | OPC_CheckField, 32, 8, 0, // 28432: check Inst[39:32] == 0x0 |
| 13201 | OPC_Scope, 9, // 28436: try { |
| 13202 | OPC_CheckField, 48, 4, 0, // 28438: check Inst[51:48] == 0x0 |
| 13203 | OPC_Decode, 212, 41, 214, 1, // 28442: decode to VDIVSWZXvi using decoder 214 |
| 13204 | // 28442: } else try { |
| 13205 | OPC_Decode, 218, 41, 231, 1, // 28447: decode to VDIVSWZXvim using decoder 231 |
| 13206 | // 28447: } |
| 13207 | // 28447: } |
| 13208 | 1, 0, // 28452: case 0x1: { |
| 13209 | OPC_CheckField, 0, 16, 0, // 28454: check Inst[15:0] == 0x0 |
| 13210 | OPC_CheckField, 32, 8, 0, // 28458: check Inst[39:32] == 0x0 |
| 13211 | OPC_Scope, 9, // 28462: try { |
| 13212 | OPC_CheckField, 48, 4, 0, // 28464: check Inst[51:48] == 0x0 |
| 13213 | OPC_Decode, 224, 41, 136, 2, // 28468: decode to VDIVSWZXvr using decoder 264 |
| 13214 | // 28468: } else try { |
| 13215 | OPC_Decode, 230, 41, 137, 2, // 28473: decode to VDIVSWZXvrm using decoder 265 |
| 13216 | // 28473: } |
| 13217 | // 28473: } |
| 13218 | // 28473: } // switch Inst[47] |
| 13219 | // 28473: } |
| 13220 | 6, 0, // 28478: case 0x6: { |
| 13221 | OPC_SwitchField, 47, 1, // 28480: switch Inst[47] { |
| 13222 | 0, 26, // 28483: case 0x0: { |
| 13223 | OPC_CheckField, 0, 8, 0, // 28485: check Inst[7:0] == 0x0 |
| 13224 | OPC_CheckField, 16, 8, 0, // 28489: check Inst[23:16] == 0x0 |
| 13225 | OPC_CheckField, 32, 8, 0, // 28493: check Inst[39:32] == 0x0 |
| 13226 | OPC_Scope, 8, // 28497: try { |
| 13227 | OPC_CheckField, 48, 4, 0, // 28499: check Inst[51:48] == 0x0 |
| 13228 | OPC_Decode, 188, 41, 123, // 28503: decode to VDIVSWZXiv using decoder 123 |
| 13229 | // 28503: } else try { |
| 13230 | OPC_Decode, 194, 41, 124, // 28507: decode to VDIVSWZXivm using decoder 124 |
| 13231 | // 28507: } |
| 13232 | // 28507: } |
| 13233 | 1, 0, // 28511: case 0x1: { |
| 13234 | OPC_CheckField, 0, 8, 0, // 28513: check Inst[7:0] == 0x0 |
| 13235 | OPC_CheckField, 16, 8, 0, // 28517: check Inst[23:16] == 0x0 |
| 13236 | OPC_CheckField, 32, 8, 0, // 28521: check Inst[39:32] == 0x0 |
| 13237 | OPC_Scope, 8, // 28525: try { |
| 13238 | OPC_CheckField, 48, 4, 0, // 28527: check Inst[51:48] == 0x0 |
| 13239 | OPC_Decode, 200, 41, 125, // 28531: decode to VDIVSWZXrv using decoder 125 |
| 13240 | // 28531: } else try { |
| 13241 | OPC_Decode, 206, 41, 126, // 28535: decode to VDIVSWZXrvm using decoder 126 |
| 13242 | // 28535: } |
| 13243 | // 28535: } |
| 13244 | // 28535: } // switch Inst[47] |
| 13245 | // 28535: } |
| 13246 | // 28535: } // switch Inst[54:52] |
| 13247 | // 28535: } |
| 13248 | 216, 3, 26, // 28539: case 0x1d8: { |
| 13249 | OPC_CheckField, 0, 16, 0, // 28542: check Inst[15:0] == 0x0 |
| 13250 | OPC_CheckField, 32, 16, 0, // 28546: check Inst[47:32] == 0x0 |
| 13251 | OPC_CheckField, 52, 3, 0, // 28550: check Inst[54:52] == 0x0 |
| 13252 | OPC_Scope, 8, // 28554: try { |
| 13253 | OPC_CheckField, 48, 4, 0, // 28556: check Inst[51:48] == 0x0 |
| 13254 | OPC_Decode, 144, 54, 119, // 28560: decode to VFSUMDv using decoder 119 |
| 13255 | // 28560: } else try { |
| 13256 | OPC_Decode, 150, 54, 120, // 28564: decode to VFSUMDvm using decoder 120 |
| 13257 | // 28564: } |
| 13258 | // 28564: } |
| 13259 | 217, 3, 26, // 28568: case 0x1d9: { |
| 13260 | OPC_CheckField, 0, 16, 0, // 28571: check Inst[15:0] == 0x0 |
| 13261 | OPC_CheckField, 32, 16, 0, // 28575: check Inst[47:32] == 0x0 |
| 13262 | OPC_CheckField, 52, 3, 0, // 28579: check Inst[54:52] == 0x0 |
| 13263 | OPC_Scope, 8, // 28583: try { |
| 13264 | OPC_CheckField, 48, 4, 0, // 28585: check Inst[51:48] == 0x0 |
| 13265 | OPC_Decode, 156, 54, 119, // 28589: decode to VFSUMSv using decoder 119 |
| 13266 | // 28589: } else try { |
| 13267 | OPC_Decode, 162, 54, 120, // 28593: decode to VFSUMSvm using decoder 120 |
| 13268 | // 28593: } |
| 13269 | // 28593: } |
| 13270 | 218, 3, 26, // 28597: case 0x1da: { |
| 13271 | OPC_CheckField, 0, 16, 0, // 28600: check Inst[15:0] == 0x0 |
| 13272 | OPC_CheckField, 32, 16, 0, // 28604: check Inst[47:32] == 0x0 |
| 13273 | OPC_CheckField, 52, 3, 0, // 28608: check Inst[54:52] == 0x0 |
| 13274 | OPC_Scope, 8, // 28612: try { |
| 13275 | OPC_CheckField, 48, 4, 0, // 28614: check Inst[51:48] == 0x0 |
| 13276 | OPC_Decode, 176, 53, 119, // 28618: decode to VFSQRTDv using decoder 119 |
| 13277 | // 28618: } else try { |
| 13278 | OPC_Decode, 182, 53, 120, // 28622: decode to VFSQRTDvm using decoder 120 |
| 13279 | // 28622: } |
| 13280 | // 28622: } |
| 13281 | 219, 3, 26, // 28626: case 0x1db: { |
| 13282 | OPC_CheckField, 0, 16, 0, // 28629: check Inst[15:0] == 0x0 |
| 13283 | OPC_CheckField, 32, 16, 0, // 28633: check Inst[47:32] == 0x0 |
| 13284 | OPC_CheckField, 52, 3, 0, // 28637: check Inst[54:52] == 0x0 |
| 13285 | OPC_Scope, 8, // 28641: try { |
| 13286 | OPC_CheckField, 48, 4, 0, // 28643: check Inst[51:48] == 0x0 |
| 13287 | OPC_Decode, 188, 53, 119, // 28647: decode to VFSQRTSv using decoder 119 |
| 13288 | // 28647: } else try { |
| 13289 | OPC_Decode, 194, 53, 120, // 28651: decode to VFSQRTSvm using decoder 120 |
| 13290 | // 28651: } |
| 13291 | // 28651: } |
| 13292 | 220, 3, 33, // 28655: case 0x1dc: { |
| 13293 | OPC_SwitchField, 47, 8, // 28658: switch Inst[54:47] { |
| 13294 | 0, 13, // 28661: case 0x0: { |
| 13295 | OPC_CheckField, 32, 8, 0, // 28663: check Inst[39:32] == 0x0 |
| 13296 | OPC_CheckField, 0, 8, 0, // 28667: check Inst[7:0] == 0x0 |
| 13297 | OPC_Decode, 180, 45, 138, 2, // 28671: decode to VFIAMDvvi using decoder 266 |
| 13298 | // 28671: } |
| 13299 | 1, 0, // 28676: case 0x1: { |
| 13300 | OPC_CheckField, 32, 8, 0, // 28678: check Inst[39:32] == 0x0 |
| 13301 | OPC_CheckField, 0, 8, 0, // 28682: check Inst[7:0] == 0x0 |
| 13302 | OPC_Decode, 186, 45, 209, 1, // 28686: decode to VFIAMDvvr using decoder 209 |
| 13303 | // 28686: } |
| 13304 | // 28686: } // switch Inst[54:47] |
| 13305 | // 28686: } |
| 13306 | 221, 3, 33, // 28691: case 0x1dd: { |
| 13307 | OPC_SwitchField, 47, 8, // 28694: switch Inst[54:47] { |
| 13308 | 0, 13, // 28697: case 0x0: { |
| 13309 | OPC_CheckField, 32, 8, 0, // 28699: check Inst[39:32] == 0x0 |
| 13310 | OPC_CheckField, 0, 8, 0, // 28703: check Inst[7:0] == 0x0 |
| 13311 | OPC_Decode, 192, 45, 138, 2, // 28707: decode to VFIAMSvvi using decoder 266 |
| 13312 | // 28707: } |
| 13313 | 1, 0, // 28712: case 0x1: { |
| 13314 | OPC_CheckField, 32, 8, 0, // 28714: check Inst[39:32] == 0x0 |
| 13315 | OPC_CheckField, 0, 8, 0, // 28718: check Inst[7:0] == 0x0 |
| 13316 | OPC_Decode, 198, 45, 139, 2, // 28722: decode to VFIAMSvvr using decoder 267 |
| 13317 | // 28722: } |
| 13318 | // 28722: } // switch Inst[54:47] |
| 13319 | // 28722: } |
| 13320 | 222, 3, 33, // 28727: case 0x1de: { |
| 13321 | OPC_SwitchField, 47, 8, // 28730: switch Inst[54:47] { |
| 13322 | 0, 13, // 28733: case 0x0: { |
| 13323 | OPC_CheckField, 32, 8, 0, // 28735: check Inst[39:32] == 0x0 |
| 13324 | OPC_CheckField, 0, 8, 0, // 28739: check Inst[7:0] == 0x0 |
| 13325 | OPC_Decode, 216, 45, 138, 2, // 28743: decode to VFIMADvvi using decoder 266 |
| 13326 | // 28743: } |
| 13327 | 1, 0, // 28748: case 0x1: { |
| 13328 | OPC_CheckField, 32, 8, 0, // 28750: check Inst[39:32] == 0x0 |
| 13329 | OPC_CheckField, 0, 8, 0, // 28754: check Inst[7:0] == 0x0 |
| 13330 | OPC_Decode, 222, 45, 209, 1, // 28758: decode to VFIMADvvr using decoder 209 |
| 13331 | // 28758: } |
| 13332 | // 28758: } // switch Inst[54:47] |
| 13333 | // 28758: } |
| 13334 | 223, 3, 33, // 28763: case 0x1df: { |
| 13335 | OPC_SwitchField, 47, 8, // 28766: switch Inst[54:47] { |
| 13336 | 0, 13, // 28769: case 0x0: { |
| 13337 | OPC_CheckField, 32, 8, 0, // 28771: check Inst[39:32] == 0x0 |
| 13338 | OPC_CheckField, 0, 8, 0, // 28775: check Inst[7:0] == 0x0 |
| 13339 | OPC_Decode, 228, 45, 138, 2, // 28779: decode to VFIMASvvi using decoder 266 |
| 13340 | // 28779: } |
| 13341 | 1, 0, // 28784: case 0x1: { |
| 13342 | OPC_CheckField, 32, 8, 0, // 28786: check Inst[39:32] == 0x0 |
| 13343 | OPC_CheckField, 0, 8, 0, // 28790: check Inst[7:0] == 0x0 |
| 13344 | OPC_Decode, 234, 45, 139, 2, // 28794: decode to VFIMASvvr using decoder 267 |
| 13345 | // 28794: } |
| 13346 | // 28794: } // switch Inst[54:47] |
| 13347 | // 28794: } |
| 13348 | 226, 3, 99, // 28799: case 0x1e2: { |
| 13349 | OPC_SwitchField, 52, 3, // 28802: switch Inst[54:52] { |
| 13350 | 0, 22, // 28805: case 0x0: { |
| 13351 | OPC_CheckField, 0, 16, 0, // 28807: check Inst[15:0] == 0x0 |
| 13352 | OPC_CheckField, 32, 16, 0, // 28811: check Inst[47:32] == 0x0 |
| 13353 | OPC_Scope, 8, // 28815: try { |
| 13354 | OPC_CheckField, 48, 4, 0, // 28817: check Inst[51:48] == 0x0 |
| 13355 | OPC_Decode, 192, 69, 119, // 28821: decode to VRSQRTDv using decoder 119 |
| 13356 | // 28821: } else try { |
| 13357 | OPC_Decode, 198, 69, 120, // 28825: decode to VRSQRTDvm using decoder 120 |
| 13358 | // 28825: } |
| 13359 | // 28825: } |
| 13360 | 1, 22, // 28829: case 0x1: { |
| 13361 | OPC_CheckField, 0, 16, 0, // 28831: check Inst[15:0] == 0x0 |
| 13362 | OPC_CheckField, 32, 16, 0, // 28835: check Inst[47:32] == 0x0 |
| 13363 | OPC_Scope, 8, // 28839: try { |
| 13364 | OPC_CheckField, 48, 4, 0, // 28841: check Inst[51:48] == 0x0 |
| 13365 | OPC_Decode, 180, 69, 119, // 28845: decode to VRSQRTDNEXv using decoder 119 |
| 13366 | // 28845: } else try { |
| 13367 | OPC_Decode, 186, 69, 120, // 28849: decode to VRSQRTDNEXvm using decoder 120 |
| 13368 | // 28849: } |
| 13369 | // 28849: } |
| 13370 | 4, 22, // 28853: case 0x4: { |
| 13371 | OPC_CheckField, 0, 16, 0, // 28855: check Inst[15:0] == 0x0 |
| 13372 | OPC_CheckField, 32, 16, 0, // 28859: check Inst[47:32] == 0x0 |
| 13373 | OPC_Scope, 8, // 28863: try { |
| 13374 | OPC_CheckField, 48, 4, 0, // 28865: check Inst[51:48] == 0x0 |
| 13375 | OPC_Decode, 143, 28, 119, // 28869: decode to PVRSQRTLOv using decoder 119 |
| 13376 | // 28869: } else try { |
| 13377 | OPC_Decode, 149, 28, 120, // 28873: decode to PVRSQRTLOvm using decoder 120 |
| 13378 | // 28873: } |
| 13379 | // 28873: } |
| 13380 | 5, 0, // 28877: case 0x5: { |
| 13381 | OPC_CheckField, 0, 16, 0, // 28879: check Inst[15:0] == 0x0 |
| 13382 | OPC_CheckField, 32, 16, 0, // 28883: check Inst[47:32] == 0x0 |
| 13383 | OPC_Scope, 8, // 28887: try { |
| 13384 | OPC_CheckField, 48, 4, 0, // 28889: check Inst[51:48] == 0x0 |
| 13385 | OPC_Decode, 131, 28, 119, // 28893: decode to PVRSQRTLONEXv using decoder 119 |
| 13386 | // 28893: } else try { |
| 13387 | OPC_Decode, 137, 28, 120, // 28897: decode to PVRSQRTLONEXvm using decoder 120 |
| 13388 | // 28897: } |
| 13389 | // 28897: } |
| 13390 | // 28897: } // switch Inst[54:52] |
| 13391 | // 28897: } |
| 13392 | 227, 3, 101, // 28901: case 0x1e3: { |
| 13393 | OPC_SwitchField, 52, 3, // 28904: switch Inst[54:52] { |
| 13394 | 0, 22, // 28907: case 0x0: { |
| 13395 | OPC_CheckField, 0, 16, 0, // 28909: check Inst[15:0] == 0x0 |
| 13396 | OPC_CheckField, 32, 16, 0, // 28913: check Inst[47:32] == 0x0 |
| 13397 | OPC_Scope, 8, // 28917: try { |
| 13398 | OPC_CheckField, 48, 4, 0, // 28919: check Inst[51:48] == 0x0 |
| 13399 | OPC_Decode, 179, 28, 119, // 28923: decode to PVRSQRTUPv using decoder 119 |
| 13400 | // 28923: } else try { |
| 13401 | OPC_Decode, 185, 28, 120, // 28927: decode to PVRSQRTUPvm using decoder 120 |
| 13402 | // 28927: } |
| 13403 | // 28927: } |
| 13404 | 1, 22, // 28931: case 0x1: { |
| 13405 | OPC_CheckField, 0, 16, 0, // 28933: check Inst[15:0] == 0x0 |
| 13406 | OPC_CheckField, 32, 16, 0, // 28937: check Inst[47:32] == 0x0 |
| 13407 | OPC_Scope, 8, // 28941: try { |
| 13408 | OPC_CheckField, 48, 4, 0, // 28943: check Inst[51:48] == 0x0 |
| 13409 | OPC_Decode, 167, 28, 119, // 28947: decode to PVRSQRTUPNEXv using decoder 119 |
| 13410 | // 28947: } else try { |
| 13411 | OPC_Decode, 173, 28, 120, // 28951: decode to PVRSQRTUPNEXvm using decoder 120 |
| 13412 | // 28951: } |
| 13413 | // 28951: } |
| 13414 | 4, 23, // 28955: case 0x4: { |
| 13415 | OPC_CheckField, 0, 16, 0, // 28957: check Inst[15:0] == 0x0 |
| 13416 | OPC_CheckField, 32, 16, 0, // 28961: check Inst[47:32] == 0x0 |
| 13417 | OPC_Scope, 8, // 28965: try { |
| 13418 | OPC_CheckField, 48, 4, 0, // 28967: check Inst[51:48] == 0x0 |
| 13419 | OPC_Decode, 191, 28, 119, // 28971: decode to PVRSQRTv using decoder 119 |
| 13420 | // 28971: } else try { |
| 13421 | OPC_Decode, 197, 28, 234, 1, // 28975: decode to PVRSQRTvm using decoder 234 |
| 13422 | // 28975: } |
| 13423 | // 28975: } |
| 13424 | 5, 0, // 28980: case 0x5: { |
| 13425 | OPC_CheckField, 0, 16, 0, // 28982: check Inst[15:0] == 0x0 |
| 13426 | OPC_CheckField, 32, 16, 0, // 28986: check Inst[47:32] == 0x0 |
| 13427 | OPC_Scope, 8, // 28990: try { |
| 13428 | OPC_CheckField, 48, 4, 0, // 28992: check Inst[51:48] == 0x0 |
| 13429 | OPC_Decode, 155, 28, 119, // 28996: decode to PVRSQRTNEXv using decoder 119 |
| 13430 | // 28996: } else try { |
| 13431 | OPC_Decode, 161, 28, 234, 1, // 29000: decode to PVRSQRTNEXvm using decoder 234 |
| 13432 | // 29000: } |
| 13433 | // 29000: } |
| 13434 | // 29000: } // switch Inst[54:52] |
| 13435 | // 29000: } |
| 13436 | 228, 3, 147, 2, // 29005: case 0x1e4: { |
| 13437 | OPC_SwitchField, 52, 3, // 29009: switch Inst[54:52] { |
| 13438 | 0, 20, // 29012: case 0x0: { |
| 13439 | OPC_CheckField, 32, 16, 0, // 29014: check Inst[47:32] == 0x0 |
| 13440 | OPC_Scope, 9, // 29018: try { |
| 13441 | OPC_CheckField, 48, 4, 0, // 29020: check Inst[51:48] == 0x0 |
| 13442 | OPC_Decode, 208, 49, 235, 1, // 29024: decode to VFMSBDvvv using decoder 235 |
| 13443 | // 29024: } else try { |
| 13444 | OPC_Decode, 214, 49, 236, 1, // 29029: decode to VFMSBDvvvm using decoder 236 |
| 13445 | // 29029: } |
| 13446 | // 29029: } |
| 13447 | 1, 55, // 29034: case 0x1: { |
| 13448 | OPC_SwitchField, 47, 1, // 29036: switch Inst[47] { |
| 13449 | 0, 24, // 29039: case 0x0: { |
| 13450 | OPC_CheckField, 8, 8, 0, // 29041: check Inst[15:8] == 0x0 |
| 13451 | OPC_CheckField, 32, 8, 0, // 29045: check Inst[39:32] == 0x0 |
| 13452 | OPC_Scope, 9, // 29049: try { |
| 13453 | OPC_CheckField, 48, 4, 0, // 29051: check Inst[51:48] == 0x0 |
| 13454 | OPC_Decode, 184, 49, 237, 1, // 29055: decode to VFMSBDviv using decoder 237 |
| 13455 | // 29055: } else try { |
| 13456 | OPC_Decode, 190, 49, 238, 1, // 29060: decode to VFMSBDvivm using decoder 238 |
| 13457 | // 29060: } |
| 13458 | // 29060: } |
| 13459 | 1, 0, // 29065: case 0x1: { |
| 13460 | OPC_CheckField, 8, 8, 0, // 29067: check Inst[15:8] == 0x0 |
| 13461 | OPC_CheckField, 32, 8, 0, // 29071: check Inst[39:32] == 0x0 |
| 13462 | OPC_Scope, 9, // 29075: try { |
| 13463 | OPC_CheckField, 48, 4, 0, // 29077: check Inst[51:48] == 0x0 |
| 13464 | OPC_Decode, 196, 49, 239, 1, // 29081: decode to VFMSBDvrv using decoder 239 |
| 13465 | // 29081: } else try { |
| 13466 | OPC_Decode, 202, 49, 240, 1, // 29086: decode to VFMSBDvrvm using decoder 240 |
| 13467 | // 29086: } |
| 13468 | // 29086: } |
| 13469 | // 29086: } // switch Inst[47] |
| 13470 | // 29086: } |
| 13471 | 2, 55, // 29091: case 0x2: { |
| 13472 | OPC_SwitchField, 47, 1, // 29093: switch Inst[47] { |
| 13473 | 0, 24, // 29096: case 0x0: { |
| 13474 | OPC_CheckField, 16, 8, 0, // 29098: check Inst[23:16] == 0x0 |
| 13475 | OPC_CheckField, 32, 8, 0, // 29102: check Inst[39:32] == 0x0 |
| 13476 | OPC_Scope, 9, // 29106: try { |
| 13477 | OPC_CheckField, 48, 4, 0, // 29108: check Inst[51:48] == 0x0 |
| 13478 | OPC_Decode, 160, 49, 241, 1, // 29112: decode to VFMSBDivv using decoder 241 |
| 13479 | // 29112: } else try { |
| 13480 | OPC_Decode, 166, 49, 242, 1, // 29117: decode to VFMSBDivvm using decoder 242 |
| 13481 | // 29117: } |
| 13482 | // 29117: } |
| 13483 | 1, 0, // 29122: case 0x1: { |
| 13484 | OPC_CheckField, 16, 8, 0, // 29124: check Inst[23:16] == 0x0 |
| 13485 | OPC_CheckField, 32, 8, 0, // 29128: check Inst[39:32] == 0x0 |
| 13486 | OPC_Scope, 9, // 29132: try { |
| 13487 | OPC_CheckField, 48, 4, 0, // 29134: check Inst[51:48] == 0x0 |
| 13488 | OPC_Decode, 172, 49, 243, 1, // 29138: decode to VFMSBDrvv using decoder 243 |
| 13489 | // 29138: } else try { |
| 13490 | OPC_Decode, 178, 49, 244, 1, // 29143: decode to VFMSBDrvvm using decoder 244 |
| 13491 | // 29143: } |
| 13492 | // 29143: } |
| 13493 | // 29143: } // switch Inst[47] |
| 13494 | // 29143: } |
| 13495 | 4, 20, // 29148: case 0x4: { |
| 13496 | OPC_CheckField, 32, 16, 0, // 29150: check Inst[47:32] == 0x0 |
| 13497 | OPC_Scope, 9, // 29154: try { |
| 13498 | OPC_CheckField, 48, 4, 0, // 29156: check Inst[51:48] == 0x0 |
| 13499 | OPC_Decode, 143, 19, 235, 1, // 29160: decode to PVFMSBLOvvv using decoder 235 |
| 13500 | // 29160: } else try { |
| 13501 | OPC_Decode, 149, 19, 236, 1, // 29165: decode to PVFMSBLOvvvm using decoder 236 |
| 13502 | // 29165: } |
| 13503 | // 29165: } |
| 13504 | 5, 55, // 29170: case 0x5: { |
| 13505 | OPC_SwitchField, 47, 1, // 29172: switch Inst[47] { |
| 13506 | 0, 24, // 29175: case 0x0: { |
| 13507 | OPC_CheckField, 8, 8, 0, // 29177: check Inst[15:8] == 0x0 |
| 13508 | OPC_CheckField, 32, 8, 0, // 29181: check Inst[39:32] == 0x0 |
| 13509 | OPC_Scope, 9, // 29185: try { |
| 13510 | OPC_CheckField, 48, 4, 0, // 29187: check Inst[51:48] == 0x0 |
| 13511 | OPC_Decode, 247, 18, 237, 1, // 29191: decode to PVFMSBLOviv using decoder 237 |
| 13512 | // 29191: } else try { |
| 13513 | OPC_Decode, 253, 18, 238, 1, // 29196: decode to PVFMSBLOvivm using decoder 238 |
| 13514 | // 29196: } |
| 13515 | // 29196: } |
| 13516 | 1, 0, // 29201: case 0x1: { |
| 13517 | OPC_CheckField, 8, 8, 0, // 29203: check Inst[15:8] == 0x0 |
| 13518 | OPC_CheckField, 32, 8, 0, // 29207: check Inst[39:32] == 0x0 |
| 13519 | OPC_Scope, 9, // 29211: try { |
| 13520 | OPC_CheckField, 48, 4, 0, // 29213: check Inst[51:48] == 0x0 |
| 13521 | OPC_Decode, 131, 19, 239, 1, // 29217: decode to PVFMSBLOvrv using decoder 239 |
| 13522 | // 29217: } else try { |
| 13523 | OPC_Decode, 137, 19, 240, 1, // 29222: decode to PVFMSBLOvrvm using decoder 240 |
| 13524 | // 29222: } |
| 13525 | // 29222: } |
| 13526 | // 29222: } // switch Inst[47] |
| 13527 | // 29222: } |
| 13528 | 6, 0, // 29227: case 0x6: { |
| 13529 | OPC_SwitchField, 47, 1, // 29229: switch Inst[47] { |
| 13530 | 0, 24, // 29232: case 0x0: { |
| 13531 | OPC_CheckField, 16, 8, 0, // 29234: check Inst[23:16] == 0x0 |
| 13532 | OPC_CheckField, 32, 8, 0, // 29238: check Inst[39:32] == 0x0 |
| 13533 | OPC_Scope, 9, // 29242: try { |
| 13534 | OPC_CheckField, 48, 4, 0, // 29244: check Inst[51:48] == 0x0 |
| 13535 | OPC_Decode, 223, 18, 241, 1, // 29248: decode to PVFMSBLOivv using decoder 241 |
| 13536 | // 29248: } else try { |
| 13537 | OPC_Decode, 229, 18, 242, 1, // 29253: decode to PVFMSBLOivvm using decoder 242 |
| 13538 | // 29253: } |
| 13539 | // 29253: } |
| 13540 | 1, 0, // 29258: case 0x1: { |
| 13541 | OPC_CheckField, 16, 8, 0, // 29260: check Inst[23:16] == 0x0 |
| 13542 | OPC_CheckField, 32, 8, 0, // 29264: check Inst[39:32] == 0x0 |
| 13543 | OPC_Scope, 9, // 29268: try { |
| 13544 | OPC_CheckField, 48, 4, 0, // 29270: check Inst[51:48] == 0x0 |
| 13545 | OPC_Decode, 235, 18, 243, 1, // 29274: decode to PVFMSBLOrvv using decoder 243 |
| 13546 | // 29274: } else try { |
| 13547 | OPC_Decode, 241, 18, 244, 1, // 29279: decode to PVFMSBLOrvvm using decoder 244 |
| 13548 | // 29279: } |
| 13549 | // 29279: } |
| 13550 | // 29279: } // switch Inst[47] |
| 13551 | // 29279: } |
| 13552 | // 29279: } // switch Inst[54:52] |
| 13553 | // 29279: } |
| 13554 | 229, 3, 147, 2, // 29284: case 0x1e5: { |
| 13555 | OPC_SwitchField, 52, 3, // 29288: switch Inst[54:52] { |
| 13556 | 0, 20, // 29291: case 0x0: { |
| 13557 | OPC_CheckField, 32, 16, 0, // 29293: check Inst[47:32] == 0x0 |
| 13558 | OPC_Scope, 9, // 29297: try { |
| 13559 | OPC_CheckField, 48, 4, 0, // 29299: check Inst[51:48] == 0x0 |
| 13560 | OPC_Decode, 203, 19, 235, 1, // 29303: decode to PVFMSBUPvvv using decoder 235 |
| 13561 | // 29303: } else try { |
| 13562 | OPC_Decode, 209, 19, 236, 1, // 29308: decode to PVFMSBUPvvvm using decoder 236 |
| 13563 | // 29308: } |
| 13564 | // 29308: } |
| 13565 | 1, 55, // 29313: case 0x1: { |
| 13566 | OPC_SwitchField, 47, 1, // 29315: switch Inst[47] { |
| 13567 | 0, 24, // 29318: case 0x0: { |
| 13568 | OPC_CheckField, 8, 8, 0, // 29320: check Inst[15:8] == 0x0 |
| 13569 | OPC_CheckField, 32, 8, 0, // 29324: check Inst[39:32] == 0x0 |
| 13570 | OPC_Scope, 9, // 29328: try { |
| 13571 | OPC_CheckField, 48, 4, 0, // 29330: check Inst[51:48] == 0x0 |
| 13572 | OPC_Decode, 179, 19, 237, 1, // 29334: decode to PVFMSBUPviv using decoder 237 |
| 13573 | // 29334: } else try { |
| 13574 | OPC_Decode, 185, 19, 238, 1, // 29339: decode to PVFMSBUPvivm using decoder 238 |
| 13575 | // 29339: } |
| 13576 | // 29339: } |
| 13577 | 1, 0, // 29344: case 0x1: { |
| 13578 | OPC_CheckField, 8, 8, 0, // 29346: check Inst[15:8] == 0x0 |
| 13579 | OPC_CheckField, 32, 8, 0, // 29350: check Inst[39:32] == 0x0 |
| 13580 | OPC_Scope, 9, // 29354: try { |
| 13581 | OPC_CheckField, 48, 4, 0, // 29356: check Inst[51:48] == 0x0 |
| 13582 | OPC_Decode, 191, 19, 245, 1, // 29360: decode to PVFMSBUPvrv using decoder 245 |
| 13583 | // 29360: } else try { |
| 13584 | OPC_Decode, 197, 19, 246, 1, // 29365: decode to PVFMSBUPvrvm using decoder 246 |
| 13585 | // 29365: } |
| 13586 | // 29365: } |
| 13587 | // 29365: } // switch Inst[47] |
| 13588 | // 29365: } |
| 13589 | 2, 55, // 29370: case 0x2: { |
| 13590 | OPC_SwitchField, 47, 1, // 29372: switch Inst[47] { |
| 13591 | 0, 24, // 29375: case 0x0: { |
| 13592 | OPC_CheckField, 16, 8, 0, // 29377: check Inst[23:16] == 0x0 |
| 13593 | OPC_CheckField, 32, 8, 0, // 29381: check Inst[39:32] == 0x0 |
| 13594 | OPC_Scope, 9, // 29385: try { |
| 13595 | OPC_CheckField, 48, 4, 0, // 29387: check Inst[51:48] == 0x0 |
| 13596 | OPC_Decode, 155, 19, 241, 1, // 29391: decode to PVFMSBUPivv using decoder 241 |
| 13597 | // 29391: } else try { |
| 13598 | OPC_Decode, 161, 19, 242, 1, // 29396: decode to PVFMSBUPivvm using decoder 242 |
| 13599 | // 29396: } |
| 13600 | // 29396: } |
| 13601 | 1, 0, // 29401: case 0x1: { |
| 13602 | OPC_CheckField, 16, 8, 0, // 29403: check Inst[23:16] == 0x0 |
| 13603 | OPC_CheckField, 32, 8, 0, // 29407: check Inst[39:32] == 0x0 |
| 13604 | OPC_Scope, 9, // 29411: try { |
| 13605 | OPC_CheckField, 48, 4, 0, // 29413: check Inst[51:48] == 0x0 |
| 13606 | OPC_Decode, 167, 19, 247, 1, // 29417: decode to PVFMSBUPrvv using decoder 247 |
| 13607 | // 29417: } else try { |
| 13608 | OPC_Decode, 173, 19, 248, 1, // 29422: decode to PVFMSBUPrvvm using decoder 248 |
| 13609 | // 29422: } |
| 13610 | // 29422: } |
| 13611 | // 29422: } // switch Inst[47] |
| 13612 | // 29422: } |
| 13613 | 4, 20, // 29427: case 0x4: { |
| 13614 | OPC_CheckField, 32, 16, 0, // 29429: check Inst[47:32] == 0x0 |
| 13615 | OPC_Scope, 9, // 29433: try { |
| 13616 | OPC_CheckField, 48, 4, 0, // 29435: check Inst[51:48] == 0x0 |
| 13617 | OPC_Decode, 135, 20, 235, 1, // 29439: decode to PVFMSBvvv using decoder 235 |
| 13618 | // 29439: } else try { |
| 13619 | OPC_Decode, 141, 20, 249, 1, // 29444: decode to PVFMSBvvvm using decoder 249 |
| 13620 | // 29444: } |
| 13621 | // 29444: } |
| 13622 | 5, 55, // 29449: case 0x5: { |
| 13623 | OPC_SwitchField, 47, 1, // 29451: switch Inst[47] { |
| 13624 | 0, 24, // 29454: case 0x0: { |
| 13625 | OPC_CheckField, 8, 8, 0, // 29456: check Inst[15:8] == 0x0 |
| 13626 | OPC_CheckField, 32, 8, 0, // 29460: check Inst[39:32] == 0x0 |
| 13627 | OPC_Scope, 9, // 29464: try { |
| 13628 | OPC_CheckField, 48, 4, 0, // 29466: check Inst[51:48] == 0x0 |
| 13629 | OPC_Decode, 239, 19, 237, 1, // 29470: decode to PVFMSBviv using decoder 237 |
| 13630 | // 29470: } else try { |
| 13631 | OPC_Decode, 245, 19, 250, 1, // 29475: decode to PVFMSBvivm using decoder 250 |
| 13632 | // 29475: } |
| 13633 | // 29475: } |
| 13634 | 1, 0, // 29480: case 0x1: { |
| 13635 | OPC_CheckField, 8, 8, 0, // 29482: check Inst[15:8] == 0x0 |
| 13636 | OPC_CheckField, 32, 8, 0, // 29486: check Inst[39:32] == 0x0 |
| 13637 | OPC_Scope, 9, // 29490: try { |
| 13638 | OPC_CheckField, 48, 4, 0, // 29492: check Inst[51:48] == 0x0 |
| 13639 | OPC_Decode, 251, 19, 239, 1, // 29496: decode to PVFMSBvrv using decoder 239 |
| 13640 | // 29496: } else try { |
| 13641 | OPC_Decode, 129, 20, 251, 1, // 29501: decode to PVFMSBvrvm using decoder 251 |
| 13642 | // 29501: } |
| 13643 | // 29501: } |
| 13644 | // 29501: } // switch Inst[47] |
| 13645 | // 29501: } |
| 13646 | 6, 0, // 29506: case 0x6: { |
| 13647 | OPC_SwitchField, 47, 1, // 29508: switch Inst[47] { |
| 13648 | 0, 24, // 29511: case 0x0: { |
| 13649 | OPC_CheckField, 16, 8, 0, // 29513: check Inst[23:16] == 0x0 |
| 13650 | OPC_CheckField, 32, 8, 0, // 29517: check Inst[39:32] == 0x0 |
| 13651 | OPC_Scope, 9, // 29521: try { |
| 13652 | OPC_CheckField, 48, 4, 0, // 29523: check Inst[51:48] == 0x0 |
| 13653 | OPC_Decode, 215, 19, 241, 1, // 29527: decode to PVFMSBivv using decoder 241 |
| 13654 | // 29527: } else try { |
| 13655 | OPC_Decode, 221, 19, 252, 1, // 29532: decode to PVFMSBivvm using decoder 252 |
| 13656 | // 29532: } |
| 13657 | // 29532: } |
| 13658 | 1, 0, // 29537: case 0x1: { |
| 13659 | OPC_CheckField, 16, 8, 0, // 29539: check Inst[23:16] == 0x0 |
| 13660 | OPC_CheckField, 32, 8, 0, // 29543: check Inst[39:32] == 0x0 |
| 13661 | OPC_Scope, 9, // 29547: try { |
| 13662 | OPC_CheckField, 48, 4, 0, // 29549: check Inst[51:48] == 0x0 |
| 13663 | OPC_Decode, 227, 19, 243, 1, // 29553: decode to PVFMSBrvv using decoder 243 |
| 13664 | // 29553: } else try { |
| 13665 | OPC_Decode, 233, 19, 253, 1, // 29558: decode to PVFMSBrvvm using decoder 253 |
| 13666 | // 29558: } |
| 13667 | // 29558: } |
| 13668 | // 29558: } // switch Inst[47] |
| 13669 | // 29558: } |
| 13670 | // 29558: } // switch Inst[54:52] |
| 13671 | // 29558: } |
| 13672 | 230, 3, 147, 2, // 29563: case 0x1e6: { |
| 13673 | OPC_SwitchField, 52, 3, // 29567: switch Inst[54:52] { |
| 13674 | 0, 20, // 29570: case 0x0: { |
| 13675 | OPC_CheckField, 32, 16, 0, // 29572: check Inst[47:32] == 0x0 |
| 13676 | OPC_Scope, 9, // 29576: try { |
| 13677 | OPC_CheckField, 48, 4, 0, // 29578: check Inst[51:48] == 0x0 |
| 13678 | OPC_Decode, 136, 52, 235, 1, // 29582: decode to VFNMSBDvvv using decoder 235 |
| 13679 | // 29582: } else try { |
| 13680 | OPC_Decode, 142, 52, 236, 1, // 29587: decode to VFNMSBDvvvm using decoder 236 |
| 13681 | // 29587: } |
| 13682 | // 29587: } |
| 13683 | 1, 55, // 29592: case 0x1: { |
| 13684 | OPC_SwitchField, 47, 1, // 29594: switch Inst[47] { |
| 13685 | 0, 24, // 29597: case 0x0: { |
| 13686 | OPC_CheckField, 8, 8, 0, // 29599: check Inst[15:8] == 0x0 |
| 13687 | OPC_CheckField, 32, 8, 0, // 29603: check Inst[39:32] == 0x0 |
| 13688 | OPC_Scope, 9, // 29607: try { |
| 13689 | OPC_CheckField, 48, 4, 0, // 29609: check Inst[51:48] == 0x0 |
| 13690 | OPC_Decode, 240, 51, 237, 1, // 29613: decode to VFNMSBDviv using decoder 237 |
| 13691 | // 29613: } else try { |
| 13692 | OPC_Decode, 246, 51, 238, 1, // 29618: decode to VFNMSBDvivm using decoder 238 |
| 13693 | // 29618: } |
| 13694 | // 29618: } |
| 13695 | 1, 0, // 29623: case 0x1: { |
| 13696 | OPC_CheckField, 8, 8, 0, // 29625: check Inst[15:8] == 0x0 |
| 13697 | OPC_CheckField, 32, 8, 0, // 29629: check Inst[39:32] == 0x0 |
| 13698 | OPC_Scope, 9, // 29633: try { |
| 13699 | OPC_CheckField, 48, 4, 0, // 29635: check Inst[51:48] == 0x0 |
| 13700 | OPC_Decode, 252, 51, 239, 1, // 29639: decode to VFNMSBDvrv using decoder 239 |
| 13701 | // 29639: } else try { |
| 13702 | OPC_Decode, 130, 52, 240, 1, // 29644: decode to VFNMSBDvrvm using decoder 240 |
| 13703 | // 29644: } |
| 13704 | // 29644: } |
| 13705 | // 29644: } // switch Inst[47] |
| 13706 | // 29644: } |
| 13707 | 2, 55, // 29649: case 0x2: { |
| 13708 | OPC_SwitchField, 47, 1, // 29651: switch Inst[47] { |
| 13709 | 0, 24, // 29654: case 0x0: { |
| 13710 | OPC_CheckField, 16, 8, 0, // 29656: check Inst[23:16] == 0x0 |
| 13711 | OPC_CheckField, 32, 8, 0, // 29660: check Inst[39:32] == 0x0 |
| 13712 | OPC_Scope, 9, // 29664: try { |
| 13713 | OPC_CheckField, 48, 4, 0, // 29666: check Inst[51:48] == 0x0 |
| 13714 | OPC_Decode, 216, 51, 241, 1, // 29670: decode to VFNMSBDivv using decoder 241 |
| 13715 | // 29670: } else try { |
| 13716 | OPC_Decode, 222, 51, 242, 1, // 29675: decode to VFNMSBDivvm using decoder 242 |
| 13717 | // 29675: } |
| 13718 | // 29675: } |
| 13719 | 1, 0, // 29680: case 0x1: { |
| 13720 | OPC_CheckField, 16, 8, 0, // 29682: check Inst[23:16] == 0x0 |
| 13721 | OPC_CheckField, 32, 8, 0, // 29686: check Inst[39:32] == 0x0 |
| 13722 | OPC_Scope, 9, // 29690: try { |
| 13723 | OPC_CheckField, 48, 4, 0, // 29692: check Inst[51:48] == 0x0 |
| 13724 | OPC_Decode, 228, 51, 243, 1, // 29696: decode to VFNMSBDrvv using decoder 243 |
| 13725 | // 29696: } else try { |
| 13726 | OPC_Decode, 234, 51, 244, 1, // 29701: decode to VFNMSBDrvvm using decoder 244 |
| 13727 | // 29701: } |
| 13728 | // 29701: } |
| 13729 | // 29701: } // switch Inst[47] |
| 13730 | // 29701: } |
| 13731 | 4, 20, // 29706: case 0x4: { |
| 13732 | OPC_CheckField, 32, 16, 0, // 29708: check Inst[47:32] == 0x0 |
| 13733 | OPC_Scope, 9, // 29712: try { |
| 13734 | OPC_CheckField, 48, 4, 0, // 29714: check Inst[51:48] == 0x0 |
| 13735 | OPC_Decode, 227, 22, 235, 1, // 29718: decode to PVFNMSBLOvvv using decoder 235 |
| 13736 | // 29718: } else try { |
| 13737 | OPC_Decode, 233, 22, 236, 1, // 29723: decode to PVFNMSBLOvvvm using decoder 236 |
| 13738 | // 29723: } |
| 13739 | // 29723: } |
| 13740 | 5, 55, // 29728: case 0x5: { |
| 13741 | OPC_SwitchField, 47, 1, // 29730: switch Inst[47] { |
| 13742 | 0, 24, // 29733: case 0x0: { |
| 13743 | OPC_CheckField, 8, 8, 0, // 29735: check Inst[15:8] == 0x0 |
| 13744 | OPC_CheckField, 32, 8, 0, // 29739: check Inst[39:32] == 0x0 |
| 13745 | OPC_Scope, 9, // 29743: try { |
| 13746 | OPC_CheckField, 48, 4, 0, // 29745: check Inst[51:48] == 0x0 |
| 13747 | OPC_Decode, 203, 22, 237, 1, // 29749: decode to PVFNMSBLOviv using decoder 237 |
| 13748 | // 29749: } else try { |
| 13749 | OPC_Decode, 209, 22, 238, 1, // 29754: decode to PVFNMSBLOvivm using decoder 238 |
| 13750 | // 29754: } |
| 13751 | // 29754: } |
| 13752 | 1, 0, // 29759: case 0x1: { |
| 13753 | OPC_CheckField, 8, 8, 0, // 29761: check Inst[15:8] == 0x0 |
| 13754 | OPC_CheckField, 32, 8, 0, // 29765: check Inst[39:32] == 0x0 |
| 13755 | OPC_Scope, 9, // 29769: try { |
| 13756 | OPC_CheckField, 48, 4, 0, // 29771: check Inst[51:48] == 0x0 |
| 13757 | OPC_Decode, 215, 22, 239, 1, // 29775: decode to PVFNMSBLOvrv using decoder 239 |
| 13758 | // 29775: } else try { |
| 13759 | OPC_Decode, 221, 22, 240, 1, // 29780: decode to PVFNMSBLOvrvm using decoder 240 |
| 13760 | // 29780: } |
| 13761 | // 29780: } |
| 13762 | // 29780: } // switch Inst[47] |
| 13763 | // 29780: } |
| 13764 | 6, 0, // 29785: case 0x6: { |
| 13765 | OPC_SwitchField, 47, 1, // 29787: switch Inst[47] { |
| 13766 | 0, 24, // 29790: case 0x0: { |
| 13767 | OPC_CheckField, 16, 8, 0, // 29792: check Inst[23:16] == 0x0 |
| 13768 | OPC_CheckField, 32, 8, 0, // 29796: check Inst[39:32] == 0x0 |
| 13769 | OPC_Scope, 9, // 29800: try { |
| 13770 | OPC_CheckField, 48, 4, 0, // 29802: check Inst[51:48] == 0x0 |
| 13771 | OPC_Decode, 179, 22, 241, 1, // 29806: decode to PVFNMSBLOivv using decoder 241 |
| 13772 | // 29806: } else try { |
| 13773 | OPC_Decode, 185, 22, 242, 1, // 29811: decode to PVFNMSBLOivvm using decoder 242 |
| 13774 | // 29811: } |
| 13775 | // 29811: } |
| 13776 | 1, 0, // 29816: case 0x1: { |
| 13777 | OPC_CheckField, 16, 8, 0, // 29818: check Inst[23:16] == 0x0 |
| 13778 | OPC_CheckField, 32, 8, 0, // 29822: check Inst[39:32] == 0x0 |
| 13779 | OPC_Scope, 9, // 29826: try { |
| 13780 | OPC_CheckField, 48, 4, 0, // 29828: check Inst[51:48] == 0x0 |
| 13781 | OPC_Decode, 191, 22, 243, 1, // 29832: decode to PVFNMSBLOrvv using decoder 243 |
| 13782 | // 29832: } else try { |
| 13783 | OPC_Decode, 197, 22, 244, 1, // 29837: decode to PVFNMSBLOrvvm using decoder 244 |
| 13784 | // 29837: } |
| 13785 | // 29837: } |
| 13786 | // 29837: } // switch Inst[47] |
| 13787 | // 29837: } |
| 13788 | // 29837: } // switch Inst[54:52] |
| 13789 | // 29837: } |
| 13790 | 231, 3, 147, 2, // 29842: case 0x1e7: { |
| 13791 | OPC_SwitchField, 52, 3, // 29846: switch Inst[54:52] { |
| 13792 | 0, 20, // 29849: case 0x0: { |
| 13793 | OPC_CheckField, 32, 16, 0, // 29851: check Inst[47:32] == 0x0 |
| 13794 | OPC_Scope, 9, // 29855: try { |
| 13795 | OPC_CheckField, 48, 4, 0, // 29857: check Inst[51:48] == 0x0 |
| 13796 | OPC_Decode, 159, 23, 235, 1, // 29861: decode to PVFNMSBUPvvv using decoder 235 |
| 13797 | // 29861: } else try { |
| 13798 | OPC_Decode, 165, 23, 236, 1, // 29866: decode to PVFNMSBUPvvvm using decoder 236 |
| 13799 | // 29866: } |
| 13800 | // 29866: } |
| 13801 | 1, 55, // 29871: case 0x1: { |
| 13802 | OPC_SwitchField, 47, 1, // 29873: switch Inst[47] { |
| 13803 | 0, 24, // 29876: case 0x0: { |
| 13804 | OPC_CheckField, 8, 8, 0, // 29878: check Inst[15:8] == 0x0 |
| 13805 | OPC_CheckField, 32, 8, 0, // 29882: check Inst[39:32] == 0x0 |
| 13806 | OPC_Scope, 9, // 29886: try { |
| 13807 | OPC_CheckField, 48, 4, 0, // 29888: check Inst[51:48] == 0x0 |
| 13808 | OPC_Decode, 135, 23, 237, 1, // 29892: decode to PVFNMSBUPviv using decoder 237 |
| 13809 | // 29892: } else try { |
| 13810 | OPC_Decode, 141, 23, 238, 1, // 29897: decode to PVFNMSBUPvivm using decoder 238 |
| 13811 | // 29897: } |
| 13812 | // 29897: } |
| 13813 | 1, 0, // 29902: case 0x1: { |
| 13814 | OPC_CheckField, 8, 8, 0, // 29904: check Inst[15:8] == 0x0 |
| 13815 | OPC_CheckField, 32, 8, 0, // 29908: check Inst[39:32] == 0x0 |
| 13816 | OPC_Scope, 9, // 29912: try { |
| 13817 | OPC_CheckField, 48, 4, 0, // 29914: check Inst[51:48] == 0x0 |
| 13818 | OPC_Decode, 147, 23, 245, 1, // 29918: decode to PVFNMSBUPvrv using decoder 245 |
| 13819 | // 29918: } else try { |
| 13820 | OPC_Decode, 153, 23, 246, 1, // 29923: decode to PVFNMSBUPvrvm using decoder 246 |
| 13821 | // 29923: } |
| 13822 | // 29923: } |
| 13823 | // 29923: } // switch Inst[47] |
| 13824 | // 29923: } |
| 13825 | 2, 55, // 29928: case 0x2: { |
| 13826 | OPC_SwitchField, 47, 1, // 29930: switch Inst[47] { |
| 13827 | 0, 24, // 29933: case 0x0: { |
| 13828 | OPC_CheckField, 16, 8, 0, // 29935: check Inst[23:16] == 0x0 |
| 13829 | OPC_CheckField, 32, 8, 0, // 29939: check Inst[39:32] == 0x0 |
| 13830 | OPC_Scope, 9, // 29943: try { |
| 13831 | OPC_CheckField, 48, 4, 0, // 29945: check Inst[51:48] == 0x0 |
| 13832 | OPC_Decode, 239, 22, 241, 1, // 29949: decode to PVFNMSBUPivv using decoder 241 |
| 13833 | // 29949: } else try { |
| 13834 | OPC_Decode, 245, 22, 242, 1, // 29954: decode to PVFNMSBUPivvm using decoder 242 |
| 13835 | // 29954: } |
| 13836 | // 29954: } |
| 13837 | 1, 0, // 29959: case 0x1: { |
| 13838 | OPC_CheckField, 16, 8, 0, // 29961: check Inst[23:16] == 0x0 |
| 13839 | OPC_CheckField, 32, 8, 0, // 29965: check Inst[39:32] == 0x0 |
| 13840 | OPC_Scope, 9, // 29969: try { |
| 13841 | OPC_CheckField, 48, 4, 0, // 29971: check Inst[51:48] == 0x0 |
| 13842 | OPC_Decode, 251, 22, 247, 1, // 29975: decode to PVFNMSBUPrvv using decoder 247 |
| 13843 | // 29975: } else try { |
| 13844 | OPC_Decode, 129, 23, 248, 1, // 29980: decode to PVFNMSBUPrvvm using decoder 248 |
| 13845 | // 29980: } |
| 13846 | // 29980: } |
| 13847 | // 29980: } // switch Inst[47] |
| 13848 | // 29980: } |
| 13849 | 4, 20, // 29985: case 0x4: { |
| 13850 | OPC_CheckField, 32, 16, 0, // 29987: check Inst[47:32] == 0x0 |
| 13851 | OPC_Scope, 9, // 29991: try { |
| 13852 | OPC_CheckField, 48, 4, 0, // 29993: check Inst[51:48] == 0x0 |
| 13853 | OPC_Decode, 219, 23, 235, 1, // 29997: decode to PVFNMSBvvv using decoder 235 |
| 13854 | // 29997: } else try { |
| 13855 | OPC_Decode, 225, 23, 249, 1, // 30002: decode to PVFNMSBvvvm using decoder 249 |
| 13856 | // 30002: } |
| 13857 | // 30002: } |
| 13858 | 5, 55, // 30007: case 0x5: { |
| 13859 | OPC_SwitchField, 47, 1, // 30009: switch Inst[47] { |
| 13860 | 0, 24, // 30012: case 0x0: { |
| 13861 | OPC_CheckField, 8, 8, 0, // 30014: check Inst[15:8] == 0x0 |
| 13862 | OPC_CheckField, 32, 8, 0, // 30018: check Inst[39:32] == 0x0 |
| 13863 | OPC_Scope, 9, // 30022: try { |
| 13864 | OPC_CheckField, 48, 4, 0, // 30024: check Inst[51:48] == 0x0 |
| 13865 | OPC_Decode, 195, 23, 237, 1, // 30028: decode to PVFNMSBviv using decoder 237 |
| 13866 | // 30028: } else try { |
| 13867 | OPC_Decode, 201, 23, 250, 1, // 30033: decode to PVFNMSBvivm using decoder 250 |
| 13868 | // 30033: } |
| 13869 | // 30033: } |
| 13870 | 1, 0, // 30038: case 0x1: { |
| 13871 | OPC_CheckField, 8, 8, 0, // 30040: check Inst[15:8] == 0x0 |
| 13872 | OPC_CheckField, 32, 8, 0, // 30044: check Inst[39:32] == 0x0 |
| 13873 | OPC_Scope, 9, // 30048: try { |
| 13874 | OPC_CheckField, 48, 4, 0, // 30050: check Inst[51:48] == 0x0 |
| 13875 | OPC_Decode, 207, 23, 239, 1, // 30054: decode to PVFNMSBvrv using decoder 239 |
| 13876 | // 30054: } else try { |
| 13877 | OPC_Decode, 213, 23, 251, 1, // 30059: decode to PVFNMSBvrvm using decoder 251 |
| 13878 | // 30059: } |
| 13879 | // 30059: } |
| 13880 | // 30059: } // switch Inst[47] |
| 13881 | // 30059: } |
| 13882 | 6, 0, // 30064: case 0x6: { |
| 13883 | OPC_SwitchField, 47, 1, // 30066: switch Inst[47] { |
| 13884 | 0, 24, // 30069: case 0x0: { |
| 13885 | OPC_CheckField, 16, 8, 0, // 30071: check Inst[23:16] == 0x0 |
| 13886 | OPC_CheckField, 32, 8, 0, // 30075: check Inst[39:32] == 0x0 |
| 13887 | OPC_Scope, 9, // 30079: try { |
| 13888 | OPC_CheckField, 48, 4, 0, // 30081: check Inst[51:48] == 0x0 |
| 13889 | OPC_Decode, 171, 23, 241, 1, // 30085: decode to PVFNMSBivv using decoder 241 |
| 13890 | // 30085: } else try { |
| 13891 | OPC_Decode, 177, 23, 252, 1, // 30090: decode to PVFNMSBivvm using decoder 252 |
| 13892 | // 30090: } |
| 13893 | // 30090: } |
| 13894 | 1, 0, // 30095: case 0x1: { |
| 13895 | OPC_CheckField, 16, 8, 0, // 30097: check Inst[23:16] == 0x0 |
| 13896 | OPC_CheckField, 32, 8, 0, // 30101: check Inst[39:32] == 0x0 |
| 13897 | OPC_Scope, 9, // 30105: try { |
| 13898 | OPC_CheckField, 48, 4, 0, // 30107: check Inst[51:48] == 0x0 |
| 13899 | OPC_Decode, 183, 23, 243, 1, // 30111: decode to PVFNMSBrvv using decoder 243 |
| 13900 | // 30111: } else try { |
| 13901 | OPC_Decode, 189, 23, 253, 1, // 30116: decode to PVFNMSBrvvm using decoder 253 |
| 13902 | // 30116: } |
| 13903 | // 30116: } |
| 13904 | // 30116: } // switch Inst[47] |
| 13905 | // 30116: } |
| 13906 | // 30116: } // switch Inst[54:52] |
| 13907 | // 30116: } |
| 13908 | 232, 3, 63, // 30121: case 0x1e8: { |
| 13909 | OPC_SwitchField, 47, 1, // 30124: switch Inst[47] { |
| 13910 | 0, 28, // 30127: case 0x0: { |
| 13911 | OPC_CheckField, 0, 8, 0, // 30129: check Inst[7:0] == 0x0 |
| 13912 | OPC_CheckField, 32, 8, 0, // 30133: check Inst[39:32] == 0x0 |
| 13913 | OPC_CheckField, 52, 3, 0, // 30137: check Inst[54:52] == 0x0 |
| 13914 | OPC_Scope, 9, // 30141: try { |
| 13915 | OPC_CheckField, 48, 4, 0, // 30143: check Inst[51:48] == 0x0 |
| 13916 | OPC_Decode, 140, 77, 208, 1, // 30147: decode to VSRDvvi using decoder 208 |
| 13917 | // 30147: } else try { |
| 13918 | OPC_Decode, 146, 77, 254, 1, // 30152: decode to VSRDvvim using decoder 254 |
| 13919 | // 30152: } |
| 13920 | // 30152: } |
| 13921 | 1, 0, // 30157: case 0x1: { |
| 13922 | OPC_CheckField, 0, 8, 0, // 30159: check Inst[7:0] == 0x0 |
| 13923 | OPC_CheckField, 32, 8, 0, // 30163: check Inst[39:32] == 0x0 |
| 13924 | OPC_CheckField, 52, 3, 0, // 30167: check Inst[54:52] == 0x0 |
| 13925 | OPC_Scope, 9, // 30171: try { |
| 13926 | OPC_CheckField, 48, 4, 0, // 30173: check Inst[51:48] == 0x0 |
| 13927 | OPC_Decode, 152, 77, 209, 1, // 30177: decode to VSRDvvr using decoder 209 |
| 13928 | // 30177: } else try { |
| 13929 | OPC_Decode, 158, 77, 255, 1, // 30182: decode to VSRDvvrm using decoder 255 |
| 13930 | // 30182: } |
| 13931 | // 30182: } |
| 13932 | // 30182: } // switch Inst[47] |
| 13933 | // 30182: } |
| 13934 | 234, 3, 185, 1, // 30187: case 0x1ea: { |
| 13935 | OPC_SwitchField, 52, 3, // 30191: switch Inst[54:52] { |
| 13936 | 0, 24, // 30194: case 0x0: { |
| 13937 | OPC_CheckField, 0, 8, 0, // 30196: check Inst[7:0] == 0x0 |
| 13938 | OPC_CheckField, 32, 16, 0, // 30200: check Inst[47:32] == 0x0 |
| 13939 | OPC_Scope, 9, // 30204: try { |
| 13940 | OPC_CheckField, 48, 4, 0, // 30206: check Inst[51:48] == 0x0 |
| 13941 | OPC_Decode, 188, 77, 217, 1, // 30210: decode to VSRLvv using decoder 217 |
| 13942 | // 30210: } else try { |
| 13943 | OPC_Decode, 194, 77, 218, 1, // 30215: decode to VSRLvvm using decoder 218 |
| 13944 | // 30215: } |
| 13945 | // 30215: } |
| 13946 | 2, 63, // 30220: case 0x2: { |
| 13947 | OPC_SwitchField, 47, 1, // 30222: switch Inst[47] { |
| 13948 | 0, 28, // 30225: case 0x0: { |
| 13949 | OPC_CheckField, 0, 8, 0, // 30227: check Inst[7:0] == 0x0 |
| 13950 | OPC_CheckField, 16, 8, 0, // 30231: check Inst[23:16] == 0x0 |
| 13951 | OPC_CheckField, 32, 8, 0, // 30235: check Inst[39:32] == 0x0 |
| 13952 | OPC_Scope, 9, // 30239: try { |
| 13953 | OPC_CheckField, 48, 4, 0, // 30241: check Inst[51:48] == 0x0 |
| 13954 | OPC_Decode, 164, 77, 219, 1, // 30245: decode to VSRLvi using decoder 219 |
| 13955 | // 30245: } else try { |
| 13956 | OPC_Decode, 170, 77, 220, 1, // 30250: decode to VSRLvim using decoder 220 |
| 13957 | // 30250: } |
| 13958 | // 30250: } |
| 13959 | 1, 0, // 30255: case 0x1: { |
| 13960 | OPC_CheckField, 0, 8, 0, // 30257: check Inst[7:0] == 0x0 |
| 13961 | OPC_CheckField, 16, 8, 0, // 30261: check Inst[23:16] == 0x0 |
| 13962 | OPC_CheckField, 32, 8, 0, // 30265: check Inst[39:32] == 0x0 |
| 13963 | OPC_Scope, 9, // 30269: try { |
| 13964 | OPC_CheckField, 48, 4, 0, // 30271: check Inst[51:48] == 0x0 |
| 13965 | OPC_Decode, 176, 77, 221, 1, // 30275: decode to VSRLvr using decoder 221 |
| 13966 | // 30275: } else try { |
| 13967 | OPC_Decode, 182, 77, 222, 1, // 30280: decode to VSRLvrm using decoder 222 |
| 13968 | // 30280: } |
| 13969 | // 30280: } |
| 13970 | // 30280: } // switch Inst[47] |
| 13971 | // 30280: } |
| 13972 | 4, 24, // 30285: case 0x4: { |
| 13973 | OPC_CheckField, 0, 8, 0, // 30287: check Inst[7:0] == 0x0 |
| 13974 | OPC_CheckField, 32, 16, 0, // 30291: check Inst[47:32] == 0x0 |
| 13975 | OPC_Scope, 9, // 30295: try { |
| 13976 | OPC_CheckField, 48, 4, 0, // 30297: check Inst[51:48] == 0x0 |
| 13977 | OPC_Decode, 203, 31, 217, 1, // 30301: decode to PVSRLLOvv using decoder 217 |
| 13978 | // 30301: } else try { |
| 13979 | OPC_Decode, 209, 31, 218, 1, // 30306: decode to PVSRLLOvvm using decoder 218 |
| 13980 | // 30306: } |
| 13981 | // 30306: } |
| 13982 | 6, 0, // 30311: case 0x6: { |
| 13983 | OPC_SwitchField, 47, 1, // 30313: switch Inst[47] { |
| 13984 | 0, 28, // 30316: case 0x0: { |
| 13985 | OPC_CheckField, 0, 8, 0, // 30318: check Inst[7:0] == 0x0 |
| 13986 | OPC_CheckField, 16, 8, 0, // 30322: check Inst[23:16] == 0x0 |
| 13987 | OPC_CheckField, 32, 8, 0, // 30326: check Inst[39:32] == 0x0 |
| 13988 | OPC_Scope, 9, // 30330: try { |
| 13989 | OPC_CheckField, 48, 4, 0, // 30332: check Inst[51:48] == 0x0 |
| 13990 | OPC_Decode, 179, 31, 219, 1, // 30336: decode to PVSRLLOvi using decoder 219 |
| 13991 | // 30336: } else try { |
| 13992 | OPC_Decode, 185, 31, 220, 1, // 30341: decode to PVSRLLOvim using decoder 220 |
| 13993 | // 30341: } |
| 13994 | // 30341: } |
| 13995 | 1, 0, // 30346: case 0x1: { |
| 13996 | OPC_CheckField, 0, 8, 0, // 30348: check Inst[7:0] == 0x0 |
| 13997 | OPC_CheckField, 16, 8, 0, // 30352: check Inst[23:16] == 0x0 |
| 13998 | OPC_CheckField, 32, 8, 0, // 30356: check Inst[39:32] == 0x0 |
| 13999 | OPC_Scope, 9, // 30360: try { |
| 14000 | OPC_CheckField, 48, 4, 0, // 30362: check Inst[51:48] == 0x0 |
| 14001 | OPC_Decode, 191, 31, 128, 2, // 30366: decode to PVSRLLOvr using decoder 256 |
| 14002 | // 30366: } else try { |
| 14003 | OPC_Decode, 197, 31, 129, 2, // 30371: decode to PVSRLLOvrm using decoder 257 |
| 14004 | // 30371: } |
| 14005 | // 30371: } |
| 14006 | // 30371: } // switch Inst[47] |
| 14007 | // 30371: } |
| 14008 | // 30371: } // switch Inst[54:52] |
| 14009 | // 30371: } |
| 14010 | 235, 3, 185, 1, // 30376: case 0x1eb: { |
| 14011 | OPC_SwitchField, 52, 3, // 30380: switch Inst[54:52] { |
| 14012 | 0, 24, // 30383: case 0x0: { |
| 14013 | OPC_CheckField, 0, 8, 0, // 30385: check Inst[7:0] == 0x0 |
| 14014 | OPC_CheckField, 32, 16, 0, // 30389: check Inst[47:32] == 0x0 |
| 14015 | OPC_Scope, 9, // 30393: try { |
| 14016 | OPC_CheckField, 48, 4, 0, // 30395: check Inst[51:48] == 0x0 |
| 14017 | OPC_Decode, 239, 31, 217, 1, // 30399: decode to PVSRLUPvv using decoder 217 |
| 14018 | // 30399: } else try { |
| 14019 | OPC_Decode, 245, 31, 218, 1, // 30404: decode to PVSRLUPvvm using decoder 218 |
| 14020 | // 30404: } |
| 14021 | // 30404: } |
| 14022 | 2, 63, // 30409: case 0x2: { |
| 14023 | OPC_SwitchField, 47, 1, // 30411: switch Inst[47] { |
| 14024 | 0, 28, // 30414: case 0x0: { |
| 14025 | OPC_CheckField, 0, 8, 0, // 30416: check Inst[7:0] == 0x0 |
| 14026 | OPC_CheckField, 16, 8, 0, // 30420: check Inst[23:16] == 0x0 |
| 14027 | OPC_CheckField, 32, 8, 0, // 30424: check Inst[39:32] == 0x0 |
| 14028 | OPC_Scope, 9, // 30428: try { |
| 14029 | OPC_CheckField, 48, 4, 0, // 30430: check Inst[51:48] == 0x0 |
| 14030 | OPC_Decode, 215, 31, 219, 1, // 30434: decode to PVSRLUPvi using decoder 219 |
| 14031 | // 30434: } else try { |
| 14032 | OPC_Decode, 221, 31, 220, 1, // 30439: decode to PVSRLUPvim using decoder 220 |
| 14033 | // 30439: } |
| 14034 | // 30439: } |
| 14035 | 1, 0, // 30444: case 0x1: { |
| 14036 | OPC_CheckField, 0, 8, 0, // 30446: check Inst[7:0] == 0x0 |
| 14037 | OPC_CheckField, 16, 8, 0, // 30450: check Inst[23:16] == 0x0 |
| 14038 | OPC_CheckField, 32, 8, 0, // 30454: check Inst[39:32] == 0x0 |
| 14039 | OPC_Scope, 9, // 30458: try { |
| 14040 | OPC_CheckField, 48, 4, 0, // 30460: check Inst[51:48] == 0x0 |
| 14041 | OPC_Decode, 227, 31, 130, 2, // 30464: decode to PVSRLUPvr using decoder 258 |
| 14042 | // 30464: } else try { |
| 14043 | OPC_Decode, 233, 31, 131, 2, // 30469: decode to PVSRLUPvrm using decoder 259 |
| 14044 | // 30469: } |
| 14045 | // 30469: } |
| 14046 | // 30469: } // switch Inst[47] |
| 14047 | // 30469: } |
| 14048 | 4, 24, // 30474: case 0x4: { |
| 14049 | OPC_CheckField, 0, 8, 0, // 30476: check Inst[7:0] == 0x0 |
| 14050 | OPC_CheckField, 32, 16, 0, // 30480: check Inst[47:32] == 0x0 |
| 14051 | OPC_Scope, 9, // 30484: try { |
| 14052 | OPC_CheckField, 48, 4, 0, // 30486: check Inst[51:48] == 0x0 |
| 14053 | OPC_Decode, 147, 32, 217, 1, // 30490: decode to PVSRLvv using decoder 217 |
| 14054 | // 30490: } else try { |
| 14055 | OPC_Decode, 153, 32, 132, 2, // 30495: decode to PVSRLvvm using decoder 260 |
| 14056 | // 30495: } |
| 14057 | // 30495: } |
| 14058 | 6, 0, // 30500: case 0x6: { |
| 14059 | OPC_SwitchField, 47, 1, // 30502: switch Inst[47] { |
| 14060 | 0, 28, // 30505: case 0x0: { |
| 14061 | OPC_CheckField, 0, 8, 0, // 30507: check Inst[7:0] == 0x0 |
| 14062 | OPC_CheckField, 16, 8, 0, // 30511: check Inst[23:16] == 0x0 |
| 14063 | OPC_CheckField, 32, 8, 0, // 30515: check Inst[39:32] == 0x0 |
| 14064 | OPC_Scope, 9, // 30519: try { |
| 14065 | OPC_CheckField, 48, 4, 0, // 30521: check Inst[51:48] == 0x0 |
| 14066 | OPC_Decode, 251, 31, 219, 1, // 30525: decode to PVSRLvi using decoder 219 |
| 14067 | // 30525: } else try { |
| 14068 | OPC_Decode, 129, 32, 133, 2, // 30530: decode to PVSRLvim using decoder 261 |
| 14069 | // 30530: } |
| 14070 | // 30530: } |
| 14071 | 1, 0, // 30535: case 0x1: { |
| 14072 | OPC_CheckField, 0, 8, 0, // 30537: check Inst[7:0] == 0x0 |
| 14073 | OPC_CheckField, 16, 8, 0, // 30541: check Inst[23:16] == 0x0 |
| 14074 | OPC_CheckField, 32, 8, 0, // 30545: check Inst[39:32] == 0x0 |
| 14075 | OPC_Scope, 9, // 30549: try { |
| 14076 | OPC_CheckField, 48, 4, 0, // 30551: check Inst[51:48] == 0x0 |
| 14077 | OPC_Decode, 135, 32, 221, 1, // 30555: decode to PVSRLvr using decoder 221 |
| 14078 | // 30555: } else try { |
| 14079 | OPC_Decode, 141, 32, 134, 2, // 30560: decode to PVSRLvrm using decoder 262 |
| 14080 | // 30560: } |
| 14081 | // 30560: } |
| 14082 | // 30560: } // switch Inst[47] |
| 14083 | // 30560: } |
| 14084 | // 30560: } // switch Inst[54:52] |
| 14085 | // 30560: } |
| 14086 | 236, 3, 185, 1, // 30565: case 0x1ec: { |
| 14087 | OPC_SwitchField, 52, 3, // 30569: switch Inst[54:52] { |
| 14088 | 0, 24, // 30572: case 0x0: { |
| 14089 | OPC_CheckField, 0, 8, 0, // 30574: check Inst[7:0] == 0x0 |
| 14090 | OPC_CheckField, 32, 16, 0, // 30578: check Inst[47:32] == 0x0 |
| 14091 | OPC_Scope, 9, // 30582: try { |
| 14092 | OPC_CheckField, 48, 4, 0, // 30584: check Inst[51:48] == 0x0 |
| 14093 | OPC_Decode, 220, 76, 217, 1, // 30588: decode to VSRAWSXvv using decoder 217 |
| 14094 | // 30588: } else try { |
| 14095 | OPC_Decode, 226, 76, 218, 1, // 30593: decode to VSRAWSXvvm using decoder 218 |
| 14096 | // 30593: } |
| 14097 | // 30593: } |
| 14098 | 2, 63, // 30598: case 0x2: { |
| 14099 | OPC_SwitchField, 47, 1, // 30600: switch Inst[47] { |
| 14100 | 0, 28, // 30603: case 0x0: { |
| 14101 | OPC_CheckField, 0, 8, 0, // 30605: check Inst[7:0] == 0x0 |
| 14102 | OPC_CheckField, 16, 8, 0, // 30609: check Inst[23:16] == 0x0 |
| 14103 | OPC_CheckField, 32, 8, 0, // 30613: check Inst[39:32] == 0x0 |
| 14104 | OPC_Scope, 9, // 30617: try { |
| 14105 | OPC_CheckField, 48, 4, 0, // 30619: check Inst[51:48] == 0x0 |
| 14106 | OPC_Decode, 196, 76, 219, 1, // 30623: decode to VSRAWSXvi using decoder 219 |
| 14107 | // 30623: } else try { |
| 14108 | OPC_Decode, 202, 76, 220, 1, // 30628: decode to VSRAWSXvim using decoder 220 |
| 14109 | // 30628: } |
| 14110 | // 30628: } |
| 14111 | 1, 0, // 30633: case 0x1: { |
| 14112 | OPC_CheckField, 0, 8, 0, // 30635: check Inst[7:0] == 0x0 |
| 14113 | OPC_CheckField, 16, 8, 0, // 30639: check Inst[23:16] == 0x0 |
| 14114 | OPC_CheckField, 32, 8, 0, // 30643: check Inst[39:32] == 0x0 |
| 14115 | OPC_Scope, 9, // 30647: try { |
| 14116 | OPC_CheckField, 48, 4, 0, // 30649: check Inst[51:48] == 0x0 |
| 14117 | OPC_Decode, 208, 76, 128, 2, // 30653: decode to VSRAWSXvr using decoder 256 |
| 14118 | // 30653: } else try { |
| 14119 | OPC_Decode, 214, 76, 129, 2, // 30658: decode to VSRAWSXvrm using decoder 257 |
| 14120 | // 30658: } |
| 14121 | // 30658: } |
| 14122 | // 30658: } // switch Inst[47] |
| 14123 | // 30658: } |
| 14124 | 4, 24, // 30663: case 0x4: { |
| 14125 | OPC_CheckField, 0, 8, 0, // 30665: check Inst[7:0] == 0x0 |
| 14126 | OPC_CheckField, 32, 16, 0, // 30669: check Inst[47:32] == 0x0 |
| 14127 | OPC_Scope, 9, // 30673: try { |
| 14128 | OPC_CheckField, 48, 4, 0, // 30675: check Inst[51:48] == 0x0 |
| 14129 | OPC_Decode, 223, 30, 217, 1, // 30679: decode to PVSRALOvv using decoder 217 |
| 14130 | // 30679: } else try { |
| 14131 | OPC_Decode, 229, 30, 218, 1, // 30684: decode to PVSRALOvvm using decoder 218 |
| 14132 | // 30684: } |
| 14133 | // 30684: } |
| 14134 | 6, 0, // 30689: case 0x6: { |
| 14135 | OPC_SwitchField, 47, 1, // 30691: switch Inst[47] { |
| 14136 | 0, 28, // 30694: case 0x0: { |
| 14137 | OPC_CheckField, 0, 8, 0, // 30696: check Inst[7:0] == 0x0 |
| 14138 | OPC_CheckField, 16, 8, 0, // 30700: check Inst[23:16] == 0x0 |
| 14139 | OPC_CheckField, 32, 8, 0, // 30704: check Inst[39:32] == 0x0 |
| 14140 | OPC_Scope, 9, // 30708: try { |
| 14141 | OPC_CheckField, 48, 4, 0, // 30710: check Inst[51:48] == 0x0 |
| 14142 | OPC_Decode, 199, 30, 219, 1, // 30714: decode to PVSRALOvi using decoder 219 |
| 14143 | // 30714: } else try { |
| 14144 | OPC_Decode, 205, 30, 220, 1, // 30719: decode to PVSRALOvim using decoder 220 |
| 14145 | // 30719: } |
| 14146 | // 30719: } |
| 14147 | 1, 0, // 30724: case 0x1: { |
| 14148 | OPC_CheckField, 0, 8, 0, // 30726: check Inst[7:0] == 0x0 |
| 14149 | OPC_CheckField, 16, 8, 0, // 30730: check Inst[23:16] == 0x0 |
| 14150 | OPC_CheckField, 32, 8, 0, // 30734: check Inst[39:32] == 0x0 |
| 14151 | OPC_Scope, 9, // 30738: try { |
| 14152 | OPC_CheckField, 48, 4, 0, // 30740: check Inst[51:48] == 0x0 |
| 14153 | OPC_Decode, 211, 30, 128, 2, // 30744: decode to PVSRALOvr using decoder 256 |
| 14154 | // 30744: } else try { |
| 14155 | OPC_Decode, 217, 30, 129, 2, // 30749: decode to PVSRALOvrm using decoder 257 |
| 14156 | // 30749: } |
| 14157 | // 30749: } |
| 14158 | // 30749: } // switch Inst[47] |
| 14159 | // 30749: } |
| 14160 | // 30749: } // switch Inst[54:52] |
| 14161 | // 30749: } |
| 14162 | 237, 3, 185, 1, // 30754: case 0x1ed: { |
| 14163 | OPC_SwitchField, 52, 3, // 30758: switch Inst[54:52] { |
| 14164 | 0, 24, // 30761: case 0x0: { |
| 14165 | OPC_CheckField, 0, 8, 0, // 30763: check Inst[7:0] == 0x0 |
| 14166 | OPC_CheckField, 32, 16, 0, // 30767: check Inst[47:32] == 0x0 |
| 14167 | OPC_Scope, 9, // 30771: try { |
| 14168 | OPC_CheckField, 48, 4, 0, // 30773: check Inst[51:48] == 0x0 |
| 14169 | OPC_Decode, 131, 31, 217, 1, // 30777: decode to PVSRAUPvv using decoder 217 |
| 14170 | // 30777: } else try { |
| 14171 | OPC_Decode, 137, 31, 218, 1, // 30782: decode to PVSRAUPvvm using decoder 218 |
| 14172 | // 30782: } |
| 14173 | // 30782: } |
| 14174 | 2, 63, // 30787: case 0x2: { |
| 14175 | OPC_SwitchField, 47, 1, // 30789: switch Inst[47] { |
| 14176 | 0, 28, // 30792: case 0x0: { |
| 14177 | OPC_CheckField, 0, 8, 0, // 30794: check Inst[7:0] == 0x0 |
| 14178 | OPC_CheckField, 16, 8, 0, // 30798: check Inst[23:16] == 0x0 |
| 14179 | OPC_CheckField, 32, 8, 0, // 30802: check Inst[39:32] == 0x0 |
| 14180 | OPC_Scope, 9, // 30806: try { |
| 14181 | OPC_CheckField, 48, 4, 0, // 30808: check Inst[51:48] == 0x0 |
| 14182 | OPC_Decode, 235, 30, 219, 1, // 30812: decode to PVSRAUPvi using decoder 219 |
| 14183 | // 30812: } else try { |
| 14184 | OPC_Decode, 241, 30, 220, 1, // 30817: decode to PVSRAUPvim using decoder 220 |
| 14185 | // 30817: } |
| 14186 | // 30817: } |
| 14187 | 1, 0, // 30822: case 0x1: { |
| 14188 | OPC_CheckField, 0, 8, 0, // 30824: check Inst[7:0] == 0x0 |
| 14189 | OPC_CheckField, 16, 8, 0, // 30828: check Inst[23:16] == 0x0 |
| 14190 | OPC_CheckField, 32, 8, 0, // 30832: check Inst[39:32] == 0x0 |
| 14191 | OPC_Scope, 9, // 30836: try { |
| 14192 | OPC_CheckField, 48, 4, 0, // 30838: check Inst[51:48] == 0x0 |
| 14193 | OPC_Decode, 247, 30, 130, 2, // 30842: decode to PVSRAUPvr using decoder 258 |
| 14194 | // 30842: } else try { |
| 14195 | OPC_Decode, 253, 30, 131, 2, // 30847: decode to PVSRAUPvrm using decoder 259 |
| 14196 | // 30847: } |
| 14197 | // 30847: } |
| 14198 | // 30847: } // switch Inst[47] |
| 14199 | // 30847: } |
| 14200 | 4, 24, // 30852: case 0x4: { |
| 14201 | OPC_CheckField, 0, 8, 0, // 30854: check Inst[7:0] == 0x0 |
| 14202 | OPC_CheckField, 32, 16, 0, // 30858: check Inst[47:32] == 0x0 |
| 14203 | OPC_Scope, 9, // 30862: try { |
| 14204 | OPC_CheckField, 48, 4, 0, // 30864: check Inst[51:48] == 0x0 |
| 14205 | OPC_Decode, 167, 31, 217, 1, // 30868: decode to PVSRAvv using decoder 217 |
| 14206 | // 30868: } else try { |
| 14207 | OPC_Decode, 173, 31, 132, 2, // 30873: decode to PVSRAvvm using decoder 260 |
| 14208 | // 30873: } |
| 14209 | // 30873: } |
| 14210 | 6, 0, // 30878: case 0x6: { |
| 14211 | OPC_SwitchField, 47, 1, // 30880: switch Inst[47] { |
| 14212 | 0, 28, // 30883: case 0x0: { |
| 14213 | OPC_CheckField, 0, 8, 0, // 30885: check Inst[7:0] == 0x0 |
| 14214 | OPC_CheckField, 16, 8, 0, // 30889: check Inst[23:16] == 0x0 |
| 14215 | OPC_CheckField, 32, 8, 0, // 30893: check Inst[39:32] == 0x0 |
| 14216 | OPC_Scope, 9, // 30897: try { |
| 14217 | OPC_CheckField, 48, 4, 0, // 30899: check Inst[51:48] == 0x0 |
| 14218 | OPC_Decode, 143, 31, 219, 1, // 30903: decode to PVSRAvi using decoder 219 |
| 14219 | // 30903: } else try { |
| 14220 | OPC_Decode, 149, 31, 133, 2, // 30908: decode to PVSRAvim using decoder 261 |
| 14221 | // 30908: } |
| 14222 | // 30908: } |
| 14223 | 1, 0, // 30913: case 0x1: { |
| 14224 | OPC_CheckField, 0, 8, 0, // 30915: check Inst[7:0] == 0x0 |
| 14225 | OPC_CheckField, 16, 8, 0, // 30919: check Inst[23:16] == 0x0 |
| 14226 | OPC_CheckField, 32, 8, 0, // 30923: check Inst[39:32] == 0x0 |
| 14227 | OPC_Scope, 9, // 30927: try { |
| 14228 | OPC_CheckField, 48, 4, 0, // 30929: check Inst[51:48] == 0x0 |
| 14229 | OPC_Decode, 155, 31, 221, 1, // 30933: decode to PVSRAvr using decoder 221 |
| 14230 | // 30933: } else try { |
| 14231 | OPC_Decode, 161, 31, 134, 2, // 30938: decode to PVSRAvrm using decoder 262 |
| 14232 | // 30938: } |
| 14233 | // 30938: } |
| 14234 | // 30938: } // switch Inst[47] |
| 14235 | // 30938: } |
| 14236 | // 30938: } // switch Inst[54:52] |
| 14237 | // 30938: } |
| 14238 | 238, 3, 63, // 30943: case 0x1ee: { |
| 14239 | OPC_SwitchField, 52, 3, // 30946: switch Inst[54:52] { |
| 14240 | 0, 28, // 30949: case 0x0: { |
| 14241 | OPC_CheckField, 0, 8, 0, // 30951: check Inst[7:0] == 0x0 |
| 14242 | OPC_CheckField, 16, 8, 0, // 30955: check Inst[23:16] == 0x0 |
| 14243 | OPC_CheckField, 32, 16, 0, // 30959: check Inst[47:32] == 0x0 |
| 14244 | OPC_Scope, 9, // 30963: try { |
| 14245 | OPC_CheckField, 48, 4, 0, // 30965: check Inst[51:48] == 0x0 |
| 14246 | OPC_Decode, 128, 38, 142, 1, // 30969: decode to VBRVv using decoder 142 |
| 14247 | // 30969: } else try { |
| 14248 | OPC_Decode, 134, 38, 143, 1, // 30974: decode to VBRVvm using decoder 143 |
| 14249 | // 30974: } |
| 14250 | // 30974: } |
| 14251 | 4, 0, // 30979: case 0x4: { |
| 14252 | OPC_CheckField, 0, 8, 0, // 30981: check Inst[7:0] == 0x0 |
| 14253 | OPC_CheckField, 16, 8, 0, // 30985: check Inst[23:16] == 0x0 |
| 14254 | OPC_CheckField, 32, 16, 0, // 30989: check Inst[47:32] == 0x0 |
| 14255 | OPC_Scope, 9, // 30993: try { |
| 14256 | OPC_CheckField, 48, 4, 0, // 30995: check Inst[51:48] == 0x0 |
| 14257 | OPC_Decode, 131, 10, 142, 1, // 30999: decode to PVBRVLOv using decoder 142 |
| 14258 | // 30999: } else try { |
| 14259 | OPC_Decode, 137, 10, 143, 1, // 31004: decode to PVBRVLOvm using decoder 143 |
| 14260 | // 31004: } |
| 14261 | // 31004: } |
| 14262 | // 31004: } // switch Inst[54:52] |
| 14263 | // 31004: } |
| 14264 | 239, 3, 63, // 31009: case 0x1ef: { |
| 14265 | OPC_SwitchField, 52, 3, // 31012: switch Inst[54:52] { |
| 14266 | 0, 28, // 31015: case 0x0: { |
| 14267 | OPC_CheckField, 0, 8, 0, // 31017: check Inst[7:0] == 0x0 |
| 14268 | OPC_CheckField, 16, 8, 0, // 31021: check Inst[23:16] == 0x0 |
| 14269 | OPC_CheckField, 32, 16, 0, // 31025: check Inst[47:32] == 0x0 |
| 14270 | OPC_Scope, 9, // 31029: try { |
| 14271 | OPC_CheckField, 48, 4, 0, // 31031: check Inst[51:48] == 0x0 |
| 14272 | OPC_Decode, 143, 10, 142, 1, // 31035: decode to PVBRVUPv using decoder 142 |
| 14273 | // 31035: } else try { |
| 14274 | OPC_Decode, 149, 10, 143, 1, // 31040: decode to PVBRVUPvm using decoder 143 |
| 14275 | // 31040: } |
| 14276 | // 31040: } |
| 14277 | 4, 0, // 31045: case 0x4: { |
| 14278 | OPC_CheckField, 0, 8, 0, // 31047: check Inst[7:0] == 0x0 |
| 14279 | OPC_CheckField, 16, 8, 0, // 31051: check Inst[23:16] == 0x0 |
| 14280 | OPC_CheckField, 32, 16, 0, // 31055: check Inst[47:32] == 0x0 |
| 14281 | OPC_Scope, 9, // 31059: try { |
| 14282 | OPC_CheckField, 48, 4, 0, // 31061: check Inst[51:48] == 0x0 |
| 14283 | OPC_Decode, 155, 10, 142, 1, // 31065: decode to PVBRVv using decoder 142 |
| 14284 | // 31065: } else try { |
| 14285 | OPC_Decode, 161, 10, 183, 1, // 31070: decode to PVBRVvm using decoder 183 |
| 14286 | // 31070: } |
| 14287 | // 31070: } |
| 14288 | // 31070: } // switch Inst[54:52] |
| 14289 | // 31070: } |
| 14290 | 240, 3, 51, // 31075: case 0x1f0: { |
| 14291 | OPC_SwitchField, 52, 3, // 31078: switch Inst[54:52] { |
| 14292 | 0, 22, // 31081: case 0x0: { |
| 14293 | OPC_CheckField, 0, 16, 0, // 31083: check Inst[15:0] == 0x0 |
| 14294 | OPC_CheckField, 32, 16, 0, // 31087: check Inst[47:32] == 0x0 |
| 14295 | OPC_Scope, 8, // 31091: try { |
| 14296 | OPC_CheckField, 48, 4, 0, // 31093: check Inst[51:48] == 0x0 |
| 14297 | OPC_Decode, 228, 39, 119, // 31097: decode to VCVTDWv using decoder 119 |
| 14298 | // 31097: } else try { |
| 14299 | OPC_Decode, 234, 39, 120, // 31101: decode to VCVTDWvm using decoder 120 |
| 14300 | // 31101: } |
| 14301 | // 31101: } |
| 14302 | 5, 0, // 31105: case 0x5: { |
| 14303 | OPC_CheckField, 0, 16, 0, // 31107: check Inst[15:0] == 0x0 |
| 14304 | OPC_CheckField, 32, 16, 0, // 31111: check Inst[47:32] == 0x0 |
| 14305 | OPC_Scope, 8, // 31115: try { |
| 14306 | OPC_CheckField, 48, 4, 0, // 31117: check Inst[51:48] == 0x0 |
| 14307 | OPC_Decode, 255, 11, 119, // 31121: decode to PVCVTSWLOv using decoder 119 |
| 14308 | // 31121: } else try { |
| 14309 | OPC_Decode, 133, 12, 120, // 31125: decode to PVCVTSWLOvm using decoder 120 |
| 14310 | // 31125: } |
| 14311 | // 31125: } |
| 14312 | // 31125: } // switch Inst[54:52] |
| 14313 | // 31125: } |
| 14314 | 241, 3, 76, // 31129: case 0x1f1: { |
| 14315 | OPC_SwitchField, 52, 3, // 31132: switch Inst[54:52] { |
| 14316 | 0, 22, // 31135: case 0x0: { |
| 14317 | OPC_CheckField, 0, 16, 0, // 31137: check Inst[15:0] == 0x0 |
| 14318 | OPC_CheckField, 32, 16, 0, // 31141: check Inst[47:32] == 0x0 |
| 14319 | OPC_Scope, 8, // 31145: try { |
| 14320 | OPC_CheckField, 48, 4, 0, // 31147: check Inst[51:48] == 0x0 |
| 14321 | OPC_Decode, 136, 40, 119, // 31151: decode to VCVTSWv using decoder 119 |
| 14322 | // 31151: } else try { |
| 14323 | OPC_Decode, 142, 40, 120, // 31155: decode to VCVTSWvm using decoder 120 |
| 14324 | // 31155: } |
| 14325 | // 31155: } |
| 14326 | 1, 22, // 31159: case 0x1: { |
| 14327 | OPC_CheckField, 0, 16, 0, // 31161: check Inst[15:0] == 0x0 |
| 14328 | OPC_CheckField, 32, 16, 0, // 31165: check Inst[47:32] == 0x0 |
| 14329 | OPC_Scope, 8, // 31169: try { |
| 14330 | OPC_CheckField, 48, 4, 0, // 31171: check Inst[51:48] == 0x0 |
| 14331 | OPC_Decode, 139, 12, 119, // 31175: decode to PVCVTSWUPv using decoder 119 |
| 14332 | // 31175: } else try { |
| 14333 | OPC_Decode, 145, 12, 120, // 31179: decode to PVCVTSWUPvm using decoder 120 |
| 14334 | // 31179: } |
| 14335 | // 31179: } |
| 14336 | 5, 0, // 31183: case 0x5: { |
| 14337 | OPC_CheckField, 0, 16, 0, // 31185: check Inst[15:0] == 0x0 |
| 14338 | OPC_CheckField, 32, 16, 0, // 31189: check Inst[47:32] == 0x0 |
| 14339 | OPC_Scope, 8, // 31193: try { |
| 14340 | OPC_CheckField, 48, 4, 0, // 31195: check Inst[51:48] == 0x0 |
| 14341 | OPC_Decode, 151, 12, 119, // 31199: decode to PVCVTSWv using decoder 119 |
| 14342 | // 31199: } else try { |
| 14343 | OPC_Decode, 157, 12, 234, 1, // 31203: decode to PVCVTSWvm using decoder 234 |
| 14344 | // 31203: } |
| 14345 | // 31203: } |
| 14346 | // 31203: } // switch Inst[54:52] |
| 14347 | // 31203: } |
| 14348 | 244, 3, 173, 1, // 31208: case 0x1f4: { |
| 14349 | OPC_SwitchField, 52, 3, // 31212: switch Inst[54:52] { |
| 14350 | 0, 22, // 31215: case 0x0: { |
| 14351 | OPC_CheckField, 0, 8, 0, // 31217: check Inst[7:0] == 0x0 |
| 14352 | OPC_CheckField, 32, 16, 0, // 31221: check Inst[47:32] == 0x0 |
| 14353 | OPC_Scope, 8, // 31225: try { |
| 14354 | OPC_CheckField, 48, 4, 0, // 31227: check Inst[51:48] == 0x0 |
| 14355 | OPC_Decode, 200, 38, 121, // 31231: decode to VCMPSWSXvv using decoder 121 |
| 14356 | // 31231: } else try { |
| 14357 | OPC_Decode, 206, 38, 122, // 31235: decode to VCMPSWSXvvm using decoder 122 |
| 14358 | // 31235: } |
| 14359 | // 31235: } |
| 14360 | 2, 59, // 31239: case 0x2: { |
| 14361 | OPC_SwitchField, 47, 1, // 31241: switch Inst[47] { |
| 14362 | 0, 26, // 31244: case 0x0: { |
| 14363 | OPC_CheckField, 0, 8, 0, // 31246: check Inst[7:0] == 0x0 |
| 14364 | OPC_CheckField, 16, 8, 0, // 31250: check Inst[23:16] == 0x0 |
| 14365 | OPC_CheckField, 32, 8, 0, // 31254: check Inst[39:32] == 0x0 |
| 14366 | OPC_Scope, 8, // 31258: try { |
| 14367 | OPC_CheckField, 48, 4, 0, // 31260: check Inst[51:48] == 0x0 |
| 14368 | OPC_Decode, 176, 38, 123, // 31264: decode to VCMPSWSXiv using decoder 123 |
| 14369 | // 31264: } else try { |
| 14370 | OPC_Decode, 182, 38, 124, // 31268: decode to VCMPSWSXivm using decoder 124 |
| 14371 | // 31268: } |
| 14372 | // 31268: } |
| 14373 | 1, 0, // 31272: case 0x1: { |
| 14374 | OPC_CheckField, 0, 8, 0, // 31274: check Inst[7:0] == 0x0 |
| 14375 | OPC_CheckField, 16, 8, 0, // 31278: check Inst[23:16] == 0x0 |
| 14376 | OPC_CheckField, 32, 8, 0, // 31282: check Inst[39:32] == 0x0 |
| 14377 | OPC_Scope, 8, // 31286: try { |
| 14378 | OPC_CheckField, 48, 4, 0, // 31288: check Inst[51:48] == 0x0 |
| 14379 | OPC_Decode, 188, 38, 125, // 31292: decode to VCMPSWSXrv using decoder 125 |
| 14380 | // 31292: } else try { |
| 14381 | OPC_Decode, 194, 38, 126, // 31296: decode to VCMPSWSXrvm using decoder 126 |
| 14382 | // 31296: } |
| 14383 | // 31296: } |
| 14384 | // 31296: } // switch Inst[47] |
| 14385 | // 31296: } |
| 14386 | 4, 22, // 31300: case 0x4: { |
| 14387 | OPC_CheckField, 0, 8, 0, // 31302: check Inst[7:0] == 0x0 |
| 14388 | OPC_CheckField, 32, 16, 0, // 31306: check Inst[47:32] == 0x0 |
| 14389 | OPC_Scope, 8, // 31310: try { |
| 14390 | OPC_CheckField, 48, 4, 0, // 31312: check Inst[51:48] == 0x0 |
| 14391 | OPC_Decode, 191, 10, 121, // 31316: decode to PVCMPSLOvv using decoder 121 |
| 14392 | // 31316: } else try { |
| 14393 | OPC_Decode, 197, 10, 122, // 31320: decode to PVCMPSLOvvm using decoder 122 |
| 14394 | // 31320: } |
| 14395 | // 31320: } |
| 14396 | 6, 0, // 31324: case 0x6: { |
| 14397 | OPC_SwitchField, 47, 1, // 31326: switch Inst[47] { |
| 14398 | 0, 26, // 31329: case 0x0: { |
| 14399 | OPC_CheckField, 0, 8, 0, // 31331: check Inst[7:0] == 0x0 |
| 14400 | OPC_CheckField, 16, 8, 0, // 31335: check Inst[23:16] == 0x0 |
| 14401 | OPC_CheckField, 32, 8, 0, // 31339: check Inst[39:32] == 0x0 |
| 14402 | OPC_Scope, 8, // 31343: try { |
| 14403 | OPC_CheckField, 48, 4, 0, // 31345: check Inst[51:48] == 0x0 |
| 14404 | OPC_Decode, 167, 10, 123, // 31349: decode to PVCMPSLOiv using decoder 123 |
| 14405 | // 31349: } else try { |
| 14406 | OPC_Decode, 173, 10, 124, // 31353: decode to PVCMPSLOivm using decoder 124 |
| 14407 | // 31353: } |
| 14408 | // 31353: } |
| 14409 | 1, 0, // 31357: case 0x1: { |
| 14410 | OPC_CheckField, 0, 8, 0, // 31359: check Inst[7:0] == 0x0 |
| 14411 | OPC_CheckField, 16, 8, 0, // 31363: check Inst[23:16] == 0x0 |
| 14412 | OPC_CheckField, 32, 8, 0, // 31367: check Inst[39:32] == 0x0 |
| 14413 | OPC_Scope, 8, // 31371: try { |
| 14414 | OPC_CheckField, 48, 4, 0, // 31373: check Inst[51:48] == 0x0 |
| 14415 | OPC_Decode, 179, 10, 125, // 31377: decode to PVCMPSLOrv using decoder 125 |
| 14416 | // 31377: } else try { |
| 14417 | OPC_Decode, 185, 10, 126, // 31381: decode to PVCMPSLOrvm using decoder 126 |
| 14418 | // 31381: } |
| 14419 | // 31381: } |
| 14420 | // 31381: } // switch Inst[47] |
| 14421 | // 31381: } |
| 14422 | // 31381: } // switch Inst[54:52] |
| 14423 | // 31381: } |
| 14424 | 245, 3, 177, 1, // 31385: case 0x1f5: { |
| 14425 | OPC_SwitchField, 52, 3, // 31389: switch Inst[54:52] { |
| 14426 | 0, 22, // 31392: case 0x0: { |
| 14427 | OPC_CheckField, 0, 8, 0, // 31394: check Inst[7:0] == 0x0 |
| 14428 | OPC_CheckField, 32, 16, 0, // 31398: check Inst[47:32] == 0x0 |
| 14429 | OPC_Scope, 8, // 31402: try { |
| 14430 | OPC_CheckField, 48, 4, 0, // 31404: check Inst[51:48] == 0x0 |
| 14431 | OPC_Decode, 227, 10, 121, // 31408: decode to PVCMPSUPvv using decoder 121 |
| 14432 | // 31408: } else try { |
| 14433 | OPC_Decode, 233, 10, 122, // 31412: decode to PVCMPSUPvvm using decoder 122 |
| 14434 | // 31412: } |
| 14435 | // 31412: } |
| 14436 | 2, 60, // 31416: case 0x2: { |
| 14437 | OPC_SwitchField, 47, 1, // 31418: switch Inst[47] { |
| 14438 | 0, 26, // 31421: case 0x0: { |
| 14439 | OPC_CheckField, 0, 8, 0, // 31423: check Inst[7:0] == 0x0 |
| 14440 | OPC_CheckField, 16, 8, 0, // 31427: check Inst[23:16] == 0x0 |
| 14441 | OPC_CheckField, 32, 8, 0, // 31431: check Inst[39:32] == 0x0 |
| 14442 | OPC_Scope, 8, // 31435: try { |
| 14443 | OPC_CheckField, 48, 4, 0, // 31437: check Inst[51:48] == 0x0 |
| 14444 | OPC_Decode, 203, 10, 123, // 31441: decode to PVCMPSUPiv using decoder 123 |
| 14445 | // 31441: } else try { |
| 14446 | OPC_Decode, 209, 10, 124, // 31445: decode to PVCMPSUPivm using decoder 124 |
| 14447 | // 31445: } |
| 14448 | // 31445: } |
| 14449 | 1, 0, // 31449: case 0x1: { |
| 14450 | OPC_CheckField, 0, 8, 0, // 31451: check Inst[7:0] == 0x0 |
| 14451 | OPC_CheckField, 16, 8, 0, // 31455: check Inst[23:16] == 0x0 |
| 14452 | OPC_CheckField, 32, 8, 0, // 31459: check Inst[39:32] == 0x0 |
| 14453 | OPC_Scope, 8, // 31463: try { |
| 14454 | OPC_CheckField, 48, 4, 0, // 31465: check Inst[51:48] == 0x0 |
| 14455 | OPC_Decode, 215, 10, 127, // 31469: decode to PVCMPSUPrv using decoder 127 |
| 14456 | // 31469: } else try { |
| 14457 | OPC_Decode, 221, 10, 128, 1, // 31473: decode to PVCMPSUPrvm using decoder 128 |
| 14458 | // 31473: } |
| 14459 | // 31473: } |
| 14460 | // 31473: } // switch Inst[47] |
| 14461 | // 31473: } |
| 14462 | 4, 23, // 31478: case 0x4: { |
| 14463 | OPC_CheckField, 0, 8, 0, // 31480: check Inst[7:0] == 0x0 |
| 14464 | OPC_CheckField, 32, 16, 0, // 31484: check Inst[47:32] == 0x0 |
| 14465 | OPC_Scope, 8, // 31488: try { |
| 14466 | OPC_CheckField, 48, 4, 0, // 31490: check Inst[51:48] == 0x0 |
| 14467 | OPC_Decode, 135, 11, 121, // 31494: decode to PVCMPSvv using decoder 121 |
| 14468 | // 31494: } else try { |
| 14469 | OPC_Decode, 141, 11, 129, 1, // 31498: decode to PVCMPSvvm using decoder 129 |
| 14470 | // 31498: } |
| 14471 | // 31498: } |
| 14472 | 6, 0, // 31503: case 0x6: { |
| 14473 | OPC_SwitchField, 47, 1, // 31505: switch Inst[47] { |
| 14474 | 0, 27, // 31508: case 0x0: { |
| 14475 | OPC_CheckField, 0, 8, 0, // 31510: check Inst[7:0] == 0x0 |
| 14476 | OPC_CheckField, 16, 8, 0, // 31514: check Inst[23:16] == 0x0 |
| 14477 | OPC_CheckField, 32, 8, 0, // 31518: check Inst[39:32] == 0x0 |
| 14478 | OPC_Scope, 8, // 31522: try { |
| 14479 | OPC_CheckField, 48, 4, 0, // 31524: check Inst[51:48] == 0x0 |
| 14480 | OPC_Decode, 239, 10, 123, // 31528: decode to PVCMPSiv using decoder 123 |
| 14481 | // 31528: } else try { |
| 14482 | OPC_Decode, 245, 10, 130, 1, // 31532: decode to PVCMPSivm using decoder 130 |
| 14483 | // 31532: } |
| 14484 | // 31532: } |
| 14485 | 1, 0, // 31537: case 0x1: { |
| 14486 | OPC_CheckField, 0, 8, 0, // 31539: check Inst[7:0] == 0x0 |
| 14487 | OPC_CheckField, 16, 8, 0, // 31543: check Inst[23:16] == 0x0 |
| 14488 | OPC_CheckField, 32, 8, 0, // 31547: check Inst[39:32] == 0x0 |
| 14489 | OPC_Scope, 8, // 31551: try { |
| 14490 | OPC_CheckField, 48, 4, 0, // 31553: check Inst[51:48] == 0x0 |
| 14491 | OPC_Decode, 251, 10, 127, // 31557: decode to PVCMPSrv using decoder 127 |
| 14492 | // 31557: } else try { |
| 14493 | OPC_Decode, 129, 11, 131, 1, // 31561: decode to PVCMPSrvm using decoder 131 |
| 14494 | // 31561: } |
| 14495 | // 31561: } |
| 14496 | // 31561: } // switch Inst[47] |
| 14497 | // 31561: } |
| 14498 | // 31561: } // switch Inst[54:52] |
| 14499 | // 31561: } |
| 14500 | 246, 3, 146, 1, // 31566: case 0x1f6: { |
| 14501 | OPC_SwitchField, 52, 3, // 31570: switch Inst[54:52] { |
| 14502 | 0, 22, // 31573: case 0x0: { |
| 14503 | OPC_CheckField, 0, 8, 0, // 31575: check Inst[7:0] == 0x0 |
| 14504 | OPC_CheckField, 32, 16, 0, // 31579: check Inst[47:32] == 0x0 |
| 14505 | OPC_Scope, 8, // 31583: try { |
| 14506 | OPC_CheckField, 48, 4, 0, // 31585: check Inst[51:48] == 0x0 |
| 14507 | OPC_Decode, 244, 40, 121, // 31589: decode to VDIVSLvv using decoder 121 |
| 14508 | // 31589: } else try { |
| 14509 | OPC_Decode, 250, 40, 122, // 31593: decode to VDIVSLvvm using decoder 122 |
| 14510 | // 31593: } |
| 14511 | // 31593: } |
| 14512 | 1, 55, // 31597: case 0x1: { |
| 14513 | OPC_SwitchField, 47, 1, // 31599: switch Inst[47] { |
| 14514 | 0, 24, // 31602: case 0x0: { |
| 14515 | OPC_CheckField, 0, 16, 0, // 31604: check Inst[15:0] == 0x0 |
| 14516 | OPC_CheckField, 32, 8, 0, // 31608: check Inst[39:32] == 0x0 |
| 14517 | OPC_Scope, 9, // 31612: try { |
| 14518 | OPC_CheckField, 48, 4, 0, // 31614: check Inst[51:48] == 0x0 |
| 14519 | OPC_Decode, 220, 40, 214, 1, // 31618: decode to VDIVSLvi using decoder 214 |
| 14520 | // 31618: } else try { |
| 14521 | OPC_Decode, 226, 40, 231, 1, // 31623: decode to VDIVSLvim using decoder 231 |
| 14522 | // 31623: } |
| 14523 | // 31623: } |
| 14524 | 1, 0, // 31628: case 0x1: { |
| 14525 | OPC_CheckField, 0, 16, 0, // 31630: check Inst[15:0] == 0x0 |
| 14526 | OPC_CheckField, 32, 8, 0, // 31634: check Inst[39:32] == 0x0 |
| 14527 | OPC_Scope, 9, // 31638: try { |
| 14528 | OPC_CheckField, 48, 4, 0, // 31640: check Inst[51:48] == 0x0 |
| 14529 | OPC_Decode, 232, 40, 215, 1, // 31644: decode to VDIVSLvr using decoder 215 |
| 14530 | // 31644: } else try { |
| 14531 | OPC_Decode, 238, 40, 232, 1, // 31649: decode to VDIVSLvrm using decoder 232 |
| 14532 | // 31649: } |
| 14533 | // 31649: } |
| 14534 | // 31649: } // switch Inst[47] |
| 14535 | // 31649: } |
| 14536 | 2, 0, // 31654: case 0x2: { |
| 14537 | OPC_SwitchField, 47, 1, // 31656: switch Inst[47] { |
| 14538 | 0, 26, // 31659: case 0x0: { |
| 14539 | OPC_CheckField, 0, 8, 0, // 31661: check Inst[7:0] == 0x0 |
| 14540 | OPC_CheckField, 16, 8, 0, // 31665: check Inst[23:16] == 0x0 |
| 14541 | OPC_CheckField, 32, 8, 0, // 31669: check Inst[39:32] == 0x0 |
| 14542 | OPC_Scope, 8, // 31673: try { |
| 14543 | OPC_CheckField, 48, 4, 0, // 31675: check Inst[51:48] == 0x0 |
| 14544 | OPC_Decode, 196, 40, 123, // 31679: decode to VDIVSLiv using decoder 123 |
| 14545 | // 31679: } else try { |
| 14546 | OPC_Decode, 202, 40, 124, // 31683: decode to VDIVSLivm using decoder 124 |
| 14547 | // 31683: } |
| 14548 | // 31683: } |
| 14549 | 1, 0, // 31687: case 0x1: { |
| 14550 | OPC_CheckField, 0, 8, 0, // 31689: check Inst[7:0] == 0x0 |
| 14551 | OPC_CheckField, 16, 8, 0, // 31693: check Inst[23:16] == 0x0 |
| 14552 | OPC_CheckField, 32, 8, 0, // 31697: check Inst[39:32] == 0x0 |
| 14553 | OPC_Scope, 8, // 31701: try { |
| 14554 | OPC_CheckField, 48, 4, 0, // 31703: check Inst[51:48] == 0x0 |
| 14555 | OPC_Decode, 208, 40, 127, // 31707: decode to VDIVSLrv using decoder 127 |
| 14556 | // 31707: } else try { |
| 14557 | OPC_Decode, 214, 40, 128, 1, // 31711: decode to VDIVSLrvm using decoder 128 |
| 14558 | // 31711: } |
| 14559 | // 31711: } |
| 14560 | // 31711: } // switch Inst[47] |
| 14561 | // 31711: } |
| 14562 | // 31711: } // switch Inst[54:52] |
| 14563 | // 31711: } |
| 14564 | 248, 3, 175, 1, // 31716: case 0x1f8: { |
| 14565 | OPC_SwitchField, 52, 3, // 31720: switch Inst[54:52] { |
| 14566 | 0, 22, // 31723: case 0x0: { |
| 14567 | OPC_CheckField, 0, 8, 0, // 31725: check Inst[7:0] == 0x0 |
| 14568 | OPC_CheckField, 32, 16, 0, // 31729: check Inst[47:32] == 0x0 |
| 14569 | OPC_Scope, 8, // 31733: try { |
| 14570 | OPC_CheckField, 48, 4, 0, // 31735: check Inst[51:48] == 0x0 |
| 14571 | OPC_Decode, 128, 44, 121, // 31739: decode to VFCMPDvv using decoder 121 |
| 14572 | // 31739: } else try { |
| 14573 | OPC_Decode, 134, 44, 122, // 31743: decode to VFCMPDvvm using decoder 122 |
| 14574 | // 31743: } |
| 14575 | // 31743: } |
| 14576 | 2, 60, // 31747: case 0x2: { |
| 14577 | OPC_SwitchField, 47, 1, // 31749: switch Inst[47] { |
| 14578 | 0, 26, // 31752: case 0x0: { |
| 14579 | OPC_CheckField, 0, 8, 0, // 31754: check Inst[7:0] == 0x0 |
| 14580 | OPC_CheckField, 16, 8, 0, // 31758: check Inst[23:16] == 0x0 |
| 14581 | OPC_CheckField, 32, 8, 0, // 31762: check Inst[39:32] == 0x0 |
| 14582 | OPC_Scope, 8, // 31766: try { |
| 14583 | OPC_CheckField, 48, 4, 0, // 31768: check Inst[51:48] == 0x0 |
| 14584 | OPC_Decode, 232, 43, 123, // 31772: decode to VFCMPDiv using decoder 123 |
| 14585 | // 31772: } else try { |
| 14586 | OPC_Decode, 238, 43, 124, // 31776: decode to VFCMPDivm using decoder 124 |
| 14587 | // 31776: } |
| 14588 | // 31776: } |
| 14589 | 1, 0, // 31780: case 0x1: { |
| 14590 | OPC_CheckField, 0, 8, 0, // 31782: check Inst[7:0] == 0x0 |
| 14591 | OPC_CheckField, 16, 8, 0, // 31786: check Inst[23:16] == 0x0 |
| 14592 | OPC_CheckField, 32, 8, 0, // 31790: check Inst[39:32] == 0x0 |
| 14593 | OPC_Scope, 8, // 31794: try { |
| 14594 | OPC_CheckField, 48, 4, 0, // 31796: check Inst[51:48] == 0x0 |
| 14595 | OPC_Decode, 244, 43, 127, // 31800: decode to VFCMPDrv using decoder 127 |
| 14596 | // 31800: } else try { |
| 14597 | OPC_Decode, 250, 43, 128, 1, // 31804: decode to VFCMPDrvm using decoder 128 |
| 14598 | // 31804: } |
| 14599 | // 31804: } |
| 14600 | // 31804: } // switch Inst[47] |
| 14601 | // 31804: } |
| 14602 | 4, 22, // 31809: case 0x4: { |
| 14603 | OPC_CheckField, 0, 8, 0, // 31811: check Inst[7:0] == 0x0 |
| 14604 | OPC_CheckField, 32, 16, 0, // 31815: check Inst[47:32] == 0x0 |
| 14605 | OPC_Scope, 8, // 31819: try { |
| 14606 | OPC_CheckField, 48, 4, 0, // 31821: check Inst[51:48] == 0x0 |
| 14607 | OPC_Decode, 183, 14, 121, // 31825: decode to PVFCMPLOvv using decoder 121 |
| 14608 | // 31825: } else try { |
| 14609 | OPC_Decode, 189, 14, 122, // 31829: decode to PVFCMPLOvvm using decoder 122 |
| 14610 | // 31829: } |
| 14611 | // 31829: } |
| 14612 | 6, 0, // 31833: case 0x6: { |
| 14613 | OPC_SwitchField, 47, 1, // 31835: switch Inst[47] { |
| 14614 | 0, 26, // 31838: case 0x0: { |
| 14615 | OPC_CheckField, 0, 8, 0, // 31840: check Inst[7:0] == 0x0 |
| 14616 | OPC_CheckField, 16, 8, 0, // 31844: check Inst[23:16] == 0x0 |
| 14617 | OPC_CheckField, 32, 8, 0, // 31848: check Inst[39:32] == 0x0 |
| 14618 | OPC_Scope, 8, // 31852: try { |
| 14619 | OPC_CheckField, 48, 4, 0, // 31854: check Inst[51:48] == 0x0 |
| 14620 | OPC_Decode, 159, 14, 123, // 31858: decode to PVFCMPLOiv using decoder 123 |
| 14621 | // 31858: } else try { |
| 14622 | OPC_Decode, 165, 14, 124, // 31862: decode to PVFCMPLOivm using decoder 124 |
| 14623 | // 31862: } |
| 14624 | // 31862: } |
| 14625 | 1, 0, // 31866: case 0x1: { |
| 14626 | OPC_CheckField, 0, 8, 0, // 31868: check Inst[7:0] == 0x0 |
| 14627 | OPC_CheckField, 16, 8, 0, // 31872: check Inst[23:16] == 0x0 |
| 14628 | OPC_CheckField, 32, 8, 0, // 31876: check Inst[39:32] == 0x0 |
| 14629 | OPC_Scope, 8, // 31880: try { |
| 14630 | OPC_CheckField, 48, 4, 0, // 31882: check Inst[51:48] == 0x0 |
| 14631 | OPC_Decode, 171, 14, 127, // 31886: decode to PVFCMPLOrv using decoder 127 |
| 14632 | // 31886: } else try { |
| 14633 | OPC_Decode, 177, 14, 128, 1, // 31890: decode to PVFCMPLOrvm using decoder 128 |
| 14634 | // 31890: } |
| 14635 | // 31890: } |
| 14636 | // 31890: } // switch Inst[47] |
| 14637 | // 31890: } |
| 14638 | // 31890: } // switch Inst[54:52] |
| 14639 | // 31890: } |
| 14640 | 249, 3, 178, 1, // 31895: case 0x1f9: { |
| 14641 | OPC_SwitchField, 52, 3, // 31899: switch Inst[54:52] { |
| 14642 | 0, 22, // 31902: case 0x0: { |
| 14643 | OPC_CheckField, 0, 8, 0, // 31904: check Inst[7:0] == 0x0 |
| 14644 | OPC_CheckField, 32, 16, 0, // 31908: check Inst[47:32] == 0x0 |
| 14645 | OPC_Scope, 8, // 31912: try { |
| 14646 | OPC_CheckField, 48, 4, 0, // 31914: check Inst[51:48] == 0x0 |
| 14647 | OPC_Decode, 219, 14, 121, // 31918: decode to PVFCMPUPvv using decoder 121 |
| 14648 | // 31918: } else try { |
| 14649 | OPC_Decode, 225, 14, 122, // 31922: decode to PVFCMPUPvvm using decoder 122 |
| 14650 | // 31922: } |
| 14651 | // 31922: } |
| 14652 | 2, 61, // 31926: case 0x2: { |
| 14653 | OPC_SwitchField, 47, 1, // 31928: switch Inst[47] { |
| 14654 | 0, 26, // 31931: case 0x0: { |
| 14655 | OPC_CheckField, 0, 8, 0, // 31933: check Inst[7:0] == 0x0 |
| 14656 | OPC_CheckField, 16, 8, 0, // 31937: check Inst[23:16] == 0x0 |
| 14657 | OPC_CheckField, 32, 8, 0, // 31941: check Inst[39:32] == 0x0 |
| 14658 | OPC_Scope, 8, // 31945: try { |
| 14659 | OPC_CheckField, 48, 4, 0, // 31947: check Inst[51:48] == 0x0 |
| 14660 | OPC_Decode, 195, 14, 123, // 31951: decode to PVFCMPUPiv using decoder 123 |
| 14661 | // 31951: } else try { |
| 14662 | OPC_Decode, 201, 14, 124, // 31955: decode to PVFCMPUPivm using decoder 124 |
| 14663 | // 31955: } |
| 14664 | // 31955: } |
| 14665 | 1, 0, // 31959: case 0x1: { |
| 14666 | OPC_CheckField, 0, 8, 0, // 31961: check Inst[7:0] == 0x0 |
| 14667 | OPC_CheckField, 16, 8, 0, // 31965: check Inst[23:16] == 0x0 |
| 14668 | OPC_CheckField, 32, 8, 0, // 31969: check Inst[39:32] == 0x0 |
| 14669 | OPC_Scope, 9, // 31973: try { |
| 14670 | OPC_CheckField, 48, 4, 0, // 31975: check Inst[51:48] == 0x0 |
| 14671 | OPC_Decode, 207, 14, 210, 1, // 31979: decode to PVFCMPUPrv using decoder 210 |
| 14672 | // 31979: } else try { |
| 14673 | OPC_Decode, 213, 14, 211, 1, // 31984: decode to PVFCMPUPrvm using decoder 211 |
| 14674 | // 31984: } |
| 14675 | // 31984: } |
| 14676 | // 31984: } // switch Inst[47] |
| 14677 | // 31984: } |
| 14678 | 4, 23, // 31989: case 0x4: { |
| 14679 | OPC_CheckField, 0, 8, 0, // 31991: check Inst[7:0] == 0x0 |
| 14680 | OPC_CheckField, 32, 16, 0, // 31995: check Inst[47:32] == 0x0 |
| 14681 | OPC_Scope, 8, // 31999: try { |
| 14682 | OPC_CheckField, 48, 4, 0, // 32001: check Inst[51:48] == 0x0 |
| 14683 | OPC_Decode, 255, 14, 121, // 32005: decode to PVFCMPvv using decoder 121 |
| 14684 | // 32005: } else try { |
| 14685 | OPC_Decode, 133, 15, 129, 1, // 32009: decode to PVFCMPvvm using decoder 129 |
| 14686 | // 32009: } |
| 14687 | // 32009: } |
| 14688 | 6, 0, // 32014: case 0x6: { |
| 14689 | OPC_SwitchField, 47, 1, // 32016: switch Inst[47] { |
| 14690 | 0, 27, // 32019: case 0x0: { |
| 14691 | OPC_CheckField, 0, 8, 0, // 32021: check Inst[7:0] == 0x0 |
| 14692 | OPC_CheckField, 16, 8, 0, // 32025: check Inst[23:16] == 0x0 |
| 14693 | OPC_CheckField, 32, 8, 0, // 32029: check Inst[39:32] == 0x0 |
| 14694 | OPC_Scope, 8, // 32033: try { |
| 14695 | OPC_CheckField, 48, 4, 0, // 32035: check Inst[51:48] == 0x0 |
| 14696 | OPC_Decode, 231, 14, 123, // 32039: decode to PVFCMPiv using decoder 123 |
| 14697 | // 32039: } else try { |
| 14698 | OPC_Decode, 237, 14, 130, 1, // 32043: decode to PVFCMPivm using decoder 130 |
| 14699 | // 32043: } |
| 14700 | // 32043: } |
| 14701 | 1, 0, // 32048: case 0x1: { |
| 14702 | OPC_CheckField, 0, 8, 0, // 32050: check Inst[7:0] == 0x0 |
| 14703 | OPC_CheckField, 16, 8, 0, // 32054: check Inst[23:16] == 0x0 |
| 14704 | OPC_CheckField, 32, 8, 0, // 32058: check Inst[39:32] == 0x0 |
| 14705 | OPC_Scope, 8, // 32062: try { |
| 14706 | OPC_CheckField, 48, 4, 0, // 32064: check Inst[51:48] == 0x0 |
| 14707 | OPC_Decode, 243, 14, 127, // 32068: decode to PVFCMPrv using decoder 127 |
| 14708 | // 32068: } else try { |
| 14709 | OPC_Decode, 249, 14, 131, 1, // 32072: decode to PVFCMPrvm using decoder 131 |
| 14710 | // 32072: } |
| 14711 | // 32072: } |
| 14712 | // 32072: } // switch Inst[47] |
| 14713 | // 32072: } |
| 14714 | // 32072: } // switch Inst[54:52] |
| 14715 | // 32072: } |
| 14716 | 252, 3, 33, // 32077: case 0x1fc: { |
| 14717 | OPC_SwitchField, 47, 8, // 32080: switch Inst[54:47] { |
| 14718 | 0, 13, // 32083: case 0x0: { |
| 14719 | OPC_CheckField, 32, 8, 0, // 32085: check Inst[39:32] == 0x0 |
| 14720 | OPC_CheckField, 0, 8, 0, // 32089: check Inst[7:0] == 0x0 |
| 14721 | OPC_Decode, 172, 46, 138, 2, // 32093: decode to VFISMDvvi using decoder 266 |
| 14722 | // 32093: } |
| 14723 | 1, 0, // 32098: case 0x1: { |
| 14724 | OPC_CheckField, 32, 8, 0, // 32100: check Inst[39:32] == 0x0 |
| 14725 | OPC_CheckField, 0, 8, 0, // 32104: check Inst[7:0] == 0x0 |
| 14726 | OPC_Decode, 178, 46, 209, 1, // 32108: decode to VFISMDvvr using decoder 209 |
| 14727 | // 32108: } |
| 14728 | // 32108: } // switch Inst[54:47] |
| 14729 | // 32108: } |
| 14730 | 253, 3, 33, // 32113: case 0x1fd: { |
| 14731 | OPC_SwitchField, 47, 8, // 32116: switch Inst[54:47] { |
| 14732 | 0, 13, // 32119: case 0x0: { |
| 14733 | OPC_CheckField, 32, 8, 0, // 32121: check Inst[39:32] == 0x0 |
| 14734 | OPC_CheckField, 0, 8, 0, // 32125: check Inst[7:0] == 0x0 |
| 14735 | OPC_Decode, 184, 46, 138, 2, // 32129: decode to VFISMSvvi using decoder 266 |
| 14736 | // 32129: } |
| 14737 | 1, 0, // 32134: case 0x1: { |
| 14738 | OPC_CheckField, 32, 8, 0, // 32136: check Inst[39:32] == 0x0 |
| 14739 | OPC_CheckField, 0, 8, 0, // 32140: check Inst[7:0] == 0x0 |
| 14740 | OPC_Decode, 190, 46, 139, 2, // 32144: decode to VFISMSvvr using decoder 267 |
| 14741 | // 32144: } |
| 14742 | // 32144: } // switch Inst[54:47] |
| 14743 | // 32144: } |
| 14744 | 254, 3, 33, // 32149: case 0x1fe: { |
| 14745 | OPC_SwitchField, 47, 8, // 32152: switch Inst[54:47] { |
| 14746 | 0, 13, // 32155: case 0x0: { |
| 14747 | OPC_CheckField, 32, 8, 0, // 32157: check Inst[39:32] == 0x0 |
| 14748 | OPC_CheckField, 0, 8, 0, // 32161: check Inst[7:0] == 0x0 |
| 14749 | OPC_Decode, 252, 45, 138, 2, // 32165: decode to VFIMSDvvi using decoder 266 |
| 14750 | // 32165: } |
| 14751 | 1, 0, // 32170: case 0x1: { |
| 14752 | OPC_CheckField, 32, 8, 0, // 32172: check Inst[39:32] == 0x0 |
| 14753 | OPC_CheckField, 0, 8, 0, // 32176: check Inst[7:0] == 0x0 |
| 14754 | OPC_Decode, 130, 46, 209, 1, // 32180: decode to VFIMSDvvr using decoder 209 |
| 14755 | // 32180: } |
| 14756 | // 32180: } // switch Inst[54:47] |
| 14757 | // 32180: } |
| 14758 | 255, 3, 0, // 32185: case 0x1ff: { |
| 14759 | OPC_SwitchField, 47, 8, // 32188: switch Inst[54:47] { |
| 14760 | 0, 13, // 32191: case 0x0: { |
| 14761 | OPC_CheckField, 32, 8, 0, // 32193: check Inst[39:32] == 0x0 |
| 14762 | OPC_CheckField, 0, 8, 0, // 32197: check Inst[7:0] == 0x0 |
| 14763 | OPC_Decode, 136, 46, 138, 2, // 32201: decode to VFIMSSvvi using decoder 266 |
| 14764 | // 32201: } |
| 14765 | 1, 0, // 32206: case 0x1: { |
| 14766 | OPC_CheckField, 32, 8, 0, // 32208: check Inst[39:32] == 0x0 |
| 14767 | OPC_CheckField, 0, 8, 0, // 32212: check Inst[7:0] == 0x0 |
| 14768 | OPC_Decode, 142, 46, 139, 2, // 32216: decode to VFIMSSvvr using decoder 267 |
| 14769 | // 32216: } |
| 14770 | // 32216: } // switch Inst[54:47] |
| 14771 | // 32216: } |
| 14772 | // 32216: } // switch Inst[63:55] |
| 14773 | }; |
| 14774 | // Handling 268 cases. |
| 14775 | template <typename InsnType> |
| 14776 | static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) { |
| 14777 | DecodeComplete = true; |
| 14778 | using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>; |
| 14779 | TmpType tmp; |
| 14780 | switch (Idx) { |
| 14781 | default: llvm_unreachable("Invalid decoder index!"); |
| 14782 | case 0: |
| 14783 | if (!Check(S, DecodeLoadI64(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14784 | return S; |
| 14785 | case 1: |
| 14786 | if (!Check(S, DecodeLoadF32(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14787 | return S; |
| 14788 | case 2: |
| 14789 | if (!Check(S, DecodeLoadI32(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14790 | return S; |
| 14791 | case 3: |
| 14792 | if (!Check(S, DecodeCall(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14793 | return S; |
| 14794 | case 4: |
| 14795 | if (!Check(S, DecodeASX(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14796 | return S; |
| 14797 | case 5: |
| 14798 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14799 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14800 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14801 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14802 | return S; |
| 14803 | case 6: |
| 14804 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14805 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14806 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14807 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14808 | return S; |
| 14809 | case 7: |
| 14810 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14811 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14812 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14813 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14814 | return S; |
| 14815 | case 8: |
| 14816 | if (!Check(S, DecodeStoreI64(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14817 | return S; |
| 14818 | case 9: |
| 14819 | if (!Check(S, DecodeStoreF32(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14820 | return S; |
| 14821 | case 10: |
| 14822 | if (!Check(S, DecodeStoreI32(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14823 | return S; |
| 14824 | case 11: |
| 14825 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14826 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14827 | return S; |
| 14828 | case 12: |
| 14829 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14830 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14831 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14832 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14833 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14834 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 14835 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14836 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14837 | return S; |
| 14838 | case 13: |
| 14839 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14840 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14841 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14842 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14843 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14844 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 14845 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14846 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14847 | return S; |
| 14848 | case 14: |
| 14849 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14850 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14851 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14852 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14853 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14854 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14855 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14856 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14857 | return S; |
| 14858 | case 15: |
| 14859 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14860 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14861 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14862 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14863 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14864 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14865 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14866 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14867 | return S; |
| 14868 | case 16: |
| 14869 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14870 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14871 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14872 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14873 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14874 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 14875 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14876 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14877 | return S; |
| 14878 | case 17: |
| 14879 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14880 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14881 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14882 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14883 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14884 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14885 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14886 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14887 | return S; |
| 14888 | case 18: |
| 14889 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14890 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14891 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14892 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14893 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14894 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14895 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14896 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14897 | return S; |
| 14898 | case 19: |
| 14899 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14900 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14901 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14902 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14903 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14904 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 14905 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14906 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14907 | return S; |
| 14908 | case 20: |
| 14909 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14910 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14911 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14912 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14913 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14914 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14915 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14916 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14917 | return S; |
| 14918 | case 21: |
| 14919 | tmp = fieldFromInstruction(insn, 48, 4); |
| 14920 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14921 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14922 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14923 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14924 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14925 | tmp = fieldFromInstruction(insn, 0, 32); |
| 14926 | if (!Check(S, DecodeSIMM32(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14927 | return S; |
| 14928 | case 22: |
| 14929 | if (!Check(S, DecodeBranchConditionAlways(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14930 | return S; |
| 14931 | case 23: |
| 14932 | if (!Check(S, DecodeBranchCondition(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14933 | return S; |
| 14934 | case 24: |
| 14935 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14936 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14937 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14938 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14939 | return S; |
| 14940 | case 25: |
| 14941 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14942 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14943 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14944 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14945 | return S; |
| 14946 | case 26: |
| 14947 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14948 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14949 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14950 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14951 | return S; |
| 14952 | case 27: |
| 14953 | tmp = fieldFromInstruction(insn, 48, 2); |
| 14954 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 14955 | return S; |
| 14956 | case 28: |
| 14957 | tmp = fieldFromInstruction(insn, 40, 3); |
| 14958 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 14959 | return S; |
| 14960 | case 29: |
| 14961 | return S; |
| 14962 | case 30: |
| 14963 | if (!Check(S, DecodeLoadASI64(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14964 | return S; |
| 14965 | case 31: |
| 14966 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14967 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14968 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14969 | if (!Check(S, DecodeMISCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14970 | return S; |
| 14971 | case 32: |
| 14972 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14973 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14974 | return S; |
| 14975 | case 33: |
| 14976 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14977 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14978 | return S; |
| 14979 | case 34: |
| 14980 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14981 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14982 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14983 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 14984 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14985 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 14986 | return S; |
| 14987 | case 35: |
| 14988 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14989 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14990 | tmp = fieldFromInstruction(insn, 32, 7); |
| 14991 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14992 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14993 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 14994 | return S; |
| 14995 | case 36: |
| 14996 | tmp = fieldFromInstruction(insn, 48, 7); |
| 14997 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14998 | tmp = fieldFromInstruction(insn, 40, 7); |
| 14999 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15000 | return S; |
| 15001 | case 37: |
| 15002 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15003 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15004 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15005 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15006 | return S; |
| 15007 | case 38: |
| 15008 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15009 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15010 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15011 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15012 | return S; |
| 15013 | case 39: |
| 15014 | if (!Check(S, DecodeStoreASI64(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15015 | return S; |
| 15016 | case 40: |
| 15017 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15018 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15019 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15020 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15021 | return S; |
| 15022 | case 41: |
| 15023 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15024 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15025 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15026 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15027 | return S; |
| 15028 | case 42: |
| 15029 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15030 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15031 | return S; |
| 15032 | case 43: |
| 15033 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15034 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15035 | tmp = fieldFromInstruction(insn, 0, 4); |
| 15036 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15037 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15038 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15039 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15040 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15041 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15042 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15043 | return S; |
| 15044 | case 44: |
| 15045 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15046 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15047 | tmp = fieldFromInstruction(insn, 0, 4); |
| 15048 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15049 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15050 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15051 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15052 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15053 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15054 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15055 | return S; |
| 15056 | case 45: |
| 15057 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15058 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15059 | tmp = fieldFromInstruction(insn, 0, 4); |
| 15060 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15061 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15062 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15063 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15064 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15065 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15066 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15067 | return S; |
| 15068 | case 46: |
| 15069 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15070 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15071 | tmp = fieldFromInstruction(insn, 0, 4); |
| 15072 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15073 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15074 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15075 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15076 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15077 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15078 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15079 | return S; |
| 15080 | case 47: |
| 15081 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15082 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15083 | tmp = fieldFromInstruction(insn, 0, 4); |
| 15084 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15085 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15086 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15087 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15088 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15089 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15090 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15091 | return S; |
| 15092 | case 48: |
| 15093 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15094 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15095 | tmp = fieldFromInstruction(insn, 0, 4); |
| 15096 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15097 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15098 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15099 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15100 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15101 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15102 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15103 | return S; |
| 15104 | case 49: |
| 15105 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15106 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15107 | tmp = fieldFromInstruction(insn, 0, 4); |
| 15108 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15109 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15110 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15111 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15112 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15113 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15114 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15115 | return S; |
| 15116 | case 50: |
| 15117 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15118 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15119 | tmp = fieldFromInstruction(insn, 0, 4); |
| 15120 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15121 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15122 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15123 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15124 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15125 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15126 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15127 | return S; |
| 15128 | case 51: |
| 15129 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15130 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15131 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15132 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15133 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15134 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15135 | return S; |
| 15136 | case 52: |
| 15137 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15138 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15139 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15140 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15141 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15142 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15143 | return S; |
| 15144 | case 53: |
| 15145 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15146 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15147 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15148 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15149 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15150 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15151 | return S; |
| 15152 | case 54: |
| 15153 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15154 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15155 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15156 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15157 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15158 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15159 | return S; |
| 15160 | case 55: |
| 15161 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15162 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15163 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15164 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15165 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15166 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15167 | return S; |
| 15168 | case 56: |
| 15169 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15170 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15171 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15172 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15173 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15174 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15175 | return S; |
| 15176 | case 57: |
| 15177 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15178 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15179 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15180 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15181 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15182 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15183 | return S; |
| 15184 | case 58: |
| 15185 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15186 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15187 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15188 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15189 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15190 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15191 | return S; |
| 15192 | case 59: |
| 15193 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15194 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15195 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15196 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15197 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15198 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15199 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15200 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15201 | return S; |
| 15202 | case 60: |
| 15203 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15204 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15205 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15206 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15207 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15208 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15209 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15210 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15211 | return S; |
| 15212 | case 61: |
| 15213 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15214 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15215 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15216 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15217 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15218 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15219 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15220 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15221 | return S; |
| 15222 | case 62: |
| 15223 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15224 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15225 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15226 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15227 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15228 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15229 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15230 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15231 | return S; |
| 15232 | case 63: |
| 15233 | if (!Check(S, DecodeTS1AMI64(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15234 | return S; |
| 15235 | case 64: |
| 15236 | if (!Check(S, DecodeTS1AMI32(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15237 | return S; |
| 15238 | case 65: |
| 15239 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15240 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15241 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15242 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15243 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15244 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15245 | return S; |
| 15246 | case 66: |
| 15247 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15248 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15249 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15250 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15251 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15252 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15253 | return S; |
| 15254 | case 67: |
| 15255 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15256 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15257 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15258 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15259 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15260 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15261 | return S; |
| 15262 | case 68: |
| 15263 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15264 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15265 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15266 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15267 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15268 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15269 | return S; |
| 15270 | case 69: |
| 15271 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15272 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15273 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15274 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15275 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15276 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15277 | return S; |
| 15278 | case 70: |
| 15279 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15280 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15281 | tmp = fieldFromInstruction(insn, 32, 4); |
| 15282 | if (!Check(S, DecodeRDOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15283 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15284 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15285 | return S; |
| 15286 | case 71: |
| 15287 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15288 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15289 | tmp = fieldFromInstruction(insn, 32, 4); |
| 15290 | if (!Check(S, DecodeRDOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15291 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15292 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15293 | return S; |
| 15294 | case 72: |
| 15295 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15296 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15297 | tmp = fieldFromInstruction(insn, 32, 4); |
| 15298 | if (!Check(S, DecodeRDOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15299 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15300 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15301 | return S; |
| 15302 | case 73: |
| 15303 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15304 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15305 | tmp = fieldFromInstruction(insn, 32, 4); |
| 15306 | if (!Check(S, DecodeRDOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15307 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15308 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15309 | return S; |
| 15310 | case 74: |
| 15311 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15312 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15313 | tmp = fieldFromInstruction(insn, 32, 4); |
| 15314 | if (!Check(S, DecodeRDOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15315 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15316 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15317 | return S; |
| 15318 | case 75: |
| 15319 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15320 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15321 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15322 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15323 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15324 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15325 | return S; |
| 15326 | case 76: |
| 15327 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15328 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15329 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15330 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15331 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15332 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15333 | return S; |
| 15334 | case 77: |
| 15335 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15336 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15337 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15338 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15339 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15340 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15341 | return S; |
| 15342 | case 78: |
| 15343 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15344 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15345 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15346 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15347 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15348 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15349 | return S; |
| 15350 | case 79: |
| 15351 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15352 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15353 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15354 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15355 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15356 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15357 | return S; |
| 15358 | case 80: |
| 15359 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15360 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15361 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15362 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15363 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15364 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15365 | return S; |
| 15366 | case 81: |
| 15367 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15368 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15369 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15370 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15371 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15372 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15373 | return S; |
| 15374 | case 82: |
| 15375 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15376 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15377 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15378 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15379 | return S; |
| 15380 | case 83: |
| 15381 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15382 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15383 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15384 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15385 | return S; |
| 15386 | case 84: |
| 15387 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15388 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15389 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15390 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15391 | return S; |
| 15392 | case 85: |
| 15393 | if (!Check(S, DecodeCASI64(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15394 | return S; |
| 15395 | case 86: |
| 15396 | if (!Check(S, DecodeCASI32(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15397 | return S; |
| 15398 | case 87: |
| 15399 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15400 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15401 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15402 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15403 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15404 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15405 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15406 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15407 | return S; |
| 15408 | case 88: |
| 15409 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15410 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15411 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15412 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15413 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15414 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15415 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15416 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15417 | return S; |
| 15418 | case 89: |
| 15419 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15420 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15421 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15422 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15423 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15424 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15425 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15426 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15427 | return S; |
| 15428 | case 90: |
| 15429 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15430 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15431 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15432 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15433 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15434 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15435 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15436 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15437 | return S; |
| 15438 | case 91: |
| 15439 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15440 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15441 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15442 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15443 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15444 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15445 | return S; |
| 15446 | case 92: |
| 15447 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15448 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15449 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15450 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15451 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15452 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15453 | return S; |
| 15454 | case 93: |
| 15455 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15456 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15457 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15458 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15459 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15460 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15461 | return S; |
| 15462 | case 94: |
| 15463 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15464 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15465 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15466 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15467 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15468 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15469 | return S; |
| 15470 | case 95: |
| 15471 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15472 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15473 | return S; |
| 15474 | case 96: |
| 15475 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15476 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15477 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15478 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15479 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15480 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15481 | return S; |
| 15482 | case 97: |
| 15483 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15484 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15485 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15486 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15487 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15488 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15489 | return S; |
| 15490 | case 98: |
| 15491 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15492 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15493 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15494 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15495 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15496 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15497 | return S; |
| 15498 | case 99: |
| 15499 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15500 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15501 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15502 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15503 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15504 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15505 | return S; |
| 15506 | case 100: |
| 15507 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15508 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15509 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15510 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15511 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15512 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15513 | return S; |
| 15514 | case 101: |
| 15515 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15516 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15517 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15518 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15519 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15520 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15521 | return S; |
| 15522 | case 102: |
| 15523 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15524 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15525 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15526 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15527 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15528 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15529 | return S; |
| 15530 | case 103: |
| 15531 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15532 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15533 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15534 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15535 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15536 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15537 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15538 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15539 | return S; |
| 15540 | case 104: |
| 15541 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15542 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15543 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15544 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15545 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15546 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15547 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15548 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15549 | return S; |
| 15550 | case 105: |
| 15551 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15552 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15553 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15554 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15555 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15556 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15557 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15558 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15559 | return S; |
| 15560 | case 106: |
| 15561 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15562 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15563 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15564 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15565 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15566 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15567 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15568 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15569 | return S; |
| 15570 | case 107: |
| 15571 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15572 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15573 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15574 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15575 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15576 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15577 | return S; |
| 15578 | case 108: |
| 15579 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15580 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15581 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15582 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15583 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15584 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15585 | return S; |
| 15586 | case 109: |
| 15587 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15588 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15589 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15590 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15591 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15592 | if (!Check(S, DecodeF128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15593 | return S; |
| 15594 | case 110: |
| 15595 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15596 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15597 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15598 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15599 | return S; |
| 15600 | case 111: |
| 15601 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15602 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15603 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15604 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15605 | return S; |
| 15606 | case 112: |
| 15607 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15608 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15609 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15610 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15611 | return S; |
| 15612 | case 113: |
| 15613 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15614 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15615 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15616 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15617 | return S; |
| 15618 | case 114: |
| 15619 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15620 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15621 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15622 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15623 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15624 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15625 | return S; |
| 15626 | case 115: |
| 15627 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15628 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15629 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15630 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15631 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15632 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15633 | return S; |
| 15634 | case 116: |
| 15635 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15636 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15637 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15638 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15639 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15640 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15641 | return S; |
| 15642 | case 117: |
| 15643 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15644 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15645 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15646 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15647 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15648 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15649 | return S; |
| 15650 | case 118: |
| 15651 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15652 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15653 | tmp = fieldFromInstruction(insn, 16, 8); |
| 15654 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15655 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15656 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15657 | return S; |
| 15658 | case 119: |
| 15659 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15660 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15661 | tmp = fieldFromInstruction(insn, 16, 8); |
| 15662 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15663 | return S; |
| 15664 | case 120: |
| 15665 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15666 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15667 | tmp = fieldFromInstruction(insn, 16, 8); |
| 15668 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15669 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15670 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15671 | return S; |
| 15672 | case 121: |
| 15673 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15674 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15675 | tmp = fieldFromInstruction(insn, 16, 8); |
| 15676 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15677 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15678 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15679 | return S; |
| 15680 | case 122: |
| 15681 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15682 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15683 | tmp = fieldFromInstruction(insn, 16, 8); |
| 15684 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15685 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15686 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15687 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15688 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15689 | return S; |
| 15690 | case 123: |
| 15691 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15692 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15693 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15694 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15695 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15696 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15697 | return S; |
| 15698 | case 124: |
| 15699 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15700 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15701 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15702 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15703 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15704 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15705 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15706 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15707 | return S; |
| 15708 | case 125: |
| 15709 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15710 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15711 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15712 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15713 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15714 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15715 | return S; |
| 15716 | case 126: |
| 15717 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15718 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15719 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15720 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15721 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15722 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15723 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15724 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15725 | return S; |
| 15726 | case 127: |
| 15727 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15728 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15729 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15730 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15731 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15732 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15733 | return S; |
| 15734 | case 128: |
| 15735 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15736 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15737 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15738 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15739 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15740 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15741 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15742 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15743 | return S; |
| 15744 | case 129: |
| 15745 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15746 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15747 | tmp = fieldFromInstruction(insn, 16, 8); |
| 15748 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15749 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15750 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15751 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15752 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15753 | return S; |
| 15754 | case 130: |
| 15755 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15756 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15757 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15758 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15759 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15760 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15761 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15762 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15763 | return S; |
| 15764 | case 131: |
| 15765 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15766 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15767 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15768 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15769 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15770 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15771 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15772 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15773 | return S; |
| 15774 | case 132: |
| 15775 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15776 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15777 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15778 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15779 | return S; |
| 15780 | case 133: |
| 15781 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15782 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15783 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15784 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15785 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15786 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15787 | return S; |
| 15788 | case 134: |
| 15789 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15790 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15791 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15792 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15793 | return S; |
| 15794 | case 135: |
| 15795 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15796 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15797 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15798 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15799 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15800 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15801 | return S; |
| 15802 | case 136: |
| 15803 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15804 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15805 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15806 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15807 | return S; |
| 15808 | case 137: |
| 15809 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15810 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15811 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15812 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15813 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15814 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15815 | return S; |
| 15816 | case 138: |
| 15817 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15818 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15819 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15820 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15821 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15822 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15823 | return S; |
| 15824 | case 139: |
| 15825 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15826 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15827 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15828 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15829 | return S; |
| 15830 | case 140: |
| 15831 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15832 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15833 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15834 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15835 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15836 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15837 | return S; |
| 15838 | case 141: |
| 15839 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15840 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15841 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15842 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15843 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15844 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15845 | return S; |
| 15846 | case 142: |
| 15847 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15848 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15849 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15850 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15851 | return S; |
| 15852 | case 143: |
| 15853 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15854 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15855 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15856 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15857 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15858 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15859 | return S; |
| 15860 | case 144: |
| 15861 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15862 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15863 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15864 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15865 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15866 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15867 | return S; |
| 15868 | case 145: |
| 15869 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15870 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15871 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15872 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15873 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15874 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15875 | return S; |
| 15876 | case 146: |
| 15877 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15878 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15879 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15880 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15881 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15882 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15883 | return S; |
| 15884 | case 147: |
| 15885 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15886 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15887 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15888 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15889 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15890 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15891 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15892 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15893 | return S; |
| 15894 | case 148: |
| 15895 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15896 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15897 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15898 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15899 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15900 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15901 | return S; |
| 15902 | case 149: |
| 15903 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15904 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15905 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15906 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15907 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15908 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15909 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15910 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15911 | return S; |
| 15912 | case 150: |
| 15913 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15914 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15915 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15916 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15917 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15918 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15919 | return S; |
| 15920 | case 151: |
| 15921 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15922 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15923 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15924 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15925 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15926 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15927 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15928 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15929 | return S; |
| 15930 | case 152: |
| 15931 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15932 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15933 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15934 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15935 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15936 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15937 | return S; |
| 15938 | case 153: |
| 15939 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15940 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15941 | tmp = fieldFromInstruction(insn, 32, 7); |
| 15942 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15943 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15944 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15945 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15946 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15947 | return S; |
| 15948 | case 154: |
| 15949 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15950 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15951 | tmp = fieldFromInstruction(insn, 16, 8); |
| 15952 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15953 | return S; |
| 15954 | case 155: |
| 15955 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15956 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15957 | return S; |
| 15958 | case 156: |
| 15959 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15960 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15961 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15962 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15963 | return S; |
| 15964 | case 157: |
| 15965 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15966 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15967 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15968 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15969 | return S; |
| 15970 | case 158: |
| 15971 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15972 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15973 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15974 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15975 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15976 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15977 | return S; |
| 15978 | case 159: |
| 15979 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15980 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15981 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15982 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15983 | tmp = fieldFromInstruction(insn, 8, 8); |
| 15984 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15985 | tmp = fieldFromInstruction(insn, 48, 4); |
| 15986 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15987 | return S; |
| 15988 | case 160: |
| 15989 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15990 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15991 | tmp = fieldFromInstruction(insn, 24, 8); |
| 15992 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15993 | tmp = fieldFromInstruction(insn, 40, 7); |
| 15994 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 15995 | return S; |
| 15996 | case 161: |
| 15997 | tmp = fieldFromInstruction(insn, 48, 7); |
| 15998 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15999 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16000 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16001 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16002 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16003 | return S; |
| 16004 | case 162: |
| 16005 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16006 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16007 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16008 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16009 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16010 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16011 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16012 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16013 | return S; |
| 16014 | case 163: |
| 16015 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16016 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16017 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16018 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16019 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16020 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16021 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16022 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16023 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16024 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16025 | return S; |
| 16026 | case 164: |
| 16027 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16028 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16029 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16030 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16031 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16032 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16033 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16034 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16035 | return S; |
| 16036 | case 165: |
| 16037 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16038 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16039 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16040 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16041 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16042 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16043 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16044 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16045 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16046 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16047 | return S; |
| 16048 | case 166: |
| 16049 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16050 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16051 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16052 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16053 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16054 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16055 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16056 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16057 | return S; |
| 16058 | case 167: |
| 16059 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16060 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16061 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16062 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16063 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16064 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16065 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16066 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16067 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16068 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16069 | return S; |
| 16070 | case 168: |
| 16071 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16072 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16073 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16074 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16075 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16076 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16077 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16078 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16079 | return S; |
| 16080 | case 169: |
| 16081 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16082 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16083 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16084 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16085 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16086 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16087 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16088 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16089 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16090 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16091 | return S; |
| 16092 | case 170: |
| 16093 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16094 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16095 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16096 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16097 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16098 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16099 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16100 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16101 | return S; |
| 16102 | case 171: |
| 16103 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16104 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16105 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16106 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16107 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16108 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16109 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16110 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16111 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16112 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16113 | return S; |
| 16114 | case 172: |
| 16115 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16116 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16117 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16118 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16119 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16120 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16121 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16122 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16123 | return S; |
| 16124 | case 173: |
| 16125 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16126 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16127 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16128 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16129 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16130 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16131 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16132 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16133 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16134 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16135 | return S; |
| 16136 | case 174: |
| 16137 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16138 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16139 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16140 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16141 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16142 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16143 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16144 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16145 | return S; |
| 16146 | case 175: |
| 16147 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16148 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16149 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16150 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16151 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16152 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16153 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16154 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16155 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16156 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16157 | return S; |
| 16158 | case 176: |
| 16159 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16160 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16161 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16162 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16163 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16164 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16165 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16166 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16167 | return S; |
| 16168 | case 177: |
| 16169 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16170 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16171 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16172 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16173 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16174 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16175 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16176 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16177 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16178 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16179 | return S; |
| 16180 | case 178: |
| 16181 | tmp = fieldFromInstruction(insn, 48, 7); |
| 16182 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16183 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16184 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16185 | return S; |
| 16186 | case 179: |
| 16187 | tmp = fieldFromInstruction(insn, 48, 7); |
| 16188 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16189 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16190 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16191 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16192 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16193 | return S; |
| 16194 | case 180: |
| 16195 | tmp = fieldFromInstruction(insn, 48, 7); |
| 16196 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16197 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16198 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16199 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16200 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16201 | return S; |
| 16202 | case 181: |
| 16203 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16204 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16205 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16206 | if (!Check(S, DecodeRDOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16207 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16208 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16209 | return S; |
| 16210 | case 182: |
| 16211 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16212 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16213 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16214 | if (!Check(S, DecodeRDOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16215 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16216 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16217 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16218 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16219 | return S; |
| 16220 | case 183: |
| 16221 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16222 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16223 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16224 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16225 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16226 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16227 | return S; |
| 16228 | case 184: |
| 16229 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16230 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16231 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16232 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16233 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16234 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16235 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16236 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16237 | return S; |
| 16238 | case 185: |
| 16239 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16240 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16241 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16242 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16243 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16244 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16245 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16246 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16247 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16248 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16249 | return S; |
| 16250 | case 186: |
| 16251 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16252 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16253 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16254 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16255 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16256 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16257 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16258 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16259 | return S; |
| 16260 | case 187: |
| 16261 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16262 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16263 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16264 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16265 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16266 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16267 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16268 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16269 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16270 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16271 | return S; |
| 16272 | case 188: |
| 16273 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16274 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16275 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16276 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16277 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16278 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16279 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16280 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16281 | return S; |
| 16282 | case 189: |
| 16283 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16284 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16285 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16286 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16287 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16288 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16289 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16290 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16291 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16292 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16293 | return S; |
| 16294 | case 190: |
| 16295 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16296 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16297 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16298 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16299 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16300 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16301 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16302 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16303 | return S; |
| 16304 | case 191: |
| 16305 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16306 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16307 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16308 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16309 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16310 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16311 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16312 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16313 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16314 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16315 | return S; |
| 16316 | case 192: |
| 16317 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16318 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16319 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16320 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16321 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16322 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16323 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16324 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16325 | return S; |
| 16326 | case 193: |
| 16327 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16328 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16329 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16330 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16331 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16332 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16333 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16334 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16335 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16336 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16337 | return S; |
| 16338 | case 194: |
| 16339 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16340 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16341 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16342 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16343 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16344 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16345 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16346 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16347 | return S; |
| 16348 | case 195: |
| 16349 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16350 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16351 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16352 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16353 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16354 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16355 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16356 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16357 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16358 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16359 | return S; |
| 16360 | case 196: |
| 16361 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16362 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16363 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16364 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16365 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16366 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16367 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16368 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16369 | return S; |
| 16370 | case 197: |
| 16371 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16372 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16373 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16374 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16375 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16376 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16377 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16378 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16379 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16380 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16381 | return S; |
| 16382 | case 198: |
| 16383 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16384 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16385 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16386 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16387 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16388 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16389 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16390 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16391 | return S; |
| 16392 | case 199: |
| 16393 | tmp = fieldFromInstruction(insn, 0, 7); |
| 16394 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16395 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16396 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16397 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16398 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16399 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16400 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16401 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16402 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16403 | return S; |
| 16404 | case 200: |
| 16405 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16406 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16407 | return S; |
| 16408 | case 201: |
| 16409 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16410 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16411 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16412 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16413 | return S; |
| 16414 | case 202: |
| 16415 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16416 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16417 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16418 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16419 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16420 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16421 | return S; |
| 16422 | case 203: |
| 16423 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16424 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16425 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16426 | if (!Check(S, DecodeCCOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16427 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16428 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16429 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16430 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16431 | return S; |
| 16432 | case 204: |
| 16433 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16434 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16435 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16436 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16437 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16438 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16439 | return S; |
| 16440 | case 205: |
| 16441 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16442 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16443 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16444 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16445 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16446 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16447 | return S; |
| 16448 | case 206: |
| 16449 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16450 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16451 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16452 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16453 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16454 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16455 | return S; |
| 16456 | case 207: |
| 16457 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16458 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16459 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16460 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16461 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16462 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16463 | return S; |
| 16464 | case 208: |
| 16465 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16466 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16467 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16468 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16469 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16470 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16471 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16472 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16473 | return S; |
| 16474 | case 209: |
| 16475 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16476 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16477 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16478 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16479 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16480 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16481 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16482 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16483 | return S; |
| 16484 | case 210: |
| 16485 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16486 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16487 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16488 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16489 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16490 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16491 | return S; |
| 16492 | case 211: |
| 16493 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16494 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16495 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16496 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16497 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16498 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16499 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16500 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16501 | return S; |
| 16502 | case 212: |
| 16503 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16504 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16505 | return S; |
| 16506 | case 213: |
| 16507 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16508 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16509 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16510 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16511 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16512 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16513 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16514 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16515 | return S; |
| 16516 | case 214: |
| 16517 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16518 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16519 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16520 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16521 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16522 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16523 | return S; |
| 16524 | case 215: |
| 16525 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16526 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16527 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16528 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16529 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16530 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16531 | return S; |
| 16532 | case 216: |
| 16533 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16534 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16535 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16536 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16537 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16538 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16539 | return S; |
| 16540 | case 217: |
| 16541 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16542 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16543 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16544 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16545 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16546 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16547 | return S; |
| 16548 | case 218: |
| 16549 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16550 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16551 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16552 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16553 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16554 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16555 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16556 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16557 | return S; |
| 16558 | case 219: |
| 16559 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16560 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16561 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16562 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16563 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16564 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16565 | return S; |
| 16566 | case 220: |
| 16567 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16568 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16569 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16570 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16571 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16572 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16573 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16574 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16575 | return S; |
| 16576 | case 221: |
| 16577 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16578 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16579 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16580 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16581 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16582 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16583 | return S; |
| 16584 | case 222: |
| 16585 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16586 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16587 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16588 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16589 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16590 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16591 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16592 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16593 | return S; |
| 16594 | case 223: |
| 16595 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16596 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16597 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16598 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16599 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16600 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16601 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16602 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16603 | return S; |
| 16604 | case 224: |
| 16605 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16606 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16607 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16608 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16609 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16610 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16611 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16612 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16613 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16614 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16615 | return S; |
| 16616 | case 225: |
| 16617 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16618 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16619 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16620 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16621 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16622 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16623 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16624 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16625 | return S; |
| 16626 | case 226: |
| 16627 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16628 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16629 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16630 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16631 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16632 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16633 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16634 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16635 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16636 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16637 | return S; |
| 16638 | case 227: |
| 16639 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16640 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16641 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16642 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16643 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16644 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16645 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16646 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16647 | return S; |
| 16648 | case 228: |
| 16649 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16650 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16651 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16652 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16653 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16654 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16655 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16656 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16657 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16658 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16659 | return S; |
| 16660 | case 229: |
| 16661 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16662 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16663 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16664 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16665 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16666 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16667 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16668 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16669 | return S; |
| 16670 | case 230: |
| 16671 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16672 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16673 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16674 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16675 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16676 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16677 | tmp = fieldFromInstruction(insn, 32, 7); |
| 16678 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16679 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16680 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16681 | return S; |
| 16682 | case 231: |
| 16683 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16684 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16685 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16686 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16687 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16688 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16689 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16690 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16691 | return S; |
| 16692 | case 232: |
| 16693 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16694 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16695 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16696 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16697 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16698 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16699 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16700 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16701 | return S; |
| 16702 | case 233: |
| 16703 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16704 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16705 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16706 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16707 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16708 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16709 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16710 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16711 | return S; |
| 16712 | case 234: |
| 16713 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16714 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16715 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16716 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16717 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16718 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16719 | return S; |
| 16720 | case 235: |
| 16721 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16722 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16723 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16724 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16725 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16726 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16727 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16728 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16729 | return S; |
| 16730 | case 236: |
| 16731 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16732 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16733 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16734 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16735 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16736 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16737 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16738 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16739 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16740 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16741 | return S; |
| 16742 | case 237: |
| 16743 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16744 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16745 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16746 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16747 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16748 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16749 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16750 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16751 | return S; |
| 16752 | case 238: |
| 16753 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16754 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16755 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16756 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16757 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16758 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16759 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16760 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16761 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16762 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16763 | return S; |
| 16764 | case 239: |
| 16765 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16766 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16767 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16768 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16769 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16770 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16771 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16772 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16773 | return S; |
| 16774 | case 240: |
| 16775 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16776 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16777 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16778 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16779 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16780 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16781 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16782 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16783 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16784 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16785 | return S; |
| 16786 | case 241: |
| 16787 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16788 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16789 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16790 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16791 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16792 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16793 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16794 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16795 | return S; |
| 16796 | case 242: |
| 16797 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16798 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16799 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16800 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16801 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16802 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16803 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16804 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16805 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16806 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16807 | return S; |
| 16808 | case 243: |
| 16809 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16810 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16811 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16812 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16813 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16814 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16815 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16816 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16817 | return S; |
| 16818 | case 244: |
| 16819 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16820 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16821 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16822 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16823 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16824 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16825 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16826 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16827 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16828 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16829 | return S; |
| 16830 | case 245: |
| 16831 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16832 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16833 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16834 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16835 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16836 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16837 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16838 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16839 | return S; |
| 16840 | case 246: |
| 16841 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16842 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16843 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16844 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16845 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16846 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16847 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16848 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16849 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16850 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16851 | return S; |
| 16852 | case 247: |
| 16853 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16854 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16855 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16856 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16857 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16858 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16859 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16860 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16861 | return S; |
| 16862 | case 248: |
| 16863 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16864 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16865 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16866 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16867 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16868 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16869 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16870 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16871 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16872 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16873 | return S; |
| 16874 | case 249: |
| 16875 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16876 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16877 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16878 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16879 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16880 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16881 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16882 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16883 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16884 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16885 | return S; |
| 16886 | case 250: |
| 16887 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16888 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16889 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16890 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16891 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16892 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16893 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16894 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16895 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16896 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16897 | return S; |
| 16898 | case 251: |
| 16899 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16900 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16901 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16902 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16903 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16904 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16905 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16906 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16907 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16908 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16909 | return S; |
| 16910 | case 252: |
| 16911 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16912 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16913 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16914 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16915 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16916 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16917 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16918 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16919 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16920 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16921 | return S; |
| 16922 | case 253: |
| 16923 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16924 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16925 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16926 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16927 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16928 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16929 | tmp = fieldFromInstruction(insn, 0, 8); |
| 16930 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16931 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16932 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16933 | return S; |
| 16934 | case 254: |
| 16935 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16936 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16937 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16938 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16939 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16940 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16941 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16942 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 16943 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16944 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16945 | return S; |
| 16946 | case 255: |
| 16947 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16948 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16949 | tmp = fieldFromInstruction(insn, 16, 8); |
| 16950 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16951 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16952 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16953 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16954 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16955 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16956 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16957 | return S; |
| 16958 | case 256: |
| 16959 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16960 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16961 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16962 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16963 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16964 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16965 | return S; |
| 16966 | case 257: |
| 16967 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16968 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16969 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16970 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16971 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16972 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16973 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16974 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16975 | return S; |
| 16976 | case 258: |
| 16977 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16978 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16979 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16980 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16981 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16982 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16983 | return S; |
| 16984 | case 259: |
| 16985 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16986 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16987 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16988 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16989 | tmp = fieldFromInstruction(insn, 40, 7); |
| 16990 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16991 | tmp = fieldFromInstruction(insn, 48, 4); |
| 16992 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16993 | return S; |
| 16994 | case 260: |
| 16995 | tmp = fieldFromInstruction(insn, 24, 8); |
| 16996 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16997 | tmp = fieldFromInstruction(insn, 8, 8); |
| 16998 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16999 | tmp = fieldFromInstruction(insn, 16, 8); |
| 17000 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17001 | tmp = fieldFromInstruction(insn, 48, 4); |
| 17002 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17003 | return S; |
| 17004 | case 261: |
| 17005 | tmp = fieldFromInstruction(insn, 24, 8); |
| 17006 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17007 | tmp = fieldFromInstruction(insn, 8, 8); |
| 17008 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17009 | tmp = fieldFromInstruction(insn, 40, 7); |
| 17010 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 17011 | tmp = fieldFromInstruction(insn, 48, 4); |
| 17012 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17013 | return S; |
| 17014 | case 262: |
| 17015 | tmp = fieldFromInstruction(insn, 24, 8); |
| 17016 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17017 | tmp = fieldFromInstruction(insn, 8, 8); |
| 17018 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17019 | tmp = fieldFromInstruction(insn, 40, 7); |
| 17020 | if (!Check(S, DecodeI64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17021 | tmp = fieldFromInstruction(insn, 48, 4); |
| 17022 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17023 | return S; |
| 17024 | case 263: |
| 17025 | tmp = fieldFromInstruction(insn, 24, 8); |
| 17026 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17027 | tmp = fieldFromInstruction(insn, 8, 8); |
| 17028 | if (!Check(S, DecodeRDOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17029 | tmp = fieldFromInstruction(insn, 16, 8); |
| 17030 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17031 | tmp = fieldFromInstruction(insn, 48, 4); |
| 17032 | if (!Check(S, DecodeVM512RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17033 | return S; |
| 17034 | case 264: |
| 17035 | tmp = fieldFromInstruction(insn, 24, 8); |
| 17036 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17037 | tmp = fieldFromInstruction(insn, 16, 8); |
| 17038 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17039 | tmp = fieldFromInstruction(insn, 40, 7); |
| 17040 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17041 | return S; |
| 17042 | case 265: |
| 17043 | tmp = fieldFromInstruction(insn, 24, 8); |
| 17044 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17045 | tmp = fieldFromInstruction(insn, 16, 8); |
| 17046 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17047 | tmp = fieldFromInstruction(insn, 40, 7); |
| 17048 | if (!Check(S, DecodeI32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17049 | tmp = fieldFromInstruction(insn, 48, 4); |
| 17050 | if (!Check(S, DecodeVMRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17051 | return S; |
| 17052 | case 266: |
| 17053 | tmp = fieldFromInstruction(insn, 24, 8); |
| 17054 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17055 | tmp = fieldFromInstruction(insn, 16, 8); |
| 17056 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17057 | tmp = fieldFromInstruction(insn, 8, 8); |
| 17058 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17059 | tmp = fieldFromInstruction(insn, 40, 7); |
| 17060 | if (!Check(S, DecodeSIMM7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17061 | return S; |
| 17062 | case 267: |
| 17063 | tmp = fieldFromInstruction(insn, 24, 8); |
| 17064 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17065 | tmp = fieldFromInstruction(insn, 16, 8); |
| 17066 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17067 | tmp = fieldFromInstruction(insn, 8, 8); |
| 17068 | if (!Check(S, DecodeV64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17069 | tmp = fieldFromInstruction(insn, 40, 7); |
| 17070 | if (!Check(S, DecodeF32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17071 | return S; |
| 17072 | } |
| 17073 | } |
| 17074 | |
| 17075 | template <typename InsnType> |
| 17076 | static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, |
| 17077 | InsnType insn, uint64_t Address, |
| 17078 | const MCDisassembler *DisAsm, |
| 17079 | const MCSubtargetInfo &STI) { |
| 17080 | const uint8_t *Ptr = DecodeTable; |
| 17081 | |
| 17082 | SmallVector<const uint8_t *, 8> ScopeStack; |
| 17083 | DecodeStatus S = MCDisassembler::Success; |
| 17084 | while (true) { |
| 17085 | ptrdiff_t Loc = Ptr - DecodeTable; |
| 17086 | const uint8_t DecoderOp = *Ptr++; |
| 17087 | switch (DecoderOp) { |
| 17088 | default: |
| 17089 | errs() << Loc << ": Unexpected decode table opcode: " |
| 17090 | << (int)DecoderOp << '\n'; |
| 17091 | return MCDisassembler::Fail; |
| 17092 | case OPC_Scope: { |
| 17093 | unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17094 | const uint8_t *SkipTo = Ptr + NumToSkip; |
| 17095 | ScopeStack.push_back(Elt: SkipTo); |
| 17096 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope("<< SkipTo - DecodeTable |
| 17097 | << ")\n"); |
| 17098 | continue; |
| 17099 | } |
| 17100 | case OPC_SwitchField: { |
| 17101 | // Decode the start value. |
| 17102 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17103 | unsigned Len = *Ptr++; |
| 17104 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 17105 | uint64_t CaseValue; |
| 17106 | unsigned CaseSize; |
| 17107 | while (true) { |
| 17108 | CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17109 | CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17110 | if (FieldValue == CaseValue || !CaseSize) |
| 17111 | break; |
| 17112 | Ptr += CaseSize; |
| 17113 | } |
| 17114 | if (FieldValue == CaseValue) { |
| 17115 | LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField("<< Start << ", "<< Len |
| 17116 | << "): "<< FieldValue << '\n'); |
| 17117 | continue; |
| 17118 | } |
| 17119 | break; |
| 17120 | } |
| 17121 | case OPC_CheckField: { |
| 17122 | // Decode the start value. |
| 17123 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17124 | unsigned Len = *Ptr; |
| 17125 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 17126 | // Decode the field value. |
| 17127 | unsigned PtrLen = 0; |
| 17128 | uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen); |
| 17129 | Ptr += PtrLen; |
| 17130 | bool Failed = ExpectedValue != FieldValue; |
| 17131 | |
| 17132 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField("<< Start << ", "<< Len |
| 17133 | << ", "<< ExpectedValue << "): FieldValue = " |
| 17134 | << FieldValue << ", ExpectedValue = "<< ExpectedValue |
| 17135 | << ": "<< (Failed ? "FAIL, ": "PASS\n");); |
| 17136 | if (!Failed) |
| 17137 | continue; |
| 17138 | break; |
| 17139 | } |
| 17140 | case OPC_Decode: { |
| 17141 | // Decode the Opcode value. |
| 17142 | unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17143 | unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17144 | |
| 17145 | MI.clear(); |
| 17146 | MI.setOpcode(Opc); |
| 17147 | bool DecodeComplete; |
| 17148 | S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm, |
| 17149 | DecodeComplete); |
| 17150 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode "<< Opc |
| 17151 | << ", using decoder "<< DecodeIdx << ": " |
| 17152 | << (S ? "PASS, ": "FAIL, ")); |
| 17153 | |
| 17154 | if (DecodeComplete) { |
| 17155 | LLVM_DEBUG(dbgs() << "decoding complete\n"); |
| 17156 | return S; |
| 17157 | } |
| 17158 | assert(S == MCDisassembler::Fail); |
| 17159 | // Reset decode status. This also drops a SoftFail status that could be |
| 17160 | // set before the decode attempt. |
| 17161 | S = MCDisassembler::Success; |
| 17162 | break; |
| 17163 | } |
| 17164 | } |
| 17165 | if (ScopeStack.empty()) { |
| 17166 | LLVM_DEBUG(dbgs() << "returning Fail\n"); |
| 17167 | return MCDisassembler::Fail; |
| 17168 | } |
| 17169 | Ptr = ScopeStack.pop_back_val(); |
| 17170 | LLVM_DEBUG(dbgs() << "continuing at "<< Ptr - DecodeTable << '\n'); |
| 17171 | } |
| 17172 | llvm_unreachable("bogosity detected in disassembler state machine!"); |
| 17173 | } |
| 17174 | |
| 17175 | |
| 17176 | } // namespace |
| 17177 |
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