1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass VEMCRegisterClasses[];
13
14namespace VE {
15
16enum : unsigned {
17 NoRegister,
18 IC = 1,
19 PMMR = 2,
20 PSW = 3,
21 SAR = 4,
22 USRCC = 5,
23 VIX = 6,
24 VL = 7,
25 PMC0 = 8,
26 PMC1 = 9,
27 PMC2 = 10,
28 PMC3 = 11,
29 PMC4 = 12,
30 PMC5 = 13,
31 PMC6 = 14,
32 PMC7 = 15,
33 PMC8 = 16,
34 PMC9 = 17,
35 PMC10 = 18,
36 PMC11 = 19,
37 PMC12 = 20,
38 PMC13 = 21,
39 PMC14 = 22,
40 PMCR0 = 23,
41 PMCR1 = 24,
42 PMCR2 = 25,
43 PMCR3 = 26,
44 Q0 = 27,
45 Q1 = 28,
46 Q2 = 29,
47 Q3 = 30,
48 Q4 = 31,
49 Q5 = 32,
50 Q6 = 33,
51 Q7 = 34,
52 Q8 = 35,
53 Q9 = 36,
54 Q10 = 37,
55 Q11 = 38,
56 Q12 = 39,
57 Q13 = 40,
58 Q14 = 41,
59 Q15 = 42,
60 Q16 = 43,
61 Q17 = 44,
62 Q18 = 45,
63 Q19 = 46,
64 Q20 = 47,
65 Q21 = 48,
66 Q22 = 49,
67 Q23 = 50,
68 Q24 = 51,
69 Q25 = 52,
70 Q26 = 53,
71 Q27 = 54,
72 Q28 = 55,
73 Q29 = 56,
74 Q30 = 57,
75 Q31 = 58,
76 SF0 = 59,
77 SF1 = 60,
78 SF2 = 61,
79 SF3 = 62,
80 SF4 = 63,
81 SF5 = 64,
82 SF6 = 65,
83 SF7 = 66,
84 SF8 = 67,
85 SF9 = 68,
86 SF10 = 69,
87 SF11 = 70,
88 SF12 = 71,
89 SF13 = 72,
90 SF14 = 73,
91 SF15 = 74,
92 SF16 = 75,
93 SF17 = 76,
94 SF18 = 77,
95 SF19 = 78,
96 SF20 = 79,
97 SF21 = 80,
98 SF22 = 81,
99 SF23 = 82,
100 SF24 = 83,
101 SF25 = 84,
102 SF26 = 85,
103 SF27 = 86,
104 SF28 = 87,
105 SF29 = 88,
106 SF30 = 89,
107 SF31 = 90,
108 SF32 = 91,
109 SF33 = 92,
110 SF34 = 93,
111 SF35 = 94,
112 SF36 = 95,
113 SF37 = 96,
114 SF38 = 97,
115 SF39 = 98,
116 SF40 = 99,
117 SF41 = 100,
118 SF42 = 101,
119 SF43 = 102,
120 SF44 = 103,
121 SF45 = 104,
122 SF46 = 105,
123 SF47 = 106,
124 SF48 = 107,
125 SF49 = 108,
126 SF50 = 109,
127 SF51 = 110,
128 SF52 = 111,
129 SF53 = 112,
130 SF54 = 113,
131 SF55 = 114,
132 SF56 = 115,
133 SF57 = 116,
134 SF58 = 117,
135 SF59 = 118,
136 SF60 = 119,
137 SF61 = 120,
138 SF62 = 121,
139 SF63 = 122,
140 SW0 = 123,
141 SW1 = 124,
142 SW2 = 125,
143 SW3 = 126,
144 SW4 = 127,
145 SW5 = 128,
146 SW6 = 129,
147 SW7 = 130,
148 SW8 = 131,
149 SW9 = 132,
150 SW10 = 133,
151 SW11 = 134,
152 SW12 = 135,
153 SW13 = 136,
154 SW14 = 137,
155 SW15 = 138,
156 SW16 = 139,
157 SW17 = 140,
158 SW18 = 141,
159 SW19 = 142,
160 SW20 = 143,
161 SW21 = 144,
162 SW22 = 145,
163 SW23 = 146,
164 SW24 = 147,
165 SW25 = 148,
166 SW26 = 149,
167 SW27 = 150,
168 SW28 = 151,
169 SW29 = 152,
170 SW30 = 153,
171 SW31 = 154,
172 SW32 = 155,
173 SW33 = 156,
174 SW34 = 157,
175 SW35 = 158,
176 SW36 = 159,
177 SW37 = 160,
178 SW38 = 161,
179 SW39 = 162,
180 SW40 = 163,
181 SW41 = 164,
182 SW42 = 165,
183 SW43 = 166,
184 SW44 = 167,
185 SW45 = 168,
186 SW46 = 169,
187 SW47 = 170,
188 SW48 = 171,
189 SW49 = 172,
190 SW50 = 173,
191 SW51 = 174,
192 SW52 = 175,
193 SW53 = 176,
194 SW54 = 177,
195 SW55 = 178,
196 SW56 = 179,
197 SW57 = 180,
198 SW58 = 181,
199 SW59 = 182,
200 SW60 = 183,
201 SW61 = 184,
202 SW62 = 185,
203 SW63 = 186,
204 SX0 = 187,
205 SX1 = 188,
206 SX2 = 189,
207 SX3 = 190,
208 SX4 = 191,
209 SX5 = 192,
210 SX6 = 193,
211 SX7 = 194,
212 SX8 = 195,
213 SX9 = 196,
214 SX10 = 197,
215 SX11 = 198,
216 SX12 = 199,
217 SX13 = 200,
218 SX14 = 201,
219 SX15 = 202,
220 SX16 = 203,
221 SX17 = 204,
222 SX18 = 205,
223 SX19 = 206,
224 SX20 = 207,
225 SX21 = 208,
226 SX22 = 209,
227 SX23 = 210,
228 SX24 = 211,
229 SX25 = 212,
230 SX26 = 213,
231 SX27 = 214,
232 SX28 = 215,
233 SX29 = 216,
234 SX30 = 217,
235 SX31 = 218,
236 SX32 = 219,
237 SX33 = 220,
238 SX34 = 221,
239 SX35 = 222,
240 SX36 = 223,
241 SX37 = 224,
242 SX38 = 225,
243 SX39 = 226,
244 SX40 = 227,
245 SX41 = 228,
246 SX42 = 229,
247 SX43 = 230,
248 SX44 = 231,
249 SX45 = 232,
250 SX46 = 233,
251 SX47 = 234,
252 SX48 = 235,
253 SX49 = 236,
254 SX50 = 237,
255 SX51 = 238,
256 SX52 = 239,
257 SX53 = 240,
258 SX54 = 241,
259 SX55 = 242,
260 SX56 = 243,
261 SX57 = 244,
262 SX58 = 245,
263 SX59 = 246,
264 SX60 = 247,
265 SX61 = 248,
266 SX62 = 249,
267 SX63 = 250,
268 V0 = 251,
269 V1 = 252,
270 V2 = 253,
271 V3 = 254,
272 V4 = 255,
273 V5 = 256,
274 V6 = 257,
275 V7 = 258,
276 V8 = 259,
277 V9 = 260,
278 V10 = 261,
279 V11 = 262,
280 V12 = 263,
281 V13 = 264,
282 V14 = 265,
283 V15 = 266,
284 V16 = 267,
285 V17 = 268,
286 V18 = 269,
287 V19 = 270,
288 V20 = 271,
289 V21 = 272,
290 V22 = 273,
291 V23 = 274,
292 V24 = 275,
293 V25 = 276,
294 V26 = 277,
295 V27 = 278,
296 V28 = 279,
297 V29 = 280,
298 V30 = 281,
299 V31 = 282,
300 V32 = 283,
301 V33 = 284,
302 V34 = 285,
303 V35 = 286,
304 V36 = 287,
305 V37 = 288,
306 V38 = 289,
307 V39 = 290,
308 V40 = 291,
309 V41 = 292,
310 V42 = 293,
311 V43 = 294,
312 V44 = 295,
313 V45 = 296,
314 V46 = 297,
315 V47 = 298,
316 V48 = 299,
317 V49 = 300,
318 V50 = 301,
319 V51 = 302,
320 V52 = 303,
321 V53 = 304,
322 V54 = 305,
323 V55 = 306,
324 V56 = 307,
325 V57 = 308,
326 V58 = 309,
327 V59 = 310,
328 V60 = 311,
329 V61 = 312,
330 V62 = 313,
331 V63 = 314,
332 VM0 = 315,
333 VM1 = 316,
334 VM2 = 317,
335 VM3 = 318,
336 VM4 = 319,
337 VM5 = 320,
338 VM6 = 321,
339 VM7 = 322,
340 VM8 = 323,
341 VM9 = 324,
342 VM10 = 325,
343 VM11 = 326,
344 VM12 = 327,
345 VM13 = 328,
346 VM14 = 329,
347 VM15 = 330,
348 VMP0 = 331,
349 VMP1 = 332,
350 VMP2 = 333,
351 VMP3 = 334,
352 VMP4 = 335,
353 VMP5 = 336,
354 VMP6 = 337,
355 VMP7 = 338,
356 NUM_TARGET_REGS // 339
357};
358
359} // namespace VE
360
361// Register classes
362
363namespace VE {
364
365enum {
366 F32RegClassID = 0,
367 I32RegClassID = 1,
368 VLSRegClassID = 2,
369 I64RegClassID = 3,
370 MISCRegClassID = 4,
371 F128RegClassID = 5,
372 VMRegClassID = 6,
373 VM512RegClassID = 7,
374 VM512_with_sub_vm_evenRegClassID = 8,
375 V64RegClassID = 9,
376
377};
378
379} // namespace VE
380
381// Register alternate name indices
382
383namespace VE {
384
385enum {
386 AsmName, // 0
387 NoRegAltName, // 1
388 NUM_TARGET_REG_ALT_NAMES = 2
389};
390
391} // namespace VE
392
393// Subregister indices
394
395namespace VE {
396
397enum : uint16_t {
398 NoSubRegister,
399 sub_even, // 1
400 sub_f32, // 2
401 sub_i32, // 3
402 sub_odd, // 4
403 sub_vm_even, // 5
404 sub_vm_odd, // 6
405 sub_odd_then_sub_f32, // 7
406 sub_odd_then_sub_i32, // 8
407 NUM_TARGET_SUBREGS
408};
409
410} // namespace VE
411// Register pressure sets enum.
412namespace VE {
413
414enum RegisterPressureSets {
415 VLS = 0,
416 VM512 = 1,
417 VM = 2,
418 VM_with_VM512 = 3,
419 MISC = 4,
420 V64 = 5,
421 F32 = 6,
422 I32 = 7,
423 I64 = 8,
424};
425
426} // namespace VE
427
428} // namespace llvm
429