1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass VEMCRegisterClasses[];
13
14namespace VE {
15enum : unsigned {
16 NoRegister,
17 IC = 1,
18 PMMR = 2,
19 PSW = 3,
20 SAR = 4,
21 USRCC = 5,
22 VIX = 6,
23 VL = 7,
24 PMC0 = 8,
25 PMC1 = 9,
26 PMC2 = 10,
27 PMC3 = 11,
28 PMC4 = 12,
29 PMC5 = 13,
30 PMC6 = 14,
31 PMC7 = 15,
32 PMC8 = 16,
33 PMC9 = 17,
34 PMC10 = 18,
35 PMC11 = 19,
36 PMC12 = 20,
37 PMC13 = 21,
38 PMC14 = 22,
39 PMCR0 = 23,
40 PMCR1 = 24,
41 PMCR2 = 25,
42 PMCR3 = 26,
43 Q0 = 27,
44 Q1 = 28,
45 Q2 = 29,
46 Q3 = 30,
47 Q4 = 31,
48 Q5 = 32,
49 Q6 = 33,
50 Q7 = 34,
51 Q8 = 35,
52 Q9 = 36,
53 Q10 = 37,
54 Q11 = 38,
55 Q12 = 39,
56 Q13 = 40,
57 Q14 = 41,
58 Q15 = 42,
59 Q16 = 43,
60 Q17 = 44,
61 Q18 = 45,
62 Q19 = 46,
63 Q20 = 47,
64 Q21 = 48,
65 Q22 = 49,
66 Q23 = 50,
67 Q24 = 51,
68 Q25 = 52,
69 Q26 = 53,
70 Q27 = 54,
71 Q28 = 55,
72 Q29 = 56,
73 Q30 = 57,
74 Q31 = 58,
75 SF0 = 59,
76 SF1 = 60,
77 SF2 = 61,
78 SF3 = 62,
79 SF4 = 63,
80 SF5 = 64,
81 SF6 = 65,
82 SF7 = 66,
83 SF8 = 67,
84 SF9 = 68,
85 SF10 = 69,
86 SF11 = 70,
87 SF12 = 71,
88 SF13 = 72,
89 SF14 = 73,
90 SF15 = 74,
91 SF16 = 75,
92 SF17 = 76,
93 SF18 = 77,
94 SF19 = 78,
95 SF20 = 79,
96 SF21 = 80,
97 SF22 = 81,
98 SF23 = 82,
99 SF24 = 83,
100 SF25 = 84,
101 SF26 = 85,
102 SF27 = 86,
103 SF28 = 87,
104 SF29 = 88,
105 SF30 = 89,
106 SF31 = 90,
107 SF32 = 91,
108 SF33 = 92,
109 SF34 = 93,
110 SF35 = 94,
111 SF36 = 95,
112 SF37 = 96,
113 SF38 = 97,
114 SF39 = 98,
115 SF40 = 99,
116 SF41 = 100,
117 SF42 = 101,
118 SF43 = 102,
119 SF44 = 103,
120 SF45 = 104,
121 SF46 = 105,
122 SF47 = 106,
123 SF48 = 107,
124 SF49 = 108,
125 SF50 = 109,
126 SF51 = 110,
127 SF52 = 111,
128 SF53 = 112,
129 SF54 = 113,
130 SF55 = 114,
131 SF56 = 115,
132 SF57 = 116,
133 SF58 = 117,
134 SF59 = 118,
135 SF60 = 119,
136 SF61 = 120,
137 SF62 = 121,
138 SF63 = 122,
139 SW0 = 123,
140 SW1 = 124,
141 SW2 = 125,
142 SW3 = 126,
143 SW4 = 127,
144 SW5 = 128,
145 SW6 = 129,
146 SW7 = 130,
147 SW8 = 131,
148 SW9 = 132,
149 SW10 = 133,
150 SW11 = 134,
151 SW12 = 135,
152 SW13 = 136,
153 SW14 = 137,
154 SW15 = 138,
155 SW16 = 139,
156 SW17 = 140,
157 SW18 = 141,
158 SW19 = 142,
159 SW20 = 143,
160 SW21 = 144,
161 SW22 = 145,
162 SW23 = 146,
163 SW24 = 147,
164 SW25 = 148,
165 SW26 = 149,
166 SW27 = 150,
167 SW28 = 151,
168 SW29 = 152,
169 SW30 = 153,
170 SW31 = 154,
171 SW32 = 155,
172 SW33 = 156,
173 SW34 = 157,
174 SW35 = 158,
175 SW36 = 159,
176 SW37 = 160,
177 SW38 = 161,
178 SW39 = 162,
179 SW40 = 163,
180 SW41 = 164,
181 SW42 = 165,
182 SW43 = 166,
183 SW44 = 167,
184 SW45 = 168,
185 SW46 = 169,
186 SW47 = 170,
187 SW48 = 171,
188 SW49 = 172,
189 SW50 = 173,
190 SW51 = 174,
191 SW52 = 175,
192 SW53 = 176,
193 SW54 = 177,
194 SW55 = 178,
195 SW56 = 179,
196 SW57 = 180,
197 SW58 = 181,
198 SW59 = 182,
199 SW60 = 183,
200 SW61 = 184,
201 SW62 = 185,
202 SW63 = 186,
203 SX0 = 187,
204 SX1 = 188,
205 SX2 = 189,
206 SX3 = 190,
207 SX4 = 191,
208 SX5 = 192,
209 SX6 = 193,
210 SX7 = 194,
211 SX8 = 195,
212 SX9 = 196,
213 SX10 = 197,
214 SX11 = 198,
215 SX12 = 199,
216 SX13 = 200,
217 SX14 = 201,
218 SX15 = 202,
219 SX16 = 203,
220 SX17 = 204,
221 SX18 = 205,
222 SX19 = 206,
223 SX20 = 207,
224 SX21 = 208,
225 SX22 = 209,
226 SX23 = 210,
227 SX24 = 211,
228 SX25 = 212,
229 SX26 = 213,
230 SX27 = 214,
231 SX28 = 215,
232 SX29 = 216,
233 SX30 = 217,
234 SX31 = 218,
235 SX32 = 219,
236 SX33 = 220,
237 SX34 = 221,
238 SX35 = 222,
239 SX36 = 223,
240 SX37 = 224,
241 SX38 = 225,
242 SX39 = 226,
243 SX40 = 227,
244 SX41 = 228,
245 SX42 = 229,
246 SX43 = 230,
247 SX44 = 231,
248 SX45 = 232,
249 SX46 = 233,
250 SX47 = 234,
251 SX48 = 235,
252 SX49 = 236,
253 SX50 = 237,
254 SX51 = 238,
255 SX52 = 239,
256 SX53 = 240,
257 SX54 = 241,
258 SX55 = 242,
259 SX56 = 243,
260 SX57 = 244,
261 SX58 = 245,
262 SX59 = 246,
263 SX60 = 247,
264 SX61 = 248,
265 SX62 = 249,
266 SX63 = 250,
267 V0 = 251,
268 V1 = 252,
269 V2 = 253,
270 V3 = 254,
271 V4 = 255,
272 V5 = 256,
273 V6 = 257,
274 V7 = 258,
275 V8 = 259,
276 V9 = 260,
277 V10 = 261,
278 V11 = 262,
279 V12 = 263,
280 V13 = 264,
281 V14 = 265,
282 V15 = 266,
283 V16 = 267,
284 V17 = 268,
285 V18 = 269,
286 V19 = 270,
287 V20 = 271,
288 V21 = 272,
289 V22 = 273,
290 V23 = 274,
291 V24 = 275,
292 V25 = 276,
293 V26 = 277,
294 V27 = 278,
295 V28 = 279,
296 V29 = 280,
297 V30 = 281,
298 V31 = 282,
299 V32 = 283,
300 V33 = 284,
301 V34 = 285,
302 V35 = 286,
303 V36 = 287,
304 V37 = 288,
305 V38 = 289,
306 V39 = 290,
307 V40 = 291,
308 V41 = 292,
309 V42 = 293,
310 V43 = 294,
311 V44 = 295,
312 V45 = 296,
313 V46 = 297,
314 V47 = 298,
315 V48 = 299,
316 V49 = 300,
317 V50 = 301,
318 V51 = 302,
319 V52 = 303,
320 V53 = 304,
321 V54 = 305,
322 V55 = 306,
323 V56 = 307,
324 V57 = 308,
325 V58 = 309,
326 V59 = 310,
327 V60 = 311,
328 V61 = 312,
329 V62 = 313,
330 V63 = 314,
331 VM0 = 315,
332 VM1 = 316,
333 VM2 = 317,
334 VM3 = 318,
335 VM4 = 319,
336 VM5 = 320,
337 VM6 = 321,
338 VM7 = 322,
339 VM8 = 323,
340 VM9 = 324,
341 VM10 = 325,
342 VM11 = 326,
343 VM12 = 327,
344 VM13 = 328,
345 VM14 = 329,
346 VM15 = 330,
347 VMP0 = 331,
348 VMP1 = 332,
349 VMP2 = 333,
350 VMP3 = 334,
351 VMP4 = 335,
352 VMP5 = 336,
353 VMP6 = 337,
354 VMP7 = 338,
355 NUM_TARGET_REGS // 339
356};
357} // end namespace VE
358
359// Register classes
360
361namespace VE {
362enum {
363 F32RegClassID = 0,
364 I32RegClassID = 1,
365 VLSRegClassID = 2,
366 I64RegClassID = 3,
367 MISCRegClassID = 4,
368 F128RegClassID = 5,
369 VMRegClassID = 6,
370 VM512RegClassID = 7,
371 VM512_with_sub_vm_evenRegClassID = 8,
372 V64RegClassID = 9,
373
374};
375} // end namespace VE
376
377
378// Register alternate name indices
379
380namespace VE {
381enum {
382 AsmName, // 0
383 NoRegAltName, // 1
384 NUM_TARGET_REG_ALT_NAMES = 2
385};
386} // end namespace VE
387
388
389// Subregister indices
390
391namespace VE {
392enum : uint16_t {
393 NoSubRegister,
394 sub_even, // 1
395 sub_f32, // 2
396 sub_i32, // 3
397 sub_odd, // 4
398 sub_vm_even, // 5
399 sub_vm_odd, // 6
400 sub_odd_then_sub_f32, // 7
401 sub_odd_then_sub_i32, // 8
402 NUM_TARGET_SUBREGS
403};
404} // end namespace VE
405
406// Register pressure sets enum.
407namespace VE {
408enum RegisterPressureSets {
409 VLS = 0,
410 VM512 = 1,
411 VM = 2,
412 VM_with_VM512 = 3,
413 MISC = 4,
414 V64 = 5,
415 F32 = 6,
416 I32 = 7,
417 I64 = 8,
418};
419} // end namespace VE
420
421} // end namespace llvm
422
423