1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace VE {
15
16enum {
17 FeatureEnableVPU = 0,
18 NumSubtargetFeatures = 1
19};
20
21} // namespace VE
22
23} // namespace llvm
24
25#endif // GET_SUBTARGETINFO_ENUM
26
27#ifdef GET_SUBTARGETINFO_MACRO
28
29GET_SUBTARGETINFO_MACRO(EnableVPU, false, enableVPU)
30
31#undef GET_SUBTARGETINFO_MACRO
32#endif // GET_SUBTARGETINFO_MACRO
33
34#ifdef GET_SUBTARGETINFO_MC_DESC
35#undef GET_SUBTARGETINFO_MC_DESC
36
37namespace llvm {
38
39// Sorted (by key) array of values for CPU features.
40extern const llvm::SubtargetFeatureKV VEFeatureKV[] = {
41 { "vpu", "Enable the VPU", VE::FeatureEnableVPU, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
42};
43
44#ifdef DBGFIELD
45#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
46#endif
47#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
48#define DBGFIELD(x) x,
49#define DBGVAL_OR_NULLPTR(x) x
50#else
51#define DBGFIELD(x)
52#define DBGVAL_OR_NULLPTR(x) nullptr
53#endif
54
55// ===============================================================
56// Data tables for the new per-operand machine model.
57
58// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
59extern const llvm::MCWriteProcResEntry VEWriteProcResTable[] = {
60 { 0, 0, 0 }, // Invalid
61}; // VEWriteProcResTable
62
63// {Cycles, WriteResourceID}
64extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[] = {
65 { 0, 0}, // Invalid
66}; // VEWriteLatencyTable
67
68// {UseIdx, WriteResourceID, Cycles}
69extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[] = {
70 {0, 0, 0}, // Invalid
71}; // VEReadAdvanceTable
72
73#ifdef __GNUC__
74#pragma GCC diagnostic push
75#pragma GCC diagnostic ignored "-Woverlength-strings"
76#endif
77static constexpr char VESchedClassNamesStorage[] =
78 "\0"
79 "InvalidSchedClass\0"
80 ;
81#ifdef __GNUC__
82#pragma GCC diagnostic pop
83#endif
84
85static constexpr llvm::StringTable
86VESchedClassNames = VESchedClassNamesStorage;
87
88static const llvm::MCSchedModel NoSchedModel = {
89 MCSchedModel::DefaultIssueWidth,
90 MCSchedModel::DefaultMicroOpBufferSize,
91 MCSchedModel::DefaultLoopMicroOpBufferSize,
92 MCSchedModel::DefaultLoadLatency,
93 MCSchedModel::DefaultHighLatency,
94 MCSchedModel::DefaultMispredictPenalty,
95 false, // PostRAScheduler
96 false, // CompleteModel
97 false, // EnableIntervals
98 0, // Processor ID
99 nullptr, nullptr, 0, 0, // No instruction-level machine model.
100 DBGVAL_OR_NULLPTR(&VESchedClassNames), // SchedClassNames
101 nullptr, // No Itinerary
102 nullptr // No extra processor descriptor
103};
104
105#undef DBGFIELD
106
107#undef DBGVAL_OR_NULLPTR
108
109// Sorted (by key) array of values for CPU subtype.
110extern const llvm::SubtargetSubTypeKV VESubTypeKV[] = {
111 { "generic", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
112};
113
114// Sorted array of names of CPU subtypes, including aliases.
115extern const llvm::StringRef VENames[] = {
116"generic"};
117
118namespace VE_MC {
119
120unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
121 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
122 // Don't know how to resolve this scheduling class.
123 return 0;
124}
125
126} // namespace VE_MC
127struct VEGenMCSubtargetInfo : public MCSubtargetInfo {
128 VEGenMCSubtargetInfo(const Triple &TT,
129 StringRef CPU, StringRef TuneCPU, StringRef FS,
130 ArrayRef<StringRef> PN,
131 ArrayRef<SubtargetFeatureKV> PF,
132 ArrayRef<SubtargetSubTypeKV> PD,
133 const MCWriteProcResEntry *WPR,
134 const MCWriteLatencyEntry *WL,
135 const MCReadAdvanceEntry *RA, const InstrStage *IS,
136 const unsigned *OC, const unsigned *FP) :
137 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
138 WPR, WL, RA, IS, OC, FP) { }
139
140 unsigned resolveVariantSchedClass(unsigned SchedClass,
141 const MCInst *MI, const MCInstrInfo *MCII,
142 unsigned CPUID) const final {
143 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
144 }
145};
146
147static inline MCSubtargetInfo *createVEMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
148 return new VEGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, VENames, VEFeatureKV, VESubTypeKV,
149 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
150 nullptr, nullptr, nullptr);
151}
152
153
154} // namespace llvm
155
156#endif // GET_SUBTARGETINFO_MC_DESC
157
158#ifdef GET_SUBTARGETINFO_TARGET_DESC
159#undef GET_SUBTARGETINFO_TARGET_DESC
160
161#include "llvm/ADT/BitmaskEnum.h"
162#include "llvm/Support/Debug.h"
163#include "llvm/Support/raw_ostream.h"
164
165// ParseSubtargetFeatures - Parses features string setting specified
166// subtarget options.
167void llvm::VESubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
168 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
169 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
170 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
171 InitMCProcessorInfo(CPU, TuneCPU, FS);
172 const FeatureBitset &Bits = getFeatureBits();
173 if (Bits[VE::FeatureEnableVPU]) EnableVPU = true;
174}
175
176#endif // GET_SUBTARGETINFO_TARGET_DESC
177
178#ifdef GET_SUBTARGETINFO_HEADER
179#undef GET_SUBTARGETINFO_HEADER
180
181namespace llvm {
182
183class DFAPacketizer;
184namespace VE_MC {
185
186unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
187
188} // namespace VE_MC
189struct VEGenSubtargetInfo : public TargetSubtargetInfo {
190 explicit VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
191public:
192 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
193 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
194 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
195};
196
197} // namespace llvm
198
199#endif // GET_SUBTARGETINFO_HEADER
200
201#ifdef GET_SUBTARGETINFO_CTOR
202#undef GET_SUBTARGETINFO_CTOR
203
204#include "llvm/CodeGen/TargetSchedule.h"
205
206namespace llvm {
207
208extern const llvm::StringRef VENames[];
209extern const llvm::SubtargetFeatureKV VEFeatureKV[];
210extern const llvm::SubtargetSubTypeKV VESubTypeKV[];
211extern const llvm::MCWriteProcResEntry VEWriteProcResTable[];
212extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[];
213extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[];
214VEGenSubtargetInfo::VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
215 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(VENames, 1), ArrayRef(VEFeatureKV, 1), ArrayRef(VESubTypeKV, 1),
216 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
217 nullptr, nullptr, nullptr) {}
218
219unsigned VEGenSubtargetInfo
220::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
221 report_fatal_error("Expected a variant SchedClass");
222} // VEGenSubtargetInfo::resolveSchedClass
223
224unsigned VEGenSubtargetInfo
225::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
226 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
227} // VEGenSubtargetInfo::resolveVariantSchedClass
228
229
230} // namespace llvm
231
232#endif // GET_SUBTARGETINFO_CTOR
233
234#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
235#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
236
237
238#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
239
240#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
241#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
242
243
244#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
245
246