1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace VE {
15
16enum {
17 FeatureEnableVPU = 0,
18 NumSubtargetFeatures = 1
19};
20
21} // namespace VE
22
23} // namespace llvm
24
25#endif // GET_SUBTARGETINFO_ENUM
26
27#ifdef GET_SUBTARGETINFO_MACRO
28
29GET_SUBTARGETINFO_MACRO(EnableVPU, false, enableVPU)
30
31#undef GET_SUBTARGETINFO_MACRO
32#endif // GET_SUBTARGETINFO_MACRO
33
34#ifdef GET_SUBTARGETINFO_MC_DESC
35#undef GET_SUBTARGETINFO_MC_DESC
36
37namespace llvm {
38
39// Sorted (by key) array of values for CPU features.
40extern const llvm::SubtargetFeatureKVStorage< 1, 21> VEFeatureKVStorage = {
41 {
42 { sizeof(SubtargetFeatureKV) * 1 + 1, sizeof(SubtargetFeatureKV) * 1 + 5, VE::FeatureEnableVPU, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
43 },
44 "\000vpu\000Enable the VPU\000"};
45
46#ifdef DBGFIELD
47#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
48#endif
49#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
50#define DBGFIELD(x) x,
51#define DBGVAL_OR_NULLPTR(x) x
52#else
53#define DBGFIELD(x)
54#define DBGVAL_OR_NULLPTR(x) nullptr
55#endif
56
57// ===============================================================
58// Data tables for the new per-operand machine model.
59
60static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
61static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
62
63// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
64extern const llvm::MCWriteProcResEntry VEWriteProcResTable[] = {
65 { 0, 0, 0 }, // Invalid
66}; // VEWriteProcResTable
67
68// {Cycles, WriteResourceID}
69extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[] = {
70 { 0, 0}, // Invalid
71}; // VEWriteLatencyTable
72
73// {UseIdx, WriteResourceID, Cycles}
74extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[] = {
75 {0, 0, 0}, // Invalid
76}; // VEReadAdvanceTable
77
78#ifdef __GNUC__
79#pragma GCC diagnostic push
80#pragma GCC diagnostic ignored "-Woverlength-strings"
81#endif
82static constexpr char VESchedClassNamesStorage[] =
83 "\0"
84 "InvalidSchedClass\0"
85 ;
86#ifdef __GNUC__
87#pragma GCC diagnostic pop
88#endif
89
90static constexpr llvm::StringTable
91VESchedClassNames = VESchedClassNamesStorage;
92
93extern const llvm::MCSchedModel VESchedModels[] = {
94{ // NoSchedModel
95 MCSchedModel::DefaultIssueWidth,
96 MCSchedModel::DefaultMicroOpBufferSize,
97 MCSchedModel::DefaultLoopMicroOpBufferSize,
98 MCSchedModel::DefaultLoadLatency,
99 MCSchedModel::DefaultHighLatency,
100 MCSchedModel::DefaultMispredictPenalty,
101 false, // PostRAScheduler
102 false, // CompleteModel
103 false, // EnableIntervals
104 0, // Processor ID
105 nullptr, nullptr, 0, 0, // No instruction-level machine model.
106 DBGVAL_OR_NULLPTR(&VESchedClassNames), // SchedClassNames
107 nullptr, // No Itinerary
108 nullptr // No extra processor descriptor
109 },
110};
111
112#undef DBGFIELD
113
114#undef DBGVAL_OR_NULLPTR
115
116// Sorted (by key) array of values for CPU subtype.
117extern const llvm::SubtargetSubTypeKVStorage< 1, 10> VESubTypeKVStorage = {
118 {
119 { sizeof(SubtargetSubTypeKV) * 1 + 1, { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
120 },
121 "\000generic\000"};
122
123namespace VE_MC {
124
125unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
126 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
127 // Don't know how to resolve this scheduling class.
128 return 0;
129}
130
131} // namespace VE_MC
132struct VEGenMCSubtargetInfo : public MCSubtargetInfo {
133 VEGenMCSubtargetInfo(const Triple &TT,
134 StringRef CPU, StringRef TuneCPU, StringRef FS,
135 StringTable PN,
136 ArrayRef<SubtargetFeatureKV> PF,
137 ArrayRef<SubtargetSubTypeKV> PD,
138 const MCSchedModel *PSM,
139 const MCWriteProcResEntry *WPR,
140 const MCWriteLatencyEntry *WL,
141 const MCReadAdvanceEntry *RA, const InstrStage *IS,
142 const unsigned *OC, const unsigned *FP) :
143 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
144 WPR, WL, RA, IS, OC, FP) { }
145
146 unsigned resolveVariantSchedClass(unsigned SchedClass,
147 const MCInst *MI, const MCInstrInfo *MCII,
148 unsigned CPUID) const final {
149 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
150 }
151};
152
153static inline MCSubtargetInfo *createVEMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
154 return new VEGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(VESubTypeKVStorage.Strings), VEFeatureKVStorage.Features, VESubTypeKVStorage.SubTypes, VESchedModels,
155 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
156 nullptr, nullptr, nullptr);
157}
158
159
160} // namespace llvm
161
162#endif // GET_SUBTARGETINFO_MC_DESC
163
164#ifdef GET_SUBTARGETINFO_TARGET_DESC
165#undef GET_SUBTARGETINFO_TARGET_DESC
166
167#include "llvm/ADT/BitmaskEnum.h"
168#include "llvm/Support/Debug.h"
169#include "llvm/Support/raw_ostream.h"
170
171// ParseSubtargetFeatures - Parses features string setting specified
172// subtarget options.
173void llvm::VESubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
174 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
175 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
176 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
177 InitMCProcessorInfo(CPU, TuneCPU, FS);
178 const FeatureBitset &Bits = getFeatureBits();
179 if (Bits[VE::FeatureEnableVPU]) EnableVPU = true;
180}
181
182#endif // GET_SUBTARGETINFO_TARGET_DESC
183
184#ifdef GET_SUBTARGETINFO_HEADER
185#undef GET_SUBTARGETINFO_HEADER
186
187namespace llvm {
188
189class DFAPacketizer;
190namespace VE_MC {
191
192unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
193
194} // namespace VE_MC
195struct VEGenSubtargetInfo : public TargetSubtargetInfo {
196 explicit VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
197public:
198 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
199 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
200 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
201 const FeatureBitset &getInlineIgnoreFeatures() const override;
202 const FeatureBitset &getInlineInverseFeatures() const override;
203 const FeatureBitset &getInlineMustMatchFeatures() const override;
204};
205
206} // namespace llvm
207
208#endif // GET_SUBTARGETINFO_HEADER
209
210#ifdef GET_SUBTARGETINFO_CTOR
211#undef GET_SUBTARGETINFO_CTOR
212
213#include "llvm/CodeGen/TargetSchedule.h"
214
215namespace llvm {
216
217extern const llvm::StringRef VENames[];
218extern const llvm::SubtargetFeatureKVStorage<1, 21> VEFeatureKVStorage;
219extern const llvm::SubtargetSubTypeKVStorage<1, 10> VESubTypeKVStorage;
220extern const llvm::MCSchedModel VESchedModels[];
221extern const llvm::MCWriteProcResEntry VEWriteProcResTable[];
222extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[];
223extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[];
224VEGenSubtargetInfo::VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
225 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(VESubTypeKVStorage.Strings), ArrayRef(VEFeatureKVStorage.Features), ArrayRef(VESubTypeKVStorage.SubTypes), VESchedModels,
226 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
227 nullptr, nullptr, nullptr) {}
228
229unsigned VEGenSubtargetInfo
230::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
231 report_fatal_error("Expected a variant SchedClass");
232} // VEGenSubtargetInfo::resolveSchedClass
233
234unsigned VEGenSubtargetInfo
235::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
236 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
237} // VEGenSubtargetInfo::resolveVariantSchedClass
238
239const FeatureBitset &VEGenSubtargetInfo::getInlineIgnoreFeatures() const {
240 static constexpr FeatureBitset Features = {
241 };
242 return Features;
243}
244
245const FeatureBitset &VEGenSubtargetInfo::getInlineInverseFeatures() const {
246 static constexpr FeatureBitset Features = {
247 };
248 return Features;
249}
250
251const FeatureBitset &VEGenSubtargetInfo::getInlineMustMatchFeatures() const {
252 static constexpr FeatureBitset Features = {
253 };
254 return Features;
255}
256
257
258} // namespace llvm
259
260#endif // GET_SUBTARGETINFO_CTOR
261
262#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
263#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
264
265
266#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
267
268#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
269#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
270
271
272#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
273
274