1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace VE {
15
16enum {
17 FeatureEnableVPU = 0,
18 NumSubtargetFeatures = 1
19};
20
21} // namespace VE
22
23} // namespace llvm
24
25#endif // GET_SUBTARGETINFO_ENUM
26
27#ifdef GET_SUBTARGETINFO_MACRO
28
29GET_SUBTARGETINFO_MACRO(EnableVPU, false, enableVPU)
30
31#undef GET_SUBTARGETINFO_MACRO
32#endif // GET_SUBTARGETINFO_MACRO
33
34#ifdef GET_SUBTARGETINFO_MC_DESC
35#undef GET_SUBTARGETINFO_MC_DESC
36
37namespace llvm {
38
39// Sorted (by key) array of values for CPU features.
40extern const llvm::SubtargetFeatureKVStorage< 1, 21> VEFeatureKVStorage = {
41 {
42 { sizeof(SubtargetFeatureKV) * 1 + 1, sizeof(SubtargetFeatureKV) * 1 + 5, VE::FeatureEnableVPU, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
43 },
44 "\000vpu\000Enable the VPU\000"};
45
46#ifdef DBGFIELD
47#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
48#endif
49#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
50#define DBGFIELD(x) x,
51#define DBGVAL_OR_NULLPTR(x) x
52#else
53#define DBGFIELD(x)
54#define DBGVAL_OR_NULLPTR(x) nullptr
55#endif
56
57// ===============================================================
58// Data tables for the new per-operand machine model.
59
60static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
61static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
62
63// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
64extern const llvm::MCWriteProcResEntry VEWriteProcResTable[] = {
65 { 0, 0, 0 }, // Invalid
66}; // VEWriteProcResTable
67
68// {Cycles, WriteResourceID}
69extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[] = {
70 { 0, 0}, // Invalid
71}; // VEWriteLatencyTable
72
73// {UseIdx, WriteResourceID, Cycles}
74extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[] = {
75 {0, 0, 0}, // Invalid
76}; // VEReadAdvanceTable
77
78#ifdef __GNUC__
79#pragma GCC diagnostic push
80#pragma GCC diagnostic ignored "-Woverlength-strings"
81#endif
82static constexpr char VESchedClassNamesStorage[] =
83 "\0"
84 "InvalidSchedClass\0"
85 ;
86#ifdef __GNUC__
87#pragma GCC diagnostic pop
88#endif
89
90static constexpr llvm::StringTable
91VESchedClassNames = VESchedClassNamesStorage;
92
93extern const llvm::MCSchedModel VESchedModels[] = {
94{ // NoSchedModel
95 MCSchedModel::DefaultIssueWidth,
96 MCSchedModel::DefaultMicroOpBufferSize,
97 MCSchedModel::DefaultLoopMicroOpBufferSize,
98 MCSchedModel::DefaultLoadLatency,
99 MCSchedModel::DefaultHighLatency,
100 MCSchedModel::DefaultMispredictPenalty,
101 false, // PostRAScheduler
102 false, // CompleteModel
103 false, // EnableIntervals
104 0, // Processor ID
105 nullptr, nullptr, 0, 0, // No instruction-level machine model.
106 DBGVAL_OR_NULLPTR(&VESchedClassNames), // SchedClassNames
107 nullptr, // No Itinerary
108 nullptr // No extra processor descriptor
109 },
110};
111
112#undef DBGFIELD
113
114#undef DBGVAL_OR_NULLPTR
115
116static constexpr size_t VECPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 0>);
117// Sorted (by key) array of values for CPU subtype.
118extern const llvm::SubtargetSubTypeKVStorage< 1, 0, 10> VESubTypeKVStorage = {
119 {
120 { sizeof(SubtargetSubTypeKV) * 1 + VECPUAliasArraySize + 1, { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
121 },
122 { {
123 } },
124 "\000generic\000"};
125
126namespace VE_MC {
127
128unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
129 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
130 // Don't know how to resolve this scheduling class.
131 return 0;
132}
133
134} // namespace VE_MC
135struct VEGenMCSubtargetInfo : public MCSubtargetInfo {
136 VEGenMCSubtargetInfo(const Triple &TT,
137 StringRef CPU, StringRef TuneCPU, StringRef FS,
138 StringTable PN,
139 ArrayRef<SubtargetFeatureKV> PF,
140 ArrayRef<SubtargetSubTypeKV> PD,
141 ArrayRef<SubtargetSubTypeAliasKV> PA,
142 const MCSchedModel *PSM,
143 const MCWriteProcResEntry *WPR,
144 const MCWriteLatencyEntry *WL,
145 const MCReadAdvanceEntry *RA, const InstrStage *IS,
146 const unsigned *OC, const unsigned *FP) :
147 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
148 WPR, WL, RA, IS, OC, FP) { }
149
150 unsigned resolveVariantSchedClass(unsigned SchedClass,
151 const MCInst *MI, const MCInstrInfo *MCII,
152 unsigned CPUID) const final {
153 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
154 }
155};
156
157static inline MCSubtargetInfo *createVEMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
158 return new VEGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(VESubTypeKVStorage.Strings), VEFeatureKVStorage.Features, VESubTypeKVStorage.SubTypes, ArrayRef(VESubTypeKVStorage.Aliases).take_front(0), VESchedModels,
159 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
160 nullptr, nullptr, nullptr);
161}
162
163
164} // namespace llvm
165
166#endif // GET_SUBTARGETINFO_MC_DESC
167
168#ifdef GET_SUBTARGETINFO_TARGET_DESC
169#undef GET_SUBTARGETINFO_TARGET_DESC
170
171#include "llvm/ADT/BitmaskEnum.h"
172#include "llvm/Support/Debug.h"
173#include "llvm/Support/raw_ostream.h"
174
175// ParseSubtargetFeatures - Parses features string setting specified
176// subtarget options.
177void llvm::VESubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
178 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
179 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
180 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
181 InitMCProcessorInfo(CPU, TuneCPU, FS);
182 const FeatureBitset &Bits = getFeatureBits();
183 if (Bits[VE::FeatureEnableVPU]) EnableVPU = true;
184}
185
186#endif // GET_SUBTARGETINFO_TARGET_DESC
187
188#ifdef GET_SUBTARGETINFO_HEADER
189#undef GET_SUBTARGETINFO_HEADER
190
191namespace llvm {
192
193class DFAPacketizer;
194namespace VE_MC {
195
196unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
197
198} // namespace VE_MC
199struct VEGenSubtargetInfo : public TargetSubtargetInfo {
200 explicit VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
201public:
202 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
203 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
204 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
205 const FeatureBitset &getInlineIgnoreFeatures() const override;
206 const FeatureBitset &getInlineInverseFeatures() const override;
207 const FeatureBitset &getInlineMustMatchFeatures() const override;
208};
209
210} // namespace llvm
211
212#endif // GET_SUBTARGETINFO_HEADER
213
214#ifdef GET_SUBTARGETINFO_CTOR
215#undef GET_SUBTARGETINFO_CTOR
216
217#include "llvm/CodeGen/TargetSchedule.h"
218
219namespace llvm {
220
221extern const llvm::StringRef VENames[];
222extern const llvm::SubtargetFeatureKVStorage<1, 21> VEFeatureKVStorage;
223extern const llvm::SubtargetSubTypeKVStorage<1, 0, 10> VESubTypeKVStorage;
224extern const llvm::MCSchedModel VESchedModels[];
225extern const llvm::MCWriteProcResEntry VEWriteProcResTable[];
226extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[];
227extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[];
228VEGenSubtargetInfo::VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
229 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(VESubTypeKVStorage.Strings), ArrayRef(VEFeatureKVStorage.Features), ArrayRef(VESubTypeKVStorage.SubTypes), ArrayRef(VESubTypeKVStorage.Aliases).take_front(0), VESchedModels,
230 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
231 nullptr, nullptr, nullptr) {}
232
233unsigned VEGenSubtargetInfo
234::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
235 report_fatal_error("Expected a variant SchedClass");
236} // VEGenSubtargetInfo::resolveSchedClass
237
238unsigned VEGenSubtargetInfo
239::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
240 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
241} // VEGenSubtargetInfo::resolveVariantSchedClass
242
243const FeatureBitset &VEGenSubtargetInfo::getInlineIgnoreFeatures() const {
244 static constexpr FeatureBitset Features = {
245 };
246 return Features;
247}
248
249const FeatureBitset &VEGenSubtargetInfo::getInlineInverseFeatures() const {
250 static constexpr FeatureBitset Features = {
251 };
252 return Features;
253}
254
255const FeatureBitset &VEGenSubtargetInfo::getInlineMustMatchFeatures() const {
256 static constexpr FeatureBitset Features = {
257 };
258 return Features;
259}
260
261
262} // namespace llvm
263
264#endif // GET_SUBTARGETINFO_CTOR
265
266#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
267#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
268
269
270#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
271
272#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
273#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
274
275
276#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
277
278