1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t WebAssemblyRegDiffLists[] = {
12 /* 0 */ 0,
13};
14
15extern const LaneBitmask WebAssemblyLaneMaskLists[] = {
16 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
17};
18
19extern const uint16_t WebAssemblySubRegIdxLists[] = {
20 /* 0 */
21 /* dummy */ 0
22};
23
24
25#ifdef __GNUC__
26#pragma GCC diagnostic push
27#pragma GCC diagnostic ignored "-Woverlength-strings"
28#endif
29extern const char WebAssemblyRegStrings[] = {
30 /* 0 */ "F32_0\000"
31 /* 6 */ "I32_0\000"
32 /* 12 */ "F64_0\000"
33 /* 18 */ "I64_0\000"
34 /* 24 */ "V128_0\000"
35 /* 31 */ "FUNCREF_0\000"
36 /* 41 */ "EXTERNREF_0\000"
37 /* 53 */ "EXNREF_0\000"
38 /* 62 */ "FP32\000"
39 /* 67 */ "SP32\000"
40 /* 72 */ "FP64\000"
41 /* 77 */ "SP64\000"
42 /* 82 */ "VALUE_STACK\000"
43 /* 94 */ "ARGUMENTS\000"
44};
45#ifdef __GNUC__
46#pragma GCC diagnostic pop
47#endif
48
49extern const MCRegisterDesc WebAssemblyRegDesc[] = { // Descriptors
50 { .Name: 5, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
51 { .Name: 94, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
52 { .Name: 82, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 1, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
53 { .Name: 53, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 2, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
54 { .Name: 41, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 3, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
55 { .Name: 62, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 4, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
56 { .Name: 72, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 5, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
57 { .Name: 31, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 6, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
58 { .Name: 67, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 7, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
59 { .Name: 77, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 8, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
60 { .Name: 0, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 9, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
61 { .Name: 12, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 10, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
62 { .Name: 6, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 11, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
63 { .Name: 18, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 12, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
64 { .Name: 24, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 13, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
65};
66
67extern const MCPhysReg WebAssemblyRegUnitRoots[][2] = {
68 { WebAssembly::ARGUMENTS },
69 { WebAssembly::VALUE_STACK },
70 { WebAssembly::EXNREF_0 },
71 { WebAssembly::EXTERNREF_0 },
72 { WebAssembly::FP32 },
73 { WebAssembly::FP64 },
74 { WebAssembly::FUNCREF_0 },
75 { WebAssembly::SP32 },
76 { WebAssembly::SP64 },
77 { WebAssembly::F32_0 },
78 { WebAssembly::F64_0 },
79 { WebAssembly::I32_0 },
80 { WebAssembly::I64_0 },
81 { WebAssembly::V128_0 },
82};
83
84namespace {
85
86// Register classes...
87 // EXNREF Register Class...
88 const MCPhysReg EXNREF[] = {
89 WebAssembly::EXNREF_0,
90 };
91
92 // EXNREF Bit set.
93 const uint8_t EXNREFBits[] = {
94 0x08,
95 };
96
97 // EXTERNREF Register Class...
98 const MCPhysReg EXTERNREF[] = {
99 WebAssembly::EXTERNREF_0,
100 };
101
102 // EXTERNREF Bit set.
103 const uint8_t EXTERNREFBits[] = {
104 0x10,
105 };
106
107 // FUNCREF Register Class...
108 const MCPhysReg FUNCREF[] = {
109 WebAssembly::FUNCREF_0,
110 };
111
112 // FUNCREF Bit set.
113 const uint8_t FUNCREFBits[] = {
114 0x80,
115 };
116
117 // I32 Register Class...
118 const MCPhysReg I32[] = {
119 WebAssembly::FP32, WebAssembly::SP32, WebAssembly::I32_0,
120 };
121
122 // I32 Bit set.
123 const uint8_t I32Bits[] = {
124 0x20, 0x11,
125 };
126
127 // F32 Register Class...
128 const MCPhysReg F32[] = {
129 WebAssembly::F32_0,
130 };
131
132 // F32 Bit set.
133 const uint8_t F32Bits[] = {
134 0x00, 0x04,
135 };
136
137 // I64 Register Class...
138 const MCPhysReg I64[] = {
139 WebAssembly::FP64, WebAssembly::SP64, WebAssembly::I64_0,
140 };
141
142 // I64 Bit set.
143 const uint8_t I64Bits[] = {
144 0x40, 0x22,
145 };
146
147 // F64 Register Class...
148 const MCPhysReg F64[] = {
149 WebAssembly::F64_0,
150 };
151
152 // F64 Bit set.
153 const uint8_t F64Bits[] = {
154 0x00, 0x08,
155 };
156
157 // V128 Register Class...
158 const MCPhysReg V128[] = {
159 WebAssembly::V128_0,
160 };
161
162 // V128 Bit set.
163 const uint8_t V128Bits[] = {
164 0x00, 0x40,
165 };
166
167} // namespace
168
169#ifdef __GNUC__
170#pragma GCC diagnostic push
171#pragma GCC diagnostic ignored "-Woverlength-strings"
172#endif
173extern const char WebAssemblyRegClassStrings[] = {
174 /* 0 */ "F32\000"
175 /* 4 */ "I32\000"
176 /* 8 */ "F64\000"
177 /* 12 */ "I64\000"
178 /* 16 */ "V128\000"
179 /* 21 */ "FUNCREF\000"
180 /* 29 */ "EXTERNREF\000"
181 /* 39 */ "EXNREF\000"
182};
183#ifdef __GNUC__
184#pragma GCC diagnostic pop
185#endif
186
187extern const MCRegisterClass WebAssemblyMCRegisterClasses[] = {
188 { .RegsBegin: EXNREF, .RegSet: EXNREFBits, .NameIdx: 39, .RegsSize: 1, .RegSetSize: sizeof(EXNREFBits), .ID: WebAssembly::EXNREFRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
189 { .RegsBegin: EXTERNREF, .RegSet: EXTERNREFBits, .NameIdx: 29, .RegsSize: 1, .RegSetSize: sizeof(EXTERNREFBits), .ID: WebAssembly::EXTERNREFRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
190 { .RegsBegin: FUNCREF, .RegSet: FUNCREFBits, .NameIdx: 21, .RegsSize: 1, .RegSetSize: sizeof(FUNCREFBits), .ID: WebAssembly::FUNCREFRegClassID, .RegSizeInBits: 0, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
191 { .RegsBegin: I32, .RegSet: I32Bits, .NameIdx: 4, .RegsSize: 3, .RegSetSize: sizeof(I32Bits), .ID: WebAssembly::I32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
192 { .RegsBegin: F32, .RegSet: F32Bits, .NameIdx: 0, .RegsSize: 1, .RegSetSize: sizeof(F32Bits), .ID: WebAssembly::F32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
193 { .RegsBegin: I64, .RegSet: I64Bits, .NameIdx: 12, .RegsSize: 3, .RegSetSize: sizeof(I64Bits), .ID: WebAssembly::I64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
194 { .RegsBegin: F64, .RegSet: F64Bits, .NameIdx: 8, .RegsSize: 1, .RegSetSize: sizeof(F64Bits), .ID: WebAssembly::F64RegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
195 { .RegsBegin: V128, .RegSet: V128Bits, .NameIdx: 16, .RegsSize: 1, .RegSetSize: sizeof(V128Bits), .ID: WebAssembly::V128RegClassID, .RegSizeInBits: 128, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
196};
197
198extern const uint16_t WebAssemblyRegEncodingTable[] = {
199 0,
200 0,
201 0,
202 0,
203 0,
204 0,
205 0,
206 0,
207 0,
208 0,
209 0,
210 0,
211 0,
212 0,
213 0,
214};
215static inline void InitWebAssemblyMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
216 RI->InitMCRegisterInfo(D: WebAssemblyRegDesc, NR: 15, RA, PC, C: WebAssemblyMCRegisterClasses, NC: 8, RURoots: WebAssemblyRegUnitRoots, NRU: 14, DL: WebAssemblyRegDiffLists, RUMS: WebAssemblyLaneMaskLists, Strings: WebAssemblyRegStrings, ClassStrings: WebAssemblyRegClassStrings, SubIndices: WebAssemblySubRegIdxLists, NumIndices: 1,
217RET: WebAssemblyRegEncodingTable, RUI: nullptr);
218
219}
220
221
222} // namespace llvm
223