1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
12
13static const MVT::SimpleValueType WebAssemblyVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::f64, MVT::Other,
18 /* 8 */ MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
19 /* 16 */ MVT::funcref, MVT::Other,
20 /* 18 */ MVT::externref, MVT::Other,
21 /* 20 */ MVT::exnref, MVT::Other,
22};
23static constexpr char WebAssemblySubRegIndexStrings[] = {
24 /* dummy */ 0
25};
26
27
28static constexpr uint32_t WebAssemblySubRegIndexNameOffsets[] = {
29 /* dummy */ 0
30};
31
32static const TargetRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRangeTable[] = {
33 { .Offset: 4294967295, .Size: 4294967295 },
34 { .Offset: 4294967295, .Size: 4294967295 },
35};
36
37
38static const LaneBitmask WebAssemblySubRegIndexLaneMaskTable[] = {
39 LaneBitmask::getAll(),
40 };
41
42
43
44static const TargetRegisterInfo::RegClassInfo WebAssemblyRegClassInfos[] = {
45 // Mode = 0 (DefaultMode)
46 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 20 }, // EXNREF
47 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 18 }, // EXTERNREF
48 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 16 }, // FUNCREF
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 0 }, // I32
50 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 4 }, // F32
51 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 2 }, // I64
52 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 6 }, // F64
53 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*WebAssemblyVTLists+*/.VTListOffset: 8 }, // V128
54 // Mode = 1 (WASM64)
55 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 20 }, // EXNREF
56 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 18 }, // EXTERNREF
57 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 16 }, // FUNCREF
58 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 0 }, // I32
59 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 4 }, // F32
60 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 2 }, // I64
61 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 6 }, // F64
62 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*WebAssemblyVTLists+*/.VTListOffset: 8 }, // V128
63};
64static const uint32_t EXNREFSubClassMask[] = {
65 0x00000001,
66};
67
68static const uint32_t EXTERNREFSubClassMask[] = {
69 0x00000002,
70};
71
72static const uint32_t FUNCREFSubClassMask[] = {
73 0x00000004,
74};
75
76static const uint32_t I32SubClassMask[] = {
77 0x00000008,
78};
79
80static const uint32_t F32SubClassMask[] = {
81 0x00000010,
82};
83
84static const uint32_t I64SubClassMask[] = {
85 0x00000020,
86};
87
88static const uint32_t F64SubClassMask[] = {
89 0x00000040,
90};
91
92static const uint32_t V128SubClassMask[] = {
93 0x00000080,
94};
95
96static const uint16_t SuperRegIdxSeqs[] = {
97 /* 0 */ 0,
98};
99
100namespace WebAssembly {
101
102// Register class instances.
103 extern const TargetRegisterClass EXNREFRegClass = {
104 .MC: &WebAssemblyMCRegisterClasses[EXNREFRegClassID],
105 .SubClassMask: EXNREFSubClassMask,
106 .SuperRegIndices: SuperRegIdxSeqs + 0,
107 .LaneMask: LaneBitmask(0x0000000000000001),
108 .AllocationPriority: 0,
109 .GlobalPriority: false,
110 .TSFlags: 0x00, /* TSFlags */
111 .SpillStackID: 0, /* SpillStackID */
112 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
113 .CoveredBySubRegs: false, /* CoveredBySubRegs */
114 .SuperClasses: nullptr, .SuperClassesSize: 0,
115 .OrderFunc: nullptr
116 };
117
118 extern const TargetRegisterClass EXTERNREFRegClass = {
119 .MC: &WebAssemblyMCRegisterClasses[EXTERNREFRegClassID],
120 .SubClassMask: EXTERNREFSubClassMask,
121 .SuperRegIndices: SuperRegIdxSeqs + 0,
122 .LaneMask: LaneBitmask(0x0000000000000001),
123 .AllocationPriority: 0,
124 .GlobalPriority: false,
125 .TSFlags: 0x00, /* TSFlags */
126 .SpillStackID: 0, /* SpillStackID */
127 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
128 .CoveredBySubRegs: false, /* CoveredBySubRegs */
129 .SuperClasses: nullptr, .SuperClassesSize: 0,
130 .OrderFunc: nullptr
131 };
132
133 extern const TargetRegisterClass FUNCREFRegClass = {
134 .MC: &WebAssemblyMCRegisterClasses[FUNCREFRegClassID],
135 .SubClassMask: FUNCREFSubClassMask,
136 .SuperRegIndices: SuperRegIdxSeqs + 0,
137 .LaneMask: LaneBitmask(0x0000000000000001),
138 .AllocationPriority: 0,
139 .GlobalPriority: false,
140 .TSFlags: 0x00, /* TSFlags */
141 .SpillStackID: 0, /* SpillStackID */
142 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
143 .CoveredBySubRegs: false, /* CoveredBySubRegs */
144 .SuperClasses: nullptr, .SuperClassesSize: 0,
145 .OrderFunc: nullptr
146 };
147
148 extern const TargetRegisterClass I32RegClass = {
149 .MC: &WebAssemblyMCRegisterClasses[I32RegClassID],
150 .SubClassMask: I32SubClassMask,
151 .SuperRegIndices: SuperRegIdxSeqs + 0,
152 .LaneMask: LaneBitmask(0x0000000000000001),
153 .AllocationPriority: 0,
154 .GlobalPriority: false,
155 .TSFlags: 0x00, /* TSFlags */
156 .SpillStackID: 0, /* SpillStackID */
157 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
158 .CoveredBySubRegs: false, /* CoveredBySubRegs */
159 .SuperClasses: nullptr, .SuperClassesSize: 0,
160 .OrderFunc: nullptr
161 };
162
163 extern const TargetRegisterClass F32RegClass = {
164 .MC: &WebAssemblyMCRegisterClasses[F32RegClassID],
165 .SubClassMask: F32SubClassMask,
166 .SuperRegIndices: SuperRegIdxSeqs + 0,
167 .LaneMask: LaneBitmask(0x0000000000000001),
168 .AllocationPriority: 0,
169 .GlobalPriority: false,
170 .TSFlags: 0x00, /* TSFlags */
171 .SpillStackID: 0, /* SpillStackID */
172 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
173 .CoveredBySubRegs: false, /* CoveredBySubRegs */
174 .SuperClasses: nullptr, .SuperClassesSize: 0,
175 .OrderFunc: nullptr
176 };
177
178 extern const TargetRegisterClass I64RegClass = {
179 .MC: &WebAssemblyMCRegisterClasses[I64RegClassID],
180 .SubClassMask: I64SubClassMask,
181 .SuperRegIndices: SuperRegIdxSeqs + 0,
182 .LaneMask: LaneBitmask(0x0000000000000001),
183 .AllocationPriority: 0,
184 .GlobalPriority: false,
185 .TSFlags: 0x00, /* TSFlags */
186 .SpillStackID: 0, /* SpillStackID */
187 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
188 .CoveredBySubRegs: false, /* CoveredBySubRegs */
189 .SuperClasses: nullptr, .SuperClassesSize: 0,
190 .OrderFunc: nullptr
191 };
192
193 extern const TargetRegisterClass F64RegClass = {
194 .MC: &WebAssemblyMCRegisterClasses[F64RegClassID],
195 .SubClassMask: F64SubClassMask,
196 .SuperRegIndices: SuperRegIdxSeqs + 0,
197 .LaneMask: LaneBitmask(0x0000000000000001),
198 .AllocationPriority: 0,
199 .GlobalPriority: false,
200 .TSFlags: 0x00, /* TSFlags */
201 .SpillStackID: 0, /* SpillStackID */
202 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
203 .CoveredBySubRegs: false, /* CoveredBySubRegs */
204 .SuperClasses: nullptr, .SuperClassesSize: 0,
205 .OrderFunc: nullptr
206 };
207
208 extern const TargetRegisterClass V128RegClass = {
209 .MC: &WebAssemblyMCRegisterClasses[V128RegClassID],
210 .SubClassMask: V128SubClassMask,
211 .SuperRegIndices: SuperRegIdxSeqs + 0,
212 .LaneMask: LaneBitmask(0x0000000000000001),
213 .AllocationPriority: 0,
214 .GlobalPriority: false,
215 .TSFlags: 0x00, /* TSFlags */
216 .SpillStackID: 0, /* SpillStackID */
217 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
218 .CoveredBySubRegs: false, /* CoveredBySubRegs */
219 .SuperClasses: nullptr, .SuperClassesSize: 0,
220 .OrderFunc: nullptr
221 };
222
223
224} // namespace WebAssembly
225static const TargetRegisterClass *const WebAssemblyRegisterClasses[] = {
226 &WebAssembly::EXNREFRegClass,
227 &WebAssembly::EXTERNREFRegClass,
228 &WebAssembly::FUNCREFRegClass,
229 &WebAssembly::I32RegClass,
230 &WebAssembly::F32RegClass,
231 &WebAssembly::I64RegClass,
232 &WebAssembly::F64RegClass,
233 &WebAssembly::V128RegClass,
234 };
235
236static const uint8_t WebAssemblyCostPerUseTable[] = {
2370, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
238
239
240static const bool WebAssemblyInAllocatableClassTable[] = {
241false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
242
243
244static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
245.CostPerUse: WebAssemblyCostPerUseTable, .NumCosts: 1, .InAllocatableClass: WebAssemblyInAllocatableClassTable};
246
247/// Get the weight in units of pressure for this register class.
248const RegClassWeight &WebAssemblyGenRegisterInfo::
249getRegClassWeight(const TargetRegisterClass *RC) const {
250 static const RegClassWeight RCWeightTable[] = {
251 {.RegWeight: 1, .WeightLimit: 1}, // EXNREF
252 {.RegWeight: 1, .WeightLimit: 1}, // EXTERNREF
253 {.RegWeight: 1, .WeightLimit: 1}, // FUNCREF
254 {.RegWeight: 1, .WeightLimit: 3}, // I32
255 {.RegWeight: 1, .WeightLimit: 1}, // F32
256 {.RegWeight: 1, .WeightLimit: 3}, // I64
257 {.RegWeight: 1, .WeightLimit: 1}, // F64
258 {.RegWeight: 1, .WeightLimit: 1}, // V128
259 };
260 return RCWeightTable[RC->getID()];
261}
262
263/// Get the weight in units of pressure for this register unit.
264unsigned WebAssemblyGenRegisterInfo::
265getRegUnitWeight(MCRegUnit RegUnit) const {
266 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
267 // All register units have unit weight.
268 return 1;
269}
270
271
272// Get the number of dimensions of register pressure.
273unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
274 return 8;
275}
276
277// Get the name of this register unit pressure set.
278const char *WebAssemblyGenRegisterInfo::
279getRegPressureSetName(unsigned Idx) const {
280 static const char *PressureNameTable[] = {
281 "EXNREF",
282 "EXTERNREF",
283 "FUNCREF",
284 "F32",
285 "F64",
286 "V128",
287 "I32",
288 "I64",
289 };
290 return PressureNameTable[Idx];
291}
292
293// Get the register unit pressure limit for this dimension.
294// This limit must be adjusted dynamically for reserved registers.
295unsigned WebAssemblyGenRegisterInfo::
296getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
297 static const uint8_t PressureLimitTable[] = {
298 1, // 0: EXNREF
299 1, // 1: EXTERNREF
300 1, // 2: FUNCREF
301 1, // 3: F32
302 1, // 4: F64
303 1, // 5: V128
304 3, // 6: I32
305 3, // 7: I64
306 };
307 return PressureLimitTable[Idx];
308}
309
310/// Table of pressure sets per register class or unit.
311static const int RCSetsTable[] = {
312 /* 0 */ 0, -1,
313 /* 2 */ 1, -1,
314 /* 4 */ 2, -1,
315 /* 6 */ 3, -1,
316 /* 8 */ 4, -1,
317 /* 10 */ 5, -1,
318 /* 12 */ 6, -1,
319 /* 14 */ 7, -1,
320};
321
322/// Get the dimensions of register pressure impacted by this register class.
323/// Returns a -1 terminated array of pressure set IDs
324const int *WebAssemblyGenRegisterInfo::
325getRegClassPressureSets(const TargetRegisterClass *RC) const {
326 static const uint8_t RCSetStartTable[] = {
327 0,2,4,12,6,14,8,10,};
328 return &RCSetsTable[RCSetStartTable[RC->getID()]];
329}
330
331/// Get the dimensions of register pressure impacted by this register unit.
332/// Returns a -1 terminated array of pressure set IDs
333const int *WebAssemblyGenRegisterInfo::
334getRegUnitPressureSets(MCRegUnit RegUnit) const {
335 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
336 static const uint8_t RUSetStartTable[] = {
337 1,1,0,2,12,14,4,12,14,6,8,12,14,10,};
338 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
339}
340
341
342// Register to minimal register class mapping
343
344const TargetRegisterClass *WebAssemblyGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
345 static const uint16_t InvalidRegClassID = UINT16_MAX;
346
347 static const uint16_t Mapping[15] = {
348 InvalidRegClassID, // NoRegister
349 InvalidRegClassID, // ARGUMENTS
350 InvalidRegClassID, // VALUE_STACK
351 WebAssembly::EXNREFRegClassID, // EXNREF_0
352 WebAssembly::EXTERNREFRegClassID, // EXTERNREF_0
353 WebAssembly::I32RegClassID, // FP32
354 WebAssembly::I64RegClassID, // FP64
355 WebAssembly::FUNCREFRegClassID, // FUNCREF_0
356 WebAssembly::I32RegClassID, // SP32
357 WebAssembly::I64RegClassID, // SP64
358 WebAssembly::F32RegClassID, // F32_0
359 WebAssembly::F64RegClassID, // F64_0
360 WebAssembly::I32RegClassID, // I32_0
361 WebAssembly::I64RegClassID, // I64_0
362 WebAssembly::V128RegClassID, // V128_0
363 };
364
365 assert(Reg < ArrayRef(Mapping).size());
366 unsigned RCID = Mapping[Reg.id()];
367 if (RCID == InvalidRegClassID)
368 return nullptr;
369 return WebAssemblyRegisterClasses[RCID];
370}
371extern const MCRegisterDesc WebAssemblyRegDesc[];
372extern const int16_t WebAssemblyRegDiffLists[];
373extern const LaneBitmask WebAssemblyLaneMaskLists[];
374extern const char WebAssemblyRegStrings[];
375extern const char WebAssemblyRegClassStrings[];
376extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
377extern const uint16_t WebAssemblySubRegIdxLists[];
378extern const uint16_t WebAssemblyRegEncodingTable[];
379
380WebAssemblyGenRegisterInfo::
381WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
382 unsigned PC, unsigned HwMode)
383 : TargetRegisterInfo(&WebAssemblyRegInfoDesc, WebAssemblyRegisterClasses,
384 WebAssemblySubRegIndexStrings, WebAssemblySubRegIndexNameOffsets,
385 WebAssemblySubRegIdxRangeTable, WebAssemblySubRegIndexLaneMaskTable,
386
387 LaneBitmask(0xFFFFFFFFFFFFFFFF), WebAssemblyRegClassInfos, WebAssemblyVTLists, HwMode) {
388 InitMCRegisterInfo(D: WebAssemblyRegDesc, NR: 15, RA, PC,
389 C: WebAssemblyMCRegisterClasses, NC: 8, RURoots: WebAssemblyRegUnitRoots, NRU: 14, DL: WebAssemblyRegDiffLists,
390 RUMS: WebAssemblyLaneMaskLists, Strings: WebAssemblyRegStrings, ClassStrings: WebAssemblyRegClassStrings, SubIndices: WebAssemblySubRegIdxLists, NumIndices: 1,
391 RET: WebAssemblyRegEncodingTable, RUI: nullptr);
392
393}
394
395
396
397ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
398 return {};
399}
400
401bool WebAssemblyGenRegisterInfo::
402isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
403 return
404 false;
405}
406
407bool WebAssemblyGenRegisterInfo::
408isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
409 return
410 false;
411}
412
413bool WebAssemblyGenRegisterInfo::
414isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
415 return
416 false;
417}
418
419bool WebAssemblyGenRegisterInfo::
420isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
421 return
422 false;
423}
424
425bool WebAssemblyGenRegisterInfo::
426isConstantPhysReg(MCRegister PhysReg) const {
427 return
428 false;
429}
430
431ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
432 return {};
433}
434
435const WebAssemblyFrameLowering *
436WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
437 return static_cast<const WebAssemblyFrameLowering *>(
438 MF.getSubtarget().getFrameLowering());
439}
440
441
442} // namespace llvm
443