1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<8, 12, 8, 8, 1, 0> WebAssemblyMCRegisterClassStorage;
12
13static const MVT::SimpleValueType WebAssemblyVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::f64, MVT::Other,
18 /* 8 */ MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
19 /* 16 */ MVT::funcref, MVT::Other,
20 /* 18 */ MVT::externref, MVT::Other,
21 /* 20 */ MVT::exnref, MVT::Other,
22};
23static constexpr char WebAssemblySubRegIndexStrings[] = {
24 /* dummy */ 0
25};
26
27
28static constexpr uint32_t WebAssemblySubRegIndexNameOffsets[] = {
29 /* dummy */ 0
30};
31
32static const TargetRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRangeTable[] = {
33 { .Offset: 4294967295, .Size: 4294967295 },
34 { .Offset: 4294967295, .Size: 4294967295 },
35};
36
37
38static const LaneBitmask WebAssemblySubRegIndexLaneMaskTable[] = {
39 LaneBitmask::getAll(),
40 };
41
42
43
44static const TargetRegisterInfo::RegClassInfo WebAssemblyRegClassInfos[] = {
45 // Mode = 0 (DefaultMode)
46 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 20 }, // EXNREF
47 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 18 }, // EXTERNREF
48 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 16 }, // FUNCREF
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 0 }, // I32
50 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 4 }, // F32
51 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 2 }, // I64
52 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 6 }, // F64
53 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*WebAssemblyVTLists+*/.VTListOffset: 8 }, // V128
54 // Mode = 1 (WASM64)
55 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 20 }, // EXNREF
56 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 18 }, // EXTERNREF
57 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 16 }, // FUNCREF
58 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 0 }, // I32
59 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 4 }, // F32
60 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 2 }, // I64
61 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 6 }, // F64
62 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*WebAssemblyVTLists+*/.VTListOffset: 8 }, // V128
63};
64
65static const uint8_t WebAssemblyCostPerUseTable[] = {
660, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
67
68
69static const bool WebAssemblyInAllocatableClassTable[] = {
70false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
71
72
73static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
74.CostPerUse: WebAssemblyCostPerUseTable, .NumCosts: 1, .InAllocatableClass: WebAssemblyInAllocatableClassTable};
75
76/// Get the weight in units of pressure for this register class.
77const RegClassWeight &WebAssemblyGenRegisterInfo::
78getRegClassWeight(const TargetRegisterClass *RC) const {
79 static const RegClassWeight RCWeightTable[] = {
80 {.RegWeight: 1, .WeightLimit: 1}, // EXNREF
81 {.RegWeight: 1, .WeightLimit: 1}, // EXTERNREF
82 {.RegWeight: 1, .WeightLimit: 1}, // FUNCREF
83 {.RegWeight: 1, .WeightLimit: 3}, // I32
84 {.RegWeight: 1, .WeightLimit: 1}, // F32
85 {.RegWeight: 1, .WeightLimit: 3}, // I64
86 {.RegWeight: 1, .WeightLimit: 1}, // F64
87 {.RegWeight: 1, .WeightLimit: 1}, // V128
88 };
89 return RCWeightTable[RC->getID()];
90}
91
92/// Get the weight in units of pressure for this register unit.
93unsigned WebAssemblyGenRegisterInfo::
94getRegUnitWeight(MCRegUnit RegUnit) const {
95 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
96 // All register units have unit weight.
97 return 1;
98}
99
100
101// Get the number of dimensions of register pressure.
102unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
103 return 8;
104}
105
106// Get the name of this register unit pressure set.
107const char *WebAssemblyGenRegisterInfo::
108getRegPressureSetName(unsigned Idx) const {
109 static const char *PressureNameTable[] = {
110 "EXNREF",
111 "EXTERNREF",
112 "FUNCREF",
113 "F32",
114 "F64",
115 "V128",
116 "I32",
117 "I64",
118 };
119 return PressureNameTable[Idx];
120}
121
122// Get the register unit pressure limit for this dimension.
123// This limit must be adjusted dynamically for reserved registers.
124unsigned WebAssemblyGenRegisterInfo::
125getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
126 static const uint8_t PressureLimitTable[] = {
127 1, // 0: EXNREF
128 1, // 1: EXTERNREF
129 1, // 2: FUNCREF
130 1, // 3: F32
131 1, // 4: F64
132 1, // 5: V128
133 3, // 6: I32
134 3, // 7: I64
135 };
136 return PressureLimitTable[Idx];
137}
138
139/// Get the register class for this pressure set with the largest
140/// `RegClassWeight::WeightLimit`.
141const TargetRegisterClass *WebAssemblyGenRegisterInfo::
142getLargestRegClassForRegPressureSet(unsigned Idx) const {
143 static const uint8_t PSetRegClassTable[] = {
144 WebAssembly::EXNREFRegClassID, // 0: EXNREF
145 WebAssembly::EXTERNREFRegClassID, // 1: EXTERNREF
146 WebAssembly::FUNCREFRegClassID, // 2: FUNCREF
147 WebAssembly::F32RegClassID, // 3: F32
148 WebAssembly::F64RegClassID, // 4: F64
149 WebAssembly::V128RegClassID, // 5: V128
150 WebAssembly::I32RegClassID, // 6: I32
151 WebAssembly::I64RegClassID, // 7: I64
152 };
153 return getRegClass(i: PSetRegClassTable[Idx]);
154}
155
156/// Table of pressure sets per register class or unit.
157static const int RCSetsTable[] = {
158 /* 0 */ 0, -1,
159 /* 2 */ 1, -1,
160 /* 4 */ 2, -1,
161 /* 6 */ 3, -1,
162 /* 8 */ 4, -1,
163 /* 10 */ 5, -1,
164 /* 12 */ 6, -1,
165 /* 14 */ 7, -1,
166};
167
168/// Get the dimensions of register pressure impacted by this register class.
169/// Returns a -1 terminated array of pressure set IDs
170const int *WebAssemblyGenRegisterInfo::
171getRegClassPressureSets(const TargetRegisterClass *RC) const {
172 static const uint8_t RCSetStartTable[] = {
173 0,2,4,12,6,14,8,10,};
174 return &RCSetsTable[RCSetStartTable[RC->getID()]];
175}
176
177/// Get the dimensions of register pressure impacted by this register unit.
178/// Returns a -1 terminated array of pressure set IDs
179const int *WebAssemblyGenRegisterInfo::
180getRegUnitPressureSets(MCRegUnit RegUnit) const {
181 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
182 static const uint8_t RUSetStartTable[] = {
183 1,1,0,2,12,14,4,12,14,6,8,12,14,10,};
184 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
185}
186
187
188// Register to minimal register class mapping
189
190const TargetRegisterClass *WebAssemblyGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
191 static const uint16_t InvalidRegClassID = UINT16_MAX;
192
193 static const uint16_t Mapping[15] = {
194 InvalidRegClassID, // NoRegister
195 InvalidRegClassID, // ARGUMENTS
196 InvalidRegClassID, // VALUE_STACK
197 WebAssembly::EXNREFRegClassID, // EXNREF_0
198 WebAssembly::EXTERNREFRegClassID, // EXTERNREF_0
199 WebAssembly::I32RegClassID, // FP32
200 WebAssembly::I64RegClassID, // FP64
201 WebAssembly::FUNCREFRegClassID, // FUNCREF_0
202 WebAssembly::I32RegClassID, // SP32
203 WebAssembly::I64RegClassID, // SP64
204 WebAssembly::F32RegClassID, // F32_0
205 WebAssembly::F64RegClassID, // F64_0
206 WebAssembly::I32RegClassID, // I32_0
207 WebAssembly::I64RegClassID, // I64_0
208 WebAssembly::V128RegClassID, // V128_0
209 };
210
211 assert(Reg < ArrayRef(Mapping).size());
212 unsigned RCID = Mapping[Reg.id()];
213 if (RCID == InvalidRegClassID)
214 return nullptr;
215 return &WebAssemblyMCRegisterClassStorage.Classes[RCID];
216}
217extern const MCRegisterDesc WebAssemblyRegDesc[];
218extern const int16_t WebAssemblyRegDiffLists[];
219extern const LaneBitmask WebAssemblyLaneMaskLists[];
220extern const char WebAssemblyRegStrings[];
221extern const char WebAssemblyRegClassStrings[];
222extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
223extern const uint16_t WebAssemblySubRegIdxLists[];
224extern const uint16_t WebAssemblyRegEncodingTable[];
225
226WebAssemblyGenRegisterInfo::
227WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
228 unsigned PC, unsigned HwMode)
229 : TargetRegisterInfo(&WebAssemblyRegInfoDesc,
230 WebAssemblySubRegIndexStrings, WebAssemblySubRegIndexNameOffsets,
231 WebAssemblySubRegIdxRangeTable, WebAssemblySubRegIndexLaneMaskTable,
232
233 LaneBitmask(0xFFFFFFFFFFFFFFFF), WebAssemblyRegClassInfos, WebAssemblyVTLists, HwMode) {
234 InitMCRegisterInfo(D: WebAssemblyRegDesc, NR: 15, RA, PC,
235 C: &getWebAssemblyMCRegisterClass(RC: 0), NC: 8, RURoots: WebAssemblyRegUnitRoots, NRU: 14, DL: WebAssemblyRegDiffLists,
236 RUMS: WebAssemblyLaneMaskLists, Strings: WebAssemblyRegStrings, ClassStrings: WebAssemblyRegClassStrings, SubIndices: WebAssemblySubRegIdxLists, NumIndices: 1,
237 RET: WebAssemblyRegEncodingTable, RUI: nullptr);
238
239}
240
241
242
243ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
244 return {};
245}
246
247bool WebAssemblyGenRegisterInfo::
248isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
249 return
250 false;
251}
252
253bool WebAssemblyGenRegisterInfo::
254isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
255 return
256 false;
257}
258
259bool WebAssemblyGenRegisterInfo::
260isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
261 return
262 false;
263}
264
265bool WebAssemblyGenRegisterInfo::
266isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
267 return
268 false;
269}
270
271bool WebAssemblyGenRegisterInfo::
272isConstantPhysReg(MCRegister PhysReg) const {
273 return
274 false;
275}
276
277ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
278 return {};
279}
280
281const WebAssemblyFrameLowering *
282WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
283 return static_cast<const WebAssemblyFrameLowering *>(
284 MF.getSubtarget().getFrameLowering());
285}
286
287
288} // namespace llvm
289