1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::f64, MVT::Other,
18 /* 8 */ MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
19 /* 16 */ MVT::funcref, MVT::Other,
20 /* 18 */ MVT::externref, MVT::Other,
21 /* 20 */ MVT::exnref, MVT::Other,
22};
23static constexpr char WebAssemblySubRegIndexStrings[] = {
24 /* dummy */ 0
25};
26
27
28static constexpr uint32_t WebAssemblySubRegIndexNameOffsets[] = {
29 /* dummy */ 0
30};
31
32static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
33 { .Offset: 65535, .Size: 65535 },
34 { .Offset: 65535, .Size: 65535 },
35};
36
37
38static const LaneBitmask SubRegIndexLaneMaskTable[] = {
39 LaneBitmask::getAll(),
40 };
41
42
43
44static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
45 // Mode = 0 (DefaultMode)
46 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 20 }, // EXNREF
47 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 18 }, // EXTERNREF
48 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 16 }, // FUNCREF
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // I32
50 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // F32
51 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // I64
52 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // F64
53 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 8 }, // V128
54 // Mode = 1 (WASM64)
55 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 20 }, // EXNREF
56 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 18 }, // EXTERNREF
57 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 16 }, // FUNCREF
58 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // I32
59 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // F32
60 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // I64
61 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // F64
62 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 8 }, // V128
63};
64static const uint32_t EXNREFSubClassMask[] = {
65 0x00000001,
66};
67
68static const uint32_t EXTERNREFSubClassMask[] = {
69 0x00000002,
70};
71
72static const uint32_t FUNCREFSubClassMask[] = {
73 0x00000004,
74};
75
76static const uint32_t I32SubClassMask[] = {
77 0x00000008,
78};
79
80static const uint32_t F32SubClassMask[] = {
81 0x00000010,
82};
83
84static const uint32_t I64SubClassMask[] = {
85 0x00000020,
86};
87
88static const uint32_t F64SubClassMask[] = {
89 0x00000040,
90};
91
92static const uint32_t V128SubClassMask[] = {
93 0x00000080,
94};
95
96static const uint16_t SuperRegIdxSeqs[] = {
97 /* 0 */ 0,
98};
99
100namespace WebAssembly {
101
102// Register class instances
103 extern const TargetRegisterClass EXNREFRegClass = {
104 .MC: &WebAssemblyMCRegisterClasses[EXNREFRegClassID],
105 .SubClassMask: EXNREFSubClassMask,
106 .SuperRegIndices: SuperRegIdxSeqs + 0,
107 .LaneMask: LaneBitmask(0x0000000000000001),
108 .AllocationPriority: 0,
109 .GlobalPriority: false,
110 .TSFlags: 0x00, /* TSFlags */
111 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
112 .CoveredBySubRegs: false, /* CoveredBySubRegs */
113 .SuperClasses: nullptr, .SuperClassesSize: 0,
114 .OrderFunc: nullptr
115 };
116
117 extern const TargetRegisterClass EXTERNREFRegClass = {
118 .MC: &WebAssemblyMCRegisterClasses[EXTERNREFRegClassID],
119 .SubClassMask: EXTERNREFSubClassMask,
120 .SuperRegIndices: SuperRegIdxSeqs + 0,
121 .LaneMask: LaneBitmask(0x0000000000000001),
122 .AllocationPriority: 0,
123 .GlobalPriority: false,
124 .TSFlags: 0x00, /* TSFlags */
125 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
126 .CoveredBySubRegs: false, /* CoveredBySubRegs */
127 .SuperClasses: nullptr, .SuperClassesSize: 0,
128 .OrderFunc: nullptr
129 };
130
131 extern const TargetRegisterClass FUNCREFRegClass = {
132 .MC: &WebAssemblyMCRegisterClasses[FUNCREFRegClassID],
133 .SubClassMask: FUNCREFSubClassMask,
134 .SuperRegIndices: SuperRegIdxSeqs + 0,
135 .LaneMask: LaneBitmask(0x0000000000000001),
136 .AllocationPriority: 0,
137 .GlobalPriority: false,
138 .TSFlags: 0x00, /* TSFlags */
139 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
140 .CoveredBySubRegs: false, /* CoveredBySubRegs */
141 .SuperClasses: nullptr, .SuperClassesSize: 0,
142 .OrderFunc: nullptr
143 };
144
145 extern const TargetRegisterClass I32RegClass = {
146 .MC: &WebAssemblyMCRegisterClasses[I32RegClassID],
147 .SubClassMask: I32SubClassMask,
148 .SuperRegIndices: SuperRegIdxSeqs + 0,
149 .LaneMask: LaneBitmask(0x0000000000000001),
150 .AllocationPriority: 0,
151 .GlobalPriority: false,
152 .TSFlags: 0x00, /* TSFlags */
153 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
154 .CoveredBySubRegs: false, /* CoveredBySubRegs */
155 .SuperClasses: nullptr, .SuperClassesSize: 0,
156 .OrderFunc: nullptr
157 };
158
159 extern const TargetRegisterClass F32RegClass = {
160 .MC: &WebAssemblyMCRegisterClasses[F32RegClassID],
161 .SubClassMask: F32SubClassMask,
162 .SuperRegIndices: SuperRegIdxSeqs + 0,
163 .LaneMask: LaneBitmask(0x0000000000000001),
164 .AllocationPriority: 0,
165 .GlobalPriority: false,
166 .TSFlags: 0x00, /* TSFlags */
167 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
168 .CoveredBySubRegs: false, /* CoveredBySubRegs */
169 .SuperClasses: nullptr, .SuperClassesSize: 0,
170 .OrderFunc: nullptr
171 };
172
173 extern const TargetRegisterClass I64RegClass = {
174 .MC: &WebAssemblyMCRegisterClasses[I64RegClassID],
175 .SubClassMask: I64SubClassMask,
176 .SuperRegIndices: SuperRegIdxSeqs + 0,
177 .LaneMask: LaneBitmask(0x0000000000000001),
178 .AllocationPriority: 0,
179 .GlobalPriority: false,
180 .TSFlags: 0x00, /* TSFlags */
181 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
182 .CoveredBySubRegs: false, /* CoveredBySubRegs */
183 .SuperClasses: nullptr, .SuperClassesSize: 0,
184 .OrderFunc: nullptr
185 };
186
187 extern const TargetRegisterClass F64RegClass = {
188 .MC: &WebAssemblyMCRegisterClasses[F64RegClassID],
189 .SubClassMask: F64SubClassMask,
190 .SuperRegIndices: SuperRegIdxSeqs + 0,
191 .LaneMask: LaneBitmask(0x0000000000000001),
192 .AllocationPriority: 0,
193 .GlobalPriority: false,
194 .TSFlags: 0x00, /* TSFlags */
195 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
196 .CoveredBySubRegs: false, /* CoveredBySubRegs */
197 .SuperClasses: nullptr, .SuperClassesSize: 0,
198 .OrderFunc: nullptr
199 };
200
201 extern const TargetRegisterClass V128RegClass = {
202 .MC: &WebAssemblyMCRegisterClasses[V128RegClassID],
203 .SubClassMask: V128SubClassMask,
204 .SuperRegIndices: SuperRegIdxSeqs + 0,
205 .LaneMask: LaneBitmask(0x0000000000000001),
206 .AllocationPriority: 0,
207 .GlobalPriority: false,
208 .TSFlags: 0x00, /* TSFlags */
209 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
210 .CoveredBySubRegs: false, /* CoveredBySubRegs */
211 .SuperClasses: nullptr, .SuperClassesSize: 0,
212 .OrderFunc: nullptr
213 };
214
215
216} // namespace WebAssembly
217namespace {
218
219 const TargetRegisterClass *const RegisterClasses[] = {
220 &WebAssembly::EXNREFRegClass,
221 &WebAssembly::EXTERNREFRegClass,
222 &WebAssembly::FUNCREFRegClass,
223 &WebAssembly::I32RegClass,
224 &WebAssembly::F32RegClass,
225 &WebAssembly::I64RegClass,
226 &WebAssembly::F64RegClass,
227 &WebAssembly::V128RegClass,
228 };
229} // namespace
230
231static const uint8_t CostPerUseTable[] = {
2320, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
233
234
235static const bool InAllocatableClassTable[] = {
236false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
237
238
239static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
240.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
241
242/// Get the weight in units of pressure for this register class.
243const RegClassWeight &WebAssemblyGenRegisterInfo::
244getRegClassWeight(const TargetRegisterClass *RC) const {
245 static const RegClassWeight RCWeightTable[] = {
246 {.RegWeight: 1, .WeightLimit: 1}, // EXNREF
247 {.RegWeight: 1, .WeightLimit: 1}, // EXTERNREF
248 {.RegWeight: 1, .WeightLimit: 1}, // FUNCREF
249 {.RegWeight: 1, .WeightLimit: 3}, // I32
250 {.RegWeight: 1, .WeightLimit: 1}, // F32
251 {.RegWeight: 1, .WeightLimit: 3}, // I64
252 {.RegWeight: 1, .WeightLimit: 1}, // F64
253 {.RegWeight: 1, .WeightLimit: 1}, // V128
254 };
255 return RCWeightTable[RC->getID()];
256}
257
258/// Get the weight in units of pressure for this register unit.
259unsigned WebAssemblyGenRegisterInfo::
260getRegUnitWeight(MCRegUnit RegUnit) const {
261 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
262 // All register units have unit weight.
263 return 1;
264}
265
266
267// Get the number of dimensions of register pressure.
268unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
269 return 8;
270}
271
272// Get the name of this register unit pressure set.
273const char *WebAssemblyGenRegisterInfo::
274getRegPressureSetName(unsigned Idx) const {
275 static const char *PressureNameTable[] = {
276 "EXNREF",
277 "EXTERNREF",
278 "FUNCREF",
279 "F32",
280 "F64",
281 "V128",
282 "I32",
283 "I64",
284 };
285 return PressureNameTable[Idx];
286}
287
288// Get the register unit pressure limit for this dimension.
289// This limit must be adjusted dynamically for reserved registers.
290unsigned WebAssemblyGenRegisterInfo::
291getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
292 static const uint8_t PressureLimitTable[] = {
293 1, // 0: EXNREF
294 1, // 1: EXTERNREF
295 1, // 2: FUNCREF
296 1, // 3: F32
297 1, // 4: F64
298 1, // 5: V128
299 3, // 6: I32
300 3, // 7: I64
301 };
302 return PressureLimitTable[Idx];
303}
304
305/// Table of pressure sets per register class or unit.
306static const int RCSetsTable[] = {
307 /* 0 */ 0, -1,
308 /* 2 */ 1, -1,
309 /* 4 */ 2, -1,
310 /* 6 */ 3, -1,
311 /* 8 */ 4, -1,
312 /* 10 */ 5, -1,
313 /* 12 */ 6, -1,
314 /* 14 */ 7, -1,
315};
316
317/// Get the dimensions of register pressure impacted by this register class.
318/// Returns a -1 terminated array of pressure set IDs
319const int *WebAssemblyGenRegisterInfo::
320getRegClassPressureSets(const TargetRegisterClass *RC) const {
321 static const uint8_t RCSetStartTable[] = {
322 0,2,4,12,6,14,8,10,};
323 return &RCSetsTable[RCSetStartTable[RC->getID()]];
324}
325
326/// Get the dimensions of register pressure impacted by this register unit.
327/// Returns a -1 terminated array of pressure set IDs
328const int *WebAssemblyGenRegisterInfo::
329getRegUnitPressureSets(MCRegUnit RegUnit) const {
330 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
331 static const uint8_t RUSetStartTable[] = {
332 1,1,0,2,12,14,4,12,14,6,8,12,14,10,};
333 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
334}
335
336extern const MCRegisterDesc WebAssemblyRegDesc[];
337extern const int16_t WebAssemblyRegDiffLists[];
338extern const LaneBitmask WebAssemblyLaneMaskLists[];
339extern const char WebAssemblyRegStrings[];
340extern const char WebAssemblyRegClassStrings[];
341extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
342extern const uint16_t WebAssemblySubRegIdxLists[];
343extern const uint16_t WebAssemblyRegEncodingTable[];
344
345WebAssemblyGenRegisterInfo::
346WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
347 unsigned PC, unsigned HwMode)
348 : TargetRegisterInfo(&WebAssemblyRegInfoDesc, RegisterClasses, RegisterClasses+8,
349 WebAssemblySubRegIndexStrings, WebAssemblySubRegIndexNameOffsets,
350 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
351
352 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
353 InitMCRegisterInfo(D: WebAssemblyRegDesc, NR: 15, RA, PC,
354 C: WebAssemblyMCRegisterClasses, NC: 8,
355 RURoots: WebAssemblyRegUnitRoots,
356 NRU: 14,
357 DL: WebAssemblyRegDiffLists,
358 RUMS: WebAssemblyLaneMaskLists,
359 Strings: WebAssemblyRegStrings,
360 ClassStrings: WebAssemblyRegClassStrings,
361 SubIndices: WebAssemblySubRegIdxLists,
362 NumIndices: 1,
363 RET: WebAssemblyRegEncodingTable,
364 RUI: nullptr);
365
366}
367
368
369
370ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
371 return {};
372}
373
374bool WebAssemblyGenRegisterInfo::
375isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
376 return
377 false;
378}
379
380bool WebAssemblyGenRegisterInfo::
381isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
382 return
383 false;
384}
385
386bool WebAssemblyGenRegisterInfo::
387isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
388 return
389 false;
390}
391
392bool WebAssemblyGenRegisterInfo::
393isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
394 return
395 false;
396}
397
398bool WebAssemblyGenRegisterInfo::
399isConstantPhysReg(MCRegister PhysReg) const {
400 return
401 false;
402}
403
404ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
405 return {};
406}
407
408const WebAssemblyFrameLowering *
409WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
410 return static_cast<const WebAssemblyFrameLowering *>(
411 MF.getSubtarget().getFrameLowering());
412}
413
414
415} // namespace llvm
416