1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
12
13static const MVT::SimpleValueType WebAssemblyVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::f64, MVT::Other,
18 /* 8 */ MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
19 /* 16 */ MVT::funcref, MVT::Other,
20 /* 18 */ MVT::externref, MVT::Other,
21 /* 20 */ MVT::exnref, MVT::Other,
22};
23static constexpr char WebAssemblySubRegIndexStrings[] = {
24 /* dummy */ 0
25};
26
27
28static constexpr uint32_t WebAssemblySubRegIndexNameOffsets[] = {
29 /* dummy */ 0
30};
31
32static const TargetRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRangeTable[] = {
33 { .Offset: 65535, .Size: 65535 },
34 { .Offset: 65535, .Size: 65535 },
35};
36
37
38static const LaneBitmask WebAssemblySubRegIndexLaneMaskTable[] = {
39 LaneBitmask::getAll(),
40 };
41
42
43
44static const TargetRegisterInfo::RegClassInfo WebAssemblyRegClassInfos[] = {
45 // Mode = 0 (DefaultMode)
46 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 20 }, // EXNREF
47 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 18 }, // EXTERNREF
48 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 16 }, // FUNCREF
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 0 }, // I32
50 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 4 }, // F32
51 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 2 }, // I64
52 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 6 }, // F64
53 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*WebAssemblyVTLists+*/.VTListOffset: 8 }, // V128
54 // Mode = 1 (WASM64)
55 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 20 }, // EXNREF
56 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 18 }, // EXTERNREF
57 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 16 }, // FUNCREF
58 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 0 }, // I32
59 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 4 }, // F32
60 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 2 }, // I64
61 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 6 }, // F64
62 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*WebAssemblyVTLists+*/.VTListOffset: 8 }, // V128
63};
64static const uint32_t EXNREFSubClassMask[] = {
65 0x00000001,
66};
67
68static const uint32_t EXTERNREFSubClassMask[] = {
69 0x00000002,
70};
71
72static const uint32_t FUNCREFSubClassMask[] = {
73 0x00000004,
74};
75
76static const uint32_t I32SubClassMask[] = {
77 0x00000008,
78};
79
80static const uint32_t F32SubClassMask[] = {
81 0x00000010,
82};
83
84static const uint32_t I64SubClassMask[] = {
85 0x00000020,
86};
87
88static const uint32_t F64SubClassMask[] = {
89 0x00000040,
90};
91
92static const uint32_t V128SubClassMask[] = {
93 0x00000080,
94};
95
96static const uint16_t SuperRegIdxSeqs[] = {
97 /* 0 */ 0,
98};
99
100namespace WebAssembly {
101
102// Register class instances.
103 extern const TargetRegisterClass EXNREFRegClass = {
104 .MC: &WebAssemblyMCRegisterClasses[EXNREFRegClassID],
105 .SubClassMask: EXNREFSubClassMask,
106 .SuperRegIndices: SuperRegIdxSeqs + 0,
107 .LaneMask: LaneBitmask(0x0000000000000001),
108 .AllocationPriority: 0,
109 .GlobalPriority: false,
110 .TSFlags: 0x00, /* TSFlags */
111 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
112 .CoveredBySubRegs: false, /* CoveredBySubRegs */
113 .SuperClasses: nullptr, .SuperClassesSize: 0,
114 .OrderFunc: nullptr
115 };
116
117 extern const TargetRegisterClass EXTERNREFRegClass = {
118 .MC: &WebAssemblyMCRegisterClasses[EXTERNREFRegClassID],
119 .SubClassMask: EXTERNREFSubClassMask,
120 .SuperRegIndices: SuperRegIdxSeqs + 0,
121 .LaneMask: LaneBitmask(0x0000000000000001),
122 .AllocationPriority: 0,
123 .GlobalPriority: false,
124 .TSFlags: 0x00, /* TSFlags */
125 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
126 .CoveredBySubRegs: false, /* CoveredBySubRegs */
127 .SuperClasses: nullptr, .SuperClassesSize: 0,
128 .OrderFunc: nullptr
129 };
130
131 extern const TargetRegisterClass FUNCREFRegClass = {
132 .MC: &WebAssemblyMCRegisterClasses[FUNCREFRegClassID],
133 .SubClassMask: FUNCREFSubClassMask,
134 .SuperRegIndices: SuperRegIdxSeqs + 0,
135 .LaneMask: LaneBitmask(0x0000000000000001),
136 .AllocationPriority: 0,
137 .GlobalPriority: false,
138 .TSFlags: 0x00, /* TSFlags */
139 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
140 .CoveredBySubRegs: false, /* CoveredBySubRegs */
141 .SuperClasses: nullptr, .SuperClassesSize: 0,
142 .OrderFunc: nullptr
143 };
144
145 extern const TargetRegisterClass I32RegClass = {
146 .MC: &WebAssemblyMCRegisterClasses[I32RegClassID],
147 .SubClassMask: I32SubClassMask,
148 .SuperRegIndices: SuperRegIdxSeqs + 0,
149 .LaneMask: LaneBitmask(0x0000000000000001),
150 .AllocationPriority: 0,
151 .GlobalPriority: false,
152 .TSFlags: 0x00, /* TSFlags */
153 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
154 .CoveredBySubRegs: false, /* CoveredBySubRegs */
155 .SuperClasses: nullptr, .SuperClassesSize: 0,
156 .OrderFunc: nullptr
157 };
158
159 extern const TargetRegisterClass F32RegClass = {
160 .MC: &WebAssemblyMCRegisterClasses[F32RegClassID],
161 .SubClassMask: F32SubClassMask,
162 .SuperRegIndices: SuperRegIdxSeqs + 0,
163 .LaneMask: LaneBitmask(0x0000000000000001),
164 .AllocationPriority: 0,
165 .GlobalPriority: false,
166 .TSFlags: 0x00, /* TSFlags */
167 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
168 .CoveredBySubRegs: false, /* CoveredBySubRegs */
169 .SuperClasses: nullptr, .SuperClassesSize: 0,
170 .OrderFunc: nullptr
171 };
172
173 extern const TargetRegisterClass I64RegClass = {
174 .MC: &WebAssemblyMCRegisterClasses[I64RegClassID],
175 .SubClassMask: I64SubClassMask,
176 .SuperRegIndices: SuperRegIdxSeqs + 0,
177 .LaneMask: LaneBitmask(0x0000000000000001),
178 .AllocationPriority: 0,
179 .GlobalPriority: false,
180 .TSFlags: 0x00, /* TSFlags */
181 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
182 .CoveredBySubRegs: false, /* CoveredBySubRegs */
183 .SuperClasses: nullptr, .SuperClassesSize: 0,
184 .OrderFunc: nullptr
185 };
186
187 extern const TargetRegisterClass F64RegClass = {
188 .MC: &WebAssemblyMCRegisterClasses[F64RegClassID],
189 .SubClassMask: F64SubClassMask,
190 .SuperRegIndices: SuperRegIdxSeqs + 0,
191 .LaneMask: LaneBitmask(0x0000000000000001),
192 .AllocationPriority: 0,
193 .GlobalPriority: false,
194 .TSFlags: 0x00, /* TSFlags */
195 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
196 .CoveredBySubRegs: false, /* CoveredBySubRegs */
197 .SuperClasses: nullptr, .SuperClassesSize: 0,
198 .OrderFunc: nullptr
199 };
200
201 extern const TargetRegisterClass V128RegClass = {
202 .MC: &WebAssemblyMCRegisterClasses[V128RegClassID],
203 .SubClassMask: V128SubClassMask,
204 .SuperRegIndices: SuperRegIdxSeqs + 0,
205 .LaneMask: LaneBitmask(0x0000000000000001),
206 .AllocationPriority: 0,
207 .GlobalPriority: false,
208 .TSFlags: 0x00, /* TSFlags */
209 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
210 .CoveredBySubRegs: false, /* CoveredBySubRegs */
211 .SuperClasses: nullptr, .SuperClassesSize: 0,
212 .OrderFunc: nullptr
213 };
214
215
216} // namespace WebAssembly
217static const TargetRegisterClass *const WebAssemblyRegisterClasses[] = {
218 &WebAssembly::EXNREFRegClass,
219 &WebAssembly::EXTERNREFRegClass,
220 &WebAssembly::FUNCREFRegClass,
221 &WebAssembly::I32RegClass,
222 &WebAssembly::F32RegClass,
223 &WebAssembly::I64RegClass,
224 &WebAssembly::F64RegClass,
225 &WebAssembly::V128RegClass,
226 };
227
228static const uint8_t WebAssemblyCostPerUseTable[] = {
2290, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
230
231
232static const bool WebAssemblyInAllocatableClassTable[] = {
233false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
234
235
236static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
237.CostPerUse: WebAssemblyCostPerUseTable, .NumCosts: 1, .InAllocatableClass: WebAssemblyInAllocatableClassTable};
238
239/// Get the weight in units of pressure for this register class.
240const RegClassWeight &WebAssemblyGenRegisterInfo::
241getRegClassWeight(const TargetRegisterClass *RC) const {
242 static const RegClassWeight RCWeightTable[] = {
243 {.RegWeight: 1, .WeightLimit: 1}, // EXNREF
244 {.RegWeight: 1, .WeightLimit: 1}, // EXTERNREF
245 {.RegWeight: 1, .WeightLimit: 1}, // FUNCREF
246 {.RegWeight: 1, .WeightLimit: 3}, // I32
247 {.RegWeight: 1, .WeightLimit: 1}, // F32
248 {.RegWeight: 1, .WeightLimit: 3}, // I64
249 {.RegWeight: 1, .WeightLimit: 1}, // F64
250 {.RegWeight: 1, .WeightLimit: 1}, // V128
251 };
252 return RCWeightTable[RC->getID()];
253}
254
255/// Get the weight in units of pressure for this register unit.
256unsigned WebAssemblyGenRegisterInfo::
257getRegUnitWeight(MCRegUnit RegUnit) const {
258 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
259 // All register units have unit weight.
260 return 1;
261}
262
263
264// Get the number of dimensions of register pressure.
265unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
266 return 8;
267}
268
269// Get the name of this register unit pressure set.
270const char *WebAssemblyGenRegisterInfo::
271getRegPressureSetName(unsigned Idx) const {
272 static const char *PressureNameTable[] = {
273 "EXNREF",
274 "EXTERNREF",
275 "FUNCREF",
276 "F32",
277 "F64",
278 "V128",
279 "I32",
280 "I64",
281 };
282 return PressureNameTable[Idx];
283}
284
285// Get the register unit pressure limit for this dimension.
286// This limit must be adjusted dynamically for reserved registers.
287unsigned WebAssemblyGenRegisterInfo::
288getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
289 static const uint8_t PressureLimitTable[] = {
290 1, // 0: EXNREF
291 1, // 1: EXTERNREF
292 1, // 2: FUNCREF
293 1, // 3: F32
294 1, // 4: F64
295 1, // 5: V128
296 3, // 6: I32
297 3, // 7: I64
298 };
299 return PressureLimitTable[Idx];
300}
301
302/// Table of pressure sets per register class or unit.
303static const int RCSetsTable[] = {
304 /* 0 */ 0, -1,
305 /* 2 */ 1, -1,
306 /* 4 */ 2, -1,
307 /* 6 */ 3, -1,
308 /* 8 */ 4, -1,
309 /* 10 */ 5, -1,
310 /* 12 */ 6, -1,
311 /* 14 */ 7, -1,
312};
313
314/// Get the dimensions of register pressure impacted by this register class.
315/// Returns a -1 terminated array of pressure set IDs
316const int *WebAssemblyGenRegisterInfo::
317getRegClassPressureSets(const TargetRegisterClass *RC) const {
318 static const uint8_t RCSetStartTable[] = {
319 0,2,4,12,6,14,8,10,};
320 return &RCSetsTable[RCSetStartTable[RC->getID()]];
321}
322
323/// Get the dimensions of register pressure impacted by this register unit.
324/// Returns a -1 terminated array of pressure set IDs
325const int *WebAssemblyGenRegisterInfo::
326getRegUnitPressureSets(MCRegUnit RegUnit) const {
327 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
328 static const uint8_t RUSetStartTable[] = {
329 1,1,0,2,12,14,4,12,14,6,8,12,14,10,};
330 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
331}
332
333extern const MCRegisterDesc WebAssemblyRegDesc[];
334extern const int16_t WebAssemblyRegDiffLists[];
335extern const LaneBitmask WebAssemblyLaneMaskLists[];
336extern const char WebAssemblyRegStrings[];
337extern const char WebAssemblyRegClassStrings[];
338extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
339extern const uint16_t WebAssemblySubRegIdxLists[];
340extern const uint16_t WebAssemblyRegEncodingTable[];
341
342WebAssemblyGenRegisterInfo::
343WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
344 unsigned PC, unsigned HwMode)
345 : TargetRegisterInfo(&WebAssemblyRegInfoDesc, WebAssemblyRegisterClasses,
346 WebAssemblySubRegIndexStrings, WebAssemblySubRegIndexNameOffsets,
347 WebAssemblySubRegIdxRangeTable, WebAssemblySubRegIndexLaneMaskTable,
348
349 LaneBitmask(0xFFFFFFFFFFFFFFFF), WebAssemblyRegClassInfos, WebAssemblyVTLists, HwMode) {
350 InitMCRegisterInfo(D: WebAssemblyRegDesc, NR: 15, RA, PC,
351 C: WebAssemblyMCRegisterClasses, NC: 8, RURoots: WebAssemblyRegUnitRoots, NRU: 14, DL: WebAssemblyRegDiffLists,
352 RUMS: WebAssemblyLaneMaskLists, Strings: WebAssemblyRegStrings, ClassStrings: WebAssemblyRegClassStrings, SubIndices: WebAssemblySubRegIdxLists, NumIndices: 1,
353 RET: WebAssemblyRegEncodingTable, RUI: nullptr);
354
355}
356
357
358
359ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
360 return {};
361}
362
363bool WebAssemblyGenRegisterInfo::
364isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
365 return
366 false;
367}
368
369bool WebAssemblyGenRegisterInfo::
370isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
371 return
372 false;
373}
374
375bool WebAssemblyGenRegisterInfo::
376isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
377 return
378 false;
379}
380
381bool WebAssemblyGenRegisterInfo::
382isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
383 return
384 false;
385}
386
387bool WebAssemblyGenRegisterInfo::
388isConstantPhysReg(MCRegister PhysReg) const {
389 return
390 false;
391}
392
393ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
394 return {};
395}
396
397const WebAssemblyFrameLowering *
398WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
399 return static_cast<const WebAssemblyFrameLowering *>(
400 MF.getSubtarget().getFrameLowering());
401}
402
403
404} // namespace llvm
405