1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::f64, MVT::Other,
18 /* 8 */ MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
19 /* 16 */ MVT::funcref, MVT::Other,
20 /* 18 */ MVT::externref, MVT::Other,
21 /* 20 */ MVT::exnref, MVT::Other,
22};
23
24static const char *SubRegIndexNameTable[] = { "" };
25
26static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
27 { .Offset: 65535, .Size: 65535 },
28 { .Offset: 65535, .Size: 65535 },
29};
30
31
32static const LaneBitmask SubRegIndexLaneMaskTable[] = {
33 LaneBitmask::getAll(),
34 };
35
36
37
38static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
39 // Mode = 0 (Default)
40 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 20 }, // EXNREF
41 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 18 }, // EXTERNREF
42 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 16 }, // FUNCREF
43 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // I32
44 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // F32
45 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // I64
46 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // F64
47 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 8 }, // V128
48 // Mode = 1 (WASM64)
49 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 20 }, // EXNREF
50 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 18 }, // EXTERNREF
51 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*VTLists+*/.VTListOffset: 16 }, // FUNCREF
52 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // I32
53 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 4 }, // F32
54 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // I64
55 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 6 }, // F64
56 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 8 }, // V128
57};
58static const uint32_t EXNREFSubClassMask[] = {
59 0x00000001,
60};
61
62static const uint32_t EXTERNREFSubClassMask[] = {
63 0x00000002,
64};
65
66static const uint32_t FUNCREFSubClassMask[] = {
67 0x00000004,
68};
69
70static const uint32_t I32SubClassMask[] = {
71 0x00000008,
72};
73
74static const uint32_t F32SubClassMask[] = {
75 0x00000010,
76};
77
78static const uint32_t I64SubClassMask[] = {
79 0x00000020,
80};
81
82static const uint32_t F64SubClassMask[] = {
83 0x00000040,
84};
85
86static const uint32_t V128SubClassMask[] = {
87 0x00000080,
88};
89
90static const uint16_t SuperRegIdxSeqs[] = {
91 /* 0 */ 0,
92};
93
94
95namespace WebAssembly { // Register class instances
96 extern const TargetRegisterClass EXNREFRegClass = {
97 .MC: &WebAssemblyMCRegisterClasses[EXNREFRegClassID],
98 .SubClassMask: EXNREFSubClassMask,
99 .SuperRegIndices: SuperRegIdxSeqs + 0,
100 .LaneMask: LaneBitmask(0x0000000000000001),
101 .AllocationPriority: 0,
102 .GlobalPriority: false,
103 .TSFlags: 0x00, /* TSFlags */
104 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
105 .CoveredBySubRegs: false, /* CoveredBySubRegs */
106 .SuperClasses: nullptr, .SuperClassesSize: 0,
107 .OrderFunc: nullptr
108 };
109
110 extern const TargetRegisterClass EXTERNREFRegClass = {
111 .MC: &WebAssemblyMCRegisterClasses[EXTERNREFRegClassID],
112 .SubClassMask: EXTERNREFSubClassMask,
113 .SuperRegIndices: SuperRegIdxSeqs + 0,
114 .LaneMask: LaneBitmask(0x0000000000000001),
115 .AllocationPriority: 0,
116 .GlobalPriority: false,
117 .TSFlags: 0x00, /* TSFlags */
118 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
119 .CoveredBySubRegs: false, /* CoveredBySubRegs */
120 .SuperClasses: nullptr, .SuperClassesSize: 0,
121 .OrderFunc: nullptr
122 };
123
124 extern const TargetRegisterClass FUNCREFRegClass = {
125 .MC: &WebAssemblyMCRegisterClasses[FUNCREFRegClassID],
126 .SubClassMask: FUNCREFSubClassMask,
127 .SuperRegIndices: SuperRegIdxSeqs + 0,
128 .LaneMask: LaneBitmask(0x0000000000000001),
129 .AllocationPriority: 0,
130 .GlobalPriority: false,
131 .TSFlags: 0x00, /* TSFlags */
132 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
133 .CoveredBySubRegs: false, /* CoveredBySubRegs */
134 .SuperClasses: nullptr, .SuperClassesSize: 0,
135 .OrderFunc: nullptr
136 };
137
138 extern const TargetRegisterClass I32RegClass = {
139 .MC: &WebAssemblyMCRegisterClasses[I32RegClassID],
140 .SubClassMask: I32SubClassMask,
141 .SuperRegIndices: SuperRegIdxSeqs + 0,
142 .LaneMask: LaneBitmask(0x0000000000000001),
143 .AllocationPriority: 0,
144 .GlobalPriority: false,
145 .TSFlags: 0x00, /* TSFlags */
146 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
147 .CoveredBySubRegs: false, /* CoveredBySubRegs */
148 .SuperClasses: nullptr, .SuperClassesSize: 0,
149 .OrderFunc: nullptr
150 };
151
152 extern const TargetRegisterClass F32RegClass = {
153 .MC: &WebAssemblyMCRegisterClasses[F32RegClassID],
154 .SubClassMask: F32SubClassMask,
155 .SuperRegIndices: SuperRegIdxSeqs + 0,
156 .LaneMask: LaneBitmask(0x0000000000000001),
157 .AllocationPriority: 0,
158 .GlobalPriority: false,
159 .TSFlags: 0x00, /* TSFlags */
160 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
161 .CoveredBySubRegs: false, /* CoveredBySubRegs */
162 .SuperClasses: nullptr, .SuperClassesSize: 0,
163 .OrderFunc: nullptr
164 };
165
166 extern const TargetRegisterClass I64RegClass = {
167 .MC: &WebAssemblyMCRegisterClasses[I64RegClassID],
168 .SubClassMask: I64SubClassMask,
169 .SuperRegIndices: SuperRegIdxSeqs + 0,
170 .LaneMask: LaneBitmask(0x0000000000000001),
171 .AllocationPriority: 0,
172 .GlobalPriority: false,
173 .TSFlags: 0x00, /* TSFlags */
174 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
175 .CoveredBySubRegs: false, /* CoveredBySubRegs */
176 .SuperClasses: nullptr, .SuperClassesSize: 0,
177 .OrderFunc: nullptr
178 };
179
180 extern const TargetRegisterClass F64RegClass = {
181 .MC: &WebAssemblyMCRegisterClasses[F64RegClassID],
182 .SubClassMask: F64SubClassMask,
183 .SuperRegIndices: SuperRegIdxSeqs + 0,
184 .LaneMask: LaneBitmask(0x0000000000000001),
185 .AllocationPriority: 0,
186 .GlobalPriority: false,
187 .TSFlags: 0x00, /* TSFlags */
188 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
189 .CoveredBySubRegs: false, /* CoveredBySubRegs */
190 .SuperClasses: nullptr, .SuperClassesSize: 0,
191 .OrderFunc: nullptr
192 };
193
194 extern const TargetRegisterClass V128RegClass = {
195 .MC: &WebAssemblyMCRegisterClasses[V128RegClassID],
196 .SubClassMask: V128SubClassMask,
197 .SuperRegIndices: SuperRegIdxSeqs + 0,
198 .LaneMask: LaneBitmask(0x0000000000000001),
199 .AllocationPriority: 0,
200 .GlobalPriority: false,
201 .TSFlags: 0x00, /* TSFlags */
202 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
203 .CoveredBySubRegs: false, /* CoveredBySubRegs */
204 .SuperClasses: nullptr, .SuperClassesSize: 0,
205 .OrderFunc: nullptr
206 };
207
208} // end namespace WebAssembly
209
210namespace {
211 const TargetRegisterClass *const RegisterClasses[] = {
212 &WebAssembly::EXNREFRegClass,
213 &WebAssembly::EXTERNREFRegClass,
214 &WebAssembly::FUNCREFRegClass,
215 &WebAssembly::I32RegClass,
216 &WebAssembly::F32RegClass,
217 &WebAssembly::I64RegClass,
218 &WebAssembly::F64RegClass,
219 &WebAssembly::V128RegClass,
220 };
221} // end anonymous namespace
222
223static const uint8_t CostPerUseTable[] = {
2240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
225
226
227static const bool InAllocatableClassTable[] = {
228false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
229
230
231static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
232.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
233
234/// Get the weight in units of pressure for this register class.
235const RegClassWeight &WebAssemblyGenRegisterInfo::
236getRegClassWeight(const TargetRegisterClass *RC) const {
237 static const RegClassWeight RCWeightTable[] = {
238 {.RegWeight: 1, .WeightLimit: 1}, // EXNREF
239 {.RegWeight: 1, .WeightLimit: 1}, // EXTERNREF
240 {.RegWeight: 1, .WeightLimit: 1}, // FUNCREF
241 {.RegWeight: 1, .WeightLimit: 3}, // I32
242 {.RegWeight: 1, .WeightLimit: 1}, // F32
243 {.RegWeight: 1, .WeightLimit: 3}, // I64
244 {.RegWeight: 1, .WeightLimit: 1}, // F64
245 {.RegWeight: 1, .WeightLimit: 1}, // V128
246 };
247 return RCWeightTable[RC->getID()];
248}
249
250/// Get the weight in units of pressure for this register unit.
251unsigned WebAssemblyGenRegisterInfo::
252getRegUnitWeight(MCRegUnit RegUnit) const {
253 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
254 // All register units have unit weight.
255 return 1;
256}
257
258
259// Get the number of dimensions of register pressure.
260unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
261 return 8;
262}
263
264// Get the name of this register unit pressure set.
265const char *WebAssemblyGenRegisterInfo::
266getRegPressureSetName(unsigned Idx) const {
267 static const char *PressureNameTable[] = {
268 "EXNREF",
269 "EXTERNREF",
270 "FUNCREF",
271 "F32",
272 "F64",
273 "V128",
274 "I32",
275 "I64",
276 };
277 return PressureNameTable[Idx];
278}
279
280// Get the register unit pressure limit for this dimension.
281// This limit must be adjusted dynamically for reserved registers.
282unsigned WebAssemblyGenRegisterInfo::
283getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
284 static const uint8_t PressureLimitTable[] = {
285 1, // 0: EXNREF
286 1, // 1: EXTERNREF
287 1, // 2: FUNCREF
288 1, // 3: F32
289 1, // 4: F64
290 1, // 5: V128
291 3, // 6: I32
292 3, // 7: I64
293 };
294 return PressureLimitTable[Idx];
295}
296
297/// Table of pressure sets per register class or unit.
298static const int RCSetsTable[] = {
299 /* 0 */ 0, -1,
300 /* 2 */ 1, -1,
301 /* 4 */ 2, -1,
302 /* 6 */ 3, -1,
303 /* 8 */ 4, -1,
304 /* 10 */ 5, -1,
305 /* 12 */ 6, -1,
306 /* 14 */ 7, -1,
307};
308
309/// Get the dimensions of register pressure impacted by this register class.
310/// Returns a -1 terminated array of pressure set IDs
311const int *WebAssemblyGenRegisterInfo::
312getRegClassPressureSets(const TargetRegisterClass *RC) const {
313 static const uint8_t RCSetStartTable[] = {
314 0,2,4,12,6,14,8,10,};
315 return &RCSetsTable[RCSetStartTable[RC->getID()]];
316}
317
318/// Get the dimensions of register pressure impacted by this register unit.
319/// Returns a -1 terminated array of pressure set IDs
320const int *WebAssemblyGenRegisterInfo::
321getRegUnitPressureSets(MCRegUnit RegUnit) const {
322 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
323 static const uint8_t RUSetStartTable[] = {
324 1,1,0,2,12,14,4,12,14,6,8,12,14,10,};
325 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
326}
327
328extern const MCRegisterDesc WebAssemblyRegDesc[];
329extern const int16_t WebAssemblyRegDiffLists[];
330extern const LaneBitmask WebAssemblyLaneMaskLists[];
331extern const char WebAssemblyRegStrings[];
332extern const char WebAssemblyRegClassStrings[];
333extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
334extern const uint16_t WebAssemblySubRegIdxLists[];
335extern const uint16_t WebAssemblyRegEncodingTable[];
336WebAssemblyGenRegisterInfo::
337WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
338 unsigned PC, unsigned HwMode)
339 : TargetRegisterInfo(&WebAssemblyRegInfoDesc, RegisterClasses, RegisterClasses+8,
340 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
341 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
342 InitMCRegisterInfo(D: WebAssemblyRegDesc, NR: 15, RA, PC,
343 C: WebAssemblyMCRegisterClasses, NC: 8,
344 RURoots: WebAssemblyRegUnitRoots,
345 NRU: 14,
346 DL: WebAssemblyRegDiffLists,
347 RUMS: WebAssemblyLaneMaskLists,
348 Strings: WebAssemblyRegStrings,
349 ClassStrings: WebAssemblyRegClassStrings,
350 SubIndices: WebAssemblySubRegIdxLists,
351 NumIndices: 1,
352 RET: WebAssemblyRegEncodingTable);
353
354}
355
356
357
358ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
359 return {};
360}
361
362bool WebAssemblyGenRegisterInfo::
363isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
364 return
365 false;
366}
367
368bool WebAssemblyGenRegisterInfo::
369isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
370 return
371 false;
372}
373
374bool WebAssemblyGenRegisterInfo::
375isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
376 return
377 false;
378}
379
380bool WebAssemblyGenRegisterInfo::
381isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
382 return
383 false;
384}
385
386bool WebAssemblyGenRegisterInfo::
387isConstantPhysReg(MCRegister PhysReg) const {
388 return
389 false;
390}
391
392ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
393 return {};
394}
395
396const WebAssemblyFrameLowering *
397WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
398 return static_cast<const WebAssemblyFrameLowering *>(
399 MF.getSubtarget().getFrameLowering());
400}
401
402} // end namespace llvm
403
404