1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<8, 12, 13, 8, 1, 0> WebAssemblyMCRegisterClassStorage;
12
13static const MVT::SimpleValueType WebAssemblyVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16 /* 4 */ MVT::f32, MVT::Other,
17 /* 6 */ MVT::f64, MVT::Other,
18 /* 8 */ MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
19 /* 16 */ MVT::funcref, MVT::Other,
20 /* 18 */ MVT::externref, MVT::Other,
21 /* 20 */ MVT::exnref, MVT::Other,
22};
23static constexpr char WebAssemblySubRegIndexStrings[] = {
24 /* dummy */ 0
25};
26
27
28static constexpr uint32_t WebAssemblySubRegIndexNameOffsets[] = {
29 /* dummy */ 0
30};
31
32static const TargetRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRangeTable[] = {
33 { .Offset: 4294967295, .Size: 4294967295 },
34 { .Offset: 4294967295, .Size: 4294967295 },
35};
36
37
38static const LaneBitmask WebAssemblySubRegIndexLaneMaskTable[] = {
39 LaneBitmask::getAll(),
40 };
41
42
43
44static const TargetRegisterInfo::RegClassInfo WebAssemblyRegClassInfos[] = {
45 // Mode = 0 (DefaultMode)
46 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 20 }, // EXNREF
47 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 18 }, // EXTERNREF
48 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 16 }, // FUNCREF
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 0 }, // I32
50 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 4 }, // F32
51 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 2 }, // I64
52 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 6 }, // F64
53 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*WebAssemblyVTLists+*/.VTListOffset: 8 }, // V128
54 // Mode = 1 (WASM64)
55 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 20 }, // EXNREF
56 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 18 }, // EXTERNREF
57 { .RegSize: 0, .SpillSize: 0, .SpillAlignment: 0, /*WebAssemblyVTLists+*/.VTListOffset: 16 }, // FUNCREF
58 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 0 }, // I32
59 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*WebAssemblyVTLists+*/.VTListOffset: 4 }, // F32
60 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 2 }, // I64
61 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*WebAssemblyVTLists+*/.VTListOffset: 6 }, // F64
62 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*WebAssemblyVTLists+*/.VTListOffset: 8 }, // V128
63};
64
65static const uint8_t WebAssemblyCostPerUseTable[] = {
660, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
67
68
69static const bool WebAssemblyInAllocatableClassTable[] = {
70false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
71
72
73static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
74.CostPerUse: WebAssemblyCostPerUseTable, .NumCosts: 1, .InAllocatableClass: WebAssemblyInAllocatableClassTable};
75
76/// Get the weight in units of pressure for this register class.
77const RegClassWeight &WebAssemblyGenRegisterInfo::
78getRegClassWeight(const TargetRegisterClass *RC) const {
79 static const RegClassWeight RCWeightTable[] = {
80 {.RegWeight: 1, .WeightLimit: 1}, // EXNREF
81 {.RegWeight: 1, .WeightLimit: 1}, // EXTERNREF
82 {.RegWeight: 1, .WeightLimit: 1}, // FUNCREF
83 {.RegWeight: 1, .WeightLimit: 3}, // I32
84 {.RegWeight: 1, .WeightLimit: 1}, // F32
85 {.RegWeight: 1, .WeightLimit: 3}, // I64
86 {.RegWeight: 1, .WeightLimit: 1}, // F64
87 {.RegWeight: 1, .WeightLimit: 1}, // V128
88 };
89 return RCWeightTable[RC->getID()];
90}
91
92/// Get the weight in units of pressure for this register unit.
93unsigned WebAssemblyGenRegisterInfo::
94getRegUnitWeight(MCRegUnit RegUnit) const {
95 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
96 // All register units have unit weight.
97 return 1;
98}
99
100
101// Get the number of dimensions of register pressure.
102unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
103 return 8;
104}
105
106// Get the name of this register unit pressure set.
107const char *WebAssemblyGenRegisterInfo::
108getRegPressureSetName(unsigned Idx) const {
109 static const char *PressureNameTable[] = {
110 "EXNREF",
111 "EXTERNREF",
112 "FUNCREF",
113 "F32",
114 "F64",
115 "V128",
116 "I32",
117 "I64",
118 };
119 return PressureNameTable[Idx];
120}
121
122// Get the register unit pressure limit for this dimension.
123// This limit must be adjusted dynamically for reserved registers.
124unsigned WebAssemblyGenRegisterInfo::
125getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
126 static const uint8_t PressureLimitTable[] = {
127 1, // 0: EXNREF
128 1, // 1: EXTERNREF
129 1, // 2: FUNCREF
130 1, // 3: F32
131 1, // 4: F64
132 1, // 5: V128
133 3, // 6: I32
134 3, // 7: I64
135 };
136 return PressureLimitTable[Idx];
137}
138
139/// Table of pressure sets per register class or unit.
140static const int RCSetsTable[] = {
141 /* 0 */ 0, -1,
142 /* 2 */ 1, -1,
143 /* 4 */ 2, -1,
144 /* 6 */ 3, -1,
145 /* 8 */ 4, -1,
146 /* 10 */ 5, -1,
147 /* 12 */ 6, -1,
148 /* 14 */ 7, -1,
149};
150
151/// Get the dimensions of register pressure impacted by this register class.
152/// Returns a -1 terminated array of pressure set IDs
153const int *WebAssemblyGenRegisterInfo::
154getRegClassPressureSets(const TargetRegisterClass *RC) const {
155 static const uint8_t RCSetStartTable[] = {
156 0,2,4,12,6,14,8,10,};
157 return &RCSetsTable[RCSetStartTable[RC->getID()]];
158}
159
160/// Get the dimensions of register pressure impacted by this register unit.
161/// Returns a -1 terminated array of pressure set IDs
162const int *WebAssemblyGenRegisterInfo::
163getRegUnitPressureSets(MCRegUnit RegUnit) const {
164 assert(static_cast<unsigned>(RegUnit) < 14 && "invalid register unit");
165 static const uint8_t RUSetStartTable[] = {
166 1,1,0,2,12,14,4,12,14,6,8,12,14,10,};
167 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
168}
169
170
171// Register to minimal register class mapping
172
173const TargetRegisterClass *WebAssemblyGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
174 static const uint16_t InvalidRegClassID = UINT16_MAX;
175
176 static const uint16_t Mapping[15] = {
177 InvalidRegClassID, // NoRegister
178 InvalidRegClassID, // ARGUMENTS
179 InvalidRegClassID, // VALUE_STACK
180 WebAssembly::EXNREFRegClassID, // EXNREF_0
181 WebAssembly::EXTERNREFRegClassID, // EXTERNREF_0
182 WebAssembly::I32RegClassID, // FP32
183 WebAssembly::I64RegClassID, // FP64
184 WebAssembly::FUNCREFRegClassID, // FUNCREF_0
185 WebAssembly::I32RegClassID, // SP32
186 WebAssembly::I64RegClassID, // SP64
187 WebAssembly::F32RegClassID, // F32_0
188 WebAssembly::F64RegClassID, // F64_0
189 WebAssembly::I32RegClassID, // I32_0
190 WebAssembly::I64RegClassID, // I64_0
191 WebAssembly::V128RegClassID, // V128_0
192 };
193
194 assert(Reg < ArrayRef(Mapping).size());
195 unsigned RCID = Mapping[Reg.id()];
196 if (RCID == InvalidRegClassID)
197 return nullptr;
198 return &WebAssemblyMCRegisterClassStorage.Classes[RCID];
199}
200extern const MCRegisterDesc WebAssemblyRegDesc[];
201extern const int16_t WebAssemblyRegDiffLists[];
202extern const LaneBitmask WebAssemblyLaneMaskLists[];
203extern const char WebAssemblyRegStrings[];
204extern const char WebAssemblyRegClassStrings[];
205extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
206extern const uint16_t WebAssemblySubRegIdxLists[];
207extern const uint16_t WebAssemblyRegEncodingTable[];
208
209WebAssemblyGenRegisterInfo::
210WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
211 unsigned PC, unsigned HwMode)
212 : TargetRegisterInfo(&WebAssemblyRegInfoDesc,
213 WebAssemblySubRegIndexStrings, WebAssemblySubRegIndexNameOffsets,
214 WebAssemblySubRegIdxRangeTable, WebAssemblySubRegIndexLaneMaskTable,
215
216 LaneBitmask(0xFFFFFFFFFFFFFFFF), WebAssemblyRegClassInfos, WebAssemblyVTLists, HwMode) {
217 InitMCRegisterInfo(D: WebAssemblyRegDesc, NR: 15, RA, PC,
218 C: &getWebAssemblyMCRegisterClass(RC: 0), NC: 8, RURoots: WebAssemblyRegUnitRoots, NRU: 14, DL: WebAssemblyRegDiffLists,
219 RUMS: WebAssemblyLaneMaskLists, Strings: WebAssemblyRegStrings, ClassStrings: WebAssemblyRegClassStrings, SubIndices: WebAssemblySubRegIdxLists, NumIndices: 1,
220 RET: WebAssemblyRegEncodingTable, RUI: nullptr);
221
222}
223
224
225
226ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
227 return {};
228}
229
230bool WebAssemblyGenRegisterInfo::
231isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
232 return
233 false;
234}
235
236bool WebAssemblyGenRegisterInfo::
237isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
238 return
239 false;
240}
241
242bool WebAssemblyGenRegisterInfo::
243isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
244 return
245 false;
246}
247
248bool WebAssemblyGenRegisterInfo::
249isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
250 return
251 false;
252}
253
254bool WebAssemblyGenRegisterInfo::
255isConstantPhysReg(MCRegister PhysReg) const {
256 return
257 false;
258}
259
260ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
261 return {};
262}
263
264const WebAssemblyFrameLowering *
265WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
266 return static_cast<const WebAssemblyFrameLowering *>(
267 MF.getSubtarget().getFrameLowering());
268}
269
270
271} // namespace llvm
272