1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::X86 {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 GPRRegBankID = 0,
17 PSRRegBankID = 1,
18 VECRRegBankID = 2,
19 NumRegisterBanks,
20};
21
22} // namespace llvm::X86
23
24#endif // GET_REGBANK_DECLARATIONS
25
26#ifdef GET_TARGET_REGBANK_CLASS
27#undef GET_TARGET_REGBANK_CLASS
28
29private:
30 static const RegisterBank *RegBanks[];
31 static const unsigned Sizes[];
32
33public:
34 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
35protected:
36 X86GenRegisterBankInfo(unsigned HwMode = 0);
37
38
39#endif // GET_TARGET_REGBANK_CLASS
40
41#ifdef GET_TARGET_REGBANK_IMPL
42#undef GET_TARGET_REGBANK_IMPL
43
44namespace llvm {
45
46namespace X86 {
47
48const uint32_t GPRRegBankCoverageData[] = {
49 // 0-31
50 (1u << (X86::GR8RegClassID - 0)) |
51 (1u << (X86::GR16RegClassID - 0)) |
52 (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
53 (1u << (X86::GR8_NOREX2RegClassID - 0)) |
54 (1u << (X86::GR16_NOREX2RegClassID - 0)) |
55 (1u << (X86::GR8_NOREXRegClassID - 0)) |
56 (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
57 (1u << (X86::GR8_ABCD_LRegClassID - 0)) |
58 (1u << (X86::GR16_NOREXRegClassID - 0)) |
59 (1u << (X86::GR16_ABCDRegClassID - 0)) |
60 0,
61 // 32-63
62 (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 32)) |
63 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 32)) |
64 (1u << (X86::GR32RegClassID - 32)) |
65 (1u << (X86::GR32_NOSPRegClassID - 32)) |
66 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID - 32)) |
67 (1u << (X86::GR32_NOREX2RegClassID - 32)) |
68 (1u << (X86::GR32_NOREX2_NOSPRegClassID - 32)) |
69 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) |
70 (1u << (X86::GR32_NOREXRegClassID - 32)) |
71 (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) |
72 (1u << (X86::GR32_ABCDRegClassID - 32)) |
73 (1u << (X86::GR32_TCRegClassID - 32)) |
74 (1u << (X86::GR32_ABCD_and_GR32_TCRegClassID - 32)) |
75 (1u << (X86::GR32_ADRegClassID - 32)) |
76 (1u << (X86::GR32_ArgRefRegClassID - 32)) |
77 (1u << (X86::GR32_DCRegClassID - 32)) |
78 (1u << (X86::GR32_AD_and_GR32_ArgRefRegClassID - 32)) |
79 (1u << (X86::GR32_CBRegClassID - 32)) |
80 (1u << (X86::GR32_SIDIRegClassID - 32)) |
81 (1u << (X86::GR32_BSIRegClassID - 32)) |
82 (1u << (X86::GR32_DIBPRegClassID - 32)) |
83 (1u << (X86::GR32_ABCD_and_GR32_BSIRegClassID - 32)) |
84 (1u << (X86::GR32_BPSPRegClassID - 32)) |
85 0,
86 // 64-95
87 (1u << (X86::GR64RegClassID - 64)) |
88 (1u << (X86::GR64_with_sub_8bitRegClassID - 64)) |
89 (1u << (X86::GR64_NOSPRegClassID - 64)) |
90 (1u << (X86::GR64_NOREX2_NOSPRegClassID - 64)) |
91 (1u << (X86::GR64PLTSafeRegClassID - 64)) |
92 (1u << (X86::GR64PLTSafe_and_GR64_TCRegClassID - 64)) |
93 (1u << (X86::GR32_ArgRef_and_GR32_CBRegClassID - 64)) |
94 (1u << (X86::GR32_BSI_and_GR32_SIDIRegClassID - 64)) |
95 (1u << (X86::GR32_DIBP_and_GR32_SIDIRegClassID - 64)) |
96 (1u << (X86::GR64_NOREX_NOSPRegClassID - 64)) |
97 (1u << (X86::GR32_BPSP_and_GR32_DIBPRegClassID - 64)) |
98 (1u << (X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID - 64)) |
99 (1u << (X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID - 64)) |
100 (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID - 64)) |
101 (1u << (X86::GR64_TC_with_sub_8bitRegClassID - 64)) |
102 (1u << (X86::GR32_BPSP_and_GR32_TCRegClassID - 64)) |
103 (1u << (X86::GR64_TCW64_with_sub_8bitRegClassID - 64)) |
104 (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) |
105 (1u << (X86::GR64_NOREX2RegClassID - 64)) |
106 (1u << (X86::GR64_TCRegClassID - 64)) |
107 (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 64)) |
108 (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 64)) |
109 (1u << (X86::GR64_NOREXRegClassID - 64)) |
110 (1u << (X86::GR64_TCW64RegClassID - 64)) |
111 0,
112 // 96-127
113 (1u << (X86::GR64PLTSafe_and_GR64_TCW64RegClassID - 96)) |
114 (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID - 96)) |
115 (1u << (X86::GR64_ADRegClassID - 96)) |
116 (1u << (X86::GR64_ARegClassID - 96)) |
117 (1u << (X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID - 96)) |
118 (1u << (X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID - 96)) |
119 (1u << (X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID - 96)) |
120 (1u << (X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID - 96)) |
121 (1u << (X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID - 96)) |
122 (1u << (X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID - 96)) |
123 (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID - 96)) |
124 (1u << (X86::GR64_ABCDRegClassID - 96)) |
125 (1u << (X86::GR64_with_sub_32bit_in_GR32_CBRegClassID - 96)) |
126 (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID - 96)) |
127 (1u << (X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID - 96)) |
128 (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID - 96)) |
129 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID - 96)) |
130 (1u << (X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID - 96)) |
131 (1u << (X86::GR64_ArgRef_and_GR64_TCRegClassID - 96)) |
132 (1u << (X86::GR64_ArgRefRegClassID - 96)) |
133 (1u << (X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID - 96)) |
134 (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 96)) |
135 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID - 96)) |
136 (1u << (X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 96)) |
137 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID - 96)) |
138 (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 96)) |
139 (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 96)) |
140 (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 96)) |
141 0,
142 // 128-159
143 0,
144};
145const uint32_t PSRRegBankCoverageData[] = {
146 // 0-31
147 0,
148 // 32-63
149 (1u << (X86::RFP32RegClassID - 32)) |
150 0,
151 // 64-95
152 (1u << (X86::RFP64RegClassID - 64)) |
153 0,
154 // 96-127
155 (1u << (X86::RFP80RegClassID - 96)) |
156 0,
157 // 128-159
158 0,
159};
160const uint32_t VECRRegBankCoverageData[] = {
161 // 0-31
162 (1u << (X86::FR16XRegClassID - 0)) |
163 (1u << (X86::FR16RegClassID - 0)) |
164 0,
165 // 32-63
166 (1u << (X86::FR32XRegClassID - 32)) |
167 (1u << (X86::FR32RegClassID - 32)) |
168 0,
169 // 64-95
170 (1u << (X86::FR64XRegClassID - 64)) |
171 (1u << (X86::FR64RegClassID - 64)) |
172 0,
173 // 96-127
174 0,
175 // 128-159
176 (1u << (X86::VR512RegClassID - 128)) |
177 (1u << (X86::VR128XRegClassID - 128)) |
178 (1u << (X86::VR256XRegClassID - 128)) |
179 (1u << (X86::VR512_0_15RegClassID - 128)) |
180 (1u << (X86::VR128RegClassID - 128)) |
181 (1u << (X86::VR256RegClassID - 128)) |
182 0,
183};
184
185constexpr RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 135);
186constexpr RegisterBank PSRRegBank(/* ID */ X86::PSRRegBankID, /* Name */ "PSR", /* CoveredRegClasses */ PSRRegBankCoverageData, /* NumRegClasses */ 135);
187constexpr RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 135);
188
189} // namespace X86
190
191const RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
192 &X86::GPRRegBank,
193 &X86::PSRRegBank,
194 &X86::VECRRegBank,
195};
196
197const unsigned X86GenRegisterBankInfo::Sizes[] = {
198 // Mode = 0 (Default)
199 64,
200 80,
201 512,
202 // Mode = 1 (X86_64)
203 64,
204 80,
205 512,
206 // Mode = 2 (X86_64_X32)
207 64,
208 80,
209 512,
210};
211
212X86GenRegisterBankInfo::X86GenRegisterBankInfo(unsigned HwMode)
213 : RegisterBankInfo(RegBanks, X86::NumRegisterBanks, Sizes, HwMode) {
214 // Assert that RegBank indices match their ID's
215#ifndef NDEBUG
216 for (auto RB : enumerate(RegBanks))
217 assert(RB.index() == RB.value()->getID() && "Index != ID");
218#endif // NDEBUG
219}
220
221const RegisterBank &
222X86GenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
223 constexpr uint32_t InvalidRegBankID = uint32_t(X86::InvalidRegBankID) & 3;
224 static const uint32_t RegClass2RegBank[9] = {
225 (uint32_t(X86::GPRRegBankID) << 0) | // GR8RegClassID
226 (uint32_t(InvalidRegBankID) << 2) |
227 (uint32_t(X86::GPRRegBankID) << 4) | // GR8_NOREX2RegClassID
228 (uint32_t(X86::GPRRegBankID) << 6) | // GR8_NOREXRegClassID
229 (uint32_t(X86::GPRRegBankID) << 8) | // GR8_ABCD_HRegClassID
230 (uint32_t(X86::GPRRegBankID) << 10) | // GR8_ABCD_LRegClassID
231 (uint32_t(InvalidRegBankID) << 12) |
232 (uint32_t(X86::GPRRegBankID) << 14) | // GR16RegClassID
233 (uint32_t(X86::GPRRegBankID) << 16) | // GR16_NOREX2RegClassID
234 (uint32_t(X86::GPRRegBankID) << 18) | // GR16_NOREXRegClassID
235 (uint32_t(InvalidRegBankID) << 20) |
236 (uint32_t(InvalidRegBankID) << 22) |
237 (uint32_t(InvalidRegBankID) << 24) |
238 (uint32_t(InvalidRegBankID) << 26) |
239 (uint32_t(InvalidRegBankID) << 28) |
240 (uint32_t(InvalidRegBankID) << 30),
241 (uint32_t(InvalidRegBankID) << 0) |
242 (uint32_t(InvalidRegBankID) << 2) |
243 (uint32_t(InvalidRegBankID) << 4) |
244 (uint32_t(InvalidRegBankID) << 6) |
245 (uint32_t(InvalidRegBankID) << 8) |
246 (uint32_t(X86::GPRRegBankID) << 10) | // GR16_ABCDRegClassID
247 (uint32_t(InvalidRegBankID) << 12) |
248 (uint32_t(X86::VECRRegBankID) << 14) | // FR16XRegClassID
249 (uint32_t(X86::VECRRegBankID) << 16) | // FR16RegClassID
250 (uint32_t(InvalidRegBankID) << 18) |
251 (uint32_t(InvalidRegBankID) << 20) |
252 (uint32_t(InvalidRegBankID) << 22) |
253 (uint32_t(InvalidRegBankID) << 24) |
254 (uint32_t(InvalidRegBankID) << 26) |
255 (uint32_t(InvalidRegBankID) << 28) |
256 (uint32_t(X86::GPRRegBankID) << 30), // LOW32_ADDR_ACCESS_RBPRegClassID
257 (uint32_t(X86::GPRRegBankID) << 0) | // LOW32_ADDR_ACCESSRegClassID
258 (uint32_t(X86::GPRRegBankID) << 2) | // LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID
259 (uint32_t(X86::VECRRegBankID) << 4) | // FR32XRegClassID
260 (uint32_t(X86::GPRRegBankID) << 6) | // GR32RegClassID
261 (uint32_t(X86::GPRRegBankID) << 8) | // GR32_NOSPRegClassID
262 (uint32_t(X86::GPRRegBankID) << 10) | // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID
263 (uint32_t(InvalidRegBankID) << 12) |
264 (uint32_t(X86::VECRRegBankID) << 14) | // FR32RegClassID
265 (uint32_t(X86::GPRRegBankID) << 16) | // GR32_NOREX2RegClassID
266 (uint32_t(X86::GPRRegBankID) << 18) | // GR32_NOREX2_NOSPRegClassID
267 (uint32_t(X86::GPRRegBankID) << 20) | // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID
268 (uint32_t(X86::GPRRegBankID) << 22) | // GR32_NOREXRegClassID
269 (uint32_t(InvalidRegBankID) << 24) |
270 (uint32_t(X86::GPRRegBankID) << 26) | // GR32_NOREX_NOSPRegClassID
271 (uint32_t(X86::PSRRegBankID) << 28) | // RFP32RegClassID
272 (uint32_t(InvalidRegBankID) << 30),
273 (uint32_t(X86::GPRRegBankID) << 0) | // GR32_ABCDRegClassID
274 (uint32_t(X86::GPRRegBankID) << 2) | // GR32_TCRegClassID
275 (uint32_t(X86::GPRRegBankID) << 4) | // GR32_ABCD_and_GR32_TCRegClassID
276 (uint32_t(X86::GPRRegBankID) << 6) | // GR32_ADRegClassID
277 (uint32_t(X86::GPRRegBankID) << 8) | // GR32_ArgRefRegClassID
278 (uint32_t(X86::GPRRegBankID) << 10) | // GR32_BPSPRegClassID
279 (uint32_t(X86::GPRRegBankID) << 12) | // GR32_BSIRegClassID
280 (uint32_t(X86::GPRRegBankID) << 14) | // GR32_CBRegClassID
281 (uint32_t(X86::GPRRegBankID) << 16) | // GR32_DCRegClassID
282 (uint32_t(X86::GPRRegBankID) << 18) | // GR32_DIBPRegClassID
283 (uint32_t(X86::GPRRegBankID) << 20) | // GR32_SIDIRegClassID
284 (uint32_t(InvalidRegBankID) << 22) |
285 (uint32_t(InvalidRegBankID) << 24) |
286 (uint32_t(InvalidRegBankID) << 26) |
287 (uint32_t(X86::GPRRegBankID) << 28) | // GR32_ABCD_and_GR32_BSIRegClassID
288 (uint32_t(X86::GPRRegBankID) << 30), // GR32_AD_and_GR32_ArgRefRegClassID
289 (uint32_t(X86::GPRRegBankID) << 0) | // GR32_ArgRef_and_GR32_CBRegClassID
290 (uint32_t(X86::GPRRegBankID) << 2) | // GR32_BPSP_and_GR32_DIBPRegClassID
291 (uint32_t(X86::GPRRegBankID) << 4) | // GR32_BPSP_and_GR32_TCRegClassID
292 (uint32_t(X86::GPRRegBankID) << 6) | // GR32_BSI_and_GR32_SIDIRegClassID
293 (uint32_t(X86::GPRRegBankID) << 8) | // GR32_DIBP_and_GR32_SIDIRegClassID
294 (uint32_t(InvalidRegBankID) << 10) |
295 (uint32_t(InvalidRegBankID) << 12) |
296 (uint32_t(X86::PSRRegBankID) << 14) | // RFP64RegClassID
297 (uint32_t(X86::GPRRegBankID) << 16) | // GR64RegClassID
298 (uint32_t(X86::VECRRegBankID) << 18) | // FR64XRegClassID
299 (uint32_t(X86::GPRRegBankID) << 20) | // GR64_with_sub_8bitRegClassID
300 (uint32_t(X86::GPRRegBankID) << 22) | // GR64_NOSPRegClassID
301 (uint32_t(X86::GPRRegBankID) << 24) | // GR64_NOREX2RegClassID
302 (uint32_t(InvalidRegBankID) << 26) |
303 (uint32_t(X86::VECRRegBankID) << 28) | // FR64RegClassID
304 (uint32_t(X86::GPRRegBankID) << 30), // GR64_with_sub_16bit_in_GR16_NOREX2RegClassID
305 (uint32_t(X86::GPRRegBankID) << 0) | // GR64_NOREX2_NOSPRegClassID
306 (uint32_t(X86::GPRRegBankID) << 2) | // GR64PLTSafeRegClassID
307 (uint32_t(X86::GPRRegBankID) << 4) | // GR64_TCRegClassID
308 (uint32_t(X86::GPRRegBankID) << 6) | // GR64_NOREXRegClassID
309 (uint32_t(X86::GPRRegBankID) << 8) | // GR64_TCW64RegClassID
310 (uint32_t(X86::GPRRegBankID) << 10) | // GR64_TC_with_sub_8bitRegClassID
311 (uint32_t(X86::GPRRegBankID) << 12) | // GR64_NOREX2_NOSP_and_GR64_TCRegClassID
312 (uint32_t(X86::GPRRegBankID) << 14) | // GR64_TCW64_with_sub_8bitRegClassID
313 (uint32_t(X86::GPRRegBankID) << 16) | // GR64_TC_and_GR64_TCW64RegClassID
314 (uint32_t(X86::GPRRegBankID) << 18) | // GR64_with_sub_16bit_in_GR16_NOREXRegClassID
315 (uint32_t(InvalidRegBankID) << 20) |
316 (uint32_t(InvalidRegBankID) << 22) |
317 (uint32_t(X86::GPRRegBankID) << 24) | // GR64PLTSafe_and_GR64_TCRegClassID
318 (uint32_t(X86::GPRRegBankID) << 26) | // GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID
319 (uint32_t(X86::GPRRegBankID) << 28) | // GR64_NOREX_NOSPRegClassID
320 (uint32_t(X86::GPRRegBankID) << 30), // GR64_NOREX_and_GR64_TCRegClassID
321 (uint32_t(X86::GPRRegBankID) << 0) | // GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID
322 (uint32_t(InvalidRegBankID) << 2) |
323 (uint32_t(X86::GPRRegBankID) << 4) | // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID
324 (uint32_t(X86::GPRRegBankID) << 6) | // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID
325 (uint32_t(X86::GPRRegBankID) << 8) | // GR64PLTSafe_and_GR64_TCW64RegClassID
326 (uint32_t(X86::GPRRegBankID) << 10) | // GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID
327 (uint32_t(X86::GPRRegBankID) << 12) | // GR64_NOREX_and_GR64_TCW64RegClassID
328 (uint32_t(X86::GPRRegBankID) << 14) | // GR64_ABCDRegClassID
329 (uint32_t(X86::GPRRegBankID) << 16) | // GR64_with_sub_32bit_in_GR32_TCRegClassID
330 (uint32_t(X86::GPRRegBankID) << 18) | // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID
331 (uint32_t(X86::GPRRegBankID) << 20) | // GR64_ADRegClassID
332 (uint32_t(X86::GPRRegBankID) << 22) | // GR64_ArgRefRegClassID
333 (uint32_t(X86::GPRRegBankID) << 24) | // GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID
334 (uint32_t(X86::GPRRegBankID) << 26) | // GR64_with_sub_32bit_in_GR32_ArgRefRegClassID
335 (uint32_t(X86::GPRRegBankID) << 28) | // GR64_with_sub_32bit_in_GR32_BPSPRegClassID
336 (uint32_t(X86::GPRRegBankID) << 30), // GR64_with_sub_32bit_in_GR32_BSIRegClassID
337 (uint32_t(X86::GPRRegBankID) << 0) | // GR64_with_sub_32bit_in_GR32_CBRegClassID
338 (uint32_t(X86::GPRRegBankID) << 2) | // GR64_with_sub_32bit_in_GR32_DIBPRegClassID
339 (uint32_t(X86::GPRRegBankID) << 4) | // GR64_with_sub_32bit_in_GR32_SIDIRegClassID
340 (uint32_t(X86::GPRRegBankID) << 6) | // GR64_ARegClassID
341 (uint32_t(X86::GPRRegBankID) << 8) | // GR64_ArgRef_and_GR64_TCRegClassID
342 (uint32_t(X86::GPRRegBankID) << 10) | // GR64_and_LOW32_ADDR_ACCESSRegClassID
343 (uint32_t(X86::GPRRegBankID) << 12) | // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID
344 (uint32_t(X86::GPRRegBankID) << 14) | // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID
345 (uint32_t(X86::GPRRegBankID) << 16) | // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID
346 (uint32_t(X86::GPRRegBankID) << 18) | // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID
347 (uint32_t(X86::GPRRegBankID) << 20) | // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID
348 (uint32_t(X86::GPRRegBankID) << 22) | // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID
349 (uint32_t(X86::GPRRegBankID) << 24) | // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID
350 (uint32_t(InvalidRegBankID) << 26) |
351 (uint32_t(X86::PSRRegBankID) << 28) | // RFP80RegClassID
352 (uint32_t(InvalidRegBankID) << 30),
353 (uint32_t(X86::VECRRegBankID) << 0) | // VR128XRegClassID
354 (uint32_t(X86::VECRRegBankID) << 2) | // VR128RegClassID
355 (uint32_t(X86::VECRRegBankID) << 4) | // VR256XRegClassID
356 (uint32_t(X86::VECRRegBankID) << 6) | // VR256RegClassID
357 (uint32_t(X86::VECRRegBankID) << 8) | // VR512RegClassID
358 (uint32_t(X86::VECRRegBankID) << 10) // VR512_0_15RegClassID
359 };
360 const unsigned RegClassID = RC.getID();
361 if (LLVM_LIKELY(RegClassID < 134)) {
362 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
363 if (RegBankID != InvalidRegBankID)
364 return getRegBank(RegBankID);
365 }
366 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
367}
368
369} // namespace llvm
370
371#endif // GET_TARGET_REGBANK_IMPL
372
373